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// SPDX-License-Identifier: GPL-2.0-or-later
/*
Hopper VP-3028 driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "zl10353.h"
#include "mantis_common.h"
#include "mantis_ioc.h"
#include "mantis_dvb.h"
#include "hopper_vp3028.h"
static struct zl10353_config hopper_vp3028_config = {
.demod_address = 0x0f,
};
#define MANTIS_MODEL_NAME "VP-3028"
#define MANTIS_DEV_TYPE "DVB-T"
static int vp3028_frontend_init(struct mantis_pci *mantis, struct dvb_frontend *fe)
{
struct i2c_adapter *adapter = &mantis->adapter;
struct mantis_hwconfig *config = mantis->hwconfig;
int err;
mantis_gpio_set_bits(mantis, config->reset, 0);
msleep(100);
err = mantis_frontend_power(mantis, POWER_ON);
msleep(100);
mantis_gpio_set_bits(mantis, config->reset, 1);
err = mantis_frontend_power(mantis, POWER_ON);
if (err == 0) {
msleep(250);
dprintk(MANTIS_ERROR, 1, "Probing for 10353 (DVB-T)");
fe = dvb_attach(zl10353_attach, &hopper_vp3028_config, adapter);
if (!fe)
return -1;
} else {
dprintk(MANTIS_ERROR, 1, "Frontend on <%s> POWER ON failed! <%d>",
adapter->name,
err);
return -EIO;
}
dprintk(MANTIS_ERROR, 1, "Done!");
return 0;
}
struct mantis_hwconfig vp3028_config = {
.model_name = MANTIS_MODEL_NAME,
.dev_type = MANTIS_DEV_TYPE,
.ts_size = MANTIS_TS_188,
.baud_rate = MANTIS_BAUD_9600,
.parity = MANTIS_PARITY_NONE,
.bytes = 0,
.frontend_init = vp3028_frontend_init,
.power = GPIF_A00,
.reset = GPIF_A03,
};
| linux-master | drivers/media/pci/mantis/hopper_vp3028.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis PCI bridge driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/i2c.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "mantis_common.h"
#include "mantis_dma.h"
#include "mantis_ca.h"
#include "mantis_ioc.h"
#include "mantis_dvb.h"
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
int mantis_frontend_power(struct mantis_pci *mantis, enum mantis_power power)
{
struct mantis_hwconfig *config = mantis->hwconfig;
switch (power) {
case POWER_ON:
dprintk(MANTIS_DEBUG, 1, "Power ON");
mantis_gpio_set_bits(mantis, config->power, POWER_ON);
msleep(100);
mantis_gpio_set_bits(mantis, config->power, POWER_ON);
msleep(100);
break;
case POWER_OFF:
dprintk(MANTIS_DEBUG, 1, "Power OFF");
mantis_gpio_set_bits(mantis, config->power, POWER_OFF);
msleep(100);
break;
default:
dprintk(MANTIS_DEBUG, 1, "Unknown state <%02x>", power);
return -1;
}
return 0;
}
EXPORT_SYMBOL_GPL(mantis_frontend_power);
void mantis_frontend_soft_reset(struct mantis_pci *mantis)
{
struct mantis_hwconfig *config = mantis->hwconfig;
dprintk(MANTIS_DEBUG, 1, "Frontend RESET");
mantis_gpio_set_bits(mantis, config->reset, 0);
msleep(100);
mantis_gpio_set_bits(mantis, config->reset, 0);
msleep(100);
mantis_gpio_set_bits(mantis, config->reset, 1);
msleep(100);
mantis_gpio_set_bits(mantis, config->reset, 1);
msleep(100);
return;
}
EXPORT_SYMBOL_GPL(mantis_frontend_soft_reset);
static int mantis_frontend_shutdown(struct mantis_pci *mantis)
{
int err;
mantis_frontend_soft_reset(mantis);
err = mantis_frontend_power(mantis, POWER_OFF);
if (err != 0) {
dprintk(MANTIS_ERROR, 1, "Frontend POWER OFF failed! <%d>", err);
return 1;
}
return 0;
}
static int mantis_dvb_start_feed(struct dvb_demux_feed *dvbdmxfeed)
{
struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
struct mantis_pci *mantis = dvbdmx->priv;
dprintk(MANTIS_DEBUG, 1, "Mantis DVB Start feed");
if (!dvbdmx->dmx.frontend) {
dprintk(MANTIS_DEBUG, 1, "no frontend ?");
return -EINVAL;
}
mantis->feeds++;
dprintk(MANTIS_DEBUG, 1, "mantis start feed, feeds=%d", mantis->feeds);
if (mantis->feeds == 1) {
dprintk(MANTIS_DEBUG, 1, "mantis start feed & dma");
mantis_dma_start(mantis);
tasklet_enable(&mantis->tasklet);
}
return mantis->feeds;
}
static int mantis_dvb_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
{
struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
struct mantis_pci *mantis = dvbdmx->priv;
dprintk(MANTIS_DEBUG, 1, "Mantis DVB Stop feed");
if (!dvbdmx->dmx.frontend) {
dprintk(MANTIS_DEBUG, 1, "no frontend ?");
return -EINVAL;
}
mantis->feeds--;
if (mantis->feeds == 0) {
dprintk(MANTIS_DEBUG, 1, "mantis stop feed and dma");
tasklet_disable(&mantis->tasklet);
mantis_dma_stop(mantis);
}
return 0;
}
int mantis_dvb_init(struct mantis_pci *mantis)
{
struct mantis_hwconfig *config = mantis->hwconfig;
int result;
dprintk(MANTIS_DEBUG, 1, "dvb_register_adapter");
result = dvb_register_adapter(&mantis->dvb_adapter,
"Mantis DVB adapter",
THIS_MODULE,
&mantis->pdev->dev,
adapter_nr);
if (result < 0) {
dprintk(MANTIS_ERROR, 1, "Error registering adapter");
return -ENODEV;
}
mantis->dvb_adapter.priv = mantis;
mantis->demux.dmx.capabilities = DMX_TS_FILTERING |
DMX_SECTION_FILTERING |
DMX_MEMORY_BASED_FILTERING;
mantis->demux.priv = mantis;
mantis->demux.filternum = 256;
mantis->demux.feednum = 256;
mantis->demux.start_feed = mantis_dvb_start_feed;
mantis->demux.stop_feed = mantis_dvb_stop_feed;
mantis->demux.write_to_decoder = NULL;
dprintk(MANTIS_DEBUG, 1, "dvb_dmx_init");
result = dvb_dmx_init(&mantis->demux);
if (result < 0) {
dprintk(MANTIS_ERROR, 1, "dvb_dmx_init failed, ERROR=%d", result);
goto err0;
}
mantis->dmxdev.filternum = 256;
mantis->dmxdev.demux = &mantis->demux.dmx;
mantis->dmxdev.capabilities = 0;
dprintk(MANTIS_DEBUG, 1, "dvb_dmxdev_init");
result = dvb_dmxdev_init(&mantis->dmxdev, &mantis->dvb_adapter);
if (result < 0) {
dprintk(MANTIS_ERROR, 1, "dvb_dmxdev_init failed, ERROR=%d", result);
goto err1;
}
mantis->fe_hw.source = DMX_FRONTEND_0;
result = mantis->demux.dmx.add_frontend(&mantis->demux.dmx, &mantis->fe_hw);
if (result < 0) {
dprintk(MANTIS_ERROR, 1, "dvb_dmx_init failed, ERROR=%d", result);
goto err2;
}
mantis->fe_mem.source = DMX_MEMORY_FE;
result = mantis->demux.dmx.add_frontend(&mantis->demux.dmx, &mantis->fe_mem);
if (result < 0) {
dprintk(MANTIS_ERROR, 1, "dvb_dmx_init failed, ERROR=%d", result);
goto err3;
}
result = mantis->demux.dmx.connect_frontend(&mantis->demux.dmx, &mantis->fe_hw);
if (result < 0) {
dprintk(MANTIS_ERROR, 1, "dvb_dmx_init failed, ERROR=%d", result);
goto err4;
}
dvb_net_init(&mantis->dvb_adapter, &mantis->dvbnet, &mantis->demux.dmx);
tasklet_setup(&mantis->tasklet, mantis_dma_xfer);
tasklet_disable(&mantis->tasklet);
if (mantis->hwconfig) {
result = config->frontend_init(mantis, mantis->fe);
if (result < 0) {
dprintk(MANTIS_ERROR, 1, "!!! NO Frontends found !!!");
goto err5;
} else {
if (mantis->fe == NULL) {
result = -ENOMEM;
dprintk(MANTIS_ERROR, 1, "FE <NULL>");
goto err5;
}
result = dvb_register_frontend(&mantis->dvb_adapter, mantis->fe);
if (result) {
dprintk(MANTIS_ERROR, 1, "ERROR: Frontend registration failed");
if (mantis->fe->ops.release)
mantis->fe->ops.release(mantis->fe);
mantis->fe = NULL;
goto err5;
}
}
}
return 0;
/* Error conditions .. */
err5:
tasklet_kill(&mantis->tasklet);
dvb_net_release(&mantis->dvbnet);
if (mantis->fe) {
dvb_unregister_frontend(mantis->fe);
dvb_frontend_detach(mantis->fe);
}
err4:
mantis->demux.dmx.remove_frontend(&mantis->demux.dmx, &mantis->fe_mem);
err3:
mantis->demux.dmx.remove_frontend(&mantis->demux.dmx, &mantis->fe_hw);
err2:
dvb_dmxdev_release(&mantis->dmxdev);
err1:
dvb_dmx_release(&mantis->demux);
err0:
dvb_unregister_adapter(&mantis->dvb_adapter);
return result;
}
EXPORT_SYMBOL_GPL(mantis_dvb_init);
int mantis_dvb_exit(struct mantis_pci *mantis)
{
int err;
if (mantis->fe) {
/* mantis_ca_exit(mantis); */
err = mantis_frontend_shutdown(mantis);
if (err != 0)
dprintk(MANTIS_ERROR, 1, "Frontend exit while POWER ON! <%d>", err);
dvb_unregister_frontend(mantis->fe);
dvb_frontend_detach(mantis->fe);
}
tasklet_kill(&mantis->tasklet);
dvb_net_release(&mantis->dvbnet);
mantis->demux.dmx.remove_frontend(&mantis->demux.dmx, &mantis->fe_mem);
mantis->demux.dmx.remove_frontend(&mantis->demux.dmx, &mantis->fe_hw);
dvb_dmxdev_release(&mantis->dmxdev);
dvb_dmx_release(&mantis->demux);
dprintk(MANTIS_DEBUG, 1, "dvb_unregister_adapter");
dvb_unregister_adapter(&mantis->dvb_adapter);
return 0;
}
EXPORT_SYMBOL_GPL(mantis_dvb_exit);
| linux-master | drivers/media/pci/mantis/mantis_dvb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis PCI bridge driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "mantis_common.h"
#include "mantis_reg.h"
#include "mantis_ioc.h"
static int read_eeprom_bytes(struct mantis_pci *mantis, u8 reg, u8 *data, u8 length)
{
struct i2c_adapter *adapter = &mantis->adapter;
int err;
u8 buf = reg;
struct i2c_msg msg[] = {
{ .addr = 0x50, .flags = 0, .buf = &buf, .len = 1 },
{ .addr = 0x50, .flags = I2C_M_RD, .buf = data, .len = length },
};
err = i2c_transfer(adapter, msg, 2);
if (err < 0) {
dprintk(MANTIS_ERROR, 1, "ERROR: i2c read: < err=%i d0=0x%02x d1=0x%02x >",
err, data[0], data[1]);
return err;
}
return 0;
}
int mantis_get_mac(struct mantis_pci *mantis)
{
int err;
u8 mac_addr[6] = {0};
err = read_eeprom_bytes(mantis, 0x08, mac_addr, 6);
if (err < 0) {
dprintk(MANTIS_ERROR, 1, "ERROR: Mantis EEPROM read error <%d>", err);
return err;
}
dprintk(MANTIS_ERROR, 0, " MAC Address=[%pM]\n", mac_addr);
return 0;
}
EXPORT_SYMBOL_GPL(mantis_get_mac);
/* Turn the given bit on or off. */
void mantis_gpio_set_bits(struct mantis_pci *mantis, u32 bitpos, u8 value)
{
u32 cur;
dprintk(MANTIS_DEBUG, 1, "Set Bit <%d> to <%d>", bitpos, value);
cur = mmread(MANTIS_GPIF_ADDR);
if (value)
mantis->gpio_status = cur | (1 << bitpos);
else
mantis->gpio_status = cur & (~(1 << bitpos));
dprintk(MANTIS_DEBUG, 1, "GPIO Value <%02x>", mantis->gpio_status);
mmwrite(mantis->gpio_status, MANTIS_GPIF_ADDR);
mmwrite(0x00, MANTIS_GPIF_DOUT);
}
EXPORT_SYMBOL_GPL(mantis_gpio_set_bits);
int mantis_stream_control(struct mantis_pci *mantis, enum mantis_stream_control stream_ctl)
{
u32 reg;
reg = mmread(MANTIS_CONTROL);
switch (stream_ctl) {
case STREAM_TO_HIF:
dprintk(MANTIS_DEBUG, 1, "Set stream to HIF");
reg &= 0xff - MANTIS_BYPASS;
mmwrite(reg, MANTIS_CONTROL);
reg |= MANTIS_BYPASS;
mmwrite(reg, MANTIS_CONTROL);
break;
case STREAM_TO_CAM:
dprintk(MANTIS_DEBUG, 1, "Set stream to CAM");
reg |= MANTIS_BYPASS;
mmwrite(reg, MANTIS_CONTROL);
reg &= 0xff - MANTIS_BYPASS;
mmwrite(reg, MANTIS_CONTROL);
break;
default:
dprintk(MANTIS_ERROR, 1, "Unknown MODE <%02x>", stream_ctl);
return -1;
}
return 0;
}
EXPORT_SYMBOL_GPL(mantis_stream_control);
| linux-master | drivers/media/pci/mantis/mantis_ioc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis PCI bridge driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "mantis_common.h"
#include "mantis_hif.h"
#include "mantis_link.h" /* temporary due to physical layer stuff */
#include "mantis_reg.h"
static int mantis_hif_sbuf_opdone_wait(struct mantis_ca *ca)
{
struct mantis_pci *mantis = ca->ca_priv;
int rc = 0;
if (wait_event_timeout(ca->hif_opdone_wq,
ca->hif_event & MANTIS_SBUF_OPDONE,
msecs_to_jiffies(500)) == -ERESTARTSYS) {
dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Smart buffer operation timeout !", mantis->num);
rc = -EREMOTEIO;
}
dprintk(MANTIS_DEBUG, 1, "Smart Buffer Operation complete");
ca->hif_event &= ~MANTIS_SBUF_OPDONE;
return rc;
}
static int mantis_hif_write_wait(struct mantis_ca *ca)
{
struct mantis_pci *mantis = ca->ca_priv;
u32 opdone = 0, timeout = 0;
int rc = 0;
if (wait_event_timeout(ca->hif_write_wq,
mantis->gpif_status & MANTIS_GPIF_WRACK,
msecs_to_jiffies(500)) == -ERESTARTSYS) {
dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Write ACK timed out !", mantis->num);
rc = -EREMOTEIO;
}
dprintk(MANTIS_DEBUG, 1, "Write Acknowledged");
mantis->gpif_status &= ~MANTIS_GPIF_WRACK;
while (!opdone) {
opdone = (mmread(MANTIS_GPIF_STATUS) & MANTIS_SBUF_OPDONE);
udelay(500);
timeout++;
if (timeout > 100) {
dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Write operation timed out!", mantis->num);
rc = -ETIMEDOUT;
break;
}
}
dprintk(MANTIS_DEBUG, 1, "HIF Write success");
return rc;
}
int mantis_hif_read_mem(struct mantis_ca *ca, u32 addr)
{
struct mantis_pci *mantis = ca->ca_priv;
u32 hif_addr = 0, data, count = 4;
dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Read", mantis->num);
mutex_lock(&ca->ca_lock);
hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
hif_addr &= ~MANTIS_GPIF_PCMCIAIOM;
hif_addr |= MANTIS_HIF_STATUS;
hif_addr |= addr;
mmwrite(hif_addr, MANTIS_GPIF_BRADDR);
mmwrite(count, MANTIS_GPIF_BRBYTES);
udelay(20);
mmwrite(hif_addr | MANTIS_GPIF_HIFRDWRN, MANTIS_GPIF_ADDR);
if (mantis_hif_sbuf_opdone_wait(ca) != 0) {
dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): GPIF Smart Buffer operation failed", mantis->num);
mutex_unlock(&ca->ca_lock);
return -EREMOTEIO;
}
data = mmread(MANTIS_GPIF_DIN);
mutex_unlock(&ca->ca_lock);
dprintk(MANTIS_DEBUG, 1, "Mem Read: 0x%02x", data);
return (data >> 24) & 0xff;
}
int mantis_hif_write_mem(struct mantis_ca *ca, u32 addr, u8 data)
{
struct mantis_slot *slot = ca->slot;
struct mantis_pci *mantis = ca->ca_priv;
u32 hif_addr = 0;
dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Write", mantis->num);
mutex_lock(&ca->ca_lock);
hif_addr &= ~MANTIS_GPIF_HIFRDWRN;
hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
hif_addr &= ~MANTIS_GPIF_PCMCIAIOM;
hif_addr |= MANTIS_HIF_STATUS;
hif_addr |= addr;
mmwrite(slot->slave_cfg, MANTIS_GPIF_CFGSLA); /* Slot0 alone for now */
mmwrite(hif_addr, MANTIS_GPIF_ADDR);
mmwrite(data, MANTIS_GPIF_DOUT);
if (mantis_hif_write_wait(ca) != 0) {
dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
mutex_unlock(&ca->ca_lock);
return -EREMOTEIO;
}
dprintk(MANTIS_DEBUG, 1, "Mem Write: (0x%02x to 0x%02x)", data, addr);
mutex_unlock(&ca->ca_lock);
return 0;
}
int mantis_hif_read_iom(struct mantis_ca *ca, u32 addr)
{
struct mantis_pci *mantis = ca->ca_priv;
u32 data, hif_addr = 0;
dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Read", mantis->num);
mutex_lock(&ca->ca_lock);
hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
hif_addr |= MANTIS_GPIF_PCMCIAIOM;
hif_addr |= MANTIS_HIF_STATUS;
hif_addr |= addr;
mmwrite(hif_addr, MANTIS_GPIF_BRADDR);
mmwrite(1, MANTIS_GPIF_BRBYTES);
udelay(20);
mmwrite(hif_addr | MANTIS_GPIF_HIFRDWRN, MANTIS_GPIF_ADDR);
if (mantis_hif_sbuf_opdone_wait(ca) != 0) {
dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
mutex_unlock(&ca->ca_lock);
return -EREMOTEIO;
}
data = mmread(MANTIS_GPIF_DIN);
dprintk(MANTIS_DEBUG, 1, "I/O Read: 0x%02x", data);
udelay(50);
mutex_unlock(&ca->ca_lock);
return (u8) data;
}
int mantis_hif_write_iom(struct mantis_ca *ca, u32 addr, u8 data)
{
struct mantis_pci *mantis = ca->ca_priv;
u32 hif_addr = 0;
dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Write", mantis->num);
mutex_lock(&ca->ca_lock);
hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
hif_addr &= ~MANTIS_GPIF_HIFRDWRN;
hif_addr |= MANTIS_GPIF_PCMCIAIOM;
hif_addr |= MANTIS_HIF_STATUS;
hif_addr |= addr;
mmwrite(hif_addr, MANTIS_GPIF_ADDR);
mmwrite(data, MANTIS_GPIF_DOUT);
if (mantis_hif_write_wait(ca) != 0) {
dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
mutex_unlock(&ca->ca_lock);
return -EREMOTEIO;
}
dprintk(MANTIS_DEBUG, 1, "I/O Write: (0x%02x to 0x%02x)", data, addr);
mutex_unlock(&ca->ca_lock);
udelay(50);
return 0;
}
int mantis_hif_init(struct mantis_ca *ca)
{
struct mantis_slot *slot = ca->slot;
struct mantis_pci *mantis = ca->ca_priv;
u32 irqcfg;
slot[0].slave_cfg = 0x70773028;
dprintk(MANTIS_ERROR, 1, "Adapter(%d) Initializing Mantis Host Interface", mantis->num);
mutex_lock(&ca->ca_lock);
irqcfg = mmread(MANTIS_GPIF_IRQCFG);
irqcfg = MANTIS_MASK_BRRDY |
MANTIS_MASK_WRACK |
MANTIS_MASK_EXTIRQ |
MANTIS_MASK_WSTO |
MANTIS_MASK_OTHERR |
MANTIS_MASK_OVFLW;
mmwrite(irqcfg, MANTIS_GPIF_IRQCFG);
mutex_unlock(&ca->ca_lock);
return 0;
}
void mantis_hif_exit(struct mantis_ca *ca)
{
struct mantis_pci *mantis = ca->ca_priv;
u32 irqcfg;
dprintk(MANTIS_ERROR, 1, "Adapter(%d) Exiting Mantis Host Interface", mantis->num);
mutex_lock(&ca->ca_lock);
irqcfg = mmread(MANTIS_GPIF_IRQCFG);
irqcfg &= ~MANTIS_MASK_BRRDY;
mmwrite(irqcfg, MANTIS_GPIF_IRQCFG);
mutex_unlock(&ca->ca_lock);
}
| linux-master | drivers/media/pci/mantis/mantis_hif.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis VP-1041 driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "mantis_common.h"
#include "mantis_ioc.h"
#include "mantis_dvb.h"
#include "mantis_vp1041.h"
#include "stb0899_reg.h"
#include "stb0899_drv.h"
#include "stb0899_cfg.h"
#include "stb6100_cfg.h"
#include "stb6100.h"
#include "lnbp21.h"
#define MANTIS_MODEL_NAME "VP-1041"
#define MANTIS_DEV_TYPE "DSS/DVB-S/DVB-S2"
static const struct stb0899_s1_reg vp1041_stb0899_s1_init_1[] = {
/* 0x0000000b, *//* SYSREG */
{ STB0899_DEV_ID , 0x30 },
{ STB0899_DISCNTRL1 , 0x32 },
{ STB0899_DISCNTRL2 , 0x80 },
{ STB0899_DISRX_ST0 , 0x04 },
{ STB0899_DISRX_ST1 , 0x00 },
{ STB0899_DISPARITY , 0x00 },
{ STB0899_DISSTATUS , 0x20 },
{ STB0899_DISF22 , 0x99 },
{ STB0899_DISF22RX , 0xa8 },
/* SYSREG ? */
{ STB0899_ACRPRESC , 0x11 },
{ STB0899_ACRDIV1 , 0x0a },
{ STB0899_ACRDIV2 , 0x05 },
{ STB0899_DACR1 , 0x00 },
{ STB0899_DACR2 , 0x00 },
{ STB0899_OUTCFG , 0x00 },
{ STB0899_MODECFG , 0x00 },
{ STB0899_IRQSTATUS_3 , 0xfe },
{ STB0899_IRQSTATUS_2 , 0x03 },
{ STB0899_IRQSTATUS_1 , 0x7c },
{ STB0899_IRQSTATUS_0 , 0xf4 },
{ STB0899_IRQMSK_3 , 0xf3 },
{ STB0899_IRQMSK_2 , 0xfc },
{ STB0899_IRQMSK_1 , 0xff },
{ STB0899_IRQMSK_0 , 0xff },
{ STB0899_IRQCFG , 0x00 },
{ STB0899_I2CCFG , 0x88 },
{ STB0899_I2CRPT , 0x58 },
{ STB0899_IOPVALUE5 , 0x00 },
{ STB0899_IOPVALUE4 , 0x33 },
{ STB0899_IOPVALUE3 , 0x6d },
{ STB0899_IOPVALUE2 , 0x90 },
{ STB0899_IOPVALUE1 , 0x60 },
{ STB0899_IOPVALUE0 , 0x00 },
{ STB0899_GPIO00CFG , 0x82 },
{ STB0899_GPIO01CFG , 0x82 },
{ STB0899_GPIO02CFG , 0x82 },
{ STB0899_GPIO03CFG , 0x82 },
{ STB0899_GPIO04CFG , 0x82 },
{ STB0899_GPIO05CFG , 0x82 },
{ STB0899_GPIO06CFG , 0x82 },
{ STB0899_GPIO07CFG , 0x82 },
{ STB0899_GPIO08CFG , 0x82 },
{ STB0899_GPIO09CFG , 0x82 },
{ STB0899_GPIO10CFG , 0x82 },
{ STB0899_GPIO11CFG , 0x82 },
{ STB0899_GPIO12CFG , 0x82 },
{ STB0899_GPIO13CFG , 0x82 },
{ STB0899_GPIO14CFG , 0x82 },
{ STB0899_GPIO15CFG , 0x82 },
{ STB0899_GPIO16CFG , 0x82 },
{ STB0899_GPIO17CFG , 0x82 },
{ STB0899_GPIO18CFG , 0x82 },
{ STB0899_GPIO19CFG , 0x82 },
{ STB0899_GPIO20CFG , 0x82 },
{ STB0899_SDATCFG , 0xb8 },
{ STB0899_SCLTCFG , 0xba },
{ STB0899_AGCRFCFG , 0x1c }, /* 0x11 */
{ STB0899_GPIO22 , 0x82 }, /* AGCBB2CFG */
{ STB0899_GPIO21 , 0x91 }, /* AGCBB1CFG */
{ STB0899_DIRCLKCFG , 0x82 },
{ STB0899_CLKOUT27CFG , 0x7e },
{ STB0899_STDBYCFG , 0x82 },
{ STB0899_CS0CFG , 0x82 },
{ STB0899_CS1CFG , 0x82 },
{ STB0899_DISEQCOCFG , 0x20 },
{ STB0899_GPIO32CFG , 0x82 },
{ STB0899_GPIO33CFG , 0x82 },
{ STB0899_GPIO34CFG , 0x82 },
{ STB0899_GPIO35CFG , 0x82 },
{ STB0899_GPIO36CFG , 0x82 },
{ STB0899_GPIO37CFG , 0x82 },
{ STB0899_GPIO38CFG , 0x82 },
{ STB0899_GPIO39CFG , 0x82 },
{ STB0899_NCOARSE , 0x17 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
{ STB0899_SYNTCTRL , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
{ STB0899_FILTCTRL , 0x00 },
{ STB0899_SYSCTRL , 0x01 },
{ STB0899_STOPCLK1 , 0x20 },
{ STB0899_STOPCLK2 , 0x00 },
{ STB0899_INTBUFSTATUS , 0x00 },
{ STB0899_INTBUFCTRL , 0x0a },
{ 0xffff , 0xff },
};
static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = {
{ STB0899_DEMOD , 0x00 },
{ STB0899_RCOMPC , 0xc9 },
{ STB0899_AGC1CN , 0x01 },
{ STB0899_AGC1REF , 0x10 },
{ STB0899_RTC , 0x23 },
{ STB0899_TMGCFG , 0x4e },
{ STB0899_AGC2REF , 0x34 },
{ STB0899_TLSR , 0x84 },
{ STB0899_CFD , 0xf7 },
{ STB0899_ACLC , 0x87 },
{ STB0899_BCLC , 0x94 },
{ STB0899_EQON , 0x41 },
{ STB0899_LDT , 0xf1 },
{ STB0899_LDT2 , 0xe3 },
{ STB0899_EQUALREF , 0xb4 },
{ STB0899_TMGRAMP , 0x10 },
{ STB0899_TMGTHD , 0x30 },
{ STB0899_IDCCOMP , 0xfd },
{ STB0899_QDCCOMP , 0xff },
{ STB0899_POWERI , 0x0c },
{ STB0899_POWERQ , 0x0f },
{ STB0899_RCOMP , 0x6c },
{ STB0899_AGCIQIN , 0x80 },
{ STB0899_AGC2I1 , 0x06 },
{ STB0899_AGC2I2 , 0x00 },
{ STB0899_TLIR , 0x30 },
{ STB0899_RTF , 0x7f },
{ STB0899_DSTATUS , 0x00 },
{ STB0899_LDI , 0xbc },
{ STB0899_CFRM , 0xea },
{ STB0899_CFRL , 0x31 },
{ STB0899_NIRM , 0x2b },
{ STB0899_NIRL , 0x80 },
{ STB0899_ISYMB , 0x1d },
{ STB0899_QSYMB , 0xa6 },
{ STB0899_SFRH , 0x2f },
{ STB0899_SFRM , 0x68 },
{ STB0899_SFRL , 0x40 },
{ STB0899_SFRUPH , 0x2f },
{ STB0899_SFRUPM , 0x68 },
{ STB0899_SFRUPL , 0x40 },
{ STB0899_EQUAI1 , 0x02 },
{ STB0899_EQUAQ1 , 0xff },
{ STB0899_EQUAI2 , 0x04 },
{ STB0899_EQUAQ2 , 0x05 },
{ STB0899_EQUAI3 , 0x02 },
{ STB0899_EQUAQ3 , 0xfd },
{ STB0899_EQUAI4 , 0x03 },
{ STB0899_EQUAQ4 , 0x07 },
{ STB0899_EQUAI5 , 0x08 },
{ STB0899_EQUAQ5 , 0xf5 },
{ STB0899_DSTATUS2 , 0x00 },
{ STB0899_VSTATUS , 0x00 },
{ STB0899_VERROR , 0x86 },
{ STB0899_IQSWAP , 0x2a },
{ STB0899_ECNT1M , 0x00 },
{ STB0899_ECNT1L , 0x00 },
{ STB0899_ECNT2M , 0x00 },
{ STB0899_ECNT2L , 0x00 },
{ STB0899_ECNT3M , 0x0a },
{ STB0899_ECNT3L , 0xad },
{ STB0899_FECAUTO1 , 0x06 },
{ STB0899_FECM , 0x01 },
{ STB0899_VTH12 , 0xb0 },
{ STB0899_VTH23 , 0x7a },
{ STB0899_VTH34 , 0x58 },
{ STB0899_VTH56 , 0x38 },
{ STB0899_VTH67 , 0x34 },
{ STB0899_VTH78 , 0x24 },
{ STB0899_PRVIT , 0xff },
{ STB0899_VITSYNC , 0x19 },
{ STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
{ STB0899_TSULC , 0x42 },
{ STB0899_RSLLC , 0x41 },
{ STB0899_TSLPL , 0x12 },
{ STB0899_TSCFGH , 0x0c },
{ STB0899_TSCFGM , 0x00 },
{ STB0899_TSCFGL , 0x00 },
{ STB0899_TSOUT , 0x69 }, /* 0x0d for CAM */
{ STB0899_RSSYNCDEL , 0x00 },
{ STB0899_TSINHDELH , 0x02 },
{ STB0899_TSINHDELM , 0x00 },
{ STB0899_TSINHDELL , 0x00 },
{ STB0899_TSLLSTKM , 0x1b },
{ STB0899_TSLLSTKL , 0xb3 },
{ STB0899_TSULSTKM , 0x00 },
{ STB0899_TSULSTKL , 0x00 },
{ STB0899_PCKLENUL , 0xbc },
{ STB0899_PCKLENLL , 0xcc },
{ STB0899_RSPCKLEN , 0xbd },
{ STB0899_TSSTATUS , 0x90 },
{ STB0899_ERRCTRL1 , 0xb6 },
{ STB0899_ERRCTRL2 , 0x95 },
{ STB0899_ERRCTRL3 , 0x8d },
{ STB0899_DMONMSK1 , 0x27 },
{ STB0899_DMONMSK0 , 0x03 },
{ STB0899_DEMAPVIT , 0x5c },
{ STB0899_PLPARM , 0x19 },
{ STB0899_PDELCTRL , 0x48 },
{ STB0899_PDELCTRL2 , 0x00 },
{ STB0899_BBHCTRL1 , 0x00 },
{ STB0899_BBHCTRL2 , 0x00 },
{ STB0899_HYSTTHRESH , 0x77 },
{ STB0899_MATCSTM , 0x00 },
{ STB0899_MATCSTL , 0x00 },
{ STB0899_UPLCSTM , 0x00 },
{ STB0899_UPLCSTL , 0x00 },
{ STB0899_DFLCSTM , 0x00 },
{ STB0899_DFLCSTL , 0x00 },
{ STB0899_SYNCCST , 0x00 },
{ STB0899_SYNCDCSTM , 0x00 },
{ STB0899_SYNCDCSTL , 0x00 },
{ STB0899_ISI_ENTRY , 0x00 },
{ STB0899_ISI_BIT_EN , 0x00 },
{ STB0899_MATSTRM , 0xf0 },
{ STB0899_MATSTRL , 0x02 },
{ STB0899_UPLSTRM , 0x45 },
{ STB0899_UPLSTRL , 0x60 },
{ STB0899_DFLSTRM , 0xe3 },
{ STB0899_DFLSTRL , 0x00 },
{ STB0899_SYNCSTR , 0x47 },
{ STB0899_SYNCDSTRM , 0x05 },
{ STB0899_SYNCDSTRL , 0x18 },
{ STB0899_CFGPDELSTATUS1 , 0x19 },
{ STB0899_CFGPDELSTATUS2 , 0x2b },
{ STB0899_BBFERRORM , 0x00 },
{ STB0899_BBFERRORL , 0x01 },
{ STB0899_UPKTERRORM , 0x00 },
{ STB0899_UPKTERRORL , 0x00 },
{ 0xffff , 0xff },
};
static struct stb0899_config vp1041_stb0899_config = {
.init_dev = vp1041_stb0899_s1_init_1,
.init_s2_demod = stb0899_s2_init_2,
.init_s1_demod = vp1041_stb0899_s1_init_3,
.init_s2_fec = stb0899_s2_init_4,
.init_tst = stb0899_s1_init_5,
.demod_address = 0x68, /* 0xd0 >> 1 */
.xtal_freq = 27000000,
.inversion = IQ_SWAP_ON,
.lo_clk = 76500000,
.hi_clk = 99000000,
.esno_ave = STB0899_DVBS2_ESNO_AVE,
.esno_quant = STB0899_DVBS2_ESNO_QUANT,
.avframes_coarse = STB0899_DVBS2_AVFRAMES_COARSE,
.avframes_fine = STB0899_DVBS2_AVFRAMES_FINE,
.miss_threshold = STB0899_DVBS2_MISS_THRESHOLD,
.uwp_threshold_acq = STB0899_DVBS2_UWP_THRESHOLD_ACQ,
.uwp_threshold_track = STB0899_DVBS2_UWP_THRESHOLD_TRACK,
.uwp_threshold_sof = STB0899_DVBS2_UWP_THRESHOLD_SOF,
.sof_search_timeout = STB0899_DVBS2_SOF_SEARCH_TIMEOUT,
.btr_nco_bits = STB0899_DVBS2_BTR_NCO_BITS,
.btr_gain_shift_offset = STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET,
.crl_nco_bits = STB0899_DVBS2_CRL_NCO_BITS,
.ldpc_max_iter = STB0899_DVBS2_LDPC_MAX_ITER,
.tuner_get_frequency = stb6100_get_frequency,
.tuner_set_frequency = stb6100_set_frequency,
.tuner_set_bandwidth = stb6100_set_bandwidth,
.tuner_get_bandwidth = stb6100_get_bandwidth,
.tuner_set_rfsiggain = NULL,
};
static struct stb6100_config vp1041_stb6100_config = {
.tuner_address = 0x60,
.refclock = 27000000,
};
static int vp1041_frontend_init(struct mantis_pci *mantis, struct dvb_frontend *fe)
{
struct i2c_adapter *adapter = &mantis->adapter;
int err = 0;
err = mantis_frontend_power(mantis, POWER_ON);
if (err == 0) {
mantis_frontend_soft_reset(mantis);
msleep(250);
mantis->fe = dvb_attach(stb0899_attach, &vp1041_stb0899_config, adapter);
if (mantis->fe) {
dprintk(MANTIS_ERROR, 1,
"found STB0899 DVB-S/DVB-S2 frontend @0x%02x",
vp1041_stb0899_config.demod_address);
if (dvb_attach(stb6100_attach, mantis->fe, &vp1041_stb6100_config, adapter)) {
if (!dvb_attach(lnbp21_attach, mantis->fe, adapter, 0, 0))
dprintk(MANTIS_ERROR, 1, "No LNBP21 found!");
}
} else {
return -EREMOTEIO;
}
} else {
dprintk(MANTIS_ERROR, 1, "Frontend on <%s> POWER ON failed! <%d>",
adapter->name,
err);
return -EIO;
}
dprintk(MANTIS_ERROR, 1, "Done!");
return 0;
}
struct mantis_hwconfig vp1041_config = {
.model_name = MANTIS_MODEL_NAME,
.dev_type = MANTIS_DEV_TYPE,
.ts_size = MANTIS_TS_188,
.baud_rate = MANTIS_BAUD_9600,
.parity = MANTIS_PARITY_NONE,
.bytes = 0,
.frontend_init = vp1041_frontend_init,
.power = GPIF_A12,
.reset = GPIF_A13,
};
| linux-master | drivers/media/pci/mantis/mantis_vp1041.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis VP-2040 driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "tda1002x.h"
#include "mantis_common.h"
#include "mantis_ioc.h"
#include "mantis_dvb.h"
#include "mantis_vp2040.h"
#define MANTIS_MODEL_NAME "VP-2040"
#define MANTIS_DEV_TYPE "DVB-C"
static struct tda1002x_config vp2040_tda1002x_cu1216_config = {
.demod_address = 0x18 >> 1,
.invert = 1,
};
static struct tda10023_config vp2040_tda10023_cu1216_config = {
.demod_address = 0x18 >> 1,
.invert = 1,
};
static int tda1002x_cu1216_tuner_set(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct mantis_pci *mantis = fe->dvb->priv;
struct i2c_adapter *adapter = &mantis->adapter;
u8 buf[6];
struct i2c_msg msg = {.addr = 0x60, .flags = 0, .buf = buf, .len = sizeof(buf)};
int i;
#define CU1216_IF 36125000
#define TUNER_MUL 62500
u32 div = (p->frequency + CU1216_IF + TUNER_MUL / 2) / TUNER_MUL;
buf[0] = (div >> 8) & 0x7f;
buf[1] = div & 0xff;
buf[2] = 0xce;
buf[3] = (p->frequency < 150000000 ? 0x01 :
p->frequency < 445000000 ? 0x02 : 0x04);
buf[4] = 0xde;
buf[5] = 0x20;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(adapter, &msg, 1) != 1)
return -EIO;
/* wait for the pll lock */
msg.flags = I2C_M_RD;
msg.len = 1;
for (i = 0; i < 20; i++) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(adapter, &msg, 1) == 1 && (buf[0] & 0x40))
break;
msleep(10);
}
/* switch the charge pump to the lower current */
msg.flags = 0;
msg.len = 2;
msg.buf = &buf[2];
buf[2] &= ~0x40;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(adapter, &msg, 1) != 1)
return -EIO;
return 0;
}
static u8 read_pwm(struct mantis_pci *mantis)
{
struct i2c_adapter *adapter = &mantis->adapter;
u8 b = 0xff;
u8 pwm;
struct i2c_msg msg[] = {
{.addr = 0x50, .flags = 0, .buf = &b, .len = 1},
{.addr = 0x50, .flags = I2C_M_RD, .buf = &pwm, .len = 1}
};
if ((i2c_transfer(adapter, msg, 2) != 2)
|| (pwm == 0xff))
pwm = 0x48;
return pwm;
}
static int vp2040_frontend_init(struct mantis_pci *mantis, struct dvb_frontend *fe)
{
struct i2c_adapter *adapter = &mantis->adapter;
int err = 0;
err = mantis_frontend_power(mantis, POWER_ON);
if (err == 0) {
mantis_frontend_soft_reset(mantis);
msleep(250);
dprintk(MANTIS_ERROR, 1, "Probing for CU1216 (DVB-C)");
fe = dvb_attach(tda10021_attach, &vp2040_tda1002x_cu1216_config,
adapter,
read_pwm(mantis));
if (fe) {
dprintk(MANTIS_ERROR, 1,
"found Philips CU1216 DVB-C frontend (TDA10021) @ 0x%02x",
vp2040_tda1002x_cu1216_config.demod_address);
} else {
fe = dvb_attach(tda10023_attach, &vp2040_tda10023_cu1216_config,
adapter,
read_pwm(mantis));
if (fe) {
dprintk(MANTIS_ERROR, 1,
"found Philips CU1216 DVB-C frontend (TDA10023) @ 0x%02x",
vp2040_tda1002x_cu1216_config.demod_address);
}
}
if (fe) {
fe->ops.tuner_ops.set_params = tda1002x_cu1216_tuner_set;
dprintk(MANTIS_ERROR, 1, "Mantis DVB-C Philips CU1216 frontend attach success");
} else {
return -1;
}
} else {
dprintk(MANTIS_ERROR, 1, "Frontend on <%s> POWER ON failed! <%d>",
adapter->name,
err);
return -EIO;
}
mantis->fe = fe;
dprintk(MANTIS_DEBUG, 1, "Done!");
return 0;
}
struct mantis_hwconfig vp2040_config = {
.model_name = MANTIS_MODEL_NAME,
.dev_type = MANTIS_DEV_TYPE,
.ts_size = MANTIS_TS_204,
.baud_rate = MANTIS_BAUD_9600,
.parity = MANTIS_PARITY_NONE,
.bytes = 0,
.frontend_init = vp2040_frontend_init,
.power = GPIF_A12,
.reset = GPIF_A13,
};
| linux-master | drivers/media/pci/mantis/mantis_vp2040.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis VP-1034 driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "mb86a16.h"
#include "mantis_common.h"
#include "mantis_ioc.h"
#include "mantis_dvb.h"
#include "mantis_vp1034.h"
#include "mantis_reg.h"
static const struct mb86a16_config vp1034_mb86a16_config = {
.demod_address = 0x08,
.set_voltage = vp1034_set_voltage,
};
#define MANTIS_MODEL_NAME "VP-1034"
#define MANTIS_DEV_TYPE "DVB-S/DSS"
int vp1034_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)
{
struct mantis_pci *mantis = fe->dvb->priv;
switch (voltage) {
case SEC_VOLTAGE_13:
dprintk(MANTIS_ERROR, 1, "Polarization=[13V]");
mantis_gpio_set_bits(mantis, 13, 1);
mantis_gpio_set_bits(mantis, 14, 0);
break;
case SEC_VOLTAGE_18:
dprintk(MANTIS_ERROR, 1, "Polarization=[18V]");
mantis_gpio_set_bits(mantis, 13, 1);
mantis_gpio_set_bits(mantis, 14, 1);
break;
case SEC_VOLTAGE_OFF:
dprintk(MANTIS_ERROR, 1, "Frontend (dummy) POWERDOWN");
break;
default:
dprintk(MANTIS_ERROR, 1, "Invalid = (%d)", (u32) voltage);
return -EINVAL;
}
mmwrite(0x00, MANTIS_GPIF_DOUT);
return 0;
}
static int vp1034_frontend_init(struct mantis_pci *mantis, struct dvb_frontend *fe)
{
struct i2c_adapter *adapter = &mantis->adapter;
int err = 0;
err = mantis_frontend_power(mantis, POWER_ON);
if (err == 0) {
mantis_frontend_soft_reset(mantis);
msleep(250);
dprintk(MANTIS_ERROR, 1, "Probing for MB86A16 (DVB-S/DSS)");
fe = dvb_attach(mb86a16_attach, &vp1034_mb86a16_config, adapter);
if (fe) {
dprintk(MANTIS_ERROR, 1,
"found MB86A16 DVB-S/DSS frontend @0x%02x",
vp1034_mb86a16_config.demod_address);
} else {
return -1;
}
} else {
dprintk(MANTIS_ERROR, 1, "Frontend on <%s> POWER ON failed! <%d>",
adapter->name,
err);
return -EIO;
}
mantis->fe = fe;
dprintk(MANTIS_ERROR, 1, "Done!");
return 0;
}
struct mantis_hwconfig vp1034_config = {
.model_name = MANTIS_MODEL_NAME,
.dev_type = MANTIS_DEV_TYPE,
.ts_size = MANTIS_TS_204,
.baud_rate = MANTIS_BAUD_9600,
.parity = MANTIS_PARITY_NONE,
.bytes = 0,
.frontend_init = vp1034_frontend_init,
.power = GPIF_A12,
.reset = GPIF_A13,
};
| linux-master | drivers/media/pci/mantis/mantis_vp1034.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis PCI bridge driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "mantis_common.h"
#include "mantis_link.h"
#include "mantis_hif.h"
#include "mantis_reg.h"
static void mantis_hifevm_work(struct work_struct *work)
{
struct mantis_ca *ca = container_of(work, struct mantis_ca, hif_evm_work);
struct mantis_pci *mantis = ca->ca_priv;
u32 gpif_stat;
gpif_stat = mmread(MANTIS_GPIF_STATUS);
if (gpif_stat & MANTIS_GPIF_DETSTAT) {
if (gpif_stat & MANTIS_CARD_PLUGIN) {
dprintk(MANTIS_DEBUG, 1, "Event Mgr: Adapter(%d) Slot(0): CAM Plugin", mantis->num);
mmwrite(0xdada0000, MANTIS_CARD_RESET);
mantis_event_cam_plugin(ca);
dvb_ca_en50221_camchange_irq(&ca->en50221,
0,
DVB_CA_EN50221_CAMCHANGE_INSERTED);
}
} else {
if (gpif_stat & MANTIS_CARD_PLUGOUT) {
dprintk(MANTIS_DEBUG, 1, "Event Mgr: Adapter(%d) Slot(0): CAM Unplug", mantis->num);
mmwrite(0xdada0000, MANTIS_CARD_RESET);
mantis_event_cam_unplug(ca);
dvb_ca_en50221_camchange_irq(&ca->en50221,
0,
DVB_CA_EN50221_CAMCHANGE_REMOVED);
}
}
if (mantis->gpif_status & MANTIS_GPIF_EXTIRQ)
dprintk(MANTIS_DEBUG, 1, "Event Mgr: Adapter(%d) Slot(0): Ext IRQ", mantis->num);
if (mantis->gpif_status & MANTIS_SBUF_WSTO)
dprintk(MANTIS_DEBUG, 1, "Event Mgr: Adapter(%d) Slot(0): Smart Buffer Timeout", mantis->num);
if (mantis->gpif_status & MANTIS_GPIF_OTHERR)
dprintk(MANTIS_DEBUG, 1, "Event Mgr: Adapter(%d) Slot(0): Alignment Error", mantis->num);
if (gpif_stat & MANTIS_SBUF_OVFLW)
dprintk(MANTIS_DEBUG, 1, "Event Mgr: Adapter(%d) Slot(0): Smart Buffer Overflow", mantis->num);
if (gpif_stat & MANTIS_GPIF_BRRDY)
dprintk(MANTIS_DEBUG, 1, "Event Mgr: Adapter(%d) Slot(0): Smart Buffer Read Ready", mantis->num);
if (gpif_stat & MANTIS_GPIF_INTSTAT)
dprintk(MANTIS_DEBUG, 1, "Event Mgr: Adapter(%d) Slot(0): GPIF IRQ", mantis->num);
if (gpif_stat & MANTIS_SBUF_EMPTY)
dprintk(MANTIS_DEBUG, 1, "Event Mgr: Adapter(%d) Slot(0): Smart Buffer Empty", mantis->num);
if (gpif_stat & MANTIS_SBUF_OPDONE) {
dprintk(MANTIS_DEBUG, 1, "Event Mgr: Adapter(%d) Slot(0): Smart Buffer operation complete", mantis->num);
ca->sbuf_status = MANTIS_SBUF_DATA_AVAIL;
ca->hif_event = MANTIS_SBUF_OPDONE;
wake_up(&ca->hif_opdone_wq);
}
}
int mantis_evmgr_init(struct mantis_ca *ca)
{
struct mantis_pci *mantis = ca->ca_priv;
dprintk(MANTIS_DEBUG, 1, "Initializing Mantis Host I/F Event manager");
INIT_WORK(&ca->hif_evm_work, mantis_hifevm_work);
mantis_pcmcia_init(ca);
schedule_work(&ca->hif_evm_work);
mantis_hif_init(ca);
return 0;
}
void mantis_evmgr_exit(struct mantis_ca *ca)
{
struct mantis_pci *mantis = ca->ca_priv;
dprintk(MANTIS_DEBUG, 1, "Mantis Host I/F Event manager exiting");
flush_work(&ca->hif_evm_work);
mantis_hif_exit(ca);
mantis_pcmcia_exit(ca);
}
| linux-master | drivers/media/pci/mantis/mantis_evm.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis VP-3030 driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "zl10353.h"
#include "tda665x.h"
#include "mantis_common.h"
#include "mantis_ioc.h"
#include "mantis_dvb.h"
#include "mantis_vp3030.h"
static struct zl10353_config mantis_vp3030_config = {
.demod_address = 0x0f,
};
static struct tda665x_config env57h12d5_config = {
.name = "ENV57H12D5 (ET-50DT)",
.addr = 0x60,
.frequency_min = 47 * MHz,
.frequency_max = 862 * MHz,
.frequency_offst = 3616667,
.ref_multiplier = 6, /* 1/6 MHz */
.ref_divider = 100000, /* 1/6 MHz */
};
#define MANTIS_MODEL_NAME "VP-3030"
#define MANTIS_DEV_TYPE "DVB-T"
static int vp3030_frontend_init(struct mantis_pci *mantis, struct dvb_frontend *fe)
{
struct i2c_adapter *adapter = &mantis->adapter;
struct mantis_hwconfig *config = mantis->hwconfig;
int err = 0;
mantis_gpio_set_bits(mantis, config->reset, 0);
msleep(100);
err = mantis_frontend_power(mantis, POWER_ON);
msleep(100);
mantis_gpio_set_bits(mantis, config->reset, 1);
if (err == 0) {
msleep(250);
dprintk(MANTIS_ERROR, 1, "Probing for 10353 (DVB-T)");
fe = dvb_attach(zl10353_attach, &mantis_vp3030_config, adapter);
if (!fe)
return -1;
dvb_attach(tda665x_attach, fe, &env57h12d5_config, adapter);
} else {
dprintk(MANTIS_ERROR, 1, "Frontend on <%s> POWER ON failed! <%d>",
adapter->name,
err);
return -EIO;
}
mantis->fe = fe;
dprintk(MANTIS_ERROR, 1, "Done!");
return 0;
}
struct mantis_hwconfig vp3030_config = {
.model_name = MANTIS_MODEL_NAME,
.dev_type = MANTIS_DEV_TYPE,
.ts_size = MANTIS_TS_188,
.baud_rate = MANTIS_BAUD_9600,
.parity = MANTIS_PARITY_NONE,
.bytes = 0,
.frontend_init = vp3030_frontend_init,
.power = GPIF_A12,
.reset = GPIF_A13,
.i2c_mode = MANTIS_BYTE_MODE
};
| linux-master | drivers/media/pci/mantis/mantis_vp3030.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis PCI bridge driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <asm/io.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "mantis_common.h"
#include "mantis_reg.h"
#include "mantis_uart.h"
#include "mantis_input.h"
struct mantis_uart_params {
enum mantis_baud baud_rate;
enum mantis_parity parity;
};
static struct {
char string[7];
} rates[5] = {
{ "9600" },
{ "19200" },
{ "38400" },
{ "57600" },
{ "115200" }
};
static struct {
char string[5];
} parity[3] = {
{ "NONE" },
{ "ODD" },
{ "EVEN" }
};
static void mantis_uart_read(struct mantis_pci *mantis)
{
struct mantis_hwconfig *config = mantis->hwconfig;
int i, scancode = 0, err = 0;
/* get data */
dprintk(MANTIS_DEBUG, 1, "UART Reading ...");
for (i = 0; i < (config->bytes + 1); i++) {
int data = mmread(MANTIS_UART_RXD);
dprintk(MANTIS_DEBUG, 0, " <%02x>", data);
scancode = (scancode << 8) | (data & 0x3f);
err |= data;
if (data & (1 << 7))
dprintk(MANTIS_ERROR, 1, "UART framing error");
if (data & (1 << 6))
dprintk(MANTIS_ERROR, 1, "UART parity error");
}
dprintk(MANTIS_DEBUG, 0, "\n");
if ((err & 0xC0) == 0)
mantis_input_process(mantis, scancode);
}
static void mantis_uart_work(struct work_struct *work)
{
struct mantis_pci *mantis = container_of(work, struct mantis_pci, uart_work);
u32 stat;
unsigned long timeout;
stat = mmread(MANTIS_UART_STAT);
if (stat & MANTIS_UART_RXFIFO_FULL)
dprintk(MANTIS_ERROR, 1, "RX Fifo FULL");
/*
* MANTIS_UART_RXFIFO_DATA is only set if at least
* config->bytes + 1 bytes are in the FIFO.
*/
/* FIXME: is 10ms good enough ? */
timeout = jiffies + msecs_to_jiffies(10);
while (stat & MANTIS_UART_RXFIFO_DATA) {
mantis_uart_read(mantis);
stat = mmread(MANTIS_UART_STAT);
if (!time_is_after_jiffies(timeout))
break;
}
/* re-enable UART (RX) interrupt */
mantis_unmask_ints(mantis, MANTIS_INT_IRQ1);
}
static int mantis_uart_setup(struct mantis_pci *mantis,
struct mantis_uart_params *params)
{
u32 reg;
mmwrite((mmread(MANTIS_UART_CTL) | (params->parity & 0x3)), MANTIS_UART_CTL);
reg = mmread(MANTIS_UART_BAUD);
switch (params->baud_rate) {
case MANTIS_BAUD_9600:
reg |= 0xd8;
break;
case MANTIS_BAUD_19200:
reg |= 0x6c;
break;
case MANTIS_BAUD_38400:
reg |= 0x36;
break;
case MANTIS_BAUD_57600:
reg |= 0x23;
break;
case MANTIS_BAUD_115200:
reg |= 0x11;
break;
default:
return -EINVAL;
}
mmwrite(reg, MANTIS_UART_BAUD);
return 0;
}
int mantis_uart_init(struct mantis_pci *mantis)
{
struct mantis_hwconfig *config = mantis->hwconfig;
struct mantis_uart_params params;
/* default parity: */
params.baud_rate = config->baud_rate;
params.parity = config->parity;
dprintk(MANTIS_INFO, 1, "Initializing UART @ %sbps parity:%s",
rates[params.baud_rate].string,
parity[params.parity].string);
INIT_WORK(&mantis->uart_work, mantis_uart_work);
/* disable interrupt */
mmwrite(mmread(MANTIS_UART_CTL) & 0xffef, MANTIS_UART_CTL);
mantis_uart_setup(mantis, ¶ms);
/* default 1 byte */
mmwrite((mmread(MANTIS_UART_BAUD) | (config->bytes << 8)), MANTIS_UART_BAUD);
/* flush buffer */
mmwrite((mmread(MANTIS_UART_CTL) | MANTIS_UART_RXFLUSH), MANTIS_UART_CTL);
/* enable interrupt */
mmwrite(mmread(MANTIS_UART_CTL) | MANTIS_UART_RXINT, MANTIS_UART_CTL);
mantis_unmask_ints(mantis, MANTIS_INT_IRQ1);
schedule_work(&mantis->uart_work);
dprintk(MANTIS_DEBUG, 1, "UART successfully initialized");
return 0;
}
EXPORT_SYMBOL_GPL(mantis_uart_init);
void mantis_uart_exit(struct mantis_pci *mantis)
{
/* disable interrupt */
mantis_mask_ints(mantis, MANTIS_INT_IRQ1);
mmwrite(mmread(MANTIS_UART_CTL) & 0xffef, MANTIS_UART_CTL);
flush_work(&mantis->uart_work);
}
EXPORT_SYMBOL_GPL(mantis_uart_exit);
| linux-master | drivers/media/pci/mantis/mantis_uart.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis PCI bridge driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/signal.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "mantis_common.h"
#include "mantis_link.h"
#include "mantis_hif.h"
#include "mantis_reg.h"
#include "mantis_ca.h"
static int mantis_ca_read_attr_mem(struct dvb_ca_en50221 *en50221, int slot, int addr)
{
struct mantis_ca *ca = en50221->data;
struct mantis_pci *mantis = ca->ca_priv;
dprintk(MANTIS_DEBUG, 1, "Slot(%d): Request Attribute Mem Read", slot);
if (slot != 0)
return -EINVAL;
return mantis_hif_read_mem(ca, addr);
}
static int mantis_ca_write_attr_mem(struct dvb_ca_en50221 *en50221, int slot, int addr, u8 data)
{
struct mantis_ca *ca = en50221->data;
struct mantis_pci *mantis = ca->ca_priv;
dprintk(MANTIS_DEBUG, 1, "Slot(%d): Request Attribute Mem Write", slot);
if (slot != 0)
return -EINVAL;
return mantis_hif_write_mem(ca, addr, data);
}
static int mantis_ca_read_cam_ctl(struct dvb_ca_en50221 *en50221, int slot, u8 addr)
{
struct mantis_ca *ca = en50221->data;
struct mantis_pci *mantis = ca->ca_priv;
dprintk(MANTIS_DEBUG, 1, "Slot(%d): Request CAM control Read", slot);
if (slot != 0)
return -EINVAL;
return mantis_hif_read_iom(ca, addr);
}
static int mantis_ca_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot, u8 addr, u8 data)
{
struct mantis_ca *ca = en50221->data;
struct mantis_pci *mantis = ca->ca_priv;
dprintk(MANTIS_DEBUG, 1, "Slot(%d): Request CAM control Write", slot);
if (slot != 0)
return -EINVAL;
return mantis_hif_write_iom(ca, addr, data);
}
static int mantis_ca_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
{
struct mantis_ca *ca = en50221->data;
struct mantis_pci *mantis = ca->ca_priv;
dprintk(MANTIS_DEBUG, 1, "Slot(%d): Slot RESET", slot);
udelay(500); /* Wait.. */
mmwrite(0xda, MANTIS_PCMCIA_RESET); /* Leading edge assert */
udelay(500);
mmwrite(0x00, MANTIS_PCMCIA_RESET); /* Trailing edge deassert */
msleep(1000);
dvb_ca_en50221_camready_irq(&ca->en50221, 0);
return 0;
}
static int mantis_ca_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
{
struct mantis_ca *ca = en50221->data;
struct mantis_pci *mantis = ca->ca_priv;
dprintk(MANTIS_DEBUG, 1, "Slot(%d): Slot shutdown", slot);
return 0;
}
static int mantis_ts_control(struct dvb_ca_en50221 *en50221, int slot)
{
struct mantis_ca *ca = en50221->data;
struct mantis_pci *mantis = ca->ca_priv;
dprintk(MANTIS_DEBUG, 1, "Slot(%d): TS control", slot);
return 0;
}
static int mantis_slot_status(struct dvb_ca_en50221 *en50221, int slot, int open)
{
struct mantis_ca *ca = en50221->data;
struct mantis_pci *mantis = ca->ca_priv;
dprintk(MANTIS_DEBUG, 1, "Slot(%d): Poll Slot status", slot);
if (ca->slot_state == MODULE_INSERTED) {
dprintk(MANTIS_DEBUG, 1, "CA Module present and ready");
return DVB_CA_EN50221_POLL_CAM_PRESENT | DVB_CA_EN50221_POLL_CAM_READY;
} else {
dprintk(MANTIS_DEBUG, 1, "CA Module not present or not ready");
}
return 0;
}
int mantis_ca_init(struct mantis_pci *mantis)
{
struct dvb_adapter *dvb_adapter = &mantis->dvb_adapter;
struct mantis_ca *ca;
int ca_flags = 0, result;
dprintk(MANTIS_DEBUG, 1, "Initializing Mantis CA");
ca = kzalloc(sizeof(struct mantis_ca), GFP_KERNEL);
if (!ca) {
dprintk(MANTIS_ERROR, 1, "Out of memory!, exiting ..");
result = -ENOMEM;
goto err;
}
ca->ca_priv = mantis;
mantis->mantis_ca = ca;
ca_flags = DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE;
/* register CA interface */
ca->en50221.owner = THIS_MODULE;
ca->en50221.read_attribute_mem = mantis_ca_read_attr_mem;
ca->en50221.write_attribute_mem = mantis_ca_write_attr_mem;
ca->en50221.read_cam_control = mantis_ca_read_cam_ctl;
ca->en50221.write_cam_control = mantis_ca_write_cam_ctl;
ca->en50221.slot_reset = mantis_ca_slot_reset;
ca->en50221.slot_shutdown = mantis_ca_slot_shutdown;
ca->en50221.slot_ts_enable = mantis_ts_control;
ca->en50221.poll_slot_status = mantis_slot_status;
ca->en50221.data = ca;
mutex_init(&ca->ca_lock);
init_waitqueue_head(&ca->hif_data_wq);
init_waitqueue_head(&ca->hif_opdone_wq);
init_waitqueue_head(&ca->hif_write_wq);
dprintk(MANTIS_ERROR, 1, "Registering EN50221 device");
result = dvb_ca_en50221_init(dvb_adapter, &ca->en50221, ca_flags, 1);
if (result != 0) {
dprintk(MANTIS_ERROR, 1, "EN50221: Initialization failed <%d>", result);
goto err;
}
dprintk(MANTIS_ERROR, 1, "Registered EN50221 device");
mantis_evmgr_init(ca);
return 0;
err:
kfree(ca);
return result;
}
EXPORT_SYMBOL_GPL(mantis_ca_init);
void mantis_ca_exit(struct mantis_pci *mantis)
{
struct mantis_ca *ca = mantis->mantis_ca;
dprintk(MANTIS_DEBUG, 1, "Mantis CA exit");
if (!ca)
return;
mantis_evmgr_exit(ca);
dprintk(MANTIS_ERROR, 1, "Unregistering EN50221 device");
dvb_ca_en50221_release(&ca->en50221);
kfree(ca);
}
EXPORT_SYMBOL_GPL(mantis_ca_exit);
| linux-master | drivers/media/pci/mantis/mantis_ca.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis PCI bridge driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <asm/irq.h>
#include <linux/interrupt.h>
#include <media/rc-map.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "mantis_common.h"
#include "mantis_vp1033.h"
#include "mantis_vp1034.h"
#include "mantis_vp1041.h"
#include "mantis_vp2033.h"
#include "mantis_vp2040.h"
#include "mantis_vp3030.h"
#include "mantis_dma.h"
#include "mantis_ca.h"
#include "mantis_dvb.h"
#include "mantis_uart.h"
#include "mantis_ioc.h"
#include "mantis_pci.h"
#include "mantis_i2c.h"
#include "mantis_reg.h"
#include "mantis_input.h"
static unsigned int verbose;
module_param(verbose, int, 0644);
MODULE_PARM_DESC(verbose, "verbose startup messages, default is 0 (no)");
static int devs;
#define DRIVER_NAME "Mantis"
static char *label[10] = {
"DMA",
"IRQ-0",
"IRQ-1",
"OCERR",
"PABRT",
"RIPRR",
"PPERR",
"FTRGT",
"RISCI",
"RACK"
};
static irqreturn_t mantis_irq_handler(int irq, void *dev_id)
{
u32 stat = 0, mask = 0;
u32 rst_stat = 0, rst_mask = 0;
struct mantis_pci *mantis;
struct mantis_ca *ca;
mantis = (struct mantis_pci *) dev_id;
if (unlikely(!mantis))
return IRQ_NONE;
ca = mantis->mantis_ca;
stat = mmread(MANTIS_INT_STAT);
mask = mmread(MANTIS_INT_MASK);
if (!(stat & mask))
return IRQ_NONE;
rst_mask = MANTIS_GPIF_WRACK |
MANTIS_GPIF_OTHERR |
MANTIS_SBUF_WSTO |
MANTIS_GPIF_EXTIRQ;
rst_stat = mmread(MANTIS_GPIF_STATUS);
rst_stat &= rst_mask;
mmwrite(rst_stat, MANTIS_GPIF_STATUS);
mantis->mantis_int_stat = stat;
mantis->mantis_int_mask = mask;
dprintk(MANTIS_DEBUG, 0, "\n-- Stat=<%02x> Mask=<%02x> --", stat, mask);
if (stat & MANTIS_INT_RISCEN) {
dprintk(MANTIS_DEBUG, 0, "<%s>", label[0]);
}
if (stat & MANTIS_INT_IRQ0) {
dprintk(MANTIS_DEBUG, 0, "<%s>", label[1]);
mantis->gpif_status = rst_stat;
wake_up(&ca->hif_write_wq);
schedule_work(&ca->hif_evm_work);
}
if (stat & MANTIS_INT_IRQ1) {
dprintk(MANTIS_DEBUG, 0, "<%s>", label[2]);
spin_lock(&mantis->intmask_lock);
mmwrite(mmread(MANTIS_INT_MASK) & ~MANTIS_INT_IRQ1,
MANTIS_INT_MASK);
spin_unlock(&mantis->intmask_lock);
schedule_work(&mantis->uart_work);
}
if (stat & MANTIS_INT_OCERR) {
dprintk(MANTIS_DEBUG, 0, "<%s>", label[3]);
}
if (stat & MANTIS_INT_PABORT) {
dprintk(MANTIS_DEBUG, 0, "<%s>", label[4]);
}
if (stat & MANTIS_INT_RIPERR) {
dprintk(MANTIS_DEBUG, 0, "<%s>", label[5]);
}
if (stat & MANTIS_INT_PPERR) {
dprintk(MANTIS_DEBUG, 0, "<%s>", label[6]);
}
if (stat & MANTIS_INT_FTRGT) {
dprintk(MANTIS_DEBUG, 0, "<%s>", label[7]);
}
if (stat & MANTIS_INT_RISCI) {
dprintk(MANTIS_DEBUG, 0, "<%s>", label[8]);
mantis->busy_block = (stat & MANTIS_INT_RISCSTAT) >> 28;
tasklet_schedule(&mantis->tasklet);
}
if (stat & MANTIS_INT_I2CDONE) {
dprintk(MANTIS_DEBUG, 0, "<%s>", label[9]);
wake_up(&mantis->i2c_wq);
}
mmwrite(stat, MANTIS_INT_STAT);
stat &= ~(MANTIS_INT_RISCEN | MANTIS_INT_I2CDONE |
MANTIS_INT_I2CRACK | MANTIS_INT_PCMCIA7 |
MANTIS_INT_PCMCIA6 | MANTIS_INT_PCMCIA5 |
MANTIS_INT_PCMCIA4 | MANTIS_INT_PCMCIA3 |
MANTIS_INT_PCMCIA2 | MANTIS_INT_PCMCIA1 |
MANTIS_INT_PCMCIA0 | MANTIS_INT_IRQ1 |
MANTIS_INT_IRQ0 | MANTIS_INT_OCERR |
MANTIS_INT_PABORT | MANTIS_INT_RIPERR |
MANTIS_INT_PPERR | MANTIS_INT_FTRGT |
MANTIS_INT_RISCI);
if (stat)
dprintk(MANTIS_DEBUG, 0, "<Unknown> Stat=<%02x> Mask=<%02x>", stat, mask);
dprintk(MANTIS_DEBUG, 0, "\n");
return IRQ_HANDLED;
}
static int mantis_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *pci_id)
{
struct mantis_pci_drvdata *drvdata;
struct mantis_pci *mantis;
struct mantis_hwconfig *config;
int err;
mantis = kzalloc(sizeof(*mantis), GFP_KERNEL);
if (!mantis)
return -ENOMEM;
drvdata = (void *)pci_id->driver_data;
mantis->num = devs;
mantis->verbose = verbose;
mantis->pdev = pdev;
config = drvdata->hwconfig;
config->irq_handler = &mantis_irq_handler;
mantis->hwconfig = config;
mantis->rc_map_name = drvdata->rc_map_name;
spin_lock_init(&mantis->intmask_lock);
err = mantis_pci_init(mantis);
if (err) {
dprintk(MANTIS_ERROR, 1, "ERROR: Mantis PCI initialization failed <%d>", err);
goto err_free_mantis;
}
err = mantis_stream_control(mantis, STREAM_TO_HIF);
if (err < 0) {
dprintk(MANTIS_ERROR, 1, "ERROR: Mantis stream control failed <%d>", err);
goto err_pci_exit;
}
err = mantis_i2c_init(mantis);
if (err < 0) {
dprintk(MANTIS_ERROR, 1, "ERROR: Mantis I2C initialization failed <%d>", err);
goto err_pci_exit;
}
err = mantis_get_mac(mantis);
if (err < 0) {
dprintk(MANTIS_ERROR, 1, "ERROR: Mantis MAC address read failed <%d>", err);
goto err_i2c_exit;
}
err = mantis_dma_init(mantis);
if (err < 0) {
dprintk(MANTIS_ERROR, 1, "ERROR: Mantis DMA initialization failed <%d>", err);
goto err_i2c_exit;
}
err = mantis_dvb_init(mantis);
if (err < 0) {
dprintk(MANTIS_ERROR, 1, "ERROR: Mantis DVB initialization failed <%d>", err);
goto err_dma_exit;
}
err = mantis_input_init(mantis);
if (err < 0) {
dprintk(MANTIS_ERROR, 1,
"ERROR: Mantis DVB initialization failed <%d>", err);
goto err_dvb_exit;
}
err = mantis_uart_init(mantis);
if (err < 0) {
dprintk(MANTIS_ERROR, 1, "ERROR: Mantis UART initialization failed <%d>", err);
goto err_input_exit;
}
devs++;
return 0;
err_input_exit:
mantis_input_exit(mantis);
err_dvb_exit:
mantis_dvb_exit(mantis);
err_dma_exit:
mantis_dma_exit(mantis);
err_i2c_exit:
mantis_i2c_exit(mantis);
err_pci_exit:
mantis_pci_exit(mantis);
err_free_mantis:
kfree(mantis);
return err;
}
static void mantis_pci_remove(struct pci_dev *pdev)
{
struct mantis_pci *mantis = pci_get_drvdata(pdev);
if (mantis) {
mantis_uart_exit(mantis);
mantis_input_exit(mantis);
mantis_dvb_exit(mantis);
mantis_dma_exit(mantis);
mantis_i2c_exit(mantis);
mantis_pci_exit(mantis);
kfree(mantis);
}
return;
}
static const struct pci_device_id mantis_pci_table[] = {
MAKE_ENTRY(TECHNISAT, CABLESTAR_HD2, &vp2040_config,
RC_MAP_TECHNISAT_TS35),
MAKE_ENTRY(TECHNISAT, SKYSTAR_HD2_10, &vp1041_config,
NULL),
MAKE_ENTRY(TECHNISAT, SKYSTAR_HD2_20, &vp1041_config,
NULL),
MAKE_ENTRY(TERRATEC, CINERGY_C, &vp2040_config,
RC_MAP_TERRATEC_CINERGY_C_PCI),
MAKE_ENTRY(TERRATEC, CINERGY_S2_PCI_HD, &vp1041_config,
RC_MAP_TERRATEC_CINERGY_S2_HD),
MAKE_ENTRY(TWINHAN_TECHNOLOGIES, MANTIS_VP_1033_DVB_S, &vp1033_config,
NULL),
MAKE_ENTRY(TWINHAN_TECHNOLOGIES, MANTIS_VP_1034_DVB_S, &vp1034_config,
NULL),
MAKE_ENTRY(TWINHAN_TECHNOLOGIES, MANTIS_VP_1041_DVB_S2, &vp1041_config,
RC_MAP_TWINHAN_DTV_CAB_CI),
MAKE_ENTRY(TWINHAN_TECHNOLOGIES, MANTIS_VP_2033_DVB_C, &vp2033_config,
RC_MAP_TWINHAN_DTV_CAB_CI),
MAKE_ENTRY(TWINHAN_TECHNOLOGIES, MANTIS_VP_2040_DVB_C, &vp2040_config,
NULL),
MAKE_ENTRY(TWINHAN_TECHNOLOGIES, MANTIS_VP_3030_DVB_T, &vp3030_config,
NULL),
{ }
};
MODULE_DEVICE_TABLE(pci, mantis_pci_table);
static struct pci_driver mantis_pci_driver = {
.name = DRIVER_NAME,
.id_table = mantis_pci_table,
.probe = mantis_pci_probe,
.remove = mantis_pci_remove,
};
module_pci_driver(mantis_pci_driver);
MODULE_DESCRIPTION("MANTIS driver");
MODULE_AUTHOR("Manu Abraham");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/pci/mantis/mantis_cards.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis VP-2033 driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "tda1002x.h"
#include "mantis_common.h"
#include "mantis_ioc.h"
#include "mantis_dvb.h"
#include "mantis_vp2033.h"
#define MANTIS_MODEL_NAME "VP-2033"
#define MANTIS_DEV_TYPE "DVB-C"
static struct tda1002x_config vp2033_tda1002x_cu1216_config = {
.demod_address = 0x18 >> 1,
.invert = 1,
};
static struct tda10023_config vp2033_tda10023_cu1216_config = {
.demod_address = 0x18 >> 1,
.invert = 1,
};
static u8 read_pwm(struct mantis_pci *mantis)
{
struct i2c_adapter *adapter = &mantis->adapter;
u8 b = 0xff;
u8 pwm;
struct i2c_msg msg[] = {
{.addr = 0x50, .flags = 0, .buf = &b, .len = 1},
{.addr = 0x50, .flags = I2C_M_RD, .buf = &pwm, .len = 1}
};
if ((i2c_transfer(adapter, msg, 2) != 2)
|| (pwm == 0xff))
pwm = 0x48;
return pwm;
}
static int tda1002x_cu1216_tuner_set(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct mantis_pci *mantis = fe->dvb->priv;
struct i2c_adapter *adapter = &mantis->adapter;
u8 buf[6];
struct i2c_msg msg = {.addr = 0x60, .flags = 0, .buf = buf, .len = sizeof(buf)};
int i;
#define CU1216_IF 36125000
#define TUNER_MUL 62500
u32 div = (p->frequency + CU1216_IF + TUNER_MUL / 2) / TUNER_MUL;
buf[0] = (div >> 8) & 0x7f;
buf[1] = div & 0xff;
buf[2] = 0xce;
buf[3] = (p->frequency < 150000000 ? 0x01 :
p->frequency < 445000000 ? 0x02 : 0x04);
buf[4] = 0xde;
buf[5] = 0x20;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(adapter, &msg, 1) != 1)
return -EIO;
/* wait for the pll lock */
msg.flags = I2C_M_RD;
msg.len = 1;
for (i = 0; i < 20; i++) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(adapter, &msg, 1) == 1 && (buf[0] & 0x40))
break;
msleep(10);
}
/* switch the charge pump to the lower current */
msg.flags = 0;
msg.len = 2;
msg.buf = &buf[2];
buf[2] &= ~0x40;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(adapter, &msg, 1) != 1)
return -EIO;
return 0;
}
static int vp2033_frontend_init(struct mantis_pci *mantis, struct dvb_frontend *fe)
{
struct i2c_adapter *adapter = &mantis->adapter;
int err = 0;
err = mantis_frontend_power(mantis, POWER_ON);
if (err == 0) {
mantis_frontend_soft_reset(mantis);
msleep(250);
dprintk(MANTIS_ERROR, 1, "Probing for CU1216 (DVB-C)");
fe = dvb_attach(tda10021_attach, &vp2033_tda1002x_cu1216_config,
adapter,
read_pwm(mantis));
if (fe) {
dprintk(MANTIS_ERROR, 1,
"found Philips CU1216 DVB-C frontend (TDA10021) @ 0x%02x",
vp2033_tda1002x_cu1216_config.demod_address);
} else {
fe = dvb_attach(tda10023_attach, &vp2033_tda10023_cu1216_config,
adapter,
read_pwm(mantis));
if (fe) {
dprintk(MANTIS_ERROR, 1,
"found Philips CU1216 DVB-C frontend (TDA10023) @ 0x%02x",
vp2033_tda1002x_cu1216_config.demod_address);
}
}
if (fe) {
fe->ops.tuner_ops.set_params = tda1002x_cu1216_tuner_set;
dprintk(MANTIS_ERROR, 1, "Mantis DVB-C Philips CU1216 frontend attach success");
} else {
return -1;
}
} else {
dprintk(MANTIS_ERROR, 1, "Frontend on <%s> POWER ON failed! <%d>",
adapter->name,
err);
return -EIO;
}
mantis->fe = fe;
dprintk(MANTIS_DEBUG, 1, "Done!");
return 0;
}
struct mantis_hwconfig vp2033_config = {
.model_name = MANTIS_MODEL_NAME,
.dev_type = MANTIS_DEV_TYPE,
.ts_size = MANTIS_TS_204,
.baud_rate = MANTIS_BAUD_9600,
.parity = MANTIS_PARITY_NONE,
.bytes = 0,
.frontend_init = vp2033_frontend_init,
.power = GPIF_A12,
.reset = GPIF_A13,
};
| linux-master | drivers/media/pci/mantis/mantis_vp2033.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis PCI bridge driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "mantis_common.h"
#include "mantis_link.h" /* temporary due to physical layer stuff */
#include "mantis_reg.h"
/*
* If Slot state is already PLUG_IN event and we are called
* again, definitely it is jitter alone
*/
void mantis_event_cam_plugin(struct mantis_ca *ca)
{
struct mantis_pci *mantis = ca->ca_priv;
u32 gpif_irqcfg;
if (ca->slot_state == MODULE_XTRACTED) {
dprintk(MANTIS_DEBUG, 1, "Event: CAM Plugged IN: Adapter(%d) Slot(0)", mantis->num);
udelay(50);
mmwrite(0xda000000, MANTIS_CARD_RESET);
gpif_irqcfg = mmread(MANTIS_GPIF_IRQCFG);
gpif_irqcfg |= MANTIS_MASK_PLUGOUT;
gpif_irqcfg &= ~MANTIS_MASK_PLUGIN;
mmwrite(gpif_irqcfg, MANTIS_GPIF_IRQCFG);
udelay(500);
ca->slot_state = MODULE_INSERTED;
}
udelay(100);
}
/*
* If Slot state is already UN_PLUG event and we are called
* again, definitely it is jitter alone
*/
void mantis_event_cam_unplug(struct mantis_ca *ca)
{
struct mantis_pci *mantis = ca->ca_priv;
u32 gpif_irqcfg;
if (ca->slot_state == MODULE_INSERTED) {
dprintk(MANTIS_DEBUG, 1, "Event: CAM Unplugged: Adapter(%d) Slot(0)", mantis->num);
udelay(50);
mmwrite(0x00da0000, MANTIS_CARD_RESET);
gpif_irqcfg = mmread(MANTIS_GPIF_IRQCFG);
gpif_irqcfg |= MANTIS_MASK_PLUGIN;
gpif_irqcfg &= ~MANTIS_MASK_PLUGOUT;
mmwrite(gpif_irqcfg, MANTIS_GPIF_IRQCFG);
udelay(500);
ca->slot_state = MODULE_XTRACTED;
}
udelay(100);
}
int mantis_pcmcia_init(struct mantis_ca *ca)
{
struct mantis_pci *mantis = ca->ca_priv;
u32 gpif_stat, card_stat;
mantis_unmask_ints(mantis, MANTIS_INT_IRQ0);
gpif_stat = mmread(MANTIS_GPIF_STATUS);
card_stat = mmread(MANTIS_GPIF_IRQCFG);
if (gpif_stat & MANTIS_GPIF_DETSTAT) {
dprintk(MANTIS_DEBUG, 1, "CAM found on Adapter(%d) Slot(0)", mantis->num);
mmwrite(card_stat | MANTIS_MASK_PLUGOUT, MANTIS_GPIF_IRQCFG);
ca->slot_state = MODULE_INSERTED;
dvb_ca_en50221_camchange_irq(&ca->en50221,
0,
DVB_CA_EN50221_CAMCHANGE_INSERTED);
} else {
dprintk(MANTIS_DEBUG, 1, "Empty Slot on Adapter(%d) Slot(0)", mantis->num);
mmwrite(card_stat | MANTIS_MASK_PLUGIN, MANTIS_GPIF_IRQCFG);
ca->slot_state = MODULE_XTRACTED;
dvb_ca_en50221_camchange_irq(&ca->en50221,
0,
DVB_CA_EN50221_CAMCHANGE_REMOVED);
}
return 0;
}
void mantis_pcmcia_exit(struct mantis_ca *ca)
{
struct mantis_pci *mantis = ca->ca_priv;
mmwrite(mmread(MANTIS_GPIF_STATUS) & (~MANTIS_CARD_PLUGOUT | ~MANTIS_CARD_PLUGIN), MANTIS_GPIF_STATUS);
mantis_mask_ints(mantis, MANTIS_INT_IRQ0);
}
| linux-master | drivers/media/pci/mantis/mantis_pcmcia.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
Mantis PCI bridge driver
Copyright (C) Manu Abraham ([email protected])
*/
#include <linux/kernel.h>
#include <asm/page.h>
#include <linux/vmalloc.h>
#include <linux/pci.h>
#include <asm/irq.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <media/dmxdev.h>
#include <media/dvbdev.h>
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include <media/dvb_net.h>
#include "mantis_common.h"
#include "mantis_reg.h"
#include "mantis_dma.h"
#define RISC_WRITE (0x01 << 28)
#define RISC_JUMP (0x07 << 28)
#define RISC_IRQ (0x01 << 24)
#define RISC_STATUS(status) ((((~status) & 0x0f) << 20) | ((status & 0x0f) << 16))
#define RISC_FLUSH(risc_pos) (risc_pos = 0)
#define RISC_INSTR(risc_pos, opcode) (mantis->risc_cpu[risc_pos++] = cpu_to_le32(opcode))
#define MANTIS_BUF_SIZE (64 * 1024)
#define MANTIS_BLOCK_BYTES (MANTIS_BUF_SIZE / 4)
#define MANTIS_DMA_TR_BYTES (2 * 1024) /* upper limit: 4095 bytes. */
#define MANTIS_BLOCK_COUNT (MANTIS_BUF_SIZE / MANTIS_BLOCK_BYTES)
#define MANTIS_DMA_TR_UNITS (MANTIS_BLOCK_BYTES / MANTIS_DMA_TR_BYTES)
/* MANTIS_BUF_SIZE / MANTIS_DMA_TR_UNITS must not exceed MANTIS_RISC_SIZE (4k RISC cmd buffer) */
#define MANTIS_RISC_SIZE PAGE_SIZE /* RISC program must fit here. */
int mantis_dma_exit(struct mantis_pci *mantis)
{
if (mantis->buf_cpu) {
dprintk(MANTIS_ERROR, 1,
"DMA=0x%lx cpu=0x%p size=%d",
(unsigned long) mantis->buf_dma,
mantis->buf_cpu,
MANTIS_BUF_SIZE);
dma_free_coherent(&mantis->pdev->dev, MANTIS_BUF_SIZE,
mantis->buf_cpu, mantis->buf_dma);
mantis->buf_cpu = NULL;
}
if (mantis->risc_cpu) {
dprintk(MANTIS_ERROR, 1,
"RISC=0x%lx cpu=0x%p size=%lx",
(unsigned long) mantis->risc_dma,
mantis->risc_cpu,
MANTIS_RISC_SIZE);
dma_free_coherent(&mantis->pdev->dev, MANTIS_RISC_SIZE,
mantis->risc_cpu, mantis->risc_dma);
mantis->risc_cpu = NULL;
}
return 0;
}
EXPORT_SYMBOL_GPL(mantis_dma_exit);
static inline int mantis_alloc_buffers(struct mantis_pci *mantis)
{
if (!mantis->buf_cpu) {
mantis->buf_cpu = dma_alloc_coherent(&mantis->pdev->dev,
MANTIS_BUF_SIZE,
&mantis->buf_dma, GFP_KERNEL);
if (!mantis->buf_cpu) {
dprintk(MANTIS_ERROR, 1,
"DMA buffer allocation failed");
goto err;
}
dprintk(MANTIS_ERROR, 1,
"DMA=0x%lx cpu=0x%p size=%d",
(unsigned long) mantis->buf_dma,
mantis->buf_cpu, MANTIS_BUF_SIZE);
}
if (!mantis->risc_cpu) {
mantis->risc_cpu = dma_alloc_coherent(&mantis->pdev->dev,
MANTIS_RISC_SIZE,
&mantis->risc_dma, GFP_KERNEL);
if (!mantis->risc_cpu) {
dprintk(MANTIS_ERROR, 1,
"RISC program allocation failed");
mantis_dma_exit(mantis);
goto err;
}
dprintk(MANTIS_ERROR, 1,
"RISC=0x%lx cpu=0x%p size=%lx",
(unsigned long) mantis->risc_dma,
mantis->risc_cpu, MANTIS_RISC_SIZE);
}
return 0;
err:
dprintk(MANTIS_ERROR, 1, "Out of memory (?) .....");
return -ENOMEM;
}
int mantis_dma_init(struct mantis_pci *mantis)
{
int err;
dprintk(MANTIS_DEBUG, 1, "Mantis DMA init");
err = mantis_alloc_buffers(mantis);
if (err < 0) {
dprintk(MANTIS_ERROR, 1, "Error allocating DMA buffer");
/* Stop RISC Engine */
mmwrite(0, MANTIS_DMA_CTL);
return err;
}
return 0;
}
EXPORT_SYMBOL_GPL(mantis_dma_init);
static inline void mantis_risc_program(struct mantis_pci *mantis)
{
u32 buf_pos = 0;
u32 line, step;
u32 risc_pos;
dprintk(MANTIS_DEBUG, 1, "Mantis create RISC program");
RISC_FLUSH(risc_pos);
dprintk(MANTIS_DEBUG, 1, "risc len lines %u, bytes per line %u, bytes per DMA tr %u",
MANTIS_BLOCK_COUNT, MANTIS_BLOCK_BYTES, MANTIS_DMA_TR_BYTES);
for (line = 0; line < MANTIS_BLOCK_COUNT; line++) {
for (step = 0; step < MANTIS_DMA_TR_UNITS; step++) {
dprintk(MANTIS_DEBUG, 1, "RISC PROG line=[%d], step=[%d]", line, step);
if (step == 0) {
RISC_INSTR(risc_pos, RISC_WRITE |
RISC_IRQ |
RISC_STATUS(line) |
MANTIS_DMA_TR_BYTES);
} else {
RISC_INSTR(risc_pos, RISC_WRITE | MANTIS_DMA_TR_BYTES);
}
RISC_INSTR(risc_pos, mantis->buf_dma + buf_pos);
buf_pos += MANTIS_DMA_TR_BYTES;
}
}
RISC_INSTR(risc_pos, RISC_JUMP);
RISC_INSTR(risc_pos, mantis->risc_dma);
}
void mantis_dma_start(struct mantis_pci *mantis)
{
dprintk(MANTIS_DEBUG, 1, "Mantis Start DMA engine");
mantis_risc_program(mantis);
mmwrite(mantis->risc_dma, MANTIS_RISC_START);
mmwrite(mmread(MANTIS_GPIF_ADDR) | MANTIS_GPIF_HIFRDWRN, MANTIS_GPIF_ADDR);
mmwrite(0, MANTIS_DMA_CTL);
mantis->last_block = mantis->busy_block = 0;
mantis_unmask_ints(mantis, MANTIS_INT_RISCI);
mmwrite(MANTIS_FIFO_EN | MANTIS_DCAP_EN
| MANTIS_RISC_EN, MANTIS_DMA_CTL);
}
void mantis_dma_stop(struct mantis_pci *mantis)
{
dprintk(MANTIS_DEBUG, 1, "Mantis Stop DMA engine");
mmwrite((mmread(MANTIS_GPIF_ADDR) & (~(MANTIS_GPIF_HIFRDWRN))), MANTIS_GPIF_ADDR);
mmwrite((mmread(MANTIS_DMA_CTL) & ~(MANTIS_FIFO_EN |
MANTIS_DCAP_EN |
MANTIS_RISC_EN)), MANTIS_DMA_CTL);
mmwrite(mmread(MANTIS_INT_STAT), MANTIS_INT_STAT);
mantis_mask_ints(mantis, MANTIS_INT_RISCI | MANTIS_INT_RISCEN);
}
void mantis_dma_xfer(struct tasklet_struct *t)
{
struct mantis_pci *mantis = from_tasklet(mantis, t, tasklet);
struct mantis_hwconfig *config = mantis->hwconfig;
while (mantis->last_block != mantis->busy_block) {
dprintk(MANTIS_DEBUG, 1, "last block=[%d] finished block=[%d]",
mantis->last_block, mantis->busy_block);
(config->ts_size ? dvb_dmx_swfilter_204 : dvb_dmx_swfilter)
(&mantis->demux, &mantis->buf_cpu[mantis->last_block * MANTIS_BLOCK_BYTES], MANTIS_BLOCK_BYTES);
mantis->last_block = (mantis->last_block + 1) % MANTIS_BLOCK_COUNT;
}
}
| linux-master | drivers/media/pci/mantis/mantis_dma.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Silicon Labs C8051F300 microcontroller.
*
* It is used for LNB power control in TeVii S470,
* TBS 6920 PCIe DVB-S2 cards.
*
* Microcontroller connected to cx23885 GPIO pins:
* GPIO0 - data - P0.3 F300
* GPIO1 - reset - P0.2 F300
* GPIO2 - clk - P0.1 F300
* GPIO3 - busy - P0.0 F300
*
* Copyright (C) 2009 Igor M. Liplianin <[email protected]>
*/
#include "cx23885.h"
#include "cx23885-f300.h"
#define F300_DATA GPIO_0
#define F300_RESET GPIO_1
#define F300_CLK GPIO_2
#define F300_BUSY GPIO_3
static void f300_set_line(struct cx23885_dev *dev, u32 line, u8 lvl)
{
cx23885_gpio_enable(dev, line, 1);
if (lvl == 1)
cx23885_gpio_set(dev, line);
else
cx23885_gpio_clear(dev, line);
}
static u8 f300_get_line(struct cx23885_dev *dev, u32 line)
{
cx23885_gpio_enable(dev, line, 0);
return cx23885_gpio_get(dev, line);
}
static void f300_send_byte(struct cx23885_dev *dev, u8 dta)
{
u8 i;
for (i = 0; i < 8; i++) {
f300_set_line(dev, F300_CLK, 0);
udelay(30);
f300_set_line(dev, F300_DATA, (dta & 0x80) >> 7);/* msb first */
udelay(30);
dta <<= 1;
f300_set_line(dev, F300_CLK, 1);
udelay(30);
}
}
static u8 f300_get_byte(struct cx23885_dev *dev)
{
u8 i, dta = 0;
for (i = 0; i < 8; i++) {
f300_set_line(dev, F300_CLK, 0);
udelay(30);
dta <<= 1;
f300_set_line(dev, F300_CLK, 1);
udelay(30);
dta |= f300_get_line(dev, F300_DATA);/* msb first */
}
return dta;
}
static u8 f300_xfer(struct dvb_frontend *fe, u8 *buf)
{
struct cx23885_tsport *port = fe->dvb->priv;
struct cx23885_dev *dev = port->dev;
u8 i, temp, ret = 0;
temp = buf[0];
for (i = 0; i < buf[0]; i++)
temp += buf[i + 1];
temp = (~temp + 1);/* get check sum */
buf[1 + buf[0]] = temp;
f300_set_line(dev, F300_RESET, 1);
f300_set_line(dev, F300_CLK, 1);
udelay(30);
f300_set_line(dev, F300_DATA, 1);
msleep(1);
/* question: */
f300_set_line(dev, F300_RESET, 0);/* begin to send data */
msleep(1);
f300_send_byte(dev, 0xe0);/* the slave address is 0xe0, write */
msleep(1);
temp = buf[0];
temp += 2;
for (i = 0; i < temp; i++)
f300_send_byte(dev, buf[i]);
f300_set_line(dev, F300_RESET, 1);/* sent data over */
f300_set_line(dev, F300_DATA, 1);
/* answer: */
temp = 0;
for (i = 0; ((i < 8) & (temp == 0)); i++) {
msleep(1);
if (f300_get_line(dev, F300_BUSY) == 0)
temp = 1;
}
if (i > 7) {
pr_err("%s: timeout, the slave no response\n",
__func__);
ret = 1; /* timeout, the slave no response */
} else { /* the slave not busy, prepare for getting data */
f300_set_line(dev, F300_RESET, 0);/*ready...*/
msleep(1);
f300_send_byte(dev, 0xe1);/* 0xe1 is Read */
msleep(1);
temp = f300_get_byte(dev);/*get the data length */
if (temp > 14)
temp = 14;
for (i = 0; i < (temp + 1); i++)
f300_get_byte(dev);/* get data to empty buffer */
f300_set_line(dev, F300_RESET, 1);/* received data over */
f300_set_line(dev, F300_DATA, 1);
}
return ret;
}
int f300_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)
{
u8 buf[16];
buf[0] = 0x05;
buf[1] = 0x38;/* write port */
buf[2] = 0x01;/* A port, lnb power */
switch (voltage) {
case SEC_VOLTAGE_13:
buf[3] = 0x01;/* power on */
buf[4] = 0x02;/* B port, H/V */
buf[5] = 0x00;/*13V v*/
break;
case SEC_VOLTAGE_18:
buf[3] = 0x01;
buf[4] = 0x02;
buf[5] = 0x01;/* 18V h*/
break;
case SEC_VOLTAGE_OFF:
buf[3] = 0x00;/* power off */
buf[4] = 0x00;
buf[5] = 0x00;
break;
}
return f300_xfer(fe, buf);
}
| linux-master | drivers/media/pci/cx23885/cx23885-f300.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* netup-init.c
*
* NetUP Dual DVB-S2 CI driver
*
* Copyright (C) 2009 NetUP Inc.
* Copyright (C) 2009 Igor M. Liplianin <[email protected]>
* Copyright (C) 2009 Abylay Ospan <[email protected]>
*/
#include "cx23885.h"
#include "netup-init.h"
static void i2c_av_write(struct i2c_adapter *i2c, u16 reg, u8 val)
{
int ret;
u8 buf[3];
struct i2c_msg msg = {
.addr = 0x88 >> 1,
.flags = 0,
.buf = buf,
.len = 3
};
buf[0] = reg >> 8;
buf[1] = reg & 0xff;
buf[2] = val;
ret = i2c_transfer(i2c, &msg, 1);
if (ret != 1)
pr_err("%s: i2c write error!\n", __func__);
}
static void i2c_av_write4(struct i2c_adapter *i2c, u16 reg, u32 val)
{
int ret;
u8 buf[6];
struct i2c_msg msg = {
.addr = 0x88 >> 1,
.flags = 0,
.buf = buf,
.len = 6
};
buf[0] = reg >> 8;
buf[1] = reg & 0xff;
buf[2] = val & 0xff;
buf[3] = (val >> 8) & 0xff;
buf[4] = (val >> 16) & 0xff;
buf[5] = val >> 24;
ret = i2c_transfer(i2c, &msg, 1);
if (ret != 1)
pr_err("%s: i2c write error!\n", __func__);
}
static u8 i2c_av_read(struct i2c_adapter *i2c, u16 reg)
{
int ret;
u8 buf[2];
struct i2c_msg msg = {
.addr = 0x88 >> 1,
.flags = 0,
.buf = buf,
.len = 2
};
buf[0] = reg >> 8;
buf[1] = reg & 0xff;
ret = i2c_transfer(i2c, &msg, 1);
if (ret != 1)
pr_err("%s: i2c write error!\n", __func__);
msg.flags = I2C_M_RD;
msg.len = 1;
ret = i2c_transfer(i2c, &msg, 1);
if (ret != 1)
pr_err("%s: i2c read error!\n", __func__);
return buf[0];
}
static void i2c_av_and_or(struct i2c_adapter *i2c, u16 reg, unsigned and_mask,
u8 or_value)
{
i2c_av_write(i2c, reg, (i2c_av_read(i2c, reg) & and_mask) | or_value);
}
/* set 27MHz on AUX_CLK */
void netup_initialize(struct cx23885_dev *dev)
{
struct cx23885_i2c *i2c_bus = &dev->i2c_bus[2];
struct i2c_adapter *i2c = &i2c_bus->i2c_adap;
/* Stop microcontroller */
i2c_av_and_or(i2c, 0x803, ~0x10, 0x00);
/* Aux PLL frac for 27 MHz */
i2c_av_write4(i2c, 0x114, 0xea0eb3);
/* Aux PLL int for 27 MHz */
i2c_av_write4(i2c, 0x110, 0x090319);
/* start microcontroller */
i2c_av_and_or(i2c, 0x803, ~0x10, 0x10);
}
| linux-master | drivers/media/pci/cx23885/netup-init.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cimax2.c
*
* CIMax2(R) SP2 driver in conjunction with NetUp Dual DVB-S2 CI card
*
* Copyright (C) 2009 NetUP Inc.
* Copyright (C) 2009 Igor M. Liplianin <[email protected]>
* Copyright (C) 2009 Abylay Ospan <[email protected]>
*/
#include "cx23885.h"
#include "cimax2.h"
#include <media/dvb_ca_en50221.h>
/* Max transfer size done by I2C transfer functions */
#define MAX_XFER_SIZE 64
/**** Bit definitions for MC417_RWD and MC417_OEN registers ***
bits 31-16
+-----------+
| Reserved |
+-----------+
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
+-------+-------+-------+-------+-------+-------+-------+-------+
| WR# | RD# | | ACK# | ADHI | ADLO | CS1# | CS0# |
+-------+-------+-------+-------+-------+-------+-------+-------+
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
+-------+-------+-------+-------+-------+-------+-------+-------+
| DATA7| DATA6| DATA5| DATA4| DATA3| DATA2| DATA1| DATA0|
+-------+-------+-------+-------+-------+-------+-------+-------+
***/
/* MC417 */
#define NETUP_DATA 0x000000ff
#define NETUP_WR 0x00008000
#define NETUP_RD 0x00004000
#define NETUP_ACK 0x00001000
#define NETUP_ADHI 0x00000800
#define NETUP_ADLO 0x00000400
#define NETUP_CS1 0x00000200
#define NETUP_CS0 0x00000100
#define NETUP_EN_ALL 0x00001000
#define NETUP_CTRL_OFF (NETUP_CS1 | NETUP_CS0 | NETUP_WR | NETUP_RD)
#define NETUP_CI_CTL 0x04
#define NETUP_CI_RD 1
#define NETUP_IRQ_DETAM 0x1
#define NETUP_IRQ_IRQAM 0x4
static unsigned int ci_dbg;
module_param(ci_dbg, int, 0644);
MODULE_PARM_DESC(ci_dbg, "Enable CI debugging");
static unsigned int ci_irq_enable;
module_param(ci_irq_enable, int, 0644);
MODULE_PARM_DESC(ci_irq_enable, "Enable IRQ from CAM");
#define ci_dbg_print(fmt, args...) \
do { \
if (ci_dbg) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##args); \
} while (0)
#define ci_irq_flags() (ci_irq_enable ? NETUP_IRQ_IRQAM : 0)
/* stores all private variables for communication with CI */
struct netup_ci_state {
struct dvb_ca_en50221 ca;
struct mutex ca_mutex;
struct i2c_adapter *i2c_adap;
u8 ci_i2c_addr;
int status;
struct work_struct work;
void *priv;
u8 current_irq_mode;
int current_ci_flag;
unsigned long next_status_checked_time;
};
static int netup_read_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
u8 *buf, int len)
{
int ret;
struct i2c_msg msg[] = {
{
.addr = addr,
.flags = 0,
.buf = ®,
.len = 1
}, {
.addr = addr,
.flags = I2C_M_RD,
.buf = buf,
.len = len
}
};
ret = i2c_transfer(i2c_adap, msg, 2);
if (ret != 2) {
ci_dbg_print("%s: i2c read error, Reg = 0x%02x, Status = %d\n",
__func__, reg, ret);
return -1;
}
ci_dbg_print("%s: i2c read Addr=0x%04x, Reg = 0x%02x, data = %02x\n",
__func__, addr, reg, buf[0]);
return 0;
}
static int netup_write_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
u8 *buf, int len)
{
int ret;
u8 buffer[MAX_XFER_SIZE];
struct i2c_msg msg = {
.addr = addr,
.flags = 0,
.buf = &buffer[0],
.len = len + 1
};
if (1 + len > sizeof(buffer)) {
pr_warn("%s: i2c wr reg=%04x: len=%d is too big!\n",
KBUILD_MODNAME, reg, len);
return -EINVAL;
}
buffer[0] = reg;
memcpy(&buffer[1], buf, len);
ret = i2c_transfer(i2c_adap, &msg, 1);
if (ret != 1) {
ci_dbg_print("%s: i2c write error, Reg=[0x%02x], Status=%d\n",
__func__, reg, ret);
return -1;
}
return 0;
}
static int netup_ci_get_mem(struct cx23885_dev *dev)
{
int mem;
unsigned long timeout = jiffies + msecs_to_jiffies(1);
for (;;) {
mem = cx_read(MC417_RWD);
if ((mem & NETUP_ACK) == 0)
break;
if (time_after(jiffies, timeout))
break;
udelay(1);
}
cx_set(MC417_RWD, NETUP_CTRL_OFF);
return mem & 0xff;
}
static int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
u8 flag, u8 read, int addr, u8 data)
{
struct netup_ci_state *state = en50221->data;
struct cx23885_tsport *port = state->priv;
struct cx23885_dev *dev = port->dev;
u8 store;
int mem;
int ret;
if (0 != slot)
return -EINVAL;
if (state->current_ci_flag != flag) {
ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
0, &store, 1);
if (ret != 0)
return ret;
store &= ~0x0c;
store |= flag;
ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
0, &store, 1);
if (ret != 0)
return ret;
}
state->current_ci_flag = flag;
mutex_lock(&dev->gpio_lock);
/* write addr */
cx_write(MC417_OEN, NETUP_EN_ALL);
cx_write(MC417_RWD, NETUP_CTRL_OFF |
NETUP_ADLO | (0xff & addr));
cx_clear(MC417_RWD, NETUP_ADLO);
cx_write(MC417_RWD, NETUP_CTRL_OFF |
NETUP_ADHI | (0xff & (addr >> 8)));
cx_clear(MC417_RWD, NETUP_ADHI);
if (read) { /* data in */
cx_write(MC417_OEN, NETUP_EN_ALL | NETUP_DATA);
} else /* data out */
cx_write(MC417_RWD, NETUP_CTRL_OFF | data);
/* choose chip */
cx_clear(MC417_RWD,
(state->ci_i2c_addr == 0x40) ? NETUP_CS0 : NETUP_CS1);
/* read/write */
cx_clear(MC417_RWD, (read) ? NETUP_RD : NETUP_WR);
mem = netup_ci_get_mem(dev);
mutex_unlock(&dev->gpio_lock);
if (!read)
if (mem < 0)
return -EREMOTEIO;
ci_dbg_print("%s: %s: chipaddr=[0x%x] addr=[0x%02x], %s=%x\n", __func__,
(read) ? "read" : "write", state->ci_i2c_addr, addr,
(flag == NETUP_CI_CTL) ? "ctl" : "mem",
(read) ? mem : data);
if (read)
return mem;
return 0;
}
int netup_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
int slot, int addr)
{
return netup_ci_op_cam(en50221, slot, 0, NETUP_CI_RD, addr, 0);
}
int netup_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
int slot, int addr, u8 data)
{
return netup_ci_op_cam(en50221, slot, 0, 0, addr, data);
}
int netup_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
u8 addr)
{
return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL,
NETUP_CI_RD, addr, 0);
}
int netup_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
u8 addr, u8 data)
{
return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL, 0, addr, data);
}
int netup_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
{
struct netup_ci_state *state = en50221->data;
u8 buf = 0x80;
int ret;
if (0 != slot)
return -EINVAL;
udelay(500);
ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
0, &buf, 1);
if (ret != 0)
return ret;
udelay(500);
buf = 0x00;
ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
0, &buf, 1);
msleep(1000);
dvb_ca_en50221_camready_irq(&state->ca, 0);
return 0;
}
int netup_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
{
/* not implemented */
return 0;
}
static int netup_ci_set_irq(struct dvb_ca_en50221 *en50221, u8 irq_mode)
{
struct netup_ci_state *state = en50221->data;
int ret;
if (irq_mode == state->current_irq_mode)
return 0;
ci_dbg_print("%s: chipaddr=[0x%x] setting ci IRQ to [0x%x] \n",
__func__, state->ci_i2c_addr, irq_mode);
ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
0x1b, &irq_mode, 1);
if (ret != 0)
return ret;
state->current_irq_mode = irq_mode;
return 0;
}
int netup_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot)
{
struct netup_ci_state *state = en50221->data;
u8 buf;
if (0 != slot)
return -EINVAL;
netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
0, &buf, 1);
buf |= 0x60;
return netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
0, &buf, 1);
}
/* work handler */
static void netup_read_ci_status(struct work_struct *work)
{
struct netup_ci_state *state =
container_of(work, struct netup_ci_state, work);
u8 buf[33];
int ret;
/* CAM module IRQ processing. fast operation */
dvb_ca_en50221_frda_irq(&state->ca, 0);
/* CAM module INSERT/REMOVE processing. slow operation because of i2c
* transfers */
if (time_after(jiffies, state->next_status_checked_time)
|| !state->status) {
ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
0, &buf[0], 33);
state->next_status_checked_time = jiffies
+ msecs_to_jiffies(1000);
if (ret != 0)
return;
ci_dbg_print("%s: Slot Status Addr=[0x%04x], Reg=[0x%02x], data=%02x, TS config = %02x\n",
__func__, state->ci_i2c_addr, 0, buf[0], buf[0]);
if (buf[0] & 1)
state->status = DVB_CA_EN50221_POLL_CAM_PRESENT |
DVB_CA_EN50221_POLL_CAM_READY;
else
state->status = 0;
}
}
/* CI irq handler */
int netup_ci_slot_status(struct cx23885_dev *dev, u32 pci_status)
{
struct cx23885_tsport *port = NULL;
struct netup_ci_state *state = NULL;
ci_dbg_print("%s:\n", __func__);
if (0 == (pci_status & (PCI_MSK_GPIO0 | PCI_MSK_GPIO1)))
return 0;
if (pci_status & PCI_MSK_GPIO0) {
port = &dev->ts1;
state = port->port_priv;
schedule_work(&state->work);
ci_dbg_print("%s: Wakeup CI0\n", __func__);
}
if (pci_status & PCI_MSK_GPIO1) {
port = &dev->ts2;
state = port->port_priv;
schedule_work(&state->work);
ci_dbg_print("%s: Wakeup CI1\n", __func__);
}
return 1;
}
int netup_poll_ci_slot_status(struct dvb_ca_en50221 *en50221,
int slot, int open)
{
struct netup_ci_state *state = en50221->data;
if (0 != slot)
return -EINVAL;
netup_ci_set_irq(en50221, open ? (NETUP_IRQ_DETAM | ci_irq_flags())
: NETUP_IRQ_DETAM);
return state->status;
}
int netup_ci_init(struct cx23885_tsport *port)
{
struct netup_ci_state *state;
u8 cimax_init[34] = {
0x00, /* module A control*/
0x00, /* auto select mask high A */
0x00, /* auto select mask low A */
0x00, /* auto select pattern high A */
0x00, /* auto select pattern low A */
0x44, /* memory access time A */
0x00, /* invert input A */
0x00, /* RFU */
0x00, /* RFU */
0x00, /* module B control*/
0x00, /* auto select mask high B */
0x00, /* auto select mask low B */
0x00, /* auto select pattern high B */
0x00, /* auto select pattern low B */
0x44, /* memory access time B */
0x00, /* invert input B */
0x00, /* RFU */
0x00, /* RFU */
0x00, /* auto select mask high Ext */
0x00, /* auto select mask low Ext */
0x00, /* auto select pattern high Ext */
0x00, /* auto select pattern low Ext */
0x00, /* RFU */
0x02, /* destination - module A */
0x01, /* power on (use it like store place) */
0x00, /* RFU */
0x00, /* int status read only */
ci_irq_flags() | NETUP_IRQ_DETAM, /* DETAM, IRQAM unmasked */
0x05, /* EXTINT=active-high, INT=push-pull */
0x00, /* USCG1 */
0x04, /* ack active low */
0x00, /* LOCK = 0 */
0x33, /* serial mode, rising in, rising out, MSB first*/
0x31, /* synchronization */
};
int ret;
ci_dbg_print("%s\n", __func__);
state = kzalloc(sizeof(struct netup_ci_state), GFP_KERNEL);
if (!state) {
ci_dbg_print("%s: Unable create CI structure!\n", __func__);
ret = -ENOMEM;
goto err;
}
port->port_priv = state;
switch (port->nr) {
case 1:
state->ci_i2c_addr = 0x40;
break;
case 2:
state->ci_i2c_addr = 0x41;
break;
}
state->i2c_adap = &port->dev->i2c_bus[0].i2c_adap;
state->ca.owner = THIS_MODULE;
state->ca.read_attribute_mem = netup_ci_read_attribute_mem;
state->ca.write_attribute_mem = netup_ci_write_attribute_mem;
state->ca.read_cam_control = netup_ci_read_cam_ctl;
state->ca.write_cam_control = netup_ci_write_cam_ctl;
state->ca.slot_reset = netup_ci_slot_reset;
state->ca.slot_shutdown = netup_ci_slot_shutdown;
state->ca.slot_ts_enable = netup_ci_slot_ts_ctl;
state->ca.poll_slot_status = netup_poll_ci_slot_status;
state->ca.data = state;
state->priv = port;
state->current_irq_mode = ci_irq_flags() | NETUP_IRQ_DETAM;
ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
0, &cimax_init[0], 34);
/* lock registers */
ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
0x1f, &cimax_init[0x18], 1);
/* power on slots */
ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
0x18, &cimax_init[0x18], 1);
if (0 != ret)
goto err;
ret = dvb_ca_en50221_init(&port->frontends.adapter,
&state->ca,
/* flags */ 0,
/* n_slots */ 1);
if (0 != ret)
goto err;
INIT_WORK(&state->work, netup_read_ci_status);
schedule_work(&state->work);
ci_dbg_print("%s: CI initialized!\n", __func__);
return 0;
err:
ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret);
kfree(state);
return ret;
}
void netup_ci_exit(struct cx23885_tsport *port)
{
struct netup_ci_state *state;
if (NULL == port)
return;
state = (struct netup_ci_state *)port->port_priv;
if (NULL == state)
return;
if (NULL == state->ca.data)
return;
dvb_ca_en50221_release(&state->ca);
kfree(state);
}
| linux-master | drivers/media/pci/cx23885/cimax2.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Conexant CX23885 PCIe bridge
*
* Copyright (c) 2006 Steven Toth <[email protected]>
*/
#include "cx23885.h"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <media/drv-intf/cx25840.h>
#include <linux/firmware.h>
#include <misc/altera.h>
#include "xc2028.h"
#include "netup-eeprom.h"
#include "netup-init.h"
#include "altera-ci.h"
#include "xc4000.h"
#include "xc5000.h"
#include "cx23888-ir.h"
static unsigned int netup_card_rev = 4;
module_param(netup_card_rev, int, 0644);
MODULE_PARM_DESC(netup_card_rev,
"NetUP Dual DVB-T/C CI card revision");
static unsigned int enable_885_ir;
module_param(enable_885_ir, int, 0644);
MODULE_PARM_DESC(enable_885_ir,
"Enable integrated IR controller for supported\n"
"\t\t CX2388[57] boards that are wired for it:\n"
"\t\t\tHVR-1250 (reported safe)\n"
"\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
"\t\t\tTeVii S470 (reported unsafe)\n"
"\t\t This can cause an interrupt storm with some cards.\n"
"\t\t Default: 0 [Disabled]");
/* ------------------------------------------------------------------ */
/* board config info */
struct cx23885_board cx23885_boards[] = {
[CX23885_BOARD_UNKNOWN] = {
.name = "UNKNOWN/GENERIC",
/* Ensure safe default for unknown boards */
.clk_freq = 0,
.input = {{
.type = CX23885_VMUX_COMPOSITE1,
.vmux = 0,
}, {
.type = CX23885_VMUX_COMPOSITE2,
.vmux = 1,
}, {
.type = CX23885_VMUX_COMPOSITE3,
.vmux = 2,
}, {
.type = CX23885_VMUX_COMPOSITE4,
.vmux = 3,
} },
},
[CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
.name = "Hauppauge WinTV-HVR1800lp",
.portc = CX23885_MPEG_DVB,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0xff00,
}, {
.type = CX23885_VMUX_DEBUG,
.vmux = 0,
.gpio0 = 0xff01,
}, {
.type = CX23885_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0xff02,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0xff02,
} },
},
[CX23885_BOARD_HAUPPAUGE_HVR1800] = {
.name = "Hauppauge WinTV-HVR1800",
.porta = CX23885_ANALOG_VIDEO,
.portb = CX23885_MPEG_ENCODER,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_PHILIPS_TDA8290,
.tuner_addr = 0x42, /* 0x84 >> 1 */
.tuner_bus = 1,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN5_CH2 |
CX25840_VIN2_CH1,
.amux = CX25840_AUDIO8,
.gpio0 = 0,
}, {
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN4_CH2 |
CX25840_VIN6_CH1,
.amux = CX25840_AUDIO7,
.gpio0 = 0,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN4_CH2 |
CX25840_VIN8_CH1 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO7,
.gpio0 = 0,
} },
},
[CX23885_BOARD_HAUPPAUGE_HVR1250] = {
.name = "Hauppauge WinTV-HVR1250",
.porta = CX23885_ANALOG_VIDEO,
.portc = CX23885_MPEG_DVB,
#ifdef MT2131_NO_ANALOG_SUPPORT_YET
.tuner_type = TUNER_PHILIPS_TDA8290,
.tuner_addr = 0x42, /* 0x84 >> 1 */
.tuner_bus = 1,
#endif
.force_bff = 1,
.input = {{
#ifdef MT2131_NO_ANALOG_SUPPORT_YET
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN5_CH2 |
CX25840_VIN2_CH1,
.amux = CX25840_AUDIO8,
.gpio0 = 0xff00,
}, {
#endif
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN4_CH2 |
CX25840_VIN6_CH1,
.amux = CX25840_AUDIO7,
.gpio0 = 0xff02,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN4_CH2 |
CX25840_VIN8_CH1 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO7,
.gpio0 = 0xff02,
} },
},
[CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
.name = "DViCO FusionHDTV5 Express",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
.name = "Hauppauge WinTV-HVR1500Q",
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_HAUPPAUGE_HVR1500] = {
.name = "Hauppauge WinTV-HVR1500",
.porta = CX23885_ANALOG_VIDEO,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61, /* 0xc2 >> 1 */
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN5_CH2 |
CX25840_VIN2_CH1,
.gpio0 = 0,
}, {
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN4_CH2 |
CX25840_VIN6_CH1,
.gpio0 = 0,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN4_CH2 |
CX25840_VIN8_CH1 |
CX25840_SVIDEO_ON,
.gpio0 = 0,
} },
},
[CX23885_BOARD_HAUPPAUGE_HVR1200] = {
.name = "Hauppauge WinTV-HVR1200",
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_HAUPPAUGE_HVR1700] = {
.name = "Hauppauge WinTV-HVR1700",
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_HAUPPAUGE_HVR1400] = {
.name = "Hauppauge WinTV-HVR1400",
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
.name = "DViCO FusionHDTV7 Dual Express",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
.name = "DViCO FusionHDTV DVB-T Dual Express",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
.name = "Leadtek Winfast PxDVR3200 H",
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = {
.name = "Leadtek Winfast PxPVR2200",
.porta = CX23885_ANALOG_VIDEO,
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61,
.tuner_bus = 1,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN2_CH1 |
CX25840_VIN5_CH2,
.amux = CX25840_AUDIO8,
.gpio0 = 0x704040,
}, {
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_COMPOSITE1,
.amux = CX25840_AUDIO7,
.gpio0 = 0x704040,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_SVIDEO_LUMA3 |
CX25840_SVIDEO_CHROMA4,
.amux = CX25840_AUDIO7,
.gpio0 = 0x704040,
}, {
.type = CX23885_VMUX_COMPONENT,
.vmux = CX25840_VIN7_CH1 |
CX25840_VIN6_CH2 |
CX25840_VIN8_CH3 |
CX25840_COMPONENT_ON,
.amux = CX25840_AUDIO7,
.gpio0 = 0x704040,
} },
},
[CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
.name = "Leadtek Winfast PxDVR3200 H XC4000",
.porta = CX23885_ANALOG_VIDEO,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_XC4000,
.tuner_addr = 0x61,
.radio_type = UNSET,
.radio_addr = ADDR_UNSET,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN2_CH1 |
CX25840_VIN5_CH2 |
CX25840_NONE0_CH3,
}, {
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_COMPOSITE1,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_SVIDEO_LUMA3 |
CX25840_SVIDEO_CHROMA4,
}, {
.type = CX23885_VMUX_COMPONENT,
.vmux = CX25840_VIN7_CH1 |
CX25840_VIN6_CH2 |
CX25840_VIN8_CH3 |
CX25840_COMPONENT_ON,
} },
},
[CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
.name = "Compro VideoMate E650F",
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_TBS_6920] = {
.name = "TurboSight TBS 6920",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_TBS_6980] = {
.name = "TurboSight TBS 6980",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_TBS_6981] = {
.name = "TurboSight TBS 6981",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_TEVII_S470] = {
.name = "TeVii S470",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_DVBWORLD_2005] = {
.name = "DVBWorld DVB-S2 2005",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
.ci_type = 1,
.name = "NetUP Dual DVB-S2 CI",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_HAUPPAUGE_HVR1270] = {
.name = "Hauppauge WinTV-HVR1270",
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_HAUPPAUGE_HVR1275] = {
.name = "Hauppauge WinTV-HVR1275",
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_HAUPPAUGE_HVR1255] = {
.name = "Hauppauge WinTV-HVR1255",
.porta = CX23885_ANALOG_VIDEO,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_ABSENT,
.tuner_addr = 0x42, /* 0x84 >> 1 */
.force_bff = 1,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN5_CH2 |
CX25840_VIN2_CH1 |
CX25840_DIF_ON,
.amux = CX25840_AUDIO8,
}, {
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN4_CH2 |
CX25840_VIN6_CH1,
.amux = CX25840_AUDIO7,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN4_CH2 |
CX25840_VIN8_CH1 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO7,
} },
},
[CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
.name = "Hauppauge WinTV-HVR1255",
.porta = CX23885_ANALOG_VIDEO,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_ABSENT,
.tuner_addr = 0x42, /* 0x84 >> 1 */
.force_bff = 1,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN5_CH2 |
CX25840_VIN2_CH1 |
CX25840_DIF_ON,
.amux = CX25840_AUDIO8,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN4_CH2 |
CX25840_VIN8_CH1 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO7,
} },
},
[CX23885_BOARD_HAUPPAUGE_HVR1210] = {
.name = "Hauppauge WinTV-HVR1210",
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_MYGICA_X8506] = {
.name = "Mygica X8506 DMB-TH",
.tuner_type = TUNER_XC5000,
.tuner_addr = 0x61,
.tuner_bus = 1,
.porta = CX23885_ANALOG_VIDEO,
.portb = CX23885_MPEG_DVB,
.input = {
{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_COMPOSITE2,
},
{
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_COMPOSITE8,
},
{
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_SVIDEO_LUMA3 |
CX25840_SVIDEO_CHROMA4,
},
{
.type = CX23885_VMUX_COMPONENT,
.vmux = CX25840_COMPONENT_ON |
CX25840_VIN1_CH1 |
CX25840_VIN6_CH2 |
CX25840_VIN7_CH3,
},
},
},
[CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
.name = "Magic-Pro ProHDTV Extreme 2",
.tuner_type = TUNER_XC5000,
.tuner_addr = 0x61,
.tuner_bus = 1,
.porta = CX23885_ANALOG_VIDEO,
.portb = CX23885_MPEG_DVB,
.input = {
{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_COMPOSITE2,
},
{
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_COMPOSITE8,
},
{
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_SVIDEO_LUMA3 |
CX25840_SVIDEO_CHROMA4,
},
{
.type = CX23885_VMUX_COMPONENT,
.vmux = CX25840_COMPONENT_ON |
CX25840_VIN1_CH1 |
CX25840_VIN6_CH2 |
CX25840_VIN7_CH3,
},
},
},
[CX23885_BOARD_HAUPPAUGE_HVR1850] = {
.name = "Hauppauge WinTV-HVR1850",
.porta = CX23885_ANALOG_VIDEO,
.portb = CX23885_MPEG_ENCODER,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_ABSENT,
.tuner_addr = 0x42, /* 0x84 >> 1 */
.force_bff = 1,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN5_CH2 |
CX25840_VIN2_CH1 |
CX25840_DIF_ON,
.amux = CX25840_AUDIO8,
}, {
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN4_CH2 |
CX25840_VIN6_CH1,
.amux = CX25840_AUDIO7,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN4_CH2 |
CX25840_VIN8_CH1 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO7,
} },
},
[CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
.name = "Compro VideoMate E800",
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_HAUPPAUGE_HVR1290] = {
.name = "Hauppauge WinTV-HVR1290",
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_MYGICA_X8558PRO] = {
.name = "Mygica X8558 PRO DMB-TH",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
.name = "LEADTEK WinFast PxTV1200",
.porta = CX23885_ANALOG_VIDEO,
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61,
.tuner_bus = 1,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN2_CH1 |
CX25840_VIN5_CH2 |
CX25840_NONE0_CH3,
}, {
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_COMPOSITE1,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_SVIDEO_LUMA3 |
CX25840_SVIDEO_CHROMA4,
}, {
.type = CX23885_VMUX_COMPONENT,
.vmux = CX25840_VIN7_CH1 |
CX25840_VIN6_CH2 |
CX25840_VIN8_CH3 |
CX25840_COMPONENT_ON,
} },
},
[CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
.name = "GoTView X5 3D Hybrid",
.tuner_type = TUNER_XC5000,
.tuner_addr = 0x64,
.tuner_bus = 1,
.porta = CX23885_ANALOG_VIDEO,
.portb = CX23885_MPEG_DVB,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN2_CH1 |
CX25840_VIN5_CH2,
.gpio0 = 0x02,
}, {
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX23885_VMUX_COMPOSITE1,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_SVIDEO_LUMA3 |
CX25840_SVIDEO_CHROMA4,
} },
},
[CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
.ci_type = 2,
.name = "NetUP Dual DVB-T/C-CI RF",
.porta = CX23885_ANALOG_VIDEO,
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
.num_fds_portb = 2,
.num_fds_portc = 2,
.tuner_type = TUNER_XC5000,
.tuner_addr = 0x64,
.input = { {
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_COMPOSITE1,
} },
},
[CX23885_BOARD_MPX885] = {
.name = "MPX-885",
.porta = CX23885_ANALOG_VIDEO,
.input = {{
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_COMPOSITE1,
.amux = CX25840_AUDIO6,
.gpio0 = 0,
}, {
.type = CX23885_VMUX_COMPOSITE2,
.vmux = CX25840_COMPOSITE2,
.amux = CX25840_AUDIO6,
.gpio0 = 0,
}, {
.type = CX23885_VMUX_COMPOSITE3,
.vmux = CX25840_COMPOSITE3,
.amux = CX25840_AUDIO7,
.gpio0 = 0,
}, {
.type = CX23885_VMUX_COMPOSITE4,
.vmux = CX25840_COMPOSITE4,
.amux = CX25840_AUDIO7,
.gpio0 = 0,
} },
},
[CX23885_BOARD_MYGICA_X8507] = {
.name = "Mygica X8502/X8507 ISDB-T",
.tuner_type = TUNER_XC5000,
.tuner_addr = 0x61,
.tuner_bus = 1,
.porta = CX23885_ANALOG_VIDEO,
.portb = CX23885_MPEG_DVB,
.input = {
{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_COMPOSITE2,
.amux = CX25840_AUDIO8,
},
{
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_COMPOSITE8,
.amux = CX25840_AUDIO7,
},
{
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_SVIDEO_LUMA3 |
CX25840_SVIDEO_CHROMA4,
.amux = CX25840_AUDIO7,
},
{
.type = CX23885_VMUX_COMPONENT,
.vmux = CX25840_COMPONENT_ON |
CX25840_VIN1_CH1 |
CX25840_VIN6_CH2 |
CX25840_VIN7_CH3,
.amux = CX25840_AUDIO7,
},
},
},
[CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
.name = "TerraTec Cinergy T PCIe Dual",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_TEVII_S471] = {
.name = "TeVii S471",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_PROF_8000] = {
.name = "Prof Revolution DVB-S2 8000",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_HAUPPAUGE_HVR4400] = {
.name = "Hauppauge WinTV-HVR4400/HVR5500",
.porta = CX23885_ANALOG_VIDEO,
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_NXP_TDA18271,
.tuner_addr = 0x60, /* 0xc0 >> 1 */
.tuner_bus = 1,
},
[CX23885_BOARD_HAUPPAUGE_STARBURST] = {
.name = "Hauppauge WinTV Starburst",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_AVERMEDIA_HC81R] = {
.name = "AVerTV Hybrid Express Slim HC81R",
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61, /* 0xc2 >> 1 */
.tuner_bus = 1,
.porta = CX23885_ANALOG_VIDEO,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN2_CH1 |
CX25840_VIN5_CH2 |
CX25840_NONE0_CH3 |
CX25840_NONE1_CH3,
.amux = CX25840_AUDIO8,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN8_CH1 |
CX25840_NONE_CH2 |
CX25840_VIN7_CH3 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO6,
}, {
.type = CX23885_VMUX_COMPONENT,
.vmux = CX25840_VIN1_CH1 |
CX25840_NONE_CH2 |
CX25840_NONE0_CH3 |
CX25840_NONE1_CH3,
.amux = CX25840_AUDIO6,
} },
},
[CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = {
.name = "DViCO FusionHDTV DVB-T Dual Express2",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = {
.name = "Hauppauge ImpactVCB-e",
.tuner_type = TUNER_ABSENT,
.porta = CX23885_ANALOG_VIDEO,
.input = {{
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_VIN6_CH1,
.amux = CX25840_AUDIO7,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN4_CH2 |
CX25840_VIN8_CH1 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO7,
} },
},
[CX23885_BOARD_DVBSKY_T9580] = {
.name = "DVBSky T9580",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_DVBSKY_T980C] = {
.name = "DVBSky T980C",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_DVBSKY_S950C] = {
.name = "DVBSky S950C",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_TT_CT2_4500_CI] = {
.name = "Technotrend TT-budget CT2-4500 CI",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_DVBSKY_S950] = {
.name = "DVBSky S950",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_DVBSKY_S952] = {
.name = "DVBSky S952",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_DVBSKY_T982] = {
.name = "DVBSky T982",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
},
[CX23885_BOARD_HAUPPAUGE_HVR5525] = {
.name = "Hauppauge WinTV-HVR5525",
.porta = CX23885_ANALOG_VIDEO,
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_ABSENT,
.force_bff = 1,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN5_CH2 |
CX25840_VIN2_CH1 |
CX25840_DIF_ON,
.amux = CX25840_AUDIO8,
}, {
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_VIN6_CH1,
.amux = CX25840_AUDIO7,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN8_CH1 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO7,
} },
},
[CX23885_BOARD_VIEWCAST_260E] = {
.name = "ViewCast 260e",
.porta = CX23885_ANALOG_VIDEO,
.force_bff = 1,
.input = {{
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_VIN6_CH1,
.amux = CX25840_AUDIO7,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN5_CH1 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO7,
}, {
.type = CX23885_VMUX_COMPONENT,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN6_CH2 |
CX25840_VIN5_CH1 |
CX25840_COMPONENT_ON,
.amux = CX25840_AUDIO7,
} },
},
[CX23885_BOARD_VIEWCAST_460E] = {
.name = "ViewCast 460e",
.porta = CX23885_ANALOG_VIDEO,
.force_bff = 1,
.input = {{
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_VIN4_CH1,
.amux = CX25840_AUDIO7,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN6_CH1 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO7,
}, {
.type = CX23885_VMUX_COMPONENT,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN6_CH1 |
CX25840_VIN5_CH2 |
CX25840_COMPONENT_ON,
.amux = CX25840_AUDIO7,
}, {
.type = CX23885_VMUX_COMPOSITE2,
.vmux = CX25840_VIN6_CH1,
.amux = CX25840_AUDIO7,
} },
},
[CX23885_BOARD_HAUPPAUGE_QUADHD_DVB] = {
.name = "Hauppauge WinTV-QuadHD-DVB",
.porta = CX23885_ANALOG_VIDEO,
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_ABSENT,
.force_bff = 1,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN5_CH2 |
CX25840_VIN2_CH1 |
CX25840_DIF_ON,
.amux = CX25840_AUDIO8,
} },
},
[CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885] = {
.name = "Hauppauge WinTV-QuadHD-DVB(885)",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_ABSENT,
},
[CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC] = {
.name = "Hauppauge WinTV-QuadHD-ATSC",
.porta = CX23885_ANALOG_VIDEO,
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_ABSENT,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN5_CH2 |
CX25840_VIN2_CH1 |
CX25840_DIF_ON,
.amux = CX25840_AUDIO8,
} },
},
[CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885] = {
.name = "Hauppauge WinTV-QuadHD-ATSC(885)",
.portb = CX23885_MPEG_DVB,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_ABSENT,
},
[CX23885_BOARD_HAUPPAUGE_HVR1265_K4] = {
.name = "Hauppauge WinTV-HVR-1265(161111)",
.porta = CX23885_ANALOG_VIDEO,
.portc = CX23885_MPEG_DVB,
.tuner_type = TUNER_ABSENT,
.input = {{
.type = CX23885_VMUX_TELEVISION,
.vmux = CX25840_VIN7_CH3 |
CX25840_VIN5_CH2 |
CX25840_VIN2_CH1 |
CX25840_DIF_ON,
.amux = CX25840_AUDIO8,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN4_CH2 |
CX25840_VIN6_CH1 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO7,
} },
},
[CX23885_BOARD_HAUPPAUGE_STARBURST2] = {
.name = "Hauppauge WinTV-Starburst2",
.portb = CX23885_MPEG_DVB,
},
[CX23885_BOARD_AVERMEDIA_CE310B] = {
.name = "AVerMedia CE310B",
.porta = CX23885_ANALOG_VIDEO,
.force_bff = 1,
.input = {{
.type = CX23885_VMUX_COMPOSITE1,
.vmux = CX25840_VIN1_CH1 |
CX25840_NONE_CH2 |
CX25840_NONE0_CH3,
.amux = CX25840_AUDIO7,
}, {
.type = CX23885_VMUX_SVIDEO,
.vmux = CX25840_VIN8_CH1 |
CX25840_NONE_CH2 |
CX25840_VIN7_CH3 |
CX25840_SVIDEO_ON,
.amux = CX25840_AUDIO7,
} },
},
};
const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
/* ------------------------------------------------------------------ */
/* PCI subsystem IDs */
struct cx23885_subid cx23885_subids[] = {
{
.subvendor = 0x0070,
.subdevice = 0x3400,
.card = CX23885_BOARD_UNKNOWN,
}, {
.subvendor = 0x0070,
.subdevice = 0x7600,
.card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
}, {
.subvendor = 0x0070,
.subdevice = 0x7800,
.card = CX23885_BOARD_HAUPPAUGE_HVR1800,
}, {
.subvendor = 0x0070,
.subdevice = 0x7801,
.card = CX23885_BOARD_HAUPPAUGE_HVR1800,
}, {
.subvendor = 0x0070,
.subdevice = 0x7809,
.card = CX23885_BOARD_HAUPPAUGE_HVR1800,
}, {
.subvendor = 0x0070,
.subdevice = 0x7911,
.card = CX23885_BOARD_HAUPPAUGE_HVR1250,
}, {
.subvendor = 0x18ac,
.subdevice = 0xd500,
.card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
}, {
.subvendor = 0x0070,
.subdevice = 0x7790,
.card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
}, {
.subvendor = 0x0070,
.subdevice = 0x7797,
.card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
}, {
.subvendor = 0x0070,
.subdevice = 0x7710,
.card = CX23885_BOARD_HAUPPAUGE_HVR1500,
}, {
.subvendor = 0x0070,
.subdevice = 0x7717,
.card = CX23885_BOARD_HAUPPAUGE_HVR1500,
}, {
.subvendor = 0x0070,
.subdevice = 0x71d1,
.card = CX23885_BOARD_HAUPPAUGE_HVR1200,
}, {
.subvendor = 0x0070,
.subdevice = 0x71d3,
.card = CX23885_BOARD_HAUPPAUGE_HVR1200,
}, {
.subvendor = 0x0070,
.subdevice = 0x8101,
.card = CX23885_BOARD_HAUPPAUGE_HVR1700,
}, {
.subvendor = 0x0070,
.subdevice = 0x8010,
.card = CX23885_BOARD_HAUPPAUGE_HVR1400,
}, {
.subvendor = 0x18ac,
.subdevice = 0xd618,
.card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
}, {
.subvendor = 0x18ac,
.subdevice = 0xdb78,
.card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
}, {
.subvendor = 0x107d,
.subdevice = 0x6681,
.card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
}, {
.subvendor = 0x107d,
.subdevice = 0x6f21,
.card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200,
}, {
.subvendor = 0x107d,
.subdevice = 0x6f39,
.card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
}, {
.subvendor = 0x185b,
.subdevice = 0xe800,
.card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
}, {
.subvendor = 0x6920,
.subdevice = 0x8888,
.card = CX23885_BOARD_TBS_6920,
}, {
.subvendor = 0x6980,
.subdevice = 0x8888,
.card = CX23885_BOARD_TBS_6980,
}, {
.subvendor = 0x6981,
.subdevice = 0x8888,
.card = CX23885_BOARD_TBS_6981,
}, {
.subvendor = 0xd470,
.subdevice = 0x9022,
.card = CX23885_BOARD_TEVII_S470,
}, {
.subvendor = 0x0001,
.subdevice = 0x2005,
.card = CX23885_BOARD_DVBWORLD_2005,
}, {
.subvendor = 0x1b55,
.subdevice = 0x2a2c,
.card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
}, {
.subvendor = 0x0070,
.subdevice = 0x2211,
.card = CX23885_BOARD_HAUPPAUGE_HVR1270,
}, {
.subvendor = 0x0070,
.subdevice = 0x2215,
.card = CX23885_BOARD_HAUPPAUGE_HVR1275,
}, {
.subvendor = 0x0070,
.subdevice = 0x221d,
.card = CX23885_BOARD_HAUPPAUGE_HVR1275,
}, {
.subvendor = 0x0070,
.subdevice = 0x2251,
.card = CX23885_BOARD_HAUPPAUGE_HVR1255,
}, {
.subvendor = 0x0070,
.subdevice = 0x2259,
.card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
}, {
.subvendor = 0x0070,
.subdevice = 0x2291,
.card = CX23885_BOARD_HAUPPAUGE_HVR1210,
}, {
.subvendor = 0x0070,
.subdevice = 0x2295,
.card = CX23885_BOARD_HAUPPAUGE_HVR1210,
}, {
.subvendor = 0x0070,
.subdevice = 0x2299,
.card = CX23885_BOARD_HAUPPAUGE_HVR1210,
}, {
.subvendor = 0x0070,
.subdevice = 0x229d,
.card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
}, {
.subvendor = 0x0070,
.subdevice = 0x22f0,
.card = CX23885_BOARD_HAUPPAUGE_HVR1210,
}, {
.subvendor = 0x0070,
.subdevice = 0x22f1,
.card = CX23885_BOARD_HAUPPAUGE_HVR1255,
}, {
.subvendor = 0x0070,
.subdevice = 0x22f2,
.card = CX23885_BOARD_HAUPPAUGE_HVR1275,
}, {
.subvendor = 0x0070,
.subdevice = 0x22f3,
.card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
}, {
.subvendor = 0x0070,
.subdevice = 0x22f4,
.card = CX23885_BOARD_HAUPPAUGE_HVR1210,
}, {
.subvendor = 0x0070,
.subdevice = 0x22f5,
.card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
}, {
.subvendor = 0x14f1,
.subdevice = 0x8651,
.card = CX23885_BOARD_MYGICA_X8506,
}, {
.subvendor = 0x14f1,
.subdevice = 0x8657,
.card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
}, {
.subvendor = 0x0070,
.subdevice = 0x8541,
.card = CX23885_BOARD_HAUPPAUGE_HVR1850,
}, {
.subvendor = 0x1858,
.subdevice = 0xe800,
.card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
}, {
.subvendor = 0x0070,
.subdevice = 0x8551,
.card = CX23885_BOARD_HAUPPAUGE_HVR1290,
}, {
.subvendor = 0x14f1,
.subdevice = 0x8578,
.card = CX23885_BOARD_MYGICA_X8558PRO,
}, {
.subvendor = 0x107d,
.subdevice = 0x6f22,
.card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
}, {
.subvendor = 0x5654,
.subdevice = 0x2390,
.card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
}, {
.subvendor = 0x1b55,
.subdevice = 0xe2e4,
.card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
}, {
.subvendor = 0x14f1,
.subdevice = 0x8502,
.card = CX23885_BOARD_MYGICA_X8507,
}, {
.subvendor = 0x153b,
.subdevice = 0x117e,
.card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
}, {
.subvendor = 0xd471,
.subdevice = 0x9022,
.card = CX23885_BOARD_TEVII_S471,
}, {
.subvendor = 0x8000,
.subdevice = 0x3034,
.card = CX23885_BOARD_PROF_8000,
}, {
.subvendor = 0x0070,
.subdevice = 0xc108,
.card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-4400 (Model 121xxx, Hybrid DVB-T/S2, IR) */
}, {
.subvendor = 0x0070,
.subdevice = 0xc138,
.card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
}, {
.subvendor = 0x0070,
.subdevice = 0xc12a,
.card = CX23885_BOARD_HAUPPAUGE_STARBURST, /* Hauppauge WinTV Starburst (Model 121x00, DVB-S2, IR) */
}, {
.subvendor = 0x0070,
.subdevice = 0xc1f8,
.card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
}, {
.subvendor = 0x1461,
.subdevice = 0xd939,
.card = CX23885_BOARD_AVERMEDIA_HC81R,
}, {
.subvendor = 0x0070,
.subdevice = 0x7133,
.card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE,
}, {
.subvendor = 0x0070,
.subdevice = 0x7137,
.card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE,
}, {
.subvendor = 0x18ac,
.subdevice = 0xdb98,
.card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2,
}, {
.subvendor = 0x4254,
.subdevice = 0x9580,
.card = CX23885_BOARD_DVBSKY_T9580,
}, {
.subvendor = 0x4254,
.subdevice = 0x980c,
.card = CX23885_BOARD_DVBSKY_T980C,
}, {
.subvendor = 0x4254,
.subdevice = 0x950c,
.card = CX23885_BOARD_DVBSKY_S950C,
}, {
.subvendor = 0x13c2,
.subdevice = 0x3013,
.card = CX23885_BOARD_TT_CT2_4500_CI,
}, {
.subvendor = 0x4254,
.subdevice = 0x0950,
.card = CX23885_BOARD_DVBSKY_S950,
}, {
.subvendor = 0x4254,
.subdevice = 0x0952,
.card = CX23885_BOARD_DVBSKY_S952,
}, {
.subvendor = 0x4254,
.subdevice = 0x0982,
.card = CX23885_BOARD_DVBSKY_T982,
}, {
.subvendor = 0x0070,
.subdevice = 0xf038,
.card = CX23885_BOARD_HAUPPAUGE_HVR5525,
}, {
.subvendor = 0x1576,
.subdevice = 0x0260,
.card = CX23885_BOARD_VIEWCAST_260E,
}, {
.subvendor = 0x1576,
.subdevice = 0x0460,
.card = CX23885_BOARD_VIEWCAST_460E,
}, {
.subvendor = 0x0070,
.subdevice = 0x6a28,
.card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 1 */
}, {
.subvendor = 0x0070,
.subdevice = 0x6b28,
.card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 2 */
}, {
.subvendor = 0x0070,
.subdevice = 0x6a18,
.card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 1 */
}, {
.subvendor = 0x0070,
.subdevice = 0x6b18,
.card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 2 */
}, {
.subvendor = 0x0070,
.subdevice = 0x2a18,
.card = CX23885_BOARD_HAUPPAUGE_HVR1265_K4, /* Hauppauge WinTV HVR-1265 (Model 161xx1, Hybrid ATSC/QAM-B) */
}, {
.subvendor = 0x0070,
.subdevice = 0xf02a,
.card = CX23885_BOARD_HAUPPAUGE_STARBURST2,
}, {
.subvendor = 0x1461,
.subdevice = 0x3100,
.card = CX23885_BOARD_AVERMEDIA_CE310B,
},
};
const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
void cx23885_card_list(struct cx23885_dev *dev)
{
int i;
if (0 == dev->pci->subsystem_vendor &&
0 == dev->pci->subsystem_device) {
pr_info("%s: Board has no valid PCIe Subsystem ID and can't\n"
"%s: be autodetected. Pass card=<n> insmod option\n"
"%s: to workaround that. Redirect complaints to the\n"
"%s: vendor of the TV card. Best regards,\n"
"%s: -- tux\n",
dev->name, dev->name, dev->name, dev->name, dev->name);
} else {
pr_info("%s: Your board isn't known (yet) to the driver.\n"
"%s: Try to pick one of the existing card configs via\n"
"%s: card=<n> insmod option. Updating to the latest\n"
"%s: version might help as well.\n",
dev->name, dev->name, dev->name, dev->name);
}
pr_info("%s: Here is a list of valid choices for the card=<n> insmod option:\n",
dev->name);
for (i = 0; i < cx23885_bcount; i++)
pr_info("%s: card=%d -> %s\n",
dev->name, i, cx23885_boards[i].name);
}
static void viewcast_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
{
u32 sn;
/* The serial number record begins with tag 0x59 */
if (*(eeprom_data + 0x00) != 0x59) {
pr_info("%s() eeprom records are undefined, no serial number\n",
__func__);
return;
}
sn = (*(eeprom_data + 0x06) << 24) |
(*(eeprom_data + 0x05) << 16) |
(*(eeprom_data + 0x04) << 8) |
(*(eeprom_data + 0x03));
pr_info("%s: card '%s' sn# MM%d\n",
dev->name,
cx23885_boards[dev->board].name,
sn);
}
static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
{
struct tveeprom tv;
tveeprom_hauppauge_analog(&tv, eeprom_data);
/* Make sure we support the board model */
switch (tv.model) {
case 22001:
/* WinTV-HVR1270 (PCIe, Retail, half height)
* ATSC/QAM and basic analog, IR Blast */
case 22009:
/* WinTV-HVR1210 (PCIe, Retail, half height)
* DVB-T and basic analog, IR Blast */
case 22011:
/* WinTV-HVR1270 (PCIe, Retail, half height)
* ATSC/QAM and basic analog, IR Recv */
case 22019:
/* WinTV-HVR1210 (PCIe, Retail, half height)
* DVB-T and basic analog, IR Recv */
case 22021:
/* WinTV-HVR1275 (PCIe, Retail, half height)
* ATSC/QAM and basic analog, IR Recv */
case 22029:
/* WinTV-HVR1210 (PCIe, Retail, half height)
* DVB-T and basic analog, IR Recv */
case 22101:
/* WinTV-HVR1270 (PCIe, Retail, full height)
* ATSC/QAM and basic analog, IR Blast */
case 22109:
/* WinTV-HVR1210 (PCIe, Retail, full height)
* DVB-T and basic analog, IR Blast */
case 22111:
/* WinTV-HVR1270 (PCIe, Retail, full height)
* ATSC/QAM and basic analog, IR Recv */
case 22119:
/* WinTV-HVR1210 (PCIe, Retail, full height)
* DVB-T and basic analog, IR Recv */
case 22121:
/* WinTV-HVR1275 (PCIe, Retail, full height)
* ATSC/QAM and basic analog, IR Recv */
case 22129:
/* WinTV-HVR1210 (PCIe, Retail, full height)
* DVB-T and basic analog, IR Recv */
case 71009:
/* WinTV-HVR1200 (PCIe, Retail, full height)
* DVB-T and basic analog */
case 71100:
/* WinTV-ImpactVCB-e (PCIe, Retail, half height)
* Basic analog */
case 71359:
/* WinTV-HVR1200 (PCIe, OEM, half height)
* DVB-T and basic analog */
case 71439:
/* WinTV-HVR1200 (PCIe, OEM, half height)
* DVB-T and basic analog */
case 71449:
/* WinTV-HVR1200 (PCIe, OEM, full height)
* DVB-T and basic analog */
case 71939:
/* WinTV-HVR1200 (PCIe, OEM, half height)
* DVB-T and basic analog */
case 71949:
/* WinTV-HVR1200 (PCIe, OEM, full height)
* DVB-T and basic analog */
case 71959:
/* WinTV-HVR1200 (PCIe, OEM, full height)
* DVB-T and basic analog */
case 71979:
/* WinTV-HVR1200 (PCIe, OEM, half height)
* DVB-T and basic analog */
case 71999:
/* WinTV-HVR1200 (PCIe, OEM, full height)
* DVB-T and basic analog */
case 76601:
/* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
channel ATSC and MPEG2 HW Encoder */
case 77001:
/* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
and Basic analog */
case 77011:
/* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
and Basic analog */
case 77041:
/* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
and Basic analog */
case 77051:
/* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
and Basic analog */
case 78011:
/* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
Dual channel ATSC and MPEG2 HW Encoder */
case 78501:
/* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
Dual channel ATSC and MPEG2 HW Encoder */
case 78521:
/* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
Dual channel ATSC and MPEG2 HW Encoder */
case 78531:
/* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
Dual channel ATSC and MPEG2 HW Encoder */
case 78631:
/* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
Dual channel ATSC and MPEG2 HW Encoder */
case 79001:
/* WinTV-HVR1250 (PCIe, Retail, IR, full height,
ATSC and Basic analog */
case 79101:
/* WinTV-HVR1250 (PCIe, Retail, IR, half height,
ATSC and Basic analog */
case 79501:
/* WinTV-HVR1250 (PCIe, No IR, half height,
ATSC [at least] and Basic analog) */
case 79561:
/* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
ATSC and Basic analog */
case 79571:
/* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
ATSC and Basic analog */
case 79671:
/* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
ATSC and Basic analog */
case 80019:
/* WinTV-HVR1400 (Express Card, Retail, IR,
* DVB-T and Basic analog */
case 81509:
/* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
* DVB-T and MPEG2 HW Encoder */
case 81519:
/* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
* DVB-T and MPEG2 HW Encoder */
break;
case 85021:
/* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
Dual channel ATSC and MPEG2 HW Encoder */
break;
case 85721:
/* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
Dual channel ATSC and Basic analog */
case 121019:
/* WinTV-HVR4400 (PCIe, DVB-S2, DVB-C/T) */
break;
case 121029:
/* WinTV-HVR5500 (PCIe, DVB-S2, DVB-C/T) */
break;
case 150329:
/* WinTV-HVR5525 (PCIe, DVB-S/S2, DVB-T/T2/C) */
break;
case 161111:
/* WinTV-HVR-1265 K4 (PCIe, Analog/ATSC/QAM-B) */
break;
case 166100: /* 888 version, hybrid */
case 166200: /* 885 version, DVB only */
/* WinTV-QuadHD (DVB) Tuner Pair 1 (PCIe, IR, half height,
DVB-T/T2/C, DVB-T/T2/C */
break;
case 166101: /* 888 version, hybrid */
case 166201: /* 885 version, DVB only */
/* WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height,
DVB-T/T2/C, DVB-T/T2/C */
break;
case 165100: /* 888 version, hybrid */
case 165200: /* 885 version, digital only */
/* WinTV-QuadHD (ATSC) Tuner Pair 1 (PCIe, IR, half height,
* ATSC/QAM-B, ATSC/QAM-B */
break;
case 165101: /* 888 version, hybrid */
case 165201: /* 885 version, digital only */
/* WinTV-QuadHD (ATSC) Tuner Pair 2 (PCIe, IR, half height,
* ATSC/QAM-B, ATSC/QAM-B */
break;
default:
pr_warn("%s: warning: unknown hauppauge model #%d\n",
dev->name, tv.model);
break;
}
pr_info("%s: hauppauge eeprom: model=%d\n",
dev->name, tv.model);
}
/* Some TBS cards require initing a chip using a bitbanged SPI attached
to the cx23885 gpio's. If this chip doesn't get init'ed the demod
doesn't respond to any command. */
static void tbs_card_init(struct cx23885_dev *dev)
{
int i;
static const u8 buf[] = {
0xe0, 0x06, 0x66, 0x33, 0x65,
0x01, 0x17, 0x06, 0xde};
switch (dev->board) {
case CX23885_BOARD_TBS_6980:
case CX23885_BOARD_TBS_6981:
cx_set(GP0_IO, 0x00070007);
usleep_range(1000, 10000);
cx_clear(GP0_IO, 2);
usleep_range(1000, 10000);
for (i = 0; i < 9 * 8; i++) {
cx_clear(GP0_IO, 7);
usleep_range(1000, 10000);
cx_set(GP0_IO,
((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4);
usleep_range(1000, 10000);
}
cx_set(GP0_IO, 7);
break;
}
}
int cx23885_tuner_callback(void *priv, int component, int command, int arg)
{
struct cx23885_tsport *port = priv;
struct cx23885_dev *dev = port->dev;
u32 bitmask = 0;
if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
return 0;
if (command != 0) {
pr_err("%s(): Unknown command 0x%x.\n",
__func__, command);
return -EINVAL;
}
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1400:
case CX23885_BOARD_HAUPPAUGE_HVR1500:
case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
/* Tuner Reset Command */
bitmask = 0x04;
break;
case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
/* Two identical tuners on two different i2c buses,
* we need to reset the correct gpio. */
if (port->nr == 1)
bitmask = 0x01;
else if (port->nr == 2)
bitmask = 0x04;
break;
case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
/* Tuner Reset Command */
bitmask = 0x02;
break;
case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
altera_ci_tuner_reset(dev, port->nr);
break;
case CX23885_BOARD_AVERMEDIA_HC81R:
/* XC3028L Reset Command */
bitmask = 1 << 2;
break;
}
if (bitmask) {
/* Drive the tuner into reset and back out */
cx_clear(GP0_IO, bitmask);
mdelay(200);
cx_set(GP0_IO, bitmask);
}
return 0;
}
void cx23885_gpio_setup(struct cx23885_dev *dev)
{
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1250:
/* GPIO-0 cx24227 demodulator reset */
cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
break;
case CX23885_BOARD_HAUPPAUGE_HVR1500:
/* GPIO-0 cx24227 demodulator */
/* GPIO-2 xc3028 tuner */
/* Put the parts into reset */
cx_set(GP0_IO, 0x00050000);
cx_clear(GP0_IO, 0x00000005);
msleep(5);
/* Bring the parts out of reset */
cx_set(GP0_IO, 0x00050005);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
/* GPIO-0 cx24227 demodulator reset */
/* GPIO-2 xc5000 tuner reset */
cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
break;
case CX23885_BOARD_HAUPPAUGE_HVR1800:
/* GPIO-0 656_CLK */
/* GPIO-1 656_D0 */
/* GPIO-2 8295A Reset */
/* GPIO-3-10 cx23417 data0-7 */
/* GPIO-11-14 cx23417 addr0-3 */
/* GPIO-15-18 cx23417 READY, CS, RD, WR */
/* GPIO-19 IR_RX */
/* CX23417 GPIO's */
/* EIO15 Zilog Reset */
/* EIO14 S5H1409/CX24227 Reset */
mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
/* Put the demod into reset and protect the eeprom */
mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
msleep(100);
/* Bring the demod and blaster out of reset */
mc417_gpio_set(dev, GPIO_15 | GPIO_14);
msleep(100);
/* Force the TDA8295A into reset and back */
cx23885_gpio_enable(dev, GPIO_2, 1);
cx23885_gpio_set(dev, GPIO_2);
msleep(20);
cx23885_gpio_clear(dev, GPIO_2);
msleep(20);
cx23885_gpio_set(dev, GPIO_2);
msleep(20);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1200:
/* GPIO-0 tda10048 demodulator reset */
/* GPIO-2 tda18271 tuner reset */
/* Put the parts into reset and back */
cx_set(GP0_IO, 0x00050000);
msleep(20);
cx_clear(GP0_IO, 0x00000005);
msleep(20);
cx_set(GP0_IO, 0x00050005);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1700:
/* GPIO-0 TDA10048 demodulator reset */
/* GPIO-2 TDA8295A Reset */
/* GPIO-3-10 cx23417 data0-7 */
/* GPIO-11-14 cx23417 addr0-3 */
/* GPIO-15-18 cx23417 READY, CS, RD, WR */
/* The following GPIO's are on the interna AVCore (cx25840) */
/* GPIO-19 IR_RX */
/* GPIO-20 IR_TX 416/DVBT Select */
/* GPIO-21 IIS DAT */
/* GPIO-22 IIS WCLK */
/* GPIO-23 IIS BCLK */
/* Put the parts into reset and back */
cx_set(GP0_IO, 0x00050000);
msleep(20);
cx_clear(GP0_IO, 0x00000005);
msleep(20);
cx_set(GP0_IO, 0x00050005);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1400:
/* GPIO-0 Dibcom7000p demodulator reset */
/* GPIO-2 xc3028L tuner reset */
/* GPIO-13 LED */
/* Put the parts into reset and back */
cx_set(GP0_IO, 0x00050000);
msleep(20);
cx_clear(GP0_IO, 0x00000005);
msleep(20);
cx_set(GP0_IO, 0x00050005);
break;
case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
/* GPIO-0 xc5000 tuner reset i2c bus 0 */
/* GPIO-1 s5h1409 demod reset i2c bus 0 */
/* GPIO-2 xc5000 tuner reset i2c bus 1 */
/* GPIO-3 s5h1409 demod reset i2c bus 0 */
/* Put the parts into reset and back */
cx_set(GP0_IO, 0x000f0000);
msleep(20);
cx_clear(GP0_IO, 0x0000000f);
msleep(20);
cx_set(GP0_IO, 0x000f000f);
break;
case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
/* GPIO-0 portb xc3028 reset */
/* GPIO-1 portb zl10353 reset */
/* GPIO-2 portc xc3028 reset */
/* GPIO-3 portc zl10353 reset */
/* Put the parts into reset and back */
cx_set(GP0_IO, 0x000f0000);
msleep(20);
cx_clear(GP0_IO, 0x0000000f);
msleep(20);
cx_set(GP0_IO, 0x000f000f);
break;
case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
/* GPIO-2 xc3028 tuner reset */
/* The following GPIO's are on the internal AVCore (cx25840) */
/* GPIO-? zl10353 demod reset */
/* Put the parts into reset and back */
cx_set(GP0_IO, 0x00040000);
msleep(20);
cx_clear(GP0_IO, 0x00000004);
msleep(20);
cx_set(GP0_IO, 0x00040004);
break;
case CX23885_BOARD_TBS_6920:
case CX23885_BOARD_TBS_6980:
case CX23885_BOARD_TBS_6981:
case CX23885_BOARD_PROF_8000:
cx_write(MC417_CTL, 0x00000036);
cx_write(MC417_OEN, 0x00001000);
cx_set(MC417_RWD, 0x00000002);
msleep(200);
cx_clear(MC417_RWD, 0x00000800);
msleep(200);
cx_set(MC417_RWD, 0x00000800);
msleep(200);
break;
case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
/* GPIO-0 INTA from CiMax1
GPIO-1 INTB from CiMax2
GPIO-2 reset chips
GPIO-3 to GPIO-10 data/addr for CA
GPIO-11 ~CS0 to CiMax1
GPIO-12 ~CS1 to CiMax2
GPIO-13 ADL0 load LSB addr
GPIO-14 ADL1 load MSB addr
GPIO-15 ~RDY from CiMax
GPIO-17 ~RD to CiMax
GPIO-18 ~WR to CiMax
*/
cx_set(GP0_IO, 0x00040000); /* GPIO as out */
/* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
cx_clear(GP0_IO, 0x00030004);
msleep(100);/* reset delay */
cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
/* GPIO-15 IN as ~ACK, rest as OUT */
cx_write(MC417_OEN, 0x00001000);
/* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
cx_write(MC417_RWD, 0x0000c300);
/* enable irq */
cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
break;
case CX23885_BOARD_HAUPPAUGE_HVR1270:
case CX23885_BOARD_HAUPPAUGE_HVR1275:
case CX23885_BOARD_HAUPPAUGE_HVR1255:
case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
case CX23885_BOARD_HAUPPAUGE_HVR1210:
/* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
/* GPIO-6 I2C Gate which can isolate the demod from the bus */
/* GPIO-9 Demod reset */
/* Put the parts into reset and back */
cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
cx23885_gpio_clear(dev, GPIO_9);
msleep(20);
cx23885_gpio_set(dev, GPIO_9);
break;
case CX23885_BOARD_MYGICA_X8506:
case CX23885_BOARD_MAGICPRO_PROHDTVE2:
case CX23885_BOARD_MYGICA_X8507:
/* GPIO-0 (0)Analog / (1)Digital TV */
/* GPIO-1 reset XC5000 */
/* GPIO-2 demod reset */
cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
msleep(100);
cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
msleep(100);
break;
case CX23885_BOARD_MYGICA_X8558PRO:
/* GPIO-0 reset first ATBM8830 */
/* GPIO-1 reset second ATBM8830 */
cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
msleep(100);
cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
msleep(100);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1850:
case CX23885_BOARD_HAUPPAUGE_HVR1290:
/* GPIO-0 656_CLK */
/* GPIO-1 656_D0 */
/* GPIO-2 Wake# */
/* GPIO-3-10 cx23417 data0-7 */
/* GPIO-11-14 cx23417 addr0-3 */
/* GPIO-15-18 cx23417 READY, CS, RD, WR */
/* GPIO-19 IR_RX */
/* GPIO-20 C_IR_TX */
/* GPIO-21 I2S DAT */
/* GPIO-22 I2S WCLK */
/* GPIO-23 I2S BCLK */
/* ALT GPIO: EXP GPIO LATCH */
/* CX23417 GPIO's */
/* GPIO-14 S5H1411/CX24228 Reset */
/* GPIO-13 EEPROM write protect */
mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
/* Put the demod into reset and protect the eeprom */
mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
msleep(100);
/* Bring the demod out of reset */
mc417_gpio_set(dev, GPIO_14);
msleep(100);
/* CX24228 GPIO */
/* Connected to IF / Mux */
break;
case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
break;
case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
/* GPIO-0 ~INT in
GPIO-1 TMS out
GPIO-2 ~reset chips out
GPIO-3 to GPIO-10 data/addr for CA in/out
GPIO-11 ~CS out
GPIO-12 ADDR out
GPIO-13 ~WR out
GPIO-14 ~RD out
GPIO-15 ~RDY in
GPIO-16 TCK out
GPIO-17 TDO in
GPIO-18 TDI out
*/
cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
/* GPIO-0 as INT, reset & TMS low */
cx_clear(GP0_IO, 0x00010006);
msleep(100);/* reset delay */
cx_set(GP0_IO, 0x00000004); /* reset high */
cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
/* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
cx_write(MC417_OEN, 0x00005000);
/* ~RD, ~WR high; ADDR low; ~CS high */
cx_write(MC417_RWD, 0x00000d00);
/* enable irq */
cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
break;
case CX23885_BOARD_HAUPPAUGE_HVR4400:
case CX23885_BOARD_HAUPPAUGE_STARBURST:
/* GPIO-8 tda10071 demod reset */
/* GPIO-9 si2165 demod reset (only HVR4400/HVR5500)*/
/* Put the parts into reset and back */
cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
msleep(100);
cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
msleep(100);
break;
case CX23885_BOARD_AVERMEDIA_HC81R:
cx_clear(MC417_CTL, 1);
/* GPIO-0,1,2 setup direction as output */
cx_set(GP0_IO, 0x00070000);
usleep_range(10000, 11000);
/* AF9013 demod reset */
cx_set(GP0_IO, 0x00010001);
usleep_range(10000, 11000);
cx_clear(GP0_IO, 0x00010001);
usleep_range(10000, 11000);
cx_set(GP0_IO, 0x00010001);
usleep_range(10000, 11000);
/* demod tune? */
cx_clear(GP0_IO, 0x00030003);
usleep_range(10000, 11000);
cx_set(GP0_IO, 0x00020002);
usleep_range(10000, 11000);
cx_set(GP0_IO, 0x00010001);
usleep_range(10000, 11000);
cx_clear(GP0_IO, 0x00020002);
/* XC3028L tuner reset */
cx_set(GP0_IO, 0x00040004);
cx_clear(GP0_IO, 0x00040004);
cx_set(GP0_IO, 0x00040004);
msleep(60);
break;
case CX23885_BOARD_DVBSKY_T9580:
case CX23885_BOARD_DVBSKY_S952:
case CX23885_BOARD_DVBSKY_T982:
/* enable GPIO3-18 pins */
cx_write(MC417_CTL, 0x00000037);
cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1);
cx23885_gpio_clear(dev, GPIO_2 | GPIO_11);
msleep(100);
cx23885_gpio_set(dev, GPIO_2 | GPIO_11);
break;
case CX23885_BOARD_DVBSKY_T980C:
case CX23885_BOARD_DVBSKY_S950C:
case CX23885_BOARD_TT_CT2_4500_CI:
/*
* GPIO-0 INTA from CiMax, input
* GPIO-1 reset CiMax, output, high active
* GPIO-2 reset demod, output, low active
* GPIO-3 to GPIO-10 data/addr for CAM
* GPIO-11 ~CS0 to CiMax1
* GPIO-12 ~CS1 to CiMax2
* GPIO-13 ADL0 load LSB addr
* GPIO-14 ADL1 load MSB addr
* GPIO-15 ~RDY from CiMax
* GPIO-17 ~RD to CiMax
* GPIO-18 ~WR to CiMax
*/
cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */
cx_clear(GP0_IO, 0x00010004); /* GPIO 0 as input */
msleep(100); /* reset delay */
cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */
cx_clear(GP0_IO, 0x00010002);
cx_write(MC417_CTL, 0x00000037); /* enable GPIO3-18 pins */
/* GPIO-15 IN as ~ACK, rest as OUT */
cx_write(MC417_OEN, 0x00001000);
/* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
cx_write(MC417_RWD, 0x0000c300);
/* enable irq */
cx_write(GPIO_ISM, 0x00000000); /* INTERRUPTS active low */
break;
case CX23885_BOARD_DVBSKY_S950:
cx23885_gpio_enable(dev, GPIO_2, 1);
cx23885_gpio_clear(dev, GPIO_2);
msleep(100);
cx23885_gpio_set(dev, GPIO_2);
break;
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_HAUPPAUGE_STARBURST2:
/*
* HVR5525 GPIO Details:
* GPIO-00 IR_WIDE
* GPIO-02 wake#
* GPIO-03 VAUX Pres.
* GPIO-07 PROG#
* GPIO-08 SAT_RESN
* GPIO-09 TER_RESN
* GPIO-10 B2_SENSE
* GPIO-11 B1_SENSE
* GPIO-15 IR_LED_STATUS
* GPIO-19 IR_NARROW
* GPIO-20 Blauster1
* ALTGPIO VAUX_SWITCH
* AUX_PLL_CLK : Blaster2
*/
/* Put the parts into reset and back */
cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
msleep(100);
cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
msleep(100);
break;
case CX23885_BOARD_VIEWCAST_260E:
case CX23885_BOARD_VIEWCAST_460E:
/* For documentation purposes, it's worth noting that this
* card does not have any GPIO's connected to subcomponents.
*/
break;
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885:
/*
* GPIO-08 TER1_RESN
* GPIO-09 TER2_RESN
*/
/* Put the parts into reset and back */
cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
msleep(100);
cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
msleep(100);
break;
}
}
int cx23885_ir_init(struct cx23885_dev *dev)
{
static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
{
.flags = BIT(V4L2_SUBDEV_IO_PIN_INPUT),
.pin = CX23885_PIN_IR_RX_GPIO19,
.function = CX23885_PAD_IR_RX,
.value = 0,
.strength = CX25840_PIN_DRIVE_MEDIUM,
}, {
.flags = BIT(V4L2_SUBDEV_IO_PIN_OUTPUT),
.pin = CX23885_PIN_IR_TX_GPIO20,
.function = CX23885_PAD_IR_TX,
.value = 0,
.strength = CX25840_PIN_DRIVE_MEDIUM,
}
};
const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
{
.flags = BIT(V4L2_SUBDEV_IO_PIN_INPUT),
.pin = CX23885_PIN_IR_RX_GPIO19,
.function = CX23885_PAD_IR_RX,
.value = 0,
.strength = CX25840_PIN_DRIVE_MEDIUM,
}
};
const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
struct v4l2_subdev_ir_parameters params;
int ret = 0;
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1500:
case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
case CX23885_BOARD_HAUPPAUGE_HVR1800:
case CX23885_BOARD_HAUPPAUGE_HVR1200:
case CX23885_BOARD_HAUPPAUGE_HVR1400:
case CX23885_BOARD_HAUPPAUGE_HVR1275:
case CX23885_BOARD_HAUPPAUGE_HVR1255:
case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
case CX23885_BOARD_HAUPPAUGE_HVR1210:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
/* FIXME: Implement me */
break;
case CX23885_BOARD_HAUPPAUGE_HVR1270:
ret = cx23888_ir_probe(dev);
if (ret)
break;
dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
ir_rx_pin_cfg_count, ir_rx_pin_cfg);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1850:
case CX23885_BOARD_HAUPPAUGE_HVR1290:
ret = cx23888_ir_probe(dev);
if (ret)
break;
dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
/*
* For these boards we need to invert the Tx output via the
* IR controller to have the LED off while idle
*/
v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms);
params.enable = false;
params.shutdown = false;
params.invert_level = true;
v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms);
params.shutdown = true;
v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms);
break;
case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
case CX23885_BOARD_TEVII_S470:
case CX23885_BOARD_MYGICA_X8507:
case CX23885_BOARD_TBS_6980:
case CX23885_BOARD_TBS_6981:
case CX23885_BOARD_DVBSKY_T9580:
case CX23885_BOARD_DVBSKY_T980C:
case CX23885_BOARD_DVBSKY_S950C:
case CX23885_BOARD_TT_CT2_4500_CI:
case CX23885_BOARD_DVBSKY_S950:
case CX23885_BOARD_DVBSKY_S952:
case CX23885_BOARD_DVBSKY_T982:
if (!enable_885_ir)
break;
dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
if (dev->sd_ir == NULL) {
ret = -ENODEV;
break;
}
v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
ir_rx_pin_cfg_count, ir_rx_pin_cfg);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1250:
if (!enable_885_ir)
break;
dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
if (dev->sd_ir == NULL) {
ret = -ENODEV;
break;
}
v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
break;
case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
request_module("ir-kbd-i2c");
break;
}
return ret;
}
void cx23885_ir_fini(struct cx23885_dev *dev)
{
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1270:
case CX23885_BOARD_HAUPPAUGE_HVR1850:
case CX23885_BOARD_HAUPPAUGE_HVR1290:
cx23885_irq_remove(dev, PCI_MSK_IR);
cx23888_ir_remove(dev);
dev->sd_ir = NULL;
break;
case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
case CX23885_BOARD_TEVII_S470:
case CX23885_BOARD_HAUPPAUGE_HVR1250:
case CX23885_BOARD_MYGICA_X8507:
case CX23885_BOARD_TBS_6980:
case CX23885_BOARD_TBS_6981:
case CX23885_BOARD_DVBSKY_T9580:
case CX23885_BOARD_DVBSKY_T980C:
case CX23885_BOARD_DVBSKY_S950C:
case CX23885_BOARD_TT_CT2_4500_CI:
case CX23885_BOARD_DVBSKY_S950:
case CX23885_BOARD_DVBSKY_S952:
case CX23885_BOARD_DVBSKY_T982:
cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
/* sd_ir is a duplicate pointer to the AV Core, just clear it */
dev->sd_ir = NULL;
break;
}
}
static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
{
int data;
int tdo = 0;
struct cx23885_dev *dev = (struct cx23885_dev *)device;
/*TMS*/
data = ((cx_read(GP0_IO)) & (~0x00000002));
data |= (tms ? 0x00020002 : 0x00020000);
cx_write(GP0_IO, data);
/*TDI*/
data = ((cx_read(MC417_RWD)) & (~0x0000a000));
data |= (tdi ? 0x00008000 : 0);
cx_write(MC417_RWD, data);
if (read_tdo)
tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
cx_write(MC417_RWD, data | 0x00002000);
udelay(1);
/*TCK*/
cx_write(MC417_RWD, data);
return tdo;
}
void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
{
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1270:
case CX23885_BOARD_HAUPPAUGE_HVR1850:
case CX23885_BOARD_HAUPPAUGE_HVR1290:
if (dev->sd_ir)
cx23885_irq_add_enable(dev, PCI_MSK_IR);
break;
case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
case CX23885_BOARD_TEVII_S470:
case CX23885_BOARD_HAUPPAUGE_HVR1250:
case CX23885_BOARD_MYGICA_X8507:
case CX23885_BOARD_TBS_6980:
case CX23885_BOARD_TBS_6981:
case CX23885_BOARD_DVBSKY_T9580:
case CX23885_BOARD_DVBSKY_T980C:
case CX23885_BOARD_DVBSKY_S950C:
case CX23885_BOARD_TT_CT2_4500_CI:
case CX23885_BOARD_DVBSKY_S950:
case CX23885_BOARD_DVBSKY_S952:
case CX23885_BOARD_DVBSKY_T982:
if (dev->sd_ir)
cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
break;
}
}
void cx23885_card_setup(struct cx23885_dev *dev)
{
struct cx23885_tsport *ts1 = &dev->ts1;
struct cx23885_tsport *ts2 = &dev->ts2;
static u8 eeprom[256];
if (dev->i2c_bus[0].i2c_rc == 0) {
dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
tveeprom_read(&dev->i2c_bus[0].i2c_client,
eeprom, sizeof(eeprom));
}
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1250:
if (dev->i2c_bus[0].i2c_rc == 0) {
if (eeprom[0x80] != 0x84)
hauppauge_eeprom(dev, eeprom+0xc0);
else
hauppauge_eeprom(dev, eeprom+0x80);
}
break;
case CX23885_BOARD_HAUPPAUGE_HVR1500:
case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
case CX23885_BOARD_HAUPPAUGE_HVR1400:
if (dev->i2c_bus[0].i2c_rc == 0)
hauppauge_eeprom(dev, eeprom+0x80);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1800:
case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
case CX23885_BOARD_HAUPPAUGE_HVR1200:
case CX23885_BOARD_HAUPPAUGE_HVR1700:
case CX23885_BOARD_HAUPPAUGE_HVR1270:
case CX23885_BOARD_HAUPPAUGE_HVR1275:
case CX23885_BOARD_HAUPPAUGE_HVR1255:
case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
case CX23885_BOARD_HAUPPAUGE_HVR1210:
case CX23885_BOARD_HAUPPAUGE_HVR1850:
case CX23885_BOARD_HAUPPAUGE_HVR1290:
case CX23885_BOARD_HAUPPAUGE_HVR4400:
case CX23885_BOARD_HAUPPAUGE_STARBURST:
case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_STARBURST2:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885:
if (dev->i2c_bus[0].i2c_rc == 0)
hauppauge_eeprom(dev, eeprom+0xc0);
break;
case CX23885_BOARD_VIEWCAST_260E:
case CX23885_BOARD_VIEWCAST_460E:
dev->i2c_bus[1].i2c_client.addr = 0xa0 >> 1;
tveeprom_read(&dev->i2c_bus[1].i2c_client,
eeprom, sizeof(eeprom));
if (dev->i2c_bus[0].i2c_rc == 0)
viewcast_eeprom(dev, eeprom);
break;
}
switch (dev->board) {
case CX23885_BOARD_AVERMEDIA_HC81R:
/* Defaults for VID B */
ts1->gen_ctrl_val = 0x4; /* Parallel */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
/* Defaults for VID C */
/* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
ts2->gen_ctrl_val = 0x10e;
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
fallthrough;
case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_HAUPPAUGE_HVR1850:
case CX23885_BOARD_HAUPPAUGE_HVR1800:
/* Defaults for VID B - Analog encoder */
/* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
ts1->gen_ctrl_val = 0x10e;
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
/* APB_TSVALERR_POL (active low)*/
ts1->vld_misc_val = 0x2000;
ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
cx_write(0x130184, 0xc);
/* Defaults for VID C */
ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_TBS_6920:
ts1->gen_ctrl_val = 0x4; /* Parallel */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_TEVII_S470:
case CX23885_BOARD_TEVII_S471:
case CX23885_BOARD_DVBWORLD_2005:
case CX23885_BOARD_PROF_8000:
case CX23885_BOARD_DVBSKY_T980C:
case CX23885_BOARD_DVBSKY_S950C:
case CX23885_BOARD_TT_CT2_4500_CI:
case CX23885_BOARD_DVBSKY_S950:
ts1->gen_ctrl_val = 0x5; /* Parallel */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_TBS_6980:
case CX23885_BOARD_TBS_6981:
ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
tbs_card_init(dev);
break;
case CX23885_BOARD_MYGICA_X8506:
case CX23885_BOARD_MAGICPRO_PROHDTVE2:
case CX23885_BOARD_MYGICA_X8507:
ts1->gen_ctrl_val = 0x5; /* Parallel */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_MYGICA_X8558PRO:
ts1->gen_ctrl_val = 0x5; /* Parallel */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_HAUPPAUGE_HVR4400:
ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_HAUPPAUGE_STARBURST:
ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_DVBSKY_T9580:
case CX23885_BOARD_DVBSKY_T982:
ts1->gen_ctrl_val = 0x5; /* Parallel */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
ts2->gen_ctrl_val = 0x8; /* Serial bus */
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_DVBSKY_S952:
ts1->gen_ctrl_val = 0x5; /* Parallel */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
ts2->gen_ctrl_val = 0xe; /* Serial bus */
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_HAUPPAUGE_STARBURST2:
ts1->gen_ctrl_val = 0x5; /* Parallel */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885:
ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
break;
case CX23885_BOARD_HAUPPAUGE_HVR1250:
case CX23885_BOARD_HAUPPAUGE_HVR1500:
case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
case CX23885_BOARD_HAUPPAUGE_HVR1200:
case CX23885_BOARD_HAUPPAUGE_HVR1700:
case CX23885_BOARD_HAUPPAUGE_HVR1400:
case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
case CX23885_BOARD_HAUPPAUGE_HVR1270:
case CX23885_BOARD_HAUPPAUGE_HVR1275:
case CX23885_BOARD_HAUPPAUGE_HVR1255:
case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
case CX23885_BOARD_HAUPPAUGE_HVR1210:
case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
case CX23885_BOARD_HAUPPAUGE_HVR1290:
case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
default:
ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
}
/* Certain boards support analog, or require the avcore to be
* loaded, ensure this happens.
*/
switch (dev->board) {
case CX23885_BOARD_TEVII_S470:
/* Currently only enabled for the integrated IR controller */
if (!enable_885_ir)
break;
fallthrough;
case CX23885_BOARD_HAUPPAUGE_HVR1250:
case CX23885_BOARD_HAUPPAUGE_HVR1800:
case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
case CX23885_BOARD_HAUPPAUGE_HVR1700:
case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
case CX23885_BOARD_HAUPPAUGE_HVR1255:
case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
case CX23885_BOARD_HAUPPAUGE_HVR1270:
case CX23885_BOARD_HAUPPAUGE_HVR1850:
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_MYGICA_X8506:
case CX23885_BOARD_MAGICPRO_PROHDTVE2:
case CX23885_BOARD_HAUPPAUGE_HVR1290:
case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
case CX23885_BOARD_HAUPPAUGE_HVR1500:
case CX23885_BOARD_MPX885:
case CX23885_BOARD_MYGICA_X8507:
case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
case CX23885_BOARD_AVERMEDIA_HC81R:
case CX23885_BOARD_TBS_6980:
case CX23885_BOARD_TBS_6981:
case CX23885_BOARD_DVBSKY_T9580:
case CX23885_BOARD_DVBSKY_T980C:
case CX23885_BOARD_DVBSKY_S950C:
case CX23885_BOARD_TT_CT2_4500_CI:
case CX23885_BOARD_DVBSKY_S950:
case CX23885_BOARD_DVBSKY_S952:
case CX23885_BOARD_DVBSKY_T982:
case CX23885_BOARD_VIEWCAST_260E:
case CX23885_BOARD_VIEWCAST_460E:
case CX23885_BOARD_AVERMEDIA_CE310B:
dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
&dev->i2c_bus[2].i2c_adap,
"cx25840", 0x88 >> 1, NULL);
if (dev->sd_cx25840) {
/* set host data for clk_freq configuration */
v4l2_set_subdev_hostdata(dev->sd_cx25840,
&dev->clk_freq);
dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
}
break;
}
switch (dev->board) {
case CX23885_BOARD_VIEWCAST_260E:
v4l2_i2c_new_subdev(&dev->v4l2_dev,
&dev->i2c_bus[0].i2c_adap,
"cs3308", 0x82 >> 1, NULL);
break;
case CX23885_BOARD_VIEWCAST_460E:
/* This cs3308 controls the audio from the breakout cable */
v4l2_i2c_new_subdev(&dev->v4l2_dev,
&dev->i2c_bus[0].i2c_adap,
"cs3308", 0x80 >> 1, NULL);
/* This cs3308 controls the audio from the onboard header */
v4l2_i2c_new_subdev(&dev->v4l2_dev,
&dev->i2c_bus[0].i2c_adap,
"cs3308", 0x82 >> 1, NULL);
break;
}
/* AUX-PLL 27MHz CLK */
switch (dev->board) {
case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
netup_initialize(dev);
break;
case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
int ret;
const struct firmware *fw;
const char *filename = "dvb-netup-altera-01.fw";
char *action = "configure";
static struct netup_card_info cinfo;
struct altera_config netup_config = {
.dev = dev,
.action = action,
.jtag_io = netup_jtag_io,
};
netup_initialize(dev);
netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
if (netup_card_rev)
cinfo.rev = netup_card_rev;
switch (cinfo.rev) {
case 0x4:
filename = "dvb-netup-altera-04.fw";
break;
default:
filename = "dvb-netup-altera-01.fw";
break;
}
pr_info("NetUP card rev=0x%x fw_filename=%s\n",
cinfo.rev, filename);
ret = request_firmware(&fw, filename, &dev->pci->dev);
if (ret != 0)
pr_err("did not find the firmware file '%s'. You can use <kernel_dir>/scripts/get_dvb_firmware to get the firmware.",
filename);
else
altera_init(&netup_config, fw);
release_firmware(fw);
break;
}
}
}
| linux-master | drivers/media/pci/cx23885/cx23885-cards.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Conexant CX23885 PCIe bridge
*
* Copyright (c) 2006 Steven Toth <[email protected]>
*/
#include "cx23885.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kmod.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <asm/div64.h>
#include <linux/firmware.h>
#include "cimax2.h"
#include "altera-ci.h"
#include "cx23888-ir.h"
#include "cx23885-ir.h"
#include "cx23885-av.h"
#include "cx23885-input.h"
MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
MODULE_AUTHOR("Steven Toth <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_VERSION(CX23885_VERSION);
/*
* Some platforms have been found to require periodic resetting of the DMA
* engine. Ryzen and XEON platforms are known to be affected. The symptom
* encountered is "mpeg risc op code error". Only Ryzen platforms employ
* this workaround if the option equals 1. The workaround can be explicitly
* disabled for all platforms by setting to 0, the workaround can be forced
* on for any platform by setting to 2.
*/
static unsigned int dma_reset_workaround = 1;
module_param(dma_reset_workaround, int, 0644);
MODULE_PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver detect (default), 2-force enable");
static unsigned int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable debug messages");
static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
module_param_array(card, int, NULL, 0444);
MODULE_PARM_DESC(card, "card type");
#define dprintk(level, fmt, arg...)\
do { if (debug >= level)\
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##arg); \
} while (0)
static unsigned int cx23885_devcount;
#define NO_SYNC_LINE (-1U)
/* FIXME, these allocations will change when
* analog arrives. The be reviewed.
* CX23887 Assumptions
* 1 line = 16 bytes of CDT
* cmds size = 80
* cdt size = 16 * linesize
* iqsize = 64
* maxlines = 6
*
* Address Space:
* 0x00000000 0x00008fff FIFO clusters
* 0x00010000 0x000104af Channel Management Data Structures
* 0x000104b0 0x000104ff Free
* 0x00010500 0x000108bf 15 channels * iqsize
* 0x000108c0 0x000108ff Free
* 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
* 15 channels * (iqsize + (maxlines * linesize))
* 0x00010ea0 0x00010xxx Free
*/
static struct sram_channel cx23885_sram_channels[] = {
[SRAM_CH01] = {
.name = "VID A",
.cmds_start = 0x10000,
.ctrl_start = 0x10380,
.cdt = 0x104c0,
.fifo_start = 0x40,
.fifo_size = 0x2800,
.ptr1_reg = DMA1_PTR1,
.ptr2_reg = DMA1_PTR2,
.cnt1_reg = DMA1_CNT1,
.cnt2_reg = DMA1_CNT2,
},
[SRAM_CH02] = {
.name = "ch2",
.cmds_start = 0x0,
.ctrl_start = 0x0,
.cdt = 0x0,
.fifo_start = 0x0,
.fifo_size = 0x0,
.ptr1_reg = DMA2_PTR1,
.ptr2_reg = DMA2_PTR2,
.cnt1_reg = DMA2_CNT1,
.cnt2_reg = DMA2_CNT2,
},
[SRAM_CH03] = {
.name = "TS1 B",
.cmds_start = 0x100A0,
.ctrl_start = 0x10400,
.cdt = 0x10580,
.fifo_start = 0x5000,
.fifo_size = 0x1000,
.ptr1_reg = DMA3_PTR1,
.ptr2_reg = DMA3_PTR2,
.cnt1_reg = DMA3_CNT1,
.cnt2_reg = DMA3_CNT2,
},
[SRAM_CH04] = {
.name = "ch4",
.cmds_start = 0x0,
.ctrl_start = 0x0,
.cdt = 0x0,
.fifo_start = 0x0,
.fifo_size = 0x0,
.ptr1_reg = DMA4_PTR1,
.ptr2_reg = DMA4_PTR2,
.cnt1_reg = DMA4_CNT1,
.cnt2_reg = DMA4_CNT2,
},
[SRAM_CH05] = {
.name = "ch5",
.cmds_start = 0x0,
.ctrl_start = 0x0,
.cdt = 0x0,
.fifo_start = 0x0,
.fifo_size = 0x0,
.ptr1_reg = DMA5_PTR1,
.ptr2_reg = DMA5_PTR2,
.cnt1_reg = DMA5_CNT1,
.cnt2_reg = DMA5_CNT2,
},
[SRAM_CH06] = {
.name = "TS2 C",
.cmds_start = 0x10140,
.ctrl_start = 0x10440,
.cdt = 0x105e0,
.fifo_start = 0x6000,
.fifo_size = 0x1000,
.ptr1_reg = DMA5_PTR1,
.ptr2_reg = DMA5_PTR2,
.cnt1_reg = DMA5_CNT1,
.cnt2_reg = DMA5_CNT2,
},
[SRAM_CH07] = {
.name = "TV Audio",
.cmds_start = 0x10190,
.ctrl_start = 0x10480,
.cdt = 0x10a00,
.fifo_start = 0x7000,
.fifo_size = 0x1000,
.ptr1_reg = DMA6_PTR1,
.ptr2_reg = DMA6_PTR2,
.cnt1_reg = DMA6_CNT1,
.cnt2_reg = DMA6_CNT2,
},
[SRAM_CH08] = {
.name = "ch8",
.cmds_start = 0x0,
.ctrl_start = 0x0,
.cdt = 0x0,
.fifo_start = 0x0,
.fifo_size = 0x0,
.ptr1_reg = DMA7_PTR1,
.ptr2_reg = DMA7_PTR2,
.cnt1_reg = DMA7_CNT1,
.cnt2_reg = DMA7_CNT2,
},
[SRAM_CH09] = {
.name = "ch9",
.cmds_start = 0x0,
.ctrl_start = 0x0,
.cdt = 0x0,
.fifo_start = 0x0,
.fifo_size = 0x0,
.ptr1_reg = DMA8_PTR1,
.ptr2_reg = DMA8_PTR2,
.cnt1_reg = DMA8_CNT1,
.cnt2_reg = DMA8_CNT2,
},
};
static struct sram_channel cx23887_sram_channels[] = {
[SRAM_CH01] = {
.name = "VID A",
.cmds_start = 0x10000,
.ctrl_start = 0x105b0,
.cdt = 0x107b0,
.fifo_start = 0x40,
.fifo_size = 0x2800,
.ptr1_reg = DMA1_PTR1,
.ptr2_reg = DMA1_PTR2,
.cnt1_reg = DMA1_CNT1,
.cnt2_reg = DMA1_CNT2,
},
[SRAM_CH02] = {
.name = "VID A (VBI)",
.cmds_start = 0x10050,
.ctrl_start = 0x105F0,
.cdt = 0x10810,
.fifo_start = 0x3000,
.fifo_size = 0x1000,
.ptr1_reg = DMA2_PTR1,
.ptr2_reg = DMA2_PTR2,
.cnt1_reg = DMA2_CNT1,
.cnt2_reg = DMA2_CNT2,
},
[SRAM_CH03] = {
.name = "TS1 B",
.cmds_start = 0x100A0,
.ctrl_start = 0x10630,
.cdt = 0x10870,
.fifo_start = 0x5000,
.fifo_size = 0x1000,
.ptr1_reg = DMA3_PTR1,
.ptr2_reg = DMA3_PTR2,
.cnt1_reg = DMA3_CNT1,
.cnt2_reg = DMA3_CNT2,
},
[SRAM_CH04] = {
.name = "ch4",
.cmds_start = 0x0,
.ctrl_start = 0x0,
.cdt = 0x0,
.fifo_start = 0x0,
.fifo_size = 0x0,
.ptr1_reg = DMA4_PTR1,
.ptr2_reg = DMA4_PTR2,
.cnt1_reg = DMA4_CNT1,
.cnt2_reg = DMA4_CNT2,
},
[SRAM_CH05] = {
.name = "ch5",
.cmds_start = 0x0,
.ctrl_start = 0x0,
.cdt = 0x0,
.fifo_start = 0x0,
.fifo_size = 0x0,
.ptr1_reg = DMA5_PTR1,
.ptr2_reg = DMA5_PTR2,
.cnt1_reg = DMA5_CNT1,
.cnt2_reg = DMA5_CNT2,
},
[SRAM_CH06] = {
.name = "TS2 C",
.cmds_start = 0x10140,
.ctrl_start = 0x10670,
.cdt = 0x108d0,
.fifo_start = 0x6000,
.fifo_size = 0x1000,
.ptr1_reg = DMA5_PTR1,
.ptr2_reg = DMA5_PTR2,
.cnt1_reg = DMA5_CNT1,
.cnt2_reg = DMA5_CNT2,
},
[SRAM_CH07] = {
.name = "TV Audio",
.cmds_start = 0x10190,
.ctrl_start = 0x106B0,
.cdt = 0x10930,
.fifo_start = 0x7000,
.fifo_size = 0x1000,
.ptr1_reg = DMA6_PTR1,
.ptr2_reg = DMA6_PTR2,
.cnt1_reg = DMA6_CNT1,
.cnt2_reg = DMA6_CNT2,
},
[SRAM_CH08] = {
.name = "ch8",
.cmds_start = 0x0,
.ctrl_start = 0x0,
.cdt = 0x0,
.fifo_start = 0x0,
.fifo_size = 0x0,
.ptr1_reg = DMA7_PTR1,
.ptr2_reg = DMA7_PTR2,
.cnt1_reg = DMA7_CNT1,
.cnt2_reg = DMA7_CNT2,
},
[SRAM_CH09] = {
.name = "ch9",
.cmds_start = 0x0,
.ctrl_start = 0x0,
.cdt = 0x0,
.fifo_start = 0x0,
.fifo_size = 0x0,
.ptr1_reg = DMA8_PTR1,
.ptr2_reg = DMA8_PTR2,
.cnt1_reg = DMA8_CNT1,
.cnt2_reg = DMA8_CNT2,
},
};
static void cx23885_irq_add(struct cx23885_dev *dev, u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
dev->pci_irqmask |= mask;
spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
}
void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
dev->pci_irqmask |= mask;
cx_set(PCI_INT_MSK, mask);
spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
}
void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask)
{
u32 v;
unsigned long flags;
spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
v = mask & dev->pci_irqmask;
if (v)
cx_set(PCI_INT_MSK, v);
spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
}
static inline void cx23885_irq_enable_all(struct cx23885_dev *dev)
{
cx23885_irq_enable(dev, 0xffffffff);
}
void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
cx_clear(PCI_INT_MSK, mask);
spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
}
static inline void cx23885_irq_disable_all(struct cx23885_dev *dev)
{
cx23885_irq_disable(dev, 0xffffffff);
}
void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
dev->pci_irqmask &= ~mask;
cx_clear(PCI_INT_MSK, mask);
spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
}
static u32 cx23885_irq_get_mask(struct cx23885_dev *dev)
{
u32 v;
unsigned long flags;
spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
v = cx_read(PCI_INT_MSK);
spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
return v;
}
static int cx23885_risc_decode(u32 risc)
{
static char *instr[16] = {
[RISC_SYNC >> 28] = "sync",
[RISC_WRITE >> 28] = "write",
[RISC_WRITEC >> 28] = "writec",
[RISC_READ >> 28] = "read",
[RISC_READC >> 28] = "readc",
[RISC_JUMP >> 28] = "jump",
[RISC_SKIP >> 28] = "skip",
[RISC_WRITERM >> 28] = "writerm",
[RISC_WRITECM >> 28] = "writecm",
[RISC_WRITECR >> 28] = "writecr",
};
static int incr[16] = {
[RISC_WRITE >> 28] = 3,
[RISC_JUMP >> 28] = 3,
[RISC_SKIP >> 28] = 1,
[RISC_SYNC >> 28] = 1,
[RISC_WRITERM >> 28] = 3,
[RISC_WRITECM >> 28] = 3,
[RISC_WRITECR >> 28] = 4,
};
static char *bits[] = {
"12", "13", "14", "resync",
"cnt0", "cnt1", "18", "19",
"20", "21", "22", "23",
"irq1", "irq2", "eol", "sol",
};
int i;
printk(KERN_DEBUG "0x%08x [ %s", risc,
instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
if (risc & (1 << (i + 12)))
pr_cont(" %s", bits[i]);
pr_cont(" count=%d ]\n", risc & 0xfff);
return incr[risc >> 28] ? incr[risc >> 28] : 1;
}
static void cx23885_wakeup(struct cx23885_tsport *port,
struct cx23885_dmaqueue *q, u32 count)
{
struct cx23885_buffer *buf;
int count_delta;
int max_buf_done = 5; /* service maximum five buffers */
do {
if (list_empty(&q->active))
return;
buf = list_entry(q->active.next,
struct cx23885_buffer, queue);
buf->vb.vb2_buf.timestamp = ktime_get_ns();
buf->vb.sequence = q->count++;
if (count != (q->count % 65536)) {
dprintk(1, "[%p/%d] wakeup reg=%d buf=%d\n", buf,
buf->vb.vb2_buf.index, count, q->count);
} else {
dprintk(7, "[%p/%d] wakeup reg=%d buf=%d\n", buf,
buf->vb.vb2_buf.index, count, q->count);
}
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
max_buf_done--;
/* count register is 16 bits so apply modulo appropriately */
count_delta = ((int)count - (int)(q->count % 65536));
} while ((count_delta > 0) && (max_buf_done > 0));
}
int cx23885_sram_channel_setup(struct cx23885_dev *dev,
struct sram_channel *ch,
unsigned int bpl, u32 risc)
{
unsigned int i, lines;
u32 cdt;
if (ch->cmds_start == 0) {
dprintk(1, "%s() Erasing channel [%s]\n", __func__,
ch->name);
cx_write(ch->ptr1_reg, 0);
cx_write(ch->ptr2_reg, 0);
cx_write(ch->cnt2_reg, 0);
cx_write(ch->cnt1_reg, 0);
return 0;
} else {
dprintk(1, "%s() Configuring channel [%s]\n", __func__,
ch->name);
}
bpl = (bpl + 7) & ~7; /* alignment */
cdt = ch->cdt;
lines = ch->fifo_size / bpl;
if (lines > 6)
lines = 6;
BUG_ON(lines < 2);
cx_write(8 + 0, RISC_JUMP | RISC_CNT_RESET);
cx_write(8 + 4, 12);
cx_write(8 + 8, 0);
/* write CDT */
for (i = 0; i < lines; i++) {
dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
ch->fifo_start + bpl*i);
cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
cx_write(cdt + 16*i + 4, 0);
cx_write(cdt + 16*i + 8, 0);
cx_write(cdt + 16*i + 12, 0);
}
/* write CMDS */
if (ch->jumponly)
cx_write(ch->cmds_start + 0, 8);
else
cx_write(ch->cmds_start + 0, risc);
cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
cx_write(ch->cmds_start + 8, cdt);
cx_write(ch->cmds_start + 12, (lines*16) >> 3);
cx_write(ch->cmds_start + 16, ch->ctrl_start);
if (ch->jumponly)
cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
else
cx_write(ch->cmds_start + 20, 64 >> 2);
for (i = 24; i < 80; i += 4)
cx_write(ch->cmds_start + i, 0);
/* fill registers */
cx_write(ch->ptr1_reg, ch->fifo_start);
cx_write(ch->ptr2_reg, cdt);
cx_write(ch->cnt2_reg, (lines*16) >> 3);
cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
dprintk(2, "[bridge %d] sram setup %s: bpl=%d lines=%d\n",
dev->bridge,
ch->name,
bpl,
lines);
return 0;
}
void cx23885_sram_channel_dump(struct cx23885_dev *dev,
struct sram_channel *ch)
{
static char *name[] = {
"init risc lo",
"init risc hi",
"cdt base",
"cdt size",
"iq base",
"iq size",
"risc pc lo",
"risc pc hi",
"iq wr ptr",
"iq rd ptr",
"cdt current",
"pci target lo",
"pci target hi",
"line / byte",
};
u32 risc;
unsigned int i, j, n;
pr_warn("%s: %s - dma channel status dump\n",
dev->name, ch->name);
for (i = 0; i < ARRAY_SIZE(name); i++)
pr_warn("%s: cmds: %-15s: 0x%08x\n",
dev->name, name[i],
cx_read(ch->cmds_start + 4*i));
for (i = 0; i < 4; i++) {
risc = cx_read(ch->cmds_start + 4 * (i + 14));
pr_warn("%s: risc%d:", dev->name, i);
cx23885_risc_decode(risc);
}
for (i = 0; i < (64 >> 2); i += n) {
risc = cx_read(ch->ctrl_start + 4 * i);
/* No consideration for bits 63-32 */
pr_warn("%s: (0x%08x) iq %x:", dev->name,
ch->ctrl_start + 4 * i, i);
n = cx23885_risc_decode(risc);
for (j = 1; j < n; j++) {
risc = cx_read(ch->ctrl_start + 4 * (i + j));
pr_warn("%s: iq %x: 0x%08x [ arg #%d ]\n",
dev->name, i+j, risc, j);
}
}
pr_warn("%s: fifo: 0x%08x -> 0x%x\n",
dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
pr_warn("%s: ctrl: 0x%08x -> 0x%x\n",
dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
pr_warn("%s: ptr1_reg: 0x%08x\n",
dev->name, cx_read(ch->ptr1_reg));
pr_warn("%s: ptr2_reg: 0x%08x\n",
dev->name, cx_read(ch->ptr2_reg));
pr_warn("%s: cnt1_reg: 0x%08x\n",
dev->name, cx_read(ch->cnt1_reg));
pr_warn("%s: cnt2_reg: 0x%08x\n",
dev->name, cx_read(ch->cnt2_reg));
}
static void cx23885_risc_disasm(struct cx23885_tsport *port,
struct cx23885_riscmem *risc)
{
struct cx23885_dev *dev = port->dev;
unsigned int i, j, n;
pr_info("%s: risc disasm: %p [dma=0x%08lx]\n",
dev->name, risc->cpu, (unsigned long)risc->dma);
for (i = 0; i < (risc->size >> 2); i += n) {
pr_info("%s: %04d:", dev->name, i);
n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
for (j = 1; j < n; j++)
pr_info("%s: %04d: 0x%08x [ arg #%d ]\n",
dev->name, i + j, risc->cpu[i + j], j);
if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
break;
}
}
static void cx23885_clear_bridge_error(struct cx23885_dev *dev)
{
uint32_t reg1_val, reg2_val;
if (!dev->need_dma_reset)
return;
reg1_val = cx_read(TC_REQ); /* read-only */
reg2_val = cx_read(TC_REQ_SET);
if (reg1_val && reg2_val) {
cx_write(TC_REQ, reg1_val);
cx_write(TC_REQ_SET, reg2_val);
cx_read(VID_B_DMA);
cx_read(VBI_B_DMA);
cx_read(VID_C_DMA);
cx_read(VBI_C_DMA);
dev_info(&dev->pci->dev,
"dma in progress detected 0x%08x 0x%08x, clearing\n",
reg1_val, reg2_val);
}
}
static void cx23885_shutdown(struct cx23885_dev *dev)
{
/* disable RISC controller */
cx_write(DEV_CNTRL2, 0);
/* Disable all IR activity */
cx_write(IR_CNTRL_REG, 0);
/* Disable Video A/B activity */
cx_write(VID_A_DMA_CTL, 0);
cx_write(VID_B_DMA_CTL, 0);
cx_write(VID_C_DMA_CTL, 0);
/* Disable Audio activity */
cx_write(AUD_INT_DMA_CTL, 0);
cx_write(AUD_EXT_DMA_CTL, 0);
/* Disable Serial port */
cx_write(UART_CTL, 0);
/* Disable Interrupts */
cx23885_irq_disable_all(dev);
cx_write(VID_A_INT_MSK, 0);
cx_write(VID_B_INT_MSK, 0);
cx_write(VID_C_INT_MSK, 0);
cx_write(AUDIO_INT_INT_MSK, 0);
cx_write(AUDIO_EXT_INT_MSK, 0);
}
static void cx23885_reset(struct cx23885_dev *dev)
{
dprintk(1, "%s()\n", __func__);
cx23885_shutdown(dev);
cx_write(PCI_INT_STAT, 0xffffffff);
cx_write(VID_A_INT_STAT, 0xffffffff);
cx_write(VID_B_INT_STAT, 0xffffffff);
cx_write(VID_C_INT_STAT, 0xffffffff);
cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
cx_write(PAD_CTRL, 0x00500300);
/* clear dma in progress */
cx23885_clear_bridge_error(dev);
msleep(100);
cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
720*4, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
188*4, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
188*4, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
cx23885_gpio_setup(dev);
cx23885_irq_get_mask(dev);
/* clear dma in progress */
cx23885_clear_bridge_error(dev);
}
static int cx23885_pci_quirks(struct cx23885_dev *dev)
{
dprintk(1, "%s()\n", __func__);
/* The cx23885 bridge has a weird bug which causes NMI to be asserted
* when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
* occur on the cx23887 bridge.
*/
if (dev->bridge == CX23885_BRIDGE_885)
cx_clear(RDR_TLCTL0, 1 << 4);
/* clear dma in progress */
cx23885_clear_bridge_error(dev);
return 0;
}
static int get_resources(struct cx23885_dev *dev)
{
if (request_mem_region(pci_resource_start(dev->pci, 0),
pci_resource_len(dev->pci, 0),
dev->name))
return 0;
pr_err("%s: can't get MMIO memory @ 0x%llx\n",
dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
return -EBUSY;
}
static int cx23885_init_tsport(struct cx23885_dev *dev,
struct cx23885_tsport *port, int portno)
{
dprintk(1, "%s(portno=%d)\n", __func__, portno);
/* Transport bus init dma queue - Common settings */
port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
port->vld_misc_val = 0x0;
port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4);
spin_lock_init(&port->slock);
port->dev = dev;
port->nr = portno;
INIT_LIST_HEAD(&port->mpegq.active);
mutex_init(&port->frontends.lock);
INIT_LIST_HEAD(&port->frontends.felist);
port->frontends.active_fe_id = 0;
/* This should be hardcoded allow a single frontend
* attachment to this tsport, keeping the -dvb.c
* code clean and safe.
*/
if (!port->num_frontends)
port->num_frontends = 1;
switch (portno) {
case 1:
port->reg_gpcnt = VID_B_GPCNT;
port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
port->reg_dma_ctl = VID_B_DMA_CTL;
port->reg_lngth = VID_B_LNGTH;
port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
port->reg_gen_ctrl = VID_B_GEN_CTL;
port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
port->reg_sop_status = VID_B_SOP_STATUS;
port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
port->reg_vld_misc = VID_B_VLD_MISC;
port->reg_ts_clk_en = VID_B_TS_CLK_EN;
port->reg_src_sel = VID_B_SRC_SEL;
port->reg_ts_int_msk = VID_B_INT_MSK;
port->reg_ts_int_stat = VID_B_INT_STAT;
port->sram_chno = SRAM_CH03; /* VID_B */
port->pci_irqmask = 0x02; /* VID_B bit1 */
break;
case 2:
port->reg_gpcnt = VID_C_GPCNT;
port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
port->reg_dma_ctl = VID_C_DMA_CTL;
port->reg_lngth = VID_C_LNGTH;
port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
port->reg_gen_ctrl = VID_C_GEN_CTL;
port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
port->reg_sop_status = VID_C_SOP_STATUS;
port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
port->reg_vld_misc = VID_C_VLD_MISC;
port->reg_ts_clk_en = VID_C_TS_CLK_EN;
port->reg_src_sel = 0;
port->reg_ts_int_msk = VID_C_INT_MSK;
port->reg_ts_int_stat = VID_C_INT_STAT;
port->sram_chno = SRAM_CH06; /* VID_C */
port->pci_irqmask = 0x04; /* VID_C bit2 */
break;
default:
BUG();
}
return 0;
}
static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
{
switch (cx_read(RDR_CFG2) & 0xff) {
case 0x00:
/* cx23885 */
dev->hwrevision = 0xa0;
break;
case 0x01:
/* CX23885-12Z */
dev->hwrevision = 0xa1;
break;
case 0x02:
/* CX23885-13Z/14Z */
dev->hwrevision = 0xb0;
break;
case 0x03:
if (dev->pci->device == 0x8880) {
/* CX23888-21Z/22Z */
dev->hwrevision = 0xc0;
} else {
/* CX23885-14Z */
dev->hwrevision = 0xa4;
}
break;
case 0x04:
if (dev->pci->device == 0x8880) {
/* CX23888-31Z */
dev->hwrevision = 0xd0;
} else {
/* CX23885-15Z, CX23888-31Z */
dev->hwrevision = 0xa5;
}
break;
case 0x0e:
/* CX23887-15Z */
dev->hwrevision = 0xc0;
break;
case 0x0f:
/* CX23887-14Z */
dev->hwrevision = 0xb1;
break;
default:
pr_err("%s() New hardware revision found 0x%x\n",
__func__, dev->hwrevision);
}
if (dev->hwrevision)
pr_info("%s() Hardware revision = 0x%02x\n",
__func__, dev->hwrevision);
else
pr_err("%s() Hardware revision unknown 0x%x\n",
__func__, dev->hwrevision);
}
/* Find the first v4l2_subdev member of the group id in hw */
struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw)
{
struct v4l2_subdev *result = NULL;
struct v4l2_subdev *sd;
spin_lock(&dev->v4l2_dev.lock);
v4l2_device_for_each_subdev(sd, &dev->v4l2_dev) {
if (sd->grp_id == hw) {
result = sd;
break;
}
}
spin_unlock(&dev->v4l2_dev.lock);
return result;
}
static int cx23885_dev_setup(struct cx23885_dev *dev)
{
int i;
spin_lock_init(&dev->pci_irqmask_lock);
spin_lock_init(&dev->slock);
mutex_init(&dev->lock);
mutex_init(&dev->gpio_lock);
atomic_inc(&dev->refcount);
dev->nr = cx23885_devcount++;
sprintf(dev->name, "cx23885[%d]", dev->nr);
/* Configure the internal memory */
if (dev->pci->device == 0x8880) {
/* Could be 887 or 888, assume an 888 default */
dev->bridge = CX23885_BRIDGE_888;
/* Apply a sensible clock frequency for the PCIe bridge */
dev->clk_freq = 50000000;
dev->sram_channels = cx23887_sram_channels;
} else
if (dev->pci->device == 0x8852) {
dev->bridge = CX23885_BRIDGE_885;
/* Apply a sensible clock frequency for the PCIe bridge */
dev->clk_freq = 28000000;
dev->sram_channels = cx23885_sram_channels;
} else
BUG();
dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
__func__, dev->bridge);
/* board config */
dev->board = UNSET;
if (card[dev->nr] < cx23885_bcount)
dev->board = card[dev->nr];
for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
dev->pci->subsystem_device == cx23885_subids[i].subdevice)
dev->board = cx23885_subids[i].card;
if (UNSET == dev->board) {
dev->board = CX23885_BOARD_UNKNOWN;
cx23885_card_list(dev);
}
if (dev->pci->device == 0x8852) {
/* no DIF on cx23885, so no analog tuner support possible */
if (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC)
dev->board = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885;
else if (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_DVB)
dev->board = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885;
}
/* If the user specific a clk freq override, apply it */
if (cx23885_boards[dev->board].clk_freq > 0)
dev->clk_freq = cx23885_boards[dev->board].clk_freq;
if (dev->board == CX23885_BOARD_HAUPPAUGE_IMPACTVCBE &&
dev->pci->subsystem_device == 0x7137) {
/* Hauppauge ImpactVCBe device ID 0x7137 is populated
* with an 888, and a 25Mhz crystal, instead of the
* usual third overtone 50Mhz. The default clock rate must
* be overridden so the cx25840 is properly configured
*/
dev->clk_freq = 25000000;
}
dev->pci_bus = dev->pci->bus->number;
dev->pci_slot = PCI_SLOT(dev->pci->devfn);
cx23885_irq_add(dev, 0x001f00);
/* External Master 1 Bus */
dev->i2c_bus[0].nr = 0;
dev->i2c_bus[0].dev = dev;
dev->i2c_bus[0].reg_stat = I2C1_STAT;
dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
dev->i2c_bus[0].reg_addr = I2C1_ADDR;
dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
/* External Master 2 Bus */
dev->i2c_bus[1].nr = 1;
dev->i2c_bus[1].dev = dev;
dev->i2c_bus[1].reg_stat = I2C2_STAT;
dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
dev->i2c_bus[1].reg_addr = I2C2_ADDR;
dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
/* Internal Master 3 Bus */
dev->i2c_bus[2].nr = 2;
dev->i2c_bus[2].dev = dev;
dev->i2c_bus[2].reg_stat = I2C3_STAT;
dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
dev->i2c_bus[2].reg_addr = I2C3_ADDR;
dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
(cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
cx23885_init_tsport(dev, &dev->ts1, 1);
if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
(cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
cx23885_init_tsport(dev, &dev->ts2, 2);
if (get_resources(dev) < 0) {
pr_err("CORE %s No more PCIe resources for subsystem: %04x:%04x\n",
dev->name, dev->pci->subsystem_vendor,
dev->pci->subsystem_device);
cx23885_devcount--;
return -ENODEV;
}
/* PCIe stuff */
dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
pci_resource_len(dev->pci, 0));
dev->bmmio = (u8 __iomem *)dev->lmmio;
pr_info("CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
dev->name, dev->pci->subsystem_vendor,
dev->pci->subsystem_device, cx23885_boards[dev->board].name,
dev->board, card[dev->nr] == dev->board ?
"insmod option" : "autodetected");
cx23885_pci_quirks(dev);
/* Assume some sensible defaults */
dev->tuner_type = cx23885_boards[dev->board].tuner_type;
dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
dev->tuner_bus = cx23885_boards[dev->board].tuner_bus;
dev->radio_type = cx23885_boards[dev->board].radio_type;
dev->radio_addr = cx23885_boards[dev->board].radio_addr;
dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x tuner_bus = %d\n",
__func__, dev->tuner_type, dev->tuner_addr, dev->tuner_bus);
dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
__func__, dev->radio_type, dev->radio_addr);
/* The cx23417 encoder has GPIO's that need to be initialised
* before DVB, so that demodulators and tuners are out of
* reset before DVB uses them.
*/
if ((cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) ||
(cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
cx23885_mc417_init(dev);
/* init hardware */
cx23885_reset(dev);
cx23885_i2c_register(&dev->i2c_bus[0]);
cx23885_i2c_register(&dev->i2c_bus[1]);
cx23885_i2c_register(&dev->i2c_bus[2]);
cx23885_card_setup(dev);
call_all(dev, tuner, standby);
cx23885_ir_init(dev);
if (dev->board == CX23885_BOARD_VIEWCAST_460E) {
/*
* GPIOs 9/8 are input detection bits for the breakout video
* (gpio 8) and audio (gpio 9) cables. When they're attached,
* this gpios are pulled high. Make sure these GPIOs are marked
* as inputs.
*/
cx23885_gpio_enable(dev, 0x300, 0);
}
if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
if (cx23885_video_register(dev) < 0) {
pr_err("%s() Failed to register analog video adapters on VID_A\n",
__func__);
}
}
if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
if (cx23885_boards[dev->board].num_fds_portb)
dev->ts1.num_frontends =
cx23885_boards[dev->board].num_fds_portb;
if (cx23885_dvb_register(&dev->ts1) < 0) {
pr_err("%s() Failed to register dvb adapters on VID_B\n",
__func__);
}
} else
if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
if (cx23885_417_register(dev) < 0) {
pr_err("%s() Failed to register 417 on VID_B\n",
__func__);
}
}
if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
if (cx23885_boards[dev->board].num_fds_portc)
dev->ts2.num_frontends =
cx23885_boards[dev->board].num_fds_portc;
if (cx23885_dvb_register(&dev->ts2) < 0) {
pr_err("%s() Failed to register dvb on VID_C\n",
__func__);
}
} else
if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
if (cx23885_417_register(dev) < 0) {
pr_err("%s() Failed to register 417 on VID_C\n",
__func__);
}
}
cx23885_dev_checkrevision(dev);
/* disable MSI for NetUP cards, otherwise CI is not working */
if (cx23885_boards[dev->board].ci_type > 0)
cx_clear(RDR_RDRCTL1, 1 << 8);
switch (dev->board) {
case CX23885_BOARD_TEVII_S470:
case CX23885_BOARD_TEVII_S471:
cx_clear(RDR_RDRCTL1, 1 << 8);
break;
}
return 0;
}
static void cx23885_dev_unregister(struct cx23885_dev *dev)
{
release_mem_region(pci_resource_start(dev->pci, 0),
pci_resource_len(dev->pci, 0));
if (!atomic_dec_and_test(&dev->refcount))
return;
if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
cx23885_video_unregister(dev);
if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
cx23885_dvb_unregister(&dev->ts1);
if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
cx23885_417_unregister(dev);
if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
cx23885_dvb_unregister(&dev->ts2);
if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
cx23885_417_unregister(dev);
cx23885_i2c_unregister(&dev->i2c_bus[2]);
cx23885_i2c_unregister(&dev->i2c_bus[1]);
cx23885_i2c_unregister(&dev->i2c_bus[0]);
iounmap(dev->lmmio);
}
static __le32 *cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
unsigned int offset, u32 sync_line,
unsigned int bpl, unsigned int padding,
unsigned int lines, unsigned int lpi, bool jump)
{
struct scatterlist *sg;
unsigned int line, todo, sol;
if (jump) {
*(rp++) = cpu_to_le32(RISC_JUMP);
*(rp++) = cpu_to_le32(0);
*(rp++) = cpu_to_le32(0); /* bits 63-32 */
}
/* sync instruction */
if (sync_line != NO_SYNC_LINE)
*(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
/* scan lines */
sg = sglist;
for (line = 0; line < lines; line++) {
while (offset && offset >= sg_dma_len(sg)) {
offset -= sg_dma_len(sg);
sg = sg_next(sg);
}
if (lpi && line > 0 && !(line % lpi))
sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
else
sol = RISC_SOL;
if (bpl <= sg_dma_len(sg)-offset) {
/* fits into current chunk */
*(rp++) = cpu_to_le32(RISC_WRITE|sol|RISC_EOL|bpl);
*(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
*(rp++) = cpu_to_le32(0); /* bits 63-32 */
offset += bpl;
} else {
/* scanline needs to be split */
todo = bpl;
*(rp++) = cpu_to_le32(RISC_WRITE|sol|
(sg_dma_len(sg)-offset));
*(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
*(rp++) = cpu_to_le32(0); /* bits 63-32 */
todo -= (sg_dma_len(sg)-offset);
offset = 0;
sg = sg_next(sg);
while (todo > sg_dma_len(sg)) {
*(rp++) = cpu_to_le32(RISC_WRITE|
sg_dma_len(sg));
*(rp++) = cpu_to_le32(sg_dma_address(sg));
*(rp++) = cpu_to_le32(0); /* bits 63-32 */
todo -= sg_dma_len(sg);
sg = sg_next(sg);
}
*(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
*(rp++) = cpu_to_le32(sg_dma_address(sg));
*(rp++) = cpu_to_le32(0); /* bits 63-32 */
offset += todo;
}
offset += padding;
}
return rp;
}
int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
struct scatterlist *sglist, unsigned int top_offset,
unsigned int bottom_offset, unsigned int bpl,
unsigned int padding, unsigned int lines)
{
u32 instructions, fields;
__le32 *rp;
fields = 0;
if (UNSET != top_offset)
fields++;
if (UNSET != bottom_offset)
fields++;
/* estimate risc mem: worst case is one write per page border +
one write per scan line + syncs + jump (all 2 dwords). Padding
can cause next bpl to start close to a page border. First DMA
region may be smaller than PAGE_SIZE */
/* write and jump need and extra dword */
instructions = fields * (1 + ((bpl + padding) * lines)
/ PAGE_SIZE + lines);
instructions += 5;
risc->size = instructions * 12;
risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma,
GFP_KERNEL);
if (risc->cpu == NULL)
return -ENOMEM;
/* write risc instructions */
rp = risc->cpu;
if (UNSET != top_offset)
rp = cx23885_risc_field(rp, sglist, top_offset, 0,
bpl, padding, lines, 0, true);
if (UNSET != bottom_offset)
rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
bpl, padding, lines, 0, UNSET == top_offset);
/* save pointer to jmp instruction address */
risc->jmp = rp;
BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
return 0;
}
int cx23885_risc_databuffer(struct pci_dev *pci,
struct cx23885_riscmem *risc,
struct scatterlist *sglist,
unsigned int bpl,
unsigned int lines, unsigned int lpi)
{
u32 instructions;
__le32 *rp;
/* estimate risc mem: worst case is one write per page border +
one write per scan line + syncs + jump (all 2 dwords). Here
there is no padding and no sync. First DMA region may be smaller
than PAGE_SIZE */
/* Jump and write need an extra dword */
instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
instructions += 4;
risc->size = instructions * 12;
risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma,
GFP_KERNEL);
if (risc->cpu == NULL)
return -ENOMEM;
/* write risc instructions */
rp = risc->cpu;
rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE,
bpl, 0, lines, lpi, lpi == 0);
/* save pointer to jmp instruction address */
risc->jmp = rp;
BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
return 0;
}
int cx23885_risc_vbibuffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
struct scatterlist *sglist, unsigned int top_offset,
unsigned int bottom_offset, unsigned int bpl,
unsigned int padding, unsigned int lines)
{
u32 instructions, fields;
__le32 *rp;
fields = 0;
if (UNSET != top_offset)
fields++;
if (UNSET != bottom_offset)
fields++;
/* estimate risc mem: worst case is one write per page border +
one write per scan line + syncs + jump (all 2 dwords). Padding
can cause next bpl to start close to a page border. First DMA
region may be smaller than PAGE_SIZE */
/* write and jump need and extra dword */
instructions = fields * (1 + ((bpl + padding) * lines)
/ PAGE_SIZE + lines);
instructions += 5;
risc->size = instructions * 12;
risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma,
GFP_KERNEL);
if (risc->cpu == NULL)
return -ENOMEM;
/* write risc instructions */
rp = risc->cpu;
/* Sync to line 6, so US CC line 21 will appear in line '12'
* in the userland vbi payload */
if (UNSET != top_offset)
rp = cx23885_risc_field(rp, sglist, top_offset, 0,
bpl, padding, lines, 0, true);
if (UNSET != bottom_offset)
rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
bpl, padding, lines, 0, UNSET == top_offset);
/* save pointer to jmp instruction address */
risc->jmp = rp;
BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
return 0;
}
void cx23885_free_buffer(struct cx23885_dev *dev, struct cx23885_buffer *buf)
{
struct cx23885_riscmem *risc = &buf->risc;
if (risc->cpu)
dma_free_coherent(&dev->pci->dev, risc->size, risc->cpu, risc->dma);
memset(risc, 0, sizeof(*risc));
}
static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
{
struct cx23885_dev *dev = port->dev;
dprintk(1, "%s() Register Dump\n", __func__);
dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__,
cx_read(DEV_CNTRL2));
dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__,
cx23885_irq_get_mask(dev));
dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__,
cx_read(AUDIO_INT_INT_MSK));
dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__,
cx_read(AUD_INT_DMA_CTL));
dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__,
cx_read(AUDIO_EXT_INT_MSK));
dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__,
cx_read(AUD_EXT_DMA_CTL));
dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__,
cx_read(PAD_CTRL));
dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__,
cx_read(ALT_PIN_OUT_SEL));
dprintk(1, "%s() GPIO2 0x%08X\n", __func__,
cx_read(GPIO2));
dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__,
port->reg_gpcnt, cx_read(port->reg_gpcnt));
dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__,
port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
if (port->reg_src_sel)
dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
port->reg_src_sel, cx_read(port->reg_src_sel));
dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
port->reg_lngth, cx_read(port->reg_lngth));
dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__,
port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__,
port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__,
port->reg_sop_status, cx_read(port->reg_sop_status));
dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__,
port->reg_vld_misc, cx_read(port->reg_vld_misc));
dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__,
port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__,
port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
dprintk(1, "%s() ts_int_status(0x%08X) 0x%08x\n", __func__,
port->reg_ts_int_stat, cx_read(port->reg_ts_int_stat));
dprintk(1, "%s() PCI_INT_STAT 0x%08X\n", __func__,
cx_read(PCI_INT_STAT));
dprintk(1, "%s() VID_B_INT_MSTAT 0x%08X\n", __func__,
cx_read(VID_B_INT_MSTAT));
dprintk(1, "%s() VID_B_INT_SSTAT 0x%08X\n", __func__,
cx_read(VID_B_INT_SSTAT));
dprintk(1, "%s() VID_C_INT_MSTAT 0x%08X\n", __func__,
cx_read(VID_C_INT_MSTAT));
dprintk(1, "%s() VID_C_INT_SSTAT 0x%08X\n", __func__,
cx_read(VID_C_INT_SSTAT));
}
int cx23885_start_dma(struct cx23885_tsport *port,
struct cx23885_dmaqueue *q,
struct cx23885_buffer *buf)
{
struct cx23885_dev *dev = port->dev;
u32 reg;
dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
dev->width, dev->height, dev->field);
/* clear dma in progress */
cx23885_clear_bridge_error(dev);
/* Stop the fifo and risc engine for this port */
cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
/* setup fifo + format */
cx23885_sram_channel_setup(dev,
&dev->sram_channels[port->sram_chno],
port->ts_packet_size, buf->risc.dma);
if (debug > 5) {
cx23885_sram_channel_dump(dev,
&dev->sram_channels[port->sram_chno]);
cx23885_risc_disasm(port, &buf->risc);
}
/* write TS length to chip */
cx_write(port->reg_lngth, port->ts_packet_size);
if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
(!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) {
pr_err("%s() Unsupported .portb/c (0x%08x)/(0x%08x)\n",
__func__,
cx23885_boards[dev->board].portb,
cx23885_boards[dev->board].portc);
return -EINVAL;
}
if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
cx23885_av_clk(dev, 0);
udelay(100);
/* If the port supports SRC SELECT, configure it */
if (port->reg_src_sel)
cx_write(port->reg_src_sel, port->src_sel_val);
cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
cx_write(port->reg_vld_misc, port->vld_misc_val);
cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
udelay(100);
/* NOTE: this is 2 (reserved) for portb, does it matter? */
/* reset counter to zero */
cx_write(port->reg_gpcnt_ctl, 3);
q->count = 0;
/* Set VIDB pins to input */
if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
reg = cx_read(PAD_CTRL);
reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
cx_write(PAD_CTRL, reg);
}
/* Set VIDC pins to input */
if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
reg = cx_read(PAD_CTRL);
reg &= ~0x4; /* Clear TS2_SOP_OE */
cx_write(PAD_CTRL, reg);
}
if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
reg = cx_read(PAD_CTRL);
reg = reg & ~0x1; /* Clear TS1_OE */
/* FIXME, bit 2 writing here is questionable */
/* set TS1_SOP_OE and TS1_OE_HI */
reg = reg | 0xa;
cx_write(PAD_CTRL, reg);
/* Sets MOE_CLK_DIS to disable MoE clock */
/* sets MCLK_DLY_SEL/BCLK_DLY_SEL to 1 buffer delay each */
cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
/* ALT_GPIO_ALT_SET: GPIO[0]
* IR_ALT_TX_SEL: GPIO[1]
* GPIO1_ALT_SEL: VIP_656_DATA[0]
* GPIO0_ALT_SEL: VIP_656_CLK
*/
cx_write(ALT_PIN_OUT_SEL, 0x10100045);
}
switch (dev->bridge) {
case CX23885_BRIDGE_885:
case CX23885_BRIDGE_887:
case CX23885_BRIDGE_888:
/* enable irqs */
dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
/* clear dma in progress */
cx23885_clear_bridge_error(dev);
cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
cx_set(port->reg_dma_ctl, port->dma_ctl_val);
/* clear dma in progress */
cx23885_clear_bridge_error(dev);
cx23885_irq_add(dev, port->pci_irqmask);
cx23885_irq_enable_all(dev);
/* clear dma in progress */
cx23885_clear_bridge_error(dev);
break;
default:
BUG();
}
cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
/* clear dma in progress */
cx23885_clear_bridge_error(dev);
if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
cx23885_av_clk(dev, 1);
if (debug > 4)
cx23885_tsport_reg_dump(port);
cx23885_irq_get_mask(dev);
/* clear dma in progress */
cx23885_clear_bridge_error(dev);
return 0;
}
static int cx23885_stop_dma(struct cx23885_tsport *port)
{
struct cx23885_dev *dev = port->dev;
u32 reg;
int delay = 0;
uint32_t reg1_val;
uint32_t reg2_val;
dprintk(1, "%s()\n", __func__);
/* Stop interrupts and DMA */
cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
/* just in case wait for any dma to complete before allowing dealloc */
mdelay(20);
for (delay = 0; delay < 100; delay++) {
reg1_val = cx_read(TC_REQ);
reg2_val = cx_read(TC_REQ_SET);
if (reg1_val == 0 || reg2_val == 0)
break;
mdelay(1);
}
dev_dbg(&dev->pci->dev, "delay=%d reg1=0x%08x reg2=0x%08x\n",
delay, reg1_val, reg2_val);
if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
reg = cx_read(PAD_CTRL);
/* Set TS1_OE */
reg = reg | 0x1;
/* clear TS1_SOP_OE and TS1_OE_HI */
reg = reg & ~0xa;
cx_write(PAD_CTRL, reg);
cx_write(port->reg_src_sel, 0);
cx_write(port->reg_gen_ctrl, 8);
}
if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
cx23885_av_clk(dev, 0);
return 0;
}
/* ------------------------------------------------------------------ */
int cx23885_buf_prepare(struct cx23885_buffer *buf, struct cx23885_tsport *port)
{
struct cx23885_dev *dev = port->dev;
int size = port->ts_packet_size * port->ts_packet_count;
struct sg_table *sgt = vb2_dma_sg_plane_desc(&buf->vb.vb2_buf, 0);
dprintk(1, "%s: %p\n", __func__, buf);
if (vb2_plane_size(&buf->vb.vb2_buf, 0) < size)
return -EINVAL;
vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
cx23885_risc_databuffer(dev->pci, &buf->risc,
sgt->sgl,
port->ts_packet_size, port->ts_packet_count, 0);
return 0;
}
/*
* The risc program for each buffer works as follows: it starts with a simple
* 'JUMP to addr + 12', which is effectively a NOP. Then the code to DMA the
* buffer follows and at the end we have a JUMP back to the start + 12 (skipping
* the initial JUMP).
*
* This is the risc program of the first buffer to be queued if the active list
* is empty and it just keeps DMAing this buffer without generating any
* interrupts.
*
* If a new buffer is added then the initial JUMP in the code for that buffer
* will generate an interrupt which signals that the previous buffer has been
* DMAed successfully and that it can be returned to userspace.
*
* It also sets the final jump of the previous buffer to the start of the new
* buffer, thus chaining the new buffer into the DMA chain. This is a single
* atomic u32 write, so there is no race condition.
*
* The end-result of all this that you only get an interrupt when a buffer
* is ready, so the control flow is very easy.
*/
void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
{
struct cx23885_buffer *prev;
struct cx23885_dev *dev = port->dev;
struct cx23885_dmaqueue *cx88q = &port->mpegq;
unsigned long flags;
buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12);
buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12);
buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
spin_lock_irqsave(&dev->slock, flags);
if (list_empty(&cx88q->active)) {
list_add_tail(&buf->queue, &cx88q->active);
dprintk(1, "[%p/%d] %s - first active\n",
buf, buf->vb.vb2_buf.index, __func__);
} else {
buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
queue);
list_add_tail(&buf->queue, &cx88q->active);
prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
dprintk(1, "[%p/%d] %s - append to active\n",
buf, buf->vb.vb2_buf.index, __func__);
}
spin_unlock_irqrestore(&dev->slock, flags);
}
/* ----------------------------------------------------------- */
static void do_cancel_buffers(struct cx23885_tsport *port, char *reason)
{
struct cx23885_dmaqueue *q = &port->mpegq;
struct cx23885_buffer *buf;
unsigned long flags;
spin_lock_irqsave(&port->slock, flags);
while (!list_empty(&q->active)) {
buf = list_entry(q->active.next, struct cx23885_buffer,
queue);
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
buf, buf->vb.vb2_buf.index, reason,
(unsigned long)buf->risc.dma);
}
spin_unlock_irqrestore(&port->slock, flags);
}
void cx23885_cancel_buffers(struct cx23885_tsport *port)
{
dprintk(1, "%s()\n", __func__);
cx23885_stop_dma(port);
do_cancel_buffers(port, "cancel");
}
int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
{
/* FIXME: port1 assumption here. */
struct cx23885_tsport *port = &dev->ts1;
int count = 0;
int handled = 0;
if (status == 0)
return handled;
count = cx_read(port->reg_gpcnt);
dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
status, cx_read(port->reg_ts_int_msk), count);
if ((status & VID_B_MSK_BAD_PKT) ||
(status & VID_B_MSK_OPC_ERR) ||
(status & VID_B_MSK_VBI_OPC_ERR) ||
(status & VID_B_MSK_SYNC) ||
(status & VID_B_MSK_VBI_SYNC) ||
(status & VID_B_MSK_OF) ||
(status & VID_B_MSK_VBI_OF)) {
pr_err("%s: V4L mpeg risc op code error, status = 0x%x\n",
dev->name, status);
if (status & VID_B_MSK_BAD_PKT)
dprintk(1, " VID_B_MSK_BAD_PKT\n");
if (status & VID_B_MSK_OPC_ERR)
dprintk(1, " VID_B_MSK_OPC_ERR\n");
if (status & VID_B_MSK_VBI_OPC_ERR)
dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
if (status & VID_B_MSK_SYNC)
dprintk(1, " VID_B_MSK_SYNC\n");
if (status & VID_B_MSK_VBI_SYNC)
dprintk(1, " VID_B_MSK_VBI_SYNC\n");
if (status & VID_B_MSK_OF)
dprintk(1, " VID_B_MSK_OF\n");
if (status & VID_B_MSK_VBI_OF)
dprintk(1, " VID_B_MSK_VBI_OF\n");
cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
cx23885_sram_channel_dump(dev,
&dev->sram_channels[port->sram_chno]);
cx23885_417_check_encoder(dev);
} else if (status & VID_B_MSK_RISCI1) {
dprintk(7, " VID_B_MSK_RISCI1\n");
spin_lock(&port->slock);
cx23885_wakeup(port, &port->mpegq, count);
spin_unlock(&port->slock);
}
if (status) {
cx_write(port->reg_ts_int_stat, status);
handled = 1;
}
return handled;
}
static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
{
struct cx23885_dev *dev = port->dev;
int handled = 0;
u32 count;
if ((status & VID_BC_MSK_OPC_ERR) ||
(status & VID_BC_MSK_BAD_PKT) ||
(status & VID_BC_MSK_SYNC) ||
(status & VID_BC_MSK_OF)) {
if (status & VID_BC_MSK_OPC_ERR)
dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
VID_BC_MSK_OPC_ERR);
if (status & VID_BC_MSK_BAD_PKT)
dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n",
VID_BC_MSK_BAD_PKT);
if (status & VID_BC_MSK_SYNC)
dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n",
VID_BC_MSK_SYNC);
if (status & VID_BC_MSK_OF)
dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n",
VID_BC_MSK_OF);
pr_err("%s: mpeg risc op code error\n", dev->name);
cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
cx23885_sram_channel_dump(dev,
&dev->sram_channels[port->sram_chno]);
} else if (status & VID_BC_MSK_RISCI1) {
dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
spin_lock(&port->slock);
count = cx_read(port->reg_gpcnt);
cx23885_wakeup(port, &port->mpegq, count);
spin_unlock(&port->slock);
}
if (status) {
cx_write(port->reg_ts_int_stat, status);
handled = 1;
}
return handled;
}
static irqreturn_t cx23885_irq(int irq, void *dev_id)
{
struct cx23885_dev *dev = dev_id;
struct cx23885_tsport *ts1 = &dev->ts1;
struct cx23885_tsport *ts2 = &dev->ts2;
u32 pci_status, pci_mask;
u32 vida_status, vida_mask;
u32 audint_status, audint_mask;
u32 ts1_status, ts1_mask;
u32 ts2_status, ts2_mask;
int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
int audint_count = 0;
bool subdev_handled;
pci_status = cx_read(PCI_INT_STAT);
pci_mask = cx23885_irq_get_mask(dev);
if ((pci_status & pci_mask) == 0) {
dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
pci_status, pci_mask);
goto out;
}
vida_status = cx_read(VID_A_INT_STAT);
vida_mask = cx_read(VID_A_INT_MSK);
audint_status = cx_read(AUDIO_INT_INT_STAT);
audint_mask = cx_read(AUDIO_INT_INT_MSK);
ts1_status = cx_read(VID_B_INT_STAT);
ts1_mask = cx_read(VID_B_INT_MSK);
ts2_status = cx_read(VID_C_INT_STAT);
ts2_mask = cx_read(VID_C_INT_MSK);
if (((pci_status & pci_mask) == 0) &&
((ts2_status & ts2_mask) == 0) &&
((ts1_status & ts1_mask) == 0))
goto out;
vida_count = cx_read(VID_A_GPCNT);
audint_count = cx_read(AUD_INT_A_GPCNT);
ts1_count = cx_read(ts1->reg_gpcnt);
ts2_count = cx_read(ts2->reg_gpcnt);
dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
pci_status, pci_mask);
dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
vida_status, vida_mask, vida_count);
dprintk(7, "audint_status: 0x%08x audint_mask: 0x%08x count: 0x%x\n",
audint_status, audint_mask, audint_count);
dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
ts1_status, ts1_mask, ts1_count);
dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
ts2_status, ts2_mask, ts2_count);
if (pci_status & (PCI_MSK_RISC_RD | PCI_MSK_RISC_WR |
PCI_MSK_AL_RD | PCI_MSK_AL_WR | PCI_MSK_APB_DMA |
PCI_MSK_VID_C | PCI_MSK_VID_B | PCI_MSK_VID_A |
PCI_MSK_AUD_INT | PCI_MSK_AUD_EXT |
PCI_MSK_GPIO0 | PCI_MSK_GPIO1 |
PCI_MSK_AV_CORE | PCI_MSK_IR)) {
if (pci_status & PCI_MSK_RISC_RD)
dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n",
PCI_MSK_RISC_RD);
if (pci_status & PCI_MSK_RISC_WR)
dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n",
PCI_MSK_RISC_WR);
if (pci_status & PCI_MSK_AL_RD)
dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n",
PCI_MSK_AL_RD);
if (pci_status & PCI_MSK_AL_WR)
dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n",
PCI_MSK_AL_WR);
if (pci_status & PCI_MSK_APB_DMA)
dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n",
PCI_MSK_APB_DMA);
if (pci_status & PCI_MSK_VID_C)
dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n",
PCI_MSK_VID_C);
if (pci_status & PCI_MSK_VID_B)
dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n",
PCI_MSK_VID_B);
if (pci_status & PCI_MSK_VID_A)
dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n",
PCI_MSK_VID_A);
if (pci_status & PCI_MSK_AUD_INT)
dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n",
PCI_MSK_AUD_INT);
if (pci_status & PCI_MSK_AUD_EXT)
dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n",
PCI_MSK_AUD_EXT);
if (pci_status & PCI_MSK_GPIO0)
dprintk(7, " (PCI_MSK_GPIO0 0x%08x)\n",
PCI_MSK_GPIO0);
if (pci_status & PCI_MSK_GPIO1)
dprintk(7, " (PCI_MSK_GPIO1 0x%08x)\n",
PCI_MSK_GPIO1);
if (pci_status & PCI_MSK_AV_CORE)
dprintk(7, " (PCI_MSK_AV_CORE 0x%08x)\n",
PCI_MSK_AV_CORE);
if (pci_status & PCI_MSK_IR)
dprintk(7, " (PCI_MSK_IR 0x%08x)\n",
PCI_MSK_IR);
}
if (cx23885_boards[dev->board].ci_type == 1 &&
(pci_status & (PCI_MSK_GPIO1 | PCI_MSK_GPIO0)))
handled += netup_ci_slot_status(dev, pci_status);
if (cx23885_boards[dev->board].ci_type == 2 &&
(pci_status & PCI_MSK_GPIO0))
handled += altera_ci_irq(dev);
if (ts1_status) {
if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
handled += cx23885_irq_ts(ts1, ts1_status);
else
if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
handled += cx23885_irq_417(dev, ts1_status);
}
if (ts2_status) {
if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
handled += cx23885_irq_ts(ts2, ts2_status);
else
if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
handled += cx23885_irq_417(dev, ts2_status);
}
if (vida_status)
handled += cx23885_video_irq(dev, vida_status);
if (audint_status)
handled += cx23885_audio_irq(dev, audint_status, audint_mask);
if (pci_status & PCI_MSK_IR) {
subdev_handled = false;
v4l2_subdev_call(dev->sd_ir, core, interrupt_service_routine,
pci_status, &subdev_handled);
if (subdev_handled)
handled++;
}
if ((pci_status & pci_mask) & PCI_MSK_AV_CORE) {
cx23885_irq_disable(dev, PCI_MSK_AV_CORE);
schedule_work(&dev->cx25840_work);
handled++;
}
if (handled)
cx_write(PCI_INT_STAT, pci_status & pci_mask);
out:
return IRQ_RETVAL(handled);
}
static void cx23885_v4l2_dev_notify(struct v4l2_subdev *sd,
unsigned int notification, void *arg)
{
struct cx23885_dev *dev;
if (sd == NULL)
return;
dev = to_cx23885(sd->v4l2_dev);
switch (notification) {
case V4L2_SUBDEV_IR_RX_NOTIFY: /* Possibly called in an IRQ context */
if (sd == dev->sd_ir)
cx23885_ir_rx_v4l2_dev_notify(sd, *(u32 *)arg);
break;
case V4L2_SUBDEV_IR_TX_NOTIFY: /* Possibly called in an IRQ context */
if (sd == dev->sd_ir)
cx23885_ir_tx_v4l2_dev_notify(sd, *(u32 *)arg);
break;
}
}
static void cx23885_v4l2_dev_notify_init(struct cx23885_dev *dev)
{
INIT_WORK(&dev->cx25840_work, cx23885_av_work_handler);
INIT_WORK(&dev->ir_rx_work, cx23885_ir_rx_work_handler);
INIT_WORK(&dev->ir_tx_work, cx23885_ir_tx_work_handler);
dev->v4l2_dev.notify = cx23885_v4l2_dev_notify;
}
static inline int encoder_on_portb(struct cx23885_dev *dev)
{
return cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER;
}
static inline int encoder_on_portc(struct cx23885_dev *dev)
{
return cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER;
}
/* Mask represents 32 different GPIOs, GPIO's are split into multiple
* registers depending on the board configuration (and whether the
* 417 encoder (wi it's own GPIO's) are present. Each GPIO bit will
* be pushed into the correct hardware register, regardless of the
* physical location. Certain registers are shared so we sanity check
* and report errors if we think we're tampering with a GPIo that might
* be assigned to the encoder (and used for the host bus).
*
* GPIO 2 through 0 - On the cx23885 bridge
* GPIO 18 through 3 - On the cx23417 host bus interface
* GPIO 23 through 19 - On the cx25840 a/v core
*/
void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask)
{
if (mask & 0x7)
cx_set(GP0_IO, mask & 0x7);
if (mask & 0x0007fff8) {
if (encoder_on_portb(dev) || encoder_on_portc(dev))
pr_err("%s: Setting GPIO on encoder ports\n",
dev->name);
cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
}
/* TODO: 23-19 */
if (mask & 0x00f80000)
pr_info("%s: Unsupported\n", dev->name);
}
void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask)
{
if (mask & 0x00000007)
cx_clear(GP0_IO, mask & 0x7);
if (mask & 0x0007fff8) {
if (encoder_on_portb(dev) || encoder_on_portc(dev))
pr_err("%s: Clearing GPIO moving on encoder ports\n",
dev->name);
cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
}
/* TODO: 23-19 */
if (mask & 0x00f80000)
pr_info("%s: Unsupported\n", dev->name);
}
u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask)
{
if (mask & 0x00000007)
return (cx_read(GP0_IO) >> 8) & mask & 0x7;
if (mask & 0x0007fff8) {
if (encoder_on_portb(dev) || encoder_on_portc(dev))
pr_err("%s: Reading GPIO moving on encoder ports\n",
dev->name);
return (cx_read(MC417_RWD) & ((mask & 0x7fff8) >> 3)) << 3;
}
/* TODO: 23-19 */
if (mask & 0x00f80000)
pr_info("%s: Unsupported\n", dev->name);
return 0;
}
void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
{
if ((mask & 0x00000007) && asoutput)
cx_set(GP0_IO, (mask & 0x7) << 16);
else if ((mask & 0x00000007) && !asoutput)
cx_clear(GP0_IO, (mask & 0x7) << 16);
if (mask & 0x0007fff8) {
if (encoder_on_portb(dev) || encoder_on_portc(dev))
pr_err("%s: Enabling GPIO on encoder ports\n",
dev->name);
}
/* MC417_OEN is active low for output, write 1 for an input */
if ((mask & 0x0007fff8) && asoutput)
cx_clear(MC417_OEN, (mask & 0x7fff8) >> 3);
else if ((mask & 0x0007fff8) && !asoutput)
cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
/* TODO: 23-19 */
}
static struct {
int vendor, dev;
} const broken_dev_id[] = {
/* According with
* https://openbenchmarking.org/system/1703021-RI-AMDZEN08075/Ryzen%207%201800X/lspci,
* 0x1451 is PCI ID for the IOMMU found on Ryzen
*/
{ PCI_VENDOR_ID_AMD, 0x1451 },
/* According to sudo lspci -nn,
* 0x1423 is the PCI ID for the IOMMU found on Kaveri
*/
{ PCI_VENDOR_ID_AMD, 0x1423 },
/* 0x1481 is the PCI ID for the IOMMU found on Starship/Matisse
*/
{ PCI_VENDOR_ID_AMD, 0x1481 },
/* 0x1419 is the PCI ID for the IOMMU found on 15h (Models 10h-1fh) family
*/
{ PCI_VENDOR_ID_AMD, 0x1419 },
/* 0x1631 is the PCI ID for the IOMMU found on Renoir/Cezanne
*/
{ PCI_VENDOR_ID_AMD, 0x1631 },
/* 0x5a23 is the PCI ID for the IOMMU found on RD890S/RD990
*/
{ PCI_VENDOR_ID_ATI, 0x5a23 },
};
static bool cx23885_does_need_dma_reset(void)
{
int i;
struct pci_dev *pdev = NULL;
if (dma_reset_workaround == 0)
return false;
else if (dma_reset_workaround == 2)
return true;
for (i = 0; i < ARRAY_SIZE(broken_dev_id); i++) {
pdev = pci_get_device(broken_dev_id[i].vendor,
broken_dev_id[i].dev, NULL);
if (pdev) {
pci_dev_put(pdev);
return true;
}
}
return false;
}
static int cx23885_initdev(struct pci_dev *pci_dev,
const struct pci_device_id *pci_id)
{
struct cx23885_dev *dev;
struct v4l2_ctrl_handler *hdl;
int err;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (NULL == dev)
return -ENOMEM;
dev->need_dma_reset = cx23885_does_need_dma_reset();
err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
if (err < 0)
goto fail_free;
hdl = &dev->ctrl_handler;
v4l2_ctrl_handler_init(hdl, 6);
if (hdl->error) {
err = hdl->error;
goto fail_ctrl;
}
dev->v4l2_dev.ctrl_handler = hdl;
/* Prepare to handle notifications from subdevices */
cx23885_v4l2_dev_notify_init(dev);
/* pci init */
dev->pci = pci_dev;
if (pci_enable_device(pci_dev)) {
err = -EIO;
goto fail_ctrl;
}
if (cx23885_dev_setup(dev) < 0) {
err = -EINVAL;
goto fail_ctrl;
}
/* print pci info */
dev->pci_rev = pci_dev->revision;
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
dev->name,
pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
dev->pci_lat,
(unsigned long long)pci_resource_start(pci_dev, 0));
pci_set_master(pci_dev);
err = dma_set_mask(&pci_dev->dev, 0xffffffff);
if (err) {
pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
goto fail_dma_set_mask;
}
err = request_irq(pci_dev->irq, cx23885_irq,
IRQF_SHARED, dev->name, dev);
if (err < 0) {
pr_err("%s: can't get IRQ %d\n",
dev->name, pci_dev->irq);
goto fail_dma_set_mask;
}
switch (dev->board) {
case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
cx23885_irq_add_enable(dev, PCI_MSK_GPIO1 | PCI_MSK_GPIO0);
break;
case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
cx23885_irq_add_enable(dev, PCI_MSK_GPIO0);
break;
}
/*
* The CX2388[58] IR controller can start firing interrupts when
* enabled, so these have to take place after the cx23885_irq() handler
* is hooked up by the call to request_irq() above.
*/
cx23885_ir_pci_int_enable(dev);
cx23885_input_init(dev);
return 0;
fail_dma_set_mask:
cx23885_dev_unregister(dev);
fail_ctrl:
v4l2_ctrl_handler_free(hdl);
v4l2_device_unregister(&dev->v4l2_dev);
fail_free:
kfree(dev);
return err;
}
static void cx23885_finidev(struct pci_dev *pci_dev)
{
struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
struct cx23885_dev *dev = to_cx23885(v4l2_dev);
cx23885_input_fini(dev);
cx23885_ir_fini(dev);
cx23885_shutdown(dev);
/* unregister stuff */
free_irq(pci_dev->irq, dev);
pci_disable_device(pci_dev);
cx23885_dev_unregister(dev);
v4l2_ctrl_handler_free(&dev->ctrl_handler);
v4l2_device_unregister(v4l2_dev);
kfree(dev);
}
static const struct pci_device_id cx23885_pci_tbl[] = {
{
/* CX23885 */
.vendor = 0x14f1,
.device = 0x8852,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
}, {
/* CX23887 Rev 2 */
.vendor = 0x14f1,
.device = 0x8880,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
}, {
/* --- end of list --- */
}
};
MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
static struct pci_driver cx23885_pci_driver = {
.name = "cx23885",
.id_table = cx23885_pci_tbl,
.probe = cx23885_initdev,
.remove = cx23885_finidev,
};
static int __init cx23885_init(void)
{
pr_info("cx23885 driver version %s loaded\n",
CX23885_VERSION);
return pci_register_driver(&cx23885_pci_driver);
}
static void __exit cx23885_fini(void)
{
pci_unregister_driver(&cx23885_pci_driver);
}
module_init(cx23885_init);
module_exit(cx23885_fini);
| linux-master | drivers/media/pci/cx23885/cx23885-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Conexant CX23885/7/8 PCIe bridge
*
* AV device support routines - non-input, non-vl42_subdev routines
*
* Copyright (C) 2010 Andy Walls <[email protected]>
*/
#include "cx23885.h"
#include "cx23885-av.h"
#include "cx23885-video.h"
void cx23885_av_work_handler(struct work_struct *work)
{
struct cx23885_dev *dev =
container_of(work, struct cx23885_dev, cx25840_work);
bool handled = false;
v4l2_subdev_call(dev->sd_cx25840, core, interrupt_service_routine,
PCI_MSK_AV_CORE, &handled);
/* Getting here with the interrupt not handled
then probbaly flatiron does have pending interrupts.
*/
if (!handled) {
/* clear left and right adc channel interrupt request flag */
cx23885_flatiron_write(dev, 0x1f,
cx23885_flatiron_read(dev, 0x1f) | 0x80);
cx23885_flatiron_write(dev, 0x23,
cx23885_flatiron_read(dev, 0x23) | 0x80);
}
cx23885_irq_enable(dev, PCI_MSK_AV_CORE);
}
| linux-master | drivers/media/pci/cx23885/cx23885-av.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Conexant CX23885 PCIe bridge
*
* Copyright (c) 2007 Steven Toth <[email protected]>
*/
#include "cx23885.h"
#include "cx23885-video.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kmod.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/kthread.h>
#include <asm/div64.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-event.h>
#include "cx23885-ioctl.h"
#include "xc2028.h"
#include <media/drv-intf/cx25840.h>
MODULE_DESCRIPTION("v4l2 driver module for cx23885 based TV cards");
MODULE_AUTHOR("Steven Toth <[email protected]>");
MODULE_LICENSE("GPL");
/* ------------------------------------------------------------------ */
static unsigned int video_nr[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
static unsigned int vbi_nr[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
module_param_array(video_nr, int, NULL, 0444);
module_param_array(vbi_nr, int, NULL, 0444);
MODULE_PARM_DESC(video_nr, "video device numbers");
MODULE_PARM_DESC(vbi_nr, "vbi device numbers");
static unsigned int video_debug;
module_param(video_debug, int, 0644);
MODULE_PARM_DESC(video_debug, "enable debug messages [video]");
static unsigned int irq_debug;
module_param(irq_debug, int, 0644);
MODULE_PARM_DESC(irq_debug, "enable debug messages [IRQ handler]");
static unsigned int vid_limit = 16;
module_param(vid_limit, int, 0644);
MODULE_PARM_DESC(vid_limit, "capture memory limit in megabytes");
#define dprintk(level, fmt, arg...)\
do { if (video_debug >= level)\
printk(KERN_DEBUG pr_fmt("%s: video:" fmt), \
__func__, ##arg); \
} while (0)
/* ------------------------------------------------------------------- */
/* static data */
#define FORMAT_FLAGS_PACKED 0x01
static struct cx23885_fmt formats[] = {
{
.fourcc = V4L2_PIX_FMT_YUYV,
.depth = 16,
.flags = FORMAT_FLAGS_PACKED,
}
};
static struct cx23885_fmt *format_by_fourcc(unsigned int fourcc)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(formats); i++)
if (formats[i].fourcc == fourcc)
return formats+i;
return NULL;
}
/* ------------------------------------------------------------------- */
void cx23885_video_wakeup(struct cx23885_dev *dev,
struct cx23885_dmaqueue *q, u32 count)
{
struct cx23885_buffer *buf;
if (list_empty(&q->active))
return;
buf = list_entry(q->active.next,
struct cx23885_buffer, queue);
buf->vb.sequence = q->count++;
buf->vb.vb2_buf.timestamp = ktime_get_ns();
dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf,
buf->vb.vb2_buf.index, count, q->count);
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm)
{
struct v4l2_subdev_format format = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
.format.code = MEDIA_BUS_FMT_FIXED,
};
dprintk(1, "%s(norm = 0x%08x) name: [%s]\n",
__func__,
(unsigned int)norm,
v4l2_norm_to_name(norm));
if (dev->tvnorm == norm)
return 0;
if (dev->tvnorm != norm) {
if (vb2_is_busy(&dev->vb2_vidq) || vb2_is_busy(&dev->vb2_vbiq) ||
vb2_is_busy(&dev->vb2_mpegq))
return -EBUSY;
}
dev->tvnorm = norm;
dev->width = 720;
dev->height = norm_maxh(norm);
dev->field = V4L2_FIELD_INTERLACED;
call_all(dev, video, s_std, norm);
format.format.width = dev->width;
format.format.height = dev->height;
format.format.field = dev->field;
call_all(dev, pad, set_fmt, NULL, &format);
return 0;
}
static struct video_device *cx23885_vdev_init(struct cx23885_dev *dev,
struct pci_dev *pci,
struct video_device *template,
char *type)
{
struct video_device *vfd;
dprintk(1, "%s()\n", __func__);
vfd = video_device_alloc();
if (NULL == vfd)
return NULL;
*vfd = *template;
vfd->v4l2_dev = &dev->v4l2_dev;
vfd->release = video_device_release;
vfd->lock = &dev->lock;
snprintf(vfd->name, sizeof(vfd->name), "%s (%s)",
cx23885_boards[dev->board].name, type);
video_set_drvdata(vfd, dev);
return vfd;
}
int cx23885_flatiron_write(struct cx23885_dev *dev, u8 reg, u8 data)
{
/* 8 bit registers, 8 bit values */
u8 buf[] = { reg, data };
struct i2c_msg msg = { .addr = 0x98 >> 1,
.flags = 0, .buf = buf, .len = 2 };
return i2c_transfer(&dev->i2c_bus[2].i2c_adap, &msg, 1);
}
u8 cx23885_flatiron_read(struct cx23885_dev *dev, u8 reg)
{
/* 8 bit registers, 8 bit values */
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{ .addr = 0x98 >> 1, .flags = 0, .buf = b0, .len = 1 },
{ .addr = 0x98 >> 1, .flags = I2C_M_RD, .buf = b1, .len = 1 }
};
ret = i2c_transfer(&dev->i2c_bus[2].i2c_adap, &msg[0], 2);
if (ret != 2)
pr_err("%s() error\n", __func__);
return b1[0];
}
static void cx23885_flatiron_dump(struct cx23885_dev *dev)
{
int i;
dprintk(1, "Flatiron dump\n");
for (i = 0; i < 0x24; i++) {
dprintk(1, "FI[%02x] = %02x\n", i,
cx23885_flatiron_read(dev, i));
}
}
static int cx23885_flatiron_mux(struct cx23885_dev *dev, int input)
{
u8 val;
dprintk(1, "%s(input = %d)\n", __func__, input);
if (input == 1)
val = cx23885_flatiron_read(dev, CH_PWR_CTRL1) & ~FLD_CH_SEL;
else if (input == 2)
val = cx23885_flatiron_read(dev, CH_PWR_CTRL1) | FLD_CH_SEL;
else
return -EINVAL;
val |= 0x20; /* Enable clock to delta-sigma and dec filter */
cx23885_flatiron_write(dev, CH_PWR_CTRL1, val);
/* Wake up */
cx23885_flatiron_write(dev, CH_PWR_CTRL2, 0);
if (video_debug)
cx23885_flatiron_dump(dev);
return 0;
}
static int cx23885_video_mux(struct cx23885_dev *dev, unsigned int input)
{
dprintk(1, "%s() video_mux: %d [vmux=%d, gpio=0x%x,0x%x,0x%x,0x%x]\n",
__func__,
input, INPUT(input)->vmux,
INPUT(input)->gpio0, INPUT(input)->gpio1,
INPUT(input)->gpio2, INPUT(input)->gpio3);
dev->input = input;
if (dev->board == CX23885_BOARD_MYGICA_X8506 ||
dev->board == CX23885_BOARD_MAGICPRO_PROHDTVE2 ||
dev->board == CX23885_BOARD_MYGICA_X8507) {
/* Select Analog TV */
if (INPUT(input)->type == CX23885_VMUX_TELEVISION)
cx23885_gpio_clear(dev, GPIO_0);
}
/* Tell the internal A/V decoder */
v4l2_subdev_call(dev->sd_cx25840, video, s_routing,
INPUT(input)->vmux, 0, 0);
if ((dev->board == CX23885_BOARD_HAUPPAUGE_HVR1800) ||
(dev->board == CX23885_BOARD_MPX885) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1250) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_IMPACTVCBE) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255_22111) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1265_K4) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_DVB) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1850) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR5525) ||
(dev->board == CX23885_BOARD_MYGICA_X8507) ||
(dev->board == CX23885_BOARD_AVERMEDIA_HC81R) ||
(dev->board == CX23885_BOARD_VIEWCAST_260E) ||
(dev->board == CX23885_BOARD_VIEWCAST_460E) ||
(dev->board == CX23885_BOARD_AVERMEDIA_CE310B)) {
/* Configure audio routing */
v4l2_subdev_call(dev->sd_cx25840, audio, s_routing,
INPUT(input)->amux, 0, 0);
if (INPUT(input)->amux == CX25840_AUDIO7)
cx23885_flatiron_mux(dev, 1);
else if (INPUT(input)->amux == CX25840_AUDIO6)
cx23885_flatiron_mux(dev, 2);
}
return 0;
}
static int cx23885_audio_mux(struct cx23885_dev *dev, unsigned int input)
{
dprintk(1, "%s(input=%d)\n", __func__, input);
/* The baseband video core of the cx23885 has two audio inputs.
* LR1 and LR2. In almost every single case so far only HVR1xxx
* cards we've only ever supported LR1. Time to support LR2,
* which is available via the optional white breakout header on
* the board.
* We'll use a could of existing enums in the card struct to allow
* devs to specify which baseband input they need, or just default
* to what we've always used.
*/
if (INPUT(input)->amux == CX25840_AUDIO7)
cx23885_flatiron_mux(dev, 1);
else if (INPUT(input)->amux == CX25840_AUDIO6)
cx23885_flatiron_mux(dev, 2);
else {
/* Not specifically defined, assume the default. */
cx23885_flatiron_mux(dev, 1);
}
return 0;
}
/* ------------------------------------------------------------------ */
static int cx23885_start_video_dma(struct cx23885_dev *dev,
struct cx23885_dmaqueue *q,
struct cx23885_buffer *buf)
{
dprintk(1, "%s()\n", __func__);
/* Stop the dma/fifo before we tamper with it's risc programs */
cx_clear(VID_A_DMA_CTL, 0x11);
/* setup fifo + format */
cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
buf->bpl, buf->risc.dma);
/* reset counter */
cx_write(VID_A_GPCNT_CTL, 3);
q->count = 0;
/* enable irq */
cx23885_irq_add_enable(dev, 0x01);
cx_set(VID_A_INT_MSK, 0x000011);
/* start dma */
cx_set(DEV_CNTRL2, (1<<5));
cx_set(VID_A_DMA_CTL, 0x11); /* FIFO and RISC enable */
return 0;
}
static int queue_setup(struct vb2_queue *q,
unsigned int *num_buffers, unsigned int *num_planes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct cx23885_dev *dev = q->drv_priv;
*num_planes = 1;
sizes[0] = (dev->fmt->depth * dev->width * dev->height) >> 3;
return 0;
}
static int buffer_prepare(struct vb2_buffer *vb)
{
int ret;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
struct cx23885_buffer *buf =
container_of(vbuf, struct cx23885_buffer, vb);
u32 line0_offset, line1_offset;
struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
int field_tff;
buf->bpl = (dev->width * dev->fmt->depth) >> 3;
if (vb2_plane_size(vb, 0) < dev->height * buf->bpl)
return -EINVAL;
vb2_set_plane_payload(vb, 0, dev->height * buf->bpl);
switch (dev->field) {
case V4L2_FIELD_TOP:
ret = cx23885_risc_buffer(dev->pci, &buf->risc,
sgt->sgl, 0, UNSET,
buf->bpl, 0, dev->height);
break;
case V4L2_FIELD_BOTTOM:
ret = cx23885_risc_buffer(dev->pci, &buf->risc,
sgt->sgl, UNSET, 0,
buf->bpl, 0, dev->height);
break;
case V4L2_FIELD_INTERLACED:
if (dev->tvnorm & V4L2_STD_525_60)
/* NTSC or */
field_tff = 1;
else
field_tff = 0;
if (cx23885_boards[dev->board].force_bff)
/* PAL / SECAM OR 888 in NTSC MODE */
field_tff = 0;
if (field_tff) {
/* cx25840 transmits NTSC bottom field first */
dprintk(1, "%s() Creating TFF/NTSC risc\n",
__func__);
line0_offset = buf->bpl;
line1_offset = 0;
} else {
/* All other formats are top field first */
dprintk(1, "%s() Creating BFF/PAL/SECAM risc\n",
__func__);
line0_offset = 0;
line1_offset = buf->bpl;
}
ret = cx23885_risc_buffer(dev->pci, &buf->risc,
sgt->sgl, line0_offset,
line1_offset,
buf->bpl, buf->bpl,
dev->height >> 1);
break;
case V4L2_FIELD_SEQ_TB:
ret = cx23885_risc_buffer(dev->pci, &buf->risc,
sgt->sgl,
0, buf->bpl * (dev->height >> 1),
buf->bpl, 0,
dev->height >> 1);
break;
case V4L2_FIELD_SEQ_BT:
ret = cx23885_risc_buffer(dev->pci, &buf->risc,
sgt->sgl,
buf->bpl * (dev->height >> 1), 0,
buf->bpl, 0,
dev->height >> 1);
break;
default:
return -EINVAL; /* should not happen */
}
dprintk(2, "[%p/%d] buffer_init - %dx%d %dbpp 0x%08x - dma=0x%08lx\n",
buf, buf->vb.vb2_buf.index,
dev->width, dev->height, dev->fmt->depth, dev->fmt->fourcc,
(unsigned long)buf->risc.dma);
return ret;
}
static void buffer_finish(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_buffer *buf = container_of(vbuf,
struct cx23885_buffer, vb);
cx23885_free_buffer(vb->vb2_queue->drv_priv, buf);
}
/*
* The risc program for each buffer works as follows: it starts with a simple
* 'JUMP to addr + 12', which is effectively a NOP. Then the code to DMA the
* buffer follows and at the end we have a JUMP back to the start + 12 (skipping
* the initial JUMP).
*
* This is the risc program of the first buffer to be queued if the active list
* is empty and it just keeps DMAing this buffer without generating any
* interrupts.
*
* If a new buffer is added then the initial JUMP in the code for that buffer
* will generate an interrupt which signals that the previous buffer has been
* DMAed successfully and that it can be returned to userspace.
*
* It also sets the final jump of the previous buffer to the start of the new
* buffer, thus chaining the new buffer into the DMA chain. This is a single
* atomic u32 write, so there is no race condition.
*
* The end-result of all this that you only get an interrupt when a buffer
* is ready, so the control flow is very easy.
*/
static void buffer_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
struct cx23885_buffer *buf = container_of(vbuf,
struct cx23885_buffer, vb);
struct cx23885_buffer *prev;
struct cx23885_dmaqueue *q = &dev->vidq;
unsigned long flags;
/* add jump to start */
buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12);
buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12);
buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
spin_lock_irqsave(&dev->slock, flags);
if (list_empty(&q->active)) {
list_add_tail(&buf->queue, &q->active);
dprintk(2, "[%p/%d] buffer_queue - first active\n",
buf, buf->vb.vb2_buf.index);
} else {
buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
prev = list_entry(q->active.prev, struct cx23885_buffer,
queue);
list_add_tail(&buf->queue, &q->active);
prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
dprintk(2, "[%p/%d] buffer_queue - append to active\n",
buf, buf->vb.vb2_buf.index);
}
spin_unlock_irqrestore(&dev->slock, flags);
}
static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
{
struct cx23885_dev *dev = q->drv_priv;
struct cx23885_dmaqueue *dmaq = &dev->vidq;
struct cx23885_buffer *buf = list_entry(dmaq->active.next,
struct cx23885_buffer, queue);
cx23885_start_video_dma(dev, dmaq, buf);
return 0;
}
static void cx23885_stop_streaming(struct vb2_queue *q)
{
struct cx23885_dev *dev = q->drv_priv;
struct cx23885_dmaqueue *dmaq = &dev->vidq;
unsigned long flags;
cx_clear(VID_A_DMA_CTL, 0x11);
spin_lock_irqsave(&dev->slock, flags);
while (!list_empty(&dmaq->active)) {
struct cx23885_buffer *buf = list_entry(dmaq->active.next,
struct cx23885_buffer, queue);
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&dev->slock, flags);
}
static const struct vb2_ops cx23885_video_qops = {
.queue_setup = queue_setup,
.buf_prepare = buffer_prepare,
.buf_finish = buffer_finish,
.buf_queue = buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = cx23885_start_streaming,
.stop_streaming = cx23885_stop_streaming,
};
/* ------------------------------------------------------------------ */
/* VIDEO IOCTLS */
static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx23885_dev *dev = video_drvdata(file);
f->fmt.pix.width = dev->width;
f->fmt.pix.height = dev->height;
f->fmt.pix.field = dev->field;
f->fmt.pix.pixelformat = dev->fmt->fourcc;
f->fmt.pix.bytesperline =
(f->fmt.pix.width * dev->fmt->depth) >> 3;
f->fmt.pix.sizeimage =
f->fmt.pix.height * f->fmt.pix.bytesperline;
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
return 0;
}
static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx23885_dev *dev = video_drvdata(file);
struct cx23885_fmt *fmt;
enum v4l2_field field;
unsigned int maxw, maxh;
fmt = format_by_fourcc(f->fmt.pix.pixelformat);
if (NULL == fmt)
return -EINVAL;
field = f->fmt.pix.field;
maxw = 720;
maxh = norm_maxh(dev->tvnorm);
if (V4L2_FIELD_ANY == field) {
field = (f->fmt.pix.height > maxh/2)
? V4L2_FIELD_INTERLACED
: V4L2_FIELD_BOTTOM;
}
switch (field) {
case V4L2_FIELD_TOP:
case V4L2_FIELD_BOTTOM:
maxh = maxh / 2;
break;
case V4L2_FIELD_INTERLACED:
case V4L2_FIELD_SEQ_TB:
case V4L2_FIELD_SEQ_BT:
break;
default:
field = V4L2_FIELD_INTERLACED;
break;
}
f->fmt.pix.field = field;
v4l_bound_align_image(&f->fmt.pix.width, 48, maxw, 2,
&f->fmt.pix.height, 32, maxh, 0, 0);
f->fmt.pix.bytesperline =
(f->fmt.pix.width * fmt->depth) >> 3;
f->fmt.pix.sizeimage =
f->fmt.pix.height * f->fmt.pix.bytesperline;
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
return 0;
}
static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx23885_dev *dev = video_drvdata(file);
struct v4l2_subdev_format format = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
int err;
dprintk(2, "%s()\n", __func__);
err = vidioc_try_fmt_vid_cap(file, priv, f);
if (0 != err)
return err;
if (vb2_is_busy(&dev->vb2_vidq) || vb2_is_busy(&dev->vb2_vbiq) ||
vb2_is_busy(&dev->vb2_mpegq))
return -EBUSY;
dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
dev->width = f->fmt.pix.width;
dev->height = f->fmt.pix.height;
dev->field = f->fmt.pix.field;
dprintk(2, "%s() width=%d height=%d field=%d\n", __func__,
dev->width, dev->height, dev->field);
v4l2_fill_mbus_format(&format.format, &f->fmt.pix, MEDIA_BUS_FMT_FIXED);
call_all(dev, pad, set_fmt, NULL, &format);
v4l2_fill_pix_format(&f->fmt.pix, &format.format);
/* set_fmt overwrites f->fmt.pix.field, restore it */
f->fmt.pix.field = dev->field;
return 0;
}
static int vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
struct cx23885_dev *dev = video_drvdata(file);
strscpy(cap->driver, "cx23885", sizeof(cap->driver));
strscpy(cap->card, cx23885_boards[dev->board].name,
sizeof(cap->card));
sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci));
cap->capabilities = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
V4L2_CAP_AUDIO | V4L2_CAP_VBI_CAPTURE |
V4L2_CAP_VIDEO_CAPTURE |
V4L2_CAP_DEVICE_CAPS;
switch (dev->board) { /* i2c device tuners */
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
cap->capabilities |= V4L2_CAP_TUNER;
break;
default:
if (dev->tuner_type != TUNER_ABSENT)
cap->capabilities |= V4L2_CAP_TUNER;
break;
}
return 0;
}
static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
if (unlikely(f->index >= ARRAY_SIZE(formats)))
return -EINVAL;
f->pixelformat = formats[f->index].fourcc;
return 0;
}
static int vidioc_g_pixelaspect(struct file *file, void *priv,
int type, struct v4l2_fract *f)
{
struct cx23885_dev *dev = video_drvdata(file);
bool is_50hz = dev->tvnorm & V4L2_STD_625_50;
if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
f->numerator = is_50hz ? 54 : 11;
f->denominator = is_50hz ? 59 : 10;
return 0;
}
static int vidioc_g_selection(struct file *file, void *fh,
struct v4l2_selection *sel)
{
struct cx23885_dev *dev = video_drvdata(file);
if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
switch (sel->target) {
case V4L2_SEL_TGT_CROP_BOUNDS:
case V4L2_SEL_TGT_CROP_DEFAULT:
sel->r.top = 0;
sel->r.left = 0;
sel->r.width = 720;
sel->r.height = norm_maxh(dev->tvnorm);
break;
default:
return -EINVAL;
}
return 0;
}
static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *id)
{
struct cx23885_dev *dev = video_drvdata(file);
dprintk(1, "%s()\n", __func__);
*id = dev->tvnorm;
return 0;
}
static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id tvnorms)
{
struct cx23885_dev *dev = video_drvdata(file);
dprintk(1, "%s()\n", __func__);
return cx23885_set_tvnorm(dev, tvnorms);
}
int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i)
{
static const char *iname[] = {
[CX23885_VMUX_COMPOSITE1] = "Composite1",
[CX23885_VMUX_COMPOSITE2] = "Composite2",
[CX23885_VMUX_COMPOSITE3] = "Composite3",
[CX23885_VMUX_COMPOSITE4] = "Composite4",
[CX23885_VMUX_SVIDEO] = "S-Video",
[CX23885_VMUX_COMPONENT] = "Component",
[CX23885_VMUX_TELEVISION] = "Television",
[CX23885_VMUX_CABLE] = "Cable TV",
[CX23885_VMUX_DVB] = "DVB",
[CX23885_VMUX_DEBUG] = "for debug only",
};
unsigned int n;
dprintk(1, "%s()\n", __func__);
n = i->index;
if (n >= MAX_CX23885_INPUT)
return -EINVAL;
if (0 == INPUT(n)->type)
return -EINVAL;
i->index = n;
i->type = V4L2_INPUT_TYPE_CAMERA;
strscpy(i->name, iname[INPUT(n)->type], sizeof(i->name));
i->std = CX23885_NORMS;
if ((CX23885_VMUX_TELEVISION == INPUT(n)->type) ||
(CX23885_VMUX_CABLE == INPUT(n)->type)) {
i->type = V4L2_INPUT_TYPE_TUNER;
i->audioset = 4;
} else {
/* Two selectable audio inputs for non-tv inputs */
i->audioset = 3;
}
if (dev->input == n) {
/* enum'd input matches our configured input.
* Ask the video decoder to process the call
* and give it an oppertunity to update the
* status field.
*/
call_all(dev, video, g_input_status, &i->status);
}
return 0;
}
static int vidioc_enum_input(struct file *file, void *priv,
struct v4l2_input *i)
{
struct cx23885_dev *dev = video_drvdata(file);
dprintk(1, "%s()\n", __func__);
return cx23885_enum_input(dev, i);
}
int cx23885_get_input(struct file *file, void *priv, unsigned int *i)
{
struct cx23885_dev *dev = video_drvdata(file);
*i = dev->input;
dprintk(1, "%s() returns %d\n", __func__, *i);
return 0;
}
static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
{
return cx23885_get_input(file, priv, i);
}
int cx23885_set_input(struct file *file, void *priv, unsigned int i)
{
struct cx23885_dev *dev = video_drvdata(file);
dprintk(1, "%s(%d)\n", __func__, i);
if (i >= MAX_CX23885_INPUT) {
dprintk(1, "%s() -EINVAL\n", __func__);
return -EINVAL;
}
if (INPUT(i)->type == 0)
return -EINVAL;
cx23885_video_mux(dev, i);
/* By default establish the default audio input for the card also */
/* Caller is free to use VIDIOC_S_AUDIO to override afterwards */
cx23885_audio_mux(dev, i);
return 0;
}
static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
{
return cx23885_set_input(file, priv, i);
}
static int vidioc_log_status(struct file *file, void *priv)
{
struct cx23885_dev *dev = video_drvdata(file);
call_all(dev, core, log_status);
return 0;
}
static int cx23885_query_audinput(struct file *file, void *priv,
struct v4l2_audio *i)
{
static const char *iname[] = {
[0] = "Baseband L/R 1",
[1] = "Baseband L/R 2",
[2] = "TV",
};
unsigned int n;
dprintk(1, "%s()\n", __func__);
n = i->index;
if (n >= 3)
return -EINVAL;
memset(i, 0, sizeof(*i));
i->index = n;
strscpy(i->name, iname[n], sizeof(i->name));
i->capability = V4L2_AUDCAP_STEREO;
return 0;
}
static int vidioc_enum_audinput(struct file *file, void *priv,
struct v4l2_audio *i)
{
return cx23885_query_audinput(file, priv, i);
}
static int vidioc_g_audinput(struct file *file, void *priv,
struct v4l2_audio *i)
{
struct cx23885_dev *dev = video_drvdata(file);
if ((CX23885_VMUX_TELEVISION == INPUT(dev->input)->type) ||
(CX23885_VMUX_CABLE == INPUT(dev->input)->type))
i->index = 2;
else
i->index = dev->audinput;
dprintk(1, "%s(input=%d)\n", __func__, i->index);
return cx23885_query_audinput(file, priv, i);
}
static int vidioc_s_audinput(struct file *file, void *priv,
const struct v4l2_audio *i)
{
struct cx23885_dev *dev = video_drvdata(file);
if ((CX23885_VMUX_TELEVISION == INPUT(dev->input)->type) ||
(CX23885_VMUX_CABLE == INPUT(dev->input)->type)) {
return i->index != 2 ? -EINVAL : 0;
}
if (i->index > 1)
return -EINVAL;
dprintk(1, "%s(%d)\n", __func__, i->index);
dev->audinput = i->index;
/* Skip the audio defaults from the cards struct, caller wants
* directly touch the audio mux hardware. */
cx23885_flatiron_mux(dev, dev->audinput + 1);
return 0;
}
static int vidioc_g_tuner(struct file *file, void *priv,
struct v4l2_tuner *t)
{
struct cx23885_dev *dev = video_drvdata(file);
switch (dev->board) { /* i2c device tuners */
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
break;
default:
if (dev->tuner_type == TUNER_ABSENT)
return -EINVAL;
break;
}
if (0 != t->index)
return -EINVAL;
strscpy(t->name, "Television", sizeof(t->name));
call_all(dev, tuner, g_tuner, t);
return 0;
}
static int vidioc_s_tuner(struct file *file, void *priv,
const struct v4l2_tuner *t)
{
struct cx23885_dev *dev = video_drvdata(file);
switch (dev->board) { /* i2c device tuners */
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
break;
default:
if (dev->tuner_type == TUNER_ABSENT)
return -EINVAL;
break;
}
if (0 != t->index)
return -EINVAL;
/* Update the A/V core */
call_all(dev, tuner, s_tuner, t);
return 0;
}
static int vidioc_g_frequency(struct file *file, void *priv,
struct v4l2_frequency *f)
{
struct cx23885_dev *dev = video_drvdata(file);
switch (dev->board) { /* i2c device tuners */
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
break;
default:
if (dev->tuner_type == TUNER_ABSENT)
return -EINVAL;
break;
}
f->type = V4L2_TUNER_ANALOG_TV;
f->frequency = dev->freq;
call_all(dev, tuner, g_frequency, f);
return 0;
}
static int cx23885_set_freq(struct cx23885_dev *dev, const struct v4l2_frequency *f)
{
struct v4l2_ctrl *mute;
int old_mute_val = 1;
switch (dev->board) { /* i2c device tuners */
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
break;
default:
if (dev->tuner_type == TUNER_ABSENT)
return -EINVAL;
break;
}
if (unlikely(f->tuner != 0))
return -EINVAL;
dev->freq = f->frequency;
/* I need to mute audio here */
mute = v4l2_ctrl_find(&dev->ctrl_handler, V4L2_CID_AUDIO_MUTE);
if (mute) {
old_mute_val = v4l2_ctrl_g_ctrl(mute);
if (!old_mute_val)
v4l2_ctrl_s_ctrl(mute, 1);
}
call_all(dev, tuner, s_frequency, f);
/* When changing channels it is required to reset TVAUDIO */
msleep(100);
/* I need to unmute audio here */
if (old_mute_val == 0)
v4l2_ctrl_s_ctrl(mute, old_mute_val);
return 0;
}
static int cx23885_set_freq_via_ops(struct cx23885_dev *dev,
const struct v4l2_frequency *f)
{
struct v4l2_ctrl *mute;
int old_mute_val = 1;
struct vb2_dvb_frontend *vfe;
struct dvb_frontend *fe;
struct analog_parameters params = {
.mode = V4L2_TUNER_ANALOG_TV,
.audmode = V4L2_TUNER_MODE_STEREO,
.std = dev->tvnorm,
.frequency = f->frequency
};
dev->freq = f->frequency;
/* I need to mute audio here */
mute = v4l2_ctrl_find(&dev->ctrl_handler, V4L2_CID_AUDIO_MUTE);
if (mute) {
old_mute_val = v4l2_ctrl_g_ctrl(mute);
if (!old_mute_val)
v4l2_ctrl_s_ctrl(mute, 1);
}
/* If HVR1850 */
dprintk(1, "%s() frequency=%d tuner=%d std=0x%llx\n", __func__,
params.frequency, f->tuner, params.std);
vfe = vb2_dvb_get_frontend(&dev->ts2.frontends, 1);
if (!vfe) {
return -EINVAL;
}
fe = vfe->dvb.frontend;
if ((dev->board == CX23885_BOARD_HAUPPAUGE_HVR1850) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255_22111) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1265_K4) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR5525) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_DVB) ||
(dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC))
fe = &dev->ts1.analog_fe;
if (fe && fe->ops.tuner_ops.set_analog_params) {
call_all(dev, video, s_std, dev->tvnorm);
fe->ops.tuner_ops.set_analog_params(fe, ¶ms);
}
else
pr_err("%s() No analog tuner, aborting\n", __func__);
/* When changing channels it is required to reset TVAUDIO */
msleep(100);
/* I need to unmute audio here */
if (old_mute_val == 0)
v4l2_ctrl_s_ctrl(mute, old_mute_val);
return 0;
}
int cx23885_set_frequency(struct file *file, void *priv,
const struct v4l2_frequency *f)
{
struct cx23885_dev *dev = video_drvdata(file);
int ret;
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1255:
case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_HVR1850:
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
ret = cx23885_set_freq_via_ops(dev, f);
break;
default:
ret = cx23885_set_freq(dev, f);
}
return ret;
}
static int vidioc_s_frequency(struct file *file, void *priv,
const struct v4l2_frequency *f)
{
return cx23885_set_frequency(file, priv, f);
}
/* ----------------------------------------------------------- */
int cx23885_video_irq(struct cx23885_dev *dev, u32 status)
{
u32 mask, count;
int handled = 0;
mask = cx_read(VID_A_INT_MSK);
if (0 == (status & mask))
return handled;
cx_write(VID_A_INT_STAT, status);
/* risc op code error, fifo overflow or line sync detection error */
if ((status & VID_BC_MSK_OPC_ERR) ||
(status & VID_BC_MSK_SYNC) ||
(status & VID_BC_MSK_OF)) {
if (status & VID_BC_MSK_OPC_ERR) {
dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
VID_BC_MSK_OPC_ERR);
pr_warn("%s: video risc op code error\n",
dev->name);
cx23885_sram_channel_dump(dev,
&dev->sram_channels[SRAM_CH01]);
}
if (status & VID_BC_MSK_SYNC)
dprintk(7, " (VID_BC_MSK_SYNC 0x%08x) video lines miss-match\n",
VID_BC_MSK_SYNC);
if (status & VID_BC_MSK_OF)
dprintk(7, " (VID_BC_MSK_OF 0x%08x) fifo overflow\n",
VID_BC_MSK_OF);
}
/* Video */
if (status & VID_BC_MSK_RISCI1) {
spin_lock(&dev->slock);
count = cx_read(VID_A_GPCNT);
cx23885_video_wakeup(dev, &dev->vidq, count);
spin_unlock(&dev->slock);
handled++;
}
/* Allow the VBI framework to process it's payload */
handled += cx23885_vbi_irq(dev, status);
return handled;
}
/* ----------------------------------------------------------- */
/* exported stuff */
static const struct v4l2_file_operations video_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.release = vb2_fop_release,
.read = vb2_fop_read,
.poll = vb2_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = vb2_fop_mmap,
};
static const struct v4l2_ioctl_ops video_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
.vidioc_g_fmt_vbi_cap = cx23885_vbi_fmt,
.vidioc_try_fmt_vbi_cap = cx23885_vbi_fmt,
.vidioc_s_fmt_vbi_cap = cx23885_vbi_fmt,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_g_pixelaspect = vidioc_g_pixelaspect,
.vidioc_g_selection = vidioc_g_selection,
.vidioc_s_std = vidioc_s_std,
.vidioc_g_std = vidioc_g_std,
.vidioc_enum_input = vidioc_enum_input,
.vidioc_g_input = vidioc_g_input,
.vidioc_s_input = vidioc_s_input,
.vidioc_log_status = vidioc_log_status,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_g_frequency = vidioc_g_frequency,
.vidioc_s_frequency = vidioc_s_frequency,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.vidioc_g_chip_info = cx23885_g_chip_info,
.vidioc_g_register = cx23885_g_register,
.vidioc_s_register = cx23885_s_register,
#endif
.vidioc_enumaudio = vidioc_enum_audinput,
.vidioc_g_audio = vidioc_g_audinput,
.vidioc_s_audio = vidioc_s_audinput,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
static struct video_device cx23885_vbi_template;
static struct video_device cx23885_video_template = {
.name = "cx23885-video",
.fops = &video_fops,
.ioctl_ops = &video_ioctl_ops,
.tvnorms = CX23885_NORMS,
};
void cx23885_video_unregister(struct cx23885_dev *dev)
{
dprintk(1, "%s()\n", __func__);
cx23885_irq_remove(dev, 0x01);
if (dev->vbi_dev) {
if (video_is_registered(dev->vbi_dev))
video_unregister_device(dev->vbi_dev);
else
video_device_release(dev->vbi_dev);
dev->vbi_dev = NULL;
}
if (dev->video_dev) {
if (video_is_registered(dev->video_dev))
video_unregister_device(dev->video_dev);
else
video_device_release(dev->video_dev);
dev->video_dev = NULL;
}
if (dev->audio_dev)
cx23885_audio_unregister(dev);
}
int cx23885_video_register(struct cx23885_dev *dev)
{
struct vb2_queue *q;
int err;
dprintk(1, "%s()\n", __func__);
/* Initialize VBI template */
cx23885_vbi_template = cx23885_video_template;
strscpy(cx23885_vbi_template.name, "cx23885-vbi",
sizeof(cx23885_vbi_template.name));
dev->tvnorm = V4L2_STD_NTSC_M;
dev->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV);
dev->field = V4L2_FIELD_INTERLACED;
dev->width = 720;
dev->height = norm_maxh(dev->tvnorm);
/* init video dma queues */
INIT_LIST_HEAD(&dev->vidq.active);
/* init vbi dma queues */
INIT_LIST_HEAD(&dev->vbiq.active);
cx23885_irq_add_enable(dev, 0x01);
if ((TUNER_ABSENT != dev->tuner_type) &&
((dev->tuner_bus == 0) || (dev->tuner_bus == 1))) {
struct v4l2_subdev *sd = NULL;
if (dev->tuner_addr)
sd = v4l2_i2c_new_subdev(&dev->v4l2_dev,
&dev->i2c_bus[dev->tuner_bus].i2c_adap,
"tuner", dev->tuner_addr, NULL);
else
sd = v4l2_i2c_new_subdev(&dev->v4l2_dev,
&dev->i2c_bus[dev->tuner_bus].i2c_adap,
"tuner", 0, v4l2_i2c_tuner_addrs(ADDRS_TV));
if (sd) {
struct tuner_setup tun_setup;
memset(&tun_setup, 0, sizeof(tun_setup));
tun_setup.mode_mask = T_ANALOG_TV;
tun_setup.type = dev->tuner_type;
tun_setup.addr = v4l2_i2c_subdev_addr(sd);
tun_setup.tuner_callback = cx23885_tuner_callback;
v4l2_subdev_call(sd, tuner, s_type_addr, &tun_setup);
if ((dev->board == CX23885_BOARD_LEADTEK_WINFAST_PXTV1200) ||
(dev->board == CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200)) {
struct xc2028_ctrl ctrl = {
.fname = XC2028_DEFAULT_FIRMWARE,
.max_len = 64
};
struct v4l2_priv_tun_config cfg = {
.tuner = dev->tuner_type,
.priv = &ctrl
};
v4l2_subdev_call(sd, tuner, s_config, &cfg);
}
if (dev->board == CX23885_BOARD_AVERMEDIA_HC81R) {
struct xc2028_ctrl ctrl = {
.fname = "xc3028L-v36.fw",
.max_len = 64
};
struct v4l2_priv_tun_config cfg = {
.tuner = dev->tuner_type,
.priv = &ctrl
};
v4l2_subdev_call(sd, tuner, s_config, &cfg);
}
}
}
/* initial device configuration */
mutex_lock(&dev->lock);
cx23885_set_tvnorm(dev, dev->tvnorm);
cx23885_video_mux(dev, 0);
cx23885_audio_mux(dev, 0);
mutex_unlock(&dev->lock);
q = &dev->vb2_vidq;
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
q->gfp_flags = GFP_DMA32;
q->min_buffers_needed = 2;
q->drv_priv = dev;
q->buf_struct_size = sizeof(struct cx23885_buffer);
q->ops = &cx23885_video_qops;
q->mem_ops = &vb2_dma_sg_memops;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &dev->lock;
q->dev = &dev->pci->dev;
err = vb2_queue_init(q);
if (err < 0)
goto fail_unreg;
q = &dev->vb2_vbiq;
q->type = V4L2_BUF_TYPE_VBI_CAPTURE;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
q->gfp_flags = GFP_DMA32;
q->min_buffers_needed = 2;
q->drv_priv = dev;
q->buf_struct_size = sizeof(struct cx23885_buffer);
q->ops = &cx23885_vbi_qops;
q->mem_ops = &vb2_dma_sg_memops;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &dev->lock;
q->dev = &dev->pci->dev;
err = vb2_queue_init(q);
if (err < 0)
goto fail_unreg;
/* register Video device */
dev->video_dev = cx23885_vdev_init(dev, dev->pci,
&cx23885_video_template, "video");
dev->video_dev->queue = &dev->vb2_vidq;
dev->video_dev->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
V4L2_CAP_AUDIO | V4L2_CAP_VIDEO_CAPTURE;
switch (dev->board) { /* i2c device tuners */
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
dev->video_dev->device_caps |= V4L2_CAP_TUNER;
break;
default:
if (dev->tuner_type != TUNER_ABSENT)
dev->video_dev->device_caps |= V4L2_CAP_TUNER;
}
err = video_register_device(dev->video_dev, VFL_TYPE_VIDEO,
video_nr[dev->nr]);
if (err < 0) {
pr_info("%s: can't register video device\n",
dev->name);
goto fail_unreg;
}
pr_info("%s: registered device %s [v4l2]\n",
dev->name, video_device_node_name(dev->video_dev));
/* register VBI device */
dev->vbi_dev = cx23885_vdev_init(dev, dev->pci,
&cx23885_vbi_template, "vbi");
dev->vbi_dev->queue = &dev->vb2_vbiq;
dev->vbi_dev->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
V4L2_CAP_AUDIO | V4L2_CAP_VBI_CAPTURE;
switch (dev->board) { /* i2c device tuners */
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
case CX23885_BOARD_HAUPPAUGE_HVR5525:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
dev->vbi_dev->device_caps |= V4L2_CAP_TUNER;
break;
default:
if (dev->tuner_type != TUNER_ABSENT)
dev->vbi_dev->device_caps |= V4L2_CAP_TUNER;
}
err = video_register_device(dev->vbi_dev, VFL_TYPE_VBI,
vbi_nr[dev->nr]);
if (err < 0) {
pr_info("%s: can't register vbi device\n",
dev->name);
goto fail_unreg;
}
pr_info("%s: registered device %s\n",
dev->name, video_device_node_name(dev->vbi_dev));
/* Register ALSA audio device */
dev->audio_dev = cx23885_audio_register(dev);
return 0;
fail_unreg:
cx23885_video_unregister(dev);
return err;
}
| linux-master | drivers/media/pci/cx23885/cx23885-video.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* altera-ci.c
*
* CI driver in conjunction with NetUp Dual DVB-T/C RF CI card
*
* Copyright (C) 2010,2011 NetUP Inc.
* Copyright (C) 2010,2011 Igor M. Liplianin <[email protected]>
*/
/*
* currently cx23885 GPIO's used.
* GPIO-0 ~INT in
* GPIO-1 TMS out
* GPIO-2 ~reset chips out
* GPIO-3 to GPIO-10 data/addr for CA in/out
* GPIO-11 ~CS out
* GPIO-12 AD_RG out
* GPIO-13 ~WR out
* GPIO-14 ~RD out
* GPIO-15 ~RDY in
* GPIO-16 TCK out
* GPIO-17 TDO in
* GPIO-18 TDI out
*/
/*
* Bit definitions for MC417_RWD and MC417_OEN registers
* bits 31-16
* +-----------+
* | Reserved |
* +-----------+
* bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
* +-------+-------+-------+-------+-------+-------+-------+-------+
* | TDI | TDO | TCK | RDY# | #RD | #WR | AD_RG | #CS |
* +-------+-------+-------+-------+-------+-------+-------+-------+
* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
* +-------+-------+-------+-------+-------+-------+-------+-------+
* | DATA7| DATA6| DATA5| DATA4| DATA3| DATA2| DATA1| DATA0|
* +-------+-------+-------+-------+-------+-------+-------+-------+
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <media/dvb_demux.h>
#include <media/dvb_frontend.h>
#include "altera-ci.h"
#include <media/dvb_ca_en50221.h>
/* FPGA regs */
#define NETUP_CI_INT_CTRL 0x00
#define NETUP_CI_BUSCTRL2 0x01
#define NETUP_CI_ADDR0 0x04
#define NETUP_CI_ADDR1 0x05
#define NETUP_CI_DATA 0x06
#define NETUP_CI_BUSCTRL 0x07
#define NETUP_CI_PID_ADDR0 0x08
#define NETUP_CI_PID_ADDR1 0x09
#define NETUP_CI_PID_DATA 0x0a
#define NETUP_CI_TSA_DIV 0x0c
#define NETUP_CI_TSB_DIV 0x0d
#define NETUP_CI_REVISION 0x0f
/* const for ci op */
#define NETUP_CI_FLG_CTL 1
#define NETUP_CI_FLG_RD 1
#define NETUP_CI_FLG_AD 1
static unsigned int ci_dbg;
module_param(ci_dbg, int, 0644);
MODULE_PARM_DESC(ci_dbg, "Enable CI debugging");
static unsigned int pid_dbg;
module_param(pid_dbg, int, 0644);
MODULE_PARM_DESC(pid_dbg, "Enable PID filtering debugging");
MODULE_DESCRIPTION("altera FPGA CI module");
MODULE_AUTHOR("Igor M. Liplianin <[email protected]>");
MODULE_LICENSE("GPL");
#define ci_dbg_print(fmt, args...) \
do { \
if (ci_dbg) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##args); \
} while (0)
#define pid_dbg_print(fmt, args...) \
do { \
if (pid_dbg) \
printk(KERN_DEBUG pr_fmt("%s: " fmt), \
__func__, ##args); \
} while (0)
struct altera_ci_state;
struct netup_hw_pid_filter;
struct fpga_internal {
void *dev;
struct mutex fpga_mutex;/* two CI's on the same fpga */
struct netup_hw_pid_filter *pid_filt[2];
struct altera_ci_state *state[2];
struct work_struct work;
int (*fpga_rw) (void *dev, int flag, int data, int rw);
int cis_used;
int filts_used;
int strt_wrk;
};
/* stores all private variables for communication with CI */
struct altera_ci_state {
struct fpga_internal *internal;
struct dvb_ca_en50221 ca;
int status;
int nr;
};
/* stores all private variables for hardware pid filtering */
struct netup_hw_pid_filter {
struct fpga_internal *internal;
struct dvb_demux *demux;
/* save old functions */
int (*start_feed)(struct dvb_demux_feed *feed);
int (*stop_feed)(struct dvb_demux_feed *feed);
int status;
int nr;
};
/* internal params node */
struct fpga_inode {
/* pointer for internal params, one for each pair of CI's */
struct fpga_internal *internal;
struct fpga_inode *next_inode;
};
/* first internal params */
static struct fpga_inode *fpga_first_inode;
/* find chip by dev */
static struct fpga_inode *find_inode(void *dev)
{
struct fpga_inode *temp_chip = fpga_first_inode;
if (temp_chip == NULL)
return temp_chip;
/*
Search for the last fpga CI chip or
find it by dev */
while ((temp_chip != NULL) &&
(temp_chip->internal->dev != dev))
temp_chip = temp_chip->next_inode;
return temp_chip;
}
/* check demux */
static struct fpga_internal *check_filter(struct fpga_internal *temp_int,
void *demux_dev, int filt_nr)
{
if (temp_int == NULL)
return NULL;
if ((temp_int->pid_filt[filt_nr]) == NULL)
return NULL;
if (temp_int->pid_filt[filt_nr]->demux == demux_dev)
return temp_int;
return NULL;
}
/* find chip by demux */
static struct fpga_inode *find_dinode(void *demux_dev)
{
struct fpga_inode *temp_chip = fpga_first_inode;
struct fpga_internal *temp_int;
/*
* Search of the last fpga CI chip or
* find it by demux
*/
while (temp_chip != NULL) {
if (temp_chip->internal != NULL) {
temp_int = temp_chip->internal;
if (check_filter(temp_int, demux_dev, 0))
break;
if (check_filter(temp_int, demux_dev, 1))
break;
}
temp_chip = temp_chip->next_inode;
}
return temp_chip;
}
/* deallocating chip */
static void remove_inode(struct fpga_internal *internal)
{
struct fpga_inode *prev_node = fpga_first_inode;
struct fpga_inode *del_node = find_inode(internal->dev);
if (del_node != NULL) {
if (del_node == fpga_first_inode) {
fpga_first_inode = del_node->next_inode;
} else {
while (prev_node->next_inode != del_node)
prev_node = prev_node->next_inode;
if (del_node->next_inode == NULL)
prev_node->next_inode = NULL;
else
prev_node->next_inode =
prev_node->next_inode->next_inode;
}
kfree(del_node);
}
}
/* allocating new chip */
static struct fpga_inode *append_internal(struct fpga_internal *internal)
{
struct fpga_inode *new_node = fpga_first_inode;
if (new_node == NULL) {
new_node = kmalloc(sizeof(struct fpga_inode), GFP_KERNEL);
fpga_first_inode = new_node;
} else {
while (new_node->next_inode != NULL)
new_node = new_node->next_inode;
new_node->next_inode =
kmalloc(sizeof(struct fpga_inode), GFP_KERNEL);
if (new_node->next_inode != NULL)
new_node = new_node->next_inode;
else
new_node = NULL;
}
if (new_node != NULL) {
new_node->internal = internal;
new_node->next_inode = NULL;
}
return new_node;
}
static int netup_fpga_op_rw(struct fpga_internal *inter, int addr,
u8 val, u8 read)
{
inter->fpga_rw(inter->dev, NETUP_CI_FLG_AD, addr, 0);
return inter->fpga_rw(inter->dev, 0, val, read);
}
/* flag - mem/io, read - read/write */
static int altera_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
u8 flag, u8 read, int addr, u8 val)
{
struct altera_ci_state *state = en50221->data;
struct fpga_internal *inter = state->internal;
u8 store;
int mem = 0;
if (0 != slot)
return -EINVAL;
mutex_lock(&inter->fpga_mutex);
netup_fpga_op_rw(inter, NETUP_CI_ADDR0, ((addr << 1) & 0xfe), 0);
netup_fpga_op_rw(inter, NETUP_CI_ADDR1, ((addr >> 7) & 0x7f), 0);
store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
store &= 0x0f;
store |= ((state->nr << 7) | (flag << 6));
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, store, 0);
mem = netup_fpga_op_rw(inter, NETUP_CI_DATA, val, read);
mutex_unlock(&inter->fpga_mutex);
ci_dbg_print("%s: %s: addr=[0x%02x], %s=%x\n", __func__,
(read) ? "read" : "write", addr,
(flag == NETUP_CI_FLG_CTL) ? "ctl" : "mem",
(read) ? mem : val);
return mem;
}
static int altera_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
int slot, int addr)
{
return altera_ci_op_cam(en50221, slot, 0, NETUP_CI_FLG_RD, addr, 0);
}
static int altera_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
int slot, int addr, u8 data)
{
return altera_ci_op_cam(en50221, slot, 0, 0, addr, data);
}
static int altera_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221,
int slot, u8 addr)
{
return altera_ci_op_cam(en50221, slot, NETUP_CI_FLG_CTL,
NETUP_CI_FLG_RD, addr, 0);
}
static int altera_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
u8 addr, u8 data)
{
return altera_ci_op_cam(en50221, slot, NETUP_CI_FLG_CTL, 0, addr, data);
}
static int altera_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
{
struct altera_ci_state *state = en50221->data;
struct fpga_internal *inter = state->internal;
/* reasonable timeout for CI reset is 10 seconds */
unsigned long t_out = jiffies + msecs_to_jiffies(9999);
int ret;
ci_dbg_print("%s\n", __func__);
if (0 != slot)
return -EINVAL;
mutex_lock(&inter->fpga_mutex);
ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
(ret & 0xcf) | (1 << (5 - state->nr)), 0);
mutex_unlock(&inter->fpga_mutex);
for (;;) {
msleep(50);
mutex_lock(&inter->fpga_mutex);
ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
0, NETUP_CI_FLG_RD);
mutex_unlock(&inter->fpga_mutex);
if ((ret & (1 << (5 - state->nr))) == 0)
break;
if (time_after(jiffies, t_out))
break;
}
ci_dbg_print("%s: %d msecs\n", __func__,
jiffies_to_msecs(jiffies + msecs_to_jiffies(9999) - t_out));
return 0;
}
static int altera_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
{
/* not implemented */
return 0;
}
static int altera_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot)
{
struct altera_ci_state *state = en50221->data;
struct fpga_internal *inter = state->internal;
int ret;
ci_dbg_print("%s\n", __func__);
if (0 != slot)
return -EINVAL;
mutex_lock(&inter->fpga_mutex);
ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
(ret & 0x0f) | (1 << (3 - state->nr)), 0);
mutex_unlock(&inter->fpga_mutex);
return 0;
}
/* work handler */
static void netup_read_ci_status(struct work_struct *work)
{
struct fpga_internal *inter =
container_of(work, struct fpga_internal, work);
int ret;
ci_dbg_print("%s\n", __func__);
mutex_lock(&inter->fpga_mutex);
/* ack' irq */
ret = netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0, NETUP_CI_FLG_RD);
ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
mutex_unlock(&inter->fpga_mutex);
if (inter->state[1] != NULL) {
inter->state[1]->status =
((ret & 1) == 0 ?
DVB_CA_EN50221_POLL_CAM_PRESENT |
DVB_CA_EN50221_POLL_CAM_READY : 0);
ci_dbg_print("%s: setting CI[1] status = 0x%x\n",
__func__, inter->state[1]->status);
}
if (inter->state[0] != NULL) {
inter->state[0]->status =
((ret & 2) == 0 ?
DVB_CA_EN50221_POLL_CAM_PRESENT |
DVB_CA_EN50221_POLL_CAM_READY : 0);
ci_dbg_print("%s: setting CI[0] status = 0x%x\n",
__func__, inter->state[0]->status);
}
}
/* CI irq handler */
int altera_ci_irq(void *dev)
{
struct fpga_inode *temp_int = NULL;
struct fpga_internal *inter = NULL;
ci_dbg_print("%s\n", __func__);
if (dev != NULL) {
temp_int = find_inode(dev);
if (temp_int != NULL) {
inter = temp_int->internal;
schedule_work(&inter->work);
}
}
return 1;
}
EXPORT_SYMBOL(altera_ci_irq);
static int altera_poll_ci_slot_status(struct dvb_ca_en50221 *en50221,
int slot, int open)
{
struct altera_ci_state *state = en50221->data;
if (0 != slot)
return -EINVAL;
return state->status;
}
static void altera_hw_filt_release(void *main_dev, int filt_nr)
{
struct fpga_inode *temp_int = find_inode(main_dev);
struct netup_hw_pid_filter *pid_filt = NULL;
ci_dbg_print("%s\n", __func__);
if (temp_int != NULL) {
pid_filt = temp_int->internal->pid_filt[filt_nr - 1];
/* stored old feed controls */
pid_filt->demux->start_feed = pid_filt->start_feed;
pid_filt->demux->stop_feed = pid_filt->stop_feed;
if (((--(temp_int->internal->filts_used)) <= 0) &&
((temp_int->internal->cis_used) <= 0)) {
ci_dbg_print("%s: Actually removing\n", __func__);
remove_inode(temp_int->internal);
kfree(pid_filt->internal);
}
kfree(pid_filt);
}
}
void altera_ci_release(void *dev, int ci_nr)
{
struct fpga_inode *temp_int = find_inode(dev);
struct altera_ci_state *state = NULL;
ci_dbg_print("%s\n", __func__);
if (temp_int != NULL) {
state = temp_int->internal->state[ci_nr - 1];
altera_hw_filt_release(dev, ci_nr);
if (((temp_int->internal->filts_used) <= 0) &&
((--(temp_int->internal->cis_used)) <= 0)) {
ci_dbg_print("%s: Actually removing\n", __func__);
remove_inode(temp_int->internal);
kfree(state->internal);
}
if (state != NULL) {
if (state->ca.data != NULL)
dvb_ca_en50221_release(&state->ca);
kfree(state);
}
}
}
EXPORT_SYMBOL(altera_ci_release);
static void altera_pid_control(struct netup_hw_pid_filter *pid_filt,
u16 pid, int onoff)
{
struct fpga_internal *inter = pid_filt->internal;
u8 store = 0;
/* pid 0-0x1f always enabled, don't touch them */
if ((pid == 0x2000) || (pid < 0x20))
return;
mutex_lock(&inter->fpga_mutex);
netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, (pid >> 3) & 0xff, 0);
netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1,
((pid >> 11) & 0x03) | (pid_filt->nr << 2), 0);
store = netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, 0, NETUP_CI_FLG_RD);
if (onoff)/* 0 - on, 1 - off */
store |= (1 << (pid & 7));
else
store &= ~(1 << (pid & 7));
netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, store, 0);
mutex_unlock(&inter->fpga_mutex);
pid_dbg_print("%s: (%d) set pid: %5d 0x%04x '%s'\n", __func__,
pid_filt->nr, pid, pid, onoff ? "off" : "on");
}
static void altera_toggle_fullts_streaming(struct netup_hw_pid_filter *pid_filt,
int filt_nr, int onoff)
{
struct fpga_internal *inter = pid_filt->internal;
u8 store = 0;
int i;
pid_dbg_print("%s: pid_filt->nr[%d] now %s\n", __func__, pid_filt->nr,
onoff ? "off" : "on");
if (onoff)/* 0 - on, 1 - off */
store = 0xff;/* ignore pid */
else
store = 0;/* enable pid */
mutex_lock(&inter->fpga_mutex);
for (i = 0; i < 1024; i++) {
netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, i & 0xff, 0);
netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1,
((i >> 8) & 0x03) | (pid_filt->nr << 2), 0);
/* pid 0-0x1f always enabled */
netup_fpga_op_rw(inter, NETUP_CI_PID_DATA,
(i > 3 ? store : 0), 0);
}
mutex_unlock(&inter->fpga_mutex);
}
static int altera_pid_feed_control(void *demux_dev, int filt_nr,
struct dvb_demux_feed *feed, int onoff)
{
struct fpga_inode *temp_int = find_dinode(demux_dev);
struct fpga_internal *inter = temp_int->internal;
struct netup_hw_pid_filter *pid_filt = inter->pid_filt[filt_nr - 1];
altera_pid_control(pid_filt, feed->pid, onoff ? 0 : 1);
/* call old feed proc's */
if (onoff)
pid_filt->start_feed(feed);
else
pid_filt->stop_feed(feed);
if (feed->pid == 0x2000)
altera_toggle_fullts_streaming(pid_filt, filt_nr,
onoff ? 0 : 1);
return 0;
}
static int altera_ci_start_feed(struct dvb_demux_feed *feed, int num)
{
altera_pid_feed_control(feed->demux, num, feed, 1);
return 0;
}
static int altera_ci_stop_feed(struct dvb_demux_feed *feed, int num)
{
altera_pid_feed_control(feed->demux, num, feed, 0);
return 0;
}
static int altera_ci_start_feed_1(struct dvb_demux_feed *feed)
{
return altera_ci_start_feed(feed, 1);
}
static int altera_ci_stop_feed_1(struct dvb_demux_feed *feed)
{
return altera_ci_stop_feed(feed, 1);
}
static int altera_ci_start_feed_2(struct dvb_demux_feed *feed)
{
return altera_ci_start_feed(feed, 2);
}
static int altera_ci_stop_feed_2(struct dvb_demux_feed *feed)
{
return altera_ci_stop_feed(feed, 2);
}
static int altera_hw_filt_init(struct altera_ci_config *config, int hw_filt_nr)
{
struct netup_hw_pid_filter *pid_filt = NULL;
struct fpga_inode *temp_int = find_inode(config->dev);
struct fpga_internal *inter = NULL;
int ret = 0;
pid_filt = kzalloc(sizeof(struct netup_hw_pid_filter), GFP_KERNEL);
ci_dbg_print("%s\n", __func__);
if (!pid_filt) {
ret = -ENOMEM;
goto err;
}
if (temp_int != NULL) {
inter = temp_int->internal;
(inter->filts_used)++;
ci_dbg_print("%s: Find Internal Structure!\n", __func__);
} else {
inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL);
if (!inter) {
ret = -ENOMEM;
goto err;
}
temp_int = append_internal(inter);
if (!temp_int) {
ret = -ENOMEM;
goto err;
}
inter->filts_used = 1;
inter->dev = config->dev;
inter->fpga_rw = config->fpga_rw;
mutex_init(&inter->fpga_mutex);
inter->strt_wrk = 1;
ci_dbg_print("%s: Create New Internal Structure!\n", __func__);
}
ci_dbg_print("%s: setting hw pid filter = %p for ci = %d\n", __func__,
pid_filt, hw_filt_nr - 1);
inter->pid_filt[hw_filt_nr - 1] = pid_filt;
pid_filt->demux = config->demux;
pid_filt->internal = inter;
pid_filt->nr = hw_filt_nr - 1;
/* store old feed controls */
pid_filt->start_feed = config->demux->start_feed;
pid_filt->stop_feed = config->demux->stop_feed;
/* replace with new feed controls */
if (hw_filt_nr == 1) {
pid_filt->demux->start_feed = altera_ci_start_feed_1;
pid_filt->demux->stop_feed = altera_ci_stop_feed_1;
} else if (hw_filt_nr == 2) {
pid_filt->demux->start_feed = altera_ci_start_feed_2;
pid_filt->demux->stop_feed = altera_ci_stop_feed_2;
}
altera_toggle_fullts_streaming(pid_filt, 0, 1);
return 0;
err:
ci_dbg_print("%s: Can't init hardware filter: Error %d\n",
__func__, ret);
kfree(pid_filt);
kfree(inter);
return ret;
}
int altera_ci_init(struct altera_ci_config *config, int ci_nr)
{
struct altera_ci_state *state;
struct fpga_inode *temp_int = find_inode(config->dev);
struct fpga_internal *inter = NULL;
int ret = 0;
u8 store = 0;
state = kzalloc(sizeof(struct altera_ci_state), GFP_KERNEL);
ci_dbg_print("%s\n", __func__);
if (!state) {
ret = -ENOMEM;
goto err;
}
if (temp_int != NULL) {
inter = temp_int->internal;
(inter->cis_used)++;
inter->fpga_rw = config->fpga_rw;
ci_dbg_print("%s: Find Internal Structure!\n", __func__);
} else {
inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL);
if (!inter) {
ret = -ENOMEM;
goto err;
}
temp_int = append_internal(inter);
if (!temp_int) {
ret = -ENOMEM;
goto err;
}
inter->cis_used = 1;
inter->dev = config->dev;
inter->fpga_rw = config->fpga_rw;
mutex_init(&inter->fpga_mutex);
inter->strt_wrk = 1;
ci_dbg_print("%s: Create New Internal Structure!\n", __func__);
}
ci_dbg_print("%s: setting state = %p for ci = %d\n", __func__,
state, ci_nr - 1);
state->internal = inter;
state->nr = ci_nr - 1;
state->ca.owner = THIS_MODULE;
state->ca.read_attribute_mem = altera_ci_read_attribute_mem;
state->ca.write_attribute_mem = altera_ci_write_attribute_mem;
state->ca.read_cam_control = altera_ci_read_cam_ctl;
state->ca.write_cam_control = altera_ci_write_cam_ctl;
state->ca.slot_reset = altera_ci_slot_reset;
state->ca.slot_shutdown = altera_ci_slot_shutdown;
state->ca.slot_ts_enable = altera_ci_slot_ts_ctl;
state->ca.poll_slot_status = altera_poll_ci_slot_status;
state->ca.data = state;
ret = dvb_ca_en50221_init(config->adapter,
&state->ca,
/* flags */ 0,
/* n_slots */ 1);
if (0 != ret)
goto err;
inter->state[ci_nr - 1] = state;
altera_hw_filt_init(config, ci_nr);
if (inter->strt_wrk) {
INIT_WORK(&inter->work, netup_read_ci_status);
inter->strt_wrk = 0;
}
ci_dbg_print("%s: CI initialized!\n", __func__);
mutex_lock(&inter->fpga_mutex);
/* Enable div */
netup_fpga_op_rw(inter, NETUP_CI_TSA_DIV, 0x0, 0);
netup_fpga_op_rw(inter, NETUP_CI_TSB_DIV, 0x0, 0);
/* enable TS out */
store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD);
store |= (3 << 4);
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
ret = netup_fpga_op_rw(inter, NETUP_CI_REVISION, 0, NETUP_CI_FLG_RD);
/* enable irq */
netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0x44, 0);
mutex_unlock(&inter->fpga_mutex);
ci_dbg_print("%s: NetUP CI Revision = 0x%x\n", __func__, ret);
schedule_work(&inter->work);
return 0;
err:
ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret);
kfree(state);
kfree(inter);
return ret;
}
EXPORT_SYMBOL(altera_ci_init);
int altera_ci_tuner_reset(void *dev, int ci_nr)
{
struct fpga_inode *temp_int = find_inode(dev);
struct fpga_internal *inter = NULL;
u8 store;
ci_dbg_print("%s\n", __func__);
if (temp_int == NULL)
return -1;
if (temp_int->internal == NULL)
return -1;
inter = temp_int->internal;
mutex_lock(&inter->fpga_mutex);
store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD);
store &= ~(4 << (2 - ci_nr));
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
msleep(100);
store |= (4 << (2 - ci_nr));
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
mutex_unlock(&inter->fpga_mutex);
return 0;
}
EXPORT_SYMBOL(altera_ci_tuner_reset);
| linux-master | drivers/media/pci/cx23885/altera-ci.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* Support for a cx23417 mpeg encoder via cx23885 host port.
*
* (c) 2004 Jelle Foks <[email protected]>
* (c) 2004 Gerd Knorr <[email protected]>
* (c) 2008 Steven Toth <[email protected]>
* - CX23885/7/8 support
*
* Includes parts from the ivtv driver <http://sourceforge.net/projects/ivtv/>
*/
#include "cx23885.h"
#include "cx23885-ioctl.h"
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/slab.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/drv-intf/cx2341x.h>
#define CX23885_FIRM_IMAGE_SIZE 376836
#define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
static unsigned int mpegbufs = 32;
module_param(mpegbufs, int, 0644);
MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
static unsigned int mpeglines = 32;
module_param(mpeglines, int, 0644);
MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
static unsigned int mpeglinesize = 512;
module_param(mpeglinesize, int, 0644);
MODULE_PARM_DESC(mpeglinesize,
"number of bytes in each line of an MPEG buffer, range 512-1024");
static unsigned int v4l_debug;
module_param(v4l_debug, int, 0644);
MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
#define dprintk(level, fmt, arg...)\
do { if (v4l_debug >= level) \
printk(KERN_DEBUG pr_fmt("%s: 417:" fmt), \
__func__, ##arg); \
} while (0)
static struct cx23885_tvnorm cx23885_tvnorms[] = {
{
.name = "NTSC-M",
.id = V4L2_STD_NTSC_M,
}, {
.name = "NTSC-JP",
.id = V4L2_STD_NTSC_M_JP,
}, {
.name = "PAL-BG",
.id = V4L2_STD_PAL_BG,
}, {
.name = "PAL-DK",
.id = V4L2_STD_PAL_DK,
}, {
.name = "PAL-I",
.id = V4L2_STD_PAL_I,
}, {
.name = "PAL-M",
.id = V4L2_STD_PAL_M,
}, {
.name = "PAL-N",
.id = V4L2_STD_PAL_N,
}, {
.name = "PAL-Nc",
.id = V4L2_STD_PAL_Nc,
}, {
.name = "PAL-60",
.id = V4L2_STD_PAL_60,
}, {
.name = "SECAM-L",
.id = V4L2_STD_SECAM_L,
}, {
.name = "SECAM-DK",
.id = V4L2_STD_SECAM_DK,
}
};
/* ------------------------------------------------------------------ */
enum cx23885_capture_type {
CX23885_MPEG_CAPTURE,
CX23885_RAW_CAPTURE,
CX23885_RAW_PASSTHRU_CAPTURE
};
enum cx23885_capture_bits {
CX23885_RAW_BITS_NONE = 0x00,
CX23885_RAW_BITS_YUV_CAPTURE = 0x01,
CX23885_RAW_BITS_PCM_CAPTURE = 0x02,
CX23885_RAW_BITS_VBI_CAPTURE = 0x04,
CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
CX23885_RAW_BITS_TO_HOST_CAPTURE = 0x10
};
enum cx23885_capture_end {
CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */
CX23885_END_NOW, /* stop immediately, no irq */
};
enum cx23885_framerate {
CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */
CX23885_FRAMERATE_PAL_25 /* PAL: 25fps */
};
enum cx23885_stream_port {
CX23885_OUTPUT_PORT_MEMORY,
CX23885_OUTPUT_PORT_STREAMING,
CX23885_OUTPUT_PORT_SERIAL
};
enum cx23885_data_xfer_status {
CX23885_MORE_BUFFERS_FOLLOW,
CX23885_LAST_BUFFER,
};
enum cx23885_picture_mask {
CX23885_PICTURE_MASK_NONE,
CX23885_PICTURE_MASK_I_FRAMES,
CX23885_PICTURE_MASK_I_P_FRAMES = 0x3,
CX23885_PICTURE_MASK_ALL_FRAMES = 0x7,
};
enum cx23885_vbi_mode_bits {
CX23885_VBI_BITS_SLICED,
CX23885_VBI_BITS_RAW,
};
enum cx23885_vbi_insertion_bits {
CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
};
enum cx23885_dma_unit {
CX23885_DMA_BYTES,
CX23885_DMA_FRAMES,
};
enum cx23885_dma_transfer_status_bits {
CX23885_DMA_TRANSFER_BITS_DONE = 0x01,
CX23885_DMA_TRANSFER_BITS_ERROR = 0x04,
CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
};
enum cx23885_pause {
CX23885_PAUSE_ENCODING,
CX23885_RESUME_ENCODING,
};
enum cx23885_copyright {
CX23885_COPYRIGHT_OFF,
CX23885_COPYRIGHT_ON,
};
enum cx23885_notification_type {
CX23885_NOTIFICATION_REFRESH,
};
enum cx23885_notification_status {
CX23885_NOTIFICATION_OFF,
CX23885_NOTIFICATION_ON,
};
enum cx23885_notification_mailbox {
CX23885_NOTIFICATION_NO_MAILBOX = -1,
};
enum cx23885_field1_lines {
CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */
CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */
CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */
};
enum cx23885_field2_lines {
CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */
CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */
CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */
};
enum cx23885_custom_data_type {
CX23885_CUSTOM_EXTENSION_USR_DATA,
CX23885_CUSTOM_PRIVATE_PACKET,
};
enum cx23885_mute {
CX23885_UNMUTE,
CX23885_MUTE,
};
enum cx23885_mute_video_mask {
CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00,
CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000,
CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000,
};
enum cx23885_mute_video_shift {
CX23885_MUTE_VIDEO_V_SHIFT = 8,
CX23885_MUTE_VIDEO_U_SHIFT = 16,
CX23885_MUTE_VIDEO_Y_SHIFT = 24,
};
/* defines below are from ivtv-driver.h */
#define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
/* Firmware API commands */
#define IVTV_API_STD_TIMEOUT 500
/* Registers */
/* IVTV_REG_OFFSET */
#define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
#define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
#define IVTV_REG_SPU (0x9050)
#define IVTV_REG_HW_BLOCKS (0x9054)
#define IVTV_REG_VPU (0x9058)
#define IVTV_REG_APU (0xA064)
/**** Bit definitions for MC417_RWD and MC417_OEN registers ***
bits 31-16
+-----------+
| Reserved |
+-----------+
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
+-------+-------+-------+-------+-------+-------+-------+-------+
| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
+-------+-------+-------+-------+-------+-------+-------+-------+
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
+-------+-------+-------+-------+-------+-------+-------+-------+
|MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
+-------+-------+-------+-------+-------+-------+-------+-------+
***/
#define MC417_MIWR 0x8000
#define MC417_MIRD 0x4000
#define MC417_MICS 0x2000
#define MC417_MIRDY 0x1000
#define MC417_MIADDR 0x0F00
#define MC417_MIDATA 0x00FF
/* MIADDR* nibble definitions */
#define MCI_MEMORY_DATA_BYTE0 0x000
#define MCI_MEMORY_DATA_BYTE1 0x100
#define MCI_MEMORY_DATA_BYTE2 0x200
#define MCI_MEMORY_DATA_BYTE3 0x300
#define MCI_MEMORY_ADDRESS_BYTE2 0x400
#define MCI_MEMORY_ADDRESS_BYTE1 0x500
#define MCI_MEMORY_ADDRESS_BYTE0 0x600
#define MCI_REGISTER_DATA_BYTE0 0x800
#define MCI_REGISTER_DATA_BYTE1 0x900
#define MCI_REGISTER_DATA_BYTE2 0xA00
#define MCI_REGISTER_DATA_BYTE3 0xB00
#define MCI_REGISTER_ADDRESS_BYTE0 0xC00
#define MCI_REGISTER_ADDRESS_BYTE1 0xD00
#define MCI_REGISTER_MODE 0xE00
/* Read and write modes */
#define MCI_MODE_REGISTER_READ 0
#define MCI_MODE_REGISTER_WRITE 1
#define MCI_MODE_MEMORY_READ 0
#define MCI_MODE_MEMORY_WRITE 0x40
/*** Bit definitions for MC417_CTL register ****
bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
+--------+-------------+--------+--------------+------------+
|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
+--------+-------------+--------+--------------+------------+
***/
#define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
#define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
#define MC417_UART_GPIO_EN 0x00000001
/* Values for speed control */
#define MC417_SPD_CTL_SLOW 0x1
#define MC417_SPD_CTL_MEDIUM 0x0
#define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
/* Values for GPIO select */
#define MC417_GPIO_SEL_GPIO3 0x3
#define MC417_GPIO_SEL_GPIO2 0x2
#define MC417_GPIO_SEL_GPIO1 0x1
#define MC417_GPIO_SEL_GPIO0 0x0
void cx23885_mc417_init(struct cx23885_dev *dev)
{
u32 regval;
dprintk(2, "%s()\n", __func__);
/* Configure MC417_CTL register to defaults. */
regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) |
MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3) |
MC417_UART_GPIO_EN;
cx_write(MC417_CTL, regval);
/* Configure MC417_OEN to defaults. */
regval = MC417_MIRDY;
cx_write(MC417_OEN, regval);
/* Configure MC417_RWD to defaults. */
regval = MC417_MIWR | MC417_MIRD | MC417_MICS;
cx_write(MC417_RWD, regval);
}
static int mc417_wait_ready(struct cx23885_dev *dev)
{
u32 mi_ready;
unsigned long timeout = jiffies + msecs_to_jiffies(1);
for (;;) {
mi_ready = cx_read(MC417_RWD) & MC417_MIRDY;
if (mi_ready != 0)
return 0;
if (time_after(jiffies, timeout))
return -1;
udelay(1);
}
}
int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value)
{
u32 regval;
/* Enable MC417 GPIO outputs except for MC417_MIRDY,
* which is an input.
*/
cx_write(MC417_OEN, MC417_MIRDY);
/* Write data byte 0 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 |
(value & 0x000000FF);
cx_write(MC417_RWD, regval);
/* Transition CS/WR to effect write transaction across bus. */
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write data byte 1 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 |
((value >> 8) & 0x000000FF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write data byte 2 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 |
((value >> 16) & 0x000000FF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write data byte 3 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 |
((value >> 24) & 0x000000FF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write address byte 0 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
(address & 0xFF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write address byte 1 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
((address >> 8) & 0xFF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Indicate that this is a write. */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
MCI_MODE_REGISTER_WRITE;
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Wait for the trans to complete (MC417_MIRDY asserted). */
return mc417_wait_ready(dev);
}
int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value)
{
int retval;
u32 regval;
u32 tempval;
u32 dataval;
/* Enable MC417 GPIO outputs except for MC417_MIRDY,
* which is an input.
*/
cx_write(MC417_OEN, MC417_MIRDY);
/* Write address byte 0 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
((address & 0x00FF));
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write address byte 1 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
((address >> 8) & 0xFF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Indicate that this is a register read. */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
MCI_MODE_REGISTER_READ;
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Wait for the trans to complete (MC417_MIRDY asserted). */
retval = mc417_wait_ready(dev);
/* switch the DAT0-7 GPIO[10:3] to input mode */
cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
/* Read data byte 0 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
cx_write(MC417_RWD, regval);
/* Transition RD to effect read transaction across bus.
* Transition 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)?
* Should it be 0x9000 -> 0xF000 (also why is RDY being set, its
* input only...)
*/
regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
cx_write(MC417_RWD, regval);
/* Collect byte */
tempval = cx_read(MC417_RWD);
dataval = tempval & 0x000000FF;
/* Bring CS and RD high. */
regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
cx_write(MC417_RWD, regval);
/* Read data byte 1 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
cx_write(MC417_RWD, regval);
regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
cx_write(MC417_RWD, regval);
tempval = cx_read(MC417_RWD);
dataval |= ((tempval & 0x000000FF) << 8);
regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
cx_write(MC417_RWD, regval);
/* Read data byte 2 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
cx_write(MC417_RWD, regval);
regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
cx_write(MC417_RWD, regval);
tempval = cx_read(MC417_RWD);
dataval |= ((tempval & 0x000000FF) << 16);
regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
cx_write(MC417_RWD, regval);
/* Read data byte 3 */
regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
cx_write(MC417_RWD, regval);
regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
cx_write(MC417_RWD, regval);
tempval = cx_read(MC417_RWD);
dataval |= ((tempval & 0x000000FF) << 24);
regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
cx_write(MC417_RWD, regval);
*value = dataval;
return retval;
}
int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value)
{
u32 regval;
/* Enable MC417 GPIO outputs except for MC417_MIRDY,
* which is an input.
*/
cx_write(MC417_OEN, MC417_MIRDY);
/* Write data byte 0 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 |
(value & 0x000000FF);
cx_write(MC417_RWD, regval);
/* Transition CS/WR to effect write transaction across bus. */
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write data byte 1 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 |
((value >> 8) & 0x000000FF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write data byte 2 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 |
((value >> 16) & 0x000000FF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write data byte 3 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 |
((value >> 24) & 0x000000FF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write address byte 2 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write address byte 1 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
((address >> 8) & 0xFF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write address byte 0 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
(address & 0xFF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Wait for the trans to complete (MC417_MIRDY asserted). */
return mc417_wait_ready(dev);
}
int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value)
{
int retval;
u32 regval;
u32 tempval;
u32 dataval;
/* Enable MC417 GPIO outputs except for MC417_MIRDY,
* which is an input.
*/
cx_write(MC417_OEN, MC417_MIRDY);
/* Write address byte 2 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write address byte 1 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
((address >> 8) & 0xFF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Write address byte 0 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
(address & 0xFF);
cx_write(MC417_RWD, regval);
regval |= MC417_MICS | MC417_MIWR;
cx_write(MC417_RWD, regval);
/* Wait for the trans to complete (MC417_MIRDY asserted). */
retval = mc417_wait_ready(dev);
/* switch the DAT0-7 GPIO[10:3] to input mode */
cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
/* Read data byte 3 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
cx_write(MC417_RWD, regval);
/* Transition RD to effect read transaction across bus. */
regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
cx_write(MC417_RWD, regval);
/* Collect byte */
tempval = cx_read(MC417_RWD);
dataval = ((tempval & 0x000000FF) << 24);
/* Bring CS and RD high. */
regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
cx_write(MC417_RWD, regval);
/* Read data byte 2 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
cx_write(MC417_RWD, regval);
regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
cx_write(MC417_RWD, regval);
tempval = cx_read(MC417_RWD);
dataval |= ((tempval & 0x000000FF) << 16);
regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
cx_write(MC417_RWD, regval);
/* Read data byte 1 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
cx_write(MC417_RWD, regval);
regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
cx_write(MC417_RWD, regval);
tempval = cx_read(MC417_RWD);
dataval |= ((tempval & 0x000000FF) << 8);
regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
cx_write(MC417_RWD, regval);
/* Read data byte 0 */
regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
cx_write(MC417_RWD, regval);
regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
cx_write(MC417_RWD, regval);
tempval = cx_read(MC417_RWD);
dataval |= (tempval & 0x000000FF);
regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
cx_write(MC417_RWD, regval);
*value = dataval;
return retval;
}
void mc417_gpio_set(struct cx23885_dev *dev, u32 mask)
{
u32 val;
/* Set the gpio value */
mc417_register_read(dev, 0x900C, &val);
val |= (mask & 0x000ffff);
mc417_register_write(dev, 0x900C, val);
}
void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask)
{
u32 val;
/* Clear the gpio value */
mc417_register_read(dev, 0x900C, &val);
val &= ~(mask & 0x0000ffff);
mc417_register_write(dev, 0x900C, val);
}
void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
{
u32 val;
/* Enable GPIO direction bits */
mc417_register_read(dev, 0x9020, &val);
if (asoutput)
val |= (mask & 0x0000ffff);
else
val &= ~(mask & 0x0000ffff);
mc417_register_write(dev, 0x9020, val);
}
/* ------------------------------------------------------------------ */
/* MPEG encoder API */
static char *cmd_to_str(int cmd)
{
switch (cmd) {
case CX2341X_ENC_PING_FW:
return "PING_FW";
case CX2341X_ENC_START_CAPTURE:
return "START_CAPTURE";
case CX2341X_ENC_STOP_CAPTURE:
return "STOP_CAPTURE";
case CX2341X_ENC_SET_AUDIO_ID:
return "SET_AUDIO_ID";
case CX2341X_ENC_SET_VIDEO_ID:
return "SET_VIDEO_ID";
case CX2341X_ENC_SET_PCR_ID:
return "SET_PCR_ID";
case CX2341X_ENC_SET_FRAME_RATE:
return "SET_FRAME_RATE";
case CX2341X_ENC_SET_FRAME_SIZE:
return "SET_FRAME_SIZE";
case CX2341X_ENC_SET_BIT_RATE:
return "SET_BIT_RATE";
case CX2341X_ENC_SET_GOP_PROPERTIES:
return "SET_GOP_PROPERTIES";
case CX2341X_ENC_SET_ASPECT_RATIO:
return "SET_ASPECT_RATIO";
case CX2341X_ENC_SET_DNR_FILTER_MODE:
return "SET_DNR_FILTER_MODE";
case CX2341X_ENC_SET_DNR_FILTER_PROPS:
return "SET_DNR_FILTER_PROPS";
case CX2341X_ENC_SET_CORING_LEVELS:
return "SET_CORING_LEVELS";
case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
return "SET_SPATIAL_FILTER_TYPE";
case CX2341X_ENC_SET_VBI_LINE:
return "SET_VBI_LINE";
case CX2341X_ENC_SET_STREAM_TYPE:
return "SET_STREAM_TYPE";
case CX2341X_ENC_SET_OUTPUT_PORT:
return "SET_OUTPUT_PORT";
case CX2341X_ENC_SET_AUDIO_PROPERTIES:
return "SET_AUDIO_PROPERTIES";
case CX2341X_ENC_HALT_FW:
return "HALT_FW";
case CX2341X_ENC_GET_VERSION:
return "GET_VERSION";
case CX2341X_ENC_SET_GOP_CLOSURE:
return "SET_GOP_CLOSURE";
case CX2341X_ENC_GET_SEQ_END:
return "GET_SEQ_END";
case CX2341X_ENC_SET_PGM_INDEX_INFO:
return "SET_PGM_INDEX_INFO";
case CX2341X_ENC_SET_VBI_CONFIG:
return "SET_VBI_CONFIG";
case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
return "SET_DMA_BLOCK_SIZE";
case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
return "GET_PREV_DMA_INFO_MB_10";
case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
return "GET_PREV_DMA_INFO_MB_9";
case CX2341X_ENC_SCHED_DMA_TO_HOST:
return "SCHED_DMA_TO_HOST";
case CX2341X_ENC_INITIALIZE_INPUT:
return "INITIALIZE_INPUT";
case CX2341X_ENC_SET_FRAME_DROP_RATE:
return "SET_FRAME_DROP_RATE";
case CX2341X_ENC_PAUSE_ENCODER:
return "PAUSE_ENCODER";
case CX2341X_ENC_REFRESH_INPUT:
return "REFRESH_INPUT";
case CX2341X_ENC_SET_COPYRIGHT:
return "SET_COPYRIGHT";
case CX2341X_ENC_SET_EVENT_NOTIFICATION:
return "SET_EVENT_NOTIFICATION";
case CX2341X_ENC_SET_NUM_VSYNC_LINES:
return "SET_NUM_VSYNC_LINES";
case CX2341X_ENC_SET_PLACEHOLDER:
return "SET_PLACEHOLDER";
case CX2341X_ENC_MUTE_VIDEO:
return "MUTE_VIDEO";
case CX2341X_ENC_MUTE_AUDIO:
return "MUTE_AUDIO";
case CX2341X_ENC_MISC:
return "MISC";
default:
return "UNKNOWN";
}
}
static int cx23885_mbox_func(void *priv,
u32 command,
int in,
int out,
u32 data[CX2341X_MBOX_MAX_DATA])
{
struct cx23885_dev *dev = priv;
unsigned long timeout;
u32 value, flag, retval = 0;
int i;
dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
cmd_to_str(command));
/* this may not be 100% safe if we can't read any memory location
without side effects */
mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
if (value != 0x12345678) {
pr_err("Firmware and/or mailbox pointer not initialized or corrupted, signature = 0x%x, cmd = %s\n",
value, cmd_to_str(command));
return -1;
}
/* This read looks at 32 bits, but flag is only 8 bits.
* Seems we also bail if CMD or TIMEOUT bytes are set???
*/
mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
if (flag) {
pr_err("ERROR: Mailbox appears to be in use (%x), cmd = %s\n",
flag, cmd_to_str(command));
return -1;
}
flag |= 1; /* tell 'em we're working on it */
mc417_memory_write(dev, dev->cx23417_mailbox, flag);
/* write command + args + fill remaining with zeros */
/* command code */
mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
mc417_memory_write(dev, dev->cx23417_mailbox + 3,
IVTV_API_STD_TIMEOUT); /* timeout */
for (i = 0; i < in; i++) {
mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
dprintk(3, "API Input %d = %d\n", i, data[i]);
}
for (; i < CX2341X_MBOX_MAX_DATA; i++)
mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
flag |= 3; /* tell 'em we're done writing */
mc417_memory_write(dev, dev->cx23417_mailbox, flag);
/* wait for firmware to handle the API command */
timeout = jiffies + msecs_to_jiffies(10);
for (;;) {
mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
if (0 != (flag & 4))
break;
if (time_after(jiffies, timeout)) {
pr_err("ERROR: API Mailbox timeout\n");
return -1;
}
udelay(10);
}
/* read output values */
for (i = 0; i < out; i++) {
mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
dprintk(3, "API Output %d = %d\n", i, data[i]);
}
mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
dprintk(3, "API result = %d\n", retval);
flag = 0;
mc417_memory_write(dev, dev->cx23417_mailbox, flag);
return retval;
}
/* We don't need to call the API often, so using just one
* mailbox will probably suffice
*/
static int cx23885_api_cmd(struct cx23885_dev *dev,
u32 command,
u32 inputcnt,
u32 outputcnt,
...)
{
u32 data[CX2341X_MBOX_MAX_DATA];
va_list vargs;
int i, err;
dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
va_start(vargs, outputcnt);
for (i = 0; i < inputcnt; i++)
data[i] = va_arg(vargs, int);
err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data);
for (i = 0; i < outputcnt; i++) {
int *vptr = va_arg(vargs, int *);
*vptr = data[i];
}
va_end(vargs);
return err;
}
static int cx23885_api_func(void *priv, u32 cmd, int in, int out, u32 data[CX2341X_MBOX_MAX_DATA])
{
return cx23885_mbox_func(priv, cmd, in, out, data);
}
static int cx23885_find_mailbox(struct cx23885_dev *dev)
{
u32 signature[4] = {
0x12345678, 0x34567812, 0x56781234, 0x78123456
};
int signaturecnt = 0;
u32 value;
int i;
dprintk(2, "%s()\n", __func__);
for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) {
mc417_memory_read(dev, i, &value);
if (value == signature[signaturecnt])
signaturecnt++;
else
signaturecnt = 0;
if (4 == signaturecnt) {
dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
return i+1;
}
}
pr_err("Mailbox signature values not found!\n");
return -1;
}
static int cx23885_load_firmware(struct cx23885_dev *dev)
{
static const unsigned char magic[8] = {
0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
};
const struct firmware *firmware;
int i, retval = 0;
u32 value = 0;
u32 gpio_output = 0;
u32 gpio_value;
u32 checksum = 0;
u32 *dataptr;
dprintk(2, "%s()\n", __func__);
/* Save GPIO settings before reset of APU */
retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
retval |= mc417_memory_read(dev, 0x900C, &gpio_value);
retval = mc417_register_write(dev,
IVTV_REG_VPU, 0xFFFFFFED);
retval |= mc417_register_write(dev,
IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
retval |= mc417_register_write(dev,
IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
retval |= mc417_register_write(dev,
IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
retval |= mc417_register_write(dev,
IVTV_REG_APU, 0);
if (retval != 0) {
pr_err("%s: Error with mc417_register_write\n",
__func__);
return -1;
}
retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME,
&dev->pci->dev);
if (retval != 0) {
pr_err("ERROR: Hotplug firmware request failed (%s).\n",
CX23885_FIRM_IMAGE_NAME);
pr_err("Please fix your hotplug setup, the board will not work without firmware loaded!\n");
return -1;
}
if (firmware->size != CX23885_FIRM_IMAGE_SIZE) {
pr_err("ERROR: Firmware size mismatch (have %zu, expected %d)\n",
firmware->size, CX23885_FIRM_IMAGE_SIZE);
release_firmware(firmware);
return -1;
}
if (0 != memcmp(firmware->data, magic, 8)) {
pr_err("ERROR: Firmware magic mismatch, wrong file?\n");
release_firmware(firmware);
return -1;
}
/* transfer to the chip */
dprintk(2, "Loading firmware ...\n");
dataptr = (u32 *)firmware->data;
for (i = 0; i < (firmware->size >> 2); i++) {
value = *dataptr;
checksum += ~value;
if (mc417_memory_write(dev, i, value) != 0) {
pr_err("ERROR: Loading firmware failed!\n");
release_firmware(firmware);
return -1;
}
dataptr++;
}
/* read back to verify with the checksum */
dprintk(1, "Verifying firmware ...\n");
for (i--; i >= 0; i--) {
if (mc417_memory_read(dev, i, &value) != 0) {
pr_err("ERROR: Reading firmware failed!\n");
release_firmware(firmware);
return -1;
}
checksum -= ~value;
}
if (checksum) {
pr_err("ERROR: Firmware load failed (checksum mismatch).\n");
release_firmware(firmware);
return -1;
}
release_firmware(firmware);
dprintk(1, "Firmware upload successful.\n");
retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
IVTV_CMD_HW_BLOCKS_RST);
/* F/W power up disturbs the GPIOs, restore state */
retval |= mc417_register_write(dev, 0x9020, gpio_output);
retval |= mc417_register_write(dev, 0x900C, gpio_value);
retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
/* Hardcoded GPIO's here */
retval |= mc417_register_write(dev, 0x9020, 0x4000);
retval |= mc417_register_write(dev, 0x900C, 0x4000);
mc417_register_read(dev, 0x9020, &gpio_output);
mc417_register_read(dev, 0x900C, &gpio_value);
if (retval < 0)
pr_err("%s: Error with mc417_register_write\n",
__func__);
return 0;
}
void cx23885_417_check_encoder(struct cx23885_dev *dev)
{
u32 status, seq;
status = seq = 0;
cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
}
static void cx23885_codec_settings(struct cx23885_dev *dev)
{
dprintk(1, "%s()\n", __func__);
/* Dynamically change the height based on video standard */
if (dev->encodernorm.id & V4L2_STD_525_60)
dev->ts1.height = 480;
else
dev->ts1.height = 576;
/* assign frame size */
cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
dev->ts1.height, dev->ts1.width);
dev->cxhdl.width = dev->ts1.width;
dev->cxhdl.height = dev->ts1.height;
dev->cxhdl.is_50hz =
(dev->encodernorm.id & V4L2_STD_625_50) != 0;
cx2341x_handler_setup(&dev->cxhdl);
cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
}
static int cx23885_initialize_codec(struct cx23885_dev *dev, int startencoder)
{
int version;
int retval;
u32 i, data[7];
dprintk(1, "%s()\n", __func__);
retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
if (retval < 0) {
dprintk(2, "%s() PING OK\n", __func__);
retval = cx23885_load_firmware(dev);
if (retval < 0) {
pr_err("%s() f/w load failed\n", __func__);
return retval;
}
retval = cx23885_find_mailbox(dev);
if (retval < 0) {
pr_err("%s() mailbox < 0, error\n",
__func__);
return -1;
}
dev->cx23417_mailbox = retval;
retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
if (retval < 0) {
pr_err("ERROR: cx23417 firmware ping failed!\n");
return -1;
}
retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
&version);
if (retval < 0) {
pr_err("ERROR: cx23417 firmware get encoder :version failed!\n");
return -1;
}
dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
msleep(200);
}
cx23885_codec_settings(dev);
msleep(60);
cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115);
cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0);
/* Setup to capture VBI */
data[0] = 0x0001BD00;
data[1] = 1; /* frames per interrupt */
data[2] = 4; /* total bufs */
data[3] = 0x91559155; /* start codes */
data[4] = 0x206080C0; /* stop codes */
data[5] = 6; /* lines */
data[6] = 64; /* BPL */
cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
data[2], data[3], data[4], data[5], data[6]);
for (i = 2; i <= 24; i++) {
int valid;
valid = ((i >= 19) && (i <= 21));
cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
valid, 0 , 0, 0);
cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
i | 0x80000000, valid, 0, 0, 0);
}
cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE);
msleep(60);
/* initialize the video input */
cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
msleep(60);
/* Enable VIP style pixel invalidation so we work with scaled mode */
mc417_memory_write(dev, 2120, 0x00000080);
/* start capturing to the host interface */
if (startencoder) {
cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE);
msleep(10);
}
return 0;
}
/* ------------------------------------------------------------------ */
static int queue_setup(struct vb2_queue *q,
unsigned int *num_buffers, unsigned int *num_planes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct cx23885_dev *dev = q->drv_priv;
dev->ts1.ts_packet_size = mpeglinesize;
dev->ts1.ts_packet_count = mpeglines;
*num_planes = 1;
sizes[0] = mpeglinesize * mpeglines;
*num_buffers = mpegbufs;
return 0;
}
static int buffer_prepare(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
struct cx23885_buffer *buf =
container_of(vbuf, struct cx23885_buffer, vb);
return cx23885_buf_prepare(buf, &dev->ts1);
}
static void buffer_finish(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
struct cx23885_buffer *buf = container_of(vbuf,
struct cx23885_buffer, vb);
cx23885_free_buffer(dev, buf);
}
static void buffer_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
struct cx23885_buffer *buf = container_of(vbuf,
struct cx23885_buffer, vb);
cx23885_buf_queue(&dev->ts1, buf);
}
static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
{
struct cx23885_dev *dev = q->drv_priv;
struct cx23885_dmaqueue *dmaq = &dev->ts1.mpegq;
unsigned long flags;
int ret;
ret = cx23885_initialize_codec(dev, 1);
if (ret == 0) {
struct cx23885_buffer *buf = list_entry(dmaq->active.next,
struct cx23885_buffer, queue);
cx23885_start_dma(&dev->ts1, dmaq, buf);
return 0;
}
spin_lock_irqsave(&dev->slock, flags);
while (!list_empty(&dmaq->active)) {
struct cx23885_buffer *buf = list_entry(dmaq->active.next,
struct cx23885_buffer, queue);
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
}
spin_unlock_irqrestore(&dev->slock, flags);
return ret;
}
static void cx23885_stop_streaming(struct vb2_queue *q)
{
struct cx23885_dev *dev = q->drv_priv;
/* stop mpeg capture */
cx23885_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
CX23885_END_NOW, CX23885_MPEG_CAPTURE,
CX23885_RAW_BITS_NONE);
msleep(500);
cx23885_417_check_encoder(dev);
cx23885_cancel_buffers(&dev->ts1);
}
static const struct vb2_ops cx23885_qops = {
.queue_setup = queue_setup,
.buf_prepare = buffer_prepare,
.buf_finish = buffer_finish,
.buf_queue = buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = cx23885_start_streaming,
.stop_streaming = cx23885_stop_streaming,
};
/* ------------------------------------------------------------------ */
static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *id)
{
struct cx23885_dev *dev = video_drvdata(file);
*id = dev->tvnorm;
return 0;
}
static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id id)
{
struct cx23885_dev *dev = video_drvdata(file);
unsigned int i;
int ret;
for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++)
if (id & cx23885_tvnorms[i].id)
break;
if (i == ARRAY_SIZE(cx23885_tvnorms))
return -EINVAL;
ret = cx23885_set_tvnorm(dev, id);
if (!ret)
dev->encodernorm = cx23885_tvnorms[i];
return ret;
}
static int vidioc_enum_input(struct file *file, void *priv,
struct v4l2_input *i)
{
struct cx23885_dev *dev = video_drvdata(file);
dprintk(1, "%s()\n", __func__);
return cx23885_enum_input(dev, i);
}
static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
{
return cx23885_get_input(file, priv, i);
}
static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
{
return cx23885_set_input(file, priv, i);
}
static int vidioc_g_tuner(struct file *file, void *priv,
struct v4l2_tuner *t)
{
struct cx23885_dev *dev = video_drvdata(file);
if (dev->tuner_type == TUNER_ABSENT)
return -EINVAL;
if (0 != t->index)
return -EINVAL;
strscpy(t->name, "Television", sizeof(t->name));
call_all(dev, tuner, g_tuner, t);
dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type);
return 0;
}
static int vidioc_s_tuner(struct file *file, void *priv,
const struct v4l2_tuner *t)
{
struct cx23885_dev *dev = video_drvdata(file);
if (dev->tuner_type == TUNER_ABSENT)
return -EINVAL;
/* Update the A/V core */
call_all(dev, tuner, s_tuner, t);
return 0;
}
static int vidioc_g_frequency(struct file *file, void *priv,
struct v4l2_frequency *f)
{
struct cx23885_dev *dev = video_drvdata(file);
if (dev->tuner_type == TUNER_ABSENT)
return -EINVAL;
f->type = V4L2_TUNER_ANALOG_TV;
f->frequency = dev->freq;
call_all(dev, tuner, g_frequency, f);
return 0;
}
static int vidioc_s_frequency(struct file *file, void *priv,
const struct v4l2_frequency *f)
{
return cx23885_set_frequency(file, priv, f);
}
static int vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
struct cx23885_dev *dev = video_drvdata(file);
struct cx23885_tsport *tsport = &dev->ts1;
strscpy(cap->driver, dev->name, sizeof(cap->driver));
strscpy(cap->card, cx23885_boards[tsport->dev->board].name,
sizeof(cap->card));
sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci));
cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
V4L2_CAP_STREAMING | V4L2_CAP_VBI_CAPTURE |
V4L2_CAP_AUDIO | V4L2_CAP_DEVICE_CAPS;
if (dev->tuner_type != TUNER_ABSENT)
cap->capabilities |= V4L2_CAP_TUNER;
return 0;
}
static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
if (f->index != 0)
return -EINVAL;
f->pixelformat = V4L2_PIX_FMT_MPEG;
return 0;
}
static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx23885_dev *dev = video_drvdata(file);
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
f->fmt.pix.bytesperline = 0;
f->fmt.pix.sizeimage =
dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
f->fmt.pix.colorspace = 0;
f->fmt.pix.width = dev->ts1.width;
f->fmt.pix.height = dev->ts1.height;
f->fmt.pix.field = V4L2_FIELD_INTERLACED;
dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d\n",
dev->ts1.width, dev->ts1.height);
return 0;
}
static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx23885_dev *dev = video_drvdata(file);
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
f->fmt.pix.bytesperline = 0;
f->fmt.pix.sizeimage =
dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
f->fmt.pix.colorspace = 0;
f->fmt.pix.field = V4L2_FIELD_INTERLACED;
dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d\n",
dev->ts1.width, dev->ts1.height);
return 0;
}
static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx23885_dev *dev = video_drvdata(file);
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
f->fmt.pix.bytesperline = 0;
f->fmt.pix.sizeimage =
dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
f->fmt.pix.colorspace = 0;
f->fmt.pix.field = V4L2_FIELD_INTERLACED;
dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n",
f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field);
return 0;
}
static int vidioc_log_status(struct file *file, void *priv)
{
struct cx23885_dev *dev = video_drvdata(file);
char name[32 + 2];
snprintf(name, sizeof(name), "%s/2", dev->name);
call_all(dev, core, log_status);
v4l2_ctrl_handler_log_status(&dev->cxhdl.hdl, name);
return 0;
}
static const struct v4l2_file_operations mpeg_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.release = vb2_fop_release,
.read = vb2_fop_read,
.poll = vb2_fop_poll,
.unlocked_ioctl = video_ioctl2,
.mmap = vb2_fop_mmap,
};
static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
.vidioc_g_std = vidioc_g_std,
.vidioc_s_std = vidioc_s_std,
.vidioc_enum_input = vidioc_enum_input,
.vidioc_g_input = vidioc_g_input,
.vidioc_s_input = vidioc_s_input,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_g_frequency = vidioc_g_frequency,
.vidioc_s_frequency = vidioc_s_frequency,
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_log_status = vidioc_log_status,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.vidioc_g_chip_info = cx23885_g_chip_info,
.vidioc_g_register = cx23885_g_register,
.vidioc_s_register = cx23885_s_register,
#endif
};
static struct video_device cx23885_mpeg_template = {
.name = "cx23885",
.fops = &mpeg_fops,
.ioctl_ops = &mpeg_ioctl_ops,
.tvnorms = CX23885_NORMS,
};
void cx23885_417_unregister(struct cx23885_dev *dev)
{
dprintk(1, "%s()\n", __func__);
if (dev->v4l_device) {
if (video_is_registered(dev->v4l_device))
video_unregister_device(dev->v4l_device);
else
video_device_release(dev->v4l_device);
v4l2_ctrl_handler_free(&dev->cxhdl.hdl);
dev->v4l_device = NULL;
}
}
static struct video_device *cx23885_video_dev_alloc(
struct cx23885_tsport *tsport,
struct pci_dev *pci,
struct video_device *template,
char *type)
{
struct video_device *vfd;
struct cx23885_dev *dev = tsport->dev;
dprintk(1, "%s()\n", __func__);
vfd = video_device_alloc();
if (NULL == vfd)
return NULL;
*vfd = *template;
snprintf(vfd->name, sizeof(vfd->name), "%s (%s)",
cx23885_boards[tsport->dev->board].name, type);
vfd->v4l2_dev = &dev->v4l2_dev;
vfd->release = video_device_release;
return vfd;
}
int cx23885_417_register(struct cx23885_dev *dev)
{
/* FIXME: Port1 hardcoded here */
int err = -ENODEV;
struct cx23885_tsport *tsport = &dev->ts1;
struct vb2_queue *q;
dprintk(1, "%s()\n", __func__);
if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER)
return err;
/* Set default TV standard */
dev->encodernorm = cx23885_tvnorms[0];
if (dev->encodernorm.id & V4L2_STD_525_60)
tsport->height = 480;
else
tsport->height = 576;
tsport->width = 720;
dev->cxhdl.port = CX2341X_PORT_SERIAL;
err = cx2341x_handler_init(&dev->cxhdl, 50);
if (err)
return err;
dev->cxhdl.priv = dev;
dev->cxhdl.func = cx23885_api_func;
cx2341x_handler_set_50hz(&dev->cxhdl, tsport->height == 576);
v4l2_ctrl_add_handler(&dev->ctrl_handler, &dev->cxhdl.hdl, NULL, false);
/* Allocate and initialize V4L video device */
dev->v4l_device = cx23885_video_dev_alloc(tsport,
dev->pci, &cx23885_mpeg_template, "mpeg");
q = &dev->vb2_mpegq;
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
q->gfp_flags = GFP_DMA32;
q->min_buffers_needed = 2;
q->drv_priv = dev;
q->buf_struct_size = sizeof(struct cx23885_buffer);
q->ops = &cx23885_qops;
q->mem_ops = &vb2_dma_sg_memops;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &dev->lock;
q->dev = &dev->pci->dev;
err = vb2_queue_init(q);
if (err < 0)
return err;
video_set_drvdata(dev->v4l_device, dev);
dev->v4l_device->lock = &dev->lock;
dev->v4l_device->queue = q;
dev->v4l_device->device_caps = V4L2_CAP_VIDEO_CAPTURE |
V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
if (dev->tuner_type != TUNER_ABSENT)
dev->v4l_device->device_caps |= V4L2_CAP_TUNER;
err = video_register_device(dev->v4l_device,
VFL_TYPE_VIDEO, -1);
if (err < 0) {
pr_info("%s: can't register mpeg device\n", dev->name);
return err;
}
pr_info("%s: registered device %s [mpeg]\n",
dev->name, video_device_node_name(dev->v4l_device));
/* ST: Configure the encoder parameters, but don't begin
* encoding, this resolves an issue where the first time the
* encoder is started video can be choppy.
*/
cx23885_initialize_codec(dev, 0);
return 0;
}
MODULE_FIRMWARE(CX23885_FIRM_IMAGE_NAME);
| linux-master | drivers/media/pci/cx23885/cx23885-417.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Conexant CX23885 PCIe bridge
*
* Copyright (c) 2006 Steven Toth <[email protected]>
*/
#include "cx23885.h"
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <media/v4l2-common.h>
static unsigned int i2c_debug;
module_param(i2c_debug, int, 0644);
MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]");
static unsigned int i2c_scan;
module_param(i2c_scan, int, 0444);
MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time");
#define dprintk(level, fmt, arg...)\
do { if (i2c_debug >= level)\
printk(KERN_DEBUG pr_fmt("%s: i2c:" fmt), \
__func__, ##arg); \
} while (0)
#define I2C_WAIT_DELAY 32
#define I2C_WAIT_RETRY 64
#define I2C_EXTEND (1 << 3)
#define I2C_NOSTOP (1 << 4)
static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
{
struct cx23885_i2c *bus = i2c_adap->algo_data;
struct cx23885_dev *dev = bus->dev;
return cx_read(bus->reg_stat) & 0x01;
}
static inline int i2c_is_busy(struct i2c_adapter *i2c_adap)
{
struct cx23885_i2c *bus = i2c_adap->algo_data;
struct cx23885_dev *dev = bus->dev;
return cx_read(bus->reg_stat) & 0x02 ? 1 : 0;
}
static int i2c_wait_done(struct i2c_adapter *i2c_adap)
{
int count;
for (count = 0; count < I2C_WAIT_RETRY; count++) {
if (!i2c_is_busy(i2c_adap))
break;
udelay(I2C_WAIT_DELAY);
}
if (I2C_WAIT_RETRY == count)
return 0;
return 1;
}
static int i2c_sendbytes(struct i2c_adapter *i2c_adap,
const struct i2c_msg *msg, int joined_rlen)
{
struct cx23885_i2c *bus = i2c_adap->algo_data;
struct cx23885_dev *dev = bus->dev;
u32 wdata, addr, ctrl;
int retval, cnt;
if (joined_rlen)
dprintk(1, "%s(msg->wlen=%d, nextmsg->rlen=%d)\n", __func__,
msg->len, joined_rlen);
else
dprintk(1, "%s(msg->len=%d)\n", __func__, msg->len);
/* Deal with i2c probe functions with zero payload */
if (msg->len == 0) {
cx_write(bus->reg_addr, msg->addr << 25);
cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2));
if (!i2c_wait_done(i2c_adap))
return -EIO;
if (!i2c_slave_did_ack(i2c_adap))
return -ENXIO;
dprintk(1, "%s() returns 0\n", __func__);
return 0;
}
/* dev, reg + first byte */
addr = (msg->addr << 25) | msg->buf[0];
wdata = msg->buf[0];
ctrl = bus->i2c_period | (1 << 12) | (1 << 2);
if (msg->len > 1)
ctrl |= I2C_NOSTOP | I2C_EXTEND;
else if (joined_rlen)
ctrl |= I2C_NOSTOP;
cx_write(bus->reg_addr, addr);
cx_write(bus->reg_wdata, wdata);
cx_write(bus->reg_ctrl, ctrl);
if (!i2c_wait_done(i2c_adap))
goto eio;
if (i2c_debug) {
printk(KERN_DEBUG " <W %02x %02x", msg->addr << 1, msg->buf[0]);
if (!(ctrl & I2C_NOSTOP))
pr_cont(" >\n");
}
for (cnt = 1; cnt < msg->len; cnt++) {
/* following bytes */
wdata = msg->buf[cnt];
ctrl = bus->i2c_period | (1 << 12) | (1 << 2);
if (cnt < msg->len - 1)
ctrl |= I2C_NOSTOP | I2C_EXTEND;
else if (joined_rlen)
ctrl |= I2C_NOSTOP;
cx_write(bus->reg_addr, addr);
cx_write(bus->reg_wdata, wdata);
cx_write(bus->reg_ctrl, ctrl);
if (!i2c_wait_done(i2c_adap))
goto eio;
if (i2c_debug) {
pr_cont(" %02x", msg->buf[cnt]);
if (!(ctrl & I2C_NOSTOP))
pr_cont(" >\n");
}
}
return msg->len;
eio:
retval = -EIO;
if (i2c_debug)
pr_err(" ERR: %d\n", retval);
return retval;
}
static int i2c_readbytes(struct i2c_adapter *i2c_adap,
const struct i2c_msg *msg, int joined)
{
struct cx23885_i2c *bus = i2c_adap->algo_data;
struct cx23885_dev *dev = bus->dev;
u32 ctrl, cnt;
int retval;
if (i2c_debug && !joined)
dprintk(1, "%s(msg->len=%d)\n", __func__, msg->len);
/* Deal with i2c probe functions with zero payload */
if (msg->len == 0) {
cx_write(bus->reg_addr, msg->addr << 25);
cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2) | 1);
if (!i2c_wait_done(i2c_adap))
return -EIO;
if (!i2c_slave_did_ack(i2c_adap))
return -ENXIO;
dprintk(1, "%s() returns 0\n", __func__);
return 0;
}
if (i2c_debug) {
if (joined)
dprintk(1, " R");
else
dprintk(1, " <R %02x", (msg->addr << 1) + 1);
}
for (cnt = 0; cnt < msg->len; cnt++) {
ctrl = bus->i2c_period | (1 << 12) | (1 << 2) | 1;
if (cnt < msg->len - 1)
ctrl |= I2C_NOSTOP | I2C_EXTEND;
cx_write(bus->reg_addr, msg->addr << 25);
cx_write(bus->reg_ctrl, ctrl);
if (!i2c_wait_done(i2c_adap))
goto eio;
msg->buf[cnt] = cx_read(bus->reg_rdata) & 0xff;
if (i2c_debug) {
dprintk(1, " %02x", msg->buf[cnt]);
if (!(ctrl & I2C_NOSTOP))
dprintk(1, " >\n");
}
}
return msg->len;
eio:
retval = -EIO;
if (i2c_debug)
pr_err(" ERR: %d\n", retval);
return retval;
}
static int i2c_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg *msgs, int num)
{
int i, retval = 0;
dprintk(1, "%s(num = %d)\n", __func__, num);
for (i = 0 ; i < num; i++) {
dprintk(1, "%s(num = %d) addr = 0x%02x len = 0x%x\n",
__func__, num, msgs[i].addr, msgs[i].len);
if (msgs[i].flags & I2C_M_RD) {
/* read */
retval = i2c_readbytes(i2c_adap, &msgs[i], 0);
} else if (i + 1 < num && (msgs[i + 1].flags & I2C_M_RD) &&
msgs[i].addr == msgs[i + 1].addr) {
/* write then read from same address */
retval = i2c_sendbytes(i2c_adap, &msgs[i],
msgs[i + 1].len);
if (retval < 0)
goto err;
i++;
retval = i2c_readbytes(i2c_adap, &msgs[i], 1);
} else {
/* write */
retval = i2c_sendbytes(i2c_adap, &msgs[i], 0);
}
if (retval < 0)
goto err;
}
return num;
err:
return retval;
}
static u32 cx23885_functionality(struct i2c_adapter *adap)
{
return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C;
}
static const struct i2c_algorithm cx23885_i2c_algo_template = {
.master_xfer = i2c_xfer,
.functionality = cx23885_functionality,
};
/* ----------------------------------------------------------------------- */
static const struct i2c_adapter cx23885_i2c_adap_template = {
.name = "cx23885",
.owner = THIS_MODULE,
.algo = &cx23885_i2c_algo_template,
};
static const struct i2c_client cx23885_i2c_client_template = {
.name = "cx23885 internal",
};
static char *i2c_devs[128] = {
[0x10 >> 1] = "tda10048",
[0x12 >> 1] = "dib7000pc",
[0x1c >> 1] = "lgdt3303",
[0x80 >> 1] = "cs3308",
[0x82 >> 1] = "cs3308",
[0x86 >> 1] = "tda9887",
[0x32 >> 1] = "cx24227",
[0x88 >> 1] = "cx25837",
[0x84 >> 1] = "tda8295",
[0x98 >> 1] = "flatiron",
[0xa0 >> 1] = "eeprom",
[0xc0 >> 1] = "tuner/mt2131/tda8275",
[0xc2 >> 1] = "tuner/mt2131/tda8275/xc5000/xc3028",
[0xc8 >> 1] = "tuner/xc3028L",
};
static void do_i2c_scan(char *name, struct i2c_client *c)
{
unsigned char buf;
int i, rc;
for (i = 0; i < 128; i++) {
c->addr = i;
rc = i2c_master_recv(c, &buf, 0);
if (rc < 0)
continue;
pr_info("%s: i2c scan: found device @ 0x%04x [%s]\n",
name, i, i2c_devs[i] ? i2c_devs[i] : "???");
}
}
/* init + register i2c adapter */
int cx23885_i2c_register(struct cx23885_i2c *bus)
{
struct cx23885_dev *dev = bus->dev;
dprintk(1, "%s(bus = %d)\n", __func__, bus->nr);
bus->i2c_adap = cx23885_i2c_adap_template;
bus->i2c_client = cx23885_i2c_client_template;
bus->i2c_adap.dev.parent = &dev->pci->dev;
strscpy(bus->i2c_adap.name, bus->dev->name,
sizeof(bus->i2c_adap.name));
bus->i2c_adap.algo_data = bus;
i2c_set_adapdata(&bus->i2c_adap, &dev->v4l2_dev);
i2c_add_adapter(&bus->i2c_adap);
bus->i2c_client.adapter = &bus->i2c_adap;
if (0 == bus->i2c_rc) {
dprintk(1, "%s: i2c bus %d registered\n", dev->name, bus->nr);
if (i2c_scan) {
pr_info("%s: scan bus %d:\n",
dev->name, bus->nr);
do_i2c_scan(dev->name, &bus->i2c_client);
}
} else
pr_warn("%s: i2c bus %d register FAILED\n",
dev->name, bus->nr);
/* Instantiate the IR receiver device, if present */
if (0 == bus->i2c_rc) {
struct i2c_board_info info;
static const unsigned short addr_list[] = {
0x6b, I2C_CLIENT_END
};
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "ir_video", I2C_NAME_SIZE);
/* Use quick read command for probe, some IR chips don't
* support writes */
i2c_new_scanned_device(&bus->i2c_adap, &info, addr_list,
i2c_probe_func_quick_read);
}
return bus->i2c_rc;
}
int cx23885_i2c_unregister(struct cx23885_i2c *bus)
{
i2c_del_adapter(&bus->i2c_adap);
return 0;
}
void cx23885_av_clk(struct cx23885_dev *dev, int enable)
{
/* write 0 to bus 2 addr 0x144 via i2x_xfer() */
char buffer[3];
struct i2c_msg msg;
dprintk(1, "%s(enabled = %d)\n", __func__, enable);
/* Register 0x144 */
buffer[0] = 0x01;
buffer[1] = 0x44;
if (enable == 1)
buffer[2] = 0x05;
else
buffer[2] = 0x00;
msg.addr = 0x44;
msg.flags = I2C_M_TEN;
msg.len = 3;
msg.buf = buffer;
i2c_xfer(&dev->i2c_bus[2].i2c_adap, &msg, 1);
}
| linux-master | drivers/media/pci/cx23885/cx23885-i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Conexant CX23885 PCIe bridge
*
* Copyright (c) 2007 Steven Toth <[email protected]>
*/
#include "cx23885.h"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
static unsigned int vbibufs = 4;
module_param(vbibufs, int, 0644);
MODULE_PARM_DESC(vbibufs, "number of vbi buffers, range 2-32");
static unsigned int vbi_debug;
module_param(vbi_debug, int, 0644);
MODULE_PARM_DESC(vbi_debug, "enable debug messages [vbi]");
#define dprintk(level, fmt, arg...)\
do { if (vbi_debug >= level)\
printk(KERN_DEBUG pr_fmt("%s: vbi:" fmt), \
__func__, ##arg); \
} while (0)
/* ------------------------------------------------------------------ */
#define VBI_LINE_LENGTH 1440
#define VBI_NTSC_LINE_COUNT 12
#define VBI_PAL_LINE_COUNT 18
int cx23885_vbi_fmt(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx23885_dev *dev = video_drvdata(file);
f->fmt.vbi.sampling_rate = 27000000;
f->fmt.vbi.samples_per_line = VBI_LINE_LENGTH;
f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
f->fmt.vbi.offset = 0;
f->fmt.vbi.flags = 0;
if (dev->tvnorm & V4L2_STD_525_60) {
/* ntsc */
f->fmt.vbi.start[0] = V4L2_VBI_ITU_525_F1_START + 9;
f->fmt.vbi.start[1] = V4L2_VBI_ITU_525_F2_START + 9;
f->fmt.vbi.count[0] = VBI_NTSC_LINE_COUNT;
f->fmt.vbi.count[1] = VBI_NTSC_LINE_COUNT;
} else if (dev->tvnorm & V4L2_STD_625_50) {
/* pal */
f->fmt.vbi.start[0] = V4L2_VBI_ITU_625_F1_START + 5;
f->fmt.vbi.start[1] = V4L2_VBI_ITU_625_F2_START + 5;
f->fmt.vbi.count[0] = VBI_PAL_LINE_COUNT;
f->fmt.vbi.count[1] = VBI_PAL_LINE_COUNT;
}
return 0;
}
/* We're given the Video Interrupt status register.
* The cx23885_video_irq() func has already validated
* the potential error bits, we just need to
* deal with vbi payload and return indication if
* we actually processed any payload.
*/
int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status)
{
u32 count;
int handled = 0;
if (status & VID_BC_MSK_VBI_RISCI1) {
dprintk(1, "%s() VID_BC_MSK_VBI_RISCI1\n", __func__);
spin_lock(&dev->slock);
count = cx_read(VBI_A_GPCNT);
cx23885_video_wakeup(dev, &dev->vbiq, count);
spin_unlock(&dev->slock);
handled++;
}
return handled;
}
static int cx23885_start_vbi_dma(struct cx23885_dev *dev,
struct cx23885_dmaqueue *q,
struct cx23885_buffer *buf)
{
dprintk(1, "%s()\n", __func__);
/* setup fifo + format */
cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02],
VBI_LINE_LENGTH, buf->risc.dma);
/* reset counter */
cx_write(VID_A_VBI_CTRL, 3);
cx_write(VBI_A_GPCNT_CTL, 3);
q->count = 0;
/* enable irq */
cx23885_irq_add_enable(dev, 0x01);
cx_set(VID_A_INT_MSK, 0x000022);
/* start dma */
cx_set(DEV_CNTRL2, (1<<5));
cx_set(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */
return 0;
}
/* ------------------------------------------------------------------ */
static int queue_setup(struct vb2_queue *q,
unsigned int *num_buffers, unsigned int *num_planes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct cx23885_dev *dev = q->drv_priv;
unsigned lines = VBI_PAL_LINE_COUNT;
if (dev->tvnorm & V4L2_STD_525_60)
lines = VBI_NTSC_LINE_COUNT;
*num_planes = 1;
sizes[0] = lines * VBI_LINE_LENGTH * 2;
return 0;
}
static int buffer_prepare(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
struct cx23885_buffer *buf = container_of(vbuf,
struct cx23885_buffer, vb);
struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
unsigned lines = VBI_PAL_LINE_COUNT;
if (dev->tvnorm & V4L2_STD_525_60)
lines = VBI_NTSC_LINE_COUNT;
if (vb2_plane_size(vb, 0) < lines * VBI_LINE_LENGTH * 2)
return -EINVAL;
vb2_set_plane_payload(vb, 0, lines * VBI_LINE_LENGTH * 2);
cx23885_risc_vbibuffer(dev->pci, &buf->risc,
sgt->sgl,
0, VBI_LINE_LENGTH * lines,
VBI_LINE_LENGTH, 0,
lines);
return 0;
}
static void buffer_finish(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_buffer *buf = container_of(vbuf,
struct cx23885_buffer, vb);
cx23885_free_buffer(vb->vb2_queue->drv_priv, buf);
}
/*
* The risc program for each buffer works as follows: it starts with a simple
* 'JUMP to addr + 12', which is effectively a NOP. Then the code to DMA the
* buffer follows and at the end we have a JUMP back to the start + 12 (skipping
* the initial JUMP).
*
* This is the risc program of the first buffer to be queued if the active list
* is empty and it just keeps DMAing this buffer without generating any
* interrupts.
*
* If a new buffer is added then the initial JUMP in the code for that buffer
* will generate an interrupt which signals that the previous buffer has been
* DMAed successfully and that it can be returned to userspace.
*
* It also sets the final jump of the previous buffer to the start of the new
* buffer, thus chaining the new buffer into the DMA chain. This is a single
* atomic u32 write, so there is no race condition.
*
* The end-result of all this that you only get an interrupt when a buffer
* is ready, so the control flow is very easy.
*/
static void buffer_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
struct cx23885_buffer *buf = container_of(vbuf,
struct cx23885_buffer, vb);
struct cx23885_buffer *prev;
struct cx23885_dmaqueue *q = &dev->vbiq;
unsigned long flags;
buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12);
buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12);
buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
if (list_empty(&q->active)) {
spin_lock_irqsave(&dev->slock, flags);
list_add_tail(&buf->queue, &q->active);
spin_unlock_irqrestore(&dev->slock, flags);
dprintk(2, "[%p/%d] vbi_queue - first active\n",
buf, buf->vb.vb2_buf.index);
} else {
buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
prev = list_entry(q->active.prev, struct cx23885_buffer,
queue);
spin_lock_irqsave(&dev->slock, flags);
list_add_tail(&buf->queue, &q->active);
spin_unlock_irqrestore(&dev->slock, flags);
prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
dprintk(2, "[%p/%d] buffer_queue - append to active\n",
buf, buf->vb.vb2_buf.index);
}
}
static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
{
struct cx23885_dev *dev = q->drv_priv;
struct cx23885_dmaqueue *dmaq = &dev->vbiq;
struct cx23885_buffer *buf = list_entry(dmaq->active.next,
struct cx23885_buffer, queue);
cx23885_start_vbi_dma(dev, dmaq, buf);
return 0;
}
static void cx23885_stop_streaming(struct vb2_queue *q)
{
struct cx23885_dev *dev = q->drv_priv;
struct cx23885_dmaqueue *dmaq = &dev->vbiq;
unsigned long flags;
cx_clear(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */
spin_lock_irqsave(&dev->slock, flags);
while (!list_empty(&dmaq->active)) {
struct cx23885_buffer *buf = list_entry(dmaq->active.next,
struct cx23885_buffer, queue);
list_del(&buf->queue);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&dev->slock, flags);
}
const struct vb2_ops cx23885_vbi_qops = {
.queue_setup = queue_setup,
.buf_prepare = buffer_prepare,
.buf_finish = buffer_finish,
.buf_queue = buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = cx23885_start_streaming,
.stop_streaming = cx23885_stop_streaming,
};
| linux-master | drivers/media/pci/cx23885/cx23885-vbi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* netup-eeprom.c
*
* 24LC02 EEPROM driver in conjunction with NetUP Dual DVB-S2 CI card
*
* Copyright (C) 2009 NetUP Inc.
* Copyright (C) 2009 Abylay Ospan <[email protected]>
*/
#
#include "cx23885.h"
#include "netup-eeprom.h"
#define EEPROM_I2C_ADDR 0x50
int netup_eeprom_read(struct i2c_adapter *i2c_adap, u8 addr)
{
int ret;
unsigned char buf[2];
/* Read from EEPROM */
struct i2c_msg msg[] = {
{
.addr = EEPROM_I2C_ADDR,
.flags = 0,
.buf = &buf[0],
.len = 1
}, {
.addr = EEPROM_I2C_ADDR,
.flags = I2C_M_RD,
.buf = &buf[1],
.len = 1
}
};
buf[0] = addr;
buf[1] = 0x0;
ret = i2c_transfer(i2c_adap, msg, 2);
if (ret != 2) {
pr_err("eeprom i2c read error, status=%d\n", ret);
return -1;
}
return buf[1];
};
int netup_eeprom_write(struct i2c_adapter *i2c_adap, u8 addr, u8 data)
{
int ret;
unsigned char bufw[2];
/* Write into EEPROM */
struct i2c_msg msg[] = {
{
.addr = EEPROM_I2C_ADDR,
.flags = 0,
.buf = &bufw[0],
.len = 2
}
};
bufw[0] = addr;
bufw[1] = data;
ret = i2c_transfer(i2c_adap, msg, 1);
if (ret != 1) {
pr_err("eeprom i2c write error, status=%d\n", ret);
return -1;
}
mdelay(10); /* prophylactic delay, datasheet write cycle time = 5 ms */
return 0;
};
void netup_get_card_info(struct i2c_adapter *i2c_adap,
struct netup_card_info *cinfo)
{
int i, j;
cinfo->rev = netup_eeprom_read(i2c_adap, 63);
for (i = 64, j = 0; i < 70; i++, j++)
cinfo->port[0].mac[j] = netup_eeprom_read(i2c_adap, i);
for (i = 70, j = 0; i < 76; i++, j++)
cinfo->port[1].mac[j] = netup_eeprom_read(i2c_adap, i);
};
| linux-master | drivers/media/pci/cx23885/netup-eeprom.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* Support for CX23885 analog audio capture
*
* (c) 2008 Mijhail Moreyra <[email protected]>
* Adapted from cx88-alsa.c
* (c) 2009 Steven Toth <[email protected]>
*/
#include "cx23885.h"
#include "cx23885-reg.h"
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/vmalloc.h>
#include <linux/dma-mapping.h>
#include <linux/pci.h>
#include <asm/delay.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/control.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#define AUDIO_SRAM_CHANNEL SRAM_CH07
#define dprintk(level, fmt, arg...) do { \
if (audio_debug + 1 > level) \
printk(KERN_DEBUG pr_fmt("%s: alsa: " fmt), \
chip->dev->name, ##arg); \
} while(0)
/****************************************************************************
Module global static vars
****************************************************************************/
static unsigned int disable_analog_audio;
module_param(disable_analog_audio, int, 0644);
MODULE_PARM_DESC(disable_analog_audio, "disable analog audio ALSA driver");
static unsigned int audio_debug;
module_param(audio_debug, int, 0644);
MODULE_PARM_DESC(audio_debug, "enable debug messages [analog audio]");
/****************************************************************************
Board specific functions
****************************************************************************/
/* Constants taken from cx88-reg.h */
#define AUD_INT_DN_RISCI1 (1 << 0)
#define AUD_INT_UP_RISCI1 (1 << 1)
#define AUD_INT_RDS_DN_RISCI1 (1 << 2)
#define AUD_INT_DN_RISCI2 (1 << 4) /* yes, 3 is skipped */
#define AUD_INT_UP_RISCI2 (1 << 5)
#define AUD_INT_RDS_DN_RISCI2 (1 << 6)
#define AUD_INT_DN_SYNC (1 << 12)
#define AUD_INT_UP_SYNC (1 << 13)
#define AUD_INT_RDS_DN_SYNC (1 << 14)
#define AUD_INT_OPC_ERR (1 << 16)
#define AUD_INT_BER_IRQ (1 << 20)
#define AUD_INT_MCHG_IRQ (1 << 21)
#define GP_COUNT_CONTROL_RESET 0x3
static int cx23885_alsa_dma_init(struct cx23885_audio_dev *chip,
unsigned long nr_pages)
{
struct cx23885_audio_buffer *buf = chip->buf;
struct page *pg;
int i;
buf->vaddr = vmalloc_32(nr_pages << PAGE_SHIFT);
if (NULL == buf->vaddr) {
dprintk(1, "vmalloc_32(%lu pages) failed\n", nr_pages);
return -ENOMEM;
}
dprintk(1, "vmalloc is at addr %p, size=%lu\n",
buf->vaddr, nr_pages << PAGE_SHIFT);
memset(buf->vaddr, 0, nr_pages << PAGE_SHIFT);
buf->nr_pages = nr_pages;
buf->sglist = vzalloc(array_size(sizeof(*buf->sglist), buf->nr_pages));
if (NULL == buf->sglist)
goto vzalloc_err;
sg_init_table(buf->sglist, buf->nr_pages);
for (i = 0; i < buf->nr_pages; i++) {
pg = vmalloc_to_page(buf->vaddr + i * PAGE_SIZE);
if (NULL == pg)
goto vmalloc_to_page_err;
sg_set_page(&buf->sglist[i], pg, PAGE_SIZE, 0);
}
return 0;
vmalloc_to_page_err:
vfree(buf->sglist);
buf->sglist = NULL;
vzalloc_err:
vfree(buf->vaddr);
buf->vaddr = NULL;
return -ENOMEM;
}
static int cx23885_alsa_dma_map(struct cx23885_audio_dev *dev)
{
struct cx23885_audio_buffer *buf = dev->buf;
buf->sglen = dma_map_sg(&dev->pci->dev, buf->sglist,
buf->nr_pages, DMA_FROM_DEVICE);
if (0 == buf->sglen) {
pr_warn("%s: cx23885_alsa_map_sg failed\n", __func__);
return -ENOMEM;
}
return 0;
}
static int cx23885_alsa_dma_unmap(struct cx23885_audio_dev *dev)
{
struct cx23885_audio_buffer *buf = dev->buf;
if (!buf->sglen)
return 0;
dma_unmap_sg(&dev->pci->dev, buf->sglist, buf->nr_pages, DMA_FROM_DEVICE);
buf->sglen = 0;
return 0;
}
static int cx23885_alsa_dma_free(struct cx23885_audio_buffer *buf)
{
vfree(buf->sglist);
buf->sglist = NULL;
vfree(buf->vaddr);
buf->vaddr = NULL;
return 0;
}
/*
* BOARD Specific: Sets audio DMA
*/
static int cx23885_start_audio_dma(struct cx23885_audio_dev *chip)
{
struct cx23885_audio_buffer *buf = chip->buf;
struct cx23885_dev *dev = chip->dev;
struct sram_channel *audio_ch =
&dev->sram_channels[AUDIO_SRAM_CHANNEL];
dprintk(1, "%s()\n", __func__);
/* Make sure RISC/FIFO are off before changing FIFO/RISC settings */
cx_clear(AUD_INT_DMA_CTL, 0x11);
/* setup fifo + format - out channel */
cx23885_sram_channel_setup(chip->dev, audio_ch, buf->bpl,
buf->risc.dma);
/* sets bpl size */
cx_write(AUD_INT_A_LNGTH, buf->bpl);
/* This is required to get good audio (1 seems to be ok) */
cx_write(AUD_INT_A_MODE, 1);
/* reset counter */
cx_write(AUD_INT_A_GPCNT_CTL, GP_COUNT_CONTROL_RESET);
atomic_set(&chip->count, 0);
dprintk(1, "Start audio DMA, %d B/line, %d lines/FIFO, %d periods, %d byte buffer\n",
buf->bpl, cx_read(audio_ch->cmds_start+12)>>1,
chip->num_periods, buf->bpl * chip->num_periods);
/* Enables corresponding bits at AUD_INT_STAT */
cx_write(AUDIO_INT_INT_MSK, AUD_INT_OPC_ERR | AUD_INT_DN_SYNC |
AUD_INT_DN_RISCI1);
/* Clean any pending interrupt bits already set */
cx_write(AUDIO_INT_INT_STAT, ~0);
/* enable audio irqs */
cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT);
/* start dma */
cx_set(DEV_CNTRL2, (1<<5)); /* Enables Risc Processor */
cx_set(AUD_INT_DMA_CTL, 0x11); /* audio downstream FIFO and
RISC enable */
if (audio_debug)
cx23885_sram_channel_dump(chip->dev, audio_ch);
return 0;
}
/*
* BOARD Specific: Resets audio DMA
*/
static int cx23885_stop_audio_dma(struct cx23885_audio_dev *chip)
{
struct cx23885_dev *dev = chip->dev;
dprintk(1, "Stopping audio DMA\n");
/* stop dma */
cx_clear(AUD_INT_DMA_CTL, 0x11);
/* disable irqs */
cx_clear(PCI_INT_MSK, PCI_MSK_AUD_INT);
cx_clear(AUDIO_INT_INT_MSK, AUD_INT_OPC_ERR | AUD_INT_DN_SYNC |
AUD_INT_DN_RISCI1);
if (audio_debug)
cx23885_sram_channel_dump(chip->dev,
&dev->sram_channels[AUDIO_SRAM_CHANNEL]);
return 0;
}
/*
* BOARD Specific: Handles audio IRQ
*/
int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask)
{
struct cx23885_audio_dev *chip = dev->audio_dev;
if (0 == (status & mask))
return 0;
cx_write(AUDIO_INT_INT_STAT, status);
/* risc op code error */
if (status & AUD_INT_OPC_ERR) {
pr_warn("%s/1: Audio risc op code error\n",
dev->name);
cx_clear(AUD_INT_DMA_CTL, 0x11);
cx23885_sram_channel_dump(dev,
&dev->sram_channels[AUDIO_SRAM_CHANNEL]);
}
if (status & AUD_INT_DN_SYNC) {
dprintk(1, "Downstream sync error\n");
cx_write(AUD_INT_A_GPCNT_CTL, GP_COUNT_CONTROL_RESET);
return 1;
}
/* risc1 downstream */
if (status & AUD_INT_DN_RISCI1) {
atomic_set(&chip->count, cx_read(AUD_INT_A_GPCNT));
snd_pcm_period_elapsed(chip->substream);
}
/* FIXME: Any other status should deserve a special handling? */
return 1;
}
static int dsp_buffer_free(struct cx23885_audio_dev *chip)
{
struct cx23885_riscmem *risc;
BUG_ON(!chip->dma_size);
dprintk(2, "Freeing buffer\n");
cx23885_alsa_dma_unmap(chip);
cx23885_alsa_dma_free(chip->buf);
risc = &chip->buf->risc;
dma_free_coherent(&chip->pci->dev, risc->size, risc->cpu, risc->dma);
kfree(chip->buf);
chip->buf = NULL;
chip->dma_size = 0;
return 0;
}
/****************************************************************************
ALSA PCM Interface
****************************************************************************/
/*
* Digital hardware definition
*/
#define DEFAULT_FIFO_SIZE 4096
static const struct snd_pcm_hardware snd_cx23885_digital_hw = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
/* Analog audio output will be full of clicks and pops if there
are not exactly four lines in the SRAM FIFO buffer. */
.period_bytes_min = DEFAULT_FIFO_SIZE/4,
.period_bytes_max = DEFAULT_FIFO_SIZE/4,
.periods_min = 1,
.periods_max = 1024,
.buffer_bytes_max = (1024*1024),
};
/*
* audio pcm capture open callback
*/
static int snd_cx23885_pcm_open(struct snd_pcm_substream *substream)
{
struct cx23885_audio_dev *chip = snd_pcm_substream_chip(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int err;
if (!chip) {
pr_err("BUG: cx23885 can't find device struct. Can't proceed with open\n");
return -ENODEV;
}
err = snd_pcm_hw_constraint_pow2(runtime, 0,
SNDRV_PCM_HW_PARAM_PERIODS);
if (err < 0)
goto _error;
chip->substream = substream;
runtime->hw = snd_cx23885_digital_hw;
if (chip->dev->sram_channels[AUDIO_SRAM_CHANNEL].fifo_size !=
DEFAULT_FIFO_SIZE) {
unsigned int bpl = chip->dev->
sram_channels[AUDIO_SRAM_CHANNEL].fifo_size / 4;
bpl &= ~7; /* must be multiple of 8 */
runtime->hw.period_bytes_min = bpl;
runtime->hw.period_bytes_max = bpl;
}
return 0;
_error:
dprintk(1, "Error opening PCM!\n");
return err;
}
/*
* audio close callback
*/
static int snd_cx23885_close(struct snd_pcm_substream *substream)
{
return 0;
}
/*
* hw_params callback
*/
static int snd_cx23885_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct cx23885_audio_dev *chip = snd_pcm_substream_chip(substream);
struct cx23885_audio_buffer *buf;
int ret;
if (substream->runtime->dma_area) {
dsp_buffer_free(chip);
substream->runtime->dma_area = NULL;
}
chip->period_size = params_period_bytes(hw_params);
chip->num_periods = params_periods(hw_params);
chip->dma_size = chip->period_size * params_periods(hw_params);
BUG_ON(!chip->dma_size);
BUG_ON(chip->num_periods & (chip->num_periods-1));
buf = kzalloc(sizeof(*buf), GFP_KERNEL);
if (NULL == buf)
return -ENOMEM;
buf->bpl = chip->period_size;
chip->buf = buf;
ret = cx23885_alsa_dma_init(chip,
(PAGE_ALIGN(chip->dma_size) >> PAGE_SHIFT));
if (ret < 0)
goto error;
ret = cx23885_alsa_dma_map(chip);
if (ret < 0)
goto error;
ret = cx23885_risc_databuffer(chip->pci, &buf->risc, buf->sglist,
chip->period_size, chip->num_periods, 1);
if (ret < 0)
goto error;
/* Loop back to start of program */
buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP|RISC_IRQ1|RISC_CNT_INC);
buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
substream->runtime->dma_area = chip->buf->vaddr;
substream->runtime->dma_bytes = chip->dma_size;
substream->runtime->dma_addr = 0;
return 0;
error:
kfree(buf);
chip->buf = NULL;
return ret;
}
/*
* hw free callback
*/
static int snd_cx23885_hw_free(struct snd_pcm_substream *substream)
{
struct cx23885_audio_dev *chip = snd_pcm_substream_chip(substream);
if (substream->runtime->dma_area) {
dsp_buffer_free(chip);
substream->runtime->dma_area = NULL;
}
return 0;
}
/*
* prepare callback
*/
static int snd_cx23885_prepare(struct snd_pcm_substream *substream)
{
return 0;
}
/*
* trigger callback
*/
static int snd_cx23885_card_trigger(struct snd_pcm_substream *substream,
int cmd)
{
struct cx23885_audio_dev *chip = snd_pcm_substream_chip(substream);
int err;
/* Local interrupts are already disabled by ALSA */
spin_lock(&chip->lock);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
err = cx23885_start_audio_dma(chip);
break;
case SNDRV_PCM_TRIGGER_STOP:
err = cx23885_stop_audio_dma(chip);
break;
default:
err = -EINVAL;
break;
}
spin_unlock(&chip->lock);
return err;
}
/*
* pointer callback
*/
static snd_pcm_uframes_t snd_cx23885_pointer(
struct snd_pcm_substream *substream)
{
struct cx23885_audio_dev *chip = snd_pcm_substream_chip(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
u16 count;
count = atomic_read(&chip->count);
return runtime->period_size * (count & (runtime->periods-1));
}
/*
* page callback (needed for mmap)
*/
static struct page *snd_cx23885_page(struct snd_pcm_substream *substream,
unsigned long offset)
{
void *pageptr = substream->runtime->dma_area + offset;
return vmalloc_to_page(pageptr);
}
/*
* operators
*/
static const struct snd_pcm_ops snd_cx23885_pcm_ops = {
.open = snd_cx23885_pcm_open,
.close = snd_cx23885_close,
.hw_params = snd_cx23885_hw_params,
.hw_free = snd_cx23885_hw_free,
.prepare = snd_cx23885_prepare,
.trigger = snd_cx23885_card_trigger,
.pointer = snd_cx23885_pointer,
.page = snd_cx23885_page,
};
/*
* create a PCM device
*/
static int snd_cx23885_pcm(struct cx23885_audio_dev *chip, int device,
char *name)
{
int err;
struct snd_pcm *pcm;
err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm);
if (err < 0)
return err;
pcm->private_data = chip;
strscpy(pcm->name, name, sizeof(pcm->name));
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cx23885_pcm_ops);
return 0;
}
/****************************************************************************
Basic Flow for Sound Devices
****************************************************************************/
/*
* Alsa Constructor - Component probe
*/
struct cx23885_audio_dev *cx23885_audio_register(struct cx23885_dev *dev)
{
struct snd_card *card;
struct cx23885_audio_dev *chip;
int err;
if (disable_analog_audio)
return NULL;
if (dev->sram_channels[AUDIO_SRAM_CHANNEL].cmds_start == 0) {
pr_warn("%s(): Missing SRAM channel configuration for analog TV Audio\n",
__func__);
return NULL;
}
err = snd_card_new(&dev->pci->dev,
SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
THIS_MODULE, sizeof(struct cx23885_audio_dev), &card);
if (err < 0)
goto error_msg;
chip = (struct cx23885_audio_dev *) card->private_data;
chip->dev = dev;
chip->pci = dev->pci;
chip->card = card;
spin_lock_init(&chip->lock);
err = snd_cx23885_pcm(chip, 0, "CX23885 Digital");
if (err < 0)
goto error;
strscpy(card->driver, "CX23885", sizeof(card->driver));
sprintf(card->shortname, "Conexant CX23885");
sprintf(card->longname, "%s at %s", card->shortname, dev->name);
err = snd_card_register(card);
if (err < 0)
goto error;
dprintk(0, "registered ALSA audio device\n");
return chip;
error:
snd_card_free(card);
error_msg:
pr_err("%s(): Failed to register analog audio adapter\n",
__func__);
return NULL;
}
/*
* ALSA destructor
*/
void cx23885_audio_unregister(struct cx23885_dev *dev)
{
struct cx23885_audio_dev *chip = dev->audio_dev;
snd_card_free(chip->card);
}
| linux-master | drivers/media/pci/cx23885/cx23885-alsa.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Conexant CX23885/7/8 PCIe bridge
*
* Infrared device support routines - non-input, non-vl42_subdev routines
*
* Copyright (C) 2009 Andy Walls <[email protected]>
*/
#include "cx23885.h"
#include "cx23885-ir.h"
#include "cx23885-input.h"
#include <media/v4l2-device.h>
#define CX23885_IR_RX_FIFO_SERVICE_REQ 0
#define CX23885_IR_RX_END_OF_RX_DETECTED 1
#define CX23885_IR_RX_HW_FIFO_OVERRUN 2
#define CX23885_IR_RX_SW_FIFO_OVERRUN 3
#define CX23885_IR_TX_FIFO_SERVICE_REQ 0
void cx23885_ir_rx_work_handler(struct work_struct *work)
{
struct cx23885_dev *dev =
container_of(work, struct cx23885_dev, ir_rx_work);
u32 events = 0;
unsigned long *notifications = &dev->ir_rx_notifications;
if (test_and_clear_bit(CX23885_IR_RX_SW_FIFO_OVERRUN, notifications))
events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
if (test_and_clear_bit(CX23885_IR_RX_HW_FIFO_OVERRUN, notifications))
events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
if (test_and_clear_bit(CX23885_IR_RX_END_OF_RX_DETECTED, notifications))
events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
if (test_and_clear_bit(CX23885_IR_RX_FIFO_SERVICE_REQ, notifications))
events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
if (events == 0)
return;
if (dev->kernel_ir)
cx23885_input_rx_work_handler(dev, events);
}
void cx23885_ir_tx_work_handler(struct work_struct *work)
{
struct cx23885_dev *dev =
container_of(work, struct cx23885_dev, ir_tx_work);
u32 events = 0;
unsigned long *notifications = &dev->ir_tx_notifications;
if (test_and_clear_bit(CX23885_IR_TX_FIFO_SERVICE_REQ, notifications))
events |= V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
if (events == 0)
return;
}
/* Possibly called in an IRQ context */
void cx23885_ir_rx_v4l2_dev_notify(struct v4l2_subdev *sd, u32 events)
{
struct cx23885_dev *dev = to_cx23885(sd->v4l2_dev);
unsigned long *notifications = &dev->ir_rx_notifications;
if (events & V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ)
set_bit(CX23885_IR_RX_FIFO_SERVICE_REQ, notifications);
if (events & V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED)
set_bit(CX23885_IR_RX_END_OF_RX_DETECTED, notifications);
if (events & V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN)
set_bit(CX23885_IR_RX_HW_FIFO_OVERRUN, notifications);
if (events & V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN)
set_bit(CX23885_IR_RX_SW_FIFO_OVERRUN, notifications);
/*
* For the integrated AV core, we are already in a workqueue context.
* For the CX23888 integrated IR, we are in an interrupt context.
*/
if (sd == dev->sd_cx25840)
cx23885_ir_rx_work_handler(&dev->ir_rx_work);
else
schedule_work(&dev->ir_rx_work);
}
/* Possibly called in an IRQ context */
void cx23885_ir_tx_v4l2_dev_notify(struct v4l2_subdev *sd, u32 events)
{
struct cx23885_dev *dev = to_cx23885(sd->v4l2_dev);
unsigned long *notifications = &dev->ir_tx_notifications;
if (events & V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ)
set_bit(CX23885_IR_TX_FIFO_SERVICE_REQ, notifications);
/*
* For the integrated AV core, we are already in a workqueue context.
* For the CX23888 integrated IR, we are in an interrupt context.
*/
if (sd == dev->sd_cx25840)
cx23885_ir_tx_work_handler(&dev->ir_tx_work);
else
schedule_work(&dev->ir_tx_work);
}
| linux-master | drivers/media/pci/cx23885/cx23885-ir.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Conexant CX23885 PCIe bridge
*
* Copyright (c) 2006 Steven Toth <[email protected]>
*/
#include "cx23885.h"
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/kthread.h>
#include <linux/file.h>
#include <linux/suspend.h>
#include <media/v4l2-common.h>
#include <media/dvb_ca_en50221.h>
#include "s5h1409.h"
#include "s5h1411.h"
#include "mt2131.h"
#include "tda8290.h"
#include "tda18271.h"
#include "lgdt330x.h"
#include "xc4000.h"
#include "xc5000.h"
#include "max2165.h"
#include "tda10048.h"
#include "xc2028.h"
#include "tuner-simple.h"
#include "dib7000p.h"
#include "dib0070.h"
#include "dibx000_common.h"
#include "zl10353.h"
#include "stv0900.h"
#include "stv0900_reg.h"
#include "stv6110.h"
#include "lnbh24.h"
#include "cx24116.h"
#include "cx24117.h"
#include "cimax2.h"
#include "lgs8gxx.h"
#include "netup-eeprom.h"
#include "netup-init.h"
#include "lgdt3305.h"
#include "atbm8830.h"
#include "ts2020.h"
#include "ds3000.h"
#include "cx23885-f300.h"
#include "altera-ci.h"
#include "stv0367.h"
#include "drxk.h"
#include "mt2063.h"
#include "stv090x.h"
#include "stb6100.h"
#include "stb6100_cfg.h"
#include "tda10071.h"
#include "a8293.h"
#include "mb86a20s.h"
#include "si2165.h"
#include "si2168.h"
#include "si2157.h"
#include "sp2.h"
#include "m88ds3103.h"
#include "m88rs6000t.h"
#include "lgdt3306a.h"
static unsigned int debug;
#define dprintk(level, fmt, arg...)\
do { if (debug >= level)\
printk(KERN_DEBUG pr_fmt("%s dvb: " fmt), \
__func__, ##arg); \
} while (0)
/* ------------------------------------------------------------------ */
static unsigned int alt_tuner;
module_param(alt_tuner, int, 0644);
MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
/* ------------------------------------------------------------------ */
static int queue_setup(struct vb2_queue *q,
unsigned int *num_buffers, unsigned int *num_planes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct cx23885_tsport *port = q->drv_priv;
port->ts_packet_size = 188 * 4;
port->ts_packet_count = 32;
*num_planes = 1;
sizes[0] = port->ts_packet_size * port->ts_packet_count;
*num_buffers = 32;
return 0;
}
static int buffer_prepare(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
struct cx23885_buffer *buf =
container_of(vbuf, struct cx23885_buffer, vb);
return cx23885_buf_prepare(buf, port);
}
static void buffer_finish(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
struct cx23885_dev *dev = port->dev;
struct cx23885_buffer *buf = container_of(vbuf,
struct cx23885_buffer, vb);
cx23885_free_buffer(dev, buf);
}
static void buffer_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
struct cx23885_buffer *buf = container_of(vbuf,
struct cx23885_buffer, vb);
cx23885_buf_queue(port, buf);
}
static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
{
struct vb2_dvb_frontends *f;
struct vb2_dvb_frontend *fe;
f = &port->frontends;
if (f->gate <= 1) /* undefined or fe0 */
fe = vb2_dvb_get_frontend(f, 1);
else
fe = vb2_dvb_get_frontend(f, f->gate);
if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
}
static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
{
struct cx23885_tsport *port = q->drv_priv;
struct cx23885_dmaqueue *dmaq = &port->mpegq;
struct cx23885_buffer *buf = list_entry(dmaq->active.next,
struct cx23885_buffer, queue);
cx23885_start_dma(port, dmaq, buf);
return 0;
}
static void cx23885_stop_streaming(struct vb2_queue *q)
{
struct cx23885_tsport *port = q->drv_priv;
cx23885_cancel_buffers(port);
}
static const struct vb2_ops dvb_qops = {
.queue_setup = queue_setup,
.buf_prepare = buffer_prepare,
.buf_finish = buffer_finish,
.buf_queue = buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = cx23885_start_streaming,
.stop_streaming = cx23885_stop_streaming,
};
static struct s5h1409_config hauppauge_generic_config = {
.demod_address = 0x32 >> 1,
.output_mode = S5H1409_SERIAL_OUTPUT,
.gpio = S5H1409_GPIO_ON,
.qam_if = 44000,
.inversion = S5H1409_INVERSION_OFF,
.status_mode = S5H1409_DEMODLOCKING,
.mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static struct tda10048_config hauppauge_hvr1200_config = {
.demod_address = 0x10 >> 1,
.output_mode = TDA10048_SERIAL_OUTPUT,
.fwbulkwritelen = TDA10048_BULKWRITE_200,
.inversion = TDA10048_INVERSION_ON,
.dtv6_if_freq_khz = TDA10048_IF_3300,
.dtv7_if_freq_khz = TDA10048_IF_3800,
.dtv8_if_freq_khz = TDA10048_IF_4300,
.clk_freq_khz = TDA10048_CLK_16000,
};
static struct tda10048_config hauppauge_hvr1210_config = {
.demod_address = 0x10 >> 1,
.output_mode = TDA10048_SERIAL_OUTPUT,
.fwbulkwritelen = TDA10048_BULKWRITE_200,
.inversion = TDA10048_INVERSION_ON,
.dtv6_if_freq_khz = TDA10048_IF_3300,
.dtv7_if_freq_khz = TDA10048_IF_3500,
.dtv8_if_freq_khz = TDA10048_IF_4000,
.clk_freq_khz = TDA10048_CLK_16000,
};
static struct s5h1409_config hauppauge_ezqam_config = {
.demod_address = 0x32 >> 1,
.output_mode = S5H1409_SERIAL_OUTPUT,
.gpio = S5H1409_GPIO_OFF,
.qam_if = 4000,
.inversion = S5H1409_INVERSION_ON,
.status_mode = S5H1409_DEMODLOCKING,
.mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static struct s5h1409_config hauppauge_hvr1800lp_config = {
.demod_address = 0x32 >> 1,
.output_mode = S5H1409_SERIAL_OUTPUT,
.gpio = S5H1409_GPIO_OFF,
.qam_if = 44000,
.inversion = S5H1409_INVERSION_OFF,
.status_mode = S5H1409_DEMODLOCKING,
.mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static struct s5h1409_config hauppauge_hvr1500_config = {
.demod_address = 0x32 >> 1,
.output_mode = S5H1409_SERIAL_OUTPUT,
.gpio = S5H1409_GPIO_OFF,
.inversion = S5H1409_INVERSION_OFF,
.status_mode = S5H1409_DEMODLOCKING,
.mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static struct mt2131_config hauppauge_generic_tunerconfig = {
0x61
};
static struct lgdt330x_config fusionhdtv_5_express = {
.demod_chip = LGDT3303,
.serial_mpeg = 0x40,
};
static struct s5h1409_config hauppauge_hvr1500q_config = {
.demod_address = 0x32 >> 1,
.output_mode = S5H1409_SERIAL_OUTPUT,
.gpio = S5H1409_GPIO_ON,
.qam_if = 44000,
.inversion = S5H1409_INVERSION_OFF,
.status_mode = S5H1409_DEMODLOCKING,
.mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static struct s5h1409_config dvico_s5h1409_config = {
.demod_address = 0x32 >> 1,
.output_mode = S5H1409_SERIAL_OUTPUT,
.gpio = S5H1409_GPIO_ON,
.qam_if = 44000,
.inversion = S5H1409_INVERSION_OFF,
.status_mode = S5H1409_DEMODLOCKING,
.mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static struct s5h1411_config dvico_s5h1411_config = {
.output_mode = S5H1411_SERIAL_OUTPUT,
.gpio = S5H1411_GPIO_ON,
.qam_if = S5H1411_IF_44000,
.vsb_if = S5H1411_IF_44000,
.inversion = S5H1411_INVERSION_OFF,
.status_mode = S5H1411_DEMODLOCKING,
.mpeg_timing = S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static struct s5h1411_config hcw_s5h1411_config = {
.output_mode = S5H1411_SERIAL_OUTPUT,
.gpio = S5H1411_GPIO_OFF,
.vsb_if = S5H1411_IF_44000,
.qam_if = S5H1411_IF_4000,
.inversion = S5H1411_INVERSION_ON,
.status_mode = S5H1411_DEMODLOCKING,
.mpeg_timing = S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
.i2c_address = 0x61,
.if_khz = 5380,
};
static struct xc5000_config dvico_xc5000_tunerconfig = {
.i2c_address = 0x64,
.if_khz = 5380,
};
static struct tda829x_config tda829x_no_probe = {
.probe_tuner = TDA829X_DONT_PROBE,
};
static struct tda18271_std_map hauppauge_tda18271_std_map = {
.atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
.if_lvl = 6, .rfagc_top = 0x37 },
.qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
.if_lvl = 6, .rfagc_top = 0x37 },
};
static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
.dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
.if_lvl = 1, .rfagc_top = 0x37, },
.dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
.if_lvl = 1, .rfagc_top = 0x37, },
.dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
.if_lvl = 1, .rfagc_top = 0x37, },
};
static struct tda18271_config hauppauge_tda18271_config = {
.std_map = &hauppauge_tda18271_std_map,
.gate = TDA18271_GATE_ANALOG,
.output_opt = TDA18271_OUTPUT_LT_OFF,
};
static struct tda18271_config hauppauge_hvr1200_tuner_config = {
.std_map = &hauppauge_hvr1200_tda18271_std_map,
.gate = TDA18271_GATE_ANALOG,
.output_opt = TDA18271_OUTPUT_LT_OFF,
};
static struct tda18271_config hauppauge_hvr1210_tuner_config = {
.gate = TDA18271_GATE_DIGITAL,
.output_opt = TDA18271_OUTPUT_LT_OFF,
};
static struct tda18271_config hauppauge_hvr4400_tuner_config = {
.gate = TDA18271_GATE_DIGITAL,
.output_opt = TDA18271_OUTPUT_LT_OFF,
};
static struct tda18271_std_map hauppauge_hvr127x_std_map = {
.atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
.if_lvl = 1, .rfagc_top = 0x58 },
.qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
.if_lvl = 1, .rfagc_top = 0x58 },
};
static struct tda18271_config hauppauge_hvr127x_config = {
.std_map = &hauppauge_hvr127x_std_map,
.output_opt = TDA18271_OUTPUT_LT_OFF,
};
static struct lgdt3305_config hauppauge_lgdt3305_config = {
.i2c_addr = 0x0e,
.mpeg_mode = LGDT3305_MPEG_SERIAL,
.tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
.tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
.deny_i2c_rptr = 1,
.spectral_inversion = 1,
.qam_if_khz = 4000,
.vsb_if_khz = 3250,
};
static struct dibx000_agc_config xc3028_agc_config = {
BAND_VHF | BAND_UHF, /* band_caps */
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
* P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
* P_agc_nb_est=2, P_agc_write=0
*/
(0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
(3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
712, /* inv_gain */
21, /* time_stabiliz */
0, /* alpha_level */
118, /* thlock */
0, /* wbd_inv */
2867, /* wbd_ref */
0, /* wbd_sel */
2, /* wbd_alpha */
0, /* agc1_max */
0, /* agc1_min */
39718, /* agc2_max */
9930, /* agc2_min */
0, /* agc1_pt1 */
0, /* agc1_pt2 */
0, /* agc1_pt3 */
0, /* agc1_slope1 */
0, /* agc1_slope2 */
0, /* agc2_pt1 */
128, /* agc2_pt2 */
29, /* agc2_slope1 */
29, /* agc2_slope2 */
17, /* alpha_mant */
27, /* alpha_exp */
23, /* beta_mant */
51, /* beta_exp */
1, /* perform_agc_softsplit */
};
/* PLL Configuration for COFDM BW_MHz = 8.000000
* With external clock = 30.000000 */
static struct dibx000_bandwidth_config xc3028_bw_config = {
60000, /* internal */
30000, /* sampling */
1, /* pll_cfg: prediv */
8, /* pll_cfg: ratio */
3, /* pll_cfg: range */
1, /* pll_cfg: reset */
0, /* pll_cfg: bypass */
0, /* misc: refdiv */
0, /* misc: bypclk_div */
1, /* misc: IO_CLK_en_core */
1, /* misc: ADClkSrc */
0, /* misc: modulo */
(3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
(1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
20452225, /* timf */
30000000 /* xtal_hz */
};
static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
.output_mpeg2_in_188_bytes = 1,
.hostbus_diversity = 1,
.tuner_is_baseband = 0,
.update_lna = NULL,
.agc_config_count = 1,
.agc = &xc3028_agc_config,
.bw = &xc3028_bw_config,
.gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
.gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
.gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
.pwm_freq_div = 0,
.agc_control = NULL,
.spur_protect = 0,
.output_mode = OUTMODE_MPEG2_SERIAL,
};
static struct zl10353_config dvico_fusionhdtv_xc3028 = {
.demod_address = 0x0f,
.if2 = 45600,
.no_tuner = 1,
.disable_i2c_gate_ctrl = 1,
};
static struct stv0900_reg stv0900_ts_regs[] = {
{ R0900_TSGENERAL, 0x00 },
{ R0900_P1_TSSPEED, 0x40 },
{ R0900_P2_TSSPEED, 0x40 },
{ R0900_P1_TSCFGM, 0xc0 },
{ R0900_P2_TSCFGM, 0xc0 },
{ R0900_P1_TSCFGH, 0xe0 },
{ R0900_P2_TSCFGH, 0xe0 },
{ R0900_P1_TSCFGL, 0x20 },
{ R0900_P2_TSCFGL, 0x20 },
{ 0xffff, 0xff }, /* terminate */
};
static struct stv0900_config netup_stv0900_config = {
.demod_address = 0x68,
.demod_mode = 1, /* dual */
.xtal = 8000000,
.clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
.diseqc_mode = 2,/* 2/3 PWM */
.ts_config_regs = stv0900_ts_regs,
.tun1_maddress = 0,/* 0x60 */
.tun2_maddress = 3,/* 0x63 */
.tun1_adc = 1,/* 1 Vpp */
.tun2_adc = 1,/* 1 Vpp */
};
static struct stv6110_config netup_stv6110_tunerconfig_a = {
.i2c_address = 0x60,
.mclk = 16000000,
.clk_div = 1,
.gain = 8, /* +16 dB - maximum gain */
};
static struct stv6110_config netup_stv6110_tunerconfig_b = {
.i2c_address = 0x63,
.mclk = 16000000,
.clk_div = 1,
.gain = 8, /* +16 dB - maximum gain */
};
static struct cx24116_config tbs_cx24116_config = {
.demod_address = 0x55,
};
static struct cx24117_config tbs_cx24117_config = {
.demod_address = 0x55,
};
static struct ds3000_config tevii_ds3000_config = {
.demod_address = 0x68,
};
static struct ts2020_config tevii_ts2020_config = {
.tuner_address = 0x60,
.clk_out_div = 1,
.frequency_div = 1146000,
};
static struct cx24116_config dvbworld_cx24116_config = {
.demod_address = 0x05,
};
static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
.prod = LGS8GXX_PROD_LGS8GL5,
.demod_address = 0x19,
.serial_ts = 0,
.ts_clk_pol = 1,
.ts_clk_gated = 1,
.if_clk_freq = 30400, /* 30.4 MHz */
.if_freq = 5380, /* 5.38 MHz */
.if_neg_center = 1,
.ext_adc = 0,
.adc_signed = 0,
.if_neg_edge = 0,
};
static struct xc5000_config mygica_x8506_xc5000_config = {
.i2c_address = 0x61,
.if_khz = 5380,
};
static struct mb86a20s_config mygica_x8507_mb86a20s_config = {
.demod_address = 0x10,
};
static struct xc5000_config mygica_x8507_xc5000_config = {
.i2c_address = 0x61,
.if_khz = 4000,
};
static struct stv090x_config prof_8000_stv090x_config = {
.device = STV0903,
.demod_mode = STV090x_SINGLE,
.clk_mode = STV090x_CLK_EXT,
.xtal = 27000000,
.address = 0x6A,
.ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
.repeater_level = STV090x_RPTLEVEL_64,
.adc1_range = STV090x_ADC_2Vpp,
.diseqc_envelope_mode = false,
.tuner_get_frequency = stb6100_get_frequency,
.tuner_set_frequency = stb6100_set_frequency,
.tuner_set_bandwidth = stb6100_set_bandwidth,
.tuner_get_bandwidth = stb6100_get_bandwidth,
};
static struct stb6100_config prof_8000_stb6100_config = {
.tuner_address = 0x60,
.refclock = 27000000,
};
static struct lgdt3306a_config hauppauge_quadHD_ATSC_a_config = {
.i2c_addr = 0x59,
.qam_if_khz = 4000,
.vsb_if_khz = 3250,
.deny_i2c_rptr = 1, /* Disabled */
.spectral_inversion = 0, /* Disabled */
.mpeg_mode = LGDT3306A_MPEG_SERIAL,
.tpclk_edge = LGDT3306A_TPCLK_RISING_EDGE,
.tpvalid_polarity = LGDT3306A_TP_VALID_HIGH,
.xtalMHz = 25, /* 24 or 25 */
};
static struct lgdt3306a_config hauppauge_quadHD_ATSC_b_config = {
.i2c_addr = 0x0e,
.qam_if_khz = 4000,
.vsb_if_khz = 3250,
.deny_i2c_rptr = 1, /* Disabled */
.spectral_inversion = 0, /* Disabled */
.mpeg_mode = LGDT3306A_MPEG_SERIAL,
.tpclk_edge = LGDT3306A_TPCLK_RISING_EDGE,
.tpvalid_polarity = LGDT3306A_TP_VALID_HIGH,
.xtalMHz = 25, /* 24 or 25 */
};
static int p8000_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx23885_tsport *port = fe->dvb->priv;
struct cx23885_dev *dev = port->dev;
if (voltage == SEC_VOLTAGE_18)
cx_write(MC417_RWD, 0x00001e00);
else if (voltage == SEC_VOLTAGE_13)
cx_write(MC417_RWD, 0x00001a00);
else
cx_write(MC417_RWD, 0x00001800);
return 0;
}
static int dvbsky_t9580_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx23885_tsport *port = fe->dvb->priv;
struct cx23885_dev *dev = port->dev;
cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
switch (voltage) {
case SEC_VOLTAGE_13:
cx23885_gpio_set(dev, GPIO_1);
cx23885_gpio_clear(dev, GPIO_0);
break;
case SEC_VOLTAGE_18:
cx23885_gpio_set(dev, GPIO_1);
cx23885_gpio_set(dev, GPIO_0);
break;
case SEC_VOLTAGE_OFF:
cx23885_gpio_clear(dev, GPIO_1);
cx23885_gpio_clear(dev, GPIO_0);
break;
}
/* call the frontend set_voltage function */
port->fe_set_voltage(fe, voltage);
return 0;
}
static int dvbsky_s952_portc_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx23885_tsport *port = fe->dvb->priv;
struct cx23885_dev *dev = port->dev;
cx23885_gpio_enable(dev, GPIO_12 | GPIO_13, 1);
switch (voltage) {
case SEC_VOLTAGE_13:
cx23885_gpio_set(dev, GPIO_13);
cx23885_gpio_clear(dev, GPIO_12);
break;
case SEC_VOLTAGE_18:
cx23885_gpio_set(dev, GPIO_13);
cx23885_gpio_set(dev, GPIO_12);
break;
case SEC_VOLTAGE_OFF:
cx23885_gpio_clear(dev, GPIO_13);
cx23885_gpio_clear(dev, GPIO_12);
break;
}
/* call the frontend set_voltage function */
return port->fe_set_voltage(fe, voltage);
}
static int cx23885_sp2_ci_ctrl(void *priv, u8 read, int addr,
u8 data, int *mem)
{
/* MC417 */
#define SP2_DATA 0x000000ff
#define SP2_WR 0x00008000
#define SP2_RD 0x00004000
#define SP2_ACK 0x00001000
#define SP2_ADHI 0x00000800
#define SP2_ADLO 0x00000400
#define SP2_CS1 0x00000200
#define SP2_CS0 0x00000100
#define SP2_EN_ALL 0x00001000
#define SP2_CTRL_OFF (SP2_CS1 | SP2_CS0 | SP2_WR | SP2_RD)
struct cx23885_tsport *port = priv;
struct cx23885_dev *dev = port->dev;
int ret;
int tmp = 0;
unsigned long timeout;
mutex_lock(&dev->gpio_lock);
/* write addr */
cx_write(MC417_OEN, SP2_EN_ALL);
cx_write(MC417_RWD, SP2_CTRL_OFF |
SP2_ADLO | (0xff & addr));
cx_clear(MC417_RWD, SP2_ADLO);
cx_write(MC417_RWD, SP2_CTRL_OFF |
SP2_ADHI | (0xff & (addr >> 8)));
cx_clear(MC417_RWD, SP2_ADHI);
if (read)
/* data in */
cx_write(MC417_OEN, SP2_EN_ALL | SP2_DATA);
else
/* data out */
cx_write(MC417_RWD, SP2_CTRL_OFF | data);
/* chip select 0 */
cx_clear(MC417_RWD, SP2_CS0);
/* read/write */
cx_clear(MC417_RWD, (read) ? SP2_RD : SP2_WR);
/* wait for a maximum of 1 msec */
timeout = jiffies + msecs_to_jiffies(1);
while (!time_after(jiffies, timeout)) {
tmp = cx_read(MC417_RWD);
if ((tmp & SP2_ACK) == 0)
break;
usleep_range(50, 100);
}
cx_set(MC417_RWD, SP2_CTRL_OFF);
*mem = tmp & 0xff;
mutex_unlock(&dev->gpio_lock);
if (!read) {
if (*mem < 0) {
ret = -EREMOTEIO;
goto err;
}
}
return 0;
err:
return ret;
}
static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct cx23885_tsport *port = fe->dvb->priv;
struct cx23885_dev *dev = port->dev;
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1275:
switch (p->modulation) {
case VSB_8:
cx23885_gpio_clear(dev, GPIO_5);
break;
case QAM_64:
case QAM_256:
default:
cx23885_gpio_set(dev, GPIO_5);
break;
}
break;
case CX23885_BOARD_MYGICA_X8506:
case CX23885_BOARD_MYGICA_X8507:
case CX23885_BOARD_MAGICPRO_PROHDTVE2:
/* Select Digital TV */
cx23885_gpio_set(dev, GPIO_0);
break;
}
/* Call the real set_frontend */
if (port->set_frontend)
return port->set_frontend(fe);
return 0;
}
static void cx23885_set_frontend_hook(struct cx23885_tsport *port,
struct dvb_frontend *fe)
{
port->set_frontend = fe->ops.set_frontend;
fe->ops.set_frontend = cx23885_dvb_set_frontend;
}
static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
.prod = LGS8GXX_PROD_LGS8G75,
.demod_address = 0x19,
.serial_ts = 0,
.ts_clk_pol = 1,
.ts_clk_gated = 1,
.if_clk_freq = 30400, /* 30.4 MHz */
.if_freq = 6500, /* 6.50 MHz */
.if_neg_center = 1,
.ext_adc = 0,
.adc_signed = 1,
.adc_vpp = 2, /* 1.6 Vpp */
.if_neg_edge = 1,
};
static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
.i2c_address = 0x61,
.if_khz = 6500,
};
static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
.prod = ATBM8830_PROD_8830,
.demod_address = 0x44,
.serial_ts = 0,
.ts_sampling_edge = 1,
.ts_clk_gated = 0,
.osc_clk_freq = 30400, /* in kHz */
.if_freq = 0, /* zero IF */
.zif_swap_iq = 1,
.agc_min = 0x2E,
.agc_max = 0xFF,
.agc_hold_loop = 0,
};
static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
.i2c_address = 0x60,
.osc_clk = 20
};
static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
.prod = ATBM8830_PROD_8830,
.demod_address = 0x44,
.serial_ts = 1,
.ts_sampling_edge = 1,
.ts_clk_gated = 0,
.osc_clk_freq = 30400, /* in kHz */
.if_freq = 0, /* zero IF */
.zif_swap_iq = 1,
.agc_min = 0x2E,
.agc_max = 0xFF,
.agc_hold_loop = 0,
};
static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
.i2c_address = 0x60,
.osc_clk = 20
};
static struct stv0367_config netup_stv0367_config[] = {
{
.demod_address = 0x1c,
.xtal = 27000000,
.if_khz = 4500,
.if_iq_mode = 0,
.ts_mode = 1,
.clk_pol = 0,
}, {
.demod_address = 0x1d,
.xtal = 27000000,
.if_khz = 4500,
.if_iq_mode = 0,
.ts_mode = 1,
.clk_pol = 0,
},
};
static struct xc5000_config netup_xc5000_config[] = {
{
.i2c_address = 0x61,
.if_khz = 4500,
}, {
.i2c_address = 0x64,
.if_khz = 4500,
},
};
static struct drxk_config terratec_drxk_config[] = {
{
.adr = 0x29,
.no_i2c_bridge = 1,
}, {
.adr = 0x2a,
.no_i2c_bridge = 1,
},
};
static struct mt2063_config terratec_mt2063_config[] = {
{
.tuner_address = 0x60,
}, {
.tuner_address = 0x67,
},
};
static const struct tda10071_platform_data hauppauge_tda10071_pdata = {
.clk = 40444000, /* 40.444 MHz */
.i2c_wr_max = 64,
.ts_mode = TDA10071_TS_SERIAL,
.pll_multiplier = 20,
.tuner_i2c_addr = 0x54,
};
static const struct m88ds3103_config dvbsky_t9580_m88ds3103_config = {
.i2c_addr = 0x68,
.clock = 27000000,
.i2c_wr_max = 33,
.clock_out = 0,
.ts_mode = M88DS3103_TS_PARALLEL,
.ts_clk = 16000,
.ts_clk_pol = 1,
.lnb_en_pol = 1,
.lnb_hv_pol = 0,
.agc = 0x99,
};
static const struct m88ds3103_config dvbsky_s950c_m88ds3103_config = {
.i2c_addr = 0x68,
.clock = 27000000,
.i2c_wr_max = 33,
.clock_out = 0,
.ts_mode = M88DS3103_TS_CI,
.ts_clk = 10000,
.ts_clk_pol = 1,
.lnb_en_pol = 1,
.lnb_hv_pol = 0,
.agc = 0x99,
};
static const struct m88ds3103_config hauppauge_hvr5525_m88ds3103_config = {
.i2c_addr = 0x69,
.clock = 27000000,
.i2c_wr_max = 33,
.ts_mode = M88DS3103_TS_PARALLEL,
.ts_clk = 16000,
.ts_clk_pol = 1,
.agc = 0x99,
};
static struct lgdt3306a_config hauppauge_hvr1265k4_config = {
.i2c_addr = 0x59,
.qam_if_khz = 4000,
.vsb_if_khz = 3250,
.deny_i2c_rptr = 1, /* Disabled */
.spectral_inversion = 0, /* Disabled */
.mpeg_mode = LGDT3306A_MPEG_SERIAL,
.tpclk_edge = LGDT3306A_TPCLK_RISING_EDGE,
.tpvalid_polarity = LGDT3306A_TP_VALID_HIGH,
.xtalMHz = 25, /* 24 or 25 */
};
static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
{
struct cx23885_dev *dev = (struct cx23885_dev *)device;
unsigned long timeout = jiffies + msecs_to_jiffies(1);
uint32_t mem = 0;
mem = cx_read(MC417_RWD);
if (read)
cx_set(MC417_OEN, ALT_DATA);
else {
cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
mem &= ~ALT_DATA;
mem |= (data & ALT_DATA);
}
if (flag)
mem |= ALT_AD_RG;
else
mem &= ~ALT_AD_RG;
mem &= ~ALT_CS;
if (read)
mem = (mem & ~ALT_RD) | ALT_WR;
else
mem = (mem & ~ALT_WR) | ALT_RD;
cx_write(MC417_RWD, mem); /* start RW cycle */
for (;;) {
mem = cx_read(MC417_RWD);
if ((mem & ALT_RDY) == 0)
break;
if (time_after(jiffies, timeout))
break;
udelay(1);
}
cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
if (read)
return mem & ALT_DATA;
return 0;
};
static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff)
{
struct dib7000p_ops *dib7000p_ops = fe->sec_priv;
return dib7000p_ops->set_gpio(fe, 8, 0, !onoff);
}
static int dib7070_tuner_sleep(struct dvb_frontend *fe, int onoff)
{
return 0;
}
static struct dib0070_config dib7070p_dib0070_config = {
.i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
.reset = dib7070_tuner_reset,
.sleep = dib7070_tuner_sleep,
.clock_khz = 12000,
.freq_offset_khz_vhf = 550,
/* .flip_chip = 1, */
};
/* DIB7070 generic */
static struct dibx000_agc_config dib7070_agc_config = {
.band_caps = BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
/*
* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5,
* P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
* P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0
*/
.setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) |
(0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
.inv_gain = 600,
.time_stabiliz = 10,
.alpha_level = 0,
.thlock = 118,
.wbd_inv = 0,
.wbd_ref = 3530,
.wbd_sel = 1,
.wbd_alpha = 5,
.agc1_max = 65535,
.agc1_min = 0,
.agc2_max = 65535,
.agc2_min = 0,
.agc1_pt1 = 0,
.agc1_pt2 = 40,
.agc1_pt3 = 183,
.agc1_slope1 = 206,
.agc1_slope2 = 255,
.agc2_pt1 = 72,
.agc2_pt2 = 152,
.agc2_slope1 = 88,
.agc2_slope2 = 90,
.alpha_mant = 17,
.alpha_exp = 27,
.beta_mant = 23,
.beta_exp = 51,
.perform_agc_softsplit = 0,
};
static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = {
.internal = 60000,
.sampling = 15000,
.pll_prediv = 1,
.pll_ratio = 20,
.pll_range = 3,
.pll_reset = 1,
.pll_bypass = 0,
.enable_refdiv = 0,
.bypclk_div = 0,
.IO_CLK_en_core = 1,
.ADClkSrc = 1,
.modulo = 2,
/* refsel, sel, freq_15k */
.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
.ifreq = (0 << 25) | 0,
.timf = 20452225,
.xtal_hz = 12000000,
};
static struct dib7000p_config dib7070p_dib7000p_config = {
/* .output_mode = OUTMODE_MPEG2_FIFO, */
.output_mode = OUTMODE_MPEG2_SERIAL,
/* .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK, */
.output_mpeg2_in_188_bytes = 1,
.agc_config_count = 1,
.agc = &dib7070_agc_config,
.bw = &dib7070_bw_config_12_mhz,
.tuner_is_baseband = 1,
.spur_protect = 1,
.gpio_dir = 0xfcef, /* DIB7000P_GPIO_DEFAULT_DIRECTIONS, */
.gpio_val = 0x0110, /* DIB7000P_GPIO_DEFAULT_VALUES, */
.gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
.hostbus_diversity = 1,
};
static int dvb_register_ci_mac(struct cx23885_tsport *port)
{
struct cx23885_dev *dev = port->dev;
struct i2c_client *client_ci = NULL;
struct vb2_dvb_frontend *fe0;
fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
if (!fe0)
return -EINVAL;
switch (dev->board) {
case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
static struct netup_card_info cinfo;
netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
memcpy(port->frontends.adapter.proposed_mac,
cinfo.port[port->nr - 1].mac, 6);
pr_info("NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
port->nr, port->frontends.adapter.proposed_mac);
netup_ci_init(port);
return 0;
}
case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
struct altera_ci_config netup_ci_cfg = {
.dev = dev,/* magic number to identify*/
.adapter = &port->frontends.adapter,/* for CI */
.demux = &fe0->dvb.demux,/* for hw pid filter */
.fpga_rw = netup_altera_fpga_rw,
};
altera_ci_init(&netup_ci_cfg, port->nr);
return 0;
}
case CX23885_BOARD_TEVII_S470: {
u8 eeprom[256]; /* 24C02 i2c eeprom */
if (port->nr != 1)
return 0;
/* Read entire EEPROM */
dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
pr_info("TeVii S470 MAC= %pM\n", eeprom + 0xa0);
memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
return 0;
}
case CX23885_BOARD_DVBSKY_T9580:
case CX23885_BOARD_DVBSKY_S950:
case CX23885_BOARD_DVBSKY_S952:
case CX23885_BOARD_DVBSKY_T982: {
u8 eeprom[256]; /* 24C02 i2c eeprom */
if (port->nr > 2)
return 0;
/* Read entire EEPROM */
dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom,
sizeof(eeprom));
pr_info("%s port %d MAC address: %pM\n",
cx23885_boards[dev->board].name, port->nr,
eeprom + 0xc0 + (port->nr-1) * 8);
memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xc0 +
(port->nr-1) * 8, 6);
return 0;
}
case CX23885_BOARD_DVBSKY_S950C:
case CX23885_BOARD_DVBSKY_T980C:
case CX23885_BOARD_TT_CT2_4500_CI: {
u8 eeprom[256]; /* 24C02 i2c eeprom */
struct sp2_config sp2_config;
struct i2c_board_info info;
struct cx23885_i2c *i2c_bus = &dev->i2c_bus[0];
/* attach CI */
memset(&sp2_config, 0, sizeof(sp2_config));
sp2_config.dvb_adap = &port->frontends.adapter;
sp2_config.priv = port;
sp2_config.ci_control = cx23885_sp2_ci_ctrl;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "sp2", I2C_NAME_SIZE);
info.addr = 0x40;
info.platform_data = &sp2_config;
request_module(info.type);
client_ci = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
if (!i2c_client_has_driver(client_ci))
return -ENODEV;
if (!try_module_get(client_ci->dev.driver->owner)) {
i2c_unregister_device(client_ci);
return -ENODEV;
}
port->i2c_client_ci = client_ci;
if (port->nr != 1)
return 0;
/* Read entire EEPROM */
dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom,
sizeof(eeprom));
pr_info("%s MAC address: %pM\n",
cx23885_boards[dev->board].name, eeprom + 0xc0);
memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xc0, 6);
return 0;
}
}
return 0;
}
static int dvb_register(struct cx23885_tsport *port)
{
struct dib7000p_ops dib7000p_ops;
struct cx23885_dev *dev = port->dev;
struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
struct vb2_dvb_frontend *fe0, *fe1 = NULL;
struct si2168_config si2168_config;
struct si2165_platform_data si2165_pdata;
struct si2157_config si2157_config;
struct ts2020_config ts2020_config;
struct m88ds3103_platform_data m88ds3103_pdata;
struct m88rs6000t_config m88rs6000t_config = {};
struct a8293_platform_data a8293_pdata = {};
struct i2c_board_info info;
struct i2c_adapter *adapter;
struct i2c_client *client_demod = NULL, *client_tuner = NULL;
struct i2c_client *client_sec = NULL;
int (*p_set_voltage)(struct dvb_frontend *fe,
enum fe_sec_voltage voltage) = NULL;
int mfe_shared = 0; /* bus not shared by default */
int ret;
/* Get the first frontend */
fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
if (!fe0)
return -EINVAL;
/* init struct vb2_dvb */
fe0->dvb.name = dev->name;
/* multi-frontend gate control is undefined or defaults to fe0 */
port->frontends.gate = 0;
/* Sets the gate control callback to be used by i2c command calls */
port->gate_ctrl = cx23885_dvb_gate_ctrl;
/* init frontend */
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1250:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(s5h1409_attach,
&hauppauge_generic_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(mt2131_attach, fe0->dvb.frontend,
&i2c_bus->i2c_adap,
&hauppauge_generic_tunerconfig, 0);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1270:
case CX23885_BOARD_HAUPPAUGE_HVR1275:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
&hauppauge_lgdt3305_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_bus[1].i2c_adap,
&hauppauge_hvr127x_config);
if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275)
cx23885_set_frontend_hook(port, fe0->dvb.frontend);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1255:
case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(s5h1411_attach,
&hcw_s5h1411_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_bus[1].i2c_adap,
&hauppauge_tda18271_config);
tda18271_attach(&dev->ts1.analog_fe,
0x60, &dev->i2c_bus[1].i2c_adap,
&hauppauge_tda18271_config);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1800:
i2c_bus = &dev->i2c_bus[0];
switch (alt_tuner) {
case 1:
fe0->dvb.frontend =
dvb_attach(s5h1409_attach,
&hauppauge_ezqam_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(tda829x_attach, fe0->dvb.frontend,
&dev->i2c_bus[1].i2c_adap, 0x42,
&tda829x_no_probe);
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_bus[1].i2c_adap,
&hauppauge_tda18271_config);
break;
case 0:
default:
fe0->dvb.frontend =
dvb_attach(s5h1409_attach,
&hauppauge_generic_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(mt2131_attach, fe0->dvb.frontend,
&i2c_bus->i2c_adap,
&hauppauge_generic_tunerconfig, 0);
}
break;
case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(s5h1409_attach,
&hauppauge_hvr1800lp_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(mt2131_attach, fe0->dvb.frontend,
&i2c_bus->i2c_adap,
&hauppauge_generic_tunerconfig, 0);
break;
case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
&fusionhdtv_5_express,
0x0e,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&i2c_bus->i2c_adap, 0x61,
TUNER_LG_TDVS_H06XF);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
i2c_bus = &dev->i2c_bus[1];
fe0->dvb.frontend = dvb_attach(s5h1409_attach,
&hauppauge_hvr1500q_config,
&dev->i2c_bus[0].i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(xc5000_attach, fe0->dvb.frontend,
&i2c_bus->i2c_adap,
&hauppauge_hvr1500q_tunerconfig);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1500:
i2c_bus = &dev->i2c_bus[1];
fe0->dvb.frontend = dvb_attach(s5h1409_attach,
&hauppauge_hvr1500_config,
&dev->i2c_bus[0].i2c_adap);
if (fe0->dvb.frontend != NULL) {
struct dvb_frontend *fe;
struct xc2028_config cfg = {
.i2c_adap = &i2c_bus->i2c_adap,
.i2c_addr = 0x61,
};
static struct xc2028_ctrl ctl = {
.fname = XC2028_DEFAULT_FIRMWARE,
.max_len = 64,
.demod = XC3028_FE_OREN538,
};
fe = dvb_attach(xc2028_attach,
fe0->dvb.frontend, &cfg);
if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
fe->ops.tuner_ops.set_config(fe, &ctl);
}
break;
case CX23885_BOARD_HAUPPAUGE_HVR1200:
case CX23885_BOARD_HAUPPAUGE_HVR1700:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(tda10048_attach,
&hauppauge_hvr1200_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(tda829x_attach, fe0->dvb.frontend,
&dev->i2c_bus[1].i2c_adap, 0x42,
&tda829x_no_probe);
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_bus[1].i2c_adap,
&hauppauge_hvr1200_tuner_config);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1210:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(tda10048_attach,
&hauppauge_hvr1210_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend != NULL) {
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_bus[1].i2c_adap,
&hauppauge_hvr1210_tuner_config);
}
break;
case CX23885_BOARD_HAUPPAUGE_HVR1400:
i2c_bus = &dev->i2c_bus[0];
if (!dvb_attach(dib7000p_attach, &dib7000p_ops))
return -ENODEV;
fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap,
0x12, &hauppauge_hvr1400_dib7000_config);
if (fe0->dvb.frontend != NULL) {
struct dvb_frontend *fe;
struct xc2028_config cfg = {
.i2c_adap = &dev->i2c_bus[1].i2c_adap,
.i2c_addr = 0x64,
};
static struct xc2028_ctrl ctl = {
.fname = XC3028L_DEFAULT_FIRMWARE,
.max_len = 64,
.demod = XC3028_FE_DIBCOM52,
/* This is true for all demods with
v36 firmware? */
.type = XC2028_D2633,
};
fe = dvb_attach(xc2028_attach,
fe0->dvb.frontend, &cfg);
if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
fe->ops.tuner_ops.set_config(fe, &ctl);
}
break;
case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
i2c_bus = &dev->i2c_bus[port->nr - 1];
fe0->dvb.frontend = dvb_attach(s5h1409_attach,
&dvico_s5h1409_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
fe0->dvb.frontend = dvb_attach(s5h1411_attach,
&dvico_s5h1411_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend != NULL)
dvb_attach(xc5000_attach, fe0->dvb.frontend,
&i2c_bus->i2c_adap,
&dvico_xc5000_tunerconfig);
break;
case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
i2c_bus = &dev->i2c_bus[port->nr - 1];
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&dvico_fusionhdtv_xc3028,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend != NULL) {
struct dvb_frontend *fe;
struct xc2028_config cfg = {
.i2c_adap = &i2c_bus->i2c_adap,
.i2c_addr = 0x61,
};
static struct xc2028_ctrl ctl = {
.fname = XC2028_DEFAULT_FIRMWARE,
.max_len = 64,
.demod = XC3028_FE_ZARLINK456,
};
fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
&cfg);
if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
fe->ops.tuner_ops.set_config(fe, &ctl);
}
break;
}
case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: {
i2c_bus = &dev->i2c_bus[port->nr - 1];
/* cxusb_ctrl_msg(adap->dev, CMD_DIGITAL, NULL, 0, NULL, 0); */
/* cxusb_bluebird_gpio_pulse(adap->dev, 0x02, 1); */
if (!dvb_attach(dib7000p_attach, &dib7000p_ops))
return -ENODEV;
if (dib7000p_ops.i2c_enumeration(&i2c_bus->i2c_adap, 1, 0x12, &dib7070p_dib7000p_config) < 0) {
pr_warn("Unable to enumerate dib7000p\n");
return -ENODEV;
}
fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap, 0x80, &dib7070p_dib7000p_config);
if (fe0->dvb.frontend != NULL) {
struct i2c_adapter *tun_i2c;
fe0->dvb.frontend->sec_priv = kmemdup(&dib7000p_ops, sizeof(dib7000p_ops), GFP_KERNEL);
if (!fe0->dvb.frontend->sec_priv)
return -ENOMEM;
tun_i2c = dib7000p_ops.get_i2c_master(fe0->dvb.frontend, DIBX000_I2C_INTERFACE_TUNER, 1);
if (!dvb_attach(dib0070_attach, fe0->dvb.frontend, tun_i2c, &dib7070p_dib0070_config))
return -ENODEV;
}
break;
}
case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&dvico_fusionhdtv_xc3028,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend != NULL) {
struct dvb_frontend *fe;
struct xc2028_config cfg = {
.i2c_adap = &dev->i2c_bus[1].i2c_adap,
.i2c_addr = 0x61,
};
static struct xc2028_ctrl ctl = {
.fname = XC2028_DEFAULT_FIRMWARE,
.max_len = 64,
.demod = XC3028_FE_ZARLINK456,
};
fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
&cfg);
if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
fe->ops.tuner_ops.set_config(fe, &ctl);
}
break;
case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&dvico_fusionhdtv_xc3028,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend != NULL) {
struct dvb_frontend *fe;
struct xc4000_config cfg = {
.i2c_address = 0x61,
.default_pm = 0,
.dvb_amplitude = 134,
.set_smoothedcvbs = 1,
.if_khz = 4560
};
fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
&dev->i2c_bus[1].i2c_adap, &cfg);
if (!fe) {
pr_err("%s/2: xc4000 attach failed\n",
dev->name);
goto frontend_detach;
}
}
break;
case CX23885_BOARD_TBS_6920:
i2c_bus = &dev->i2c_bus[1];
fe0->dvb.frontend = dvb_attach(cx24116_attach,
&tbs_cx24116_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend != NULL)
fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
break;
case CX23885_BOARD_TBS_6980:
case CX23885_BOARD_TBS_6981:
i2c_bus = &dev->i2c_bus[1];
switch (port->nr) {
/* PORT B */
case 1:
fe0->dvb.frontend = dvb_attach(cx24117_attach,
&tbs_cx24117_config,
&i2c_bus->i2c_adap);
break;
/* PORT C */
case 2:
fe0->dvb.frontend = dvb_attach(cx24117_attach,
&tbs_cx24117_config,
&i2c_bus->i2c_adap);
break;
}
break;
case CX23885_BOARD_TEVII_S470:
i2c_bus = &dev->i2c_bus[1];
fe0->dvb.frontend = dvb_attach(ds3000_attach,
&tevii_ds3000_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend != NULL) {
dvb_attach(ts2020_attach, fe0->dvb.frontend,
&tevii_ts2020_config, &i2c_bus->i2c_adap);
fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
}
break;
case CX23885_BOARD_DVBWORLD_2005:
i2c_bus = &dev->i2c_bus[1];
fe0->dvb.frontend = dvb_attach(cx24116_attach,
&dvbworld_cx24116_config,
&i2c_bus->i2c_adap);
break;
case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
i2c_bus = &dev->i2c_bus[0];
switch (port->nr) {
/* port B */
case 1:
fe0->dvb.frontend = dvb_attach(stv0900_attach,
&netup_stv0900_config,
&i2c_bus->i2c_adap, 0);
if (fe0->dvb.frontend != NULL) {
if (dvb_attach(stv6110_attach,
fe0->dvb.frontend,
&netup_stv6110_tunerconfig_a,
&i2c_bus->i2c_adap)) {
if (!dvb_attach(lnbh24_attach,
fe0->dvb.frontend,
&i2c_bus->i2c_adap,
LNBH24_PCL | LNBH24_TTX,
LNBH24_TEN, 0x09))
pr_err("No LNBH24 found!\n");
}
}
break;
/* port C */
case 2:
fe0->dvb.frontend = dvb_attach(stv0900_attach,
&netup_stv0900_config,
&i2c_bus->i2c_adap, 1);
if (fe0->dvb.frontend != NULL) {
if (dvb_attach(stv6110_attach,
fe0->dvb.frontend,
&netup_stv6110_tunerconfig_b,
&i2c_bus->i2c_adap)) {
if (!dvb_attach(lnbh24_attach,
fe0->dvb.frontend,
&i2c_bus->i2c_adap,
LNBH24_PCL | LNBH24_TTX,
LNBH24_TEN, 0x0a))
pr_err("No LNBH24 found!\n");
}
}
break;
}
break;
case CX23885_BOARD_MYGICA_X8506:
i2c_bus = &dev->i2c_bus[0];
i2c_bus2 = &dev->i2c_bus[1];
fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
&mygica_x8506_lgs8gl5_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(xc5000_attach, fe0->dvb.frontend,
&i2c_bus2->i2c_adap, &mygica_x8506_xc5000_config);
cx23885_set_frontend_hook(port, fe0->dvb.frontend);
break;
case CX23885_BOARD_MYGICA_X8507:
i2c_bus = &dev->i2c_bus[0];
i2c_bus2 = &dev->i2c_bus[1];
fe0->dvb.frontend = dvb_attach(mb86a20s_attach,
&mygica_x8507_mb86a20s_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(xc5000_attach, fe0->dvb.frontend,
&i2c_bus2->i2c_adap,
&mygica_x8507_xc5000_config);
cx23885_set_frontend_hook(port, fe0->dvb.frontend);
break;
case CX23885_BOARD_MAGICPRO_PROHDTVE2:
i2c_bus = &dev->i2c_bus[0];
i2c_bus2 = &dev->i2c_bus[1];
fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
&magicpro_prohdtve2_lgs8g75_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(xc5000_attach, fe0->dvb.frontend,
&i2c_bus2->i2c_adap,
&magicpro_prohdtve2_xc5000_config);
cx23885_set_frontend_hook(port, fe0->dvb.frontend);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1850:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(s5h1411_attach,
&hcw_s5h1411_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_bus[0].i2c_adap,
&hauppauge_tda18271_config);
tda18271_attach(&dev->ts1.analog_fe,
0x60, &dev->i2c_bus[1].i2c_adap,
&hauppauge_tda18271_config);
break;
case CX23885_BOARD_HAUPPAUGE_HVR1290:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(s5h1411_attach,
&hcw_s5h1411_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_bus[0].i2c_adap,
&hauppauge_tda18271_config);
break;
case CX23885_BOARD_MYGICA_X8558PRO:
switch (port->nr) {
/* port B */
case 1:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(atbm8830_attach,
&mygica_x8558pro_atbm8830_cfg1,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(max2165_attach, fe0->dvb.frontend,
&i2c_bus->i2c_adap,
&mygic_x8558pro_max2165_cfg1);
break;
/* port C */
case 2:
i2c_bus = &dev->i2c_bus[1];
fe0->dvb.frontend = dvb_attach(atbm8830_attach,
&mygica_x8558pro_atbm8830_cfg2,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(max2165_attach, fe0->dvb.frontend,
&i2c_bus->i2c_adap,
&mygic_x8558pro_max2165_cfg2);
}
break;
case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
if (port->nr > 2)
return 0;
i2c_bus = &dev->i2c_bus[0];
mfe_shared = 1;/* MFE */
port->frontends.gate = 0;/* not clear for me yet */
/* ports B, C */
/* MFE frontend 1 DVB-T */
fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
&netup_stv0367_config[port->nr - 1],
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
if (NULL == dvb_attach(xc5000_attach, fe0->dvb.frontend,
&i2c_bus->i2c_adap,
&netup_xc5000_config[port->nr - 1]))
goto frontend_detach;
/* load xc5000 firmware */
fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
/* MFE frontend 2 */
fe1 = vb2_dvb_get_frontend(&port->frontends, 2);
if (fe1 == NULL)
goto frontend_detach;
/* DVB-C init */
fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
&netup_stv0367_config[port->nr - 1],
&i2c_bus->i2c_adap);
if (fe1->dvb.frontend == NULL)
break;
fe1->dvb.frontend->id = 1;
if (NULL == dvb_attach(xc5000_attach,
fe1->dvb.frontend,
&i2c_bus->i2c_adap,
&netup_xc5000_config[port->nr - 1]))
goto frontend_detach;
break;
case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
i2c_bus = &dev->i2c_bus[0];
i2c_bus2 = &dev->i2c_bus[1];
switch (port->nr) {
/* port b */
case 1:
fe0->dvb.frontend = dvb_attach(drxk_attach,
&terratec_drxk_config[0],
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
if (!dvb_attach(mt2063_attach,
fe0->dvb.frontend,
&terratec_mt2063_config[0],
&i2c_bus2->i2c_adap))
goto frontend_detach;
break;
/* port c */
case 2:
fe0->dvb.frontend = dvb_attach(drxk_attach,
&terratec_drxk_config[1],
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
if (!dvb_attach(mt2063_attach,
fe0->dvb.frontend,
&terratec_mt2063_config[1],
&i2c_bus2->i2c_adap))
goto frontend_detach;
break;
}
break;
case CX23885_BOARD_TEVII_S471:
i2c_bus = &dev->i2c_bus[1];
fe0->dvb.frontend = dvb_attach(ds3000_attach,
&tevii_ds3000_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
dvb_attach(ts2020_attach, fe0->dvb.frontend,
&tevii_ts2020_config, &i2c_bus->i2c_adap);
break;
case CX23885_BOARD_PROF_8000:
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(stv090x_attach,
&prof_8000_stv090x_config,
&i2c_bus->i2c_adap,
STV090x_DEMODULATOR_0);
if (fe0->dvb.frontend == NULL)
break;
if (!dvb_attach(stb6100_attach,
fe0->dvb.frontend,
&prof_8000_stb6100_config,
&i2c_bus->i2c_adap))
goto frontend_detach;
fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
break;
case CX23885_BOARD_HAUPPAUGE_HVR4400: {
struct tda10071_platform_data tda10071_pdata = hauppauge_tda10071_pdata;
struct a8293_platform_data a8293_pdata = {};
i2c_bus = &dev->i2c_bus[0];
i2c_bus2 = &dev->i2c_bus[1];
switch (port->nr) {
/* port b */
case 1:
/* attach demod + tuner combo */
memset(&info, 0, sizeof(info));
strscpy(info.type, "tda10071_cx24118", I2C_NAME_SIZE);
info.addr = 0x05;
info.platform_data = &tda10071_pdata;
request_module("tda10071");
client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
if (!i2c_client_has_driver(client_demod))
goto frontend_detach;
if (!try_module_get(client_demod->dev.driver->owner)) {
i2c_unregister_device(client_demod);
goto frontend_detach;
}
fe0->dvb.frontend = tda10071_pdata.get_dvb_frontend(client_demod);
port->i2c_client_demod = client_demod;
/* attach SEC */
a8293_pdata.dvb_frontend = fe0->dvb.frontend;
memset(&info, 0, sizeof(info));
strscpy(info.type, "a8293", I2C_NAME_SIZE);
info.addr = 0x0b;
info.platform_data = &a8293_pdata;
request_module("a8293");
client_sec = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
if (!i2c_client_has_driver(client_sec))
goto frontend_detach;
if (!try_module_get(client_sec->dev.driver->owner)) {
i2c_unregister_device(client_sec);
goto frontend_detach;
}
port->i2c_client_sec = client_sec;
break;
/* port c */
case 2:
/* attach frontend */
memset(&si2165_pdata, 0, sizeof(si2165_pdata));
si2165_pdata.fe = &fe0->dvb.frontend;
si2165_pdata.chip_mode = SI2165_MODE_PLL_XTAL;
si2165_pdata.ref_freq_hz = 16000000;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2165", I2C_NAME_SIZE);
info.addr = 0x64;
info.platform_data = &si2165_pdata;
request_module(info.type);
client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
if (!i2c_client_has_driver(client_demod))
goto frontend_detach;
if (!try_module_get(client_demod->dev.driver->owner)) {
i2c_unregister_device(client_demod);
goto frontend_detach;
}
port->i2c_client_demod = client_demod;
if (fe0->dvb.frontend == NULL)
break;
fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
if (!dvb_attach(tda18271_attach,
fe0->dvb.frontend,
0x60, &i2c_bus2->i2c_adap,
&hauppauge_hvr4400_tuner_config))
goto frontend_detach;
break;
}
break;
}
case CX23885_BOARD_HAUPPAUGE_STARBURST: {
struct tda10071_platform_data tda10071_pdata = hauppauge_tda10071_pdata;
struct a8293_platform_data a8293_pdata = {};
i2c_bus = &dev->i2c_bus[0];
/* attach demod + tuner combo */
memset(&info, 0, sizeof(info));
strscpy(info.type, "tda10071_cx24118", I2C_NAME_SIZE);
info.addr = 0x05;
info.platform_data = &tda10071_pdata;
request_module("tda10071");
client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
if (!i2c_client_has_driver(client_demod))
goto frontend_detach;
if (!try_module_get(client_demod->dev.driver->owner)) {
i2c_unregister_device(client_demod);
goto frontend_detach;
}
fe0->dvb.frontend = tda10071_pdata.get_dvb_frontend(client_demod);
port->i2c_client_demod = client_demod;
/* attach SEC */
a8293_pdata.dvb_frontend = fe0->dvb.frontend;
memset(&info, 0, sizeof(info));
strscpy(info.type, "a8293", I2C_NAME_SIZE);
info.addr = 0x0b;
info.platform_data = &a8293_pdata;
request_module("a8293");
client_sec = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
if (!i2c_client_has_driver(client_sec))
goto frontend_detach;
if (!try_module_get(client_sec->dev.driver->owner)) {
i2c_unregister_device(client_sec);
goto frontend_detach;
}
port->i2c_client_sec = client_sec;
break;
}
case CX23885_BOARD_DVBSKY_T9580:
case CX23885_BOARD_DVBSKY_S950:
i2c_bus = &dev->i2c_bus[0];
i2c_bus2 = &dev->i2c_bus[1];
switch (port->nr) {
/* port b - satellite */
case 1:
/* attach frontend */
fe0->dvb.frontend = dvb_attach(m88ds3103_attach,
&dvbsky_t9580_m88ds3103_config,
&i2c_bus2->i2c_adap, &adapter);
if (fe0->dvb.frontend == NULL)
break;
/* attach tuner */
memset(&ts2020_config, 0, sizeof(ts2020_config));
ts2020_config.fe = fe0->dvb.frontend;
ts2020_config.get_agc_pwm = m88ds3103_get_agc_pwm;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "ts2020", I2C_NAME_SIZE);
info.addr = 0x60;
info.platform_data = &ts2020_config;
request_module(info.type);
client_tuner = i2c_new_client_device(adapter, &info);
if (!i2c_client_has_driver(client_tuner))
goto frontend_detach;
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
goto frontend_detach;
}
/* delegate signal strength measurement to tuner */
fe0->dvb.frontend->ops.read_signal_strength =
fe0->dvb.frontend->ops.tuner_ops.get_rf_strength;
/*
* for setting the voltage we need to set GPIOs on
* the card.
*/
port->fe_set_voltage =
fe0->dvb.frontend->ops.set_voltage;
fe0->dvb.frontend->ops.set_voltage =
dvbsky_t9580_set_voltage;
port->i2c_client_tuner = client_tuner;
break;
/* port c - terrestrial/cable */
case 2:
/* attach frontend */
memset(&si2168_config, 0, sizeof(si2168_config));
si2168_config.i2c_adapter = &adapter;
si2168_config.fe = &fe0->dvb.frontend;
si2168_config.ts_mode = SI2168_TS_SERIAL;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2168", I2C_NAME_SIZE);
info.addr = 0x64;
info.platform_data = &si2168_config;
request_module(info.type);
client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
if (!i2c_client_has_driver(client_demod))
goto frontend_detach;
if (!try_module_get(client_demod->dev.driver->owner)) {
i2c_unregister_device(client_demod);
goto frontend_detach;
}
port->i2c_client_demod = client_demod;
/* attach tuner */
memset(&si2157_config, 0, sizeof(si2157_config));
si2157_config.fe = fe0->dvb.frontend;
si2157_config.if_port = 1;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2157", I2C_NAME_SIZE);
info.addr = 0x60;
info.platform_data = &si2157_config;
request_module(info.type);
client_tuner = i2c_new_client_device(adapter, &info);
if (!i2c_client_has_driver(client_tuner))
goto frontend_detach;
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;
break;
}
break;
case CX23885_BOARD_DVBSKY_T980C:
case CX23885_BOARD_TT_CT2_4500_CI:
i2c_bus = &dev->i2c_bus[0];
i2c_bus2 = &dev->i2c_bus[1];
/* attach frontend */
memset(&si2168_config, 0, sizeof(si2168_config));
si2168_config.i2c_adapter = &adapter;
si2168_config.fe = &fe0->dvb.frontend;
si2168_config.ts_mode = SI2168_TS_PARALLEL;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2168", I2C_NAME_SIZE);
info.addr = 0x64;
info.platform_data = &si2168_config;
request_module(info.type);
client_demod = i2c_new_client_device(&i2c_bus2->i2c_adap, &info);
if (!i2c_client_has_driver(client_demod))
goto frontend_detach;
if (!try_module_get(client_demod->dev.driver->owner)) {
i2c_unregister_device(client_demod);
goto frontend_detach;
}
port->i2c_client_demod = client_demod;
/* attach tuner */
memset(&si2157_config, 0, sizeof(si2157_config));
si2157_config.fe = fe0->dvb.frontend;
si2157_config.if_port = 1;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2157", I2C_NAME_SIZE);
info.addr = 0x60;
info.platform_data = &si2157_config;
request_module(info.type);
client_tuner = i2c_new_client_device(adapter, &info);
if (!i2c_client_has_driver(client_tuner))
goto frontend_detach;
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;
break;
case CX23885_BOARD_DVBSKY_S950C:
i2c_bus = &dev->i2c_bus[0];
i2c_bus2 = &dev->i2c_bus[1];
/* attach frontend */
fe0->dvb.frontend = dvb_attach(m88ds3103_attach,
&dvbsky_s950c_m88ds3103_config,
&i2c_bus2->i2c_adap, &adapter);
if (fe0->dvb.frontend == NULL)
break;
/* attach tuner */
memset(&ts2020_config, 0, sizeof(ts2020_config));
ts2020_config.fe = fe0->dvb.frontend;
ts2020_config.get_agc_pwm = m88ds3103_get_agc_pwm;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "ts2020", I2C_NAME_SIZE);
info.addr = 0x60;
info.platform_data = &ts2020_config;
request_module(info.type);
client_tuner = i2c_new_client_device(adapter, &info);
if (!i2c_client_has_driver(client_tuner))
goto frontend_detach;
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
goto frontend_detach;
}
/* delegate signal strength measurement to tuner */
fe0->dvb.frontend->ops.read_signal_strength =
fe0->dvb.frontend->ops.tuner_ops.get_rf_strength;
port->i2c_client_tuner = client_tuner;
break;
case CX23885_BOARD_DVBSKY_S952:
/* attach frontend */
memset(&m88ds3103_pdata, 0, sizeof(m88ds3103_pdata));
m88ds3103_pdata.clk = 27000000;
m88ds3103_pdata.i2c_wr_max = 33;
m88ds3103_pdata.agc = 0x99;
m88ds3103_pdata.clk_out = M88DS3103_CLOCK_OUT_DISABLED;
m88ds3103_pdata.lnb_en_pol = 1;
switch (port->nr) {
/* port b */
case 1:
i2c_bus = &dev->i2c_bus[1];
m88ds3103_pdata.ts_mode = M88DS3103_TS_PARALLEL;
m88ds3103_pdata.ts_clk = 16000;
m88ds3103_pdata.ts_clk_pol = 1;
p_set_voltage = dvbsky_t9580_set_voltage;
break;
/* port c */
case 2:
i2c_bus = &dev->i2c_bus[0];
m88ds3103_pdata.ts_mode = M88DS3103_TS_SERIAL;
m88ds3103_pdata.ts_clk = 96000;
m88ds3103_pdata.ts_clk_pol = 0;
p_set_voltage = dvbsky_s952_portc_set_voltage;
break;
default:
return 0;
}
memset(&info, 0, sizeof(info));
strscpy(info.type, "m88ds3103", I2C_NAME_SIZE);
info.addr = 0x68;
info.platform_data = &m88ds3103_pdata;
request_module(info.type);
client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
if (!i2c_client_has_driver(client_demod))
goto frontend_detach;
if (!try_module_get(client_demod->dev.driver->owner)) {
i2c_unregister_device(client_demod);
goto frontend_detach;
}
port->i2c_client_demod = client_demod;
adapter = m88ds3103_pdata.get_i2c_adapter(client_demod);
fe0->dvb.frontend = m88ds3103_pdata.get_dvb_frontend(client_demod);
/* attach tuner */
memset(&ts2020_config, 0, sizeof(ts2020_config));
ts2020_config.fe = fe0->dvb.frontend;
ts2020_config.get_agc_pwm = m88ds3103_get_agc_pwm;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "ts2020", I2C_NAME_SIZE);
info.addr = 0x60;
info.platform_data = &ts2020_config;
request_module(info.type);
client_tuner = i2c_new_client_device(adapter, &info);
if (!i2c_client_has_driver(client_tuner))
goto frontend_detach;
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
goto frontend_detach;
}
/* delegate signal strength measurement to tuner */
fe0->dvb.frontend->ops.read_signal_strength =
fe0->dvb.frontend->ops.tuner_ops.get_rf_strength;
/*
* for setting the voltage we need to set GPIOs on
* the card.
*/
port->fe_set_voltage =
fe0->dvb.frontend->ops.set_voltage;
fe0->dvb.frontend->ops.set_voltage = p_set_voltage;
port->i2c_client_tuner = client_tuner;
break;
case CX23885_BOARD_DVBSKY_T982:
memset(&si2168_config, 0, sizeof(si2168_config));
switch (port->nr) {
/* port b */
case 1:
i2c_bus = &dev->i2c_bus[1];
si2168_config.ts_mode = SI2168_TS_PARALLEL;
break;
/* port c */
case 2:
i2c_bus = &dev->i2c_bus[0];
si2168_config.ts_mode = SI2168_TS_SERIAL;
break;
}
/* attach frontend */
si2168_config.i2c_adapter = &adapter;
si2168_config.fe = &fe0->dvb.frontend;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2168", I2C_NAME_SIZE);
info.addr = 0x64;
info.platform_data = &si2168_config;
request_module(info.type);
client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
if (!i2c_client_has_driver(client_demod))
goto frontend_detach;
if (!try_module_get(client_demod->dev.driver->owner)) {
i2c_unregister_device(client_demod);
goto frontend_detach;
}
port->i2c_client_demod = client_demod;
/* attach tuner */
memset(&si2157_config, 0, sizeof(si2157_config));
si2157_config.fe = fe0->dvb.frontend;
si2157_config.if_port = 1;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2157", I2C_NAME_SIZE);
info.addr = 0x60;
info.platform_data = &si2157_config;
request_module(info.type);
client_tuner = i2c_new_client_device(adapter, &info);
if (!i2c_client_has_driver(client_tuner))
goto frontend_detach;
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;
break;
case CX23885_BOARD_HAUPPAUGE_STARBURST2:
case CX23885_BOARD_HAUPPAUGE_HVR5525:
i2c_bus = &dev->i2c_bus[0];
i2c_bus2 = &dev->i2c_bus[1];
switch (port->nr) {
/* port b - satellite */
case 1:
/* attach frontend */
fe0->dvb.frontend = dvb_attach(m88ds3103_attach,
&hauppauge_hvr5525_m88ds3103_config,
&i2c_bus->i2c_adap, &adapter);
if (fe0->dvb.frontend == NULL)
break;
/* attach SEC */
a8293_pdata.dvb_frontend = fe0->dvb.frontend;
memset(&info, 0, sizeof(info));
strscpy(info.type, "a8293", I2C_NAME_SIZE);
info.addr = 0x0b;
info.platform_data = &a8293_pdata;
request_module("a8293");
client_sec = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
if (!i2c_client_has_driver(client_sec))
goto frontend_detach;
if (!try_module_get(client_sec->dev.driver->owner)) {
i2c_unregister_device(client_sec);
goto frontend_detach;
}
port->i2c_client_sec = client_sec;
/* attach tuner */
memset(&m88rs6000t_config, 0, sizeof(m88rs6000t_config));
m88rs6000t_config.fe = fe0->dvb.frontend;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "m88rs6000t", I2C_NAME_SIZE);
info.addr = 0x21;
info.platform_data = &m88rs6000t_config;
request_module("%s", info.type);
client_tuner = i2c_new_client_device(adapter, &info);
if (!i2c_client_has_driver(client_tuner))
goto frontend_detach;
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;
/* delegate signal strength measurement to tuner */
fe0->dvb.frontend->ops.read_signal_strength =
fe0->dvb.frontend->ops.tuner_ops.get_rf_strength;
break;
/* port c - terrestrial/cable */
case 2:
/* attach frontend */
memset(&si2168_config, 0, sizeof(si2168_config));
si2168_config.i2c_adapter = &adapter;
si2168_config.fe = &fe0->dvb.frontend;
si2168_config.ts_mode = SI2168_TS_SERIAL;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2168", I2C_NAME_SIZE);
info.addr = 0x64;
info.platform_data = &si2168_config;
request_module("%s", info.type);
client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
if (!i2c_client_has_driver(client_demod))
goto frontend_detach;
if (!try_module_get(client_demod->dev.driver->owner)) {
i2c_unregister_device(client_demod);
goto frontend_detach;
}
port->i2c_client_demod = client_demod;
/* attach tuner */
memset(&si2157_config, 0, sizeof(si2157_config));
si2157_config.fe = fe0->dvb.frontend;
si2157_config.if_port = 1;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2157", I2C_NAME_SIZE);
info.addr = 0x60;
info.platform_data = &si2157_config;
request_module("%s", info.type);
client_tuner = i2c_new_client_device(&i2c_bus2->i2c_adap, &info);
if (!i2c_client_has_driver(client_tuner)) {
module_put(client_demod->dev.driver->owner);
i2c_unregister_device(client_demod);
port->i2c_client_demod = NULL;
goto frontend_detach;
}
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
module_put(client_demod->dev.driver->owner);
i2c_unregister_device(client_demod);
port->i2c_client_demod = NULL;
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;
dev->ts1.analog_fe.tuner_priv = client_tuner;
memcpy(&dev->ts1.analog_fe.ops.tuner_ops,
&fe0->dvb.frontend->ops.tuner_ops,
sizeof(struct dvb_tuner_ops));
break;
}
break;
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885:
pr_info("%s(): board=%d port=%d\n", __func__,
dev->board, port->nr);
switch (port->nr) {
/* port b - Terrestrial/cable */
case 1:
/* attach frontend */
memset(&si2168_config, 0, sizeof(si2168_config));
si2168_config.i2c_adapter = &adapter;
si2168_config.fe = &fe0->dvb.frontend;
si2168_config.ts_mode = SI2168_TS_SERIAL;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2168", I2C_NAME_SIZE);
info.addr = 0x64;
info.platform_data = &si2168_config;
request_module("%s", info.type);
client_demod = i2c_new_client_device(&dev->i2c_bus[0].i2c_adap, &info);
if (!i2c_client_has_driver(client_demod))
goto frontend_detach;
if (!try_module_get(client_demod->dev.driver->owner)) {
i2c_unregister_device(client_demod);
goto frontend_detach;
}
port->i2c_client_demod = client_demod;
/* attach tuner */
memset(&si2157_config, 0, sizeof(si2157_config));
si2157_config.fe = fe0->dvb.frontend;
si2157_config.if_port = 1;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2157", I2C_NAME_SIZE);
info.addr = 0x60;
info.platform_data = &si2157_config;
request_module("%s", info.type);
client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
if (!i2c_client_has_driver(client_tuner)) {
module_put(client_demod->dev.driver->owner);
i2c_unregister_device(client_demod);
port->i2c_client_demod = NULL;
goto frontend_detach;
}
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
module_put(client_demod->dev.driver->owner);
i2c_unregister_device(client_demod);
port->i2c_client_demod = NULL;
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;
/* we only attach tuner for analog on the 888 version */
if (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_DVB) {
pr_info("%s(): QUADHD_DVB analog setup\n",
__func__);
dev->ts1.analog_fe.tuner_priv = client_tuner;
memcpy(&dev->ts1.analog_fe.ops.tuner_ops,
&fe0->dvb.frontend->ops.tuner_ops,
sizeof(struct dvb_tuner_ops));
}
break;
/* port c - terrestrial/cable */
case 2:
/* attach frontend */
memset(&si2168_config, 0, sizeof(si2168_config));
si2168_config.i2c_adapter = &adapter;
si2168_config.fe = &fe0->dvb.frontend;
si2168_config.ts_mode = SI2168_TS_SERIAL;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2168", I2C_NAME_SIZE);
info.addr = 0x66;
info.platform_data = &si2168_config;
request_module("%s", info.type);
client_demod = i2c_new_client_device(&dev->i2c_bus[0].i2c_adap, &info);
if (!i2c_client_has_driver(client_demod))
goto frontend_detach;
if (!try_module_get(client_demod->dev.driver->owner)) {
i2c_unregister_device(client_demod);
goto frontend_detach;
}
port->i2c_client_demod = client_demod;
/* attach tuner */
memset(&si2157_config, 0, sizeof(si2157_config));
si2157_config.fe = fe0->dvb.frontend;
si2157_config.if_port = 1;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2157", I2C_NAME_SIZE);
info.addr = 0x62;
info.platform_data = &si2157_config;
request_module("%s", info.type);
client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
if (!i2c_client_has_driver(client_tuner)) {
module_put(client_demod->dev.driver->owner);
i2c_unregister_device(client_demod);
port->i2c_client_demod = NULL;
goto frontend_detach;
}
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
module_put(client_demod->dev.driver->owner);
i2c_unregister_device(client_demod);
port->i2c_client_demod = NULL;
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;
break;
}
break;
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885:
pr_info("%s(): board=%d port=%d\n", __func__,
dev->board, port->nr);
switch (port->nr) {
/* port b - Terrestrial/cable */
case 1:
/* attach frontend */
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(lgdt3306a_attach,
&hauppauge_quadHD_ATSC_a_config, &i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
/* attach tuner */
memset(&si2157_config, 0, sizeof(si2157_config));
si2157_config.fe = fe0->dvb.frontend;
si2157_config.if_port = 1;
si2157_config.inversion = 1;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2157", I2C_NAME_SIZE);
info.addr = 0x60;
info.platform_data = &si2157_config;
request_module("%s", info.type);
client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
if (!i2c_client_has_driver(client_tuner)) {
goto frontend_detach;
}
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;
/* we only attach tuner for analog on the 888 version */
if (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC) {
pr_info("%s(): QUADHD_ATSC analog setup\n",
__func__);
dev->ts1.analog_fe.tuner_priv = client_tuner;
memcpy(&dev->ts1.analog_fe.ops.tuner_ops,
&fe0->dvb.frontend->ops.tuner_ops,
sizeof(struct dvb_tuner_ops));
}
break;
/* port c - terrestrial/cable */
case 2:
/* attach frontend */
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(lgdt3306a_attach,
&hauppauge_quadHD_ATSC_b_config, &i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
/* attach tuner */
memset(&si2157_config, 0, sizeof(si2157_config));
si2157_config.fe = fe0->dvb.frontend;
si2157_config.if_port = 1;
si2157_config.inversion = 1;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2157", I2C_NAME_SIZE);
info.addr = 0x62;
info.platform_data = &si2157_config;
request_module("%s", info.type);
client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
if (!i2c_client_has_driver(client_tuner)) {
goto frontend_detach;
}
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;
break;
}
break;
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
switch (port->nr) {
/* port c - Terrestrial/cable */
case 2:
/* attach frontend */
i2c_bus = &dev->i2c_bus[0];
fe0->dvb.frontend = dvb_attach(lgdt3306a_attach,
&hauppauge_hvr1265k4_config,
&i2c_bus->i2c_adap);
if (fe0->dvb.frontend == NULL)
break;
/* attach tuner */
memset(&si2157_config, 0, sizeof(si2157_config));
si2157_config.fe = fe0->dvb.frontend;
si2157_config.if_port = 1;
si2157_config.inversion = 1;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "si2157", I2C_NAME_SIZE);
info.addr = 0x60;
info.platform_data = &si2157_config;
request_module("%s", info.type);
client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
if (!i2c_client_has_driver(client_tuner))
goto frontend_detach;
if (!try_module_get(client_tuner->dev.driver->owner)) {
i2c_unregister_device(client_tuner);
client_tuner = NULL;
goto frontend_detach;
}
port->i2c_client_tuner = client_tuner;
dev->ts1.analog_fe.tuner_priv = client_tuner;
memcpy(&dev->ts1.analog_fe.ops.tuner_ops,
&fe0->dvb.frontend->ops.tuner_ops,
sizeof(struct dvb_tuner_ops));
break;
}
break;
default:
pr_info("%s: The frontend of your DVB/ATSC card isn't supported yet\n",
dev->name);
break;
}
if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
pr_err("%s: frontend initialization failed\n",
dev->name);
goto frontend_detach;
}
/* define general-purpose callback pointer */
fe0->dvb.frontend->callback = cx23885_tuner_callback;
if (fe1)
fe1->dvb.frontend->callback = cx23885_tuner_callback;
#if 0
/* Ensure all frontends negotiate bus access */
fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
if (fe1)
fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
#endif
/* Put the tuner in standby to keep it quiet */
call_all(dev, tuner, standby);
if (fe0->dvb.frontend->ops.analog_ops.standby)
fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
/* register everything */
ret = vb2_dvb_register_bus(&port->frontends, THIS_MODULE, port,
&dev->pci->dev, NULL,
adapter_nr, mfe_shared);
if (ret)
goto frontend_detach;
ret = dvb_register_ci_mac(port);
if (ret)
goto frontend_detach;
return 0;
frontend_detach:
/* remove I2C client for SEC */
client_sec = port->i2c_client_sec;
if (client_sec) {
module_put(client_sec->dev.driver->owner);
i2c_unregister_device(client_sec);
port->i2c_client_sec = NULL;
}
/* remove I2C client for tuner */
client_tuner = port->i2c_client_tuner;
if (client_tuner) {
module_put(client_tuner->dev.driver->owner);
i2c_unregister_device(client_tuner);
port->i2c_client_tuner = NULL;
}
/* remove I2C client for demodulator */
client_demod = port->i2c_client_demod;
if (client_demod) {
module_put(client_demod->dev.driver->owner);
i2c_unregister_device(client_demod);
port->i2c_client_demod = NULL;
}
port->gate_ctrl = NULL;
vb2_dvb_dealloc_frontends(&port->frontends);
return -EINVAL;
}
int cx23885_dvb_register(struct cx23885_tsport *port)
{
struct vb2_dvb_frontend *fe0;
struct cx23885_dev *dev = port->dev;
int err, i;
/* Here we need to allocate the correct number of frontends,
* as reflected in the cards struct. The reality is that currently
* no cx23885 boards support this - yet. But, if we don't modify this
* code then the second frontend would never be allocated (later)
* and fail with error before the attach in dvb_register().
* Without these changes we risk an OOPS later. The changes here
* are for safety, and should provide a good foundation for the
* future addition of any multi-frontend cx23885 based boards.
*/
pr_info("%s() allocating %d frontend(s)\n", __func__,
port->num_frontends);
for (i = 1; i <= port->num_frontends; i++) {
struct vb2_queue *q;
if (vb2_dvb_alloc_frontend(
&port->frontends, i) == NULL) {
pr_err("%s() failed to alloc\n", __func__);
return -ENOMEM;
}
fe0 = vb2_dvb_get_frontend(&port->frontends, i);
if (!fe0)
return -EINVAL;
dprintk(1, "%s\n", __func__);
dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
dev->board,
dev->name,
dev->pci_bus,
dev->pci_slot);
/* dvb stuff */
/* We have to init the queue for each frontend on a port. */
pr_info("%s: cx23885 based dvb card\n", dev->name);
q = &fe0->dvb.dvbq;
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
q->gfp_flags = GFP_DMA32;
q->min_buffers_needed = 2;
q->drv_priv = port;
q->buf_struct_size = sizeof(struct cx23885_buffer);
q->ops = &dvb_qops;
q->mem_ops = &vb2_dma_sg_memops;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &dev->lock;
q->dev = &dev->pci->dev;
err = vb2_queue_init(q);
if (err < 0)
return err;
}
err = dvb_register(port);
if (err != 0)
pr_err("%s() dvb_register failed err = %d\n",
__func__, err);
return err;
}
int cx23885_dvb_unregister(struct cx23885_tsport *port)
{
struct vb2_dvb_frontend *fe0;
struct i2c_client *client;
fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
if (fe0 && fe0->dvb.frontend)
vb2_dvb_unregister_bus(&port->frontends);
/* remove I2C client for CI */
client = port->i2c_client_ci;
if (client) {
module_put(client->dev.driver->owner);
i2c_unregister_device(client);
}
/* remove I2C client for SEC */
client = port->i2c_client_sec;
if (client) {
module_put(client->dev.driver->owner);
i2c_unregister_device(client);
}
/* remove I2C client for tuner */
client = port->i2c_client_tuner;
if (client) {
module_put(client->dev.driver->owner);
i2c_unregister_device(client);
}
/* remove I2C client for demodulator */
client = port->i2c_client_demod;
if (client) {
module_put(client->dev.driver->owner);
i2c_unregister_device(client);
}
switch (port->dev->board) {
case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
netup_ci_exit(port);
break;
case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
altera_ci_release(port->dev, port->nr);
break;
}
port->gate_ctrl = NULL;
return 0;
}
| linux-master | drivers/media/pci/cx23885/cx23885-dvb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Conexant CX23885/7/8 PCIe bridge
*
* Various common ioctl() support functions
*
* Copyright (c) 2009 Andy Walls <[email protected]>
*/
#include "cx23885.h"
#include "cx23885-ioctl.h"
#ifdef CONFIG_VIDEO_ADV_DEBUG
int cx23885_g_chip_info(struct file *file, void *fh,
struct v4l2_dbg_chip_info *chip)
{
struct cx23885_dev *dev = video_drvdata(file);
if (chip->match.addr > 1)
return -EINVAL;
if (chip->match.addr == 1) {
if (dev->v4l_device == NULL)
return -EINVAL;
strscpy(chip->name, "cx23417", sizeof(chip->name));
} else {
strscpy(chip->name, dev->v4l2_dev.name, sizeof(chip->name));
}
return 0;
}
static int cx23417_g_register(struct cx23885_dev *dev,
struct v4l2_dbg_register *reg)
{
u32 value;
if (dev->v4l_device == NULL)
return -EINVAL;
if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000)
return -EINVAL;
if (mc417_register_read(dev, (u16) reg->reg, &value))
return -EINVAL; /* V4L2 spec, but -EREMOTEIO really */
reg->size = 4;
reg->val = value;
return 0;
}
int cx23885_g_register(struct file *file, void *fh,
struct v4l2_dbg_register *reg)
{
struct cx23885_dev *dev = video_drvdata(file);
if (reg->match.addr > 1)
return -EINVAL;
if (reg->match.addr)
return cx23417_g_register(dev, reg);
if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0))
return -EINVAL;
reg->size = 4;
reg->val = cx_read(reg->reg);
return 0;
}
static int cx23417_s_register(struct cx23885_dev *dev,
const struct v4l2_dbg_register *reg)
{
if (dev->v4l_device == NULL)
return -EINVAL;
if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000)
return -EINVAL;
if (mc417_register_write(dev, (u16) reg->reg, (u32) reg->val))
return -EINVAL; /* V4L2 spec, but -EREMOTEIO really */
return 0;
}
int cx23885_s_register(struct file *file, void *fh,
const struct v4l2_dbg_register *reg)
{
struct cx23885_dev *dev = video_drvdata(file);
if (reg->match.addr > 1)
return -EINVAL;
if (reg->match.addr)
return cx23417_s_register(dev, reg);
if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0))
return -EINVAL;
cx_write(reg->reg, reg->val);
return 0;
}
#endif
| linux-master | drivers/media/pci/cx23885/cx23885-ioctl.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Conexant CX23885/7/8 PCIe bridge
*
* CX23888 Integrated Consumer Infrared Controller
*
* Copyright (C) 2009 Andy Walls <[email protected]>
*/
#include "cx23885.h"
#include "cx23888-ir.h"
#include <linux/kfifo.h>
#include <linux/slab.h>
#include <media/v4l2-device.h>
#include <media/rc-core.h>
static unsigned int ir_888_debug;
module_param(ir_888_debug, int, 0644);
MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
#define CX23888_IR_REG_BASE 0x170000
/*
* These CX23888 register offsets have a straightforward one to one mapping
* to the CX23885 register offsets of 0x200 through 0x218
*/
#define CX23888_IR_CNTRL_REG 0x170000
#define CNTRL_WIN_3_3 0x00000000
#define CNTRL_WIN_4_3 0x00000001
#define CNTRL_WIN_3_4 0x00000002
#define CNTRL_WIN_4_4 0x00000003
#define CNTRL_WIN 0x00000003
#define CNTRL_EDG_NONE 0x00000000
#define CNTRL_EDG_FALL 0x00000004
#define CNTRL_EDG_RISE 0x00000008
#define CNTRL_EDG_BOTH 0x0000000C
#define CNTRL_EDG 0x0000000C
#define CNTRL_DMD 0x00000010
#define CNTRL_MOD 0x00000020
#define CNTRL_RFE 0x00000040
#define CNTRL_TFE 0x00000080
#define CNTRL_RXE 0x00000100
#define CNTRL_TXE 0x00000200
#define CNTRL_RIC 0x00000400
#define CNTRL_TIC 0x00000800
#define CNTRL_CPL 0x00001000
#define CNTRL_LBM 0x00002000
#define CNTRL_R 0x00004000
/* CX23888 specific control flag */
#define CNTRL_IVO 0x00008000
#define CX23888_IR_TXCLK_REG 0x170004
#define TXCLK_TCD 0x0000FFFF
#define CX23888_IR_RXCLK_REG 0x170008
#define RXCLK_RCD 0x0000FFFF
#define CX23888_IR_CDUTY_REG 0x17000C
#define CDUTY_CDC 0x0000000F
#define CX23888_IR_STATS_REG 0x170010
#define STATS_RTO 0x00000001
#define STATS_ROR 0x00000002
#define STATS_RBY 0x00000004
#define STATS_TBY 0x00000008
#define STATS_RSR 0x00000010
#define STATS_TSR 0x00000020
#define CX23888_IR_IRQEN_REG 0x170014
#define IRQEN_RTE 0x00000001
#define IRQEN_ROE 0x00000002
#define IRQEN_RSE 0x00000010
#define IRQEN_TSE 0x00000020
#define CX23888_IR_FILTR_REG 0x170018
#define FILTR_LPF 0x0000FFFF
/* This register doesn't follow the pattern; it's 0x23C on a CX23885 */
#define CX23888_IR_FIFO_REG 0x170040
#define FIFO_RXTX 0x0000FFFF
#define FIFO_RXTX_LVL 0x00010000
#define FIFO_RXTX_RTO 0x0001FFFF
#define FIFO_RX_NDV 0x00020000
#define FIFO_RX_DEPTH 8
#define FIFO_TX_DEPTH 8
/* CX23888 unique registers */
#define CX23888_IR_SEEDP_REG 0x17001C
#define CX23888_IR_TIMOL_REG 0x170020
#define CX23888_IR_WAKE0_REG 0x170024
#define CX23888_IR_WAKE1_REG 0x170028
#define CX23888_IR_WAKE2_REG 0x17002C
#define CX23888_IR_MASK0_REG 0x170030
#define CX23888_IR_MASK1_REG 0x170034
#define CX23888_IR_MAKS2_REG 0x170038
#define CX23888_IR_DPIPG_REG 0x17003C
#define CX23888_IR_LEARN_REG 0x170044
#define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
#define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2)
/*
* We use this union internally for convenience, but callers to tx_write
* and rx_read will be expecting records of type struct ir_raw_event.
* Always ensure the size of this union is dictated by struct ir_raw_event.
*/
union cx23888_ir_fifo_rec {
u32 hw_fifo_data;
struct ir_raw_event ir_core_data;
};
#define CX23888_IR_RX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec))
#define CX23888_IR_TX_KFIFO_SIZE (256 * sizeof(union cx23888_ir_fifo_rec))
struct cx23888_ir_state {
struct v4l2_subdev sd;
struct cx23885_dev *dev;
struct v4l2_subdev_ir_parameters rx_params;
struct mutex rx_params_lock;
atomic_t rxclk_divider;
atomic_t rx_invert;
struct kfifo rx_kfifo;
spinlock_t rx_kfifo_lock;
struct v4l2_subdev_ir_parameters tx_params;
struct mutex tx_params_lock;
atomic_t txclk_divider;
};
static inline struct cx23888_ir_state *to_state(struct v4l2_subdev *sd)
{
return v4l2_get_subdevdata(sd);
}
/*
* IR register block read and write functions
*/
static
inline int cx23888_ir_write4(struct cx23885_dev *dev, u32 addr, u32 value)
{
cx_write(addr, value);
return 0;
}
static inline u32 cx23888_ir_read4(struct cx23885_dev *dev, u32 addr)
{
return cx_read(addr);
}
static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
u32 and_mask, u32 or_value)
{
cx_andor(addr, ~and_mask, or_value);
return 0;
}
/*
* Rx and Tx Clock Divider register computations
*
* Note the largest clock divider value of 0xffff corresponds to:
* (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
* which fits in 21 bits, so we'll use unsigned int for time arguments.
*/
static inline u16 count_to_clock_divider(unsigned int d)
{
if (d > RXCLK_RCD + 1)
d = RXCLK_RCD;
else if (d < 2)
d = 1;
else
d--;
return (u16) d;
}
static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
{
return count_to_clock_divider(
DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, freq * 16));
}
static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
{
return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
}
static inline unsigned int clock_divider_to_freq(unsigned int divider,
unsigned int rollovers)
{
return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ,
(divider + 1) * rollovers);
}
/*
* Low Pass Filter register calculations
*
* Note the largest count value of 0xffff corresponds to:
* 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
* which fits in 21 bits, so we'll use unsigned int for time arguments.
*/
static inline u16 count_to_lpf_count(unsigned int d)
{
if (d > FILTR_LPF)
d = FILTR_LPF;
else if (d < 4)
d = 0;
return (u16) d;
}
static inline u16 ns_to_lpf_count(unsigned int ns)
{
return count_to_lpf_count(
DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
}
static inline unsigned int lpf_count_to_ns(unsigned int count)
{
/* Duration of the Low Pass Filter rejection window in ns */
return DIV_ROUND_CLOSEST(count * 1000,
CX23888_IR_REFCLK_FREQ / 1000000);
}
static inline unsigned int lpf_count_to_us(unsigned int count)
{
/* Duration of the Low Pass Filter rejection window in us */
return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000);
}
/*
* FIFO register pulse width count computations
*/
static u32 clock_divider_to_resolution(u16 divider)
{
/*
* Resolution is the duration of 1 tick of the readable portion of
* the pulse width counter as read from the FIFO. The two lsb's are
* not readable, hence the << 2. This function returns ns.
*/
return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
CX23888_IR_REFCLK_FREQ / 1000000);
}
static u64 pulse_width_count_to_ns(u16 count, u16 divider)
{
u64 n;
u32 rem;
/*
* The 2 lsb's of the pulse width timer count are not readable, hence
* the (count << 2) | 0x3
*/
n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
n++;
return n;
}
static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
{
u64 n;
u32 rem;
/*
* The 2 lsb's of the pulse width timer count are not readable, hence
* the (count << 2) | 0x3
*/
n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
n++;
return (unsigned int) n;
}
/*
* Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
*
* The total pulse clock count is an 18 bit pulse width timer count as the most
* significant part and (up to) 16 bit clock divider count as a modulus.
* When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
* width timer count's least significant bit.
*/
static u64 ns_to_pulse_clocks(u32 ns)
{
u64 clocks;
u32 rem;
clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
rem = do_div(clocks, 1000); /* /1000 = cycles */
if (rem >= 1000 / 2)
clocks++;
return clocks;
}
static u16 pulse_clocks_to_clock_divider(u64 count)
{
do_div(count, (FIFO_RXTX << 2) | 0x3);
/* net result needs to be rounded down and decremented by 1 */
if (count > RXCLK_RCD + 1)
count = RXCLK_RCD;
else if (count < 2)
count = 1;
else
count--;
return (u16) count;
}
/*
* IR Control Register helpers
*/
enum tx_fifo_watermark {
TX_FIFO_HALF_EMPTY = 0,
TX_FIFO_EMPTY = CNTRL_TIC,
};
enum rx_fifo_watermark {
RX_FIFO_HALF_FULL = 0,
RX_FIFO_NOT_EMPTY = CNTRL_RIC,
};
static inline void control_tx_irq_watermark(struct cx23885_dev *dev,
enum tx_fifo_watermark level)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_TIC, level);
}
static inline void control_rx_irq_watermark(struct cx23885_dev *dev,
enum rx_fifo_watermark level)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_RIC, level);
}
static inline void control_tx_enable(struct cx23885_dev *dev, bool enable)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
}
static inline void control_rx_enable(struct cx23885_dev *dev, bool enable)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
}
static inline void control_tx_modulation_enable(struct cx23885_dev *dev,
bool enable)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_MOD,
enable ? CNTRL_MOD : 0);
}
static inline void control_rx_demodulation_enable(struct cx23885_dev *dev,
bool enable)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_DMD,
enable ? CNTRL_DMD : 0);
}
static inline void control_rx_s_edge_detection(struct cx23885_dev *dev,
u32 edge_types)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
edge_types & CNTRL_EDG_BOTH);
}
static void control_rx_s_carrier_window(struct cx23885_dev *dev,
unsigned int carrier,
unsigned int *carrier_range_low,
unsigned int *carrier_range_high)
{
u32 v;
unsigned int c16 = carrier * 16;
if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
v = CNTRL_WIN_3_4;
*carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
} else {
v = CNTRL_WIN_3_3;
*carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
}
if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
v |= CNTRL_WIN_4_3;
*carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
} else {
v |= CNTRL_WIN_3_3;
*carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
}
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v);
}
static inline void control_tx_polarity_invert(struct cx23885_dev *dev,
bool invert)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_CPL,
invert ? CNTRL_CPL : 0);
}
static inline void control_tx_level_invert(struct cx23885_dev *dev,
bool invert)
{
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_IVO,
invert ? CNTRL_IVO : 0);
}
/*
* IR Rx & Tx Clock Register helpers
*/
static unsigned int txclk_tx_s_carrier(struct cx23885_dev *dev,
unsigned int freq,
u16 *divider)
{
*divider = carrier_freq_to_clock_divider(freq);
cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
return clock_divider_to_carrier_freq(*divider);
}
static unsigned int rxclk_rx_s_carrier(struct cx23885_dev *dev,
unsigned int freq,
u16 *divider)
{
*divider = carrier_freq_to_clock_divider(freq);
cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
return clock_divider_to_carrier_freq(*divider);
}
static u32 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
u16 *divider)
{
u64 pulse_clocks;
if (ns > IR_MAX_DURATION)
ns = IR_MAX_DURATION;
pulse_clocks = ns_to_pulse_clocks(ns);
*divider = pulse_clocks_to_clock_divider(pulse_clocks);
cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
}
static u32 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns,
u16 *divider)
{
u64 pulse_clocks;
if (ns > IR_MAX_DURATION)
ns = IR_MAX_DURATION;
pulse_clocks = ns_to_pulse_clocks(ns);
*divider = pulse_clocks_to_clock_divider(pulse_clocks);
cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
}
/*
* IR Tx Carrier Duty Cycle register helpers
*/
static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev,
unsigned int duty_cycle)
{
u32 n;
n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
if (n != 0)
n--;
if (n > 15)
n = 15;
cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n);
return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
}
/*
* IR Filter Register helpers
*/
static u32 filter_rx_s_min_width(struct cx23885_dev *dev, u32 min_width_ns)
{
u32 count = ns_to_lpf_count(min_width_ns);
cx23888_ir_write4(dev, CX23888_IR_FILTR_REG, count);
return lpf_count_to_ns(count);
}
/*
* IR IRQ Enable Register helpers
*/
static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask)
{
mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG,
~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
}
static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask)
{
mask &= IRQEN_TSE;
cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask);
}
/*
* V4L2 Subdevice IR Ops
*/
static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status,
bool *handled)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
unsigned long flags;
u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
union cx23888_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
unsigned int i, j, k;
u32 events, v;
int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
ror = stats & STATS_ROR; /* Rx FIFO Over Run */
tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
rse = irqen & IRQEN_RSE; /* Rx FIFO Service Request IRQ Enable */
rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
*handled = false;
v4l2_dbg(2, ir_888_debug, sd, "IRQ Status: %s %s %s %s %s %s\n",
tsr ? "tsr" : " ", rsr ? "rsr" : " ",
rto ? "rto" : " ", ror ? "ror" : " ",
stats & STATS_TBY ? "tby" : " ",
stats & STATS_RBY ? "rby" : " ");
v4l2_dbg(2, ir_888_debug, sd, "IRQ Enables: %s %s %s %s\n",
tse ? "tse" : " ", rse ? "rse" : " ",
rte ? "rte" : " ", roe ? "roe" : " ");
/*
* Transmitter interrupt service
*/
if (tse && tsr) {
/*
* TODO:
* Check the watermark threshold setting
* Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
* Push the data to the hardware FIFO.
* If there was nothing more to send in the tx_kfifo, disable
* the TSR IRQ and notify the v4l2_device.
* If there was something in the tx_kfifo, check the tx_kfifo
* level and notify the v4l2_device, if it is low.
*/
/* For now, inhibit TSR interrupt until Tx is implemented */
irqenable_tx(dev, 0);
events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
*handled = true;
}
/*
* Receiver interrupt service
*/
kror = 0;
if ((rse && rsr) || (rte && rto)) {
/*
* Receive data on RSR to clear the STATS_RSR.
* Receive data on RTO, since we may not have yet hit the RSR
* watermark when we receive the RTO.
*/
for (i = 0, v = FIFO_RX_NDV;
(v & FIFO_RX_NDV) && !kror; i = 0) {
for (j = 0;
(v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG);
rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
i++;
}
if (i == 0)
break;
j = i * sizeof(union cx23888_ir_fifo_rec);
k = kfifo_in_locked(&state->rx_kfifo,
(unsigned char *) rx_data, j,
&state->rx_kfifo_lock);
if (k != j)
kror++; /* rx_kfifo over run */
}
*handled = true;
}
events = 0;
v = 0;
if (kror) {
events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
v4l2_err(sd, "IR receiver software FIFO overrun\n");
}
if (roe && ror) {
/*
* The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
* the Rx FIFO Over Run status (STATS_ROR)
*/
v |= CNTRL_RFE;
events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
}
if (rte && rto) {
/*
* The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
* the Rx Pulse Width Timer Time Out (STATS_RTO)
*/
v |= CNTRL_RXE;
events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
}
if (v) {
/* Clear STATS_ROR & STATS_RTO as needed by resetting hardware */
cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
*handled = true;
}
spin_lock_irqsave(&state->rx_kfifo_lock, flags);
if (kfifo_len(&state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2)
events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
if (events)
v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
return 0;
}
/* Receiver */
static int cx23888_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
ssize_t *num)
{
struct cx23888_ir_state *state = to_state(sd);
bool invert = (bool) atomic_read(&state->rx_invert);
u16 divider = (u16) atomic_read(&state->rxclk_divider);
unsigned int i, n;
union cx23888_ir_fifo_rec *p;
unsigned u, v, w;
n = count / sizeof(union cx23888_ir_fifo_rec)
* sizeof(union cx23888_ir_fifo_rec);
if (n == 0) {
*num = 0;
return 0;
}
n = kfifo_out_locked(&state->rx_kfifo, buf, n, &state->rx_kfifo_lock);
n /= sizeof(union cx23888_ir_fifo_rec);
*num = n * sizeof(union cx23888_ir_fifo_rec);
for (p = (union cx23888_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
/* Assume RTO was because of no IR light input */
u = 0;
w = 1;
} else {
u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
if (invert)
u = u ? 0 : 1;
w = 0;
}
v = (unsigned) pulse_width_count_to_ns(
(u16)(p->hw_fifo_data & FIFO_RXTX), divider) / 1000;
if (v > IR_MAX_DURATION)
v = IR_MAX_DURATION;
p->ir_core_data = (struct ir_raw_event)
{ .pulse = u, .duration = v, .timeout = w };
v4l2_dbg(2, ir_888_debug, sd, "rx read: %10u ns %s %s\n",
v, u ? "mark" : "space", w ? "(timed out)" : "");
if (w)
v4l2_dbg(2, ir_888_debug, sd, "rx read: end of rx\n");
}
return 0;
}
static int cx23888_ir_rx_g_parameters(struct v4l2_subdev *sd,
struct v4l2_subdev_ir_parameters *p)
{
struct cx23888_ir_state *state = to_state(sd);
mutex_lock(&state->rx_params_lock);
memcpy(p, &state->rx_params, sizeof(struct v4l2_subdev_ir_parameters));
mutex_unlock(&state->rx_params_lock);
return 0;
}
static int cx23888_ir_rx_shutdown(struct v4l2_subdev *sd)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
mutex_lock(&state->rx_params_lock);
/* Disable or slow down all IR Rx circuits and counters */
irqenable_rx(dev, 0);
control_rx_enable(dev, false);
control_rx_demodulation_enable(dev, false);
control_rx_s_edge_detection(dev, CNTRL_EDG_NONE);
filter_rx_s_min_width(dev, 0);
cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, RXCLK_RCD);
state->rx_params.shutdown = true;
mutex_unlock(&state->rx_params_lock);
return 0;
}
static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd,
struct v4l2_subdev_ir_parameters *p)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
struct v4l2_subdev_ir_parameters *o = &state->rx_params;
u16 rxclk_divider;
if (p->shutdown)
return cx23888_ir_rx_shutdown(sd);
if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
return -ENOSYS;
mutex_lock(&state->rx_params_lock);
o->shutdown = p->shutdown;
o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
o->bytes_per_data_element = p->bytes_per_data_element
= sizeof(union cx23888_ir_fifo_rec);
/* Before we tweak the hardware, we have to disable the receiver */
irqenable_rx(dev, 0);
control_rx_enable(dev, false);
control_rx_demodulation_enable(dev, p->modulation);
o->modulation = p->modulation;
if (p->modulation) {
p->carrier_freq = rxclk_rx_s_carrier(dev, p->carrier_freq,
&rxclk_divider);
o->carrier_freq = p->carrier_freq;
o->duty_cycle = p->duty_cycle = 50;
control_rx_s_carrier_window(dev, p->carrier_freq,
&p->carrier_range_lower,
&p->carrier_range_upper);
o->carrier_range_lower = p->carrier_range_lower;
o->carrier_range_upper = p->carrier_range_upper;
p->max_pulse_width =
(u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
} else {
p->max_pulse_width =
rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width,
&rxclk_divider);
}
o->max_pulse_width = p->max_pulse_width;
atomic_set(&state->rxclk_divider, rxclk_divider);
p->noise_filter_min_width =
filter_rx_s_min_width(dev, p->noise_filter_min_width);
o->noise_filter_min_width = p->noise_filter_min_width;
p->resolution = clock_divider_to_resolution(rxclk_divider);
o->resolution = p->resolution;
/* FIXME - make this dependent on resolution for better performance */
control_rx_irq_watermark(dev, RX_FIFO_HALF_FULL);
control_rx_s_edge_detection(dev, CNTRL_EDG_BOTH);
o->invert_level = p->invert_level;
atomic_set(&state->rx_invert, p->invert_level);
o->interrupt_enable = p->interrupt_enable;
o->enable = p->enable;
if (p->enable) {
unsigned long flags;
spin_lock_irqsave(&state->rx_kfifo_lock, flags);
kfifo_reset(&state->rx_kfifo);
/* reset tx_fifo too if there is one... */
spin_unlock_irqrestore(&state->rx_kfifo_lock, flags);
if (p->interrupt_enable)
irqenable_rx(dev, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
control_rx_enable(dev, p->enable);
}
mutex_unlock(&state->rx_params_lock);
return 0;
}
/* Transmitter */
static int cx23888_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
ssize_t *num)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
/* For now enable the Tx FIFO Service interrupt & pretend we did work */
irqenable_tx(dev, IRQEN_TSE);
*num = count;
return 0;
}
static int cx23888_ir_tx_g_parameters(struct v4l2_subdev *sd,
struct v4l2_subdev_ir_parameters *p)
{
struct cx23888_ir_state *state = to_state(sd);
mutex_lock(&state->tx_params_lock);
memcpy(p, &state->tx_params, sizeof(struct v4l2_subdev_ir_parameters));
mutex_unlock(&state->tx_params_lock);
return 0;
}
static int cx23888_ir_tx_shutdown(struct v4l2_subdev *sd)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
mutex_lock(&state->tx_params_lock);
/* Disable or slow down all IR Tx circuits and counters */
irqenable_tx(dev, 0);
control_tx_enable(dev, false);
control_tx_modulation_enable(dev, false);
cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, TXCLK_TCD);
state->tx_params.shutdown = true;
mutex_unlock(&state->tx_params_lock);
return 0;
}
static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd,
struct v4l2_subdev_ir_parameters *p)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
struct v4l2_subdev_ir_parameters *o = &state->tx_params;
u16 txclk_divider;
if (p->shutdown)
return cx23888_ir_tx_shutdown(sd);
if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
return -ENOSYS;
mutex_lock(&state->tx_params_lock);
o->shutdown = p->shutdown;
o->mode = p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
o->bytes_per_data_element = p->bytes_per_data_element
= sizeof(union cx23888_ir_fifo_rec);
/* Before we tweak the hardware, we have to disable the transmitter */
irqenable_tx(dev, 0);
control_tx_enable(dev, false);
control_tx_modulation_enable(dev, p->modulation);
o->modulation = p->modulation;
if (p->modulation) {
p->carrier_freq = txclk_tx_s_carrier(dev, p->carrier_freq,
&txclk_divider);
o->carrier_freq = p->carrier_freq;
p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle);
o->duty_cycle = p->duty_cycle;
p->max_pulse_width =
(u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
} else {
p->max_pulse_width =
txclk_tx_s_max_pulse_width(dev, p->max_pulse_width,
&txclk_divider);
}
o->max_pulse_width = p->max_pulse_width;
atomic_set(&state->txclk_divider, txclk_divider);
p->resolution = clock_divider_to_resolution(txclk_divider);
o->resolution = p->resolution;
/* FIXME - make this dependent on resolution for better performance */
control_tx_irq_watermark(dev, TX_FIFO_HALF_EMPTY);
control_tx_polarity_invert(dev, p->invert_carrier_sense);
o->invert_carrier_sense = p->invert_carrier_sense;
control_tx_level_invert(dev, p->invert_level);
o->invert_level = p->invert_level;
o->interrupt_enable = p->interrupt_enable;
o->enable = p->enable;
if (p->enable) {
if (p->interrupt_enable)
irqenable_tx(dev, IRQEN_TSE);
control_tx_enable(dev, p->enable);
}
mutex_unlock(&state->tx_params_lock);
return 0;
}
/*
* V4L2 Subdevice Core Ops
*/
static int cx23888_ir_log_status(struct v4l2_subdev *sd)
{
struct cx23888_ir_state *state = to_state(sd);
struct cx23885_dev *dev = state->dev;
char *s;
int i, j;
u32 cntrl = cx23888_ir_read4(dev, CX23888_IR_CNTRL_REG);
u32 txclk = cx23888_ir_read4(dev, CX23888_IR_TXCLK_REG) & TXCLK_TCD;
u32 rxclk = cx23888_ir_read4(dev, CX23888_IR_RXCLK_REG) & RXCLK_RCD;
u32 cduty = cx23888_ir_read4(dev, CX23888_IR_CDUTY_REG) & CDUTY_CDC;
u32 stats = cx23888_ir_read4(dev, CX23888_IR_STATS_REG);
u32 irqen = cx23888_ir_read4(dev, CX23888_IR_IRQEN_REG);
u32 filtr = cx23888_ir_read4(dev, CX23888_IR_FILTR_REG) & FILTR_LPF;
v4l2_info(sd, "IR Receiver:\n");
v4l2_info(sd, "\tEnabled: %s\n",
cntrl & CNTRL_RXE ? "yes" : "no");
v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
cntrl & CNTRL_DMD ? "enabled" : "disabled");
v4l2_info(sd, "\tFIFO: %s\n",
cntrl & CNTRL_RFE ? "enabled" : "disabled");
switch (cntrl & CNTRL_EDG) {
case CNTRL_EDG_NONE:
s = "disabled";
break;
case CNTRL_EDG_FALL:
s = "falling edge";
break;
case CNTRL_EDG_RISE:
s = "rising edge";
break;
case CNTRL_EDG_BOTH:
s = "rising & falling edges";
break;
default:
s = "??? edge";
break;
}
v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
cntrl & CNTRL_R ? "not loaded" : "overflow marker");
v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
v4l2_info(sd, "\tLoopback mode: %s\n",
cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
if (cntrl & CNTRL_DMD) {
v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
clock_divider_to_carrier_freq(rxclk));
switch (cntrl & CNTRL_WIN) {
case CNTRL_WIN_3_3:
i = 3;
j = 3;
break;
case CNTRL_WIN_4_3:
i = 4;
j = 3;
break;
case CNTRL_WIN_3_4:
i = 3;
j = 4;
break;
case CNTRL_WIN_4_4:
i = 4;
j = 4;
break;
default:
i = 0;
j = 0;
break;
}
v4l2_info(sd, "\tNext carrier edge window: 16 clocks -%1d/+%1d, %u to %u Hz\n",
i, j,
clock_divider_to_freq(rxclk, 16 + j),
clock_divider_to_freq(rxclk, 16 - i));
}
v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n",
pulse_width_count_to_us(FIFO_RXTX, rxclk),
pulse_width_count_to_ns(FIFO_RXTX, rxclk));
v4l2_info(sd, "\tLow pass filter: %s\n",
filtr ? "enabled" : "disabled");
if (filtr)
v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, %u ns\n",
lpf_count_to_us(filtr),
lpf_count_to_ns(filtr));
v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
stats & STATS_RTO ? "yes" : "no");
v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
irqen & IRQEN_RTE ? "enabled" : "disabled");
v4l2_info(sd, "\tFIFO overrun: %s\n",
stats & STATS_ROR ? "yes" : "no");
v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
irqen & IRQEN_ROE ? "enabled" : "disabled");
v4l2_info(sd, "\tBusy: %s\n",
stats & STATS_RBY ? "yes" : "no");
v4l2_info(sd, "\tFIFO service requested: %s\n",
stats & STATS_RSR ? "yes" : "no");
v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
irqen & IRQEN_RSE ? "enabled" : "disabled");
v4l2_info(sd, "IR Transmitter:\n");
v4l2_info(sd, "\tEnabled: %s\n",
cntrl & CNTRL_TXE ? "yes" : "no");
v4l2_info(sd, "\tModulation onto a carrier: %s\n",
cntrl & CNTRL_MOD ? "enabled" : "disabled");
v4l2_info(sd, "\tFIFO: %s\n",
cntrl & CNTRL_TFE ? "enabled" : "disabled");
v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
cntrl & CNTRL_TIC ? "not empty" : "half full or less");
v4l2_info(sd, "\tOutput pin level inversion %s\n",
cntrl & CNTRL_IVO ? "yes" : "no");
v4l2_info(sd, "\tCarrier polarity: %s\n",
cntrl & CNTRL_CPL ? "space:burst mark:noburst"
: "space:noburst mark:burst");
if (cntrl & CNTRL_MOD) {
v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
clock_divider_to_carrier_freq(txclk));
v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
cduty + 1);
}
v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n",
pulse_width_count_to_us(FIFO_RXTX, txclk),
pulse_width_count_to_ns(FIFO_RXTX, txclk));
v4l2_info(sd, "\tBusy: %s\n",
stats & STATS_TBY ? "yes" : "no");
v4l2_info(sd, "\tFIFO service requested: %s\n",
stats & STATS_TSR ? "yes" : "no");
v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
irqen & IRQEN_TSE ? "enabled" : "disabled");
return 0;
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int cx23888_ir_g_register(struct v4l2_subdev *sd,
struct v4l2_dbg_register *reg)
{
struct cx23888_ir_state *state = to_state(sd);
u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
if ((addr & 0x3) != 0)
return -EINVAL;
if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
return -EINVAL;
reg->size = 4;
reg->val = cx23888_ir_read4(state->dev, addr);
return 0;
}
static int cx23888_ir_s_register(struct v4l2_subdev *sd,
const struct v4l2_dbg_register *reg)
{
struct cx23888_ir_state *state = to_state(sd);
u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg;
if ((addr & 0x3) != 0)
return -EINVAL;
if (addr < CX23888_IR_CNTRL_REG || addr > CX23888_IR_LEARN_REG)
return -EINVAL;
cx23888_ir_write4(state->dev, addr, reg->val);
return 0;
}
#endif
static const struct v4l2_subdev_core_ops cx23888_ir_core_ops = {
.log_status = cx23888_ir_log_status,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.g_register = cx23888_ir_g_register,
.s_register = cx23888_ir_s_register,
#endif
.interrupt_service_routine = cx23888_ir_irq_handler,
};
static const struct v4l2_subdev_ir_ops cx23888_ir_ir_ops = {
.rx_read = cx23888_ir_rx_read,
.rx_g_parameters = cx23888_ir_rx_g_parameters,
.rx_s_parameters = cx23888_ir_rx_s_parameters,
.tx_write = cx23888_ir_tx_write,
.tx_g_parameters = cx23888_ir_tx_g_parameters,
.tx_s_parameters = cx23888_ir_tx_s_parameters,
};
static const struct v4l2_subdev_ops cx23888_ir_controller_ops = {
.core = &cx23888_ir_core_ops,
.ir = &cx23888_ir_ir_ops,
};
static const struct v4l2_subdev_ir_parameters default_rx_params = {
.bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
.mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
.enable = false,
.interrupt_enable = false,
.shutdown = true,
.modulation = true,
.carrier_freq = 36000, /* 36 kHz - RC-5, RC-6, and RC-6A carrier */
/* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
/* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
.noise_filter_min_width = 333333, /* ns */
.carrier_range_lower = 35000,
.carrier_range_upper = 37000,
.invert_level = false,
};
static const struct v4l2_subdev_ir_parameters default_tx_params = {
.bytes_per_data_element = sizeof(union cx23888_ir_fifo_rec),
.mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
.enable = false,
.interrupt_enable = false,
.shutdown = true,
.modulation = true,
.carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
.duty_cycle = 25, /* 25 % - RC-5 carrier */
.invert_level = false,
.invert_carrier_sense = false,
};
int cx23888_ir_probe(struct cx23885_dev *dev)
{
struct cx23888_ir_state *state;
struct v4l2_subdev *sd;
struct v4l2_subdev_ir_parameters default_params;
int ret;
state = kzalloc(sizeof(struct cx23888_ir_state), GFP_KERNEL);
if (state == NULL)
return -ENOMEM;
spin_lock_init(&state->rx_kfifo_lock);
if (kfifo_alloc(&state->rx_kfifo, CX23888_IR_RX_KFIFO_SIZE,
GFP_KERNEL)) {
kfree(state);
return -ENOMEM;
}
state->dev = dev;
sd = &state->sd;
v4l2_subdev_init(sd, &cx23888_ir_controller_ops);
v4l2_set_subdevdata(sd, state);
/* FIXME - fix the formatting of dev->v4l2_dev.name and use it */
snprintf(sd->name, sizeof(sd->name), "%s/888-ir", dev->name);
sd->grp_id = CX23885_HW_888_IR;
ret = v4l2_device_register_subdev(&dev->v4l2_dev, sd);
if (ret == 0) {
/*
* Ensure no interrupts arrive from '888 specific conditions,
* since we ignore them in this driver to have commonality with
* similar IR controller cores.
*/
cx23888_ir_write4(dev, CX23888_IR_IRQEN_REG, 0);
mutex_init(&state->rx_params_lock);
default_params = default_rx_params;
v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
mutex_init(&state->tx_params_lock);
default_params = default_tx_params;
v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
} else {
kfifo_free(&state->rx_kfifo);
}
return ret;
}
int cx23888_ir_remove(struct cx23885_dev *dev)
{
struct v4l2_subdev *sd;
struct cx23888_ir_state *state;
sd = cx23885_find_hw(dev, CX23885_HW_888_IR);
if (sd == NULL)
return -ENODEV;
cx23888_ir_rx_shutdown(sd);
cx23888_ir_tx_shutdown(sd);
state = to_state(sd);
v4l2_device_unregister_subdev(sd);
kfifo_free(&state->rx_kfifo);
kfree(state);
/* Nothing more to free() as state held the actual v4l2_subdev object */
return 0;
}
| linux-master | drivers/media/pci/cx23885/cx23888-ir.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Conexant CX23885/7/8 PCIe bridge
*
* Infrared remote control input device
*
* Most of this file is
*
* Copyright (C) 2009 Andy Walls <[email protected]>
*
* However, the cx23885_input_{init,fini} functions contained herein are
* derived from Linux kernel files linux/media/video/.../...-input.c marked as:
*
* Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
* Copyright (C) 2005 Ludovico Cavedon <[email protected]>
* Markus Rechberger <[email protected]>
* Mauro Carvalho Chehab <[email protected]>
* Sascha Sommer <[email protected]>
* Copyright (C) 2004, 2005 Chris Pascoe
* Copyright (C) 2003, 2004 Gerd Knorr
* Copyright (C) 2003 Pavel Machek
*/
#include "cx23885.h"
#include "cx23885-input.h"
#include <linux/slab.h>
#include <media/rc-core.h>
#include <media/v4l2-subdev.h>
#define MODULE_NAME "cx23885"
static void cx23885_input_process_measurements(struct cx23885_dev *dev,
bool overrun)
{
struct cx23885_kernel_ir *kernel_ir = dev->kernel_ir;
ssize_t num;
int count, i;
bool handle = false;
struct ir_raw_event ir_core_event[64];
do {
num = 0;
v4l2_subdev_call(dev->sd_ir, ir, rx_read, (u8 *) ir_core_event,
sizeof(ir_core_event), &num);
count = num / sizeof(struct ir_raw_event);
for (i = 0; i < count; i++) {
ir_raw_event_store(kernel_ir->rc,
&ir_core_event[i]);
handle = true;
}
} while (num != 0);
if (overrun)
ir_raw_event_overflow(kernel_ir->rc);
else if (handle)
ir_raw_event_handle(kernel_ir->rc);
}
void cx23885_input_rx_work_handler(struct cx23885_dev *dev, u32 events)
{
struct v4l2_subdev_ir_parameters params;
int overrun, data_available;
if (dev->sd_ir == NULL || events == 0)
return;
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1270:
case CX23885_BOARD_HAUPPAUGE_HVR1850:
case CX23885_BOARD_HAUPPAUGE_HVR1290:
case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
case CX23885_BOARD_TEVII_S470:
case CX23885_BOARD_HAUPPAUGE_HVR1250:
case CX23885_BOARD_MYGICA_X8507:
case CX23885_BOARD_TBS_6980:
case CX23885_BOARD_TBS_6981:
case CX23885_BOARD_DVBSKY_T9580:
case CX23885_BOARD_DVBSKY_T980C:
case CX23885_BOARD_DVBSKY_S950C:
case CX23885_BOARD_TT_CT2_4500_CI:
case CX23885_BOARD_DVBSKY_S950:
case CX23885_BOARD_DVBSKY_S952:
case CX23885_BOARD_DVBSKY_T982:
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
/*
* The only boards we handle right now. However other boards
* using the CX2388x integrated IR controller should be similar
*/
break;
default:
return;
}
overrun = events & (V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN |
V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN);
data_available = events & (V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED |
V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ);
if (overrun) {
/* If there was a FIFO overrun, stop the device */
v4l2_subdev_call(dev->sd_ir, ir, rx_g_parameters, ¶ms);
params.enable = false;
/* Mitigate race with cx23885_input_ir_stop() */
params.shutdown = atomic_read(&dev->ir_input_stopping);
v4l2_subdev_call(dev->sd_ir, ir, rx_s_parameters, ¶ms);
}
if (data_available)
cx23885_input_process_measurements(dev, overrun);
if (overrun) {
/* If there was a FIFO overrun, clear & restart the device */
params.enable = true;
/* Mitigate race with cx23885_input_ir_stop() */
params.shutdown = atomic_read(&dev->ir_input_stopping);
v4l2_subdev_call(dev->sd_ir, ir, rx_s_parameters, ¶ms);
}
}
static int cx23885_input_ir_start(struct cx23885_dev *dev)
{
struct v4l2_subdev_ir_parameters params;
if (dev->sd_ir == NULL)
return -ENODEV;
atomic_set(&dev->ir_input_stopping, 0);
v4l2_subdev_call(dev->sd_ir, ir, rx_g_parameters, ¶ms);
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1270:
case CX23885_BOARD_HAUPPAUGE_HVR1850:
case CX23885_BOARD_HAUPPAUGE_HVR1290:
case CX23885_BOARD_HAUPPAUGE_HVR1250:
case CX23885_BOARD_MYGICA_X8507:
case CX23885_BOARD_DVBSKY_T9580:
case CX23885_BOARD_DVBSKY_T980C:
case CX23885_BOARD_DVBSKY_S950C:
case CX23885_BOARD_TT_CT2_4500_CI:
case CX23885_BOARD_DVBSKY_S950:
case CX23885_BOARD_DVBSKY_S952:
case CX23885_BOARD_DVBSKY_T982:
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
/*
* The IR controller on this board only returns pulse widths.
* Any other mode setting will fail to set up the device.
*/
params.mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
params.enable = true;
params.interrupt_enable = true;
params.shutdown = false;
/* Setup for baseband compatible with both RC-5 and RC-6A */
params.modulation = false;
/* RC-5: 2,222,222 ns = 1/36 kHz * 32 cycles * 2 marks * 1.25*/
/* RC-6A: 3,333,333 ns = 1/36 kHz * 16 cycles * 6 marks * 1.25*/
params.max_pulse_width = 3333333; /* ns */
/* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
/* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
params.noise_filter_min_width = 333333; /* ns */
/*
* This board has inverted receive sense:
* mark is received as low logic level;
* falling edges are detected as rising edges; etc.
*/
params.invert_level = true;
break;
case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
case CX23885_BOARD_TEVII_S470:
case CX23885_BOARD_TBS_6980:
case CX23885_BOARD_TBS_6981:
/*
* The IR controller on this board only returns pulse widths.
* Any other mode setting will fail to set up the device.
*/
params.mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
params.enable = true;
params.interrupt_enable = true;
params.shutdown = false;
/* Setup for a standard NEC protocol */
params.carrier_freq = 37917; /* Hz, 455 kHz/12 for NEC */
params.carrier_range_lower = 33000; /* Hz */
params.carrier_range_upper = 43000; /* Hz */
params.duty_cycle = 33; /* percent, 33 percent for NEC */
/*
* NEC max pulse width: (64/3)/(455 kHz/12) * 16 nec_units
* (64/3)/(455 kHz/12) * 16 nec_units * 1.375 = 12378022 ns
*/
params.max_pulse_width = 12378022; /* ns */
/*
* NEC noise filter min width: (64/3)/(455 kHz/12) * 1 nec_unit
* (64/3)/(455 kHz/12) * 1 nec_units * 0.625 = 351648 ns
*/
params.noise_filter_min_width = 351648; /* ns */
params.modulation = false;
params.invert_level = true;
break;
}
v4l2_subdev_call(dev->sd_ir, ir, rx_s_parameters, ¶ms);
return 0;
}
static int cx23885_input_ir_open(struct rc_dev *rc)
{
struct cx23885_kernel_ir *kernel_ir = rc->priv;
if (kernel_ir->cx == NULL)
return -ENODEV;
return cx23885_input_ir_start(kernel_ir->cx);
}
static void cx23885_input_ir_stop(struct cx23885_dev *dev)
{
struct v4l2_subdev_ir_parameters params;
if (dev->sd_ir == NULL)
return;
/*
* Stop the sd_ir subdevice from generating notifications and
* scheduling work.
* It is shutdown this way in order to mitigate a race with
* cx23885_input_rx_work_handler() in the overrun case, which could
* re-enable the subdevice.
*/
atomic_set(&dev->ir_input_stopping, 1);
v4l2_subdev_call(dev->sd_ir, ir, rx_g_parameters, ¶ms);
while (params.shutdown == false) {
params.enable = false;
params.interrupt_enable = false;
params.shutdown = true;
v4l2_subdev_call(dev->sd_ir, ir, rx_s_parameters, ¶ms);
v4l2_subdev_call(dev->sd_ir, ir, rx_g_parameters, ¶ms);
}
flush_work(&dev->cx25840_work);
flush_work(&dev->ir_rx_work);
flush_work(&dev->ir_tx_work);
}
static void cx23885_input_ir_close(struct rc_dev *rc)
{
struct cx23885_kernel_ir *kernel_ir = rc->priv;
if (kernel_ir->cx != NULL)
cx23885_input_ir_stop(kernel_ir->cx);
}
int cx23885_input_init(struct cx23885_dev *dev)
{
struct cx23885_kernel_ir *kernel_ir;
struct rc_dev *rc;
char *rc_map;
u64 allowed_protos;
int ret;
/*
* If the IR device (hardware registers, chip, GPIO lines, etc.) isn't
* encapsulated in a v4l2_subdev, then I'm not going to deal with it.
*/
if (dev->sd_ir == NULL)
return -ENODEV;
switch (dev->board) {
case CX23885_BOARD_HAUPPAUGE_HVR1270:
case CX23885_BOARD_HAUPPAUGE_HVR1850:
case CX23885_BOARD_HAUPPAUGE_HVR1290:
case CX23885_BOARD_HAUPPAUGE_HVR1250:
case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
/* Integrated CX2388[58] IR controller */
allowed_protos = RC_PROTO_BIT_ALL_IR_DECODER;
/* The grey Hauppauge RC-5 remote */
rc_map = RC_MAP_HAUPPAUGE;
break;
case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
/* Integrated CX23885 IR controller */
allowed_protos = RC_PROTO_BIT_ALL_IR_DECODER;
/* The grey Terratec remote with orange buttons */
rc_map = RC_MAP_NEC_TERRATEC_CINERGY_XS;
break;
case CX23885_BOARD_TEVII_S470:
/* Integrated CX23885 IR controller */
allowed_protos = RC_PROTO_BIT_ALL_IR_DECODER;
/* A guess at the remote */
rc_map = RC_MAP_TEVII_NEC;
break;
case CX23885_BOARD_MYGICA_X8507:
/* Integrated CX23885 IR controller */
allowed_protos = RC_PROTO_BIT_ALL_IR_DECODER;
/* A guess at the remote */
rc_map = RC_MAP_TOTAL_MEDIA_IN_HAND_02;
break;
case CX23885_BOARD_TBS_6980:
case CX23885_BOARD_TBS_6981:
/* Integrated CX23885 IR controller */
allowed_protos = RC_PROTO_BIT_ALL_IR_DECODER;
/* A guess at the remote */
rc_map = RC_MAP_TBS_NEC;
break;
case CX23885_BOARD_DVBSKY_T9580:
case CX23885_BOARD_DVBSKY_T980C:
case CX23885_BOARD_DVBSKY_S950C:
case CX23885_BOARD_DVBSKY_S950:
case CX23885_BOARD_DVBSKY_S952:
case CX23885_BOARD_DVBSKY_T982:
/* Integrated CX23885 IR controller */
allowed_protos = RC_PROTO_BIT_ALL_IR_DECODER;
rc_map = RC_MAP_DVBSKY;
break;
case CX23885_BOARD_TT_CT2_4500_CI:
/* Integrated CX23885 IR controller */
allowed_protos = RC_PROTO_BIT_ALL_IR_DECODER;
rc_map = RC_MAP_TT_1500;
break;
default:
return -ENODEV;
}
/* cx23885 board instance kernel IR state */
kernel_ir = kzalloc(sizeof(struct cx23885_kernel_ir), GFP_KERNEL);
if (kernel_ir == NULL)
return -ENOMEM;
kernel_ir->cx = dev;
kernel_ir->name = kasprintf(GFP_KERNEL, "cx23885 IR (%s)",
cx23885_boards[dev->board].name);
if (!kernel_ir->name) {
ret = -ENOMEM;
goto err_out_free;
}
kernel_ir->phys = kasprintf(GFP_KERNEL, "pci-%s/ir0",
pci_name(dev->pci));
if (!kernel_ir->phys) {
ret = -ENOMEM;
goto err_out_free_name;
}
/* input device */
rc = rc_allocate_device(RC_DRIVER_IR_RAW);
if (!rc) {
ret = -ENOMEM;
goto err_out_free_phys;
}
kernel_ir->rc = rc;
rc->device_name = kernel_ir->name;
rc->input_phys = kernel_ir->phys;
rc->input_id.bustype = BUS_PCI;
rc->input_id.version = 1;
if (dev->pci->subsystem_vendor) {
rc->input_id.vendor = dev->pci->subsystem_vendor;
rc->input_id.product = dev->pci->subsystem_device;
} else {
rc->input_id.vendor = dev->pci->vendor;
rc->input_id.product = dev->pci->device;
}
rc->dev.parent = &dev->pci->dev;
rc->allowed_protocols = allowed_protos;
rc->priv = kernel_ir;
rc->open = cx23885_input_ir_open;
rc->close = cx23885_input_ir_close;
rc->map_name = rc_map;
rc->driver_name = MODULE_NAME;
/* Go */
dev->kernel_ir = kernel_ir;
ret = rc_register_device(rc);
if (ret)
goto err_out_stop;
return 0;
err_out_stop:
cx23885_input_ir_stop(dev);
dev->kernel_ir = NULL;
rc_free_device(rc);
err_out_free_phys:
kfree(kernel_ir->phys);
err_out_free_name:
kfree(kernel_ir->name);
err_out_free:
kfree(kernel_ir);
return ret;
}
void cx23885_input_fini(struct cx23885_dev *dev)
{
/* Always stop the IR hardware from generating interrupts */
cx23885_input_ir_stop(dev);
if (dev->kernel_ir == NULL)
return;
rc_unregister_device(dev->kernel_ir->rc);
kfree(dev->kernel_ir->phys);
kfree(dev->kernel_ir->name);
kfree(dev->kernel_ir);
dev->kernel_ir = NULL;
}
| linux-master | drivers/media/pci/cx23885/cx23885-input.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 ADEC firmware functions
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include <linux/firmware.h>
#define CX18_AUDIO_ENABLE 0xc72014
#define CX18_AI1_MUX_MASK 0x30
#define CX18_AI1_MUX_I2S1 0x00
#define CX18_AI1_MUX_I2S2 0x10
#define CX18_AI1_MUX_843_I2S 0x20
#define CX18_AI1_MUX_INVALID 0x30
#define FWFILE "v4l-cx23418-dig.fw"
static int cx18_av_verifyfw(struct cx18 *cx, const struct firmware *fw)
{
struct v4l2_subdev *sd = &cx->av_state.sd;
int ret = 0;
const u8 *data;
u32 size;
int addr;
u32 expected, dl_control;
/* Ensure we put the 8051 in reset and enable firmware upload mode */
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
do {
dl_control &= 0x00ffffff;
dl_control |= 0x0f000000;
cx18_av_write4_noretry(cx, CXADEC_DL_CTL, dl_control);
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
} while ((dl_control & 0xff000000) != 0x0f000000);
/* Read and auto increment until at address 0x0000 */
while (dl_control & 0x3fff)
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
data = fw->data;
size = fw->size;
for (addr = 0; addr < size; addr++) {
dl_control &= 0xffff3fff; /* ignore top 2 bits of address */
expected = 0x0f000000 | ((u32)data[addr] << 16) | addr;
if (expected != dl_control) {
CX18_ERR_DEV(sd, "verification of %s firmware load failed: expected %#010x got %#010x\n",
FWFILE, expected, dl_control);
ret = -EIO;
break;
}
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
}
if (ret == 0)
CX18_INFO_DEV(sd, "verified load of %s firmware (%d bytes)\n",
FWFILE, size);
return ret;
}
int cx18_av_loadfw(struct cx18 *cx)
{
struct v4l2_subdev *sd = &cx->av_state.sd;
const struct firmware *fw = NULL;
u32 size;
u32 u, v;
const u8 *ptr;
int i;
int retries1 = 0;
if (request_firmware(&fw, FWFILE, &cx->pci_dev->dev) != 0) {
CX18_ERR_DEV(sd, "unable to open firmware %s\n", FWFILE);
return -EINVAL;
}
/* The firmware load often has byte errors, so allow for several
retries, both at byte level and at the firmware load level. */
while (retries1 < 5) {
cx18_av_write4_expect(cx, CXADEC_CHIP_CTRL, 0x00010000,
0x00008430, 0xffffffff); /* cx25843 */
cx18_av_write_expect(cx, CXADEC_STD_DET_CTL, 0xf6, 0xf6, 0xff);
/* Reset the Mako core, Register is alias of CXADEC_CHIP_CTRL */
cx18_av_write4_expect(cx, 0x8100, 0x00010000,
0x00008430, 0xffffffff); /* cx25843 */
/* Put the 8051 in reset and enable firmware upload */
cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);
ptr = fw->data;
size = fw->size;
for (i = 0; i < size; i++) {
u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
u32 value = 0;
int retries2;
int unrec_err = 0;
for (retries2 = 0; retries2 < CX18_MAX_MMIO_WR_RETRIES;
retries2++) {
cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
dl_control);
udelay(10);
value = cx18_av_read4(cx, CXADEC_DL_CTL);
if (value == dl_control)
break;
/* Check if we can correct the byte by changing
the address. We can only write the lower
address byte of the address. */
if ((value & 0x3F00) != (dl_control & 0x3F00)) {
unrec_err = 1;
break;
}
}
if (unrec_err || retries2 >= CX18_MAX_MMIO_WR_RETRIES)
break;
}
if (i == size)
break;
retries1++;
}
if (retries1 >= 5) {
CX18_ERR_DEV(sd, "unable to load firmware %s\n", FWFILE);
release_firmware(fw);
return -EIO;
}
cx18_av_write4_expect(cx, CXADEC_DL_CTL,
0x03000000 | fw->size, 0x03000000, 0x13000000);
CX18_INFO_DEV(sd, "loaded %s firmware (%d bytes)\n", FWFILE, size);
if (cx18_av_verifyfw(cx, fw) == 0)
cx18_av_write4_expect(cx, CXADEC_DL_CTL,
0x13000000 | fw->size, 0x13000000, 0x13000000);
/* Output to the 416 */
cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000);
/* Audio input control 1 set to Sony mode */
/* Audio output input 2 is 0 for slave operation input */
/* 0xC4000914[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
/* 0xC4000914[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
after WS transition for first bit of audio word. */
cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0);
/* Audio output control 1 is set to Sony mode */
/* Audio output control 2 is set to 1 for master mode */
/* 0xC4000918[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
/* 0xC4000918[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
after WS transition for first bit of audio word. */
/* 0xC4000918[8]: 0 = slave operation, 1 = master (SCK_OUT and WS_OUT
are generated) */
cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);
/* set alt I2s master clock to /0x16 and enable alt divider i2s
passthrough */
cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687);
cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6,
0x3F00FFFF);
/* CxDevWrReg(CXADEC_STD_DET_CTL, 0x000000FF); */
/* Set bit 0 in register 0x9CC to signify that this is MiniMe. */
/* Register 0x09CC is defined by the Merlin firmware, and doesn't
have a name in the spec. */
cx18_av_write4(cx, 0x09CC, 1);
v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
/* If bit 11 is 1, clear bit 10 */
if (v & 0x800)
cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE,
0, 0x400);
/* Toggle the AI1 MUX */
v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
u = v & CX18_AI1_MUX_MASK;
v &= ~CX18_AI1_MUX_MASK;
if (u == CX18_AI1_MUX_843_I2S || u == CX18_AI1_MUX_INVALID) {
/* Switch to I2S1 */
v |= CX18_AI1_MUX_I2S1;
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
v, CX18_AI1_MUX_MASK);
/* Switch back to the A/V decoder core I2S output */
v = (v & ~CX18_AI1_MUX_MASK) | CX18_AI1_MUX_843_I2S;
} else {
/* Switch to the A/V decoder core I2S output */
v |= CX18_AI1_MUX_843_I2S;
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
v, CX18_AI1_MUX_MASK);
/* Switch back to I2S1 or I2S2 */
v = (v & ~CX18_AI1_MUX_MASK) | u;
}
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
v, CX18_AI1_MUX_MASK);
/* Enable WW auto audio standard detection */
v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
v |= 0xFF; /* Auto by default */
v |= 0x400; /* Stereo by default */
v |= 0x14000000;
cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF);
release_firmware(fw);
return 0;
}
MODULE_FIRMWARE(FWFILE);
| linux-master | drivers/media/pci/cx18/cx18-av-firmware.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 I2C functions
*
* Derived from ivtv-i2c.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-cards.h"
#include "cx18-gpio.h"
#include "cx18-i2c.h"
#include "cx18-irq.h"
#define CX18_REG_I2C_1_WR 0xf15000
#define CX18_REG_I2C_1_RD 0xf15008
#define CX18_REG_I2C_2_WR 0xf25100
#define CX18_REG_I2C_2_RD 0xf25108
#define SETSCL_BIT 0x0001
#define SETSDL_BIT 0x0002
#define GETSCL_BIT 0x0004
#define GETSDL_BIT 0x0008
#define CX18_CS5345_I2C_ADDR 0x4c
#define CX18_Z8F0811_IR_TX_I2C_ADDR 0x70
#define CX18_Z8F0811_IR_RX_I2C_ADDR 0x71
/* This array should match the CX18_HW_ defines */
static const u8 hw_addrs[] = {
0, /* CX18_HW_TUNER */
0, /* CX18_HW_TVEEPROM */
CX18_CS5345_I2C_ADDR, /* CX18_HW_CS5345 */
0, /* CX18_HW_DVB */
0, /* CX18_HW_418_AV */
0, /* CX18_HW_GPIO_MUX */
0, /* CX18_HW_GPIO_RESET_CTRL */
CX18_Z8F0811_IR_RX_I2C_ADDR, /* CX18_HW_Z8F0811_IR_HAUP */
};
/* This array should match the CX18_HW_ defines */
/* This might well become a card-specific array */
static const u8 hw_bus[] = {
1, /* CX18_HW_TUNER */
0, /* CX18_HW_TVEEPROM */
0, /* CX18_HW_CS5345 */
0, /* CX18_HW_DVB */
0, /* CX18_HW_418_AV */
0, /* CX18_HW_GPIO_MUX */
0, /* CX18_HW_GPIO_RESET_CTRL */
0, /* CX18_HW_Z8F0811_IR_HAUP */
};
/* This array should match the CX18_HW_ defines */
static const char * const hw_devicenames[] = {
"tuner",
"tveeprom",
"cs5345",
"cx23418_DTV",
"cx23418_AV",
"gpio_mux",
"gpio_reset_ctrl",
"ir_z8f0811_haup",
};
static int cx18_i2c_new_ir(struct cx18 *cx, struct i2c_adapter *adap, u32 hw,
const char *type, u8 addr)
{
struct i2c_board_info info;
struct IR_i2c_init_data *init_data = &cx->ir_i2c_init_data;
unsigned short addr_list[2] = { addr, I2C_CLIENT_END };
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, type, I2C_NAME_SIZE);
/* Our default information for ir-kbd-i2c.c to use */
switch (hw) {
case CX18_HW_Z8F0811_IR_HAUP:
init_data->ir_codes = RC_MAP_HAUPPAUGE;
init_data->internal_get_key_func = IR_KBD_GET_KEY_HAUP_XVR;
init_data->type = RC_PROTO_BIT_RC5 | RC_PROTO_BIT_RC6_MCE |
RC_PROTO_BIT_RC6_6A_32;
init_data->name = cx->card_name;
info.platform_data = init_data;
break;
}
return IS_ERR(i2c_new_scanned_device(adap, &info, addr_list, NULL)) ?
-1 : 0;
}
int cx18_i2c_register(struct cx18 *cx, unsigned idx)
{
struct v4l2_subdev *sd;
int bus = hw_bus[idx];
struct i2c_adapter *adap = &cx->i2c_adap[bus];
const char *type = hw_devicenames[idx];
u32 hw = 1 << idx;
if (hw == CX18_HW_TUNER) {
/* special tuner group handling */
sd = v4l2_i2c_new_subdev(&cx->v4l2_dev,
adap, type, 0, cx->card_i2c->radio);
if (sd != NULL)
sd->grp_id = hw;
sd = v4l2_i2c_new_subdev(&cx->v4l2_dev,
adap, type, 0, cx->card_i2c->demod);
if (sd != NULL)
sd->grp_id = hw;
sd = v4l2_i2c_new_subdev(&cx->v4l2_dev,
adap, type, 0, cx->card_i2c->tv);
if (sd != NULL)
sd->grp_id = hw;
return sd != NULL ? 0 : -1;
}
if (hw == CX18_HW_Z8F0811_IR_HAUP)
return cx18_i2c_new_ir(cx, adap, hw, type, hw_addrs[idx]);
/* Is it not an I2C device or one we do not wish to register? */
if (!hw_addrs[idx])
return -1;
/* It's an I2C device other than an analog tuner or IR chip */
sd = v4l2_i2c_new_subdev(&cx->v4l2_dev, adap, type, hw_addrs[idx],
NULL);
if (sd != NULL)
sd->grp_id = hw;
return sd != NULL ? 0 : -1;
}
/* Find the first member of the subdev group id in hw */
struct v4l2_subdev *cx18_find_hw(struct cx18 *cx, u32 hw)
{
struct v4l2_subdev *result = NULL;
struct v4l2_subdev *sd;
spin_lock(&cx->v4l2_dev.lock);
v4l2_device_for_each_subdev(sd, &cx->v4l2_dev) {
if (sd->grp_id == hw) {
result = sd;
break;
}
}
spin_unlock(&cx->v4l2_dev.lock);
return result;
}
static void cx18_setscl(void *data, int state)
{
struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx;
int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index;
u32 addr = bus_index ? CX18_REG_I2C_2_WR : CX18_REG_I2C_1_WR;
u32 r = cx18_read_reg(cx, addr);
if (state)
cx18_write_reg(cx, r | SETSCL_BIT, addr);
else
cx18_write_reg(cx, r & ~SETSCL_BIT, addr);
}
static void cx18_setsda(void *data, int state)
{
struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx;
int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index;
u32 addr = bus_index ? CX18_REG_I2C_2_WR : CX18_REG_I2C_1_WR;
u32 r = cx18_read_reg(cx, addr);
if (state)
cx18_write_reg(cx, r | SETSDL_BIT, addr);
else
cx18_write_reg(cx, r & ~SETSDL_BIT, addr);
}
static int cx18_getscl(void *data)
{
struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx;
int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index;
u32 addr = bus_index ? CX18_REG_I2C_2_RD : CX18_REG_I2C_1_RD;
return cx18_read_reg(cx, addr) & GETSCL_BIT;
}
static int cx18_getsda(void *data)
{
struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx;
int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index;
u32 addr = bus_index ? CX18_REG_I2C_2_RD : CX18_REG_I2C_1_RD;
return cx18_read_reg(cx, addr) & GETSDL_BIT;
}
/* template for i2c-bit-algo */
static const struct i2c_adapter cx18_i2c_adap_template = {
.name = "cx18 i2c driver",
.algo = NULL, /* set by i2c-algo-bit */
.algo_data = NULL, /* filled from template */
.owner = THIS_MODULE,
};
#define CX18_SCL_PERIOD (10) /* usecs. 10 usec is period for a 100 KHz clock */
#define CX18_ALGO_BIT_TIMEOUT (2) /* seconds */
static const struct i2c_algo_bit_data cx18_i2c_algo_template = {
.setsda = cx18_setsda,
.setscl = cx18_setscl,
.getsda = cx18_getsda,
.getscl = cx18_getscl,
.udelay = CX18_SCL_PERIOD/2, /* 1/2 clock period in usec*/
.timeout = CX18_ALGO_BIT_TIMEOUT*HZ /* jiffies */
};
/* init + register i2c adapter */
int init_cx18_i2c(struct cx18 *cx)
{
int i, err;
CX18_DEBUG_I2C("i2c init\n");
for (i = 0; i < 2; i++) {
/* Setup algorithm for adapter */
cx->i2c_algo[i] = cx18_i2c_algo_template;
cx->i2c_algo_cb_data[i].cx = cx;
cx->i2c_algo_cb_data[i].bus_index = i;
cx->i2c_algo[i].data = &cx->i2c_algo_cb_data[i];
/* Setup adapter */
cx->i2c_adap[i] = cx18_i2c_adap_template;
cx->i2c_adap[i].algo_data = &cx->i2c_algo[i];
sprintf(cx->i2c_adap[i].name + strlen(cx->i2c_adap[i].name),
" #%d-%d", cx->instance, i);
i2c_set_adapdata(&cx->i2c_adap[i], &cx->v4l2_dev);
cx->i2c_adap[i].dev.parent = &cx->pci_dev->dev;
}
if (cx18_read_reg(cx, CX18_REG_I2C_2_WR) != 0x0003c02f) {
/* Reset/Unreset I2C hardware block */
/* Clock select 220MHz */
cx18_write_reg_expect(cx, 0x10000000, 0xc71004,
0x00000000, 0x10001000);
/* Clock Enable */
cx18_write_reg_expect(cx, 0x10001000, 0xc71024,
0x00001000, 0x10001000);
}
/* courtesy of Steven Toth <[email protected]> */
cx18_write_reg_expect(cx, 0x00c00000, 0xc7001c, 0x00000000, 0x00c000c0);
mdelay(10);
cx18_write_reg_expect(cx, 0x00c000c0, 0xc7001c, 0x000000c0, 0x00c000c0);
mdelay(10);
cx18_write_reg_expect(cx, 0x00c00000, 0xc7001c, 0x00000000, 0x00c000c0);
mdelay(10);
/* Set to edge-triggered intrs. */
cx18_write_reg(cx, 0x00c00000, 0xc730c8);
/* Clear any stale intrs */
cx18_write_reg_expect(cx, HW2_I2C1_INT|HW2_I2C2_INT, HW2_INT_CLR_STATUS,
~(HW2_I2C1_INT|HW2_I2C2_INT), HW2_I2C1_INT|HW2_I2C2_INT);
/* Hw I2C1 Clock Freq ~100kHz */
cx18_write_reg(cx, 0x00021c0f & ~4, CX18_REG_I2C_1_WR);
cx18_setscl(&cx->i2c_algo_cb_data[0], 1);
cx18_setsda(&cx->i2c_algo_cb_data[0], 1);
/* Hw I2C2 Clock Freq ~100kHz */
cx18_write_reg(cx, 0x00021c0f & ~4, CX18_REG_I2C_2_WR);
cx18_setscl(&cx->i2c_algo_cb_data[1], 1);
cx18_setsda(&cx->i2c_algo_cb_data[1], 1);
cx18_call_hw(cx, CX18_HW_GPIO_RESET_CTRL,
core, reset, (u32) CX18_GPIO_RESET_I2C);
err = i2c_bit_add_bus(&cx->i2c_adap[0]);
if (err)
goto err;
err = i2c_bit_add_bus(&cx->i2c_adap[1]);
if (err)
goto err_del_bus_0;
return 0;
err_del_bus_0:
i2c_del_adapter(&cx->i2c_adap[0]);
err:
return err;
}
void exit_cx18_i2c(struct cx18 *cx)
{
int i;
CX18_DEBUG_I2C("i2c exit\n");
cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_1_WR) | 4,
CX18_REG_I2C_1_WR);
cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_2_WR) | 4,
CX18_REG_I2C_2_WR);
for (i = 0; i < 2; i++) {
i2c_del_adapter(&cx->i2c_adap[i]);
}
}
/*
Hauppauge HVR1600 should have:
32 cx24227
98 unknown
a0 eeprom
c2 tuner
e? zilog ir
*/
| linux-master | drivers/media/pci/cx18/cx18-i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 ioctl control functions
*
* Derived from ivtv-controls.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include "cx18-driver.h"
#include "cx18-cards.h"
#include "cx18-ioctl.h"
#include "cx18-audio.h"
#include "cx18-mailbox.h"
#include "cx18-controls.h"
static int cx18_s_stream_vbi_fmt(struct cx2341x_handler *cxhdl, u32 fmt)
{
struct cx18 *cx = container_of(cxhdl, struct cx18, cxhdl);
int type = cxhdl->stream_type->val;
if (atomic_read(&cx->ana_capturing) > 0)
return -EBUSY;
if (fmt != V4L2_MPEG_STREAM_VBI_FMT_IVTV ||
!(type == V4L2_MPEG_STREAM_TYPE_MPEG2_PS ||
type == V4L2_MPEG_STREAM_TYPE_MPEG2_DVD ||
type == V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD)) {
/* Only IVTV fmt VBI insertion & only MPEG-2 PS type streams */
cx->vbi.insert_mpeg = V4L2_MPEG_STREAM_VBI_FMT_NONE;
CX18_DEBUG_INFO("disabled insertion of sliced VBI data into the MPEG stream\n");
return 0;
}
/* Allocate sliced VBI buffers if needed. */
if (cx->vbi.sliced_mpeg_data[0] == NULL) {
int i;
for (i = 0; i < CX18_VBI_FRAMES; i++) {
cx->vbi.sliced_mpeg_data[i] =
kmalloc(CX18_SLICED_MPEG_DATA_BUFSZ, GFP_KERNEL);
if (cx->vbi.sliced_mpeg_data[i] == NULL) {
while (--i >= 0) {
kfree(cx->vbi.sliced_mpeg_data[i]);
cx->vbi.sliced_mpeg_data[i] = NULL;
}
cx->vbi.insert_mpeg =
V4L2_MPEG_STREAM_VBI_FMT_NONE;
CX18_WARN("Unable to allocate buffers for sliced VBI data insertion\n");
return -ENOMEM;
}
}
}
cx->vbi.insert_mpeg = fmt;
CX18_DEBUG_INFO("enabled insertion of sliced VBI data into the MPEG PS,when sliced VBI is enabled\n");
/*
* If our current settings have no lines set for capture, store a valid,
* default set of service lines to capture, in our current settings.
*/
if (cx18_get_service_set(cx->vbi.sliced_in) == 0) {
if (cx->is_60hz)
cx->vbi.sliced_in->service_set =
V4L2_SLICED_CAPTION_525;
else
cx->vbi.sliced_in->service_set = V4L2_SLICED_WSS_625;
cx18_expand_service_set(cx->vbi.sliced_in, cx->is_50hz);
}
return 0;
}
static int cx18_s_video_encoding(struct cx2341x_handler *cxhdl, u32 val)
{
struct cx18 *cx = container_of(cxhdl, struct cx18, cxhdl);
int is_mpeg1 = val == V4L2_MPEG_VIDEO_ENCODING_MPEG_1;
struct v4l2_subdev_format format = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
struct v4l2_mbus_framefmt *fmt = &format.format;
/* fix videodecoder resolution */
fmt->width = cxhdl->width / (is_mpeg1 ? 2 : 1);
fmt->height = cxhdl->height;
fmt->code = MEDIA_BUS_FMT_FIXED;
v4l2_subdev_call(cx->sd_av, pad, set_fmt, NULL, &format);
return 0;
}
static int cx18_s_audio_sampling_freq(struct cx2341x_handler *cxhdl, u32 idx)
{
static const u32 freqs[3] = { 44100, 48000, 32000 };
struct cx18 *cx = container_of(cxhdl, struct cx18, cxhdl);
/* The audio clock of the digitizer must match the codec sample
rate otherwise you get some very strange effects. */
if (idx < ARRAY_SIZE(freqs))
cx18_call_all(cx, audio, s_clock_freq, freqs[idx]);
return 0;
}
static int cx18_s_audio_mode(struct cx2341x_handler *cxhdl, u32 val)
{
struct cx18 *cx = container_of(cxhdl, struct cx18, cxhdl);
cx->dualwatch_stereo_mode = val;
return 0;
}
const struct cx2341x_handler_ops cx18_cxhdl_ops = {
.s_audio_mode = cx18_s_audio_mode,
.s_audio_sampling_freq = cx18_s_audio_sampling_freq,
.s_video_encoding = cx18_s_video_encoding,
.s_stream_vbi_fmt = cx18_s_stream_vbi_fmt,
};
| linux-master | drivers/media/pci/cx18/cx18-controls.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 gpio functions
*
* Derived from ivtv-gpio.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-cards.h"
#include "cx18-gpio.h"
#include "xc2028.h"
/********************* GPIO stuffs *********************/
/* GPIO registers */
#define CX18_REG_GPIO_IN 0xc72010
#define CX18_REG_GPIO_OUT1 0xc78100
#define CX18_REG_GPIO_DIR1 0xc78108
#define CX18_REG_GPIO_OUT2 0xc78104
#define CX18_REG_GPIO_DIR2 0xc7810c
/*
* HVR-1600 GPIO pins, courtesy of Hauppauge:
*
* gpio0: zilog ir process reset pin
* gpio1: zilog programming pin (you should never use this)
* gpio12: cx24227 reset pin
* gpio13: cs5345 reset pin
*/
/*
* File scope utility functions
*/
static void gpio_write(struct cx18 *cx)
{
u32 dir_lo = cx->gpio_dir & 0xffff;
u32 val_lo = cx->gpio_val & 0xffff;
u32 dir_hi = cx->gpio_dir >> 16;
u32 val_hi = cx->gpio_val >> 16;
cx18_write_reg_expect(cx, dir_lo << 16,
CX18_REG_GPIO_DIR1, ~dir_lo, dir_lo);
cx18_write_reg_expect(cx, (dir_lo << 16) | val_lo,
CX18_REG_GPIO_OUT1, val_lo, dir_lo);
cx18_write_reg_expect(cx, dir_hi << 16,
CX18_REG_GPIO_DIR2, ~dir_hi, dir_hi);
cx18_write_reg_expect(cx, (dir_hi << 16) | val_hi,
CX18_REG_GPIO_OUT2, val_hi, dir_hi);
}
static void gpio_update(struct cx18 *cx, u32 mask, u32 data)
{
if (mask == 0)
return;
mutex_lock(&cx->gpio_lock);
cx->gpio_val = (cx->gpio_val & ~mask) | (data & mask);
gpio_write(cx);
mutex_unlock(&cx->gpio_lock);
}
static void gpio_reset_seq(struct cx18 *cx, u32 active_lo, u32 active_hi,
unsigned int assert_msecs,
unsigned int recovery_msecs)
{
u32 mask;
mask = active_lo | active_hi;
if (mask == 0)
return;
/*
* Assuming that active_hi and active_lo are a subsets of the bits in
* gpio_dir. Also assumes that active_lo and active_hi don't overlap
* in any bit position
*/
/* Assert */
gpio_update(cx, mask, ~active_lo);
schedule_timeout_uninterruptible(msecs_to_jiffies(assert_msecs));
/* Deassert */
gpio_update(cx, mask, ~active_hi);
schedule_timeout_uninterruptible(msecs_to_jiffies(recovery_msecs));
}
/*
* GPIO Multiplexer - logical device
*/
static int gpiomux_log_status(struct v4l2_subdev *sd)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
mutex_lock(&cx->gpio_lock);
CX18_INFO_DEV(sd, "GPIO: direction 0x%08x, value 0x%08x\n",
cx->gpio_dir, cx->gpio_val);
mutex_unlock(&cx->gpio_lock);
return 0;
}
static int gpiomux_s_radio(struct v4l2_subdev *sd)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
/*
* FIXME - work out the cx->active/audio_input mess - this is
* intended to handle the switch to radio mode and set the
* audio routing, but we need to update the state in cx
*/
gpio_update(cx, cx->card->gpio_audio_input.mask,
cx->card->gpio_audio_input.radio);
return 0;
}
static int gpiomux_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
u32 data;
switch (cx->card->audio_inputs[cx->audio_input].muxer_input) {
case 1:
data = cx->card->gpio_audio_input.linein;
break;
case 0:
data = cx->card->gpio_audio_input.tuner;
break;
default:
/*
* FIXME - work out the cx->active/audio_input mess - this is
* intended to handle the switch from radio mode and set the
* audio routing, but we need to update the state in cx
*/
data = cx->card->gpio_audio_input.tuner;
break;
}
gpio_update(cx, cx->card->gpio_audio_input.mask, data);
return 0;
}
static int gpiomux_s_audio_routing(struct v4l2_subdev *sd,
u32 input, u32 output, u32 config)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
u32 data;
switch (input) {
case 0:
data = cx->card->gpio_audio_input.tuner;
break;
case 1:
data = cx->card->gpio_audio_input.linein;
break;
case 2:
data = cx->card->gpio_audio_input.radio;
break;
default:
return -EINVAL;
}
gpio_update(cx, cx->card->gpio_audio_input.mask, data);
return 0;
}
static const struct v4l2_subdev_core_ops gpiomux_core_ops = {
.log_status = gpiomux_log_status,
};
static const struct v4l2_subdev_tuner_ops gpiomux_tuner_ops = {
.s_radio = gpiomux_s_radio,
};
static const struct v4l2_subdev_audio_ops gpiomux_audio_ops = {
.s_routing = gpiomux_s_audio_routing,
};
static const struct v4l2_subdev_video_ops gpiomux_video_ops = {
.s_std = gpiomux_s_std,
};
static const struct v4l2_subdev_ops gpiomux_ops = {
.core = &gpiomux_core_ops,
.tuner = &gpiomux_tuner_ops,
.audio = &gpiomux_audio_ops,
.video = &gpiomux_video_ops,
};
/*
* GPIO Reset Controller - logical device
*/
static int resetctrl_log_status(struct v4l2_subdev *sd)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
mutex_lock(&cx->gpio_lock);
CX18_INFO_DEV(sd, "GPIO: direction 0x%08x, value 0x%08x\n",
cx->gpio_dir, cx->gpio_val);
mutex_unlock(&cx->gpio_lock);
return 0;
}
static int resetctrl_reset(struct v4l2_subdev *sd, u32 val)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
const struct cx18_gpio_i2c_slave_reset *p;
p = &cx->card->gpio_i2c_slave_reset;
switch (val) {
case CX18_GPIO_RESET_I2C:
gpio_reset_seq(cx, p->active_lo_mask, p->active_hi_mask,
p->msecs_asserted, p->msecs_recovery);
break;
case CX18_GPIO_RESET_Z8F0811:
/*
* Assert timing for the Z8F0811 on HVR-1600 boards:
* 1. Assert RESET for min of 4 clock cycles at 18.432 MHz to
* initiate
* 2. Reset then takes 66 WDT cycles at 10 kHz + 16 xtal clock
* cycles (6,601,085 nanoseconds ~= 7 milliseconds)
* 3. DBG pin must be high before chip exits reset for normal
* operation. DBG is open drain and hopefully pulled high
* since we don't normally drive it (GPIO 1?) for the
* HVR-1600
* 4. Z8F0811 won't exit reset until RESET is deasserted
* 5. Zilog comes out of reset, loads reset vector address and
* executes from there. Required recovery delay unknown.
*/
gpio_reset_seq(cx, p->ir_reset_mask, 0,
p->msecs_asserted, p->msecs_recovery);
break;
case CX18_GPIO_RESET_XC2028:
if (cx->card->tuners[0].tuner == TUNER_XC2028)
gpio_reset_seq(cx, (1 << cx->card->xceive_pin), 0,
1, 1);
break;
}
return 0;
}
static const struct v4l2_subdev_core_ops resetctrl_core_ops = {
.log_status = resetctrl_log_status,
.reset = resetctrl_reset,
};
static const struct v4l2_subdev_ops resetctrl_ops = {
.core = &resetctrl_core_ops,
};
/*
* External entry points
*/
void cx18_gpio_init(struct cx18 *cx)
{
mutex_lock(&cx->gpio_lock);
cx->gpio_dir = cx->card->gpio_init.direction;
cx->gpio_val = cx->card->gpio_init.initial_value;
if (cx->card->tuners[0].tuner == TUNER_XC2028) {
cx->gpio_dir |= 1 << cx->card->xceive_pin;
cx->gpio_val |= 1 << cx->card->xceive_pin;
}
if (cx->gpio_dir == 0) {
mutex_unlock(&cx->gpio_lock);
return;
}
CX18_DEBUG_INFO("GPIO initial dir: %08x/%08x out: %08x/%08x\n",
cx18_read_reg(cx, CX18_REG_GPIO_DIR1),
cx18_read_reg(cx, CX18_REG_GPIO_DIR2),
cx18_read_reg(cx, CX18_REG_GPIO_OUT1),
cx18_read_reg(cx, CX18_REG_GPIO_OUT2));
gpio_write(cx);
mutex_unlock(&cx->gpio_lock);
}
int cx18_gpio_register(struct cx18 *cx, u32 hw)
{
struct v4l2_subdev *sd;
const struct v4l2_subdev_ops *ops;
char *str;
switch (hw) {
case CX18_HW_GPIO_MUX:
sd = &cx->sd_gpiomux;
ops = &gpiomux_ops;
str = "gpio-mux";
break;
case CX18_HW_GPIO_RESET_CTRL:
sd = &cx->sd_resetctrl;
ops = &resetctrl_ops;
str = "gpio-reset-ctrl";
break;
default:
return -EINVAL;
}
v4l2_subdev_init(sd, ops);
v4l2_set_subdevdata(sd, cx);
snprintf(sd->name, sizeof(sd->name), "%s %s", cx->v4l2_dev.name, str);
sd->grp_id = hw;
return v4l2_device_register_subdev(&cx->v4l2_dev, sd);
}
void cx18_reset_ir_gpio(void *data)
{
struct cx18 *cx = to_cx18(data);
if (cx->card->gpio_i2c_slave_reset.ir_reset_mask == 0)
return;
CX18_DEBUG_INFO("Resetting IR microcontroller\n");
v4l2_subdev_call(&cx->sd_resetctrl,
core, reset, CX18_GPIO_RESET_Z8F0811);
}
EXPORT_SYMBOL(cx18_reset_ir_gpio);
/* This symbol is exported for use by lirc_pvr150 for the IR-blaster */
/* Xceive tuner reset function */
int cx18_reset_tuner_gpio(void *dev, int component, int cmd, int value)
{
struct i2c_algo_bit_data *algo = dev;
struct cx18_i2c_algo_callback_data *cb_data = algo->data;
struct cx18 *cx = cb_data->cx;
if (cmd != XC2028_TUNER_RESET ||
cx->card->tuners[0].tuner != TUNER_XC2028)
return 0;
CX18_DEBUG_INFO("Resetting XCeive tuner\n");
return v4l2_subdev_call(&cx->sd_resetctrl,
core, reset, CX18_GPIO_RESET_XC2028);
}
| linux-master | drivers/media/pci/cx18/cx18-gpio.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 Vertical Blank Interval support functions
*
* Derived from ivtv-vbi.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-vbi.h"
#include "cx18-ioctl.h"
#include "cx18-queue.h"
/*
* Raster Reference/Protection (RP) bytes, used in Start/End Active
* Video codes emitted from the digitzer in VIP 1.x mode, that flag the start
* of VBI sample or VBI ancillary data regions in the digital ratser line.
*
* Task FieldEven VerticalBlank HorizontalBlank 0 0 0 0
*/
static const u8 raw_vbi_sav_rp[2] = { 0x20, 0x60 }; /* __V_, _FV_ */
static const u8 sliced_vbi_eav_rp[2] = { 0xb0, 0xf0 }; /* T_VH, TFVH */
static void copy_vbi_data(struct cx18 *cx, int lines, u32 pts_stamp)
{
int line = 0;
int i;
u32 linemask[2] = { 0, 0 };
unsigned short size;
static const u8 mpeg_hdr_data[] = {
/* MPEG-2 Program Pack */
0x00, 0x00, 0x01, 0xba, /* Prog Pack start code */
0x44, 0x00, 0x0c, 0x66, 0x24, 0x01, /* SCR, SCR Ext, markers */
0x01, 0xd1, 0xd3, /* Mux Rate, markers */
0xfa, 0xff, 0xff, /* Res, Suff cnt, Stuff */
/* MPEG-2 Private Stream 1 PES Packet */
0x00, 0x00, 0x01, 0xbd, /* Priv Stream 1 start */
0x00, 0x1a, /* length */
0x84, 0x80, 0x07, /* flags, hdr data len */
0x21, 0x00, 0x5d, 0x63, 0xa7, /* PTS, markers */
0xff, 0xff /* stuffing */
};
const int sd = sizeof(mpeg_hdr_data); /* start of vbi data */
int idx = cx->vbi.frame % CX18_VBI_FRAMES;
u8 *dst = &cx->vbi.sliced_mpeg_data[idx][0];
for (i = 0; i < lines; i++) {
struct v4l2_sliced_vbi_data *sdata = cx->vbi.sliced_data + i;
int f, l;
if (sdata->id == 0)
continue;
l = sdata->line - 6;
f = sdata->field;
if (f)
l += 18;
if (l < 32)
linemask[0] |= (1 << l);
else
linemask[1] |= (1 << (l - 32));
dst[sd + 12 + line * 43] = cx18_service2vbi(sdata->id);
memcpy(dst + sd + 12 + line * 43 + 1, sdata->data, 42);
line++;
}
memcpy(dst, mpeg_hdr_data, sizeof(mpeg_hdr_data));
if (line == 36) {
/* All lines are used, so there is no space for the linemask
(the max size of the VBI data is 36 * 43 + 4 bytes).
So in this case we use the magic number 'ITV0'. */
memcpy(dst + sd, "ITV0", 4);
memmove(dst + sd + 4, dst + sd + 12, line * 43);
size = 4 + ((43 * line + 3) & ~3);
} else {
memcpy(dst + sd, "itv0", 4);
cpu_to_le32s(&linemask[0]);
cpu_to_le32s(&linemask[1]);
memcpy(dst + sd + 4, &linemask[0], 8);
size = 12 + ((43 * line + 3) & ~3);
}
dst[4+16] = (size + 10) >> 8;
dst[5+16] = (size + 10) & 0xff;
dst[9+16] = 0x21 | ((pts_stamp >> 29) & 0x6);
dst[10+16] = (pts_stamp >> 22) & 0xff;
dst[11+16] = 1 | ((pts_stamp >> 14) & 0xff);
dst[12+16] = (pts_stamp >> 7) & 0xff;
dst[13+16] = 1 | ((pts_stamp & 0x7f) << 1);
cx->vbi.sliced_mpeg_size[idx] = sd + size;
}
/* Compress raw VBI format, removes leading SAV codes and surplus space
after the frame. Returns new compressed size. */
/* FIXME - this function ignores the input size. */
static u32 compress_raw_buf(struct cx18 *cx, u8 *buf, u32 size, u32 hdr_size)
{
u32 line_size = VBI_ACTIVE_SAMPLES;
u32 lines = cx->vbi.count * 2;
u8 *q = buf;
u8 *p;
int i;
/* Skip the header */
buf += hdr_size;
for (i = 0; i < lines; i++) {
p = buf + i * line_size;
/* Look for SAV code */
if (p[0] != 0xff || p[1] || p[2] ||
(p[3] != raw_vbi_sav_rp[0] &&
p[3] != raw_vbi_sav_rp[1]))
break;
if (i == lines - 1) {
/* last line is hdr_size bytes short - extrapolate it */
memcpy(q, p + 4, line_size - 4 - hdr_size);
q += line_size - 4 - hdr_size;
p += line_size - hdr_size - 1;
memset(q, (int) *p, hdr_size);
} else {
memcpy(q, p + 4, line_size - 4);
q += line_size - 4;
}
}
return lines * (line_size - 4);
}
static u32 compress_sliced_buf(struct cx18 *cx, u8 *buf, u32 size,
const u32 hdr_size)
{
struct v4l2_decode_vbi_line vbi;
int i;
u32 line = 0;
u32 line_size = cx->is_60hz ? VBI_HBLANK_SAMPLES_60HZ
: VBI_HBLANK_SAMPLES_50HZ;
/* find the first valid line */
for (i = hdr_size, buf += hdr_size; i < size; i++, buf++) {
if (buf[0] == 0xff && !buf[1] && !buf[2] &&
(buf[3] == sliced_vbi_eav_rp[0] ||
buf[3] == sliced_vbi_eav_rp[1]))
break;
}
/*
* The last line is short by hdr_size bytes, but for the remaining
* checks against size, we pretend that it is not, by counting the
* header bytes we knowingly skipped
*/
size -= (i - hdr_size);
if (size < line_size)
return line;
for (i = 0; i < size / line_size; i++) {
u8 *p = buf + i * line_size;
/* Look for EAV code */
if (p[0] != 0xff || p[1] || p[2] ||
(p[3] != sliced_vbi_eav_rp[0] &&
p[3] != sliced_vbi_eav_rp[1]))
continue;
vbi.p = p + 4;
v4l2_subdev_call(cx->sd_av, vbi, decode_vbi_line, &vbi);
if (vbi.type) {
cx->vbi.sliced_data[line].id = vbi.type;
cx->vbi.sliced_data[line].field = vbi.is_second_field;
cx->vbi.sliced_data[line].line = vbi.line;
memcpy(cx->vbi.sliced_data[line].data, vbi.p, 42);
line++;
}
}
return line;
}
static void _cx18_process_vbi_data(struct cx18 *cx, struct cx18_buffer *buf)
{
/*
* The CX23418 provides a 12 byte header in its raw VBI buffers to us:
* 0x3fffffff [4 bytes of something] [4 byte presentation time stamp]
*/
struct vbi_data_hdr {
__be32 magic;
__be32 unknown;
__be32 pts;
} *hdr = (struct vbi_data_hdr *) buf->buf;
u8 *p = (u8 *) buf->buf;
u32 size = buf->bytesused;
u32 pts;
int lines;
/*
* The CX23418 sends us data that is 32 bit little-endian swapped,
* but we want the raw VBI bytes in the order they were in the raster
* line. This has a side effect of making the header big endian
*/
cx18_buf_swap(buf);
/* Raw VBI data */
if (cx18_raw_vbi(cx)) {
size = buf->bytesused =
compress_raw_buf(cx, p, size, sizeof(struct vbi_data_hdr));
/*
* Hack needed for compatibility with old VBI software.
* Write the frame # at the last 4 bytes of the frame
*/
p += size - 4;
memcpy(p, &cx->vbi.frame, 4);
cx->vbi.frame++;
return;
}
/* Sliced VBI data with data insertion */
pts = (be32_to_cpu(hdr->magic) == 0x3fffffff) ? be32_to_cpu(hdr->pts)
: 0;
lines = compress_sliced_buf(cx, p, size, sizeof(struct vbi_data_hdr));
/* always return at least one empty line */
if (lines == 0) {
cx->vbi.sliced_data[0].id = 0;
cx->vbi.sliced_data[0].line = 0;
cx->vbi.sliced_data[0].field = 0;
lines = 1;
}
buf->bytesused = size = lines * sizeof(cx->vbi.sliced_data[0]);
memcpy(p, &cx->vbi.sliced_data[0], size);
if (cx->vbi.insert_mpeg)
copy_vbi_data(cx, lines, pts);
cx->vbi.frame++;
}
void cx18_process_vbi_data(struct cx18 *cx, struct cx18_mdl *mdl,
int streamtype)
{
struct cx18_buffer *buf;
u32 orig_used;
if (streamtype != CX18_ENC_STREAM_TYPE_VBI)
return;
/*
* Big assumption here:
* Every buffer hooked to the MDL's buf_list is a complete VBI frame
* that ends at the end of the buffer.
*
* To assume anything else would make the code in this file
* more complex, or require extra memcpy()'s to make the
* buffers satisfy the above assumption. It's just simpler to set
* up the encoder buffer transfers to make the assumption true.
*/
list_for_each_entry(buf, &mdl->buf_list, list) {
orig_used = buf->bytesused;
if (orig_used == 0)
break;
_cx18_process_vbi_data(cx, buf);
mdl->bytesused -= (orig_used - buf->bytesused);
}
}
| linux-master | drivers/media/pci/cx18/cx18-vbi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ALSA interface to cx18 PCM capture streams
*
* Copyright (C) 2009 Andy Walls <[email protected]>
* Copyright (C) 2009 Devin Heitmueller <[email protected]>
*
* Portions of this work were sponsored by ONELAN Limited.
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/spinlock.h>
#include <media/v4l2-device.h>
#include <sound/core.h>
#include <sound/initval.h>
#include "cx18-driver.h"
#include "cx18-version.h"
#include "cx18-alsa.h"
#include "cx18-alsa-pcm.h"
int cx18_alsa_debug;
#define CX18_DEBUG_ALSA_INFO(fmt, arg...) \
do { \
if (cx18_alsa_debug & 2) \
printk(KERN_INFO "%s: " fmt, "cx18-alsa", ## arg); \
} while (0);
module_param_named(debug, cx18_alsa_debug, int, 0644);
MODULE_PARM_DESC(debug,
"Debug level (bitmask). Default: 0\n"
"\t\t\t 1/0x0001: warning\n"
"\t\t\t 2/0x0002: info\n");
MODULE_AUTHOR("Andy Walls");
MODULE_DESCRIPTION("CX23418 ALSA Interface");
MODULE_LICENSE("GPL");
MODULE_VERSION(CX18_VERSION);
static inline
struct snd_cx18_card *to_snd_cx18_card(struct v4l2_device *v4l2_dev)
{
return to_cx18(v4l2_dev)->alsa;
}
static void snd_cx18_card_free(struct snd_cx18_card *cxsc)
{
if (cxsc == NULL)
return;
if (cxsc->v4l2_dev != NULL)
to_cx18(cxsc->v4l2_dev)->alsa = NULL;
/* FIXME - take any other stopping actions needed */
kfree(cxsc);
}
static void snd_cx18_card_private_free(struct snd_card *sc)
{
if (sc == NULL)
return;
snd_cx18_card_free(sc->private_data);
sc->private_data = NULL;
sc->private_free = NULL;
}
static int snd_cx18_card_create(struct v4l2_device *v4l2_dev,
struct snd_card *sc,
struct snd_cx18_card **cxsc)
{
*cxsc = kzalloc(sizeof(struct snd_cx18_card), GFP_KERNEL);
if (*cxsc == NULL)
return -ENOMEM;
(*cxsc)->v4l2_dev = v4l2_dev;
(*cxsc)->sc = sc;
sc->private_data = *cxsc;
sc->private_free = snd_cx18_card_private_free;
return 0;
}
static int snd_cx18_card_set_names(struct snd_cx18_card *cxsc)
{
struct cx18 *cx = to_cx18(cxsc->v4l2_dev);
struct snd_card *sc = cxsc->sc;
/* sc->driver is used by alsa-lib's configurator: simple, unique */
strscpy(sc->driver, "CX23418", sizeof(sc->driver));
/* sc->shortname is a symlink in /proc/asound: CX18-M -> cardN */
snprintf(sc->shortname, sizeof(sc->shortname), "CX18-%d",
cx->instance);
/* sc->longname is read from /proc/asound/cards */
snprintf(sc->longname, sizeof(sc->longname),
"CX23418 #%d %s TV/FM Radio/Line-In Capture",
cx->instance, cx->card_name);
return 0;
}
static int snd_cx18_init(struct v4l2_device *v4l2_dev)
{
struct cx18 *cx = to_cx18(v4l2_dev);
struct snd_card *sc = NULL;
struct snd_cx18_card *cxsc;
int ret;
/* Numbrs steps from "Writing an ALSA Driver" by Takashi Iwai */
/* (1) Check and increment the device index */
/* This is a no-op for us. We'll use the cx->instance */
/* (2) Create a card instance */
ret = snd_card_new(&cx->pci_dev->dev,
SNDRV_DEFAULT_IDX1, /* use first available id */
SNDRV_DEFAULT_STR1, /* xid from end of shortname*/
THIS_MODULE, 0, &sc);
if (ret) {
CX18_ALSA_ERR("%s: snd_card_new() failed with err %d\n",
__func__, ret);
goto err_exit;
}
/* (3) Create a main component */
ret = snd_cx18_card_create(v4l2_dev, sc, &cxsc);
if (ret) {
CX18_ALSA_ERR("%s: snd_cx18_card_create() failed with err %d\n",
__func__, ret);
goto err_exit_free;
}
/* (4) Set the driver ID and name strings */
snd_cx18_card_set_names(cxsc);
ret = snd_cx18_pcm_create(cxsc);
if (ret) {
CX18_ALSA_ERR("%s: snd_cx18_pcm_create() failed with err %d\n",
__func__, ret);
goto err_exit_free;
}
/* FIXME - proc files */
/* (7) Set the driver data and return 0 */
/* We do this out of normal order for PCI drivers to avoid races */
cx->alsa = cxsc;
/* (6) Register the card instance */
ret = snd_card_register(sc);
if (ret) {
cx->alsa = NULL;
CX18_ALSA_ERR("%s: snd_card_register() failed with err %d\n",
__func__, ret);
goto err_exit_free;
}
return 0;
err_exit_free:
if (sc != NULL)
snd_card_free(sc);
kfree(cxsc);
err_exit:
return ret;
}
static int cx18_alsa_load(struct cx18 *cx)
{
struct v4l2_device *v4l2_dev = &cx->v4l2_dev;
struct cx18_stream *s;
if (v4l2_dev == NULL) {
printk(KERN_ERR "cx18-alsa: %s: struct v4l2_device * is NULL\n",
__func__);
return 0;
}
cx = to_cx18(v4l2_dev);
if (cx == NULL) {
printk(KERN_ERR "cx18-alsa cx is NULL\n");
return 0;
}
s = &cx->streams[CX18_ENC_STREAM_TYPE_PCM];
if (s->video_dev.v4l2_dev == NULL) {
CX18_DEBUG_ALSA_INFO("%s: PCM stream for card is disabled - skipping\n",
__func__);
return 0;
}
if (cx->alsa != NULL) {
CX18_ALSA_ERR("%s: struct snd_cx18_card * already exists\n",
__func__);
return 0;
}
if (snd_cx18_init(v4l2_dev)) {
CX18_ALSA_ERR("%s: failed to create struct snd_cx18_card\n",
__func__);
} else {
CX18_DEBUG_ALSA_INFO("%s: created cx18 ALSA interface instance\n",
__func__);
}
return 0;
}
static int __init cx18_alsa_init(void)
{
printk(KERN_INFO "cx18-alsa: module loading...\n");
cx18_ext_init = &cx18_alsa_load;
return 0;
}
static void __exit snd_cx18_exit(struct snd_cx18_card *cxsc)
{
struct cx18 *cx = to_cx18(cxsc->v4l2_dev);
/* FIXME - pointer checks & shutdown cxsc */
snd_card_free(cxsc->sc);
cx->alsa = NULL;
}
static int __exit cx18_alsa_exit_callback(struct device *dev, void *data)
{
struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
struct snd_cx18_card *cxsc;
if (v4l2_dev == NULL) {
printk(KERN_ERR "cx18-alsa: %s: struct v4l2_device * is NULL\n",
__func__);
return 0;
}
cxsc = to_snd_cx18_card(v4l2_dev);
if (cxsc == NULL) {
CX18_ALSA_WARN("%s: struct snd_cx18_card * is NULL\n",
__func__);
return 0;
}
snd_cx18_exit(cxsc);
return 0;
}
static void __exit cx18_alsa_exit(void)
{
struct device_driver *drv;
int ret;
printk(KERN_INFO "cx18-alsa: module unloading...\n");
drv = driver_find("cx18", &pci_bus_type);
ret = driver_for_each_device(drv, NULL, NULL, cx18_alsa_exit_callback);
(void)ret; /* suppress compiler warning */
cx18_ext_init = NULL;
printk(KERN_INFO "cx18-alsa: module unload complete\n");
}
module_init(cx18_alsa_init);
module_exit(cx18_alsa_exit);
| linux-master | drivers/media/pci/cx18/cx18-alsa-main.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 ADEC audio functions
*
* Derived from cx25840-core.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-cards.h"
int cx18_av_write(struct cx18 *cx, u16 addr, u8 value)
{
u32 reg = 0xc40000 + (addr & ~3);
u32 mask = 0xff;
int shift = (addr & 3) * 8;
u32 x = cx18_read_reg(cx, reg);
x = (x & ~(mask << shift)) | ((u32)value << shift);
cx18_write_reg(cx, x, reg);
return 0;
}
int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask)
{
u32 reg = 0xc40000 + (addr & ~3);
int shift = (addr & 3) * 8;
u32 x = cx18_read_reg(cx, reg);
x = (x & ~((u32)0xff << shift)) | ((u32)value << shift);
cx18_write_reg_expect(cx, x, reg,
((u32)eval << shift), ((u32)mask << shift));
return 0;
}
int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
{
cx18_write_reg(cx, value, 0xc40000 + addr);
return 0;
}
int
cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask)
{
cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask);
return 0;
}
int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
{
cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
return 0;
}
u8 cx18_av_read(struct cx18 *cx, u16 addr)
{
u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
int shift = (addr & 3) * 8;
return (x >> shift) & 0xff;
}
u32 cx18_av_read4(struct cx18 *cx, u16 addr)
{
return cx18_read_reg(cx, 0xc40000 + addr);
}
int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
u8 or_value)
{
return cx18_av_write(cx, addr,
(cx18_av_read(cx, addr) & and_mask) |
or_value);
}
int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask,
u32 or_value)
{
return cx18_av_write4(cx, addr,
(cx18_av_read4(cx, addr) & and_mask) |
or_value);
}
static void cx18_av_init(struct cx18 *cx)
{
/*
* The crystal freq used in calculations in this driver will be
* 28.636360 MHz.
* Aim to run the PLLs' VCOs near 400 MHz to minimize errors.
*/
/*
* VDCLK Integer = 0x0f, Post Divider = 0x04
* AIMCLK Integer = 0x0e, Post Divider = 0x16
*/
cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f);
/* VDCLK Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */
cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe);
/* AIMCLK Fraction = 0x05227ad */
/* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/
cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56);
}
static void cx18_av_initialize(struct v4l2_subdev *sd)
{
struct cx18_av_state *state = to_cx18_av_state(sd);
struct cx18 *cx = v4l2_get_subdevdata(sd);
int default_volume;
u32 v;
cx18_av_loadfw(cx);
/* Stop 8051 code execution */
cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
0x03000000, 0x13000000);
/* initialize the PLL by toggling sleep bit */
v = cx18_av_read4(cx, CXADEC_HOST_REG1);
/* enable sleep mode - register appears to be read only... */
cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);
/* disable sleep mode */
cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe,
v & 0xfffe, 0xffff);
/* initialize DLLs */
v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF;
/* disable FLD */
cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v);
/* enable FLD */
cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100);
v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF;
/* disable FLD */
cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v);
/* enable FLD */
cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100);
/* set analog bias currents. Set Vreg to 1.20V. */
cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802);
v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1;
/* enable TUNE_FIL_RST */
cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F);
/* disable TUNE_FIL_RST */
cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3,
v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F);
/* enable 656 output */
cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00);
/* video output drive strength */
cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2);
/* reset video */
cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000);
cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0);
/*
* Disable Video Auto-config of the Analog Front End and Video PLL.
*
* Since we only use BT.656 pixel mode, which works for both 525 and 625
* line systems, it's just easier for us to set registers
* 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL),
* 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC)
* ourselves, than to run around cleaning up after the auto-config.
*
* (Note: my CX23418 chip doesn't seem to let the ACFG_DIS bit
* get set to 1, but OTOH, it doesn't seem to do AFE and VID PLL
* autoconfig either.)
*
* As a default, also turn off Dual mode for ADC2 and set ADC2 to CH3.
*/
cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000);
/* Setup the Video and Aux/Audio PLLs */
cx18_av_init(cx);
/* set video to auto-detect */
/* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */
/* set the comb notch = 1 */
cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800);
/* Enable wtw_en in CRUSH_CTRL (Set bit 22) */
/* Enable maj_sel in CRUSH_CTRL (Set bit 20) */
cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000);
/* Set VGA_TRACK_RANGE to 0x20 */
cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000);
/*
* Initial VBI setup
* VIP-1.1, 10 bit mode, enable Raw, disable sliced,
* don't clamp raw samples when codes are in use, 1 byte user D-words,
* IDID0 has line #, RP code V bit transition on VBLANK, data during
* blanking intervals
*/
cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e);
/* Set the video input.
The setting in MODE_CTRL gets lost when we do the above setup */
/* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */
/* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */
/*
* Analog Front End (AFE)
* Default to luma on ch1/ADC1, chroma on ch2/ADC2, SIF on ch3/ADC2
* bypass_ch[1-3] use filter
* droop_comp_ch[1-3] disable
* clamp_en_ch[1-3] disable
* aud_in_sel ADC2
* luma_in_sel ADC1
* chroma_in_sel ADC2
* clamp_sel_ch[2-3] midcode
* clamp_sel_ch1 video decoder
* vga_sel_ch3 audio decoder
* vga_sel_ch[1-2] video decoder
* half_bw_ch[1-3] disable
* +12db_ch[1-3] disable
*/
cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00);
/* if(dwEnable && dw3DCombAvailable) { */
/* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
/* } else { */
/* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */
/* } */
cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F);
default_volume = cx18_av_read(cx, 0x8d4);
/*
* Enforce the legacy volume scale mapping limits to avoid
* -ERANGE errors when initializing the volume control
*/
if (default_volume > 228) {
/* Bottom out at -96 dB, v4l2 vol range 0x2e00-0x2fff */
default_volume = 228;
cx18_av_write(cx, 0x8d4, 228);
} else if (default_volume < 20) {
/* Top out at + 8 dB, v4l2 vol range 0xfe00-0xffff */
default_volume = 20;
cx18_av_write(cx, 0x8d4, 20);
}
default_volume = (((228 - default_volume) >> 1) + 23) << 9;
state->volume->cur.val = state->volume->default_value = default_volume;
v4l2_ctrl_handler_setup(&state->hdl);
}
static int cx18_av_reset(struct v4l2_subdev *sd, u32 val)
{
cx18_av_initialize(sd);
return 0;
}
static int cx18_av_load_fw(struct v4l2_subdev *sd)
{
struct cx18_av_state *state = to_cx18_av_state(sd);
if (!state->is_initialized) {
/* initialize on first use */
state->is_initialized = 1;
cx18_av_initialize(sd);
}
return 0;
}
void cx18_av_std_setup(struct cx18 *cx)
{
struct cx18_av_state *state = &cx->av_state;
struct v4l2_subdev *sd = &state->sd;
v4l2_std_id std = state->std;
/*
* Video ADC crystal clock to pixel clock SRC decimation ratio
* 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b
*/
const int src_decimation = 0x21f;
int hblank, hactive, burst, vblank, vactive, sc;
int vblank656;
int luma_lpf, uv_lpf, comb;
u32 pll_int, pll_frac, pll_post;
/* datasheet startup, step 8d */
if (std & ~V4L2_STD_NTSC)
cx18_av_write(cx, 0x49f, 0x11);
else
cx18_av_write(cx, 0x49f, 0x14);
/*
* Note: At the end of a field, there are 3 sets of half line duration
* (double horizontal rate) pulses:
*
* 5 (625) or 6 (525) half-lines to blank for the vertical retrace
* 5 (625) or 6 (525) vertical sync pulses of half line duration
* 5 (625) or 6 (525) half-lines of equalization pulses
*/
if (std & V4L2_STD_625_50) {
/*
* The following relationships of half line counts should hold:
* 625 = vblank656 + vactive
* 10 = vblank656 - vblank = vsync pulses + equalization pulses
*
* vblank656: half lines after line 625/mid-313 of blanked video
* vblank: half lines, after line 5/317, of blanked video
* vactive: half lines of active video +
* 5 half lines after the end of active video
*
* As far as I can tell:
* vblank656 starts counting from the falling edge of the first
* vsync pulse (start of line 1 or mid-313)
* vblank starts counting from the after the 5 vsync pulses and
* 5 or 4 equalization pulses (start of line 6 or 318)
*
* For 625 line systems the driver will extract VBI information
* from lines 6-23 and lines 318-335 (but the slicer can only
* handle 17 lines, not the 18 in the vblank region).
* In addition, we need vblank656 and vblank to be one whole
* line longer, to cover line 24 and 336, so the SAV/EAV RP
* codes get generated such that the encoder can actually
* extract line 23 & 335 (WSS). We'll lose 1 line in each field
* at the top of the screen.
*
* It appears the 5 half lines that happen after active
* video must be included in vactive (579 instead of 574),
* otherwise the colors get badly displayed in various regions
* of the screen. I guess the chroma comb filter gets confused
* without them (at least when a PVR-350 is the PAL source).
*/
vblank656 = 48; /* lines 1 - 24 & 313 - 336 */
vblank = 38; /* lines 6 - 24 & 318 - 336 */
vactive = 579; /* lines 24 - 313 & 337 - 626 */
/*
* For a 13.5 Mpps clock and 15,625 Hz line rate, a line is
* 864 pixels = 720 active + 144 blanking. ITU-R BT.601
* specifies 12 luma clock periods or ~ 0.9 * 13.5 Mpps after
* the end of active video to start a horizontal line, so that
* leaves 132 pixels of hblank to ignore.
*/
hblank = 132;
hactive = 720;
/*
* Burst gate delay (for 625 line systems)
* Hsync leading edge to color burst rise = 5.6 us
* Color burst width = 2.25 us
* Gate width = 4 pixel clocks
* (5.6 us + 2.25/2 us) * 13.5 Mpps + 4/2 clocks = 92.79 clocks
*/
burst = 93;
luma_lpf = 2;
if (std & V4L2_STD_PAL) {
uv_lpf = 1;
comb = 0x20;
/* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
sc = 688700;
} else if (std == V4L2_STD_PAL_Nc) {
uv_lpf = 1;
comb = 0x20;
/* sc = 3582056.25 * src_decimation/28636360 * 2^13 */
sc = 556422;
} else { /* SECAM */
uv_lpf = 0;
comb = 0;
/* (fr + fb)/2 = (4406260 + 4250000)/2 = 4328130 */
/* sc = 4328130 * src_decimation/28636360 * 2^13 */
sc = 672314;
}
} else {
/*
* The following relationships of half line counts should hold:
* 525 = prevsync + vblank656 + vactive
* 12 = vblank656 - vblank = vsync pulses + equalization pulses
*
* prevsync: 6 half-lines before the vsync pulses
* vblank656: half lines, after line 3/mid-266, of blanked video
* vblank: half lines, after line 9/272, of blanked video
* vactive: half lines of active video
*
* As far as I can tell:
* vblank656 starts counting from the falling edge of the first
* vsync pulse (start of line 4 or mid-266)
* vblank starts counting from the after the 6 vsync pulses and
* 6 or 5 equalization pulses (start of line 10 or 272)
*
* For 525 line systems the driver will extract VBI information
* from lines 10-21 and lines 273-284.
*/
vblank656 = 38; /* lines 4 - 22 & 266 - 284 */
vblank = 26; /* lines 10 - 22 & 272 - 284 */
vactive = 481; /* lines 23 - 263 & 285 - 525 */
/*
* For a 13.5 Mpps clock and 15,734.26 Hz line rate, a line is
* 858 pixels = 720 active + 138 blanking. The Hsync leading
* edge should happen 1.2 us * 13.5 Mpps ~= 16 pixels after the
* end of active video, leaving 122 pixels of hblank to ignore
* before active video starts.
*/
hactive = 720;
hblank = 122;
luma_lpf = 1;
uv_lpf = 1;
/*
* Burst gate delay (for 525 line systems)
* Hsync leading edge to color burst rise = 5.3 us
* Color burst width = 2.5 us
* Gate width = 4 pixel clocks
* (5.3 us + 2.5/2 us) * 13.5 Mpps + 4/2 clocks = 90.425 clocks
*/
if (std == V4L2_STD_PAL_60) {
burst = 90;
luma_lpf = 2;
comb = 0x20;
/* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
sc = 688700;
} else if (std == V4L2_STD_PAL_M) {
/* The 97 needs to be verified against PAL-M timings */
burst = 97;
comb = 0x20;
/* sc = 3575611.49 * src_decimation/28636360 * 2^13 */
sc = 555421;
} else {
burst = 90;
comb = 0x66;
/* sc = 3579545.45.. * src_decimation/28636360 * 2^13 */
sc = 556032;
}
}
/* DEBUG: Displays configured PLL frequency */
pll_int = cx18_av_read(cx, 0x108);
pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff;
pll_post = cx18_av_read(cx, 0x109);
CX18_DEBUG_INFO_DEV(sd, "PLL regs = int: %u, frac: %u, post: %u\n",
pll_int, pll_frac, pll_post);
if (pll_post) {
int fsc, pll;
u64 tmp;
pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
pll /= pll_post;
CX18_DEBUG_INFO_DEV(sd, "Video PLL = %d.%06d MHz\n",
pll / 1000000, pll % 1000000);
CX18_DEBUG_INFO_DEV(sd, "Pixel rate = %d.%06d Mpixel/sec\n",
pll / 8000000, (pll / 8) % 1000000);
CX18_DEBUG_INFO_DEV(sd, "ADC XTAL/pixel clock decimation ratio = %d.%03d\n",
src_decimation / 256,
((src_decimation % 256) * 1000) / 256);
tmp = 28636360 * (u64) sc;
do_div(tmp, src_decimation);
fsc = tmp >> 13;
CX18_DEBUG_INFO_DEV(sd,
"Chroma sub-carrier initial freq = %d.%06d MHz\n",
fsc / 1000000, fsc % 1000000);
CX18_DEBUG_INFO_DEV(sd,
"hblank %i, hactive %i, vblank %i, vactive %i, vblank656 %i, src_dec %i, burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, sc 0x%06x\n",
hblank, hactive, vblank, vactive, vblank656,
src_decimation, burst, luma_lpf, uv_lpf,
comb, sc);
}
/* Sets horizontal blanking delay and active lines */
cx18_av_write(cx, 0x470, hblank);
cx18_av_write(cx, 0x471,
(((hblank >> 8) & 0x3) | (hactive << 4)) & 0xff);
cx18_av_write(cx, 0x472, hactive >> 4);
/* Sets burst gate delay */
cx18_av_write(cx, 0x473, burst);
/* Sets vertical blanking delay and active duration */
cx18_av_write(cx, 0x474, vblank);
cx18_av_write(cx, 0x475,
(((vblank >> 8) & 0x3) | (vactive << 4)) & 0xff);
cx18_av_write(cx, 0x476, vactive >> 4);
cx18_av_write(cx, 0x477, vblank656);
/* Sets src decimation rate */
cx18_av_write(cx, 0x478, src_decimation & 0xff);
cx18_av_write(cx, 0x479, (src_decimation >> 8) & 0xff);
/* Sets Luma and UV Low pass filters */
cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
/* Enables comb filters */
cx18_av_write(cx, 0x47b, comb);
/* Sets SC Step*/
cx18_av_write(cx, 0x47c, sc);
cx18_av_write(cx, 0x47d, (sc >> 8) & 0xff);
cx18_av_write(cx, 0x47e, (sc >> 16) & 0xff);
if (std & V4L2_STD_625_50) {
state->slicer_line_delay = 1;
state->slicer_line_offset = (6 + state->slicer_line_delay - 2);
} else {
state->slicer_line_delay = 0;
state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
}
cx18_av_write(cx, 0x47f, state->slicer_line_delay);
}
static void input_change(struct cx18 *cx)
{
struct cx18_av_state *state = &cx->av_state;
v4l2_std_id std = state->std;
u8 v;
/* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */
cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
cx18_av_and_or(cx, 0x401, ~0x60, 0);
cx18_av_and_or(cx, 0x401, ~0x60, 0x60);
if (std & V4L2_STD_525_60) {
if (std == V4L2_STD_NTSC_M_JP) {
/* Japan uses EIAJ audio standard */
cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff);
cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f);
} else if (std == V4L2_STD_NTSC_M_KR) {
/* South Korea uses A2 audio standard */
cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff);
cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
} else {
/* Others use the BTSC audio standard */
cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff);
cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f);
}
} else if (std & V4L2_STD_PAL) {
/* Follow tuner change procedure for PAL */
cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
} else if (std & V4L2_STD_SECAM) {
/* Select autodetect for SECAM */
cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
}
v = cx18_av_read(cx, 0x803);
if (v & 0x10) {
/* restart audio decoder microcontroller */
v &= ~0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
v |= 0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
}
}
static int cx18_av_s_frequency(struct v4l2_subdev *sd,
const struct v4l2_frequency *freq)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
input_change(cx);
return 0;
}
static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
enum cx18_av_audio_input aud_input)
{
struct cx18_av_state *state = &cx->av_state;
struct v4l2_subdev *sd = &state->sd;
enum analog_signal_type {
NONE, CVBS, Y, C, SIF, Pb, Pr
} ch[3] = {NONE, NONE, NONE};
u8 afe_mux_cfg;
u8 adc2_cfg;
u8 input_mode;
u32 afe_cfg;
int i;
CX18_DEBUG_INFO_DEV(sd, "decoder set video input %d, audio input %d\n",
vid_input, aud_input);
if (vid_input >= CX18_AV_COMPOSITE1 &&
vid_input <= CX18_AV_COMPOSITE8) {
afe_mux_cfg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1);
ch[0] = CVBS;
input_mode = 0x0;
} else if (vid_input >= CX18_AV_COMPONENT_LUMA1) {
int luma = vid_input & 0xf000;
int r_chroma = vid_input & 0xf0000;
int b_chroma = vid_input & 0xf00000;
if ((vid_input & ~0xfff000) ||
luma < CX18_AV_COMPONENT_LUMA1 ||
luma > CX18_AV_COMPONENT_LUMA8 ||
r_chroma < CX18_AV_COMPONENT_R_CHROMA4 ||
r_chroma > CX18_AV_COMPONENT_R_CHROMA6 ||
b_chroma < CX18_AV_COMPONENT_B_CHROMA7 ||
b_chroma > CX18_AV_COMPONENT_B_CHROMA8) {
CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n",
vid_input);
return -EINVAL;
}
afe_mux_cfg = (luma - CX18_AV_COMPONENT_LUMA1) >> 12;
ch[0] = Y;
afe_mux_cfg |= (r_chroma - CX18_AV_COMPONENT_R_CHROMA4) >> 12;
ch[1] = Pr;
afe_mux_cfg |= (b_chroma - CX18_AV_COMPONENT_B_CHROMA7) >> 14;
ch[2] = Pb;
input_mode = 0x6;
} else {
int luma = vid_input & 0xf0;
int chroma = vid_input & 0xf00;
if ((vid_input & ~0xff0) ||
luma < CX18_AV_SVIDEO_LUMA1 ||
luma > CX18_AV_SVIDEO_LUMA8 ||
chroma < CX18_AV_SVIDEO_CHROMA4 ||
chroma > CX18_AV_SVIDEO_CHROMA8) {
CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n",
vid_input);
return -EINVAL;
}
afe_mux_cfg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4);
ch[0] = Y;
if (chroma >= CX18_AV_SVIDEO_CHROMA7) {
afe_mux_cfg &= 0x3f;
afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2;
ch[2] = C;
} else {
afe_mux_cfg &= 0xcf;
afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4;
ch[1] = C;
}
input_mode = 0x2;
}
switch (aud_input) {
case CX18_AV_AUDIO_SERIAL1:
case CX18_AV_AUDIO_SERIAL2:
/* do nothing, use serial audio input */
break;
case CX18_AV_AUDIO4:
afe_mux_cfg &= ~0x30;
ch[1] = SIF;
break;
case CX18_AV_AUDIO5:
afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x10;
ch[1] = SIF;
break;
case CX18_AV_AUDIO6:
afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x20;
ch[1] = SIF;
break;
case CX18_AV_AUDIO7:
afe_mux_cfg &= ~0xc0;
ch[2] = SIF;
break;
case CX18_AV_AUDIO8:
afe_mux_cfg = (afe_mux_cfg & ~0xc0) | 0x40;
ch[2] = SIF;
break;
default:
CX18_ERR_DEV(sd, "0x%04x is not a valid audio input!\n",
aud_input);
return -EINVAL;
}
/* Set up analog front end multiplexers */
cx18_av_write_expect(cx, 0x103, afe_mux_cfg, afe_mux_cfg, 0xf7);
/* Set INPUT_MODE to Composite, S-Video, or Component */
cx18_av_and_or(cx, 0x401, ~0x6, input_mode);
/* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
adc2_cfg = cx18_av_read(cx, 0x102);
if (ch[2] == NONE)
adc2_cfg &= ~0x2; /* No sig on CH3, set ADC2 to CH2 for input */
else
adc2_cfg |= 0x2; /* Signal on CH3, set ADC2 to CH3 for input */
/* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */
if (ch[1] != NONE && ch[2] != NONE)
adc2_cfg |= 0x4; /* Set dual mode */
else
adc2_cfg &= ~0x4; /* Clear dual mode */
cx18_av_write_expect(cx, 0x102, adc2_cfg, adc2_cfg, 0x17);
/* Configure the analog front end */
afe_cfg = cx18_av_read4(cx, CXADEC_AFE_CTRL);
afe_cfg &= 0xff000000;
afe_cfg |= 0x00005000; /* CHROMA_IN, AUD_IN: ADC2; LUMA_IN: ADC1 */
if (ch[1] != NONE && ch[2] != NONE)
afe_cfg |= 0x00000030; /* half_bw_ch[2-3] since in dual mode */
for (i = 0; i < 3; i++) {
switch (ch[i]) {
default:
case NONE:
/* CLAMP_SEL = Fixed to midcode clamp level */
afe_cfg |= (0x00000200 << i);
break;
case CVBS:
case Y:
if (i > 0)
afe_cfg |= 0x00002000; /* LUMA_IN_SEL: ADC2 */
break;
case C:
case Pb:
case Pr:
/* CLAMP_SEL = Fixed to midcode clamp level */
afe_cfg |= (0x00000200 << i);
if (i == 0 && ch[i] == C)
afe_cfg &= ~0x00001000; /* CHROMA_IN_SEL ADC1 */
break;
case SIF:
/*
* VGA_GAIN_SEL = Audio Decoder
* CLAMP_SEL = Fixed to midcode clamp level
*/
afe_cfg |= (0x00000240 << i);
if (i == 0)
afe_cfg &= ~0x00004000; /* AUD_IN_SEL ADC1 */
break;
}
}
cx18_av_write4(cx, CXADEC_AFE_CTRL, afe_cfg);
state->vid_input = vid_input;
state->aud_input = aud_input;
cx18_av_audio_set_path(cx);
input_change(cx);
return 0;
}
static int cx18_av_s_video_routing(struct v4l2_subdev *sd,
u32 input, u32 output, u32 config)
{
struct cx18_av_state *state = to_cx18_av_state(sd);
struct cx18 *cx = v4l2_get_subdevdata(sd);
return set_input(cx, input, state->aud_input);
}
static int cx18_av_s_audio_routing(struct v4l2_subdev *sd,
u32 input, u32 output, u32 config)
{
struct cx18_av_state *state = to_cx18_av_state(sd);
struct cx18 *cx = v4l2_get_subdevdata(sd);
return set_input(cx, state->vid_input, input);
}
static int cx18_av_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
{
struct cx18_av_state *state = to_cx18_av_state(sd);
struct cx18 *cx = v4l2_get_subdevdata(sd);
u8 vpres;
u8 mode;
int val = 0;
if (state->radio)
return 0;
vpres = cx18_av_read(cx, 0x40e) & 0x20;
vt->signal = vpres ? 0xffff : 0x0;
vt->capability |=
V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
mode = cx18_av_read(cx, 0x804);
/* get rxsubchans and audmode */
if ((mode & 0xf) == 1)
val |= V4L2_TUNER_SUB_STEREO;
else
val |= V4L2_TUNER_SUB_MONO;
if (mode == 2 || mode == 4)
val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
if (mode & 0x10)
val |= V4L2_TUNER_SUB_SAP;
vt->rxsubchans = val;
vt->audmode = state->audmode;
return 0;
}
static int cx18_av_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *vt)
{
struct cx18_av_state *state = to_cx18_av_state(sd);
struct cx18 *cx = v4l2_get_subdevdata(sd);
u8 v;
if (state->radio)
return 0;
v = cx18_av_read(cx, 0x809);
v &= ~0xf;
switch (vt->audmode) {
case V4L2_TUNER_MODE_MONO:
/* mono -> mono
stereo -> mono
bilingual -> lang1 */
break;
case V4L2_TUNER_MODE_STEREO:
case V4L2_TUNER_MODE_LANG1:
/* mono -> mono
stereo -> stereo
bilingual -> lang1 */
v |= 0x4;
break;
case V4L2_TUNER_MODE_LANG1_LANG2:
/* mono -> mono
stereo -> stereo
bilingual -> lang1/lang2 */
v |= 0x7;
break;
case V4L2_TUNER_MODE_LANG2:
/* mono -> mono
stereo -> stereo
bilingual -> lang2 */
v |= 0x1;
break;
default:
return -EINVAL;
}
cx18_av_write_expect(cx, 0x809, v, v, 0xff);
state->audmode = vt->audmode;
return 0;
}
static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
{
struct cx18_av_state *state = to_cx18_av_state(sd);
struct cx18 *cx = v4l2_get_subdevdata(sd);
u8 fmt = 0; /* zero is autodetect */
u8 pal_m = 0;
if (state->radio == 0 && state->std == norm)
return 0;
state->radio = 0;
state->std = norm;
/* First tests should be against specific std */
if (state->std == V4L2_STD_NTSC_M_JP) {
fmt = 0x2;
} else if (state->std == V4L2_STD_NTSC_443) {
fmt = 0x3;
} else if (state->std == V4L2_STD_PAL_M) {
pal_m = 1;
fmt = 0x5;
} else if (state->std == V4L2_STD_PAL_N) {
fmt = 0x6;
} else if (state->std == V4L2_STD_PAL_Nc) {
fmt = 0x7;
} else if (state->std == V4L2_STD_PAL_60) {
fmt = 0x8;
} else {
/* Then, test against generic ones */
if (state->std & V4L2_STD_NTSC)
fmt = 0x1;
else if (state->std & V4L2_STD_PAL)
fmt = 0x4;
else if (state->std & V4L2_STD_SECAM)
fmt = 0xc;
}
CX18_DEBUG_INFO_DEV(sd, "changing video std to fmt %i\n", fmt);
/* Follow step 9 of section 3.16 in the cx18_av datasheet.
Without this PAL may display a vertical ghosting effect.
This happens for example with the Yuan MPC622. */
if (fmt >= 4 && fmt < 8) {
/* Set format to NTSC-M */
cx18_av_and_or(cx, 0x400, ~0xf, 1);
/* Turn off LCOMB */
cx18_av_and_or(cx, 0x47b, ~6, 0);
}
cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20);
cx18_av_and_or(cx, 0x403, ~0x3, pal_m);
cx18_av_std_setup(cx);
input_change(cx);
return 0;
}
static int cx18_av_s_radio(struct v4l2_subdev *sd)
{
struct cx18_av_state *state = to_cx18_av_state(sd);
state->radio = 1;
return 0;
}
static int cx18_av_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct v4l2_subdev *sd = to_sd(ctrl);
struct cx18 *cx = v4l2_get_subdevdata(sd);
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
cx18_av_write(cx, 0x414, ctrl->val - 128);
break;
case V4L2_CID_CONTRAST:
cx18_av_write(cx, 0x415, ctrl->val << 1);
break;
case V4L2_CID_SATURATION:
cx18_av_write(cx, 0x420, ctrl->val << 1);
cx18_av_write(cx, 0x421, ctrl->val << 1);
break;
case V4L2_CID_HUE:
cx18_av_write(cx, 0x422, ctrl->val);
break;
default:
return -EINVAL;
}
return 0;
}
static int cx18_av_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *format)
{
struct v4l2_mbus_framefmt *fmt = &format->format;
struct cx18_av_state *state = to_cx18_av_state(sd);
struct cx18 *cx = v4l2_get_subdevdata(sd);
int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
int is_50Hz = !(state->std & V4L2_STD_525_60);
if (format->pad || fmt->code != MEDIA_BUS_FMT_FIXED)
return -EINVAL;
fmt->field = V4L2_FIELD_INTERLACED;
fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4;
Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4;
Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4;
Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4;
/*
* This adjustment reflects the excess of vactive, set in
* cx18_av_std_setup(), above standard values:
*
* 480 + 1 for 60 Hz systems
* 576 + 3 for 50 Hz systems
*/
Vlines = fmt->height + (is_50Hz ? 3 : 1);
/*
* Invalid height and width scaling requests are:
* 1. width less than 1/16 of the source width
* 2. width greater than the source width
* 3. height less than 1/8 of the source height
* 4. height greater than the source height
*/
if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) ||
(Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
CX18_ERR_DEV(sd, "%dx%d is not a valid size!\n",
fmt->width, fmt->height);
return -ERANGE;
}
if (format->which == V4L2_SUBDEV_FORMAT_TRY)
return 0;
HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20);
VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
VSC &= 0x1fff;
if (fmt->width >= 385)
filter = 0;
else if (fmt->width > 192)
filter = 1;
else if (fmt->width > 96)
filter = 2;
else
filter = 3;
CX18_DEBUG_INFO_DEV(sd,
"decoder set size %dx%d -> scale %ux%u\n",
fmt->width, fmt->height, HSC, VSC);
/* HSCALE=HSC */
cx18_av_write(cx, 0x418, HSC & 0xff);
cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff);
cx18_av_write(cx, 0x41a, HSC >> 16);
/* VSCALE=VSC */
cx18_av_write(cx, 0x41c, VSC & 0xff);
cx18_av_write(cx, 0x41d, VSC >> 8);
/* VS_INTRLACE=1 VFILT=filter */
cx18_av_write(cx, 0x41e, 0x8 | filter);
return 0;
}
static int cx18_av_s_stream(struct v4l2_subdev *sd, int enable)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
CX18_DEBUG_INFO_DEV(sd, "%s output\n", enable ? "enable" : "disable");
if (enable) {
cx18_av_write(cx, 0x115, 0x8c);
cx18_av_write(cx, 0x116, 0x07);
} else {
cx18_av_write(cx, 0x115, 0x00);
cx18_av_write(cx, 0x116, 0x00);
}
return 0;
}
static void log_video_status(struct cx18 *cx)
{
static const char *const fmt_strs[] = {
"0x0",
"NTSC-M", "NTSC-J", "NTSC-4.43",
"PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
"0x9", "0xA", "0xB",
"SECAM",
"0xD", "0xE", "0xF"
};
struct cx18_av_state *state = &cx->av_state;
struct v4l2_subdev *sd = &state->sd;
u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf;
u8 gen_stat1 = cx18_av_read(cx, 0x40d);
u8 gen_stat2 = cx18_av_read(cx, 0x40e);
int vid_input = state->vid_input;
CX18_INFO_DEV(sd, "Video signal: %spresent\n",
(gen_stat2 & 0x20) ? "" : "not ");
CX18_INFO_DEV(sd, "Detected format: %s\n",
fmt_strs[gen_stat1 & 0xf]);
CX18_INFO_DEV(sd, "Specified standard: %s\n",
vidfmt_sel ? fmt_strs[vidfmt_sel]
: "automatic detection");
if (vid_input >= CX18_AV_COMPOSITE1 &&
vid_input <= CX18_AV_COMPOSITE8) {
CX18_INFO_DEV(sd, "Specified video input: Composite %d\n",
vid_input - CX18_AV_COMPOSITE1 + 1);
} else {
CX18_INFO_DEV(sd, "Specified video input: S-Video (Luma In%d, Chroma In%d)\n",
(vid_input & 0xf0) >> 4,
(vid_input & 0xf00) >> 8);
}
CX18_INFO_DEV(sd, "Specified audioclock freq: %d Hz\n",
state->audclk_freq);
}
static void log_audio_status(struct cx18 *cx)
{
struct cx18_av_state *state = &cx->av_state;
struct v4l2_subdev *sd = &state->sd;
u8 download_ctl = cx18_av_read(cx, 0x803);
u8 mod_det_stat0 = cx18_av_read(cx, 0x804);
u8 mod_det_stat1 = cx18_av_read(cx, 0x805);
u8 audio_config = cx18_av_read(cx, 0x808);
u8 pref_mode = cx18_av_read(cx, 0x809);
u8 afc0 = cx18_av_read(cx, 0x80b);
u8 mute_ctl = cx18_av_read(cx, 0x8d3);
int aud_input = state->aud_input;
char *p;
switch (mod_det_stat0) {
case 0x00: p = "mono"; break;
case 0x01: p = "stereo"; break;
case 0x02: p = "dual"; break;
case 0x04: p = "tri"; break;
case 0x10: p = "mono with SAP"; break;
case 0x11: p = "stereo with SAP"; break;
case 0x12: p = "dual with SAP"; break;
case 0x14: p = "tri with SAP"; break;
case 0xfe: p = "forced mode"; break;
default: p = "not defined"; break;
}
CX18_INFO_DEV(sd, "Detected audio mode: %s\n", p);
switch (mod_det_stat1) {
case 0x00: p = "not defined"; break;
case 0x01: p = "EIAJ"; break;
case 0x02: p = "A2-M"; break;
case 0x03: p = "A2-BG"; break;
case 0x04: p = "A2-DK1"; break;
case 0x05: p = "A2-DK2"; break;
case 0x06: p = "A2-DK3"; break;
case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
case 0x08: p = "AM-L"; break;
case 0x09: p = "NICAM-BG"; break;
case 0x0a: p = "NICAM-DK"; break;
case 0x0b: p = "NICAM-I"; break;
case 0x0c: p = "NICAM-L"; break;
case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
case 0x0e: p = "IF FM Radio"; break;
case 0x0f: p = "BTSC"; break;
case 0x10: p = "detected chrominance"; break;
case 0xfd: p = "unknown audio standard"; break;
case 0xfe: p = "forced audio standard"; break;
case 0xff: p = "no detected audio standard"; break;
default: p = "not defined"; break;
}
CX18_INFO_DEV(sd, "Detected audio standard: %s\n", p);
CX18_INFO_DEV(sd, "Audio muted: %s\n",
(mute_ctl & 0x2) ? "yes" : "no");
CX18_INFO_DEV(sd, "Audio microcontroller: %s\n",
(download_ctl & 0x10) ? "running" : "stopped");
switch (audio_config >> 4) {
case 0x00: p = "undefined"; break;
case 0x01: p = "BTSC"; break;
case 0x02: p = "EIAJ"; break;
case 0x03: p = "A2-M"; break;
case 0x04: p = "A2-BG"; break;
case 0x05: p = "A2-DK1"; break;
case 0x06: p = "A2-DK2"; break;
case 0x07: p = "A2-DK3"; break;
case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
case 0x09: p = "AM-L"; break;
case 0x0a: p = "NICAM-BG"; break;
case 0x0b: p = "NICAM-DK"; break;
case 0x0c: p = "NICAM-I"; break;
case 0x0d: p = "NICAM-L"; break;
case 0x0e: p = "FM radio"; break;
case 0x0f: p = "automatic detection"; break;
default: p = "undefined"; break;
}
CX18_INFO_DEV(sd, "Configured audio standard: %s\n", p);
if ((audio_config >> 4) < 0xF) {
switch (audio_config & 0xF) {
case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
case 0x01: p = "MONO2 (LANGUAGE B)"; break;
case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
case 0x04: p = "STEREO"; break;
case 0x05: p = "DUAL1 (AC)"; break;
case 0x06: p = "DUAL2 (BC)"; break;
case 0x07: p = "DUAL3 (AB)"; break;
default: p = "undefined";
}
CX18_INFO_DEV(sd, "Configured audio mode: %s\n", p);
} else {
switch (audio_config & 0xF) {
case 0x00: p = "BG"; break;
case 0x01: p = "DK1"; break;
case 0x02: p = "DK2"; break;
case 0x03: p = "DK3"; break;
case 0x04: p = "I"; break;
case 0x05: p = "L"; break;
case 0x06: p = "BTSC"; break;
case 0x07: p = "EIAJ"; break;
case 0x08: p = "A2-M"; break;
case 0x09: p = "FM Radio (4.5 MHz)"; break;
case 0x0a: p = "FM Radio (5.5 MHz)"; break;
case 0x0b: p = "S-Video"; break;
case 0x0f: p = "automatic standard and mode detection"; break;
default: p = "undefined"; break;
}
CX18_INFO_DEV(sd, "Configured audio system: %s\n", p);
}
if (aud_input)
CX18_INFO_DEV(sd, "Specified audio input: Tuner (In%d)\n",
aud_input);
else
CX18_INFO_DEV(sd, "Specified audio input: External\n");
switch (pref_mode & 0xf) {
case 0: p = "mono/language A"; break;
case 1: p = "language B"; break;
case 2: p = "language C"; break;
case 3: p = "analog fallback"; break;
case 4: p = "stereo"; break;
case 5: p = "language AC"; break;
case 6: p = "language BC"; break;
case 7: p = "language AB"; break;
default: p = "undefined"; break;
}
CX18_INFO_DEV(sd, "Preferred audio mode: %s\n", p);
if ((audio_config & 0xf) == 0xf) {
switch ((afc0 >> 3) & 0x1) {
case 0: p = "system DK"; break;
case 1: p = "system L"; break;
}
CX18_INFO_DEV(sd, "Selected 65 MHz format: %s\n", p);
switch (afc0 & 0x7) {
case 0: p = "Chroma"; break;
case 1: p = "BTSC"; break;
case 2: p = "EIAJ"; break;
case 3: p = "A2-M"; break;
case 4: p = "autodetect"; break;
default: p = "undefined"; break;
}
CX18_INFO_DEV(sd, "Selected 45 MHz format: %s\n", p);
}
}
static int cx18_av_log_status(struct v4l2_subdev *sd)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
log_video_status(cx);
log_audio_status(cx);
return 0;
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int cx18_av_g_register(struct v4l2_subdev *sd,
struct v4l2_dbg_register *reg)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
if ((reg->reg & 0x3) != 0)
return -EINVAL;
reg->size = 4;
reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc);
return 0;
}
static int cx18_av_s_register(struct v4l2_subdev *sd,
const struct v4l2_dbg_register *reg)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
if ((reg->reg & 0x3) != 0)
return -EINVAL;
cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val);
return 0;
}
#endif
static const struct v4l2_ctrl_ops cx18_av_ctrl_ops = {
.s_ctrl = cx18_av_s_ctrl,
};
static const struct v4l2_subdev_core_ops cx18_av_general_ops = {
.log_status = cx18_av_log_status,
.load_fw = cx18_av_load_fw,
.reset = cx18_av_reset,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.g_register = cx18_av_g_register,
.s_register = cx18_av_s_register,
#endif
};
static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops = {
.s_radio = cx18_av_s_radio,
.s_frequency = cx18_av_s_frequency,
.g_tuner = cx18_av_g_tuner,
.s_tuner = cx18_av_s_tuner,
};
static const struct v4l2_subdev_audio_ops cx18_av_audio_ops = {
.s_clock_freq = cx18_av_s_clock_freq,
.s_routing = cx18_av_s_audio_routing,
};
static const struct v4l2_subdev_video_ops cx18_av_video_ops = {
.s_std = cx18_av_s_std,
.s_routing = cx18_av_s_video_routing,
.s_stream = cx18_av_s_stream,
};
static const struct v4l2_subdev_vbi_ops cx18_av_vbi_ops = {
.decode_vbi_line = cx18_av_decode_vbi_line,
.g_sliced_fmt = cx18_av_g_sliced_fmt,
.s_sliced_fmt = cx18_av_s_sliced_fmt,
.s_raw_fmt = cx18_av_s_raw_fmt,
};
static const struct v4l2_subdev_pad_ops cx18_av_pad_ops = {
.set_fmt = cx18_av_set_fmt,
};
static const struct v4l2_subdev_ops cx18_av_ops = {
.core = &cx18_av_general_ops,
.tuner = &cx18_av_tuner_ops,
.audio = &cx18_av_audio_ops,
.video = &cx18_av_video_ops,
.vbi = &cx18_av_vbi_ops,
.pad = &cx18_av_pad_ops,
};
int cx18_av_probe(struct cx18 *cx)
{
struct cx18_av_state *state = &cx->av_state;
struct v4l2_subdev *sd;
int err;
state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff;
state->vid_input = CX18_AV_COMPOSITE7;
state->aud_input = CX18_AV_AUDIO8;
state->audclk_freq = 48000;
state->audmode = V4L2_TUNER_MODE_LANG1;
state->slicer_line_delay = 0;
state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
sd = &state->sd;
v4l2_subdev_init(sd, &cx18_av_ops);
v4l2_set_subdevdata(sd, cx);
snprintf(sd->name, sizeof(sd->name),
"%s %03x", cx->v4l2_dev.name, (state->rev >> 4));
sd->grp_id = CX18_HW_418_AV;
v4l2_ctrl_handler_init(&state->hdl, 9);
v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
V4L2_CID_CONTRAST, 0, 127, 1, 64);
v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
V4L2_CID_SATURATION, 0, 127, 1, 64);
v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
V4L2_CID_HUE, -128, 127, 1, 0);
state->volume = v4l2_ctrl_new_std(&state->hdl,
&cx18_av_audio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
0, 65535, 65535 / 100, 0);
v4l2_ctrl_new_std(&state->hdl,
&cx18_av_audio_ctrl_ops, V4L2_CID_AUDIO_MUTE,
0, 1, 1, 0);
v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops,
V4L2_CID_AUDIO_BALANCE,
0, 65535, 65535 / 100, 32768);
v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops,
V4L2_CID_AUDIO_BASS,
0, 65535, 65535 / 100, 32768);
v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops,
V4L2_CID_AUDIO_TREBLE,
0, 65535, 65535 / 100, 32768);
sd->ctrl_handler = &state->hdl;
if (state->hdl.error) {
int err = state->hdl.error;
v4l2_ctrl_handler_free(&state->hdl);
return err;
}
err = v4l2_device_register_subdev(&cx->v4l2_dev, sd);
if (err)
v4l2_ctrl_handler_free(&state->hdl);
else
cx18_av_init(cx);
return err;
}
| linux-master | drivers/media/pci/cx18/cx18-av-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 ioctl system call
*
* Derived from ivtv-ioctl.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-version.h"
#include "cx18-mailbox.h"
#include "cx18-i2c.h"
#include "cx18-queue.h"
#include "cx18-fileops.h"
#include "cx18-vbi.h"
#include "cx18-audio.h"
#include "cx18-video.h"
#include "cx18-streams.h"
#include "cx18-ioctl.h"
#include "cx18-gpio.h"
#include "cx18-controls.h"
#include "cx18-cards.h"
#include "cx18-av-core.h"
#include <media/tveeprom.h>
#include <media/v4l2-event.h>
static const struct v4l2_fmtdesc cx18_formats_yuv[] = {
{
.index = 0,
.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
.pixelformat = V4L2_PIX_FMT_NV12_16L16,
},
{
.index = 1,
.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
.pixelformat = V4L2_PIX_FMT_UYVY,
},
};
static const struct v4l2_fmtdesc cx18_formats_mpeg[] = {
{
.index = 0,
.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
.flags = V4L2_FMT_FLAG_COMPRESSED,
.pixelformat = V4L2_PIX_FMT_MPEG,
},
};
static int cx18_g_fmt_vid_cap(struct file *file, void *fh,
struct v4l2_format *fmt)
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[id->type];
struct v4l2_pix_format *pixfmt = &fmt->fmt.pix;
pixfmt->width = cx->cxhdl.width;
pixfmt->height = cx->cxhdl.height;
pixfmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
pixfmt->field = V4L2_FIELD_INTERLACED;
if (id->type == CX18_ENC_STREAM_TYPE_YUV) {
pixfmt->pixelformat = s->pixelformat;
pixfmt->sizeimage = s->vb_bytes_per_frame;
pixfmt->bytesperline = s->vb_bytes_per_line;
} else {
pixfmt->pixelformat = V4L2_PIX_FMT_MPEG;
pixfmt->sizeimage = 128 * 1024;
pixfmt->bytesperline = 0;
}
return 0;
}
static int cx18_try_fmt_vid_cap(struct file *file, void *fh,
struct v4l2_format *fmt)
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
struct v4l2_pix_format *pixfmt = &fmt->fmt.pix;
int w = pixfmt->width;
int h = pixfmt->height;
w = min(w, 720);
w = max(w, 720 / 16);
h = min(h, cx->is_50hz ? 576 : 480);
h = max(h, (cx->is_50hz ? 576 : 480) / 8);
if (id->type == CX18_ENC_STREAM_TYPE_YUV) {
if (pixfmt->pixelformat != V4L2_PIX_FMT_NV12_16L16 &&
pixfmt->pixelformat != V4L2_PIX_FMT_UYVY)
pixfmt->pixelformat = V4L2_PIX_FMT_UYVY;
/* YUV height must be a multiple of 32 */
h = round_up(h, 32);
/*
* HM12 YUV size is (Y=(h*720) + UV=(h*(720/2)))
* UYUV YUV size is (Y=(h*720) + UV=(h*(720)))
*/
if (pixfmt->pixelformat == V4L2_PIX_FMT_NV12_16L16) {
pixfmt->sizeimage = h * 720 * 3 / 2;
pixfmt->bytesperline = 720; /* First plane */
} else {
pixfmt->sizeimage = h * 720 * 2;
pixfmt->bytesperline = 1440; /* Packed */
}
} else {
pixfmt->pixelformat = V4L2_PIX_FMT_MPEG;
pixfmt->sizeimage = 128 * 1024;
pixfmt->bytesperline = 0;
}
pixfmt->width = w;
pixfmt->height = h;
pixfmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
pixfmt->field = V4L2_FIELD_INTERLACED;
return 0;
}
static int cx18_s_fmt_vid_cap(struct file *file, void *fh,
struct v4l2_format *fmt)
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
struct v4l2_subdev_format format = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
struct cx18_stream *s = &cx->streams[id->type];
int ret;
int w, h;
ret = cx18_try_fmt_vid_cap(file, fh, fmt);
if (ret)
return ret;
w = fmt->fmt.pix.width;
h = fmt->fmt.pix.height;
if (cx->cxhdl.width == w && cx->cxhdl.height == h &&
s->pixelformat == fmt->fmt.pix.pixelformat)
return 0;
if (atomic_read(&cx->ana_capturing) > 0)
return -EBUSY;
s->pixelformat = fmt->fmt.pix.pixelformat;
s->vb_bytes_per_frame = fmt->fmt.pix.sizeimage;
s->vb_bytes_per_line = fmt->fmt.pix.bytesperline;
format.format.width = cx->cxhdl.width = w;
format.format.height = cx->cxhdl.height = h;
format.format.code = MEDIA_BUS_FMT_FIXED;
v4l2_subdev_call(cx->sd_av, pad, set_fmt, NULL, &format);
return cx18_g_fmt_vid_cap(file, fh, fmt);
}
u16 cx18_service2vbi(int type)
{
switch (type) {
case V4L2_SLICED_TELETEXT_B:
return CX18_SLICED_TYPE_TELETEXT_B;
case V4L2_SLICED_CAPTION_525:
return CX18_SLICED_TYPE_CAPTION_525;
case V4L2_SLICED_WSS_625:
return CX18_SLICED_TYPE_WSS_625;
case V4L2_SLICED_VPS:
return CX18_SLICED_TYPE_VPS;
default:
return 0;
}
}
/* Check if VBI services are allowed on the (field, line) for the video std */
static int valid_service_line(int field, int line, int is_pal)
{
return (is_pal && line >= 6 &&
((field == 0 && line <= 23) || (field == 1 && line <= 22))) ||
(!is_pal && line >= 10 && line < 22);
}
/*
* For a (field, line, std) and inbound potential set of services for that line,
* return the first valid service of those passed in the incoming set for that
* line in priority order:
* CC, VPS, or WSS over TELETEXT for well known lines
* TELETEXT, before VPS, before CC, before WSS, for other lines
*/
static u16 select_service_from_set(int field, int line, u16 set, int is_pal)
{
u16 valid_set = (is_pal ? V4L2_SLICED_VBI_625 : V4L2_SLICED_VBI_525);
int i;
set = set & valid_set;
if (set == 0 || !valid_service_line(field, line, is_pal))
return 0;
if (!is_pal) {
if (line == 21 && (set & V4L2_SLICED_CAPTION_525))
return V4L2_SLICED_CAPTION_525;
} else {
if (line == 16 && field == 0 && (set & V4L2_SLICED_VPS))
return V4L2_SLICED_VPS;
if (line == 23 && field == 0 && (set & V4L2_SLICED_WSS_625))
return V4L2_SLICED_WSS_625;
if (line == 23)
return 0;
}
for (i = 0; i < 32; i++) {
if (BIT(i) & set)
return 1 << i;
}
return 0;
}
/*
* Expand the service_set of *fmt into valid service_lines for the std,
* and clear the passed in fmt->service_set
*/
void cx18_expand_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal)
{
u16 set = fmt->service_set;
int f, l;
fmt->service_set = 0;
for (f = 0; f < 2; f++) {
for (l = 0; l < 24; l++)
fmt->service_lines[f][l] = select_service_from_set(f, l, set, is_pal);
}
}
/*
* Sanitize the service_lines in *fmt per the video std, and return 1
* if any service_line is left as valid after santization
*/
static int check_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal)
{
int f, l;
u16 set = 0;
for (f = 0; f < 2; f++) {
for (l = 0; l < 24; l++) {
fmt->service_lines[f][l] = select_service_from_set(f, l, fmt->service_lines[f][l], is_pal);
set |= fmt->service_lines[f][l];
}
}
return set != 0;
}
/* Compute the service_set from the assumed valid service_lines of *fmt */
u16 cx18_get_service_set(struct v4l2_sliced_vbi_format *fmt)
{
int f, l;
u16 set = 0;
for (f = 0; f < 2; f++) {
for (l = 0; l < 24; l++)
set |= fmt->service_lines[f][l];
}
return set;
}
static int cx18_g_fmt_vbi_cap(struct file *file, void *fh,
struct v4l2_format *fmt)
{
struct cx18 *cx = fh2id(fh)->cx;
struct v4l2_vbi_format *vbifmt = &fmt->fmt.vbi;
vbifmt->sampling_rate = 27000000;
vbifmt->offset = 248; /* FIXME - slightly wrong for both 50 & 60 Hz */
vbifmt->samples_per_line = VBI_ACTIVE_SAMPLES - 4;
vbifmt->sample_format = V4L2_PIX_FMT_GREY;
vbifmt->start[0] = cx->vbi.start[0];
vbifmt->start[1] = cx->vbi.start[1];
vbifmt->count[0] = vbifmt->count[1] = cx->vbi.count;
vbifmt->flags = 0;
vbifmt->reserved[0] = 0;
vbifmt->reserved[1] = 0;
return 0;
}
static int cx18_g_fmt_sliced_vbi_cap(struct file *file, void *fh,
struct v4l2_format *fmt)
{
struct cx18 *cx = fh2id(fh)->cx;
struct v4l2_sliced_vbi_format *vbifmt = &fmt->fmt.sliced;
/* sane, V4L2 spec compliant, defaults */
vbifmt->reserved[0] = 0;
vbifmt->reserved[1] = 0;
vbifmt->io_size = sizeof(struct v4l2_sliced_vbi_data) * 36;
memset(vbifmt->service_lines, 0, sizeof(vbifmt->service_lines));
vbifmt->service_set = 0;
/*
* Fetch the configured service_lines and total service_set from the
* digitizer/slicer. Note, cx18_av_vbi() wipes the passed in
* fmt->fmt.sliced under valid calling conditions
*/
if (v4l2_subdev_call(cx->sd_av, vbi, g_sliced_fmt, &fmt->fmt.sliced))
return -EINVAL;
vbifmt->service_set = cx18_get_service_set(vbifmt);
return 0;
}
static int cx18_try_fmt_vbi_cap(struct file *file, void *fh,
struct v4l2_format *fmt)
{
return cx18_g_fmt_vbi_cap(file, fh, fmt);
}
static int cx18_try_fmt_sliced_vbi_cap(struct file *file, void *fh,
struct v4l2_format *fmt)
{
struct cx18 *cx = fh2id(fh)->cx;
struct v4l2_sliced_vbi_format *vbifmt = &fmt->fmt.sliced;
vbifmt->io_size = sizeof(struct v4l2_sliced_vbi_data) * 36;
vbifmt->reserved[0] = 0;
vbifmt->reserved[1] = 0;
/* If given a service set, expand it validly & clear passed in set */
if (vbifmt->service_set)
cx18_expand_service_set(vbifmt, cx->is_50hz);
/* Sanitize the service_lines, and compute the new set if any valid */
if (check_service_set(vbifmt, cx->is_50hz))
vbifmt->service_set = cx18_get_service_set(vbifmt);
return 0;
}
static int cx18_s_fmt_vbi_cap(struct file *file, void *fh,
struct v4l2_format *fmt)
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
int ret;
/*
* Changing the Encoder's Raw VBI parameters won't have any effect
* if any analog capture is ongoing
*/
if (!cx18_raw_vbi(cx) && atomic_read(&cx->ana_capturing) > 0)
return -EBUSY;
/*
* Set the digitizer registers for raw active VBI.
* Note cx18_av_vbi_wipes out a lot of the passed in fmt under valid
* calling conditions
*/
ret = v4l2_subdev_call(cx->sd_av, vbi, s_raw_fmt, &fmt->fmt.vbi);
if (ret)
return ret;
/* Store our new v4l2 (non-)sliced VBI state */
cx->vbi.sliced_in->service_set = 0;
cx->vbi.in.type = V4L2_BUF_TYPE_VBI_CAPTURE;
return cx18_g_fmt_vbi_cap(file, fh, fmt);
}
static int cx18_s_fmt_sliced_vbi_cap(struct file *file, void *fh,
struct v4l2_format *fmt)
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
int ret;
struct v4l2_sliced_vbi_format *vbifmt = &fmt->fmt.sliced;
cx18_try_fmt_sliced_vbi_cap(file, fh, fmt);
/*
* Changing the Encoder's Raw VBI parameters won't have any effect
* if any analog capture is ongoing
*/
if (cx18_raw_vbi(cx) && atomic_read(&cx->ana_capturing) > 0)
return -EBUSY;
/*
* Set the service_lines requested in the digitizer/slicer registers.
* Note, cx18_av_vbi() wipes some "impossible" service lines in the
* passed in fmt->fmt.sliced under valid calling conditions
*/
ret = v4l2_subdev_call(cx->sd_av, vbi, s_sliced_fmt, &fmt->fmt.sliced);
if (ret)
return ret;
/* Store our current v4l2 sliced VBI settings */
cx->vbi.in.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
memcpy(cx->vbi.sliced_in, vbifmt, sizeof(*cx->vbi.sliced_in));
return 0;
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int cx18_g_register(struct file *file, void *fh,
struct v4l2_dbg_register *reg)
{
struct cx18 *cx = fh2id(fh)->cx;
if (reg->reg & 0x3)
return -EINVAL;
if (reg->reg >= CX18_MEM_OFFSET + CX18_MEM_SIZE)
return -EINVAL;
reg->size = 4;
reg->val = cx18_read_enc(cx, reg->reg);
return 0;
}
static int cx18_s_register(struct file *file, void *fh,
const struct v4l2_dbg_register *reg)
{
struct cx18 *cx = fh2id(fh)->cx;
if (reg->reg & 0x3)
return -EINVAL;
if (reg->reg >= CX18_MEM_OFFSET + CX18_MEM_SIZE)
return -EINVAL;
cx18_write_enc(cx, reg->val, reg->reg);
return 0;
}
#endif
static int cx18_querycap(struct file *file, void *fh,
struct v4l2_capability *vcap)
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
strscpy(vcap->driver, CX18_DRIVER_NAME, sizeof(vcap->driver));
strscpy(vcap->card, cx->card_name, sizeof(vcap->card));
vcap->capabilities = cx->v4l2_cap | V4L2_CAP_DEVICE_CAPS;
return 0;
}
static int cx18_enumaudio(struct file *file, void *fh, struct v4l2_audio *vin)
{
struct cx18 *cx = fh2id(fh)->cx;
return cx18_get_audio_input(cx, vin->index, vin);
}
static int cx18_g_audio(struct file *file, void *fh, struct v4l2_audio *vin)
{
struct cx18 *cx = fh2id(fh)->cx;
vin->index = cx->audio_input;
return cx18_get_audio_input(cx, vin->index, vin);
}
static int cx18_s_audio(struct file *file, void *fh, const struct v4l2_audio *vout)
{
struct cx18 *cx = fh2id(fh)->cx;
if (vout->index >= cx->nof_audio_inputs)
return -EINVAL;
cx->audio_input = vout->index;
cx18_audio_set_io(cx);
return 0;
}
static int cx18_enum_input(struct file *file, void *fh, struct v4l2_input *vin)
{
struct cx18 *cx = fh2id(fh)->cx;
/* set it to defaults from our table */
return cx18_get_input(cx, vin->index, vin);
}
static int cx18_g_pixelaspect(struct file *file, void *fh,
int type, struct v4l2_fract *f)
{
struct cx18 *cx = fh2id(fh)->cx;
if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
f->numerator = cx->is_50hz ? 54 : 11;
f->denominator = cx->is_50hz ? 59 : 10;
return 0;
}
static int cx18_g_selection(struct file *file, void *fh,
struct v4l2_selection *sel)
{
struct cx18 *cx = fh2id(fh)->cx;
if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
switch (sel->target) {
case V4L2_SEL_TGT_CROP_BOUNDS:
case V4L2_SEL_TGT_CROP_DEFAULT:
sel->r.top = sel->r.left = 0;
sel->r.width = 720;
sel->r.height = cx->is_50hz ? 576 : 480;
break;
default:
return -EINVAL;
}
return 0;
}
static int cx18_enum_fmt_vid_cap(struct file *file, void *fh,
struct v4l2_fmtdesc *fmt)
{
struct cx18_open_id *id = fh2id(fh);
if (id->type == CX18_ENC_STREAM_TYPE_YUV) {
if (fmt->index >= ARRAY_SIZE(cx18_formats_yuv))
return -EINVAL;
*fmt = cx18_formats_yuv[fmt->index];
return 0;
}
if (fmt->index)
return -EINVAL;
*fmt = cx18_formats_mpeg[0];
return 0;
}
static int cx18_g_input(struct file *file, void *fh, unsigned int *i)
{
struct cx18 *cx = fh2id(fh)->cx;
*i = cx->active_input;
return 0;
}
int cx18_s_input(struct file *file, void *fh, unsigned int inp)
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
v4l2_std_id std = V4L2_STD_ALL;
const struct cx18_card_video_input *card_input =
cx->card->video_inputs + inp;
if (inp >= cx->nof_inputs)
return -EINVAL;
if (inp == cx->active_input) {
CX18_DEBUG_INFO("Input unchanged\n");
return 0;
}
CX18_DEBUG_INFO("Changing input from %d to %d\n",
cx->active_input, inp);
cx->active_input = inp;
/* Set the audio input to whatever is appropriate for the input type. */
cx->audio_input = cx->card->video_inputs[inp].audio_index;
if (card_input->video_type == V4L2_INPUT_TYPE_TUNER)
std = cx->tuner_std;
cx->streams[CX18_ENC_STREAM_TYPE_MPG].video_dev.tvnorms = std;
cx->streams[CX18_ENC_STREAM_TYPE_YUV].video_dev.tvnorms = std;
cx->streams[CX18_ENC_STREAM_TYPE_VBI].video_dev.tvnorms = std;
/* prevent others from messing with the streams until
we're finished changing inputs. */
cx18_mute(cx);
cx18_video_set_io(cx);
cx18_audio_set_io(cx);
cx18_unmute(cx);
return 0;
}
static int cx18_g_frequency(struct file *file, void *fh,
struct v4l2_frequency *vf)
{
struct cx18 *cx = fh2id(fh)->cx;
if (vf->tuner != 0)
return -EINVAL;
cx18_call_all(cx, tuner, g_frequency, vf);
return 0;
}
int cx18_s_frequency(struct file *file, void *fh, const struct v4l2_frequency *vf)
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
if (vf->tuner != 0)
return -EINVAL;
cx18_mute(cx);
CX18_DEBUG_INFO("v4l2 ioctl: set frequency %d\n", vf->frequency);
cx18_call_all(cx, tuner, s_frequency, vf);
cx18_unmute(cx);
return 0;
}
static int cx18_g_std(struct file *file, void *fh, v4l2_std_id *std)
{
struct cx18 *cx = fh2id(fh)->cx;
*std = cx->std;
return 0;
}
int cx18_s_std(struct file *file, void *fh, v4l2_std_id std)
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
if ((std & V4L2_STD_ALL) == 0)
return -EINVAL;
if (std == cx->std)
return 0;
if (test_bit(CX18_F_I_RADIO_USER, &cx->i_flags) ||
atomic_read(&cx->ana_capturing) > 0) {
/* Switching standard would turn off the radio or mess
with already running streams, prevent that by
returning EBUSY. */
return -EBUSY;
}
cx->std = std;
cx->is_60hz = (std & V4L2_STD_525_60) ? 1 : 0;
cx->is_50hz = !cx->is_60hz;
cx2341x_handler_set_50hz(&cx->cxhdl, cx->is_50hz);
cx->cxhdl.width = 720;
cx->cxhdl.height = cx->is_50hz ? 576 : 480;
/*
* HM12 YUV size is (Y=(h*720) + UV=(h*(720/2)))
* UYUV YUV size is (Y=(h*720) + UV=(h*(720)))
*/
if (cx->streams[CX18_ENC_STREAM_TYPE_YUV].pixelformat == V4L2_PIX_FMT_NV12_16L16) {
cx->streams[CX18_ENC_STREAM_TYPE_YUV].vb_bytes_per_frame =
cx->cxhdl.height * 720 * 3 / 2;
cx->streams[CX18_ENC_STREAM_TYPE_YUV].vb_bytes_per_line = 720;
} else {
cx->streams[CX18_ENC_STREAM_TYPE_YUV].vb_bytes_per_frame =
cx->cxhdl.height * 720 * 2;
cx->streams[CX18_ENC_STREAM_TYPE_YUV].vb_bytes_per_line = 1440;
}
cx->vbi.count = cx->is_50hz ? 18 : 12;
cx->vbi.start[0] = cx->is_50hz ? 6 : 10;
cx->vbi.start[1] = cx->is_50hz ? 318 : 273;
CX18_DEBUG_INFO("Switching standard to %llx.\n",
(unsigned long long) cx->std);
/* Tuner */
cx18_call_all(cx, video, s_std, cx->std);
return 0;
}
static int cx18_s_tuner(struct file *file, void *fh, const struct v4l2_tuner *vt)
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
if (vt->index != 0)
return -EINVAL;
cx18_call_all(cx, tuner, s_tuner, vt);
return 0;
}
static int cx18_g_tuner(struct file *file, void *fh, struct v4l2_tuner *vt)
{
struct cx18 *cx = fh2id(fh)->cx;
if (vt->index != 0)
return -EINVAL;
cx18_call_all(cx, tuner, g_tuner, vt);
if (vt->type == V4L2_TUNER_RADIO)
strscpy(vt->name, "cx18 Radio Tuner", sizeof(vt->name));
else
strscpy(vt->name, "cx18 TV Tuner", sizeof(vt->name));
return 0;
}
static int cx18_g_sliced_vbi_cap(struct file *file, void *fh,
struct v4l2_sliced_vbi_cap *cap)
{
struct cx18 *cx = fh2id(fh)->cx;
int set = cx->is_50hz ? V4L2_SLICED_VBI_625 : V4L2_SLICED_VBI_525;
int f, l;
if (cap->type != V4L2_BUF_TYPE_SLICED_VBI_CAPTURE)
return -EINVAL;
cap->service_set = 0;
for (f = 0; f < 2; f++) {
for (l = 0; l < 24; l++) {
if (valid_service_line(f, l, cx->is_50hz)) {
/*
* We can find all v4l2 supported vbi services
* for the standard, on a valid line for the std
*/
cap->service_lines[f][l] = set;
cap->service_set |= set;
} else
cap->service_lines[f][l] = 0;
}
}
for (f = 0; f < 3; f++)
cap->reserved[f] = 0;
return 0;
}
static int _cx18_process_idx_data(struct cx18_buffer *buf,
struct v4l2_enc_idx *idx)
{
int consumed, remaining;
struct v4l2_enc_idx_entry *e_idx;
struct cx18_enc_idx_entry *e_buf;
/* Frame type lookup: 1=I, 2=P, 4=B */
static const int mapping[8] = {
-1, V4L2_ENC_IDX_FRAME_I, V4L2_ENC_IDX_FRAME_P,
-1, V4L2_ENC_IDX_FRAME_B, -1, -1, -1
};
/*
* Assumption here is that a buf holds an integral number of
* struct cx18_enc_idx_entry objects and is properly aligned.
* This is enforced by the module options on IDX buffer sizes.
*/
remaining = buf->bytesused - buf->readpos;
consumed = 0;
e_idx = &idx->entry[idx->entries];
e_buf = (struct cx18_enc_idx_entry *) &buf->buf[buf->readpos];
while (remaining >= sizeof(struct cx18_enc_idx_entry) &&
idx->entries < V4L2_ENC_IDX_ENTRIES) {
e_idx->offset = (((u64) le32_to_cpu(e_buf->offset_high)) << 32)
| le32_to_cpu(e_buf->offset_low);
e_idx->pts = (((u64) (le32_to_cpu(e_buf->pts_high) & 1)) << 32)
| le32_to_cpu(e_buf->pts_low);
e_idx->length = le32_to_cpu(e_buf->length);
e_idx->flags = mapping[le32_to_cpu(e_buf->flags) & 0x7];
e_idx->reserved[0] = 0;
e_idx->reserved[1] = 0;
idx->entries++;
e_idx = &idx->entry[idx->entries];
e_buf++;
remaining -= sizeof(struct cx18_enc_idx_entry);
consumed += sizeof(struct cx18_enc_idx_entry);
}
/* Swallow any partial entries at the end, if there are any */
if (remaining > 0 && remaining < sizeof(struct cx18_enc_idx_entry))
consumed += remaining;
buf->readpos += consumed;
return consumed;
}
static int cx18_process_idx_data(struct cx18_stream *s, struct cx18_mdl *mdl,
struct v4l2_enc_idx *idx)
{
if (s->type != CX18_ENC_STREAM_TYPE_IDX)
return -EINVAL;
if (mdl->curr_buf == NULL)
mdl->curr_buf = list_first_entry(&mdl->buf_list,
struct cx18_buffer, list);
if (list_entry_is_past_end(mdl->curr_buf, &mdl->buf_list, list)) {
/*
* For some reason we've exhausted the buffers, but the MDL
* object still said some data was unread.
* Fix that and bail out.
*/
mdl->readpos = mdl->bytesused;
return 0;
}
list_for_each_entry_from(mdl->curr_buf, &mdl->buf_list, list) {
/* Skip any empty buffers in the MDL */
if (mdl->curr_buf->readpos >= mdl->curr_buf->bytesused)
continue;
mdl->readpos += _cx18_process_idx_data(mdl->curr_buf, idx);
/* exit when MDL drained or request satisfied */
if (idx->entries >= V4L2_ENC_IDX_ENTRIES ||
mdl->curr_buf->readpos < mdl->curr_buf->bytesused ||
mdl->readpos >= mdl->bytesused)
break;
}
return 0;
}
static int cx18_g_enc_index(struct file *file, void *fh,
struct v4l2_enc_idx *idx)
{
struct cx18 *cx = fh2id(fh)->cx;
struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
s32 tmp;
struct cx18_mdl *mdl;
if (!cx18_stream_enabled(s)) /* Module options inhibited IDX stream */
return -EINVAL;
/* Compute the best case number of entries we can buffer */
tmp = s->buffers -
s->bufs_per_mdl * CX18_ENC_STREAM_TYPE_IDX_FW_MDL_MIN;
if (tmp <= 0)
tmp = 1;
tmp = tmp * s->buf_size / sizeof(struct cx18_enc_idx_entry);
/* Fill out the header of the return structure */
idx->entries = 0;
idx->entries_cap = tmp;
memset(idx->reserved, 0, sizeof(idx->reserved));
/* Pull IDX MDLs and buffers from q_full and populate the entries */
do {
mdl = cx18_dequeue(s, &s->q_full);
if (mdl == NULL) /* No more IDX data right now */
break;
/* Extract the Index entry data from the MDL and buffers */
cx18_process_idx_data(s, mdl, idx);
if (mdl->readpos < mdl->bytesused) {
/* We finished with data remaining, push the MDL back */
cx18_push(s, mdl, &s->q_full);
break;
}
/* We drained this MDL, schedule it to go to the firmware */
cx18_enqueue(s, mdl, &s->q_free);
} while (idx->entries < V4L2_ENC_IDX_ENTRIES);
/* Tell the work handler to send free IDX MDLs to the firmware */
cx18_stream_load_fw_queue(s);
return 0;
}
static int cx18_encoder_cmd(struct file *file, void *fh,
struct v4l2_encoder_cmd *enc)
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
u32 h;
switch (enc->cmd) {
case V4L2_ENC_CMD_START:
CX18_DEBUG_IOCTL("V4L2_ENC_CMD_START\n");
enc->flags = 0;
return cx18_start_capture(id);
case V4L2_ENC_CMD_STOP:
CX18_DEBUG_IOCTL("V4L2_ENC_CMD_STOP\n");
enc->flags &= V4L2_ENC_CMD_STOP_AT_GOP_END;
cx18_stop_capture(&cx->streams[id->type],
enc->flags & V4L2_ENC_CMD_STOP_AT_GOP_END);
break;
case V4L2_ENC_CMD_PAUSE:
CX18_DEBUG_IOCTL("V4L2_ENC_CMD_PAUSE\n");
enc->flags = 0;
if (!atomic_read(&cx->ana_capturing))
return -EPERM;
if (test_and_set_bit(CX18_F_I_ENC_PAUSED, &cx->i_flags))
return 0;
h = cx18_find_handle(cx);
if (h == CX18_INVALID_TASK_HANDLE) {
CX18_ERR("Can't find valid task handle for V4L2_ENC_CMD_PAUSE\n");
return -EBADFD;
}
cx18_mute(cx);
cx18_vapi(cx, CX18_CPU_CAPTURE_PAUSE, 1, h);
break;
case V4L2_ENC_CMD_RESUME:
CX18_DEBUG_IOCTL("V4L2_ENC_CMD_RESUME\n");
enc->flags = 0;
if (!atomic_read(&cx->ana_capturing))
return -EPERM;
if (!test_and_clear_bit(CX18_F_I_ENC_PAUSED, &cx->i_flags))
return 0;
h = cx18_find_handle(cx);
if (h == CX18_INVALID_TASK_HANDLE) {
CX18_ERR("Can't find valid task handle for V4L2_ENC_CMD_RESUME\n");
return -EBADFD;
}
cx18_vapi(cx, CX18_CPU_CAPTURE_RESUME, 1, h);
cx18_unmute(cx);
break;
default:
CX18_DEBUG_IOCTL("Unknown cmd %d\n", enc->cmd);
return -EINVAL;
}
return 0;
}
static int cx18_try_encoder_cmd(struct file *file, void *fh,
struct v4l2_encoder_cmd *enc)
{
struct cx18 *cx = fh2id(fh)->cx;
switch (enc->cmd) {
case V4L2_ENC_CMD_START:
CX18_DEBUG_IOCTL("V4L2_ENC_CMD_START\n");
enc->flags = 0;
break;
case V4L2_ENC_CMD_STOP:
CX18_DEBUG_IOCTL("V4L2_ENC_CMD_STOP\n");
enc->flags &= V4L2_ENC_CMD_STOP_AT_GOP_END;
break;
case V4L2_ENC_CMD_PAUSE:
CX18_DEBUG_IOCTL("V4L2_ENC_CMD_PAUSE\n");
enc->flags = 0;
break;
case V4L2_ENC_CMD_RESUME:
CX18_DEBUG_IOCTL("V4L2_ENC_CMD_RESUME\n");
enc->flags = 0;
break;
default:
CX18_DEBUG_IOCTL("Unknown cmd %d\n", enc->cmd);
return -EINVAL;
}
return 0;
}
static int cx18_log_status(struct file *file, void *fh)
{
struct cx18 *cx = fh2id(fh)->cx;
struct v4l2_input vidin;
struct v4l2_audio audin;
int i;
CX18_INFO("Version: %s Card: %s\n", CX18_VERSION, cx->card_name);
if (cx->hw_flags & CX18_HW_TVEEPROM) {
struct tveeprom tv;
cx18_read_eeprom(cx, &tv);
}
cx18_call_all(cx, core, log_status);
cx18_get_input(cx, cx->active_input, &vidin);
cx18_get_audio_input(cx, cx->audio_input, &audin);
CX18_INFO("Video Input: %s\n", vidin.name);
CX18_INFO("Audio Input: %s\n", audin.name);
mutex_lock(&cx->gpio_lock);
CX18_INFO("GPIO: direction 0x%08x, value 0x%08x\n",
cx->gpio_dir, cx->gpio_val);
mutex_unlock(&cx->gpio_lock);
CX18_INFO("Tuner: %s\n",
test_bit(CX18_F_I_RADIO_USER, &cx->i_flags) ? "Radio" : "TV");
v4l2_ctrl_handler_log_status(&cx->cxhdl.hdl, cx->v4l2_dev.name);
CX18_INFO("Status flags: 0x%08lx\n", cx->i_flags);
for (i = 0; i < CX18_MAX_STREAMS; i++) {
struct cx18_stream *s = &cx->streams[i];
if (s->video_dev.v4l2_dev == NULL || s->buffers == 0)
continue;
CX18_INFO("Stream %s: status 0x%04lx, %d%% of %d KiB (%d buffers) in use\n",
s->name, s->s_flags,
atomic_read(&s->q_full.depth) * s->bufs_per_mdl * 100
/ s->buffers,
(s->buffers * s->buf_size) / 1024, s->buffers);
}
CX18_INFO("Read MPEG/VBI: %lld/%lld bytes\n",
(long long)cx->mpg_data_received,
(long long)cx->vbi_data_inserted);
return 0;
}
static long cx18_default(struct file *file, void *fh, bool valid_prio,
unsigned int cmd, void *arg)
{
struct cx18 *cx = fh2id(fh)->cx;
switch (cmd) {
case VIDIOC_INT_RESET: {
u32 val = *(u32 *)arg;
if ((val == 0) || (val & 0x01))
cx18_call_hw(cx, CX18_HW_GPIO_RESET_CTRL, core, reset,
(u32) CX18_GPIO_RESET_Z8F0811);
break;
}
default:
return -ENOTTY;
}
return 0;
}
static const struct v4l2_ioctl_ops cx18_ioctl_ops = {
.vidioc_querycap = cx18_querycap,
.vidioc_s_audio = cx18_s_audio,
.vidioc_g_audio = cx18_g_audio,
.vidioc_enumaudio = cx18_enumaudio,
.vidioc_enum_input = cx18_enum_input,
.vidioc_g_pixelaspect = cx18_g_pixelaspect,
.vidioc_g_selection = cx18_g_selection,
.vidioc_g_input = cx18_g_input,
.vidioc_s_input = cx18_s_input,
.vidioc_g_frequency = cx18_g_frequency,
.vidioc_s_frequency = cx18_s_frequency,
.vidioc_s_tuner = cx18_s_tuner,
.vidioc_g_tuner = cx18_g_tuner,
.vidioc_g_enc_index = cx18_g_enc_index,
.vidioc_g_std = cx18_g_std,
.vidioc_s_std = cx18_s_std,
.vidioc_log_status = cx18_log_status,
.vidioc_enum_fmt_vid_cap = cx18_enum_fmt_vid_cap,
.vidioc_encoder_cmd = cx18_encoder_cmd,
.vidioc_try_encoder_cmd = cx18_try_encoder_cmd,
.vidioc_g_fmt_vid_cap = cx18_g_fmt_vid_cap,
.vidioc_g_fmt_vbi_cap = cx18_g_fmt_vbi_cap,
.vidioc_g_fmt_sliced_vbi_cap = cx18_g_fmt_sliced_vbi_cap,
.vidioc_s_fmt_vid_cap = cx18_s_fmt_vid_cap,
.vidioc_s_fmt_vbi_cap = cx18_s_fmt_vbi_cap,
.vidioc_s_fmt_sliced_vbi_cap = cx18_s_fmt_sliced_vbi_cap,
.vidioc_try_fmt_vid_cap = cx18_try_fmt_vid_cap,
.vidioc_try_fmt_vbi_cap = cx18_try_fmt_vbi_cap,
.vidioc_try_fmt_sliced_vbi_cap = cx18_try_fmt_sliced_vbi_cap,
.vidioc_g_sliced_vbi_cap = cx18_g_sliced_vbi_cap,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.vidioc_g_register = cx18_g_register,
.vidioc_s_register = cx18_s_register,
#endif
.vidioc_default = cx18_default,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_create_bufs = vb2_ioctl_create_bufs,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
void cx18_set_funcs(struct video_device *vdev)
{
vdev->ioctl_ops = &cx18_ioctl_ops;
}
| linux-master | drivers/media/pci/cx18/cx18-ioctl.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 functions for DVB support
*
* Copyright (c) 2008 Steven Toth <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-version.h"
#include "cx18-dvb.h"
#include "cx18-io.h"
#include "cx18-queue.h"
#include "cx18-streams.h"
#include "cx18-cards.h"
#include "cx18-gpio.h"
#include "s5h1409.h"
#include "mxl5005s.h"
#include "s5h1411.h"
#include "tda18271.h"
#include "zl10353.h"
#include <linux/firmware.h>
#include "mt352.h"
#include "mt352_priv.h"
#include "xc2028.h"
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
#define FWFILE "dvb-cx18-mpc718-mt352.fw"
#define CX18_REG_DMUX_NUM_PORT_0_CONTROL 0xd5a000
#define CX18_CLOCK_ENABLE2 0xc71024
#define CX18_DMUX_CLK_MASK 0x0080
/*
* CX18_CARD_HVR_1600_ESMT
* CX18_CARD_HVR_1600_SAMSUNG
*/
static struct mxl5005s_config hauppauge_hvr1600_tuner = {
.i2c_address = 0xC6 >> 1,
.if_freq = IF_FREQ_5380000HZ,
.xtal_freq = CRYSTAL_FREQ_16000000HZ,
.agc_mode = MXL_SINGLE_AGC,
.tracking_filter = MXL_TF_C_H,
.rssi_enable = MXL_RSSI_ENABLE,
.cap_select = MXL_CAP_SEL_ENABLE,
.div_out = MXL_DIV_OUT_4,
.clock_out = MXL_CLOCK_OUT_DISABLE,
.output_load = MXL5005S_IF_OUTPUT_LOAD_200_OHM,
.top = MXL5005S_TOP_25P2,
.mod_mode = MXL_DIGITAL_MODE,
.if_mode = MXL_ZERO_IF,
.qam_gain = 0x02,
.AgcMasterByte = 0x00,
};
static struct s5h1409_config hauppauge_hvr1600_config = {
.demod_address = 0x32 >> 1,
.output_mode = S5H1409_SERIAL_OUTPUT,
.gpio = S5H1409_GPIO_ON,
.qam_if = 44000,
.inversion = S5H1409_INVERSION_OFF,
.status_mode = S5H1409_DEMODLOCKING,
.mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
.hvr1600_opt = S5H1409_HVR1600_OPTIMIZE
};
/*
* CX18_CARD_HVR_1600_S5H1411
*/
static struct s5h1411_config hcw_s5h1411_config = {
.output_mode = S5H1411_SERIAL_OUTPUT,
.gpio = S5H1411_GPIO_OFF,
.vsb_if = S5H1411_IF_44000,
.qam_if = S5H1411_IF_4000,
.inversion = S5H1411_INVERSION_ON,
.status_mode = S5H1411_DEMODLOCKING,
.mpeg_timing = S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static struct tda18271_std_map hauppauge_tda18271_std_map = {
.atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
.if_lvl = 6, .rfagc_top = 0x37 },
.qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
.if_lvl = 6, .rfagc_top = 0x37 },
};
static struct tda18271_config hauppauge_tda18271_config = {
.std_map = &hauppauge_tda18271_std_map,
.gate = TDA18271_GATE_DIGITAL,
.output_opt = TDA18271_OUTPUT_LT_OFF,
};
/*
* CX18_CARD_LEADTEK_DVR3100H
*/
/* Information/confirmation of proper config values provided by Terry Wu */
static struct zl10353_config leadtek_dvr3100h_demod = {
.demod_address = 0x1e >> 1, /* Datasheet suggested straps */
.if2 = 45600, /* 4.560 MHz IF from the XC3028 */
.parallel_ts = 1, /* Not a serial TS */
.no_tuner = 1, /* XC3028 is not behind the gate */
.disable_i2c_gate_ctrl = 1, /* Disable the I2C gate */
};
/*
* CX18_CARD_YUAN_MPC718
*/
/*
* Due to
*
* 1. an absence of information on how to program the MT352
* 2. the Linux mt352 module pushing MT352 initialization off onto us here
*
* We have to use an init sequence that *you* must extract from the Windows
* driver (yuanrap.sys) and which we load as a firmware.
*
* If someone can provide me with a Zarlink MT352 (Intel CE6352?) Design Manual
* with chip programming details, then I can remove this annoyance.
*/
static int yuan_mpc718_mt352_reqfw(struct cx18_stream *stream,
const struct firmware **fw)
{
struct cx18 *cx = stream->cx;
const char *fn = FWFILE;
int ret;
ret = request_firmware(fw, fn, &cx->pci_dev->dev);
if (ret)
CX18_ERR("Unable to open firmware file %s\n", fn);
else {
size_t sz = (*fw)->size;
if (sz < 2 || sz > 64 || (sz % 2) != 0) {
CX18_ERR("Firmware %s has a bad size: %lu bytes\n",
fn, (unsigned long) sz);
ret = -EILSEQ;
release_firmware(*fw);
*fw = NULL;
}
}
if (ret) {
CX18_ERR("The MPC718 board variant with the MT352 DVB-T demodulator will not work without it\n");
CX18_ERR("Run 'linux/scripts/get_dvb_firmware mpc718' if you need the firmware\n");
}
return ret;
}
static int yuan_mpc718_mt352_init(struct dvb_frontend *fe)
{
struct cx18_dvb *dvb = container_of(fe->dvb,
struct cx18_dvb, dvb_adapter);
struct cx18_stream *stream = dvb->stream;
const struct firmware *fw = NULL;
int ret;
int i;
u8 buf[3];
ret = yuan_mpc718_mt352_reqfw(stream, &fw);
if (ret)
return ret;
/* Loop through all the register-value pairs in the firmware file */
for (i = 0; i < fw->size; i += 2) {
buf[0] = fw->data[i];
/* Intercept a few registers we want to set ourselves */
switch (buf[0]) {
case TRL_NOMINAL_RATE_0:
/* Set our custom OFDM bandwidth in the case below */
break;
case TRL_NOMINAL_RATE_1:
/* 6 MHz: 64/7 * 6/8 / 20.48 * 2^16 = 0x55b6.db6 */
/* 7 MHz: 64/7 * 7/8 / 20.48 * 2^16 = 0x6400 */
/* 8 MHz: 64/7 * 8/8 / 20.48 * 2^16 = 0x7249.249 */
buf[1] = 0x72;
buf[2] = 0x49;
mt352_write(fe, buf, 3);
break;
case INPUT_FREQ_0:
/* Set our custom IF in the case below */
break;
case INPUT_FREQ_1:
/* 4.56 MHz IF: (20.48 - 4.56)/20.48 * 2^14 = 0x31c0 */
buf[1] = 0x31;
buf[2] = 0xc0;
mt352_write(fe, buf, 3);
break;
default:
/* Pass through the register-value pair from the fw */
buf[1] = fw->data[i+1];
mt352_write(fe, buf, 2);
break;
}
}
buf[0] = (u8) TUNER_GO;
buf[1] = 0x01; /* Go */
mt352_write(fe, buf, 2);
release_firmware(fw);
return 0;
}
static struct mt352_config yuan_mpc718_mt352_demod = {
.demod_address = 0x1e >> 1,
.adc_clock = 20480, /* 20.480 MHz */
.if2 = 4560, /* 4.560 MHz */
.no_tuner = 1, /* XC3028 is not behind the gate */
.demod_init = yuan_mpc718_mt352_init,
};
static struct zl10353_config yuan_mpc718_zl10353_demod = {
.demod_address = 0x1e >> 1, /* Datasheet suggested straps */
.if2 = 45600, /* 4.560 MHz IF from the XC3028 */
.parallel_ts = 1, /* Not a serial TS */
.no_tuner = 1, /* XC3028 is not behind the gate */
.disable_i2c_gate_ctrl = 1, /* Disable the I2C gate */
};
static struct zl10353_config gotview_dvd3_zl10353_demod = {
.demod_address = 0x1e >> 1, /* Datasheet suggested straps */
.if2 = 45600, /* 4.560 MHz IF from the XC3028 */
.parallel_ts = 1, /* Not a serial TS */
.no_tuner = 1, /* XC3028 is not behind the gate */
.disable_i2c_gate_ctrl = 1, /* Disable the I2C gate */
};
static int dvb_register(struct cx18_stream *stream);
/* Kernel DVB framework calls this when the feed needs to start.
* The CX18 framework should enable the transport DMA handling
* and queue processing.
*/
static int cx18_dvb_start_feed(struct dvb_demux_feed *feed)
{
struct dvb_demux *demux = feed->demux;
struct cx18_stream *stream = demux->priv;
struct cx18 *cx;
int ret;
u32 v;
if (!stream)
return -EINVAL;
cx = stream->cx;
CX18_DEBUG_INFO("Start feed: pid = 0x%x index = %d\n",
feed->pid, feed->index);
mutex_lock(&cx->serialize_lock);
ret = cx18_init_on_first_open(cx);
mutex_unlock(&cx->serialize_lock);
if (ret) {
CX18_ERR("Failed to initialize firmware starting DVB feed\n");
return ret;
}
ret = -EINVAL;
switch (cx->card->type) {
case CX18_CARD_HVR_1600_ESMT:
case CX18_CARD_HVR_1600_SAMSUNG:
case CX18_CARD_HVR_1600_S5H1411:
v = cx18_read_reg(cx, CX18_REG_DMUX_NUM_PORT_0_CONTROL);
v |= 0x00400000; /* Serial Mode */
v |= 0x00002000; /* Data Length - Byte */
v |= 0x00010000; /* Error - Polarity */
v |= 0x00020000; /* Error - Passthru */
v |= 0x000c0000; /* Error - Ignore */
cx18_write_reg(cx, v, CX18_REG_DMUX_NUM_PORT_0_CONTROL);
break;
case CX18_CARD_LEADTEK_DVR3100H:
case CX18_CARD_YUAN_MPC718:
case CX18_CARD_GOTVIEW_PCI_DVD3:
default:
/* Assumption - Parallel transport - Signalling
* undefined or default.
*/
break;
}
if (!demux->dmx.frontend)
return -EINVAL;
mutex_lock(&stream->dvb->feedlock);
if (stream->dvb->feeding++ == 0) {
CX18_DEBUG_INFO("Starting Transport DMA\n");
mutex_lock(&cx->serialize_lock);
set_bit(CX18_F_S_STREAMING, &stream->s_flags);
ret = cx18_start_v4l2_encode_stream(stream);
if (ret < 0) {
CX18_DEBUG_INFO("Failed to start Transport DMA\n");
stream->dvb->feeding--;
if (stream->dvb->feeding == 0)
clear_bit(CX18_F_S_STREAMING, &stream->s_flags);
}
mutex_unlock(&cx->serialize_lock);
} else
ret = 0;
mutex_unlock(&stream->dvb->feedlock);
return ret;
}
/* Kernel DVB framework calls this when the feed needs to stop. */
static int cx18_dvb_stop_feed(struct dvb_demux_feed *feed)
{
struct dvb_demux *demux = feed->demux;
struct cx18_stream *stream = demux->priv;
struct cx18 *cx;
int ret = -EINVAL;
if (stream) {
cx = stream->cx;
CX18_DEBUG_INFO("Stop feed: pid = 0x%x index = %d\n",
feed->pid, feed->index);
mutex_lock(&stream->dvb->feedlock);
if (--stream->dvb->feeding == 0) {
CX18_DEBUG_INFO("Stopping Transport DMA\n");
mutex_lock(&cx->serialize_lock);
ret = cx18_stop_v4l2_encode_stream(stream, 0);
mutex_unlock(&cx->serialize_lock);
} else
ret = 0;
mutex_unlock(&stream->dvb->feedlock);
}
return ret;
}
int cx18_dvb_register(struct cx18_stream *stream)
{
struct cx18 *cx = stream->cx;
struct cx18_dvb *dvb = stream->dvb;
struct dvb_adapter *dvb_adapter;
struct dvb_demux *dvbdemux;
struct dmx_demux *dmx;
int ret;
if (!dvb)
return -EINVAL;
dvb->enabled = 0;
dvb->stream = stream;
ret = dvb_register_adapter(&dvb->dvb_adapter,
CX18_DRIVER_NAME,
THIS_MODULE, &cx->pci_dev->dev, adapter_nr);
if (ret < 0)
goto err_out;
dvb_adapter = &dvb->dvb_adapter;
dvbdemux = &dvb->demux;
dvbdemux->priv = (void *)stream;
dvbdemux->filternum = 256;
dvbdemux->feednum = 256;
dvbdemux->start_feed = cx18_dvb_start_feed;
dvbdemux->stop_feed = cx18_dvb_stop_feed;
dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
ret = dvb_dmx_init(dvbdemux);
if (ret < 0)
goto err_dvb_unregister_adapter;
dmx = &dvbdemux->dmx;
dvb->hw_frontend.source = DMX_FRONTEND_0;
dvb->mem_frontend.source = DMX_MEMORY_FE;
dvb->dmxdev.filternum = 256;
dvb->dmxdev.demux = dmx;
ret = dvb_dmxdev_init(&dvb->dmxdev, dvb_adapter);
if (ret < 0)
goto err_dvb_dmx_release;
ret = dmx->add_frontend(dmx, &dvb->hw_frontend);
if (ret < 0)
goto err_dvb_dmxdev_release;
ret = dmx->add_frontend(dmx, &dvb->mem_frontend);
if (ret < 0)
goto err_remove_hw_frontend;
ret = dmx->connect_frontend(dmx, &dvb->hw_frontend);
if (ret < 0)
goto err_remove_mem_frontend;
ret = dvb_register(stream);
if (ret < 0)
goto err_disconnect_frontend;
dvb_net_init(dvb_adapter, &dvb->dvbnet, dmx);
CX18_INFO("DVB Frontend registered\n");
CX18_INFO("Registered DVB adapter%d for %s (%d x %d.%02d kB)\n",
stream->dvb->dvb_adapter.num, stream->name,
stream->buffers, stream->buf_size/1024,
(stream->buf_size * 100 / 1024) % 100);
mutex_init(&dvb->feedlock);
dvb->enabled = 1;
return ret;
err_disconnect_frontend:
dmx->disconnect_frontend(dmx);
err_remove_mem_frontend:
dmx->remove_frontend(dmx, &dvb->mem_frontend);
err_remove_hw_frontend:
dmx->remove_frontend(dmx, &dvb->hw_frontend);
err_dvb_dmxdev_release:
dvb_dmxdev_release(&dvb->dmxdev);
err_dvb_dmx_release:
dvb_dmx_release(dvbdemux);
err_dvb_unregister_adapter:
dvb_unregister_adapter(dvb_adapter);
err_out:
return ret;
}
void cx18_dvb_unregister(struct cx18_stream *stream)
{
struct cx18 *cx = stream->cx;
struct cx18_dvb *dvb = stream->dvb;
struct dvb_adapter *dvb_adapter;
struct dvb_demux *dvbdemux;
struct dmx_demux *dmx;
CX18_INFO("unregister DVB\n");
if (dvb == NULL || !dvb->enabled)
return;
dvb_adapter = &dvb->dvb_adapter;
dvbdemux = &dvb->demux;
dmx = &dvbdemux->dmx;
dmx->close(dmx);
dvb_net_release(&dvb->dvbnet);
dmx->remove_frontend(dmx, &dvb->mem_frontend);
dmx->remove_frontend(dmx, &dvb->hw_frontend);
dvb_dmxdev_release(&dvb->dmxdev);
dvb_dmx_release(dvbdemux);
dvb_unregister_frontend(dvb->fe);
dvb_frontend_detach(dvb->fe);
dvb_unregister_adapter(dvb_adapter);
}
/* All the DVB attach calls go here, this function gets modified
* for each new card. cx18_dvb_start_feed() will also need changes.
*/
static int dvb_register(struct cx18_stream *stream)
{
struct cx18_dvb *dvb = stream->dvb;
struct cx18 *cx = stream->cx;
int ret = 0;
switch (cx->card->type) {
case CX18_CARD_HVR_1600_ESMT:
case CX18_CARD_HVR_1600_SAMSUNG:
dvb->fe = dvb_attach(s5h1409_attach,
&hauppauge_hvr1600_config,
&cx->i2c_adap[0]);
if (dvb->fe != NULL) {
dvb_attach(mxl5005s_attach, dvb->fe,
&cx->i2c_adap[0],
&hauppauge_hvr1600_tuner);
ret = 0;
}
break;
case CX18_CARD_HVR_1600_S5H1411:
dvb->fe = dvb_attach(s5h1411_attach,
&hcw_s5h1411_config,
&cx->i2c_adap[0]);
if (dvb->fe != NULL)
dvb_attach(tda18271_attach, dvb->fe,
0x60, &cx->i2c_adap[0],
&hauppauge_tda18271_config);
break;
case CX18_CARD_LEADTEK_DVR3100H:
dvb->fe = dvb_attach(zl10353_attach,
&leadtek_dvr3100h_demod,
&cx->i2c_adap[1]);
if (dvb->fe != NULL) {
struct dvb_frontend *fe;
struct xc2028_config cfg = {
.i2c_adap = &cx->i2c_adap[1],
.i2c_addr = 0xc2 >> 1,
.ctrl = NULL,
};
static struct xc2028_ctrl ctrl = {
.fname = XC2028_DEFAULT_FIRMWARE,
.max_len = 64,
.demod = XC3028_FE_ZARLINK456,
.type = XC2028_AUTO,
};
fe = dvb_attach(xc2028_attach, dvb->fe, &cfg);
if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
fe->ops.tuner_ops.set_config(fe, &ctrl);
}
break;
case CX18_CARD_YUAN_MPC718:
/*
* TODO
* Apparently, these cards also could instead have a
* DiBcom demod supported by one of the db7000 drivers
*/
dvb->fe = dvb_attach(mt352_attach,
&yuan_mpc718_mt352_demod,
&cx->i2c_adap[1]);
if (dvb->fe == NULL)
dvb->fe = dvb_attach(zl10353_attach,
&yuan_mpc718_zl10353_demod,
&cx->i2c_adap[1]);
if (dvb->fe != NULL) {
struct dvb_frontend *fe;
struct xc2028_config cfg = {
.i2c_adap = &cx->i2c_adap[1],
.i2c_addr = 0xc2 >> 1,
.ctrl = NULL,
};
static struct xc2028_ctrl ctrl = {
.fname = XC2028_DEFAULT_FIRMWARE,
.max_len = 64,
.demod = XC3028_FE_ZARLINK456,
.type = XC2028_AUTO,
};
fe = dvb_attach(xc2028_attach, dvb->fe, &cfg);
if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
fe->ops.tuner_ops.set_config(fe, &ctrl);
}
break;
case CX18_CARD_GOTVIEW_PCI_DVD3:
dvb->fe = dvb_attach(zl10353_attach,
&gotview_dvd3_zl10353_demod,
&cx->i2c_adap[1]);
if (dvb->fe != NULL) {
struct dvb_frontend *fe;
struct xc2028_config cfg = {
.i2c_adap = &cx->i2c_adap[1],
.i2c_addr = 0xc2 >> 1,
.ctrl = NULL,
};
static struct xc2028_ctrl ctrl = {
.fname = XC2028_DEFAULT_FIRMWARE,
.max_len = 64,
.demod = XC3028_FE_ZARLINK456,
.type = XC2028_AUTO,
};
fe = dvb_attach(xc2028_attach, dvb->fe, &cfg);
if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
fe->ops.tuner_ops.set_config(fe, &ctrl);
}
break;
default:
/* No Digital Tv Support */
break;
}
if (dvb->fe == NULL) {
CX18_ERR("frontend initialization failed\n");
return -1;
}
dvb->fe->callback = cx18_reset_tuner_gpio;
ret = dvb_register_frontend(&dvb->dvb_adapter, dvb->fe);
if (ret < 0) {
if (dvb->fe->ops.release)
dvb->fe->ops.release(dvb->fe);
return ret;
}
/*
* The firmware seems to enable the TS DMUX clock
* under various circumstances. However, since we know we
* might use it, let's just turn it on ourselves here.
*/
cx18_write_reg_expect(cx,
(CX18_DMUX_CLK_MASK << 16) | CX18_DMUX_CLK_MASK,
CX18_CLOCK_ENABLE2,
CX18_DMUX_CLK_MASK,
(CX18_DMUX_CLK_MASK << 16) | CX18_DMUX_CLK_MASK);
return ret;
}
MODULE_FIRMWARE(FWFILE);
| linux-master | drivers/media/pci/cx18/cx18-dvb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 interrupt handling
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-irq.h"
#include "cx18-mailbox.h"
#include "cx18-scb.h"
static void xpu_ack(struct cx18 *cx, u32 sw2)
{
if (sw2 & IRQ_CPU_TO_EPU_ACK)
wake_up(&cx->mb_cpu_waitq);
if (sw2 & IRQ_APU_TO_EPU_ACK)
wake_up(&cx->mb_apu_waitq);
}
static void epu_cmd(struct cx18 *cx, u32 sw1)
{
if (sw1 & IRQ_CPU_TO_EPU)
cx18_api_epu_cmd_irq(cx, CPU);
if (sw1 & IRQ_APU_TO_EPU)
cx18_api_epu_cmd_irq(cx, APU);
}
irqreturn_t cx18_irq_handler(int irq, void *dev_id)
{
struct cx18 *cx = dev_id;
u32 sw1, sw2, hw2;
sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & cx->sw1_irq_mask;
sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & cx->sw2_irq_mask;
hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & cx->hw2_irq_mask;
if (sw1)
cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1);
if (sw2)
cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2);
if (hw2)
cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2);
if (sw1 || sw2 || hw2)
CX18_DEBUG_HI_IRQ("received interrupts SW1: %x SW2: %x HW2: %x\n",
sw1, sw2, hw2);
/*
* SW1 responses have to happen first. The sending XPU times out the
* incoming mailboxes on us rather rapidly.
*/
if (sw1)
epu_cmd(cx, sw1);
/* To do: interrupt-based I2C handling
if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) {
}
*/
if (sw2)
xpu_ack(cx, sw2);
return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE;
}
| linux-master | drivers/media/pci/cx18/cx18-irq.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 audio-related functions
*
* Derived from ivtv-audio.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-cards.h"
#include "cx18-audio.h"
#define CX18_AUDIO_ENABLE 0xc72014
#define CX18_AI1_MUX_MASK 0x30
#define CX18_AI1_MUX_I2S1 0x00
#define CX18_AI1_MUX_I2S2 0x10
#define CX18_AI1_MUX_843_I2S 0x20
/* Selects the audio input and output according to the current
settings. */
int cx18_audio_set_io(struct cx18 *cx)
{
const struct cx18_card_audio_input *in;
u32 u, v;
int err;
/* Determine which input to use */
if (test_bit(CX18_F_I_RADIO_USER, &cx->i_flags))
in = &cx->card->radio_input;
else
in = &cx->card->audio_inputs[cx->audio_input];
/* handle muxer chips */
v4l2_subdev_call(cx->sd_extmux, audio, s_routing,
(u32) in->muxer_input, 0, 0);
err = cx18_call_hw_err(cx, cx->card->hw_audio_ctrl,
audio, s_routing, in->audio_input, 0, 0);
if (err)
return err;
/* FIXME - this internal mux should be abstracted to a subdev */
u = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
v = u & ~CX18_AI1_MUX_MASK;
switch (in->audio_input) {
case CX18_AV_AUDIO_SERIAL1:
v |= CX18_AI1_MUX_I2S1;
break;
case CX18_AV_AUDIO_SERIAL2:
v |= CX18_AI1_MUX_I2S2;
break;
default:
v |= CX18_AI1_MUX_843_I2S;
break;
}
if (v == u) {
/* force a toggle of some AI1 MUX control bits */
u &= ~CX18_AI1_MUX_MASK;
switch (in->audio_input) {
case CX18_AV_AUDIO_SERIAL1:
u |= CX18_AI1_MUX_843_I2S;
break;
case CX18_AV_AUDIO_SERIAL2:
u |= CX18_AI1_MUX_843_I2S;
break;
default:
u |= CX18_AI1_MUX_I2S1;
break;
}
cx18_write_reg_expect(cx, u | 0xb00, CX18_AUDIO_ENABLE,
u, CX18_AI1_MUX_MASK);
}
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
v, CX18_AI1_MUX_MASK);
return 0;
}
| linux-master | drivers/media/pci/cx18/cx18-audio.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ALSA PCM device for the
* ALSA interface to cx18 PCM capture streams
*
* Copyright (C) 2009 Andy Walls <[email protected]>
* Copyright (C) 2009 Devin Heitmueller <[email protected]>
*
* Portions of this work were sponsored by ONELAN Limited.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <media/v4l2-device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include "cx18-driver.h"
#include "cx18-queue.h"
#include "cx18-streams.h"
#include "cx18-fileops.h"
#include "cx18-alsa.h"
#include "cx18-alsa-pcm.h"
static unsigned int pcm_debug;
module_param(pcm_debug, int, 0644);
MODULE_PARM_DESC(pcm_debug, "enable debug messages for pcm");
#define dprintk(fmt, arg...) do { \
if (pcm_debug) \
printk(KERN_INFO "cx18-alsa-pcm %s: " fmt, \
__func__, ##arg); \
} while (0)
static const struct snd_pcm_hardware snd_cx18_hw_capture = {
.info = SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
.buffer_bytes_max = 62720 * 8, /* just about the value in usbaudio.c */
.period_bytes_min = 64, /* 12544/2, */
.period_bytes_max = 12544,
.periods_min = 2,
.periods_max = 98, /* 12544, */
};
void cx18_alsa_announce_pcm_data(struct snd_cx18_card *cxsc, u8 *pcm_data,
size_t num_bytes)
{
struct snd_pcm_substream *substream;
struct snd_pcm_runtime *runtime;
unsigned int oldptr;
unsigned int stride;
int period_elapsed = 0;
int length;
dprintk("cx18 alsa announce ptr=%p data=%p num_bytes=%zu\n", cxsc,
pcm_data, num_bytes);
substream = cxsc->capture_pcm_substream;
if (substream == NULL) {
dprintk("substream was NULL\n");
return;
}
runtime = substream->runtime;
if (runtime == NULL) {
dprintk("runtime was NULL\n");
return;
}
stride = runtime->frame_bits >> 3;
if (stride == 0) {
dprintk("stride is zero\n");
return;
}
length = num_bytes / stride;
if (length == 0) {
dprintk("%s: length was zero\n", __func__);
return;
}
if (runtime->dma_area == NULL) {
dprintk("dma area was NULL - ignoring\n");
return;
}
oldptr = cxsc->hwptr_done_capture;
if (oldptr + length >= runtime->buffer_size) {
unsigned int cnt =
runtime->buffer_size - oldptr;
memcpy(runtime->dma_area + oldptr * stride, pcm_data,
cnt * stride);
memcpy(runtime->dma_area, pcm_data + cnt * stride,
length * stride - cnt * stride);
} else {
memcpy(runtime->dma_area + oldptr * stride, pcm_data,
length * stride);
}
snd_pcm_stream_lock(substream);
cxsc->hwptr_done_capture += length;
if (cxsc->hwptr_done_capture >=
runtime->buffer_size)
cxsc->hwptr_done_capture -=
runtime->buffer_size;
cxsc->capture_transfer_done += length;
if (cxsc->capture_transfer_done >=
runtime->period_size) {
cxsc->capture_transfer_done -=
runtime->period_size;
period_elapsed = 1;
}
snd_pcm_stream_unlock(substream);
if (period_elapsed)
snd_pcm_period_elapsed(substream);
}
static int snd_cx18_pcm_capture_open(struct snd_pcm_substream *substream)
{
struct snd_cx18_card *cxsc = snd_pcm_substream_chip(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
struct v4l2_device *v4l2_dev = cxsc->v4l2_dev;
struct cx18 *cx = to_cx18(v4l2_dev);
struct cx18_stream *s;
struct cx18_open_id item;
int ret;
/* Instruct the cx18 to start sending packets */
snd_cx18_lock(cxsc);
s = &cx->streams[CX18_ENC_STREAM_TYPE_PCM];
item.cx = cx;
item.type = s->type;
item.open_id = cx->open_id++;
/* See if the stream is available */
if (cx18_claim_stream(&item, item.type)) {
/* No, it's already in use */
snd_cx18_unlock(cxsc);
return -EBUSY;
}
if (test_bit(CX18_F_S_STREAMOFF, &s->s_flags) ||
test_and_set_bit(CX18_F_S_STREAMING, &s->s_flags)) {
/* We're already streaming. No additional action required */
snd_cx18_unlock(cxsc);
return 0;
}
runtime->hw = snd_cx18_hw_capture;
snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
cxsc->capture_pcm_substream = substream;
runtime->private_data = cx;
cx->pcm_announce_callback = cx18_alsa_announce_pcm_data;
/* Not currently streaming, so start it up */
set_bit(CX18_F_S_STREAMING, &s->s_flags);
ret = cx18_start_v4l2_encode_stream(s);
snd_cx18_unlock(cxsc);
return ret;
}
static int snd_cx18_pcm_capture_close(struct snd_pcm_substream *substream)
{
struct snd_cx18_card *cxsc = snd_pcm_substream_chip(substream);
struct v4l2_device *v4l2_dev = cxsc->v4l2_dev;
struct cx18 *cx = to_cx18(v4l2_dev);
struct cx18_stream *s;
/* Instruct the cx18 to stop sending packets */
snd_cx18_lock(cxsc);
s = &cx->streams[CX18_ENC_STREAM_TYPE_PCM];
cx18_stop_v4l2_encode_stream(s, 0);
clear_bit(CX18_F_S_STREAMING, &s->s_flags);
cx18_release_stream(s);
cx->pcm_announce_callback = NULL;
snd_cx18_unlock(cxsc);
return 0;
}
static int snd_cx18_pcm_prepare(struct snd_pcm_substream *substream)
{
struct snd_cx18_card *cxsc = snd_pcm_substream_chip(substream);
cxsc->hwptr_done_capture = 0;
cxsc->capture_transfer_done = 0;
return 0;
}
static int snd_cx18_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
{
return 0;
}
static
snd_pcm_uframes_t snd_cx18_pcm_pointer(struct snd_pcm_substream *substream)
{
unsigned long flags;
snd_pcm_uframes_t hwptr_done;
struct snd_cx18_card *cxsc = snd_pcm_substream_chip(substream);
spin_lock_irqsave(&cxsc->slock, flags);
hwptr_done = cxsc->hwptr_done_capture;
spin_unlock_irqrestore(&cxsc->slock, flags);
return hwptr_done;
}
static const struct snd_pcm_ops snd_cx18_pcm_capture_ops = {
.open = snd_cx18_pcm_capture_open,
.close = snd_cx18_pcm_capture_close,
.prepare = snd_cx18_pcm_prepare,
.trigger = snd_cx18_pcm_trigger,
.pointer = snd_cx18_pcm_pointer,
};
int snd_cx18_pcm_create(struct snd_cx18_card *cxsc)
{
struct snd_pcm *sp;
struct snd_card *sc = cxsc->sc;
struct v4l2_device *v4l2_dev = cxsc->v4l2_dev;
struct cx18 *cx = to_cx18(v4l2_dev);
int ret;
ret = snd_pcm_new(sc, "CX23418 PCM",
0, /* PCM device 0, the only one for this card */
0, /* 0 playback substreams */
1, /* 1 capture substream */
&sp);
if (ret) {
CX18_ALSA_ERR("%s: snd_cx18_pcm_create() failed with err %d\n",
__func__, ret);
goto err_exit;
}
spin_lock_init(&cxsc->slock);
snd_pcm_set_ops(sp, SNDRV_PCM_STREAM_CAPTURE,
&snd_cx18_pcm_capture_ops);
snd_pcm_set_managed_buffer_all(sp, SNDRV_DMA_TYPE_VMALLOC, NULL, 0, 0);
sp->info_flags = 0;
sp->private_data = cxsc;
strscpy(sp->name, cx->card_name, sizeof(sp->name));
return 0;
err_exit:
return ret;
}
| linux-master | drivers/media/pci/cx18/cx18-alsa-pcm.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 video interface functions
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-video.h"
#include "cx18-cards.h"
void cx18_video_set_io(struct cx18 *cx)
{
int inp = cx->active_input;
v4l2_subdev_call(cx->sd_av, video, s_routing,
cx->card->video_inputs[inp].video_input, 0, 0);
}
| linux-master | drivers/media/pci/cx18/cx18-video.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 firmware functions
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-scb.h"
#include "cx18-irq.h"
#include "cx18-firmware.h"
#include "cx18-cards.h"
#include <linux/firmware.h>
#define CX18_PROC_SOFT_RESET 0xc70010
#define CX18_DDR_SOFT_RESET 0xc70014
#define CX18_CLOCK_SELECT1 0xc71000
#define CX18_CLOCK_SELECT2 0xc71004
#define CX18_HALF_CLOCK_SELECT1 0xc71008
#define CX18_HALF_CLOCK_SELECT2 0xc7100C
#define CX18_CLOCK_POLARITY1 0xc71010
#define CX18_CLOCK_POLARITY2 0xc71014
#define CX18_ADD_DELAY_ENABLE1 0xc71018
#define CX18_ADD_DELAY_ENABLE2 0xc7101C
#define CX18_CLOCK_ENABLE1 0xc71020
#define CX18_CLOCK_ENABLE2 0xc71024
#define CX18_REG_BUS_TIMEOUT_EN 0xc72024
#define CX18_FAST_CLOCK_PLL_INT 0xc78000
#define CX18_FAST_CLOCK_PLL_FRAC 0xc78004
#define CX18_FAST_CLOCK_PLL_POST 0xc78008
#define CX18_FAST_CLOCK_PLL_PRESCALE 0xc7800C
#define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010
#define CX18_SLOW_CLOCK_PLL_INT 0xc78014
#define CX18_SLOW_CLOCK_PLL_FRAC 0xc78018
#define CX18_SLOW_CLOCK_PLL_POST 0xc7801C
#define CX18_MPEG_CLOCK_PLL_INT 0xc78040
#define CX18_MPEG_CLOCK_PLL_FRAC 0xc78044
#define CX18_MPEG_CLOCK_PLL_POST 0xc78048
#define CX18_PLL_POWER_DOWN 0xc78088
#define CX18_SW1_INT_STATUS 0xc73104
#define CX18_SW1_INT_ENABLE_PCI 0xc7311C
#define CX18_SW2_INT_SET 0xc73140
#define CX18_SW2_INT_STATUS 0xc73144
#define CX18_ADEC_CONTROL 0xc78120
#define CX18_DDR_REQUEST_ENABLE 0xc80000
#define CX18_DDR_CHIP_CONFIG 0xc80004
#define CX18_DDR_REFRESH 0xc80008
#define CX18_DDR_TIMING1 0xc8000C
#define CX18_DDR_TIMING2 0xc80010
#define CX18_DDR_POWER_REG 0xc8001C
#define CX18_DDR_TUNE_LANE 0xc80048
#define CX18_DDR_INITIAL_EMRS 0xc80054
#define CX18_DDR_MB_PER_ROW_7 0xc8009C
#define CX18_DDR_BASE_63_ADDR 0xc804FC
#define CX18_WMB_CLIENT02 0xc90108
#define CX18_WMB_CLIENT05 0xc90114
#define CX18_WMB_CLIENT06 0xc90118
#define CX18_WMB_CLIENT07 0xc9011C
#define CX18_WMB_CLIENT08 0xc90120
#define CX18_WMB_CLIENT09 0xc90124
#define CX18_WMB_CLIENT10 0xc90128
#define CX18_WMB_CLIENT11 0xc9012C
#define CX18_WMB_CLIENT12 0xc90130
#define CX18_WMB_CLIENT13 0xc90134
#define CX18_WMB_CLIENT14 0xc90138
#define CX18_DSP0_INTERRUPT_MASK 0xd0004C
#define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */
#define APU_ROM_SYNC2 0x72646548 /* "rdeH" */
struct cx18_apu_rom_seghdr {
u32 sync1;
u32 sync2;
u32 addr;
u32 size;
};
static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx)
{
const struct firmware *fw = NULL;
int i, j;
unsigned size;
u32 __iomem *dst = (u32 __iomem *)mem;
const u32 *src;
if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {
CX18_ERR("Unable to open firmware %s\n", fn);
CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n");
return -ENOMEM;
}
src = (const u32 *)fw->data;
for (i = 0; i < fw->size; i += 4096) {
cx18_setup_page(cx, i);
for (j = i; j < fw->size && j < i + 4096; j += 4) {
/* no need for endianness conversion on the ppc */
cx18_raw_writel(cx, *src, dst);
if (cx18_raw_readl(cx, dst) != *src) {
CX18_ERR("Mismatch at offset %x\n", i);
release_firmware(fw);
cx18_setup_page(cx, 0);
return -EIO;
}
dst++;
src++;
}
}
if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
CX18_INFO("loaded %s firmware (%zu bytes)\n", fn, fw->size);
size = fw->size;
release_firmware(fw);
cx18_setup_page(cx, SCB_OFFSET);
return size;
}
static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx,
u32 *entry_addr)
{
const struct firmware *fw = NULL;
int i, j;
unsigned size;
const u32 *src;
struct cx18_apu_rom_seghdr seghdr;
const u8 *vers;
u32 offset = 0;
u32 apu_version = 0;
int sz;
if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {
CX18_ERR("unable to open firmware %s\n", fn);
CX18_ERR("did you put the firmware in the hotplug firmware directory?\n");
cx18_setup_page(cx, 0);
return -ENOMEM;
}
*entry_addr = 0;
src = (const u32 *)fw->data;
vers = fw->data + sizeof(seghdr);
sz = fw->size;
apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
while (offset + sizeof(seghdr) < fw->size) {
const __le32 *shptr = (__force __le32 *)src + offset / 4;
seghdr.sync1 = le32_to_cpu(shptr[0]);
seghdr.sync2 = le32_to_cpu(shptr[1]);
seghdr.addr = le32_to_cpu(shptr[2]);
seghdr.size = le32_to_cpu(shptr[3]);
offset += sizeof(seghdr);
if (seghdr.sync1 != APU_ROM_SYNC1 ||
seghdr.sync2 != APU_ROM_SYNC2) {
offset += seghdr.size;
continue;
}
CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr,
seghdr.addr + seghdr.size - 1);
if (*entry_addr == 0)
*entry_addr = seghdr.addr;
if (offset + seghdr.size > sz)
break;
for (i = 0; i < seghdr.size; i += 4096) {
cx18_setup_page(cx, seghdr.addr + i);
for (j = i; j < seghdr.size && j < i + 4096; j += 4) {
/* no need for endianness conversion on the ppc */
cx18_raw_writel(cx, src[(offset + j) / 4],
dst + seghdr.addr + j);
if (cx18_raw_readl(cx, dst + seghdr.addr + j)
!= src[(offset + j) / 4]) {
CX18_ERR("Mismatch at offset %x\n",
offset + j);
release_firmware(fw);
cx18_setup_page(cx, 0);
return -EIO;
}
}
}
offset += seghdr.size;
}
if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
CX18_INFO("loaded %s firmware V%08x (%zu bytes)\n",
fn, apu_version, fw->size);
size = fw->size;
release_firmware(fw);
cx18_setup_page(cx, 0);
return size;
}
void cx18_halt_firmware(struct cx18 *cx)
{
CX18_DEBUG_INFO("Preparing for firmware halt.\n");
cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
0x0000000F, 0x000F000F);
cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL,
0x00000002, 0x00020002);
}
void cx18_init_power(struct cx18 *cx, int lowpwr)
{
/* power-down Spare and AOM PLLs */
/* power-up fast, slow and mpeg PLLs */
cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);
/* ADEC out of sleep */
cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL,
0x00000000, 0x00020002);
/*
* The PLL parameters are based on the external crystal frequency that
* would ideally be:
*
* NTSC Color subcarrier freq * 8 =
* 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
*
* The accidents of history and rationale that explain from where this
* combination of magic numbers originate can be found in:
*
* [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in
* the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80
*
* [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the
* NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83
*
* As Mike Bradley has rightly pointed out, it's not the exact crystal
* frequency that matters, only that all parts of the driver and
* firmware are using the same value (close to the ideal value).
*
* Since I have a strong suspicion that, if the firmware ever assumes a
* crystal value at all, it will assume 28.636360 MHz, the crystal
* freq used in calculations in this driver will be:
*
* xtal_freq = 28.636360 MHz
*
* an error of less than 0.13 ppm which is way, way better than any off
* the shelf crystal will have for accuracy anyway.
*
* Below I aim to run the PLLs' VCOs near 400 MHz to minimize errors.
*
* Many thanks to Jeff Campbell and Mike Bradley for their extensive
* investigation, experimentation, testing, and suggested solutions of
* audio/video sync problems with SVideo and CVBS captures.
*/
/* the fast clock is at 200/245 MHz */
/* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/
/* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/
cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
CX18_FAST_CLOCK_PLL_FRAC);
cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST);
cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE);
cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
/* set slow clock to 125/120 MHz */
/* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */
/* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */
cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT);
cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F,
CX18_SLOW_CLOCK_PLL_FRAC);
cx18_write_reg(cx, 3, CX18_SLOW_CLOCK_PLL_POST);
/* mpeg clock pll 54MHz */
/* xtal_freq * 0xf.15f17f0 / 8 = 54 MHz: 432 MHz before post-divide */
cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC);
cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
/* Defaults */
/* APU = SC or SC/2 = 125/62.5 */
/* EPU = SC = 125 */
/* DDR = FC = 180 */
/* ENC = SC = 125 */
/* AI1 = SC = 125 */
/* VIM2 = disabled */
/* PCI = FC/2 = 90 */
/* AI2 = disabled */
/* DEMUX = disabled */
/* AO = SC/2 = 62.5 */
/* SER = 54MHz */
/* VFC = disabled */
/* USB = disabled */
if (lowpwr) {
cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1,
0x00000020, 0xFFFFFFFF);
cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2,
0x00000004, 0xFFFFFFFF);
} else {
/* This doesn't explicitly set every clock select */
cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1,
0x00000004, 0x00060006);
cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2,
0x00000006, 0x00060006);
}
cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1,
0x00000002, 0xFFFFFFFF);
cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2,
0x00000104, 0xFFFFFFFF);
cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1,
0x00009026, 0xFFFFFFFF);
cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2,
0x00003105, 0xFFFFFFFF);
}
void cx18_init_memory(struct cx18 *cx)
{
cx18_msleep_timeout(10, 0);
cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET,
0x00000000, 0x00010001);
cx18_msleep_timeout(10, 0);
cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
cx18_msleep_timeout(10, 0);
cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);
cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);
cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);
cx18_msleep_timeout(10, 0);
/* Initialize DQS pad time */
cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
cx18_msleep_timeout(10, 0);
cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET,
0x00000000, 0x00020002);
cx18_msleep_timeout(10, 0);
/* use power-down mode when idle */
cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);
cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN,
0x00000001, 0x00010001);
cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);
cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02); /* AO */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09); /* AI2 */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05); /* VIM1 */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06); /* AI1 */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07); /* 3D comb */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10); /* ME */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12); /* ENC */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13); /* PK */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11); /* RC */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14); /* AVO */
}
#define CX18_CPU_FIRMWARE "v4l-cx23418-cpu.fw"
#define CX18_APU_FIRMWARE "v4l-cx23418-apu.fw"
int cx18_firmware_init(struct cx18 *cx)
{
u32 fw_entry_addr;
int sz, retries;
u32 api_args[MAX_MB_ARGUMENTS];
/* Allow chip to control CLKRUN */
cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);
/* Stop the firmware */
cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
0x0000000F, 0x000F000F);
cx18_msleep_timeout(1, 0);
/* If the CPU is still running */
if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) == 0) {
CX18_ERR("%s: couldn't stop CPU to load firmware\n", __func__);
return -EIO;
}
cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
sz = load_cpu_fw_direct(CX18_CPU_FIRMWARE, cx->enc_mem, cx);
if (sz <= 0)
return sz;
/* The SCB & IPC area *must* be correct before starting the firmwares */
cx18_init_scb(cx);
fw_entry_addr = 0;
sz = load_apu_fw_direct(CX18_APU_FIRMWARE, cx->enc_mem, cx,
&fw_entry_addr);
if (sz <= 0)
return sz;
/* Start the CPU. The CPU will take care of the APU for us. */
cx18_write_reg_expect(cx, 0x00080000, CX18_PROC_SOFT_RESET,
0x00000000, 0x00080008);
/* Wait up to 500 ms for the APU to come out of reset */
for (retries = 0;
retries < 50 && (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1;
retries++)
cx18_msleep_timeout(10, 0);
cx18_msleep_timeout(200, 0);
if (retries == 50 &&
(cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1) {
CX18_ERR("Could not start the CPU\n");
return -EIO;
}
/*
* The CPU had once before set up to receive an interrupt for it's
* outgoing IRQ_CPU_TO_EPU_ACK to us. If it ever does this, we get an
* interrupt when it sends us an ack, but by the time we process it,
* that flag in the SW2 status register has been cleared by the CPU
* firmware. We'll prevent that not so useful condition from happening
* by clearing the CPU's interrupt enables for Ack IRQ's we want to
* process.
*/
cx18_sw2_irq_disable_cpu(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
/* Try a benign command to see if the CPU is alive and well */
sz = cx18_vapi_result(cx, api_args, CX18_CPU_DEBUG_PEEK32, 1, 0);
if (sz < 0)
return sz;
/* initialize GPIO */
cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400);
return 0;
}
MODULE_FIRMWARE(CX18_CPU_FIRMWARE);
MODULE_FIRMWARE(CX18_APU_FIRMWARE);
| linux-master | drivers/media/pci/cx18/cx18-firmware.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 driver PCI memory mapped IO access routines
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-irq.h"
void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
{
u8 __iomem *dst = addr;
u16 val2 = val | (val << 8);
u32 val4 = val2 | (val2 << 16);
/* Align writes on the CX23418's addresses */
if ((count > 0) && ((unsigned long)dst & 1)) {
cx18_writeb(cx, (u8) val, dst);
count--;
dst++;
}
if ((count > 1) && ((unsigned long)dst & 2)) {
cx18_writew(cx, val2, dst);
count -= 2;
dst += 2;
}
while (count > 3) {
cx18_writel(cx, val4, dst);
count -= 4;
dst += 4;
}
if (count > 1) {
cx18_writew(cx, val2, dst);
count -= 2;
dst += 2;
}
if (count > 0)
cx18_writeb(cx, (u8) val, dst);
}
void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
{
cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
}
void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
{
cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
}
void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
{
cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
}
void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
{
cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
}
void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
{
u32 r;
r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
}
void cx18_setup_page(struct cx18 *cx, u32 addr)
{
u32 val;
val = cx18_read_reg(cx, 0xD000F8);
val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
cx18_write_reg(cx, val, 0xD000F8);
}
| linux-master | drivers/media/pci/cx18/cx18-io.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 file operation functions
*
* Derived from ivtv-fileops.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-fileops.h"
#include "cx18-i2c.h"
#include "cx18-queue.h"
#include "cx18-vbi.h"
#include "cx18-audio.h"
#include "cx18-mailbox.h"
#include "cx18-scb.h"
#include "cx18-streams.h"
#include "cx18-controls.h"
#include "cx18-ioctl.h"
#include "cx18-cards.h"
#include <media/v4l2-event.h>
/* This function tries to claim the stream for a specific file descriptor.
If no one else is using this stream then the stream is claimed and
associated VBI and IDX streams are also automatically claimed.
Possible error returns: -EBUSY if someone else has claimed
the stream or 0 on success. */
int cx18_claim_stream(struct cx18_open_id *id, int type)
{
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[type];
struct cx18_stream *s_assoc;
/* Nothing should ever try to directly claim the IDX stream */
if (type == CX18_ENC_STREAM_TYPE_IDX) {
CX18_WARN("MPEG Index stream cannot be claimed directly, but something tried.\n");
return -EINVAL;
}
if (test_and_set_bit(CX18_F_S_CLAIMED, &s->s_flags)) {
/* someone already claimed this stream */
if (s->id == id->open_id) {
/* yes, this file descriptor did. So that's OK. */
return 0;
}
if (s->id == -1 && type == CX18_ENC_STREAM_TYPE_VBI) {
/* VBI is handled already internally, now also assign
the file descriptor to this stream for external
reading of the stream. */
s->id = id->open_id;
CX18_DEBUG_INFO("Start Read VBI\n");
return 0;
}
/* someone else is using this stream already */
CX18_DEBUG_INFO("Stream %d is busy\n", type);
return -EBUSY;
}
s->id = id->open_id;
/*
* CX18_ENC_STREAM_TYPE_MPG needs to claim:
* CX18_ENC_STREAM_TYPE_VBI, if VBI insertion is on for sliced VBI, or
* CX18_ENC_STREAM_TYPE_IDX, if VBI insertion is off for sliced VBI
* (We don't yet fix up MPEG Index entries for our inserted packets).
*
* For all other streams we're done.
*/
if (type != CX18_ENC_STREAM_TYPE_MPG)
return 0;
s_assoc = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
if (cx->vbi.insert_mpeg && !cx18_raw_vbi(cx))
s_assoc = &cx->streams[CX18_ENC_STREAM_TYPE_VBI];
else if (!cx18_stream_enabled(s_assoc))
return 0;
set_bit(CX18_F_S_CLAIMED, &s_assoc->s_flags);
/* mark that it is used internally */
set_bit(CX18_F_S_INTERNAL_USE, &s_assoc->s_flags);
return 0;
}
EXPORT_SYMBOL(cx18_claim_stream);
/* This function releases a previously claimed stream. It will take into
account associated VBI streams. */
void cx18_release_stream(struct cx18_stream *s)
{
struct cx18 *cx = s->cx;
struct cx18_stream *s_assoc;
s->id = -1;
if (s->type == CX18_ENC_STREAM_TYPE_IDX) {
/*
* The IDX stream is only used internally, and can
* only be indirectly unclaimed by unclaiming the MPG stream.
*/
return;
}
if (s->type == CX18_ENC_STREAM_TYPE_VBI &&
test_bit(CX18_F_S_INTERNAL_USE, &s->s_flags)) {
/* this stream is still in use internally */
return;
}
if (!test_and_clear_bit(CX18_F_S_CLAIMED, &s->s_flags)) {
CX18_DEBUG_WARN("Release stream %s not in use!\n", s->name);
return;
}
cx18_flush_queues(s);
/*
* CX18_ENC_STREAM_TYPE_MPG needs to release the
* CX18_ENC_STREAM_TYPE_VBI and/or CX18_ENC_STREAM_TYPE_IDX streams.
*
* For all other streams we're done.
*/
if (s->type != CX18_ENC_STREAM_TYPE_MPG)
return;
/* Unclaim the associated MPEG Index stream */
s_assoc = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
if (test_and_clear_bit(CX18_F_S_INTERNAL_USE, &s_assoc->s_flags)) {
clear_bit(CX18_F_S_CLAIMED, &s_assoc->s_flags);
cx18_flush_queues(s_assoc);
}
/* Unclaim the associated VBI stream */
s_assoc = &cx->streams[CX18_ENC_STREAM_TYPE_VBI];
if (test_and_clear_bit(CX18_F_S_INTERNAL_USE, &s_assoc->s_flags)) {
if (s_assoc->id == -1) {
/*
* The VBI stream is not still claimed by a file
* descriptor, so completely unclaim it.
*/
clear_bit(CX18_F_S_CLAIMED, &s_assoc->s_flags);
cx18_flush_queues(s_assoc);
}
}
}
EXPORT_SYMBOL(cx18_release_stream);
static void cx18_dualwatch(struct cx18 *cx)
{
struct v4l2_tuner vt;
u32 new_stereo_mode;
const u32 dual = 0x0200;
new_stereo_mode = v4l2_ctrl_g_ctrl(cx->cxhdl.audio_mode);
memset(&vt, 0, sizeof(vt));
cx18_call_all(cx, tuner, g_tuner, &vt);
if (vt.audmode == V4L2_TUNER_MODE_LANG1_LANG2 &&
(vt.rxsubchans & V4L2_TUNER_SUB_LANG2))
new_stereo_mode = dual;
if (new_stereo_mode == cx->dualwatch_stereo_mode)
return;
CX18_DEBUG_INFO("dualwatch: change stereo flag from 0x%x to 0x%x.\n",
cx->dualwatch_stereo_mode, new_stereo_mode);
if (v4l2_ctrl_s_ctrl(cx->cxhdl.audio_mode, new_stereo_mode))
CX18_DEBUG_INFO("dualwatch: changing stereo flag failed\n");
}
static struct cx18_mdl *cx18_get_mdl(struct cx18_stream *s, int non_block,
int *err)
{
struct cx18 *cx = s->cx;
struct cx18_stream *s_vbi = &cx->streams[CX18_ENC_STREAM_TYPE_VBI];
struct cx18_mdl *mdl;
DEFINE_WAIT(wait);
*err = 0;
while (1) {
if (s->type == CX18_ENC_STREAM_TYPE_MPG) {
/* Process pending program updates and VBI data */
if (time_after(jiffies, cx->dualwatch_jiffies + msecs_to_jiffies(1000))) {
cx->dualwatch_jiffies = jiffies;
cx18_dualwatch(cx);
}
if (test_bit(CX18_F_S_INTERNAL_USE, &s_vbi->s_flags) &&
!test_bit(CX18_F_S_APPL_IO, &s_vbi->s_flags)) {
while ((mdl = cx18_dequeue(s_vbi,
&s_vbi->q_full))) {
/* byteswap and process VBI data */
cx18_process_vbi_data(cx, mdl,
s_vbi->type);
cx18_stream_put_mdl_fw(s_vbi, mdl);
}
}
mdl = &cx->vbi.sliced_mpeg_mdl;
if (mdl->readpos != mdl->bytesused)
return mdl;
}
/* do we have new data? */
mdl = cx18_dequeue(s, &s->q_full);
if (mdl) {
if (!test_and_clear_bit(CX18_F_M_NEED_SWAP,
&mdl->m_flags))
return mdl;
if (s->type == CX18_ENC_STREAM_TYPE_MPG)
/* byteswap MPG data */
cx18_mdl_swap(mdl);
else {
/* byteswap and process VBI data */
cx18_process_vbi_data(cx, mdl, s->type);
}
return mdl;
}
/* return if end of stream */
if (!test_bit(CX18_F_S_STREAMING, &s->s_flags)) {
CX18_DEBUG_INFO("EOS %s\n", s->name);
return NULL;
}
/* return if file was opened with O_NONBLOCK */
if (non_block) {
*err = -EAGAIN;
return NULL;
}
/* wait for more data to arrive */
prepare_to_wait(&s->waitq, &wait, TASK_INTERRUPTIBLE);
/* New buffers might have become available before we were added
to the waitqueue */
if (!atomic_read(&s->q_full.depth))
schedule();
finish_wait(&s->waitq, &wait);
if (signal_pending(current)) {
/* return if a signal was received */
CX18_DEBUG_INFO("User stopped %s\n", s->name);
*err = -EINTR;
return NULL;
}
}
}
static void cx18_setup_sliced_vbi_mdl(struct cx18 *cx)
{
struct cx18_mdl *mdl = &cx->vbi.sliced_mpeg_mdl;
struct cx18_buffer *buf = &cx->vbi.sliced_mpeg_buf;
int idx = cx->vbi.inserted_frame % CX18_VBI_FRAMES;
buf->buf = cx->vbi.sliced_mpeg_data[idx];
buf->bytesused = cx->vbi.sliced_mpeg_size[idx];
buf->readpos = 0;
mdl->curr_buf = NULL;
mdl->bytesused = cx->vbi.sliced_mpeg_size[idx];
mdl->readpos = 0;
}
static size_t cx18_copy_buf_to_user(struct cx18_stream *s,
struct cx18_buffer *buf, char __user *ubuf, size_t ucount, bool *stop)
{
struct cx18 *cx = s->cx;
size_t len = buf->bytesused - buf->readpos;
*stop = false;
if (len > ucount)
len = ucount;
if (cx->vbi.insert_mpeg && s->type == CX18_ENC_STREAM_TYPE_MPG &&
!cx18_raw_vbi(cx) && buf != &cx->vbi.sliced_mpeg_buf) {
/*
* Try to find a good splice point in the PS, just before
* an MPEG-2 Program Pack start code, and provide only
* up to that point to the user, so it's easy to insert VBI data
* the next time around.
*
* This will not work for an MPEG-2 TS and has only been
* verified by analysis to work for an MPEG-2 PS. Helen Buus
* pointed out this works for the CX23416 MPEG-2 DVD compatible
* stream, and research indicates both the MPEG 2 SVCD and DVD
* stream types use an MPEG-2 PS container.
*/
/*
* An MPEG-2 Program Stream (PS) is a series of
* MPEG-2 Program Packs terminated by an
* MPEG Program End Code after the last Program Pack.
* A Program Pack may hold a PS System Header packet and any
* number of Program Elementary Stream (PES) Packets
*/
const char *start = buf->buf + buf->readpos;
const char *p = start + 1;
const u8 *q;
u8 ch = cx->search_pack_header ? 0xba : 0xe0;
int stuffing, i;
while (start + len > p) {
/* Scan for a 0 to find a potential MPEG-2 start code */
q = memchr(p, 0, start + len - p);
if (q == NULL)
break;
p = q + 1;
/*
* Keep looking if not a
* MPEG-2 Pack header start code: 0x00 0x00 0x01 0xba
* or MPEG-2 video PES start code: 0x00 0x00 0x01 0xe0
*/
if ((char *)q + 15 >= buf->buf + buf->bytesused ||
q[1] != 0 || q[2] != 1 || q[3] != ch)
continue;
/* If expecting the primary video PES */
if (!cx->search_pack_header) {
/* Continue if it couldn't be a PES packet */
if ((q[6] & 0xc0) != 0x80)
continue;
/* Check if a PTS or PTS & DTS follow */
if (((q[7] & 0xc0) == 0x80 && /* PTS only */
(q[9] & 0xf0) == 0x20) || /* PTS only */
((q[7] & 0xc0) == 0xc0 && /* PTS & DTS */
(q[9] & 0xf0) == 0x30)) { /* DTS follows */
/* Assume we found the video PES hdr */
ch = 0xba; /* next want a Program Pack*/
cx->search_pack_header = 1;
p = q + 9; /* Skip this video PES hdr */
}
continue;
}
/* We may have found a Program Pack start code */
/* Get the count of stuffing bytes & verify them */
stuffing = q[13] & 7;
/* all stuffing bytes must be 0xff */
for (i = 0; i < stuffing; i++)
if (q[14 + i] != 0xff)
break;
if (i == stuffing && /* right number of stuffing bytes*/
(q[4] & 0xc4) == 0x44 && /* marker check */
(q[12] & 3) == 3 && /* marker check */
q[14 + stuffing] == 0 && /* PES Pack or Sys Hdr */
q[15 + stuffing] == 0 &&
q[16 + stuffing] == 1) {
/* We declare we actually found a Program Pack*/
cx->search_pack_header = 0; /* expect vid PES */
len = (char *)q - start;
cx18_setup_sliced_vbi_mdl(cx);
*stop = true;
break;
}
}
}
if (copy_to_user(ubuf, (u8 *)buf->buf + buf->readpos, len)) {
CX18_DEBUG_WARN("copy %zd bytes to user failed for %s\n",
len, s->name);
return -EFAULT;
}
buf->readpos += len;
if (s->type == CX18_ENC_STREAM_TYPE_MPG &&
buf != &cx->vbi.sliced_mpeg_buf)
cx->mpg_data_received += len;
return len;
}
static size_t cx18_copy_mdl_to_user(struct cx18_stream *s,
struct cx18_mdl *mdl, char __user *ubuf, size_t ucount)
{
size_t tot_written = 0;
int rc;
bool stop = false;
if (mdl->curr_buf == NULL)
mdl->curr_buf = list_first_entry(&mdl->buf_list,
struct cx18_buffer, list);
if (list_entry_is_past_end(mdl->curr_buf, &mdl->buf_list, list)) {
/*
* For some reason we've exhausted the buffers, but the MDL
* object still said some data was unread.
* Fix that and bail out.
*/
mdl->readpos = mdl->bytesused;
return 0;
}
list_for_each_entry_from(mdl->curr_buf, &mdl->buf_list, list) {
if (mdl->curr_buf->readpos >= mdl->curr_buf->bytesused)
continue;
rc = cx18_copy_buf_to_user(s, mdl->curr_buf, ubuf + tot_written,
ucount - tot_written, &stop);
if (rc < 0)
return rc;
mdl->readpos += rc;
tot_written += rc;
if (stop || /* Forced stopping point for VBI insertion */
tot_written >= ucount || /* Reader request satisfied */
mdl->curr_buf->readpos < mdl->curr_buf->bytesused ||
mdl->readpos >= mdl->bytesused) /* MDL buffers drained */
break;
}
return tot_written;
}
static ssize_t cx18_read(struct cx18_stream *s, char __user *ubuf,
size_t tot_count, int non_block)
{
struct cx18 *cx = s->cx;
size_t tot_written = 0;
int single_frame = 0;
if (atomic_read(&cx->ana_capturing) == 0 && s->id == -1) {
/* shouldn't happen */
CX18_DEBUG_WARN("Stream %s not initialized before read\n",
s->name);
return -EIO;
}
/* Each VBI buffer is one frame, the v4l2 API says that for VBI the
frames should arrive one-by-one, so make sure we never output more
than one VBI frame at a time */
if (s->type == CX18_ENC_STREAM_TYPE_VBI && !cx18_raw_vbi(cx))
single_frame = 1;
for (;;) {
struct cx18_mdl *mdl;
int rc;
mdl = cx18_get_mdl(s, non_block, &rc);
/* if there is no data available... */
if (mdl == NULL) {
/* if we got data, then return that regardless */
if (tot_written)
break;
/* EOS condition */
if (rc == 0) {
clear_bit(CX18_F_S_STREAMOFF, &s->s_flags);
clear_bit(CX18_F_S_APPL_IO, &s->s_flags);
cx18_release_stream(s);
}
/* set errno */
return rc;
}
rc = cx18_copy_mdl_to_user(s, mdl, ubuf + tot_written,
tot_count - tot_written);
if (mdl != &cx->vbi.sliced_mpeg_mdl) {
if (mdl->readpos == mdl->bytesused)
cx18_stream_put_mdl_fw(s, mdl);
else
cx18_push(s, mdl, &s->q_full);
} else if (mdl->readpos == mdl->bytesused) {
int idx = cx->vbi.inserted_frame % CX18_VBI_FRAMES;
cx->vbi.sliced_mpeg_size[idx] = 0;
cx->vbi.inserted_frame++;
cx->vbi_data_inserted += mdl->bytesused;
}
if (rc < 0)
return rc;
tot_written += rc;
if (tot_written == tot_count || single_frame)
break;
}
return tot_written;
}
static ssize_t cx18_read_pos(struct cx18_stream *s, char __user *ubuf,
size_t count, loff_t *pos, int non_block)
{
ssize_t rc = count ? cx18_read(s, ubuf, count, non_block) : 0;
struct cx18 *cx = s->cx;
CX18_DEBUG_HI_FILE("read %zd from %s, got %zd\n", count, s->name, rc);
if (rc > 0)
*pos += rc;
return rc;
}
int cx18_start_capture(struct cx18_open_id *id)
{
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[id->type];
struct cx18_stream *s_vbi;
struct cx18_stream *s_idx;
if (s->type == CX18_ENC_STREAM_TYPE_RAD) {
/* you cannot read from these stream types. */
return -EPERM;
}
/* Try to claim this stream. */
if (cx18_claim_stream(id, s->type))
return -EBUSY;
/* If capture is already in progress, then we also have to
do nothing extra. */
if (test_bit(CX18_F_S_STREAMOFF, &s->s_flags) ||
test_and_set_bit(CX18_F_S_STREAMING, &s->s_flags)) {
set_bit(CX18_F_S_APPL_IO, &s->s_flags);
return 0;
}
/* Start associated VBI or IDX stream capture if required */
s_vbi = &cx->streams[CX18_ENC_STREAM_TYPE_VBI];
s_idx = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
if (s->type == CX18_ENC_STREAM_TYPE_MPG) {
/*
* The VBI and IDX streams should have been claimed
* automatically, if for internal use, when the MPG stream was
* claimed. We only need to start these streams capturing.
*/
if (test_bit(CX18_F_S_INTERNAL_USE, &s_idx->s_flags) &&
!test_and_set_bit(CX18_F_S_STREAMING, &s_idx->s_flags)) {
if (cx18_start_v4l2_encode_stream(s_idx)) {
CX18_DEBUG_WARN("IDX capture start failed\n");
clear_bit(CX18_F_S_STREAMING, &s_idx->s_flags);
goto start_failed;
}
CX18_DEBUG_INFO("IDX capture started\n");
}
if (test_bit(CX18_F_S_INTERNAL_USE, &s_vbi->s_flags) &&
!test_and_set_bit(CX18_F_S_STREAMING, &s_vbi->s_flags)) {
if (cx18_start_v4l2_encode_stream(s_vbi)) {
CX18_DEBUG_WARN("VBI capture start failed\n");
clear_bit(CX18_F_S_STREAMING, &s_vbi->s_flags);
goto start_failed;
}
CX18_DEBUG_INFO("VBI insertion started\n");
}
}
/* Tell the card to start capturing */
if (!cx18_start_v4l2_encode_stream(s)) {
/* We're done */
set_bit(CX18_F_S_APPL_IO, &s->s_flags);
/* Resume a possibly paused encoder */
if (test_and_clear_bit(CX18_F_I_ENC_PAUSED, &cx->i_flags))
cx18_vapi(cx, CX18_CPU_CAPTURE_PAUSE, 1, s->handle);
return 0;
}
start_failed:
CX18_DEBUG_WARN("Failed to start capturing for stream %s\n", s->name);
/*
* The associated VBI and IDX streams for internal use are released
* automatically when the MPG stream is released. We only need to stop
* the associated stream.
*/
if (s->type == CX18_ENC_STREAM_TYPE_MPG) {
/* Stop the IDX stream which is always for internal use */
if (test_bit(CX18_F_S_STREAMING, &s_idx->s_flags)) {
cx18_stop_v4l2_encode_stream(s_idx, 0);
clear_bit(CX18_F_S_STREAMING, &s_idx->s_flags);
}
/* Stop the VBI stream, if only running for internal use */
if (test_bit(CX18_F_S_STREAMING, &s_vbi->s_flags) &&
!test_bit(CX18_F_S_APPL_IO, &s_vbi->s_flags)) {
cx18_stop_v4l2_encode_stream(s_vbi, 0);
clear_bit(CX18_F_S_STREAMING, &s_vbi->s_flags);
}
}
clear_bit(CX18_F_S_STREAMING, &s->s_flags);
cx18_release_stream(s); /* Also releases associated streams */
return -EIO;
}
ssize_t cx18_v4l2_read(struct file *filp, char __user *buf, size_t count,
loff_t *pos)
{
struct cx18_open_id *id = file2id(filp);
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[id->type];
int rc;
CX18_DEBUG_HI_FILE("read %zd bytes from %s\n", count, s->name);
mutex_lock(&cx->serialize_lock);
rc = cx18_start_capture(id);
mutex_unlock(&cx->serialize_lock);
if (rc)
return rc;
return cx18_read_pos(s, buf, count, pos, filp->f_flags & O_NONBLOCK);
}
__poll_t cx18_v4l2_enc_poll(struct file *filp, poll_table *wait)
{
__poll_t req_events = poll_requested_events(wait);
struct cx18_open_id *id = file2id(filp);
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[id->type];
int eof = test_bit(CX18_F_S_STREAMOFF, &s->s_flags);
__poll_t res = 0;
/* Start a capture if there is none */
if (!eof && !test_bit(CX18_F_S_STREAMING, &s->s_flags) &&
(req_events & (EPOLLIN | EPOLLRDNORM))) {
int rc;
mutex_lock(&cx->serialize_lock);
rc = cx18_start_capture(id);
mutex_unlock(&cx->serialize_lock);
if (rc) {
CX18_DEBUG_INFO("Could not start capture for %s (%d)\n",
s->name, rc);
return EPOLLERR;
}
CX18_DEBUG_FILE("Encoder poll started capture\n");
}
/* add stream's waitq to the poll list */
CX18_DEBUG_HI_FILE("Encoder poll\n");
if (v4l2_event_pending(&id->fh))
res |= EPOLLPRI;
else
poll_wait(filp, &s->waitq, wait);
if (atomic_read(&s->q_full.depth))
return res | EPOLLIN | EPOLLRDNORM;
if (eof)
return res | EPOLLHUP;
return res;
}
void cx18_vb_timeout(struct timer_list *t)
{
struct cx18_stream *s = from_timer(s, t, vb_timeout);
/*
* Return all of the buffers in error state, so the vbi/vid inode
* can return from blocking.
*/
cx18_clear_queue(s, VB2_BUF_STATE_ERROR);
}
void cx18_stop_capture(struct cx18_stream *s, int gop_end)
{
struct cx18 *cx = s->cx;
struct cx18_stream *s_vbi = &cx->streams[CX18_ENC_STREAM_TYPE_VBI];
struct cx18_stream *s_idx = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
CX18_DEBUG_IOCTL("close() of %s\n", s->name);
/* 'Unclaim' this stream */
/* Stop capturing */
if (test_bit(CX18_F_S_STREAMING, &s->s_flags)) {
CX18_DEBUG_INFO("close stopping capture\n");
if (s->type == CX18_ENC_STREAM_TYPE_MPG) {
/* Stop internal use associated VBI and IDX streams */
if (test_bit(CX18_F_S_STREAMING, &s_vbi->s_flags) &&
!test_bit(CX18_F_S_APPL_IO, &s_vbi->s_flags)) {
CX18_DEBUG_INFO("close stopping embedded VBI capture\n");
cx18_stop_v4l2_encode_stream(s_vbi, 0);
}
if (test_bit(CX18_F_S_STREAMING, &s_idx->s_flags)) {
CX18_DEBUG_INFO("close stopping IDX capture\n");
cx18_stop_v4l2_encode_stream(s_idx, 0);
}
}
if (s->type == CX18_ENC_STREAM_TYPE_VBI &&
test_bit(CX18_F_S_INTERNAL_USE, &s->s_flags))
/* Also used internally, don't stop capturing */
s->id = -1;
else
cx18_stop_v4l2_encode_stream(s, gop_end);
}
if (!gop_end) {
clear_bit(CX18_F_S_APPL_IO, &s->s_flags);
clear_bit(CX18_F_S_STREAMOFF, &s->s_flags);
cx18_release_stream(s);
}
}
int cx18_v4l2_close(struct file *filp)
{
struct v4l2_fh *fh = filp->private_data;
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[id->type];
struct video_device *vdev = &s->video_dev;
CX18_DEBUG_IOCTL("close() of %s\n", s->name);
mutex_lock(&cx->serialize_lock);
/* Stop radio */
if (id->type == CX18_ENC_STREAM_TYPE_RAD &&
v4l2_fh_is_singular_file(filp)) {
/* Closing radio device, return to TV mode */
cx18_mute(cx);
/* Mark that the radio is no longer in use */
clear_bit(CX18_F_I_RADIO_USER, &cx->i_flags);
/* Switch tuner to TV */
cx18_call_all(cx, video, s_std, cx->std);
/* Select correct audio input (i.e. TV tuner or Line in) */
cx18_audio_set_io(cx);
if (atomic_read(&cx->ana_capturing) > 0) {
/* Undo video mute */
cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle,
(v4l2_ctrl_g_ctrl(cx->cxhdl.video_mute) |
(v4l2_ctrl_g_ctrl(cx->cxhdl.video_mute_yuv) << 8)));
}
/* Done! Unmute and continue. */
cx18_unmute(cx);
}
if (id->type == CX18_ENC_STREAM_TYPE_YUV &&
filp->private_data == vdev->queue->owner) {
vb2_queue_release(vdev->queue);
vdev->queue->owner = NULL;
}
v4l2_fh_del(fh);
v4l2_fh_exit(fh);
/* 'Unclaim' this stream */
if (id->type != CX18_ENC_STREAM_TYPE_YUV && s->id == id->open_id)
cx18_stop_capture(s, 0);
kfree(id);
mutex_unlock(&cx->serialize_lock);
return 0;
}
static int cx18_serialized_open(struct cx18_stream *s, struct file *filp)
{
struct cx18 *cx = s->cx;
struct cx18_open_id *item;
CX18_DEBUG_FILE("open %s\n", s->name);
/* Allocate memory */
item = kzalloc(sizeof(struct cx18_open_id), GFP_KERNEL);
if (NULL == item) {
CX18_DEBUG_WARN("nomem on v4l2 open\n");
return -ENOMEM;
}
v4l2_fh_init(&item->fh, &s->video_dev);
item->cx = cx;
item->type = s->type;
item->open_id = cx->open_id++;
filp->private_data = &item->fh;
v4l2_fh_add(&item->fh);
if (item->type == CX18_ENC_STREAM_TYPE_RAD &&
v4l2_fh_is_singular_file(filp)) {
if (!test_bit(CX18_F_I_RADIO_USER, &cx->i_flags)) {
if (atomic_read(&cx->ana_capturing) > 0) {
/* switching to radio while capture is
in progress is not polite */
v4l2_fh_del(&item->fh);
v4l2_fh_exit(&item->fh);
kfree(item);
return -EBUSY;
}
}
/* Mark that the radio is being used. */
set_bit(CX18_F_I_RADIO_USER, &cx->i_flags);
/* We have the radio */
cx18_mute(cx);
/* Switch tuner to radio */
cx18_call_all(cx, tuner, s_radio);
/* Select the correct audio input (i.e. radio tuner) */
cx18_audio_set_io(cx);
/* Done! Unmute and continue. */
cx18_unmute(cx);
}
return 0;
}
int cx18_v4l2_open(struct file *filp)
{
int res;
struct video_device *video_dev = video_devdata(filp);
struct cx18_stream *s = video_get_drvdata(video_dev);
struct cx18 *cx = s->cx;
mutex_lock(&cx->serialize_lock);
if (cx18_init_on_first_open(cx)) {
CX18_ERR("Failed to initialize on %s\n",
video_device_node_name(video_dev));
mutex_unlock(&cx->serialize_lock);
return -ENXIO;
}
res = cx18_serialized_open(s, filp);
mutex_unlock(&cx->serialize_lock);
return res;
}
void cx18_mute(struct cx18 *cx)
{
u32 h;
if (atomic_read(&cx->ana_capturing)) {
h = cx18_find_handle(cx);
if (h != CX18_INVALID_TASK_HANDLE)
cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2, h, 1);
else
CX18_ERR("Can't find valid task handle for mute\n");
}
CX18_DEBUG_INFO("Mute\n");
}
void cx18_unmute(struct cx18 *cx)
{
u32 h;
if (atomic_read(&cx->ana_capturing)) {
h = cx18_find_handle(cx);
if (h != CX18_INVALID_TASK_HANDLE) {
cx18_msleep_timeout(100, 0);
cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 2, h, 12);
cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2, h, 0);
} else
CX18_ERR("Can't find valid task handle for unmute\n");
}
CX18_DEBUG_INFO("Unmute\n");
}
| linux-master | drivers/media/pci/cx18/cx18-fileops.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 mailbox functions
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include <linux/bitops.h>
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-scb.h"
#include "cx18-irq.h"
#include "cx18-mailbox.h"
#include "cx18-queue.h"
#include "cx18-streams.h"
#include "cx18-alsa-pcm.h" /* FIXME make configurable */
static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
#define API_FAST (1 << 2) /* Short timeout */
#define API_SLOW (1 << 3) /* Additional 300ms timeout */
struct cx18_api_info {
u32 cmd;
u8 flags; /* Flags, see above */
u8 rpu; /* Processing unit */
const char *name; /* The name of the command */
};
#define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
static const struct cx18_api_info api_info[] = {
/* MPEG encoder API */
API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
API_ENTRY(CPU, CX18_CREATE_TASK, 0),
API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0),
API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0),
API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0),
API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0),
API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0),
API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0),
API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0),
API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0),
API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0),
API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0),
API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0),
API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0),
API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW),
API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0),
API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0),
API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0),
API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0),
API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0),
API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0),
API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0),
API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0),
API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0),
API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0),
API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0),
API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
API_ENTRY(CPU, CX18_CPU_SET_VFC_PARAM, 0),
API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
API_ENTRY(APU, CX18_APU_START, 0),
API_ENTRY(APU, CX18_APU_STOP, 0),
API_ENTRY(APU, CX18_APU_RESETAI, 0),
API_ENTRY(CPU, CX18_CPU_DEBUG_PEEK32, 0),
API_ENTRY(0, 0, 0),
};
static const struct cx18_api_info *find_api_info(u32 cmd)
{
int i;
for (i = 0; api_info[i].cmd; i++)
if (api_info[i].cmd == cmd)
return &api_info[i];
return NULL;
}
/* Call with buf of n*11+1 bytes */
static char *u32arr2hex(u32 data[], int n, char *buf)
{
char *p;
int i;
for (i = 0, p = buf; i < n; i++, p += 11) {
/* kernel snprintf() appends '\0' always */
snprintf(p, 12, " %#010x", data[i]);
}
*p = '\0';
return buf;
}
static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
{
char argstr[MAX_MB_ARGUMENTS*11+1];
if (!(cx18_debug & CX18_DBGFLG_API))
return;
CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s\n",
name, mb->request, mb->ack, mb->cmd, mb->error,
u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr));
}
/*
* Functions that run in a work_queue work handling context
*/
static void cx18_mdl_send_to_dvb(struct cx18_stream *s, struct cx18_mdl *mdl)
{
struct cx18_buffer *buf;
if (s->dvb == NULL || !s->dvb->enabled || mdl->bytesused == 0)
return;
/* We ignore mdl and buf readpos accounting here - it doesn't matter */
/* The likely case */
if (list_is_singular(&mdl->buf_list)) {
buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
list);
if (buf->bytesused)
dvb_dmx_swfilter(&s->dvb->demux,
buf->buf, buf->bytesused);
return;
}
list_for_each_entry(buf, &mdl->buf_list, list) {
if (buf->bytesused == 0)
break;
dvb_dmx_swfilter(&s->dvb->demux, buf->buf, buf->bytesused);
}
}
static void cx18_mdl_send_to_vb2(struct cx18_stream *s, struct cx18_mdl *mdl)
{
struct cx18_vb2_buffer *vb_buf;
struct cx18_buffer *buf;
u8 *p;
u32 offset = 0;
int dispatch = 0;
unsigned long bsize;
if (mdl->bytesused == 0)
return;
/* Acquire a vb2 buffer, clone to and release it */
spin_lock(&s->vb_lock);
if (list_empty(&s->vb_capture))
goto out;
vb_buf = list_first_entry(&s->vb_capture, struct cx18_vb2_buffer,
list);
p = vb2_plane_vaddr(&vb_buf->vb.vb2_buf, 0);
if (!p)
goto out;
bsize = vb2_get_plane_payload(&vb_buf->vb.vb2_buf, 0);
offset = vb_buf->bytes_used;
list_for_each_entry(buf, &mdl->buf_list, list) {
if (buf->bytesused == 0)
break;
if ((offset + buf->bytesused) <= bsize) {
memcpy(p + offset, buf->buf, buf->bytesused);
offset += buf->bytesused;
vb_buf->bytes_used += buf->bytesused;
}
}
/* If we've filled the buffer as per the callers res then dispatch it */
if (vb_buf->bytes_used >= s->vb_bytes_per_frame) {
dispatch = 1;
vb_buf->bytes_used = 0;
}
if (dispatch) {
vb_buf->vb.vb2_buf.timestamp = ktime_get_ns();
vb_buf->vb.sequence = s->sequence++;
list_del(&vb_buf->list);
vb2_buffer_done(&vb_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
mod_timer(&s->vb_timeout, msecs_to_jiffies(2000) + jiffies);
out:
spin_unlock(&s->vb_lock);
}
static void cx18_mdl_send_to_alsa(struct cx18 *cx, struct cx18_stream *s,
struct cx18_mdl *mdl)
{
struct cx18_buffer *buf;
if (mdl->bytesused == 0)
return;
/* We ignore mdl and buf readpos accounting here - it doesn't matter */
/* The likely case */
if (list_is_singular(&mdl->buf_list)) {
buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
list);
if (buf->bytesused)
cx->pcm_announce_callback(cx->alsa, buf->buf,
buf->bytesused);
return;
}
list_for_each_entry(buf, &mdl->buf_list, list) {
if (buf->bytesused == 0)
break;
cx->pcm_announce_callback(cx->alsa, buf->buf, buf->bytesused);
}
}
static void epu_dma_done(struct cx18 *cx, struct cx18_in_work_order *order)
{
u32 handle, mdl_ack_count, id;
struct cx18_mailbox *mb;
struct cx18_mdl_ack *mdl_ack;
struct cx18_stream *s;
struct cx18_mdl *mdl;
int i;
mb = &order->mb;
handle = mb->args[0];
s = cx18_handle_to_stream(cx, handle);
if (s == NULL) {
CX18_WARN("Got DMA done notification for unknown/inactive handle %d, %s mailbox seq no %d\n",
handle,
(order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
"stale" : "good", mb->request);
return;
}
mdl_ack_count = mb->args[2];
mdl_ack = order->mdl_ack;
for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
id = mdl_ack->id;
/*
* Simple integrity check for processing a stale (and possibly
* inconsistent mailbox): make sure the MDL id is in the
* valid range for the stream.
*
* We go through the trouble of dealing with stale mailboxes
* because most of the time, the mailbox data is still valid and
* unchanged (and in practice the firmware ping-pongs the
* two mdl_ack buffers so mdl_acks are not stale).
*
* There are occasions when we get a half changed mailbox,
* which this check catches for a handle & id mismatch. If the
* handle and id do correspond, the worst case is that we
* completely lost the old MDL, but pick up the new MDL
* early (but the new mdl_ack is guaranteed to be good in this
* case as the firmware wouldn't point us to a new mdl_ack until
* it's filled in).
*
* cx18_queue_get_mdl() will detect the lost MDLs
* and send them back to q_free for fw rotation eventually.
*/
if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
!(id >= s->mdl_base_idx &&
id < (s->mdl_base_idx + s->buffers))) {
CX18_WARN("Fell behind! Ignoring stale mailbox with inconsistent data. Lost MDL for mailbox seq no %d\n",
mb->request);
break;
}
mdl = cx18_queue_get_mdl(s, id, mdl_ack->data_used);
CX18_DEBUG_HI_DMA("DMA DONE for %s (MDL %d)\n", s->name, id);
if (mdl == NULL) {
CX18_WARN("Could not find MDL %d for stream %s\n",
id, s->name);
continue;
}
CX18_DEBUG_HI_DMA("%s recv bytesused = %d\n",
s->name, mdl->bytesused);
if (s->type == CX18_ENC_STREAM_TYPE_TS) {
cx18_mdl_send_to_dvb(s, mdl);
cx18_enqueue(s, mdl, &s->q_free);
} else if (s->type == CX18_ENC_STREAM_TYPE_PCM) {
/* Pass the data to cx18-alsa */
if (cx->pcm_announce_callback != NULL) {
cx18_mdl_send_to_alsa(cx, s, mdl);
cx18_enqueue(s, mdl, &s->q_free);
} else {
cx18_enqueue(s, mdl, &s->q_full);
}
} else if (s->type == CX18_ENC_STREAM_TYPE_YUV) {
cx18_mdl_send_to_vb2(s, mdl);
cx18_enqueue(s, mdl, &s->q_free);
} else {
cx18_enqueue(s, mdl, &s->q_full);
if (s->type == CX18_ENC_STREAM_TYPE_IDX)
cx18_stream_rotate_idx_mdls(cx);
}
}
/* Put as many MDLs as possible back into fw use */
cx18_stream_load_fw_queue(s);
wake_up(&cx->dma_waitq);
if (s->id != -1)
wake_up(&s->waitq);
}
static void epu_debug(struct cx18 *cx, struct cx18_in_work_order *order)
{
char *p;
char *str = order->str;
CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
p = strchr(str, '.');
if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
CX18_INFO("FW version: %s\n", p - 1);
}
static void epu_cmd(struct cx18 *cx, struct cx18_in_work_order *order)
{
switch (order->rpu) {
case CPU:
{
switch (order->mb.cmd) {
case CX18_EPU_DMA_DONE:
epu_dma_done(cx, order);
break;
case CX18_EPU_DEBUG:
epu_debug(cx, order);
break;
default:
CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
order->mb.cmd);
break;
}
break;
}
case APU:
CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
order->mb.cmd);
break;
default:
break;
}
}
static
void free_in_work_order(struct cx18 *cx, struct cx18_in_work_order *order)
{
atomic_set(&order->pending, 0);
}
void cx18_in_work_handler(struct work_struct *work)
{
struct cx18_in_work_order *order =
container_of(work, struct cx18_in_work_order, work);
struct cx18 *cx = order->cx;
epu_cmd(cx, order);
free_in_work_order(cx, order);
}
/*
* Functions that run in an interrupt handling context
*/
static void mb_ack_irq(struct cx18 *cx, struct cx18_in_work_order *order)
{
struct cx18_mailbox __iomem *ack_mb;
u32 ack_irq, req;
switch (order->rpu) {
case APU:
ack_irq = IRQ_EPU_TO_APU_ACK;
ack_mb = &cx->scb->apu2epu_mb;
break;
case CPU:
ack_irq = IRQ_EPU_TO_CPU_ACK;
ack_mb = &cx->scb->cpu2epu_mb;
break;
default:
CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
order->rpu, order->mb.cmd);
return;
}
req = order->mb.request;
/* Don't ack if the RPU has gotten impatient and timed us out */
if (req != cx18_readl(cx, &ack_mb->request) ||
req == cx18_readl(cx, &ack_mb->ack)) {
CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our incoming %s to EPU mailbox (sequence no. %u) while processing\n",
rpu_str[order->rpu], rpu_str[order->rpu], req);
order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
return;
}
cx18_writel(cx, req, &ack_mb->ack);
cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
return;
}
static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
{
u32 handle, mdl_ack_offset, mdl_ack_count;
struct cx18_mailbox *mb;
int i;
mb = &order->mb;
handle = mb->args[0];
mdl_ack_offset = mb->args[1];
mdl_ack_count = mb->args[2];
if (handle == CX18_INVALID_TASK_HANDLE ||
mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
mb_ack_irq(cx, order);
return -1;
}
for (i = 0; i < sizeof(struct cx18_mdl_ack) * mdl_ack_count; i += sizeof(u32))
((u32 *)order->mdl_ack)[i / sizeof(u32)] =
cx18_readl(cx, cx->enc_mem + mdl_ack_offset + i);
if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
mb_ack_irq(cx, order);
return 1;
}
static
int epu_debug_irq(struct cx18 *cx, struct cx18_in_work_order *order)
{
u32 str_offset;
char *str = order->str;
str[0] = '\0';
str_offset = order->mb.args[1];
if (str_offset) {
cx18_setup_page(cx, str_offset);
cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
str[252] = '\0';
cx18_setup_page(cx, SCB_OFFSET);
}
if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
mb_ack_irq(cx, order);
return str_offset ? 1 : 0;
}
static inline
int epu_cmd_irq(struct cx18 *cx, struct cx18_in_work_order *order)
{
int ret = -1;
switch (order->rpu) {
case CPU:
{
switch (order->mb.cmd) {
case CX18_EPU_DMA_DONE:
ret = epu_dma_done_irq(cx, order);
break;
case CX18_EPU_DEBUG:
ret = epu_debug_irq(cx, order);
break;
default:
CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
order->mb.cmd);
break;
}
break;
}
case APU:
CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
order->mb.cmd);
break;
default:
break;
}
return ret;
}
static inline
struct cx18_in_work_order *alloc_in_work_order_irq(struct cx18 *cx)
{
int i;
struct cx18_in_work_order *order = NULL;
for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) {
/*
* We only need "pending" atomic to inspect its contents,
* and need not do a check and set because:
* 1. Any work handler thread only clears "pending" and only
* on one, particular work order at a time, per handler thread.
* 2. "pending" is only set here, and we're serialized because
* we're called in an IRQ handler context.
*/
if (atomic_read(&cx->in_work_order[i].pending) == 0) {
order = &cx->in_work_order[i];
atomic_set(&order->pending, 1);
break;
}
}
return order;
}
void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
{
struct cx18_mailbox __iomem *mb;
struct cx18_mailbox *order_mb;
struct cx18_in_work_order *order;
int submit;
int i;
switch (rpu) {
case CPU:
mb = &cx->scb->cpu2epu_mb;
break;
case APU:
mb = &cx->scb->apu2epu_mb;
break;
default:
return;
}
order = alloc_in_work_order_irq(cx);
if (order == NULL) {
CX18_WARN("Unable to find blank work order form to schedule incoming mailbox command processing\n");
return;
}
order->flags = 0;
order->rpu = rpu;
order_mb = &order->mb;
/* mb->cmd and mb->args[0] through mb->args[2] */
for (i = 0; i < 4; i++)
(&order_mb->cmd)[i] = cx18_readl(cx, &mb->cmd + i);
/* mb->request and mb->ack. N.B. we want to read mb->ack last */
for (i = 0; i < 2; i++)
(&order_mb->request)[i] = cx18_readl(cx, &mb->request + i);
if (order_mb->request == order_mb->ack) {
CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our incoming %s to EPU mailbox (sequence no. %u)\n",
rpu_str[rpu], rpu_str[rpu], order_mb->request);
if (cx18_debug & CX18_DBGFLG_WARN)
dump_mb(cx, order_mb, "incoming");
order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
}
/*
* Individual EPU command processing is responsible for ack-ing
* a non-stale mailbox as soon as possible
*/
submit = epu_cmd_irq(cx, order);
if (submit > 0) {
queue_work(cx->in_work_queue, &order->work);
}
}
/*
* Functions called from a non-interrupt, non work_queue context
*/
static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
{
const struct cx18_api_info *info = find_api_info(cmd);
u32 irq, req, ack, err;
struct cx18_mailbox __iomem *mb;
wait_queue_head_t *waitq;
struct mutex *mb_lock;
unsigned long int t0, timeout, ret;
int i;
char argstr[MAX_MB_ARGUMENTS*11+1];
DEFINE_WAIT(w);
if (info == NULL) {
CX18_WARN("unknown cmd %x\n", cmd);
return -EINVAL;
}
if (cx18_debug & CX18_DBGFLG_API) { /* only call u32arr2hex if needed */
if (cmd == CX18_CPU_DE_SET_MDL) {
if (cx18_debug & CX18_DBGFLG_HIGHVOL)
CX18_DEBUG_HI_API("%s\tcmd %#010x args%s\n",
info->name, cmd,
u32arr2hex(data, args, argstr));
} else
CX18_DEBUG_API("%s\tcmd %#010x args%s\n",
info->name, cmd,
u32arr2hex(data, args, argstr));
}
switch (info->rpu) {
case APU:
waitq = &cx->mb_apu_waitq;
mb_lock = &cx->epu2apu_mb_lock;
irq = IRQ_EPU_TO_APU;
mb = &cx->scb->epu2apu_mb;
break;
case CPU:
waitq = &cx->mb_cpu_waitq;
mb_lock = &cx->epu2cpu_mb_lock;
irq = IRQ_EPU_TO_CPU;
mb = &cx->scb->epu2cpu_mb;
break;
default:
CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
return -EINVAL;
}
mutex_lock(mb_lock);
/*
* Wait for an in-use mailbox to complete
*
* If the XPU is responding with Ack's, the mailbox shouldn't be in
* a busy state, since we serialize access to it on our end.
*
* If the wait for ack after sending a previous command was interrupted
* by a signal, we may get here and find a busy mailbox. After waiting,
* mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
*/
req = cx18_readl(cx, &mb->request);
timeout = msecs_to_jiffies(10);
ret = wait_event_timeout(*waitq,
(ack = cx18_readl(cx, &mb->ack)) == req,
timeout);
if (req != ack) {
/* waited long enough, make the mbox "not busy" from our end */
cx18_writel(cx, req, &mb->ack);
CX18_ERR("mbox was found stuck busy when setting up for %s; clearing busy and trying to proceed\n",
info->name);
} else if (ret != timeout)
CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
jiffies_to_msecs(timeout-ret));
/* Build the outgoing mailbox */
req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
cx18_writel(cx, cmd, &mb->cmd);
for (i = 0; i < args; i++)
cx18_writel(cx, data[i], &mb->args[i]);
cx18_writel(cx, 0, &mb->error);
cx18_writel(cx, req, &mb->request);
cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
/*
* Notify the XPU and wait for it to send an Ack back
*/
timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
irq, info->name);
/* So we don't miss the wakeup, prepare to wait before notifying fw */
prepare_to_wait(waitq, &w, TASK_UNINTERRUPTIBLE);
cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
t0 = jiffies;
ack = cx18_readl(cx, &mb->ack);
if (ack != req) {
schedule_timeout(timeout);
ret = jiffies - t0;
ack = cx18_readl(cx, &mb->ack);
} else {
ret = jiffies - t0;
}
finish_wait(waitq, &w);
if (req != ack) {
mutex_unlock(mb_lock);
if (ret >= timeout) {
/* Timed out */
CX18_DEBUG_WARN("sending %s timed out waiting %d msecs for RPU acknowledgment\n",
info->name, jiffies_to_msecs(ret));
} else {
CX18_DEBUG_WARN("woken up before mailbox ack was ready after submitting %s to RPU. only waited %d msecs on req %u but awakened with unmatched ack %u\n",
info->name,
jiffies_to_msecs(ret),
req, ack);
}
return -EINVAL;
}
if (ret >= timeout)
CX18_DEBUG_WARN("failed to be awakened upon RPU acknowledgment sending %s; timed out waiting %d msecs\n",
info->name, jiffies_to_msecs(ret));
else
CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
jiffies_to_msecs(ret), info->name);
/* Collect data returned by the XPU */
for (i = 0; i < MAX_MB_ARGUMENTS; i++)
data[i] = cx18_readl(cx, &mb->args[i]);
err = cx18_readl(cx, &mb->error);
mutex_unlock(mb_lock);
/*
* Wait for XPU to perform extra actions for the caller in some cases.
* e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all MDLs
* back in a burst shortly thereafter
*/
if (info->flags & API_SLOW)
cx18_msleep_timeout(300, 0);
if (err)
CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
info->name);
return err ? -EIO : 0;
}
int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
{
return cx18_api_call(cx, cmd, args, data);
}
static int cx18_set_filter_param(struct cx18_stream *s)
{
struct cx18 *cx = s->cx;
u32 mode;
int ret;
mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
s->handle, 1, mode, cx->spatial_strength);
mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
s->handle, 0, mode, cx->temporal_strength);
ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
s->handle, 2, cx->filter_mode >> 2, 0);
return ret;
}
int cx18_api_func(void *priv, u32 cmd, int in, int out,
u32 data[CX2341X_MBOX_MAX_DATA])
{
struct cx18_stream *s = priv;
struct cx18 *cx = s->cx;
switch (cmd) {
case CX2341X_ENC_SET_OUTPUT_PORT:
return 0;
case CX2341X_ENC_SET_FRAME_RATE:
return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
s->handle, 0, 0, 0, 0, data[0]);
case CX2341X_ENC_SET_FRAME_SIZE:
return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
s->handle, data[1], data[0]);
case CX2341X_ENC_SET_STREAM_TYPE:
return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
s->handle, data[0]);
case CX2341X_ENC_SET_ASPECT_RATIO:
return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
s->handle, data[0]);
case CX2341X_ENC_SET_GOP_PROPERTIES:
return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
s->handle, data[0], data[1]);
case CX2341X_ENC_SET_GOP_CLOSURE:
return 0;
case CX2341X_ENC_SET_AUDIO_PROPERTIES:
return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
s->handle, data[0]);
case CX2341X_ENC_MUTE_AUDIO:
return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
s->handle, data[0]);
case CX2341X_ENC_SET_BIT_RATE:
return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
s->handle, data[0], data[1], data[2], data[3]);
case CX2341X_ENC_MUTE_VIDEO:
return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
s->handle, data[0]);
case CX2341X_ENC_SET_FRAME_DROP_RATE:
return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
s->handle, data[0]);
case CX2341X_ENC_MISC:
return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
s->handle, data[0], data[1], data[2]);
case CX2341X_ENC_SET_DNR_FILTER_MODE:
cx->filter_mode = (data[0] & 3) | (data[1] << 2);
return cx18_set_filter_param(s);
case CX2341X_ENC_SET_DNR_FILTER_PROPS:
cx->spatial_strength = data[0];
cx->temporal_strength = data[1];
return cx18_set_filter_param(s);
case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
s->handle, data[0], data[1]);
case CX2341X_ENC_SET_CORING_LEVELS:
return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
s->handle, data[0], data[1], data[2], data[3]);
}
CX18_WARN("Unknown cmd %x\n", cmd);
return 0;
}
int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
u32 cmd, int args, ...)
{
va_list ap;
int i;
va_start(ap, args);
for (i = 0; i < args; i++)
data[i] = va_arg(ap, u32);
va_end(ap);
return cx18_api(cx, cmd, args, data);
}
int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
{
u32 data[MAX_MB_ARGUMENTS];
va_list ap;
int i;
if (cx == NULL) {
CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
return 0;
}
if (args > MAX_MB_ARGUMENTS) {
CX18_ERR("args too big (cmd=%x)\n", cmd);
args = MAX_MB_ARGUMENTS;
}
va_start(ap, args);
for (i = 0; i < args; i++)
data[i] = va_arg(ap, u32);
va_end(ap);
return cx18_api(cx, cmd, args, data);
}
| linux-master | drivers/media/pci/cx18/cx18-mailbox.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 buffer queues
*
* Derived from ivtv-queue.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-queue.h"
#include "cx18-streams.h"
#include "cx18-scb.h"
#include "cx18-io.h"
void cx18_buf_swap(struct cx18_buffer *buf)
{
int i;
for (i = 0; i < buf->bytesused; i += 4)
swab32s((u32 *)(buf->buf + i));
}
void _cx18_mdl_swap(struct cx18_mdl *mdl)
{
struct cx18_buffer *buf;
list_for_each_entry(buf, &mdl->buf_list, list) {
if (buf->bytesused == 0)
break;
cx18_buf_swap(buf);
}
}
void cx18_queue_init(struct cx18_queue *q)
{
INIT_LIST_HEAD(&q->list);
atomic_set(&q->depth, 0);
q->bytesused = 0;
}
struct cx18_queue *_cx18_enqueue(struct cx18_stream *s, struct cx18_mdl *mdl,
struct cx18_queue *q, int to_front)
{
/* clear the mdl if it is not to be enqueued to the full queue */
if (q != &s->q_full) {
mdl->bytesused = 0;
mdl->readpos = 0;
mdl->m_flags = 0;
mdl->skipped = 0;
mdl->curr_buf = NULL;
}
/* q_busy is restricted to a max buffer count imposed by firmware */
if (q == &s->q_busy &&
atomic_read(&q->depth) >= CX18_MAX_FW_MDLS_PER_STREAM)
q = &s->q_free;
spin_lock(&q->lock);
if (to_front)
list_add(&mdl->list, &q->list); /* LIFO */
else
list_add_tail(&mdl->list, &q->list); /* FIFO */
q->bytesused += mdl->bytesused - mdl->readpos;
atomic_inc(&q->depth);
spin_unlock(&q->lock);
return q;
}
struct cx18_mdl *cx18_dequeue(struct cx18_stream *s, struct cx18_queue *q)
{
struct cx18_mdl *mdl = NULL;
spin_lock(&q->lock);
if (!list_empty(&q->list)) {
mdl = list_first_entry(&q->list, struct cx18_mdl, list);
list_del_init(&mdl->list);
q->bytesused -= mdl->bytesused - mdl->readpos;
mdl->skipped = 0;
atomic_dec(&q->depth);
}
spin_unlock(&q->lock);
return mdl;
}
static void _cx18_mdl_update_bufs_for_cpu(struct cx18_stream *s,
struct cx18_mdl *mdl)
{
struct cx18_buffer *buf;
u32 buf_size = s->buf_size;
u32 bytesused = mdl->bytesused;
list_for_each_entry(buf, &mdl->buf_list, list) {
buf->readpos = 0;
if (bytesused >= buf_size) {
buf->bytesused = buf_size;
bytesused -= buf_size;
} else {
buf->bytesused = bytesused;
bytesused = 0;
}
cx18_buf_sync_for_cpu(s, buf);
}
}
static inline void cx18_mdl_update_bufs_for_cpu(struct cx18_stream *s,
struct cx18_mdl *mdl)
{
struct cx18_buffer *buf;
if (list_is_singular(&mdl->buf_list)) {
buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
list);
buf->bytesused = mdl->bytesused;
buf->readpos = 0;
cx18_buf_sync_for_cpu(s, buf);
} else {
_cx18_mdl_update_bufs_for_cpu(s, mdl);
}
}
struct cx18_mdl *cx18_queue_get_mdl(struct cx18_stream *s, u32 id,
u32 bytesused)
{
struct cx18 *cx = s->cx;
struct cx18_mdl *mdl;
struct cx18_mdl *tmp;
struct cx18_mdl *ret = NULL;
LIST_HEAD(sweep_up);
/*
* We don't have to acquire multiple q locks here, because we are
* serialized by the single threaded work handler.
* MDLs from the firmware will thus remain in order as
* they are moved from q_busy to q_full or to the dvb ring buffer.
*/
spin_lock(&s->q_busy.lock);
list_for_each_entry_safe(mdl, tmp, &s->q_busy.list, list) {
/*
* We should find what the firmware told us is done,
* right at the front of the queue. If we don't, we likely have
* missed an mdl done message from the firmware.
* Once we skip an mdl repeatedly, relative to the size of
* q_busy, we have high confidence we've missed it.
*/
if (mdl->id != id) {
mdl->skipped++;
if (mdl->skipped >= atomic_read(&s->q_busy.depth)-1) {
/* mdl must have fallen out of rotation */
CX18_WARN("Skipped %s, MDL %d, %d times - it must have dropped out of rotation\n",
s->name, mdl->id,
mdl->skipped);
/* Sweep it up to put it back into rotation */
list_move_tail(&mdl->list, &sweep_up);
atomic_dec(&s->q_busy.depth);
}
continue;
}
/*
* We pull the desired mdl off of the queue here. Something
* will have to put it back on a queue later.
*/
list_del_init(&mdl->list);
atomic_dec(&s->q_busy.depth);
ret = mdl;
break;
}
spin_unlock(&s->q_busy.lock);
/*
* We found the mdl for which we were looking. Get it ready for
* the caller to put on q_full or in the dvb ring buffer.
*/
if (ret != NULL) {
ret->bytesused = bytesused;
ret->skipped = 0;
/* 0'ed readpos, m_flags & curr_buf when mdl went on q_busy */
cx18_mdl_update_bufs_for_cpu(s, ret);
if (s->type != CX18_ENC_STREAM_TYPE_TS)
set_bit(CX18_F_M_NEED_SWAP, &ret->m_flags);
}
/* Put any mdls the firmware is ignoring back into normal rotation */
list_for_each_entry_safe(mdl, tmp, &sweep_up, list) {
list_del_init(&mdl->list);
cx18_enqueue(s, mdl, &s->q_free);
}
return ret;
}
/* Move all mdls of a queue, while flushing the mdl */
static void cx18_queue_flush(struct cx18_stream *s,
struct cx18_queue *q_src, struct cx18_queue *q_dst)
{
struct cx18_mdl *mdl;
/* It only makes sense to flush to q_free or q_idle */
if (q_src == q_dst || q_dst == &s->q_full || q_dst == &s->q_busy)
return;
spin_lock(&q_src->lock);
spin_lock(&q_dst->lock);
while (!list_empty(&q_src->list)) {
mdl = list_first_entry(&q_src->list, struct cx18_mdl, list);
list_move_tail(&mdl->list, &q_dst->list);
mdl->bytesused = 0;
mdl->readpos = 0;
mdl->m_flags = 0;
mdl->skipped = 0;
mdl->curr_buf = NULL;
atomic_inc(&q_dst->depth);
}
cx18_queue_init(q_src);
spin_unlock(&q_src->lock);
spin_unlock(&q_dst->lock);
}
void cx18_flush_queues(struct cx18_stream *s)
{
cx18_queue_flush(s, &s->q_busy, &s->q_free);
cx18_queue_flush(s, &s->q_full, &s->q_free);
}
/*
* Note, s->buf_pool is not protected by a lock,
* the stream better not have *anything* going on when calling this
*/
void cx18_unload_queues(struct cx18_stream *s)
{
struct cx18_queue *q_idle = &s->q_idle;
struct cx18_mdl *mdl;
struct cx18_buffer *buf;
/* Move all MDLS to q_idle */
cx18_queue_flush(s, &s->q_busy, q_idle);
cx18_queue_flush(s, &s->q_full, q_idle);
cx18_queue_flush(s, &s->q_free, q_idle);
/* Reset MDL id's and move all buffers back to the stream's buf_pool */
spin_lock(&q_idle->lock);
list_for_each_entry(mdl, &q_idle->list, list) {
while (!list_empty(&mdl->buf_list)) {
buf = list_first_entry(&mdl->buf_list,
struct cx18_buffer, list);
list_move_tail(&buf->list, &s->buf_pool);
buf->bytesused = 0;
buf->readpos = 0;
}
mdl->id = s->mdl_base_idx; /* reset id to a "safe" value */
/* all other mdl fields were cleared by cx18_queue_flush() */
}
spin_unlock(&q_idle->lock);
}
/*
* Note, s->buf_pool is not protected by a lock,
* the stream better not have *anything* going on when calling this
*/
void cx18_load_queues(struct cx18_stream *s)
{
struct cx18 *cx = s->cx;
struct cx18_mdl *mdl;
struct cx18_buffer *buf;
int mdl_id;
int i;
u32 partial_buf_size;
/*
* Attach buffers to MDLs, give the MDLs ids, and add MDLs to q_free
* Excess MDLs are left on q_idle
* Excess buffers are left in buf_pool and/or on an MDL in q_idle
*/
mdl_id = s->mdl_base_idx;
for (mdl = cx18_dequeue(s, &s->q_idle), i = s->bufs_per_mdl;
mdl != NULL && i == s->bufs_per_mdl;
mdl = cx18_dequeue(s, &s->q_idle)) {
mdl->id = mdl_id;
for (i = 0; i < s->bufs_per_mdl; i++) {
if (list_empty(&s->buf_pool))
break;
buf = list_first_entry(&s->buf_pool, struct cx18_buffer,
list);
list_move_tail(&buf->list, &mdl->buf_list);
/* update the firmware's MDL array with this buffer */
cx18_writel(cx, buf->dma_handle,
&cx->scb->cpu_mdl[mdl_id + i].paddr);
cx18_writel(cx, s->buf_size,
&cx->scb->cpu_mdl[mdl_id + i].length);
}
if (i == s->bufs_per_mdl) {
/*
* The encoder doesn't honor s->mdl_size. So in the
* case of a non-integral number of buffers to meet
* mdl_size, we lie about the size of the last buffer
* in the MDL to get the encoder to really only send
* us mdl_size bytes per MDL transfer.
*/
partial_buf_size = s->mdl_size % s->buf_size;
if (partial_buf_size) {
cx18_writel(cx, partial_buf_size,
&cx->scb->cpu_mdl[mdl_id + i - 1].length);
}
cx18_enqueue(s, mdl, &s->q_free);
} else {
/* Not enough buffers for this MDL; we won't use it */
cx18_push(s, mdl, &s->q_idle);
}
mdl_id += i;
}
}
void _cx18_mdl_sync_for_device(struct cx18_stream *s, struct cx18_mdl *mdl)
{
int dma = s->dma;
u32 buf_size = s->buf_size;
struct pci_dev *pci_dev = s->cx->pci_dev;
struct cx18_buffer *buf;
list_for_each_entry(buf, &mdl->buf_list, list)
dma_sync_single_for_device(&pci_dev->dev, buf->dma_handle,
buf_size, dma);
}
int cx18_stream_alloc(struct cx18_stream *s)
{
struct cx18 *cx = s->cx;
int i;
if (s->buffers == 0)
return 0;
CX18_DEBUG_INFO("Allocate %s stream: %d x %d buffers (%d.%02d kB total)\n",
s->name, s->buffers, s->buf_size,
s->buffers * s->buf_size / 1024,
(s->buffers * s->buf_size * 100 / 1024) % 100);
if (((char __iomem *)&cx->scb->cpu_mdl[cx->free_mdl_idx + s->buffers] -
(char __iomem *)cx->scb) > SCB_RESERVED_SIZE) {
unsigned bufsz = (((char __iomem *)cx->scb) + SCB_RESERVED_SIZE -
((char __iomem *)cx->scb->cpu_mdl));
CX18_ERR("Too many buffers, cannot fit in SCB area\n");
CX18_ERR("Max buffers = %zu\n",
bufsz / sizeof(struct cx18_mdl_ent));
return -ENOMEM;
}
s->mdl_base_idx = cx->free_mdl_idx;
/* allocate stream buffers and MDLs */
for (i = 0; i < s->buffers; i++) {
struct cx18_mdl *mdl;
struct cx18_buffer *buf;
/* 1 MDL per buffer to handle the worst & also default case */
mdl = kzalloc(sizeof(struct cx18_mdl), GFP_KERNEL|__GFP_NOWARN);
if (mdl == NULL)
break;
buf = kzalloc(sizeof(struct cx18_buffer),
GFP_KERNEL|__GFP_NOWARN);
if (buf == NULL) {
kfree(mdl);
break;
}
buf->buf = kmalloc(s->buf_size, GFP_KERNEL|__GFP_NOWARN);
if (buf->buf == NULL) {
kfree(mdl);
kfree(buf);
break;
}
INIT_LIST_HEAD(&mdl->list);
INIT_LIST_HEAD(&mdl->buf_list);
mdl->id = s->mdl_base_idx; /* a somewhat safe value */
cx18_enqueue(s, mdl, &s->q_idle);
INIT_LIST_HEAD(&buf->list);
buf->dma_handle = dma_map_single(&s->cx->pci_dev->dev,
buf->buf, s->buf_size,
s->dma);
cx18_buf_sync_for_cpu(s, buf);
list_add_tail(&buf->list, &s->buf_pool);
}
if (i == s->buffers) {
cx->free_mdl_idx += s->buffers;
return 0;
}
CX18_ERR("Couldn't allocate buffers for %s stream\n", s->name);
cx18_stream_free(s);
return -ENOMEM;
}
void cx18_stream_free(struct cx18_stream *s)
{
struct cx18_mdl *mdl;
struct cx18_buffer *buf;
struct cx18 *cx = s->cx;
CX18_DEBUG_INFO("Deallocating buffers for %s stream\n", s->name);
/* move all buffers to buf_pool and all MDLs to q_idle */
cx18_unload_queues(s);
/* empty q_idle */
while ((mdl = cx18_dequeue(s, &s->q_idle)))
kfree(mdl);
/* empty buf_pool */
while (!list_empty(&s->buf_pool)) {
buf = list_first_entry(&s->buf_pool, struct cx18_buffer, list);
list_del_init(&buf->list);
dma_unmap_single(&s->cx->pci_dev->dev, buf->dma_handle,
s->buf_size, s->dma);
kfree(buf->buf);
kfree(buf);
}
}
| linux-master | drivers/media/pci/cx18/cx18-queue.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 driver initialization and card probing
*
* Derived from ivtv-driver.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-version.h"
#include "cx18-cards.h"
#include "cx18-i2c.h"
#include "cx18-irq.h"
#include "cx18-gpio.h"
#include "cx18-firmware.h"
#include "cx18-queue.h"
#include "cx18-streams.h"
#include "cx18-av-core.h"
#include "cx18-scb.h"
#include "cx18-mailbox.h"
#include "cx18-ioctl.h"
#include "cx18-controls.h"
#include "xc2028.h"
#include <linux/dma-mapping.h>
#include <media/tveeprom.h>
/* If you have already X v4l cards, then set this to X. This way
the device numbers stay matched. Example: you have a WinTV card
without radio and a Compro H900 with. Normally this would give a
video1 device together with a radio0 device for the Compro. By
setting this to 1 you ensure that radio0 is now also radio1. */
int cx18_first_minor;
/* Callback for registering extensions */
int (*cx18_ext_init)(struct cx18 *);
EXPORT_SYMBOL(cx18_ext_init);
/* add your revision and whatnot here */
static const struct pci_device_id cx18_pci_tbl[] = {
{PCI_VENDOR_ID_CX, PCI_DEVICE_ID_CX23418,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{0,}
};
MODULE_DEVICE_TABLE(pci, cx18_pci_tbl);
static atomic_t cx18_instance = ATOMIC_INIT(0);
/* Parameter declarations */
static int cardtype[CX18_MAX_CARDS];
static int tuner[CX18_MAX_CARDS] = { -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1 };
static int radio[CX18_MAX_CARDS] = { -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1 };
static unsigned cardtype_c = 1;
static unsigned tuner_c = 1;
static unsigned radio_c = 1;
static char pal[] = "--";
static char secam[] = "--";
static char ntsc[] = "-";
/* Buffers */
static int enc_ts_buffers = CX18_DEFAULT_ENC_TS_BUFFERS;
static int enc_mpg_buffers = CX18_DEFAULT_ENC_MPG_BUFFERS;
static int enc_idx_buffers = CX18_DEFAULT_ENC_IDX_BUFFERS;
static int enc_yuv_buffers = CX18_DEFAULT_ENC_YUV_BUFFERS;
static int enc_vbi_buffers = CX18_DEFAULT_ENC_VBI_BUFFERS;
static int enc_pcm_buffers = CX18_DEFAULT_ENC_PCM_BUFFERS;
static int enc_ts_bufsize = CX18_DEFAULT_ENC_TS_BUFSIZE;
static int enc_mpg_bufsize = CX18_DEFAULT_ENC_MPG_BUFSIZE;
static int enc_idx_bufsize = CX18_DEFAULT_ENC_IDX_BUFSIZE;
static int enc_yuv_bufsize = CX18_DEFAULT_ENC_YUV_BUFSIZE;
static int enc_pcm_bufsize = CX18_DEFAULT_ENC_PCM_BUFSIZE;
static int enc_ts_bufs = -1;
static int enc_mpg_bufs = -1;
static int enc_idx_bufs = CX18_MAX_FW_MDLS_PER_STREAM;
static int enc_yuv_bufs = -1;
static int enc_vbi_bufs = -1;
static int enc_pcm_bufs = -1;
static int cx18_pci_latency = 1;
static int mmio_ndelay;
static int retry_mmio = 1;
int cx18_debug;
module_param_array(tuner, int, &tuner_c, 0644);
module_param_array(radio, int, &radio_c, 0644);
module_param_array(cardtype, int, &cardtype_c, 0644);
module_param_string(pal, pal, sizeof(pal), 0644);
module_param_string(secam, secam, sizeof(secam), 0644);
module_param_string(ntsc, ntsc, sizeof(ntsc), 0644);
module_param_named(debug, cx18_debug, int, 0644);
module_param(mmio_ndelay, int, 0644);
module_param(retry_mmio, int, 0644);
module_param(cx18_pci_latency, int, 0644);
module_param(cx18_first_minor, int, 0644);
module_param(enc_ts_buffers, int, 0644);
module_param(enc_mpg_buffers, int, 0644);
module_param(enc_idx_buffers, int, 0644);
module_param(enc_yuv_buffers, int, 0644);
module_param(enc_vbi_buffers, int, 0644);
module_param(enc_pcm_buffers, int, 0644);
module_param(enc_ts_bufsize, int, 0644);
module_param(enc_mpg_bufsize, int, 0644);
module_param(enc_idx_bufsize, int, 0644);
module_param(enc_yuv_bufsize, int, 0644);
module_param(enc_pcm_bufsize, int, 0644);
module_param(enc_ts_bufs, int, 0644);
module_param(enc_mpg_bufs, int, 0644);
module_param(enc_idx_bufs, int, 0644);
module_param(enc_yuv_bufs, int, 0644);
module_param(enc_vbi_bufs, int, 0644);
module_param(enc_pcm_bufs, int, 0644);
MODULE_PARM_DESC(tuner, "Tuner type selection,\n"
"\t\t\tsee tuner.h for values");
MODULE_PARM_DESC(radio,
"Enable or disable the radio. Use only if autodetection\n"
"\t\t\tfails. 0 = disable, 1 = enable");
MODULE_PARM_DESC(cardtype,
"Only use this option if your card is not detected properly.\n"
"\t\tSpecify card type:\n"
"\t\t\t 1 = Hauppauge HVR 1600 (ESMT memory)\n"
"\t\t\t 2 = Hauppauge HVR 1600 (Samsung memory)\n"
"\t\t\t 3 = Compro VideoMate H900\n"
"\t\t\t 4 = Yuan MPC718\n"
"\t\t\t 5 = Conexant Raptor PAL/SECAM\n"
"\t\t\t 6 = Toshiba Qosmio DVB-T/Analog\n"
"\t\t\t 7 = Leadtek WinFast PVR2100\n"
"\t\t\t 8 = Leadtek WinFast DVR3100 H\n"
"\t\t\t 9 = GoTView PCI DVD3 Hybrid\n"
"\t\t\t 10 = Hauppauge HVR 1600 (S5H1411)\n"
"\t\t\t 0 = Autodetect (default)\n"
"\t\t\t-1 = Ignore this card\n\t\t");
MODULE_PARM_DESC(pal, "Set PAL standard: B, G, H, D, K, I, M, N, Nc, 60");
MODULE_PARM_DESC(secam, "Set SECAM standard: B, G, H, D, K, L, LC");
MODULE_PARM_DESC(ntsc, "Set NTSC standard: M, J, K");
MODULE_PARM_DESC(debug,
"Debug level (bitmask). Default: 0\n"
"\t\t\t 1/0x0001: warning\n"
"\t\t\t 2/0x0002: info\n"
"\t\t\t 4/0x0004: mailbox\n"
"\t\t\t 8/0x0008: dma\n"
"\t\t\t 16/0x0010: ioctl\n"
"\t\t\t 32/0x0020: file\n"
"\t\t\t 64/0x0040: i2c\n"
"\t\t\t128/0x0080: irq\n"
"\t\t\t256/0x0100: high volume\n");
MODULE_PARM_DESC(cx18_pci_latency,
"Change the PCI latency to 64 if lower: 0 = No, 1 = Yes,\n"
"\t\t\tDefault: Yes");
MODULE_PARM_DESC(retry_mmio,
"(Deprecated) MMIO writes are now always checked and retried\n"
"\t\t\tEffectively: 1 [Yes]");
MODULE_PARM_DESC(mmio_ndelay,
"(Deprecated) MMIO accesses are now never purposely delayed\n"
"\t\t\tEffectively: 0 ns");
MODULE_PARM_DESC(enc_ts_buffers,
"Encoder TS buffer memory (MB). (enc_ts_bufs can override)\n"
"\t\t\tDefault: " __stringify(CX18_DEFAULT_ENC_TS_BUFFERS));
MODULE_PARM_DESC(enc_ts_bufsize,
"Size of an encoder TS buffer (kB)\n"
"\t\t\tDefault: " __stringify(CX18_DEFAULT_ENC_TS_BUFSIZE));
MODULE_PARM_DESC(enc_ts_bufs,
"Number of encoder TS buffers\n"
"\t\t\tDefault is computed from other enc_ts_* parameters");
MODULE_PARM_DESC(enc_mpg_buffers,
"Encoder MPG buffer memory (MB). (enc_mpg_bufs can override)\n"
"\t\t\tDefault: " __stringify(CX18_DEFAULT_ENC_MPG_BUFFERS));
MODULE_PARM_DESC(enc_mpg_bufsize,
"Size of an encoder MPG buffer (kB)\n"
"\t\t\tDefault: " __stringify(CX18_DEFAULT_ENC_MPG_BUFSIZE));
MODULE_PARM_DESC(enc_mpg_bufs,
"Number of encoder MPG buffers\n"
"\t\t\tDefault is computed from other enc_mpg_* parameters");
MODULE_PARM_DESC(enc_idx_buffers,
"(Deprecated) Encoder IDX buffer memory (MB)\n"
"\t\t\tIgnored, except 0 disables IDX buffer allocations\n"
"\t\t\tDefault: 1 [Enabled]");
MODULE_PARM_DESC(enc_idx_bufsize,
"Size of an encoder IDX buffer (kB)\n"
"\t\t\tAllowed values are multiples of 1.5 kB rounded up\n"
"\t\t\t(multiples of size required for 64 index entries)\n"
"\t\t\tDefault: 2");
MODULE_PARM_DESC(enc_idx_bufs,
"Number of encoder IDX buffers\n"
"\t\t\tDefault: " __stringify(CX18_MAX_FW_MDLS_PER_STREAM));
MODULE_PARM_DESC(enc_yuv_buffers,
"Encoder YUV buffer memory (MB). (enc_yuv_bufs can override)\n"
"\t\t\tDefault: " __stringify(CX18_DEFAULT_ENC_YUV_BUFFERS));
MODULE_PARM_DESC(enc_yuv_bufsize,
"Size of an encoder YUV buffer (kB)\n"
"\t\t\tAllowed values are multiples of 33.75 kB rounded up\n"
"\t\t\t(multiples of size required for 32 screen lines)\n"
"\t\t\tDefault: 102");
MODULE_PARM_DESC(enc_yuv_bufs,
"Number of encoder YUV buffers\n"
"\t\t\tDefault is computed from other enc_yuv_* parameters");
MODULE_PARM_DESC(enc_vbi_buffers,
"Encoder VBI buffer memory (MB). (enc_vbi_bufs can override)\n"
"\t\t\tDefault: " __stringify(CX18_DEFAULT_ENC_VBI_BUFFERS));
MODULE_PARM_DESC(enc_vbi_bufs,
"Number of encoder VBI buffers\n"
"\t\t\tDefault is computed from enc_vbi_buffers");
MODULE_PARM_DESC(enc_pcm_buffers,
"Encoder PCM buffer memory (MB). (enc_pcm_bufs can override)\n"
"\t\t\tDefault: " __stringify(CX18_DEFAULT_ENC_PCM_BUFFERS));
MODULE_PARM_DESC(enc_pcm_bufsize,
"Size of an encoder PCM buffer (kB)\n"
"\t\t\tDefault: " __stringify(CX18_DEFAULT_ENC_PCM_BUFSIZE));
MODULE_PARM_DESC(enc_pcm_bufs,
"Number of encoder PCM buffers\n"
"\t\t\tDefault is computed from other enc_pcm_* parameters");
MODULE_PARM_DESC(cx18_first_minor,
"Set device node number assigned to first card");
MODULE_AUTHOR("Hans Verkuil");
MODULE_DESCRIPTION("CX23418 driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(CX18_VERSION);
#if defined(CONFIG_MODULES) && defined(MODULE)
static void request_module_async(struct work_struct *work)
{
struct cx18 *dev = container_of(work, struct cx18, request_module_wk);
/* Make sure cx18-alsa module is loaded */
request_module("cx18-alsa");
/* Initialize cx18-alsa for this instance of the cx18 device */
if (cx18_ext_init)
cx18_ext_init(dev);
}
static void request_modules(struct cx18 *dev)
{
INIT_WORK(&dev->request_module_wk, request_module_async);
schedule_work(&dev->request_module_wk);
}
static void flush_request_modules(struct cx18 *dev)
{
flush_work(&dev->request_module_wk);
}
#else
#define request_modules(dev)
#define flush_request_modules(dev)
#endif /* CONFIG_MODULES */
/* Generic utility functions */
int cx18_msleep_timeout(unsigned int msecs, int intr)
{
long int timeout = msecs_to_jiffies(msecs);
int sig;
do {
set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
timeout = schedule_timeout(timeout);
sig = intr ? signal_pending(current) : 0;
} while (!sig && timeout);
return sig;
}
/* Release ioremapped memory */
static void cx18_iounmap(struct cx18 *cx)
{
if (!cx)
return;
/* Release io memory */
if (cx->enc_mem) {
CX18_DEBUG_INFO("releasing enc_mem\n");
iounmap(cx->enc_mem);
cx->enc_mem = NULL;
}
}
static void cx18_eeprom_dump(struct cx18 *cx, unsigned char *eedata, int len)
{
int i;
CX18_INFO("eeprom dump:\n");
for (i = 0; i < len; i++) {
if (0 == (i % 16))
CX18_INFO("eeprom %02x:", i);
printk(KERN_CONT " %02x", eedata[i]);
if (15 == (i % 16))
printk(KERN_CONT "\n");
}
}
/* Hauppauge card? get values from tveeprom */
void cx18_read_eeprom(struct cx18 *cx, struct tveeprom *tv)
{
struct i2c_client *c;
u8 eedata[256];
memset(tv, 0, sizeof(*tv));
c = kzalloc(sizeof(*c), GFP_KERNEL);
if (!c)
return;
strscpy(c->name, "cx18 tveeprom tmp", sizeof(c->name));
c->adapter = &cx->i2c_adap[0];
c->addr = 0xa0 >> 1;
if (tveeprom_read(c, eedata, sizeof(eedata)))
goto ret;
switch (cx->card->type) {
case CX18_CARD_HVR_1600_ESMT:
case CX18_CARD_HVR_1600_SAMSUNG:
case CX18_CARD_HVR_1600_S5H1411:
tveeprom_hauppauge_analog(tv, eedata);
break;
case CX18_CARD_YUAN_MPC718:
case CX18_CARD_GOTVIEW_PCI_DVD3:
tv->model = 0x718;
cx18_eeprom_dump(cx, eedata, sizeof(eedata));
CX18_INFO("eeprom PCI ID: %02x%02x:%02x%02x\n",
eedata[2], eedata[1], eedata[4], eedata[3]);
break;
default:
tv->model = 0xffffffff;
cx18_eeprom_dump(cx, eedata, sizeof(eedata));
break;
}
ret:
kfree(c);
}
static void cx18_process_eeprom(struct cx18 *cx)
{
struct tveeprom tv;
cx18_read_eeprom(cx, &tv);
/* Many thanks to Steven Toth from Hauppauge for providing the
model numbers */
/* Note: the Samsung memory models cannot be reliably determined
from the model number. Use the cardtype module option if you
have one of these preproduction models. */
switch (tv.model) {
case 74301: /* Retail models */
case 74321:
case 74351: /* OEM models */
case 74361:
/* Digital side is s5h1411/tda18271 */
cx->card = cx18_get_card(CX18_CARD_HVR_1600_S5H1411);
break;
case 74021: /* Retail models */
case 74031:
case 74041:
case 74141:
case 74541: /* OEM models */
case 74551:
case 74591:
case 74651:
case 74691:
case 74751:
case 74891:
/* Digital side is s5h1409/mxl5005s */
cx->card = cx18_get_card(CX18_CARD_HVR_1600_ESMT);
break;
case 0x718:
return;
case 0xffffffff:
CX18_INFO("Unknown EEPROM encoding\n");
return;
case 0:
CX18_ERR("Invalid EEPROM\n");
return;
default:
CX18_ERR("Unknown model %d, defaulting to original HVR-1600 (cardtype=1)\n",
tv.model);
cx->card = cx18_get_card(CX18_CARD_HVR_1600_ESMT);
break;
}
cx->v4l2_cap = cx->card->v4l2_capabilities;
cx->card_name = cx->card->name;
cx->card_i2c = cx->card->i2c;
CX18_INFO("Autodetected %s\n", cx->card_name);
if (tv.tuner_type == TUNER_ABSENT)
CX18_ERR("tveeprom cannot autodetect tuner!\n");
if (cx->options.tuner == -1)
cx->options.tuner = tv.tuner_type;
if (cx->options.radio == -1)
cx->options.radio = (tv.has_radio != 0);
if (cx->std != 0)
/* user specified tuner standard */
return;
/* autodetect tuner standard */
#define TVEEPROM_TUNER_FORMAT_ALL (V4L2_STD_B | V4L2_STD_GH | \
V4L2_STD_MN | \
V4L2_STD_PAL_I | \
V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC | \
V4L2_STD_DK)
if ((tv.tuner_formats & TVEEPROM_TUNER_FORMAT_ALL)
== TVEEPROM_TUNER_FORMAT_ALL) {
CX18_DEBUG_INFO("Worldwide tuner detected\n");
cx->std = V4L2_STD_ALL;
} else if (tv.tuner_formats & V4L2_STD_PAL) {
CX18_DEBUG_INFO("PAL tuner detected\n");
cx->std |= V4L2_STD_PAL_BG | V4L2_STD_PAL_H;
} else if (tv.tuner_formats & V4L2_STD_NTSC) {
CX18_DEBUG_INFO("NTSC tuner detected\n");
cx->std |= V4L2_STD_NTSC_M;
} else if (tv.tuner_formats & V4L2_STD_SECAM) {
CX18_DEBUG_INFO("SECAM tuner detected\n");
cx->std |= V4L2_STD_SECAM_L;
} else {
CX18_INFO("No tuner detected, default to NTSC-M\n");
cx->std |= V4L2_STD_NTSC_M;
}
}
static v4l2_std_id cx18_parse_std(struct cx18 *cx)
{
switch (pal[0]) {
case '6':
return V4L2_STD_PAL_60;
case 'b':
case 'B':
case 'g':
case 'G':
return V4L2_STD_PAL_BG;
case 'h':
case 'H':
return V4L2_STD_PAL_H;
case 'n':
case 'N':
if (pal[1] == 'c' || pal[1] == 'C')
return V4L2_STD_PAL_Nc;
return V4L2_STD_PAL_N;
case 'i':
case 'I':
return V4L2_STD_PAL_I;
case 'd':
case 'D':
case 'k':
case 'K':
return V4L2_STD_PAL_DK;
case 'M':
case 'm':
return V4L2_STD_PAL_M;
case '-':
break;
default:
CX18_WARN("pal= argument not recognised\n");
return 0;
}
switch (secam[0]) {
case 'b':
case 'B':
case 'g':
case 'G':
case 'h':
case 'H':
return V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H;
case 'd':
case 'D':
case 'k':
case 'K':
return V4L2_STD_SECAM_DK;
case 'l':
case 'L':
if (secam[1] == 'C' || secam[1] == 'c')
return V4L2_STD_SECAM_LC;
return V4L2_STD_SECAM_L;
case '-':
break;
default:
CX18_WARN("secam= argument not recognised\n");
return 0;
}
switch (ntsc[0]) {
case 'm':
case 'M':
return V4L2_STD_NTSC_M;
case 'j':
case 'J':
return V4L2_STD_NTSC_M_JP;
case 'k':
case 'K':
return V4L2_STD_NTSC_M_KR;
case '-':
break;
default:
CX18_WARN("ntsc= argument not recognised\n");
return 0;
}
/* no match found */
return 0;
}
static void cx18_process_options(struct cx18 *cx)
{
int i, j;
cx->options.megabytes[CX18_ENC_STREAM_TYPE_TS] = enc_ts_buffers;
cx->options.megabytes[CX18_ENC_STREAM_TYPE_MPG] = enc_mpg_buffers;
cx->options.megabytes[CX18_ENC_STREAM_TYPE_IDX] = enc_idx_buffers;
cx->options.megabytes[CX18_ENC_STREAM_TYPE_YUV] = enc_yuv_buffers;
cx->options.megabytes[CX18_ENC_STREAM_TYPE_VBI] = enc_vbi_buffers;
cx->options.megabytes[CX18_ENC_STREAM_TYPE_PCM] = enc_pcm_buffers;
cx->options.megabytes[CX18_ENC_STREAM_TYPE_RAD] = 0; /* control only */
cx->stream_buffers[CX18_ENC_STREAM_TYPE_TS] = enc_ts_bufs;
cx->stream_buffers[CX18_ENC_STREAM_TYPE_MPG] = enc_mpg_bufs;
cx->stream_buffers[CX18_ENC_STREAM_TYPE_IDX] = enc_idx_bufs;
cx->stream_buffers[CX18_ENC_STREAM_TYPE_YUV] = enc_yuv_bufs;
cx->stream_buffers[CX18_ENC_STREAM_TYPE_VBI] = enc_vbi_bufs;
cx->stream_buffers[CX18_ENC_STREAM_TYPE_PCM] = enc_pcm_bufs;
cx->stream_buffers[CX18_ENC_STREAM_TYPE_RAD] = 0; /* control, no data */
cx->stream_buf_size[CX18_ENC_STREAM_TYPE_TS] = enc_ts_bufsize;
cx->stream_buf_size[CX18_ENC_STREAM_TYPE_MPG] = enc_mpg_bufsize;
cx->stream_buf_size[CX18_ENC_STREAM_TYPE_IDX] = enc_idx_bufsize;
cx->stream_buf_size[CX18_ENC_STREAM_TYPE_YUV] = enc_yuv_bufsize;
cx->stream_buf_size[CX18_ENC_STREAM_TYPE_VBI] = VBI_ACTIVE_SAMPLES * 36;
cx->stream_buf_size[CX18_ENC_STREAM_TYPE_PCM] = enc_pcm_bufsize;
cx->stream_buf_size[CX18_ENC_STREAM_TYPE_RAD] = 0; /* control no data */
/* Ensure stream_buffers & stream_buf_size are valid */
for (i = 0; i < CX18_MAX_STREAMS; i++) {
if (cx->stream_buffers[i] == 0 || /* User said 0 buffers */
cx->options.megabytes[i] <= 0 || /* User said 0 MB total */
cx->stream_buf_size[i] <= 0) { /* User said buf size 0 */
cx->options.megabytes[i] = 0;
cx->stream_buffers[i] = 0;
cx->stream_buf_size[i] = 0;
continue;
}
/*
* YUV is a special case where the stream_buf_size needs to be
* an integral multiple of 33.75 kB (storage for 32 screens
* lines to maintain alignment in case of lost buffers).
*
* IDX is a special case where the stream_buf_size should be
* an integral multiple of 1.5 kB (storage for 64 index entries
* to maintain alignment in case of lost buffers).
*
*/
if (i == CX18_ENC_STREAM_TYPE_YUV) {
cx->stream_buf_size[i] *= 1024;
cx->stream_buf_size[i] -=
(cx->stream_buf_size[i] % CX18_UNIT_ENC_YUV_BUFSIZE);
if (cx->stream_buf_size[i] < CX18_UNIT_ENC_YUV_BUFSIZE)
cx->stream_buf_size[i] =
CX18_UNIT_ENC_YUV_BUFSIZE;
} else if (i == CX18_ENC_STREAM_TYPE_IDX) {
cx->stream_buf_size[i] *= 1024;
cx->stream_buf_size[i] -=
(cx->stream_buf_size[i] % CX18_UNIT_ENC_IDX_BUFSIZE);
if (cx->stream_buf_size[i] < CX18_UNIT_ENC_IDX_BUFSIZE)
cx->stream_buf_size[i] =
CX18_UNIT_ENC_IDX_BUFSIZE;
}
/*
* YUV and IDX are special cases where the stream_buf_size is
* now in bytes.
* VBI is a special case where the stream_buf_size is fixed
* and already in bytes
*/
if (i == CX18_ENC_STREAM_TYPE_VBI ||
i == CX18_ENC_STREAM_TYPE_YUV ||
i == CX18_ENC_STREAM_TYPE_IDX) {
if (cx->stream_buffers[i] < 0) {
cx->stream_buffers[i] =
cx->options.megabytes[i] * 1024 * 1024
/ cx->stream_buf_size[i];
} else {
/* N.B. This might round down to 0 */
cx->options.megabytes[i] =
cx->stream_buffers[i]
* cx->stream_buf_size[i]/(1024 * 1024);
}
} else {
/* All other streams have stream_buf_size in kB here */
if (cx->stream_buffers[i] < 0) {
cx->stream_buffers[i] =
cx->options.megabytes[i] * 1024
/ cx->stream_buf_size[i];
} else {
/* N.B. This might round down to 0 */
cx->options.megabytes[i] =
cx->stream_buffers[i]
* cx->stream_buf_size[i] / 1024;
}
/* convert from kB to bytes */
cx->stream_buf_size[i] *= 1024;
}
CX18_DEBUG_INFO("Stream type %d options: %d MB, %d buffers, %d bytes\n",
i, cx->options.megabytes[i],
cx->stream_buffers[i], cx->stream_buf_size[i]);
}
cx->options.cardtype = cardtype[cx->instance];
cx->options.tuner = tuner[cx->instance];
cx->options.radio = radio[cx->instance];
cx->std = cx18_parse_std(cx);
if (cx->options.cardtype == -1) {
CX18_INFO("Ignore card\n");
return;
}
cx->card = cx18_get_card(cx->options.cardtype - 1);
if (cx->card)
CX18_INFO("User specified %s card\n", cx->card->name);
else if (cx->options.cardtype != 0)
CX18_ERR("Unknown user specified type, trying to autodetect card\n");
if (!cx->card) {
if (cx->pci_dev->subsystem_vendor == CX18_PCI_ID_HAUPPAUGE) {
cx->card = cx18_get_card(CX18_CARD_HVR_1600_ESMT);
CX18_INFO("Autodetected Hauppauge card\n");
}
}
if (!cx->card) {
for (i = 0; (cx->card = cx18_get_card(i)); i++) {
if (!cx->card->pci_list)
continue;
for (j = 0; cx->card->pci_list[j].device; j++) {
if (cx->pci_dev->device !=
cx->card->pci_list[j].device)
continue;
if (cx->pci_dev->subsystem_vendor !=
cx->card->pci_list[j].subsystem_vendor)
continue;
if (cx->pci_dev->subsystem_device !=
cx->card->pci_list[j].subsystem_device)
continue;
CX18_INFO("Autodetected %s card\n", cx->card->name);
goto done;
}
}
}
done:
if (!cx->card) {
cx->card = cx18_get_card(CX18_CARD_HVR_1600_ESMT);
CX18_ERR("Unknown card: vendor/device: [%04x:%04x]\n",
cx->pci_dev->vendor, cx->pci_dev->device);
CX18_ERR(" subsystem vendor/device: [%04x:%04x]\n",
cx->pci_dev->subsystem_vendor,
cx->pci_dev->subsystem_device);
CX18_ERR("Defaulting to %s card\n", cx->card->name);
CX18_ERR("Please mail the vendor/device and subsystem vendor/device IDs and what kind of\n");
CX18_ERR("card you have to the linux-media mailinglist (www.linuxtv.org)\n");
CX18_ERR("Prefix your subject line with [UNKNOWN CX18 CARD].\n");
}
cx->v4l2_cap = cx->card->v4l2_capabilities;
cx->card_name = cx->card->name;
cx->card_i2c = cx->card->i2c;
}
static int cx18_create_in_workq(struct cx18 *cx)
{
snprintf(cx->in_workq_name, sizeof(cx->in_workq_name), "%s-in",
cx->v4l2_dev.name);
cx->in_work_queue = alloc_ordered_workqueue("%s", 0, cx->in_workq_name);
if (!cx->in_work_queue) {
CX18_ERR("Unable to create incoming mailbox handler thread\n");
return -ENOMEM;
}
return 0;
}
static void cx18_init_in_work_orders(struct cx18 *cx)
{
int i;
for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) {
cx->in_work_order[i].cx = cx;
cx->in_work_order[i].str = cx->epu_debug_str;
INIT_WORK(&cx->in_work_order[i].work, cx18_in_work_handler);
}
}
/* Precondition: the cx18 structure has been memset to 0. Only
the dev and instance fields have been filled in.
No assumptions on the card type may be made here (see cx18_init_struct2
for that).
*/
static int cx18_init_struct1(struct cx18 *cx)
{
int ret;
cx->base_addr = pci_resource_start(cx->pci_dev, 0);
mutex_init(&cx->serialize_lock);
mutex_init(&cx->gpio_lock);
mutex_init(&cx->epu2apu_mb_lock);
mutex_init(&cx->epu2cpu_mb_lock);
ret = cx18_create_in_workq(cx);
if (ret)
return ret;
cx18_init_in_work_orders(cx);
/* start counting open_id at 1 */
cx->open_id = 1;
/* Initial settings */
cx->cxhdl.port = CX2341X_PORT_MEMORY;
cx->cxhdl.capabilities = CX2341X_CAP_HAS_TS | CX2341X_CAP_HAS_SLICED_VBI;
cx->cxhdl.ops = &cx18_cxhdl_ops;
cx->cxhdl.func = cx18_api_func;
cx->cxhdl.priv = &cx->streams[CX18_ENC_STREAM_TYPE_MPG];
ret = cx2341x_handler_init(&cx->cxhdl, 50);
if (ret)
return ret;
cx->v4l2_dev.ctrl_handler = &cx->cxhdl.hdl;
cx->temporal_strength = cx->cxhdl.video_temporal_filter->cur.val;
cx->spatial_strength = cx->cxhdl.video_spatial_filter->cur.val;
cx->filter_mode = cx->cxhdl.video_spatial_filter_mode->cur.val |
(cx->cxhdl.video_temporal_filter_mode->cur.val << 1) |
(cx->cxhdl.video_median_filter_type->cur.val << 2);
init_waitqueue_head(&cx->cap_w);
init_waitqueue_head(&cx->mb_apu_waitq);
init_waitqueue_head(&cx->mb_cpu_waitq);
init_waitqueue_head(&cx->dma_waitq);
/* VBI */
cx->vbi.in.type = V4L2_BUF_TYPE_VBI_CAPTURE;
cx->vbi.sliced_in = &cx->vbi.in.fmt.sliced;
/* IVTV style VBI insertion into MPEG streams */
INIT_LIST_HEAD(&cx->vbi.sliced_mpeg_buf.list);
INIT_LIST_HEAD(&cx->vbi.sliced_mpeg_mdl.list);
INIT_LIST_HEAD(&cx->vbi.sliced_mpeg_mdl.buf_list);
list_add(&cx->vbi.sliced_mpeg_buf.list,
&cx->vbi.sliced_mpeg_mdl.buf_list);
return 0;
}
/* Second initialization part. Here the card type has been
autodetected. */
static void cx18_init_struct2(struct cx18 *cx)
{
int i;
for (i = 0; i < CX18_CARD_MAX_VIDEO_INPUTS; i++)
if (cx->card->video_inputs[i].video_type == 0)
break;
cx->nof_inputs = i;
for (i = 0; i < CX18_CARD_MAX_AUDIO_INPUTS; i++)
if (cx->card->audio_inputs[i].audio_type == 0)
break;
cx->nof_audio_inputs = i;
/* Find tuner input */
for (i = 0; i < cx->nof_inputs; i++) {
if (cx->card->video_inputs[i].video_type ==
CX18_CARD_INPUT_VID_TUNER)
break;
}
if (i == cx->nof_inputs)
i = 0;
cx->active_input = i;
cx->audio_input = cx->card->video_inputs[i].audio_index;
}
static int cx18_setup_pci(struct cx18 *cx, struct pci_dev *pci_dev,
const struct pci_device_id *pci_id)
{
u16 cmd;
unsigned char pci_latency;
CX18_DEBUG_INFO("Enabling pci device\n");
if (pci_enable_device(pci_dev)) {
CX18_ERR("Can't enable device %d!\n", cx->instance);
return -EIO;
}
if (dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) {
CX18_ERR("No suitable DMA available, card %d\n", cx->instance);
return -EIO;
}
if (!request_mem_region(cx->base_addr, CX18_MEM_SIZE, "cx18 encoder")) {
CX18_ERR("Cannot request encoder memory region, card %d\n",
cx->instance);
return -EIO;
}
/* Enable bus mastering and memory mapped IO for the CX23418 */
pci_read_config_word(pci_dev, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
pci_write_config_word(pci_dev, PCI_COMMAND, cmd);
cx->card_rev = pci_dev->revision;
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &pci_latency);
if (pci_latency < 64 && cx18_pci_latency) {
CX18_INFO("Unreasonably low latency timer, setting to 64 (was %d)\n",
pci_latency);
pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, 64);
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &pci_latency);
}
CX18_DEBUG_INFO("cx%d (rev %d) at %02x:%02x.%x, irq: %d, latency: %d, memory: 0x%llx\n",
cx->pci_dev->device, cx->card_rev, pci_dev->bus->number,
PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn),
cx->pci_dev->irq, pci_latency, (u64)cx->base_addr);
return 0;
}
static void cx18_init_subdevs(struct cx18 *cx)
{
u32 hw = cx->card->hw_all;
u32 device;
int i;
for (i = 0, device = 1; i < 32; i++, device <<= 1) {
if (!(device & hw))
continue;
switch (device) {
case CX18_HW_DVB:
case CX18_HW_TVEEPROM:
/* These subordinate devices do not use probing */
cx->hw_flags |= device;
break;
case CX18_HW_418_AV:
/* The A/V decoder gets probed earlier to set PLLs */
/* Just note that the card uses it (i.e. has analog) */
cx->hw_flags |= device;
break;
case CX18_HW_GPIO_RESET_CTRL:
/*
* The Reset Controller gets probed and added to
* hw_flags earlier for i2c adapter/bus initialization
*/
break;
case CX18_HW_GPIO_MUX:
if (cx18_gpio_register(cx, device) == 0)
cx->hw_flags |= device;
break;
default:
if (cx18_i2c_register(cx, i) == 0)
cx->hw_flags |= device;
break;
}
}
if (cx->hw_flags & CX18_HW_418_AV)
cx->sd_av = cx18_find_hw(cx, CX18_HW_418_AV);
if (cx->card->hw_muxer != 0)
cx->sd_extmux = cx18_find_hw(cx, cx->card->hw_muxer);
}
static int cx18_probe(struct pci_dev *pci_dev,
const struct pci_device_id *pci_id)
{
int retval = 0;
int i;
u32 devtype;
struct cx18 *cx;
/* FIXME - module parameter arrays constrain max instances */
i = atomic_inc_return(&cx18_instance) - 1;
if (i >= CX18_MAX_CARDS) {
printk(KERN_ERR "cx18: cannot manage card %d, driver has a limit of 0 - %d\n",
i, CX18_MAX_CARDS - 1);
return -ENOMEM;
}
cx = kzalloc(sizeof(*cx), GFP_KERNEL);
if (!cx)
return -ENOMEM;
cx->pci_dev = pci_dev;
cx->instance = i;
retval = v4l2_device_register(&pci_dev->dev, &cx->v4l2_dev);
if (retval) {
printk(KERN_ERR "cx18: v4l2_device_register of card %d failed\n",
cx->instance);
kfree(cx);
return retval;
}
snprintf(cx->v4l2_dev.name, sizeof(cx->v4l2_dev.name), "cx18-%d",
cx->instance);
CX18_INFO("Initializing card %d\n", cx->instance);
cx18_process_options(cx);
if (cx->options.cardtype == -1) {
retval = -ENODEV;
goto err;
}
retval = cx18_init_struct1(cx);
if (retval)
goto err;
CX18_DEBUG_INFO("base addr: 0x%llx\n", (u64)cx->base_addr);
/* PCI Device Setup */
retval = cx18_setup_pci(cx, pci_dev, pci_id);
if (retval != 0)
goto free_workqueues;
/* map io memory */
CX18_DEBUG_INFO("attempting ioremap at 0x%llx len 0x%08x\n",
(u64)cx->base_addr + CX18_MEM_OFFSET, CX18_MEM_SIZE);
cx->enc_mem = ioremap(cx->base_addr + CX18_MEM_OFFSET,
CX18_MEM_SIZE);
if (!cx->enc_mem) {
CX18_ERR("ioremap failed. Can't get a window into CX23418 memory and register space\n");
CX18_ERR("Each capture card with a CX23418 needs 64 MB of vmalloc address space for the window\n");
CX18_ERR("Check the output of 'grep Vmalloc /proc/meminfo'\n");
CX18_ERR("Use the vmalloc= kernel command line option to set VmallocTotal to a larger value\n");
retval = -ENOMEM;
goto free_mem;
}
cx->reg_mem = cx->enc_mem + CX18_REG_OFFSET;
devtype = cx18_read_reg(cx, 0xC72028);
switch (devtype & 0xff000000) {
case 0xff000000:
CX18_INFO("cx23418 revision %08x (A)\n", devtype);
break;
case 0x01000000:
CX18_INFO("cx23418 revision %08x (B)\n", devtype);
break;
default:
CX18_INFO("cx23418 revision %08x (Unknown)\n", devtype);
break;
}
cx18_init_power(cx, 1);
cx18_init_memory(cx);
cx->scb = (struct cx18_scb __iomem *)(cx->enc_mem + SCB_OFFSET);
cx18_init_scb(cx);
cx18_gpio_init(cx);
/* Initialize integrated A/V decoder early to set PLLs, just in case */
retval = cx18_av_probe(cx);
if (retval) {
CX18_ERR("Could not register A/V decoder subdevice\n");
goto free_map;
}
/* Initialize GPIO Reset Controller to do chip resets during i2c init */
if (cx->card->hw_all & CX18_HW_GPIO_RESET_CTRL) {
if (cx18_gpio_register(cx, CX18_HW_GPIO_RESET_CTRL) != 0)
CX18_WARN("Could not register GPIO reset controllersubdevice; proceeding anyway.\n");
else
cx->hw_flags |= CX18_HW_GPIO_RESET_CTRL;
}
/* active i2c */
CX18_DEBUG_INFO("activating i2c...\n");
retval = init_cx18_i2c(cx);
if (retval) {
CX18_ERR("Could not initialize i2c\n");
goto free_map;
}
if (cx->card->hw_all & CX18_HW_TVEEPROM) {
/* Based on the model number the cardtype may be changed.
The PCI IDs are not always reliable. */
const struct cx18_card *orig_card = cx->card;
cx18_process_eeprom(cx);
if (cx->card != orig_card) {
/* Changed the cardtype; re-reset the I2C chips */
cx18_gpio_init(cx);
cx18_call_hw(cx, CX18_HW_GPIO_RESET_CTRL,
core, reset, (u32) CX18_GPIO_RESET_I2C);
}
}
if (cx->card->comment)
CX18_INFO("%s", cx->card->comment);
if (cx->card->v4l2_capabilities == 0) {
retval = -ENODEV;
goto free_i2c;
}
cx18_init_memory(cx);
cx18_init_scb(cx);
/* Register IRQ */
retval = request_irq(cx->pci_dev->irq, cx18_irq_handler,
IRQF_SHARED, cx->v4l2_dev.name, (void *)cx);
if (retval) {
CX18_ERR("Failed to register irq %d\n", retval);
goto free_i2c;
}
if (cx->std == 0)
cx->std = V4L2_STD_NTSC_M;
if (cx->options.tuner == -1) {
for (i = 0; i < CX18_CARD_MAX_TUNERS; i++) {
if ((cx->std & cx->card->tuners[i].std) == 0)
continue;
cx->options.tuner = cx->card->tuners[i].tuner;
break;
}
}
/* if no tuner was found, then pick the first tuner in the card list */
if (cx->options.tuner == -1 && cx->card->tuners[0].std) {
cx->std = cx->card->tuners[0].std;
if (cx->std & V4L2_STD_PAL)
cx->std = V4L2_STD_PAL_BG | V4L2_STD_PAL_H;
else if (cx->std & V4L2_STD_NTSC)
cx->std = V4L2_STD_NTSC_M;
else if (cx->std & V4L2_STD_SECAM)
cx->std = V4L2_STD_SECAM_L;
cx->options.tuner = cx->card->tuners[0].tuner;
}
if (cx->options.radio == -1)
cx->options.radio = (cx->card->radio_input.audio_type != 0);
/* The card is now fully identified, continue with card-specific
initialization. */
cx18_init_struct2(cx);
cx18_init_subdevs(cx);
if (cx->std & V4L2_STD_525_60)
cx->is_60hz = 1;
else
cx->is_50hz = 1;
cx2341x_handler_set_50hz(&cx->cxhdl, !cx->is_60hz);
if (cx->options.radio > 0)
cx->v4l2_cap |= V4L2_CAP_RADIO;
if (cx->options.tuner > -1) {
struct tuner_setup setup;
setup.addr = ADDR_UNSET;
setup.type = cx->options.tuner;
setup.mode_mask = T_ANALOG_TV; /* matches TV tuners */
setup.config = NULL;
if (cx->options.radio > 0)
setup.mode_mask |= T_RADIO;
setup.tuner_callback = (setup.type == TUNER_XC2028) ?
cx18_reset_tuner_gpio : NULL;
cx18_call_all(cx, tuner, s_type_addr, &setup);
if (setup.type == TUNER_XC2028) {
static struct xc2028_ctrl ctrl = {
.fname = XC2028_DEFAULT_FIRMWARE,
.max_len = 64,
};
struct v4l2_priv_tun_config cfg = {
.tuner = cx->options.tuner,
.priv = &ctrl,
};
cx18_call_all(cx, tuner, s_config, &cfg);
}
}
/* The tuner is fixed to the standard. The other inputs (e.g. S-Video)
are not. */
cx->tuner_std = cx->std;
if (cx->std == V4L2_STD_ALL)
cx->std = V4L2_STD_NTSC_M;
retval = cx18_streams_setup(cx);
if (retval) {
CX18_ERR("Error %d setting up streams\n", retval);
goto free_irq;
}
retval = cx18_streams_register(cx);
if (retval) {
CX18_ERR("Error %d registering devices\n", retval);
goto free_streams;
}
CX18_INFO("Initialized card: %s\n", cx->card_name);
/* Load cx18 submodules (cx18-alsa) */
request_modules(cx);
return 0;
free_streams:
cx18_streams_cleanup(cx, 1);
free_irq:
free_irq(cx->pci_dev->irq, (void *)cx);
free_i2c:
exit_cx18_i2c(cx);
free_map:
cx18_iounmap(cx);
free_mem:
release_mem_region(cx->base_addr, CX18_MEM_SIZE);
free_workqueues:
destroy_workqueue(cx->in_work_queue);
err:
CX18_ERR("Error %d on initialization\n", retval);
v4l2_device_unregister(&cx->v4l2_dev);
kfree(cx);
return retval;
}
int cx18_init_on_first_open(struct cx18 *cx)
{
int video_input;
int fw_retry_count = 3;
struct v4l2_frequency vf;
struct cx18_open_id fh;
v4l2_std_id std;
fh.cx = cx;
if (test_bit(CX18_F_I_FAILED, &cx->i_flags))
return -ENXIO;
if (test_and_set_bit(CX18_F_I_INITED, &cx->i_flags))
return 0;
while (--fw_retry_count > 0) {
/* load firmware */
if (cx18_firmware_init(cx) == 0)
break;
if (fw_retry_count > 1)
CX18_WARN("Retry loading firmware\n");
}
if (fw_retry_count == 0) {
set_bit(CX18_F_I_FAILED, &cx->i_flags);
return -ENXIO;
}
set_bit(CX18_F_I_LOADED_FW, &cx->i_flags);
/*
* Init the firmware twice to work around a silicon bug
* with the digital TS.
*
* The second firmware load requires us to normalize the APU state,
* or the audio for the first analog capture will be badly incorrect.
*
* I can't seem to call APU_RESETAI and have it succeed without the
* APU capturing audio, so we start and stop it here to do the reset
*/
/* MPEG Encoding, 224 kbps, MPEG Layer II, 48 ksps */
cx18_vapi(cx, CX18_APU_START, 2, CX18_APU_ENCODING_METHOD_MPEG|0xb9, 0);
cx18_vapi(cx, CX18_APU_RESETAI, 0);
cx18_vapi(cx, CX18_APU_STOP, 1, CX18_APU_ENCODING_METHOD_MPEG);
fw_retry_count = 3;
while (--fw_retry_count > 0) {
/* load firmware */
if (cx18_firmware_init(cx) == 0)
break;
if (fw_retry_count > 1)
CX18_WARN("Retry loading firmware\n");
}
if (fw_retry_count == 0) {
set_bit(CX18_F_I_FAILED, &cx->i_flags);
return -ENXIO;
}
/*
* The second firmware load requires us to normalize the APU state,
* or the audio for the first analog capture will be badly incorrect.
*
* I can't seem to call APU_RESETAI and have it succeed without the
* APU capturing audio, so we start and stop it here to do the reset
*/
/* MPEG Encoding, 224 kbps, MPEG Layer II, 48 ksps */
cx18_vapi(cx, CX18_APU_START, 2, CX18_APU_ENCODING_METHOD_MPEG|0xb9, 0);
cx18_vapi(cx, CX18_APU_RESETAI, 0);
cx18_vapi(cx, CX18_APU_STOP, 1, CX18_APU_ENCODING_METHOD_MPEG);
/* Init the A/V decoder, if it hasn't been already */
v4l2_subdev_call(cx->sd_av, core, load_fw);
vf.tuner = 0;
vf.type = V4L2_TUNER_ANALOG_TV;
vf.frequency = 6400; /* the tuner 'baseline' frequency */
/* Set initial frequency. For PAL/SECAM broadcasts no
'default' channel exists AFAIK. */
if (cx->std == V4L2_STD_NTSC_M_JP)
vf.frequency = 1460; /* ch. 1 91250*16/1000 */
else if (cx->std & V4L2_STD_NTSC_M)
vf.frequency = 1076; /* ch. 4 67250*16/1000 */
video_input = cx->active_input;
cx->active_input++; /* Force update of input */
cx18_s_input(NULL, &fh, video_input);
/* Let the VIDIOC_S_STD ioctl do all the work, keeps the code
in one place. */
cx->std++; /* Force full standard initialization */
std = (cx->tuner_std == V4L2_STD_ALL) ? V4L2_STD_NTSC_M : cx->tuner_std;
cx18_s_std(NULL, &fh, std);
cx18_s_frequency(NULL, &fh, &vf);
return 0;
}
static void cx18_cancel_in_work_orders(struct cx18 *cx)
{
int i;
for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++)
cancel_work_sync(&cx->in_work_order[i].work);
}
static void cx18_cancel_out_work_orders(struct cx18 *cx)
{
int i;
for (i = 0; i < CX18_MAX_STREAMS; i++)
if (cx->streams[i].video_dev.v4l2_dev)
cancel_work_sync(&cx->streams[i].out_work_order);
}
static void cx18_remove(struct pci_dev *pci_dev)
{
struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
struct cx18 *cx = to_cx18(v4l2_dev);
int i;
CX18_DEBUG_INFO("Removing Card\n");
flush_request_modules(cx);
/* Stop all captures */
CX18_DEBUG_INFO("Stopping all streams\n");
if (atomic_read(&cx->tot_capturing) > 0)
cx18_stop_all_captures(cx);
/* Stop interrupts that cause incoming work to be queued */
cx18_sw1_irq_disable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
/* Incoming work can cause outgoing work, so clean up incoming first */
cx18_cancel_in_work_orders(cx);
cx18_cancel_out_work_orders(cx);
/* Stop ack interrupts that may have been needed for work to finish */
cx18_sw2_irq_disable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
cx18_halt_firmware(cx);
destroy_workqueue(cx->in_work_queue);
cx18_streams_cleanup(cx, 1);
exit_cx18_i2c(cx);
free_irq(cx->pci_dev->irq, (void *)cx);
cx18_iounmap(cx);
release_mem_region(cx->base_addr, CX18_MEM_SIZE);
pci_disable_device(cx->pci_dev);
if (cx->vbi.sliced_mpeg_data[0])
for (i = 0; i < CX18_VBI_FRAMES; i++)
kfree(cx->vbi.sliced_mpeg_data[i]);
v4l2_ctrl_handler_free(&cx->av_state.hdl);
CX18_INFO("Removed %s\n", cx->card_name);
v4l2_device_unregister(v4l2_dev);
kfree(cx);
}
/* define a pci_driver for card detection */
static struct pci_driver cx18_pci_driver = {
.name = "cx18",
.id_table = cx18_pci_tbl,
.probe = cx18_probe,
.remove = cx18_remove,
};
static int __init module_start(void)
{
printk(KERN_INFO "cx18: Start initialization, version %s\n",
CX18_VERSION);
/* Validate parameters */
if (cx18_first_minor < 0 || cx18_first_minor >= CX18_MAX_CARDS) {
printk(KERN_ERR "cx18: Exiting, cx18_first_minor must be between 0 and %d\n",
CX18_MAX_CARDS - 1);
return -1;
}
if (cx18_debug < 0 || cx18_debug > 511) {
cx18_debug = 0;
printk(KERN_INFO "cx18: Debug value must be >= 0 and <= 511!\n");
}
if (pci_register_driver(&cx18_pci_driver)) {
printk(KERN_ERR "cx18: Error detecting PCI card\n");
return -ENODEV;
}
printk(KERN_INFO "cx18: End initialization\n");
return 0;
}
static void __exit module_cleanup(void)
{
pci_unregister_driver(&cx18_pci_driver);
}
module_init(module_start);
module_exit(module_cleanup);
MODULE_FIRMWARE(XC2028_DEFAULT_FIRMWARE);
| linux-master | drivers/media/pci/cx18/cx18-driver.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 ADEC VBI functions
*
* Derived from cx25840-vbi.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
*/
#include "cx18-driver.h"
/*
* For sliced VBI output, we set up to use VIP-1.1, 8-bit mode,
* NN counts 1 byte Dwords, an IDID with the VBI line # in it.
* Thus, according to the VIP-2 Spec, our VBI ancillary data lines
* (should!) look like:
* 4 byte EAV code: 0xff 0x00 0x00 0xRP
* unknown number of possible idle bytes
* 3 byte Anc data preamble: 0x00 0xff 0xff
* 1 byte data identifier: ne010iii (parity bits, 010, DID bits)
* 1 byte secondary data id: nessssss (parity bits, SDID bits)
* 1 byte data word count: necccccc (parity bits, NN Dword count)
* 2 byte Internal DID: VBI-line-# 0x80
* NN data bytes
* 1 byte checksum
* Fill bytes needed to fil out to 4*NN bytes of payload
*
* The RP codes for EAVs when in VIP-1.1 mode, not in raw mode, &
* in the vertical blanking interval are:
* 0xb0 (Task 0 VerticalBlank HorizontalBlank 0 0 0 0)
* 0xf0 (Task EvenField VerticalBlank HorizontalBlank 0 0 0 0)
*
* Since the V bit is only allowed to toggle in the EAV RP code, just
* before the first active region line and for active lines, they are:
* 0x90 (Task 0 0 HorizontalBlank 0 0 0 0)
* 0xd0 (Task EvenField 0 HorizontalBlank 0 0 0 0)
*
* The user application DID bytes we care about are:
* 0x91 (1 0 010 0 !ActiveLine AncDataPresent)
* 0x55 (0 1 010 2ndField !ActiveLine AncDataPresent)
*
*/
static const u8 sliced_vbi_did[2] = { 0x91, 0x55 };
struct vbi_anc_data {
/* u8 eav[4]; */
/* u8 idle[]; Variable number of idle bytes */
u8 preamble[3];
u8 did;
u8 sdid;
u8 data_count;
u8 idid[2];
u8 payload[]; /* data_count of payload */
/* u8 checksum; */
/* u8 fill[]; Variable number of fill bytes */
};
static int odd_parity(u8 c)
{
c ^= (c >> 4);
c ^= (c >> 2);
c ^= (c >> 1);
return c & 1;
}
static int decode_vps(u8 *dst, u8 *p)
{
static const u8 biphase_tbl[] = {
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
};
u8 c, err = 0;
int i;
for (i = 0; i < 2 * 13; i += 2) {
err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
c = (biphase_tbl[p[i + 1]] & 0xf) |
((biphase_tbl[p[i]] & 0xf) << 4);
dst[i / 2] = c;
}
return err & 0xf0;
}
int cx18_av_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
struct cx18_av_state *state = &cx->av_state;
static const u16 lcr2vbi[] = {
0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */
0, V4L2_SLICED_WSS_625, 0, /* 4 */
V4L2_SLICED_CAPTION_525, /* 6 */
0, 0, V4L2_SLICED_VPS, 0, 0, /* 9 */
0, 0, 0, 0
};
int is_pal = !(state->std & V4L2_STD_525_60);
int i;
memset(svbi->service_lines, 0, sizeof(svbi->service_lines));
svbi->service_set = 0;
/* we're done if raw VBI is active */
if ((cx18_av_read(cx, 0x404) & 0x10) == 0)
return 0;
if (is_pal) {
for (i = 7; i <= 23; i++) {
u8 v = cx18_av_read(cx, 0x424 + i - 7);
svbi->service_lines[0][i] = lcr2vbi[v >> 4];
svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
svbi->service_set |= svbi->service_lines[0][i] |
svbi->service_lines[1][i];
}
} else {
for (i = 10; i <= 21; i++) {
u8 v = cx18_av_read(cx, 0x424 + i - 10);
svbi->service_lines[0][i] = lcr2vbi[v >> 4];
svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
svbi->service_set |= svbi->service_lines[0][i] |
svbi->service_lines[1][i];
}
}
return 0;
}
int cx18_av_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
struct cx18_av_state *state = &cx->av_state;
/* Setup standard */
cx18_av_std_setup(cx);
/* VBI Offset */
cx18_av_write(cx, 0x47f, state->slicer_line_delay);
cx18_av_write(cx, 0x404, 0x2e);
return 0;
}
int cx18_av_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
struct cx18_av_state *state = &cx->av_state;
int is_pal = !(state->std & V4L2_STD_525_60);
int i, x;
u8 lcr[24];
for (x = 0; x <= 23; x++)
lcr[x] = 0x00;
/* Setup standard */
cx18_av_std_setup(cx);
/* Sliced VBI */
cx18_av_write(cx, 0x404, 0x32); /* Ancillary data */
cx18_av_write(cx, 0x406, 0x13);
cx18_av_write(cx, 0x47f, state->slicer_line_delay);
/* Force impossible lines to 0 */
if (is_pal) {
for (i = 0; i <= 6; i++)
svbi->service_lines[0][i] =
svbi->service_lines[1][i] = 0;
} else {
for (i = 0; i <= 9; i++)
svbi->service_lines[0][i] =
svbi->service_lines[1][i] = 0;
for (i = 22; i <= 23; i++)
svbi->service_lines[0][i] =
svbi->service_lines[1][i] = 0;
}
/* Build register values for requested service lines */
for (i = 7; i <= 23; i++) {
for (x = 0; x <= 1; x++) {
switch (svbi->service_lines[1-x][i]) {
case V4L2_SLICED_TELETEXT_B:
lcr[i] |= 1 << (4 * x);
break;
case V4L2_SLICED_WSS_625:
lcr[i] |= 4 << (4 * x);
break;
case V4L2_SLICED_CAPTION_525:
lcr[i] |= 6 << (4 * x);
break;
case V4L2_SLICED_VPS:
lcr[i] |= 9 << (4 * x);
break;
}
}
}
if (is_pal) {
for (x = 1, i = 0x424; i <= 0x434; i++, x++)
cx18_av_write(cx, i, lcr[6 + x]);
} else {
for (x = 1, i = 0x424; i <= 0x430; i++, x++)
cx18_av_write(cx, i, lcr[9 + x]);
for (i = 0x431; i <= 0x434; i++)
cx18_av_write(cx, i, 0);
}
cx18_av_write(cx, 0x43c, 0x16);
/* Should match vblank set in cx18_av_std_setup() */
cx18_av_write(cx, 0x474, is_pal ? 38 : 26);
return 0;
}
int cx18_av_decode_vbi_line(struct v4l2_subdev *sd,
struct v4l2_decode_vbi_line *vbi)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
struct cx18_av_state *state = &cx->av_state;
struct vbi_anc_data *anc = (struct vbi_anc_data *)vbi->p;
u8 *p;
int did, sdid, l, err = 0;
/*
* Check for the ancillary data header for sliced VBI
*/
if (anc->preamble[0] ||
anc->preamble[1] != 0xff || anc->preamble[2] != 0xff ||
(anc->did != sliced_vbi_did[0] &&
anc->did != sliced_vbi_did[1])) {
vbi->line = vbi->type = 0;
return 0;
}
did = anc->did;
sdid = anc->sdid & 0xf;
l = anc->idid[0] & 0x3f;
l += state->slicer_line_offset;
p = anc->payload;
/* Decode the SDID set by the slicer */
switch (sdid) {
case 1:
sdid = V4L2_SLICED_TELETEXT_B;
break;
case 4:
sdid = V4L2_SLICED_WSS_625;
break;
case 6:
sdid = V4L2_SLICED_CAPTION_525;
err = !odd_parity(p[0]) || !odd_parity(p[1]);
break;
case 9:
sdid = V4L2_SLICED_VPS;
if (decode_vps(p, p) != 0)
err = 1;
break;
default:
sdid = 0;
err = 1;
break;
}
vbi->type = err ? 0 : sdid;
vbi->line = err ? 0 : l;
vbi->is_second_field = err ? 0 : (did == sliced_vbi_did[1]);
vbi->p = p;
return 0;
}
| linux-master | drivers/media/pci/cx18/cx18-av-vbi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 System Control Block initialization
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-scb.h"
void cx18_init_scb(struct cx18 *cx)
{
cx18_setup_page(cx, SCB_OFFSET);
cx18_memset_io(cx, cx->scb, 0, 0x10000);
cx18_writel(cx, IRQ_APU_TO_CPU, &cx->scb->apu2cpu_irq);
cx18_writel(cx, IRQ_CPU_TO_APU_ACK, &cx->scb->cpu2apu_irq_ack);
cx18_writel(cx, IRQ_HPU_TO_CPU, &cx->scb->hpu2cpu_irq);
cx18_writel(cx, IRQ_CPU_TO_HPU_ACK, &cx->scb->cpu2hpu_irq_ack);
cx18_writel(cx, IRQ_PPU_TO_CPU, &cx->scb->ppu2cpu_irq);
cx18_writel(cx, IRQ_CPU_TO_PPU_ACK, &cx->scb->cpu2ppu_irq_ack);
cx18_writel(cx, IRQ_EPU_TO_CPU, &cx->scb->epu2cpu_irq);
cx18_writel(cx, IRQ_CPU_TO_EPU_ACK, &cx->scb->cpu2epu_irq_ack);
cx18_writel(cx, IRQ_CPU_TO_APU, &cx->scb->cpu2apu_irq);
cx18_writel(cx, IRQ_APU_TO_CPU_ACK, &cx->scb->apu2cpu_irq_ack);
cx18_writel(cx, IRQ_HPU_TO_APU, &cx->scb->hpu2apu_irq);
cx18_writel(cx, IRQ_APU_TO_HPU_ACK, &cx->scb->apu2hpu_irq_ack);
cx18_writel(cx, IRQ_PPU_TO_APU, &cx->scb->ppu2apu_irq);
cx18_writel(cx, IRQ_APU_TO_PPU_ACK, &cx->scb->apu2ppu_irq_ack);
cx18_writel(cx, IRQ_EPU_TO_APU, &cx->scb->epu2apu_irq);
cx18_writel(cx, IRQ_APU_TO_EPU_ACK, &cx->scb->apu2epu_irq_ack);
cx18_writel(cx, IRQ_CPU_TO_HPU, &cx->scb->cpu2hpu_irq);
cx18_writel(cx, IRQ_HPU_TO_CPU_ACK, &cx->scb->hpu2cpu_irq_ack);
cx18_writel(cx, IRQ_APU_TO_HPU, &cx->scb->apu2hpu_irq);
cx18_writel(cx, IRQ_HPU_TO_APU_ACK, &cx->scb->hpu2apu_irq_ack);
cx18_writel(cx, IRQ_PPU_TO_HPU, &cx->scb->ppu2hpu_irq);
cx18_writel(cx, IRQ_HPU_TO_PPU_ACK, &cx->scb->hpu2ppu_irq_ack);
cx18_writel(cx, IRQ_EPU_TO_HPU, &cx->scb->epu2hpu_irq);
cx18_writel(cx, IRQ_HPU_TO_EPU_ACK, &cx->scb->hpu2epu_irq_ack);
cx18_writel(cx, IRQ_CPU_TO_PPU, &cx->scb->cpu2ppu_irq);
cx18_writel(cx, IRQ_PPU_TO_CPU_ACK, &cx->scb->ppu2cpu_irq_ack);
cx18_writel(cx, IRQ_APU_TO_PPU, &cx->scb->apu2ppu_irq);
cx18_writel(cx, IRQ_PPU_TO_APU_ACK, &cx->scb->ppu2apu_irq_ack);
cx18_writel(cx, IRQ_HPU_TO_PPU, &cx->scb->hpu2ppu_irq);
cx18_writel(cx, IRQ_PPU_TO_HPU_ACK, &cx->scb->ppu2hpu_irq_ack);
cx18_writel(cx, IRQ_EPU_TO_PPU, &cx->scb->epu2ppu_irq);
cx18_writel(cx, IRQ_PPU_TO_EPU_ACK, &cx->scb->ppu2epu_irq_ack);
cx18_writel(cx, IRQ_CPU_TO_EPU, &cx->scb->cpu2epu_irq);
cx18_writel(cx, IRQ_EPU_TO_CPU_ACK, &cx->scb->epu2cpu_irq_ack);
cx18_writel(cx, IRQ_APU_TO_EPU, &cx->scb->apu2epu_irq);
cx18_writel(cx, IRQ_EPU_TO_APU_ACK, &cx->scb->epu2apu_irq_ack);
cx18_writel(cx, IRQ_HPU_TO_EPU, &cx->scb->hpu2epu_irq);
cx18_writel(cx, IRQ_EPU_TO_HPU_ACK, &cx->scb->epu2hpu_irq_ack);
cx18_writel(cx, IRQ_PPU_TO_EPU, &cx->scb->ppu2epu_irq);
cx18_writel(cx, IRQ_EPU_TO_PPU_ACK, &cx->scb->epu2ppu_irq_ack);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2cpu_mb),
&cx->scb->apu2cpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2cpu_mb),
&cx->scb->hpu2cpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2cpu_mb),
&cx->scb->ppu2cpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2cpu_mb),
&cx->scb->epu2cpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2apu_mb),
&cx->scb->cpu2apu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2apu_mb),
&cx->scb->hpu2apu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2apu_mb),
&cx->scb->ppu2apu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2apu_mb),
&cx->scb->epu2apu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2hpu_mb),
&cx->scb->cpu2hpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2hpu_mb),
&cx->scb->apu2hpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2hpu_mb),
&cx->scb->ppu2hpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2hpu_mb),
&cx->scb->epu2hpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2ppu_mb),
&cx->scb->cpu2ppu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2ppu_mb),
&cx->scb->apu2ppu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2ppu_mb),
&cx->scb->hpu2ppu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2ppu_mb),
&cx->scb->epu2ppu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2epu_mb),
&cx->scb->cpu2epu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2epu_mb),
&cx->scb->apu2epu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2epu_mb),
&cx->scb->hpu2epu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2epu_mb),
&cx->scb->ppu2epu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu_state),
&cx->scb->ipc_offset);
cx18_writel(cx, 1, &cx->scb->epu_state);
}
| linux-master | drivers/media/pci/cx18/cx18-scb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 ADEC audio functions
*
* Derived from cx25840-audio.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
static int set_audclk_freq(struct cx18 *cx, u32 freq)
{
struct cx18_av_state *state = &cx->av_state;
if (freq != 32000 && freq != 44100 && freq != 48000)
return -EINVAL;
/*
* The PLL parameters are based on the external crystal frequency that
* would ideally be:
*
* NTSC Color subcarrier freq * 8 =
* 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
*
* The accidents of history and rationale that explain from where this
* combination of magic numbers originate can be found in:
*
* [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in
* the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80
*
* [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the
* NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83
*
* As Mike Bradley has rightly pointed out, it's not the exact crystal
* frequency that matters, only that all parts of the driver and
* firmware are using the same value (close to the ideal value).
*
* Since I have a strong suspicion that, if the firmware ever assumes a
* crystal value at all, it will assume 28.636360 MHz, the crystal
* freq used in calculations in this driver will be:
*
* xtal_freq = 28.636360 MHz
*
* an error of less than 0.13 ppm which is way, way better than any off
* the shelf crystal will have for accuracy anyway.
*
* Below I aim to run the PLLs' VCOs near 400 MHz to minimize error.
*
* Many thanks to Jeff Campbell and Mike Bradley for their extensive
* investigation, experimentation, testing, and suggested solutions of
* audio/video sync problems with SVideo and CVBS captures.
*/
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
switch (freq) {
case 32000:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20
*/
cx18_av_write4(cx, 0x108, 0x200d040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x176740c */
/* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x0176740c);
/* src3/4/6_ctl */
/* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */
cx18_av_write4(cx, 0x900, 0x0801f77f);
cx18_av_write4(cx, 0x904, 0x0801f77f);
cx18_av_write4(cx, 0x90c, 0x0801f77f);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */
cx18_av_write(cx, 0x127, 0x60);
/* AUD_COUNT = 0x2fff = 8 samples * 4 * 384 - 1 */
cx18_av_write4(cx, 0x12c, 0x11202fff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x0d2ef8 = 107999.000 * 8 =
* ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa00d2ef8);
break;
case 44100:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x18
*/
cx18_av_write4(cx, 0x108, 0x180e040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x062a1f2 */
/* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x0062a1f2);
/* src3/4/6_ctl */
/* 0x1.6d59 = (4 * xtal/8*2/455) / 44100 */
cx18_av_write4(cx, 0x900, 0x08016d59);
cx18_av_write4(cx, 0x904, 0x08016d59);
cx18_av_write4(cx, 0x90c, 0x08016d59);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x18 */
cx18_av_write(cx, 0x127, 0x58);
/* AUD_COUNT = 0x92ff = 49 samples * 2 * 384 - 1 */
cx18_av_write4(cx, 0x12c, 0x112092ff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x1d4bf8 = 239999.000 * 8 =
* ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa01d4bf8);
break;
case 48000:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x16
*/
cx18_av_write4(cx, 0x108, 0x160e040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x05227ad */
/* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x005227ad);
/* src3/4/6_ctl */
/* 0x1.4faa = (4 * xtal/8*2/455) / 48000 */
cx18_av_write4(cx, 0x900, 0x08014faa);
cx18_av_write4(cx, 0x904, 0x08014faa);
cx18_av_write4(cx, 0x90c, 0x08014faa);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
cx18_av_write(cx, 0x127, 0x56);
/* AUD_COUNT = 0x5fff = 4 samples * 16 * 384 - 1 */
cx18_av_write4(cx, 0x12c, 0x11205fff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x1193f8 = 143999.000 * 8 =
* ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa01193f8);
break;
}
} else {
switch (freq) {
case 32000:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x30
*/
cx18_av_write4(cx, 0x108, 0x300d040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x176740c */
/* xtal * 0xd.bb3a060/0x30 = 32000 * 256: 393 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x0176740c);
/* src1_ctl */
/* 0x1.0000 = 32000/32000 */
cx18_av_write4(cx, 0x8f8, 0x08010000);
/* src3/4/6_ctl */
/* 0x2.0000 = 2 * (32000/32000) */
cx18_av_write4(cx, 0x900, 0x08020000);
cx18_av_write4(cx, 0x904, 0x08020000);
cx18_av_write4(cx, 0x90c, 0x08020000);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x30 */
cx18_av_write(cx, 0x127, 0x70);
/* AUD_COUNT = 0x1fff = 8 samples * 4 * 256 - 1 */
cx18_av_write4(cx, 0x12c, 0x11201fff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x0d2ef8 = 107999.000 * 8 =
* ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa00d2ef8);
break;
case 44100:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x24
*/
cx18_av_write4(cx, 0x108, 0x240e040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x062a1f2 */
/* xtal * 0xe.3150f90/0x24 = 44100 * 256: 406 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x0062a1f2);
/* src1_ctl */
/* 0x1.60cd = 44100/32000 */
cx18_av_write4(cx, 0x8f8, 0x080160cd);
/* src3/4/6_ctl */
/* 0x1.7385 = 2 * (32000/44100) */
cx18_av_write4(cx, 0x900, 0x08017385);
cx18_av_write4(cx, 0x904, 0x08017385);
cx18_av_write4(cx, 0x90c, 0x08017385);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x24 */
cx18_av_write(cx, 0x127, 0x64);
/* AUD_COUNT = 0x61ff = 49 samples * 2 * 256 - 1 */
cx18_av_write4(cx, 0x12c, 0x112061ff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x1d4bf8 = 239999.000 * 8 =
* ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa01d4bf8);
break;
case 48000:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20
*/
cx18_av_write4(cx, 0x108, 0x200d040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x176740c */
/* xtal * 0xd.bb3a060/0x20 = 48000 * 256: 393 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x0176740c);
/* src1_ctl */
/* 0x1.8000 = 48000/32000 */
cx18_av_write4(cx, 0x8f8, 0x08018000);
/* src3/4/6_ctl */
/* 0x1.5555 = 2 * (32000/48000) */
cx18_av_write4(cx, 0x900, 0x08015555);
cx18_av_write4(cx, 0x904, 0x08015555);
cx18_av_write4(cx, 0x90c, 0x08015555);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */
cx18_av_write(cx, 0x127, 0x60);
/* AUD_COUNT = 0x3fff = 4 samples * 16 * 256 - 1 */
cx18_av_write4(cx, 0x12c, 0x11203fff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x1193f8 = 143999.000 * 8 =
* ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa01193f8);
break;
}
}
state->audclk_freq = freq;
return 0;
}
void cx18_av_audio_set_path(struct cx18 *cx)
{
struct cx18_av_state *state = &cx->av_state;
u8 v;
/* stop microcontroller */
v = cx18_av_read(cx, 0x803) & ~0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
/* assert soft reset */
v = cx18_av_read(cx, 0x810) | 0x01;
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
/* Mute everything to prevent the PFFT! */
cx18_av_write(cx, 0x8d3, 0x1f);
if (state->aud_input <= CX18_AV_AUDIO_SERIAL2) {
/* Set Path1 to Serial Audio Input */
cx18_av_write4(cx, 0x8d0, 0x01011012);
/* The microcontroller should not be started for the
* non-tuner inputs: autodetection is specific for
* TV audio. */
} else {
/* Set Path1 to Analog Demod Main Channel */
cx18_av_write4(cx, 0x8d0, 0x1f063870);
}
set_audclk_freq(cx, state->audclk_freq);
/* deassert soft reset */
v = cx18_av_read(cx, 0x810) & ~0x01;
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
/* When the microcontroller detects the
* audio format, it will unmute the lines */
v = cx18_av_read(cx, 0x803) | 0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
}
}
static void set_volume(struct cx18 *cx, int volume)
{
/* First convert the volume to msp3400 values (0-127) */
int vol = volume >> 9;
/* now scale it up to cx18_av values
* -114dB to -96dB maps to 0
* this should be 19, but in my testing that was 4dB too loud */
if (vol <= 23)
vol = 0;
else
vol -= 23;
/* PATH1_VOLUME */
cx18_av_write(cx, 0x8d4, 228 - (vol * 2));
}
static void set_bass(struct cx18 *cx, int bass)
{
/* PATH1_EQ_BASS_VOL */
cx18_av_and_or(cx, 0x8d9, ~0x3f, 48 - (bass * 48 / 0xffff));
}
static void set_treble(struct cx18 *cx, int treble)
{
/* PATH1_EQ_TREBLE_VOL */
cx18_av_and_or(cx, 0x8db, ~0x3f, 48 - (treble * 48 / 0xffff));
}
static void set_balance(struct cx18 *cx, int balance)
{
int bal = balance >> 8;
if (bal > 0x80) {
/* PATH1_BAL_LEFT */
cx18_av_and_or(cx, 0x8d5, 0x7f, 0x80);
/* PATH1_BAL_LEVEL */
cx18_av_and_or(cx, 0x8d5, ~0x7f, bal & 0x7f);
} else {
/* PATH1_BAL_LEFT */
cx18_av_and_or(cx, 0x8d5, 0x7f, 0x00);
/* PATH1_BAL_LEVEL */
cx18_av_and_or(cx, 0x8d5, ~0x7f, 0x80 - bal);
}
}
static void set_mute(struct cx18 *cx, int mute)
{
struct cx18_av_state *state = &cx->av_state;
u8 v;
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
/* Must turn off microcontroller in order to mute sound.
* Not sure if this is the best method, but it does work.
* If the microcontroller is running, then it will undo any
* changes to the mute register. */
v = cx18_av_read(cx, 0x803);
if (mute) {
/* disable microcontroller */
v &= ~0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
cx18_av_write(cx, 0x8d3, 0x1f);
} else {
/* enable microcontroller */
v |= 0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
}
} else {
/* SRC1_MUTE_EN */
cx18_av_and_or(cx, 0x8d3, ~0x2, mute ? 0x02 : 0x00);
}
}
int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
struct cx18_av_state *state = &cx->av_state;
int retval;
u8 v;
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
v = cx18_av_read(cx, 0x803) & ~0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
cx18_av_write(cx, 0x8d3, 0x1f);
}
v = cx18_av_read(cx, 0x810) | 0x1;
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
retval = set_audclk_freq(cx, freq);
v = cx18_av_read(cx, 0x810) & ~0x1;
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
v = cx18_av_read(cx, 0x803) | 0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
}
return retval;
}
static int cx18_av_audio_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct v4l2_subdev *sd = to_sd(ctrl);
struct cx18 *cx = v4l2_get_subdevdata(sd);
switch (ctrl->id) {
case V4L2_CID_AUDIO_VOLUME:
set_volume(cx, ctrl->val);
break;
case V4L2_CID_AUDIO_BASS:
set_bass(cx, ctrl->val);
break;
case V4L2_CID_AUDIO_TREBLE:
set_treble(cx, ctrl->val);
break;
case V4L2_CID_AUDIO_BALANCE:
set_balance(cx, ctrl->val);
break;
case V4L2_CID_AUDIO_MUTE:
set_mute(cx, ctrl->val);
break;
default:
return -EINVAL;
}
return 0;
}
const struct v4l2_ctrl_ops cx18_av_audio_ctrl_ops = {
.s_ctrl = cx18_av_audio_s_ctrl,
};
| linux-master | drivers/media/pci/cx18/cx18-av-audio.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 init/start/stop/exit stream functions
*
* Derived from ivtv-streams.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-fileops.h"
#include "cx18-mailbox.h"
#include "cx18-i2c.h"
#include "cx18-queue.h"
#include "cx18-ioctl.h"
#include "cx18-streams.h"
#include "cx18-cards.h"
#include "cx18-scb.h"
#include "cx18-dvb.h"
#define CX18_DSP0_INTERRUPT_MASK 0xd0004C
static const struct v4l2_file_operations cx18_v4l2_enc_fops = {
.owner = THIS_MODULE,
.read = cx18_v4l2_read,
.open = cx18_v4l2_open,
.unlocked_ioctl = video_ioctl2,
.release = cx18_v4l2_close,
.poll = cx18_v4l2_enc_poll,
};
static const struct v4l2_file_operations cx18_v4l2_enc_yuv_fops = {
.owner = THIS_MODULE,
.open = cx18_v4l2_open,
.unlocked_ioctl = video_ioctl2,
.release = cx18_v4l2_close,
.poll = vb2_fop_poll,
.read = vb2_fop_read,
.mmap = vb2_fop_mmap,
};
/* offset from 0 to register ts v4l2 minors on */
#define CX18_V4L2_ENC_TS_OFFSET 16
/* offset from 0 to register pcm v4l2 minors on */
#define CX18_V4L2_ENC_PCM_OFFSET 24
/* offset from 0 to register yuv v4l2 minors on */
#define CX18_V4L2_ENC_YUV_OFFSET 32
static struct {
const char *name;
int vfl_type;
int num_offset;
int dma;
u32 caps;
} cx18_stream_info[] = {
{ /* CX18_ENC_STREAM_TYPE_MPG */
"encoder MPEG",
VFL_TYPE_VIDEO, 0,
DMA_FROM_DEVICE,
V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
V4L2_CAP_AUDIO | V4L2_CAP_TUNER
},
{ /* CX18_ENC_STREAM_TYPE_TS */
"TS",
VFL_TYPE_VIDEO, -1,
DMA_FROM_DEVICE,
},
{ /* CX18_ENC_STREAM_TYPE_YUV */
"encoder YUV",
VFL_TYPE_VIDEO, CX18_V4L2_ENC_YUV_OFFSET,
DMA_FROM_DEVICE,
V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
V4L2_CAP_STREAMING | V4L2_CAP_AUDIO | V4L2_CAP_TUNER
},
{ /* CX18_ENC_STREAM_TYPE_VBI */
"encoder VBI",
VFL_TYPE_VBI, 0,
DMA_FROM_DEVICE,
V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE |
V4L2_CAP_READWRITE | V4L2_CAP_AUDIO | V4L2_CAP_TUNER
},
{ /* CX18_ENC_STREAM_TYPE_PCM */
"encoder PCM audio",
VFL_TYPE_VIDEO, CX18_V4L2_ENC_PCM_OFFSET,
DMA_FROM_DEVICE,
V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE,
},
{ /* CX18_ENC_STREAM_TYPE_IDX */
"encoder IDX",
VFL_TYPE_VIDEO, -1,
DMA_FROM_DEVICE,
},
{ /* CX18_ENC_STREAM_TYPE_RAD */
"encoder radio",
VFL_TYPE_RADIO, 0,
DMA_NONE,
V4L2_CAP_RADIO | V4L2_CAP_TUNER
},
};
static int cx18_queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct cx18_stream *s = vb2_get_drv_priv(vq);
struct cx18 *cx = s->cx;
unsigned int szimage;
/*
* HM12 YUV size is (Y=(h*720) + UV=(h*(720/2)))
* UYUV YUV size is (Y=(h*720) + UV=(h*(720)))
*/
if (s->pixelformat == V4L2_PIX_FMT_NV12_16L16)
szimage = cx->cxhdl.height * 720 * 3 / 2;
else
szimage = cx->cxhdl.height * 720 * 2;
/*
* Let's request at least three buffers: two for the
* DMA engine and one for userspace.
*/
if (vq->num_buffers + *nbuffers < 3)
*nbuffers = 3 - vq->num_buffers;
if (*nplanes) {
if (*nplanes != 1 || sizes[0] < szimage)
return -EINVAL;
return 0;
}
sizes[0] = szimage;
*nplanes = 1;
return 0;
}
static void cx18_buf_queue(struct vb2_buffer *vb)
{
struct cx18_stream *s = vb2_get_drv_priv(vb->vb2_queue);
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx18_vb2_buffer *buf =
container_of(vbuf, struct cx18_vb2_buffer, vb);
unsigned long flags;
spin_lock_irqsave(&s->vb_lock, flags);
list_add_tail(&buf->list, &s->vb_capture);
spin_unlock_irqrestore(&s->vb_lock, flags);
}
static int cx18_buf_prepare(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx18_stream *s = vb2_get_drv_priv(vb->vb2_queue);
struct cx18 *cx = s->cx;
unsigned int size;
/*
* HM12 YUV size is (Y=(h*720) + UV=(h*(720/2)))
* UYUV YUV size is (Y=(h*720) + UV=(h*(720)))
*/
if (s->pixelformat == V4L2_PIX_FMT_NV12_16L16)
size = cx->cxhdl.height * 720 * 3 / 2;
else
size = cx->cxhdl.height * 720 * 2;
if (vb2_plane_size(vb, 0) < size)
return -EINVAL;
vb2_set_plane_payload(vb, 0, size);
vbuf->field = V4L2_FIELD_INTERLACED;
return 0;
}
void cx18_clear_queue(struct cx18_stream *s, enum vb2_buffer_state state)
{
while (!list_empty(&s->vb_capture)) {
struct cx18_vb2_buffer *buf;
buf = list_first_entry(&s->vb_capture,
struct cx18_vb2_buffer, list);
list_del(&buf->list);
vb2_buffer_done(&buf->vb.vb2_buf, state);
}
}
static int cx18_start_streaming(struct vb2_queue *vq, unsigned int count)
{
struct v4l2_fh *owner = vq->owner;
struct cx18_stream *s = vb2_get_drv_priv(vq);
unsigned long flags;
int rc;
if (WARN_ON(!owner)) {
rc = -EIO;
goto clear_queue;
}
s->sequence = 0;
rc = cx18_start_capture(fh2id(owner));
if (!rc) {
/* Establish a buffer timeout */
mod_timer(&s->vb_timeout, msecs_to_jiffies(2000) + jiffies);
return 0;
}
clear_queue:
spin_lock_irqsave(&s->vb_lock, flags);
cx18_clear_queue(s, VB2_BUF_STATE_QUEUED);
spin_unlock_irqrestore(&s->vb_lock, flags);
return rc;
}
static void cx18_stop_streaming(struct vb2_queue *vq)
{
struct cx18_stream *s = vb2_get_drv_priv(vq);
unsigned long flags;
cx18_stop_capture(s, 0);
timer_delete_sync(&s->vb_timeout);
spin_lock_irqsave(&s->vb_lock, flags);
cx18_clear_queue(s, VB2_BUF_STATE_ERROR);
spin_unlock_irqrestore(&s->vb_lock, flags);
}
static const struct vb2_ops cx18_vb2_qops = {
.queue_setup = cx18_queue_setup,
.buf_queue = cx18_buf_queue,
.buf_prepare = cx18_buf_prepare,
.start_streaming = cx18_start_streaming,
.stop_streaming = cx18_stop_streaming,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
static int cx18_stream_init(struct cx18 *cx, int type)
{
struct cx18_stream *s = &cx->streams[type];
int err = 0;
memset(s, 0, sizeof(*s));
/* initialize cx18_stream fields */
s->dvb = NULL;
s->cx = cx;
s->type = type;
s->name = cx18_stream_info[type].name;
s->handle = CX18_INVALID_TASK_HANDLE;
s->dma = cx18_stream_info[type].dma;
s->v4l2_dev_caps = cx18_stream_info[type].caps;
s->buffers = cx->stream_buffers[type];
s->buf_size = cx->stream_buf_size[type];
INIT_LIST_HEAD(&s->buf_pool);
s->bufs_per_mdl = 1;
s->mdl_size = s->buf_size * s->bufs_per_mdl;
init_waitqueue_head(&s->waitq);
s->id = -1;
spin_lock_init(&s->q_free.lock);
cx18_queue_init(&s->q_free);
spin_lock_init(&s->q_busy.lock);
cx18_queue_init(&s->q_busy);
spin_lock_init(&s->q_full.lock);
cx18_queue_init(&s->q_full);
spin_lock_init(&s->q_idle.lock);
cx18_queue_init(&s->q_idle);
INIT_WORK(&s->out_work_order, cx18_out_work_handler);
INIT_LIST_HEAD(&s->vb_capture);
timer_setup(&s->vb_timeout, cx18_vb_timeout, 0);
spin_lock_init(&s->vb_lock);
if (type == CX18_ENC_STREAM_TYPE_YUV) {
s->vb_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
/* Assume the previous pixel default */
s->pixelformat = V4L2_PIX_FMT_NV12_16L16;
s->vb_bytes_per_frame = cx->cxhdl.height * 720 * 3 / 2;
s->vb_bytes_per_line = 720;
s->vidq.io_modes = VB2_READ | VB2_MMAP | VB2_DMABUF;
s->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
s->vidq.drv_priv = s;
s->vidq.buf_struct_size = sizeof(struct cx18_vb2_buffer);
s->vidq.ops = &cx18_vb2_qops;
s->vidq.mem_ops = &vb2_vmalloc_memops;
s->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
s->vidq.min_buffers_needed = 2;
s->vidq.gfp_flags = GFP_DMA32;
s->vidq.dev = &cx->pci_dev->dev;
s->vidq.lock = &cx->serialize_lock;
err = vb2_queue_init(&s->vidq);
if (err)
v4l2_err(&cx->v4l2_dev, "cannot init vb2 queue\n");
s->video_dev.queue = &s->vidq;
}
return err;
}
static int cx18_prep_dev(struct cx18 *cx, int type)
{
struct cx18_stream *s = &cx->streams[type];
u32 cap = cx->v4l2_cap;
int num_offset = cx18_stream_info[type].num_offset;
int num = cx->instance + cx18_first_minor + num_offset;
int err;
/*
* These five fields are always initialized.
* For analog capture related streams, if video_dev.v4l2_dev == NULL then the
* stream is not in use.
* For the TS stream, if dvb == NULL then the stream is not in use.
* In those cases no other fields but these four can be used.
*/
s->video_dev.v4l2_dev = NULL;
s->dvb = NULL;
s->cx = cx;
s->type = type;
s->name = cx18_stream_info[type].name;
/* Check whether the radio is supported */
if (type == CX18_ENC_STREAM_TYPE_RAD && !(cap & V4L2_CAP_RADIO))
return 0;
/* Check whether VBI is supported */
if (type == CX18_ENC_STREAM_TYPE_VBI &&
!(cap & (V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE)))
return 0;
/* User explicitly selected 0 buffers for these streams, so don't
create them. */
if (cx18_stream_info[type].dma != DMA_NONE &&
cx->stream_buffers[type] == 0) {
CX18_INFO("Disabled %s device\n", cx18_stream_info[type].name);
return 0;
}
err = cx18_stream_init(cx, type);
if (err)
return err;
/* Allocate the cx18_dvb struct only for the TS on cards with DTV */
if (type == CX18_ENC_STREAM_TYPE_TS) {
if (cx->card->hw_all & CX18_HW_DVB) {
s->dvb = kzalloc(sizeof(struct cx18_dvb), GFP_KERNEL);
if (s->dvb == NULL) {
CX18_ERR("Couldn't allocate cx18_dvb structure for %s\n",
s->name);
return -ENOMEM;
}
} else {
/* Don't need buffers for the TS, if there is no DVB */
s->buffers = 0;
}
}
if (num_offset == -1)
return 0;
/* initialize the v4l2 video device structure */
snprintf(s->video_dev.name, sizeof(s->video_dev.name), "%s %s",
cx->v4l2_dev.name, s->name);
s->video_dev.num = num;
s->video_dev.v4l2_dev = &cx->v4l2_dev;
if (type == CX18_ENC_STREAM_TYPE_YUV)
s->video_dev.fops = &cx18_v4l2_enc_yuv_fops;
else
s->video_dev.fops = &cx18_v4l2_enc_fops;
s->video_dev.release = video_device_release_empty;
if (cx->card->video_inputs->video_type == CX18_CARD_INPUT_VID_TUNER)
s->video_dev.tvnorms = cx->tuner_std;
else
s->video_dev.tvnorms = V4L2_STD_ALL;
s->video_dev.lock = &cx->serialize_lock;
cx18_set_funcs(&s->video_dev);
return 0;
}
/* Initialize v4l2 variables and register v4l2 devices */
int cx18_streams_setup(struct cx18 *cx)
{
int type, ret;
/* Setup V4L2 Devices */
for (type = 0; type < CX18_MAX_STREAMS; type++) {
/* Prepare device */
ret = cx18_prep_dev(cx, type);
if (ret < 0)
break;
/* Allocate Stream */
ret = cx18_stream_alloc(&cx->streams[type]);
if (ret < 0)
break;
}
if (type == CX18_MAX_STREAMS)
return 0;
/* One or more streams could not be initialized. Clean 'em all up. */
cx18_streams_cleanup(cx, 0);
return ret;
}
static int cx18_reg_dev(struct cx18 *cx, int type)
{
struct cx18_stream *s = &cx->streams[type];
int vfl_type = cx18_stream_info[type].vfl_type;
const char *name;
int num, ret;
if (type == CX18_ENC_STREAM_TYPE_TS && s->dvb != NULL) {
ret = cx18_dvb_register(s);
if (ret < 0) {
CX18_ERR("DVB failed to register\n");
return ret;
}
}
if (s->video_dev.v4l2_dev == NULL)
return 0;
num = s->video_dev.num;
s->video_dev.device_caps = s->v4l2_dev_caps; /* device capabilities */
/* card number + user defined offset + device offset */
if (type != CX18_ENC_STREAM_TYPE_MPG) {
struct cx18_stream *s_mpg = &cx->streams[CX18_ENC_STREAM_TYPE_MPG];
if (s_mpg->video_dev.v4l2_dev)
num = s_mpg->video_dev.num
+ cx18_stream_info[type].num_offset;
}
video_set_drvdata(&s->video_dev, s);
/* Register device. First try the desired minor, then any free one. */
ret = video_register_device_no_warn(&s->video_dev, vfl_type, num);
if (ret < 0) {
CX18_ERR("Couldn't register v4l2 device for %s (device node number %d)\n",
s->name, num);
s->video_dev.v4l2_dev = NULL;
return ret;
}
name = video_device_node_name(&s->video_dev);
switch (vfl_type) {
case VFL_TYPE_VIDEO:
CX18_INFO("Registered device %s for %s (%d x %d.%02d kB)\n",
name, s->name, cx->stream_buffers[type],
cx->stream_buf_size[type] / 1024,
(cx->stream_buf_size[type] * 100 / 1024) % 100);
break;
case VFL_TYPE_RADIO:
CX18_INFO("Registered device %s for %s\n", name, s->name);
break;
case VFL_TYPE_VBI:
if (cx->stream_buffers[type])
CX18_INFO("Registered device %s for %s (%d x %d bytes)\n",
name, s->name, cx->stream_buffers[type],
cx->stream_buf_size[type]);
else
CX18_INFO("Registered device %s for %s\n",
name, s->name);
break;
}
return 0;
}
/* Register v4l2 devices */
int cx18_streams_register(struct cx18 *cx)
{
int type;
int err;
int ret = 0;
/* Register V4L2 devices */
for (type = 0; type < CX18_MAX_STREAMS; type++) {
err = cx18_reg_dev(cx, type);
if (err && ret == 0)
ret = err;
}
if (ret == 0)
return 0;
/* One or more streams could not be initialized. Clean 'em all up. */
cx18_streams_cleanup(cx, 1);
return ret;
}
/* Unregister v4l2 devices */
void cx18_streams_cleanup(struct cx18 *cx, int unregister)
{
struct video_device *vdev;
int type;
/* Teardown all streams */
for (type = 0; type < CX18_MAX_STREAMS; type++) {
/* The TS has a cx18_dvb structure, not a video_device */
if (type == CX18_ENC_STREAM_TYPE_TS) {
if (cx->streams[type].dvb != NULL) {
if (unregister)
cx18_dvb_unregister(&cx->streams[type]);
kfree(cx->streams[type].dvb);
cx->streams[type].dvb = NULL;
cx18_stream_free(&cx->streams[type]);
}
continue;
}
/* No struct video_device, but can have buffers allocated */
if (type == CX18_ENC_STREAM_TYPE_IDX) {
/* If the module params didn't inhibit IDX ... */
if (cx->stream_buffers[type] != 0) {
cx->stream_buffers[type] = 0;
/*
* Before calling cx18_stream_free(),
* check if the IDX stream was actually set up.
* Needed, since the cx18_probe() error path
* exits through here as well as normal clean up
*/
if (cx->streams[type].buffers != 0)
cx18_stream_free(&cx->streams[type]);
}
continue;
}
/* If struct video_device exists, can have buffers allocated */
vdev = &cx->streams[type].video_dev;
if (vdev->v4l2_dev == NULL)
continue;
cx18_stream_free(&cx->streams[type]);
if (type == CX18_ENC_STREAM_TYPE_YUV)
vb2_video_unregister_device(vdev);
else
video_unregister_device(vdev);
}
}
static void cx18_vbi_setup(struct cx18_stream *s)
{
struct cx18 *cx = s->cx;
int raw = cx18_raw_vbi(cx);
u32 data[CX2341X_MBOX_MAX_DATA];
int lines;
if (cx->is_60hz) {
cx->vbi.count = 12;
cx->vbi.start[0] = 10;
cx->vbi.start[1] = 273;
} else { /* PAL/SECAM */
cx->vbi.count = 18;
cx->vbi.start[0] = 6;
cx->vbi.start[1] = 318;
}
/* setup VBI registers */
if (raw)
v4l2_subdev_call(cx->sd_av, vbi, s_raw_fmt, &cx->vbi.in.fmt.vbi);
else
v4l2_subdev_call(cx->sd_av, vbi, s_sliced_fmt, &cx->vbi.in.fmt.sliced);
/*
* Send the CX18_CPU_SET_RAW_VBI_PARAM API command to setup Encoder Raw
* VBI when the first analog capture channel starts, as once it starts
* (e.g. MPEG), we can't effect any change in the Encoder Raw VBI setup
* (i.e. for the VBI capture channels). We also send it for each
* analog capture channel anyway just to make sure we get the proper
* behavior
*/
if (raw) {
lines = cx->vbi.count * 2;
} else {
/*
* For 525/60 systems, according to the VIP 2 & BT.656 std:
* The EAV RP code's Field bit toggles on line 4, a few lines
* after the Vertcal Blank bit has already toggled.
* Tell the encoder to capture 21-4+1=18 lines per field,
* since we want lines 10 through 21.
*
* For 625/50 systems, according to the VIP 2 & BT.656 std:
* The EAV RP code's Field bit toggles on line 1, a few lines
* after the Vertcal Blank bit has already toggled.
* (We've actually set the digitizer so that the Field bit
* toggles on line 2.) Tell the encoder to capture 23-2+1=22
* lines per field, since we want lines 6 through 23.
*/
lines = cx->is_60hz ? (21 - 4 + 1) * 2 : (23 - 2 + 1) * 2;
}
data[0] = s->handle;
/* Lines per field */
data[1] = (lines / 2) | ((lines / 2) << 16);
/* bytes per line */
data[2] = (raw ? VBI_ACTIVE_SAMPLES
: (cx->is_60hz ? VBI_HBLANK_SAMPLES_60HZ
: VBI_HBLANK_SAMPLES_50HZ));
/* Every X number of frames a VBI interrupt arrives
(frames as in 25 or 30 fps) */
data[3] = 1;
/*
* Set the SAV/EAV RP codes to look for as start/stop points
* when in VIP-1.1 mode
*/
if (raw) {
/*
* Start codes for beginning of "active" line in vertical blank
* 0x20 ( VerticalBlank )
* 0x60 ( EvenField VerticalBlank )
*/
data[4] = 0x20602060;
/*
* End codes for end of "active" raw lines and regular lines
* 0x30 ( VerticalBlank HorizontalBlank)
* 0x70 ( EvenField VerticalBlank HorizontalBlank)
* 0x90 (Task HorizontalBlank)
* 0xd0 (Task EvenField HorizontalBlank)
*/
data[5] = 0x307090d0;
} else {
/*
* End codes for active video, we want data in the hblank region
* 0xb0 (Task 0 VerticalBlank HorizontalBlank)
* 0xf0 (Task EvenField VerticalBlank HorizontalBlank)
*
* Since the V bit is only allowed to toggle in the EAV RP code,
* just before the first active region line, these two
* are problematic:
* 0x90 (Task HorizontalBlank)
* 0xd0 (Task EvenField HorizontalBlank)
*
* We have set the digitzer such that we don't have to worry
* about these problem codes.
*/
data[4] = 0xB0F0B0F0;
/*
* Start codes for beginning of active line in vertical blank
* 0xa0 (Task VerticalBlank )
* 0xe0 (Task EvenField VerticalBlank )
*/
data[5] = 0xA0E0A0E0;
}
CX18_DEBUG_INFO("Setup VBI h: %d lines %x bpl %d fr %d %x %x\n",
data[0], data[1], data[2], data[3], data[4], data[5]);
cx18_api(cx, CX18_CPU_SET_RAW_VBI_PARAM, 6, data);
}
void cx18_stream_rotate_idx_mdls(struct cx18 *cx)
{
struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
struct cx18_mdl *mdl;
if (!cx18_stream_enabled(s))
return;
/* Return if the firmware is not running low on MDLs */
if ((atomic_read(&s->q_free.depth) + atomic_read(&s->q_busy.depth)) >=
CX18_ENC_STREAM_TYPE_IDX_FW_MDL_MIN)
return;
/* Return if there are no MDLs to rotate back to the firmware */
if (atomic_read(&s->q_full.depth) < 2)
return;
/*
* Take the oldest IDX MDL still holding data, and discard its index
* entries by scheduling the MDL to go back to the firmware
*/
mdl = cx18_dequeue(s, &s->q_full);
if (mdl != NULL)
cx18_enqueue(s, mdl, &s->q_free);
}
static
struct cx18_queue *_cx18_stream_put_mdl_fw(struct cx18_stream *s,
struct cx18_mdl *mdl)
{
struct cx18 *cx = s->cx;
struct cx18_queue *q;
/* Don't give it to the firmware, if we're not running a capture */
if (s->handle == CX18_INVALID_TASK_HANDLE ||
test_bit(CX18_F_S_STOPPING, &s->s_flags) ||
!test_bit(CX18_F_S_STREAMING, &s->s_flags))
return cx18_enqueue(s, mdl, &s->q_free);
q = cx18_enqueue(s, mdl, &s->q_busy);
if (q != &s->q_busy)
return q; /* The firmware has the max MDLs it can handle */
cx18_mdl_sync_for_device(s, mdl);
cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle,
(void __iomem *) &cx->scb->cpu_mdl[mdl->id] - cx->enc_mem,
s->bufs_per_mdl, mdl->id, s->mdl_size);
return q;
}
static
void _cx18_stream_load_fw_queue(struct cx18_stream *s)
{
struct cx18_queue *q;
struct cx18_mdl *mdl;
if (atomic_read(&s->q_free.depth) == 0 ||
atomic_read(&s->q_busy.depth) >= CX18_MAX_FW_MDLS_PER_STREAM)
return;
/* Move from q_free to q_busy notifying the firmware, until the limit */
do {
mdl = cx18_dequeue(s, &s->q_free);
if (mdl == NULL)
break;
q = _cx18_stream_put_mdl_fw(s, mdl);
} while (atomic_read(&s->q_busy.depth) < CX18_MAX_FW_MDLS_PER_STREAM
&& q == &s->q_busy);
}
void cx18_out_work_handler(struct work_struct *work)
{
struct cx18_stream *s =
container_of(work, struct cx18_stream, out_work_order);
_cx18_stream_load_fw_queue(s);
}
static void cx18_stream_configure_mdls(struct cx18_stream *s)
{
cx18_unload_queues(s);
switch (s->type) {
case CX18_ENC_STREAM_TYPE_YUV:
/*
* Height should be a multiple of 32 lines.
* Set the MDL size to the exact size needed for one frame.
* Use enough buffers per MDL to cover the MDL size
*/
if (s->pixelformat == V4L2_PIX_FMT_NV12_16L16)
s->mdl_size = 720 * s->cx->cxhdl.height * 3 / 2;
else
s->mdl_size = 720 * s->cx->cxhdl.height * 2;
s->bufs_per_mdl = s->mdl_size / s->buf_size;
if (s->mdl_size % s->buf_size)
s->bufs_per_mdl++;
break;
case CX18_ENC_STREAM_TYPE_VBI:
s->bufs_per_mdl = 1;
if (cx18_raw_vbi(s->cx)) {
s->mdl_size = (s->cx->is_60hz ? 12 : 18)
* 2 * VBI_ACTIVE_SAMPLES;
} else {
/*
* See comment in cx18_vbi_setup() below about the
* extra lines we capture in sliced VBI mode due to
* the lines on which EAV RP codes toggle.
*/
s->mdl_size = s->cx->is_60hz
? (21 - 4 + 1) * 2 * VBI_HBLANK_SAMPLES_60HZ
: (23 - 2 + 1) * 2 * VBI_HBLANK_SAMPLES_50HZ;
}
break;
default:
s->bufs_per_mdl = 1;
s->mdl_size = s->buf_size * s->bufs_per_mdl;
break;
}
cx18_load_queues(s);
}
int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
{
u32 data[MAX_MB_ARGUMENTS];
struct cx18 *cx = s->cx;
int captype = 0;
struct cx18_stream *s_idx;
if (!cx18_stream_enabled(s))
return -EINVAL;
CX18_DEBUG_INFO("Start encoder stream %s\n", s->name);
switch (s->type) {
case CX18_ENC_STREAM_TYPE_MPG:
captype = CAPTURE_CHANNEL_TYPE_MPEG;
cx->mpg_data_received = cx->vbi_data_inserted = 0;
cx->dualwatch_jiffies = jiffies;
cx->dualwatch_stereo_mode = v4l2_ctrl_g_ctrl(cx->cxhdl.audio_mode);
cx->search_pack_header = 0;
break;
case CX18_ENC_STREAM_TYPE_IDX:
captype = CAPTURE_CHANNEL_TYPE_INDEX;
break;
case CX18_ENC_STREAM_TYPE_TS:
captype = CAPTURE_CHANNEL_TYPE_TS;
break;
case CX18_ENC_STREAM_TYPE_YUV:
captype = CAPTURE_CHANNEL_TYPE_YUV;
break;
case CX18_ENC_STREAM_TYPE_PCM:
captype = CAPTURE_CHANNEL_TYPE_PCM;
break;
case CX18_ENC_STREAM_TYPE_VBI:
#ifdef CX18_ENCODER_PARSES_SLICED
captype = cx18_raw_vbi(cx) ?
CAPTURE_CHANNEL_TYPE_VBI : CAPTURE_CHANNEL_TYPE_SLICED_VBI;
#else
/*
* Currently we set things up so that Sliced VBI from the
* digitizer is handled as Raw VBI by the encoder
*/
captype = CAPTURE_CHANNEL_TYPE_VBI;
#endif
cx->vbi.frame = 0;
cx->vbi.inserted_frame = 0;
memset(cx->vbi.sliced_mpeg_size,
0, sizeof(cx->vbi.sliced_mpeg_size));
break;
default:
return -EINVAL;
}
/* Clear Streamoff flags in case left from last capture */
clear_bit(CX18_F_S_STREAMOFF, &s->s_flags);
cx18_vapi_result(cx, data, CX18_CREATE_TASK, 1, CPU_CMD_MASK_CAPTURE);
s->handle = data[0];
cx18_vapi(cx, CX18_CPU_SET_CHANNEL_TYPE, 2, s->handle, captype);
/*
* For everything but CAPTURE_CHANNEL_TYPE_TS, play it safe and
* set up all the parameters, as it is not obvious which parameters the
* firmware shares across capture channel types and which it does not.
*
* Some of the cx18_vapi() calls below apply to only certain capture
* channel types. We're hoping there's no harm in calling most of them
* anyway, as long as the values are all consistent. Setting some
* shared parameters will have no effect once an analog capture channel
* has started streaming.
*/
if (captype != CAPTURE_CHANNEL_TYPE_TS) {
cx18_vapi(cx, CX18_CPU_SET_VER_CROP_LINE, 2, s->handle, 0);
cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 3, 1);
cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 8, 0);
cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 4, 1);
/*
* Audio related reset according to
* Documentation/driver-api/media/drivers/cx2341x-devel.rst
*/
if (atomic_read(&cx->ana_capturing) == 0)
cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 2,
s->handle, 12);
/*
* Number of lines for Field 1 & Field 2 according to
* Documentation/driver-api/media/drivers/cx2341x-devel.rst
* Field 1 is 312 for 625 line systems in BT.656
* Field 2 is 313 for 625 line systems in BT.656
*/
cx18_vapi(cx, CX18_CPU_SET_CAPTURE_LINE_NO, 3,
s->handle, 312, 313);
if (cx->v4l2_cap & V4L2_CAP_VBI_CAPTURE)
cx18_vbi_setup(s);
/*
* Select to receive I, P, and B frame index entries, if the
* index stream is enabled. Otherwise disable index entry
* generation.
*/
s_idx = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
cx18_vapi_result(cx, data, CX18_CPU_SET_INDEXTABLE, 2,
s->handle, cx18_stream_enabled(s_idx) ? 7 : 0);
/* Call out to the common CX2341x API setup for user controls */
cx->cxhdl.priv = s;
cx2341x_handler_setup(&cx->cxhdl);
/*
* When starting a capture and we're set for radio,
* ensure the video is muted, despite the user control.
*/
if (!cx->cxhdl.video_mute &&
test_bit(CX18_F_I_RADIO_USER, &cx->i_flags))
cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle,
(v4l2_ctrl_g_ctrl(cx->cxhdl.video_mute_yuv) << 8) | 1);
/* Enable the Video Format Converter for UYVY 4:2:2 support,
* rather than the default HM12 Macroblovk 4:2:0 support.
*/
if (captype == CAPTURE_CHANNEL_TYPE_YUV) {
if (s->pixelformat == V4L2_PIX_FMT_UYVY)
cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2,
s->handle, 1);
else
/* If in doubt, default to HM12 */
cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2,
s->handle, 0);
}
}
if (atomic_read(&cx->tot_capturing) == 0) {
cx2341x_handler_set_busy(&cx->cxhdl, 1);
clear_bit(CX18_F_I_EOS, &cx->i_flags);
cx18_write_reg(cx, 7, CX18_DSP0_INTERRUPT_MASK);
}
cx18_vapi(cx, CX18_CPU_DE_SET_MDL_ACK, 3, s->handle,
(void __iomem *)&cx->scb->cpu_mdl_ack[s->type][0] - cx->enc_mem,
(void __iomem *)&cx->scb->cpu_mdl_ack[s->type][1] - cx->enc_mem);
/* Init all the cpu_mdls for this stream */
cx18_stream_configure_mdls(s);
_cx18_stream_load_fw_queue(s);
/* begin_capture */
if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) {
CX18_DEBUG_WARN("Error starting capture!\n");
/* Ensure we're really not capturing before releasing MDLs */
set_bit(CX18_F_S_STOPPING, &s->s_flags);
if (s->type == CX18_ENC_STREAM_TYPE_MPG)
cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1);
else
cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
clear_bit(CX18_F_S_STREAMING, &s->s_flags);
/* FIXME - CX18_F_S_STREAMOFF as well? */
cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
s->handle = CX18_INVALID_TASK_HANDLE;
clear_bit(CX18_F_S_STOPPING, &s->s_flags);
if (atomic_read(&cx->tot_capturing) == 0) {
set_bit(CX18_F_I_EOS, &cx->i_flags);
cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
}
return -EINVAL;
}
/* you're live! sit back and await interrupts :) */
if (captype != CAPTURE_CHANNEL_TYPE_TS)
atomic_inc(&cx->ana_capturing);
atomic_inc(&cx->tot_capturing);
return 0;
}
EXPORT_SYMBOL(cx18_start_v4l2_encode_stream);
void cx18_stop_all_captures(struct cx18 *cx)
{
int i;
for (i = CX18_MAX_STREAMS - 1; i >= 0; i--) {
struct cx18_stream *s = &cx->streams[i];
if (!cx18_stream_enabled(s))
continue;
if (test_bit(CX18_F_S_STREAMING, &s->s_flags))
cx18_stop_v4l2_encode_stream(s, 0);
}
}
int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end)
{
struct cx18 *cx = s->cx;
if (!cx18_stream_enabled(s))
return -EINVAL;
/* This function assumes that you are allowed to stop the capture
and that we are actually capturing */
CX18_DEBUG_INFO("Stop Capture\n");
if (atomic_read(&cx->tot_capturing) == 0)
return 0;
set_bit(CX18_F_S_STOPPING, &s->s_flags);
if (s->type == CX18_ENC_STREAM_TYPE_MPG)
cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end);
else
cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
if (s->type == CX18_ENC_STREAM_TYPE_MPG && gop_end) {
CX18_INFO("ignoring gop_end: not (yet?) supported by the firmware\n");
}
if (s->type != CX18_ENC_STREAM_TYPE_TS)
atomic_dec(&cx->ana_capturing);
atomic_dec(&cx->tot_capturing);
/* Clear capture and no-read bits */
clear_bit(CX18_F_S_STREAMING, &s->s_flags);
/* Tell the CX23418 it can't use our buffers anymore */
cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
s->handle = CX18_INVALID_TASK_HANDLE;
clear_bit(CX18_F_S_STOPPING, &s->s_flags);
if (atomic_read(&cx->tot_capturing) > 0)
return 0;
cx2341x_handler_set_busy(&cx->cxhdl, 0);
cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
wake_up(&s->waitq);
return 0;
}
EXPORT_SYMBOL(cx18_stop_v4l2_encode_stream);
u32 cx18_find_handle(struct cx18 *cx)
{
int i;
/* find first available handle to be used for global settings */
for (i = 0; i < CX18_MAX_STREAMS; i++) {
struct cx18_stream *s = &cx->streams[i];
if (s->video_dev.v4l2_dev && (s->handle != CX18_INVALID_TASK_HANDLE))
return s->handle;
}
return CX18_INVALID_TASK_HANDLE;
}
struct cx18_stream *cx18_handle_to_stream(struct cx18 *cx, u32 handle)
{
int i;
struct cx18_stream *s;
if (handle == CX18_INVALID_TASK_HANDLE)
return NULL;
for (i = 0; i < CX18_MAX_STREAMS; i++) {
s = &cx->streams[i];
if (s->handle != handle)
continue;
if (cx18_stream_enabled(s))
return s;
}
return NULL;
}
| linux-master | drivers/media/pci/cx18/cx18-streams.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx18 functions to query card hardware
*
* Derived from ivtv-cards.c
*
* Copyright (C) 2007 Hans Verkuil <[email protected]>
* Copyright (C) 2008 Andy Walls <[email protected]>
*/
#include "cx18-driver.h"
#include "cx18-cards.h"
#include "cx18-av-core.h"
#include "cx18-i2c.h"
#include <media/i2c/cs5345.h>
#define V4L2_STD_PAL_SECAM (V4L2_STD_PAL|V4L2_STD_SECAM)
/********************** card configuration *******************************/
/* usual i2c tuner addresses to probe */
static struct cx18_card_tuner_i2c cx18_i2c_std = {
.radio = { I2C_CLIENT_END },
.demod = { 0x43, I2C_CLIENT_END },
.tv = { 0x61, 0x60, I2C_CLIENT_END },
};
/*
* usual i2c tuner addresses to probe with additional demod address for
* an NXP TDA8295 at 0x42 (N.B. it can possibly be at 0x4b or 0x4c too).
*/
static struct cx18_card_tuner_i2c cx18_i2c_nxp = {
.radio = { I2C_CLIENT_END },
.demod = { 0x42, 0x43, I2C_CLIENT_END },
.tv = { 0x61, 0x60, I2C_CLIENT_END },
};
/* Please add new PCI IDs to: https://pci-ids.ucw.cz/
This keeps the PCI ID database up to date. Note that the entries
must be added under vendor 0x4444 (Conexant) as subsystem IDs.
New vendor IDs should still be added to the vendor ID list. */
/* Hauppauge HVR-1600 cards */
/* Note: for Hauppauge cards the tveeprom information is used instead
of PCI IDs */
static const struct cx18_card cx18_card_hvr1600_esmt = {
.type = CX18_CARD_HVR_1600_ESMT,
.name = "Hauppauge HVR-1600",
.comment = "Simultaneous Digital and Analog TV capture supported\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_CS5345,
.hw_all = CX18_HW_TVEEPROM | CX18_HW_418_AV | CX18_HW_TUNER |
CX18_HW_CS5345 | CX18_HW_DVB | CX18_HW_GPIO_RESET_CTRL |
CX18_HW_Z8F0811_IR_HAUP,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE7 },
{ CX18_CARD_INPUT_SVIDEO1, 1, CX18_AV_SVIDEO1 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE3 },
{ CX18_CARD_INPUT_SVIDEO2, 2, CX18_AV_SVIDEO2 },
{ CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE4 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO8, CS5345_IN_1 | CS5345_MCLK_1_5 },
{ CX18_CARD_INPUT_LINE_IN1,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_2 },
{ CX18_CARD_INPUT_LINE_IN2,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_3 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_4 },
.ddr = {
/* ESMT M13S128324A-5B memory */
.chip_config = 0x003,
.refresh = 0x30c,
.timing1 = 0x44220e82,
.timing2 = 0x08,
.tune_lane = 0,
.initial_emrs = 0,
},
.gpio_init.initial_value = 0x3001,
.gpio_init.direction = 0x3001,
.gpio_i2c_slave_reset = {
.active_lo_mask = 0x3001,
.msecs_asserted = 10,
.msecs_recovery = 40,
.ir_reset_mask = 0x0001,
},
.i2c = &cx18_i2c_std,
};
static const struct cx18_card cx18_card_hvr1600_s5h1411 = {
.type = CX18_CARD_HVR_1600_S5H1411,
.name = "Hauppauge HVR-1600",
.comment = "Simultaneous Digital and Analog TV capture supported\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_CS5345,
.hw_all = CX18_HW_TVEEPROM | CX18_HW_418_AV | CX18_HW_TUNER |
CX18_HW_CS5345 | CX18_HW_DVB | CX18_HW_GPIO_RESET_CTRL |
CX18_HW_Z8F0811_IR_HAUP,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE7 },
{ CX18_CARD_INPUT_SVIDEO1, 1, CX18_AV_SVIDEO1 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE3 },
{ CX18_CARD_INPUT_SVIDEO2, 2, CX18_AV_SVIDEO2 },
{ CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE4 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO8, CS5345_IN_1 | CS5345_MCLK_1_5 },
{ CX18_CARD_INPUT_LINE_IN1,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_2 },
{ CX18_CARD_INPUT_LINE_IN2,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_3 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_4 },
.ddr = {
/* ESMT M13S128324A-5B memory */
.chip_config = 0x003,
.refresh = 0x30c,
.timing1 = 0x44220e82,
.timing2 = 0x08,
.tune_lane = 0,
.initial_emrs = 0,
},
.gpio_init.initial_value = 0x3801,
.gpio_init.direction = 0x3801,
.gpio_i2c_slave_reset = {
.active_lo_mask = 0x3801,
.msecs_asserted = 10,
.msecs_recovery = 40,
.ir_reset_mask = 0x0001,
},
.i2c = &cx18_i2c_nxp,
};
static const struct cx18_card cx18_card_hvr1600_samsung = {
.type = CX18_CARD_HVR_1600_SAMSUNG,
.name = "Hauppauge HVR-1600 (Preproduction)",
.comment = "Simultaneous Digital and Analog TV capture supported\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_CS5345,
.hw_all = CX18_HW_TVEEPROM | CX18_HW_418_AV | CX18_HW_TUNER |
CX18_HW_CS5345 | CX18_HW_DVB | CX18_HW_GPIO_RESET_CTRL |
CX18_HW_Z8F0811_IR_HAUP,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE7 },
{ CX18_CARD_INPUT_SVIDEO1, 1, CX18_AV_SVIDEO1 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE3 },
{ CX18_CARD_INPUT_SVIDEO2, 2, CX18_AV_SVIDEO2 },
{ CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE4 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO8, CS5345_IN_1 | CS5345_MCLK_1_5 },
{ CX18_CARD_INPUT_LINE_IN1,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_2 },
{ CX18_CARD_INPUT_LINE_IN2,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_3 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_4 },
.ddr = {
/* Samsung K4D263238G-VC33 memory */
.chip_config = 0x003,
.refresh = 0x30c,
.timing1 = 0x23230b73,
.timing2 = 0x08,
.tune_lane = 0,
.initial_emrs = 2,
},
.gpio_init.initial_value = 0x3001,
.gpio_init.direction = 0x3001,
.gpio_i2c_slave_reset = {
.active_lo_mask = 0x3001,
.msecs_asserted = 10,
.msecs_recovery = 40,
.ir_reset_mask = 0x0001,
},
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Compro VideoMate H900: note that this card is analog only! */
static const struct cx18_card_pci_info cx18_pci_h900[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_COMPRO, 0xe100 },
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_h900 = {
.type = CX18_CARD_COMPRO_H900,
.name = "Compro VideoMate H900",
.comment = "Analog TV capture supported\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_all = CX18_HW_418_AV | CX18_HW_TUNER | CX18_HW_GPIO_RESET_CTRL,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1,
CX18_AV_AUDIO_SERIAL1, 0 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO_SERIAL1, 0 },
.tuners = {
{ .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
},
.ddr = {
/* EtronTech EM6A9160TS-5G memory */
.chip_config = 0x50003,
.refresh = 0x753,
.timing1 = 0x24330e84,
.timing2 = 0x1f,
.tune_lane = 0,
.initial_emrs = 0,
},
.xceive_pin = 15,
.pci_list = cx18_pci_h900,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Yuan MPC718: not working at the moment! */
static const struct cx18_card_pci_info cx18_pci_mpc718[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_YUAN, 0x0718 },
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_mpc718 = {
.type = CX18_CARD_YUAN_MPC718,
.name = "Yuan MPC718 MiniPCI DVB-T/Analog",
.comment = "Experimenters needed for device to work well.\n"
"\tTo help, mail the linux-media list (www.linuxtv.org).\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_GPIO_MUX,
.hw_all = CX18_HW_TVEEPROM | CX18_HW_418_AV | CX18_HW_TUNER |
CX18_HW_GPIO_MUX | CX18_HW_DVB | CX18_HW_GPIO_RESET_CTRL,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 },
{ CX18_CARD_INPUT_SVIDEO2, 2,
CX18_AV_SVIDEO_LUMA7 | CX18_AV_SVIDEO_CHROMA8 },
{ CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE6 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL1, 1 },
{ CX18_CARD_INPUT_LINE_IN2, CX18_AV_AUDIO_SERIAL2, 1 },
},
.tuners = {
/* XC3028 tuner */
{ .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
},
/* FIXME - the FM radio is just a guess and driver doesn't use SIF */
.radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 2 },
.ddr = {
/* Hynix HY5DU283222B DDR RAM */
.chip_config = 0x303,
.refresh = 0x3bd,
.timing1 = 0x36320966,
.timing2 = 0x1f,
.tune_lane = 0,
.initial_emrs = 2,
},
.gpio_init.initial_value = 0x1,
.gpio_init.direction = 0x3,
/* FIXME - these GPIO's are just guesses */
.gpio_audio_input = { .mask = 0x3,
.tuner = 0x1,
.linein = 0x3,
.radio = 0x1 },
.xceive_pin = 0,
.pci_list = cx18_pci_mpc718,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* GoTView PCI */
static const struct cx18_card_pci_info cx18_pci_gotview_dvd3[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_GOTVIEW, 0x3343 },
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_gotview_dvd3 = {
.type = CX18_CARD_GOTVIEW_PCI_DVD3,
.name = "GoTView PCI DVD3 Hybrid",
.comment = "Experimenters needed for device to work well.\n"
"\tTo help, mail the linux-media list (www.linuxtv.org).\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_GPIO_MUX,
.hw_all = CX18_HW_TVEEPROM | CX18_HW_418_AV | CX18_HW_TUNER |
CX18_HW_GPIO_MUX | CX18_HW_DVB | CX18_HW_GPIO_RESET_CTRL,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 },
{ CX18_CARD_INPUT_SVIDEO2, 2,
CX18_AV_SVIDEO_LUMA7 | CX18_AV_SVIDEO_CHROMA8 },
{ CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE6 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL1, 1 },
{ CX18_CARD_INPUT_LINE_IN2, CX18_AV_AUDIO_SERIAL2, 1 },
},
.tuners = {
/* XC3028 tuner */
{ .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
},
/* FIXME - the FM radio is just a guess and driver doesn't use SIF */
.radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 2 },
.ddr = {
/* Hynix HY5DU283222B DDR RAM */
.chip_config = 0x303,
.refresh = 0x3bd,
.timing1 = 0x36320966,
.timing2 = 0x1f,
.tune_lane = 0,
.initial_emrs = 2,
},
.gpio_init.initial_value = 0x1,
.gpio_init.direction = 0x3,
.gpio_audio_input = { .mask = 0x3,
.tuner = 0x1,
.linein = 0x2,
.radio = 0x1 },
.xceive_pin = 0,
.pci_list = cx18_pci_gotview_dvd3,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Conexant Raptor PAL/SECAM: note that this card is analog only! */
static const struct cx18_card_pci_info cx18_pci_cnxt_raptor_pal[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_CONEXANT, 0x0009 },
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_cnxt_raptor_pal = {
.type = CX18_CARD_CNXT_RAPTOR_PAL,
.name = "Conexant Raptor PAL/SECAM",
.comment = "Analog TV capture supported\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_GPIO_MUX,
.hw_all = CX18_HW_418_AV | CX18_HW_TUNER | CX18_HW_GPIO_MUX,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 },
{ CX18_CARD_INPUT_SVIDEO2, 2,
CX18_AV_SVIDEO_LUMA7 | CX18_AV_SVIDEO_CHROMA8 },
{ CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE6 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL1, 1 },
{ CX18_CARD_INPUT_LINE_IN2, CX18_AV_AUDIO_SERIAL2, 1 },
},
.tuners = {
{ .std = V4L2_STD_PAL_SECAM, .tuner = TUNER_PHILIPS_FM1216ME_MK3 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO_SERIAL1, 2 },
.ddr = {
/* MT 46V16M16 memory */
.chip_config = 0x50306,
.refresh = 0x753,
.timing1 = 0x33220953,
.timing2 = 0x09,
.tune_lane = 0,
.initial_emrs = 0,
},
.gpio_init.initial_value = 0x1002,
.gpio_init.direction = 0xf002,
.gpio_audio_input = { .mask = 0xf002,
.tuner = 0x1002, /* LED D1 Tuner AF */
.linein = 0x2000, /* LED D2 Line In 1 */
.radio = 0x4002 }, /* LED D3 Tuner AF */
.pci_list = cx18_pci_cnxt_raptor_pal,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Toshiba Qosmio laptop internal DVB-T/Analog Hybrid Tuner */
static const struct cx18_card_pci_info cx18_pci_toshiba_qosmio_dvbt[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_TOSHIBA, 0x0110 },
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_toshiba_qosmio_dvbt = {
.type = CX18_CARD_TOSHIBA_QOSMIO_DVBT,
.name = "Toshiba Qosmio DVB-T/Analog",
.comment = "Experimenters and photos needed for device to work well.\n"
"\tTo help, mail the linux-media list (www.linuxtv.org).\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_all = CX18_HW_418_AV | CX18_HW_TUNER | CX18_HW_GPIO_RESET_CTRL,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE6 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL1, 1 },
},
.tuners = {
{ .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
},
.ddr = {
.chip_config = 0x202,
.refresh = 0x3bb,
.timing1 = 0x33320a63,
.timing2 = 0x0a,
.tune_lane = 0,
.initial_emrs = 0x42,
},
.xceive_pin = 15,
.pci_list = cx18_pci_toshiba_qosmio_dvbt,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Leadtek WinFast PVR2100 */
static const struct cx18_card_pci_info cx18_pci_leadtek_pvr2100[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_LEADTEK, 0x6f27 }, /* PVR2100 */
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_leadtek_pvr2100 = {
.type = CX18_CARD_LEADTEK_PVR2100,
.name = "Leadtek WinFast PVR2100",
.comment = "Experimenters and photos needed for device to work well.\n"
"\tTo help, mail the linux-media list (www.linuxtv.org).\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_GPIO_MUX,
.hw_all = CX18_HW_418_AV | CX18_HW_TUNER | CX18_HW_GPIO_MUX |
CX18_HW_GPIO_RESET_CTRL,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE7 },
{ CX18_CARD_INPUT_COMPONENT1, 1, CX18_AV_COMPONENT1 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL1, 1 },
},
.tuners = {
/* XC2028 tuner */
{ .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 2 },
.ddr = {
/* Pointer to proper DDR config values provided by Terry Wu */
.chip_config = 0x303,
.refresh = 0x3bb,
.timing1 = 0x24220e83,
.timing2 = 0x1f,
.tune_lane = 0,
.initial_emrs = 0x2,
},
.gpio_init.initial_value = 0x6,
.gpio_init.direction = 0x7,
.gpio_audio_input = { .mask = 0x7,
.tuner = 0x6, .linein = 0x2, .radio = 0x2 },
.xceive_pin = 1,
.pci_list = cx18_pci_leadtek_pvr2100,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Leadtek WinFast DVR3100 H */
static const struct cx18_card_pci_info cx18_pci_leadtek_dvr3100h[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_LEADTEK, 0x6690 }, /* DVR3100 H */
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_leadtek_dvr3100h = {
.type = CX18_CARD_LEADTEK_DVR3100H,
.name = "Leadtek WinFast DVR3100 H",
.comment = "Simultaneous DVB-T and Analog capture supported,\n"
"\texcept when capturing Analog from the antenna input.\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_GPIO_MUX,
.hw_all = CX18_HW_418_AV | CX18_HW_TUNER | CX18_HW_GPIO_MUX |
CX18_HW_DVB | CX18_HW_GPIO_RESET_CTRL,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE7 },
{ CX18_CARD_INPUT_COMPONENT1, 1, CX18_AV_COMPONENT1 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL1, 1 },
},
.tuners = {
/* XC3028 tuner */
{ .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 2 },
.ddr = {
/* Pointer to proper DDR config values provided by Terry Wu */
.chip_config = 0x303,
.refresh = 0x3bb,
.timing1 = 0x24220e83,
.timing2 = 0x1f,
.tune_lane = 0,
.initial_emrs = 0x2,
},
.gpio_init.initial_value = 0x6,
.gpio_init.direction = 0x7,
.gpio_audio_input = { .mask = 0x7,
.tuner = 0x6, .linein = 0x2, .radio = 0x2 },
.xceive_pin = 1,
.pci_list = cx18_pci_leadtek_dvr3100h,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
static const struct cx18_card *cx18_card_list[] = {
&cx18_card_hvr1600_esmt,
&cx18_card_hvr1600_samsung,
&cx18_card_h900,
&cx18_card_mpc718,
&cx18_card_cnxt_raptor_pal,
&cx18_card_toshiba_qosmio_dvbt,
&cx18_card_leadtek_pvr2100,
&cx18_card_leadtek_dvr3100h,
&cx18_card_gotview_dvd3,
&cx18_card_hvr1600_s5h1411
};
const struct cx18_card *cx18_get_card(u16 index)
{
if (index >= ARRAY_SIZE(cx18_card_list))
return NULL;
return cx18_card_list[index];
}
int cx18_get_input(struct cx18 *cx, u16 index, struct v4l2_input *input)
{
const struct cx18_card_video_input *card_input =
cx->card->video_inputs + index;
static const char * const input_strs[] = {
"Tuner 1",
"S-Video 1",
"S-Video 2",
"Composite 1",
"Composite 2",
"Component 1"
};
if (index >= cx->nof_inputs)
return -EINVAL;
input->index = index;
strscpy(input->name, input_strs[card_input->video_type - 1],
sizeof(input->name));
input->type = (card_input->video_type == CX18_CARD_INPUT_VID_TUNER ?
V4L2_INPUT_TYPE_TUNER : V4L2_INPUT_TYPE_CAMERA);
input->audioset = (1 << cx->nof_audio_inputs) - 1;
input->std = (input->type == V4L2_INPUT_TYPE_TUNER) ?
cx->tuner_std : V4L2_STD_ALL;
return 0;
}
int cx18_get_audio_input(struct cx18 *cx, u16 index, struct v4l2_audio *audio)
{
const struct cx18_card_audio_input *aud_input =
cx->card->audio_inputs + index;
static const char * const input_strs[] = {
"Tuner 1",
"Line In 1",
"Line In 2"
};
memset(audio, 0, sizeof(*audio));
if (index >= cx->nof_audio_inputs)
return -EINVAL;
strscpy(audio->name, input_strs[aud_input->audio_type - 1],
sizeof(audio->name));
audio->index = index;
audio->capability = V4L2_AUDCAP_STEREO;
return 0;
}
| linux-master | drivers/media/pci/cx18/cx18-cards.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx88-vp3054-i2c.c -- support for the secondary I2C bus of the
* DNTV Live! DVB-T Pro (VP-3054), wired as:
* GPIO[0] -> SCL, GPIO[1] -> SDA
*
* (c) 2005 Chris Pascoe <[email protected]>
*/
#include "cx88.h"
#include "cx88-vp3054-i2c.h"
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/io.h>
MODULE_DESCRIPTION("driver for cx2388x VP3054 design");
MODULE_AUTHOR("Chris Pascoe <[email protected]>");
MODULE_LICENSE("GPL");
/* ----------------------------------------------------------------------- */
static void vp3054_bit_setscl(void *data, int state)
{
struct cx8802_dev *dev = data;
struct cx88_core *core = dev->core;
struct vp3054_i2c_state *vp3054_i2c = dev->vp3054;
if (state) {
vp3054_i2c->state |= 0x0001; /* SCL high */
vp3054_i2c->state &= ~0x0100; /* external pullup */
} else {
vp3054_i2c->state &= ~0x0001; /* SCL low */
vp3054_i2c->state |= 0x0100; /* drive pin */
}
cx_write(MO_GP0_IO, 0x010000 | vp3054_i2c->state);
cx_read(MO_GP0_IO);
}
static void vp3054_bit_setsda(void *data, int state)
{
struct cx8802_dev *dev = data;
struct cx88_core *core = dev->core;
struct vp3054_i2c_state *vp3054_i2c = dev->vp3054;
if (state) {
vp3054_i2c->state |= 0x0002; /* SDA high */
vp3054_i2c->state &= ~0x0200; /* tristate pin */
} else {
vp3054_i2c->state &= ~0x0002; /* SDA low */
vp3054_i2c->state |= 0x0200; /* drive pin */
}
cx_write(MO_GP0_IO, 0x020000 | vp3054_i2c->state);
cx_read(MO_GP0_IO);
}
static int vp3054_bit_getscl(void *data)
{
struct cx8802_dev *dev = data;
struct cx88_core *core = dev->core;
u32 state;
state = cx_read(MO_GP0_IO);
return (state & 0x01) ? 1 : 0;
}
static int vp3054_bit_getsda(void *data)
{
struct cx8802_dev *dev = data;
struct cx88_core *core = dev->core;
u32 state;
state = cx_read(MO_GP0_IO);
return (state & 0x02) ? 1 : 0;
}
/* ----------------------------------------------------------------------- */
static const struct i2c_algo_bit_data vp3054_i2c_algo_template = {
.setsda = vp3054_bit_setsda,
.setscl = vp3054_bit_setscl,
.getsda = vp3054_bit_getsda,
.getscl = vp3054_bit_getscl,
.udelay = 16,
.timeout = 200,
};
/* ----------------------------------------------------------------------- */
int vp3054_i2c_probe(struct cx8802_dev *dev)
{
struct cx88_core *core = dev->core;
struct vp3054_i2c_state *vp3054_i2c;
int rc;
if (core->boardnr != CX88_BOARD_DNTV_LIVE_DVB_T_PRO)
return 0;
vp3054_i2c = kzalloc(sizeof(*vp3054_i2c), GFP_KERNEL);
if (!vp3054_i2c)
return -ENOMEM;
dev->vp3054 = vp3054_i2c;
vp3054_i2c->algo = vp3054_i2c_algo_template;
vp3054_i2c->adap.dev.parent = &dev->pci->dev;
strscpy(vp3054_i2c->adap.name, core->name,
sizeof(vp3054_i2c->adap.name));
vp3054_i2c->adap.owner = THIS_MODULE;
vp3054_i2c->algo.data = dev;
i2c_set_adapdata(&vp3054_i2c->adap, dev);
vp3054_i2c->adap.algo_data = &vp3054_i2c->algo;
vp3054_bit_setscl(dev, 1);
vp3054_bit_setsda(dev, 1);
rc = i2c_bit_add_bus(&vp3054_i2c->adap);
if (rc != 0) {
pr_err("vp3054_i2c register FAILED\n");
kfree(dev->vp3054);
dev->vp3054 = NULL;
}
return rc;
}
EXPORT_SYMBOL(vp3054_i2c_probe);
void vp3054_i2c_remove(struct cx8802_dev *dev)
{
struct vp3054_i2c_state *vp3054_i2c = dev->vp3054;
if (!vp3054_i2c ||
dev->core->boardnr != CX88_BOARD_DNTV_LIVE_DVB_T_PRO)
return;
i2c_del_adapter(&vp3054_i2c->adap);
kfree(vp3054_i2c);
}
EXPORT_SYMBOL(vp3054_i2c_remove);
| linux-master | drivers/media/pci/cx88/cx88-vp3054-i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* device driver for Conexant 2388x based TV cards
* video4linux video interface
*
* (c) 2003-04 Gerd Knorr <[email protected]> [SuSE Labs]
*
* (c) 2005-2006 Mauro Carvalho Chehab <[email protected]>
* - Multituner support
* - video_ioctl2 conversion
* - PAL/M fixes
*/
#include "cx88.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kmod.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/kthread.h>
#include <asm/div64.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-event.h>
#include <media/i2c/wm8775.h>
MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards");
MODULE_AUTHOR("Gerd Knorr <[email protected]> [SuSE Labs]");
MODULE_LICENSE("GPL v2");
MODULE_VERSION(CX88_VERSION);
/* ------------------------------------------------------------------ */
static unsigned int video_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
static unsigned int vbi_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
static unsigned int radio_nr[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
module_param_array(video_nr, int, NULL, 0444);
module_param_array(vbi_nr, int, NULL, 0444);
module_param_array(radio_nr, int, NULL, 0444);
MODULE_PARM_DESC(video_nr, "video device numbers");
MODULE_PARM_DESC(vbi_nr, "vbi device numbers");
MODULE_PARM_DESC(radio_nr, "radio device numbers");
static unsigned int video_debug;
module_param(video_debug, int, 0644);
MODULE_PARM_DESC(video_debug, "enable debug messages [video]");
static unsigned int irq_debug;
module_param(irq_debug, int, 0644);
MODULE_PARM_DESC(irq_debug, "enable debug messages [IRQ handler]");
#define dprintk(level, fmt, arg...) do { \
if (video_debug >= level) \
printk(KERN_DEBUG pr_fmt("%s: video:" fmt), \
__func__, ##arg); \
} while (0)
/* ------------------------------------------------------------------- */
/* static data */
static const struct cx8800_fmt formats[] = {
{
.fourcc = V4L2_PIX_FMT_GREY,
.cxformat = ColorFormatY8,
.depth = 8,
.flags = FORMAT_FLAGS_PACKED,
}, {
.fourcc = V4L2_PIX_FMT_RGB555,
.cxformat = ColorFormatRGB15,
.depth = 16,
.flags = FORMAT_FLAGS_PACKED,
}, {
.fourcc = V4L2_PIX_FMT_RGB555X,
.cxformat = ColorFormatRGB15 | ColorFormatBSWAP,
.depth = 16,
.flags = FORMAT_FLAGS_PACKED,
}, {
.fourcc = V4L2_PIX_FMT_RGB565,
.cxformat = ColorFormatRGB16,
.depth = 16,
.flags = FORMAT_FLAGS_PACKED,
}, {
.fourcc = V4L2_PIX_FMT_RGB565X,
.cxformat = ColorFormatRGB16 | ColorFormatBSWAP,
.depth = 16,
.flags = FORMAT_FLAGS_PACKED,
}, {
.fourcc = V4L2_PIX_FMT_BGR24,
.cxformat = ColorFormatRGB24,
.depth = 24,
.flags = FORMAT_FLAGS_PACKED,
}, {
.fourcc = V4L2_PIX_FMT_BGR32,
.cxformat = ColorFormatRGB32,
.depth = 32,
.flags = FORMAT_FLAGS_PACKED,
}, {
.fourcc = V4L2_PIX_FMT_RGB32,
.cxformat = ColorFormatRGB32 | ColorFormatBSWAP |
ColorFormatWSWAP,
.depth = 32,
.flags = FORMAT_FLAGS_PACKED,
}, {
.fourcc = V4L2_PIX_FMT_YUYV,
.cxformat = ColorFormatYUY2,
.depth = 16,
.flags = FORMAT_FLAGS_PACKED,
}, {
.fourcc = V4L2_PIX_FMT_UYVY,
.cxformat = ColorFormatYUY2 | ColorFormatBSWAP,
.depth = 16,
.flags = FORMAT_FLAGS_PACKED,
},
};
static const struct cx8800_fmt *format_by_fourcc(unsigned int fourcc)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(formats); i++)
if (formats[i].fourcc == fourcc)
return formats + i;
return NULL;
}
/* ------------------------------------------------------------------- */
struct cx88_ctrl {
/* control information */
u32 id;
s32 minimum;
s32 maximum;
u32 step;
s32 default_value;
/* control register information */
u32 off;
u32 reg;
u32 sreg;
u32 mask;
u32 shift;
};
static const struct cx88_ctrl cx8800_vid_ctls[] = {
/* --- video --- */
{
.id = V4L2_CID_BRIGHTNESS,
.minimum = 0x00,
.maximum = 0xff,
.step = 1,
.default_value = 0x7f,
.off = 128,
.reg = MO_CONTR_BRIGHT,
.mask = 0x00ff,
.shift = 0,
}, {
.id = V4L2_CID_CONTRAST,
.minimum = 0,
.maximum = 0xff,
.step = 1,
.default_value = 0x3f,
.off = 0,
.reg = MO_CONTR_BRIGHT,
.mask = 0xff00,
.shift = 8,
}, {
.id = V4L2_CID_HUE,
.minimum = 0,
.maximum = 0xff,
.step = 1,
.default_value = 0x7f,
.off = 128,
.reg = MO_HUE,
.mask = 0x00ff,
.shift = 0,
}, {
/* strictly, this only describes only U saturation.
* V saturation is handled specially through code.
*/
.id = V4L2_CID_SATURATION,
.minimum = 0,
.maximum = 0xff,
.step = 1,
.default_value = 0x7f,
.off = 0,
.reg = MO_UV_SATURATION,
.mask = 0x00ff,
.shift = 0,
}, {
.id = V4L2_CID_SHARPNESS,
.minimum = 0,
.maximum = 4,
.step = 1,
.default_value = 0x0,
.off = 0,
/*
* NOTE: the value is converted and written to both even
* and odd registers in the code
*/
.reg = MO_FILTER_ODD,
.mask = 7 << 7,
.shift = 7,
}, {
.id = V4L2_CID_CHROMA_AGC,
.minimum = 0,
.maximum = 1,
.default_value = 0x1,
.reg = MO_INPUT_FORMAT,
.mask = 1 << 10,
.shift = 10,
}, {
.id = V4L2_CID_COLOR_KILLER,
.minimum = 0,
.maximum = 1,
.default_value = 0x1,
.reg = MO_INPUT_FORMAT,
.mask = 1 << 9,
.shift = 9,
}, {
.id = V4L2_CID_BAND_STOP_FILTER,
.minimum = 0,
.maximum = 1,
.step = 1,
.default_value = 0x0,
.off = 0,
.reg = MO_HTOTAL,
.mask = 3 << 11,
.shift = 11,
}
};
static const struct cx88_ctrl cx8800_aud_ctls[] = {
{
/* --- audio --- */
.id = V4L2_CID_AUDIO_MUTE,
.minimum = 0,
.maximum = 1,
.default_value = 1,
.reg = AUD_VOL_CTL,
.sreg = SHADOW_AUD_VOL_CTL,
.mask = (1 << 6),
.shift = 6,
}, {
.id = V4L2_CID_AUDIO_VOLUME,
.minimum = 0,
.maximum = 0x3f,
.step = 1,
.default_value = 0x3f,
.reg = AUD_VOL_CTL,
.sreg = SHADOW_AUD_VOL_CTL,
.mask = 0x3f,
.shift = 0,
}, {
.id = V4L2_CID_AUDIO_BALANCE,
.minimum = 0,
.maximum = 0x7f,
.step = 1,
.default_value = 0x40,
.reg = AUD_BAL_CTL,
.sreg = SHADOW_AUD_BAL_CTL,
.mask = 0x7f,
.shift = 0,
}
};
enum {
CX8800_VID_CTLS = ARRAY_SIZE(cx8800_vid_ctls),
CX8800_AUD_CTLS = ARRAY_SIZE(cx8800_aud_ctls),
};
/* ------------------------------------------------------------------ */
int cx88_video_mux(struct cx88_core *core, unsigned int input)
{
/* struct cx88_core *core = dev->core; */
dprintk(1, "video_mux: %d [vmux=%d,gpio=0x%x,0x%x,0x%x,0x%x]\n",
input, INPUT(input).vmux,
INPUT(input).gpio0, INPUT(input).gpio1,
INPUT(input).gpio2, INPUT(input).gpio3);
core->input = input;
cx_andor(MO_INPUT_FORMAT, 0x03 << 14, INPUT(input).vmux << 14);
cx_write(MO_GP3_IO, INPUT(input).gpio3);
cx_write(MO_GP0_IO, INPUT(input).gpio0);
cx_write(MO_GP1_IO, INPUT(input).gpio1);
cx_write(MO_GP2_IO, INPUT(input).gpio2);
switch (INPUT(input).type) {
case CX88_VMUX_SVIDEO:
cx_set(MO_AFECFG_IO, 0x00000001);
cx_set(MO_INPUT_FORMAT, 0x00010010);
cx_set(MO_FILTER_EVEN, 0x00002020);
cx_set(MO_FILTER_ODD, 0x00002020);
break;
default:
cx_clear(MO_AFECFG_IO, 0x00000001);
cx_clear(MO_INPUT_FORMAT, 0x00010010);
cx_clear(MO_FILTER_EVEN, 0x00002020);
cx_clear(MO_FILTER_ODD, 0x00002020);
break;
}
/*
* if there are audioroutes defined, we have an external
* ADC to deal with audio
*/
if (INPUT(input).audioroute) {
/*
* The wm8775 module has the "2" route hardwired into
* the initialization. Some boards may use different
* routes for different inputs. HVR-1300 surely does
*/
if (core->sd_wm8775) {
call_all(core, audio, s_routing,
INPUT(input).audioroute, 0, 0);
}
/*
* cx2388's C-ADC is connected to the tuner only.
* When used with S-Video, that ADC is busy dealing with
* chroma, so an external must be used for baseband audio
*/
if (INPUT(input).type != CX88_VMUX_TELEVISION &&
INPUT(input).type != CX88_VMUX_CABLE) {
/* "I2S ADC mode" */
core->tvaudio = WW_I2SADC;
cx88_set_tvaudio(core);
} else {
/* Normal mode */
cx_write(AUD_I2SCNTL, 0x0);
cx_clear(AUD_CTL, EN_I2SIN_ENABLE);
}
}
return 0;
}
EXPORT_SYMBOL(cx88_video_mux);
/* ------------------------------------------------------------------ */
static int start_video_dma(struct cx8800_dev *dev,
struct cx88_dmaqueue *q,
struct cx88_buffer *buf)
{
struct cx88_core *core = dev->core;
/* setup fifo + format */
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21],
buf->bpl, buf->risc.dma);
cx88_set_scale(core, core->width, core->height, core->field);
cx_write(MO_COLOR_CTRL, dev->fmt->cxformat | ColorFormatGamma);
/* reset counter */
cx_write(MO_VIDY_GPCNTRL, GP_COUNT_CONTROL_RESET);
q->count = 0;
/* enable irqs */
cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
/*
* Enables corresponding bits at PCI_INT_STAT:
* bits 0 to 4: video, audio, transport stream, VIP, Host
* bit 7: timer
* bits 8 and 9: DMA complete for: SRC, DST
* bits 10 and 11: BERR signal asserted for RISC: RD, WR
* bits 12 to 15: BERR signal asserted for: BRDG, SRC, DST, IPB
*/
cx_set(MO_VID_INTMSK, 0x0f0011);
/* enable capture */
cx_set(VID_CAPTURE_CONTROL, 0x06);
/* start dma */
cx_set(MO_DEV_CNTRL2, (1 << 5));
cx_set(MO_VID_DMACNTRL, 0x11); /* Planar Y and packed FIFO and RISC enable */
return 0;
}
static int __maybe_unused stop_video_dma(struct cx8800_dev *dev)
{
struct cx88_core *core = dev->core;
/* stop dma */
cx_clear(MO_VID_DMACNTRL, 0x11);
/* disable capture */
cx_clear(VID_CAPTURE_CONTROL, 0x06);
/* disable irqs */
cx_clear(MO_PCI_INTMSK, PCI_INT_VIDINT);
cx_clear(MO_VID_INTMSK, 0x0f0011);
return 0;
}
static int __maybe_unused restart_video_queue(struct cx8800_dev *dev,
struct cx88_dmaqueue *q)
{
struct cx88_buffer *buf;
if (!list_empty(&q->active)) {
buf = list_entry(q->active.next, struct cx88_buffer, list);
dprintk(2, "restart_queue [%p/%d]: restart dma\n",
buf, buf->vb.vb2_buf.index);
start_video_dma(dev, q, buf);
}
return 0;
}
/* ------------------------------------------------------------------ */
static int queue_setup(struct vb2_queue *q,
unsigned int *num_buffers, unsigned int *num_planes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct cx8800_dev *dev = q->drv_priv;
struct cx88_core *core = dev->core;
*num_planes = 1;
sizes[0] = (dev->fmt->depth * core->width * core->height) >> 3;
return 0;
}
static int buffer_prepare(struct vb2_buffer *vb)
{
int ret;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_core *core = dev->core;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
buf->bpl = core->width * dev->fmt->depth >> 3;
if (vb2_plane_size(vb, 0) < core->height * buf->bpl)
return -EINVAL;
vb2_set_plane_payload(vb, 0, core->height * buf->bpl);
switch (core->field) {
case V4L2_FIELD_TOP:
ret = cx88_risc_buffer(dev->pci, &buf->risc,
sgt->sgl, 0, UNSET,
buf->bpl, 0, core->height);
break;
case V4L2_FIELD_BOTTOM:
ret = cx88_risc_buffer(dev->pci, &buf->risc,
sgt->sgl, UNSET, 0,
buf->bpl, 0, core->height);
break;
case V4L2_FIELD_SEQ_TB:
ret = cx88_risc_buffer(dev->pci, &buf->risc,
sgt->sgl,
0, buf->bpl * (core->height >> 1),
buf->bpl, 0,
core->height >> 1);
break;
case V4L2_FIELD_SEQ_BT:
ret = cx88_risc_buffer(dev->pci, &buf->risc,
sgt->sgl,
buf->bpl * (core->height >> 1), 0,
buf->bpl, 0,
core->height >> 1);
break;
case V4L2_FIELD_INTERLACED:
default:
ret = cx88_risc_buffer(dev->pci, &buf->risc,
sgt->sgl, 0, buf->bpl,
buf->bpl, buf->bpl,
core->height >> 1);
break;
}
dprintk(2,
"[%p/%d] %s - %dx%d %dbpp 0x%08x - dma=0x%08lx\n",
buf, buf->vb.vb2_buf.index, __func__,
core->width, core->height, dev->fmt->depth, dev->fmt->fourcc,
(unsigned long)buf->risc.dma);
return ret;
}
static void buffer_finish(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
struct cx88_riscmem *risc = &buf->risc;
if (risc->cpu)
dma_free_coherent(&dev->pci->dev, risc->size, risc->cpu,
risc->dma);
memset(risc, 0, sizeof(*risc));
}
static void buffer_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
struct cx88_buffer *prev;
struct cx88_dmaqueue *q = &dev->vidq;
/* add jump to start */
buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8);
buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8);
if (list_empty(&q->active)) {
list_add_tail(&buf->list, &q->active);
dprintk(2, "[%p/%d] buffer_queue - first active\n",
buf, buf->vb.vb2_buf.index);
} else {
buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
prev = list_entry(q->active.prev, struct cx88_buffer, list);
list_add_tail(&buf->list, &q->active);
prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
dprintk(2, "[%p/%d] buffer_queue - append to active\n",
buf, buf->vb.vb2_buf.index);
}
}
static int start_streaming(struct vb2_queue *q, unsigned int count)
{
struct cx8800_dev *dev = q->drv_priv;
struct cx88_dmaqueue *dmaq = &dev->vidq;
struct cx88_buffer *buf = list_entry(dmaq->active.next,
struct cx88_buffer, list);
start_video_dma(dev, dmaq, buf);
return 0;
}
static void stop_streaming(struct vb2_queue *q)
{
struct cx8800_dev *dev = q->drv_priv;
struct cx88_core *core = dev->core;
struct cx88_dmaqueue *dmaq = &dev->vidq;
unsigned long flags;
cx_clear(MO_VID_DMACNTRL, 0x11);
cx_clear(VID_CAPTURE_CONTROL, 0x06);
spin_lock_irqsave(&dev->slock, flags);
while (!list_empty(&dmaq->active)) {
struct cx88_buffer *buf = list_entry(dmaq->active.next,
struct cx88_buffer, list);
list_del(&buf->list);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&dev->slock, flags);
}
static const struct vb2_ops cx8800_video_qops = {
.queue_setup = queue_setup,
.buf_prepare = buffer_prepare,
.buf_finish = buffer_finish,
.buf_queue = buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = start_streaming,
.stop_streaming = stop_streaming,
};
/* ------------------------------------------------------------------ */
static int radio_open(struct file *file)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
int ret = v4l2_fh_open(file);
if (ret)
return ret;
cx_write(MO_GP3_IO, core->board.radio.gpio3);
cx_write(MO_GP0_IO, core->board.radio.gpio0);
cx_write(MO_GP1_IO, core->board.radio.gpio1);
cx_write(MO_GP2_IO, core->board.radio.gpio2);
if (core->board.radio.audioroute) {
if (core->sd_wm8775) {
call_all(core, audio, s_routing,
core->board.radio.audioroute, 0, 0);
}
/* "I2S ADC mode" */
core->tvaudio = WW_I2SADC;
cx88_set_tvaudio(core);
} else {
/* FM Mode */
core->tvaudio = WW_FM;
cx88_set_tvaudio(core);
cx88_set_stereo(core, V4L2_TUNER_MODE_STEREO, 1);
}
call_all(core, tuner, s_radio);
return 0;
}
/* ------------------------------------------------------------------ */
/* VIDEO CTRL IOCTLS */
static int cx8800_s_vid_ctrl(struct v4l2_ctrl *ctrl)
{
struct cx88_core *core =
container_of(ctrl->handler, struct cx88_core, video_hdl);
const struct cx88_ctrl *cc = ctrl->priv;
u32 value, mask;
mask = cc->mask;
switch (ctrl->id) {
case V4L2_CID_SATURATION:
/* special v_sat handling */
value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
if (core->tvnorm & V4L2_STD_SECAM) {
/* For SECAM, both U and V sat should be equal */
value = value << 8 | value;
} else {
/* Keeps U Saturation proportional to V Sat */
value = (value * 0x5a) / 0x7f << 8 | value;
}
mask = 0xffff;
break;
case V4L2_CID_SHARPNESS:
/* 0b000, 0b100, 0b101, 0b110, or 0b111 */
value = (ctrl->val < 1 ? 0 : ((ctrl->val + 3) << 7));
/* needs to be set for both fields */
cx_andor(MO_FILTER_EVEN, mask, value);
break;
case V4L2_CID_CHROMA_AGC:
value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
break;
default:
value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
break;
}
dprintk(1,
"set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n",
ctrl->id, ctrl->name, ctrl->val, cc->reg, value,
mask, cc->sreg ? " [shadowed]" : "");
if (cc->sreg)
cx_sandor(cc->sreg, cc->reg, mask, value);
else
cx_andor(cc->reg, mask, value);
return 0;
}
static int cx8800_s_aud_ctrl(struct v4l2_ctrl *ctrl)
{
struct cx88_core *core =
container_of(ctrl->handler, struct cx88_core, audio_hdl);
const struct cx88_ctrl *cc = ctrl->priv;
u32 value, mask;
/* Pass changes onto any WM8775 */
if (core->sd_wm8775) {
switch (ctrl->id) {
case V4L2_CID_AUDIO_MUTE:
wm8775_s_ctrl(core, ctrl->id, ctrl->val);
break;
case V4L2_CID_AUDIO_VOLUME:
wm8775_s_ctrl(core, ctrl->id, (ctrl->val) ?
(0x90 + ctrl->val) << 8 : 0);
break;
case V4L2_CID_AUDIO_BALANCE:
wm8775_s_ctrl(core, ctrl->id, ctrl->val << 9);
break;
default:
break;
}
}
mask = cc->mask;
switch (ctrl->id) {
case V4L2_CID_AUDIO_BALANCE:
value = (ctrl->val < 0x40) ?
(0x7f - ctrl->val) : (ctrl->val - 0x40);
break;
case V4L2_CID_AUDIO_VOLUME:
value = 0x3f - (ctrl->val & 0x3f);
break;
default:
value = ((ctrl->val - cc->off) << cc->shift) & cc->mask;
break;
}
dprintk(1,
"set_control id=0x%X(%s) ctrl=0x%02x, reg=0x%02x val=0x%02x (mask 0x%02x)%s\n",
ctrl->id, ctrl->name, ctrl->val, cc->reg, value,
mask, cc->sreg ? " [shadowed]" : "");
if (cc->sreg)
cx_sandor(cc->sreg, cc->reg, mask, value);
else
cx_andor(cc->reg, mask, value);
return 0;
}
/* ------------------------------------------------------------------ */
/* VIDEO IOCTLS */
static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
f->fmt.pix.width = core->width;
f->fmt.pix.height = core->height;
f->fmt.pix.field = core->field;
f->fmt.pix.pixelformat = dev->fmt->fourcc;
f->fmt.pix.bytesperline =
(f->fmt.pix.width * dev->fmt->depth) >> 3;
f->fmt.pix.sizeimage =
f->fmt.pix.height * f->fmt.pix.bytesperline;
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
return 0;
}
static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
const struct cx8800_fmt *fmt;
enum v4l2_field field;
unsigned int maxw, maxh;
fmt = format_by_fourcc(f->fmt.pix.pixelformat);
if (!fmt)
return -EINVAL;
maxw = norm_maxw(core->tvnorm);
maxh = norm_maxh(core->tvnorm);
field = f->fmt.pix.field;
switch (field) {
case V4L2_FIELD_TOP:
case V4L2_FIELD_BOTTOM:
case V4L2_FIELD_INTERLACED:
case V4L2_FIELD_SEQ_BT:
case V4L2_FIELD_SEQ_TB:
break;
default:
field = (f->fmt.pix.height > maxh / 2)
? V4L2_FIELD_INTERLACED
: V4L2_FIELD_BOTTOM;
break;
}
if (V4L2_FIELD_HAS_T_OR_B(field))
maxh /= 2;
v4l_bound_align_image(&f->fmt.pix.width, 48, maxw, 2,
&f->fmt.pix.height, 32, maxh, 0, 0);
f->fmt.pix.field = field;
f->fmt.pix.bytesperline =
(f->fmt.pix.width * fmt->depth) >> 3;
f->fmt.pix.sizeimage =
f->fmt.pix.height * f->fmt.pix.bytesperline;
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
return 0;
}
static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
int err = vidioc_try_fmt_vid_cap(file, priv, f);
if (err != 0)
return err;
if (vb2_is_busy(&dev->vb2_vidq) || vb2_is_busy(&dev->vb2_vbiq))
return -EBUSY;
if (core->dvbdev && vb2_is_busy(&core->dvbdev->vb2_mpegq))
return -EBUSY;
dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
core->width = f->fmt.pix.width;
core->height = f->fmt.pix.height;
core->field = f->fmt.pix.field;
return 0;
}
int cx88_querycap(struct file *file, struct cx88_core *core,
struct v4l2_capability *cap)
{
strscpy(cap->card, core->board.name, sizeof(cap->card));
cap->capabilities = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VBI_CAPTURE |
V4L2_CAP_DEVICE_CAPS;
if (core->board.tuner_type != UNSET)
cap->capabilities |= V4L2_CAP_TUNER;
if (core->board.radio.type == CX88_RADIO)
cap->capabilities |= V4L2_CAP_RADIO;
return 0;
}
EXPORT_SYMBOL(cx88_querycap);
static int vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
strscpy(cap->driver, "cx8800", sizeof(cap->driver));
return cx88_querycap(file, core, cap);
}
static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
if (unlikely(f->index >= ARRAY_SIZE(formats)))
return -EINVAL;
f->pixelformat = formats[f->index].fourcc;
return 0;
}
static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorm)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
*tvnorm = core->tvnorm;
return 0;
}
static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id tvnorms)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
return cx88_set_tvnorm(core, tvnorms);
}
/* only one input in this sample driver */
int cx88_enum_input(struct cx88_core *core, struct v4l2_input *i)
{
static const char * const iname[] = {
[CX88_VMUX_COMPOSITE1] = "Composite1",
[CX88_VMUX_COMPOSITE2] = "Composite2",
[CX88_VMUX_COMPOSITE3] = "Composite3",
[CX88_VMUX_COMPOSITE4] = "Composite4",
[CX88_VMUX_SVIDEO] = "S-Video",
[CX88_VMUX_TELEVISION] = "Television",
[CX88_VMUX_CABLE] = "Cable TV",
[CX88_VMUX_DVB] = "DVB",
[CX88_VMUX_DEBUG] = "for debug only",
};
unsigned int n = i->index;
if (n >= 4)
return -EINVAL;
if (!INPUT(n).type)
return -EINVAL;
i->type = V4L2_INPUT_TYPE_CAMERA;
strscpy(i->name, iname[INPUT(n).type], sizeof(i->name));
if ((INPUT(n).type == CX88_VMUX_TELEVISION) ||
(INPUT(n).type == CX88_VMUX_CABLE))
i->type = V4L2_INPUT_TYPE_TUNER;
i->std = CX88_NORMS;
return 0;
}
EXPORT_SYMBOL(cx88_enum_input);
static int vidioc_enum_input(struct file *file, void *priv,
struct v4l2_input *i)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
return cx88_enum_input(core, i);
}
static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
*i = core->input;
return 0;
}
static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
if (i >= 4)
return -EINVAL;
if (!INPUT(i).type)
return -EINVAL;
cx88_newstation(core);
cx88_video_mux(core, i);
return 0;
}
static int vidioc_g_tuner(struct file *file, void *priv,
struct v4l2_tuner *t)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
u32 reg;
if (unlikely(core->board.tuner_type == UNSET))
return -EINVAL;
if (t->index != 0)
return -EINVAL;
strscpy(t->name, "Television", sizeof(t->name));
t->capability = V4L2_TUNER_CAP_NORM;
t->rangehigh = 0xffffffffUL;
call_all(core, tuner, g_tuner, t);
cx88_get_stereo(core, t);
reg = cx_read(MO_DEVICE_STATUS);
t->signal = (reg & (1 << 5)) ? 0xffff : 0x0000;
return 0;
}
static int vidioc_s_tuner(struct file *file, void *priv,
const struct v4l2_tuner *t)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
if (core->board.tuner_type == UNSET)
return -EINVAL;
if (t->index != 0)
return -EINVAL;
cx88_set_stereo(core, t->audmode, 1);
return 0;
}
static int vidioc_g_frequency(struct file *file, void *priv,
struct v4l2_frequency *f)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
if (unlikely(core->board.tuner_type == UNSET))
return -EINVAL;
if (f->tuner)
return -EINVAL;
f->frequency = core->freq;
call_all(core, tuner, g_frequency, f);
return 0;
}
int cx88_set_freq(struct cx88_core *core,
const struct v4l2_frequency *f)
{
struct v4l2_frequency new_freq = *f;
if (unlikely(core->board.tuner_type == UNSET))
return -EINVAL;
if (unlikely(f->tuner != 0))
return -EINVAL;
cx88_newstation(core);
call_all(core, tuner, s_frequency, f);
call_all(core, tuner, g_frequency, &new_freq);
core->freq = new_freq.frequency;
/* When changing channels it is required to reset TVAUDIO */
usleep_range(10000, 20000);
cx88_set_tvaudio(core);
return 0;
}
EXPORT_SYMBOL(cx88_set_freq);
static int vidioc_s_frequency(struct file *file, void *priv,
const struct v4l2_frequency *f)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
return cx88_set_freq(core, f);
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int vidioc_g_register(struct file *file, void *fh,
struct v4l2_dbg_register *reg)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
/* cx2388x has a 24-bit register space */
reg->val = cx_read(reg->reg & 0xfffffc);
reg->size = 4;
return 0;
}
static int vidioc_s_register(struct file *file, void *fh,
const struct v4l2_dbg_register *reg)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
cx_write(reg->reg & 0xfffffc, reg->val);
return 0;
}
#endif
/* ----------------------------------------------------------- */
/* RADIO ESPECIFIC IOCTLS */
/* ----------------------------------------------------------- */
static int radio_g_tuner(struct file *file, void *priv,
struct v4l2_tuner *t)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
if (unlikely(t->index > 0))
return -EINVAL;
strscpy(t->name, "Radio", sizeof(t->name));
call_all(core, tuner, g_tuner, t);
return 0;
}
static int radio_s_tuner(struct file *file, void *priv,
const struct v4l2_tuner *t)
{
struct cx8800_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
if (t->index != 0)
return -EINVAL;
call_all(core, tuner, s_tuner, t);
return 0;
}
/* ----------------------------------------------------------- */
static const char *cx88_vid_irqs[32] = {
"y_risci1", "u_risci1", "v_risci1", "vbi_risc1",
"y_risci2", "u_risci2", "v_risci2", "vbi_risc2",
"y_oflow", "u_oflow", "v_oflow", "vbi_oflow",
"y_sync", "u_sync", "v_sync", "vbi_sync",
"opc_err", "par_err", "rip_err", "pci_abort",
};
static void cx8800_vid_irq(struct cx8800_dev *dev)
{
struct cx88_core *core = dev->core;
u32 status, mask, count;
status = cx_read(MO_VID_INTSTAT);
mask = cx_read(MO_VID_INTMSK);
if (0 == (status & mask))
return;
cx_write(MO_VID_INTSTAT, status);
if (irq_debug || (status & mask & ~0xff))
cx88_print_irqbits("irq vid",
cx88_vid_irqs, ARRAY_SIZE(cx88_vid_irqs),
status, mask);
/* risc op code error */
if (status & (1 << 16)) {
pr_warn("video risc op code error\n");
cx_clear(MO_VID_DMACNTRL, 0x11);
cx_clear(VID_CAPTURE_CONTROL, 0x06);
cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH21]);
}
/* risc1 y */
if (status & 0x01) {
spin_lock(&dev->slock);
count = cx_read(MO_VIDY_GPCNT);
cx88_wakeup(core, &dev->vidq, count);
spin_unlock(&dev->slock);
}
/* risc1 vbi */
if (status & 0x08) {
spin_lock(&dev->slock);
count = cx_read(MO_VBI_GPCNT);
cx88_wakeup(core, &dev->vbiq, count);
spin_unlock(&dev->slock);
}
}
static irqreturn_t cx8800_irq(int irq, void *dev_id)
{
struct cx8800_dev *dev = dev_id;
struct cx88_core *core = dev->core;
u32 status;
int loop, handled = 0;
for (loop = 0; loop < 10; loop++) {
status = cx_read(MO_PCI_INTSTAT) &
(core->pci_irqmask | PCI_INT_VIDINT);
if (status == 0)
goto out;
cx_write(MO_PCI_INTSTAT, status);
handled = 1;
if (status & core->pci_irqmask)
cx88_core_irq(core, status);
if (status & PCI_INT_VIDINT)
cx8800_vid_irq(dev);
}
if (loop == 10) {
pr_warn("irq loop -- clearing mask\n");
cx_write(MO_PCI_INTMSK, 0);
}
out:
return IRQ_RETVAL(handled);
}
/* ----------------------------------------------------------- */
/* exported stuff */
static const struct v4l2_file_operations video_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.release = vb2_fop_release,
.read = vb2_fop_read,
.poll = vb2_fop_poll,
.mmap = vb2_fop_mmap,
.unlocked_ioctl = video_ioctl2,
};
static const struct v4l2_ioctl_ops video_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_g_std = vidioc_g_std,
.vidioc_s_std = vidioc_s_std,
.vidioc_enum_input = vidioc_enum_input,
.vidioc_g_input = vidioc_g_input,
.vidioc_s_input = vidioc_s_input,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_g_frequency = vidioc_g_frequency,
.vidioc_s_frequency = vidioc_s_frequency,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.vidioc_g_register = vidioc_g_register,
.vidioc_s_register = vidioc_s_register,
#endif
};
static const struct video_device cx8800_video_template = {
.name = "cx8800-video",
.fops = &video_fops,
.ioctl_ops = &video_ioctl_ops,
.tvnorms = CX88_NORMS,
};
static const struct v4l2_ioctl_ops vbi_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_fmt_vbi_cap = cx8800_vbi_fmt,
.vidioc_try_fmt_vbi_cap = cx8800_vbi_fmt,
.vidioc_s_fmt_vbi_cap = cx8800_vbi_fmt,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_g_std = vidioc_g_std,
.vidioc_s_std = vidioc_s_std,
.vidioc_enum_input = vidioc_enum_input,
.vidioc_g_input = vidioc_g_input,
.vidioc_s_input = vidioc_s_input,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_g_frequency = vidioc_g_frequency,
.vidioc_s_frequency = vidioc_s_frequency,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.vidioc_g_register = vidioc_g_register,
.vidioc_s_register = vidioc_s_register,
#endif
};
static const struct video_device cx8800_vbi_template = {
.name = "cx8800-vbi",
.fops = &video_fops,
.ioctl_ops = &vbi_ioctl_ops,
.tvnorms = CX88_NORMS,
};
static const struct v4l2_file_operations radio_fops = {
.owner = THIS_MODULE,
.open = radio_open,
.poll = v4l2_ctrl_poll,
.release = v4l2_fh_release,
.unlocked_ioctl = video_ioctl2,
};
static const struct v4l2_ioctl_ops radio_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_g_tuner = radio_g_tuner,
.vidioc_s_tuner = radio_s_tuner,
.vidioc_g_frequency = vidioc_g_frequency,
.vidioc_s_frequency = vidioc_s_frequency,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.vidioc_g_register = vidioc_g_register,
.vidioc_s_register = vidioc_s_register,
#endif
};
static const struct video_device cx8800_radio_template = {
.name = "cx8800-radio",
.fops = &radio_fops,
.ioctl_ops = &radio_ioctl_ops,
};
static const struct v4l2_ctrl_ops cx8800_ctrl_vid_ops = {
.s_ctrl = cx8800_s_vid_ctrl,
};
static const struct v4l2_ctrl_ops cx8800_ctrl_aud_ops = {
.s_ctrl = cx8800_s_aud_ctrl,
};
/* ----------------------------------------------------------- */
static void cx8800_unregister_video(struct cx8800_dev *dev)
{
video_unregister_device(&dev->radio_dev);
video_unregister_device(&dev->vbi_dev);
video_unregister_device(&dev->video_dev);
}
static int cx8800_initdev(struct pci_dev *pci_dev,
const struct pci_device_id *pci_id)
{
struct cx8800_dev *dev;
struct cx88_core *core;
struct vb2_queue *q;
int err;
int i;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
/* pci init */
dev->pci = pci_dev;
if (pci_enable_device(pci_dev)) {
err = -EIO;
goto fail_free;
}
core = cx88_core_get(dev->pci);
if (!core) {
err = -EINVAL;
goto fail_disable;
}
dev->core = core;
/* print pci info */
dev->pci_rev = pci_dev->revision;
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
pr_info("found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
dev->pci_lat,
(unsigned long long)pci_resource_start(pci_dev, 0));
pci_set_master(pci_dev);
err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32));
if (err) {
pr_err("Oops: no 32bit PCI DMA ???\n");
goto fail_core;
}
/* initialize driver struct */
spin_lock_init(&dev->slock);
/* init video dma queues */
INIT_LIST_HEAD(&dev->vidq.active);
/* init vbi dma queues */
INIT_LIST_HEAD(&dev->vbiq.active);
/* get irq */
err = request_irq(pci_dev->irq, cx8800_irq,
IRQF_SHARED, core->name, dev);
if (err < 0) {
pr_err("can't get IRQ %d\n", pci_dev->irq);
goto fail_core;
}
cx_set(MO_PCI_INTMSK, core->pci_irqmask);
for (i = 0; i < CX8800_AUD_CTLS; i++) {
const struct cx88_ctrl *cc = &cx8800_aud_ctls[i];
struct v4l2_ctrl *vc;
vc = v4l2_ctrl_new_std(&core->audio_hdl, &cx8800_ctrl_aud_ops,
cc->id, cc->minimum, cc->maximum,
cc->step, cc->default_value);
if (!vc) {
err = core->audio_hdl.error;
goto fail_irq;
}
vc->priv = (void *)cc;
}
for (i = 0; i < CX8800_VID_CTLS; i++) {
const struct cx88_ctrl *cc = &cx8800_vid_ctls[i];
struct v4l2_ctrl *vc;
vc = v4l2_ctrl_new_std(&core->video_hdl, &cx8800_ctrl_vid_ops,
cc->id, cc->minimum, cc->maximum,
cc->step, cc->default_value);
if (!vc) {
err = core->video_hdl.error;
goto fail_irq;
}
vc->priv = (void *)cc;
if (vc->id == V4L2_CID_CHROMA_AGC)
core->chroma_agc = vc;
}
v4l2_ctrl_add_handler(&core->video_hdl, &core->audio_hdl, NULL, false);
/* load and configure helper modules */
if (core->board.audio_chip == CX88_AUDIO_WM8775) {
struct i2c_board_info wm8775_info = {
.type = "wm8775",
.addr = 0x36 >> 1,
.platform_data = &core->wm8775_data,
};
struct v4l2_subdev *sd;
if (core->boardnr == CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1)
core->wm8775_data.is_nova_s = true;
else
core->wm8775_data.is_nova_s = false;
sd = v4l2_i2c_new_subdev_board(&core->v4l2_dev, &core->i2c_adap,
&wm8775_info, NULL);
if (sd) {
core->sd_wm8775 = sd;
sd->grp_id = WM8775_GID;
}
}
if (core->board.audio_chip == CX88_AUDIO_TVAUDIO) {
/*
* This probes for a tda9874 as is used on some
* Pixelview Ultra boards.
*/
v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap,
"tvaudio", 0, I2C_ADDRS(0xb0 >> 1));
}
switch (core->boardnr) {
case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: {
static const struct i2c_board_info rtc_info = {
I2C_BOARD_INFO("isl1208", 0x6f)
};
request_module("rtc-isl1208");
core->i2c_rtc = i2c_new_client_device(&core->i2c_adap, &rtc_info);
}
fallthrough;
case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
case CX88_BOARD_NOTONLYTV_LV3H:
request_module("ir-kbd-i2c");
}
/* Sets device info at pci_dev */
pci_set_drvdata(pci_dev, dev);
dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24);
/* Maintain a reference so cx88-blackbird can query the 8800 device. */
core->v4ldev = dev;
/* initial device configuration */
mutex_lock(&core->lock);
cx88_set_tvnorm(core, V4L2_STD_NTSC_M);
v4l2_ctrl_handler_setup(&core->video_hdl);
v4l2_ctrl_handler_setup(&core->audio_hdl);
cx88_video_mux(core, 0);
q = &dev->vb2_vidq;
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
q->gfp_flags = GFP_DMA32;
q->min_buffers_needed = 2;
q->drv_priv = dev;
q->buf_struct_size = sizeof(struct cx88_buffer);
q->ops = &cx8800_video_qops;
q->mem_ops = &vb2_dma_sg_memops;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &core->lock;
q->dev = &dev->pci->dev;
err = vb2_queue_init(q);
if (err < 0)
goto fail_unreg;
q = &dev->vb2_vbiq;
q->type = V4L2_BUF_TYPE_VBI_CAPTURE;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
q->gfp_flags = GFP_DMA32;
q->min_buffers_needed = 2;
q->drv_priv = dev;
q->buf_struct_size = sizeof(struct cx88_buffer);
q->ops = &cx8800_vbi_qops;
q->mem_ops = &vb2_dma_sg_memops;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &core->lock;
q->dev = &dev->pci->dev;
err = vb2_queue_init(q);
if (err < 0)
goto fail_unreg;
/* register v4l devices */
cx88_vdev_init(core, dev->pci, &dev->video_dev,
&cx8800_video_template, "video");
video_set_drvdata(&dev->video_dev, dev);
dev->video_dev.ctrl_handler = &core->video_hdl;
dev->video_dev.queue = &dev->vb2_vidq;
dev->video_dev.device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
V4L2_CAP_VIDEO_CAPTURE;
if (core->board.tuner_type != UNSET)
dev->video_dev.device_caps |= V4L2_CAP_TUNER;
err = video_register_device(&dev->video_dev, VFL_TYPE_VIDEO,
video_nr[core->nr]);
if (err < 0) {
pr_err("can't register video device\n");
goto fail_unreg;
}
pr_info("registered device %s [v4l2]\n",
video_device_node_name(&dev->video_dev));
cx88_vdev_init(core, dev->pci, &dev->vbi_dev,
&cx8800_vbi_template, "vbi");
video_set_drvdata(&dev->vbi_dev, dev);
dev->vbi_dev.queue = &dev->vb2_vbiq;
dev->vbi_dev.device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
V4L2_CAP_VBI_CAPTURE;
if (core->board.tuner_type != UNSET)
dev->vbi_dev.device_caps |= V4L2_CAP_TUNER;
err = video_register_device(&dev->vbi_dev, VFL_TYPE_VBI,
vbi_nr[core->nr]);
if (err < 0) {
pr_err("can't register vbi device\n");
goto fail_unreg;
}
pr_info("registered device %s\n",
video_device_node_name(&dev->vbi_dev));
if (core->board.radio.type == CX88_RADIO) {
cx88_vdev_init(core, dev->pci, &dev->radio_dev,
&cx8800_radio_template, "radio");
video_set_drvdata(&dev->radio_dev, dev);
dev->radio_dev.ctrl_handler = &core->audio_hdl;
dev->radio_dev.device_caps = V4L2_CAP_RADIO | V4L2_CAP_TUNER;
err = video_register_device(&dev->radio_dev, VFL_TYPE_RADIO,
radio_nr[core->nr]);
if (err < 0) {
pr_err("can't register radio device\n");
goto fail_unreg;
}
pr_info("registered device %s\n",
video_device_node_name(&dev->radio_dev));
}
/* start tvaudio thread */
if (core->board.tuner_type != UNSET) {
core->kthread = kthread_run(cx88_audio_thread,
core, "cx88 tvaudio");
if (IS_ERR(core->kthread)) {
err = PTR_ERR(core->kthread);
pr_err("failed to create cx88 audio thread, err=%d\n",
err);
}
}
mutex_unlock(&core->lock);
return 0;
fail_unreg:
cx8800_unregister_video(dev);
mutex_unlock(&core->lock);
fail_irq:
free_irq(pci_dev->irq, dev);
fail_core:
core->v4ldev = NULL;
cx88_core_put(core, dev->pci);
fail_disable:
pci_disable_device(pci_dev);
fail_free:
kfree(dev);
return err;
}
static void cx8800_finidev(struct pci_dev *pci_dev)
{
struct cx8800_dev *dev = pci_get_drvdata(pci_dev);
struct cx88_core *core = dev->core;
/* stop thread */
if (core->kthread) {
kthread_stop(core->kthread);
core->kthread = NULL;
}
if (core->ir)
cx88_ir_stop(core);
cx88_shutdown(core); /* FIXME */
/* unregister stuff */
free_irq(pci_dev->irq, dev);
cx8800_unregister_video(dev);
pci_disable_device(pci_dev);
core->v4ldev = NULL;
/* free memory */
cx88_core_put(core, dev->pci);
kfree(dev);
}
static int __maybe_unused cx8800_suspend(struct device *dev_d)
{
struct cx8800_dev *dev = dev_get_drvdata(dev_d);
struct cx88_core *core = dev->core;
unsigned long flags;
/* stop video+vbi capture */
spin_lock_irqsave(&dev->slock, flags);
if (!list_empty(&dev->vidq.active)) {
pr_info("suspend video\n");
stop_video_dma(dev);
}
if (!list_empty(&dev->vbiq.active)) {
pr_info("suspend vbi\n");
cx8800_stop_vbi_dma(dev);
}
spin_unlock_irqrestore(&dev->slock, flags);
if (core->ir)
cx88_ir_stop(core);
/* FIXME -- shutdown device */
cx88_shutdown(core);
dev->state.disabled = 1;
return 0;
}
static int __maybe_unused cx8800_resume(struct device *dev_d)
{
struct cx8800_dev *dev = dev_get_drvdata(dev_d);
struct cx88_core *core = dev->core;
unsigned long flags;
dev->state.disabled = 0;
/* FIXME: re-initialize hardware */
cx88_reset(core);
if (core->ir)
cx88_ir_start(core);
cx_set(MO_PCI_INTMSK, core->pci_irqmask);
/* restart video+vbi capture */
spin_lock_irqsave(&dev->slock, flags);
if (!list_empty(&dev->vidq.active)) {
pr_info("resume video\n");
restart_video_queue(dev, &dev->vidq);
}
if (!list_empty(&dev->vbiq.active)) {
pr_info("resume vbi\n");
cx8800_restart_vbi_queue(dev, &dev->vbiq);
}
spin_unlock_irqrestore(&dev->slock, flags);
return 0;
}
/* ----------------------------------------------------------- */
static const struct pci_device_id cx8800_pci_tbl[] = {
{
.vendor = 0x14f1,
.device = 0x8800,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
}, {
/* --- end of list --- */
}
};
MODULE_DEVICE_TABLE(pci, cx8800_pci_tbl);
static SIMPLE_DEV_PM_OPS(cx8800_pm_ops, cx8800_suspend, cx8800_resume);
static struct pci_driver cx8800_pci_driver = {
.name = "cx8800",
.id_table = cx8800_pci_tbl,
.probe = cx8800_initdev,
.remove = cx8800_finidev,
.driver.pm = &cx8800_pm_ops,
};
module_pci_driver(cx8800_pci_driver);
| linux-master | drivers/media/pci/cx88/cx88-video.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for a cx23416 mpeg encoder via cx2388x host port.
* "blackbird" reference design.
*
* (c) 2004 Jelle Foks <[email protected]>
* (c) 2004 Gerd Knorr <[email protected]>
*
* (c) 2005-2006 Mauro Carvalho Chehab <[email protected]>
* - video_ioctl2 conversion
*
* Includes parts from the ivtv driver <http://sourceforge.net/projects/ivtv/>
*/
#include "cx88.h"
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/fs.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/firmware.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-event.h>
#include <media/drv-intf/cx2341x.h>
MODULE_DESCRIPTION("driver for cx2388x/cx23416 based mpeg encoder cards");
MODULE_AUTHOR("Jelle Foks <[email protected]>, Gerd Knorr <[email protected]> [SuSE Labs]");
MODULE_LICENSE("GPL v2");
MODULE_VERSION(CX88_VERSION);
static unsigned int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable debug messages [blackbird]");
#define dprintk(level, fmt, arg...) do { \
if (debug + 1 > level) \
printk(KERN_DEBUG pr_fmt("%s: blackbird:" fmt), \
__func__, ##arg); \
} while (0)
/* ------------------------------------------------------------------ */
#define BLACKBIRD_FIRM_IMAGE_SIZE 376836
/* defines below are from ivtv-driver.h */
#define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
/* Firmware API commands */
#define IVTV_API_STD_TIMEOUT 500
enum blackbird_capture_type {
BLACKBIRD_MPEG_CAPTURE,
BLACKBIRD_RAW_CAPTURE,
BLACKBIRD_RAW_PASSTHRU_CAPTURE
};
enum blackbird_capture_bits {
BLACKBIRD_RAW_BITS_NONE = 0x00,
BLACKBIRD_RAW_BITS_YUV_CAPTURE = 0x01,
BLACKBIRD_RAW_BITS_PCM_CAPTURE = 0x02,
BLACKBIRD_RAW_BITS_VBI_CAPTURE = 0x04,
BLACKBIRD_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
BLACKBIRD_RAW_BITS_TO_HOST_CAPTURE = 0x10
};
enum blackbird_capture_end {
BLACKBIRD_END_AT_GOP, /* stop at the end of gop, generate irq */
BLACKBIRD_END_NOW, /* stop immediately, no irq */
};
enum blackbird_framerate {
BLACKBIRD_FRAMERATE_NTSC_30, /* NTSC: 30fps */
BLACKBIRD_FRAMERATE_PAL_25 /* PAL: 25fps */
};
enum blackbird_stream_port {
BLACKBIRD_OUTPUT_PORT_MEMORY,
BLACKBIRD_OUTPUT_PORT_STREAMING,
BLACKBIRD_OUTPUT_PORT_SERIAL
};
enum blackbird_data_xfer_status {
BLACKBIRD_MORE_BUFFERS_FOLLOW,
BLACKBIRD_LAST_BUFFER,
};
enum blackbird_picture_mask {
BLACKBIRD_PICTURE_MASK_NONE,
BLACKBIRD_PICTURE_MASK_I_FRAMES,
BLACKBIRD_PICTURE_MASK_I_P_FRAMES = 0x3,
BLACKBIRD_PICTURE_MASK_ALL_FRAMES = 0x7,
};
enum blackbird_vbi_mode_bits {
BLACKBIRD_VBI_BITS_SLICED,
BLACKBIRD_VBI_BITS_RAW,
};
enum blackbird_vbi_insertion_bits {
BLACKBIRD_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
BLACKBIRD_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
BLACKBIRD_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
BLACKBIRD_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
BLACKBIRD_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
};
enum blackbird_dma_unit {
BLACKBIRD_DMA_BYTES,
BLACKBIRD_DMA_FRAMES,
};
enum blackbird_dma_transfer_status_bits {
BLACKBIRD_DMA_TRANSFER_BITS_DONE = 0x01,
BLACKBIRD_DMA_TRANSFER_BITS_ERROR = 0x04,
BLACKBIRD_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
};
enum blackbird_pause {
BLACKBIRD_PAUSE_ENCODING,
BLACKBIRD_RESUME_ENCODING,
};
enum blackbird_copyright {
BLACKBIRD_COPYRIGHT_OFF,
BLACKBIRD_COPYRIGHT_ON,
};
enum blackbird_notification_type {
BLACKBIRD_NOTIFICATION_REFRESH,
};
enum blackbird_notification_status {
BLACKBIRD_NOTIFICATION_OFF,
BLACKBIRD_NOTIFICATION_ON,
};
enum blackbird_notification_mailbox {
BLACKBIRD_NOTIFICATION_NO_MAILBOX = -1,
};
enum blackbird_field1_lines {
BLACKBIRD_FIELD1_SAA7114 = 0x00EF, /* 239 */
BLACKBIRD_FIELD1_SAA7115 = 0x00F0, /* 240 */
BLACKBIRD_FIELD1_MICRONAS = 0x0105, /* 261 */
};
enum blackbird_field2_lines {
BLACKBIRD_FIELD2_SAA7114 = 0x00EF, /* 239 */
BLACKBIRD_FIELD2_SAA7115 = 0x00F0, /* 240 */
BLACKBIRD_FIELD2_MICRONAS = 0x0106, /* 262 */
};
enum blackbird_custom_data_type {
BLACKBIRD_CUSTOM_EXTENSION_USR_DATA,
BLACKBIRD_CUSTOM_PRIVATE_PACKET,
};
enum blackbird_mute {
BLACKBIRD_UNMUTE,
BLACKBIRD_MUTE,
};
enum blackbird_mute_video_mask {
BLACKBIRD_MUTE_VIDEO_V_MASK = 0x0000FF00,
BLACKBIRD_MUTE_VIDEO_U_MASK = 0x00FF0000,
BLACKBIRD_MUTE_VIDEO_Y_MASK = 0xFF000000,
};
enum blackbird_mute_video_shift {
BLACKBIRD_MUTE_VIDEO_V_SHIFT = 8,
BLACKBIRD_MUTE_VIDEO_U_SHIFT = 16,
BLACKBIRD_MUTE_VIDEO_Y_SHIFT = 24,
};
/* Registers */
#define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8 /*| IVTV_REG_OFFSET*/)
#define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC /*| IVTV_REG_OFFSET*/)
#define IVTV_REG_SPU (0x9050 /*| IVTV_REG_OFFSET*/)
#define IVTV_REG_HW_BLOCKS (0x9054 /*| IVTV_REG_OFFSET*/)
#define IVTV_REG_VPU (0x9058 /*| IVTV_REG_OFFSET*/)
#define IVTV_REG_APU (0xA064 /*| IVTV_REG_OFFSET*/)
/* ------------------------------------------------------------------ */
static void host_setup(struct cx88_core *core)
{
/* toggle reset of the host */
cx_write(MO_GPHST_SOFT_RST, 1);
udelay(100);
cx_write(MO_GPHST_SOFT_RST, 0);
udelay(100);
/* host port setup */
cx_write(MO_GPHST_WSC, 0x44444444U);
cx_write(MO_GPHST_XFR, 0);
cx_write(MO_GPHST_WDTH, 15);
cx_write(MO_GPHST_HDSHK, 0);
cx_write(MO_GPHST_MUX16, 0x44448888U);
cx_write(MO_GPHST_MODE, 0);
}
/* ------------------------------------------------------------------ */
#define P1_MDATA0 0x390000
#define P1_MDATA1 0x390001
#define P1_MDATA2 0x390002
#define P1_MDATA3 0x390003
#define P1_MADDR2 0x390004
#define P1_MADDR1 0x390005
#define P1_MADDR0 0x390006
#define P1_RDATA0 0x390008
#define P1_RDATA1 0x390009
#define P1_RDATA2 0x39000A
#define P1_RDATA3 0x39000B
#define P1_RADDR0 0x39000C
#define P1_RADDR1 0x39000D
#define P1_RRDWR 0x39000E
static int wait_ready_gpio0_bit1(struct cx88_core *core, u32 state)
{
unsigned long timeout = jiffies + msecs_to_jiffies(1);
u32 gpio0, need;
need = state ? 2 : 0;
for (;;) {
gpio0 = cx_read(MO_GP0_IO) & 2;
if (need == gpio0)
return 0;
if (time_after(jiffies, timeout))
return -1;
udelay(1);
}
}
static int memory_write(struct cx88_core *core, u32 address, u32 value)
{
/* Warning: address is dword address (4 bytes) */
cx_writeb(P1_MDATA0, (unsigned int)value);
cx_writeb(P1_MDATA1, (unsigned int)(value >> 8));
cx_writeb(P1_MDATA2, (unsigned int)(value >> 16));
cx_writeb(P1_MDATA3, (unsigned int)(value >> 24));
cx_writeb(P1_MADDR2, (unsigned int)(address >> 16) | 0x40);
cx_writeb(P1_MADDR1, (unsigned int)(address >> 8));
cx_writeb(P1_MADDR0, (unsigned int)address);
cx_read(P1_MDATA0);
cx_read(P1_MADDR0);
return wait_ready_gpio0_bit1(core, 1);
}
static int memory_read(struct cx88_core *core, u32 address, u32 *value)
{
int retval;
u32 val;
/* Warning: address is dword address (4 bytes) */
cx_writeb(P1_MADDR2, (unsigned int)(address >> 16) & ~0xC0);
cx_writeb(P1_MADDR1, (unsigned int)(address >> 8));
cx_writeb(P1_MADDR0, (unsigned int)address);
cx_read(P1_MADDR0);
retval = wait_ready_gpio0_bit1(core, 1);
cx_writeb(P1_MDATA3, 0);
val = (unsigned char)cx_read(P1_MDATA3) << 24;
cx_writeb(P1_MDATA2, 0);
val |= (unsigned char)cx_read(P1_MDATA2) << 16;
cx_writeb(P1_MDATA1, 0);
val |= (unsigned char)cx_read(P1_MDATA1) << 8;
cx_writeb(P1_MDATA0, 0);
val |= (unsigned char)cx_read(P1_MDATA0);
*value = val;
return retval;
}
static int register_write(struct cx88_core *core, u32 address, u32 value)
{
cx_writeb(P1_RDATA0, (unsigned int)value);
cx_writeb(P1_RDATA1, (unsigned int)(value >> 8));
cx_writeb(P1_RDATA2, (unsigned int)(value >> 16));
cx_writeb(P1_RDATA3, (unsigned int)(value >> 24));
cx_writeb(P1_RADDR0, (unsigned int)address);
cx_writeb(P1_RADDR1, (unsigned int)(address >> 8));
cx_writeb(P1_RRDWR, 1);
cx_read(P1_RDATA0);
cx_read(P1_RADDR0);
return wait_ready_gpio0_bit1(core, 1);
}
static int register_read(struct cx88_core *core, u32 address, u32 *value)
{
int retval;
u32 val;
cx_writeb(P1_RADDR0, (unsigned int)address);
cx_writeb(P1_RADDR1, (unsigned int)(address >> 8));
cx_writeb(P1_RRDWR, 0);
cx_read(P1_RADDR0);
retval = wait_ready_gpio0_bit1(core, 1);
val = (unsigned char)cx_read(P1_RDATA0);
val |= (unsigned char)cx_read(P1_RDATA1) << 8;
val |= (unsigned char)cx_read(P1_RDATA2) << 16;
val |= (unsigned char)cx_read(P1_RDATA3) << 24;
*value = val;
return retval;
}
/* ------------------------------------------------------------------ */
static int blackbird_mbox_func(void *priv, u32 command, int in,
int out, u32 data[CX2341X_MBOX_MAX_DATA])
{
struct cx8802_dev *dev = priv;
unsigned long timeout;
u32 value, flag, retval;
int i;
dprintk(1, "%s: 0x%X\n", __func__, command);
/*
* this may not be 100% safe if we can't read any memory location
* without side effects
*/
memory_read(dev->core, dev->mailbox - 4, &value);
if (value != 0x12345678) {
dprintk(0,
"Firmware and/or mailbox pointer not initialized or corrupted\n");
return -EIO;
}
memory_read(dev->core, dev->mailbox, &flag);
if (flag) {
dprintk(0, "ERROR: Mailbox appears to be in use (%x)\n", flag);
return -EIO;
}
flag |= 1; /* tell 'em we're working on it */
memory_write(dev->core, dev->mailbox, flag);
/* write command + args + fill remaining with zeros */
memory_write(dev->core, dev->mailbox + 1, command); /* command code */
/* timeout */
memory_write(dev->core, dev->mailbox + 3, IVTV_API_STD_TIMEOUT);
for (i = 0; i < in; i++) {
memory_write(dev->core, dev->mailbox + 4 + i, data[i]);
dprintk(1, "API Input %d = %d\n", i, data[i]);
}
for (; i < CX2341X_MBOX_MAX_DATA; i++)
memory_write(dev->core, dev->mailbox + 4 + i, 0);
flag |= 3; /* tell 'em we're done writing */
memory_write(dev->core, dev->mailbox, flag);
/* wait for firmware to handle the API command */
timeout = jiffies + msecs_to_jiffies(1000);
for (;;) {
memory_read(dev->core, dev->mailbox, &flag);
if (0 != (flag & 4))
break;
if (time_after(jiffies, timeout)) {
dprintk(0, "ERROR: API Mailbox timeout %x\n", command);
return -EIO;
}
udelay(10);
}
/* read output values */
for (i = 0; i < out; i++) {
memory_read(dev->core, dev->mailbox + 4 + i, data + i);
dprintk(1, "API Output %d = %d\n", i, data[i]);
}
memory_read(dev->core, dev->mailbox + 2, &retval);
dprintk(1, "API result = %d\n", retval);
flag = 0;
memory_write(dev->core, dev->mailbox, flag);
return retval;
}
/* ------------------------------------------------------------------ */
/*
* We don't need to call the API often, so using just one mailbox
* will probably suffice
*/
static int blackbird_api_cmd(struct cx8802_dev *dev, u32 command,
u32 inputcnt, u32 outputcnt, ...)
{
u32 data[CX2341X_MBOX_MAX_DATA];
va_list vargs;
int i, err;
va_start(vargs, outputcnt);
for (i = 0; i < inputcnt; i++)
data[i] = va_arg(vargs, int);
err = blackbird_mbox_func(dev, command, inputcnt, outputcnt, data);
for (i = 0; i < outputcnt; i++) {
int *vptr = va_arg(vargs, int *);
*vptr = data[i];
}
va_end(vargs);
return err;
}
static int blackbird_find_mailbox(struct cx8802_dev *dev)
{
u32 signature[4] = {0x12345678, 0x34567812, 0x56781234, 0x78123456};
int signaturecnt = 0;
u32 value;
int i;
for (i = 0; i < BLACKBIRD_FIRM_IMAGE_SIZE; i++) {
memory_read(dev->core, i, &value);
if (value == signature[signaturecnt])
signaturecnt++;
else
signaturecnt = 0;
if (signaturecnt == 4) {
dprintk(1, "Mailbox signature found\n");
return i + 1;
}
}
dprintk(0, "Mailbox signature values not found!\n");
return -EIO;
}
static int blackbird_load_firmware(struct cx8802_dev *dev)
{
static const unsigned char magic[8] = {
0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
};
const struct firmware *firmware;
int i, retval = 0;
u32 value = 0;
u32 checksum = 0;
__le32 *dataptr;
retval = register_write(dev->core, IVTV_REG_VPU, 0xFFFFFFED);
retval |= register_write(dev->core, IVTV_REG_HW_BLOCKS,
IVTV_CMD_HW_BLOCKS_RST);
retval |= register_write(dev->core, IVTV_REG_ENC_SDRAM_REFRESH,
0x80000640);
retval |= register_write(dev->core, IVTV_REG_ENC_SDRAM_PRECHARGE,
0x1A);
usleep_range(10000, 20000);
retval |= register_write(dev->core, IVTV_REG_APU, 0);
if (retval < 0)
dprintk(0, "Error with register_write\n");
retval = request_firmware(&firmware, CX2341X_FIRM_ENC_FILENAME,
&dev->pci->dev);
if (retval != 0) {
pr_err("Hotplug firmware request failed (%s).\n",
CX2341X_FIRM_ENC_FILENAME);
pr_err("Please fix your hotplug setup, the board will not work without firmware loaded!\n");
return -EIO;
}
if (firmware->size != BLACKBIRD_FIRM_IMAGE_SIZE) {
pr_err("Firmware size mismatch (have %zd, expected %d)\n",
firmware->size, BLACKBIRD_FIRM_IMAGE_SIZE);
release_firmware(firmware);
return -EINVAL;
}
if (memcmp(firmware->data, magic, 8) != 0) {
pr_err("Firmware magic mismatch, wrong file?\n");
release_firmware(firmware);
return -EINVAL;
}
/* transfer to the chip */
dprintk(1, "Loading firmware ...\n");
dataptr = (__le32 *)firmware->data;
for (i = 0; i < (firmware->size >> 2); i++) {
value = le32_to_cpu(*dataptr);
checksum += ~value;
memory_write(dev->core, i, value);
dataptr++;
}
/* read back to verify with the checksum */
for (i--; i >= 0; i--) {
memory_read(dev->core, i, &value);
checksum -= ~value;
}
release_firmware(firmware);
if (checksum) {
pr_err("Firmware load might have failed (checksum mismatch).\n");
return -EIO;
}
dprintk(0, "Firmware upload successful.\n");
retval |= register_write(dev->core, IVTV_REG_HW_BLOCKS,
IVTV_CMD_HW_BLOCKS_RST);
retval |= register_read(dev->core, IVTV_REG_SPU, &value);
retval |= register_write(dev->core, IVTV_REG_SPU, value & 0xFFFFFFFE);
usleep_range(10000, 20000);
retval |= register_read(dev->core, IVTV_REG_VPU, &value);
retval |= register_write(dev->core, IVTV_REG_VPU, value & 0xFFFFFFE8);
if (retval < 0)
dprintk(0, "Error with register_write\n");
return 0;
}
/*
* Settings used by the windows tv app for PVR2000:
* =================================================================================================================
* Profile | Codec | Resolution | CBR/VBR | Video Qlty | V. Bitrate | Frmrate | Audio Codec | A. Bitrate | A. Mode
* -----------------------------------------------------------------------------------------------------------------
* MPEG-1 | MPEG1 | 352x288PAL | (CBR) | 1000:Optimal | 2000 Kbps | 25fps | MPG1 Layer2 | 224kbps | Stereo
* MPEG-2 | MPEG2 | 720x576PAL | VBR | 600 :Good | 4000 Kbps | 25fps | MPG1 Layer2 | 224kbps | Stereo
* VCD | MPEG1 | 352x288PAL | (CBR) | 1000:Optimal | 1150 Kbps | 25fps | MPG1 Layer2 | 224kbps | Stereo
* DVD | MPEG2 | 720x576PAL | VBR | 600 :Good | 6000 Kbps | 25fps | MPG1 Layer2 | 224kbps | Stereo
* DB* DVD | MPEG2 | 720x576PAL | CBR | 600 :Good | 6000 Kbps | 25fps | MPG1 Layer2 | 224kbps | Stereo
* =================================================================================================================
* [*] DB: "DirectBurn"
*/
static void blackbird_codec_settings(struct cx8802_dev *dev)
{
struct cx88_core *core = dev->core;
/* assign frame size */
blackbird_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
core->height, core->width);
dev->cxhdl.width = core->width;
dev->cxhdl.height = core->height;
cx2341x_handler_set_50hz(&dev->cxhdl,
dev->core->tvnorm & V4L2_STD_625_50);
cx2341x_handler_setup(&dev->cxhdl);
}
static int blackbird_initialize_codec(struct cx8802_dev *dev)
{
struct cx88_core *core = dev->core;
int version;
int retval;
dprintk(1, "Initialize codec\n");
retval = blackbird_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
if (retval < 0) {
/* ping was not successful, reset and upload firmware */
cx_write(MO_SRST_IO, 0); /* SYS_RSTO=0 */
cx_write(MO_SRST_IO, 1); /* SYS_RSTO=1 */
retval = blackbird_load_firmware(dev);
if (retval < 0)
return retval;
retval = blackbird_find_mailbox(dev);
if (retval < 0)
return -1;
dev->mailbox = retval;
/* ping */
retval = blackbird_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
if (retval < 0) {
dprintk(0, "ERROR: Firmware ping failed!\n");
return -1;
}
retval = blackbird_api_cmd(dev, CX2341X_ENC_GET_VERSION,
0, 1, &version);
if (retval < 0) {
dprintk(0,
"ERROR: Firmware get encoder version failed!\n");
return -1;
}
dprintk(0, "Firmware version is 0x%08x\n", version);
}
cx_write(MO_PINMUX_IO, 0x88); /* 656-8bit IO and enable MPEG parallel IO */
cx_clear(MO_INPUT_FORMAT, 0x100); /* chroma subcarrier lock to normal? */
cx_write(MO_VBOS_CONTROL, 0x84A00); /* no 656 mode, 8-bit pixels, disable VBI */
cx_clear(MO_OUTPUT_FORMAT, 0x0008); /* Normal Y-limits to let the mpeg encoder sync */
blackbird_codec_settings(dev);
blackbird_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
BLACKBIRD_FIELD1_SAA7115, BLACKBIRD_FIELD2_SAA7115);
blackbird_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
BLACKBIRD_CUSTOM_EXTENSION_USR_DATA,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
return 0;
}
static int blackbird_start_codec(struct cx8802_dev *dev)
{
struct cx88_core *core = dev->core;
/* start capturing to the host interface */
u32 reg;
int i;
int lastchange = -1;
int lastval = 0;
for (i = 0; (i < 10) && (i < (lastchange + 4)); i++) {
reg = cx_read(AUD_STATUS);
dprintk(1, "AUD_STATUS:%dL: 0x%x\n", i, reg);
if ((reg & 0x0F) != lastval) {
lastval = reg & 0x0F;
lastchange = i;
}
msleep(100);
}
/* unmute audio source */
cx_clear(AUD_VOL_CTL, (1 << 6));
blackbird_api_cmd(dev, CX2341X_ENC_REFRESH_INPUT, 0, 0);
/* initialize the video input */
blackbird_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
cx2341x_handler_set_busy(&dev->cxhdl, 1);
/* start capturing to the host interface */
blackbird_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
BLACKBIRD_MPEG_CAPTURE, BLACKBIRD_RAW_BITS_NONE);
return 0;
}
static int blackbird_stop_codec(struct cx8802_dev *dev)
{
blackbird_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
BLACKBIRD_END_NOW,
BLACKBIRD_MPEG_CAPTURE,
BLACKBIRD_RAW_BITS_NONE);
cx2341x_handler_set_busy(&dev->cxhdl, 0);
return 0;
}
/* ------------------------------------------------------------------ */
static int queue_setup(struct vb2_queue *q,
unsigned int *num_buffers, unsigned int *num_planes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct cx8802_dev *dev = q->drv_priv;
*num_planes = 1;
dev->ts_packet_size = 188 * 4;
dev->ts_packet_count = 32;
sizes[0] = dev->ts_packet_size * dev->ts_packet_count;
return 0;
}
static int buffer_prepare(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
return cx8802_buf_prepare(vb->vb2_queue, dev, buf);
}
static void buffer_finish(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
struct cx88_riscmem *risc = &buf->risc;
if (risc->cpu)
dma_free_coherent(&dev->pci->dev, risc->size, risc->cpu,
risc->dma);
memset(risc, 0, sizeof(*risc));
}
static void buffer_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
cx8802_buf_queue(dev, buf);
}
static int start_streaming(struct vb2_queue *q, unsigned int count)
{
struct cx8802_dev *dev = q->drv_priv;
struct cx88_dmaqueue *dmaq = &dev->mpegq;
struct cx8802_driver *drv;
struct cx88_buffer *buf;
unsigned long flags;
int err;
/* Make sure we can acquire the hardware */
drv = cx8802_get_driver(dev, CX88_MPEG_BLACKBIRD);
if (!drv) {
dprintk(1, "%s: blackbird driver is not loaded\n", __func__);
err = -ENODEV;
goto fail;
}
err = drv->request_acquire(drv);
if (err != 0) {
dprintk(1, "%s: Unable to acquire hardware, %d\n", __func__,
err);
goto fail;
}
if (blackbird_initialize_codec(dev) < 0) {
drv->request_release(drv);
err = -EINVAL;
goto fail;
}
err = blackbird_start_codec(dev);
if (err == 0) {
buf = list_entry(dmaq->active.next, struct cx88_buffer, list);
cx8802_start_dma(dev, dmaq, buf);
return 0;
}
fail:
spin_lock_irqsave(&dev->slock, flags);
while (!list_empty(&dmaq->active)) {
struct cx88_buffer *buf = list_entry(dmaq->active.next,
struct cx88_buffer, list);
list_del(&buf->list);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
}
spin_unlock_irqrestore(&dev->slock, flags);
return err;
}
static void stop_streaming(struct vb2_queue *q)
{
struct cx8802_dev *dev = q->drv_priv;
struct cx88_dmaqueue *dmaq = &dev->mpegq;
struct cx8802_driver *drv = NULL;
unsigned long flags;
cx8802_cancel_buffers(dev);
blackbird_stop_codec(dev);
/* Make sure we release the hardware */
drv = cx8802_get_driver(dev, CX88_MPEG_BLACKBIRD);
WARN_ON(!drv);
if (drv)
drv->request_release(drv);
spin_lock_irqsave(&dev->slock, flags);
while (!list_empty(&dmaq->active)) {
struct cx88_buffer *buf = list_entry(dmaq->active.next,
struct cx88_buffer, list);
list_del(&buf->list);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&dev->slock, flags);
}
static const struct vb2_ops blackbird_qops = {
.queue_setup = queue_setup,
.buf_prepare = buffer_prepare,
.buf_finish = buffer_finish,
.buf_queue = buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = start_streaming,
.stop_streaming = stop_streaming,
};
/* ------------------------------------------------------------------ */
static int vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
strscpy(cap->driver, "cx88_blackbird", sizeof(cap->driver));
return cx88_querycap(file, core, cap);
}
static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
if (f->index != 0)
return -EINVAL;
f->pixelformat = V4L2_PIX_FMT_MPEG;
return 0;
}
static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
f->fmt.pix.bytesperline = 0;
f->fmt.pix.sizeimage = dev->ts_packet_size * dev->ts_packet_count;
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
f->fmt.pix.width = core->width;
f->fmt.pix.height = core->height;
f->fmt.pix.field = core->field;
return 0;
}
static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
unsigned int maxw, maxh;
enum v4l2_field field;
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
f->fmt.pix.bytesperline = 0;
f->fmt.pix.sizeimage = dev->ts_packet_size * dev->ts_packet_count;
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
maxw = norm_maxw(core->tvnorm);
maxh = norm_maxh(core->tvnorm);
field = f->fmt.pix.field;
switch (field) {
case V4L2_FIELD_TOP:
case V4L2_FIELD_BOTTOM:
case V4L2_FIELD_INTERLACED:
case V4L2_FIELD_SEQ_BT:
case V4L2_FIELD_SEQ_TB:
break;
default:
field = (f->fmt.pix.height > maxh / 2)
? V4L2_FIELD_INTERLACED
: V4L2_FIELD_BOTTOM;
break;
}
if (V4L2_FIELD_HAS_T_OR_B(field))
maxh /= 2;
v4l_bound_align_image(&f->fmt.pix.width, 48, maxw, 2,
&f->fmt.pix.height, 32, maxh, 0, 0);
f->fmt.pix.field = field;
return 0;
}
static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
if (vb2_is_busy(&dev->vb2_mpegq))
return -EBUSY;
if (core->v4ldev && (vb2_is_busy(&core->v4ldev->vb2_vidq) ||
vb2_is_busy(&core->v4ldev->vb2_vbiq)))
return -EBUSY;
vidioc_try_fmt_vid_cap(file, priv, f);
core->width = f->fmt.pix.width;
core->height = f->fmt.pix.height;
core->field = f->fmt.pix.field;
cx88_set_scale(core, f->fmt.pix.width, f->fmt.pix.height,
f->fmt.pix.field);
blackbird_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
f->fmt.pix.height, f->fmt.pix.width);
return 0;
}
static int vidioc_s_frequency(struct file *file, void *priv,
const struct v4l2_frequency *f)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
bool streaming;
if (unlikely(core->board.tuner_type == UNSET))
return -EINVAL;
if (unlikely(f->tuner != 0))
return -EINVAL;
streaming = vb2_start_streaming_called(&dev->vb2_mpegq);
if (streaming)
blackbird_stop_codec(dev);
cx88_set_freq(core, f);
blackbird_initialize_codec(dev);
cx88_set_scale(core, core->width, core->height, core->field);
if (streaming)
blackbird_start_codec(dev);
return 0;
}
static int vidioc_log_status(struct file *file, void *priv)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
char name[32 + 2];
snprintf(name, sizeof(name), "%s/2", core->name);
call_all(core, core, log_status);
v4l2_ctrl_handler_log_status(&dev->cxhdl.hdl, name);
return 0;
}
static int vidioc_enum_input(struct file *file, void *priv,
struct v4l2_input *i)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
return cx88_enum_input(core, i);
}
static int vidioc_g_frequency(struct file *file, void *priv,
struct v4l2_frequency *f)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
if (unlikely(core->board.tuner_type == UNSET))
return -EINVAL;
if (unlikely(f->tuner != 0))
return -EINVAL;
f->frequency = core->freq;
call_all(core, tuner, g_frequency, f);
return 0;
}
static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
*i = core->input;
return 0;
}
static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
if (i >= 4)
return -EINVAL;
if (!INPUT(i).type)
return -EINVAL;
cx88_newstation(core);
cx88_video_mux(core, i);
return 0;
}
static int vidioc_g_tuner(struct file *file, void *priv,
struct v4l2_tuner *t)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
u32 reg;
if (unlikely(core->board.tuner_type == UNSET))
return -EINVAL;
if (t->index != 0)
return -EINVAL;
strscpy(t->name, "Television", sizeof(t->name));
t->capability = V4L2_TUNER_CAP_NORM;
t->rangehigh = 0xffffffffUL;
call_all(core, tuner, g_tuner, t);
cx88_get_stereo(core, t);
reg = cx_read(MO_DEVICE_STATUS);
t->signal = (reg & (1 << 5)) ? 0xffff : 0x0000;
return 0;
}
static int vidioc_s_tuner(struct file *file, void *priv,
const struct v4l2_tuner *t)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
if (core->board.tuner_type == UNSET)
return -EINVAL;
if (t->index != 0)
return -EINVAL;
cx88_set_stereo(core, t->audmode, 1);
return 0;
}
static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorm)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
*tvnorm = core->tvnorm;
return 0;
}
static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id id)
{
struct cx8802_dev *dev = video_drvdata(file);
struct cx88_core *core = dev->core;
return cx88_set_tvnorm(core, id);
}
static const struct v4l2_file_operations mpeg_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.release = vb2_fop_release,
.read = vb2_fop_read,
.poll = vb2_fop_poll,
.mmap = vb2_fop_mmap,
.unlocked_ioctl = video_ioctl2,
};
static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_s_frequency = vidioc_s_frequency,
.vidioc_log_status = vidioc_log_status,
.vidioc_enum_input = vidioc_enum_input,
.vidioc_g_frequency = vidioc_g_frequency,
.vidioc_g_input = vidioc_g_input,
.vidioc_s_input = vidioc_s_input,
.vidioc_g_tuner = vidioc_g_tuner,
.vidioc_s_tuner = vidioc_s_tuner,
.vidioc_g_std = vidioc_g_std,
.vidioc_s_std = vidioc_s_std,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
static const struct video_device cx8802_mpeg_template = {
.name = "cx8802",
.fops = &mpeg_fops,
.ioctl_ops = &mpeg_ioctl_ops,
.tvnorms = CX88_NORMS,
};
/* ------------------------------------------------------------------ */
/* The CX8802 MPEG API will call this when we can use the hardware */
static int cx8802_blackbird_advise_acquire(struct cx8802_driver *drv)
{
struct cx88_core *core = drv->core;
int err = 0;
switch (core->boardnr) {
case CX88_BOARD_HAUPPAUGE_HVR1300:
/*
* By default, core setup will leave the cx22702 out of reset,
* on the bus.
* We left the hardware on power up with the cx22702 active.
* We're being given access to re-arrange the GPIOs.
* Take the bus off the cx22702 and put the cx23416 on it.
*/
/* Toggle reset on cx22702 leaving i2c active */
cx_set(MO_GP0_IO, 0x00000080);
udelay(1000);
cx_clear(MO_GP0_IO, 0x00000080);
udelay(50);
cx_set(MO_GP0_IO, 0x00000080);
udelay(1000);
/* tri-state the cx22702 pins */
cx_set(MO_GP0_IO, 0x00000004);
udelay(1000);
break;
default:
err = -ENODEV;
}
return err;
}
/* The CX8802 MPEG API will call this when we need to release the hardware */
static int cx8802_blackbird_advise_release(struct cx8802_driver *drv)
{
struct cx88_core *core = drv->core;
int err = 0;
switch (core->boardnr) {
case CX88_BOARD_HAUPPAUGE_HVR1300:
/* Exit leaving the cx23416 on the bus */
break;
default:
err = -ENODEV;
}
return err;
}
static void blackbird_unregister_video(struct cx8802_dev *dev)
{
video_unregister_device(&dev->mpeg_dev);
}
static int blackbird_register_video(struct cx8802_dev *dev)
{
int err;
cx88_vdev_init(dev->core, dev->pci, &dev->mpeg_dev,
&cx8802_mpeg_template, "mpeg");
dev->mpeg_dev.ctrl_handler = &dev->cxhdl.hdl;
video_set_drvdata(&dev->mpeg_dev, dev);
dev->mpeg_dev.queue = &dev->vb2_mpegq;
dev->mpeg_dev.device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
V4L2_CAP_VIDEO_CAPTURE;
if (dev->core->board.tuner_type != UNSET)
dev->mpeg_dev.device_caps |= V4L2_CAP_TUNER;
err = video_register_device(&dev->mpeg_dev, VFL_TYPE_VIDEO, -1);
if (err < 0) {
pr_info("can't register mpeg device\n");
return err;
}
pr_info("registered device %s [mpeg]\n",
video_device_node_name(&dev->mpeg_dev));
return 0;
}
/* ----------------------------------------------------------- */
static int cx8802_blackbird_probe(struct cx8802_driver *drv)
{
struct cx88_core *core = drv->core;
struct cx8802_dev *dev = core->dvbdev;
struct vb2_queue *q;
int err;
dprintk(1, "%s\n", __func__);
dprintk(1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
core->boardnr,
core->name,
core->pci_bus,
core->pci_slot);
err = -ENODEV;
if (!(core->board.mpeg & CX88_MPEG_BLACKBIRD))
goto fail_core;
dev->cxhdl.port = CX2341X_PORT_STREAMING;
dev->cxhdl.width = core->width;
dev->cxhdl.height = core->height;
dev->cxhdl.func = blackbird_mbox_func;
dev->cxhdl.priv = dev;
err = cx2341x_handler_init(&dev->cxhdl, 36);
if (err)
goto fail_core;
v4l2_ctrl_add_handler(&dev->cxhdl.hdl, &core->video_hdl, NULL, false);
/* blackbird stuff */
pr_info("cx23416 based mpeg encoder (blackbird reference design)\n");
host_setup(dev->core);
blackbird_initialize_codec(dev);
/* initial device configuration: needed ? */
// init_controls(core);
cx88_set_tvnorm(core, core->tvnorm);
cx88_video_mux(core, 0);
cx2341x_handler_set_50hz(&dev->cxhdl, core->height == 576);
cx2341x_handler_setup(&dev->cxhdl);
q = &dev->vb2_mpegq;
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
q->gfp_flags = GFP_DMA32;
q->min_buffers_needed = 2;
q->drv_priv = dev;
q->buf_struct_size = sizeof(struct cx88_buffer);
q->ops = &blackbird_qops;
q->mem_ops = &vb2_dma_sg_memops;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &core->lock;
q->dev = &dev->pci->dev;
err = vb2_queue_init(q);
if (err < 0)
goto fail_core;
blackbird_register_video(dev);
return 0;
fail_core:
return err;
}
static int cx8802_blackbird_remove(struct cx8802_driver *drv)
{
struct cx88_core *core = drv->core;
struct cx8802_dev *dev = core->dvbdev;
/* blackbird */
blackbird_unregister_video(drv->core->dvbdev);
v4l2_ctrl_handler_free(&dev->cxhdl.hdl);
return 0;
}
static struct cx8802_driver cx8802_blackbird_driver = {
.type_id = CX88_MPEG_BLACKBIRD,
.hw_access = CX8802_DRVCTL_SHARED,
.probe = cx8802_blackbird_probe,
.remove = cx8802_blackbird_remove,
.advise_acquire = cx8802_blackbird_advise_acquire,
.advise_release = cx8802_blackbird_advise_release,
};
static int __init blackbird_init(void)
{
pr_info("cx2388x blackbird driver version %s loaded\n",
CX88_VERSION);
return cx8802_register_driver(&cx8802_blackbird_driver);
}
static void __exit blackbird_fini(void)
{
cx8802_unregister_driver(&cx8802_blackbird_driver);
}
module_init(blackbird_init);
module_exit(blackbird_fini);
| linux-master | drivers/media/pci/cx88/cx88-blackbird.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* Support for the mpeg transport stream transfers
* PCI function #2 of the cx2388x.
*
* (c) 2004 Jelle Foks <[email protected]>
* (c) 2004 Chris Pascoe <[email protected]>
* (c) 2004 Gerd Knorr <[email protected]>
*/
#include "cx88.h"
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
/* ------------------------------------------------------------------ */
MODULE_DESCRIPTION("mpeg driver for cx2388x based TV cards");
MODULE_AUTHOR("Jelle Foks <[email protected]>");
MODULE_AUTHOR("Chris Pascoe <[email protected]>");
MODULE_AUTHOR("Gerd Knorr <[email protected]> [SuSE Labs]");
MODULE_LICENSE("GPL");
MODULE_VERSION(CX88_VERSION);
static unsigned int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable debug messages [mpeg]");
#define dprintk(level, fmt, arg...) do { \
if (debug + 1 > level) \
printk(KERN_DEBUG pr_fmt("%s: mpeg:" fmt), \
__func__, ##arg); \
} while (0)
#if defined(CONFIG_MODULES) && defined(MODULE)
static void request_module_async(struct work_struct *work)
{
struct cx8802_dev *dev = container_of(work, struct cx8802_dev,
request_module_wk);
if (dev->core->board.mpeg & CX88_MPEG_DVB)
request_module("cx88-dvb");
if (dev->core->board.mpeg & CX88_MPEG_BLACKBIRD)
request_module("cx88-blackbird");
}
static void request_modules(struct cx8802_dev *dev)
{
INIT_WORK(&dev->request_module_wk, request_module_async);
schedule_work(&dev->request_module_wk);
}
static void flush_request_modules(struct cx8802_dev *dev)
{
flush_work(&dev->request_module_wk);
}
#else
#define request_modules(dev)
#define flush_request_modules(dev)
#endif /* CONFIG_MODULES */
static LIST_HEAD(cx8802_devlist);
static DEFINE_MUTEX(cx8802_mutex);
/* ------------------------------------------------------------------ */
int cx8802_start_dma(struct cx8802_dev *dev,
struct cx88_dmaqueue *q,
struct cx88_buffer *buf)
{
struct cx88_core *core = dev->core;
dprintk(1, "w: %d, h: %d, f: %d\n",
core->width, core->height, core->field);
/* setup fifo + format */
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],
dev->ts_packet_size, buf->risc.dma);
/* write TS length to chip */
cx_write(MO_TS_LNGTH, dev->ts_packet_size);
/*
* FIXME: this needs a review.
* also: move to cx88-blackbird + cx88-dvb source files?
*/
dprintk(1, "core->active_type_id = 0x%08x\n", core->active_type_id);
if ((core->active_type_id == CX88_MPEG_DVB) &&
(core->board.mpeg & CX88_MPEG_DVB)) {
dprintk(1, "cx8802_start_dma doing .dvb\n");
/* negedge driven & software reset */
cx_write(TS_GEN_CNTRL, 0x0040 | dev->ts_gen_cntrl);
udelay(100);
cx_write(MO_PINMUX_IO, 0x00);
cx_write(TS_HW_SOP_CNTRL, 0x47 << 16 | 188 << 4 | 0x01);
switch (core->boardnr) {
case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
case CX88_BOARD_PCHDTV_HD5500:
cx_write(TS_SOP_STAT, 1 << 13);
break;
case CX88_BOARD_SAMSUNG_SMT_7020:
cx_write(TS_SOP_STAT, 0x00);
break;
case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
/* Enable MPEG parallel IO and video signal pins */
cx_write(MO_PINMUX_IO, 0x88);
udelay(100);
break;
case CX88_BOARD_HAUPPAUGE_HVR1300:
/* Enable MPEG parallel IO and video signal pins */
cx_write(MO_PINMUX_IO, 0x88);
cx_write(TS_SOP_STAT, 0);
cx_write(TS_VALERR_CNTRL, 0);
break;
case CX88_BOARD_PINNACLE_PCTV_HD_800i:
/* Enable MPEG parallel IO and video signal pins */
cx_write(MO_PINMUX_IO, 0x88);
cx_write(TS_HW_SOP_CNTRL, (0x47 << 16) | (188 << 4));
dev->ts_gen_cntrl = 5;
cx_write(TS_SOP_STAT, 0);
cx_write(TS_VALERR_CNTRL, 0);
udelay(100);
break;
default:
cx_write(TS_SOP_STAT, 0x00);
break;
}
cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl);
udelay(100);
} else if ((core->active_type_id == CX88_MPEG_BLACKBIRD) &&
(core->board.mpeg & CX88_MPEG_BLACKBIRD)) {
dprintk(1, "cx8802_start_dma doing .blackbird\n");
cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */
/* punctured clock TS & posedge driven & software reset */
cx_write(TS_GEN_CNTRL, 0x46);
udelay(100);
cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */
cx_write(TS_VALERR_CNTRL, 0x2000);
/* punctured clock TS & posedge driven */
cx_write(TS_GEN_CNTRL, 0x06);
udelay(100);
} else {
pr_err("%s() Failed. Unsupported value in .mpeg (0x%08x)\n",
__func__, core->board.mpeg);
return -EINVAL;
}
/* reset counter */
cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);
q->count = 0;
/* clear interrupt status register */
cx_write(MO_TS_INTSTAT, 0x1f1111);
/* enable irqs */
dprintk(1, "setting the interrupt mask\n");
cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_TSINT);
cx_set(MO_TS_INTMSK, 0x1f0011);
/* start dma */
cx_set(MO_DEV_CNTRL2, (1 << 5));
cx_set(MO_TS_DMACNTRL, 0x11);
return 0;
}
EXPORT_SYMBOL(cx8802_start_dma);
static int cx8802_stop_dma(struct cx8802_dev *dev)
{
struct cx88_core *core = dev->core;
dprintk(1, "\n");
/* stop dma */
cx_clear(MO_TS_DMACNTRL, 0x11);
/* disable irqs */
cx_clear(MO_PCI_INTMSK, PCI_INT_TSINT);
cx_clear(MO_TS_INTMSK, 0x1f0011);
/* Reset the controller */
cx_write(TS_GEN_CNTRL, 0xcd);
return 0;
}
static int cx8802_restart_queue(struct cx8802_dev *dev,
struct cx88_dmaqueue *q)
{
struct cx88_buffer *buf;
dprintk(1, "\n");
if (list_empty(&q->active))
return 0;
buf = list_entry(q->active.next, struct cx88_buffer, list);
dprintk(2, "restart_queue [%p/%d]: restart dma\n",
buf, buf->vb.vb2_buf.index);
cx8802_start_dma(dev, q, buf);
return 0;
}
/* ------------------------------------------------------------------ */
int cx8802_buf_prepare(struct vb2_queue *q, struct cx8802_dev *dev,
struct cx88_buffer *buf)
{
int size = dev->ts_packet_size * dev->ts_packet_count;
struct sg_table *sgt = vb2_dma_sg_plane_desc(&buf->vb.vb2_buf, 0);
struct cx88_riscmem *risc = &buf->risc;
int rc;
if (vb2_plane_size(&buf->vb.vb2_buf, 0) < size)
return -EINVAL;
vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
rc = cx88_risc_databuffer(dev->pci, risc, sgt->sgl,
dev->ts_packet_size, dev->ts_packet_count, 0);
if (rc) {
if (risc->cpu)
dma_free_coherent(&dev->pci->dev, risc->size,
risc->cpu, risc->dma);
memset(risc, 0, sizeof(*risc));
return rc;
}
return 0;
}
EXPORT_SYMBOL(cx8802_buf_prepare);
void cx8802_buf_queue(struct cx8802_dev *dev, struct cx88_buffer *buf)
{
struct cx88_buffer *prev;
struct cx88_dmaqueue *cx88q = &dev->mpegq;
dprintk(1, "\n");
/* add jump to start */
buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8);
buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8);
if (list_empty(&cx88q->active)) {
dprintk(1, "queue is empty - first active\n");
list_add_tail(&buf->list, &cx88q->active);
dprintk(1, "[%p/%d] %s - first active\n",
buf, buf->vb.vb2_buf.index, __func__);
} else {
buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
dprintk(1, "queue is not empty - append to active\n");
prev = list_entry(cx88q->active.prev, struct cx88_buffer, list);
list_add_tail(&buf->list, &cx88q->active);
prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
dprintk(1, "[%p/%d] %s - append to active\n",
buf, buf->vb.vb2_buf.index, __func__);
}
}
EXPORT_SYMBOL(cx8802_buf_queue);
/* ----------------------------------------------------------- */
static void do_cancel_buffers(struct cx8802_dev *dev)
{
struct cx88_dmaqueue *q = &dev->mpegq;
struct cx88_buffer *buf;
unsigned long flags;
spin_lock_irqsave(&dev->slock, flags);
while (!list_empty(&q->active)) {
buf = list_entry(q->active.next, struct cx88_buffer, list);
list_del(&buf->list);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&dev->slock, flags);
}
void cx8802_cancel_buffers(struct cx8802_dev *dev)
{
dprintk(1, "\n");
cx8802_stop_dma(dev);
do_cancel_buffers(dev);
}
EXPORT_SYMBOL(cx8802_cancel_buffers);
static const char *cx88_mpeg_irqs[32] = {
"ts_risci1", NULL, NULL, NULL,
"ts_risci2", NULL, NULL, NULL,
"ts_oflow", NULL, NULL, NULL,
"ts_sync", NULL, NULL, NULL,
"opc_err", "par_err", "rip_err", "pci_abort",
"ts_err?",
};
static void cx8802_mpeg_irq(struct cx8802_dev *dev)
{
struct cx88_core *core = dev->core;
u32 status, mask, count;
dprintk(1, "\n");
status = cx_read(MO_TS_INTSTAT);
mask = cx_read(MO_TS_INTMSK);
if (0 == (status & mask))
return;
cx_write(MO_TS_INTSTAT, status);
if (debug || (status & mask & ~0xff))
cx88_print_irqbits("irq mpeg ",
cx88_mpeg_irqs, ARRAY_SIZE(cx88_mpeg_irqs),
status, mask);
/* risc op code error */
if (status & (1 << 16)) {
pr_warn("mpeg risc op code error\n");
cx_clear(MO_TS_DMACNTRL, 0x11);
cx88_sram_channel_dump(dev->core,
&cx88_sram_channels[SRAM_CH28]);
}
/* risc1 y */
if (status & 0x01) {
dprintk(1, "wake up\n");
spin_lock(&dev->slock);
count = cx_read(MO_TS_GPCNT);
cx88_wakeup(dev->core, &dev->mpegq, count);
spin_unlock(&dev->slock);
}
/* other general errors */
if (status & 0x1f0100) {
dprintk(0, "general errors: 0x%08x\n", status & 0x1f0100);
spin_lock(&dev->slock);
cx8802_stop_dma(dev);
spin_unlock(&dev->slock);
}
}
#define MAX_IRQ_LOOP 10
static irqreturn_t cx8802_irq(int irq, void *dev_id)
{
struct cx8802_dev *dev = dev_id;
struct cx88_core *core = dev->core;
u32 status;
int loop, handled = 0;
for (loop = 0; loop < MAX_IRQ_LOOP; loop++) {
status = cx_read(MO_PCI_INTSTAT) &
(core->pci_irqmask | PCI_INT_TSINT);
if (status == 0)
goto out;
dprintk(1, "cx8802_irq\n");
dprintk(1, " loop: %d/%d\n", loop, MAX_IRQ_LOOP);
dprintk(1, " status: %d\n", status);
handled = 1;
cx_write(MO_PCI_INTSTAT, status);
if (status & core->pci_irqmask)
cx88_core_irq(core, status);
if (status & PCI_INT_TSINT)
cx8802_mpeg_irq(dev);
}
if (loop == MAX_IRQ_LOOP) {
dprintk(0, "clearing mask\n");
pr_warn("irq loop -- clearing mask\n");
cx_write(MO_PCI_INTMSK, 0);
}
out:
return IRQ_RETVAL(handled);
}
static int cx8802_init_common(struct cx8802_dev *dev)
{
struct cx88_core *core = dev->core;
int err;
/* pci init */
if (pci_enable_device(dev->pci))
return -EIO;
pci_set_master(dev->pci);
err = dma_set_mask(&dev->pci->dev, DMA_BIT_MASK(32));
if (err) {
pr_err("Oops: no 32bit PCI DMA ???\n");
return -EIO;
}
dev->pci_rev = dev->pci->revision;
pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER, &dev->pci_lat);
pr_info("found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
pci_name(dev->pci), dev->pci_rev, dev->pci->irq,
dev->pci_lat,
(unsigned long long)pci_resource_start(dev->pci, 0));
/* initialize driver struct */
spin_lock_init(&dev->slock);
/* init dma queue */
INIT_LIST_HEAD(&dev->mpegq.active);
/* get irq */
err = request_irq(dev->pci->irq, cx8802_irq,
IRQF_SHARED, dev->core->name, dev);
if (err < 0) {
pr_err("can't get IRQ %d\n", dev->pci->irq);
return err;
}
cx_set(MO_PCI_INTMSK, core->pci_irqmask);
/* everything worked */
pci_set_drvdata(dev->pci, dev);
return 0;
}
static void cx8802_fini_common(struct cx8802_dev *dev)
{
dprintk(2, "\n");
cx8802_stop_dma(dev);
pci_disable_device(dev->pci);
/* unregister stuff */
free_irq(dev->pci->irq, dev);
}
/* ----------------------------------------------------------- */
static int cx8802_suspend_common(struct pci_dev *pci_dev, pm_message_t state)
{
struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
unsigned long flags;
/* stop mpeg dma */
spin_lock_irqsave(&dev->slock, flags);
if (!list_empty(&dev->mpegq.active)) {
dprintk(2, "suspend\n");
pr_info("suspend mpeg\n");
cx8802_stop_dma(dev);
}
spin_unlock_irqrestore(&dev->slock, flags);
/* FIXME -- shutdown device */
cx88_shutdown(dev->core);
pci_save_state(pci_dev);
if (pci_set_power_state(pci_dev,
pci_choose_state(pci_dev, state)) != 0) {
pci_disable_device(pci_dev);
dev->state.disabled = 1;
}
return 0;
}
static int cx8802_resume_common(struct pci_dev *pci_dev)
{
struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
unsigned long flags;
int err;
if (dev->state.disabled) {
err = pci_enable_device(pci_dev);
if (err) {
pr_err("can't enable device\n");
return err;
}
dev->state.disabled = 0;
}
err = pci_set_power_state(pci_dev, PCI_D0);
if (err) {
pr_err("can't enable device\n");
pci_disable_device(pci_dev);
dev->state.disabled = 1;
return err;
}
pci_restore_state(pci_dev);
/* FIXME: re-initialize hardware */
cx88_reset(dev->core);
/* restart video+vbi capture */
spin_lock_irqsave(&dev->slock, flags);
if (!list_empty(&dev->mpegq.active)) {
pr_info("resume mpeg\n");
cx8802_restart_queue(dev, &dev->mpegq);
}
spin_unlock_irqrestore(&dev->slock, flags);
return 0;
}
struct cx8802_driver *cx8802_get_driver(struct cx8802_dev *dev,
enum cx88_board_type btype)
{
struct cx8802_driver *d;
list_for_each_entry(d, &dev->drvlist, drvlist)
if (d->type_id == btype)
return d;
return NULL;
}
EXPORT_SYMBOL(cx8802_get_driver);
/* Driver asked for hardware access. */
static int cx8802_request_acquire(struct cx8802_driver *drv)
{
struct cx88_core *core = drv->core;
unsigned int i;
/* Fail a request for hardware if the device is busy. */
if (core->active_type_id != CX88_BOARD_NONE &&
core->active_type_id != drv->type_id)
return -EBUSY;
if (drv->type_id == CX88_MPEG_DVB) {
/* When switching to DVB, always set the input to the tuner */
core->last_analog_input = core->input;
core->input = 0;
for (i = 0;
i < ARRAY_SIZE(core->board.input);
i++) {
if (core->board.input[i].type == CX88_VMUX_DVB) {
core->input = i;
break;
}
}
}
if (drv->advise_acquire) {
core->active_ref++;
if (core->active_type_id == CX88_BOARD_NONE) {
core->active_type_id = drv->type_id;
drv->advise_acquire(drv);
}
dprintk(1, "Post acquire GPIO=%x\n", cx_read(MO_GP0_IO));
}
return 0;
}
/* Driver asked to release hardware. */
static int cx8802_request_release(struct cx8802_driver *drv)
{
struct cx88_core *core = drv->core;
if (drv->advise_release && --core->active_ref == 0) {
if (drv->type_id == CX88_MPEG_DVB) {
/*
* If the DVB driver is releasing, reset the input
* state to the last configured analog input
*/
core->input = core->last_analog_input;
}
drv->advise_release(drv);
core->active_type_id = CX88_BOARD_NONE;
dprintk(1, "Post release GPIO=%x\n", cx_read(MO_GP0_IO));
}
return 0;
}
static int cx8802_check_driver(struct cx8802_driver *drv)
{
if (!drv)
return -ENODEV;
if ((drv->type_id != CX88_MPEG_DVB) &&
(drv->type_id != CX88_MPEG_BLACKBIRD))
return -EINVAL;
if ((drv->hw_access != CX8802_DRVCTL_SHARED) &&
(drv->hw_access != CX8802_DRVCTL_EXCLUSIVE))
return -EINVAL;
if ((!drv->probe) ||
(!drv->remove) ||
(!drv->advise_acquire) ||
(!drv->advise_release))
return -EINVAL;
return 0;
}
int cx8802_register_driver(struct cx8802_driver *drv)
{
struct cx8802_dev *dev;
struct cx8802_driver *driver;
int err, i = 0;
pr_info("registering cx8802 driver, type: %s access: %s\n",
drv->type_id == CX88_MPEG_DVB ? "dvb" : "blackbird",
drv->hw_access == CX8802_DRVCTL_SHARED ?
"shared" : "exclusive");
err = cx8802_check_driver(drv);
if (err) {
pr_err("cx8802_driver is invalid\n");
return err;
}
mutex_lock(&cx8802_mutex);
list_for_each_entry(dev, &cx8802_devlist, devlist) {
pr_info("subsystem: %04x:%04x, board: %s [card=%d]\n",
dev->pci->subsystem_vendor,
dev->pci->subsystem_device, dev->core->board.name,
dev->core->boardnr);
/* Bring up a new struct for each driver instance */
driver = kzalloc(sizeof(*drv), GFP_KERNEL);
if (!driver) {
err = -ENOMEM;
goto out;
}
/* Snapshot of the driver registration data */
drv->core = dev->core;
drv->suspend = cx8802_suspend_common;
drv->resume = cx8802_resume_common;
drv->request_acquire = cx8802_request_acquire;
drv->request_release = cx8802_request_release;
memcpy(driver, drv, sizeof(*driver));
mutex_lock(&drv->core->lock);
err = drv->probe(driver);
if (err == 0) {
i++;
list_add_tail(&driver->drvlist, &dev->drvlist);
} else {
pr_err("cx8802 probe failed, err = %d\n", err);
}
mutex_unlock(&drv->core->lock);
}
err = i ? 0 : -ENODEV;
out:
mutex_unlock(&cx8802_mutex);
return err;
}
EXPORT_SYMBOL(cx8802_register_driver);
int cx8802_unregister_driver(struct cx8802_driver *drv)
{
struct cx8802_dev *dev;
struct cx8802_driver *d, *dtmp;
int err = 0;
pr_info("unregistering cx8802 driver, type: %s access: %s\n",
drv->type_id == CX88_MPEG_DVB ? "dvb" : "blackbird",
drv->hw_access == CX8802_DRVCTL_SHARED ?
"shared" : "exclusive");
mutex_lock(&cx8802_mutex);
list_for_each_entry(dev, &cx8802_devlist, devlist) {
pr_info("subsystem: %04x:%04x, board: %s [card=%d]\n",
dev->pci->subsystem_vendor,
dev->pci->subsystem_device, dev->core->board.name,
dev->core->boardnr);
mutex_lock(&dev->core->lock);
list_for_each_entry_safe(d, dtmp, &dev->drvlist, drvlist) {
/* only unregister the correct driver type */
if (d->type_id != drv->type_id)
continue;
err = d->remove(d);
if (err == 0) {
list_del(&d->drvlist);
kfree(d);
} else
pr_err("cx8802 driver remove failed (%d)\n",
err);
}
mutex_unlock(&dev->core->lock);
}
mutex_unlock(&cx8802_mutex);
return err;
}
EXPORT_SYMBOL(cx8802_unregister_driver);
/* ----------------------------------------------------------- */
static int cx8802_probe(struct pci_dev *pci_dev,
const struct pci_device_id *pci_id)
{
struct cx8802_dev *dev;
struct cx88_core *core;
int err;
/* general setup */
core = cx88_core_get(pci_dev);
if (!core)
return -EINVAL;
pr_info("cx2388x 8802 Driver Manager\n");
err = -ENODEV;
if (!core->board.mpeg)
goto fail_core;
err = -ENOMEM;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev)
goto fail_core;
dev->pci = pci_dev;
dev->core = core;
/* Maintain a reference so cx88-video can query the 8802 device. */
core->dvbdev = dev;
err = cx8802_init_common(dev);
if (err != 0)
goto fail_dev;
INIT_LIST_HEAD(&dev->drvlist);
mutex_lock(&cx8802_mutex);
list_add_tail(&dev->devlist, &cx8802_devlist);
mutex_unlock(&cx8802_mutex);
/* now autoload cx88-dvb or cx88-blackbird */
request_modules(dev);
return 0;
fail_dev:
kfree(dev);
fail_core:
core->dvbdev = NULL;
cx88_core_put(core, pci_dev);
return err;
}
static void cx8802_remove(struct pci_dev *pci_dev)
{
struct cx8802_dev *dev;
dev = pci_get_drvdata(pci_dev);
dprintk(1, "%s\n", __func__);
flush_request_modules(dev);
mutex_lock(&dev->core->lock);
if (!list_empty(&dev->drvlist)) {
struct cx8802_driver *drv, *tmp;
int err;
pr_warn("Trying to remove cx8802 driver while cx8802 sub-drivers still loaded?!\n");
list_for_each_entry_safe(drv, tmp, &dev->drvlist, drvlist) {
err = drv->remove(drv);
if (err == 0) {
list_del(&drv->drvlist);
} else
pr_err("cx8802 driver remove failed (%d)\n",
err);
kfree(drv);
}
}
mutex_unlock(&dev->core->lock);
/* Destroy any 8802 reference. */
dev->core->dvbdev = NULL;
/* common */
cx8802_fini_common(dev);
cx88_core_put(dev->core, dev->pci);
kfree(dev);
}
static const struct pci_device_id cx8802_pci_tbl[] = {
{
.vendor = 0x14f1,
.device = 0x8802,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
}, {
/* --- end of list --- */
}
};
MODULE_DEVICE_TABLE(pci, cx8802_pci_tbl);
static struct pci_driver cx8802_pci_driver = {
.name = "cx88-mpeg driver manager",
.id_table = cx8802_pci_tbl,
.probe = cx8802_probe,
.remove = cx8802_remove,
};
module_pci_driver(cx8802_pci_driver);
| linux-master | drivers/media/pci/cx88/cx88-mpeg.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for audio capture
* PCI function #1 of the cx2388x.
*
* (c) 2007 Trent Piepho <[email protected]>
* (c) 2005,2006 Ricardo Cerqueira <[email protected]>
* (c) 2005 Mauro Carvalho Chehab <[email protected]>
* Based on a dummy cx88 module by Gerd Knorr <[email protected]>
* Based on dummy.c by Jaroslav Kysela <[email protected]>
*/
#include "cx88.h"
#include "cx88-reg.h"
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/vmalloc.h>
#include <linux/dma-mapping.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/control.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <media/i2c/wm8775.h>
#define dprintk(level, fmt, arg...) do { \
if (debug + 1 > level) \
printk(KERN_DEBUG pr_fmt("%s: alsa: " fmt), \
chip->core->name, ##arg); \
} while (0)
/*
* Data type declarations - Can be moded to a header file later
*/
struct cx88_audio_buffer {
unsigned int bpl;
struct cx88_riscmem risc;
void *vaddr;
struct scatterlist *sglist;
int sglen;
unsigned long nr_pages;
};
struct cx88_audio_dev {
struct cx88_core *core;
struct cx88_dmaqueue q;
/* pci i/o */
struct pci_dev *pci;
/* audio controls */
int irq;
struct snd_card *card;
spinlock_t reg_lock;
atomic_t count;
unsigned int dma_size;
unsigned int period_size;
unsigned int num_periods;
struct cx88_audio_buffer *buf;
struct snd_pcm_substream *substream;
};
/*
* Module global static vars
*/
static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
static const char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable cx88x soundcard. default enabled.");
module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for cx88x capture interface(s).");
/*
* Module macros
*/
MODULE_DESCRIPTION("ALSA driver module for cx2388x based TV cards");
MODULE_AUTHOR("Ricardo Cerqueira");
MODULE_AUTHOR("Mauro Carvalho Chehab <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_VERSION(CX88_VERSION);
static unsigned int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable debug messages");
/*
* Module specific functions
*/
/*
* BOARD Specific: Sets audio DMA
*/
static int _cx88_start_audio_dma(struct cx88_audio_dev *chip)
{
struct cx88_audio_buffer *buf = chip->buf;
struct cx88_core *core = chip->core;
const struct sram_channel *audio_ch = &cx88_sram_channels[SRAM_CH25];
/* Make sure RISC/FIFO are off before changing FIFO/RISC settings */
cx_clear(MO_AUD_DMACNTRL, 0x11);
/* setup fifo + format - out channel */
cx88_sram_channel_setup(chip->core, audio_ch, buf->bpl, buf->risc.dma);
/* sets bpl size */
cx_write(MO_AUDD_LNGTH, buf->bpl);
/* reset counter */
cx_write(MO_AUDD_GPCNTRL, GP_COUNT_CONTROL_RESET);
atomic_set(&chip->count, 0);
dprintk(1,
"Start audio DMA, %d B/line, %d lines/FIFO, %d periods, %d byte buffer\n",
buf->bpl, cx_read(audio_ch->cmds_start + 8) >> 1,
chip->num_periods, buf->bpl * chip->num_periods);
/* Enables corresponding bits at AUD_INT_STAT */
cx_write(MO_AUD_INTMSK, AUD_INT_OPC_ERR | AUD_INT_DN_SYNC |
AUD_INT_DN_RISCI2 | AUD_INT_DN_RISCI1);
/* Clean any pending interrupt bits already set */
cx_write(MO_AUD_INTSTAT, ~0);
/* enable audio irqs */
cx_set(MO_PCI_INTMSK, chip->core->pci_irqmask | PCI_INT_AUDINT);
/* start dma */
/* Enables Risc Processor */
cx_set(MO_DEV_CNTRL2, (1 << 5));
/* audio downstream FIFO and RISC enable */
cx_set(MO_AUD_DMACNTRL, 0x11);
if (debug)
cx88_sram_channel_dump(chip->core, audio_ch);
return 0;
}
/*
* BOARD Specific: Resets audio DMA
*/
static int _cx88_stop_audio_dma(struct cx88_audio_dev *chip)
{
struct cx88_core *core = chip->core;
dprintk(1, "Stopping audio DMA\n");
/* stop dma */
cx_clear(MO_AUD_DMACNTRL, 0x11);
/* disable irqs */
cx_clear(MO_PCI_INTMSK, PCI_INT_AUDINT);
cx_clear(MO_AUD_INTMSK, AUD_INT_OPC_ERR | AUD_INT_DN_SYNC |
AUD_INT_DN_RISCI2 | AUD_INT_DN_RISCI1);
if (debug)
cx88_sram_channel_dump(chip->core,
&cx88_sram_channels[SRAM_CH25]);
return 0;
}
#define MAX_IRQ_LOOP 50
/*
* BOARD Specific: IRQ dma bits
*/
static const char *cx88_aud_irqs[32] = {
"dn_risci1", "up_risci1", "rds_dn_risc1", /* 0-2 */
NULL, /* reserved */
"dn_risci2", "up_risci2", "rds_dn_risc2", /* 4-6 */
NULL, /* reserved */
"dnf_of", "upf_uf", "rds_dnf_uf", /* 8-10 */
NULL, /* reserved */
"dn_sync", "up_sync", "rds_dn_sync", /* 12-14 */
NULL, /* reserved */
"opc_err", "par_err", "rip_err", /* 16-18 */
"pci_abort", "ber_irq", "mchg_irq" /* 19-21 */
};
/*
* BOARD Specific: Threats IRQ audio specific calls
*/
static void cx8801_aud_irq(struct cx88_audio_dev *chip)
{
struct cx88_core *core = chip->core;
u32 status, mask;
status = cx_read(MO_AUD_INTSTAT);
mask = cx_read(MO_AUD_INTMSK);
if (0 == (status & mask))
return;
cx_write(MO_AUD_INTSTAT, status);
if (debug > 1 || (status & mask & ~0xff))
cx88_print_irqbits("irq aud",
cx88_aud_irqs, ARRAY_SIZE(cx88_aud_irqs),
status, mask);
/* risc op code error */
if (status & AUD_INT_OPC_ERR) {
pr_warn("Audio risc op code error\n");
cx_clear(MO_AUD_DMACNTRL, 0x11);
cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH25]);
}
if (status & AUD_INT_DN_SYNC) {
dprintk(1, "Downstream sync error\n");
cx_write(MO_AUDD_GPCNTRL, GP_COUNT_CONTROL_RESET);
return;
}
/* risc1 downstream */
if (status & AUD_INT_DN_RISCI1) {
atomic_set(&chip->count, cx_read(MO_AUDD_GPCNT));
snd_pcm_period_elapsed(chip->substream);
}
/* FIXME: Any other status should deserve a special handling? */
}
/*
* BOARD Specific: Handles IRQ calls
*/
static irqreturn_t cx8801_irq(int irq, void *dev_id)
{
struct cx88_audio_dev *chip = dev_id;
struct cx88_core *core = chip->core;
u32 status;
int loop, handled = 0;
for (loop = 0; loop < MAX_IRQ_LOOP; loop++) {
status = cx_read(MO_PCI_INTSTAT) &
(core->pci_irqmask | PCI_INT_AUDINT);
if (status == 0)
goto out;
dprintk(3, "cx8801_irq loop %d/%d, status %x\n",
loop, MAX_IRQ_LOOP, status);
handled = 1;
cx_write(MO_PCI_INTSTAT, status);
if (status & core->pci_irqmask)
cx88_core_irq(core, status);
if (status & PCI_INT_AUDINT)
cx8801_aud_irq(chip);
}
if (loop == MAX_IRQ_LOOP) {
pr_err("IRQ loop detected, disabling interrupts\n");
cx_clear(MO_PCI_INTMSK, PCI_INT_AUDINT);
}
out:
return IRQ_RETVAL(handled);
}
static int cx88_alsa_dma_init(struct cx88_audio_dev *chip,
unsigned long nr_pages)
{
struct cx88_audio_buffer *buf = chip->buf;
struct page *pg;
int i;
buf->vaddr = vmalloc_32(nr_pages << PAGE_SHIFT);
if (!buf->vaddr) {
dprintk(1, "vmalloc_32(%lu pages) failed\n", nr_pages);
return -ENOMEM;
}
dprintk(1, "vmalloc is at addr %p, size=%lu\n",
buf->vaddr, nr_pages << PAGE_SHIFT);
memset(buf->vaddr, 0, nr_pages << PAGE_SHIFT);
buf->nr_pages = nr_pages;
buf->sglist = vzalloc(array_size(sizeof(*buf->sglist), buf->nr_pages));
if (!buf->sglist)
goto vzalloc_err;
sg_init_table(buf->sglist, buf->nr_pages);
for (i = 0; i < buf->nr_pages; i++) {
pg = vmalloc_to_page(buf->vaddr + i * PAGE_SIZE);
if (!pg)
goto vmalloc_to_page_err;
sg_set_page(&buf->sglist[i], pg, PAGE_SIZE, 0);
}
return 0;
vmalloc_to_page_err:
vfree(buf->sglist);
buf->sglist = NULL;
vzalloc_err:
vfree(buf->vaddr);
buf->vaddr = NULL;
return -ENOMEM;
}
static int cx88_alsa_dma_map(struct cx88_audio_dev *dev)
{
struct cx88_audio_buffer *buf = dev->buf;
buf->sglen = dma_map_sg(&dev->pci->dev, buf->sglist,
buf->nr_pages, DMA_FROM_DEVICE);
if (buf->sglen == 0) {
pr_warn("%s: cx88_alsa_map_sg failed\n", __func__);
return -ENOMEM;
}
return 0;
}
static int cx88_alsa_dma_unmap(struct cx88_audio_dev *dev)
{
struct cx88_audio_buffer *buf = dev->buf;
if (!buf->sglen)
return 0;
dma_unmap_sg(&dev->pci->dev, buf->sglist, buf->nr_pages,
DMA_FROM_DEVICE);
buf->sglen = 0;
return 0;
}
static int cx88_alsa_dma_free(struct cx88_audio_buffer *buf)
{
vfree(buf->sglist);
buf->sglist = NULL;
vfree(buf->vaddr);
buf->vaddr = NULL;
return 0;
}
static int dsp_buffer_free(struct cx88_audio_dev *chip)
{
struct cx88_riscmem *risc = &chip->buf->risc;
WARN_ON(!chip->dma_size);
dprintk(2, "Freeing buffer\n");
cx88_alsa_dma_unmap(chip);
cx88_alsa_dma_free(chip->buf);
if (risc->cpu)
dma_free_coherent(&chip->pci->dev, risc->size, risc->cpu,
risc->dma);
kfree(chip->buf);
chip->buf = NULL;
return 0;
}
/*
* ALSA PCM Interface
*/
/*
* Digital hardware definition
*/
#define DEFAULT_FIFO_SIZE 4096
static const struct snd_pcm_hardware snd_cx88_digital_hw = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
/*
* Analog audio output will be full of clicks and pops if there
* are not exactly four lines in the SRAM FIFO buffer.
*/
.period_bytes_min = DEFAULT_FIFO_SIZE / 4,
.period_bytes_max = DEFAULT_FIFO_SIZE / 4,
.periods_min = 1,
.periods_max = 1024,
.buffer_bytes_max = (1024 * 1024),
};
/*
* audio pcm capture open callback
*/
static int snd_cx88_pcm_open(struct snd_pcm_substream *substream)
{
struct cx88_audio_dev *chip = snd_pcm_substream_chip(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int err;
if (!chip) {
pr_err("BUG: cx88 can't find device struct. Can't proceed with open\n");
return -ENODEV;
}
err = snd_pcm_hw_constraint_pow2(runtime, 0,
SNDRV_PCM_HW_PARAM_PERIODS);
if (err < 0)
goto _error;
chip->substream = substream;
runtime->hw = snd_cx88_digital_hw;
if (cx88_sram_channels[SRAM_CH25].fifo_size != DEFAULT_FIFO_SIZE) {
unsigned int bpl = cx88_sram_channels[SRAM_CH25].fifo_size / 4;
bpl &= ~7; /* must be multiple of 8 */
runtime->hw.period_bytes_min = bpl;
runtime->hw.period_bytes_max = bpl;
}
return 0;
_error:
dprintk(1, "Error opening PCM!\n");
return err;
}
/*
* audio close callback
*/
static int snd_cx88_close(struct snd_pcm_substream *substream)
{
return 0;
}
/*
* hw_params callback
*/
static int snd_cx88_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct cx88_audio_dev *chip = snd_pcm_substream_chip(substream);
struct cx88_audio_buffer *buf;
int ret;
if (substream->runtime->dma_area) {
dsp_buffer_free(chip);
substream->runtime->dma_area = NULL;
}
chip->period_size = params_period_bytes(hw_params);
chip->num_periods = params_periods(hw_params);
chip->dma_size = chip->period_size * params_periods(hw_params);
WARN_ON(!chip->dma_size);
WARN_ON(chip->num_periods & (chip->num_periods - 1));
buf = kzalloc(sizeof(*buf), GFP_KERNEL);
if (!buf)
return -ENOMEM;
chip->buf = buf;
buf->bpl = chip->period_size;
ret = cx88_alsa_dma_init(chip,
(PAGE_ALIGN(chip->dma_size) >> PAGE_SHIFT));
if (ret < 0)
goto error;
ret = cx88_alsa_dma_map(chip);
if (ret < 0)
goto error;
ret = cx88_risc_databuffer(chip->pci, &buf->risc, buf->sglist,
chip->period_size, chip->num_periods, 1);
if (ret < 0)
goto error;
/* Loop back to start of program */
buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
substream->runtime->dma_area = chip->buf->vaddr;
substream->runtime->dma_bytes = chip->dma_size;
substream->runtime->dma_addr = 0;
return 0;
error:
kfree(buf);
return ret;
}
/*
* hw free callback
*/
static int snd_cx88_hw_free(struct snd_pcm_substream *substream)
{
struct cx88_audio_dev *chip = snd_pcm_substream_chip(substream);
if (substream->runtime->dma_area) {
dsp_buffer_free(chip);
substream->runtime->dma_area = NULL;
}
return 0;
}
/*
* prepare callback
*/
static int snd_cx88_prepare(struct snd_pcm_substream *substream)
{
return 0;
}
/*
* trigger callback
*/
static int snd_cx88_card_trigger(struct snd_pcm_substream *substream, int cmd)
{
struct cx88_audio_dev *chip = snd_pcm_substream_chip(substream);
int err;
/* Local interrupts are already disabled by ALSA */
spin_lock(&chip->reg_lock);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
err = _cx88_start_audio_dma(chip);
break;
case SNDRV_PCM_TRIGGER_STOP:
err = _cx88_stop_audio_dma(chip);
break;
default:
err = -EINVAL;
break;
}
spin_unlock(&chip->reg_lock);
return err;
}
/*
* pointer callback
*/
static snd_pcm_uframes_t snd_cx88_pointer(struct snd_pcm_substream *substream)
{
struct cx88_audio_dev *chip = snd_pcm_substream_chip(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
u16 count;
count = atomic_read(&chip->count);
// dprintk(2, "%s - count %d (+%u), period %d, frame %lu\n", __func__,
// count, new, count & (runtime->periods-1),
// runtime->period_size * (count & (runtime->periods-1)));
return runtime->period_size * (count & (runtime->periods - 1));
}
/*
* page callback (needed for mmap)
*/
static struct page *snd_cx88_page(struct snd_pcm_substream *substream,
unsigned long offset)
{
void *pageptr = substream->runtime->dma_area + offset;
return vmalloc_to_page(pageptr);
}
/*
* operators
*/
static const struct snd_pcm_ops snd_cx88_pcm_ops = {
.open = snd_cx88_pcm_open,
.close = snd_cx88_close,
.hw_params = snd_cx88_hw_params,
.hw_free = snd_cx88_hw_free,
.prepare = snd_cx88_prepare,
.trigger = snd_cx88_card_trigger,
.pointer = snd_cx88_pointer,
.page = snd_cx88_page,
};
/*
* create a PCM device
*/
static int snd_cx88_pcm(struct cx88_audio_dev *chip, int device,
const char *name)
{
int err;
struct snd_pcm *pcm;
err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm);
if (err < 0)
return err;
pcm->private_data = chip;
strscpy(pcm->name, name, sizeof(pcm->name));
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cx88_pcm_ops);
return 0;
}
/*
* CONTROL INTERFACE
*/
static int snd_cx88_volume_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *info)
{
info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
info->count = 2;
info->value.integer.min = 0;
info->value.integer.max = 0x3f;
return 0;
}
static int snd_cx88_volume_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *value)
{
struct cx88_audio_dev *chip = snd_kcontrol_chip(kcontrol);
struct cx88_core *core = chip->core;
int vol = 0x3f - (cx_read(AUD_VOL_CTL) & 0x3f),
bal = cx_read(AUD_BAL_CTL);
value->value.integer.value[(bal & 0x40) ? 0 : 1] = vol;
vol -= (bal & 0x3f);
value->value.integer.value[(bal & 0x40) ? 1 : 0] = vol < 0 ? 0 : vol;
return 0;
}
static void snd_cx88_wm8775_volume_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *value)
{
struct cx88_audio_dev *chip = snd_kcontrol_chip(kcontrol);
struct cx88_core *core = chip->core;
u16 left = value->value.integer.value[0];
u16 right = value->value.integer.value[1];
int v, b;
/* Pass volume & balance onto any WM8775 */
if (left >= right) {
v = left << 10;
b = left ? (0x8000 * right) / left : 0x8000;
} else {
v = right << 10;
b = right ? 0xffff - (0x8000 * left) / right : 0x8000;
}
wm8775_s_ctrl(core, V4L2_CID_AUDIO_VOLUME, v);
wm8775_s_ctrl(core, V4L2_CID_AUDIO_BALANCE, b);
}
/* OK - TODO: test it */
static int snd_cx88_volume_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *value)
{
struct cx88_audio_dev *chip = snd_kcontrol_chip(kcontrol);
struct cx88_core *core = chip->core;
int left, right, v, b;
int changed = 0;
u32 old;
if (core->sd_wm8775)
snd_cx88_wm8775_volume_put(kcontrol, value);
left = value->value.integer.value[0] & 0x3f;
right = value->value.integer.value[1] & 0x3f;
b = right - left;
if (b < 0) {
v = 0x3f - left;
b = (-b) | 0x40;
} else {
v = 0x3f - right;
}
/* Do we really know this will always be called with IRQs on? */
spin_lock_irq(&chip->reg_lock);
old = cx_read(AUD_VOL_CTL);
if (v != (old & 0x3f)) {
cx_swrite(SHADOW_AUD_VOL_CTL, AUD_VOL_CTL, (old & ~0x3f) | v);
changed = 1;
}
if ((cx_read(AUD_BAL_CTL) & 0x7f) != b) {
cx_write(AUD_BAL_CTL, b);
changed = 1;
}
spin_unlock_irq(&chip->reg_lock);
return changed;
}
static const DECLARE_TLV_DB_SCALE(snd_cx88_db_scale, -6300, 100, 0);
static const struct snd_kcontrol_new snd_cx88_volume = {
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
SNDRV_CTL_ELEM_ACCESS_TLV_READ,
.name = "Analog-TV Volume",
.info = snd_cx88_volume_info,
.get = snd_cx88_volume_get,
.put = snd_cx88_volume_put,
.tlv.p = snd_cx88_db_scale,
};
static int snd_cx88_switch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *value)
{
struct cx88_audio_dev *chip = snd_kcontrol_chip(kcontrol);
struct cx88_core *core = chip->core;
u32 bit = kcontrol->private_value;
value->value.integer.value[0] = !(cx_read(AUD_VOL_CTL) & bit);
return 0;
}
static int snd_cx88_switch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *value)
{
struct cx88_audio_dev *chip = snd_kcontrol_chip(kcontrol);
struct cx88_core *core = chip->core;
u32 bit = kcontrol->private_value;
int ret = 0;
u32 vol;
spin_lock_irq(&chip->reg_lock);
vol = cx_read(AUD_VOL_CTL);
if (value->value.integer.value[0] != !(vol & bit)) {
vol ^= bit;
cx_swrite(SHADOW_AUD_VOL_CTL, AUD_VOL_CTL, vol);
/* Pass mute onto any WM8775 */
if (core->sd_wm8775 && ((1 << 6) == bit))
wm8775_s_ctrl(core,
V4L2_CID_AUDIO_MUTE, 0 != (vol & bit));
ret = 1;
}
spin_unlock_irq(&chip->reg_lock);
return ret;
}
static const struct snd_kcontrol_new snd_cx88_dac_switch = {
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Audio-Out Switch",
.info = snd_ctl_boolean_mono_info,
.get = snd_cx88_switch_get,
.put = snd_cx88_switch_put,
.private_value = (1 << 8),
};
static const struct snd_kcontrol_new snd_cx88_source_switch = {
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Analog-TV Switch",
.info = snd_ctl_boolean_mono_info,
.get = snd_cx88_switch_get,
.put = snd_cx88_switch_put,
.private_value = (1 << 6),
};
static int snd_cx88_alc_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *value)
{
struct cx88_audio_dev *chip = snd_kcontrol_chip(kcontrol);
struct cx88_core *core = chip->core;
s32 val;
val = wm8775_g_ctrl(core, V4L2_CID_AUDIO_LOUDNESS);
value->value.integer.value[0] = val ? 1 : 0;
return 0;
}
static int snd_cx88_alc_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *value)
{
struct cx88_audio_dev *chip = snd_kcontrol_chip(kcontrol);
struct cx88_core *core = chip->core;
wm8775_s_ctrl(core, V4L2_CID_AUDIO_LOUDNESS,
value->value.integer.value[0] != 0);
return 0;
}
static const struct snd_kcontrol_new snd_cx88_alc_switch = {
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Line-In ALC Switch",
.info = snd_ctl_boolean_mono_info,
.get = snd_cx88_alc_get,
.put = snd_cx88_alc_put,
};
/*
* Basic Flow for Sound Devices
*/
/*
* PCI ID Table - 14f1:8801 and 14f1:8811 means function 1: Audio
* Only boards with eeprom and byte 1 at eeprom=1 have it
*/
static const struct pci_device_id cx88_audio_pci_tbl[] = {
{0x14f1, 0x8801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{0x14f1, 0x8811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{0, }
};
MODULE_DEVICE_TABLE(pci, cx88_audio_pci_tbl);
/*
* Chip-specific destructor
*/
static int snd_cx88_free(struct cx88_audio_dev *chip)
{
if (chip->irq >= 0)
free_irq(chip->irq, chip);
cx88_core_put(chip->core, chip->pci);
pci_disable_device(chip->pci);
return 0;
}
/*
* Component Destructor
*/
static void snd_cx88_dev_free(struct snd_card *card)
{
struct cx88_audio_dev *chip = card->private_data;
snd_cx88_free(chip);
}
/*
* Alsa Constructor - Component probe
*/
static int devno;
static int snd_cx88_create(struct snd_card *card, struct pci_dev *pci,
struct cx88_audio_dev **rchip,
struct cx88_core **core_ptr)
{
struct cx88_audio_dev *chip;
struct cx88_core *core;
int err;
unsigned char pci_lat;
*rchip = NULL;
err = pci_enable_device(pci);
if (err < 0)
return err;
pci_set_master(pci);
chip = card->private_data;
core = cx88_core_get(pci);
if (!core) {
err = -EINVAL;
return err;
}
err = dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
if (err) {
dprintk(0, "%s/1: Oops: no 32bit PCI DMA ???\n", core->name);
cx88_core_put(core, pci);
return err;
}
/* pci init */
chip->card = card;
chip->pci = pci;
chip->irq = -1;
spin_lock_init(&chip->reg_lock);
chip->core = core;
/* get irq */
err = request_irq(chip->pci->irq, cx8801_irq,
IRQF_SHARED, chip->core->name, chip);
if (err < 0) {
dprintk(0, "%s: can't get IRQ %d\n",
chip->core->name, chip->pci->irq);
return err;
}
/* print pci info */
pci_read_config_byte(pci, PCI_LATENCY_TIMER, &pci_lat);
dprintk(1,
"ALSA %s/%i: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
core->name, devno,
pci_name(pci), pci->revision, pci->irq,
pci_lat, (unsigned long long)pci_resource_start(pci, 0));
chip->irq = pci->irq;
synchronize_irq(chip->irq);
*rchip = chip;
*core_ptr = core;
return 0;
}
static int cx88_audio_initdev(struct pci_dev *pci,
const struct pci_device_id *pci_id)
{
struct snd_card *card;
struct cx88_audio_dev *chip;
struct cx88_core *core = NULL;
int err;
if (devno >= SNDRV_CARDS)
return (-ENODEV);
if (!enable[devno]) {
++devno;
return (-ENOENT);
}
err = snd_card_new(&pci->dev, index[devno], id[devno], THIS_MODULE,
sizeof(struct cx88_audio_dev), &card);
if (err < 0)
return err;
card->private_free = snd_cx88_dev_free;
err = snd_cx88_create(card, pci, &chip, &core);
if (err < 0)
goto error;
err = snd_cx88_pcm(chip, 0, "CX88 Digital");
if (err < 0)
goto error;
err = snd_ctl_add(card, snd_ctl_new1(&snd_cx88_volume, chip));
if (err < 0)
goto error;
err = snd_ctl_add(card, snd_ctl_new1(&snd_cx88_dac_switch, chip));
if (err < 0)
goto error;
err = snd_ctl_add(card, snd_ctl_new1(&snd_cx88_source_switch, chip));
if (err < 0)
goto error;
/* If there's a wm8775 then add a Line-In ALC switch */
if (core->sd_wm8775) {
err = snd_ctl_add(card, snd_ctl_new1(&snd_cx88_alc_switch, chip));
if (err < 0)
goto error;
}
strscpy(card->driver, "CX88x", sizeof(card->driver));
sprintf(card->shortname, "Conexant CX%x", pci->device);
sprintf(card->longname, "%s at %#llx",
card->shortname,
(unsigned long long)pci_resource_start(pci, 0));
strscpy(card->mixername, "CX88", sizeof(card->mixername));
dprintk(0, "%s/%i: ALSA support for cx2388x boards\n",
card->driver, devno);
err = snd_card_register(card);
if (err < 0)
goto error;
pci_set_drvdata(pci, card);
devno++;
return 0;
error:
snd_card_free(card);
return err;
}
/*
* ALSA destructor
*/
static void cx88_audio_finidev(struct pci_dev *pci)
{
struct snd_card *card = pci_get_drvdata(pci);
snd_card_free(card);
devno--;
}
/*
* PCI driver definition
*/
static struct pci_driver cx88_audio_pci_driver = {
.name = "cx88_audio",
.id_table = cx88_audio_pci_tbl,
.probe = cx88_audio_initdev,
.remove = cx88_audio_finidev,
};
module_pci_driver(cx88_audio_pci_driver);
| linux-master | drivers/media/pci/cx88/cx88-alsa.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* device driver for Conexant 2388x based TV cards
* card-specific stuff.
*
* (c) 2003 Gerd Knorr <[email protected]> [SuSE Labs]
*/
#include "cx88.h"
#include "tea5767.h"
#include "xc4000.h"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/slab.h>
static unsigned int tuner[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
static unsigned int radio[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
static unsigned int card[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
module_param_array(tuner, int, NULL, 0444);
module_param_array(radio, int, NULL, 0444);
module_param_array(card, int, NULL, 0444);
MODULE_PARM_DESC(tuner, "tuner type");
MODULE_PARM_DESC(radio, "radio tuner type");
MODULE_PARM_DESC(card, "card type");
static unsigned int latency = UNSET;
module_param(latency, int, 0444);
MODULE_PARM_DESC(latency, "pci latency timer");
static int disable_ir;
module_param(disable_ir, int, 0444);
MODULE_PARM_DESC(disable_ir, "Disable IR support");
#define dprintk(level, fmt, arg...) do { \
if (cx88_core_debug >= level) \
printk(KERN_DEBUG pr_fmt("%s: core:" fmt), \
__func__, ##arg); \
} while (0)
/* ------------------------------------------------------------------ */
/* board config info */
/* If radio_type !=UNSET, radio_addr should be specified
*/
static const struct cx88_board cx88_boards[] = {
[CX88_BOARD_UNKNOWN] = {
.name = "UNKNOWN/GENERIC",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 0,
}, {
.type = CX88_VMUX_COMPOSITE2,
.vmux = 1,
}, {
.type = CX88_VMUX_COMPOSITE3,
.vmux = 2,
}, {
.type = CX88_VMUX_COMPOSITE4,
.vmux = 3,
} },
},
[CX88_BOARD_HAUPPAUGE] = {
.name = "Hauppauge WinTV 34xxx models",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0xff00, // internal decoder
}, {
.type = CX88_VMUX_DEBUG,
.vmux = 0,
.gpio0 = 0xff01, // mono from tuner chip
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0xff02,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0xff02,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0xff01,
},
},
[CX88_BOARD_GDI] = {
.name = "GDI Black Gold",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
} },
},
[CX88_BOARD_PIXELVIEW] = {
.name = "PixelView",
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0xff00, // internal decoder
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0xff10,
},
},
[CX88_BOARD_ATI_WONDER_PRO] = {
.name = "ATI TV Wonder Pro",
.tuner_type = TUNER_PHILIPS_4IN1,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT | TDA9887_INTERCARRIER,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x03ff,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x03fe,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x03fe,
} },
},
[CX88_BOARD_WINFAST2000XP_EXPERT] = {
.name = "Leadtek Winfast 2000XP Expert",
.tuner_type = TUNER_PHILIPS_4IN1,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x00F5e700,
.gpio1 = 0x00003004,
.gpio2 = 0x00F5e700,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x00F5c700,
.gpio1 = 0x00003004,
.gpio2 = 0x00F5c700,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x00F5c700,
.gpio1 = 0x00003004,
.gpio2 = 0x00F5c700,
.gpio3 = 0x02000000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x00F5d700,
.gpio1 = 0x00003004,
.gpio2 = 0x00F5d700,
.gpio3 = 0x02000000,
},
},
[CX88_BOARD_AVERTV_STUDIO_303] = {
.name = "AverTV Studio 303 (M126)",
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio1 = 0xe09f,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio1 = 0xe05f,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio1 = 0xe05f,
} },
.radio = {
.gpio1 = 0xe0df,
.type = CX88_RADIO,
},
},
[CX88_BOARD_MSI_TVANYWHERE_MASTER] = {
// added gpio values thanks to Michal
// values for PAL from DScaler
.name = "MSI TV-@nywhere Master",
.tuner_type = TUNER_MT2032,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT | TDA9887_INTERCARRIER_NTSC,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x000040bf,
.gpio1 = 0x000080c0,
.gpio2 = 0x0000ff40,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x000040bf,
.gpio1 = 0x000080c0,
.gpio2 = 0x0000ff40,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x000040bf,
.gpio1 = 0x000080c0,
.gpio2 = 0x0000ff40,
} },
.radio = {
.type = CX88_RADIO,
.vmux = 3,
.gpio0 = 0x000040bf,
.gpio1 = 0x000080c0,
.gpio2 = 0x0000ff20,
},
},
[CX88_BOARD_WINFAST_DV2000] = {
.name = "Leadtek Winfast DV2000",
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0035e700,
.gpio1 = 0x00003004,
.gpio2 = 0x0035e700,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0035c700,
.gpio1 = 0x00003004,
.gpio2 = 0x0035c700,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0035c700,
.gpio1 = 0x0035c700,
.gpio2 = 0x02000000,
.gpio3 = 0x02000000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x0035d700,
.gpio1 = 0x00007004,
.gpio2 = 0x0035d700,
.gpio3 = 0x02000000,
},
},
[CX88_BOARD_LEADTEK_PVR2000] = {
// gpio values for PAL version from regspy by DScaler
.name = "Leadtek PVR 2000",
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0000bde2,
.audioroute = 1,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0000bde6,
.audioroute = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0000bde6,
.audioroute = 1,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x0000bd62,
.audioroute = 1,
},
.mpeg = CX88_MPEG_BLACKBIRD,
},
[CX88_BOARD_IODATA_GVVCP3PCI] = {
.name = "IODATA GV-VCP3/PCI",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 0,
}, {
.type = CX88_VMUX_COMPOSITE2,
.vmux = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
} },
},
[CX88_BOARD_PROLINK_PLAYTVPVR] = {
.name = "Prolink PlayTV PVR",
.tuner_type = TUNER_PHILIPS_FM1236_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0xbff0,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0xbff3,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0xbff3,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0xbff0,
},
},
[CX88_BOARD_ASUS_PVR_416] = {
.name = "ASUS PVR-416",
.tuner_type = TUNER_PHILIPS_FM1236_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0000fde6,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0000fde6, // 0x0000fda6 L,R RCA audio in?
.audioroute = 1,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x0000fde2,
},
.mpeg = CX88_MPEG_BLACKBIRD,
},
[CX88_BOARD_MSI_TVANYWHERE] = {
.name = "MSI TV-@nywhere",
.tuner_type = TUNER_MT2032,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x00000fbf,
.gpio2 = 0x0000fc08,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x00000fbf,
.gpio2 = 0x0000fc68,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x00000fbf,
.gpio2 = 0x0000fc68,
} },
},
[CX88_BOARD_KWORLD_DVB_T] = {
.name = "KWorld/VStream XPert DVB-T",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0700,
.gpio2 = 0x0101,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0700,
.gpio2 = 0x0101,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1] = {
.name = "DViCO FusionHDTV DVB-T1",
.tuner_type = UNSET, /* No analog tuner */
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x000027df,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x000027df,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_KWORLD_LTV883] = {
.name = "KWorld LTV883RF",
.tuner_type = TUNER_TNF_8831BGFF,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x07f8,
}, {
.type = CX88_VMUX_DEBUG,
.vmux = 0,
.gpio0 = 0x07f9, // mono from tuner chip
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x000007fa,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x000007fa,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x000007f8,
},
},
[CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q] = {
.name = "DViCO FusionHDTV 3 Gold-Q",
.tuner_type = TUNER_MICROTUNE_4042FI5,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
/*
* GPIO[0] resets DT3302 DTV receiver
* 0 - reset asserted
* 1 - normal operation
* GPIO[1] mutes analog audio output connector
* 0 - enable selected source
* 1 - mute
* GPIO[2] selects source for analog audio output connector
* 0 - analog audio input connector on tab
* 1 - analog DAC output from CX23881 chip
* GPIO[3] selects RF input connector on tuner module
* 0 - RF connector labeled CABLE
* 1 - RF connector labeled ANT
* GPIO[4] selects high RF for QAM256 mode
* 0 - normal RF
* 1 - high RF
*/
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0f0d,
}, {
.type = CX88_VMUX_CABLE,
.vmux = 0,
.gpio0 = 0x0f05,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0f00,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0f00,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_HAUPPAUGE_DVB_T1] = {
.name = "Hauppauge Nova-T DVB-T",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_CONEXANT_DVB_T1] = {
.name = "Conexant DVB-T reference design",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_PROVIDEO_PV259] = {
.name = "Provideo PV259",
.tuner_type = TUNER_PHILIPS_FQ1216ME,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.audioroute = 1,
} },
.mpeg = CX88_MPEG_BLACKBIRD,
},
[CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS] = {
.name = "DViCO FusionHDTV DVB-T Plus",
.tuner_type = UNSET, /* No analog tuner */
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x000027df,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x000027df,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_DNTV_LIVE_DVB_T] = {
.name = "digitalnow DNTV Live! DVB-T",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x00000700,
.gpio2 = 0x00000101,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x00000700,
.gpio2 = 0x00000101,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_PCHDTV_HD3000] = {
.name = "pcHDTV HD3000 HDTV",
.tuner_type = TUNER_THOMSON_DTT761X,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
/* GPIO[2] = audio source for analog audio out connector
* 0 = analog audio input connector
* 1 = CX88 audio DACs
*
* GPIO[7] = input to CX88's audio/chroma ADC
* 0 = FM 10.7 MHz IF
* 1 = Sound 4.5 MHz IF
*
* GPIO[1,5,6] = Oren 51132 pins 27,35,28 respectively
*
* GPIO[16] = Remote control input
*/
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x00008484,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x00008400,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x00008400,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x00008404,
},
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_HAUPPAUGE_ROSLYN] = {
// entry added by Kaustubh D. Bhalerao <[email protected]>
// GPIO values obtained from regspy, courtesy Sean Covel
.name = "Hauppauge WinTV 28xxx (Roslyn) models",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0xed1a,
.gpio2 = 0x00ff,
}, {
.type = CX88_VMUX_DEBUG,
.vmux = 0,
.gpio0 = 0xff01,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0xff02,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0xed92,
.gpio2 = 0x00ff,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0xed96,
.gpio2 = 0x00ff,
},
.mpeg = CX88_MPEG_BLACKBIRD,
},
[CX88_BOARD_DIGITALLOGIC_MEC] = {
.name = "Digital-Logic MICROSPACE Entertainment Center (MEC)",
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x00009d80,
.audioroute = 1,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x00009d76,
.audioroute = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x00009d76,
.audioroute = 1,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x00009d00,
.audioroute = 1,
},
.mpeg = CX88_MPEG_BLACKBIRD,
},
[CX88_BOARD_IODATA_GVBCTV7E] = {
.name = "IODATA GV/BCTV7E",
.tuner_type = TUNER_PHILIPS_FQ1286,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 1,
.gpio1 = 0x0000e03f,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 2,
.gpio1 = 0x0000e07f,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 3,
.gpio1 = 0x0000e07f,
} }
},
[CX88_BOARD_PIXELVIEW_PLAYTV_ULTRA_PRO] = {
.name = "PixelView PlayTV Ultra Pro (Stereo)",
/* May be also TUNER_YMEC_TVF_5533MF for NTSC/M or PAL/M */
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
/*
* Some variants use a tda9874 and so need the
* tvaudio module.
*/
.audio_chip = CX88_AUDIO_TVAUDIO,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0xbf61, /* internal decoder */
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0xbf63,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0xbf63,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0xbf60,
},
},
[CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T] = {
.name = "DViCO FusionHDTV 3 Gold-T",
.tuner_type = TUNER_THOMSON_DTT761X,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x97ed,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x97e9,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x97e9,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_ADSTECH_DVB_T_PCI] = {
.name = "ADS Tech Instant TV DVB-T PCI",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0700,
.gpio2 = 0x0101,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0700,
.gpio2 = 0x0101,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1] = {
.name = "TerraTec Cinergy 1400 DVB-T",
.tuner_type = UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 2,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD] = {
.name = "DViCO FusionHDTV 5 Gold",
.tuner_type = TUNER_LG_TDVS_H06XF, /* TDVS-H062F */
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x87fd,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x87f9,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x87f9,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_AVERMEDIA_ULTRATV_MC_550] = {
.name = "AverMedia UltraTV Media Center PCI 550",
.tuner_type = TUNER_PHILIPS_FM1236_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 0,
.gpio0 = 0x0000cd73,
.audioroute = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 1,
.gpio0 = 0x0000cd73,
.audioroute = 1,
}, {
.type = CX88_VMUX_TELEVISION,
.vmux = 3,
.gpio0 = 0x0000cdb3,
.audioroute = 1,
} },
.radio = {
.type = CX88_RADIO,
.vmux = 2,
.gpio0 = 0x0000cdf3,
.audioroute = 1,
},
.mpeg = CX88_MPEG_BLACKBIRD,
},
[CX88_BOARD_KWORLD_VSTREAM_EXPERT_DVD] = {
/* Alexander Wold <[email protected]> */
.name = "Kworld V-Stream Xpert DVD",
.tuner_type = UNSET,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x03000000,
.gpio1 = 0x01000000,
.gpio2 = 0x02000000,
.gpio3 = 0x00100000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x03000000,
.gpio1 = 0x01000000,
.gpio2 = 0x02000000,
.gpio3 = 0x00100000,
} },
},
[CX88_BOARD_ATI_HDTVWONDER] = {
.name = "ATI HDTV Wonder",
.tuner_type = TUNER_PHILIPS_TUV1236D,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x00000ff7,
.gpio1 = 0x000000ff,
.gpio2 = 0x00000001,
.gpio3 = 0x00000000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x00000ffe,
.gpio1 = 0x000000ff,
.gpio2 = 0x00000001,
.gpio3 = 0x00000000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x00000ffe,
.gpio1 = 0x000000ff,
.gpio2 = 0x00000001,
.gpio3 = 0x00000000,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_WINFAST_DTV1000] = {
.name = "WinFast DTV1000-T",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_AVERTV_303] = {
.name = "AVerTV 303 (M126)",
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x00ff,
.gpio1 = 0xe09f,
.gpio2 = 0x0010,
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x00ff,
.gpio1 = 0xe05f,
.gpio2 = 0x0010,
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x00ff,
.gpio1 = 0xe05f,
.gpio2 = 0x0010,
.gpio3 = 0x0000,
} },
},
[CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1] = {
.name = "Hauppauge Nova-S-Plus DVB-S",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.audio_chip = CX88_AUDIO_WM8775,
.i2sinputcntl = 2,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
/* 2: Line-In */
.audioroute = 2,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
/* 2: Line-In */
.audioroute = 2,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
/* 2: Line-In */
.audioroute = 2,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_HAUPPAUGE_NOVASE2_S1] = {
.name = "Hauppauge Nova-SE2 DVB-S",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_KWORLD_DVBS_100] = {
.name = "KWorld DVB-S 100",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.audio_chip = CX88_AUDIO_WM8775,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
/* 2: Line-In */
.audioroute = 2,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
/* 2: Line-In */
.audioroute = 2,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
/* 2: Line-In */
.audioroute = 2,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_HAUPPAUGE_HVR1100] = {
.name = "Hauppauge WinTV-HVR1100 DVB-T/Hybrid",
.tuner_type = TUNER_PHILIPS_FMD1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
} },
/* fixme: Add radio support */
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_HAUPPAUGE_HVR1100LP] = {
.name = "Hauppauge WinTV-HVR1100 DVB-T/Hybrid (Low Profile)",
.tuner_type = TUNER_PHILIPS_FMD1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
} },
/* fixme: Add radio support */
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_DNTV_LIVE_DVB_T_PRO] = {
.name = "digitalnow DNTV Live! DVB-T Pro",
.tuner_type = TUNER_PHILIPS_FMD1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT | TDA9887_PORT1_ACTIVE |
TDA9887_PORT2_ACTIVE,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0xf80808,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0xf80808,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0xf80808,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0xf80808,
},
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_KWORLD_DVB_T_CX22702] = {
/* Kworld V-stream Xpert DVB-T with Thomson tuner */
/* DTT 7579 Conexant CX22702-19 Conexant CX2388x */
/* Manenti Marco <[email protected]> */
.name = "KWorld/VStream XPert DVB-T with cx22702",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0700,
.gpio2 = 0x0101,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0700,
.gpio2 = 0x0101,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL] = {
.name = "DViCO FusionHDTV DVB-T Dual Digital",
.tuner_type = UNSET, /* No analog tuner */
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x000067df,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x000067df,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_KWORLD_HARDWARE_MPEG_TV_XPERT] = {
.name = "KWorld HardwareMpegTV XPert",
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x3de2,
.gpio2 = 0x00ff,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x3de6,
.audioroute = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x3de6,
.audioroute = 1,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x3de6,
.gpio2 = 0x00ff,
},
.mpeg = CX88_MPEG_BLACKBIRD,
},
[CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID] = {
.name = "DViCO FusionHDTV DVB-T Hybrid",
.tuner_type = TUNER_THOMSON_FE6600,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0000a75f,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0000a75b,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0000a75b,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_PCHDTV_HD5500] = {
.name = "pcHDTV HD5500 HDTV",
.tuner_type = TUNER_LG_TDVS_H06XF, /* TDVS-H064F */
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x87fd,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x87f9,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x87f9,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_KWORLD_MCE200_DELUXE] = {
/*
* FIXME: tested TV input only, disabled composite,
* svideo and radio until they can be tested also.
*/
.name = "Kworld MCE 200 Deluxe",
.tuner_type = TUNER_TENA_9533_DI,
.radio_type = UNSET,
.tda9887_conf = TDA9887_PRESENT,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0000BDE6
} },
.mpeg = CX88_MPEG_BLACKBIRD,
},
[CX88_BOARD_PIXELVIEW_PLAYTV_P7000] = {
/* FIXME: SVideo, Composite and FM inputs are untested */
.name = "PixelView PlayTV P7000",
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT | TDA9887_PORT1_ACTIVE |
TDA9887_PORT2_ACTIVE,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x5da6,
} },
.mpeg = CX88_MPEG_BLACKBIRD,
},
[CX88_BOARD_NPGTECH_REALTV_TOP10FM] = {
.name = "NPG Tech Real TV FM Top 10",
.tuner_type = TUNER_TNF_5335MF, /* Actually a TNF9535 */
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0788,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x078b,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x078b,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x074a,
},
},
[CX88_BOARD_WINFAST_DTV2000H] = {
.name = "WinFast DTV2000 H",
.tuner_type = TUNER_PHILIPS_FMD1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x00017304,
.gpio1 = 0x00008203,
.gpio2 = 0x00017304,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0001d701,
.gpio1 = 0x0000b207,
.gpio2 = 0x0001d701,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_COMPOSITE2,
.vmux = 2,
.gpio0 = 0x0001d503,
.gpio1 = 0x0000b207,
.gpio2 = 0x0001d503,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 3,
.gpio0 = 0x0001d701,
.gpio1 = 0x0000b207,
.gpio2 = 0x0001d701,
.gpio3 = 0x02000000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x00015702,
.gpio1 = 0x0000f207,
.gpio2 = 0x00015702,
.gpio3 = 0x02000000,
},
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_WINFAST_DTV2000H_J] = {
.name = "WinFast DTV2000 H rev. J",
.tuner_type = TUNER_PHILIPS_FMD1216MEX_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x00017300,
.gpio1 = 0x00008207,
.gpio2 = 0x00000000,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x00018300,
.gpio1 = 0x0000f207,
.gpio2 = 0x00017304,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x00018301,
.gpio1 = 0x0000f207,
.gpio2 = 0x00017304,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x00018301,
.gpio1 = 0x0000f207,
.gpio2 = 0x00017304,
.gpio3 = 0x02000000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x00015702,
.gpio1 = 0x0000f207,
.gpio2 = 0x00015702,
.gpio3 = 0x02000000,
},
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_GENIATECH_DVBS] = {
.name = "Geniatech DVB-S",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_HAUPPAUGE_HVR3000] = {
.name = "Hauppauge WinTV-HVR3000 TriMode Analog/DVB-S/DVB-T",
.tuner_type = TUNER_PHILIPS_FMD1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.audio_chip = CX88_AUDIO_WM8775,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x84bf,
/* 1: TV Audio / FM Mono */
.audioroute = 1,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x84bf,
/* 2: Line-In */
.audioroute = 2,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x84bf,
/* 2: Line-In */
.audioroute = 2,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x84bf,
/* 4: FM Stereo (untested) */
.audioroute = 8,
},
.mpeg = CX88_MPEG_DVB,
.num_frontends = 2,
},
[CX88_BOARD_NORWOOD_MICRO] = {
.name = "Norwood Micro TV Tuner",
.tuner_type = TUNER_TNF_5335MF,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0709,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x070b,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x070b,
} },
},
[CX88_BOARD_TE_DTV_250_OEM_SWANN] = {
.name = "Shenzhen Tungsten Ages Tech TE-DTV-250 / Swann OEM",
.tuner_type = TUNER_LG_PAL_NEW_TAPC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x003fffff,
.gpio1 = 0x00e00000,
.gpio2 = 0x003fffff,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x003fffff,
.gpio1 = 0x00e00000,
.gpio2 = 0x003fffff,
.gpio3 = 0x02000000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x003fffff,
.gpio1 = 0x00e00000,
.gpio2 = 0x003fffff,
.gpio3 = 0x02000000,
} },
},
[CX88_BOARD_HAUPPAUGE_HVR1300] = {
.name = "Hauppauge WinTV-HVR1300 DVB-T/Hybrid MPEG Encoder",
.tuner_type = TUNER_PHILIPS_FMD1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.audio_chip = CX88_AUDIO_WM8775,
/*
* gpio0 as reported by Mike Crash <mike AT mikecrash.com>
*/
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0xef88,
/* 1: TV Audio / FM Mono */
.audioroute = 1,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0xef88,
/* 2: Line-In */
.audioroute = 2,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0xef88,
/* 2: Line-In */
.audioroute = 2,
} },
.mpeg = CX88_MPEG_DVB | CX88_MPEG_BLACKBIRD,
.radio = {
.type = CX88_RADIO,
.gpio0 = 0xef88,
/* 4: FM Stereo (untested) */
.audioroute = 8,
},
},
[CX88_BOARD_SAMSUNG_SMT_7020] = {
.name = "Samsung SMT 7020 DVB-S",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_ADSTECH_PTV_390] = {
.name = "ADS Tech Instant Video PCI",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DEBUG,
.vmux = 3,
.gpio0 = 0x04ff,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x07fa,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x07fa,
} },
},
[CX88_BOARD_PINNACLE_PCTV_HD_800i] = {
.name = "Pinnacle PCTV HD 800i",
.tuner_type = TUNER_XC5000,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x04fb,
.gpio1 = 0x10ff,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x04fb,
.gpio1 = 0x10ef,
.audioroute = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x04fb,
.gpio1 = 0x10ef,
.audioroute = 1,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO] = {
.name = "DViCO FusionHDTV 5 PCI nano",
/* xc3008 tuner, digital only for now */
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x000027df, /* Unconfirmed */
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x000027df, /* Unconfirmed */
.audioroute = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x000027df, /* Unconfirmed */
.audioroute = 1,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_PINNACLE_HYBRID_PCTV] = {
.name = "Pinnacle Hybrid PCTV",
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61,
.radio_type = UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x004ff,
.gpio1 = 0x010ff,
.gpio2 = 0x00001,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x004fb,
.gpio1 = 0x010ef,
.audioroute = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x004fb,
.gpio1 = 0x010ef,
.audioroute = 1,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x004ff,
.gpio1 = 0x010ff,
.gpio2 = 0x0ff,
},
.mpeg = CX88_MPEG_DVB,
},
/* Terry Wu <[email protected]> */
/* TV Audio : set GPIO 2, 18, 19 value to 0, 1, 0 */
/* FM Audio : set GPIO 2, 18, 19 value to 0, 0, 0 */
/* Line-in Audio : set GPIO 2, 18, 19 value to 0, 1, 1 */
/* Mute Audio : set GPIO 2 value to 1 */
[CX88_BOARD_WINFAST_TV2000_XP_GLOBAL] = {
.name = "Leadtek TV2000 XP Global",
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61,
.radio_type = UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x0000,
.gpio2 = 0x0C04, /* pin 18 = 1, pin 19 = 0 */
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x0000,
.gpio2 = 0x0C0C, /* pin 18 = 1, pin 19 = 1 */
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x0000,
.gpio2 = 0x0C0C, /* pin 18 = 1, pin 19 = 1 */
.gpio3 = 0x0000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x0000,
.gpio2 = 0x0C00, /* pin 18 = 0, pin 19 = 0 */
.gpio3 = 0x0000,
},
},
[CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F36] = {
.name = "Leadtek TV2000 XP Global (SC4100)",
.tuner_type = TUNER_XC4000,
.tuner_addr = 0x61,
.radio_type = UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x0000,
.gpio2 = 0x0C04, /* pin 18 = 1, pin 19 = 0 */
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x0000,
.gpio2 = 0x0C0C, /* pin 18 = 1, pin 19 = 1 */
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x0000,
.gpio2 = 0x0C0C, /* pin 18 = 1, pin 19 = 1 */
.gpio3 = 0x0000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x0000,
.gpio2 = 0x0C00, /* pin 18 = 0, pin 19 = 0 */
.gpio3 = 0x0000,
},
},
[CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F43] = {
.name = "Leadtek TV2000 XP Global (XC4100)",
.tuner_type = TUNER_XC4000,
.tuner_addr = 0x61,
.radio_type = UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6040, /* pin 14 = 1, pin 13 = 0 */
.gpio2 = 0x0000,
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6060, /* pin 14 = 1, pin 13 = 1 */
.gpio2 = 0x0000,
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6060, /* pin 14 = 1, pin 13 = 1 */
.gpio2 = 0x0000,
.gpio3 = 0x0000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6000, /* pin 14 = 1, pin 13 = 0 */
.gpio2 = 0x0000,
.gpio3 = 0x0000,
},
},
[CX88_BOARD_POWERCOLOR_REAL_ANGEL] = {
/* Long names may confuse LIRC. */
.name = "PowerColor RA330",
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61,
.input = { {
/*
* Due to the way the cx88 driver is written,
* there is no way to deactivate audio pass-
* through without this entry. Furthermore, if
* the TV mux entry is first, you get audio
* from the tuner on boot for a little while.
*/
.type = CX88_VMUX_DEBUG,
.vmux = 3,
.gpio0 = 0x00ff,
.gpio1 = 0xf39d,
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x00ff,
.gpio1 = 0xf35d,
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x00ff,
.gpio1 = 0xf37d,
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x000ff,
.gpio1 = 0x0f37d,
.gpio3 = 0x00000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x000ff,
.gpio1 = 0x0f35d,
.gpio3 = 0x00000,
},
},
[CX88_BOARD_GENIATECH_X8000_MT] = {
/* Also PowerColor Real Angel 330 and Geniatech X800 OEM */
.name = "Geniatech X8000-MT DVBT",
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x00000000,
.gpio1 = 0x00e3e341,
.gpio2 = 0x00000000,
.gpio3 = 0x00000000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x00000000,
.gpio1 = 0x00e3e361,
.gpio2 = 0x00000000,
.gpio3 = 0x00000000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x00000000,
.gpio1 = 0x00e3e361,
.gpio2 = 0x00000000,
.gpio3 = 0x00000000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x00000000,
.gpio1 = 0x00e3e341,
.gpio2 = 0x00000000,
.gpio3 = 0x00000000,
},
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_NOTONLYTV_LV3H] = {
.name = "NotOnlyTV LV3H",
.tuner_type = TUNER_XC2028,
.radio_type = UNSET,
.tuner_addr = 0x61,
.radio_addr = ADDR_UNSET,
/* if gpio1:bit9 is enabled, DVB-T won't work */
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0000,
.gpio1 = 0xa141,
.gpio2 = 0x0000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0000,
.gpio1 = 0xa161,
.gpio2 = 0x0000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0000,
.gpio1 = 0xa161,
.gpio2 = 0x0000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x0000,
.gpio1 = 0xa141,
.gpio2 = 0x0000,
},
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO] = {
.name = "DViCO FusionHDTV DVB-T PRO",
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61,
.radio_type = UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x000067df,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x000067df,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD] = {
.name = "DViCO FusionHDTV 7 Gold",
.tuner_type = TUNER_XC5000,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x10df,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x16d9,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x16d9,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_PROLINK_PV_8000GT] = {
.name = "Prolink Pixelview MPEG 8000GT",
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0ff,
.gpio2 = 0x0cfb,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio2 = 0x0cfb,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio2 = 0x0cfb,
} },
.radio = {
.type = CX88_RADIO,
.gpio2 = 0x0cfb,
},
},
[CX88_BOARD_PROLINK_PV_GLOBAL_XTREME] = {
.name = "Prolink Pixelview Global Extreme",
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x04fb,
.gpio1 = 0x04080,
.gpio2 = 0x0cf7,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x04fb,
.gpio1 = 0x04080,
.gpio2 = 0x0cfb,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x04fb,
.gpio1 = 0x04080,
.gpio2 = 0x0cfb,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x04ff,
.gpio1 = 0x04080,
.gpio2 = 0x0cf7,
},
},
/*
* Both radio, analog and ATSC work with this board.
* However, for analog to work, s5h1409 gate should be open,
* otherwise, tuner-xc3028 won't be detected.
* A proper fix require using the newer i2c methods to add
* tuner-xc3028 without doing an i2c probe.
*/
[CX88_BOARD_KWORLD_ATSC_120] = {
.name = "Kworld PlusTV HD PCI 120 (ATSC 120)",
.tuner_type = TUNER_XC2028,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x000000ff,
.gpio1 = 0x0000f35d,
.gpio2 = 0x00000000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x000000ff,
.gpio1 = 0x0000f37e,
.gpio2 = 0x00000000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x000000ff,
.gpio1 = 0x0000f37e,
.gpio2 = 0x00000000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x000000ff,
.gpio1 = 0x0000f35d,
.gpio2 = 0x00000000,
},
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_HAUPPAUGE_HVR4000] = {
.name = "Hauppauge WinTV-HVR4000 DVB-S/S2/T/Hybrid",
.tuner_type = TUNER_PHILIPS_FMD1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.audio_chip = CX88_AUDIO_WM8775,
/*
* GPIO0 (WINTV2000)
*
* Analogue SAT DVB-T
* Antenna 0xc4bf 0xc4bb
* Composite 0xc4bf 0xc4bb
* S-Video 0xc4bf 0xc4bb
* Composite1 0xc4ff 0xc4fb
* S-Video1 0xc4ff 0xc4fb
*
* BIT VALUE FUNCTION GP{x}_IO
* 0 1 I:?
* 1 1 I:?
* 2 1 O:MPEG PORT 0=DVB-T 1=DVB-S
* 3 1 I:?
* 4 1 I:?
* 5 1 I:?
* 6 0 O:INPUT SELECTOR 0=INTERNAL 1=EXPANSION
* 7 1 O:DVB-T DEMOD RESET LOW
*
* BIT VALUE FUNCTION GP{x}_OE
* 8 0 I
* 9 0 I
* a 1 O
* b 0 I
* c 0 I
* d 0 I
* e 1 O
* f 1 O
*
* WM8775 ADC
*
* 1: TV Audio / FM Mono
* 2: Line-In
* 3: Line-In Expansion
* 4: FM Stereo
*/
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0xc4bf,
/* 1: TV Audio / FM Mono */
.audioroute = 1,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0xc4bf,
/* 2: Line-In */
.audioroute = 2,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0xc4bf,
/* 2: Line-In */
.audioroute = 2,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0xc4bf,
/* 4: FM Stereo */
.audioroute = 8,
},
.mpeg = CX88_MPEG_DVB,
.num_frontends = 2,
},
[CX88_BOARD_HAUPPAUGE_HVR4000LITE] = {
.name = "Hauppauge WinTV-HVR4000(Lite) DVB-S/S2",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_TEVII_S420] = {
.name = "TeVii S420 DVB-S",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_TEVII_S460] = {
.name = "TeVii S460 DVB-S/S2",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_TEVII_S464] = {
.name = "TeVii S464 DVB-S/S2",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_OMICOM_SS4_PCI] = {
.name = "Omicom SS4 DVB-S/S2 PCI",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_TBS_8910] = {
.name = "TBS 8910 DVB-S",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_TBS_8920] = {
.name = "TBS 8920 DVB-S/S2",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
.gpio0 = 0x8080,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_PROF_6200] = {
.name = "Prof 6200 DVB-S",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_PROF_7300] = {
.name = "PROF 7300 DVB-S/S2",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_SATTRADE_ST4200] = {
.name = "SATTRADE ST4200 DVB-S/S2",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII] = {
.name = "Terratec Cinergy HT PCI MKII",
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61,
.radio_type = UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x004ff,
.gpio1 = 0x010ff,
.gpio2 = 0x00001,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x004fb,
.gpio1 = 0x010ef,
.audioroute = 1,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x004fb,
.gpio1 = 0x010ef,
.audioroute = 1,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x004ff,
.gpio1 = 0x010ff,
.gpio2 = 0x0ff,
},
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_HAUPPAUGE_IRONLY] = {
.name = "Hauppauge WinTV-IR Only",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
},
[CX88_BOARD_WINFAST_DTV1800H] = {
.name = "Leadtek WinFast DTV1800 Hybrid",
.tuner_type = TUNER_XC2028,
.radio_type = UNSET,
.tuner_addr = 0x61,
.radio_addr = ADDR_UNSET,
/*
* GPIO setting
*
* 2: mute (0=off,1=on)
* 12: tuner reset pin
* 13: audio source (0=tuner audio,1=line in)
* 14: FM (0=on,1=off ???)
*/
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6040, /* pin 13 = 0, pin 14 = 1 */
.gpio2 = 0x0000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6060, /* pin 13 = 1, pin 14 = 1 */
.gpio2 = 0x0000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6060, /* pin 13 = 1, pin 14 = 1 */
.gpio2 = 0x0000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6000, /* pin 13 = 0, pin 14 = 0 */
.gpio2 = 0x0000,
},
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_WINFAST_DTV1800H_XC4000] = {
.name = "Leadtek WinFast DTV1800 H (XC4000)",
.tuner_type = TUNER_XC4000,
.radio_type = UNSET,
.tuner_addr = 0x61,
.radio_addr = ADDR_UNSET,
/*
* GPIO setting
*
* 2: mute (0=off,1=on)
* 12: tuner reset pin
* 13: audio source (0=tuner audio,1=line in)
* 14: FM (0=on,1=off ???)
*/
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6040, /* pin 13 = 0, pin 14 = 1 */
.gpio2 = 0x0000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6060, /* pin 13 = 1, pin 14 = 1 */
.gpio2 = 0x0000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6060, /* pin 13 = 1, pin 14 = 1 */
.gpio2 = 0x0000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x0400, /* pin 2 = 0 */
.gpio1 = 0x6000, /* pin 13 = 0, pin 14 = 0 */
.gpio2 = 0x0000,
},
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_WINFAST_DTV2000H_PLUS] = {
.name = "Leadtek WinFast DTV2000 H PLUS",
.tuner_type = TUNER_XC4000,
.radio_type = UNSET,
.tuner_addr = 0x61,
.radio_addr = ADDR_UNSET,
/*
* GPIO
* 2: 1: mute audio
* 12: 0: reset XC4000
* 13: 1: audio input is line in (0: tuner)
* 14: 0: FM radio
* 16: 0: RF input is cable
*/
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0403,
.gpio1 = 0xF0D7,
.gpio2 = 0x0101,
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_CABLE,
.vmux = 0,
.gpio0 = 0x0403,
.gpio1 = 0xF0D7,
.gpio2 = 0x0100,
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio0 = 0x0403, /* was 0x0407 */
.gpio1 = 0xF0F7,
.gpio2 = 0x0101,
.gpio3 = 0x0000,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio0 = 0x0403, /* was 0x0407 */
.gpio1 = 0xF0F7,
.gpio2 = 0x0101,
.gpio3 = 0x0000,
} },
.radio = {
.type = CX88_RADIO,
.gpio0 = 0x0403,
.gpio1 = 0xF097,
.gpio2 = 0x0100,
.gpio3 = 0x0000,
},
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_PROF_7301] = {
.name = "Prof 7301 DVB-S/S2",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
[CX88_BOARD_TWINHAN_VP1027_DVBS] = {
.name = "Twinhan VP-1027 DVB-S",
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.input = { {
.type = CX88_VMUX_DVB,
.vmux = 0,
} },
.mpeg = CX88_MPEG_DVB,
},
};
/* ------------------------------------------------------------------ */
/* PCI subsystem IDs */
static const struct cx88_subid cx88_subids[] = {
{
.subvendor = 0x0070,
.subdevice = 0x3400,
.card = CX88_BOARD_HAUPPAUGE,
}, {
.subvendor = 0x0070,
.subdevice = 0x3401,
.card = CX88_BOARD_HAUPPAUGE,
}, {
.subvendor = 0x14c7,
.subdevice = 0x0106,
.card = CX88_BOARD_GDI,
}, {
.subvendor = 0x14c7,
.subdevice = 0x0107, /* with mpeg encoder */
.card = CX88_BOARD_GDI,
}, {
.subvendor = PCI_VENDOR_ID_ATI,
.subdevice = 0x00f8,
.card = CX88_BOARD_ATI_WONDER_PRO,
}, {
.subvendor = PCI_VENDOR_ID_ATI,
.subdevice = 0x00f9,
.card = CX88_BOARD_ATI_WONDER_PRO,
}, {
.subvendor = 0x107d,
.subdevice = 0x6611,
.card = CX88_BOARD_WINFAST2000XP_EXPERT,
}, {
.subvendor = 0x107d,
.subdevice = 0x6613, /* NTSC */
.card = CX88_BOARD_WINFAST2000XP_EXPERT,
}, {
.subvendor = 0x107d,
.subdevice = 0x6620,
.card = CX88_BOARD_WINFAST_DV2000,
}, {
.subvendor = 0x107d,
.subdevice = 0x663b,
.card = CX88_BOARD_LEADTEK_PVR2000,
}, {
.subvendor = 0x107d,
.subdevice = 0x663c,
.card = CX88_BOARD_LEADTEK_PVR2000,
}, {
.subvendor = 0x1461,
.subdevice = 0x000b,
.card = CX88_BOARD_AVERTV_STUDIO_303,
}, {
.subvendor = 0x1462,
.subdevice = 0x8606,
.card = CX88_BOARD_MSI_TVANYWHERE_MASTER,
}, {
.subvendor = 0x10fc,
.subdevice = 0xd003,
.card = CX88_BOARD_IODATA_GVVCP3PCI,
}, {
.subvendor = 0x1043,
.subdevice = 0x4823, /* with mpeg encoder */
.card = CX88_BOARD_ASUS_PVR_416,
}, {
.subvendor = 0x17de,
.subdevice = 0x08a6,
.card = CX88_BOARD_KWORLD_DVB_T,
}, {
.subvendor = 0x18ac,
.subdevice = 0xd810,
.card = CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q,
}, {
.subvendor = 0x18ac,
.subdevice = 0xd820,
.card = CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T,
}, {
.subvendor = 0x18ac,
.subdevice = 0xdb00,
.card = CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1,
}, {
.subvendor = 0x0070,
.subdevice = 0x9002,
.card = CX88_BOARD_HAUPPAUGE_DVB_T1,
}, {
.subvendor = 0x14f1,
.subdevice = 0x0187,
.card = CX88_BOARD_CONEXANT_DVB_T1,
}, {
.subvendor = 0x1540,
.subdevice = 0x2580,
.card = CX88_BOARD_PROVIDEO_PV259,
}, {
.subvendor = 0x18ac,
.subdevice = 0xdb10,
.card = CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS,
}, {
.subvendor = 0x1554,
.subdevice = 0x4811,
.card = CX88_BOARD_PIXELVIEW,
}, {
.subvendor = 0x7063,
.subdevice = 0x3000, /* HD-3000 card */
.card = CX88_BOARD_PCHDTV_HD3000,
}, {
.subvendor = 0x17de,
.subdevice = 0xa8a6,
.card = CX88_BOARD_DNTV_LIVE_DVB_T,
}, {
.subvendor = 0x0070,
.subdevice = 0x2801,
.card = CX88_BOARD_HAUPPAUGE_ROSLYN,
}, {
.subvendor = 0x14f1,
.subdevice = 0x0342,
.card = CX88_BOARD_DIGITALLOGIC_MEC,
}, {
.subvendor = 0x10fc,
.subdevice = 0xd035,
.card = CX88_BOARD_IODATA_GVBCTV7E,
}, {
.subvendor = 0x1421,
.subdevice = 0x0334,
.card = CX88_BOARD_ADSTECH_DVB_T_PCI,
}, {
.subvendor = 0x153b,
.subdevice = 0x1166,
.card = CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1,
}, {
.subvendor = 0x18ac,
.subdevice = 0xd500,
.card = CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD,
}, {
.subvendor = 0x1461,
.subdevice = 0x8011,
.card = CX88_BOARD_AVERMEDIA_ULTRATV_MC_550,
}, {
.subvendor = PCI_VENDOR_ID_ATI,
.subdevice = 0xa101,
.card = CX88_BOARD_ATI_HDTVWONDER,
}, {
.subvendor = 0x107d,
.subdevice = 0x665f,
.card = CX88_BOARD_WINFAST_DTV1000,
}, {
.subvendor = 0x1461,
.subdevice = 0x000a,
.card = CX88_BOARD_AVERTV_303,
}, {
.subvendor = 0x0070,
.subdevice = 0x9200,
.card = CX88_BOARD_HAUPPAUGE_NOVASE2_S1,
}, {
.subvendor = 0x0070,
.subdevice = 0x9201,
.card = CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1,
}, {
.subvendor = 0x0070,
.subdevice = 0x9202,
.card = CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1,
}, {
.subvendor = 0x17de,
.subdevice = 0x08b2,
.card = CX88_BOARD_KWORLD_DVBS_100,
}, {
.subvendor = 0x0070,
.subdevice = 0x9400,
.card = CX88_BOARD_HAUPPAUGE_HVR1100,
}, {
.subvendor = 0x0070,
.subdevice = 0x9402,
.card = CX88_BOARD_HAUPPAUGE_HVR1100,
}, {
.subvendor = 0x0070,
.subdevice = 0x9800,
.card = CX88_BOARD_HAUPPAUGE_HVR1100LP,
}, {
.subvendor = 0x0070,
.subdevice = 0x9802,
.card = CX88_BOARD_HAUPPAUGE_HVR1100LP,
}, {
.subvendor = 0x0070,
.subdevice = 0x9001,
.card = CX88_BOARD_HAUPPAUGE_DVB_T1,
}, {
.subvendor = 0x1822,
.subdevice = 0x0025,
.card = CX88_BOARD_DNTV_LIVE_DVB_T_PRO,
}, {
.subvendor = 0x17de,
.subdevice = 0x08a1,
.card = CX88_BOARD_KWORLD_DVB_T_CX22702,
}, {
.subvendor = 0x18ac,
.subdevice = 0xdb50,
.card = CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL,
}, {
.subvendor = 0x18ac,
.subdevice = 0xdb54,
.card = CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL,
/* Re-branded DViCO: DigitalNow DVB-T Dual */
}, {
.subvendor = 0x18ac,
.subdevice = 0xdb11,
.card = CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS,
/* Re-branded DViCO: UltraView DVB-T Plus */
}, {
.subvendor = 0x18ac,
.subdevice = 0xdb30,
.card = CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO,
}, {
.subvendor = 0x17de,
.subdevice = 0x0840,
.card = CX88_BOARD_KWORLD_HARDWARE_MPEG_TV_XPERT,
}, {
.subvendor = 0x1421,
.subdevice = 0x0305,
.card = CX88_BOARD_KWORLD_HARDWARE_MPEG_TV_XPERT,
}, {
.subvendor = 0x18ac,
.subdevice = 0xdb40,
.card = CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID,
}, {
.subvendor = 0x18ac,
.subdevice = 0xdb44,
.card = CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID,
}, {
.subvendor = 0x7063,
.subdevice = 0x5500,
.card = CX88_BOARD_PCHDTV_HD5500,
}, {
.subvendor = 0x17de,
.subdevice = 0x0841,
.card = CX88_BOARD_KWORLD_MCE200_DELUXE,
}, {
.subvendor = 0x1822,
.subdevice = 0x0019,
.card = CX88_BOARD_DNTV_LIVE_DVB_T_PRO,
}, {
.subvendor = 0x1554,
.subdevice = 0x4813,
.card = CX88_BOARD_PIXELVIEW_PLAYTV_P7000,
}, {
.subvendor = 0x14f1,
.subdevice = 0x0842,
.card = CX88_BOARD_NPGTECH_REALTV_TOP10FM,
}, {
.subvendor = 0x107d,
.subdevice = 0x665e,
.card = CX88_BOARD_WINFAST_DTV2000H,
}, {
.subvendor = 0x107d,
.subdevice = 0x6f2b,
.card = CX88_BOARD_WINFAST_DTV2000H_J,
}, {
.subvendor = 0x18ac,
.subdevice = 0xd800, /* FusionHDTV 3 Gold (original revision) */
.card = CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q,
}, {
.subvendor = 0x14f1,
.subdevice = 0x0084,
.card = CX88_BOARD_GENIATECH_DVBS,
}, {
.subvendor = 0x0070,
.subdevice = 0x1404,
.card = CX88_BOARD_HAUPPAUGE_HVR3000,
}, {
.subvendor = 0x18ac,
.subdevice = 0xdc00,
.card = CX88_BOARD_SAMSUNG_SMT_7020,
}, {
.subvendor = 0x18ac,
.subdevice = 0xdccd,
.card = CX88_BOARD_SAMSUNG_SMT_7020,
}, {
.subvendor = 0x1461,
.subdevice = 0xc111, /* AverMedia M150-D */
/* This board is known to work with the ASUS PVR416 config */
.card = CX88_BOARD_ASUS_PVR_416,
}, {
.subvendor = 0xc180,
.subdevice = 0xc980,
.card = CX88_BOARD_TE_DTV_250_OEM_SWANN,
}, {
.subvendor = 0x0070,
.subdevice = 0x9600,
.card = CX88_BOARD_HAUPPAUGE_HVR1300,
}, {
.subvendor = 0x0070,
.subdevice = 0x9601,
.card = CX88_BOARD_HAUPPAUGE_HVR1300,
}, {
.subvendor = 0x0070,
.subdevice = 0x9602,
.card = CX88_BOARD_HAUPPAUGE_HVR1300,
}, {
.subvendor = 0x107d,
.subdevice = 0x6632,
.card = CX88_BOARD_LEADTEK_PVR2000,
}, {
.subvendor = 0x12ab,
.subdevice = 0x2300, /* Club3D Zap TV2100 */
.card = CX88_BOARD_KWORLD_DVB_T_CX22702,
}, {
.subvendor = 0x0070,
.subdevice = 0x9000,
.card = CX88_BOARD_HAUPPAUGE_DVB_T1,
}, {
.subvendor = 0x0070,
.subdevice = 0x1400,
.card = CX88_BOARD_HAUPPAUGE_HVR3000,
}, {
.subvendor = 0x0070,
.subdevice = 0x1401,
.card = CX88_BOARD_HAUPPAUGE_HVR3000,
}, {
.subvendor = 0x0070,
.subdevice = 0x1402,
.card = CX88_BOARD_HAUPPAUGE_HVR3000,
}, {
.subvendor = 0x1421,
.subdevice = 0x0341, /* ADS Tech InstantTV DVB-S */
.card = CX88_BOARD_KWORLD_DVBS_100,
}, {
.subvendor = 0x1421,
.subdevice = 0x0390,
.card = CX88_BOARD_ADSTECH_PTV_390,
}, {
.subvendor = 0x11bd,
.subdevice = 0x0051,
.card = CX88_BOARD_PINNACLE_PCTV_HD_800i,
}, {
.subvendor = 0x18ac,
.subdevice = 0xd530,
.card = CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO,
}, {
.subvendor = 0x12ab,
.subdevice = 0x1788,
.card = CX88_BOARD_PINNACLE_HYBRID_PCTV,
}, {
.subvendor = 0x14f1,
.subdevice = 0xea3d,
.card = CX88_BOARD_POWERCOLOR_REAL_ANGEL,
}, {
.subvendor = 0x107d,
.subdevice = 0x6f18,
.card = CX88_BOARD_WINFAST_TV2000_XP_GLOBAL,
}, {
/* Also NotOnlyTV LV3H (version 1.11 is silkscreened on the board) */
.subvendor = 0x14f1,
.subdevice = 0x8852,
.card = CX88_BOARD_GENIATECH_X8000_MT,
}, {
.subvendor = 0x18ac,
.subdevice = 0xd610,
.card = CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD,
}, {
.subvendor = 0x1554,
.subdevice = 0x4935,
.card = CX88_BOARD_PROLINK_PV_8000GT,
}, {
.subvendor = 0x1554,
.subdevice = 0x4976,
.card = CX88_BOARD_PROLINK_PV_GLOBAL_XTREME,
}, {
.subvendor = 0x17de,
.subdevice = 0x08c1,
.card = CX88_BOARD_KWORLD_ATSC_120,
}, {
.subvendor = 0x0070,
.subdevice = 0x6900,
.card = CX88_BOARD_HAUPPAUGE_HVR4000,
}, {
.subvendor = 0x0070,
.subdevice = 0x6904,
.card = CX88_BOARD_HAUPPAUGE_HVR4000,
}, {
.subvendor = 0x0070,
.subdevice = 0x6902,
.card = CX88_BOARD_HAUPPAUGE_HVR4000,
}, {
.subvendor = 0x0070,
.subdevice = 0x6905,
.card = CX88_BOARD_HAUPPAUGE_HVR4000LITE,
}, {
.subvendor = 0x0070,
.subdevice = 0x6906,
.card = CX88_BOARD_HAUPPAUGE_HVR4000LITE,
}, {
.subvendor = 0xd420,
.subdevice = 0x9022,
.card = CX88_BOARD_TEVII_S420,
}, {
.subvendor = 0xd460,
.subdevice = 0x9022,
.card = CX88_BOARD_TEVII_S460,
}, {
.subvendor = 0xd464,
.subdevice = 0x9022,
.card = CX88_BOARD_TEVII_S464,
}, {
.subvendor = 0xA044,
.subdevice = 0x2011,
.card = CX88_BOARD_OMICOM_SS4_PCI,
}, {
.subvendor = 0x8910,
.subdevice = 0x8888,
.card = CX88_BOARD_TBS_8910,
}, {
.subvendor = 0x8920,
.subdevice = 0x8888,
.card = CX88_BOARD_TBS_8920,
}, {
.subvendor = 0xb022,
.subdevice = 0x3022,
.card = CX88_BOARD_PROF_6200,
}, {
.subvendor = 0xB033,
.subdevice = 0x3033,
.card = CX88_BOARD_PROF_7300,
}, {
.subvendor = 0xb200,
.subdevice = 0x4200,
.card = CX88_BOARD_SATTRADE_ST4200,
}, {
.subvendor = 0x153b,
.subdevice = 0x1177,
.card = CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII,
}, {
.subvendor = 0x0070,
.subdevice = 0x9290,
.card = CX88_BOARD_HAUPPAUGE_IRONLY,
}, {
.subvendor = 0x107d,
.subdevice = 0x6654,
.card = CX88_BOARD_WINFAST_DTV1800H,
}, {
/* WinFast DTV1800 H with XC4000 tuner */
.subvendor = 0x107d,
.subdevice = 0x6f38,
.card = CX88_BOARD_WINFAST_DTV1800H_XC4000,
}, {
.subvendor = 0x107d,
.subdevice = 0x6f42,
.card = CX88_BOARD_WINFAST_DTV2000H_PLUS,
}, {
/* PVR2000 PAL Model [107d:6630] */
.subvendor = 0x107d,
.subdevice = 0x6630,
.card = CX88_BOARD_LEADTEK_PVR2000,
}, {
/* PVR2000 PAL Model [107d:6638] */
.subvendor = 0x107d,
.subdevice = 0x6638,
.card = CX88_BOARD_LEADTEK_PVR2000,
}, {
/* PVR2000 NTSC Model [107d:6631] */
.subvendor = 0x107d,
.subdevice = 0x6631,
.card = CX88_BOARD_LEADTEK_PVR2000,
}, {
/* PVR2000 NTSC Model [107d:6637] */
.subvendor = 0x107d,
.subdevice = 0x6637,
.card = CX88_BOARD_LEADTEK_PVR2000,
}, {
/* PVR2000 NTSC Model [107d:663d] */
.subvendor = 0x107d,
.subdevice = 0x663d,
.card = CX88_BOARD_LEADTEK_PVR2000,
}, {
/* DV2000 NTSC Model [107d:6621] */
.subvendor = 0x107d,
.subdevice = 0x6621,
.card = CX88_BOARD_WINFAST_DV2000,
}, {
/* TV2000 XP Global [107d:6618] */
.subvendor = 0x107d,
.subdevice = 0x6618,
.card = CX88_BOARD_WINFAST_TV2000_XP_GLOBAL,
}, {
/* TV2000 XP Global [107d:6618] */
.subvendor = 0x107d,
.subdevice = 0x6619,
.card = CX88_BOARD_WINFAST_TV2000_XP_GLOBAL,
}, {
/* WinFast TV2000 XP Global with XC4000 tuner */
.subvendor = 0x107d,
.subdevice = 0x6f36,
.card = CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F36,
}, {
/* WinFast TV2000 XP Global with XC4000 tuner and different GPIOs */
.subvendor = 0x107d,
.subdevice = 0x6f43,
.card = CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F43,
}, {
.subvendor = 0xb034,
.subdevice = 0x3034,
.card = CX88_BOARD_PROF_7301,
}, {
.subvendor = 0x1822,
.subdevice = 0x0023,
.card = CX88_BOARD_TWINHAN_VP1027_DVBS,
},
};
/*
* some leadtek specific stuff
*/
static void leadtek_eeprom(struct cx88_core *core, u8 *eeprom_data)
{
if (eeprom_data[4] != 0x7d ||
eeprom_data[5] != 0x10 ||
eeprom_data[7] != 0x66) {
pr_warn("Leadtek eeprom invalid.\n");
return;
}
/* Terry Wu <[email protected]> */
switch (eeprom_data[6]) {
case 0x13: /* SSID 6613 for TV2000 XP Expert NTSC Model */
case 0x21: /* SSID 6621 for DV2000 NTSC Model */
case 0x31: /* SSID 6631 for PVR2000 NTSC Model */
case 0x37: /* SSID 6637 for PVR2000 NTSC Model */
case 0x3d: /* SSID 6637 for PVR2000 NTSC Model */
core->board.tuner_type = TUNER_PHILIPS_FM1236_MK3;
break;
default:
core->board.tuner_type = TUNER_PHILIPS_FM1216ME_MK3;
break;
}
pr_info("Leadtek Winfast 2000XP Expert config: tuner=%d, eeprom[0]=0x%02x\n",
core->board.tuner_type, eeprom_data[0]);
}
static void hauppauge_eeprom(struct cx88_core *core, u8 *eeprom_data)
{
struct tveeprom tv;
tveeprom_hauppauge_analog(&tv, eeprom_data);
core->board.tuner_type = tv.tuner_type;
core->tuner_formats = tv.tuner_formats;
core->board.radio.type = tv.has_radio ? CX88_RADIO : 0;
core->model = tv.model;
/* Make sure we support the board model */
switch (tv.model) {
case 14009: /* WinTV-HVR3000 (Retail, IR, b/panel video, 3.5mm audio in) */
case 14019: /* WinTV-HVR3000 (Retail, IR Blaster, b/panel video, 3.5mm audio in) */
case 14029: /* WinTV-HVR3000 (Retail, IR, b/panel video, 3.5mm audio in - 880 bridge) */
case 14109: /* WinTV-HVR3000 (Retail, IR, b/panel video, 3.5mm audio in - low profile) */
case 14129: /* WinTV-HVR3000 (Retail, IR, b/panel video, 3.5mm audio in - 880 bridge - LP) */
case 14559: /* WinTV-HVR3000 (OEM, no IR, b/panel video, 3.5mm audio in) */
case 14569: /* WinTV-HVR3000 (OEM, no IR, no back panel video) */
case 14659: /* WinTV-HVR3000 (OEM, no IR, b/panel video, RCA audio in - Low profile) */
case 14669: /* WinTV-HVR3000 (OEM, no IR, no b/panel video - Low profile) */
case 28552: /* WinTV-PVR 'Roslyn' (No IR) */
case 34519: /* WinTV-PCI-FM */
case 69009:
/* WinTV-HVR4000 (DVBS/S2/T, Video and IR, back panel inputs) */
case 69100: /* WinTV-HVR4000LITE (DVBS/S2, IR) */
case 69500: /* WinTV-HVR4000LITE (DVBS/S2, No IR) */
case 69559:
/* WinTV-HVR4000 (DVBS/S2/T, Video no IR, back panel inputs) */
case 69569: /* WinTV-HVR4000 (DVBS/S2/T, Video no IR) */
case 90002: /* Nova-T-PCI (9002) */
case 92001: /* Nova-S-Plus (Video and IR) */
case 92002: /* Nova-S-Plus (Video and IR) */
case 90003: /* Nova-T-PCI (9002 No RF out) */
case 90500: /* Nova-T-PCI (oem) */
case 90501: /* Nova-T-PCI (oem/IR) */
case 92000: /* Nova-SE2 (OEM, No Video or IR) */
case 92900: /* WinTV-IROnly (No analog or digital Video inputs) */
case 94009: /* WinTV-HVR1100 (Video and IR Retail) */
case 94501: /* WinTV-HVR1100 (Video and IR OEM) */
case 96009: /* WinTV-HVR1300 (PAL Video, MPEG Video and IR RX) */
case 96019: /* WinTV-HVR1300 (PAL Video, MPEG Video and IR RX/TX) */
case 96559: /* WinTV-HVR1300 (PAL Video, MPEG Video no IR) */
case 96569: /* WinTV-HVR1300 () */
case 96659: /* WinTV-HVR1300 () */
case 98559: /* WinTV-HVR1100LP (Video no IR, Retail - Low Profile) */
/* known */
break;
case CX88_BOARD_SAMSUNG_SMT_7020:
cx_set(MO_GP0_IO, 0x008989FF);
break;
default:
pr_warn("warning: unknown hauppauge model #%d\n", tv.model);
break;
}
pr_info("hauppauge eeprom: model=%d\n", tv.model);
}
/*
* some GDI (was: Modular Technology) specific stuff
*/
static const struct {
int id;
int fm;
const char *name;
} gdi_tuner[] = {
[0x01] = { .id = UNSET,
.name = "NTSC_M" },
[0x02] = { .id = UNSET,
.name = "PAL_B" },
[0x03] = { .id = UNSET,
.name = "PAL_I" },
[0x04] = { .id = UNSET,
.name = "PAL_D" },
[0x05] = { .id = UNSET,
.name = "SECAM" },
[0x10] = { .id = UNSET,
.fm = 1,
.name = "TEMIC_4049" },
[0x11] = { .id = TUNER_TEMIC_4136FY5,
.name = "TEMIC_4136" },
[0x12] = { .id = UNSET,
.name = "TEMIC_4146" },
[0x20] = { .id = TUNER_PHILIPS_FQ1216ME,
.fm = 1,
.name = "PHILIPS_FQ1216_MK3" },
[0x21] = { .id = UNSET, .fm = 1,
.name = "PHILIPS_FQ1236_MK3" },
[0x22] = { .id = UNSET,
.name = "PHILIPS_FI1236_MK3" },
[0x23] = { .id = UNSET,
.name = "PHILIPS_FI1216_MK3" },
};
static void gdi_eeprom(struct cx88_core *core, u8 *eeprom_data)
{
const char *name = (eeprom_data[0x0d] < ARRAY_SIZE(gdi_tuner))
? gdi_tuner[eeprom_data[0x0d]].name : NULL;
pr_info("GDI: tuner=%s\n", name ? name : "unknown");
if (!name)
return;
core->board.tuner_type = gdi_tuner[eeprom_data[0x0d]].id;
core->board.radio.type = gdi_tuner[eeprom_data[0x0d]].fm ?
CX88_RADIO : 0;
}
/*
* some Divco specific stuff
*/
static int cx88_dvico_xc2028_callback(struct cx88_core *core,
int command, int arg)
{
switch (command) {
case XC2028_TUNER_RESET:
switch (core->boardnr) {
case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
/* GPIO-4 xc3028 tuner */
cx_set(MO_GP0_IO, 0x00001000);
cx_clear(MO_GP0_IO, 0x00000010);
msleep(100);
cx_set(MO_GP0_IO, 0x00000010);
msleep(100);
break;
default:
cx_write(MO_GP0_IO, 0x101000);
mdelay(5);
cx_set(MO_GP0_IO, 0x101010);
}
break;
default:
return -EINVAL;
}
return 0;
}
/*
* some Geniatech specific stuff
*/
static int cx88_xc3028_geniatech_tuner_callback(struct cx88_core *core,
int command, int mode)
{
switch (command) {
case XC2028_TUNER_RESET:
switch (INPUT(core->input).type) {
case CX88_RADIO:
break;
case CX88_VMUX_DVB:
cx_write(MO_GP1_IO, 0x030302);
mdelay(50);
break;
default:
cx_write(MO_GP1_IO, 0x030301);
mdelay(50);
}
cx_write(MO_GP1_IO, 0x101010);
mdelay(50);
cx_write(MO_GP1_IO, 0x101000);
mdelay(50);
cx_write(MO_GP1_IO, 0x101010);
mdelay(50);
return 0;
}
return -EINVAL;
}
static int cx88_xc3028_winfast1800h_callback(struct cx88_core *core,
int command, int arg)
{
switch (command) {
case XC2028_TUNER_RESET:
/* GPIO 12 (xc3028 tuner reset) */
cx_set(MO_GP1_IO, 0x1010);
mdelay(50);
cx_clear(MO_GP1_IO, 0x10);
mdelay(75);
cx_set(MO_GP1_IO, 0x10);
mdelay(75);
return 0;
}
return -EINVAL;
}
static int cx88_xc4000_winfast2000h_plus_callback(struct cx88_core *core,
int command, int arg)
{
switch (command) {
case XC4000_TUNER_RESET:
/* GPIO 12 (xc4000 tuner reset) */
cx_set(MO_GP1_IO, 0x1010);
mdelay(50);
cx_clear(MO_GP1_IO, 0x10);
mdelay(75);
cx_set(MO_GP1_IO, 0x10);
mdelay(75);
return 0;
}
return -EINVAL;
}
/*
* some Divco specific stuff
*/
static int cx88_pv_8000gt_callback(struct cx88_core *core,
int command, int arg)
{
switch (command) {
case XC2028_TUNER_RESET:
cx_write(MO_GP2_IO, 0xcf7);
mdelay(50);
cx_write(MO_GP2_IO, 0xef5);
mdelay(50);
cx_write(MO_GP2_IO, 0xcf7);
break;
default:
return -EINVAL;
}
return 0;
}
/*
* some DViCO specific stuff
*/
static void dvico_fusionhdtv_hybrid_init(struct cx88_core *core)
{
struct i2c_msg msg = { .addr = 0x45, .flags = 0 };
int i, err;
static u8 init_bufs[13][5] = {
{ 0x10, 0x00, 0x20, 0x01, 0x03 },
{ 0x10, 0x10, 0x01, 0x00, 0x21 },
{ 0x10, 0x10, 0x10, 0x00, 0xCA },
{ 0x10, 0x10, 0x12, 0x00, 0x08 },
{ 0x10, 0x10, 0x13, 0x00, 0x0A },
{ 0x10, 0x10, 0x16, 0x01, 0xC0 },
{ 0x10, 0x10, 0x22, 0x01, 0x3D },
{ 0x10, 0x10, 0x73, 0x01, 0x2E },
{ 0x10, 0x10, 0x72, 0x00, 0xC5 },
{ 0x10, 0x10, 0x71, 0x01, 0x97 },
{ 0x10, 0x10, 0x70, 0x00, 0x0F },
{ 0x10, 0x10, 0xB0, 0x00, 0x01 },
{ 0x03, 0x0C },
};
for (i = 0; i < ARRAY_SIZE(init_bufs); i++) {
msg.buf = init_bufs[i];
msg.len = (i != 12 ? 5 : 2);
err = i2c_transfer(&core->i2c_adap, &msg, 1);
if (err != 1) {
pr_warn("dvico_fusionhdtv_hybrid_init buf %d failed (err = %d)!\n",
i, err);
return;
}
}
}
static int cx88_xc2028_tuner_callback(struct cx88_core *core,
int command, int arg)
{
/* Board-specific callbacks */
switch (core->boardnr) {
case CX88_BOARD_POWERCOLOR_REAL_ANGEL:
case CX88_BOARD_GENIATECH_X8000_MT:
case CX88_BOARD_KWORLD_ATSC_120:
return cx88_xc3028_geniatech_tuner_callback(core,
command, arg);
case CX88_BOARD_PROLINK_PV_8000GT:
case CX88_BOARD_PROLINK_PV_GLOBAL_XTREME:
return cx88_pv_8000gt_callback(core, command, arg);
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
return cx88_dvico_xc2028_callback(core, command, arg);
case CX88_BOARD_NOTONLYTV_LV3H:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL:
case CX88_BOARD_WINFAST_DTV1800H:
return cx88_xc3028_winfast1800h_callback(core, command, arg);
}
switch (command) {
case XC2028_TUNER_RESET:
switch (INPUT(core->input).type) {
case CX88_RADIO:
dprintk(1, "setting GPIO to radio!\n");
cx_write(MO_GP0_IO, 0x4ff);
mdelay(250);
cx_write(MO_GP2_IO, 0xff);
mdelay(250);
break;
case CX88_VMUX_DVB: /* Digital TV*/
default: /* Analog TV */
dprintk(1, "setting GPIO to TV!\n");
break;
}
cx_write(MO_GP1_IO, 0x101010);
mdelay(250);
cx_write(MO_GP1_IO, 0x101000);
mdelay(250);
cx_write(MO_GP1_IO, 0x101010);
mdelay(250);
return 0;
}
return -EINVAL;
}
static int cx88_xc4000_tuner_callback(struct cx88_core *core,
int command, int arg)
{
/* Board-specific callbacks */
switch (core->boardnr) {
case CX88_BOARD_WINFAST_DTV1800H_XC4000:
case CX88_BOARD_WINFAST_DTV2000H_PLUS:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F36:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F43:
return cx88_xc4000_winfast2000h_plus_callback(core,
command, arg);
}
return -EINVAL;
}
/*
* Tuner callback function. Currently only needed for the Pinnacle
* PCTV HD 800i with an xc5000 silicon tuner. This is used for both
* analog tuner attach (tuner-core.c) and dvb tuner attach (cx88-dvb.c)
*/
static int cx88_xc5000_tuner_callback(struct cx88_core *core,
int command, int arg)
{
switch (core->boardnr) {
case CX88_BOARD_PINNACLE_PCTV_HD_800i:
if (command == 0) { /* This is the reset command from xc5000 */
/*
* djh - According to the engineer at PCTV Systems,
* the xc5000 reset pin is supposed to be on GPIO12.
* However, despite three nights of effort, pulling
* that GPIO low didn't reset the xc5000. While
* pulling MO_SRST_IO low does reset the xc5000, this
* also resets in the s5h1409 being reset as well.
* This causes tuning to always fail since the internal
* state of the s5h1409 does not match the driver's
* state. Given that the only two conditions in which
* the driver performs a reset is during firmware load
* and powering down the chip, I am taking out the
* reset. We know that the chip is being reset
* when the cx88 comes online, and not being able to
* do power management for this board is worse than
* not having any tuning at all.
*/
return 0;
}
dprintk(1, "xc5000: unknown tuner callback command.\n");
return -EINVAL;
case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD:
if (command == 0) { /* This is the reset command from xc5000 */
cx_clear(MO_GP0_IO, 0x00000010);
usleep_range(10000, 20000);
cx_set(MO_GP0_IO, 0x00000010);
return 0;
}
dprintk(1, "xc5000: unknown tuner callback command.\n");
return -EINVAL;
}
return 0; /* Should never be here */
}
int cx88_tuner_callback(void *priv, int component, int command, int arg)
{
struct i2c_algo_bit_data *i2c_algo = priv;
struct cx88_core *core;
if (!i2c_algo) {
pr_err("Error - i2c private data undefined.\n");
return -EINVAL;
}
core = i2c_algo->data;
if (!core) {
pr_err("Error - device struct undefined.\n");
return -EINVAL;
}
if (component != DVB_FRONTEND_COMPONENT_TUNER)
return -EINVAL;
switch (core->board.tuner_type) {
case TUNER_XC2028:
dprintk(1, "Calling XC2028/3028 callback\n");
return cx88_xc2028_tuner_callback(core, command, arg);
case TUNER_XC4000:
dprintk(1, "Calling XC4000 callback\n");
return cx88_xc4000_tuner_callback(core, command, arg);
case TUNER_XC5000:
dprintk(1, "Calling XC5000 callback\n");
return cx88_xc5000_tuner_callback(core, command, arg);
}
pr_err("Error: Calling callback for tuner %d\n",
core->board.tuner_type);
return -EINVAL;
}
EXPORT_SYMBOL(cx88_tuner_callback);
/* ----------------------------------------------------------------------- */
static void cx88_card_list(struct cx88_core *core, struct pci_dev *pci)
{
int i;
if (!pci->subsystem_vendor && !pci->subsystem_device) {
pr_err("Your board has no valid PCI Subsystem ID and thus can't\n");
pr_err("be autodetected. Please pass card=<n> insmod option to\n");
pr_err("workaround that. Redirect complaints to the vendor of\n");
pr_err("the TV card\n");
} else {
pr_err("Your board isn't known (yet) to the driver. You can\n");
pr_err("try to pick one of the existing card configs via\n");
pr_err("card=<n> insmod option. Updating to the latest\n");
pr_err("version might help as well.\n");
}
pr_err("Here is a list of valid choices for the card=<n> insmod option:\n");
for (i = 0; i < ARRAY_SIZE(cx88_boards); i++)
pr_err(" card=%d -> %s\n", i, cx88_boards[i].name);
}
static void cx88_card_setup_pre_i2c(struct cx88_core *core)
{
switch (core->boardnr) {
case CX88_BOARD_HAUPPAUGE_HVR1300:
/*
* Bring the 702 demod up before i2c scanning/attach or
* devices are hidden.
*
* We leave here with the 702 on the bus
*
* "reset the IR receiver on GPIO[3]"
* Reported by Mike Crash <mike AT mikecrash.com>
*/
cx_write(MO_GP0_IO, 0x0000ef88);
udelay(1000);
cx_clear(MO_GP0_IO, 0x00000088);
udelay(50);
cx_set(MO_GP0_IO, 0x00000088); /* 702 out of reset */
udelay(1000);
break;
case CX88_BOARD_PROLINK_PV_GLOBAL_XTREME:
case CX88_BOARD_PROLINK_PV_8000GT:
cx_write(MO_GP2_IO, 0xcf7);
msleep(50);
cx_write(MO_GP2_IO, 0xef5);
msleep(50);
cx_write(MO_GP2_IO, 0xcf7);
usleep_range(10000, 20000);
break;
case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD:
/* Enable the xc5000 tuner */
cx_set(MO_GP0_IO, 0x00001010);
break;
case CX88_BOARD_WINFAST_DTV2000H_J:
case CX88_BOARD_HAUPPAUGE_HVR3000:
case CX88_BOARD_HAUPPAUGE_HVR4000:
/* Init GPIO */
cx_write(MO_GP0_IO, core->board.input[0].gpio0);
udelay(1000);
cx_clear(MO_GP0_IO, 0x00000080);
udelay(50);
cx_set(MO_GP0_IO, 0x00000080); /* 702 out of reset */
udelay(1000);
break;
case CX88_BOARD_NOTONLYTV_LV3H:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL:
case CX88_BOARD_WINFAST_DTV1800H:
cx88_xc3028_winfast1800h_callback(core, XC2028_TUNER_RESET, 0);
break;
case CX88_BOARD_WINFAST_DTV1800H_XC4000:
case CX88_BOARD_WINFAST_DTV2000H_PLUS:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F36:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F43:
cx88_xc4000_winfast2000h_plus_callback(core,
XC4000_TUNER_RESET, 0);
break;
case CX88_BOARD_TWINHAN_VP1027_DVBS:
cx_write(MO_GP0_IO, 0x00003230);
cx_write(MO_GP0_IO, 0x00003210);
usleep_range(10000, 20000);
cx_write(MO_GP0_IO, 0x00001230);
break;
}
}
/*
* Sets board-dependent xc3028 configuration
*/
void cx88_setup_xc3028(struct cx88_core *core, struct xc2028_ctrl *ctl)
{
memset(ctl, 0, sizeof(*ctl));
ctl->fname = XC2028_DEFAULT_FIRMWARE;
ctl->max_len = 64;
switch (core->boardnr) {
case CX88_BOARD_POWERCOLOR_REAL_ANGEL:
/* Now works with firmware version 2.7 */
if (core->i2c_algo.udelay < 16)
core->i2c_algo.udelay = 16;
break;
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
case CX88_BOARD_WINFAST_DTV1800H:
ctl->demod = XC3028_FE_ZARLINK456;
break;
case CX88_BOARD_KWORLD_ATSC_120:
case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
ctl->demod = XC3028_FE_OREN538;
break;
case CX88_BOARD_GENIATECH_X8000_MT:
/*
* FIXME: For this board, the xc3028 never recovers after being
* powered down (the reset GPIO probably is not set properly).
* We don't have access to the hardware so we cannot determine
* which GPIO is used for xc3028, so just disable power xc3028
* power management for now
*/
ctl->disable_power_mgmt = 1;
break;
case CX88_BOARD_NOTONLYTV_LV3H:
ctl->demod = XC3028_FE_ZARLINK456;
ctl->fname = XC3028L_DEFAULT_FIRMWARE;
ctl->read_not_reliable = 1;
break;
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL:
case CX88_BOARD_PROLINK_PV_GLOBAL_XTREME:
case CX88_BOARD_PROLINK_PV_8000GT:
/*
* Those boards uses non-MTS firmware
*/
break;
case CX88_BOARD_PINNACLE_HYBRID_PCTV:
case CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII:
ctl->demod = XC3028_FE_ZARLINK456;
ctl->mts = 1;
break;
default:
ctl->demod = XC3028_FE_OREN538;
ctl->mts = 1;
}
}
EXPORT_SYMBOL_GPL(cx88_setup_xc3028);
static void cx88_card_setup(struct cx88_core *core)
{
static u8 eeprom[256];
struct tuner_setup tun_setup;
unsigned int mode_mask = T_RADIO | T_ANALOG_TV;
memset(&tun_setup, 0, sizeof(tun_setup));
if (!core->i2c_rc) {
core->i2c_client.addr = 0xa0 >> 1;
tveeprom_read(&core->i2c_client, eeprom, sizeof(eeprom));
}
switch (core->boardnr) {
case CX88_BOARD_HAUPPAUGE:
case CX88_BOARD_HAUPPAUGE_ROSLYN:
if (!core->i2c_rc)
hauppauge_eeprom(core, eeprom + 8);
break;
case CX88_BOARD_GDI:
if (!core->i2c_rc)
gdi_eeprom(core, eeprom);
break;
case CX88_BOARD_LEADTEK_PVR2000:
case CX88_BOARD_WINFAST_DV2000:
case CX88_BOARD_WINFAST2000XP_EXPERT:
if (!core->i2c_rc)
leadtek_eeprom(core, eeprom);
break;
case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
case CX88_BOARD_HAUPPAUGE_DVB_T1:
case CX88_BOARD_HAUPPAUGE_HVR1100:
case CX88_BOARD_HAUPPAUGE_HVR1100LP:
case CX88_BOARD_HAUPPAUGE_HVR3000:
case CX88_BOARD_HAUPPAUGE_HVR1300:
case CX88_BOARD_HAUPPAUGE_HVR4000:
case CX88_BOARD_HAUPPAUGE_HVR4000LITE:
case CX88_BOARD_HAUPPAUGE_IRONLY:
if (!core->i2c_rc)
hauppauge_eeprom(core, eeprom);
break;
case CX88_BOARD_KWORLD_DVBS_100:
cx_write(MO_GP0_IO, 0x000007f8);
cx_write(MO_GP1_IO, 0x00000001);
break;
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
/* GPIO0:0 is hooked to demod reset */
/* GPIO0:4 is hooked to xc3028 reset */
cx_write(MO_GP0_IO, 0x00111100);
usleep_range(10000, 20000);
cx_write(MO_GP0_IO, 0x00111111);
break;
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
/* GPIO0:6 is hooked to FX2 reset pin */
cx_set(MO_GP0_IO, 0x00004040);
cx_clear(MO_GP0_IO, 0x00000040);
msleep(1000);
cx_set(MO_GP0_IO, 0x00004040);
fallthrough;
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
/* GPIO0:0 is hooked to mt352 reset pin */
cx_set(MO_GP0_IO, 0x00000101);
cx_clear(MO_GP0_IO, 0x00000001);
usleep_range(10000, 20000);
cx_set(MO_GP0_IO, 0x00000101);
if (!core->i2c_rc &&
core->boardnr == CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID)
dvico_fusionhdtv_hybrid_init(core);
break;
case CX88_BOARD_KWORLD_DVB_T:
case CX88_BOARD_DNTV_LIVE_DVB_T:
cx_set(MO_GP0_IO, 0x00000707);
cx_set(MO_GP2_IO, 0x00000101);
cx_clear(MO_GP2_IO, 0x00000001);
usleep_range(10000, 20000);
cx_clear(MO_GP0_IO, 0x00000007);
cx_set(MO_GP2_IO, 0x00000101);
break;
case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
cx_write(MO_GP0_IO, 0x00080808);
break;
case CX88_BOARD_ATI_HDTVWONDER:
if (!core->i2c_rc) {
/* enable tuner */
int i;
static const u8 buffer[][2] = {
{0x10, 0x12},
{0x13, 0x04},
{0x16, 0x00},
{0x14, 0x04},
{0x17, 0x00}
};
core->i2c_client.addr = 0x0a;
for (i = 0; i < ARRAY_SIZE(buffer); i++)
if (i2c_master_send(&core->i2c_client,
buffer[i], 2) != 2)
pr_warn("Unable to enable tuner(%i).\n",
i);
}
break;
case CX88_BOARD_MSI_TVANYWHERE_MASTER:
{
struct v4l2_priv_tun_config tea5767_cfg;
struct tea5767_ctrl ctl;
memset(&ctl, 0, sizeof(ctl));
ctl.high_cut = 1;
ctl.st_noise = 1;
ctl.deemph_75 = 1;
ctl.xtal_freq = TEA5767_HIGH_LO_13MHz;
tea5767_cfg.tuner = TUNER_TEA5767;
tea5767_cfg.priv = &ctl;
call_all(core, tuner, s_config, &tea5767_cfg);
break;
}
case CX88_BOARD_TEVII_S420:
case CX88_BOARD_TEVII_S460:
case CX88_BOARD_TEVII_S464:
case CX88_BOARD_OMICOM_SS4_PCI:
case CX88_BOARD_TBS_8910:
case CX88_BOARD_TBS_8920:
case CX88_BOARD_PROF_6200:
case CX88_BOARD_PROF_7300:
case CX88_BOARD_PROF_7301:
case CX88_BOARD_SATTRADE_ST4200:
cx_write(MO_GP0_IO, 0x8000);
msleep(100);
cx_write(MO_SRST_IO, 0);
usleep_range(10000, 20000);
cx_write(MO_GP0_IO, 0x8080);
msleep(100);
cx_write(MO_SRST_IO, 1);
msleep(100);
break;
} /*end switch() */
/* Setup tuners */
if (core->board.radio_type != UNSET) {
tun_setup.mode_mask = T_RADIO;
tun_setup.type = core->board.radio_type;
tun_setup.addr = core->board.radio_addr;
tun_setup.tuner_callback = cx88_tuner_callback;
call_all(core, tuner, s_type_addr, &tun_setup);
mode_mask &= ~T_RADIO;
}
if (core->board.tuner_type != UNSET) {
tun_setup.mode_mask = mode_mask;
tun_setup.type = core->board.tuner_type;
tun_setup.addr = core->board.tuner_addr;
tun_setup.tuner_callback = cx88_tuner_callback;
call_all(core, tuner, s_type_addr, &tun_setup);
}
if (core->board.tda9887_conf) {
struct v4l2_priv_tun_config tda9887_cfg;
tda9887_cfg.tuner = TUNER_TDA9887;
tda9887_cfg.priv = &core->board.tda9887_conf;
call_all(core, tuner, s_config, &tda9887_cfg);
}
if (core->board.tuner_type == TUNER_XC2028) {
struct v4l2_priv_tun_config xc2028_cfg;
struct xc2028_ctrl ctl;
/* Fills device-dependent initialization parameters */
cx88_setup_xc3028(core, &ctl);
/* Sends parameters to xc2028/3028 tuner */
memset(&xc2028_cfg, 0, sizeof(xc2028_cfg));
xc2028_cfg.tuner = TUNER_XC2028;
xc2028_cfg.priv = &ctl;
dprintk(1, "Asking xc2028/3028 to load firmware %s\n",
ctl.fname);
call_all(core, tuner, s_config, &xc2028_cfg);
}
call_all(core, tuner, standby);
}
/* ------------------------------------------------------------------ */
static int cx88_pci_quirks(const char *name, struct pci_dev *pci)
{
unsigned int lat = UNSET;
u8 ctrl = 0;
u8 value;
/* check pci quirks */
if (pci_pci_problems & PCIPCI_TRITON) {
pr_info("quirk: PCIPCI_TRITON -- set TBFX\n");
ctrl |= CX88X_EN_TBFX;
}
if (pci_pci_problems & PCIPCI_NATOMA) {
pr_info("quirk: PCIPCI_NATOMA -- set TBFX\n");
ctrl |= CX88X_EN_TBFX;
}
if (pci_pci_problems & PCIPCI_VIAETBF) {
pr_info("quirk: PCIPCI_VIAETBF -- set TBFX\n");
ctrl |= CX88X_EN_TBFX;
}
if (pci_pci_problems & PCIPCI_VSFX) {
pr_info("quirk: PCIPCI_VSFX -- set VSFX\n");
ctrl |= CX88X_EN_VSFX;
}
#ifdef PCIPCI_ALIMAGIK
if (pci_pci_problems & PCIPCI_ALIMAGIK) {
pr_info("quirk: PCIPCI_ALIMAGIK -- latency fixup\n");
lat = 0x0A;
}
#endif
/* check insmod options */
if (latency != UNSET)
lat = latency;
/* apply stuff */
if (ctrl) {
pci_read_config_byte(pci, CX88X_DEVCTRL, &value);
value |= ctrl;
pci_write_config_byte(pci, CX88X_DEVCTRL, value);
}
if (lat != UNSET) {
pr_info("setting pci latency timer to %d\n", latency);
pci_write_config_byte(pci, PCI_LATENCY_TIMER, latency);
}
return 0;
}
int cx88_get_resources(const struct cx88_core *core, struct pci_dev *pci)
{
if (request_mem_region(pci_resource_start(pci, 0),
pci_resource_len(pci, 0),
core->name))
return 0;
pr_err("func %d: Can't get MMIO memory @ 0x%llx, subsystem: %04x:%04x\n",
PCI_FUNC(pci->devfn),
(unsigned long long)pci_resource_start(pci, 0),
pci->subsystem_vendor, pci->subsystem_device);
return -EBUSY;
}
/*
* Allocate and initialize the cx88 core struct. One should hold the
* devlist mutex before calling this.
*/
struct cx88_core *cx88_core_create(struct pci_dev *pci, int nr)
{
struct cx88_core *core;
int i;
core = kzalloc(sizeof(*core), GFP_KERNEL);
if (!core)
return NULL;
refcount_set(&core->refcount, 1);
core->pci_bus = pci->bus->number;
core->pci_slot = PCI_SLOT(pci->devfn);
core->pci_irqmask = PCI_INT_RISC_RD_BERRINT | PCI_INT_RISC_WR_BERRINT |
PCI_INT_BRDG_BERRINT | PCI_INT_SRC_DMA_BERRINT |
PCI_INT_DST_DMA_BERRINT | PCI_INT_IPB_DMA_BERRINT;
mutex_init(&core->lock);
core->nr = nr;
sprintf(core->name, "cx88[%d]", core->nr);
/*
* Note: Setting initial standard here would cause first call to
* cx88_set_tvnorm() to return without programming any registers. Leave
* it blank for at this point and it will get set later in
* cx8800_initdev()
*/
core->tvnorm = 0;
core->width = 320;
core->height = 240;
core->field = V4L2_FIELD_INTERLACED;
strscpy(core->v4l2_dev.name, core->name, sizeof(core->v4l2_dev.name));
if (v4l2_device_register(NULL, &core->v4l2_dev)) {
kfree(core);
return NULL;
}
if (v4l2_ctrl_handler_init(&core->video_hdl, 13)) {
v4l2_device_unregister(&core->v4l2_dev);
kfree(core);
return NULL;
}
if (v4l2_ctrl_handler_init(&core->audio_hdl, 13)) {
v4l2_ctrl_handler_free(&core->video_hdl);
v4l2_device_unregister(&core->v4l2_dev);
kfree(core);
return NULL;
}
if (cx88_get_resources(core, pci) != 0) {
v4l2_ctrl_handler_free(&core->video_hdl);
v4l2_ctrl_handler_free(&core->audio_hdl);
v4l2_device_unregister(&core->v4l2_dev);
kfree(core);
return NULL;
}
/* PCI stuff */
cx88_pci_quirks(core->name, pci);
core->lmmio = ioremap(pci_resource_start(pci, 0),
pci_resource_len(pci, 0));
core->bmmio = (u8 __iomem *)core->lmmio;
if (!core->lmmio) {
release_mem_region(pci_resource_start(pci, 0),
pci_resource_len(pci, 0));
v4l2_ctrl_handler_free(&core->video_hdl);
v4l2_ctrl_handler_free(&core->audio_hdl);
v4l2_device_unregister(&core->v4l2_dev);
kfree(core);
return NULL;
}
/* board config */
core->boardnr = UNSET;
if (card[core->nr] < ARRAY_SIZE(cx88_boards))
core->boardnr = card[core->nr];
for (i = 0; core->boardnr == UNSET && i < ARRAY_SIZE(cx88_subids); i++)
if (pci->subsystem_vendor == cx88_subids[i].subvendor &&
pci->subsystem_device == cx88_subids[i].subdevice)
core->boardnr = cx88_subids[i].card;
if (core->boardnr == UNSET) {
core->boardnr = CX88_BOARD_UNKNOWN;
cx88_card_list(core, pci);
}
core->board = cx88_boards[core->boardnr];
if (!core->board.num_frontends && (core->board.mpeg & CX88_MPEG_DVB))
core->board.num_frontends = 1;
pr_info("subsystem: %04x:%04x, board: %s [card=%d,%s], frontend(s): %d\n",
pci->subsystem_vendor, pci->subsystem_device, core->board.name,
core->boardnr, card[core->nr] == core->boardnr ?
"insmod option" : "autodetected",
core->board.num_frontends);
if (tuner[core->nr] != UNSET)
core->board.tuner_type = tuner[core->nr];
if (radio[core->nr] != UNSET)
core->board.radio_type = radio[core->nr];
dprintk(1, "TV tuner type %d, Radio tuner type %d\n",
core->board.tuner_type, core->board.radio_type);
/* init hardware */
cx88_reset(core);
cx88_card_setup_pre_i2c(core);
cx88_i2c_init(core, pci);
/* load tuner module, if needed */
if (core->board.tuner_type != UNSET) {
/*
* Ignore 0x6b and 0x6f on cx88 boards.
* FusionHDTV5 RT Gold has an ir receiver at 0x6b
* and an RTC at 0x6f which can get corrupted if probed.
*/
static const unsigned short tv_addrs[] = {
0x42, 0x43, 0x4a, 0x4b, /* tda8290 */
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6c, 0x6d, 0x6e,
I2C_CLIENT_END
};
int has_demod = (core->board.tda9887_conf & TDA9887_PRESENT);
/*
* I don't trust the radio_type as is stored in the card
* definitions, so we just probe for it.
* The radio_type is sometimes missing, or set to UNSET but
* later code configures a tea5767.
*/
v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap,
"tuner", 0,
v4l2_i2c_tuner_addrs(ADDRS_RADIO));
if (has_demod)
v4l2_i2c_new_subdev(&core->v4l2_dev,
&core->i2c_adap, "tuner",
0, v4l2_i2c_tuner_addrs(ADDRS_DEMOD));
if (core->board.tuner_addr == ADDR_UNSET) {
v4l2_i2c_new_subdev(&core->v4l2_dev,
&core->i2c_adap, "tuner",
0, has_demod ? tv_addrs + 4 : tv_addrs);
} else {
v4l2_i2c_new_subdev(&core->v4l2_dev, &core->i2c_adap,
"tuner", core->board.tuner_addr,
NULL);
}
}
cx88_card_setup(core);
if (!disable_ir) {
cx88_i2c_init_ir(core);
cx88_ir_init(core, pci);
}
return core;
}
| linux-master | drivers/media/pci/cx88/cx88-cards.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* Device driver for GPIO attached remote control interfaces
* on Conexant 2388x based TV/DVB cards.
*
* Copyright (c) 2003 Pavel Machek
* Copyright (c) 2004 Gerd Knorr
* Copyright (c) 2004, 2005 Chris Pascoe
*/
#include "cx88.h"
#include <linux/init.h>
#include <linux/hrtimer.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <media/rc-core.h>
#define MODULE_NAME "cx88xx"
/* ---------------------------------------------------------------------- */
struct cx88_IR {
struct cx88_core *core;
struct rc_dev *dev;
int users;
char name[32];
char phys[32];
/* sample from gpio pin 16 */
u32 sampling;
/* poll external decoder */
int polling;
struct hrtimer timer;
u32 gpio_addr;
u32 last_gpio;
u32 mask_keycode;
u32 mask_keydown;
u32 mask_keyup;
};
static unsigned int ir_samplerate = 4;
module_param(ir_samplerate, uint, 0444);
MODULE_PARM_DESC(ir_samplerate, "IR samplerate in kHz, 1 - 20, default 4");
static int ir_debug;
module_param(ir_debug, int, 0644); /* debug level [IR] */
MODULE_PARM_DESC(ir_debug, "enable debug messages [IR]");
#define ir_dprintk(fmt, arg...) do { \
if (ir_debug) \
printk(KERN_DEBUG "%s IR: " fmt, ir->core->name, ##arg);\
} while (0)
#define dprintk(fmt, arg...) do { \
if (ir_debug) \
printk(KERN_DEBUG "cx88 IR: " fmt, ##arg); \
} while (0)
/* ---------------------------------------------------------------------- */
static void cx88_ir_handle_key(struct cx88_IR *ir)
{
struct cx88_core *core = ir->core;
u32 gpio, data, auxgpio;
/* read gpio value */
gpio = cx_read(ir->gpio_addr);
switch (core->boardnr) {
case CX88_BOARD_NPGTECH_REALTV_TOP10FM:
/*
* This board apparently uses a combination of 2 GPIO
* to represent the keys. Additionally, the second GPIO
* can be used for parity.
*
* Example:
*
* for key "5"
* gpio = 0x758, auxgpio = 0xe5 or 0xf5
* for key "Power"
* gpio = 0x758, auxgpio = 0xed or 0xfd
*/
auxgpio = cx_read(MO_GP1_IO);
/* Take out the parity part */
gpio = (gpio & 0x7fd) + (auxgpio & 0xef);
break;
case CX88_BOARD_WINFAST_DTV1000:
case CX88_BOARD_WINFAST_DTV1800H:
case CX88_BOARD_WINFAST_DTV1800H_XC4000:
case CX88_BOARD_WINFAST_DTV2000H_PLUS:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F36:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F43:
gpio = (gpio & 0x6ff) | ((cx_read(MO_GP1_IO) << 8) & 0x900);
auxgpio = gpio;
break;
default:
auxgpio = gpio;
}
if (ir->polling) {
if (ir->last_gpio == auxgpio)
return;
ir->last_gpio = auxgpio;
}
/* extract data */
data = ir_extract_bits(gpio, ir->mask_keycode);
ir_dprintk("irq gpio=0x%x code=%d | %s%s%s\n",
gpio, data,
ir->polling ? "poll" : "irq",
(gpio & ir->mask_keydown) ? " down" : "",
(gpio & ir->mask_keyup) ? " up" : "");
if (ir->core->boardnr == CX88_BOARD_NORWOOD_MICRO) {
u32 gpio_key = cx_read(MO_GP0_IO);
data = (data << 4) | ((gpio_key & 0xf0) >> 4);
rc_keydown(ir->dev, RC_PROTO_UNKNOWN, data, 0);
} else if (ir->core->boardnr == CX88_BOARD_PROLINK_PLAYTVPVR ||
ir->core->boardnr == CX88_BOARD_PIXELVIEW_PLAYTV_ULTRA_PRO) {
/* bit cleared on keydown, NEC scancode, 0xAAAACC, A = 0x866b */
u16 addr;
u8 cmd;
u32 scancode;
addr = (data >> 8) & 0xffff;
cmd = (data >> 0) & 0x00ff;
scancode = RC_SCANCODE_NECX(addr, cmd);
if (0 == (gpio & ir->mask_keyup))
rc_keydown_notimeout(ir->dev, RC_PROTO_NECX, scancode,
0);
else
rc_keyup(ir->dev);
} else if (ir->mask_keydown) {
/* bit set on keydown */
if (gpio & ir->mask_keydown)
rc_keydown_notimeout(ir->dev, RC_PROTO_UNKNOWN, data,
0);
else
rc_keyup(ir->dev);
} else if (ir->mask_keyup) {
/* bit cleared on keydown */
if (0 == (gpio & ir->mask_keyup))
rc_keydown_notimeout(ir->dev, RC_PROTO_UNKNOWN, data,
0);
else
rc_keyup(ir->dev);
} else {
/* can't distinguish keydown/up :-/ */
rc_keydown_notimeout(ir->dev, RC_PROTO_UNKNOWN, data, 0);
rc_keyup(ir->dev);
}
}
static enum hrtimer_restart cx88_ir_work(struct hrtimer *timer)
{
u64 missed;
struct cx88_IR *ir = container_of(timer, struct cx88_IR, timer);
cx88_ir_handle_key(ir);
missed = hrtimer_forward_now(&ir->timer,
ktime_set(0, ir->polling * 1000000));
if (missed > 1)
ir_dprintk("Missed ticks %llu\n", missed - 1);
return HRTIMER_RESTART;
}
static int __cx88_ir_start(void *priv)
{
struct cx88_core *core = priv;
struct cx88_IR *ir;
if (!core || !core->ir)
return -EINVAL;
ir = core->ir;
if (ir->polling) {
hrtimer_init(&ir->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
ir->timer.function = cx88_ir_work;
hrtimer_start(&ir->timer,
ktime_set(0, ir->polling * 1000000),
HRTIMER_MODE_REL);
}
if (ir->sampling) {
core->pci_irqmask |= PCI_INT_IR_SMPINT;
cx_write(MO_DDS_IO, 0x33F286 * ir_samplerate); /* samplerate */
cx_write(MO_DDSCFG_IO, 0x5); /* enable */
}
return 0;
}
static void __cx88_ir_stop(void *priv)
{
struct cx88_core *core = priv;
struct cx88_IR *ir;
if (!core || !core->ir)
return;
ir = core->ir;
if (ir->sampling) {
cx_write(MO_DDSCFG_IO, 0x0);
core->pci_irqmask &= ~PCI_INT_IR_SMPINT;
}
if (ir->polling)
hrtimer_cancel(&ir->timer);
}
int cx88_ir_start(struct cx88_core *core)
{
if (core->ir->users)
return __cx88_ir_start(core);
return 0;
}
EXPORT_SYMBOL(cx88_ir_start);
void cx88_ir_stop(struct cx88_core *core)
{
if (core->ir->users)
__cx88_ir_stop(core);
}
EXPORT_SYMBOL(cx88_ir_stop);
static int cx88_ir_open(struct rc_dev *rc)
{
struct cx88_core *core = rc->priv;
core->ir->users++;
return __cx88_ir_start(core);
}
static void cx88_ir_close(struct rc_dev *rc)
{
struct cx88_core *core = rc->priv;
core->ir->users--;
if (!core->ir->users)
__cx88_ir_stop(core);
}
/* ---------------------------------------------------------------------- */
int cx88_ir_init(struct cx88_core *core, struct pci_dev *pci)
{
struct cx88_IR *ir;
struct rc_dev *dev;
char *ir_codes = NULL;
u64 rc_proto = RC_PROTO_BIT_OTHER;
int err = -ENOMEM;
u32 hardware_mask = 0; /* For devices with a hardware mask, when
* used with a full-code IR table
*/
ir = kzalloc(sizeof(*ir), GFP_KERNEL);
dev = rc_allocate_device(RC_DRIVER_IR_RAW);
if (!ir || !dev)
goto err_out_free;
ir->dev = dev;
/* detect & configure */
switch (core->boardnr) {
case CX88_BOARD_DNTV_LIVE_DVB_T:
case CX88_BOARD_KWORLD_DVB_T:
case CX88_BOARD_KWORLD_DVB_T_CX22702:
ir_codes = RC_MAP_DNTV_LIVE_DVB_T;
ir->gpio_addr = MO_GP1_IO;
ir->mask_keycode = 0x1f;
ir->mask_keyup = 0x60;
ir->polling = 50; /* ms */
break;
case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
ir_codes = RC_MAP_CINERGY_1400;
ir->sampling = 0xeb04; /* address */
break;
case CX88_BOARD_HAUPPAUGE:
case CX88_BOARD_HAUPPAUGE_DVB_T1:
case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
case CX88_BOARD_HAUPPAUGE_HVR1100:
case CX88_BOARD_HAUPPAUGE_HVR3000:
case CX88_BOARD_HAUPPAUGE_HVR4000:
case CX88_BOARD_HAUPPAUGE_HVR4000LITE:
case CX88_BOARD_PCHDTV_HD3000:
case CX88_BOARD_PCHDTV_HD5500:
case CX88_BOARD_HAUPPAUGE_IRONLY:
ir_codes = RC_MAP_HAUPPAUGE;
ir->sampling = 1;
break;
case CX88_BOARD_WINFAST_DTV2000H:
case CX88_BOARD_WINFAST_DTV2000H_J:
case CX88_BOARD_WINFAST_DTV1800H:
case CX88_BOARD_WINFAST_DTV1800H_XC4000:
case CX88_BOARD_WINFAST_DTV2000H_PLUS:
ir_codes = RC_MAP_WINFAST;
ir->gpio_addr = MO_GP0_IO;
ir->mask_keycode = 0x8f8;
ir->mask_keyup = 0x100;
ir->polling = 50; /* ms */
break;
case CX88_BOARD_WINFAST2000XP_EXPERT:
case CX88_BOARD_WINFAST_DTV1000:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F36:
case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F43:
ir_codes = RC_MAP_WINFAST;
ir->gpio_addr = MO_GP0_IO;
ir->mask_keycode = 0x8f8;
ir->mask_keyup = 0x100;
ir->polling = 1; /* ms */
break;
case CX88_BOARD_IODATA_GVBCTV7E:
ir_codes = RC_MAP_IODATA_BCTV7E;
ir->gpio_addr = MO_GP0_IO;
ir->mask_keycode = 0xfd;
ir->mask_keydown = 0x02;
ir->polling = 5; /* ms */
break;
case CX88_BOARD_PROLINK_PLAYTVPVR:
case CX88_BOARD_PIXELVIEW_PLAYTV_ULTRA_PRO:
/*
* It seems that this hardware is paired with NEC extended
* address 0x866b. So, unfortunately, its usage with other
* IR's with different address won't work. Still, there are
* other IR's from the same manufacturer that works, like the
* 002-T mini RC, provided with newer PV hardware
*/
ir_codes = RC_MAP_PIXELVIEW_MK12;
rc_proto = RC_PROTO_BIT_NECX;
ir->gpio_addr = MO_GP1_IO;
ir->mask_keyup = 0x80;
ir->polling = 10; /* ms */
hardware_mask = 0x3f; /* Hardware returns only 6 bits from command part */
break;
case CX88_BOARD_PROLINK_PV_8000GT:
case CX88_BOARD_PROLINK_PV_GLOBAL_XTREME:
ir_codes = RC_MAP_PIXELVIEW_NEW;
ir->gpio_addr = MO_GP1_IO;
ir->mask_keycode = 0x3f;
ir->mask_keyup = 0x80;
ir->polling = 1; /* ms */
break;
case CX88_BOARD_KWORLD_LTV883:
ir_codes = RC_MAP_PIXELVIEW;
ir->gpio_addr = MO_GP1_IO;
ir->mask_keycode = 0x1f;
ir->mask_keyup = 0x60;
ir->polling = 1; /* ms */
break;
case CX88_BOARD_ADSTECH_DVB_T_PCI:
ir_codes = RC_MAP_ADSTECH_DVB_T_PCI;
ir->gpio_addr = MO_GP1_IO;
ir->mask_keycode = 0xbf;
ir->mask_keyup = 0x40;
ir->polling = 50; /* ms */
break;
case CX88_BOARD_MSI_TVANYWHERE_MASTER:
ir_codes = RC_MAP_MSI_TVANYWHERE;
ir->gpio_addr = MO_GP1_IO;
ir->mask_keycode = 0x1f;
ir->mask_keyup = 0x40;
ir->polling = 1; /* ms */
break;
case CX88_BOARD_AVERTV_303:
case CX88_BOARD_AVERTV_STUDIO_303:
ir_codes = RC_MAP_AVERTV_303;
ir->gpio_addr = MO_GP2_IO;
ir->mask_keycode = 0xfb;
ir->mask_keydown = 0x02;
ir->polling = 50; /* ms */
break;
case CX88_BOARD_OMICOM_SS4_PCI:
case CX88_BOARD_SATTRADE_ST4200:
case CX88_BOARD_TBS_8920:
case CX88_BOARD_TBS_8910:
case CX88_BOARD_PROF_7300:
case CX88_BOARD_PROF_7301:
case CX88_BOARD_PROF_6200:
ir_codes = RC_MAP_TBS_NEC;
ir->sampling = 0xff00; /* address */
break;
case CX88_BOARD_TEVII_S464:
case CX88_BOARD_TEVII_S460:
case CX88_BOARD_TEVII_S420:
ir_codes = RC_MAP_TEVII_NEC;
ir->sampling = 0xff00; /* address */
break;
case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
ir_codes = RC_MAP_DNTV_LIVE_DVBT_PRO;
ir->sampling = 0xff00; /* address */
break;
case CX88_BOARD_NORWOOD_MICRO:
ir_codes = RC_MAP_NORWOOD;
ir->gpio_addr = MO_GP1_IO;
ir->mask_keycode = 0x0e;
ir->mask_keyup = 0x80;
ir->polling = 50; /* ms */
break;
case CX88_BOARD_NPGTECH_REALTV_TOP10FM:
ir_codes = RC_MAP_NPGTECH;
ir->gpio_addr = MO_GP0_IO;
ir->mask_keycode = 0xfa;
ir->polling = 50; /* ms */
break;
case CX88_BOARD_PINNACLE_PCTV_HD_800i:
ir_codes = RC_MAP_PINNACLE_PCTV_HD;
ir->sampling = 1;
break;
case CX88_BOARD_POWERCOLOR_REAL_ANGEL:
ir_codes = RC_MAP_POWERCOLOR_REAL_ANGEL;
ir->gpio_addr = MO_GP2_IO;
ir->mask_keycode = 0x7e;
ir->polling = 100; /* ms */
break;
case CX88_BOARD_TWINHAN_VP1027_DVBS:
ir_codes = RC_MAP_TWINHAN_VP1027_DVBS;
ir->sampling = 0xff00; /* address */
break;
}
if (!ir_codes) {
err = -ENODEV;
goto err_out_free;
}
/*
* The usage of mask_keycode were very convenient, due to several
* reasons. Among others, the scancode tables were using the scancode
* as the index elements. So, the less bits it was used, the smaller
* the table were stored. After the input changes, the better is to use
* the full scancodes, since it allows replacing the IR remote by
* another one. Unfortunately, there are still some hardware, like
* Pixelview Ultra Pro, where only part of the scancode is sent via
* GPIO. So, there's no way to get the full scancode. Due to that,
* hardware_mask were introduced here: it represents those hardware
* that has such limits.
*/
if (hardware_mask && !ir->mask_keycode)
ir->mask_keycode = hardware_mask;
/* init input device */
snprintf(ir->name, sizeof(ir->name), "cx88 IR (%s)", core->board.name);
snprintf(ir->phys, sizeof(ir->phys), "pci-%s/ir0", pci_name(pci));
dev->device_name = ir->name;
dev->input_phys = ir->phys;
dev->input_id.bustype = BUS_PCI;
dev->input_id.version = 1;
if (pci->subsystem_vendor) {
dev->input_id.vendor = pci->subsystem_vendor;
dev->input_id.product = pci->subsystem_device;
} else {
dev->input_id.vendor = pci->vendor;
dev->input_id.product = pci->device;
}
dev->dev.parent = &pci->dev;
dev->map_name = ir_codes;
dev->driver_name = MODULE_NAME;
dev->priv = core;
dev->open = cx88_ir_open;
dev->close = cx88_ir_close;
dev->scancode_mask = hardware_mask;
if (ir->sampling) {
dev->timeout = MS_TO_US(10); /* 10 ms */
} else {
dev->driver_type = RC_DRIVER_SCANCODE;
dev->allowed_protocols = rc_proto;
}
ir->core = core;
core->ir = ir;
/* all done */
err = rc_register_device(dev);
if (err)
goto err_out_free;
return 0;
err_out_free:
rc_free_device(dev);
core->ir = NULL;
kfree(ir);
return err;
}
int cx88_ir_fini(struct cx88_core *core)
{
struct cx88_IR *ir = core->ir;
/* skip detach on non attached boards */
if (!ir)
return 0;
cx88_ir_stop(core);
rc_unregister_device(ir->dev);
kfree(ir);
/* done */
core->ir = NULL;
return 0;
}
/* ---------------------------------------------------------------------- */
void cx88_ir_irq(struct cx88_core *core)
{
struct cx88_IR *ir = core->ir;
u32 samples;
unsigned int todo, bits;
struct ir_raw_event ev = {};
if (!ir || !ir->sampling)
return;
/*
* Samples are stored in a 32 bit register, oldest sample in
* the msb. A set bit represents space and an unset bit
* represents a pulse.
*/
samples = cx_read(MO_SAMPLE_IO);
if (samples == 0xff && ir->dev->idle)
return;
for (todo = 32; todo > 0; todo -= bits) {
ev.pulse = samples & 0x80000000 ? false : true;
bits = min(todo, 32U - fls(ev.pulse ? samples : ~samples));
ev.duration = (bits * (USEC_PER_SEC / 1000)) / ir_samplerate;
ir_raw_event_store_with_filter(ir->dev, &ev);
samples <<= bits;
}
ir_raw_event_handle(ir->dev);
}
static int get_key_pvr2000(struct IR_i2c *ir, enum rc_proto *protocol,
u32 *scancode, u8 *toggle)
{
int flags, code;
/* poll IR chip */
flags = i2c_smbus_read_byte_data(ir->c, 0x10);
if (flags < 0) {
dprintk("read error\n");
return 0;
}
/* key pressed ? */
if (0 == (flags & 0x80))
return 0;
/* read actual key code */
code = i2c_smbus_read_byte_data(ir->c, 0x00);
if (code < 0) {
dprintk("read error\n");
return 0;
}
dprintk("IR Key/Flags: (0x%02x/0x%02x)\n",
code & 0xff, flags & 0xff);
*protocol = RC_PROTO_UNKNOWN;
*scancode = code & 0xff;
*toggle = 0;
return 1;
}
void cx88_i2c_init_ir(struct cx88_core *core)
{
struct i2c_board_info info;
static const unsigned short default_addr_list[] = {
0x18, 0x33, 0x6b, 0x71,
I2C_CLIENT_END
};
static const unsigned short pvr2000_addr_list[] = {
0x18, 0x1a,
I2C_CLIENT_END
};
const unsigned short *addr_list = default_addr_list;
const unsigned short *addrp;
/* Instantiate the IR receiver device, if present */
if (core->i2c_rc != 0)
return;
memset(&info, 0, sizeof(struct i2c_board_info));
strscpy(info.type, "ir_video", I2C_NAME_SIZE);
switch (core->boardnr) {
case CX88_BOARD_LEADTEK_PVR2000:
addr_list = pvr2000_addr_list;
core->init_data.name = "cx88 Leadtek PVR 2000 remote";
core->init_data.type = RC_PROTO_BIT_UNKNOWN;
core->init_data.get_key = get_key_pvr2000;
core->init_data.ir_codes = RC_MAP_EMPTY;
break;
}
/*
* We can't call i2c_new_scanned_device() because it uses
* quick writes for probing and at least some RC receiver
* devices only reply to reads.
* Also, Hauppauge XVR needs to be specified, as address 0x71
* conflicts with another remote type used with saa7134
*/
for (addrp = addr_list; *addrp != I2C_CLIENT_END; addrp++) {
info.platform_data = NULL;
memset(&core->init_data, 0, sizeof(core->init_data));
if (*addrp == 0x71) {
/* Hauppauge Z8F0811 */
strscpy(info.type, "ir_z8f0811_haup", I2C_NAME_SIZE);
core->init_data.name = core->board.name;
core->init_data.ir_codes = RC_MAP_HAUPPAUGE;
core->init_data.type = RC_PROTO_BIT_RC5 |
RC_PROTO_BIT_RC6_MCE | RC_PROTO_BIT_RC6_6A_32;
core->init_data.internal_get_key_func = IR_KBD_GET_KEY_HAUP_XVR;
info.platform_data = &core->init_data;
}
if (i2c_smbus_xfer(&core->i2c_adap, *addrp, 0,
I2C_SMBUS_READ, 0,
I2C_SMBUS_QUICK, NULL) >= 0) {
info.addr = *addrp;
i2c_new_client_device(&core->i2c_adap, &info);
break;
}
}
}
/* ---------------------------------------------------------------------- */
MODULE_AUTHOR("Gerd Knorr, Pavel Machek, Chris Pascoe");
MODULE_DESCRIPTION("input driver for cx88 GPIO-based IR remote controls");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/pci/cx88/cx88-input.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Stereo and SAP detection for cx88
*
* Copyright (c) 2009 Marton Balint <[email protected]>
*/
#include "cx88.h"
#include "cx88-reg.h"
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/jiffies.h>
#include <asm/div64.h>
#define INT_PI ((s32)(3.141592653589 * 32768.0))
#define compat_remainder(a, b) \
((float)(((s32)((a) * 100)) % ((s32)((b) * 100))) / 100.0)
#define baseband_freq(carrier, srate, tone) ((s32)( \
(compat_remainder(carrier + tone, srate)) / srate * 2 * INT_PI))
/*
* We calculate the baseband frequencies of the carrier and the pilot tones
* based on the sampling rate of the audio rds fifo.
*/
#define FREQ_A2_CARRIER baseband_freq(54687.5, 2689.36, 0.0)
#define FREQ_A2_DUAL baseband_freq(54687.5, 2689.36, 274.1)
#define FREQ_A2_STEREO baseband_freq(54687.5, 2689.36, 117.5)
/*
* The frequencies below are from the reference driver. They probably need
* further adjustments, because they are not tested at all. You may even need
* to play a bit with the registers of the chip to select the proper signal
* for the input of the audio rds fifo, and measure it's sampling rate to
* calculate the proper baseband frequencies...
*/
#define FREQ_A2M_CARRIER ((s32)(2.114516 * 32768.0))
#define FREQ_A2M_DUAL ((s32)(2.754916 * 32768.0))
#define FREQ_A2M_STEREO ((s32)(2.462326 * 32768.0))
#define FREQ_EIAJ_CARRIER ((s32)(1.963495 * 32768.0)) /* 5pi/8 */
#define FREQ_EIAJ_DUAL ((s32)(2.562118 * 32768.0))
#define FREQ_EIAJ_STEREO ((s32)(2.601053 * 32768.0))
#define FREQ_BTSC_DUAL ((s32)(1.963495 * 32768.0)) /* 5pi/8 */
#define FREQ_BTSC_DUAL_REF ((s32)(1.374446 * 32768.0)) /* 7pi/16 */
#define FREQ_BTSC_SAP ((s32)(2.471532 * 32768.0))
#define FREQ_BTSC_SAP_REF ((s32)(1.730072 * 32768.0))
/* The spectrum of the signal should be empty between these frequencies. */
#define FREQ_NOISE_START ((s32)(0.100000 * 32768.0))
#define FREQ_NOISE_END ((s32)(1.200000 * 32768.0))
static unsigned int dsp_debug;
module_param(dsp_debug, int, 0644);
MODULE_PARM_DESC(dsp_debug, "enable audio dsp debug messages");
#define dprintk(level, fmt, arg...) do { \
if (dsp_debug >= level) \
printk(KERN_DEBUG pr_fmt("%s: dsp:" fmt), \
__func__, ##arg); \
} while (0)
static s32 int_cos(u32 x)
{
u32 t2, t4, t6, t8;
s32 ret;
u16 period = x / INT_PI;
if (period % 2)
return -int_cos(x - INT_PI);
x = x % INT_PI;
if (x > INT_PI / 2)
return -int_cos(INT_PI / 2 - (x % (INT_PI / 2)));
/*
* Now x is between 0 and INT_PI/2.
* To calculate cos(x) we use it's Taylor polinom.
*/
t2 = x * x / 32768 / 2;
t4 = t2 * x / 32768 * x / 32768 / 3 / 4;
t6 = t4 * x / 32768 * x / 32768 / 5 / 6;
t8 = t6 * x / 32768 * x / 32768 / 7 / 8;
ret = 32768 - t2 + t4 - t6 + t8;
return ret;
}
static u32 int_goertzel(s16 x[], u32 N, u32 freq)
{
/*
* We use the Goertzel algorithm to determine the power of the
* given frequency in the signal
*/
s32 s_prev = 0;
s32 s_prev2 = 0;
s32 coeff = 2 * int_cos(freq);
u32 i;
u64 tmp;
u32 divisor;
for (i = 0; i < N; i++) {
s32 s = x[i] + ((s64)coeff * s_prev / 32768) - s_prev2;
s_prev2 = s_prev;
s_prev = s;
}
tmp = (s64)s_prev2 * s_prev2 + (s64)s_prev * s_prev -
(s64)coeff * s_prev2 * s_prev / 32768;
/*
* XXX: N must be low enough so that N*N fits in s32.
* Else we need two divisions.
*/
divisor = N * N;
do_div(tmp, divisor);
return (u32)tmp;
}
static u32 freq_magnitude(s16 x[], u32 N, u32 freq)
{
u32 sum = int_goertzel(x, N, freq);
return (u32)int_sqrt(sum);
}
static u32 noise_magnitude(s16 x[], u32 N, u32 freq_start, u32 freq_end)
{
int i;
u32 sum = 0;
u32 freq_step;
int samples = 5;
if (N > 192) {
/* The last 192 samples are enough for noise detection */
x += (N - 192);
N = 192;
}
freq_step = (freq_end - freq_start) / (samples - 1);
for (i = 0; i < samples; i++) {
sum += int_goertzel(x, N, freq_start);
freq_start += freq_step;
}
return (u32)int_sqrt(sum / samples);
}
static s32 detect_a2_a2m_eiaj(struct cx88_core *core, s16 x[], u32 N)
{
s32 carrier, stereo, dual, noise;
s32 carrier_freq, stereo_freq, dual_freq;
s32 ret;
switch (core->tvaudio) {
case WW_BG:
case WW_DK:
carrier_freq = FREQ_A2_CARRIER;
stereo_freq = FREQ_A2_STEREO;
dual_freq = FREQ_A2_DUAL;
break;
case WW_M:
carrier_freq = FREQ_A2M_CARRIER;
stereo_freq = FREQ_A2M_STEREO;
dual_freq = FREQ_A2M_DUAL;
break;
case WW_EIAJ:
carrier_freq = FREQ_EIAJ_CARRIER;
stereo_freq = FREQ_EIAJ_STEREO;
dual_freq = FREQ_EIAJ_DUAL;
break;
default:
pr_warn("unsupported audio mode %d for %s\n",
core->tvaudio, __func__);
return UNSET;
}
carrier = freq_magnitude(x, N, carrier_freq);
stereo = freq_magnitude(x, N, stereo_freq);
dual = freq_magnitude(x, N, dual_freq);
noise = noise_magnitude(x, N, FREQ_NOISE_START, FREQ_NOISE_END);
dprintk(1,
"detect a2/a2m/eiaj: carrier=%d, stereo=%d, dual=%d, noise=%d\n",
carrier, stereo, dual, noise);
if (stereo > dual)
ret = V4L2_TUNER_SUB_STEREO;
else
ret = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
if (core->tvaudio == WW_EIAJ) {
/* EIAJ checks may need adjustments */
if ((carrier > max(stereo, dual) * 2) &&
(carrier < max(stereo, dual) * 6) &&
(carrier > 20 && carrier < 200) &&
(max(stereo, dual) > min(stereo, dual))) {
/*
* For EIAJ the carrier is always present,
* so we probably don't need noise detection
*/
return ret;
}
} else {
if ((carrier > max(stereo, dual) * 2) &&
(carrier < max(stereo, dual) * 8) &&
(carrier > 20 && carrier < 200) &&
(noise < 10) &&
(max(stereo, dual) > min(stereo, dual) * 2)) {
return ret;
}
}
return V4L2_TUNER_SUB_MONO;
}
static s32 detect_btsc(struct cx88_core *core, s16 x[], u32 N)
{
s32 sap_ref = freq_magnitude(x, N, FREQ_BTSC_SAP_REF);
s32 sap = freq_magnitude(x, N, FREQ_BTSC_SAP);
s32 dual_ref = freq_magnitude(x, N, FREQ_BTSC_DUAL_REF);
s32 dual = freq_magnitude(x, N, FREQ_BTSC_DUAL);
dprintk(1, "detect btsc: dual_ref=%d, dual=%d, sap_ref=%d, sap=%d\n",
dual_ref, dual, sap_ref, sap);
/* FIXME: Currently not supported */
return UNSET;
}
static s16 *read_rds_samples(struct cx88_core *core, u32 *N)
{
const struct sram_channel *srch = &cx88_sram_channels[SRAM_CH27];
s16 *samples;
unsigned int i;
unsigned int bpl = srch->fifo_size / AUD_RDS_LINES;
unsigned int spl = bpl / 4;
unsigned int sample_count = spl * (AUD_RDS_LINES - 1);
u32 current_address = cx_read(srch->ptr1_reg);
u32 offset = (current_address - srch->fifo_start + bpl);
dprintk(1,
"read RDS samples: current_address=%08x (offset=%08x), sample_count=%d, aud_intstat=%08x\n",
current_address,
current_address - srch->fifo_start, sample_count,
cx_read(MO_AUD_INTSTAT));
samples = kmalloc_array(sample_count, sizeof(*samples), GFP_KERNEL);
if (!samples)
return NULL;
*N = sample_count;
for (i = 0; i < sample_count; i++) {
offset = offset % (AUD_RDS_LINES * bpl);
samples[i] = cx_read(srch->fifo_start + offset);
offset += 4;
}
dprintk(2, "RDS samples dump: %*ph\n", sample_count, samples);
return samples;
}
s32 cx88_dsp_detect_stereo_sap(struct cx88_core *core)
{
s16 *samples;
u32 N = 0;
s32 ret = UNSET;
/* If audio RDS fifo is disabled, we can't read the samples */
if (!(cx_read(MO_AUD_DMACNTRL) & 0x04))
return ret;
if (!(cx_read(AUD_CTL) & EN_FMRADIO_EN_RDS))
return ret;
/* Wait at least 500 ms after an audio standard change */
if (time_before(jiffies, core->last_change + msecs_to_jiffies(500)))
return ret;
samples = read_rds_samples(core, &N);
if (!samples)
return ret;
switch (core->tvaudio) {
case WW_BG:
case WW_DK:
case WW_EIAJ:
case WW_M:
ret = detect_a2_a2m_eiaj(core, samples, N);
break;
case WW_BTSC:
ret = detect_btsc(core, samples, N);
break;
case WW_NONE:
case WW_I:
case WW_L:
case WW_I2SPT:
case WW_FM:
case WW_I2SADC:
break;
}
kfree(samples);
if (ret != UNSET)
dprintk(1, "stereo/sap detection result:%s%s%s\n",
(ret & V4L2_TUNER_SUB_MONO) ? " mono" : "",
(ret & V4L2_TUNER_SUB_STEREO) ? " stereo" : "",
(ret & V4L2_TUNER_SUB_LANG2) ? " dual" : "");
return ret;
}
EXPORT_SYMBOL(cx88_dsp_detect_stereo_sap);
| linux-master | drivers/media/pci/cx88/cx88-dsp.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* device driver for Conexant 2388x based TV cards
* MPEG Transport Stream (DVB) routines
*
* (c) 2004, 2005 Chris Pascoe <[email protected]>
* (c) 2004 Gerd Knorr <[email protected]> [SuSE Labs]
*/
#include "cx88.h"
#include "dvb-pll.h"
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/kthread.h>
#include <linux/file.h>
#include <linux/suspend.h>
#include <media/v4l2-common.h>
#include "mt352.h"
#include "mt352_priv.h"
#include "cx88-vp3054-i2c.h"
#include "zl10353.h"
#include "cx22702.h"
#include "or51132.h"
#include "lgdt330x.h"
#include "s5h1409.h"
#include "xc4000.h"
#include "xc5000.h"
#include "nxt200x.h"
#include "cx24123.h"
#include "isl6421.h"
#include "tuner-simple.h"
#include "tda9887.h"
#include "s5h1411.h"
#include "stv0299.h"
#include "z0194a.h"
#include "stv0288.h"
#include "stb6000.h"
#include "cx24116.h"
#include "stv0900.h"
#include "stb6100.h"
#include "stb6100_proc.h"
#include "mb86a16.h"
#include "ts2020.h"
#include "ds3000.h"
MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
MODULE_AUTHOR("Chris Pascoe <[email protected]>");
MODULE_AUTHOR("Gerd Knorr <[email protected]> [SuSE Labs]");
MODULE_LICENSE("GPL");
MODULE_VERSION(CX88_VERSION);
static unsigned int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable debug messages [dvb]");
static unsigned int dvb_buf_tscnt = 32;
module_param(dvb_buf_tscnt, int, 0644);
MODULE_PARM_DESC(dvb_buf_tscnt, "DVB Buffer TS count [dvb]");
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
#define dprintk(level, fmt, arg...) do { \
if (debug >= level) \
printk(KERN_DEBUG pr_fmt("%s: dvb:" fmt), \
__func__, ##arg); \
} while (0)
/* ------------------------------------------------------------------ */
static int queue_setup(struct vb2_queue *q,
unsigned int *num_buffers, unsigned int *num_planes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct cx8802_dev *dev = q->drv_priv;
*num_planes = 1;
dev->ts_packet_size = 188 * 4;
dev->ts_packet_count = dvb_buf_tscnt;
sizes[0] = dev->ts_packet_size * dev->ts_packet_count;
*num_buffers = dvb_buf_tscnt;
return 0;
}
static int buffer_prepare(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
return cx8802_buf_prepare(vb->vb2_queue, dev, buf);
}
static void buffer_finish(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
struct cx88_riscmem *risc = &buf->risc;
if (risc->cpu)
dma_free_coherent(&dev->pci->dev, risc->size, risc->cpu,
risc->dma);
memset(risc, 0, sizeof(*risc));
}
static void buffer_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
cx8802_buf_queue(dev, buf);
}
static int start_streaming(struct vb2_queue *q, unsigned int count)
{
struct cx8802_dev *dev = q->drv_priv;
struct cx88_dmaqueue *dmaq = &dev->mpegq;
struct cx88_buffer *buf;
buf = list_entry(dmaq->active.next, struct cx88_buffer, list);
cx8802_start_dma(dev, dmaq, buf);
return 0;
}
static void stop_streaming(struct vb2_queue *q)
{
struct cx8802_dev *dev = q->drv_priv;
struct cx88_dmaqueue *dmaq = &dev->mpegq;
unsigned long flags;
cx8802_cancel_buffers(dev);
spin_lock_irqsave(&dev->slock, flags);
while (!list_empty(&dmaq->active)) {
struct cx88_buffer *buf = list_entry(dmaq->active.next,
struct cx88_buffer, list);
list_del(&buf->list);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&dev->slock, flags);
}
static const struct vb2_ops dvb_qops = {
.queue_setup = queue_setup,
.buf_prepare = buffer_prepare,
.buf_finish = buffer_finish,
.buf_queue = buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = start_streaming,
.stop_streaming = stop_streaming,
};
/* ------------------------------------------------------------------ */
static int cx88_dvb_bus_ctrl(struct dvb_frontend *fe, int acquire)
{
struct cx8802_dev *dev = fe->dvb->priv;
struct cx8802_driver *drv = NULL;
int ret = 0;
int fe_id;
fe_id = vb2_dvb_find_frontend(&dev->frontends, fe);
if (!fe_id) {
pr_err("%s() No frontend found\n", __func__);
return -EINVAL;
}
mutex_lock(&dev->core->lock);
drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
if (drv) {
if (acquire) {
dev->frontends.active_fe_id = fe_id;
ret = drv->request_acquire(drv);
} else {
ret = drv->request_release(drv);
dev->frontends.active_fe_id = 0;
}
}
mutex_unlock(&dev->core->lock);
return ret;
}
static void cx88_dvb_gate_ctrl(struct cx88_core *core, int open)
{
struct vb2_dvb_frontends *f;
struct vb2_dvb_frontend *fe;
if (!core->dvbdev)
return;
f = &core->dvbdev->frontends;
if (!f)
return;
if (f->gate <= 1) /* undefined or fe0 */
fe = vb2_dvb_get_frontend(f, 1);
else
fe = vb2_dvb_get_frontend(f, f->gate);
if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
}
/* ------------------------------------------------------------------ */
static int dvico_fusionhdtv_demod_init(struct dvb_frontend *fe)
{
static const u8 clock_config[] = { CLOCK_CTL, 0x38, 0x39 };
static const u8 reset[] = { RESET, 0x80 };
static const u8 adc_ctl_1_cfg[] = { ADC_CTL_1, 0x40 };
static const u8 agc_cfg[] = { AGC_TARGET, 0x24, 0x20 };
static const u8 gpp_ctl_cfg[] = { GPP_CTL, 0x33 };
static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
mt352_write(fe, clock_config, sizeof(clock_config));
udelay(200);
mt352_write(fe, reset, sizeof(reset));
mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
mt352_write(fe, agc_cfg, sizeof(agc_cfg));
mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
return 0;
}
static int dvico_dual_demod_init(struct dvb_frontend *fe)
{
static const u8 clock_config[] = { CLOCK_CTL, 0x38, 0x38 };
static const u8 reset[] = { RESET, 0x80 };
static const u8 adc_ctl_1_cfg[] = { ADC_CTL_1, 0x40 };
static const u8 agc_cfg[] = { AGC_TARGET, 0x28, 0x20 };
static const u8 gpp_ctl_cfg[] = { GPP_CTL, 0x33 };
static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
mt352_write(fe, clock_config, sizeof(clock_config));
udelay(200);
mt352_write(fe, reset, sizeof(reset));
mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
mt352_write(fe, agc_cfg, sizeof(agc_cfg));
mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
return 0;
}
static int dntv_live_dvbt_demod_init(struct dvb_frontend *fe)
{
static const u8 clock_config[] = { 0x89, 0x38, 0x39 };
static const u8 reset[] = { 0x50, 0x80 };
static const u8 adc_ctl_1_cfg[] = { 0x8E, 0x40 };
static const u8 agc_cfg[] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
0x00, 0xFF, 0x00, 0x40, 0x40 };
static const u8 dntv_extra[] = { 0xB5, 0x7A };
static const u8 capt_range_cfg[] = { 0x75, 0x32 };
mt352_write(fe, clock_config, sizeof(clock_config));
udelay(2000);
mt352_write(fe, reset, sizeof(reset));
mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
mt352_write(fe, agc_cfg, sizeof(agc_cfg));
udelay(2000);
mt352_write(fe, dntv_extra, sizeof(dntv_extra));
mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
return 0;
}
static const struct mt352_config dvico_fusionhdtv = {
.demod_address = 0x0f,
.demod_init = dvico_fusionhdtv_demod_init,
};
static const struct mt352_config dntv_live_dvbt_config = {
.demod_address = 0x0f,
.demod_init = dntv_live_dvbt_demod_init,
};
static const struct mt352_config dvico_fusionhdtv_dual = {
.demod_address = 0x0f,
.demod_init = dvico_dual_demod_init,
};
static const struct zl10353_config cx88_terratec_cinergy_ht_pci_mkii_config = {
.demod_address = (0x1e >> 1),
.no_tuner = 1,
.if2 = 45600,
};
static const struct mb86a16_config twinhan_vp1027 = {
.demod_address = 0x08,
};
#if IS_ENABLED(CONFIG_VIDEO_CX88_VP3054)
static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend *fe)
{
static const u8 clock_config[] = { 0x89, 0x38, 0x38 };
static const u8 reset[] = { 0x50, 0x80 };
static const u8 adc_ctl_1_cfg[] = { 0x8E, 0x40 };
static const u8 agc_cfg[] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
0x00, 0xFF, 0x00, 0x40, 0x40 };
static const u8 dntv_extra[] = { 0xB5, 0x7A };
static const u8 capt_range_cfg[] = { 0x75, 0x32 };
mt352_write(fe, clock_config, sizeof(clock_config));
udelay(2000);
mt352_write(fe, reset, sizeof(reset));
mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
mt352_write(fe, agc_cfg, sizeof(agc_cfg));
udelay(2000);
mt352_write(fe, dntv_extra, sizeof(dntv_extra));
mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
return 0;
}
static const struct mt352_config dntv_live_dvbt_pro_config = {
.demod_address = 0x0f,
.no_tuner = 1,
.demod_init = dntv_live_dvbt_pro_demod_init,
};
#endif
static const struct zl10353_config dvico_fusionhdtv_hybrid = {
.demod_address = 0x0f,
.no_tuner = 1,
};
static const struct zl10353_config dvico_fusionhdtv_xc3028 = {
.demod_address = 0x0f,
.if2 = 45600,
.no_tuner = 1,
};
static const struct mt352_config dvico_fusionhdtv_mt352_xc3028 = {
.demod_address = 0x0f,
.if2 = 4560,
.no_tuner = 1,
.demod_init = dvico_fusionhdtv_demod_init,
};
static const struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
.demod_address = 0x0f,
};
static const struct cx22702_config connexant_refboard_config = {
.demod_address = 0x43,
.output_mode = CX22702_SERIAL_OUTPUT,
};
static const struct cx22702_config hauppauge_hvr_config = {
.demod_address = 0x63,
.output_mode = CX22702_SERIAL_OUTPUT,
};
static int or51132_set_ts_param(struct dvb_frontend *fe, int is_punctured)
{
struct cx8802_dev *dev = fe->dvb->priv;
dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
return 0;
}
static const struct or51132_config pchdtv_hd3000 = {
.demod_address = 0x15,
.set_ts_params = or51132_set_ts_param,
};
static int lgdt330x_pll_rf_set(struct dvb_frontend *fe, int index)
{
struct cx8802_dev *dev = fe->dvb->priv;
struct cx88_core *core = dev->core;
dprintk(1, "%s: index = %d\n", __func__, index);
if (index == 0)
cx_clear(MO_GP0_IO, 8);
else
cx_set(MO_GP0_IO, 8);
return 0;
}
static int lgdt330x_set_ts_param(struct dvb_frontend *fe, int is_punctured)
{
struct cx8802_dev *dev = fe->dvb->priv;
if (is_punctured)
dev->ts_gen_cntrl |= 0x04;
else
dev->ts_gen_cntrl &= ~0x04;
return 0;
}
static struct lgdt330x_config fusionhdtv_3_gold = {
.demod_chip = LGDT3302,
.serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
.set_ts_params = lgdt330x_set_ts_param,
};
static const struct lgdt330x_config fusionhdtv_5_gold = {
.demod_chip = LGDT3303,
.serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
.set_ts_params = lgdt330x_set_ts_param,
};
static const struct lgdt330x_config pchdtv_hd5500 = {
.demod_chip = LGDT3303,
.serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
.set_ts_params = lgdt330x_set_ts_param,
};
static int nxt200x_set_ts_param(struct dvb_frontend *fe, int is_punctured)
{
struct cx8802_dev *dev = fe->dvb->priv;
dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
return 0;
}
static const struct nxt200x_config ati_hdtvwonder = {
.demod_address = 0x0a,
.set_ts_params = nxt200x_set_ts_param,
};
static int cx24123_set_ts_param(struct dvb_frontend *fe,
int is_punctured)
{
struct cx8802_dev *dev = fe->dvb->priv;
dev->ts_gen_cntrl = 0x02;
return 0;
}
static int kworld_dvbs_100_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx8802_dev *dev = fe->dvb->priv;
struct cx88_core *core = dev->core;
if (voltage == SEC_VOLTAGE_OFF)
cx_write(MO_GP0_IO, 0x000006fb);
else
cx_write(MO_GP0_IO, 0x000006f9);
if (core->prev_set_voltage)
return core->prev_set_voltage(fe, voltage);
return 0;
}
static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx8802_dev *dev = fe->dvb->priv;
struct cx88_core *core = dev->core;
if (voltage == SEC_VOLTAGE_OFF) {
dprintk(1, "LNB Voltage OFF\n");
cx_write(MO_GP0_IO, 0x0000efff);
}
if (core->prev_set_voltage)
return core->prev_set_voltage(fe, voltage);
return 0;
}
static int tevii_dvbs_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx8802_dev *dev = fe->dvb->priv;
struct cx88_core *core = dev->core;
cx_set(MO_GP0_IO, 0x6040);
switch (voltage) {
case SEC_VOLTAGE_13:
cx_clear(MO_GP0_IO, 0x20);
break;
case SEC_VOLTAGE_18:
cx_set(MO_GP0_IO, 0x20);
break;
case SEC_VOLTAGE_OFF:
cx_clear(MO_GP0_IO, 0x20);
break;
}
if (core->prev_set_voltage)
return core->prev_set_voltage(fe, voltage);
return 0;
}
static int vp1027_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx8802_dev *dev = fe->dvb->priv;
struct cx88_core *core = dev->core;
switch (voltage) {
case SEC_VOLTAGE_13:
dprintk(1, "LNB SEC Voltage=13\n");
cx_write(MO_GP0_IO, 0x00001220);
break;
case SEC_VOLTAGE_18:
dprintk(1, "LNB SEC Voltage=18\n");
cx_write(MO_GP0_IO, 0x00001222);
break;
case SEC_VOLTAGE_OFF:
dprintk(1, "LNB Voltage OFF\n");
cx_write(MO_GP0_IO, 0x00001230);
break;
}
if (core->prev_set_voltage)
return core->prev_set_voltage(fe, voltage);
return 0;
}
static const struct cx24123_config geniatech_dvbs_config = {
.demod_address = 0x55,
.set_ts_params = cx24123_set_ts_param,
};
static const struct cx24123_config hauppauge_novas_config = {
.demod_address = 0x55,
.set_ts_params = cx24123_set_ts_param,
};
static const struct cx24123_config kworld_dvbs_100_config = {
.demod_address = 0x15,
.set_ts_params = cx24123_set_ts_param,
.lnb_polarity = 1,
};
static const struct s5h1409_config pinnacle_pctv_hd_800i_config = {
.demod_address = 0x32 >> 1,
.output_mode = S5H1409_PARALLEL_OUTPUT,
.gpio = S5H1409_GPIO_ON,
.qam_if = 44000,
.inversion = S5H1409_INVERSION_OFF,
.status_mode = S5H1409_DEMODLOCKING,
.mpeg_timing = S5H1409_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK,
};
static const struct s5h1409_config dvico_hdtv5_pci_nano_config = {
.demod_address = 0x32 >> 1,
.output_mode = S5H1409_SERIAL_OUTPUT,
.gpio = S5H1409_GPIO_OFF,
.inversion = S5H1409_INVERSION_OFF,
.status_mode = S5H1409_DEMODLOCKING,
.mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static const struct s5h1409_config kworld_atsc_120_config = {
.demod_address = 0x32 >> 1,
.output_mode = S5H1409_SERIAL_OUTPUT,
.gpio = S5H1409_GPIO_OFF,
.inversion = S5H1409_INVERSION_OFF,
.status_mode = S5H1409_DEMODLOCKING,
.mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static const struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = {
.i2c_address = 0x64,
.if_khz = 5380,
};
static const struct zl10353_config cx88_pinnacle_hybrid_pctv = {
.demod_address = (0x1e >> 1),
.no_tuner = 1,
.if2 = 45600,
};
static const struct zl10353_config cx88_geniatech_x8000_mt = {
.demod_address = (0x1e >> 1),
.no_tuner = 1,
.disable_i2c_gate_ctrl = 1,
};
static const struct s5h1411_config dvico_fusionhdtv7_config = {
.output_mode = S5H1411_SERIAL_OUTPUT,
.gpio = S5H1411_GPIO_ON,
.mpeg_timing = S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
.qam_if = S5H1411_IF_44000,
.vsb_if = S5H1411_IF_44000,
.inversion = S5H1411_INVERSION_OFF,
.status_mode = S5H1411_DEMODLOCKING
};
static const struct xc5000_config dvico_fusionhdtv7_tuner_config = {
.i2c_address = 0xc2 >> 1,
.if_khz = 5380,
};
static int attach_xc3028(u8 addr, struct cx8802_dev *dev)
{
struct dvb_frontend *fe;
struct vb2_dvb_frontend *fe0 = NULL;
struct xc2028_ctrl ctl;
struct xc2028_config cfg = {
.i2c_adap = &dev->core->i2c_adap,
.i2c_addr = addr,
.ctrl = &ctl,
};
/* Get the first frontend */
fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
if (!fe0)
return -EINVAL;
if (!fe0->dvb.frontend) {
pr_err("dvb frontend not attached. Can't attach xc3028\n");
return -EINVAL;
}
/*
* Some xc3028 devices may be hidden by an I2C gate. This is known
* to happen with some s5h1409-based devices.
* Now that I2C gate is open, sets up xc3028 configuration
*/
cx88_setup_xc3028(dev->core, &ctl);
fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, &cfg);
if (!fe) {
pr_err("xc3028 attach failed\n");
dvb_frontend_detach(fe0->dvb.frontend);
dvb_unregister_frontend(fe0->dvb.frontend);
fe0->dvb.frontend = NULL;
return -EINVAL;
}
pr_info("xc3028 attached\n");
return 0;
}
static int attach_xc4000(struct cx8802_dev *dev, struct xc4000_config *cfg)
{
struct dvb_frontend *fe;
struct vb2_dvb_frontend *fe0 = NULL;
/* Get the first frontend */
fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
if (!fe0)
return -EINVAL;
if (!fe0->dvb.frontend) {
pr_err("dvb frontend not attached. Can't attach xc4000\n");
return -EINVAL;
}
fe = dvb_attach(xc4000_attach, fe0->dvb.frontend, &dev->core->i2c_adap,
cfg);
if (!fe) {
pr_err("xc4000 attach failed\n");
dvb_frontend_detach(fe0->dvb.frontend);
dvb_unregister_frontend(fe0->dvb.frontend);
fe0->dvb.frontend = NULL;
return -EINVAL;
}
pr_info("xc4000 attached\n");
return 0;
}
static int cx24116_set_ts_param(struct dvb_frontend *fe,
int is_punctured)
{
struct cx8802_dev *dev = fe->dvb->priv;
dev->ts_gen_cntrl = 0x2;
return 0;
}
static int stv0900_set_ts_param(struct dvb_frontend *fe,
int is_punctured)
{
struct cx8802_dev *dev = fe->dvb->priv;
dev->ts_gen_cntrl = 0;
return 0;
}
static int cx24116_reset_device(struct dvb_frontend *fe)
{
struct cx8802_dev *dev = fe->dvb->priv;
struct cx88_core *core = dev->core;
/* Reset the part */
/* Put the cx24116 into reset */
cx_write(MO_SRST_IO, 0);
usleep_range(10000, 20000);
/* Take the cx24116 out of reset */
cx_write(MO_SRST_IO, 1);
usleep_range(10000, 20000);
return 0;
}
static const struct cx24116_config hauppauge_hvr4000_config = {
.demod_address = 0x05,
.set_ts_params = cx24116_set_ts_param,
.reset_device = cx24116_reset_device,
};
static const struct cx24116_config tevii_s460_config = {
.demod_address = 0x55,
.set_ts_params = cx24116_set_ts_param,
.reset_device = cx24116_reset_device,
};
static int ds3000_set_ts_param(struct dvb_frontend *fe,
int is_punctured)
{
struct cx8802_dev *dev = fe->dvb->priv;
dev->ts_gen_cntrl = 4;
return 0;
}
static struct ds3000_config tevii_ds3000_config = {
.demod_address = 0x68,
.set_ts_params = ds3000_set_ts_param,
};
static struct ts2020_config tevii_ts2020_config = {
.tuner_address = 0x60,
.clk_out_div = 1,
};
static const struct stv0900_config prof_7301_stv0900_config = {
.demod_address = 0x6a,
/* demod_mode = 0,*/
.xtal = 27000000,
.clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
.diseqc_mode = 2,/* 2/3 PWM */
.tun1_maddress = 0,/* 0x60 */
.tun1_adc = 0,/* 2 Vpp */
.path1_mode = 3,
.set_ts_params = stv0900_set_ts_param,
};
static const struct stb6100_config prof_7301_stb6100_config = {
.tuner_address = 0x60,
.refclock = 27000000,
};
static const struct stv0299_config tevii_tuner_sharp_config = {
.demod_address = 0x68,
.inittab = sharp_z0194a_inittab,
.mclk = 88000000UL,
.invert = 1,
.skip_reinit = 0,
.lock_output = 1,
.volt13_op0_op1 = STV0299_VOLT13_OP1,
.min_delay_ms = 100,
.set_symbol_rate = sharp_z0194a_set_symbol_rate,
.set_ts_params = cx24116_set_ts_param,
};
static const struct stv0288_config tevii_tuner_earda_config = {
.demod_address = 0x68,
.min_delay_ms = 100,
.set_ts_params = cx24116_set_ts_param,
};
static int cx8802_alloc_frontends(struct cx8802_dev *dev)
{
struct cx88_core *core = dev->core;
struct vb2_dvb_frontend *fe = NULL;
int i;
mutex_init(&dev->frontends.lock);
INIT_LIST_HEAD(&dev->frontends.felist);
if (!core->board.num_frontends)
return -ENODEV;
pr_info("%s: allocating %d frontend(s)\n", __func__,
core->board.num_frontends);
for (i = 1; i <= core->board.num_frontends; i++) {
fe = vb2_dvb_alloc_frontend(&dev->frontends, i);
if (!fe) {
pr_err("%s() failed to alloc\n", __func__);
vb2_dvb_dealloc_frontends(&dev->frontends);
return -ENOMEM;
}
}
return 0;
}
static const u8 samsung_smt_7020_inittab[] = {
0x01, 0x15,
0x02, 0x00,
0x03, 0x00,
0x04, 0x7D,
0x05, 0x0F,
0x06, 0x02,
0x07, 0x00,
0x08, 0x60,
0x0A, 0xC2,
0x0B, 0x00,
0x0C, 0x01,
0x0D, 0x81,
0x0E, 0x44,
0x0F, 0x09,
0x10, 0x3C,
0x11, 0x84,
0x12, 0xDA,
0x13, 0x99,
0x14, 0x8D,
0x15, 0xCE,
0x16, 0xE8,
0x17, 0x43,
0x18, 0x1C,
0x19, 0x1B,
0x1A, 0x1D,
0x1C, 0x12,
0x1D, 0x00,
0x1E, 0x00,
0x1F, 0x00,
0x20, 0x00,
0x21, 0x00,
0x22, 0x00,
0x23, 0x00,
0x28, 0x02,
0x29, 0x28,
0x2A, 0x14,
0x2B, 0x0F,
0x2C, 0x09,
0x2D, 0x05,
0x31, 0x1F,
0x32, 0x19,
0x33, 0xFC,
0x34, 0x13,
0xff, 0xff,
};
static int samsung_smt_7020_tuner_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct cx8802_dev *dev = fe->dvb->priv;
u8 buf[4];
u32 div;
struct i2c_msg msg = {
.addr = 0x61,
.flags = 0,
.buf = buf,
.len = sizeof(buf) };
div = c->frequency / 125;
buf[0] = (div >> 8) & 0x7f;
buf[1] = div & 0xff;
buf[2] = 0x84; /* 0xC4 */
buf[3] = 0x00;
if (c->frequency < 1500000)
buf[3] |= 0x10;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(&dev->core->i2c_adap, &msg, 1) != 1)
return -EIO;
return 0;
}
static int samsung_smt_7020_set_tone(struct dvb_frontend *fe,
enum fe_sec_tone_mode tone)
{
struct cx8802_dev *dev = fe->dvb->priv;
struct cx88_core *core = dev->core;
cx_set(MO_GP0_IO, 0x0800);
switch (tone) {
case SEC_TONE_ON:
cx_set(MO_GP0_IO, 0x08);
break;
case SEC_TONE_OFF:
cx_clear(MO_GP0_IO, 0x08);
break;
default:
return -EINVAL;
}
return 0;
}
static int samsung_smt_7020_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct cx8802_dev *dev = fe->dvb->priv;
struct cx88_core *core = dev->core;
u8 data;
struct i2c_msg msg = {
.addr = 8,
.flags = 0,
.buf = &data,
.len = sizeof(data) };
cx_set(MO_GP0_IO, 0x8000);
switch (voltage) {
case SEC_VOLTAGE_OFF:
break;
case SEC_VOLTAGE_13:
data = ISL6421_EN1 | ISL6421_LLC1;
cx_clear(MO_GP0_IO, 0x80);
break;
case SEC_VOLTAGE_18:
data = ISL6421_EN1 | ISL6421_LLC1 | ISL6421_VSEL1;
cx_clear(MO_GP0_IO, 0x80);
break;
default:
return -EINVAL;
}
return (i2c_transfer(&dev->core->i2c_adap, &msg, 1) == 1) ? 0 : -EIO;
}
static int samsung_smt_7020_stv0299_set_symbol_rate(struct dvb_frontend *fe,
u32 srate, u32 ratio)
{
u8 aclk = 0;
u8 bclk = 0;
if (srate < 1500000) {
aclk = 0xb7;
bclk = 0x47;
} else if (srate < 3000000) {
aclk = 0xb7;
bclk = 0x4b;
} else if (srate < 7000000) {
aclk = 0xb7;
bclk = 0x4f;
} else if (srate < 14000000) {
aclk = 0xb7;
bclk = 0x53;
} else if (srate < 30000000) {
aclk = 0xb6;
bclk = 0x53;
} else if (srate < 45000000) {
aclk = 0xb4;
bclk = 0x51;
}
stv0299_writereg(fe, 0x13, aclk);
stv0299_writereg(fe, 0x14, bclk);
stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
stv0299_writereg(fe, 0x21, ratio & 0xf0);
return 0;
}
static const struct stv0299_config samsung_stv0299_config = {
.demod_address = 0x68,
.inittab = samsung_smt_7020_inittab,
.mclk = 88000000UL,
.invert = 0,
.skip_reinit = 0,
.lock_output = STV0299_LOCKOUTPUT_LK,
.volt13_op0_op1 = STV0299_VOLT13_OP1,
.min_delay_ms = 100,
.set_symbol_rate = samsung_smt_7020_stv0299_set_symbol_rate,
};
static int dvb_register(struct cx8802_dev *dev)
{
struct cx88_core *core = dev->core;
struct vb2_dvb_frontend *fe0, *fe1 = NULL;
int mfe_shared = 0; /* bus not shared by default */
int res = -EINVAL;
if (core->i2c_rc != 0) {
pr_err("no i2c-bus available, cannot attach dvb drivers\n");
goto frontend_detach;
}
/* Get the first frontend */
fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
if (!fe0)
goto frontend_detach;
/* multi-frontend gate control is undefined or defaults to fe0 */
dev->frontends.gate = 0;
/* Sets the gate control callback to be used by i2c command calls */
core->gate_ctrl = cx88_dvb_gate_ctrl;
/* init frontend(s) */
switch (core->boardnr) {
case CX88_BOARD_HAUPPAUGE_DVB_T1:
fe0->dvb.frontend = dvb_attach(cx22702_attach,
&connexant_refboard_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0x61, &core->i2c_adap,
DVB_PLL_THOMSON_DTT759X))
goto frontend_detach;
}
break;
case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
case CX88_BOARD_CONEXANT_DVB_T1:
case CX88_BOARD_KWORLD_DVB_T_CX22702:
case CX88_BOARD_WINFAST_DTV1000:
fe0->dvb.frontend = dvb_attach(cx22702_attach,
&connexant_refboard_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0x60, &core->i2c_adap,
DVB_PLL_THOMSON_DTT7579))
goto frontend_detach;
}
break;
case CX88_BOARD_WINFAST_DTV2000H:
case CX88_BOARD_HAUPPAUGE_HVR1100:
case CX88_BOARD_HAUPPAUGE_HVR1100LP:
case CX88_BOARD_HAUPPAUGE_HVR1300:
fe0->dvb.frontend = dvb_attach(cx22702_attach,
&hauppauge_hvr_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x61,
TUNER_PHILIPS_FMD1216ME_MK3))
goto frontend_detach;
}
break;
case CX88_BOARD_WINFAST_DTV2000H_J:
fe0->dvb.frontend = dvb_attach(cx22702_attach,
&hauppauge_hvr_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x61,
TUNER_PHILIPS_FMD1216MEX_MK3))
goto frontend_detach;
}
break;
case CX88_BOARD_HAUPPAUGE_HVR3000:
/* MFE frontend 1 */
mfe_shared = 1;
dev->frontends.gate = 2;
/* DVB-S init */
fe0->dvb.frontend = dvb_attach(cx24123_attach,
&hauppauge_novas_config,
&dev->core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(isl6421_attach,
fe0->dvb.frontend,
&dev->core->i2c_adap,
0x08, ISL6421_DCL, 0x00, false))
goto frontend_detach;
}
/* MFE frontend 2 */
fe1 = vb2_dvb_get_frontend(&dev->frontends, 2);
if (!fe1)
goto frontend_detach;
/* DVB-T init */
fe1->dvb.frontend = dvb_attach(cx22702_attach,
&hauppauge_hvr_config,
&dev->core->i2c_adap);
if (fe1->dvb.frontend) {
fe1->dvb.frontend->id = 1;
if (!dvb_attach(simple_tuner_attach,
fe1->dvb.frontend,
&dev->core->i2c_adap,
0x61, TUNER_PHILIPS_FMD1216ME_MK3))
goto frontend_detach;
}
break;
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
fe0->dvb.frontend = dvb_attach(mt352_attach,
&dvico_fusionhdtv,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0x60, NULL, DVB_PLL_THOMSON_DTT7579))
goto frontend_detach;
break;
}
/* ZL10353 replaces MT352 on later cards */
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&dvico_fusionhdtv_plus_v1_1,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0x60, NULL, DVB_PLL_THOMSON_DTT7579))
goto frontend_detach;
}
break;
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
/*
* The tin box says DEE1601, but it seems to be DTT7579
* compatible, with a slightly different MT352 AGC gain.
*/
fe0->dvb.frontend = dvb_attach(mt352_attach,
&dvico_fusionhdtv_dual,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0x61, NULL, DVB_PLL_THOMSON_DTT7579))
goto frontend_detach;
break;
}
/* ZL10353 replaces MT352 on later cards */
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&dvico_fusionhdtv_plus_v1_1,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0x61, NULL, DVB_PLL_THOMSON_DTT7579))
goto frontend_detach;
}
break;
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
fe0->dvb.frontend = dvb_attach(mt352_attach,
&dvico_fusionhdtv,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0x61, NULL, DVB_PLL_LG_Z201))
goto frontend_detach;
}
break;
case CX88_BOARD_KWORLD_DVB_T:
case CX88_BOARD_DNTV_LIVE_DVB_T:
case CX88_BOARD_ADSTECH_DVB_T_PCI:
fe0->dvb.frontend = dvb_attach(mt352_attach,
&dntv_live_dvbt_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0x61, NULL, DVB_PLL_UNKNOWN_1))
goto frontend_detach;
}
break;
case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
#if IS_ENABLED(CONFIG_VIDEO_CX88_VP3054)
/* MT352 is on a secondary I2C bus made from some GPIO lines */
fe0->dvb.frontend = dvb_attach(mt352_attach,
&dntv_live_dvbt_pro_config,
&dev->vp3054->adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x61,
TUNER_PHILIPS_FMD1216ME_MK3))
goto frontend_detach;
}
#else
pr_err("built without vp3054 support\n");
#endif
break;
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&dvico_fusionhdtv_hybrid,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x61,
TUNER_THOMSON_FE6600))
goto frontend_detach;
}
break;
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&dvico_fusionhdtv_xc3028,
&core->i2c_adap);
if (!fe0->dvb.frontend)
fe0->dvb.frontend = dvb_attach(mt352_attach,
&dvico_fusionhdtv_mt352_xc3028,
&core->i2c_adap);
/*
* On this board, the demod provides the I2C bus pullup.
* We must not permit gate_ctrl to be performed, or
* the xc3028 cannot communicate on the bus.
*/
if (fe0->dvb.frontend)
fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
if (attach_xc3028(0x61, dev) < 0)
goto frontend_detach;
break;
case CX88_BOARD_PCHDTV_HD3000:
fe0->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x61,
TUNER_THOMSON_DTT761X))
goto frontend_detach;
}
break;
case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
dev->ts_gen_cntrl = 0x08;
/* Do a hardware reset of chip before using it. */
cx_clear(MO_GP0_IO, 1);
msleep(100);
cx_set(MO_GP0_IO, 1);
msleep(200);
/* Select RF connector callback */
fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
&fusionhdtv_3_gold,
0x0e,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x61,
TUNER_MICROTUNE_4042FI5))
goto frontend_detach;
}
break;
case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
dev->ts_gen_cntrl = 0x08;
/* Do a hardware reset of chip before using it. */
cx_clear(MO_GP0_IO, 1);
msleep(100);
cx_set(MO_GP0_IO, 9);
msleep(200);
fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
&fusionhdtv_3_gold,
0x0e,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x61,
TUNER_THOMSON_DTT761X))
goto frontend_detach;
}
break;
case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
dev->ts_gen_cntrl = 0x08;
/* Do a hardware reset of chip before using it. */
cx_clear(MO_GP0_IO, 1);
msleep(100);
cx_set(MO_GP0_IO, 1);
msleep(200);
fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
&fusionhdtv_5_gold,
0x0e,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x61,
TUNER_LG_TDVS_H06XF))
goto frontend_detach;
if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x43))
goto frontend_detach;
}
break;
case CX88_BOARD_PCHDTV_HD5500:
dev->ts_gen_cntrl = 0x08;
/* Do a hardware reset of chip before using it. */
cx_clear(MO_GP0_IO, 1);
msleep(100);
cx_set(MO_GP0_IO, 1);
msleep(200);
fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
&pchdtv_hd5500,
0x59,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x61,
TUNER_LG_TDVS_H06XF))
goto frontend_detach;
if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x43))
goto frontend_detach;
}
break;
case CX88_BOARD_ATI_HDTVWONDER:
fe0->dvb.frontend = dvb_attach(nxt200x_attach,
&ati_hdtvwonder,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x61,
TUNER_PHILIPS_TUV1236D))
goto frontend_detach;
}
break;
case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
fe0->dvb.frontend = dvb_attach(cx24123_attach,
&hauppauge_novas_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
bool override_tone;
if (core->model == 92001)
override_tone = true;
else
override_tone = false;
if (!dvb_attach(isl6421_attach, fe0->dvb.frontend,
&core->i2c_adap, 0x08, ISL6421_DCL,
0x00, override_tone))
goto frontend_detach;
}
break;
case CX88_BOARD_KWORLD_DVBS_100:
fe0->dvb.frontend = dvb_attach(cx24123_attach,
&kworld_dvbs_100_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
fe0->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
}
break;
case CX88_BOARD_GENIATECH_DVBS:
fe0->dvb.frontend = dvb_attach(cx24123_attach,
&geniatech_dvbs_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
fe0->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
}
break;
case CX88_BOARD_PINNACLE_PCTV_HD_800i:
fe0->dvb.frontend = dvb_attach(s5h1409_attach,
&pinnacle_pctv_hd_800i_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
&core->i2c_adap,
&pinnacle_pctv_hd_800i_tuner_config))
goto frontend_detach;
}
break;
case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
fe0->dvb.frontend = dvb_attach(s5h1409_attach,
&dvico_hdtv5_pci_nano_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
struct dvb_frontend *fe;
struct xc2028_config cfg = {
.i2c_adap = &core->i2c_adap,
.i2c_addr = 0x61,
};
static struct xc2028_ctrl ctl = {
.fname = XC2028_DEFAULT_FIRMWARE,
.max_len = 64,
.scode_table = XC3028_FE_OREN538,
};
fe = dvb_attach(xc2028_attach,
fe0->dvb.frontend, &cfg);
if (fe && fe->ops.tuner_ops.set_config)
fe->ops.tuner_ops.set_config(fe, &ctl);
}
break;
case CX88_BOARD_NOTONLYTV_LV3H:
case CX88_BOARD_PINNACLE_HYBRID_PCTV:
case CX88_BOARD_WINFAST_DTV1800H:
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&cx88_pinnacle_hybrid_pctv,
&core->i2c_adap);
if (fe0->dvb.frontend) {
fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
if (attach_xc3028(0x61, dev) < 0)
goto frontend_detach;
}
break;
case CX88_BOARD_WINFAST_DTV1800H_XC4000:
case CX88_BOARD_WINFAST_DTV2000H_PLUS:
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&cx88_pinnacle_hybrid_pctv,
&core->i2c_adap);
if (fe0->dvb.frontend) {
struct xc4000_config cfg = {
.i2c_address = 0x61,
.default_pm = 0,
.dvb_amplitude = 134,
.set_smoothedcvbs = 1,
.if_khz = 4560
};
fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
if (attach_xc4000(dev, &cfg) < 0)
goto frontend_detach;
}
break;
case CX88_BOARD_GENIATECH_X8000_MT:
dev->ts_gen_cntrl = 0x00;
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&cx88_geniatech_x8000_mt,
&core->i2c_adap);
if (attach_xc3028(0x61, dev) < 0)
goto frontend_detach;
break;
case CX88_BOARD_KWORLD_ATSC_120:
fe0->dvb.frontend = dvb_attach(s5h1409_attach,
&kworld_atsc_120_config,
&core->i2c_adap);
if (attach_xc3028(0x61, dev) < 0)
goto frontend_detach;
break;
case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD:
fe0->dvb.frontend = dvb_attach(s5h1411_attach,
&dvico_fusionhdtv7_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
&core->i2c_adap,
&dvico_fusionhdtv7_tuner_config))
goto frontend_detach;
}
break;
case CX88_BOARD_HAUPPAUGE_HVR4000:
/* MFE frontend 1 */
mfe_shared = 1;
dev->frontends.gate = 2;
/* DVB-S/S2 Init */
fe0->dvb.frontend = dvb_attach(cx24116_attach,
&hauppauge_hvr4000_config,
&dev->core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(isl6421_attach,
fe0->dvb.frontend,
&dev->core->i2c_adap,
0x08, ISL6421_DCL, 0x00, false))
goto frontend_detach;
}
/* MFE frontend 2 */
fe1 = vb2_dvb_get_frontend(&dev->frontends, 2);
if (!fe1)
goto frontend_detach;
/* DVB-T Init */
fe1->dvb.frontend = dvb_attach(cx22702_attach,
&hauppauge_hvr_config,
&dev->core->i2c_adap);
if (fe1->dvb.frontend) {
fe1->dvb.frontend->id = 1;
if (!dvb_attach(simple_tuner_attach,
fe1->dvb.frontend,
&dev->core->i2c_adap,
0x61, TUNER_PHILIPS_FMD1216ME_MK3))
goto frontend_detach;
}
break;
case CX88_BOARD_HAUPPAUGE_HVR4000LITE:
fe0->dvb.frontend = dvb_attach(cx24116_attach,
&hauppauge_hvr4000_config,
&dev->core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(isl6421_attach,
fe0->dvb.frontend,
&dev->core->i2c_adap,
0x08, ISL6421_DCL, 0x00, false))
goto frontend_detach;
}
break;
case CX88_BOARD_PROF_6200:
case CX88_BOARD_TBS_8910:
case CX88_BOARD_TEVII_S420:
fe0->dvb.frontend = dvb_attach(stv0299_attach,
&tevii_tuner_sharp_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, 0x60,
&core->i2c_adap, DVB_PLL_OPERA1))
goto frontend_detach;
core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
} else {
fe0->dvb.frontend = dvb_attach(stv0288_attach,
&tevii_tuner_earda_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
if (!dvb_attach(stb6000_attach,
fe0->dvb.frontend, 0x61,
&core->i2c_adap))
goto frontend_detach;
core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
}
}
break;
case CX88_BOARD_TEVII_S460:
fe0->dvb.frontend = dvb_attach(cx24116_attach,
&tevii_s460_config,
&core->i2c_adap);
if (fe0->dvb.frontend)
fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
break;
case CX88_BOARD_TEVII_S464:
fe0->dvb.frontend = dvb_attach(ds3000_attach,
&tevii_ds3000_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
dvb_attach(ts2020_attach, fe0->dvb.frontend,
&tevii_ts2020_config, &core->i2c_adap);
fe0->dvb.frontend->ops.set_voltage =
tevii_dvbs_set_voltage;
}
break;
case CX88_BOARD_OMICOM_SS4_PCI:
case CX88_BOARD_TBS_8920:
case CX88_BOARD_PROF_7300:
case CX88_BOARD_SATTRADE_ST4200:
fe0->dvb.frontend = dvb_attach(cx24116_attach,
&hauppauge_hvr4000_config,
&core->i2c_adap);
if (fe0->dvb.frontend)
fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
break;
case CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII:
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&cx88_terratec_cinergy_ht_pci_mkii_config,
&core->i2c_adap);
if (fe0->dvb.frontend) {
fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
if (attach_xc3028(0x61, dev) < 0)
goto frontend_detach;
}
break;
case CX88_BOARD_PROF_7301:{
struct dvb_tuner_ops *tuner_ops = NULL;
fe0->dvb.frontend = dvb_attach(stv0900_attach,
&prof_7301_stv0900_config,
&core->i2c_adap, 0);
if (fe0->dvb.frontend) {
if (!dvb_attach(stb6100_attach, fe0->dvb.frontend,
&prof_7301_stb6100_config,
&core->i2c_adap))
goto frontend_detach;
tuner_ops = &fe0->dvb.frontend->ops.tuner_ops;
tuner_ops->set_frequency = stb6100_set_freq;
tuner_ops->get_frequency = stb6100_get_freq;
tuner_ops->set_bandwidth = stb6100_set_bandw;
tuner_ops->get_bandwidth = stb6100_get_bandw;
core->prev_set_voltage =
fe0->dvb.frontend->ops.set_voltage;
fe0->dvb.frontend->ops.set_voltage =
tevii_dvbs_set_voltage;
}
break;
}
case CX88_BOARD_SAMSUNG_SMT_7020:
dev->ts_gen_cntrl = 0x08;
cx_set(MO_GP0_IO, 0x0101);
cx_clear(MO_GP0_IO, 0x01);
msleep(100);
cx_set(MO_GP0_IO, 0x01);
msleep(200);
fe0->dvb.frontend = dvb_attach(stv0299_attach,
&samsung_stv0299_config,
&dev->core->i2c_adap);
if (fe0->dvb.frontend) {
fe0->dvb.frontend->ops.tuner_ops.set_params =
samsung_smt_7020_tuner_set_params;
fe0->dvb.frontend->tuner_priv =
&dev->core->i2c_adap;
fe0->dvb.frontend->ops.set_voltage =
samsung_smt_7020_set_voltage;
fe0->dvb.frontend->ops.set_tone =
samsung_smt_7020_set_tone;
}
break;
case CX88_BOARD_TWINHAN_VP1027_DVBS:
dev->ts_gen_cntrl = 0x00;
fe0->dvb.frontend = dvb_attach(mb86a16_attach,
&twinhan_vp1027,
&core->i2c_adap);
if (fe0->dvb.frontend) {
core->prev_set_voltage =
fe0->dvb.frontend->ops.set_voltage;
fe0->dvb.frontend->ops.set_voltage =
vp1027_set_voltage;
}
break;
default:
pr_err("The frontend of your DVB/ATSC card isn't supported yet\n");
break;
}
if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
pr_err("frontend initialization failed\n");
goto frontend_detach;
}
/* define general-purpose callback pointer */
fe0->dvb.frontend->callback = cx88_tuner_callback;
/* Ensure all frontends negotiate bus access */
fe0->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
if (fe1)
fe1->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
/* Put the tuner in standby to keep it quiet */
call_all(core, tuner, standby);
/* register everything */
res = vb2_dvb_register_bus(&dev->frontends, THIS_MODULE, dev,
&dev->pci->dev, NULL, adapter_nr,
mfe_shared);
if (res)
goto frontend_detach;
return res;
frontend_detach:
core->gate_ctrl = NULL;
vb2_dvb_dealloc_frontends(&dev->frontends);
return res;
}
/* ----------------------------------------------------------- */
/* CX8802 MPEG -> mini driver - We have been given the hardware */
static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
{
struct cx88_core *core = drv->core;
int err = 0;
dprintk(1, "%s\n", __func__);
switch (core->boardnr) {
case CX88_BOARD_HAUPPAUGE_HVR1300:
/* We arrive here with either the cx23416 or the cx22702
* on the bus. Take the bus from the cx23416 and enable the
* cx22702 demod
*/
/* Toggle reset on cx22702 leaving i2c active */
cx_set(MO_GP0_IO, 0x00000080);
udelay(1000);
cx_clear(MO_GP0_IO, 0x00000080);
udelay(50);
cx_set(MO_GP0_IO, 0x00000080);
udelay(1000);
/* enable the cx22702 pins */
cx_clear(MO_GP0_IO, 0x00000004);
udelay(1000);
break;
case CX88_BOARD_HAUPPAUGE_HVR3000:
case CX88_BOARD_HAUPPAUGE_HVR4000:
/* Toggle reset on cx22702 leaving i2c active */
cx_set(MO_GP0_IO, 0x00000080);
udelay(1000);
cx_clear(MO_GP0_IO, 0x00000080);
udelay(50);
cx_set(MO_GP0_IO, 0x00000080);
udelay(1000);
switch (core->dvbdev->frontends.active_fe_id) {
case 1: /* DVB-S/S2 Enabled */
/* tri-state the cx22702 pins */
cx_set(MO_GP0_IO, 0x00000004);
/* Take the cx24116/cx24123 out of reset */
cx_write(MO_SRST_IO, 1);
core->dvbdev->ts_gen_cntrl = 0x02; /* Parallel IO */
break;
case 2: /* DVB-T Enabled */
/* Put the cx24116/cx24123 into reset */
cx_write(MO_SRST_IO, 0);
/* enable the cx22702 pins */
cx_clear(MO_GP0_IO, 0x00000004);
core->dvbdev->ts_gen_cntrl = 0x0c; /* Serial IO */
break;
}
udelay(1000);
break;
case CX88_BOARD_WINFAST_DTV2000H_PLUS:
/* set RF input to AIR for DVB-T (GPIO 16) */
cx_write(MO_GP2_IO, 0x0101);
break;
default:
err = -ENODEV;
}
return err;
}
/* CX8802 MPEG -> mini driver - We no longer have the hardware */
static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
{
struct cx88_core *core = drv->core;
int err = 0;
dprintk(1, "%s\n", __func__);
switch (core->boardnr) {
case CX88_BOARD_HAUPPAUGE_HVR1300:
/* Do Nothing, leave the cx22702 on the bus. */
break;
case CX88_BOARD_HAUPPAUGE_HVR3000:
case CX88_BOARD_HAUPPAUGE_HVR4000:
break;
default:
err = -ENODEV;
}
return err;
}
static int cx8802_dvb_probe(struct cx8802_driver *drv)
{
struct cx88_core *core = drv->core;
struct cx8802_dev *dev = drv->core->dvbdev;
int err;
struct vb2_dvb_frontend *fe;
int i;
dprintk(1, "%s\n", __func__);
dprintk(1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
core->boardnr,
core->name,
core->pci_bus,
core->pci_slot);
err = -ENODEV;
if (!(core->board.mpeg & CX88_MPEG_DVB))
goto fail_core;
/* If vp3054 isn't enabled, a stub will just return 0 */
err = vp3054_i2c_probe(dev);
if (err != 0)
goto fail_core;
/* dvb stuff */
pr_info("cx2388x based DVB/ATSC card\n");
dev->ts_gen_cntrl = 0x0c;
err = cx8802_alloc_frontends(dev);
if (err)
goto fail_core;
for (i = 1; i <= core->board.num_frontends; i++) {
struct vb2_queue *q;
fe = vb2_dvb_get_frontend(&core->dvbdev->frontends, i);
if (!fe) {
pr_err("%s() failed to get frontend(%d)\n",
__func__, i);
err = -ENODEV;
goto fail_probe;
}
q = &fe->dvb.dvbq;
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
q->gfp_flags = GFP_DMA32;
q->min_buffers_needed = 2;
q->drv_priv = dev;
q->buf_struct_size = sizeof(struct cx88_buffer);
q->ops = &dvb_qops;
q->mem_ops = &vb2_dma_sg_memops;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &core->lock;
q->dev = &dev->pci->dev;
err = vb2_queue_init(q);
if (err < 0)
goto fail_probe;
/* init struct vb2_dvb */
fe->dvb.name = dev->core->name;
}
err = dvb_register(dev);
if (err)
/* frontends/adapter de-allocated in dvb_register */
pr_err("dvb_register failed (err = %d)\n", err);
return err;
fail_probe:
vb2_dvb_dealloc_frontends(&core->dvbdev->frontends);
fail_core:
return err;
}
static int cx8802_dvb_remove(struct cx8802_driver *drv)
{
struct cx88_core *core = drv->core;
struct cx8802_dev *dev = drv->core->dvbdev;
dprintk(1, "%s\n", __func__);
vb2_dvb_unregister_bus(&dev->frontends);
vp3054_i2c_remove(dev);
core->gate_ctrl = NULL;
return 0;
}
static struct cx8802_driver cx8802_dvb_driver = {
.type_id = CX88_MPEG_DVB,
.hw_access = CX8802_DRVCTL_SHARED,
.probe = cx8802_dvb_probe,
.remove = cx8802_dvb_remove,
.advise_acquire = cx8802_dvb_advise_acquire,
.advise_release = cx8802_dvb_advise_release,
};
static int __init dvb_init(void)
{
pr_info("cx2388x dvb driver version %s loaded\n", CX88_VERSION);
return cx8802_register_driver(&cx8802_dvb_driver);
}
static void __exit dvb_fini(void)
{
cx8802_unregister_driver(&cx8802_dvb_driver);
}
module_init(dvb_init);
module_exit(dvb_fini);
| linux-master | drivers/media/pci/cx88/cx88-dvb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* device driver for Conexant 2388x based TV cards
* driver core
*
* (c) 2003 Gerd Knorr <[email protected]> [SuSE Labs]
*
* (c) 2005-2006 Mauro Carvalho Chehab <[email protected]>
* - Multituner support
* - video_ioctl2 conversion
* - PAL/M fixes
*/
#include "cx88.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/kmod.h>
#include <linux/sound.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <linux/mutex.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards");
MODULE_AUTHOR("Gerd Knorr <[email protected]> [SuSE Labs]");
MODULE_LICENSE("GPL v2");
/* ------------------------------------------------------------------ */
unsigned int cx88_core_debug;
module_param_named(core_debug, cx88_core_debug, int, 0644);
MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
static unsigned int nicam;
module_param(nicam, int, 0644);
MODULE_PARM_DESC(nicam, "tv audio is nicam");
static unsigned int nocomb;
module_param(nocomb, int, 0644);
MODULE_PARM_DESC(nocomb, "disable comb filter");
#define dprintk0(fmt, arg...) \
printk(KERN_DEBUG pr_fmt("%s: core:" fmt), \
__func__, ##arg) \
#define dprintk(level, fmt, arg...) do { \
if (cx88_core_debug >= level) \
printk(KERN_DEBUG pr_fmt("%s: core:" fmt), \
__func__, ##arg); \
} while (0)
static unsigned int cx88_devcount;
static LIST_HEAD(cx88_devlist);
static DEFINE_MUTEX(devlist);
#define NO_SYNC_LINE (-1U)
/*
* @lpi: lines per IRQ, or 0 to not generate irqs. Note: IRQ to be
* generated _after_ lpi lines are transferred.
*/
static __le32 *cx88_risc_field(__le32 *rp, struct scatterlist *sglist,
unsigned int offset, u32 sync_line,
unsigned int bpl, unsigned int padding,
unsigned int lines, unsigned int lpi, bool jump)
{
struct scatterlist *sg;
unsigned int line, todo, sol;
if (jump) {
(*rp++) = cpu_to_le32(RISC_JUMP);
(*rp++) = 0;
}
/* sync instruction */
if (sync_line != NO_SYNC_LINE)
*(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
/* scan lines */
sg = sglist;
for (line = 0; line < lines; line++) {
while (offset && offset >= sg_dma_len(sg)) {
offset -= sg_dma_len(sg);
sg = sg_next(sg);
}
if (lpi && line > 0 && !(line % lpi))
sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
else
sol = RISC_SOL;
if (bpl <= sg_dma_len(sg) - offset) {
/* fits into current chunk */
*(rp++) = cpu_to_le32(RISC_WRITE | sol |
RISC_EOL | bpl);
*(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
offset += bpl;
} else {
/* scanline needs to be split */
todo = bpl;
*(rp++) = cpu_to_le32(RISC_WRITE | sol |
(sg_dma_len(sg) - offset));
*(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
todo -= (sg_dma_len(sg) - offset);
offset = 0;
sg = sg_next(sg);
while (todo > sg_dma_len(sg)) {
*(rp++) = cpu_to_le32(RISC_WRITE |
sg_dma_len(sg));
*(rp++) = cpu_to_le32(sg_dma_address(sg));
todo -= sg_dma_len(sg);
sg = sg_next(sg);
}
*(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
*(rp++) = cpu_to_le32(sg_dma_address(sg));
offset += todo;
}
offset += padding;
}
return rp;
}
int cx88_risc_buffer(struct pci_dev *pci, struct cx88_riscmem *risc,
struct scatterlist *sglist,
unsigned int top_offset, unsigned int bottom_offset,
unsigned int bpl, unsigned int padding, unsigned int lines)
{
u32 instructions, fields;
__le32 *rp;
fields = 0;
if (top_offset != UNSET)
fields++;
if (bottom_offset != UNSET)
fields++;
/*
* estimate risc mem: worst case is one write per page border +
* one write per scan line + syncs + jump (all 2 dwords). Padding
* can cause next bpl to start close to a page border. First DMA
* region may be smaller than PAGE_SIZE
*/
instructions = fields * (1 + ((bpl + padding) * lines) /
PAGE_SIZE + lines);
instructions += 4;
risc->size = instructions * 8;
risc->dma = 0;
risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma,
GFP_KERNEL);
if (!risc->cpu)
return -ENOMEM;
/* write risc instructions */
rp = risc->cpu;
if (top_offset != UNSET)
rp = cx88_risc_field(rp, sglist, top_offset, 0,
bpl, padding, lines, 0, true);
if (bottom_offset != UNSET)
rp = cx88_risc_field(rp, sglist, bottom_offset, 0x200,
bpl, padding, lines, 0,
top_offset == UNSET);
/* save pointer to jmp instruction address */
risc->jmp = rp;
WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
return 0;
}
EXPORT_SYMBOL(cx88_risc_buffer);
int cx88_risc_databuffer(struct pci_dev *pci, struct cx88_riscmem *risc,
struct scatterlist *sglist, unsigned int bpl,
unsigned int lines, unsigned int lpi)
{
u32 instructions;
__le32 *rp;
/*
* estimate risc mem: worst case is one write per page border +
* one write per scan line + syncs + jump (all 2 dwords). Here
* there is no padding and no sync. First DMA region may be smaller
* than PAGE_SIZE
*/
instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
instructions += 3;
risc->size = instructions * 8;
risc->dma = 0;
risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma,
GFP_KERNEL);
if (!risc->cpu)
return -ENOMEM;
/* write risc instructions */
rp = risc->cpu;
rp = cx88_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
lines, lpi, !lpi);
/* save pointer to jmp instruction address */
risc->jmp = rp;
WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
return 0;
}
EXPORT_SYMBOL(cx88_risc_databuffer);
/*
* our SRAM memory layout
*/
/*
* we are going to put all thr risc programs into host memory, so we
* can use the whole SDRAM for the DMA fifos. To simplify things, we
* use a static memory layout. That surely will waste memory in case
* we don't use all DMA channels at the same time (which will be the
* case most of the time). But that still gives us enough FIFO space
* to be able to deal with insane long pci latencies ...
*
* FIFO space allocations:
* channel 21 (y video) - 10.0k
* channel 22 (u video) - 2.0k
* channel 23 (v video) - 2.0k
* channel 24 (vbi) - 4.0k
* channels 25+26 (audio) - 4.0k
* channel 28 (mpeg) - 4.0k
* channel 27 (audio rds)- 3.0k
* TOTAL = 29.0k
*
* Every channel has 160 bytes control data (64 bytes instruction
* queue and 6 CDT entries), which is close to 2k total.
*
* Address layout:
* 0x0000 - 0x03ff CMDs / reserved
* 0x0400 - 0x0bff instruction queues + CDs
* 0x0c00 - FIFOs
*/
const struct sram_channel cx88_sram_channels[] = {
[SRAM_CH21] = {
.name = "video y / packed",
.cmds_start = 0x180040,
.ctrl_start = 0x180400,
.cdt = 0x180400 + 64,
.fifo_start = 0x180c00,
.fifo_size = 0x002800,
.ptr1_reg = MO_DMA21_PTR1,
.ptr2_reg = MO_DMA21_PTR2,
.cnt1_reg = MO_DMA21_CNT1,
.cnt2_reg = MO_DMA21_CNT2,
},
[SRAM_CH22] = {
.name = "video u",
.cmds_start = 0x180080,
.ctrl_start = 0x1804a0,
.cdt = 0x1804a0 + 64,
.fifo_start = 0x183400,
.fifo_size = 0x000800,
.ptr1_reg = MO_DMA22_PTR1,
.ptr2_reg = MO_DMA22_PTR2,
.cnt1_reg = MO_DMA22_CNT1,
.cnt2_reg = MO_DMA22_CNT2,
},
[SRAM_CH23] = {
.name = "video v",
.cmds_start = 0x1800c0,
.ctrl_start = 0x180540,
.cdt = 0x180540 + 64,
.fifo_start = 0x183c00,
.fifo_size = 0x000800,
.ptr1_reg = MO_DMA23_PTR1,
.ptr2_reg = MO_DMA23_PTR2,
.cnt1_reg = MO_DMA23_CNT1,
.cnt2_reg = MO_DMA23_CNT2,
},
[SRAM_CH24] = {
.name = "vbi",
.cmds_start = 0x180100,
.ctrl_start = 0x1805e0,
.cdt = 0x1805e0 + 64,
.fifo_start = 0x184400,
.fifo_size = 0x001000,
.ptr1_reg = MO_DMA24_PTR1,
.ptr2_reg = MO_DMA24_PTR2,
.cnt1_reg = MO_DMA24_CNT1,
.cnt2_reg = MO_DMA24_CNT2,
},
[SRAM_CH25] = {
.name = "audio from",
.cmds_start = 0x180140,
.ctrl_start = 0x180680,
.cdt = 0x180680 + 64,
.fifo_start = 0x185400,
.fifo_size = 0x001000,
.ptr1_reg = MO_DMA25_PTR1,
.ptr2_reg = MO_DMA25_PTR2,
.cnt1_reg = MO_DMA25_CNT1,
.cnt2_reg = MO_DMA25_CNT2,
},
[SRAM_CH26] = {
.name = "audio to",
.cmds_start = 0x180180,
.ctrl_start = 0x180720,
.cdt = 0x180680 + 64, /* same as audio IN */
.fifo_start = 0x185400, /* same as audio IN */
.fifo_size = 0x001000, /* same as audio IN */
.ptr1_reg = MO_DMA26_PTR1,
.ptr2_reg = MO_DMA26_PTR2,
.cnt1_reg = MO_DMA26_CNT1,
.cnt2_reg = MO_DMA26_CNT2,
},
[SRAM_CH28] = {
.name = "mpeg",
.cmds_start = 0x180200,
.ctrl_start = 0x1807C0,
.cdt = 0x1807C0 + 64,
.fifo_start = 0x186400,
.fifo_size = 0x001000,
.ptr1_reg = MO_DMA28_PTR1,
.ptr2_reg = MO_DMA28_PTR2,
.cnt1_reg = MO_DMA28_CNT1,
.cnt2_reg = MO_DMA28_CNT2,
},
[SRAM_CH27] = {
.name = "audio rds",
.cmds_start = 0x1801C0,
.ctrl_start = 0x180860,
.cdt = 0x180860 + 64,
.fifo_start = 0x187400,
.fifo_size = 0x000C00,
.ptr1_reg = MO_DMA27_PTR1,
.ptr2_reg = MO_DMA27_PTR2,
.cnt1_reg = MO_DMA27_CNT1,
.cnt2_reg = MO_DMA27_CNT2,
},
};
EXPORT_SYMBOL(cx88_sram_channels);
int cx88_sram_channel_setup(struct cx88_core *core,
const struct sram_channel *ch,
unsigned int bpl, u32 risc)
{
unsigned int i, lines;
u32 cdt;
bpl = (bpl + 7) & ~7; /* alignment */
cdt = ch->cdt;
lines = ch->fifo_size / bpl;
if (lines > 6)
lines = 6;
WARN_ON(lines < 2);
/* write CDT */
for (i = 0; i < lines; i++)
cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
/* write CMDS */
cx_write(ch->cmds_start + 0, risc);
cx_write(ch->cmds_start + 4, cdt);
cx_write(ch->cmds_start + 8, (lines * 16) >> 3);
cx_write(ch->cmds_start + 12, ch->ctrl_start);
cx_write(ch->cmds_start + 16, 64 >> 2);
for (i = 20; i < 64; i += 4)
cx_write(ch->cmds_start + i, 0);
/* fill registers */
cx_write(ch->ptr1_reg, ch->fifo_start);
cx_write(ch->ptr2_reg, cdt);
cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
cx_write(ch->cnt2_reg, (lines * 16) >> 3);
dprintk(2, "sram setup %s: bpl=%d lines=%d\n", ch->name, bpl, lines);
return 0;
}
EXPORT_SYMBOL(cx88_sram_channel_setup);
/* ------------------------------------------------------------------ */
/* debug helper code */
static int cx88_risc_decode(u32 risc)
{
static const char * const instr[16] = {
[RISC_SYNC >> 28] = "sync",
[RISC_WRITE >> 28] = "write",
[RISC_WRITEC >> 28] = "writec",
[RISC_READ >> 28] = "read",
[RISC_READC >> 28] = "readc",
[RISC_JUMP >> 28] = "jump",
[RISC_SKIP >> 28] = "skip",
[RISC_WRITERM >> 28] = "writerm",
[RISC_WRITECM >> 28] = "writecm",
[RISC_WRITECR >> 28] = "writecr",
};
static int const incr[16] = {
[RISC_WRITE >> 28] = 2,
[RISC_JUMP >> 28] = 2,
[RISC_WRITERM >> 28] = 3,
[RISC_WRITECM >> 28] = 3,
[RISC_WRITECR >> 28] = 4,
};
static const char * const bits[] = {
"12", "13", "14", "resync",
"cnt0", "cnt1", "18", "19",
"20", "21", "22", "23",
"irq1", "irq2", "eol", "sol",
};
int i;
dprintk0("0x%08x [ %s", risc,
instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
if (risc & (1 << (i + 12)))
pr_cont(" %s", bits[i]);
pr_cont(" count=%d ]\n", risc & 0xfff);
return incr[risc >> 28] ? incr[risc >> 28] : 1;
}
void cx88_sram_channel_dump(struct cx88_core *core,
const struct sram_channel *ch)
{
static const char * const name[] = {
"initial risc",
"cdt base",
"cdt size",
"iq base",
"iq size",
"risc pc",
"iq wr ptr",
"iq rd ptr",
"cdt current",
"pci target",
"line / byte",
};
u32 risc;
unsigned int i, j, n;
dprintk0("%s - dma channel status dump\n", ch->name);
for (i = 0; i < ARRAY_SIZE(name); i++)
dprintk0(" cmds: %-12s: 0x%08x\n",
name[i], cx_read(ch->cmds_start + 4 * i));
for (n = 1, i = 0; i < 4; i++) {
risc = cx_read(ch->cmds_start + 4 * (i + 11));
pr_cont(" risc%d: ", i);
if (--n)
pr_cont("0x%08x [ arg #%d ]\n", risc, n);
else
n = cx88_risc_decode(risc);
}
for (i = 0; i < 16; i += n) {
risc = cx_read(ch->ctrl_start + 4 * i);
dprintk0(" iq %x: ", i);
n = cx88_risc_decode(risc);
for (j = 1; j < n; j++) {
risc = cx_read(ch->ctrl_start + 4 * (i + j));
pr_cont(" iq %x: 0x%08x [ arg #%d ]\n",
i + j, risc, j);
}
}
dprintk0("fifo: 0x%08x -> 0x%x\n",
ch->fifo_start, ch->fifo_start + ch->fifo_size);
dprintk0("ctrl: 0x%08x -> 0x%x\n",
ch->ctrl_start, ch->ctrl_start + 6 * 16);
dprintk0(" ptr1_reg: 0x%08x\n", cx_read(ch->ptr1_reg));
dprintk0(" ptr2_reg: 0x%08x\n", cx_read(ch->ptr2_reg));
dprintk0(" cnt1_reg: 0x%08x\n", cx_read(ch->cnt1_reg));
dprintk0(" cnt2_reg: 0x%08x\n", cx_read(ch->cnt2_reg));
}
EXPORT_SYMBOL(cx88_sram_channel_dump);
static const char *cx88_pci_irqs[32] = {
"vid", "aud", "ts", "vip", "hst", "5", "6", "tm1",
"src_dma", "dst_dma", "risc_rd_err", "risc_wr_err",
"brdg_err", "src_dma_err", "dst_dma_err", "ipb_dma_err",
"i2c", "i2c_rack", "ir_smp", "gpio0", "gpio1"
};
void cx88_print_irqbits(const char *tag, const char *strings[],
int len, u32 bits, u32 mask)
{
unsigned int i;
dprintk0("%s [0x%x]", tag, bits);
for (i = 0; i < len; i++) {
if (!(bits & (1 << i)))
continue;
if (strings[i])
pr_cont(" %s", strings[i]);
else
pr_cont(" %d", i);
if (!(mask & (1 << i)))
continue;
pr_cont("*");
}
pr_cont("\n");
}
EXPORT_SYMBOL(cx88_print_irqbits);
/* ------------------------------------------------------------------ */
int cx88_core_irq(struct cx88_core *core, u32 status)
{
int handled = 0;
if (status & PCI_INT_IR_SMPINT) {
cx88_ir_irq(core);
handled++;
}
if (!handled)
cx88_print_irqbits("irq pci",
cx88_pci_irqs, ARRAY_SIZE(cx88_pci_irqs),
status, core->pci_irqmask);
return handled;
}
EXPORT_SYMBOL(cx88_core_irq);
void cx88_wakeup(struct cx88_core *core,
struct cx88_dmaqueue *q, u32 count)
{
struct cx88_buffer *buf;
buf = list_entry(q->active.next,
struct cx88_buffer, list);
buf->vb.vb2_buf.timestamp = ktime_get_ns();
buf->vb.field = core->field;
buf->vb.sequence = q->count++;
list_del(&buf->list);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
EXPORT_SYMBOL(cx88_wakeup);
void cx88_shutdown(struct cx88_core *core)
{
/* disable RISC controller + IRQs */
cx_write(MO_DEV_CNTRL2, 0);
/* stop dma transfers */
cx_write(MO_VID_DMACNTRL, 0x0);
cx_write(MO_AUD_DMACNTRL, 0x0);
cx_write(MO_TS_DMACNTRL, 0x0);
cx_write(MO_VIP_DMACNTRL, 0x0);
cx_write(MO_GPHST_DMACNTRL, 0x0);
/* stop interrupts */
cx_write(MO_PCI_INTMSK, 0x0);
cx_write(MO_VID_INTMSK, 0x0);
cx_write(MO_AUD_INTMSK, 0x0);
cx_write(MO_TS_INTMSK, 0x0);
cx_write(MO_VIP_INTMSK, 0x0);
cx_write(MO_GPHST_INTMSK, 0x0);
/* stop capturing */
cx_write(VID_CAPTURE_CONTROL, 0);
}
EXPORT_SYMBOL(cx88_shutdown);
int cx88_reset(struct cx88_core *core)
{
dprintk(1, "");
cx88_shutdown(core);
/* clear irq status */
cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int
cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int
cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int
/* wait a bit */
msleep(100);
/* init sram */
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21],
720 * 4, 0);
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH22], 128, 0);
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH23], 128, 0);
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH24], 128, 0);
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], 128, 0);
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], 128, 0);
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],
188 * 4, 0);
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27], 128, 0);
/* misc init ... */
cx_write(MO_INPUT_FORMAT, ((1 << 13) | // agc enable
(1 << 12) | // agc gain
(1 << 11) | // adaptibe agc
(0 << 10) | // chroma agc
(0 << 9) | // ckillen
(7)));
/* setup image format */
cx_andor(MO_COLOR_CTRL, 0x4000, 0x4000);
/* setup FIFO Thresholds */
cx_write(MO_PDMA_STHRSH, 0x0807);
cx_write(MO_PDMA_DTHRSH, 0x0807);
/* fixes flashing of image */
cx_write(MO_AGC_SYNC_TIP1, 0x0380000F);
cx_write(MO_AGC_BACK_VBI, 0x00E00555);
cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int
cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int
cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int
/* Reset on-board parts */
cx_write(MO_SRST_IO, 0);
usleep_range(10000, 20000);
cx_write(MO_SRST_IO, 1);
return 0;
}
EXPORT_SYMBOL(cx88_reset);
/* ------------------------------------------------------------------ */
static inline unsigned int norm_swidth(v4l2_std_id norm)
{
if (norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M))
return 754;
if (norm & V4L2_STD_PAL_Nc)
return 745;
return 922;
}
static inline unsigned int norm_hdelay(v4l2_std_id norm)
{
if (norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M))
return 135;
if (norm & V4L2_STD_PAL_Nc)
return 149;
return 186;
}
static inline unsigned int norm_vdelay(v4l2_std_id norm)
{
return (norm & V4L2_STD_625_50) ? 0x24 : 0x18;
}
static inline unsigned int norm_fsc8(v4l2_std_id norm)
{
if (norm & V4L2_STD_PAL_M)
return 28604892; // 3.575611 MHz
if (norm & V4L2_STD_PAL_Nc)
return 28656448; // 3.582056 MHz
if (norm & V4L2_STD_NTSC) // All NTSC/M and variants
return 28636360; // 3.57954545 MHz +/- 10 Hz
/*
* SECAM have also different sub carrier for chroma,
* but step_db and step_dr, at cx88_set_tvnorm already handles that.
*
* The same FSC applies to PAL/BGDKIH, PAL/60, NTSC/4.43 and PAL/N
*/
return 35468950; // 4.43361875 MHz +/- 5 Hz
}
static inline unsigned int norm_htotal(v4l2_std_id norm)
{
unsigned int fsc4 = norm_fsc8(norm) / 2;
/* returns 4*FSC / vtotal / frames per seconds */
return (norm & V4L2_STD_625_50) ?
((fsc4 + 312) / 625 + 12) / 25 :
((fsc4 + 262) / 525 * 1001 + 15000) / 30000;
}
static inline unsigned int norm_vbipack(v4l2_std_id norm)
{
return (norm & V4L2_STD_625_50) ? 511 : 400;
}
int cx88_set_scale(struct cx88_core *core, unsigned int width,
unsigned int height, enum v4l2_field field)
{
unsigned int swidth = norm_swidth(core->tvnorm);
unsigned int sheight = norm_maxh(core->tvnorm);
u32 value;
dprintk(1, "set_scale: %dx%d [%s%s,%s]\n", width, height,
V4L2_FIELD_HAS_TOP(field) ? "T" : "",
V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "",
v4l2_norm_to_name(core->tvnorm));
if (!V4L2_FIELD_HAS_BOTH(field))
height *= 2;
// recalc H delay and scale registers
value = (width * norm_hdelay(core->tvnorm)) / swidth;
value &= 0x3fe;
cx_write(MO_HDELAY_EVEN, value);
cx_write(MO_HDELAY_ODD, value);
dprintk(1, "set_scale: hdelay 0x%04x (width %d)\n", value, swidth);
value = (swidth * 4096 / width) - 4096;
cx_write(MO_HSCALE_EVEN, value);
cx_write(MO_HSCALE_ODD, value);
dprintk(1, "set_scale: hscale 0x%04x\n", value);
cx_write(MO_HACTIVE_EVEN, width);
cx_write(MO_HACTIVE_ODD, width);
dprintk(1, "set_scale: hactive 0x%04x\n", width);
// recalc V scale Register (delay is constant)
cx_write(MO_VDELAY_EVEN, norm_vdelay(core->tvnorm));
cx_write(MO_VDELAY_ODD, norm_vdelay(core->tvnorm));
dprintk(1, "set_scale: vdelay 0x%04x\n", norm_vdelay(core->tvnorm));
value = (0x10000 - (sheight * 512 / height - 512)) & 0x1fff;
cx_write(MO_VSCALE_EVEN, value);
cx_write(MO_VSCALE_ODD, value);
dprintk(1, "set_scale: vscale 0x%04x\n", value);
cx_write(MO_VACTIVE_EVEN, sheight);
cx_write(MO_VACTIVE_ODD, sheight);
dprintk(1, "set_scale: vactive 0x%04x\n", sheight);
// setup filters
value = 0;
value |= (1 << 19); // CFILT (default)
if (core->tvnorm & V4L2_STD_SECAM) {
value |= (1 << 15);
value |= (1 << 16);
}
if (INPUT(core->input).type == CX88_VMUX_SVIDEO)
value |= (1 << 13) | (1 << 5);
if (field == V4L2_FIELD_INTERLACED)
value |= (1 << 3); // VINT (interlaced vertical scaling)
if (width < 385)
value |= (1 << 0); // 3-tap interpolation
if (width < 193)
value |= (1 << 1); // 5-tap interpolation
if (nocomb)
value |= (3 << 5); // disable comb filter
cx_andor(MO_FILTER_EVEN, 0x7ffc7f, value); /* preserve PEAKEN, PSEL */
cx_andor(MO_FILTER_ODD, 0x7ffc7f, value);
dprintk(1, "set_scale: filter 0x%04x\n", value);
return 0;
}
EXPORT_SYMBOL(cx88_set_scale);
static const u32 xtal = 28636363;
static int set_pll(struct cx88_core *core, int prescale, u32 ofreq)
{
static const u32 pre[] = { 0, 0, 0, 3, 2, 1 };
u64 pll;
u32 reg;
int i;
if (prescale < 2)
prescale = 2;
if (prescale > 5)
prescale = 5;
pll = ofreq * 8 * prescale * (u64)(1 << 20);
do_div(pll, xtal);
reg = (pll & 0x3ffffff) | (pre[prescale] << 26);
if (((reg >> 20) & 0x3f) < 14) {
pr_err("pll out of range\n");
return -1;
}
dprintk(1, "set_pll: MO_PLL_REG 0x%08x [old=0x%08x,freq=%d]\n",
reg, cx_read(MO_PLL_REG), ofreq);
cx_write(MO_PLL_REG, reg);
for (i = 0; i < 100; i++) {
reg = cx_read(MO_DEVICE_STATUS);
if (reg & (1 << 2)) {
dprintk(1, "pll locked [pre=%d,ofreq=%d]\n",
prescale, ofreq);
return 0;
}
dprintk(1, "pll not locked yet, waiting ...\n");
usleep_range(10000, 20000);
}
dprintk(1, "pll NOT locked [pre=%d,ofreq=%d]\n", prescale, ofreq);
return -1;
}
int cx88_start_audio_dma(struct cx88_core *core)
{
/* constant 128 made buzz in analog Nicam-stereo for bigger fifo_size */
int bpl = cx88_sram_channels[SRAM_CH25].fifo_size / 4;
int rds_bpl = cx88_sram_channels[SRAM_CH27].fifo_size / AUD_RDS_LINES;
/* If downstream RISC is enabled, bail out; ALSA is managing DMA */
if (cx_read(MO_AUD_DMACNTRL) & 0x10)
return 0;
/* setup fifo + format */
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], bpl, 0);
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], bpl, 0);
cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27],
rds_bpl, 0);
cx_write(MO_AUDD_LNGTH, bpl); /* fifo bpl size */
cx_write(MO_AUDR_LNGTH, rds_bpl); /* fifo bpl size */
/* enable Up, Down and Audio RDS fifo */
cx_write(MO_AUD_DMACNTRL, 0x0007);
return 0;
}
int cx88_stop_audio_dma(struct cx88_core *core)
{
/* If downstream RISC is enabled, bail out; ALSA is managing DMA */
if (cx_read(MO_AUD_DMACNTRL) & 0x10)
return 0;
/* stop dma */
cx_write(MO_AUD_DMACNTRL, 0x0000);
return 0;
}
static int set_tvaudio(struct cx88_core *core)
{
v4l2_std_id norm = core->tvnorm;
if (INPUT(core->input).type != CX88_VMUX_TELEVISION &&
INPUT(core->input).type != CX88_VMUX_CABLE)
return 0;
if (V4L2_STD_PAL_BG & norm) {
core->tvaudio = WW_BG;
} else if (V4L2_STD_PAL_DK & norm) {
core->tvaudio = WW_DK;
} else if (V4L2_STD_PAL_I & norm) {
core->tvaudio = WW_I;
} else if (V4L2_STD_SECAM_L & norm) {
core->tvaudio = WW_L;
} else if ((V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H) &
norm) {
core->tvaudio = WW_BG;
} else if (V4L2_STD_SECAM_DK & norm) {
core->tvaudio = WW_DK;
} else if ((V4L2_STD_NTSC_M | V4L2_STD_PAL_M | V4L2_STD_PAL_Nc) &
norm) {
core->tvaudio = WW_BTSC;
} else if (V4L2_STD_NTSC_M_JP & norm) {
core->tvaudio = WW_EIAJ;
} else {
pr_info("tvaudio support needs work for this tv norm [%s], sorry\n",
v4l2_norm_to_name(core->tvnorm));
core->tvaudio = WW_NONE;
return 0;
}
cx_andor(MO_AFECFG_IO, 0x1f, 0x0);
cx88_set_tvaudio(core);
/* cx88_set_stereo(dev,V4L2_TUNER_MODE_STEREO); */
/*
* This should be needed only on cx88-alsa. It seems that some cx88 chips have
* bugs and does require DMA enabled for it to work.
*/
cx88_start_audio_dma(core);
return 0;
}
int cx88_set_tvnorm(struct cx88_core *core, v4l2_std_id norm)
{
u32 fsc8;
u32 adc_clock;
u32 vdec_clock;
u32 step_db, step_dr;
u64 tmp64;
u32 bdelay, agcdelay, htotal;
u32 cxiformat, cxoformat;
if (norm == core->tvnorm)
return 0;
if (core->v4ldev && (vb2_is_busy(&core->v4ldev->vb2_vidq) ||
vb2_is_busy(&core->v4ldev->vb2_vbiq)))
return -EBUSY;
if (core->dvbdev && vb2_is_busy(&core->dvbdev->vb2_mpegq))
return -EBUSY;
core->tvnorm = norm;
fsc8 = norm_fsc8(norm);
adc_clock = xtal;
vdec_clock = fsc8;
step_db = fsc8;
step_dr = fsc8;
if (norm & V4L2_STD_NTSC_M_JP) {
cxiformat = VideoFormatNTSCJapan;
cxoformat = 0x181f0008;
} else if (norm & V4L2_STD_NTSC_443) {
cxiformat = VideoFormatNTSC443;
cxoformat = 0x181f0008;
} else if (norm & V4L2_STD_PAL_M) {
cxiformat = VideoFormatPALM;
cxoformat = 0x1c1f0008;
} else if (norm & V4L2_STD_PAL_N) {
cxiformat = VideoFormatPALN;
cxoformat = 0x1c1f0008;
} else if (norm & V4L2_STD_PAL_Nc) {
cxiformat = VideoFormatPALNC;
cxoformat = 0x1c1f0008;
} else if (norm & V4L2_STD_PAL_60) {
cxiformat = VideoFormatPAL60;
cxoformat = 0x181f0008;
} else if (norm & V4L2_STD_NTSC) {
cxiformat = VideoFormatNTSC;
cxoformat = 0x181f0008;
} else if (norm & V4L2_STD_SECAM) {
step_db = 4250000 * 8;
step_dr = 4406250 * 8;
cxiformat = VideoFormatSECAM;
cxoformat = 0x181f0008;
} else { /* PAL */
cxiformat = VideoFormatPAL;
cxoformat = 0x181f0008;
}
dprintk(1, "set_tvnorm: \"%s\" fsc8=%d adc=%d vdec=%d db/dr=%d/%d\n",
v4l2_norm_to_name(core->tvnorm), fsc8, adc_clock, vdec_clock,
step_db, step_dr);
set_pll(core, 2, vdec_clock);
dprintk(1, "set_tvnorm: MO_INPUT_FORMAT 0x%08x [old=0x%08x]\n",
cxiformat, cx_read(MO_INPUT_FORMAT) & 0x0f);
/*
* Chroma AGC must be disabled if SECAM is used, we enable it
* by default on PAL and NTSC
*/
cx_andor(MO_INPUT_FORMAT, 0x40f,
norm & V4L2_STD_SECAM ? cxiformat : cxiformat | 0x400);
// FIXME: as-is from DScaler
dprintk(1, "set_tvnorm: MO_OUTPUT_FORMAT 0x%08x [old=0x%08x]\n",
cxoformat, cx_read(MO_OUTPUT_FORMAT));
cx_write(MO_OUTPUT_FORMAT, cxoformat);
// MO_SCONV_REG = adc clock / video dec clock * 2^17
tmp64 = adc_clock * (u64)(1 << 17);
do_div(tmp64, vdec_clock);
dprintk(1, "set_tvnorm: MO_SCONV_REG 0x%08x [old=0x%08x]\n",
(u32)tmp64, cx_read(MO_SCONV_REG));
cx_write(MO_SCONV_REG, (u32)tmp64);
// MO_SUB_STEP = 8 * fsc / video dec clock * 2^22
tmp64 = step_db * (u64)(1 << 22);
do_div(tmp64, vdec_clock);
dprintk(1, "set_tvnorm: MO_SUB_STEP 0x%08x [old=0x%08x]\n",
(u32)tmp64, cx_read(MO_SUB_STEP));
cx_write(MO_SUB_STEP, (u32)tmp64);
// MO_SUB_STEP_DR = 8 * 4406250 / video dec clock * 2^22
tmp64 = step_dr * (u64)(1 << 22);
do_div(tmp64, vdec_clock);
dprintk(1, "set_tvnorm: MO_SUB_STEP_DR 0x%08x [old=0x%08x]\n",
(u32)tmp64, cx_read(MO_SUB_STEP_DR));
cx_write(MO_SUB_STEP_DR, (u32)tmp64);
// bdelay + agcdelay
bdelay = vdec_clock * 65 / 20000000 + 21;
agcdelay = vdec_clock * 68 / 20000000 + 15;
dprintk(1,
"set_tvnorm: MO_AGC_BURST 0x%08x [old=0x%08x,bdelay=%d,agcdelay=%d]\n",
(bdelay << 8) | agcdelay, cx_read(MO_AGC_BURST),
bdelay, agcdelay);
cx_write(MO_AGC_BURST, (bdelay << 8) | agcdelay);
// htotal
tmp64 = norm_htotal(norm) * (u64)vdec_clock;
do_div(tmp64, fsc8);
htotal = (u32)tmp64;
dprintk(1,
"set_tvnorm: MO_HTOTAL 0x%08x [old=0x%08x,htotal=%d]\n",
htotal, cx_read(MO_HTOTAL), (u32)tmp64);
cx_andor(MO_HTOTAL, 0x07ff, htotal);
// vbi stuff, set vbi offset to 10 (for 20 Clk*2 pixels), this makes
// the effective vbi offset ~244 samples, the same as the Bt8x8
cx_write(MO_VBI_PACKET, (10 << 11) | norm_vbipack(norm));
// this is needed as well to set all tvnorm parameter
cx88_set_scale(core, 320, 240, V4L2_FIELD_INTERLACED);
// audio
set_tvaudio(core);
// tell i2c chips
call_all(core, video, s_std, norm);
/*
* The chroma_agc control should be inaccessible
* if the video format is SECAM
*/
v4l2_ctrl_grab(core->chroma_agc, cxiformat == VideoFormatSECAM);
// done
return 0;
}
EXPORT_SYMBOL(cx88_set_tvnorm);
/* ------------------------------------------------------------------ */
void cx88_vdev_init(struct cx88_core *core,
struct pci_dev *pci,
struct video_device *vfd,
const struct video_device *template_,
const char *type)
{
*vfd = *template_;
/*
* The dev pointer of v4l2_device is NULL, instead we set the
* video_device dev_parent pointer to the correct PCI bus device.
* This driver is a rare example where there is one v4l2_device,
* but the video nodes have different parent (PCI) devices.
*/
vfd->v4l2_dev = &core->v4l2_dev;
vfd->dev_parent = &pci->dev;
vfd->release = video_device_release_empty;
vfd->lock = &core->lock;
snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)",
core->name, type, core->board.name);
}
EXPORT_SYMBOL(cx88_vdev_init);
struct cx88_core *cx88_core_get(struct pci_dev *pci)
{
struct cx88_core *core;
mutex_lock(&devlist);
list_for_each_entry(core, &cx88_devlist, devlist) {
if (pci->bus->number != core->pci_bus)
continue;
if (PCI_SLOT(pci->devfn) != core->pci_slot)
continue;
if (cx88_get_resources(core, pci) != 0) {
mutex_unlock(&devlist);
return NULL;
}
refcount_inc(&core->refcount);
mutex_unlock(&devlist);
return core;
}
core = cx88_core_create(pci, cx88_devcount);
if (core) {
cx88_devcount++;
list_add_tail(&core->devlist, &cx88_devlist);
}
mutex_unlock(&devlist);
return core;
}
EXPORT_SYMBOL(cx88_core_get);
void cx88_core_put(struct cx88_core *core, struct pci_dev *pci)
{
release_mem_region(pci_resource_start(pci, 0),
pci_resource_len(pci, 0));
if (!refcount_dec_and_test(&core->refcount))
return;
mutex_lock(&devlist);
cx88_ir_fini(core);
if (core->i2c_rc == 0) {
i2c_unregister_device(core->i2c_rtc);
i2c_del_adapter(&core->i2c_adap);
}
list_del(&core->devlist);
iounmap(core->lmmio);
cx88_devcount--;
mutex_unlock(&devlist);
v4l2_ctrl_handler_free(&core->video_hdl);
v4l2_ctrl_handler_free(&core->audio_hdl);
v4l2_device_unregister(&core->v4l2_dev);
kfree(core);
}
EXPORT_SYMBOL(cx88_core_put);
| linux-master | drivers/media/pci/cx88/cx88-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cx88x-audio.c - Conexant CX23880/23881 audio downstream driver driver
*
* (c) 2001 Michael Eskin, Tom Zakrajsek [Windows version]
* (c) 2002 Yurij Sysoev <[email protected]>
* (c) 2003 Gerd Knorr <[email protected]>
*
* -----------------------------------------------------------------------
*
* Lot of voodoo here. Even the data sheet doesn't help to
* understand what is going on here, the documentation for the audio
* part of the cx2388x chip is *very* bad.
*
* Some of this comes from party done linux driver sources I got from
* [undocumented].
*
* Some comes from the dscaler sources, one of the dscaler driver guy works
* for Conexant ...
*
* -----------------------------------------------------------------------
*/
#include "cx88.h"
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/freezer.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/poll.h>
#include <linux/signal.h>
#include <linux/ioport.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/kthread.h>
static unsigned int audio_debug;
module_param(audio_debug, int, 0644);
MODULE_PARM_DESC(audio_debug, "enable debug messages [audio]");
static unsigned int always_analog;
module_param(always_analog, int, 0644);
MODULE_PARM_DESC(always_analog, "force analog audio out");
static unsigned int radio_deemphasis;
module_param(radio_deemphasis, int, 0644);
MODULE_PARM_DESC(radio_deemphasis,
"Radio deemphasis time constant, 0=None, 1=50us (elsewhere), 2=75us (USA)");
#define dprintk(fmt, arg...) do { \
if (audio_debug) \
printk(KERN_DEBUG pr_fmt("%s: tvaudio:" fmt), \
__func__, ##arg); \
} while (0)
/* ----------------------------------------------------------- */
static const char * const aud_ctl_names[64] = {
[EN_BTSC_FORCE_MONO] = "BTSC_FORCE_MONO",
[EN_BTSC_FORCE_STEREO] = "BTSC_FORCE_STEREO",
[EN_BTSC_FORCE_SAP] = "BTSC_FORCE_SAP",
[EN_BTSC_AUTO_STEREO] = "BTSC_AUTO_STEREO",
[EN_BTSC_AUTO_SAP] = "BTSC_AUTO_SAP",
[EN_A2_FORCE_MONO1] = "A2_FORCE_MONO1",
[EN_A2_FORCE_MONO2] = "A2_FORCE_MONO2",
[EN_A2_FORCE_STEREO] = "A2_FORCE_STEREO",
[EN_A2_AUTO_MONO2] = "A2_AUTO_MONO2",
[EN_A2_AUTO_STEREO] = "A2_AUTO_STEREO",
[EN_EIAJ_FORCE_MONO1] = "EIAJ_FORCE_MONO1",
[EN_EIAJ_FORCE_MONO2] = "EIAJ_FORCE_MONO2",
[EN_EIAJ_FORCE_STEREO] = "EIAJ_FORCE_STEREO",
[EN_EIAJ_AUTO_MONO2] = "EIAJ_AUTO_MONO2",
[EN_EIAJ_AUTO_STEREO] = "EIAJ_AUTO_STEREO",
[EN_NICAM_FORCE_MONO1] = "NICAM_FORCE_MONO1",
[EN_NICAM_FORCE_MONO2] = "NICAM_FORCE_MONO2",
[EN_NICAM_FORCE_STEREO] = "NICAM_FORCE_STEREO",
[EN_NICAM_AUTO_MONO2] = "NICAM_AUTO_MONO2",
[EN_NICAM_AUTO_STEREO] = "NICAM_AUTO_STEREO",
[EN_FMRADIO_FORCE_MONO] = "FMRADIO_FORCE_MONO",
[EN_FMRADIO_FORCE_STEREO] = "FMRADIO_FORCE_STEREO",
[EN_FMRADIO_AUTO_STEREO] = "FMRADIO_AUTO_STEREO",
};
struct rlist {
u32 reg;
u32 val;
};
static void set_audio_registers(struct cx88_core *core, const struct rlist *l)
{
int i;
for (i = 0; l[i].reg; i++) {
switch (l[i].reg) {
case AUD_PDF_DDS_CNST_BYTE2:
case AUD_PDF_DDS_CNST_BYTE1:
case AUD_PDF_DDS_CNST_BYTE0:
case AUD_QAM_MODE:
case AUD_PHACC_FREQ_8MSB:
case AUD_PHACC_FREQ_8LSB:
cx_writeb(l[i].reg, l[i].val);
break;
default:
cx_write(l[i].reg, l[i].val);
break;
}
}
}
static void set_audio_start(struct cx88_core *core, u32 mode)
{
/* mute */
cx_write(AUD_VOL_CTL, (1 << 6));
/* start programming */
cx_write(AUD_INIT, mode);
cx_write(AUD_INIT_LD, 0x0001);
cx_write(AUD_SOFT_RESET, 0x0001);
}
static void set_audio_finish(struct cx88_core *core, u32 ctl)
{
u32 volume;
/* restart dma; This avoids buzz in NICAM and is good in others */
cx88_stop_audio_dma(core);
cx_write(AUD_RATE_THRES_DMD, 0x000000C0);
cx88_start_audio_dma(core);
if (core->board.mpeg & CX88_MPEG_BLACKBIRD) {
cx_write(AUD_I2SINPUTCNTL, 4);
cx_write(AUD_BAUDRATE, 1);
/*
* 'pass-thru mode': this enables the i2s
* output to the mpeg encoder
*/
cx_set(AUD_CTL, EN_I2SOUT_ENABLE);
cx_write(AUD_I2SOUTPUTCNTL, 1);
cx_write(AUD_I2SCNTL, 0);
/* cx_write(AUD_APB_IN_RATE_ADJ, 0); */
}
if ((always_analog) || (!(core->board.mpeg & CX88_MPEG_BLACKBIRD))) {
ctl |= EN_DAC_ENABLE;
cx_write(AUD_CTL, ctl);
}
/* finish programming */
cx_write(AUD_SOFT_RESET, 0x0000);
/* unmute */
volume = cx_sread(SHADOW_AUD_VOL_CTL);
cx_swrite(SHADOW_AUD_VOL_CTL, AUD_VOL_CTL, volume);
core->last_change = jiffies;
}
/* ----------------------------------------------------------- */
static void set_audio_standard_BTSC(struct cx88_core *core, unsigned int sap,
u32 mode)
{
static const struct rlist btsc[] = {
{AUD_AFE_12DB_EN, 0x00000001},
{AUD_OUT1_SEL, 0x00000013},
{AUD_OUT1_SHIFT, 0x00000000},
{AUD_POLY0_DDS_CONSTANT, 0x0012010c},
{AUD_DMD_RA_DDS, 0x00c3e7aa},
{AUD_DBX_IN_GAIN, 0x00004734},
{AUD_DBX_WBE_GAIN, 0x00004640},
{AUD_DBX_SE_GAIN, 0x00008d31},
{AUD_DCOC_0_SRC, 0x0000001a},
{AUD_IIR1_4_SEL, 0x00000021},
{AUD_DCOC_PASS_IN, 0x00000003},
{AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
{AUD_DCOC_0_SHIFT_IN1, 0x00000008},
{AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
{AUD_DCOC_1_SHIFT_IN1, 0x00000008},
{AUD_DN0_FREQ, 0x0000283b},
{AUD_DN2_SRC_SEL, 0x00000008},
{AUD_DN2_FREQ, 0x00003000},
{AUD_DN2_AFC, 0x00000002},
{AUD_DN2_SHFT, 0x00000000},
{AUD_IIR2_2_SEL, 0x00000020},
{AUD_IIR2_2_SHIFT, 0x00000000},
{AUD_IIR2_3_SEL, 0x0000001f},
{AUD_IIR2_3_SHIFT, 0x00000000},
{AUD_CRDC1_SRC_SEL, 0x000003ce},
{AUD_CRDC1_SHIFT, 0x00000000},
{AUD_CORDIC_SHIFT_1, 0x00000007},
{AUD_DCOC_1_SRC, 0x0000001b},
{AUD_DCOC1_SHIFT, 0x00000000},
{AUD_RDSI_SEL, 0x00000008},
{AUD_RDSQ_SEL, 0x00000008},
{AUD_RDSI_SHIFT, 0x00000000},
{AUD_RDSQ_SHIFT, 0x00000000},
{AUD_POLYPH80SCALEFAC, 0x00000003},
{ /* end of list */ },
};
static const struct rlist btsc_sap[] = {
{AUD_AFE_12DB_EN, 0x00000001},
{AUD_DBX_IN_GAIN, 0x00007200},
{AUD_DBX_WBE_GAIN, 0x00006200},
{AUD_DBX_SE_GAIN, 0x00006200},
{AUD_IIR1_1_SEL, 0x00000000},
{AUD_IIR1_3_SEL, 0x00000001},
{AUD_DN1_SRC_SEL, 0x00000007},
{AUD_IIR1_4_SHIFT, 0x00000006},
{AUD_IIR2_1_SHIFT, 0x00000000},
{AUD_IIR2_2_SHIFT, 0x00000000},
{AUD_IIR3_0_SHIFT, 0x00000000},
{AUD_IIR3_1_SHIFT, 0x00000000},
{AUD_IIR3_0_SEL, 0x0000000d},
{AUD_IIR3_1_SEL, 0x0000000e},
{AUD_DEEMPH1_SRC_SEL, 0x00000014},
{AUD_DEEMPH1_SHIFT, 0x00000000},
{AUD_DEEMPH1_G0, 0x00004000},
{AUD_DEEMPH1_A0, 0x00000000},
{AUD_DEEMPH1_B0, 0x00000000},
{AUD_DEEMPH1_A1, 0x00000000},
{AUD_DEEMPH1_B1, 0x00000000},
{AUD_OUT0_SEL, 0x0000003f},
{AUD_OUT1_SEL, 0x0000003f},
{AUD_DN1_AFC, 0x00000002},
{AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
{AUD_DCOC_0_SHIFT_IN1, 0x00000008},
{AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
{AUD_DCOC_1_SHIFT_IN1, 0x00000008},
{AUD_IIR1_0_SEL, 0x0000001d},
{AUD_IIR1_2_SEL, 0x0000001e},
{AUD_IIR2_1_SEL, 0x00000002},
{AUD_IIR2_2_SEL, 0x00000004},
{AUD_IIR3_2_SEL, 0x0000000f},
{AUD_DCOC2_SHIFT, 0x00000001},
{AUD_IIR3_2_SHIFT, 0x00000001},
{AUD_DEEMPH0_SRC_SEL, 0x00000014},
{AUD_CORDIC_SHIFT_1, 0x00000006},
{AUD_POLY0_DDS_CONSTANT, 0x000e4db2},
{AUD_DMD_RA_DDS, 0x00f696e6},
{AUD_IIR2_3_SEL, 0x00000025},
{AUD_IIR1_4_SEL, 0x00000021},
{AUD_DN1_FREQ, 0x0000c965},
{AUD_DCOC_PASS_IN, 0x00000003},
{AUD_DCOC_0_SRC, 0x0000001a},
{AUD_DCOC_1_SRC, 0x0000001b},
{AUD_DCOC1_SHIFT, 0x00000000},
{AUD_RDSI_SEL, 0x00000009},
{AUD_RDSQ_SEL, 0x00000009},
{AUD_RDSI_SHIFT, 0x00000000},
{AUD_RDSQ_SHIFT, 0x00000000},
{AUD_POLYPH80SCALEFAC, 0x00000003},
{ /* end of list */ },
};
mode |= EN_FMRADIO_EN_RDS;
if (sap) {
dprintk("%s SAP (status: unknown)\n", __func__);
set_audio_start(core, SEL_SAP);
set_audio_registers(core, btsc_sap);
set_audio_finish(core, mode);
} else {
dprintk("%s (status: known-good)\n", __func__);
set_audio_start(core, SEL_BTSC);
set_audio_registers(core, btsc);
set_audio_finish(core, mode);
}
}
static void set_audio_standard_NICAM(struct cx88_core *core, u32 mode)
{
static const struct rlist nicam_l[] = {
{AUD_AFE_12DB_EN, 0x00000001},
{AUD_RATE_ADJ1, 0x00000060},
{AUD_RATE_ADJ2, 0x000000F9},
{AUD_RATE_ADJ3, 0x000001CC},
{AUD_RATE_ADJ4, 0x000002B3},
{AUD_RATE_ADJ5, 0x00000726},
{AUD_DEEMPHDENOM1_R, 0x0000F3D0},
{AUD_DEEMPHDENOM2_R, 0x00000000},
{AUD_ERRLOGPERIOD_R, 0x00000064},
{AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF},
{AUD_ERRINTRPTTHSHLD2_R, 0x0000001F},
{AUD_ERRINTRPTTHSHLD3_R, 0x0000000F},
{AUD_POLYPH80SCALEFAC, 0x00000003},
{AUD_DMD_RA_DDS, 0x00C00000},
{AUD_PLL_INT, 0x0000001E},
{AUD_PLL_DDS, 0x00000000},
{AUD_PLL_FRAC, 0x0000E542},
{AUD_START_TIMER, 0x00000000},
{AUD_DEEMPHNUMER1_R, 0x000353DE},
{AUD_DEEMPHNUMER2_R, 0x000001B1},
{AUD_PDF_DDS_CNST_BYTE2, 0x06},
{AUD_PDF_DDS_CNST_BYTE1, 0x82},
{AUD_PDF_DDS_CNST_BYTE0, 0x12},
{AUD_QAM_MODE, 0x05},
{AUD_PHACC_FREQ_8MSB, 0x34},
{AUD_PHACC_FREQ_8LSB, 0x4C},
{AUD_DEEMPHGAIN_R, 0x00006680},
{AUD_RATE_THRES_DMD, 0x000000C0},
{ /* end of list */ },
};
static const struct rlist nicam_bgdki_common[] = {
{AUD_AFE_12DB_EN, 0x00000001},
{AUD_RATE_ADJ1, 0x00000010},
{AUD_RATE_ADJ2, 0x00000040},
{AUD_RATE_ADJ3, 0x00000100},
{AUD_RATE_ADJ4, 0x00000400},
{AUD_RATE_ADJ5, 0x00001000},
{AUD_ERRLOGPERIOD_R, 0x00000fff},
{AUD_ERRINTRPTTHSHLD1_R, 0x000003ff},
{AUD_ERRINTRPTTHSHLD2_R, 0x000000ff},
{AUD_ERRINTRPTTHSHLD3_R, 0x0000003f},
{AUD_POLYPH80SCALEFAC, 0x00000003},
{AUD_DEEMPHGAIN_R, 0x000023c2},
{AUD_DEEMPHNUMER1_R, 0x0002a7bc},
{AUD_DEEMPHNUMER2_R, 0x0003023e},
{AUD_DEEMPHDENOM1_R, 0x0000f3d0},
{AUD_DEEMPHDENOM2_R, 0x00000000},
{AUD_PDF_DDS_CNST_BYTE2, 0x06},
{AUD_PDF_DDS_CNST_BYTE1, 0x82},
{AUD_QAM_MODE, 0x05},
{ /* end of list */ },
};
static const struct rlist nicam_i[] = {
{AUD_PDF_DDS_CNST_BYTE0, 0x12},
{AUD_PHACC_FREQ_8MSB, 0x3a},
{AUD_PHACC_FREQ_8LSB, 0x93},
{ /* end of list */ },
};
static const struct rlist nicam_default[] = {
{AUD_PDF_DDS_CNST_BYTE0, 0x16},
{AUD_PHACC_FREQ_8MSB, 0x34},
{AUD_PHACC_FREQ_8LSB, 0x4c},
{ /* end of list */ },
};
set_audio_start(core, SEL_NICAM);
switch (core->tvaudio) {
case WW_L:
dprintk("%s SECAM-L NICAM (status: devel)\n", __func__);
set_audio_registers(core, nicam_l);
break;
case WW_I:
dprintk("%s PAL-I NICAM (status: known-good)\n", __func__);
set_audio_registers(core, nicam_bgdki_common);
set_audio_registers(core, nicam_i);
break;
case WW_NONE:
case WW_BTSC:
case WW_BG:
case WW_DK:
case WW_EIAJ:
case WW_I2SPT:
case WW_FM:
case WW_I2SADC:
case WW_M:
dprintk("%s PAL-BGDK NICAM (status: known-good)\n", __func__);
set_audio_registers(core, nicam_bgdki_common);
set_audio_registers(core, nicam_default);
break;
}
mode |= EN_DMTRX_LR | EN_DMTRX_BYPASS;
set_audio_finish(core, mode);
}
static void set_audio_standard_A2(struct cx88_core *core, u32 mode)
{
static const struct rlist a2_bgdk_common[] = {
{AUD_ERRLOGPERIOD_R, 0x00000064},
{AUD_ERRINTRPTTHSHLD1_R, 0x00000fff},
{AUD_ERRINTRPTTHSHLD2_R, 0x0000001f},
{AUD_ERRINTRPTTHSHLD3_R, 0x0000000f},
{AUD_PDF_DDS_CNST_BYTE2, 0x06},
{AUD_PDF_DDS_CNST_BYTE1, 0x82},
{AUD_PDF_DDS_CNST_BYTE0, 0x12},
{AUD_QAM_MODE, 0x05},
{AUD_PHACC_FREQ_8MSB, 0x34},
{AUD_PHACC_FREQ_8LSB, 0x4c},
{AUD_RATE_ADJ1, 0x00000100},
{AUD_RATE_ADJ2, 0x00000200},
{AUD_RATE_ADJ3, 0x00000300},
{AUD_RATE_ADJ4, 0x00000400},
{AUD_RATE_ADJ5, 0x00000500},
{AUD_THR_FR, 0x00000000},
{AAGC_HYST, 0x0000001a},
{AUD_PILOT_BQD_1_K0, 0x0000755b},
{AUD_PILOT_BQD_1_K1, 0x00551340},
{AUD_PILOT_BQD_1_K2, 0x006d30be},
{AUD_PILOT_BQD_1_K3, 0xffd394af},
{AUD_PILOT_BQD_1_K4, 0x00400000},
{AUD_PILOT_BQD_2_K0, 0x00040000},
{AUD_PILOT_BQD_2_K1, 0x002a4841},
{AUD_PILOT_BQD_2_K2, 0x00400000},
{AUD_PILOT_BQD_2_K3, 0x00000000},
{AUD_PILOT_BQD_2_K4, 0x00000000},
{AUD_MODE_CHG_TIMER, 0x00000040},
{AUD_AFE_12DB_EN, 0x00000001},
{AUD_CORDIC_SHIFT_0, 0x00000007},
{AUD_CORDIC_SHIFT_1, 0x00000007},
{AUD_DEEMPH0_G0, 0x00000380},
{AUD_DEEMPH1_G0, 0x00000380},
{AUD_DCOC_0_SRC, 0x0000001a},
{AUD_DCOC0_SHIFT, 0x00000000},
{AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
{AUD_DCOC_0_SHIFT_IN1, 0x00000008},
{AUD_DCOC_PASS_IN, 0x00000003},
{AUD_IIR3_0_SEL, 0x00000021},
{AUD_DN2_AFC, 0x00000002},
{AUD_DCOC_1_SRC, 0x0000001b},
{AUD_DCOC1_SHIFT, 0x00000000},
{AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
{AUD_DCOC_1_SHIFT_IN1, 0x00000008},
{AUD_IIR3_1_SEL, 0x00000023},
{AUD_RDSI_SEL, 0x00000017},
{AUD_RDSI_SHIFT, 0x00000000},
{AUD_RDSQ_SEL, 0x00000017},
{AUD_RDSQ_SHIFT, 0x00000000},
{AUD_PLL_INT, 0x0000001e},
{AUD_PLL_DDS, 0x00000000},
{AUD_PLL_FRAC, 0x0000e542},
{AUD_POLYPH80SCALEFAC, 0x00000001},
{AUD_START_TIMER, 0x00000000},
{ /* end of list */ },
};
static const struct rlist a2_bg[] = {
{AUD_DMD_RA_DDS, 0x002a4f2f},
{AUD_C1_UP_THR, 0x00007000},
{AUD_C1_LO_THR, 0x00005400},
{AUD_C2_UP_THR, 0x00005400},
{AUD_C2_LO_THR, 0x00003000},
{ /* end of list */ },
};
static const struct rlist a2_dk[] = {
{AUD_DMD_RA_DDS, 0x002a4f2f},
{AUD_C1_UP_THR, 0x00007000},
{AUD_C1_LO_THR, 0x00005400},
{AUD_C2_UP_THR, 0x00005400},
{AUD_C2_LO_THR, 0x00003000},
{AUD_DN0_FREQ, 0x00003a1c},
{AUD_DN2_FREQ, 0x0000d2e0},
{ /* end of list */ },
};
static const struct rlist a1_i[] = {
{AUD_ERRLOGPERIOD_R, 0x00000064},
{AUD_ERRINTRPTTHSHLD1_R, 0x00000fff},
{AUD_ERRINTRPTTHSHLD2_R, 0x0000001f},
{AUD_ERRINTRPTTHSHLD3_R, 0x0000000f},
{AUD_PDF_DDS_CNST_BYTE2, 0x06},
{AUD_PDF_DDS_CNST_BYTE1, 0x82},
{AUD_PDF_DDS_CNST_BYTE0, 0x12},
{AUD_QAM_MODE, 0x05},
{AUD_PHACC_FREQ_8MSB, 0x3a},
{AUD_PHACC_FREQ_8LSB, 0x93},
{AUD_DMD_RA_DDS, 0x002a4f2f},
{AUD_PLL_INT, 0x0000001e},
{AUD_PLL_DDS, 0x00000004},
{AUD_PLL_FRAC, 0x0000e542},
{AUD_RATE_ADJ1, 0x00000100},
{AUD_RATE_ADJ2, 0x00000200},
{AUD_RATE_ADJ3, 0x00000300},
{AUD_RATE_ADJ4, 0x00000400},
{AUD_RATE_ADJ5, 0x00000500},
{AUD_THR_FR, 0x00000000},
{AUD_PILOT_BQD_1_K0, 0x0000755b},
{AUD_PILOT_BQD_1_K1, 0x00551340},
{AUD_PILOT_BQD_1_K2, 0x006d30be},
{AUD_PILOT_BQD_1_K3, 0xffd394af},
{AUD_PILOT_BQD_1_K4, 0x00400000},
{AUD_PILOT_BQD_2_K0, 0x00040000},
{AUD_PILOT_BQD_2_K1, 0x002a4841},
{AUD_PILOT_BQD_2_K2, 0x00400000},
{AUD_PILOT_BQD_2_K3, 0x00000000},
{AUD_PILOT_BQD_2_K4, 0x00000000},
{AUD_MODE_CHG_TIMER, 0x00000060},
{AUD_AFE_12DB_EN, 0x00000001},
{AAGC_HYST, 0x0000000a},
{AUD_CORDIC_SHIFT_0, 0x00000007},
{AUD_CORDIC_SHIFT_1, 0x00000007},
{AUD_C1_UP_THR, 0x00007000},
{AUD_C1_LO_THR, 0x00005400},
{AUD_C2_UP_THR, 0x00005400},
{AUD_C2_LO_THR, 0x00003000},
{AUD_DCOC_0_SRC, 0x0000001a},
{AUD_DCOC0_SHIFT, 0x00000000},
{AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
{AUD_DCOC_0_SHIFT_IN1, 0x00000008},
{AUD_DCOC_PASS_IN, 0x00000003},
{AUD_IIR3_0_SEL, 0x00000021},
{AUD_DN2_AFC, 0x00000002},
{AUD_DCOC_1_SRC, 0x0000001b},
{AUD_DCOC1_SHIFT, 0x00000000},
{AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
{AUD_DCOC_1_SHIFT_IN1, 0x00000008},
{AUD_IIR3_1_SEL, 0x00000023},
{AUD_DN0_FREQ, 0x000035a3},
{AUD_DN2_FREQ, 0x000029c7},
{AUD_CRDC0_SRC_SEL, 0x00000511},
{AUD_IIR1_0_SEL, 0x00000001},
{AUD_IIR1_1_SEL, 0x00000000},
{AUD_IIR3_2_SEL, 0x00000003},
{AUD_IIR3_2_SHIFT, 0x00000000},
{AUD_IIR3_0_SEL, 0x00000002},
{AUD_IIR2_0_SEL, 0x00000021},
{AUD_IIR2_0_SHIFT, 0x00000002},
{AUD_DEEMPH0_SRC_SEL, 0x0000000b},
{AUD_DEEMPH1_SRC_SEL, 0x0000000b},
{AUD_POLYPH80SCALEFAC, 0x00000001},
{AUD_START_TIMER, 0x00000000},
{ /* end of list */ },
};
static const struct rlist am_l[] = {
{AUD_ERRLOGPERIOD_R, 0x00000064},
{AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF},
{AUD_ERRINTRPTTHSHLD2_R, 0x0000001F},
{AUD_ERRINTRPTTHSHLD3_R, 0x0000000F},
{AUD_PDF_DDS_CNST_BYTE2, 0x48},
{AUD_PDF_DDS_CNST_BYTE1, 0x3D},
{AUD_QAM_MODE, 0x00},
{AUD_PDF_DDS_CNST_BYTE0, 0xf5},
{AUD_PHACC_FREQ_8MSB, 0x3a},
{AUD_PHACC_FREQ_8LSB, 0x4a},
{AUD_DEEMPHGAIN_R, 0x00006680},
{AUD_DEEMPHNUMER1_R, 0x000353DE},
{AUD_DEEMPHNUMER2_R, 0x000001B1},
{AUD_DEEMPHDENOM1_R, 0x0000F3D0},
{AUD_DEEMPHDENOM2_R, 0x00000000},
{AUD_FM_MODE_ENABLE, 0x00000007},
{AUD_POLYPH80SCALEFAC, 0x00000003},
{AUD_AFE_12DB_EN, 0x00000001},
{AAGC_GAIN, 0x00000000},
{AAGC_HYST, 0x00000018},
{AAGC_DEF, 0x00000020},
{AUD_DN0_FREQ, 0x00000000},
{AUD_POLY0_DDS_CONSTANT, 0x000E4DB2},
{AUD_DCOC_0_SRC, 0x00000021},
{AUD_IIR1_0_SEL, 0x00000000},
{AUD_IIR1_0_SHIFT, 0x00000007},
{AUD_IIR1_1_SEL, 0x00000002},
{AUD_IIR1_1_SHIFT, 0x00000000},
{AUD_DCOC_1_SRC, 0x00000003},
{AUD_DCOC1_SHIFT, 0x00000000},
{AUD_DCOC_PASS_IN, 0x00000000},
{AUD_IIR1_2_SEL, 0x00000023},
{AUD_IIR1_2_SHIFT, 0x00000000},
{AUD_IIR1_3_SEL, 0x00000004},
{AUD_IIR1_3_SHIFT, 0x00000007},
{AUD_IIR1_4_SEL, 0x00000005},
{AUD_IIR1_4_SHIFT, 0x00000007},
{AUD_IIR3_0_SEL, 0x00000007},
{AUD_IIR3_0_SHIFT, 0x00000000},
{AUD_DEEMPH0_SRC_SEL, 0x00000011},
{AUD_DEEMPH0_SHIFT, 0x00000000},
{AUD_DEEMPH0_G0, 0x00007000},
{AUD_DEEMPH0_A0, 0x00000000},
{AUD_DEEMPH0_B0, 0x00000000},
{AUD_DEEMPH0_A1, 0x00000000},
{AUD_DEEMPH0_B1, 0x00000000},
{AUD_DEEMPH1_SRC_SEL, 0x00000011},
{AUD_DEEMPH1_SHIFT, 0x00000000},
{AUD_DEEMPH1_G0, 0x00007000},
{AUD_DEEMPH1_A0, 0x00000000},
{AUD_DEEMPH1_B0, 0x00000000},
{AUD_DEEMPH1_A1, 0x00000000},
{AUD_DEEMPH1_B1, 0x00000000},
{AUD_OUT0_SEL, 0x0000003F},
{AUD_OUT1_SEL, 0x0000003F},
{AUD_DMD_RA_DDS, 0x00F5C285},
{AUD_PLL_INT, 0x0000001E},
{AUD_PLL_DDS, 0x00000000},
{AUD_PLL_FRAC, 0x0000E542},
{AUD_RATE_ADJ1, 0x00000100},
{AUD_RATE_ADJ2, 0x00000200},
{AUD_RATE_ADJ3, 0x00000300},
{AUD_RATE_ADJ4, 0x00000400},
{AUD_RATE_ADJ5, 0x00000500},
{AUD_RATE_THRES_DMD, 0x000000C0},
{ /* end of list */ },
};
static const struct rlist a2_deemph50[] = {
{AUD_DEEMPH0_G0, 0x00000380},
{AUD_DEEMPH1_G0, 0x00000380},
{AUD_DEEMPHGAIN_R, 0x000011e1},
{AUD_DEEMPHNUMER1_R, 0x0002a7bc},
{AUD_DEEMPHNUMER2_R, 0x0003023c},
{ /* end of list */ },
};
set_audio_start(core, SEL_A2);
switch (core->tvaudio) {
case WW_BG:
dprintk("%s PAL-BG A1/2 (status: known-good)\n", __func__);
set_audio_registers(core, a2_bgdk_common);
set_audio_registers(core, a2_bg);
set_audio_registers(core, a2_deemph50);
break;
case WW_DK:
dprintk("%s PAL-DK A1/2 (status: known-good)\n", __func__);
set_audio_registers(core, a2_bgdk_common);
set_audio_registers(core, a2_dk);
set_audio_registers(core, a2_deemph50);
break;
case WW_I:
dprintk("%s PAL-I A1 (status: known-good)\n", __func__);
set_audio_registers(core, a1_i);
set_audio_registers(core, a2_deemph50);
break;
case WW_L:
dprintk("%s AM-L (status: devel)\n", __func__);
set_audio_registers(core, am_l);
break;
case WW_NONE:
case WW_BTSC:
case WW_EIAJ:
case WW_I2SPT:
case WW_FM:
case WW_I2SADC:
case WW_M:
dprintk("%s Warning: wrong value\n", __func__);
return;
}
mode |= EN_FMRADIO_EN_RDS | EN_DMTRX_SUMDIFF;
set_audio_finish(core, mode);
}
static void set_audio_standard_EIAJ(struct cx88_core *core)
{
static const struct rlist eiaj[] = {
/* TODO: eiaj register settings are not there yet ... */
{ /* end of list */ },
};
dprintk("%s (status: unknown)\n", __func__);
set_audio_start(core, SEL_EIAJ);
set_audio_registers(core, eiaj);
set_audio_finish(core, EN_EIAJ_AUTO_STEREO);
}
static void set_audio_standard_FM(struct cx88_core *core,
enum cx88_deemph_type deemph)
{
static const struct rlist fm_deemph_50[] = {
{AUD_DEEMPH0_G0, 0x0C45},
{AUD_DEEMPH0_A0, 0x6262},
{AUD_DEEMPH0_B0, 0x1C29},
{AUD_DEEMPH0_A1, 0x3FC66},
{AUD_DEEMPH0_B1, 0x399A},
{AUD_DEEMPH1_G0, 0x0D80},
{AUD_DEEMPH1_A0, 0x6262},
{AUD_DEEMPH1_B0, 0x1C29},
{AUD_DEEMPH1_A1, 0x3FC66},
{AUD_DEEMPH1_B1, 0x399A},
{AUD_POLYPH80SCALEFAC, 0x0003},
{ /* end of list */ },
};
static const struct rlist fm_deemph_75[] = {
{AUD_DEEMPH0_G0, 0x091B},
{AUD_DEEMPH0_A0, 0x6B68},
{AUD_DEEMPH0_B0, 0x11EC},
{AUD_DEEMPH0_A1, 0x3FC66},
{AUD_DEEMPH0_B1, 0x399A},
{AUD_DEEMPH1_G0, 0x0AA0},
{AUD_DEEMPH1_A0, 0x6B68},
{AUD_DEEMPH1_B0, 0x11EC},
{AUD_DEEMPH1_A1, 0x3FC66},
{AUD_DEEMPH1_B1, 0x399A},
{AUD_POLYPH80SCALEFAC, 0x0003},
{ /* end of list */ },
};
/*
* It is enough to leave default values?
*
* No, it's not! The deemphasis registers are reset to the 75us
* values by default. Analyzing the spectrum of the decoded audio
* reveals that "no deemphasis" is the same as 75 us, while the 50 us
* setting results in less deemphasis.
*/
static const struct rlist fm_no_deemph[] = {
{AUD_POLYPH80SCALEFAC, 0x0003},
{ /* end of list */ },
};
dprintk("%s (status: unknown)\n", __func__);
set_audio_start(core, SEL_FMRADIO);
switch (deemph) {
default:
case FM_NO_DEEMPH:
set_audio_registers(core, fm_no_deemph);
break;
case FM_DEEMPH_50:
set_audio_registers(core, fm_deemph_50);
break;
case FM_DEEMPH_75:
set_audio_registers(core, fm_deemph_75);
break;
}
set_audio_finish(core, EN_FMRADIO_AUTO_STEREO);
}
/* ----------------------------------------------------------- */
static int cx88_detect_nicam(struct cx88_core *core)
{
int i, j = 0;
dprintk("start nicam autodetect.\n");
for (i = 0; i < 6; i++) {
/* if bit1=1 then nicam is detected */
j += ((cx_read(AUD_NICAM_STATUS2) & 0x02) >> 1);
if (j == 1) {
dprintk("nicam is detected.\n");
return 1;
}
/* wait a little bit for next reading status */
usleep_range(10000, 20000);
}
dprintk("nicam is not detected.\n");
return 0;
}
void cx88_set_tvaudio(struct cx88_core *core)
{
switch (core->tvaudio) {
case WW_BTSC:
set_audio_standard_BTSC(core, 0, EN_BTSC_AUTO_STEREO);
break;
case WW_BG:
case WW_DK:
case WW_M:
case WW_I:
case WW_L:
/* prepare all dsp registers */
set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
/*
* set nicam mode - otherwise
* AUD_NICAM_STATUS2 contains wrong values
*/
set_audio_standard_NICAM(core, EN_NICAM_AUTO_STEREO);
if (cx88_detect_nicam(core) == 0) {
/* fall back to fm / am mono */
set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
core->audiomode_current = V4L2_TUNER_MODE_MONO;
core->use_nicam = 0;
} else {
core->use_nicam = 1;
}
break;
case WW_EIAJ:
set_audio_standard_EIAJ(core);
break;
case WW_FM:
set_audio_standard_FM(core, radio_deemphasis);
break;
case WW_I2SADC:
set_audio_start(core, 0x01);
/*
* Slave/Philips/Autobaud
* NB on Nova-S bit1 NPhilipsSony appears to be inverted:
* 0= Sony, 1=Philips
*/
cx_write(AUD_I2SINPUTCNTL, core->board.i2sinputcntl);
/* Switch to "I2S ADC mode" */
cx_write(AUD_I2SCNTL, 0x1);
set_audio_finish(core, EN_I2SIN_ENABLE);
break;
case WW_NONE:
case WW_I2SPT:
pr_info("unknown tv audio mode [%d]\n", core->tvaudio);
break;
}
}
EXPORT_SYMBOL(cx88_set_tvaudio);
void cx88_newstation(struct cx88_core *core)
{
core->audiomode_manual = UNSET;
core->last_change = jiffies;
}
EXPORT_SYMBOL(cx88_newstation);
void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
{
static const char * const m[] = { "stereo", "dual mono",
"mono", "sap" };
static const char * const p[] = { "no pilot", "pilot c1",
"pilot c2", "?" };
u32 reg, mode, pilot;
reg = cx_read(AUD_STATUS);
mode = reg & 0x03;
pilot = (reg >> 2) & 0x03;
if (core->astat != reg)
dprintk("AUD_STATUS: 0x%x [%s/%s] ctl=%s\n",
reg, m[mode], p[pilot],
aud_ctl_names[cx_read(AUD_CTL) & 63]);
core->astat = reg;
t->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_SAP |
V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
t->rxsubchans = UNSET;
t->audmode = V4L2_TUNER_MODE_MONO;
switch (mode) {
case 0:
t->audmode = V4L2_TUNER_MODE_STEREO;
break;
case 1:
t->audmode = V4L2_TUNER_MODE_LANG2;
break;
case 2:
t->audmode = V4L2_TUNER_MODE_MONO;
break;
case 3:
t->audmode = V4L2_TUNER_MODE_SAP;
break;
}
switch (core->tvaudio) {
case WW_BTSC:
case WW_BG:
case WW_DK:
case WW_M:
case WW_EIAJ:
if (!core->use_nicam) {
t->rxsubchans = cx88_dsp_detect_stereo_sap(core);
break;
}
break;
case WW_NONE:
case WW_I:
case WW_L:
case WW_I2SPT:
case WW_FM:
case WW_I2SADC:
/* nothing */
break;
}
/* If software stereo detection is not supported... */
if (t->rxsubchans == UNSET) {
t->rxsubchans = V4L2_TUNER_SUB_MONO;
/*
* If the hardware itself detected stereo, also return
* stereo as an available subchannel
*/
if (t->audmode == V4L2_TUNER_MODE_STEREO)
t->rxsubchans |= V4L2_TUNER_SUB_STEREO;
}
}
EXPORT_SYMBOL(cx88_get_stereo);
void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual)
{
u32 ctl = UNSET;
u32 mask = UNSET;
if (manual) {
core->audiomode_manual = mode;
} else {
if (core->audiomode_manual != UNSET)
return;
}
core->audiomode_current = mode;
switch (core->tvaudio) {
case WW_BTSC:
switch (mode) {
case V4L2_TUNER_MODE_MONO:
set_audio_standard_BTSC(core, 0, EN_BTSC_FORCE_MONO);
break;
case V4L2_TUNER_MODE_LANG1:
set_audio_standard_BTSC(core, 0, EN_BTSC_AUTO_STEREO);
break;
case V4L2_TUNER_MODE_LANG2:
set_audio_standard_BTSC(core, 1, EN_BTSC_FORCE_SAP);
break;
case V4L2_TUNER_MODE_STEREO:
case V4L2_TUNER_MODE_LANG1_LANG2:
set_audio_standard_BTSC(core, 0, EN_BTSC_FORCE_STEREO);
break;
}
break;
case WW_BG:
case WW_DK:
case WW_M:
case WW_I:
case WW_L:
if (core->use_nicam == 1) {
switch (mode) {
case V4L2_TUNER_MODE_MONO:
case V4L2_TUNER_MODE_LANG1:
set_audio_standard_NICAM(core,
EN_NICAM_FORCE_MONO1);
break;
case V4L2_TUNER_MODE_LANG2:
set_audio_standard_NICAM(core,
EN_NICAM_FORCE_MONO2);
break;
case V4L2_TUNER_MODE_STEREO:
case V4L2_TUNER_MODE_LANG1_LANG2:
set_audio_standard_NICAM(core,
EN_NICAM_FORCE_STEREO);
break;
}
} else {
if ((core->tvaudio == WW_I) ||
(core->tvaudio == WW_L)) {
/* fall back to fm / am mono */
set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
} else {
/* TODO: Add A2 autodection */
mask = 0x3f;
switch (mode) {
case V4L2_TUNER_MODE_MONO:
case V4L2_TUNER_MODE_LANG1:
ctl = EN_A2_FORCE_MONO1;
break;
case V4L2_TUNER_MODE_LANG2:
ctl = EN_A2_FORCE_MONO2;
break;
case V4L2_TUNER_MODE_STEREO:
case V4L2_TUNER_MODE_LANG1_LANG2:
ctl = EN_A2_FORCE_STEREO;
break;
}
}
}
break;
case WW_FM:
switch (mode) {
case V4L2_TUNER_MODE_MONO:
ctl = EN_FMRADIO_FORCE_MONO;
mask = 0x3f;
break;
case V4L2_TUNER_MODE_STEREO:
ctl = EN_FMRADIO_AUTO_STEREO;
mask = 0x3f;
break;
}
break;
case WW_I2SADC:
case WW_NONE:
case WW_EIAJ:
case WW_I2SPT:
/* DO NOTHING */
break;
}
if (ctl != UNSET) {
dprintk("cx88_set_stereo: mask 0x%x, ctl 0x%x [status=0x%x,ctl=0x%x,vol=0x%x]\n",
mask, ctl, cx_read(AUD_STATUS),
cx_read(AUD_CTL), cx_sread(SHADOW_AUD_VOL_CTL));
cx_andor(AUD_CTL, mask, ctl);
}
}
EXPORT_SYMBOL(cx88_set_stereo);
int cx88_audio_thread(void *data)
{
struct cx88_core *core = data;
struct v4l2_tuner t;
u32 mode = 0;
dprintk("cx88: tvaudio thread started\n");
set_freezable();
for (;;) {
msleep_interruptible(1000);
if (kthread_should_stop())
break;
try_to_freeze();
switch (core->tvaudio) {
case WW_BG:
case WW_DK:
case WW_M:
case WW_I:
case WW_L:
if (core->use_nicam)
goto hw_autodetect;
/* just monitor the audio status for now ... */
memset(&t, 0, sizeof(t));
cx88_get_stereo(core, &t);
if (core->audiomode_manual != UNSET)
/* manually set, don't do anything. */
continue;
/* monitor signal and set stereo if available */
if (t.rxsubchans & V4L2_TUNER_SUB_STEREO)
mode = V4L2_TUNER_MODE_STEREO;
else
mode = V4L2_TUNER_MODE_MONO;
if (mode == core->audiomode_current)
continue;
/* automatically switch to best available mode */
cx88_set_stereo(core, mode, 0);
break;
case WW_NONE:
case WW_BTSC:
case WW_EIAJ:
case WW_I2SPT:
case WW_FM:
case WW_I2SADC:
hw_autodetect:
/*
* stereo autodetection is supported by hardware so
* we don't need to do it manually. Do nothing.
*/
break;
}
}
dprintk("cx88: tvaudio thread exiting\n");
return 0;
}
EXPORT_SYMBOL(cx88_audio_thread);
| linux-master | drivers/media/pci/cx88/cx88-tvaudio.c |
// SPDX-License-Identifier: GPL-2.0
/*
*/
#include "cx88.h"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
static unsigned int vbi_debug;
module_param(vbi_debug, int, 0644);
MODULE_PARM_DESC(vbi_debug, "enable debug messages [vbi]");
#define dprintk(level, fmt, arg...) do { \
if (vbi_debug >= level) \
printk(KERN_DEBUG pr_fmt("%s: vbi:" fmt), \
__func__, ##arg); \
} while (0)
/* ------------------------------------------------------------------ */
int cx8800_vbi_fmt(struct file *file, void *priv,
struct v4l2_format *f)
{
struct cx8800_dev *dev = video_drvdata(file);
f->fmt.vbi.samples_per_line = VBI_LINE_LENGTH;
f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
f->fmt.vbi.offset = 244;
if (dev->core->tvnorm & V4L2_STD_525_60) {
/* ntsc */
f->fmt.vbi.sampling_rate = 28636363;
f->fmt.vbi.start[0] = 10;
f->fmt.vbi.start[1] = 273;
f->fmt.vbi.count[0] = VBI_LINE_NTSC_COUNT;
f->fmt.vbi.count[1] = VBI_LINE_NTSC_COUNT;
} else if (dev->core->tvnorm & V4L2_STD_625_50) {
/* pal */
f->fmt.vbi.sampling_rate = 35468950;
f->fmt.vbi.start[0] = V4L2_VBI_ITU_625_F1_START + 5;
f->fmt.vbi.start[1] = V4L2_VBI_ITU_625_F2_START + 5;
f->fmt.vbi.count[0] = VBI_LINE_PAL_COUNT;
f->fmt.vbi.count[1] = VBI_LINE_PAL_COUNT;
}
return 0;
}
static int cx8800_start_vbi_dma(struct cx8800_dev *dev,
struct cx88_dmaqueue *q,
struct cx88_buffer *buf)
{
struct cx88_core *core = dev->core;
/* setup fifo + format */
cx88_sram_channel_setup(dev->core, &cx88_sram_channels[SRAM_CH24],
VBI_LINE_LENGTH, buf->risc.dma);
cx_write(MO_VBOS_CONTROL, (1 << 18) | /* comb filter delay fixup */
(1 << 15) | /* enable vbi capture */
(1 << 11));
/* reset counter */
cx_write(MO_VBI_GPCNTRL, GP_COUNT_CONTROL_RESET);
q->count = 0;
/* enable irqs */
cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
cx_set(MO_VID_INTMSK, 0x0f0088);
/* enable capture */
cx_set(VID_CAPTURE_CONTROL, 0x18);
/* start dma */
cx_set(MO_DEV_CNTRL2, (1 << 5));
cx_set(MO_VID_DMACNTRL, 0x88);
return 0;
}
void cx8800_stop_vbi_dma(struct cx8800_dev *dev)
{
struct cx88_core *core = dev->core;
/* stop dma */
cx_clear(MO_VID_DMACNTRL, 0x88);
/* disable capture */
cx_clear(VID_CAPTURE_CONTROL, 0x18);
/* disable irqs */
cx_clear(MO_PCI_INTMSK, PCI_INT_VIDINT);
cx_clear(MO_VID_INTMSK, 0x0f0088);
}
int cx8800_restart_vbi_queue(struct cx8800_dev *dev,
struct cx88_dmaqueue *q)
{
struct cx88_buffer *buf;
if (list_empty(&q->active))
return 0;
buf = list_entry(q->active.next, struct cx88_buffer, list);
dprintk(2, "restart_queue [%p/%d]: restart dma\n",
buf, buf->vb.vb2_buf.index);
cx8800_start_vbi_dma(dev, q, buf);
return 0;
}
/* ------------------------------------------------------------------ */
static int queue_setup(struct vb2_queue *q,
unsigned int *num_buffers, unsigned int *num_planes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct cx8800_dev *dev = q->drv_priv;
*num_planes = 1;
if (dev->core->tvnorm & V4L2_STD_525_60)
sizes[0] = VBI_LINE_NTSC_COUNT * VBI_LINE_LENGTH * 2;
else
sizes[0] = VBI_LINE_PAL_COUNT * VBI_LINE_LENGTH * 2;
return 0;
}
static int buffer_prepare(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
unsigned int lines;
unsigned int size;
if (dev->core->tvnorm & V4L2_STD_525_60)
lines = VBI_LINE_NTSC_COUNT;
else
lines = VBI_LINE_PAL_COUNT;
size = lines * VBI_LINE_LENGTH * 2;
if (vb2_plane_size(vb, 0) < size)
return -EINVAL;
vb2_set_plane_payload(vb, 0, size);
return cx88_risc_buffer(dev->pci, &buf->risc, sgt->sgl,
0, VBI_LINE_LENGTH * lines,
VBI_LINE_LENGTH, 0,
lines);
}
static void buffer_finish(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
struct cx88_riscmem *risc = &buf->risc;
if (risc->cpu)
dma_free_coherent(&dev->pci->dev, risc->size, risc->cpu,
risc->dma);
memset(risc, 0, sizeof(*risc));
}
static void buffer_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
struct cx88_buffer *prev;
struct cx88_dmaqueue *q = &dev->vbiq;
/* add jump to start */
buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8);
buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8);
if (list_empty(&q->active)) {
list_add_tail(&buf->list, &q->active);
dprintk(2, "[%p/%d] vbi_queue - first active\n",
buf, buf->vb.vb2_buf.index);
} else {
buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
prev = list_entry(q->active.prev, struct cx88_buffer, list);
list_add_tail(&buf->list, &q->active);
prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
dprintk(2, "[%p/%d] buffer_queue - append to active\n",
buf, buf->vb.vb2_buf.index);
}
}
static int start_streaming(struct vb2_queue *q, unsigned int count)
{
struct cx8800_dev *dev = q->drv_priv;
struct cx88_dmaqueue *dmaq = &dev->vbiq;
struct cx88_buffer *buf = list_entry(dmaq->active.next,
struct cx88_buffer, list);
cx8800_start_vbi_dma(dev, dmaq, buf);
return 0;
}
static void stop_streaming(struct vb2_queue *q)
{
struct cx8800_dev *dev = q->drv_priv;
struct cx88_core *core = dev->core;
struct cx88_dmaqueue *dmaq = &dev->vbiq;
unsigned long flags;
cx_clear(MO_VID_DMACNTRL, 0x11);
cx_clear(VID_CAPTURE_CONTROL, 0x06);
cx8800_stop_vbi_dma(dev);
spin_lock_irqsave(&dev->slock, flags);
while (!list_empty(&dmaq->active)) {
struct cx88_buffer *buf = list_entry(dmaq->active.next,
struct cx88_buffer, list);
list_del(&buf->list);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&dev->slock, flags);
}
const struct vb2_ops cx8800_vbi_qops = {
.queue_setup = queue_setup,
.buf_prepare = buffer_prepare,
.buf_finish = buffer_finish,
.buf_queue = buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = start_streaming,
.stop_streaming = stop_streaming,
};
| linux-master | drivers/media/pci/cx88/cx88-vbi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* cx88-i2c.c -- all the i2c code is here
*
* Copyright (C) 1996,97,98 Ralph Metzler ([email protected])
* & Marcus Metzler ([email protected])
* (c) 2002 Yurij Sysoev <[email protected]>
* (c) 1999-2003 Gerd Knorr <[email protected]>
* (c) 2005 Mauro Carvalho Chehab <[email protected]>
* - Multituner support and i2c address binding
*/
#include "cx88.h"
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <media/v4l2-common.h>
static unsigned int i2c_debug;
module_param(i2c_debug, int, 0644);
MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]");
static unsigned int i2c_scan;
module_param(i2c_scan, int, 0444);
MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time");
static unsigned int i2c_udelay = 5;
module_param(i2c_udelay, int, 0644);
MODULE_PARM_DESC(i2c_udelay,
"i2c delay at insmod time, in usecs (should be 5 or higher). Lower value means higher bus speed.");
#define dprintk(level, fmt, arg...) do { \
if (i2c_debug >= level) \
printk(KERN_DEBUG pr_fmt("%s: i2c:" fmt), \
__func__, ##arg); \
} while (0)
/* ----------------------------------------------------------------------- */
static void cx8800_bit_setscl(void *data, int state)
{
struct cx88_core *core = data;
if (state)
core->i2c_state |= 0x02;
else
core->i2c_state &= ~0x02;
cx_write(MO_I2C, core->i2c_state);
cx_read(MO_I2C);
}
static void cx8800_bit_setsda(void *data, int state)
{
struct cx88_core *core = data;
if (state)
core->i2c_state |= 0x01;
else
core->i2c_state &= ~0x01;
cx_write(MO_I2C, core->i2c_state);
cx_read(MO_I2C);
}
static int cx8800_bit_getscl(void *data)
{
struct cx88_core *core = data;
u32 state;
state = cx_read(MO_I2C);
return state & 0x02 ? 1 : 0;
}
static int cx8800_bit_getsda(void *data)
{
struct cx88_core *core = data;
u32 state;
state = cx_read(MO_I2C);
return state & 0x01;
}
/* ----------------------------------------------------------------------- */
static const struct i2c_algo_bit_data cx8800_i2c_algo_template = {
.setsda = cx8800_bit_setsda,
.setscl = cx8800_bit_setscl,
.getsda = cx8800_bit_getsda,
.getscl = cx8800_bit_getscl,
.udelay = 16,
.timeout = 200,
};
/* ----------------------------------------------------------------------- */
static const char * const i2c_devs[128] = {
[0x1c >> 1] = "lgdt330x",
[0x86 >> 1] = "tda9887/cx22702",
[0xa0 >> 1] = "eeprom",
[0xc0 >> 1] = "tuner (analog)",
[0xc2 >> 1] = "tuner (analog/dvb)",
[0xc8 >> 1] = "xc5000",
};
static void do_i2c_scan(const char *name, struct i2c_client *c)
{
unsigned char buf;
int i, rc;
for (i = 0; i < ARRAY_SIZE(i2c_devs); i++) {
c->addr = i;
rc = i2c_master_recv(c, &buf, 0);
if (rc < 0)
continue;
pr_info("i2c scan: found device @ 0x%x [%s]\n",
i << 1, i2c_devs[i] ? i2c_devs[i] : "???");
}
}
/* init + register i2c adapter */
int cx88_i2c_init(struct cx88_core *core, struct pci_dev *pci)
{
/* Prevents usage of invalid delay values */
if (i2c_udelay < 5)
i2c_udelay = 5;
core->i2c_algo = cx8800_i2c_algo_template;
core->i2c_adap.dev.parent = &pci->dev;
strscpy(core->i2c_adap.name, core->name, sizeof(core->i2c_adap.name));
core->i2c_adap.owner = THIS_MODULE;
core->i2c_algo.udelay = i2c_udelay;
core->i2c_algo.data = core;
i2c_set_adapdata(&core->i2c_adap, &core->v4l2_dev);
core->i2c_adap.algo_data = &core->i2c_algo;
core->i2c_client.adapter = &core->i2c_adap;
strscpy(core->i2c_client.name, "cx88xx internal", I2C_NAME_SIZE);
cx8800_bit_setscl(core, 1);
cx8800_bit_setsda(core, 1);
core->i2c_rc = i2c_bit_add_bus(&core->i2c_adap);
if (core->i2c_rc == 0) {
static u8 tuner_data[] = {
0x0b, 0xdc, 0x86, 0x52 };
static struct i2c_msg tuner_msg = {
.flags = 0,
.addr = 0xc2 >> 1,
.buf = tuner_data,
.len = 4
};
dprintk(1, "i2c register ok\n");
switch (core->boardnr) {
case CX88_BOARD_HAUPPAUGE_HVR1300:
case CX88_BOARD_HAUPPAUGE_HVR3000:
case CX88_BOARD_HAUPPAUGE_HVR4000:
pr_info("i2c init: enabling analog demod on HVR1300/3000/4000 tuner\n");
i2c_transfer(core->i2c_client.adapter, &tuner_msg, 1);
break;
default:
break;
}
if (i2c_scan)
do_i2c_scan(core->name, &core->i2c_client);
} else
pr_err("i2c register FAILED\n");
return core->i2c_rc;
}
| linux-master | drivers/media/pci/cx88/cx88-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Linux driver the digital TV devices equipped with B2C2 FlexcopII(b)/III
* flexcop-pci.c - covers the PCI part including DMA transfers
* see flexcop.c for copyright information
*/
#define FC_LOG_PREFIX "flexcop-pci"
#include "flexcop-common.h"
static int enable_pid_filtering = 1;
module_param(enable_pid_filtering, int, 0444);
MODULE_PARM_DESC(enable_pid_filtering,
"enable hardware pid filtering: supported values: 0 (fullts), 1");
static int irq_chk_intv = 100;
module_param(irq_chk_intv, int, 0644);
MODULE_PARM_DESC(irq_chk_intv, "set the interval for IRQ streaming watchdog.");
#ifdef CONFIG_DVB_B2C2_FLEXCOP_DEBUG
#define dprintk(level, args...) \
do { if ((debug & (level))) printk(args); } while (0)
#define DEBSTATUS ""
#else
#define dprintk(level, args...) no_printk(args)
#define DEBSTATUS " (debugging is not enabled)"
#endif
#define deb_info(args...) dprintk(0x01, args)
#define deb_reg(args...) dprintk(0x02, args)
#define deb_ts(args...) dprintk(0x04, args)
#define deb_irq(args...) dprintk(0x08, args)
#define deb_chk(args...) dprintk(0x10, args)
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug,
"set debug level (1=info,2=regs,4=TS,8=irqdma,16=check (|-able))."
DEBSTATUS);
#define DRIVER_VERSION "0.1"
#define DRIVER_NAME "flexcop-pci"
#define DRIVER_AUTHOR "Patrick Boettcher <[email protected]>"
struct flexcop_pci {
struct pci_dev *pdev;
#define FC_PCI_INIT 0x01
#define FC_PCI_DMA_INIT 0x02
int init_state;
void __iomem *io_mem;
u32 irq;
/* buffersize (at least for DMA1, need to be % 188 == 0,
* this logic is required */
#define FC_DEFAULT_DMA1_BUFSIZE (1280 * 188)
#define FC_DEFAULT_DMA2_BUFSIZE (10 * 188)
struct flexcop_dma dma[2];
int active_dma1_addr; /* 0 = addr0 of dma1; 1 = addr1 of dma1 */
u32 last_dma1_cur_pos;
/* position of the pointer last time the timer/packet irq occurred */
int count;
int count_prev;
int stream_problem;
spinlock_t irq_lock;
unsigned long last_irq;
struct delayed_work irq_check_work;
struct flexcop_device *fc_dev;
};
static int lastwreg, lastwval, lastrreg, lastrval;
static flexcop_ibi_value flexcop_pci_read_ibi_reg(struct flexcop_device *fc,
flexcop_ibi_register r)
{
struct flexcop_pci *fc_pci = fc->bus_specific;
flexcop_ibi_value v;
v.raw = readl(fc_pci->io_mem + r);
if (lastrreg != r || lastrval != v.raw) {
lastrreg = r; lastrval = v.raw;
deb_reg("new rd: %3x: %08x\n", r, v.raw);
}
return v;
}
static int flexcop_pci_write_ibi_reg(struct flexcop_device *fc,
flexcop_ibi_register r, flexcop_ibi_value v)
{
struct flexcop_pci *fc_pci = fc->bus_specific;
if (lastwreg != r || lastwval != v.raw) {
lastwreg = r; lastwval = v.raw;
deb_reg("new wr: %3x: %08x\n", r, v.raw);
}
writel(v.raw, fc_pci->io_mem + r);
return 0;
}
static void flexcop_pci_irq_check_work(struct work_struct *work)
{
struct flexcop_pci *fc_pci =
container_of(work, struct flexcop_pci, irq_check_work.work);
struct flexcop_device *fc = fc_pci->fc_dev;
if (fc->feedcount) {
if (fc_pci->count == fc_pci->count_prev) {
deb_chk("no IRQ since the last check\n");
if (fc_pci->stream_problem++ == 3) {
struct dvb_demux_feed *feed;
deb_info("flexcop-pci: stream problem, resetting pid filter\n");
spin_lock_irq(&fc->demux.lock);
list_for_each_entry(feed, &fc->demux.feed_list,
list_head) {
flexcop_pid_feed_control(fc, feed, 0);
}
list_for_each_entry(feed, &fc->demux.feed_list,
list_head) {
flexcop_pid_feed_control(fc, feed, 1);
}
spin_unlock_irq(&fc->demux.lock);
fc_pci->stream_problem = 0;
}
} else {
fc_pci->stream_problem = 0;
fc_pci->count_prev = fc_pci->count;
}
}
schedule_delayed_work(&fc_pci->irq_check_work,
msecs_to_jiffies(irq_chk_intv < 100 ? 100 : irq_chk_intv));
}
/* When PID filtering is turned on, we use the timer IRQ, because small amounts
* of data need to be passed to the user space instantly as well. When PID
* filtering is turned off, we use the page-change-IRQ */
static irqreturn_t flexcop_pci_isr(int irq, void *dev_id)
{
struct flexcop_pci *fc_pci = dev_id;
struct flexcop_device *fc = fc_pci->fc_dev;
unsigned long flags;
flexcop_ibi_value v;
irqreturn_t ret = IRQ_HANDLED;
spin_lock_irqsave(&fc_pci->irq_lock, flags);
v = fc->read_ibi_reg(fc, irq_20c);
/* errors */
if (v.irq_20c.Data_receiver_error)
deb_chk("data receiver error\n");
if (v.irq_20c.Continuity_error_flag)
deb_chk("Continuity error flag is set\n");
if (v.irq_20c.LLC_SNAP_FLAG_set)
deb_chk("LLC_SNAP_FLAG_set is set\n");
if (v.irq_20c.Transport_Error)
deb_chk("Transport error\n");
if ((fc_pci->count % 1000) == 0)
deb_chk("%d valid irq took place so far\n", fc_pci->count);
if (v.irq_20c.DMA1_IRQ_Status == 1) {
if (fc_pci->active_dma1_addr == 0)
flexcop_pass_dmx_packets(fc_pci->fc_dev,
fc_pci->dma[0].cpu_addr0,
fc_pci->dma[0].size / 188);
else
flexcop_pass_dmx_packets(fc_pci->fc_dev,
fc_pci->dma[0].cpu_addr1,
fc_pci->dma[0].size / 188);
deb_irq("page change to page: %d\n",!fc_pci->active_dma1_addr);
fc_pci->active_dma1_addr = !fc_pci->active_dma1_addr;
/* for the timer IRQ we only can use buffer dmx feeding, because we don't have
* complete TS packets when reading from the DMA memory */
} else if (v.irq_20c.DMA1_Timer_Status == 1) {
dma_addr_t cur_addr =
fc->read_ibi_reg(fc,dma1_008).dma_0x8.dma_cur_addr << 2;
u32 cur_pos = cur_addr - fc_pci->dma[0].dma_addr0;
if (cur_pos > fc_pci->dma[0].size * 2)
goto error;
deb_irq("%u irq: %08x cur_addr: %llx: cur_pos: %08x, last_cur_pos: %08x ",
jiffies_to_usecs(jiffies - fc_pci->last_irq),
v.raw, (unsigned long long)cur_addr, cur_pos,
fc_pci->last_dma1_cur_pos);
fc_pci->last_irq = jiffies;
/* buffer end was reached, restarted from the beginning
* pass the data from last_cur_pos to the buffer end to the demux
*/
if (cur_pos < fc_pci->last_dma1_cur_pos) {
deb_irq(" end was reached: passing %d bytes ",
(fc_pci->dma[0].size*2 - 1) -
fc_pci->last_dma1_cur_pos);
flexcop_pass_dmx_data(fc_pci->fc_dev,
fc_pci->dma[0].cpu_addr0 +
fc_pci->last_dma1_cur_pos,
(fc_pci->dma[0].size*2) -
fc_pci->last_dma1_cur_pos);
fc_pci->last_dma1_cur_pos = 0;
}
if (cur_pos > fc_pci->last_dma1_cur_pos) {
deb_irq(" passing %d bytes ",
cur_pos - fc_pci->last_dma1_cur_pos);
flexcop_pass_dmx_data(fc_pci->fc_dev,
fc_pci->dma[0].cpu_addr0 +
fc_pci->last_dma1_cur_pos,
cur_pos - fc_pci->last_dma1_cur_pos);
}
deb_irq("\n");
fc_pci->last_dma1_cur_pos = cur_pos;
fc_pci->count++;
} else {
deb_irq("isr for flexcop called, apparently without reason (%08x)\n",
v.raw);
ret = IRQ_NONE;
}
error:
spin_unlock_irqrestore(&fc_pci->irq_lock, flags);
return ret;
}
static int flexcop_pci_stream_control(struct flexcop_device *fc, int onoff)
{
struct flexcop_pci *fc_pci = fc->bus_specific;
if (onoff) {
flexcop_dma_config(fc, &fc_pci->dma[0], FC_DMA_1);
flexcop_dma_config(fc, &fc_pci->dma[1], FC_DMA_2);
flexcop_dma_config_timer(fc, FC_DMA_1, 0);
flexcop_dma_xfer_control(fc, FC_DMA_1,
FC_DMA_SUBADDR_0 | FC_DMA_SUBADDR_1, 1);
deb_irq("DMA xfer enabled\n");
fc_pci->last_dma1_cur_pos = 0;
flexcop_dma_control_timer_irq(fc, FC_DMA_1, 1);
deb_irq("IRQ enabled\n");
fc_pci->count_prev = fc_pci->count;
} else {
flexcop_dma_control_timer_irq(fc, FC_DMA_1, 0);
deb_irq("IRQ disabled\n");
flexcop_dma_xfer_control(fc, FC_DMA_1,
FC_DMA_SUBADDR_0 | FC_DMA_SUBADDR_1, 0);
deb_irq("DMA xfer disabled\n");
}
return 0;
}
static int flexcop_pci_dma_init(struct flexcop_pci *fc_pci)
{
int ret;
ret = flexcop_dma_allocate(fc_pci->pdev, &fc_pci->dma[0],
FC_DEFAULT_DMA1_BUFSIZE);
if (ret != 0)
return ret;
ret = flexcop_dma_allocate(fc_pci->pdev, &fc_pci->dma[1],
FC_DEFAULT_DMA2_BUFSIZE);
if (ret != 0) {
flexcop_dma_free(&fc_pci->dma[0]);
return ret;
}
flexcop_sram_set_dest(fc_pci->fc_dev, FC_SRAM_DEST_MEDIA |
FC_SRAM_DEST_NET, FC_SRAM_DEST_TARGET_DMA1);
flexcop_sram_set_dest(fc_pci->fc_dev, FC_SRAM_DEST_CAO |
FC_SRAM_DEST_CAI, FC_SRAM_DEST_TARGET_DMA2);
fc_pci->init_state |= FC_PCI_DMA_INIT;
return ret;
}
static void flexcop_pci_dma_exit(struct flexcop_pci *fc_pci)
{
if (fc_pci->init_state & FC_PCI_DMA_INIT) {
flexcop_dma_free(&fc_pci->dma[0]);
flexcop_dma_free(&fc_pci->dma[1]);
}
fc_pci->init_state &= ~FC_PCI_DMA_INIT;
}
static int flexcop_pci_init(struct flexcop_pci *fc_pci)
{
int ret;
info("card revision %x", fc_pci->pdev->revision);
if ((ret = pci_enable_device(fc_pci->pdev)) != 0)
return ret;
pci_set_master(fc_pci->pdev);
if ((ret = pci_request_regions(fc_pci->pdev, DRIVER_NAME)) != 0)
goto err_pci_disable_device;
fc_pci->io_mem = pci_iomap(fc_pci->pdev, 0, 0x800);
if (!fc_pci->io_mem) {
err("cannot map io memory\n");
ret = -EIO;
goto err_pci_release_regions;
}
pci_set_drvdata(fc_pci->pdev, fc_pci);
spin_lock_init(&fc_pci->irq_lock);
if ((ret = request_irq(fc_pci->pdev->irq, flexcop_pci_isr,
IRQF_SHARED, DRIVER_NAME, fc_pci)) != 0)
goto err_pci_iounmap;
fc_pci->init_state |= FC_PCI_INIT;
return ret;
err_pci_iounmap:
pci_iounmap(fc_pci->pdev, fc_pci->io_mem);
err_pci_release_regions:
pci_release_regions(fc_pci->pdev);
err_pci_disable_device:
pci_disable_device(fc_pci->pdev);
return ret;
}
static void flexcop_pci_exit(struct flexcop_pci *fc_pci)
{
if (fc_pci->init_state & FC_PCI_INIT) {
free_irq(fc_pci->pdev->irq, fc_pci);
pci_iounmap(fc_pci->pdev, fc_pci->io_mem);
pci_release_regions(fc_pci->pdev);
pci_disable_device(fc_pci->pdev);
}
fc_pci->init_state &= ~FC_PCI_INIT;
}
static int flexcop_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct flexcop_device *fc;
struct flexcop_pci *fc_pci;
int ret = -ENOMEM;
if ((fc = flexcop_device_kmalloc(sizeof(struct flexcop_pci))) == NULL) {
err("out of memory\n");
return -ENOMEM;
}
/* general flexcop init */
fc_pci = fc->bus_specific;
fc_pci->fc_dev = fc;
fc->read_ibi_reg = flexcop_pci_read_ibi_reg;
fc->write_ibi_reg = flexcop_pci_write_ibi_reg;
fc->i2c_request = flexcop_i2c_request;
fc->get_mac_addr = flexcop_eeprom_check_mac_addr;
fc->stream_control = flexcop_pci_stream_control;
if (enable_pid_filtering)
info("will use the HW PID filter.");
else
info("will pass the complete TS to the demuxer.");
fc->pid_filtering = enable_pid_filtering;
fc->bus_type = FC_PCI;
fc->dev = &pdev->dev;
fc->owner = THIS_MODULE;
/* bus specific part */
fc_pci->pdev = pdev;
if ((ret = flexcop_pci_init(fc_pci)) != 0)
goto err_kfree;
/* init flexcop */
if ((ret = flexcop_device_initialize(fc)) != 0)
goto err_pci_exit;
/* init dma */
if ((ret = flexcop_pci_dma_init(fc_pci)) != 0)
goto err_fc_exit;
INIT_DELAYED_WORK(&fc_pci->irq_check_work, flexcop_pci_irq_check_work);
if (irq_chk_intv > 0)
schedule_delayed_work(&fc_pci->irq_check_work,
msecs_to_jiffies(irq_chk_intv < 100 ?
100 :
irq_chk_intv));
return ret;
err_fc_exit:
flexcop_device_exit(fc);
err_pci_exit:
flexcop_pci_exit(fc_pci);
err_kfree:
flexcop_device_kfree(fc);
return ret;
}
/* in theory every _exit function should be called exactly two times,
* here and in the bail-out-part of the _init-function
*/
static void flexcop_pci_remove(struct pci_dev *pdev)
{
struct flexcop_pci *fc_pci = pci_get_drvdata(pdev);
if (irq_chk_intv > 0)
cancel_delayed_work(&fc_pci->irq_check_work);
flexcop_pci_dma_exit(fc_pci);
flexcop_device_exit(fc_pci->fc_dev);
flexcop_pci_exit(fc_pci);
flexcop_device_kfree(fc_pci->fc_dev);
}
static const struct pci_device_id flexcop_pci_tbl[] = {
{ PCI_DEVICE(0x13d0, 0x2103) },
{ },
};
MODULE_DEVICE_TABLE(pci, flexcop_pci_tbl);
static struct pci_driver flexcop_pci_driver = {
.name = "b2c2_flexcop_pci",
.id_table = flexcop_pci_tbl,
.probe = flexcop_pci_probe,
.remove = flexcop_pci_remove,
};
module_pci_driver(flexcop_pci_driver);
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_NAME);
MODULE_LICENSE("GPL");
| linux-master | drivers/media/pci/b2c2/flexcop-pci.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
* flexcop-dma.c - configuring and controlling the DMA of the FlexCop
* see flexcop.c for copyright information
*/
#include "flexcop.h"
int flexcop_dma_allocate(struct pci_dev *pdev,
struct flexcop_dma *dma, u32 size)
{
u8 *tcpu;
dma_addr_t tdma = 0;
if (size % 2) {
err("dma buffersize has to be even.");
return -EINVAL;
}
tcpu = dma_alloc_coherent(&pdev->dev, size, &tdma, GFP_KERNEL);
if (tcpu != NULL) {
dma->pdev = pdev;
dma->cpu_addr0 = tcpu;
dma->dma_addr0 = tdma;
dma->cpu_addr1 = tcpu + size/2;
dma->dma_addr1 = tdma + size/2;
dma->size = size/2;
return 0;
}
return -ENOMEM;
}
EXPORT_SYMBOL(flexcop_dma_allocate);
void flexcop_dma_free(struct flexcop_dma *dma)
{
dma_free_coherent(&dma->pdev->dev, dma->size * 2, dma->cpu_addr0,
dma->dma_addr0);
memset(dma, 0, sizeof(struct flexcop_dma));
}
EXPORT_SYMBOL(flexcop_dma_free);
int flexcop_dma_config(struct flexcop_device *fc,
struct flexcop_dma *dma,
flexcop_dma_index_t dma_idx)
{
flexcop_ibi_value v0x0, v0x4, v0xc;
v0x0.raw = v0x4.raw = v0xc.raw = 0;
v0x0.dma_0x0.dma_address0 = dma->dma_addr0 >> 2;
v0xc.dma_0xc.dma_address1 = dma->dma_addr1 >> 2;
v0x4.dma_0x4_write.dma_addr_size = dma->size / 4;
if ((dma_idx & FC_DMA_1) == dma_idx) {
fc->write_ibi_reg(fc, dma1_000, v0x0);
fc->write_ibi_reg(fc, dma1_004, v0x4);
fc->write_ibi_reg(fc, dma1_00c, v0xc);
} else if ((dma_idx & FC_DMA_2) == dma_idx) {
fc->write_ibi_reg(fc, dma2_010, v0x0);
fc->write_ibi_reg(fc, dma2_014, v0x4);
fc->write_ibi_reg(fc, dma2_01c, v0xc);
} else {
err("either DMA1 or DMA2 can be configured within one %s call.",
__func__);
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL(flexcop_dma_config);
/* start the DMA transfers, but not the DMA IRQs */
int flexcop_dma_xfer_control(struct flexcop_device *fc,
flexcop_dma_index_t dma_idx,
flexcop_dma_addr_index_t index,
int onoff)
{
flexcop_ibi_value v0x0, v0xc;
flexcop_ibi_register r0x0, r0xc;
if ((dma_idx & FC_DMA_1) == dma_idx) {
r0x0 = dma1_000;
r0xc = dma1_00c;
} else if ((dma_idx & FC_DMA_2) == dma_idx) {
r0x0 = dma2_010;
r0xc = dma2_01c;
} else {
err("transfer DMA1 or DMA2 can be started within one %s call.",
__func__);
return -EINVAL;
}
v0x0 = fc->read_ibi_reg(fc, r0x0);
v0xc = fc->read_ibi_reg(fc, r0xc);
deb_rdump("reg: %03x: %x\n", r0x0, v0x0.raw);
deb_rdump("reg: %03x: %x\n", r0xc, v0xc.raw);
if (index & FC_DMA_SUBADDR_0)
v0x0.dma_0x0.dma_0start = onoff;
if (index & FC_DMA_SUBADDR_1)
v0xc.dma_0xc.dma_1start = onoff;
fc->write_ibi_reg(fc, r0x0, v0x0);
fc->write_ibi_reg(fc, r0xc, v0xc);
deb_rdump("reg: %03x: %x\n", r0x0, v0x0.raw);
deb_rdump("reg: %03x: %x\n", r0xc, v0xc.raw);
return 0;
}
EXPORT_SYMBOL(flexcop_dma_xfer_control);
static int flexcop_dma_remap(struct flexcop_device *fc,
flexcop_dma_index_t dma_idx,
int onoff)
{
flexcop_ibi_register r = (dma_idx & FC_DMA_1) ? dma1_00c : dma2_01c;
flexcop_ibi_value v = fc->read_ibi_reg(fc, r);
deb_info("%s\n", __func__);
v.dma_0xc.remap_enable = onoff;
fc->write_ibi_reg(fc, r, v);
return 0;
}
int flexcop_dma_control_size_irq(struct flexcop_device *fc,
flexcop_dma_index_t no,
int onoff)
{
flexcop_ibi_value v = fc->read_ibi_reg(fc, ctrl_208);
if (no & FC_DMA_1)
v.ctrl_208.DMA1_IRQ_Enable_sig = onoff;
if (no & FC_DMA_2)
v.ctrl_208.DMA2_IRQ_Enable_sig = onoff;
fc->write_ibi_reg(fc, ctrl_208, v);
return 0;
}
EXPORT_SYMBOL(flexcop_dma_control_size_irq);
int flexcop_dma_control_timer_irq(struct flexcop_device *fc,
flexcop_dma_index_t no,
int onoff)
{
flexcop_ibi_value v = fc->read_ibi_reg(fc, ctrl_208);
if (no & FC_DMA_1)
v.ctrl_208.DMA1_Timer_Enable_sig = onoff;
if (no & FC_DMA_2)
v.ctrl_208.DMA2_Timer_Enable_sig = onoff;
fc->write_ibi_reg(fc, ctrl_208, v);
return 0;
}
EXPORT_SYMBOL(flexcop_dma_control_timer_irq);
/* 1 cycles = 1.97 msec */
int flexcop_dma_config_timer(struct flexcop_device *fc,
flexcop_dma_index_t dma_idx, u8 cycles)
{
flexcop_ibi_register r = (dma_idx & FC_DMA_1) ? dma1_004 : dma2_014;
flexcop_ibi_value v = fc->read_ibi_reg(fc, r);
flexcop_dma_remap(fc, dma_idx, 0);
deb_info("%s\n", __func__);
v.dma_0x4_write.dmatimer = cycles;
fc->write_ibi_reg(fc, r, v);
return 0;
}
EXPORT_SYMBOL(flexcop_dma_config_timer);
| linux-master | drivers/media/pci/b2c2/flexcop-dma.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Copyright (C) 2006-2010 by Marin Mitov *
* [email protected] *
* *
* *
***************************************************************************/
#include <linux/module.h>
#include <linux/stringify.h>
#include <linux/delay.h>
#include <linux/kthread.h>
#include <linux/slab.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-common.h>
#include <media/videobuf2-dma-contig.h>
#include "dt3155.h"
#define DT3155_DEVICE_ID 0x1223
/**
* read_i2c_reg - reads an internal i2c register
*
* @addr: dt3155 mmio base address
* @index: index (internal address) of register to read
* @data: pointer to byte the read data will be placed in
*
* returns: zero on success or error code
*
* This function starts reading the specified (by index) register
* and busy waits for the process to finish. The result is placed
* in a byte pointed by data.
*/
static int read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
{
u32 tmp = index;
iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2);
udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
return -EIO; /* error: NEW_CYCLE not cleared */
tmp = ioread32(addr + IIC_CSR1);
if (tmp & DIRECT_ABORT) {
/* reset DIRECT_ABORT bit */
iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
return -EIO; /* error: DIRECT_ABORT set */
}
*data = tmp >> 24;
return 0;
}
/**
* write_i2c_reg - writes to an internal i2c register
*
* @addr: dt3155 mmio base address
* @index: index (internal address) of register to read
* @data: data to be written
*
* returns: zero on success or error code
*
* This function starts writing the specified (by index) register
* and busy waits for the process to finish.
*/
static int write_i2c_reg(void __iomem *addr, u8 index, u8 data)
{
u32 tmp = index;
iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
return -EIO; /* error: NEW_CYCLE not cleared */
if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
/* reset DIRECT_ABORT bit */
iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
return -EIO; /* error: DIRECT_ABORT set */
}
return 0;
}
/**
* write_i2c_reg_nowait - writes to an internal i2c register
*
* @addr: dt3155 mmio base address
* @index: index (internal address) of register to read
* @data: data to be written
*
* This function starts writing the specified (by index) register
* and then returns.
*/
static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
{
u32 tmp = index;
iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
}
/**
* wait_i2c_reg - waits the read/write to finish
*
* @addr: dt3155 mmio base address
*
* returns: zero on success or error code
*
* This function waits reading/writing to finish.
*/
static int wait_i2c_reg(void __iomem *addr)
{
if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
return -EIO; /* error: NEW_CYCLE not cleared */
if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
/* reset DIRECT_ABORT bit */
iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
return -EIO; /* error: DIRECT_ABORT set */
}
return 0;
}
static int
dt3155_queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers, unsigned int *num_planes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct dt3155_priv *pd = vb2_get_drv_priv(vq);
unsigned size = pd->width * pd->height;
if (vq->num_buffers + *nbuffers < 2)
*nbuffers = 2 - vq->num_buffers;
if (*num_planes)
return sizes[0] < size ? -EINVAL : 0;
*num_planes = 1;
sizes[0] = size;
return 0;
}
static int dt3155_buf_prepare(struct vb2_buffer *vb)
{
struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
vb2_set_plane_payload(vb, 0, pd->width * pd->height);
return 0;
}
static int dt3155_start_streaming(struct vb2_queue *q, unsigned count)
{
struct dt3155_priv *pd = vb2_get_drv_priv(q);
struct vb2_buffer *vb = &pd->curr_buf->vb2_buf;
dma_addr_t dma_addr;
pd->sequence = 0;
dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START);
iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE);
iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE);
/* enable interrupts, clear all irq flags */
iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
pd->regs + CSR1);
wait_i2c_reg(pd->regs);
write_i2c_reg(pd->regs, CONFIG, pd->config);
write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
/* start the board */
write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
return 0;
}
static void dt3155_stop_streaming(struct vb2_queue *q)
{
struct dt3155_priv *pd = vb2_get_drv_priv(q);
struct vb2_buffer *vb;
spin_lock_irq(&pd->lock);
/* stop the board */
write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2);
iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
/* disable interrupts, clear all irq flags */
iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
spin_unlock_irq(&pd->lock);
/*
* It is not clear whether the DMA stops at once or whether it
* will finish the current frame or field first. To be on the
* safe side we wait a bit.
*/
msleep(45);
spin_lock_irq(&pd->lock);
if (pd->curr_buf) {
vb2_buffer_done(&pd->curr_buf->vb2_buf, VB2_BUF_STATE_ERROR);
pd->curr_buf = NULL;
}
while (!list_empty(&pd->dmaq)) {
vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
list_del(&vb->done_entry);
vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
}
spin_unlock_irq(&pd->lock);
}
static void dt3155_buf_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
/* pd->vidq.streaming = 1 when dt3155_buf_queue() is invoked */
spin_lock_irq(&pd->lock);
if (pd->curr_buf)
list_add_tail(&vb->done_entry, &pd->dmaq);
else
pd->curr_buf = vbuf;
spin_unlock_irq(&pd->lock);
}
static const struct vb2_ops q_ops = {
.queue_setup = dt3155_queue_setup,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.buf_prepare = dt3155_buf_prepare,
.start_streaming = dt3155_start_streaming,
.stop_streaming = dt3155_stop_streaming,
.buf_queue = dt3155_buf_queue,
};
static irqreturn_t dt3155_irq_handler_even(int irq, void *dev_id)
{
struct dt3155_priv *ipd = dev_id;
struct vb2_buffer *ivb;
dma_addr_t dma_addr;
u32 tmp;
tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
if (!tmp)
return IRQ_NONE; /* not our irq */
if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
ipd->regs + INT_CSR);
return IRQ_HANDLED; /* start of field irq */
}
tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
if (tmp) {
iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
FLD_DN_ODD | FLD_DN_EVEN |
CAP_CONT_EVEN | CAP_CONT_ODD,
ipd->regs + CSR1);
}
spin_lock(&ipd->lock);
if (ipd->curr_buf && !list_empty(&ipd->dmaq)) {
ipd->curr_buf->vb2_buf.timestamp = ktime_get_ns();
ipd->curr_buf->sequence = ipd->sequence++;
ipd->curr_buf->field = V4L2_FIELD_NONE;
vb2_buffer_done(&ipd->curr_buf->vb2_buf, VB2_BUF_STATE_DONE);
ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
list_del(&ivb->done_entry);
ipd->curr_buf = to_vb2_v4l2_buffer(ivb);
dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START);
iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE);
iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE);
}
/* enable interrupts, clear all irq flags */
iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
spin_unlock(&ipd->lock);
return IRQ_HANDLED;
}
static const struct v4l2_file_operations dt3155_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.release = vb2_fop_release,
.unlocked_ioctl = video_ioctl2,
.read = vb2_fop_read,
.mmap = vb2_fop_mmap,
.poll = vb2_fop_poll
};
static int dt3155_querycap(struct file *filp, void *p,
struct v4l2_capability *cap)
{
strscpy(cap->driver, DT3155_NAME, sizeof(cap->driver));
strscpy(cap->card, DT3155_NAME " frame grabber", sizeof(cap->card));
return 0;
}
static int dt3155_enum_fmt_vid_cap(struct file *filp,
void *p, struct v4l2_fmtdesc *f)
{
if (f->index)
return -EINVAL;
f->pixelformat = V4L2_PIX_FMT_GREY;
return 0;
}
static int dt3155_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
{
struct dt3155_priv *pd = video_drvdata(filp);
f->fmt.pix.width = pd->width;
f->fmt.pix.height = pd->height;
f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
f->fmt.pix.field = V4L2_FIELD_NONE;
f->fmt.pix.bytesperline = f->fmt.pix.width;
f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
return 0;
}
static int dt3155_g_std(struct file *filp, void *p, v4l2_std_id *norm)
{
struct dt3155_priv *pd = video_drvdata(filp);
*norm = pd->std;
return 0;
}
static int dt3155_s_std(struct file *filp, void *p, v4l2_std_id norm)
{
struct dt3155_priv *pd = video_drvdata(filp);
if (pd->std == norm)
return 0;
if (vb2_is_busy(&pd->vidq))
return -EBUSY;
pd->std = norm;
if (pd->std & V4L2_STD_525_60) {
pd->csr2 = VT_60HZ;
pd->width = 640;
pd->height = 480;
} else {
pd->csr2 = VT_50HZ;
pd->width = 768;
pd->height = 576;
}
return 0;
}
static int dt3155_enum_input(struct file *filp, void *p,
struct v4l2_input *input)
{
if (input->index > 3)
return -EINVAL;
if (input->index)
snprintf(input->name, sizeof(input->name), "VID%d",
input->index);
else
strscpy(input->name, "J2/VID0", sizeof(input->name));
input->type = V4L2_INPUT_TYPE_CAMERA;
input->std = V4L2_STD_ALL;
input->status = 0;
return 0;
}
static int dt3155_g_input(struct file *filp, void *p, unsigned int *i)
{
struct dt3155_priv *pd = video_drvdata(filp);
*i = pd->input;
return 0;
}
static int dt3155_s_input(struct file *filp, void *p, unsigned int i)
{
struct dt3155_priv *pd = video_drvdata(filp);
if (i > 3)
return -EINVAL;
pd->input = i;
write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3);
return 0;
}
static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
.vidioc_querycap = dt3155_querycap,
.vidioc_enum_fmt_vid_cap = dt3155_enum_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = dt3155_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = dt3155_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = dt3155_fmt_vid_cap,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_create_bufs = vb2_ioctl_create_bufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_expbuf = vb2_ioctl_expbuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_g_std = dt3155_g_std,
.vidioc_s_std = dt3155_s_std,
.vidioc_enum_input = dt3155_enum_input,
.vidioc_g_input = dt3155_g_input,
.vidioc_s_input = dt3155_s_input,
};
static int dt3155_init_board(struct dt3155_priv *pd)
{
struct pci_dev *pdev = pd->pdev;
int i;
u8 tmp = 0;
pci_set_master(pdev); /* dt3155 needs it */
/* resetting the adapter */
iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN |
FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
msleep(20);
/* initializing adapter registers */
iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
iowrite32(0x00000020, pd->regs + FIFO_TRIGGER);
iowrite32(0x00000103, pd->regs + XFER_MODE);
iowrite32(0, pd->regs + RETRY_WAIT_CNT);
iowrite32(0, pd->regs + INT_CSR);
iowrite32(1, pd->regs + EVEN_FLD_MASK);
iowrite32(1, pd->regs + ODD_FLD_MASK);
iowrite32(0, pd->regs + MASK_LENGTH);
iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
/* verifying that we have a DT3155 board (not just a SAA7116 chip) */
read_i2c_reg(pd->regs, DT_ID, &tmp);
if (tmp != DT3155_ID)
return -ENODEV;
/* initialize AD LUT */
write_i2c_reg(pd->regs, AD_ADDR, 0);
for (i = 0; i < 256; i++)
write_i2c_reg(pd->regs, AD_LUT, i);
/* initialize ADC references */
/* FIXME: pos_ref & neg_ref depend on VT_50HZ */
write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
write_i2c_reg(pd->regs, AD_CMD, 34);
write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
write_i2c_reg(pd->regs, AD_CMD, 0);
/* initialize PM LUT */
write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
for (i = 0; i < 256; i++) {
write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
write_i2c_reg(pd->regs, PM_LUT_DATA, i);
}
write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
for (i = 0; i < 256; i++) {
write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
write_i2c_reg(pd->regs, PM_LUT_DATA, i);
}
write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */
/* select channel 1 for input and set sync level */
write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
/* disable all irqs, clear all irq flags */
iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
pd->regs + INT_CSR);
return 0;
}
static const struct video_device dt3155_vdev = {
.name = DT3155_NAME,
.fops = &dt3155_fops,
.ioctl_ops = &dt3155_ioctl_ops,
.minor = -1,
.release = video_device_release_empty,
.tvnorms = V4L2_STD_ALL,
.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
V4L2_CAP_READWRITE,
};
static int dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
int err;
struct dt3155_priv *pd;
err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (err)
return -ENODEV;
pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return -ENOMEM;
err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev);
if (err)
return err;
pd->vdev = dt3155_vdev;
pd->vdev.v4l2_dev = &pd->v4l2_dev;
video_set_drvdata(&pd->vdev, pd); /* for use in video_fops */
pd->pdev = pdev;
pd->std = V4L2_STD_625_50;
pd->csr2 = VT_50HZ;
pd->width = 768;
pd->height = 576;
INIT_LIST_HEAD(&pd->dmaq);
mutex_init(&pd->mux);
pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */
pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
pd->vidq.ops = &q_ops;
pd->vidq.mem_ops = &vb2_dma_contig_memops;
pd->vidq.drv_priv = pd;
pd->vidq.min_buffers_needed = 2;
pd->vidq.gfp_flags = GFP_DMA32;
pd->vidq.lock = &pd->mux; /* for locking v4l2_file_operations */
pd->vidq.dev = &pdev->dev;
pd->vdev.queue = &pd->vidq;
err = vb2_queue_init(&pd->vidq);
if (err < 0)
goto err_v4l2_dev_unreg;
spin_lock_init(&pd->lock);
pd->config = ACQ_MODE_EVEN;
err = pci_enable_device(pdev);
if (err)
goto err_v4l2_dev_unreg;
err = pci_request_region(pdev, 0, pci_name(pdev));
if (err)
goto err_pci_disable;
pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
if (!pd->regs) {
err = -ENOMEM;
goto err_free_reg;
}
err = dt3155_init_board(pd);
if (err)
goto err_iounmap;
err = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
IRQF_SHARED, DT3155_NAME, pd);
if (err)
goto err_iounmap;
err = video_register_device(&pd->vdev, VFL_TYPE_VIDEO, -1);
if (err)
goto err_free_irq;
dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor);
return 0; /* success */
err_free_irq:
free_irq(pd->pdev->irq, pd);
err_iounmap:
pci_iounmap(pdev, pd->regs);
err_free_reg:
pci_release_region(pdev, 0);
err_pci_disable:
pci_disable_device(pdev);
err_v4l2_dev_unreg:
v4l2_device_unregister(&pd->v4l2_dev);
return err;
}
static void dt3155_remove(struct pci_dev *pdev)
{
struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev);
struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv,
v4l2_dev);
vb2_video_unregister_device(&pd->vdev);
free_irq(pd->pdev->irq, pd);
v4l2_device_unregister(&pd->v4l2_dev);
pci_iounmap(pdev, pd->regs);
pci_release_region(pdev, 0);
pci_disable_device(pdev);
}
static const struct pci_device_id pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) },
{ 0, /* zero marks the end */ },
};
MODULE_DEVICE_TABLE(pci, pci_ids);
static struct pci_driver pci_driver = {
.name = DT3155_NAME,
.id_table = pci_ids,
.probe = dt3155_probe,
.remove = dt3155_remove,
};
module_pci_driver(pci_driver);
MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
MODULE_AUTHOR("Marin Mitov <[email protected]>");
MODULE_VERSION(DT3155_VERSION);
MODULE_LICENSE("GPL");
| linux-master | drivers/media/pci/dt3155/dt3155.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* device driver for philips saa7134 based TV cards
* driver core
*
* (c) 2001-03 Gerd Knorr <[email protected]> [SuSE Labs]
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/kmod.h>
#include <linux/sound.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/dma-mapping.h>
#include <linux/pm.h>
MODULE_DESCRIPTION("v4l2 driver module for saa7130/34 based TV cards");
MODULE_AUTHOR("Gerd Knorr <[email protected]> [SuSE Labs]");
MODULE_LICENSE("GPL");
MODULE_VERSION(SAA7134_VERSION);
/* ------------------------------------------------------------------ */
static unsigned int irq_debug;
module_param(irq_debug, int, 0644);
MODULE_PARM_DESC(irq_debug,"enable debug messages [IRQ handler]");
static unsigned int core_debug;
module_param(core_debug, int, 0644);
MODULE_PARM_DESC(core_debug,"enable debug messages [core]");
static unsigned int gpio_tracking;
module_param(gpio_tracking, int, 0644);
MODULE_PARM_DESC(gpio_tracking,"enable debug messages [gpio]");
static unsigned int alsa = 1;
module_param(alsa, int, 0644);
MODULE_PARM_DESC(alsa,"enable/disable ALSA DMA sound [dmasound]");
static unsigned int latency = UNSET;
module_param(latency, int, 0444);
MODULE_PARM_DESC(latency,"pci latency timer");
bool saa7134_userptr;
module_param(saa7134_userptr, bool, 0644);
MODULE_PARM_DESC(saa7134_userptr, "enable page-aligned userptr support");
static unsigned int video_nr[] = {[0 ... (SAA7134_MAXBOARDS - 1)] = UNSET };
static unsigned int vbi_nr[] = {[0 ... (SAA7134_MAXBOARDS - 1)] = UNSET };
static unsigned int radio_nr[] = {[0 ... (SAA7134_MAXBOARDS - 1)] = UNSET };
static unsigned int tuner[] = {[0 ... (SAA7134_MAXBOARDS - 1)] = UNSET };
static unsigned int card[] = {[0 ... (SAA7134_MAXBOARDS - 1)] = UNSET };
module_param_array(video_nr, int, NULL, 0444);
module_param_array(vbi_nr, int, NULL, 0444);
module_param_array(radio_nr, int, NULL, 0444);
module_param_array(tuner, int, NULL, 0444);
module_param_array(card, int, NULL, 0444);
MODULE_PARM_DESC(video_nr, "video device number");
MODULE_PARM_DESC(vbi_nr, "vbi device number");
MODULE_PARM_DESC(radio_nr, "radio device number");
MODULE_PARM_DESC(tuner, "tuner type");
MODULE_PARM_DESC(card, "card type");
DEFINE_MUTEX(saa7134_devlist_lock);
EXPORT_SYMBOL(saa7134_devlist_lock);
LIST_HEAD(saa7134_devlist);
EXPORT_SYMBOL(saa7134_devlist);
static LIST_HEAD(mops_list);
static unsigned int saa7134_devcount;
int (*saa7134_dmasound_init)(struct saa7134_dev *dev);
int (*saa7134_dmasound_exit)(struct saa7134_dev *dev);
#define core_dbg(fmt, arg...) do { \
if (core_debug) \
printk(KERN_DEBUG pr_fmt("core: " fmt), ## arg); \
} while (0)
#define irq_dbg(level, fmt, arg...) do {\
if (irq_debug > level) \
printk(KERN_DEBUG pr_fmt("irq: " fmt), ## arg); \
} while (0)
void saa7134_track_gpio(struct saa7134_dev *dev, const char *msg)
{
unsigned long mode,status;
if (!gpio_tracking)
return;
/* rising SAA7134_GPIO_GPRESCAN reads the status */
saa_andorb(SAA7134_GPIO_GPMODE3,SAA7134_GPIO_GPRESCAN,0);
saa_andorb(SAA7134_GPIO_GPMODE3,SAA7134_GPIO_GPRESCAN,SAA7134_GPIO_GPRESCAN);
mode = saa_readl(SAA7134_GPIO_GPMODE0 >> 2) & 0xfffffff;
status = saa_readl(SAA7134_GPIO_GPSTATUS0 >> 2) & 0xfffffff;
core_dbg("%s: gpio: mode=0x%07lx in=0x%07lx out=0x%07lx [%s]\n",
dev->name, mode, (~mode) & status, mode & status, msg);
}
void saa7134_set_gpio(struct saa7134_dev *dev, int bit_no, int value)
{
u32 index, bitval;
index = 1 << bit_no;
switch (value) {
case 0: /* static value */
case 1:
core_dbg("setting GPIO%d to static %d\n", bit_no, value);
/* turn sync mode off if necessary */
if (index & 0x00c00000)
saa_andorb(SAA7134_VIDEO_PORT_CTRL6, 0x0f, 0x00);
if (value)
bitval = index;
else
bitval = 0;
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, index, index);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, index, bitval);
break;
case 3: /* tristate */
core_dbg("setting GPIO%d to tristate\n", bit_no);
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, index, 0);
break;
}
}
/* ------------------------------------------------------------------ */
/* ----------------------------------------------------------- */
/* delayed request_module */
#if defined(CONFIG_MODULES) && defined(MODULE)
static void request_module_async(struct work_struct *work){
struct saa7134_dev* dev = container_of(work, struct saa7134_dev, request_module_wk);
if (card_is_empress(dev))
request_module("saa7134-empress");
if (card_is_dvb(dev))
request_module("saa7134-dvb");
if (card_is_go7007(dev))
request_module("saa7134-go7007");
if (alsa) {
if (dev->pci->device != PCI_DEVICE_ID_PHILIPS_SAA7130)
request_module("saa7134-alsa");
}
}
static void request_submodules(struct saa7134_dev *dev)
{
INIT_WORK(&dev->request_module_wk, request_module_async);
schedule_work(&dev->request_module_wk);
}
static void flush_request_submodules(struct saa7134_dev *dev)
{
flush_work(&dev->request_module_wk);
}
#else
#define request_submodules(dev)
#define flush_request_submodules(dev)
#endif /* CONFIG_MODULES */
/* ------------------------------------------------------------------ */
/* nr of (saa7134-)pages for the given buffer size */
static int saa7134_buffer_pages(int size)
{
size = PAGE_ALIGN(size);
size += PAGE_SIZE; /* for non-page-aligned buffers */
size /= 4096;
return size;
}
/* calc max # of buffers from size (must not exceed the 4MB virtual
* address space per DMA channel) */
int saa7134_buffer_count(unsigned int size, unsigned int count)
{
unsigned int maxcount;
maxcount = 1024 / saa7134_buffer_pages(size);
if (count > maxcount)
count = maxcount;
return count;
}
int saa7134_buffer_startpage(struct saa7134_buf *buf)
{
return saa7134_buffer_pages(vb2_plane_size(&buf->vb2.vb2_buf, 0))
* buf->vb2.vb2_buf.index;
}
unsigned long saa7134_buffer_base(struct saa7134_buf *buf)
{
unsigned long base;
struct sg_table *dma = vb2_dma_sg_plane_desc(&buf->vb2.vb2_buf, 0);
base = saa7134_buffer_startpage(buf) * 4096;
base += dma->sgl[0].offset;
return base;
}
/* ------------------------------------------------------------------ */
int saa7134_pgtable_alloc(struct pci_dev *pci, struct saa7134_pgtable *pt)
{
__le32 *cpu;
dma_addr_t dma_addr = 0;
cpu = dma_alloc_coherent(&pci->dev, SAA7134_PGTABLE_SIZE, &dma_addr,
GFP_KERNEL);
if (NULL == cpu)
return -ENOMEM;
pt->size = SAA7134_PGTABLE_SIZE;
pt->cpu = cpu;
pt->dma = dma_addr;
return 0;
}
int saa7134_pgtable_build(struct pci_dev *pci, struct saa7134_pgtable *pt,
struct scatterlist *list, unsigned int length,
unsigned int startpage)
{
__le32 *ptr;
unsigned int i, p;
BUG_ON(NULL == pt || NULL == pt->cpu);
ptr = pt->cpu + startpage;
for (i = 0; i < length; i++, list = sg_next(list)) {
for (p = 0; p * 4096 < sg_dma_len(list); p++, ptr++)
*ptr = cpu_to_le32(sg_dma_address(list) +
list->offset + p * 4096);
}
return 0;
}
void saa7134_pgtable_free(struct pci_dev *pci, struct saa7134_pgtable *pt)
{
if (NULL == pt->cpu)
return;
dma_free_coherent(&pci->dev, pt->size, pt->cpu, pt->dma);
pt->cpu = NULL;
}
/* ------------------------------------------------------------------ */
int saa7134_buffer_queue(struct saa7134_dev *dev,
struct saa7134_dmaqueue *q,
struct saa7134_buf *buf)
{
struct saa7134_buf *next = NULL;
unsigned long flags;
spin_lock_irqsave(&dev->slock, flags);
core_dbg("buffer_queue %p\n", buf);
if (NULL == q->curr) {
if (!q->need_two) {
q->curr = buf;
buf->activate(dev, buf, NULL);
} else if (list_empty(&q->queue)) {
list_add_tail(&buf->entry, &q->queue);
} else {
next = list_entry(q->queue.next, struct saa7134_buf,
entry);
q->curr = buf;
buf->activate(dev, buf, next);
}
} else {
list_add_tail(&buf->entry, &q->queue);
}
spin_unlock_irqrestore(&dev->slock, flags);
return 0;
}
void saa7134_buffer_finish(struct saa7134_dev *dev,
struct saa7134_dmaqueue *q,
unsigned int state)
{
core_dbg("buffer_finish %p\n", q->curr);
/* finish current buffer */
q->curr->vb2.vb2_buf.timestamp = ktime_get_ns();
q->curr->vb2.sequence = q->seq_nr++;
vb2_buffer_done(&q->curr->vb2.vb2_buf, state);
q->curr = NULL;
}
void saa7134_buffer_next(struct saa7134_dev *dev,
struct saa7134_dmaqueue *q)
{
struct saa7134_buf *buf,*next = NULL;
assert_spin_locked(&dev->slock);
BUG_ON(NULL != q->curr);
if (!list_empty(&q->queue)) {
/* activate next one from queue */
buf = list_entry(q->queue.next, struct saa7134_buf, entry);
core_dbg("buffer_next %p [prev=%p/next=%p]\n",
buf, q->queue.prev, q->queue.next);
list_del(&buf->entry);
if (!list_empty(&q->queue))
next = list_entry(q->queue.next, struct saa7134_buf, entry);
q->curr = buf;
buf->activate(dev, buf, next);
core_dbg("buffer_next #2 prev=%p/next=%p\n",
q->queue.prev, q->queue.next);
} else {
/* nothing to do -- just stop DMA */
core_dbg("buffer_next %p\n", NULL);
saa7134_set_dmabits(dev);
del_timer(&q->timeout);
}
}
void saa7134_buffer_timeout(struct timer_list *t)
{
struct saa7134_dmaqueue *q = from_timer(q, t, timeout);
struct saa7134_dev *dev = q->dev;
unsigned long flags;
spin_lock_irqsave(&dev->slock, flags);
/* try to reset the hardware (SWRST) */
saa_writeb(SAA7134_REGION_ENABLE, 0x00);
saa_writeb(SAA7134_REGION_ENABLE, 0x80);
saa_writeb(SAA7134_REGION_ENABLE, 0x00);
/* flag current buffer as failed,
try to start over with the next one. */
if (q->curr) {
core_dbg("timeout on %p\n", q->curr);
saa7134_buffer_finish(dev, q, VB2_BUF_STATE_ERROR);
}
saa7134_buffer_next(dev, q);
spin_unlock_irqrestore(&dev->slock, flags);
}
void saa7134_stop_streaming(struct saa7134_dev *dev, struct saa7134_dmaqueue *q)
{
unsigned long flags;
struct list_head *pos, *n;
struct saa7134_buf *tmp;
spin_lock_irqsave(&dev->slock, flags);
list_for_each_safe(pos, n, &q->queue) {
tmp = list_entry(pos, struct saa7134_buf, entry);
vb2_buffer_done(&tmp->vb2.vb2_buf,
VB2_BUF_STATE_ERROR);
list_del(pos);
tmp = NULL;
}
spin_unlock_irqrestore(&dev->slock, flags);
saa7134_buffer_timeout(&q->timeout); /* also calls del_timer(&q->timeout) */
}
EXPORT_SYMBOL_GPL(saa7134_stop_streaming);
/* ------------------------------------------------------------------ */
int saa7134_set_dmabits(struct saa7134_dev *dev)
{
u32 split, task=0, ctrl=0, irq=0;
enum v4l2_field cap = V4L2_FIELD_ANY;
enum v4l2_field ov = V4L2_FIELD_ANY;
assert_spin_locked(&dev->slock);
if (dev->insuspend)
return 0;
/* video capture -- dma 0 + video task A */
if (dev->video_q.curr) {
task |= 0x01;
ctrl |= SAA7134_MAIN_CTRL_TE0;
irq |= SAA7134_IRQ1_INTE_RA0_1 |
SAA7134_IRQ1_INTE_RA0_0;
cap = dev->field;
}
/* video capture -- dma 1+2 (planar modes) */
if (dev->video_q.curr && dev->fmt->planar) {
ctrl |= SAA7134_MAIN_CTRL_TE4 |
SAA7134_MAIN_CTRL_TE5;
}
/* vbi capture -- dma 0 + vbi task A+B */
if (dev->vbi_q.curr) {
task |= 0x22;
ctrl |= SAA7134_MAIN_CTRL_TE2 |
SAA7134_MAIN_CTRL_TE3;
irq |= SAA7134_IRQ1_INTE_RA0_7 |
SAA7134_IRQ1_INTE_RA0_6 |
SAA7134_IRQ1_INTE_RA0_5 |
SAA7134_IRQ1_INTE_RA0_4;
}
/* audio capture -- dma 3 */
if (dev->dmasound.dma_running) {
ctrl |= SAA7134_MAIN_CTRL_TE6;
irq |= SAA7134_IRQ1_INTE_RA3_1 |
SAA7134_IRQ1_INTE_RA3_0;
}
/* TS capture -- dma 5 */
if (dev->ts_q.curr) {
ctrl |= SAA7134_MAIN_CTRL_TE5;
irq |= SAA7134_IRQ1_INTE_RA2_1 |
SAA7134_IRQ1_INTE_RA2_0;
}
/* set task conditions + field handling */
if (V4L2_FIELD_HAS_BOTH(cap) || V4L2_FIELD_HAS_BOTH(ov) || cap == ov) {
/* default config -- use full frames */
saa_writeb(SAA7134_TASK_CONDITIONS(TASK_A), 0x0d);
saa_writeb(SAA7134_TASK_CONDITIONS(TASK_B), 0x0d);
saa_writeb(SAA7134_FIELD_HANDLING(TASK_A), 0x02);
saa_writeb(SAA7134_FIELD_HANDLING(TASK_B), 0x02);
split = 0;
} else {
/* split fields between tasks */
if (V4L2_FIELD_TOP == cap) {
/* odd A, even B, repeat */
saa_writeb(SAA7134_TASK_CONDITIONS(TASK_A), 0x0d);
saa_writeb(SAA7134_TASK_CONDITIONS(TASK_B), 0x0e);
} else {
/* odd B, even A, repeat */
saa_writeb(SAA7134_TASK_CONDITIONS(TASK_A), 0x0e);
saa_writeb(SAA7134_TASK_CONDITIONS(TASK_B), 0x0d);
}
saa_writeb(SAA7134_FIELD_HANDLING(TASK_A), 0x01);
saa_writeb(SAA7134_FIELD_HANDLING(TASK_B), 0x01);
split = 1;
}
/* irqs */
saa_writeb(SAA7134_REGION_ENABLE, task);
saa_writel(SAA7134_IRQ1, irq);
saa_andorl(SAA7134_MAIN_CTRL,
SAA7134_MAIN_CTRL_TE0 |
SAA7134_MAIN_CTRL_TE1 |
SAA7134_MAIN_CTRL_TE2 |
SAA7134_MAIN_CTRL_TE3 |
SAA7134_MAIN_CTRL_TE4 |
SAA7134_MAIN_CTRL_TE5 |
SAA7134_MAIN_CTRL_TE6,
ctrl);
core_dbg("dmabits: task=0x%02x ctrl=0x%02x irq=0x%x split=%s\n",
task, ctrl, irq, split ? "no" : "yes");
return 0;
}
/* ------------------------------------------------------------------ */
/* IRQ handler + helpers */
static char *irqbits[] = {
"DONE_RA0", "DONE_RA1", "DONE_RA2", "DONE_RA3",
"AR", "PE", "PWR_ON", "RDCAP", "INTL", "FIDT", "MMC",
"TRIG_ERR", "CONF_ERR", "LOAD_ERR",
"GPIO16", "GPIO18", "GPIO22", "GPIO23"
};
#define IRQBITS ARRAY_SIZE(irqbits)
static void print_irqstatus(struct saa7134_dev *dev, int loop,
unsigned long report, unsigned long status)
{
unsigned int i;
irq_dbg(1, "[%d,%ld]: r=0x%lx s=0x%02lx",
loop, jiffies, report, status);
for (i = 0; i < IRQBITS; i++) {
if (!(report & (1 << i)))
continue;
pr_cont(" %s", irqbits[i]);
}
if (report & SAA7134_IRQ_REPORT_DONE_RA0) {
pr_cont(" | RA0=%s,%s,%s,%ld",
(status & 0x40) ? "vbi" : "video",
(status & 0x20) ? "b" : "a",
(status & 0x10) ? "odd" : "even",
(status & 0x0f));
}
pr_cont("\n");
}
static irqreturn_t saa7134_irq(int irq, void *dev_id)
{
struct saa7134_dev *dev = (struct saa7134_dev*) dev_id;
unsigned long report,status;
int loop, handled = 0;
if (dev->insuspend)
goto out;
for (loop = 0; loop < 10; loop++) {
report = saa_readl(SAA7134_IRQ_REPORT);
status = saa_readl(SAA7134_IRQ_STATUS);
/* If dmasound support is active and we get a sound report,
* mask out the report and let the saa7134-alsa module deal
* with it */
if ((report & SAA7134_IRQ_REPORT_DONE_RA3) &&
(dev->dmasound.priv_data != NULL) )
{
irq_dbg(2, "preserving DMA sound interrupt\n");
report &= ~SAA7134_IRQ_REPORT_DONE_RA3;
}
if (0 == report) {
irq_dbg(2, "no (more) work\n");
goto out;
}
handled = 1;
saa_writel(SAA7134_IRQ_REPORT,report);
if (irq_debug)
print_irqstatus(dev,loop,report,status);
if ((report & SAA7134_IRQ_REPORT_RDCAP) ||
(report & SAA7134_IRQ_REPORT_INTL))
saa7134_irq_video_signalchange(dev);
if ((report & SAA7134_IRQ_REPORT_DONE_RA0) &&
(status & 0x60) == 0)
saa7134_irq_video_done(dev,status);
if ((report & SAA7134_IRQ_REPORT_DONE_RA0) &&
(status & 0x40) == 0x40)
saa7134_irq_vbi_done(dev,status);
if ((report & SAA7134_IRQ_REPORT_DONE_RA2) &&
card_has_mpeg(dev)) {
if (dev->mops->irq_ts_done != NULL)
dev->mops->irq_ts_done(dev, status);
else
saa7134_irq_ts_done(dev, status);
}
if (report & SAA7134_IRQ_REPORT_GPIO16) {
switch (dev->has_remote) {
case SAA7134_REMOTE_GPIO:
if (!dev->remote)
break;
if (dev->remote->mask_keydown & 0x10000) {
saa7134_input_irq(dev);
}
break;
case SAA7134_REMOTE_I2C:
break; /* FIXME: invoke I2C get_key() */
default: /* GPIO16 not used by IR remote */
break;
}
}
if (report & SAA7134_IRQ_REPORT_GPIO18) {
switch (dev->has_remote) {
case SAA7134_REMOTE_GPIO:
if (!dev->remote)
break;
if ((dev->remote->mask_keydown & 0x40000) ||
(dev->remote->mask_keyup & 0x40000)) {
saa7134_input_irq(dev);
}
break;
case SAA7134_REMOTE_I2C:
break; /* FIXME: invoke I2C get_key() */
default: /* GPIO18 not used by IR remote */
break;
}
}
}
if (10 == loop) {
print_irqstatus(dev,loop,report,status);
if (report & SAA7134_IRQ_REPORT_PE) {
/* disable all parity error */
pr_warn("%s/irq: looping -- clearing PE (parity error!) enable bit\n",
dev->name);
saa_clearl(SAA7134_IRQ2,SAA7134_IRQ2_INTE_PE);
} else if (report & SAA7134_IRQ_REPORT_GPIO16) {
/* disable gpio16 IRQ */
pr_warn("%s/irq: looping -- clearing GPIO16 enable bit\n",
dev->name);
saa_clearl(SAA7134_IRQ2, SAA7134_IRQ2_INTE_GPIO16_P);
saa_clearl(SAA7134_IRQ2, SAA7134_IRQ2_INTE_GPIO16_N);
} else if (report & SAA7134_IRQ_REPORT_GPIO18) {
/* disable gpio18 IRQs */
pr_warn("%s/irq: looping -- clearing GPIO18 enable bit\n",
dev->name);
saa_clearl(SAA7134_IRQ2, SAA7134_IRQ2_INTE_GPIO18_P);
saa_clearl(SAA7134_IRQ2, SAA7134_IRQ2_INTE_GPIO18_N);
} else {
/* disable all irqs */
pr_warn("%s/irq: looping -- clearing all enable bits\n",
dev->name);
saa_writel(SAA7134_IRQ1,0);
saa_writel(SAA7134_IRQ2,0);
}
}
out:
return IRQ_RETVAL(handled);
}
/* ------------------------------------------------------------------ */
/* early init (no i2c, no irq) */
static int saa7134_hw_enable1(struct saa7134_dev *dev)
{
/* RAM FIFO config */
saa_writel(SAA7134_FIFO_SIZE, 0x08070503);
saa_writel(SAA7134_THRESHOULD, 0x02020202);
/* enable audio + video processing */
saa_writel(SAA7134_MAIN_CTRL,
SAA7134_MAIN_CTRL_VPLLE |
SAA7134_MAIN_CTRL_APLLE |
SAA7134_MAIN_CTRL_EXOSC |
SAA7134_MAIN_CTRL_EVFE1 |
SAA7134_MAIN_CTRL_EVFE2 |
SAA7134_MAIN_CTRL_ESFE |
SAA7134_MAIN_CTRL_EBDAC);
/*
* Initialize OSS _after_ enabling audio clock PLL and audio processing.
* OSS initialization writes to registers via the audio DSP; these
* writes will fail unless the audio clock has been started. At worst,
* audio will not work.
*/
/* enable peripheral devices */
saa_writeb(SAA7134_SPECIAL_MODE, 0x01);
/* set vertical line numbering start (vbi needs this) */
saa_writeb(SAA7134_SOURCE_TIMING2, 0x20);
return 0;
}
static int saa7134_hwinit1(struct saa7134_dev *dev)
{
core_dbg("hwinit1\n");
saa_writel(SAA7134_IRQ1, 0);
saa_writel(SAA7134_IRQ2, 0);
/* Clear any stale IRQ reports */
saa_writel(SAA7134_IRQ_REPORT, saa_readl(SAA7134_IRQ_REPORT));
mutex_init(&dev->lock);
spin_lock_init(&dev->slock);
saa7134_track_gpio(dev,"pre-init");
saa7134_video_init1(dev);
saa7134_vbi_init1(dev);
if (card_has_mpeg(dev))
saa7134_ts_init1(dev);
saa7134_input_init1(dev);
saa7134_hw_enable1(dev);
return 0;
}
/* late init (with i2c + irq) */
static int saa7134_hw_enable2(struct saa7134_dev *dev)
{
unsigned int irq2_mask;
/* enable IRQ's */
irq2_mask =
SAA7134_IRQ2_INTE_DEC3 |
SAA7134_IRQ2_INTE_DEC2 |
SAA7134_IRQ2_INTE_DEC1 |
SAA7134_IRQ2_INTE_DEC0 |
SAA7134_IRQ2_INTE_PE |
SAA7134_IRQ2_INTE_AR;
if (dev->has_remote == SAA7134_REMOTE_GPIO && dev->remote) {
if (dev->remote->mask_keydown & 0x10000)
irq2_mask |= SAA7134_IRQ2_INTE_GPIO16_N;
else { /* Allow enabling both IRQ edge triggers */
if (dev->remote->mask_keydown & 0x40000)
irq2_mask |= SAA7134_IRQ2_INTE_GPIO18_P;
if (dev->remote->mask_keyup & 0x40000)
irq2_mask |= SAA7134_IRQ2_INTE_GPIO18_N;
}
}
if (dev->has_remote == SAA7134_REMOTE_I2C) {
request_module("ir-kbd-i2c");
}
saa_writel(SAA7134_IRQ1, 0);
saa_writel(SAA7134_IRQ2, irq2_mask);
return 0;
}
static int saa7134_hwinit2(struct saa7134_dev *dev)
{
core_dbg("hwinit2\n");
saa7134_video_init2(dev);
saa7134_tvaudio_init2(dev);
saa7134_hw_enable2(dev);
return 0;
}
/* shutdown */
static int saa7134_hwfini(struct saa7134_dev *dev)
{
core_dbg("hwfini\n");
if (card_has_mpeg(dev))
saa7134_ts_fini(dev);
saa7134_input_fini(dev);
saa7134_vbi_fini(dev);
saa7134_tvaudio_fini(dev);
saa7134_video_fini(dev);
return 0;
}
static void must_configure_manually(int has_eeprom)
{
unsigned int i,p;
if (!has_eeprom)
pr_warn("saa7134: <rant>\n"
"saa7134: Congratulations! Your TV card vendor saved a few\n"
"saa7134: cents for a eeprom, thus your pci board has no\n"
"saa7134: subsystem ID and I can't identify it automatically\n"
"saa7134: </rant>\n"
"saa7134: I feel better now. Ok, here are the good news:\n"
"saa7134: You can use the card=<nr> insmod option to specify\n"
"saa7134: which board do you have. The list:\n");
else
pr_warn("saa7134: Board is currently unknown. You might try to use the card=<nr>\n"
"saa7134: insmod option to specify which board do you have, but this is\n"
"saa7134: somewhat risky, as might damage your card. It is better to ask\n"
"saa7134: for support at [email protected].\n"
"saa7134: The supported cards are:\n");
for (i = 0; i < saa7134_bcount; i++) {
pr_warn("saa7134: card=%d -> %-40.40s",
i,saa7134_boards[i].name);
for (p = 0; saa7134_pci_tbl[p].driver_data; p++) {
if (saa7134_pci_tbl[p].driver_data != i)
continue;
pr_cont(" %04x:%04x",
saa7134_pci_tbl[p].subvendor,
saa7134_pci_tbl[p].subdevice);
}
pr_cont("\n");
}
}
static void saa7134_unregister_media_device(struct saa7134_dev *dev)
{
#ifdef CONFIG_MEDIA_CONTROLLER
if (!dev->media_dev)
return;
media_device_unregister(dev->media_dev);
media_device_cleanup(dev->media_dev);
kfree(dev->media_dev);
dev->media_dev = NULL;
#endif
}
static void saa7134_media_release(struct saa7134_dev *dev)
{
#ifdef CONFIG_MEDIA_CONTROLLER
int i;
for (i = 0; i < SAA7134_INPUT_MAX + 1; i++)
media_device_unregister_entity(&dev->input_ent[i]);
#endif
}
#if defined(CONFIG_MEDIA_CONTROLLER)
static void saa7134_create_entities(struct saa7134_dev *dev)
{
int ret, i;
struct media_entity *entity;
struct media_entity *decoder = NULL;
/* Check if it is using an external analog TV demod */
media_device_for_each_entity(entity, dev->media_dev) {
if (entity->function == MEDIA_ENT_F_ATV_DECODER) {
decoder = entity;
break;
}
}
/*
* saa713x is not using an external ATV demod.
* Register the internal one
*/
if (!decoder) {
dev->demod.name = "saa713x";
dev->demod_pad[SAA7134_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK;
dev->demod_pad[SAA7134_PAD_IF_INPUT].sig_type = PAD_SIGNAL_ANALOG;
dev->demod_pad[SAA7134_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE;
dev->demod_pad[SAA7134_PAD_VID_OUT].sig_type = PAD_SIGNAL_DV;
dev->demod.function = MEDIA_ENT_F_ATV_DECODER;
ret = media_entity_pads_init(&dev->demod, SAA7134_NUM_PADS,
dev->demod_pad);
if (ret < 0)
pr_err("failed to initialize demod pad!\n");
ret = media_device_register_entity(dev->media_dev, &dev->demod);
if (ret < 0)
pr_err("failed to register demod entity!\n");
dev->decoder = &dev->demod;
} else {
dev->decoder = decoder;
}
/* Initialize Video, VBI and Radio pads */
dev->video_pad.flags = MEDIA_PAD_FL_SINK;
ret = media_entity_pads_init(&dev->video_dev->entity, 1,
&dev->video_pad);
if (ret < 0)
pr_err("failed to initialize video media entity!\n");
dev->vbi_pad.flags = MEDIA_PAD_FL_SINK;
ret = media_entity_pads_init(&dev->vbi_dev->entity, 1,
&dev->vbi_pad);
if (ret < 0)
pr_err("failed to initialize vbi media entity!\n");
/* Create entities for each input connector */
for (i = 0; i < SAA7134_INPUT_MAX; i++) {
struct media_entity *ent = &dev->input_ent[i];
struct saa7134_input *in = &card_in(dev, i);
if (in->type == SAA7134_NO_INPUT)
break;
/* This input uses the S-Video connector */
if (in->type == SAA7134_INPUT_COMPOSITE_OVER_SVIDEO)
continue;
ent->name = saa7134_input_name[in->type];
ent->flags = MEDIA_ENT_FL_CONNECTOR;
dev->input_pad[i].flags = MEDIA_PAD_FL_SOURCE;
switch (in->type) {
case SAA7134_INPUT_COMPOSITE:
case SAA7134_INPUT_COMPOSITE0:
case SAA7134_INPUT_COMPOSITE1:
case SAA7134_INPUT_COMPOSITE2:
case SAA7134_INPUT_COMPOSITE3:
case SAA7134_INPUT_COMPOSITE4:
ent->function = MEDIA_ENT_F_CONN_COMPOSITE;
break;
case SAA7134_INPUT_SVIDEO:
case SAA7134_INPUT_SVIDEO0:
case SAA7134_INPUT_SVIDEO1:
ent->function = MEDIA_ENT_F_CONN_SVIDEO;
break;
default:
/*
* SAA7134_INPUT_TV and SAA7134_INPUT_TV_MONO.
*
* Please notice that neither SAA7134_INPUT_MUTE or
* SAA7134_INPUT_RADIO are defined at
* saa7134_board.input.
*/
ent->function = MEDIA_ENT_F_CONN_RF;
break;
}
ret = media_entity_pads_init(ent, 1, &dev->input_pad[i]);
if (ret < 0)
pr_err("failed to initialize input pad[%d]!\n", i);
ret = media_device_register_entity(dev->media_dev, ent);
if (ret < 0)
pr_err("failed to register input entity %d!\n", i);
}
/* Create input for Radio RF connector */
if (card_has_radio(dev)) {
struct saa7134_input *in = &saa7134_boards[dev->board].radio;
struct media_entity *ent = &dev->input_ent[i];
ent->name = saa7134_input_name[in->type];
ent->flags = MEDIA_ENT_FL_CONNECTOR;
dev->input_pad[i].flags = MEDIA_PAD_FL_SOURCE;
ent->function = MEDIA_ENT_F_CONN_RF;
ret = media_entity_pads_init(ent, 1, &dev->input_pad[i]);
if (ret < 0)
pr_err("failed to initialize input pad[%d]!\n", i);
ret = media_device_register_entity(dev->media_dev, ent);
if (ret < 0)
pr_err("failed to register input entity %d!\n", i);
}
}
#endif
static struct video_device *vdev_init(struct saa7134_dev *dev,
struct video_device *template,
char *type)
{
struct video_device *vfd;
vfd = video_device_alloc();
if (NULL == vfd)
return NULL;
*vfd = *template;
vfd->v4l2_dev = &dev->v4l2_dev;
vfd->release = video_device_release;
snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)",
dev->name, type, saa7134_boards[dev->board].name);
video_set_drvdata(vfd, dev);
return vfd;
}
static void saa7134_unregister_video(struct saa7134_dev *dev)
{
saa7134_media_release(dev);
if (dev->video_dev) {
if (video_is_registered(dev->video_dev))
vb2_video_unregister_device(dev->video_dev);
else
video_device_release(dev->video_dev);
dev->video_dev = NULL;
}
if (dev->vbi_dev) {
if (video_is_registered(dev->vbi_dev))
vb2_video_unregister_device(dev->vbi_dev);
else
video_device_release(dev->vbi_dev);
dev->vbi_dev = NULL;
}
if (dev->radio_dev) {
if (video_is_registered(dev->radio_dev))
video_unregister_device(dev->radio_dev);
else
video_device_release(dev->radio_dev);
dev->radio_dev = NULL;
}
}
static void mpeg_ops_attach(struct saa7134_mpeg_ops *ops,
struct saa7134_dev *dev)
{
int err;
if (NULL != dev->mops)
return;
if (saa7134_boards[dev->board].mpeg != ops->type)
return;
err = ops->init(dev);
if (0 != err)
return;
dev->mops = ops;
}
static void mpeg_ops_detach(struct saa7134_mpeg_ops *ops,
struct saa7134_dev *dev)
{
if (NULL == dev->mops)
return;
if (dev->mops != ops)
return;
dev->mops->fini(dev);
dev->mops = NULL;
}
static int saa7134_initdev(struct pci_dev *pci_dev,
const struct pci_device_id *pci_id)
{
struct saa7134_dev *dev;
struct saa7134_mpeg_ops *mops;
int err;
if (saa7134_devcount == SAA7134_MAXBOARDS)
return -ENOMEM;
dev = kzalloc(sizeof(*dev),GFP_KERNEL);
if (NULL == dev)
return -ENOMEM;
dev->nr = saa7134_devcount;
sprintf(dev->name, "saa%x[%d]", pci_dev->device, dev->nr);
#ifdef CONFIG_MEDIA_CONTROLLER
dev->media_dev = kzalloc(sizeof(*dev->media_dev), GFP_KERNEL);
if (!dev->media_dev) {
err = -ENOMEM;
goto err_free_dev;
}
media_device_pci_init(dev->media_dev, pci_dev, dev->name);
dev->v4l2_dev.mdev = dev->media_dev;
#endif
err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
if (err)
goto err_free_dev;
/* pci init */
dev->pci = pci_dev;
if (pci_enable_device(pci_dev)) {
err = -EIO;
goto err_v4l2_unregister;
}
/* pci quirks */
if (pci_pci_problems) {
if (pci_pci_problems & PCIPCI_TRITON)
pr_info("%s: quirk: PCIPCI_TRITON\n", dev->name);
if (pci_pci_problems & PCIPCI_NATOMA)
pr_info("%s: quirk: PCIPCI_NATOMA\n", dev->name);
if (pci_pci_problems & PCIPCI_VIAETBF)
pr_info("%s: quirk: PCIPCI_VIAETBF\n", dev->name);
if (pci_pci_problems & PCIPCI_VSFX)
pr_info("%s: quirk: PCIPCI_VSFX\n", dev->name);
#ifdef PCIPCI_ALIMAGIK
if (pci_pci_problems & PCIPCI_ALIMAGIK) {
pr_info("%s: quirk: PCIPCI_ALIMAGIK -- latency fixup\n",
dev->name);
latency = 0x0A;
}
#endif
}
if (UNSET != latency) {
pr_info("%s: setting pci latency timer to %d\n",
dev->name,latency);
pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, latency);
}
/* print pci info */
dev->pci_rev = pci_dev->revision;
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
pr_info("%s: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
dev->pci_lat,
(unsigned long long)pci_resource_start(pci_dev, 0));
pci_set_master(pci_dev);
err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32));
if (err) {
pr_warn("%s: Oops: no 32bit PCI DMA ???\n", dev->name);
goto err_v4l2_unregister;
}
/* board config */
dev->board = pci_id->driver_data;
if ((unsigned)card[dev->nr] < saa7134_bcount)
dev->board = card[dev->nr];
if (SAA7134_BOARD_UNKNOWN == dev->board)
must_configure_manually(0);
else if (SAA7134_BOARD_NOAUTO == dev->board) {
must_configure_manually(1);
dev->board = SAA7134_BOARD_UNKNOWN;
}
dev->autodetected = card[dev->nr] != dev->board;
dev->tuner_type = saa7134_boards[dev->board].tuner_type;
dev->tuner_addr = saa7134_boards[dev->board].tuner_addr;
dev->radio_type = saa7134_boards[dev->board].radio_type;
dev->radio_addr = saa7134_boards[dev->board].radio_addr;
dev->tda9887_conf = saa7134_boards[dev->board].tda9887_conf;
if (UNSET != tuner[dev->nr])
dev->tuner_type = tuner[dev->nr];
pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
dev->name,pci_dev->subsystem_vendor,
pci_dev->subsystem_device,saa7134_boards[dev->board].name,
dev->board, dev->autodetected ?
"autodetected" : "insmod option");
/* get mmio */
if (!request_mem_region(pci_resource_start(pci_dev,0),
pci_resource_len(pci_dev,0),
dev->name)) {
err = -EBUSY;
pr_err("%s: can't get MMIO memory @ 0x%llx\n",
dev->name,(unsigned long long)pci_resource_start(pci_dev,0));
goto err_v4l2_unregister;
}
dev->lmmio = ioremap(pci_resource_start(pci_dev, 0),
pci_resource_len(pci_dev, 0));
dev->bmmio = (__u8 __iomem *)dev->lmmio;
if (NULL == dev->lmmio) {
err = -EIO;
pr_err("%s: can't ioremap() MMIO memory\n",
dev->name);
goto err_release_mem_reg;
}
/* initialize hardware #1 */
saa7134_board_init1(dev);
saa7134_hwinit1(dev);
/* get irq */
err = request_irq(pci_dev->irq, saa7134_irq,
IRQF_SHARED, dev->name, dev);
if (err < 0) {
pr_err("%s: can't get IRQ %d\n",
dev->name,pci_dev->irq);
goto err_iounmap;
}
/* wait a bit, register i2c bus */
msleep(100);
saa7134_i2c_register(dev);
saa7134_board_init2(dev);
saa7134_hwinit2(dev);
/* load i2c helpers */
if (card_is_empress(dev)) {
dev->empress_sd =
v4l2_i2c_new_subdev(&dev->v4l2_dev, &dev->i2c_adap,
"saa6752hs",
saa7134_boards[dev->board].empress_addr, NULL);
if (dev->empress_sd)
dev->empress_sd->grp_id = GRP_EMPRESS;
}
if (saa7134_boards[dev->board].rds_addr) {
struct v4l2_subdev *sd;
sd = v4l2_i2c_new_subdev(&dev->v4l2_dev,
&dev->i2c_adap, "saa6588",
0, I2C_ADDRS(saa7134_boards[dev->board].rds_addr));
if (sd) {
pr_info("%s: found RDS decoder\n", dev->name);
dev->has_rds = 1;
}
}
mutex_lock(&saa7134_devlist_lock);
list_for_each_entry(mops, &mops_list, next)
mpeg_ops_attach(mops, dev);
list_add_tail(&dev->devlist, &saa7134_devlist);
mutex_unlock(&saa7134_devlist_lock);
/* check for signal */
saa7134_irq_video_signalchange(dev);
if (TUNER_ABSENT != dev->tuner_type)
saa_call_all(dev, core, s_power, 0);
/* register v4l devices */
dev->video_dev = vdev_init(dev,&saa7134_video_template,"video");
dev->video_dev->ctrl_handler = &dev->ctrl_handler;
dev->video_dev->lock = &dev->lock;
dev->video_dev->queue = &dev->video_vbq;
dev->video_dev->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
V4L2_CAP_VIDEO_CAPTURE;
if (dev->tuner_type != TUNER_ABSENT && dev->tuner_type != UNSET)
dev->video_dev->device_caps |= V4L2_CAP_TUNER;
err = video_register_device(dev->video_dev,VFL_TYPE_VIDEO,
video_nr[dev->nr]);
if (err < 0) {
pr_info("%s: can't register video device\n",
dev->name);
goto err_unregister_video;
}
pr_info("%s: registered device %s [v4l2]\n",
dev->name, video_device_node_name(dev->video_dev));
dev->vbi_dev = vdev_init(dev, &saa7134_video_template, "vbi");
dev->vbi_dev->ctrl_handler = &dev->ctrl_handler;
dev->vbi_dev->lock = &dev->lock;
dev->vbi_dev->queue = &dev->vbi_vbq;
dev->vbi_dev->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
V4L2_CAP_VBI_CAPTURE;
if (dev->tuner_type != TUNER_ABSENT && dev->tuner_type != UNSET)
dev->vbi_dev->device_caps |= V4L2_CAP_TUNER;
err = video_register_device(dev->vbi_dev,VFL_TYPE_VBI,
vbi_nr[dev->nr]);
if (err < 0)
goto err_unregister_video;
pr_info("%s: registered device %s\n",
dev->name, video_device_node_name(dev->vbi_dev));
if (card_has_radio(dev)) {
dev->radio_dev = vdev_init(dev,&saa7134_radio_template,"radio");
dev->radio_dev->ctrl_handler = &dev->radio_ctrl_handler;
dev->radio_dev->lock = &dev->lock;
dev->radio_dev->device_caps = V4L2_CAP_RADIO | V4L2_CAP_TUNER;
if (dev->has_rds)
dev->radio_dev->device_caps |= V4L2_CAP_RDS_CAPTURE;
err = video_register_device(dev->radio_dev,VFL_TYPE_RADIO,
radio_nr[dev->nr]);
if (err < 0)
goto err_unregister_video;
pr_info("%s: registered device %s\n",
dev->name, video_device_node_name(dev->radio_dev));
}
#ifdef CONFIG_MEDIA_CONTROLLER
saa7134_create_entities(dev);
err = v4l2_mc_create_media_graph(dev->media_dev);
if (err) {
pr_err("failed to create media graph\n");
goto err_unregister_video;
}
#endif
/* everything worked */
saa7134_devcount++;
if (saa7134_dmasound_init && !dev->dmasound.priv_data)
saa7134_dmasound_init(dev);
request_submodules(dev);
/*
* Do it at the end, to reduce dynamic configuration changes during
* the device init. Yet, as request_modules() can be async, the
* topology will likely change after load the saa7134 subdrivers.
*/
#ifdef CONFIG_MEDIA_CONTROLLER
err = media_device_register(dev->media_dev);
if (err) {
media_device_cleanup(dev->media_dev);
goto err_unregister_video;
}
#endif
return 0;
err_unregister_video:
saa7134_unregister_video(dev);
list_del(&dev->devlist);
saa7134_i2c_unregister(dev);
free_irq(pci_dev->irq, dev);
err_iounmap:
saa7134_hwfini(dev);
iounmap(dev->lmmio);
err_release_mem_reg:
release_mem_region(pci_resource_start(pci_dev,0),
pci_resource_len(pci_dev,0));
err_v4l2_unregister:
v4l2_device_unregister(&dev->v4l2_dev);
err_free_dev:
#ifdef CONFIG_MEDIA_CONTROLLER
kfree(dev->media_dev);
#endif
kfree(dev);
return err;
}
static void saa7134_finidev(struct pci_dev *pci_dev)
{
struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
struct saa7134_dev *dev = container_of(v4l2_dev, struct saa7134_dev, v4l2_dev);
struct saa7134_mpeg_ops *mops;
flush_request_submodules(dev);
/* Release DMA sound modules if present */
if (saa7134_dmasound_exit && dev->dmasound.priv_data) {
saa7134_dmasound_exit(dev);
}
/* debugging ... */
if (irq_debug) {
u32 report = saa_readl(SAA7134_IRQ_REPORT);
u32 status = saa_readl(SAA7134_IRQ_STATUS);
print_irqstatus(dev,42,report,status);
}
/* disable peripheral devices */
saa_writeb(SAA7134_SPECIAL_MODE,0);
/* shutdown hardware */
saa_writel(SAA7134_IRQ1,0);
saa_writel(SAA7134_IRQ2,0);
saa_writel(SAA7134_MAIN_CTRL,0);
/* shutdown subsystems */
saa7134_hwfini(dev);
/* unregister */
mutex_lock(&saa7134_devlist_lock);
list_del(&dev->devlist);
list_for_each_entry(mops, &mops_list, next)
mpeg_ops_detach(mops, dev);
mutex_unlock(&saa7134_devlist_lock);
saa7134_devcount--;
saa7134_i2c_unregister(dev);
saa7134_unregister_video(dev);
/* the DMA sound modules should be unloaded before reaching
this, but just in case they are still present... */
if (dev->dmasound.priv_data != NULL) {
free_irq(pci_dev->irq, &dev->dmasound);
dev->dmasound.priv_data = NULL;
}
/* release resources */
free_irq(pci_dev->irq, dev);
iounmap(dev->lmmio);
release_mem_region(pci_resource_start(pci_dev,0),
pci_resource_len(pci_dev,0));
v4l2_device_unregister(&dev->v4l2_dev);
saa7134_unregister_media_device(dev);
/* free memory */
kfree(dev);
}
/* resends a current buffer in queue after resume */
static int __maybe_unused saa7134_buffer_requeue(struct saa7134_dev *dev,
struct saa7134_dmaqueue *q)
{
struct saa7134_buf *buf, *next;
assert_spin_locked(&dev->slock);
buf = q->curr;
next = buf;
core_dbg("buffer_requeue\n");
if (!buf)
return 0;
core_dbg("buffer_requeue : resending active buffer\n");
if (!list_empty(&q->queue))
next = list_entry(q->queue.next, struct saa7134_buf,
entry);
buf->activate(dev, buf, next);
return 0;
}
static int __maybe_unused saa7134_suspend(struct device *dev_d)
{
struct pci_dev *pci_dev = to_pci_dev(dev_d);
struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
struct saa7134_dev *dev = container_of(v4l2_dev, struct saa7134_dev, v4l2_dev);
/* Disable interrupts, DMA, and rest of the chip*/
saa_writel(SAA7134_IRQ1, 0);
saa_writel(SAA7134_IRQ2, 0);
saa_writel(SAA7134_MAIN_CTRL, 0);
dev->insuspend = 1;
synchronize_irq(pci_dev->irq);
/* ACK interrupts once more, just in case,
since the IRQ handler won't ack them anymore*/
saa_writel(SAA7134_IRQ_REPORT, saa_readl(SAA7134_IRQ_REPORT));
/* Disable timeout timers - if we have active buffers, we will
fill them on resume*/
del_timer(&dev->video_q.timeout);
del_timer(&dev->vbi_q.timeout);
del_timer(&dev->ts_q.timeout);
if (dev->remote && dev->remote->dev->users)
saa7134_ir_close(dev->remote->dev);
return 0;
}
static int __maybe_unused saa7134_resume(struct device *dev_d)
{
struct v4l2_device *v4l2_dev = dev_get_drvdata(dev_d);
struct saa7134_dev *dev = container_of(v4l2_dev, struct saa7134_dev, v4l2_dev);
unsigned long flags;
/* Do things that are done in saa7134_initdev ,
except of initializing memory structures.*/
saa7134_board_init1(dev);
/* saa7134_hwinit1 */
if (saa7134_boards[dev->board].video_out)
saa7134_videoport_init(dev);
if (card_has_mpeg(dev))
saa7134_ts_init_hw(dev);
if (dev->remote && dev->remote->dev->users)
saa7134_ir_open(dev->remote->dev);
saa7134_hw_enable1(dev);
msleep(100);
saa7134_board_init2(dev);
/*saa7134_hwinit2*/
saa7134_set_tvnorm_hw(dev);
saa7134_tvaudio_setmute(dev);
saa7134_tvaudio_setvolume(dev, dev->ctl_volume);
saa7134_tvaudio_init(dev);
saa7134_enable_i2s(dev);
saa7134_hw_enable2(dev);
saa7134_irq_video_signalchange(dev);
/*resume unfinished buffer(s)*/
spin_lock_irqsave(&dev->slock, flags);
saa7134_buffer_requeue(dev, &dev->video_q);
saa7134_buffer_requeue(dev, &dev->vbi_q);
saa7134_buffer_requeue(dev, &dev->ts_q);
/* FIXME: Disable DMA audio sound - temporary till proper support
is implemented*/
dev->dmasound.dma_running = 0;
/* start DMA now*/
dev->insuspend = 0;
smp_wmb();
saa7134_set_dmabits(dev);
spin_unlock_irqrestore(&dev->slock, flags);
return 0;
}
/* ----------------------------------------------------------- */
int saa7134_ts_register(struct saa7134_mpeg_ops *ops)
{
struct saa7134_dev *dev;
mutex_lock(&saa7134_devlist_lock);
list_for_each_entry(dev, &saa7134_devlist, devlist)
mpeg_ops_attach(ops, dev);
list_add_tail(&ops->next,&mops_list);
mutex_unlock(&saa7134_devlist_lock);
return 0;
}
void saa7134_ts_unregister(struct saa7134_mpeg_ops *ops)
{
struct saa7134_dev *dev;
mutex_lock(&saa7134_devlist_lock);
list_del(&ops->next);
list_for_each_entry(dev, &saa7134_devlist, devlist)
mpeg_ops_detach(ops, dev);
mutex_unlock(&saa7134_devlist_lock);
}
EXPORT_SYMBOL(saa7134_ts_register);
EXPORT_SYMBOL(saa7134_ts_unregister);
/* ----------------------------------------------------------- */
static SIMPLE_DEV_PM_OPS(saa7134_pm_ops, saa7134_suspend, saa7134_resume);
static struct pci_driver saa7134_pci_driver = {
.name = "saa7134",
.id_table = saa7134_pci_tbl,
.probe = saa7134_initdev,
.remove = saa7134_finidev,
.driver.pm = &saa7134_pm_ops,
};
static int __init saa7134_init(void)
{
pr_info("saa7130/34: v4l2 driver version %s loaded\n",
SAA7134_VERSION);
return pci_register_driver(&saa7134_pci_driver);
}
static void __exit saa7134_fini(void)
{
pci_unregister_driver(&saa7134_pci_driver);
}
module_init(saa7134_init);
module_exit(saa7134_fini);
/* ----------------------------------------------------------- */
EXPORT_SYMBOL(saa7134_set_gpio);
EXPORT_SYMBOL(saa7134_boards);
/* ----------------- for the DMA sound modules --------------- */
EXPORT_SYMBOL(saa7134_dmasound_init);
EXPORT_SYMBOL(saa7134_dmasound_exit);
EXPORT_SYMBOL(saa7134_pgtable_free);
EXPORT_SYMBOL(saa7134_pgtable_build);
EXPORT_SYMBOL(saa7134_pgtable_alloc);
EXPORT_SYMBOL(saa7134_set_dmabits);
| linux-master | drivers/media/pci/saa7134/saa7134-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/mm.h>
#include <linux/usb.h>
#include <linux/i2c.h>
#include <asm/byteorder.h>
#include <media/v4l2-common.h>
#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
#include "go7007-priv.h"
/*#define GO7007_HPI_DEBUG*/
enum hpi_address {
HPI_ADDR_VIDEO_BUFFER = 0xe4,
HPI_ADDR_INIT_BUFFER = 0xea,
HPI_ADDR_INTR_RET_VALUE = 0xee,
HPI_ADDR_INTR_RET_DATA = 0xec,
HPI_ADDR_INTR_STATUS = 0xf4,
HPI_ADDR_INTR_WR_PARAM = 0xf6,
HPI_ADDR_INTR_WR_INDEX = 0xf8,
};
enum gpio_command {
GPIO_COMMAND_RESET = 0x00, /* 000b */
GPIO_COMMAND_REQ1 = 0x04, /* 001b */
GPIO_COMMAND_WRITE = 0x20, /* 010b */
GPIO_COMMAND_REQ2 = 0x24, /* 011b */
GPIO_COMMAND_READ = 0x80, /* 100b */
GPIO_COMMAND_VIDEO = 0x84, /* 101b */
GPIO_COMMAND_IDLE = 0xA0, /* 110b */
GPIO_COMMAND_ADDR = 0xA4, /* 111b */
};
struct saa7134_go7007 {
struct v4l2_subdev sd;
struct saa7134_dev *dev;
u8 *top;
u8 *bottom;
dma_addr_t top_dma;
dma_addr_t bottom_dma;
};
static const struct go7007_board_info board_voyager = {
.flags = 0,
.sensor_flags = GO7007_SENSOR_656 |
GO7007_SENSOR_VALID_ENABLE |
GO7007_SENSOR_TV |
GO7007_SENSOR_VBI,
.audio_flags = GO7007_AUDIO_I2S_MODE_1 |
GO7007_AUDIO_WORD_16,
.audio_rate = 48000,
.audio_bclk_div = 8,
.audio_main_div = 2,
.hpi_buffer_cap = 7,
.num_inputs = 1,
.inputs = {
{
.name = "SAA7134",
},
},
};
/********************* Driver for GPIO HPI interface *********************/
static int gpio_write(struct saa7134_dev *dev, u8 addr, u16 data)
{
saa_writeb(SAA7134_GPIO_GPMODE0, 0xff);
/* Write HPI address */
saa_writeb(SAA7134_GPIO_GPSTATUS0, addr);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_ADDR);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
/* Write low byte */
saa_writeb(SAA7134_GPIO_GPSTATUS0, data & 0xff);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_WRITE);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
/* Write high byte */
saa_writeb(SAA7134_GPIO_GPSTATUS0, data >> 8);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_WRITE);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
return 0;
}
static int gpio_read(struct saa7134_dev *dev, u8 addr, u16 *data)
{
saa_writeb(SAA7134_GPIO_GPMODE0, 0xff);
/* Write HPI address */
saa_writeb(SAA7134_GPIO_GPSTATUS0, addr);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_ADDR);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
saa_writeb(SAA7134_GPIO_GPMODE0, 0x00);
/* Read low byte */
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_READ);
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
*data = saa_readb(SAA7134_GPIO_GPSTATUS0);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
/* Read high byte */
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_READ);
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
*data |= saa_readb(SAA7134_GPIO_GPSTATUS0) << 8;
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
return 0;
}
static int saa7134_go7007_interface_reset(struct go7007 *go)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev = saa->dev;
u16 intr_val, intr_data;
int count = 20;
saa_clearb(SAA7134_TS_PARALLEL, 0x80); /* Disable TS interface */
saa_writeb(SAA7134_GPIO_GPMODE2, 0xa4);
saa_writeb(SAA7134_GPIO_GPMODE0, 0xff);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_REQ1);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_RESET);
msleep(1);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_REQ1);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_REQ2);
msleep(10);
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_readb(SAA7134_GPIO_GPSTATUS2);
/*pr_debug("status is %s\n", saa_readb(SAA7134_GPIO_GPSTATUS2) & 0x40 ? "OK" : "not OK"); */
/* enter command mode...(?) */
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_REQ1);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_REQ2);
do {
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_readb(SAA7134_GPIO_GPSTATUS2);
/*pr_info("gpio is %08x\n", saa_readl(SAA7134_GPIO_GPSTATUS0 >> 2)); */
} while (--count > 0);
/* Wait for an interrupt to indicate successful hardware reset */
if (go7007_read_interrupt(go, &intr_val, &intr_data) < 0 ||
(intr_val & ~0x1) != 0x55aa) {
pr_err("saa7134-go7007: unable to reset the GO7007\n");
return -1;
}
return 0;
}
static int saa7134_go7007_write_interrupt(struct go7007 *go, int addr, int data)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev = saa->dev;
int i;
u16 status_reg;
#ifdef GO7007_HPI_DEBUG
pr_debug("saa7134-go7007: WriteInterrupt: %04x %04x\n", addr, data);
#endif
for (i = 0; i < 100; ++i) {
gpio_read(dev, HPI_ADDR_INTR_STATUS, &status_reg);
if (!(status_reg & 0x0010))
break;
msleep(10);
}
if (i == 100) {
pr_err("saa7134-go7007: device is hung, status reg = 0x%04x\n",
status_reg);
return -1;
}
gpio_write(dev, HPI_ADDR_INTR_WR_PARAM, data);
gpio_write(dev, HPI_ADDR_INTR_WR_INDEX, addr);
return 0;
}
static int saa7134_go7007_read_interrupt(struct go7007 *go)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev = saa->dev;
/* XXX we need to wait if there is no interrupt available */
go->interrupt_available = 1;
gpio_read(dev, HPI_ADDR_INTR_RET_VALUE, &go->interrupt_value);
gpio_read(dev, HPI_ADDR_INTR_RET_DATA, &go->interrupt_data);
#ifdef GO7007_HPI_DEBUG
pr_debug("saa7134-go7007: ReadInterrupt: %04x %04x\n",
go->interrupt_value, go->interrupt_data);
#endif
return 0;
}
static void saa7134_go7007_irq_ts_done(struct saa7134_dev *dev,
unsigned long status)
{
struct go7007 *go = video_get_drvdata(dev->empress_dev);
struct saa7134_go7007 *saa = go->hpi_context;
if (!vb2_is_streaming(&go->vidq))
return;
if (0 != (status & 0x000f0000))
pr_debug("saa7134-go7007: irq: lost %ld\n",
(status >> 16) & 0x0f);
if (status & 0x100000) {
dma_sync_single_for_cpu(&dev->pci->dev,
saa->bottom_dma, PAGE_SIZE, DMA_FROM_DEVICE);
go7007_parse_video_stream(go, saa->bottom, PAGE_SIZE);
saa_writel(SAA7134_RS_BA2(5), saa->bottom_dma);
} else {
dma_sync_single_for_cpu(&dev->pci->dev,
saa->top_dma, PAGE_SIZE, DMA_FROM_DEVICE);
go7007_parse_video_stream(go, saa->top, PAGE_SIZE);
saa_writel(SAA7134_RS_BA1(5), saa->top_dma);
}
}
static int saa7134_go7007_stream_start(struct go7007 *go)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev = saa->dev;
saa->top_dma = dma_map_page(&dev->pci->dev, virt_to_page(saa->top),
0, PAGE_SIZE, DMA_FROM_DEVICE);
if (dma_mapping_error(&dev->pci->dev, saa->top_dma))
return -ENOMEM;
saa->bottom_dma = dma_map_page(&dev->pci->dev,
virt_to_page(saa->bottom),
0, PAGE_SIZE, DMA_FROM_DEVICE);
if (dma_mapping_error(&dev->pci->dev, saa->bottom_dma)) {
dma_unmap_page(&dev->pci->dev, saa->top_dma, PAGE_SIZE,
DMA_FROM_DEVICE);
return -ENOMEM;
}
saa_writel(SAA7134_VIDEO_PORT_CTRL0 >> 2, 0xA300B000);
saa_writel(SAA7134_VIDEO_PORT_CTRL4 >> 2, 0x40000200);
/* Set HPI interface for video */
saa_writeb(SAA7134_GPIO_GPMODE0, 0xff);
saa_writeb(SAA7134_GPIO_GPSTATUS0, HPI_ADDR_VIDEO_BUFFER);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_ADDR);
saa_writeb(SAA7134_GPIO_GPMODE0, 0x00);
/* Enable TS interface */
saa_writeb(SAA7134_TS_PARALLEL, 0xe6);
/* Reset TS interface */
saa_setb(SAA7134_TS_SERIAL1, 0x01);
saa_clearb(SAA7134_TS_SERIAL1, 0x01);
/* Set up transfer block size */
saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 128 - 1);
saa_writeb(SAA7134_TS_DMA0, ((PAGE_SIZE >> 7) - 1) & 0xff);
saa_writeb(SAA7134_TS_DMA1, (PAGE_SIZE >> 15) & 0xff);
saa_writeb(SAA7134_TS_DMA2, (PAGE_SIZE >> 31) & 0x3f);
/* Enable video streaming mode */
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_VIDEO);
saa_writel(SAA7134_RS_BA1(5), saa->top_dma);
saa_writel(SAA7134_RS_BA2(5), saa->bottom_dma);
saa_writel(SAA7134_RS_PITCH(5), 128);
saa_writel(SAA7134_RS_CONTROL(5), SAA7134_RS_CONTROL_BURST_MAX);
/* Enable TS FIFO */
saa_setl(SAA7134_MAIN_CTRL, SAA7134_MAIN_CTRL_TE5);
/* Enable DMA IRQ */
saa_setl(SAA7134_IRQ1,
SAA7134_IRQ1_INTE_RA2_1 | SAA7134_IRQ1_INTE_RA2_0);
return 0;
}
static int saa7134_go7007_stream_stop(struct go7007 *go)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev;
if (!saa)
return -EINVAL;
dev = saa->dev;
if (!dev)
return -EINVAL;
/* Shut down TS FIFO */
saa_clearl(SAA7134_MAIN_CTRL, SAA7134_MAIN_CTRL_TE5);
/* Disable DMA IRQ */
saa_clearl(SAA7134_IRQ1,
SAA7134_IRQ1_INTE_RA2_1 | SAA7134_IRQ1_INTE_RA2_0);
/* Disable TS interface */
saa_clearb(SAA7134_TS_PARALLEL, 0x80);
dma_unmap_page(&dev->pci->dev, saa->top_dma, PAGE_SIZE,
DMA_FROM_DEVICE);
dma_unmap_page(&dev->pci->dev, saa->bottom_dma, PAGE_SIZE,
DMA_FROM_DEVICE);
return 0;
}
static int saa7134_go7007_send_firmware(struct go7007 *go, u8 *data, int len)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev = saa->dev;
u16 status_reg;
int i;
#ifdef GO7007_HPI_DEBUG
pr_debug("saa7134-go7007: DownloadBuffer sending %d bytes\n", len);
#endif
while (len > 0) {
i = len > 64 ? 64 : len;
saa_writeb(SAA7134_GPIO_GPMODE0, 0xff);
saa_writeb(SAA7134_GPIO_GPSTATUS0, HPI_ADDR_INIT_BUFFER);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_ADDR);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
while (i-- > 0) {
saa_writeb(SAA7134_GPIO_GPSTATUS0, *data);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_WRITE);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
++data;
--len;
}
for (i = 0; i < 100; ++i) {
gpio_read(dev, HPI_ADDR_INTR_STATUS, &status_reg);
if (!(status_reg & 0x0002))
break;
}
if (i == 100) {
pr_err("saa7134-go7007: device is hung, status reg = 0x%04x\n",
status_reg);
return -1;
}
}
return 0;
}
static const struct go7007_hpi_ops saa7134_go7007_hpi_ops = {
.interface_reset = saa7134_go7007_interface_reset,
.write_interrupt = saa7134_go7007_write_interrupt,
.read_interrupt = saa7134_go7007_read_interrupt,
.stream_start = saa7134_go7007_stream_start,
.stream_stop = saa7134_go7007_stream_stop,
.send_firmware = saa7134_go7007_send_firmware,
};
MODULE_FIRMWARE("go7007/go7007tv.bin");
/* --------------------------------------------------------------------------*/
static int saa7134_go7007_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
{
#if 0
struct saa7134_go7007 *saa = container_of(sd, struct saa7134_go7007, sd);
struct saa7134_dev *dev = saa->dev;
return saa7134_s_std_internal(dev, NULL, norm);
#else
return 0;
#endif
}
static const struct v4l2_subdev_video_ops saa7134_go7007_video_ops = {
.s_std = saa7134_go7007_s_std,
};
static const struct v4l2_subdev_ops saa7134_go7007_sd_ops = {
.video = &saa7134_go7007_video_ops,
};
/* --------------------------------------------------------------------------*/
/********************* Add/remove functions *********************/
static int saa7134_go7007_init(struct saa7134_dev *dev)
{
struct go7007 *go;
struct saa7134_go7007 *saa;
struct v4l2_subdev *sd;
pr_debug("saa7134-go7007: probing new SAA713X board\n");
go = go7007_alloc(&board_voyager, &dev->pci->dev);
if (go == NULL)
return -ENOMEM;
saa = kzalloc(sizeof(struct saa7134_go7007), GFP_KERNEL);
if (saa == NULL) {
kfree(go);
return -ENOMEM;
}
go->board_id = GO7007_BOARDID_PCI_VOYAGER;
snprintf(go->bus_info, sizeof(go->bus_info), "PCI:%s", pci_name(dev->pci));
strscpy(go->name, saa7134_boards[dev->board].name, sizeof(go->name));
go->hpi_ops = &saa7134_go7007_hpi_ops;
go->hpi_context = saa;
saa->dev = dev;
/* Init the subdevice interface */
sd = &saa->sd;
v4l2_subdev_init(sd, &saa7134_go7007_sd_ops);
v4l2_set_subdevdata(sd, saa);
strscpy(sd->name, "saa7134-go7007", sizeof(sd->name));
/* Allocate a couple pages for receiving the compressed stream */
saa->top = (u8 *)get_zeroed_page(GFP_KERNEL);
if (!saa->top)
goto allocfail;
saa->bottom = (u8 *)get_zeroed_page(GFP_KERNEL);
if (!saa->bottom)
goto allocfail;
/* Boot the GO7007 */
if (go7007_boot_encoder(go, go->board_info->flags &
GO7007_BOARD_USE_ONBOARD_I2C) < 0)
goto allocfail;
/* Do any final GO7007 initialization, then register the
* V4L2 and ALSA interfaces */
if (go7007_register_encoder(go, go->board_info->num_i2c_devs) < 0)
goto allocfail;
/* Register the subdevice interface with the go7007 device */
if (v4l2_device_register_subdev(&go->v4l2_dev, sd) < 0)
pr_info("saa7134-go7007: register subdev failed\n");
dev->empress_dev = &go->vdev;
go->status = STATUS_ONLINE;
return 0;
allocfail:
if (saa->top)
free_page((unsigned long)saa->top);
if (saa->bottom)
free_page((unsigned long)saa->bottom);
kfree(saa);
kfree(go);
return -ENOMEM;
}
static int saa7134_go7007_fini(struct saa7134_dev *dev)
{
struct go7007 *go;
struct saa7134_go7007 *saa;
if (NULL == dev->empress_dev)
return 0;
go = video_get_drvdata(dev->empress_dev);
if (go->audio_enabled)
go7007_snd_remove(go);
saa = go->hpi_context;
go->status = STATUS_SHUTDOWN;
free_page((unsigned long)saa->top);
free_page((unsigned long)saa->bottom);
v4l2_device_unregister_subdev(&saa->sd);
kfree(saa);
vb2_video_unregister_device(&go->vdev);
v4l2_device_put(&go->v4l2_dev);
dev->empress_dev = NULL;
return 0;
}
static struct saa7134_mpeg_ops saa7134_go7007_ops = {
.type = SAA7134_MPEG_GO7007,
.init = saa7134_go7007_init,
.fini = saa7134_go7007_fini,
.irq_ts_done = saa7134_go7007_irq_ts_done,
};
static int __init saa7134_go7007_mod_init(void)
{
return saa7134_ts_register(&saa7134_go7007_ops);
}
static void __exit saa7134_go7007_mod_cleanup(void)
{
saa7134_ts_unregister(&saa7134_go7007_ops);
}
module_init(saa7134_go7007_mod_init);
module_exit(saa7134_go7007_mod_cleanup);
MODULE_LICENSE("GPL v2");
| linux-master | drivers/media/pci/saa7134/saa7134-go7007.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* device driver for philips saa7134 based TV cards
* card-specific stuff.
*
* (c) 2001-04 Gerd Knorr <[email protected]> [SuSE Labs]
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include "xc2028.h"
#include <media/v4l2-common.h>
#include <media/tveeprom.h>
#include "tea5767.h"
#include "tda18271.h"
#include "xc5000.h"
#include "s5h1411.h"
/* Input names */
const char * const saa7134_input_name[] = {
[SAA7134_INPUT_MUTE] = "mute",
[SAA7134_INPUT_RADIO] = "Radio",
[SAA7134_INPUT_TV] = "Television",
[SAA7134_INPUT_TV_MONO] = "TV (mono only)",
[SAA7134_INPUT_COMPOSITE] = "Composite",
[SAA7134_INPUT_COMPOSITE0] = "Composite0",
[SAA7134_INPUT_COMPOSITE1] = "Composite1",
[SAA7134_INPUT_COMPOSITE2] = "Composite2",
[SAA7134_INPUT_COMPOSITE3] = "Composite3",
[SAA7134_INPUT_COMPOSITE4] = "Composite4",
[SAA7134_INPUT_SVIDEO] = "S-Video",
[SAA7134_INPUT_SVIDEO0] = "S-Video0",
[SAA7134_INPUT_SVIDEO1] = "S-Video1",
[SAA7134_INPUT_COMPOSITE_OVER_SVIDEO] = "Composite over S-Video",
};
/* ------------------------------------------------------------------ */
/* board config info */
static struct tda18271_std_map aver_a706_std_map = {
.fm_radio = { .if_freq = 5500, .fm_rfn = 0, .agc_mode = 3, .std = 0,
.if_lvl = 0, .rfagc_top = 0x2c, },
};
/* If radio_type !=UNSET, radio_addr should be specified
*/
struct saa7134_board saa7134_boards[] = {
[SAA7134_BOARD_UNKNOWN] = {
.name = "UNKNOWN/GENERIC",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 0,
.amux = LINE1,
}},
},
[SAA7134_BOARD_PROTEUS_PRO] = {
/* /me */
.name = "Proteus Pro [philips reference design]",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_FLYVIDEO3000] = {
/* "Marco d'Itri" <[email protected]> */
.name = "LifeView FlyVIDEO3000",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0xe000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x8000,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
.gpio = 0x0000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
.gpio = 0x4000,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
.gpio = 0x4000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x4000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x2000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x8000,
},
},
[SAA7134_BOARD_FLYVIDEO2000] = {
/* "TC Wan" <[email protected]> */
.name = "LifeView/Typhoon FlyVIDEO2000",
.audio_clock = 0x00200000,
.tuner_type = TUNER_LG_PAL_NEW_TAPC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0xe000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
.gpio = 0x0000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
.gpio = 0x4000,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
.gpio = 0x4000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x4000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x2000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE2,
.gpio = 0x8000,
},
},
[SAA7134_BOARD_FLYTVPLATINUM_MINI] = {
/* "Arnaud Quette" <[email protected]> */
.name = "LifeView FlyTV Platinum Mini",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_FLYTVPLATINUM_FM] = {
/* LifeView FlyTV Platinum FM (LR214WF) */
/* "Peter Missel <[email protected]> */
.name = "LifeView FlyTV Platinum FM / Gold",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x1E000, /* Set GP16 and unused 15,14,13 to Output */
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x10000, /* GP16=1 selects TV input */
},{
/* .type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
.gpio = 0x0000,
},{
*/ .type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE2,
/* .gpio = 0x4000, */
},{
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 3,
.amux = LINE2,
/* .gpio = 0x4000, */
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
/* .gpio = 0x4000, */
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x00000, /* GP16=0 selects FM radio antenna */
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x10000,
},
},
[SAA7134_BOARD_ROVERMEDIA_LINK_PRO_FM] = {
/* RoverMedia TV Link Pro FM (LR138 REV:I) */
/* Eugene Yudin <[email protected]> */
.name = "RoverMedia TV Link Pro FM",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3, /* TCL MFPE05 2 */
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0xe000,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x8000,
}, {
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
.gpio = 0x0000,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
.gpio = 0x4000,
}, {
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
.gpio = 0x4000,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x4000,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x2000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x8000,
},
},
[SAA7134_BOARD_EMPRESS] = {
/* "Gert Vervoort" <[email protected]> */
.name = "EMPRESS",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.empress_addr = 0x20,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
.mpeg = SAA7134_MPEG_EMPRESS,
.video_out = CCIR656,
},
[SAA7134_BOARD_MONSTERTV] = {
/* "K.Ohta" <[email protected]> */
.name = "SKNet Monster TV",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_NTSC_M,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_MD9717] = {
.name = "Tevion MD 9717",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
/* workaround for problems with normal TV sound */
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
},
},
[SAA7134_BOARD_TVSTATION_RDS] = {
/* Typhoon TV Tuner RDS: Art.Nr. 50694 */
.name = "KNC One TV-Station RDS / Typhoon TV Tuner RDS",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_TVSTATION_DVR] = {
.name = "KNC One TV-Station DVR",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.empress_addr = 0x20,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x820000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x20000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x20000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x20000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x20000,
},
.mpeg = SAA7134_MPEG_EMPRESS,
.video_out = CCIR656,
},
[SAA7134_BOARD_CINERGY400] = {
.name = "Terratec Cinergy 400 TV",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 4,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE1,
}}
},
[SAA7134_BOARD_MD5044] = {
.name = "Medion 5044",
.audio_clock = 0x00187de7, /* was: 0x00200000, */
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
/* workaround for problems with normal TV sound */
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_KWORLD] = {
.name = "Kworld/KuroutoShikou SAA7130-TVPCI",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_NTSC_M,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
}},
},
[SAA7134_BOARD_CINERGY600] = {
.name = "Terratec Cinergy 600 TV",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 4,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_MD7134] = {
.name = "Medion 7134",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FMD1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
},
},
[SAA7134_BOARD_TYPHOON_90031] = {
/* aka Typhoon "TV+Radio", Art.Nr 90031 */
/* Tom Zoerner <tomzo at users sourceforge net> */
.name = "Typhoon TV+Radio 90031",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_ELSA] = {
.name = "ELSA EX-VISION 300TV",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_HITACHI_NTSC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 4,
.amux = LINE2,
}},
},
[SAA7134_BOARD_ELSA_500TV] = {
.name = "ELSA EX-VISION 500TV",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_HITACHI_NTSC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 7,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 8,
.amux = TV,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_ELSA_700TV] = {
.name = "ELSA EX-VISION 700TV",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_HITACHI_NTSC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 4,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 6,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 7,
.amux = LINE1,
}},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
},
},
[SAA7134_BOARD_ASUSTeK_TVFM7134] = {
.name = "ASUS TV-FM 7134",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 4,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
},
},
[SAA7134_BOARD_ASUSTeK_TVFM7135] = {
.name = "ASUS TV-FM 7135",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x200000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x0000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 4,
.amux = LINE2,
.gpio = 0x0000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE2,
.gpio = 0x0000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x200000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.gpio = 0x0000,
},
},
[SAA7134_BOARD_VA1000POWER] = {
.name = "AOPEN VA1000 POWER",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_NTSC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
}},
},
[SAA7134_BOARD_10MOONSTVMASTER] = {
/* "lilicheng" <[email protected]> */
.name = "10MOONS PCI TV CAPTURE CARD",
.audio_clock = 0x00200000,
.tuner_type = TUNER_LG_PAL_NEW_TAPC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0xe000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
.gpio = 0x0000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
.gpio = 0x4000,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
.gpio = 0x4000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x4000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x2000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE2,
.gpio = 0x8000,
},
},
[SAA7134_BOARD_BMK_MPEX_NOTUNER] = {
/* "Andrew de Quincey" <[email protected]> */
.name = "BMK MPEX No Tuner",
.audio_clock = 0x200000,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.empress_addr = 0x20,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 4,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE3,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE4,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.mpeg = SAA7134_MPEG_EMPRESS,
.video_out = CCIR656,
},
[SAA7134_BOARD_VIDEOMATE_TV] = {
.name = "Compro VideoMate TV",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_NTSC_M,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
}},
},
[SAA7134_BOARD_VIDEOMATE_TV_GOLD_PLUS] = {
.name = "Compro VideoMate TV Gold+",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_NTSC_M,
.gpiomask = 0x800c0000,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x06c00012,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x0ac20012,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
.gpio = 0x08c20012,
}}, /* radio and probably mute is missing */
},
[SAA7134_BOARD_CRONOS_PLUS] = {
/*
gpio pins:
0 .. 3 BASE_ID
4 .. 7 PROTECT_ID
8 .. 11 USER_OUT
12 .. 13 USER_IN
14 .. 15 VIDIN_SEL
*/
.name = "Matrox CronosPlus",
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0xcf00,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.gpio = 2 << 14,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 0,
.gpio = 1 << 14,
},{
.type = SAA7134_INPUT_COMPOSITE3,
.vmux = 0,
.gpio = 0 << 14,
},{
.type = SAA7134_INPUT_COMPOSITE4,
.vmux = 0,
.gpio = 3 << 14,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.gpio = 2 << 14,
}},
},
[SAA7134_BOARD_MD2819] = {
.name = "AverMedia M156 / Medion 2819",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x03,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x00,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x02,
}, {
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 0,
.amux = LINE1,
.gpio = 0x02,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x02,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
.gpio = 0x01,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x00,
},
},
[SAA7134_BOARD_BMK_MPEX_TUNER] = {
/* "Greg Wickham <[email protected]> */
.name = "BMK MPEX Tuner",
.audio_clock = 0x200000,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.empress_addr = 0x20,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}},
.mpeg = SAA7134_MPEG_EMPRESS,
.video_out = CCIR656,
},
[SAA7134_BOARD_ASUSTEK_TVFM7133] = {
.name = "ASUS TV-FM 7133",
.audio_clock = 0x00187de7,
/* probably wrong, the 7133 one is the NTSC version ...
* .tuner_type = TUNER_PHILIPS_FM1236_MK3 */
.tuner_type = TUNER_LG_NTSC_NEW_TAPC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 4,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
},
},
[SAA7134_BOARD_PINNACLE_PCTV_STEREO] = {
.name = "Pinnacle PCTV Stereo (saa7134)",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_MT2032,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT | TDA9887_INTERCARRIER | TDA9887_PORT2_INACTIVE,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_MANLI_MTV002] = {
/* Ognjen Nastic <[email protected]> */
.name = "Manli MuchTV M-TV002",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_MANLI_MTV001] = {
/* Ognjen Nastic <[email protected]> UNTESTED */
.name = "Manli MuchTV M-TV001",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
}},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
},
[SAA7134_BOARD_TG3000TV] = {
/* TransGear 3000TV */
.name = "Nagase Sangyo TransGear 3000TV",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_NTSC_M,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_ECS_TVP3XP] = {
.name = "Elitegroup ECS TVP3XP FM1216 Tuner Card(PAL-BG,FM) ",
.audio_clock = 0x187de7, /* xtal 32.1 MHz */
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_ECS_TVP3XP_4CB5] = {
.name = "Elitegroup ECS TVP3XP FM1236 Tuner Card (NTSC,FM)",
.audio_clock = 0x187de7,
.tuner_type = TUNER_PHILIPS_NTSC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_ECS_TVP3XP_4CB6] = {
/* Barry Scott <[email protected]> */
.name = "Elitegroup ECS TVP3XP FM1246 Tuner Card (PAL,FM)",
.audio_clock = 0x187de7,
.tuner_type = TUNER_PHILIPS_PAL_I,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_AVACSSMARTTV] = {
/* Roman Pszonczenko <[email protected]> */
.name = "AVACS SmartTV",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x200000,
},
},
[SAA7134_BOARD_AVERMEDIA_DVD_EZMAKER] = {
/* Michael Smith <[email protected]> */
.name = "AVerMedia DVD EZMaker",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
}},
},
[SAA7134_BOARD_AVERMEDIA_M103] = {
/* Massimo Piccioni <[email protected]> */
.name = "AVerMedia MiniPCI DVB-T Hybrid M103",
.audio_clock = 0x187de7,
.tuner_type = TUNER_XC2028,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
} },
},
[SAA7134_BOARD_NOVAC_PRIMETV7133] = {
/* [email protected] */
.name = "Noval Prime TV 7133",
.audio_clock = 0x00200000,
.tuner_type = TUNER_ALPS_TSBH1_NTSC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
}},
},
[SAA7134_BOARD_AVERMEDIA_STUDIO_305] = {
.name = "AverMedia AverTV Studio 305",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1256_IH3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
},
[SAA7134_BOARD_AVERMEDIA_STUDIO_505] = {
/* Vasiliy Temnikov <[email protected]> */
.name = "AverMedia AverTV Studio 505",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
},
[SAA7134_BOARD_UPMOST_PURPLE_TV] = {
.name = "UPMOST PURPLE TV",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1236_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 7,
.amux = TV,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 7,
.amux = LINE1,
}},
},
[SAA7134_BOARD_ITEMS_MTV005] = {
/* Norman Jonas <[email protected]> */
.name = "Items MuchTV Plus / IT-005",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_CINERGY200] = {
.name = "Terratec Cinergy 200 TV",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 4,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE1,
}},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE2,
},
},
[SAA7134_BOARD_VIDEOMATE_TV_PVR] = {
/* Alain St-Denis <[email protected]> */
.name = "Compro VideoMate TV PVR/FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_NTSC_M,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x808c0080,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x00080,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x00080,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2_LEFT,
.gpio = 0x00080,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x80000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE2,
.gpio = 0x40000,
},
},
[SAA7134_BOARD_SABRENT_SBTTVFM] = {
/* Michael Rodriguez-Torrent <[email protected]> */
.name = "Sabrent SBT-TVFM (saa7130)",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_NTSC_M,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_ZOLID_XPERT_TV7134] = {
/* Helge Jensen <[email protected]> */
.name = ":Zolid Xpert TV7134",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_NTSC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
}},
},
[SAA7134_BOARD_EMPIRE_PCI_TV_RADIO_LE] = {
/* "Matteo Az" <[email protected]> ;-) */
.name = "Empire PCI TV-Radio LE",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x4000,
.inputs = {{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
.gpio = 0x8000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x8000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE1,
.gpio = 0x8000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
.gpio = 0x8000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio =0x8000,
}
},
[SAA7134_BOARD_AVERMEDIA_STUDIO_307] = {
/*
Nickolay V. Shmyrev <[email protected]>
Lots of thanks to Andrey Zolotarev <[email protected]>
*/
.name = "Avermedia AVerTV Studio 307",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1256_IH3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x03,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x00,
},{
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 3,
.amux = LINE1,
.gpio = 0x02,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x02,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
.gpio = 0x01,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
.gpio = 0x00,
},
},
[SAA7134_BOARD_AVERMEDIA_GO_007_FM] = {
.name = "Avermedia AVerTV GO 007 FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x00300003,
/* .gpiomask = 0x8c240003, */
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x01,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
.gpio = 0x02,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE1,
.gpio = 0x02,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x00300001,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x01,
},
},
[SAA7134_BOARD_AVERMEDIA_CARDBUS] = {
/* [email protected] */
.name = "AVerMedia Cardbus TV/Radio (E500)",
.audio_clock = 0x187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
},
},
[SAA7134_BOARD_AVERMEDIA_CARDBUS_501] = {
/* Oldrich Jedlicka <[email protected]> */
.name = "AVerMedia Cardbus TV/Radio (E501R)",
.audio_clock = 0x187de7,
.tuner_type = TUNER_ALPS_TSBE5_PAL,
.radio_type = TUNER_TEA5767,
.tuner_addr = 0x61,
.radio_addr = 0x60,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x08000000,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x08000000,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x08000000,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x08000000,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x00000000,
},
},
[SAA7134_BOARD_CINERGY400_CARDBUS] = {
.name = "Terratec Cinergy 400 mobile",
.audio_clock = 0x187de7,
.tuner_type = TUNER_ALPS_TSBE5_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
},
[SAA7134_BOARD_CINERGY600_MK3] = {
.name = "Terratec Cinergy 600 TV MK3",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.rds_addr = 0x10,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 4,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_VIDEOMATE_GOLD_PLUS] = {
/* Dylan Walkden <[email protected]> */
.name = "Compro VideoMate Gold+ Pal",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_PAL,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x1ce780,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE1,
.gpio = 0x008080,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x008080,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x008080,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x80000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE2,
.gpio = 0x0c8000,
},
},
[SAA7134_BOARD_PINNACLE_300I_DVBT_PAL] = {
.name = "Pinnacle PCTV 300i DVB-T + PAL",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_MT2032,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT | TDA9887_INTERCARRIER | TDA9887_PORT2_INACTIVE,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_PROVIDEO_PV952] = {
/* [email protected] */
.name = "ProVideo PV952",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_AVERMEDIA_305] = {
/* much like the "studio" version but without radio
* and another tuner ([email protected]) */
.name = "AverMedia AverTV/305",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FQ1216ME,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
},
[SAA7134_BOARD_FLYDVBTDUO] = {
/* LifeView FlyDVB-T DUO */
/* "Nico Sabbi <[email protected]> Hartmut Hackmann [email protected]*/
.name = "LifeView FlyDVB-T DUO / MSI TV@nywhere Duo",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x00200000,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x200000, /* GPIO21=High for TV input */
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x000000, /* GPIO21=Low for FM radio antenna */
},
},
[SAA7134_BOARD_PHILIPS_TOUGH] = {
.name = "Philips TOUGH DVB-T reference design",
.tuner_type = TUNER_ABSENT,
.audio_clock = 0x00187de7,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
},
[SAA7134_BOARD_AVERMEDIA_307] = {
/*
Davydov Vladimir <[email protected]>
*/
.name = "Avermedia AVerTV 307",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FQ1216ME,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
},
[SAA7134_BOARD_ADS_INSTANT_TV] = {
.name = "ADS Tech Instant TV (saa7135)",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_KWORLD_VSTREAM_XPERT] = {
.name = "Kworld/Tevion V-Stream Xpert TV PVR7134",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_PAL_I,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x0700,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x200, /* gpio by DScaler */
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 0,
.amux = LINE1,
.gpio = 0x200,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
.gpio = 0x100,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x000,
},
},
[SAA7134_BOARD_FLYDVBT_DUO_CARDBUS] = {
.name = "LifeView/Typhoon/Genius FlyDVB-T Duo Cardbus",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 0x00200000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x200000, /* GPIO21=High for TV input */
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x000000, /* GPIO21=Low for FM radio antenna */
},
},
[SAA7134_BOARD_VIDEOMATE_TV_GOLD_PLUSII] = {
.name = "Compro VideoMate TV Gold+II",
.audio_clock = 0x002187de7,
.tuner_type = TUNER_LG_PAL_NEW_TAPC,
.radio_type = TUNER_TEA5767,
.tuner_addr = 0x63,
.radio_addr = 0x60,
.gpiomask = 0x8c1880,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 0,
.amux = LINE1,
.gpio = 0x800800,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x801000,
},{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x800000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x880000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE2,
.gpio = 0x840000,
},
},
[SAA7134_BOARD_KWORLD_XPERT] = {
/*
FIXME:
- Remote control doesn't initialize properly.
- Audio volume starts muted,
then gradually increases after channel change.
- Composite S-Video untested.
From: Konrad Rzepecki <[email protected]>
*/
.name = "Kworld Xpert TV PVR7134",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_TENA_9533_DI,
.radio_type = TUNER_TEA5767,
.tuner_addr = 0x61,
.radio_addr = 0x60,
.gpiomask = 0x0700,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x200, /* gpio by DScaler */
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 0,
.amux = LINE1,
.gpio = 0x200,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
.gpio = 0x100,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x000,
},
},
[SAA7134_BOARD_FLYTV_DIGIMATRIX] = {
.name = "FlyTV mini Asus Digimatrix",
.audio_clock = 0x00200000,
.tuner_type = TUNER_LG_TALN,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO, /* radio unconfirmed */
.amux = LINE2,
},
},
[SAA7134_BOARD_KWORLD_TERMINATOR] = {
/* Kworld V-Stream Studio TV Terminator */
/* "James Webb <[email protected]> */
.name = "V-Stream Studio TV Terminator",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 1 << 21,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x0000000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
.gpio = 0x0000000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x0000000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_YUAN_TUN900] = {
/* FIXME:
* S-Video and composite sources untested.
* Radio not working.
* Remote control not yet implemented.
* From : [email protected] */
.name = "Yuan TUN-900 (saa7135)",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr= ADDR_UNSET,
.radio_addr= ADDR_UNSET,
.gpiomask = 0x00010003,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x01,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
.gpio = 0x02,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE2,
.gpio = 0x02,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
.gpio = 0x00010003,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x01,
},
},
[SAA7134_BOARD_BEHOLD_409FM] = {
/* <http://tuner.beholder.ru>, Sergey <[email protected]> */
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 409 FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_GOTVIEW_7135] = {
/* Mike Baikov <[email protected]> */
/* Andrey Cvetcov <[email protected]> */
.name = "GoTView 7135 PCI",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00200003,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x00200003,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
.gpio = 0x00200003,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x00200003,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x00200003,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x00200003,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x00200003,
},
},
[SAA7134_BOARD_PHILIPS_EUROPA] = {
.name = "Philips EUROPA V3 reference design",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TD1316,
.radio_type = UNSET,
.tuner_addr = 0x61,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT | TDA9887_PORT1_ACTIVE,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_VIDEOMATE_DVBT_300] = {
.name = "Compro Videomate DVB-T300",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TD1316,
.radio_type = UNSET,
.tuner_addr = 0x61,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT | TDA9887_PORT1_ACTIVE,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_VIDEOMATE_DVBT_200] = {
.name = "Compro Videomate DVB-T200",
.tuner_type = TUNER_ABSENT,
.audio_clock = 0x00187de7,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
},
[SAA7134_BOARD_RTD_VFG7350] = {
.name = "RTD Embedded Technologies VFG7350",
.audio_clock = 0x00200000,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.empress_addr = 0x21,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE0,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 2,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE3,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO0,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO1,
.vmux = 9,
.amux = LINE2,
}},
.mpeg = SAA7134_MPEG_EMPRESS,
.video_out = CCIR656,
.vid_port_opts = ( SET_T_CODE_POLARITY_NON_INVERTED |
SET_CLOCK_NOT_DELAYED |
SET_CLOCK_INVERTED |
SET_VSYNC_OFF ),
},
[SAA7134_BOARD_RTD_VFG7330] = {
.name = "RTD Embedded Technologies VFG7330",
.audio_clock = 0x00200000,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE0,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 2,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE3,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO0,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO1,
.vmux = 9,
.amux = LINE2,
}},
},
[SAA7134_BOARD_FLYTVPLATINUM_MINI2] = {
.name = "LifeView FlyTV Platinum Mini2",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180] = {
/* Michael Krufky <[email protected]>
* Uses Alps Electric TDHU2, containing NXT2004 ATSC Decoder
* AFAIK, there is no analog demod, thus,
* no support for analog television.
*/
.name = "AVerMedia AVerTVHD MCE A180",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_MONSTERTV_MOBILE] = {
.name = "SKNet MonsterTV Mobile",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE1,
}},
},
[SAA7134_BOARD_PINNACLE_PCTV_110i] = {
.name = "Pinnacle PCTV 40i/50i/110i (saa7133)",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x080200000,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 4,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 0,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_ASUSTeK_P7131_DUAL] = {
.name = "ASUSTeK P7131 Dual",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 1 << 21,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x0000000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
.gpio = 0x0200000,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 0,
.amux = LINE2,
.gpio = 0x0200000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x0200000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_SEDNA_PC_TV_CARDBUS] = {
/* Paul Tom Zalac <[email protected]> */
/* Pavel Mihaylov <[email protected]> */
.name = "Sedna/MuchTV PC TV Cardbus TV/Radio (ITO25 Rev:2B)",
/* Sedna/MuchTV (OEM) Cardbus TV Tuner */
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0xe880c0,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_ASUSTEK_DIGIMATRIX_TV] = {
/* "Cyril Lacoux (Yack)" <[email protected]> */
.name = "ASUS Digimatrix TV",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_FQ1216ME,
.tda9887_conf = TDA9887_PRESENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
},
[SAA7134_BOARD_PHILIPS_TIGER] = {
.name = "Philips Tiger reference design",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_OFF },
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 0x0200000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_MSI_TVATANYWHERE_PLUS] = {
.name = "MSI TV@Anywhere plus",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 1 << 21,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 3,
.amux = LINE2, /* unconfirmed, taken from Philips driver */
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0, /* untested */
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_CINERGY250PCI] = {
/* remote-control does not work. The signal about a
key press comes in via gpio, but the key code
doesn't. Neither does it have an i2c remote control
interface. */
.name = "Terratec Cinergy 250 PCI TV",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x80200000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_SVIDEO, /* NOT tested */
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_FLYDVB_TRIO] = {
/* LifeView LR319 FlyDVB Trio */
/* Peter Missel <[email protected]> */
.name = "LifeView FlyDVB Trio",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x00200000,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV, /* Analog broadcast/cable TV */
.vmux = 1,
.amux = TV,
.gpio = 0x200000, /* GPIO21=High for TV input */
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x000000, /* GPIO21=Low for FM radio antenna */
},
},
[SAA7134_BOARD_AVERMEDIA_777] = {
.name = "AverTV DVB-T 777",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
},
[SAA7134_BOARD_FLYDVBT_LR301] = {
/* LifeView FlyDVB-T */
/* Giampiero Giancipoli <[email protected]> */
.name = "LifeView FlyDVB-T / Genius VideoWonder DVB-T",
.audio_clock = 0x00200000,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_ADS_DUO_CARDBUS_PTV331] = {
.name = "ADS Instant TV Duo Cardbus PTV331",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 0x00600000, /* Bit 21 0=Radio, Bit 22 0=TV */
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x00200000,
}},
},
[SAA7134_BOARD_TEVION_DVBT_220RF] = {
.name = "Tevion/KWorld DVB-T 220RF",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 1 << 21,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_KWORLD_DVBT_210] = {
.name = "KWorld DVB-T 210",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 1 << 21,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_KWORLD_ATSC110] = {
.name = "Kworld ATSC110/115",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TUV1236D,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_AVERMEDIA_A169_B] = {
/* AVerMedia A169 */
/* Rickard Osser <[email protected]> */
/* This card has two saa7134 chips on it,
but only one of them is currently working. */
.name = "AVerMedia A169 B",
.audio_clock = 0x02187de7,
.tuner_type = TUNER_LG_TALN,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x0a60000,
},
[SAA7134_BOARD_AVERMEDIA_A169_B1] = {
/* AVerMedia A169 */
/* Rickard Osser <[email protected]> */
.name = "AVerMedia A169 B1",
.audio_clock = 0x02187de7,
.tuner_type = TUNER_LG_TALN,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0xca60000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 4,
.amux = TV,
.gpio = 0x04a61000,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 9, /* 9 is correct as S-VIDEO1 according to a169.inf! */
.amux = LINE1,
}},
},
[SAA7134_BOARD_MD7134_BRIDGE_2] = {
/* The second saa7134 on this card only serves as DVB-S host bridge */
.name = "Medion 7134 Bridge #2",
.audio_clock = 0x00187de7,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
},
[SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS] = {
.name = "LifeView FlyDVB-T Hybrid Cardbus/MSI TV @nywhere A/D NB",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 0x00600000, /* Bit 21 0=Radio, Bit 22 0=TV */
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x200000, /* GPIO21=High for TV input */
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE_OVER_SVIDEO,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 3,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x000000, /* GPIO21=Low for FM radio antenna */
},
},
[SAA7134_BOARD_FLYVIDEO3000_NTSC] = {
/* "Zac Bowling" <[email protected]> */
.name = "LifeView FlyVIDEO3000 (NTSC)",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_NTSC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0xe000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x8000,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
.gpio = 0x0000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
.gpio = 0x4000,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
.gpio = 0x4000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x4000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x2000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x8000,
},
},
[SAA7134_BOARD_MEDION_MD8800_QUADRO] = {
.name = "Medion Md8800 Quadro",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
},
[SAA7134_BOARD_FLYDVBS_LR300] = {
/* LifeView FlyDVB-s */
/* Igor M. Liplianin <[email protected]> */
.name = "LifeView FlyDVB-S /Acorp TV134DS",
.audio_clock = 0x00200000,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
},
[SAA7134_BOARD_PROTEUS_2309] = {
.name = "Proteus Pro 2309",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
},
[SAA7134_BOARD_AVERMEDIA_A16AR] = {
/* Petr Baudis <[email protected]> */
.name = "AVerMedia TV Hybrid A16AR",
.audio_clock = 0x187de7,
.tuner_type = TUNER_PHILIPS_TD1316, /* untested */
.radio_type = TUNER_TEA5767, /* untested */
.tuner_addr = ADDR_UNSET,
.radio_addr = 0x60,
.tda9887_conf = TDA9887_PRESENT,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
},
},
[SAA7134_BOARD_ASUS_EUROPA2_HYBRID] = {
.name = "Asus Europa2 OEM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FMD1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT| TDA9887_PORT1_ACTIVE | TDA9887_PORT2_ACTIVE,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 4,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
},
},
[SAA7134_BOARD_PINNACLE_PCTV_310i] = {
.name = "Pinnacle PCTV 310i",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_GP0_HIGH_ON },
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 0x000200000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 4,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_AVERMEDIA_STUDIO_507] = {
/* Mikhail Fedotov <[email protected]> */
.name = "Avermedia AVerTV Studio 507",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1256_IH3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x03,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x00,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
.gpio = 0x00,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
.gpio = 0x00,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x00,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x01,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
.gpio = 0x00,
},
},
[SAA7134_BOARD_VIDEOMATE_DVBT_200A] = {
/* Francis Barber <[email protected]> */
.name = "Compro Videomate DVB-T200A",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT | TDA9887_PORT1_ACTIVE,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
}},
},
[SAA7134_BOARD_HAUPPAUGE_HVR1110] = {
/* Thomas Genty <[email protected]> */
/* David Bentham <[email protected]> */
.name = "Hauppauge WinTV-HVR1110 DVB-T/Hybrid",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_GP0_HIGH_ON },
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 0x0200100,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x0000100,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200100,
},
},
[SAA7134_BOARD_HAUPPAUGE_HVR1150] = {
.name = "Hauppauge WinTV-HVR1150 ATSC/QAM-Hybrid",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_ON_BRIDGE },
.mpeg = SAA7134_MPEG_DVB,
.ts_type = SAA7134_MPEG_TS_SERIAL,
.ts_force_val = 1,
.gpiomask = 0x0800100, /* GPIO 21 is an INPUT */
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x0000100,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0800100, /* GPIO 23 HI for FM */
},
},
[SAA7134_BOARD_HAUPPAUGE_HVR1120] = {
.name = "Hauppauge WinTV-HVR1120 DVB-T/Hybrid",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_ON_BRIDGE },
.mpeg = SAA7134_MPEG_DVB,
.ts_type = SAA7134_MPEG_TS_SERIAL,
.gpiomask = 0x0800100, /* GPIO 21 is an INPUT */
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x0000100,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0800100, /* GPIO 23 HI for FM */
},
},
[SAA7134_BOARD_CINERGY_HT_PCMCIA] = {
.name = "Terratec Cinergy HT PCMCIA",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE1,
}},
},
[SAA7134_BOARD_ENCORE_ENLTV] = {
/* Steven Walter <[email protected]>
Juan Pablo Sormani <[email protected]> */
.name = "Encore ENLTV",
.audio_clock = 0x00200000,
.tuner_type = TUNER_TNF_5335MF,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = 3,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 7,
.amux = 4,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = 2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 0,
.amux = 2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
/* .gpio = 0x00300001,*/
.gpio = 0x20000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = 0,
},
},
[SAA7134_BOARD_ENCORE_ENLTV_FM] = {
/* Juan Pablo Sormani <[email protected]> */
.name = "Encore ENLTV-FM",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_FCV1236D,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = 3,
},{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 7,
.amux = 4,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = 2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 0,
.amux = 2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x20000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = 0,
},
},
[SAA7134_BOARD_ENCORE_ENLTV_FM53] = {
.name = "Encore ENLTV-FM v5.3",
.audio_clock = 0x00200000,
.tuner_type = TUNER_TNF_5335MF,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x7000,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = 1,
.gpio = 0x50000,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = 2,
.gpio = 0x2000,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = 2,
.gpio = 0x2000,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.vmux = 1,
.amux = 1,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.gpio = 0xf000,
.amux = 0,
},
},
[SAA7134_BOARD_ENCORE_ENLTV_FM3] = {
.name = "Encore ENLTV-FM 3",
.audio_clock = 0x02187de7,
.tuner_type = TUNER_TENA_TNF_5337,
.radio_type = TUNER_TEA5767,
.tuner_addr = 0x61,
.radio_addr = 0x60,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.vmux = 1,
.amux = LINE1,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
.gpio = 0x43000,
},
},
[SAA7134_BOARD_CINERGY_HT_PCI] = {
.name = "Terratec Cinergy HT PCI",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE1,
}},
},
[SAA7134_BOARD_PHILIPS_TIGER_S] = {
.name = "Philips Tiger - S Reference design",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_GP0_HIGH_OFF },
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 0x0200000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_AVERMEDIA_M102] = {
.name = "Avermedia M102",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 1<<21,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE2,
}},
},
[SAA7134_BOARD_ASUS_P7131_4871] = {
.name = "ASUS P7131 4871",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_GP0_HIGH_OFF },
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 0x0200000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x0200000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
.gpio = 0x0200000,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 0,
.amux = LINE2,
.gpio = 0x0200000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x0200000,
}},
},
[SAA7134_BOARD_ASUSTeK_P7131_HYBRID_LNA] = {
.name = "ASUSTeK P7131 Hybrid",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_GP0_HIGH_OFF },
.gpiomask = 1 << 21,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x0000000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
.gpio = 0x0200000,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 0,
.amux = LINE2,
.gpio = 0x0200000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x0200000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_ASUSTeK_P7131_ANALOG] = {
.name = "ASUSTeK P7131 Analog",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 1 << 21,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x0000000,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 0,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_SABRENT_TV_PCB05] = {
.name = "Sabrent PCMCIA TV-PCB05",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 0,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
},
},
[SAA7134_BOARD_10MOONSTVMASTER3] = {
/* Tony Wan <[email protected]> */
.name = "10MOONS TM300 TV Card",
.audio_clock = 0x00200000,
.tuner_type = TUNER_LG_PAL_NEW_TAPC,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x7000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
.gpio = 0x0000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x2000,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x2000,
}},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE2,
.gpio = 0x3000,
},
},
[SAA7134_BOARD_AVERMEDIA_SUPER_007] = {
.name = "Avermedia Super 007",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_OFF },
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV, /* FIXME: analog tv untested */
.vmux = 1,
.amux = TV,
}},
},
[SAA7134_BOARD_AVERMEDIA_M135A] = {
.name = "Avermedia PCI pure analog (M135A)",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_GP0_HIGH_OFF },
.gpiomask = 0x020200000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x00200000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x01,
},
},
[SAA7134_BOARD_AVERMEDIA_M733A] = {
.name = "Avermedia PCI M733A",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_OFF },
.gpiomask = 0x020200000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x00200000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x01,
},
},
[SAA7134_BOARD_BEHOLD_401] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 401",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FQ1216ME,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
}},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
},
[SAA7134_BOARD_BEHOLD_403] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 403",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FQ1216ME,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
}},
},
[SAA7134_BOARD_BEHOLD_403FM] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 403 FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FQ1216ME,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_405] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 405",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
}},
},
[SAA7134_BOARD_BEHOLD_405FM] = {
/* Sergey <[email protected]> */
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 405 FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
},{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_407] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 407",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0xc0c000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
.gpio = 0xc0c000,
},{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
.gpio = 0xc0c000,
}},
},
[SAA7134_BOARD_BEHOLD_407FM] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 407 FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0xc0c000,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
.gpio = 0xc0c000,
},{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
.gpio = 0xc0c000,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0xc0c000,
},
},
[SAA7134_BOARD_BEHOLD_409] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 409",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
},
[SAA7134_BOARD_BEHOLD_505FM] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 505 FM",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_505RDS_MK5] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 505 RDS",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_FM1216MK5,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.rds_addr = 0x10,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_507_9FM] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 507 FM / BeholdTV 509 FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_507RDS_MK5] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 507 RDS",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216MK5,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.rds_addr = 0x10,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_507RDS_MK3] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 507 RDS",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.rds_addr = 0x10,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_COLUMBUS_TVFM] = {
/* Beholder Intl. Ltd. 2008 */
/* Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV Columbus TV/FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_ALPS_TSBE5_PAL,
.radio_type = TUNER_TEA5767,
.tuner_addr = 0xc2 >> 1,
.radio_addr = 0xc0 >> 1,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x000A8004,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
.gpio = 0x000A8004,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
.gpio = 0x000A8000,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x000A8000,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x000A8000,
},
},
[SAA7134_BOARD_BEHOLD_607FM_MK3] = {
/* Andrey Melnikoff <[email protected]> */
.name = "Beholder BeholdTV 607 FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_609FM_MK3] = {
/* Andrey Melnikoff <[email protected]> */
.name = "Beholder BeholdTV 609 FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_607FM_MK5] = {
/* Andrey Melnikoff <[email protected]> */
.name = "Beholder BeholdTV 607 FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216MK5,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_609FM_MK5] = {
/* Andrey Melnikoff <[email protected]> */
.name = "Beholder BeholdTV 609 FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216MK5,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_607RDS_MK3] = {
/* Andrey Melnikoff <[email protected]> */
.name = "Beholder BeholdTV 607 RDS",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.rds_addr = 0x10,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_609RDS_MK3] = {
/* Andrey Melnikoff <[email protected]> */
.name = "Beholder BeholdTV 609 RDS",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.rds_addr = 0x10,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_607RDS_MK5] = {
/* Andrey Melnikoff <[email protected]> */
.name = "Beholder BeholdTV 607 RDS",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216MK5,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.rds_addr = 0x10,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_609RDS_MK5] = {
/* Andrey Melnikoff <[email protected]> */
.name = "Beholder BeholdTV 609 RDS",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216MK5,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.rds_addr = 0x10,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
},{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
},{
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_BEHOLD_M6] = {
/* Igor Kuznetsov <[email protected]> */
/* Andrey Melnikoff <[email protected]> */
/* Beholder Intl. Ltd. Dmitry Belimov <[email protected]> */
/* Alexey Osipov <[email protected]> */
.name = "Beholder BeholdTV M6",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.empress_addr = 0x20,
.tda9887_conf = TDA9887_PRESENT,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
.mpeg = SAA7134_MPEG_EMPRESS,
.video_out = CCIR656,
.vid_port_opts = (SET_T_CODE_POLARITY_NON_INVERTED |
SET_CLOCK_NOT_DELAYED |
SET_CLOCK_INVERTED |
SET_VSYNC_OFF),
},
[SAA7134_BOARD_BEHOLD_M63] = {
/* Igor Kuznetsov <[email protected]> */
/* Andrey Melnikoff <[email protected]> */
/* Beholder Intl. Ltd. Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV M63",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.empress_addr = 0x20,
.tda9887_conf = TDA9887_PRESENT,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
.mpeg = SAA7134_MPEG_EMPRESS,
.video_out = CCIR656,
.vid_port_opts = (SET_T_CODE_POLARITY_NON_INVERTED |
SET_CLOCK_NOT_DELAYED |
SET_CLOCK_INVERTED |
SET_VSYNC_OFF),
},
[SAA7134_BOARD_BEHOLD_M6_EXTRA] = {
/* Igor Kuznetsov <[email protected]> */
/* Andrey Melnikoff <[email protected]> */
/* Beholder Intl. Ltd. Dmitry Belimov <[email protected]> */
/* Alexey Osipov <[email protected]> */
.name = "Beholder BeholdTV M6 Extra",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216MK5,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.rds_addr = 0x10,
.empress_addr = 0x20,
.tda9887_conf = TDA9887_PRESENT,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
.mpeg = SAA7134_MPEG_EMPRESS,
.video_out = CCIR656,
.vid_port_opts = (SET_T_CODE_POLARITY_NON_INVERTED |
SET_CLOCK_NOT_DELAYED |
SET_CLOCK_INVERTED |
SET_VSYNC_OFF),
},
[SAA7134_BOARD_TWINHAN_DTV_DVB_3056] = {
.name = "Twinhan Hybrid DTV-DVB 3056 PCI",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_GP0_HIGH_OFF },
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 0x0200000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8, /* untested */
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_GENIUS_TVGO_A11MCE] = {
/* Adrian Pardini <[email protected]> */
.name = "Genius TVGO AM11MCE",
.audio_clock = 0x00200000,
.tuner_type = TUNER_TNF_5335MF,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0xf000,
.inputs = {{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE2,
.gpio = 0x0000,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x2000,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x2000,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x1000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE2,
.gpio = 0x6000,
},
},
[SAA7134_BOARD_PHILIPS_SNAKE] = {
.name = "NXP Snake DVB-S reference design",
.audio_clock = 0x00200000,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
},
[SAA7134_BOARD_CREATIX_CTX953] = {
.name = "Medion/Creatix CTX953 Hybrid",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_OFF },
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
},
[SAA7134_BOARD_MSI_TVANYWHERE_AD11] = {
.name = "MSI TV@nywhere A/D v1.1",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_GP0_HIGH_OFF },
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 0x0200000,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_AVERMEDIA_CARDBUS_506] = {
.name = "AVerMedia Cardbus TV/Radio (E506R)",
.audio_clock = 0x187de7,
.tuner_type = TUNER_XC2028,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
},
},
[SAA7134_BOARD_AVERMEDIA_A16D] = {
.name = "AVerMedia Hybrid TV/Radio (A16D)",
.audio_clock = 0x187de7,
.tuner_type = TUNER_XC2028,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 0,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
},
},
[SAA7134_BOARD_AVERMEDIA_M115] = {
.name = "Avermedia M115",
.audio_clock = 0x187de7,
.tuner_type = TUNER_XC2028,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
},
[SAA7134_BOARD_VIDEOMATE_T750] = {
/* John Newbigin <[email protected]> */
.name = "Compro VideoMate T750",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_XC2028,
.radio_type = UNSET,
.tuner_addr = 0x61,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
}
},
[SAA7134_BOARD_AVERMEDIA_A700_PRO] = {
/* Matthias Schwarzott <[email protected]> */
.name = "Avermedia DVB-S Pro A700",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = { {
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE1,
} },
},
[SAA7134_BOARD_AVERMEDIA_A700_HYBRID] = {
/* Matthias Schwarzott <[email protected]> */
.name = "Avermedia DVB-S Hybrid+FM A700",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_XC2028,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 4,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
},
},
[SAA7134_BOARD_BEHOLD_H6] = {
/* Igor Kuznetsov <[email protected]> */
.name = "Beholder BeholdTV H6",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FMD1216MEX_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_ASUSTeK_TIGER_3IN1] = {
.name = "Asus Tiger 3in1",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_GP0_HIGH_OFF },
.gpiomask = 1 << 21,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 0,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_ASUSTeK_PS3_100] = {
.name = "Asus My Cinema PS3-100",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_GP0_HIGH_OFF },
.gpiomask = 1 << 21,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 0,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_REAL_ANGEL_220] = {
.name = "Zogis Real Angel 220",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_TNF_5335MF,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x801a8087,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
.gpio = 0x624000,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
.gpio = 0x624000,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 1,
.amux = LINE1,
.gpio = 0x624000,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x624001,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
},
},
[SAA7134_BOARD_ADS_INSTANT_HDTV_PCI] = {
.name = "ADS Tech Instant HDTV",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TUV1236D,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.mpeg = SAA7134_MPEG_DVB,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 4,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
},
[SAA7134_BOARD_ASUSTeK_TIGER] = {
.name = "Asus Tiger Rev:1.00",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_OFF },
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 0x0200000,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 0,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_KWORLD_PLUS_TV_ANALOG] = {
.name = "Kworld Plus TV Analog Lite PCI",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_YMEC_TVF_5533MF,
.radio_type = TUNER_TEA5767,
.tuner_addr = ADDR_UNSET,
.radio_addr = 0x60,
.gpiomask = 0x80000700,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
.gpio = 0x100,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x200,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x200,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.vmux = 1,
.amux = LINE1,
.gpio = 0x100,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.vmux = 8,
.amux = 2,
},
},
[SAA7134_BOARD_KWORLD_PCI_SBTVD_FULLSEG] = {
.name = "Kworld PCI SBTVD/ISDB-T Full-Seg Hybrid",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.tuner_addr = ADDR_UNSET,
.radio_type = UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x8e054000,
.mpeg = SAA7134_MPEG_DVB,
.ts_type = SAA7134_MPEG_TS_PARALLEL,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
#if 0 /* FIXME */
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x200,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x200,
#endif
} },
#if 0
.radio = {
.type = SAA7134_INPUT_RADIO,
.vmux = 1,
.amux = LINE1,
.gpio = 0x100,
},
#endif
.mute = {
.type = SAA7134_INPUT_MUTE,
.vmux = 0,
.amux = TV,
},
},
[SAA7134_BOARD_AVERMEDIA_GO_007_FM_PLUS] = {
.name = "Avermedia AVerTV GO 007 FM Plus",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x00300003,
/* .gpiomask = 0x8c240003, */
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x01,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE1,
.gpio = 0x02,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x00300001,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
.gpio = 0x01,
},
},
[SAA7134_BOARD_AVERMEDIA_STUDIO_507UA] = {
/* Andy Shevchenko <[email protected]> */
.name = "Avermedia AVerTV Studio 507UA",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3, /* Should be MK5 */
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x03,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x00,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x00,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x00,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
.gpio = 0x01,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
.gpio = 0x00,
},
},
[SAA7134_BOARD_VIDEOMATE_S350] = {
/* Jan D. Louw <[email protected] */
.name = "Compro VideoMate S350/S300",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = { {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8, /* Not tested */
.amux = LINE1
} },
},
[SAA7134_BOARD_BEHOLD_X7] = {
/* Beholder Intl. Ltd. Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV X7",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_XC5000,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 2,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 9,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
},
},
[SAA7134_BOARD_ZOLID_HYBRID_PCI] = {
.name = "Zolid Hybrid TV Tuner PCI",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_OFF },
.mpeg = SAA7134_MPEG_DVB,
.ts_type = SAA7134_MPEG_TS_PARALLEL,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
} },
.radio = { /* untested */
.type = SAA7134_INPUT_RADIO,
.amux = TV,
},
},
[SAA7134_BOARD_ASUS_EUROPA_HYBRID] = {
.name = "Asus Europa Hybrid OEM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TD1316,
.radio_type = UNSET,
.tuner_addr = 0x61,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT | TDA9887_PORT1_ACTIVE,
.mpeg = SAA7134_MPEG_DVB,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 4,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
},
[SAA7134_BOARD_LEADTEK_WINFAST_DTV1000S] = {
.name = "Leadtek Winfast DTV1000S",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.inputs = { {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
} },
},
[SAA7134_BOARD_BEHOLD_505RDS_MK3] = {
/* Beholder Intl. Ltd. 2008 */
/*Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 505 RDS",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_FM1216ME_MK3,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.rds_addr = 0x10,
.tda9887_conf = TDA9887_PRESENT,
.gpiomask = 0x00008000,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE2,
},
},
[SAA7134_BOARD_HAWELL_HW_404M7] = {
/* Hawell HW-404M7 & Hawell HW-808M7 */
/* Bogoslovskiy Viktor <[email protected]> */
.name = "Hawell HW-404M7",
.audio_clock = 0x00200000,
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x389c00,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x01fc00,
} },
},
[SAA7134_BOARD_BEHOLD_H7] = {
/* Beholder Intl. Ltd. Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV H7",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_XC5000,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.ts_type = SAA7134_MPEG_TS_PARALLEL,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 2,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 9,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
},
},
[SAA7134_BOARD_BEHOLD_A7] = {
/* Beholder Intl. Ltd. Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV A7",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_XC5000,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 2,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 9,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
},
},
[SAA7134_BOARD_TECHNOTREND_BUDGET_T3000] = {
.name = "TechoTrend TT-budget T-3000",
.tuner_type = TUNER_PHILIPS_TD1316,
.audio_clock = 0x00187de7,
.radio_type = UNSET,
.tuner_addr = 0x63,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT | TDA9887_PORT1_ACTIVE,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
},
[SAA7134_BOARD_VIDEOMATE_M1F] = {
/* Pavel Osnova <[email protected]> */
.name = "Compro VideoMate Vista M1F",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_LG_PAL_NEW_TAPC,
.radio_type = TUNER_TEA5767,
.tuner_addr = ADDR_UNSET,
.radio_addr = 0x60,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = TV,
},
},
[SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2] = {
/* Timothy Lee <[email protected]> */
.name = "MagicPro ProHDTV Pro2 DMB-TH/Hybrid",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_ON_BRIDGE },
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x02050000,
.mpeg = SAA7134_MPEG_DVB,
.ts_type = SAA7134_MPEG_TS_PARALLEL,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x00050000,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x00050000,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x00050000,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x00050000,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.vmux = 0,
.amux = TV,
.gpio = 0x00050000,
},
},
[SAA7134_BOARD_BEHOLD_501] = {
/* Beholder Intl. Ltd. 2010 */
/* Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 501",
.audio_clock = 0x00200000,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x00008000,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
},
[SAA7134_BOARD_BEHOLD_503FM] = {
/* Beholder Intl. Ltd. 2010 */
/* Dmitry Belimov <[email protected]> */
.name = "Beholder BeholdTV 503 FM",
.audio_clock = 0x00200000,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x00008000,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 1,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
},
[SAA7134_BOARD_SENSORAY811_911] = {
.name = "Sensoray 811/911",
.audio_clock = 0x00200000,
.tuner_type = TUNER_ABSENT,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_COMPOSITE3,
.vmux = 2,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
},
[SAA7134_BOARD_KWORLD_PC150U] = {
.name = "Kworld PC150-U",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.gpiomask = 1 << 21,
.ts_type = SAA7134_MPEG_TS_PARALLEL,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 3,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0000000,
},
},
[SAA7134_BOARD_HAWELL_HW_9004V1] = {
/* Hawell HW-9004V1 */
/* Vadim Frolov <[email protected]> */
.name = "Hawell HW-9004V1",
.audio_clock = 0x00200000,
.tuner_type = UNSET,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x618E700,
.inputs = {{
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE1,
.gpio = 0x6010000,
} },
},
[SAA7134_BOARD_AVERMEDIA_A706] = {
.name = "AverMedia AverTV Satellite Hybrid+FM A706",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda829x_conf = { .lna_cfg = TDA8290_LNA_OFF,
.no_i2c_gate = 1,
.tda18271_std_map = &aver_a706_std_map },
.gpiomask = 1 << 11,
.mpeg = SAA7134_MPEG_DVB,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
}, {
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 4,
.amux = LINE1,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0000800,
},
},
[SAA7134_BOARD_WIS_VOYAGER] = {
.name = "WIS Voyager or compatible",
.audio_clock = 0x00200000,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_GO7007,
.inputs = { {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_TV,
.vmux = 3,
.amux = TV,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 6,
.amux = LINE1,
} },
},
[SAA7134_BOARD_AVERMEDIA_505] = {
/* much like the "studio" version but without radio
* and another tuner ([email protected]) */
.name = "AverMedia AverTV/505",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_FQ1216ME,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.tda9887_conf = TDA9887_PRESENT,
.inputs = {{
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 0,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_COMPOSITE2,
.vmux = 3,
.amux = LINE2,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
} },
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
},
},
[SAA7134_BOARD_LEADTEK_WINFAST_TV2100_FM] = {
.name = "Leadtek Winfast TV2100 FM",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_TNF_5335MF,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 0x0d,
.inputs = {{
.type = SAA7134_INPUT_TV_MONO,
.vmux = 1,
.amux = LINE1,
.gpio = 0x00,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
.gpio = 0x08,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x08,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = LINE1,
.gpio = 0x04,
},
.mute = {
.type = SAA7134_INPUT_MUTE,
.amux = LINE1,
.gpio = 0x08,
},
},
[SAA7134_BOARD_SNAZIO_TVPVR_PRO] = {
.name = "SnaZio* TVPVR PRO",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.gpiomask = 1 << 21,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x0000000,
}, {
.type = SAA7134_INPUT_COMPOSITE1,
.vmux = 3,
.amux = LINE2,
.gpio = 0x0000000,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE2,
.gpio = 0x0000000,
} },
.radio = {
.type = SAA7134_INPUT_RADIO,
.amux = TV,
.gpio = 0x0200000,
},
},
[SAA7134_BOARD_LEADTEK_WINFAST_HDTV200_H] = {
.name = "Leadtek Winfast HDTV200 H",
.audio_clock = 0x00187de7,
.tuner_type = TUNER_PHILIPS_TDA8290,
.radio_type = UNSET,
.tuner_addr = ADDR_UNSET,
.radio_addr = ADDR_UNSET,
.mpeg = SAA7134_MPEG_DVB,
.ts_type = SAA7134_MPEG_TS_PARALLEL,
.gpiomask = 0x00200700,
.inputs = { {
.type = SAA7134_INPUT_TV,
.vmux = 1,
.amux = TV,
.gpio = 0x00000300,
}, {
.type = SAA7134_INPUT_COMPOSITE,
.vmux = 3,
.amux = LINE1,
.gpio = 0x00200300,
}, {
.type = SAA7134_INPUT_SVIDEO,
.vmux = 8,
.amux = LINE1,
.gpio = 0x00200300,
} },
},
};
const unsigned int saa7134_bcount = ARRAY_SIZE(saa7134_boards);
/* ------------------------------------------------------------------ */
/* PCI ids + subsystem IDs */
struct pci_device_id saa7134_pci_tbl[] = {
{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0x2001,
.driver_data = SAA7134_BOARD_PROTEUS_PRO,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0x2001,
.driver_data = SAA7134_BOARD_PROTEUS_PRO,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0x6752,
.driver_data = SAA7134_BOARD_EMPRESS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1131,
.subdevice = 0x4e85,
.driver_data = SAA7134_BOARD_MONSTERTV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x153b,
.subdevice = 0x1142,
.driver_data = SAA7134_BOARD_CINERGY400,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x153b,
.subdevice = 0x1143,
.driver_data = SAA7134_BOARD_CINERGY600,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x153b,
.subdevice = 0x1158,
.driver_data = SAA7134_BOARD_CINERGY600_MK3,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x153b,
.subdevice = 0x1162,
.driver_data = SAA7134_BOARD_CINERGY400_CARDBUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x5169,
.subdevice = 0x0138,
.driver_data = SAA7134_BOARD_FLYVIDEO3000_NTSC,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x5168,
.subdevice = 0x0138,
.driver_data = SAA7134_BOARD_FLYVIDEO3000,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x4e42, /* "Typhoon PCI Capture TV Card" Art.No. 50673 */
.subdevice = 0x0138,
.driver_data = SAA7134_BOARD_FLYVIDEO3000,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x5168,
.subdevice = 0x0138,
.driver_data = SAA7134_BOARD_FLYVIDEO2000,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x4e42, /* Typhoon */
.subdevice = 0x0138, /* LifeView FlyTV Prime30 OEM */
.driver_data = SAA7134_BOARD_FLYVIDEO2000,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5168,
.subdevice = 0x0212, /* minipci, LR212 */
.driver_data = SAA7134_BOARD_FLYTVPLATINUM_MINI,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x14c0,
.subdevice = 0x1212, /* minipci, LR1212 */
.driver_data = SAA7134_BOARD_FLYTVPLATINUM_MINI2,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x4e42,
.subdevice = 0x0212, /* OEM minipci, LR212 */
.driver_data = SAA7134_BOARD_FLYTVPLATINUM_MINI,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5168, /* Animation Technologies (LifeView) */
.subdevice = 0x0214, /* Standard PCI, LR214 Rev E and earlier (SAA7135) */
.driver_data = SAA7134_BOARD_FLYTVPLATINUM_FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5168, /* Animation Technologies (LifeView) */
.subdevice = 0x5214, /* Standard PCI, LR214 Rev F onwards (SAA7131) */
.driver_data = SAA7134_BOARD_FLYTVPLATINUM_FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1489, /* KYE */
.subdevice = 0x0214, /* Genius VideoWonder ProTV */
.driver_data = SAA7134_BOARD_FLYTVPLATINUM_FM, /* is an LR214WF actually */
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x16be,
.subdevice = 0x0003,
.driver_data = SAA7134_BOARD_MD7134,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x16be, /* CTX946 analog TV, HW mpeg, DVB-T */
.subdevice = 0x5000, /* only analog TV and DVB-T for now */
.driver_data = SAA7134_BOARD_MD7134,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1048,
.subdevice = 0x226b,
.driver_data = SAA7134_BOARD_ELSA,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1048,
.subdevice = 0x226a,
.driver_data = SAA7134_BOARD_ELSA_500TV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1048,
.subdevice = 0x226c,
.driver_data = SAA7134_BOARD_ELSA_700TV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = PCI_VENDOR_ID_ASUSTEK,
.subdevice = 0x4842,
.driver_data = SAA7134_BOARD_ASUSTeK_TVFM7134,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = PCI_VENDOR_ID_ASUSTEK,
.subdevice = 0x4845,
.driver_data = SAA7134_BOARD_ASUSTeK_TVFM7135,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = PCI_VENDOR_ID_ASUSTEK,
.subdevice = 0x4830,
.driver_data = SAA7134_BOARD_ASUSTeK_TVFM7134,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = PCI_VENDOR_ID_ASUSTEK,
.subdevice = 0x4843,
.driver_data = SAA7134_BOARD_ASUSTEK_TVFM7133,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = PCI_VENDOR_ID_ASUSTEK,
.subdevice = 0x4840,
.driver_data = SAA7134_BOARD_ASUSTeK_TVFM7134,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0xfe01,
.driver_data = SAA7134_BOARD_TVSTATION_RDS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1894,
.subdevice = 0xfe01,
.driver_data = SAA7134_BOARD_TVSTATION_RDS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1894,
.subdevice = 0xa006,
.driver_data = SAA7134_BOARD_TVSTATION_DVR,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1131,
.subdevice = 0x7133,
.driver_data = SAA7134_BOARD_VA1000POWER,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0x2001,
.driver_data = SAA7134_BOARD_10MOONSTVMASTER,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x185b,
.subdevice = 0xc100,
.driver_data = SAA7134_BOARD_VIDEOMATE_TV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x185b,
.subdevice = 0xc100,
.driver_data = SAA7134_BOARD_VIDEOMATE_TV_GOLD_PLUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = PCI_VENDOR_ID_MATROX,
.subdevice = 0x48d0,
.driver_data = SAA7134_BOARD_CRONOS_PLUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xa70b,
.driver_data = SAA7134_BOARD_MD2819,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xa7a1,
.driver_data = SAA7134_BOARD_AVERMEDIA_A700_PRO,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xa7a2,
.driver_data = SAA7134_BOARD_AVERMEDIA_A700_HYBRID,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0x2115,
.driver_data = SAA7134_BOARD_AVERMEDIA_STUDIO_305,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xa115,
.driver_data = SAA7134_BOARD_AVERMEDIA_STUDIO_505,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0x2108,
.driver_data = SAA7134_BOARD_AVERMEDIA_305,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0x10ff,
.driver_data = SAA7134_BOARD_AVERMEDIA_DVD_EZMAKER,
},{
/* AVerMedia CardBus */
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xd6ee,
.driver_data = SAA7134_BOARD_AVERMEDIA_CARDBUS,
},{
/* AVerMedia CardBus */
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xb7e9,
.driver_data = SAA7134_BOARD_AVERMEDIA_CARDBUS_501,
}, {
/* TransGear 3000TV */
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0x050c,
.driver_data = SAA7134_BOARD_TG3000TV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x11bd,
.subdevice = 0x002b,
.driver_data = SAA7134_BOARD_PINNACLE_PCTV_STEREO,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x11bd,
.subdevice = 0x002d,
.driver_data = SAA7134_BOARD_PINNACLE_300I_DVBT_PAL,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1019,
.subdevice = 0x4cb4,
.driver_data = SAA7134_BOARD_ECS_TVP3XP,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1019,
.subdevice = 0x4cb5,
.driver_data = SAA7134_BOARD_ECS_TVP3XP_4CB5,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1019,
.subdevice = 0x4cb6,
.driver_data = SAA7134_BOARD_ECS_TVP3XP_4CB6,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x12ab,
.subdevice = 0x0800,
.driver_data = SAA7134_BOARD_UPMOST_PURPLE_TV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x153b,
.subdevice = 0x1152,
.driver_data = SAA7134_BOARD_CINERGY200,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x185b,
.subdevice = 0xc100,
.driver_data = SAA7134_BOARD_VIDEOMATE_TV_PVR,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0x9715,
.driver_data = SAA7134_BOARD_AVERMEDIA_STUDIO_307,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xa70a,
.driver_data = SAA7134_BOARD_AVERMEDIA_307,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x185b,
.subdevice = 0xc200,
.driver_data = SAA7134_BOARD_VIDEOMATE_GOLD_PLUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1540,
.subdevice = 0x9524,
.driver_data = SAA7134_BOARD_PROVIDEO_PV952,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5168,
.subdevice = 0x0502, /* Cardbus version */
.driver_data = SAA7134_BOARD_FLYDVBT_DUO_CARDBUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5168,
.subdevice = 0x0306, /* PCI version */
.driver_data = SAA7134_BOARD_FLYDVBTDUO,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xf31f,
.driver_data = SAA7134_BOARD_AVERMEDIA_GO_007_FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xf11d,
.driver_data = SAA7134_BOARD_AVERMEDIA_M135A,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0x4155,
.driver_data = SAA7134_BOARD_AVERMEDIA_M733A,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0x4255,
.driver_data = SAA7134_BOARD_AVERMEDIA_M733A,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0x2004,
.driver_data = SAA7134_BOARD_PHILIPS_TOUGH,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1421,
.subdevice = 0x0350, /* PCI version */
.driver_data = SAA7134_BOARD_ADS_INSTANT_TV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1421,
.subdevice = 0x0351, /* PCI version, new revision */
.driver_data = SAA7134_BOARD_ADS_INSTANT_TV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1421,
.subdevice = 0x0370, /* cardbus version */
.driver_data = SAA7134_BOARD_ADS_INSTANT_TV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1421,
.subdevice = 0x1370, /* cardbus version */
.driver_data = SAA7134_BOARD_ADS_INSTANT_TV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x4e42, /* Typhoon */
.subdevice = 0x0502, /* LifeView LR502 OEM */
.driver_data = SAA7134_BOARD_FLYDVBT_DUO_CARDBUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1043,
.subdevice = 0x0210, /* mini pci NTSC version */
.driver_data = SAA7134_BOARD_FLYTV_DIGIMATRIX,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1043,
.subdevice = 0x0210, /* mini pci PAL/SECAM version */
.driver_data = SAA7134_BOARD_ASUSTEK_DIGIMATRIX_TV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0000, /* It shouldn't break anything, since subdevice id seems unique */
.subdevice = 0x4091,
.driver_data = SAA7134_BOARD_BEHOLD_409FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5456, /* GoTView */
.subdevice = 0x7135,
.driver_data = SAA7134_BOARD_GOTVIEW_7135,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0x2004,
.driver_data = SAA7134_BOARD_PHILIPS_EUROPA,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x185b,
.subdevice = 0xc900,
.driver_data = SAA7134_BOARD_VIDEOMATE_DVBT_300,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x185b,
.subdevice = 0xc901,
.driver_data = SAA7134_BOARD_VIDEOMATE_DVBT_200,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1435,
.subdevice = 0x7350,
.driver_data = SAA7134_BOARD_RTD_VFG7350,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1435,
.subdevice = 0x7330,
.driver_data = SAA7134_BOARD_RTD_VFG7330,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461,
.subdevice = 0x1044,
.driver_data = SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1131,
.subdevice = 0x4ee9,
.driver_data = SAA7134_BOARD_MONSTERTV_MOBILE,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x11bd,
.subdevice = 0x002e,
.driver_data = SAA7134_BOARD_PINNACLE_PCTV_110i,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1043,
.subdevice = 0x4862,
.driver_data = SAA7134_BOARD_ASUSTeK_P7131_DUAL,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0x2018,
.driver_data = SAA7134_BOARD_PHILIPS_TIGER,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1462,
.subdevice = 0x6231, /* tda8275a, ks003 IR */
.driver_data = SAA7134_BOARD_MSI_TVATANYWHERE_PLUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1462,
.subdevice = 0x8624, /* tda8275, ks003 IR */
.driver_data = SAA7134_BOARD_MSI_TVATANYWHERE_PLUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x153b,
.subdevice = 0x1160,
.driver_data = SAA7134_BOARD_CINERGY250PCI,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133, /* SAA 7131E */
.subvendor = 0x5168,
.subdevice = 0x0319,
.driver_data = SAA7134_BOARD_FLYDVB_TRIO,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1461,
.subdevice = 0x2c05,
.driver_data = SAA7134_BOARD_AVERMEDIA_777,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x5168,
.subdevice = 0x0301,
.driver_data = SAA7134_BOARD_FLYDVBT_LR301,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0331,
.subdevice = 0x1421,
.driver_data = SAA7134_BOARD_ADS_DUO_CARDBUS_PTV331,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x17de,
.subdevice = 0x7201,
.driver_data = SAA7134_BOARD_TEVION_DVBT_220RF,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x17de,
.subdevice = 0x7250,
.driver_data = SAA7134_BOARD_KWORLD_DVBT_210,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133, /* SAA7135HL */
.subvendor = 0x17de,
.subdevice = 0x7350,
.driver_data = SAA7134_BOARD_KWORLD_ATSC110,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133, /* SAA7135HL */
.subvendor = 0x17de,
.subdevice = 0x7352,
.driver_data = SAA7134_BOARD_KWORLD_ATSC110, /* ATSC 115 */
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133, /* SAA7135HL */
.subvendor = 0x17de,
.subdevice = 0xa134,
.driver_data = SAA7134_BOARD_KWORLD_PC150U,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1461,
.subdevice = 0x7360,
.driver_data = SAA7134_BOARD_AVERMEDIA_A169_B,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1461,
.subdevice = 0x6360,
.driver_data = SAA7134_BOARD_AVERMEDIA_A169_B1,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x16be,
.subdevice = 0x0005,
.driver_data = SAA7134_BOARD_MD7134_BRIDGE_2,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x5168,
.subdevice = 0x0300,
.driver_data = SAA7134_BOARD_FLYDVBS_LR300,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x4e42,
.subdevice = 0x0300,/* LR300 */
.driver_data = SAA7134_BOARD_FLYDVBS_LR300,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1489,
.subdevice = 0x0301,
.driver_data = SAA7134_BOARD_FLYDVBT_LR301,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5168, /* Animation Technologies (LifeView) */
.subdevice = 0x0304,
.driver_data = SAA7134_BOARD_FLYTVPLATINUM_FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5168,
.subdevice = 0x3306,
.driver_data = SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5168,
.subdevice = 0x3502, /* what's the difference to 0x3306 ?*/
.driver_data = SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5168,
.subdevice = 0x3307, /* FlyDVB-T Hybrid Mini PCI */
.driver_data = SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x16be,
.subdevice = 0x0007,
.driver_data = SAA7134_BOARD_MEDION_MD8800_QUADRO,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x16be,
.subdevice = 0x0008,
.driver_data = SAA7134_BOARD_MEDION_MD8800_QUADRO,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x16be,
.subdevice = 0x000d, /* triple CTX948_V1.1.1 */
.driver_data = SAA7134_BOARD_MEDION_MD8800_QUADRO,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461,
.subdevice = 0x2c05,
.driver_data = SAA7134_BOARD_AVERMEDIA_777,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1489,
.subdevice = 0x0502, /* Cardbus version */
.driver_data = SAA7134_BOARD_FLYDVBT_DUO_CARDBUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x0919, /* Philips Proteus PRO 2309 */
.subdevice = 0x2003,
.driver_data = SAA7134_BOARD_PROTEUS_2309,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1461,
.subdevice = 0x2c00,
.driver_data = SAA7134_BOARD_AVERMEDIA_A16AR,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1043,
.subdevice = 0x4860,
.driver_data = SAA7134_BOARD_ASUS_EUROPA2_HYBRID,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x11bd,
.subdevice = 0x002f,
.driver_data = SAA7134_BOARD_PINNACLE_PCTV_310i,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0x9715,
.driver_data = SAA7134_BOARD_AVERMEDIA_STUDIO_507,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xa11b,
.driver_data = SAA7134_BOARD_AVERMEDIA_STUDIO_507UA,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1043,
.subdevice = 0x4876,
.driver_data = SAA7134_BOARD_ASUSTeK_P7131_HYBRID_LNA,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0070,
.subdevice = 0x6700,
.driver_data = SAA7134_BOARD_HAUPPAUGE_HVR1110,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0070,
.subdevice = 0x6701,
.driver_data = SAA7134_BOARD_HAUPPAUGE_HVR1110,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0070,
.subdevice = 0x6702,
.driver_data = SAA7134_BOARD_HAUPPAUGE_HVR1110,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0070,
.subdevice = 0x6703,
.driver_data = SAA7134_BOARD_HAUPPAUGE_HVR1110,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0070,
.subdevice = 0x6704,
.driver_data = SAA7134_BOARD_HAUPPAUGE_HVR1110,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0070,
.subdevice = 0x6705,
.driver_data = SAA7134_BOARD_HAUPPAUGE_HVR1110,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0070,
.subdevice = 0x6706,
.driver_data = SAA7134_BOARD_HAUPPAUGE_HVR1150,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0070,
.subdevice = 0x6707,
.driver_data = SAA7134_BOARD_HAUPPAUGE_HVR1120,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0070,
.subdevice = 0x6708,
.driver_data = SAA7134_BOARD_HAUPPAUGE_HVR1150,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0070,
.subdevice = 0x6709,
.driver_data = SAA7134_BOARD_HAUPPAUGE_HVR1120,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0070,
.subdevice = 0x670a,
.driver_data = SAA7134_BOARD_HAUPPAUGE_HVR1120,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x153b,
.subdevice = 0x1172,
.driver_data = SAA7134_BOARD_CINERGY_HT_PCMCIA,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0x2342,
.driver_data = SAA7134_BOARD_ENCORE_ENLTV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1131,
.subdevice = 0x2341,
.driver_data = SAA7134_BOARD_ENCORE_ENLTV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x3016,
.subdevice = 0x2344,
.driver_data = SAA7134_BOARD_ENCORE_ENLTV,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1131,
.subdevice = 0x230f,
.driver_data = SAA7134_BOARD_ENCORE_ENLTV_FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1a7f,
.subdevice = 0x2008,
.driver_data = SAA7134_BOARD_ENCORE_ENLTV_FM53,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1a7f,
.subdevice = 0x2108,
.driver_data = SAA7134_BOARD_ENCORE_ENLTV_FM3,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x153b,
.subdevice = 0x1175,
.driver_data = SAA7134_BOARD_CINERGY_HT_PCI,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xf31e,
.driver_data = SAA7134_BOARD_AVERMEDIA_M102,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x4E42, /* MSI */
.subdevice = 0x0306, /* TV@nywhere DUO */
.driver_data = SAA7134_BOARD_FLYDVBTDUO,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1043,
.subdevice = 0x4871,
.driver_data = SAA7134_BOARD_ASUS_P7131_4871,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1043,
.subdevice = 0x4857, /* REV:1.00 */
.driver_data = SAA7134_BOARD_ASUSTeK_TIGER,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x0919, /* SinoVideo PCI 2309 Proteus (7134) */
.subdevice = 0x2003, /* OEM cardbus */
.driver_data = SAA7134_BOARD_SABRENT_TV_PCB05,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0x2304,
.driver_data = SAA7134_BOARD_10MOONSTVMASTER3,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xf01d, /* AVerTV DVB-T Super 007 */
.driver_data = SAA7134_BOARD_AVERMEDIA_SUPER_007,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x0000,
.subdevice = 0x4016,
.driver_data = SAA7134_BOARD_BEHOLD_401,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x0000,
.subdevice = 0x4036,
.driver_data = SAA7134_BOARD_BEHOLD_403,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x0000,
.subdevice = 0x4037,
.driver_data = SAA7134_BOARD_BEHOLD_403FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x0000,
.subdevice = 0x4050,
.driver_data = SAA7134_BOARD_BEHOLD_405,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x0000,
.subdevice = 0x4051,
.driver_data = SAA7134_BOARD_BEHOLD_405FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x0000,
.subdevice = 0x4070,
.driver_data = SAA7134_BOARD_BEHOLD_407,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x0000,
.subdevice = 0x4071,
.driver_data = SAA7134_BOARD_BEHOLD_407FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0000,
.subdevice = 0x4090,
.driver_data = SAA7134_BOARD_BEHOLD_409,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x0000,
.subdevice = 0x505B,
.driver_data = SAA7134_BOARD_BEHOLD_505RDS_MK5,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x0000,
.subdevice = 0x5051,
.driver_data = SAA7134_BOARD_BEHOLD_505RDS_MK3,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x5ace,
.subdevice = 0x5050,
.driver_data = SAA7134_BOARD_BEHOLD_505FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0000,
.subdevice = 0x5071,
.driver_data = SAA7134_BOARD_BEHOLD_507RDS_MK3,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0000,
.subdevice = 0x507B,
.driver_data = SAA7134_BOARD_BEHOLD_507RDS_MK5,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x5ace,
.subdevice = 0x5070,
.driver_data = SAA7134_BOARD_BEHOLD_507_9FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace,
.subdevice = 0x5090,
.driver_data = SAA7134_BOARD_BEHOLD_507_9FM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x0000,
.subdevice = 0x5201,
.driver_data = SAA7134_BOARD_BEHOLD_COLUMBUS_TVFM,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x5ace,
.subdevice = 0x6070,
.driver_data = SAA7134_BOARD_BEHOLD_607FM_MK3,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x5ace,
.subdevice = 0x6071,
.driver_data = SAA7134_BOARD_BEHOLD_607FM_MK5,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x5ace,
.subdevice = 0x6072,
.driver_data = SAA7134_BOARD_BEHOLD_607RDS_MK3,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x5ace,
.subdevice = 0x6073,
.driver_data = SAA7134_BOARD_BEHOLD_607RDS_MK5,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace,
.subdevice = 0x6090,
.driver_data = SAA7134_BOARD_BEHOLD_609FM_MK3,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace,
.subdevice = 0x6091,
.driver_data = SAA7134_BOARD_BEHOLD_609FM_MK5,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace,
.subdevice = 0x6092,
.driver_data = SAA7134_BOARD_BEHOLD_609RDS_MK3,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace,
.subdevice = 0x6093,
.driver_data = SAA7134_BOARD_BEHOLD_609RDS_MK5,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace,
.subdevice = 0x6190,
.driver_data = SAA7134_BOARD_BEHOLD_M6,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace,
.subdevice = 0x6193,
.driver_data = SAA7134_BOARD_BEHOLD_M6_EXTRA,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace,
.subdevice = 0x6191,
.driver_data = SAA7134_BOARD_BEHOLD_M63,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x4e42,
.subdevice = 0x3502,
.driver_data = SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1822, /*Twinhan Technology Co. Ltd*/
.subdevice = 0x0022,
.driver_data = SAA7134_BOARD_TWINHAN_DTV_DVB_3056,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x16be,
.subdevice = 0x0010, /* Medion version CTX953_V.1.4.3 */
.driver_data = SAA7134_BOARD_CREATIX_CTX953,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1462, /* MSI */
.subdevice = 0x8625, /* TV@nywhere A/D v1.1 */
.driver_data = SAA7134_BOARD_MSI_TVANYWHERE_AD11,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xf436,
.driver_data = SAA7134_BOARD_AVERMEDIA_CARDBUS_506,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xf936,
.driver_data = SAA7134_BOARD_AVERMEDIA_A16D,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xa836,
.driver_data = SAA7134_BOARD_AVERMEDIA_M115,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x185b,
.subdevice = 0xc900,
.driver_data = SAA7134_BOARD_VIDEOMATE_T750,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133, /* SAA7135HL */
.subvendor = 0x1421,
.subdevice = 0x0380,
.driver_data = SAA7134_BOARD_ADS_INSTANT_HDTV_PCI,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5169,
.subdevice = 0x1502,
.driver_data = SAA7134_BOARD_FLYTVPLATINUM_MINI,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace,
.subdevice = 0x6290,
.driver_data = SAA7134_BOARD_BEHOLD_H6,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xf636,
.driver_data = SAA7134_BOARD_AVERMEDIA_M103,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xf736,
.driver_data = SAA7134_BOARD_AVERMEDIA_M103,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1043,
.subdevice = 0x4878, /* REV:1.02G */
.driver_data = SAA7134_BOARD_ASUSTeK_TIGER_3IN1,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1043,
.subdevice = 0x48cd,
.driver_data = SAA7134_BOARD_ASUSTeK_PS3_100,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x17de,
.subdevice = 0x7128,
.driver_data = SAA7134_BOARD_KWORLD_PLUS_TV_ANALOG,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x17de,
.subdevice = 0xb136,
.driver_data = SAA7134_BOARD_KWORLD_PCI_SBTVD_FULLSEG,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xf31d,
.driver_data = SAA7134_BOARD_AVERMEDIA_GO_007_FM_PLUS,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x185b,
.subdevice = 0xc900,
.driver_data = SAA7134_BOARD_VIDEOMATE_S350,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace, /* Beholder Intl. Ltd. */
.subdevice = 0x7595,
.driver_data = SAA7134_BOARD_BEHOLD_X7,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x19d1, /* RoverMedia */
.subdevice = 0x0138, /* LifeView FlyTV Prime30 OEM */
.driver_data = SAA7134_BOARD_ROVERMEDIA_LINK_PRO_FM,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0x2004,
.driver_data = SAA7134_BOARD_ZOLID_HYBRID_PCI,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x1043,
.subdevice = 0x4847,
.driver_data = SAA7134_BOARD_ASUS_EUROPA_HYBRID,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x107d,
.subdevice = 0x6655,
.driver_data = SAA7134_BOARD_LEADTEK_WINFAST_DTV1000S,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x13c2,
.subdevice = 0x2804,
.driver_data = SAA7134_BOARD_TECHNOTREND_BUDGET_T3000,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace, /* Beholder Intl. Ltd. */
.subdevice = 0x7190,
.driver_data = SAA7134_BOARD_BEHOLD_H7,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace, /* Beholder Intl. Ltd. */
.subdevice = 0x7090,
.driver_data = SAA7134_BOARD_BEHOLD_A7,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7135,
.subvendor = 0x185b,
.subdevice = 0xc900,
.driver_data = SAA7134_BOARD_VIDEOMATE_M1F,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5ace,
.subdevice = 0x5030,
.driver_data = SAA7134_BOARD_BEHOLD_503FM,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x5ace,
.subdevice = 0x5010,
.driver_data = SAA7134_BOARD_BEHOLD_501,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = 0x17de,
.subdevice = 0xd136,
.driver_data = SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x6000,
.subdevice = 0x0811,
.driver_data = SAA7134_BOARD_SENSORAY811_911,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x6000,
.subdevice = 0x0911,
.driver_data = SAA7134_BOARD_SENSORAY811_911,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0x2055, /* AverTV Satellite Hybrid+FM A706 */
.driver_data = SAA7134_BOARD_AVERMEDIA_A706,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1905, /* WIS */
.subdevice = 0x7007,
.driver_data = SAA7134_BOARD_WIS_VOYAGER,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x1461, /* Avermedia Technologies Inc */
.subdevice = 0xa10a,
.driver_data = SAA7134_BOARD_AVERMEDIA_505,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = 0x107d,
.subdevice = 0x6f3a,
.driver_data = SAA7134_BOARD_LEADTEK_WINFAST_TV2100_FM,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x1779, /* V One Multimedia PTE Ltd */
.subdevice = 0x13cf,
.driver_data = SAA7134_BOARD_SNAZIO_TVPVR_PRO,
}, {
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x107d,
.subdevice = 0x6f2e,
.driver_data = SAA7134_BOARD_LEADTEK_WINFAST_HDTV200_H,
}, {
/* --- boards without eeprom + subsystem ID --- */
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0,
.driver_data = SAA7134_BOARD_NOAUTO,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = PCI_VENDOR_ID_PHILIPS,
.subdevice = 0,
.driver_data = SAA7134_BOARD_NOAUTO,
},{
/* --- default catch --- */
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7130,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.driver_data = SAA7134_BOARD_UNKNOWN,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.driver_data = SAA7134_BOARD_UNKNOWN,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.driver_data = SAA7134_BOARD_UNKNOWN,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7135,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.driver_data = SAA7134_BOARD_UNKNOWN,
},{
/* --- end of list --- */
}
};
MODULE_DEVICE_TABLE(pci, saa7134_pci_tbl);
/* ----------------------------------------------------------- */
/* flyvideo tweaks */
static void board_flyvideo(struct saa7134_dev *dev)
{
pr_warn("%s: there are different flyvideo cards with different tuners\n"
"%s: out there, you might have to use the tuner=<nr> insmod\n"
"%s: option to override the default value.\n",
dev->name, dev->name, dev->name);
}
static int saa7134_xc2028_callback(struct saa7134_dev *dev,
int command, int arg)
{
switch (command) {
case XC2028_TUNER_RESET:
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x00008000, 0x00000000);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x00008000, 0x00008000);
switch (dev->board) {
case SAA7134_BOARD_AVERMEDIA_CARDBUS_506:
case SAA7134_BOARD_AVERMEDIA_M103:
saa7134_set_gpio(dev, 23, 0);
msleep(10);
saa7134_set_gpio(dev, 23, 1);
break;
case SAA7134_BOARD_AVERMEDIA_A16D:
saa7134_set_gpio(dev, 21, 0);
msleep(10);
saa7134_set_gpio(dev, 21, 1);
break;
case SAA7134_BOARD_AVERMEDIA_A700_HYBRID:
saa7134_set_gpio(dev, 18, 0);
msleep(10);
saa7134_set_gpio(dev, 18, 1);
break;
case SAA7134_BOARD_VIDEOMATE_T750:
saa7134_set_gpio(dev, 20, 0);
msleep(10);
saa7134_set_gpio(dev, 20, 1);
break;
}
return 0;
}
return -EINVAL;
}
static int saa7134_xc5000_callback(struct saa7134_dev *dev,
int command, int arg)
{
switch (dev->board) {
case SAA7134_BOARD_BEHOLD_X7:
case SAA7134_BOARD_BEHOLD_H7:
case SAA7134_BOARD_BEHOLD_A7:
if (command == XC5000_TUNER_RESET) {
/* Down and UP pheripherial RESET pin for reset all chips */
saa_writeb(SAA7134_SPECIAL_MODE, 0x00);
msleep(10);
saa_writeb(SAA7134_SPECIAL_MODE, 0x01);
msleep(10);
}
break;
default:
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x06e20000, 0x06e20000);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x06a20000, 0x06a20000);
saa_andorl(SAA7133_ANALOG_IO_SELECT >> 2, 0x02, 0x02);
saa_andorl(SAA7134_ANALOG_IN_CTRL1 >> 2, 0x81, 0x81);
saa_andorl(SAA7134_AUDIO_CLOCK0 >> 2, 0x03187de7, 0x03187de7);
saa_andorl(SAA7134_AUDIO_PLL_CTRL >> 2, 0x03, 0x03);
saa_andorl(SAA7134_AUDIO_CLOCKS_PER_FIELD0 >> 2,
0x0001e000, 0x0001e000);
break;
}
return 0;
}
static int saa7134_tda8290_827x_callback(struct saa7134_dev *dev,
int command, int arg)
{
u8 sync_control;
switch (command) {
case 0: /* switch LNA gain through GPIO 22*/
saa7134_set_gpio(dev, 22, arg) ;
break;
case 1: /* vsync output at GPIO22. 50 / 60Hz */
saa_andorb(SAA7134_VIDEO_PORT_CTRL3, 0x80, 0x80);
saa_andorb(SAA7134_VIDEO_PORT_CTRL6, 0x0f, 0x03);
if (arg == 1)
sync_control = 11;
else
sync_control = 17;
saa_writeb(SAA7134_VGATE_START, sync_control);
saa_writeb(SAA7134_VGATE_STOP, sync_control + 1);
saa_andorb(SAA7134_MISC_VGATE_MSB, 0x03, 0x00);
break;
default:
return -EINVAL;
}
return 0;
}
static inline int saa7134_tda18271_hvr11x0_toggle_agc(struct saa7134_dev *dev,
enum tda18271_mode mode)
{
/* toggle AGC switch through GPIO 26 */
switch (mode) {
case TDA18271_ANALOG:
saa7134_set_gpio(dev, 26, 0);
break;
case TDA18271_DIGITAL:
saa7134_set_gpio(dev, 26, 1);
break;
default:
return -EINVAL;
}
return 0;
}
static inline int saa7134_kworld_sbtvd_toggle_agc(struct saa7134_dev *dev,
enum tda18271_mode mode)
{
/* toggle AGC switch through GPIO 27 */
switch (mode) {
case TDA18271_ANALOG:
saa_writel(SAA7134_GPIO_GPMODE0 >> 2, 0x4000);
saa_writel(SAA7134_GPIO_GPSTATUS0 >> 2, 0x4000);
msleep(20);
break;
case TDA18271_DIGITAL:
saa_writel(SAA7134_GPIO_GPMODE0 >> 2, 0x14000);
saa_writel(SAA7134_GPIO_GPSTATUS0 >> 2, 0x14000);
msleep(20);
saa_writel(SAA7134_GPIO_GPMODE0 >> 2, 0x54000);
saa_writel(SAA7134_GPIO_GPSTATUS0 >> 2, 0x54000);
msleep(30);
break;
default:
return -EINVAL;
}
return 0;
}
static int saa7134_kworld_pc150u_toggle_agc(struct saa7134_dev *dev,
enum tda18271_mode mode)
{
switch (mode) {
case TDA18271_ANALOG:
saa7134_set_gpio(dev, 18, 0);
break;
case TDA18271_DIGITAL:
saa7134_set_gpio(dev, 18, 1);
msleep(30);
break;
default:
return -EINVAL;
}
return 0;
}
static int saa7134_leadtek_hdtv200h_toggle_agc(struct saa7134_dev *dev,
enum tda18271_mode mode)
{
switch (mode) {
case TDA18271_ANALOG:
saa7134_set_gpio(dev, 10, 0);
break;
case TDA18271_DIGITAL:
saa7134_set_gpio(dev, 10, 1);
break;
default:
return -EINVAL;
}
return 0;
}
static int saa7134_tda8290_18271_callback(struct saa7134_dev *dev,
int command, int arg)
{
int ret = 0;
switch (command) {
case TDA18271_CALLBACK_CMD_AGC_ENABLE: /* 0 */
switch (dev->board) {
case SAA7134_BOARD_HAUPPAUGE_HVR1150:
case SAA7134_BOARD_HAUPPAUGE_HVR1120:
case SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2:
ret = saa7134_tda18271_hvr11x0_toggle_agc(dev, arg);
break;
case SAA7134_BOARD_KWORLD_PCI_SBTVD_FULLSEG:
ret = saa7134_kworld_sbtvd_toggle_agc(dev, arg);
break;
case SAA7134_BOARD_KWORLD_PC150U:
ret = saa7134_kworld_pc150u_toggle_agc(dev, arg);
break;
case SAA7134_BOARD_LEADTEK_WINFAST_HDTV200_H:
ret = saa7134_leadtek_hdtv200h_toggle_agc(dev, arg);
break;
default:
break;
}
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int saa7134_tda8290_callback(struct saa7134_dev *dev,
int command, int arg)
{
int ret;
switch (dev->board) {
case SAA7134_BOARD_HAUPPAUGE_HVR1150:
case SAA7134_BOARD_HAUPPAUGE_HVR1120:
case SAA7134_BOARD_AVERMEDIA_M733A:
case SAA7134_BOARD_KWORLD_PCI_SBTVD_FULLSEG:
case SAA7134_BOARD_KWORLD_PC150U:
case SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2:
case SAA7134_BOARD_LEADTEK_WINFAST_HDTV200_H:
/* tda8290 + tda18271 */
ret = saa7134_tda8290_18271_callback(dev, command, arg);
break;
default:
/* tda8290 + tda827x */
ret = saa7134_tda8290_827x_callback(dev, command, arg);
break;
}
return ret;
}
int saa7134_tuner_callback(void *priv, int component, int command, int arg)
{
struct saa7134_dev *dev = priv;
if (dev != NULL) {
switch (dev->tuner_type) {
case TUNER_PHILIPS_TDA8290:
return saa7134_tda8290_callback(dev, command, arg);
case TUNER_XC2028:
return saa7134_xc2028_callback(dev, command, arg);
case TUNER_XC5000:
return saa7134_xc5000_callback(dev, command, arg);
}
} else {
pr_err("saa7134: Error - device struct undefined.\n");
return -EINVAL;
}
return -EINVAL;
}
EXPORT_SYMBOL(saa7134_tuner_callback);
/* ----------------------------------------------------------- */
static void hauppauge_eeprom(struct saa7134_dev *dev, u8 *eeprom_data)
{
struct tveeprom tv;
tveeprom_hauppauge_analog(&tv, eeprom_data);
/* Make sure we support the board model */
switch (tv.model) {
case 67019: /* WinTV-HVR1110 (Retail, IR Blaster, hybrid, FM, SVid/Comp, 3.5mm audio in) */
case 67109: /* WinTV-HVR1000 (Retail, IR Receive, analog, no FM, SVid/Comp, 3.5mm audio in) */
case 67201: /* WinTV-HVR1150 (Retail, IR Receive, hybrid, FM, SVid/Comp, 3.5mm audio in) */
case 67301: /* WinTV-HVR1000 (Retail, IR Receive, analog, no FM, SVid/Comp, 3.5mm audio in) */
case 67209: /* WinTV-HVR1110 (Retail, IR Receive, hybrid, FM, SVid/Comp, 3.5mm audio in) */
case 67559: /* WinTV-HVR1110 (OEM, no IR, hybrid, FM, SVid/Comp, RCA aud) */
case 67569: /* WinTV-HVR1110 (OEM, no IR, hybrid, FM) */
case 67579: /* WinTV-HVR1110 (OEM, no IR, hybrid, no FM) */
case 67589: /* WinTV-HVR1110 (OEM, no IR, hybrid, no FM, SVid/Comp, RCA aud) */
case 67599: /* WinTV-HVR1110 (OEM, no IR, hybrid, no FM, SVid/Comp, RCA aud) */
case 67651: /* WinTV-HVR1150 (OEM, no IR, hybrid, FM, SVid/Comp, RCA aud) */
case 67659: /* WinTV-HVR1110 (OEM, no IR, hybrid, FM, SVid/Comp, RCA aud) */
break;
default:
pr_warn("%s: warning: unknown hauppauge model #%d\n",
dev->name, tv.model);
break;
}
pr_info("%s: hauppauge eeprom: model=%d\n",
dev->name, tv.model);
}
/* ----------------------------------------------------------- */
int saa7134_board_init1(struct saa7134_dev *dev)
{
/* Always print gpio, often manufacturers encode tuner type and other info. */
saa_writel(SAA7134_GPIO_GPMODE0 >> 2, 0);
dev->gpio_value = saa_readl(SAA7134_GPIO_GPSTATUS0 >> 2);
pr_info("%s: board init: gpio is %x\n", dev->name, dev->gpio_value);
switch (dev->board) {
case SAA7134_BOARD_FLYVIDEO2000:
case SAA7134_BOARD_FLYVIDEO3000:
case SAA7134_BOARD_FLYVIDEO3000_NTSC:
dev->has_remote = SAA7134_REMOTE_GPIO;
board_flyvideo(dev);
break;
case SAA7134_BOARD_FLYTVPLATINUM_MINI2:
case SAA7134_BOARD_FLYTVPLATINUM_FM:
case SAA7134_BOARD_CINERGY400:
case SAA7134_BOARD_CINERGY600:
case SAA7134_BOARD_CINERGY600_MK3:
case SAA7134_BOARD_ECS_TVP3XP:
case SAA7134_BOARD_ECS_TVP3XP_4CB5:
case SAA7134_BOARD_ECS_TVP3XP_4CB6:
case SAA7134_BOARD_MD2819:
case SAA7134_BOARD_KWORLD_VSTREAM_XPERT:
case SAA7134_BOARD_KWORLD_XPERT:
case SAA7134_BOARD_AVERMEDIA_STUDIO_305:
case SAA7134_BOARD_AVERMEDIA_305:
case SAA7134_BOARD_AVERMEDIA_STUDIO_505:
case SAA7134_BOARD_AVERMEDIA_505:
case SAA7134_BOARD_AVERMEDIA_STUDIO_307:
case SAA7134_BOARD_AVERMEDIA_307:
case SAA7134_BOARD_AVERMEDIA_STUDIO_507:
case SAA7134_BOARD_AVERMEDIA_GO_007_FM:
case SAA7134_BOARD_AVERMEDIA_777:
case SAA7134_BOARD_AVERMEDIA_M135A:
/* case SAA7134_BOARD_SABRENT_SBTTVFM: */ /* not finished yet */
case SAA7134_BOARD_VIDEOMATE_TV_PVR:
case SAA7134_BOARD_VIDEOMATE_GOLD_PLUS:
case SAA7134_BOARD_VIDEOMATE_TV_GOLD_PLUSII:
case SAA7134_BOARD_VIDEOMATE_M1F:
case SAA7134_BOARD_VIDEOMATE_DVBT_300:
case SAA7134_BOARD_VIDEOMATE_DVBT_200:
case SAA7134_BOARD_VIDEOMATE_DVBT_200A:
case SAA7134_BOARD_MANLI_MTV001:
case SAA7134_BOARD_MANLI_MTV002:
case SAA7134_BOARD_BEHOLD_409FM:
case SAA7134_BOARD_AVACSSMARTTV:
case SAA7134_BOARD_GOTVIEW_7135:
case SAA7134_BOARD_KWORLD_TERMINATOR:
case SAA7134_BOARD_SEDNA_PC_TV_CARDBUS:
case SAA7134_BOARD_FLYDVBT_LR301:
case SAA7134_BOARD_ASUSTeK_PS3_100:
case SAA7134_BOARD_ASUSTeK_P7131_DUAL:
case SAA7134_BOARD_ASUSTeK_P7131_HYBRID_LNA:
case SAA7134_BOARD_ASUSTeK_P7131_ANALOG:
case SAA7134_BOARD_FLYDVBTDUO:
case SAA7134_BOARD_PROTEUS_2309:
case SAA7134_BOARD_AVERMEDIA_A16AR:
case SAA7134_BOARD_ENCORE_ENLTV:
case SAA7134_BOARD_ENCORE_ENLTV_FM:
case SAA7134_BOARD_ENCORE_ENLTV_FM53:
case SAA7134_BOARD_ENCORE_ENLTV_FM3:
case SAA7134_BOARD_10MOONSTVMASTER3:
case SAA7134_BOARD_BEHOLD_401:
case SAA7134_BOARD_BEHOLD_403:
case SAA7134_BOARD_BEHOLD_403FM:
case SAA7134_BOARD_BEHOLD_405:
case SAA7134_BOARD_BEHOLD_405FM:
case SAA7134_BOARD_BEHOLD_407:
case SAA7134_BOARD_BEHOLD_407FM:
case SAA7134_BOARD_BEHOLD_409:
case SAA7134_BOARD_BEHOLD_505FM:
case SAA7134_BOARD_BEHOLD_505RDS_MK5:
case SAA7134_BOARD_BEHOLD_505RDS_MK3:
case SAA7134_BOARD_BEHOLD_507_9FM:
case SAA7134_BOARD_BEHOLD_507RDS_MK3:
case SAA7134_BOARD_BEHOLD_507RDS_MK5:
case SAA7134_BOARD_GENIUS_TVGO_A11MCE:
case SAA7134_BOARD_REAL_ANGEL_220:
case SAA7134_BOARD_KWORLD_PLUS_TV_ANALOG:
case SAA7134_BOARD_AVERMEDIA_GO_007_FM_PLUS:
case SAA7134_BOARD_ROVERMEDIA_LINK_PRO_FM:
case SAA7134_BOARD_LEADTEK_WINFAST_DTV1000S:
case SAA7134_BOARD_LEADTEK_WINFAST_TV2100_FM:
dev->has_remote = SAA7134_REMOTE_GPIO;
break;
case SAA7134_BOARD_FLYDVBS_LR300:
saa_writeb(SAA7134_GPIO_GPMODE3, 0x80);
saa_writeb(SAA7134_GPIO_GPSTATUS2, 0x40);
dev->has_remote = SAA7134_REMOTE_GPIO;
break;
case SAA7134_BOARD_MD5044:
pr_warn("%s: seems there are two different versions of the MD5044\n"
"%s: (with the same ID) out there. If sound doesn't work for\n"
"%s: you try the audio_clock_override=0x200000 insmod option.\n",
dev->name, dev->name, dev->name);
break;
case SAA7134_BOARD_CINERGY400_CARDBUS:
/* power-up tuner chip */
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x00040000, 0x00040000);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x00040000, 0x00000000);
break;
case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL:
/* this turns the remote control chip off to work around a bug in it */
saa_writeb(SAA7134_GPIO_GPMODE1, 0x80);
saa_writeb(SAA7134_GPIO_GPSTATUS1, 0x80);
break;
case SAA7134_BOARD_MONSTERTV_MOBILE:
/* power-up tuner chip */
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x00040000, 0x00040000);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x00040000, 0x00000004);
break;
case SAA7134_BOARD_FLYDVBT_DUO_CARDBUS:
/* turn the fan on */
saa_writeb(SAA7134_GPIO_GPMODE3, 0x08);
saa_writeb(SAA7134_GPIO_GPSTATUS3, 0x06);
break;
case SAA7134_BOARD_ADS_DUO_CARDBUS_PTV331:
case SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS:
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x08000000, 0x08000000);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x08000000, 0x00000000);
break;
case SAA7134_BOARD_AVERMEDIA_CARDBUS:
case SAA7134_BOARD_AVERMEDIA_M115:
/* power-down tuner chip */
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0xffffffff, 0);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0xffffffff, 0);
msleep(10);
/* power-up tuner chip */
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0xffffffff, 0xffffffff);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0xffffffff, 0xffffffff);
msleep(10);
break;
case SAA7134_BOARD_AVERMEDIA_CARDBUS_501:
/* power-down tuner chip */
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x08400000, 0x08400000);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x08400000, 0);
msleep(10);
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x08400000, 0x08400000);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x08400000, 0x08400000);
msleep(10);
dev->has_remote = SAA7134_REMOTE_I2C;
break;
case SAA7134_BOARD_AVERMEDIA_CARDBUS_506:
saa7134_set_gpio(dev, 23, 0);
msleep(10);
saa7134_set_gpio(dev, 23, 1);
dev->has_remote = SAA7134_REMOTE_I2C;
break;
case SAA7134_BOARD_AVERMEDIA_M103:
saa7134_set_gpio(dev, 23, 0);
msleep(10);
saa7134_set_gpio(dev, 23, 1);
break;
case SAA7134_BOARD_AVERMEDIA_A16D:
saa7134_set_gpio(dev, 21, 0);
msleep(10);
saa7134_set_gpio(dev, 21, 1);
msleep(1);
dev->has_remote = SAA7134_REMOTE_GPIO;
break;
case SAA7134_BOARD_BEHOLD_COLUMBUS_TVFM:
/* power-down tuner chip */
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x000A8004, 0x000A8004);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x000A8004, 0);
msleep(10);
/* power-up tuner chip */
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x000A8004, 0x000A8004);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x000A8004, 0x000A8004);
msleep(10);
/* remote via GPIO */
dev->has_remote = SAA7134_REMOTE_GPIO;
break;
case SAA7134_BOARD_RTD_VFG7350:
/*
* Make sure Production Test Register at offset 0x1D1 is cleared
* to take chip out of test mode. Clearing bit 4 (TST_EN_AOUT)
* prevents pin 105 from remaining low; keeping pin 105 low
* continually resets the SAA6752 chip.
*/
saa_writeb (SAA7134_PRODUCTION_TEST_MODE, 0x00);
break;
case SAA7134_BOARD_HAUPPAUGE_HVR1150:
case SAA7134_BOARD_HAUPPAUGE_HVR1120:
dev->has_remote = SAA7134_REMOTE_GPIO;
/* GPIO 26 high for digital, low for analog */
saa7134_set_gpio(dev, 26, 0);
msleep(1);
saa7134_set_gpio(dev, 22, 0);
msleep(10);
saa7134_set_gpio(dev, 22, 1);
break;
/* i2c remotes */
case SAA7134_BOARD_PINNACLE_PCTV_110i:
case SAA7134_BOARD_PINNACLE_PCTV_310i:
case SAA7134_BOARD_UPMOST_PURPLE_TV:
case SAA7134_BOARD_MSI_TVATANYWHERE_PLUS:
case SAA7134_BOARD_HAUPPAUGE_HVR1110:
case SAA7134_BOARD_BEHOLD_607FM_MK3:
case SAA7134_BOARD_BEHOLD_607FM_MK5:
case SAA7134_BOARD_BEHOLD_609FM_MK3:
case SAA7134_BOARD_BEHOLD_609FM_MK5:
case SAA7134_BOARD_BEHOLD_607RDS_MK3:
case SAA7134_BOARD_BEHOLD_607RDS_MK5:
case SAA7134_BOARD_BEHOLD_609RDS_MK3:
case SAA7134_BOARD_BEHOLD_609RDS_MK5:
case SAA7134_BOARD_BEHOLD_M6:
case SAA7134_BOARD_BEHOLD_M63:
case SAA7134_BOARD_BEHOLD_M6_EXTRA:
case SAA7134_BOARD_BEHOLD_H6:
case SAA7134_BOARD_BEHOLD_X7:
case SAA7134_BOARD_BEHOLD_H7:
case SAA7134_BOARD_BEHOLD_A7:
case SAA7134_BOARD_KWORLD_PC150U:
case SAA7134_BOARD_SNAZIO_TVPVR_PRO:
dev->has_remote = SAA7134_REMOTE_I2C;
break;
case SAA7134_BOARD_AVERMEDIA_A169_B:
pr_warn("%s: %s: dual saa713x broadcast decoders\n"
"%s: Sorry, none of the inputs to this chip are supported yet.\n"
"%s: Dual decoder functionality is disabled for now, use the other chip.\n",
dev->name, card(dev).name, dev->name, dev->name);
break;
case SAA7134_BOARD_AVERMEDIA_M102:
/* enable tuner */
dev->has_remote = SAA7134_REMOTE_GPIO;
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x8c040007, 0x8c040007);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x0c0007cd, 0x0c0007cd);
break;
case SAA7134_BOARD_AVERMEDIA_A700_HYBRID:
case SAA7134_BOARD_AVERMEDIA_A700_PRO:
/* write windows gpio values */
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x80040100, 0x80040100);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x80040100, 0x00040100);
break;
case SAA7134_BOARD_AVERMEDIA_A706:
/* radio antenna select: tristate both as in Windows driver */
saa7134_set_gpio(dev, 12, 3); /* TV antenna */
saa7134_set_gpio(dev, 13, 3); /* FM antenna */
dev->has_remote = SAA7134_REMOTE_I2C;
/*
* Disable CE5039 DVB-S tuner now (SLEEP pin high) to prevent
* it from interfering with analog tuner detection
*/
saa7134_set_gpio(dev, 23, 1);
break;
case SAA7134_BOARD_VIDEOMATE_S350:
dev->has_remote = SAA7134_REMOTE_GPIO;
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x0000C000, 0x0000C000);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x0000C000, 0x0000C000);
break;
case SAA7134_BOARD_AVERMEDIA_M733A:
saa7134_set_gpio(dev, 1, 1);
msleep(10);
saa7134_set_gpio(dev, 1, 0);
msleep(10);
saa7134_set_gpio(dev, 1, 1);
dev->has_remote = SAA7134_REMOTE_GPIO;
break;
case SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2:
/* enable LGS-8G75 */
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x0e050000, 0x0c050000);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x0e050000, 0x0c050000);
break;
case SAA7134_BOARD_VIDEOMATE_T750:
/* enable the analog tuner */
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x00008000, 0x00008000);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x00008000, 0x00008000);
break;
}
return 0;
}
static void saa7134_tuner_setup(struct saa7134_dev *dev)
{
struct tuner_setup tun_setup;
unsigned int mode_mask = T_RADIO | T_ANALOG_TV;
memset(&tun_setup, 0, sizeof(tun_setup));
tun_setup.tuner_callback = saa7134_tuner_callback;
if (saa7134_boards[dev->board].radio_type != UNSET) {
tun_setup.type = saa7134_boards[dev->board].radio_type;
tun_setup.addr = saa7134_boards[dev->board].radio_addr;
tun_setup.mode_mask = T_RADIO;
saa_call_all(dev, tuner, s_type_addr, &tun_setup);
mode_mask &= ~T_RADIO;
}
if ((dev->tuner_type != TUNER_ABSENT) && (dev->tuner_type != UNSET)) {
tun_setup.type = dev->tuner_type;
tun_setup.addr = dev->tuner_addr;
tun_setup.config = &saa7134_boards[dev->board].tda829x_conf;
tun_setup.tuner_callback = saa7134_tuner_callback;
tun_setup.mode_mask = mode_mask;
saa_call_all(dev, tuner, s_type_addr, &tun_setup);
}
if (dev->tda9887_conf) {
struct v4l2_priv_tun_config tda9887_cfg;
tda9887_cfg.tuner = TUNER_TDA9887;
tda9887_cfg.priv = &dev->tda9887_conf;
saa_call_all(dev, tuner, s_config, &tda9887_cfg);
}
if (dev->tuner_type == TUNER_XC2028) {
struct v4l2_priv_tun_config xc2028_cfg;
struct xc2028_ctrl ctl;
memset(&xc2028_cfg, 0, sizeof(xc2028_cfg));
memset(&ctl, 0, sizeof(ctl));
ctl.fname = XC2028_DEFAULT_FIRMWARE;
ctl.max_len = 64;
switch (dev->board) {
case SAA7134_BOARD_AVERMEDIA_A16D:
case SAA7134_BOARD_AVERMEDIA_CARDBUS_506:
case SAA7134_BOARD_AVERMEDIA_M103:
case SAA7134_BOARD_AVERMEDIA_A700_HYBRID:
ctl.demod = XC3028_FE_ZARLINK456;
break;
default:
ctl.demod = XC3028_FE_OREN538;
ctl.mts = 1;
}
xc2028_cfg.tuner = TUNER_XC2028;
xc2028_cfg.priv = &ctl;
saa_call_all(dev, tuner, s_config, &xc2028_cfg);
}
}
/* stuff which needs working i2c */
int saa7134_board_init2(struct saa7134_dev *dev)
{
unsigned char buf;
int board;
/* Put here the code that enables the chips that are needed
for analog mode and doesn't depend on the tuner attachment.
It is also a good idea to get tuner type from eeprom, etc before
initializing tuner, since we can avoid loading tuner driver
on devices that has TUNER_ABSENT
*/
switch (dev->board) {
case SAA7134_BOARD_BMK_MPEX_NOTUNER:
case SAA7134_BOARD_BMK_MPEX_TUNER:
/* Checks if the device has a tuner at 0x60 addr
If the device doesn't have a tuner, TUNER_ABSENT
will be used at tuner_type, avoiding loading tuner
without needing it
*/
dev->i2c_client.addr = 0x60;
board = (i2c_master_recv(&dev->i2c_client, &buf, 0) < 0)
? SAA7134_BOARD_BMK_MPEX_NOTUNER
: SAA7134_BOARD_BMK_MPEX_TUNER;
if (board == dev->board)
break;
dev->board = board;
pr_warn("%s: board type fixup: %s\n", dev->name,
saa7134_boards[dev->board].name);
dev->tuner_type = saa7134_boards[dev->board].tuner_type;
break;
case SAA7134_BOARD_MD7134:
{
u8 subaddr;
u8 data[3], data1[] = { 0x09, 0x9f, 0x86, 0x11};
int ret, tuner_t;
struct i2c_msg msg[] = {{.addr = 0x50, .flags = 0, .buf = &subaddr, .len = 1},
{.addr = 0x50, .flags = I2C_M_RD, .buf = data, .len = 3}},
msg1 = {.addr = 0x61, .flags = 0, .buf = data1, .len = sizeof(data1)};
subaddr= 0x14;
tuner_t = 0;
/* Retrieve device data from eeprom, checking for the
proper tuner_type.
*/
ret = i2c_transfer(&dev->i2c_adap, msg, 2);
if (ret != 2) {
pr_err("EEPROM read failure\n");
} else if ((data[0] != 0) && (data[0] != 0xff)) {
/* old config structure */
subaddr = data[0] + 2;
msg[1].len = 2;
i2c_transfer(&dev->i2c_adap, msg, 2);
tuner_t = (data[0] << 8) + data[1];
switch (tuner_t){
case 0x0103:
dev->tuner_type = TUNER_PHILIPS_PAL;
break;
case 0x010C:
dev->tuner_type = TUNER_PHILIPS_FM1216ME_MK3;
break;
default:
pr_err("%s Can't determine tuner type %x from EEPROM\n",
dev->name, tuner_t);
}
} else if ((data[1] != 0) && (data[1] != 0xff)) {
/* new config structure */
subaddr = data[1] + 1;
msg[1].len = 1;
i2c_transfer(&dev->i2c_adap, msg, 2);
subaddr = data[0] + 1;
msg[1].len = 2;
i2c_transfer(&dev->i2c_adap, msg, 2);
tuner_t = (data[1] << 8) + data[0];
switch (tuner_t) {
case 0x0005:
dev->tuner_type = TUNER_PHILIPS_FM1216ME_MK3;
break;
case 0x001d:
dev->tuner_type = TUNER_PHILIPS_FMD1216ME_MK3;
pr_info("%s Board has DVB-T\n",
dev->name);
break;
default:
pr_err("%s Can't determine tuner type %x from EEPROM\n",
dev->name, tuner_t);
}
} else {
pr_err("%s unexpected config structure\n", dev->name);
}
pr_info("%s Tuner type is %d\n", dev->name, dev->tuner_type);
/* The tuner TUNER_PHILIPS_FMD1216ME_MK3 after hardware */
/* start has disabled IF and enabled DVB-T. When saa7134 */
/* scan I2C devices it will not detect IF tda9887 and can`t*/
/* watch TV without software reboot. To solve this problem */
/* switch the tuner to analog TV mode manually. */
if (dev->tuner_type == TUNER_PHILIPS_FMD1216ME_MK3) {
if (i2c_transfer(&dev->i2c_adap, &msg1, 1) != 1)
printk(KERN_WARNING "%s: Unable to enable IF of the tuner.\n", dev->name);
}
break;
}
case SAA7134_BOARD_PHILIPS_EUROPA:
if (dev->autodetected && (dev->eedata[0x41] == 0x1c)) {
/* Reconfigure board as Snake reference design */
dev->board = SAA7134_BOARD_PHILIPS_SNAKE;
dev->tuner_type = saa7134_boards[dev->board].tuner_type;
pr_info("%s: Reconfigured board as %s\n",
dev->name, saa7134_boards[dev->board].name);
break;
}
fallthrough;
case SAA7134_BOARD_VIDEOMATE_DVBT_300:
case SAA7134_BOARD_ASUS_EUROPA2_HYBRID:
case SAA7134_BOARD_ASUS_EUROPA_HYBRID:
case SAA7134_BOARD_TECHNOTREND_BUDGET_T3000:
{
/* The Philips EUROPA based hybrid boards have the tuner
connected through the channel decoder. We have to make it
transparent to find it
*/
u8 data[] = { 0x07, 0x02};
struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
i2c_transfer(&dev->i2c_adap, &msg, 1);
break;
}
case SAA7134_BOARD_PHILIPS_TIGER:
case SAA7134_BOARD_PHILIPS_TIGER_S:
{
u8 data[] = { 0x3c, 0x33, 0x60};
struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
if (dev->autodetected && (dev->eedata[0x49] == 0x50)) {
dev->board = SAA7134_BOARD_PHILIPS_TIGER_S;
pr_info("%s: Reconfigured board as %s\n",
dev->name, saa7134_boards[dev->board].name);
}
if (dev->board == SAA7134_BOARD_PHILIPS_TIGER_S) {
dev->tuner_type = TUNER_PHILIPS_TDA8290;
data[2] = 0x68;
i2c_transfer(&dev->i2c_adap, &msg, 1);
break;
}
i2c_transfer(&dev->i2c_adap, &msg, 1);
break;
}
case SAA7134_BOARD_ASUSTeK_TVFM7135:
/* The card below is detected as card=53, but is different */
if (dev->autodetected && (dev->eedata[0x27] == 0x03)) {
dev->board = SAA7134_BOARD_ASUSTeK_P7131_ANALOG;
pr_info("%s: P7131 analog only, using entry of %s\n",
dev->name, saa7134_boards[dev->board].name);
/*
* IR init has already happened for other cards, so
* we have to catch up.
*/
dev->has_remote = SAA7134_REMOTE_GPIO;
saa7134_input_init1(dev);
}
break;
case SAA7134_BOARD_HAUPPAUGE_HVR1150:
case SAA7134_BOARD_HAUPPAUGE_HVR1120:
hauppauge_eeprom(dev, dev->eedata+0x80);
break;
case SAA7134_BOARD_HAUPPAUGE_HVR1110:
hauppauge_eeprom(dev, dev->eedata+0x80);
fallthrough;
case SAA7134_BOARD_PINNACLE_PCTV_310i:
case SAA7134_BOARD_KWORLD_DVBT_210:
case SAA7134_BOARD_TEVION_DVBT_220RF:
case SAA7134_BOARD_ASUSTeK_TIGER:
case SAA7134_BOARD_ASUSTeK_P7131_DUAL:
case SAA7134_BOARD_ASUSTeK_P7131_HYBRID_LNA:
case SAA7134_BOARD_MEDION_MD8800_QUADRO:
case SAA7134_BOARD_AVERMEDIA_SUPER_007:
case SAA7134_BOARD_TWINHAN_DTV_DVB_3056:
case SAA7134_BOARD_CREATIX_CTX953:
{
/* this is a hybrid board, initialize to analog mode
* and configure firmware eeprom address
*/
u8 data[] = { 0x3c, 0x33, 0x60};
struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
i2c_transfer(&dev->i2c_adap, &msg, 1);
break;
}
case SAA7134_BOARD_ASUSTeK_TIGER_3IN1:
{
u8 data[] = { 0x3c, 0x33, 0x60};
struct i2c_msg msg = {.addr = 0x0b, .flags = 0, .buf = data,
.len = sizeof(data)};
i2c_transfer(&dev->i2c_adap, &msg, 1);
break;
}
case SAA7134_BOARD_ASUSTeK_PS3_100:
{
u8 data[] = { 0x3c, 0x33, 0x60};
struct i2c_msg msg = {.addr = 0x0b, .flags = 0, .buf = data,
.len = sizeof(data)};
i2c_transfer(&dev->i2c_adap, &msg, 1);
break;
}
case SAA7134_BOARD_FLYDVB_TRIO:
{
u8 temp = 0;
int rc;
u8 data[] = { 0x3c, 0x33, 0x62};
struct i2c_msg msg = {.addr=0x09, .flags=0, .buf=data, .len = sizeof(data)};
i2c_transfer(&dev->i2c_adap, &msg, 1);
/*
* send weak up message to pic16C505 chip
* @ LifeView FlyDVB Trio
*/
msg.buf = &temp;
msg.addr = 0x0b;
msg.len = 1;
if (1 != i2c_transfer(&dev->i2c_adap, &msg, 1)) {
pr_warn("%s: send wake up byte to pic16C505(IR chip) failed\n",
dev->name);
} else {
msg.flags = I2C_M_RD;
rc = i2c_transfer(&dev->i2c_adap, &msg, 1);
pr_info("%s: probe IR chip @ i2c 0x%02x: %s\n",
dev->name, msg.addr,
(1 == rc) ? "yes" : "no");
if (rc == 1)
dev->has_remote = SAA7134_REMOTE_I2C;
}
break;
}
case SAA7134_BOARD_ADS_DUO_CARDBUS_PTV331:
case SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS:
{
/* initialize analog mode */
u8 data[] = { 0x3c, 0x33, 0x6a};
struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
i2c_transfer(&dev->i2c_adap, &msg, 1);
break;
}
case SAA7134_BOARD_CINERGY_HT_PCMCIA:
case SAA7134_BOARD_CINERGY_HT_PCI:
{
/* initialize analog mode */
u8 data[] = { 0x3c, 0x33, 0x68};
struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
i2c_transfer(&dev->i2c_adap, &msg, 1);
break;
}
case SAA7134_BOARD_VIDEOMATE_DVBT_200:
case SAA7134_BOARD_VIDEOMATE_DVBT_200A:
/* The T200 and the T200A share the same pci id. Consequently,
* we are going to query eeprom to try to find out which one we
* are actually looking at. */
/* Don't do this if the board was specifically selected with an
* insmod option or if we have the default configuration T200*/
if (!dev->autodetected || (dev->eedata[0x41] == 0xd0))
break;
if (dev->eedata[0x41] == 0x02) {
/* Reconfigure board as T200A */
dev->board = SAA7134_BOARD_VIDEOMATE_DVBT_200A;
dev->tuner_type = saa7134_boards[dev->board].tuner_type;
dev->tda9887_conf = saa7134_boards[dev->board].tda9887_conf;
pr_info("%s: Reconfigured board as %s\n",
dev->name, saa7134_boards[dev->board].name);
} else {
pr_warn("%s: Unexpected tuner type info: %x in eeprom\n",
dev->name, dev->eedata[0x41]);
break;
}
break;
case SAA7134_BOARD_ADS_INSTANT_HDTV_PCI:
case SAA7134_BOARD_KWORLD_ATSC110:
{
struct i2c_msg msg = { .addr = 0x0a, .flags = 0 };
int i;
static u8 buffer[][2] = {
{ 0x10, 0x12 },
{ 0x13, 0x04 },
{ 0x16, 0x00 },
{ 0x14, 0x04 },
{ 0x17, 0x00 },
};
for (i = 0; i < ARRAY_SIZE(buffer); i++) {
msg.buf = &buffer[i][0];
msg.len = ARRAY_SIZE(buffer[0]);
if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1)
pr_warn("%s: Unable to enable tuner(%i).\n",
dev->name, i);
}
break;
}
case SAA7134_BOARD_BEHOLD_H6:
{
u8 data[] = { 0x09, 0x9f, 0x86, 0x11};
struct i2c_msg msg = {.addr = 0x61, .flags = 0, .buf = data,
.len = sizeof(data)};
/* The tuner TUNER_PHILIPS_FMD1216MEX_MK3 after hardware */
/* start has disabled IF and enabled DVB-T. When saa7134 */
/* scan I2C devices it not detect IF tda9887 and can`t */
/* watch TV without software reboot. For solve this problem */
/* switch the tuner to analog TV mode manually. */
if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1)
pr_warn("%s: Unable to enable IF of the tuner.\n",
dev->name);
break;
}
case SAA7134_BOARD_KWORLD_PCI_SBTVD_FULLSEG:
saa_writel(SAA7134_GPIO_GPMODE0 >> 2, 0x4000);
saa_writel(SAA7134_GPIO_GPSTATUS0 >> 2, 0x4000);
saa7134_set_gpio(dev, 27, 0);
break;
} /* switch() */
/* initialize tuner (don't do this when resuming) */
if (!dev->insuspend && TUNER_ABSENT != dev->tuner_type) {
int has_demod = (dev->tda9887_conf & TDA9887_PRESENT);
/* Note: radio tuner address is always filled in,
so we do not need to probe for a radio tuner device. */
if (dev->radio_type != UNSET)
v4l2_i2c_new_subdev(&dev->v4l2_dev,
&dev->i2c_adap, "tuner",
dev->radio_addr, NULL);
if (has_demod)
v4l2_i2c_new_subdev(&dev->v4l2_dev,
&dev->i2c_adap, "tuner",
0, v4l2_i2c_tuner_addrs(ADDRS_DEMOD));
if (dev->tuner_addr == ADDR_UNSET) {
enum v4l2_i2c_tuner_type type =
has_demod ? ADDRS_TV_WITH_DEMOD : ADDRS_TV;
v4l2_i2c_new_subdev(&dev->v4l2_dev,
&dev->i2c_adap, "tuner",
0, v4l2_i2c_tuner_addrs(type));
} else {
v4l2_i2c_new_subdev(&dev->v4l2_dev,
&dev->i2c_adap, "tuner",
dev->tuner_addr, NULL);
}
}
saa7134_tuner_setup(dev);
switch (dev->board) {
case SAA7134_BOARD_BEHOLD_COLUMBUS_TVFM:
case SAA7134_BOARD_AVERMEDIA_CARDBUS_501:
{
struct v4l2_priv_tun_config tea5767_cfg;
struct tea5767_ctrl ctl;
dev->i2c_client.addr = 0xC0;
/* set TEA5767(analog FM) defines */
memset(&ctl, 0, sizeof(ctl));
ctl.xtal_freq = TEA5767_HIGH_LO_13MHz;
tea5767_cfg.tuner = TUNER_TEA5767;
tea5767_cfg.priv = &ctl;
saa_call_all(dev, tuner, s_config, &tea5767_cfg);
break;
}
} /* switch() */
return 0;
}
| linux-master | drivers/media/pci/saa7134/saa7134-cards.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* (c) 2004 Gerd Knorr <[email protected]> [SuSE Labs]
*
* Extended 3 / 2005 by Hartmut Hackmann to support various
* cards with the tda10046 DVB-T channel decoder
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/kthread.h>
#include <linux/suspend.h>
#include <media/v4l2-common.h>
#include "dvb-pll.h"
#include <media/dvb_frontend.h>
#include "mt352.h"
#include "mt352_priv.h" /* FIXME */
#include "tda1004x.h"
#include "nxt200x.h"
#include "xc2028.h"
#include "xc5000.h"
#include "tda10086.h"
#include "tda826x.h"
#include "tda827x.h"
#include "isl6421.h"
#include "isl6405.h"
#include "lnbp21.h"
#include "tuner-simple.h"
#include "tda10048.h"
#include "tda18271.h"
#include "lgdt3305.h"
#include "tda8290.h"
#include "mb86a20s.h"
#include "lgs8gxx.h"
#include "zl10353.h"
#include "qt1010.h"
#include "zl10036.h"
#include "zl10039.h"
#include "mt312.h"
#include "s5h1411.h"
MODULE_AUTHOR("Gerd Knorr <[email protected]> [SuSE Labs]");
MODULE_LICENSE("GPL");
static unsigned int antenna_pwr;
module_param(antenna_pwr, int, 0444);
MODULE_PARM_DESC(antenna_pwr,"enable antenna power (Pinnacle 300i)");
static int use_frontend;
module_param(use_frontend, int, 0644);
MODULE_PARM_DESC(use_frontend,"for cards with multiple frontends (0: terrestrial, 1: satellite)");
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
/* ------------------------------------------------------------------
* mt352 based DVB-T cards
*/
static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on)
{
u32 ok;
if (!on) {
saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26));
saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
return 0;
}
saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26));
saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
udelay(10);
saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 28));
saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28));
udelay(10);
saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28));
udelay(10);
ok = saa_readl(SAA7134_GPIO_GPSTATUS0) & (1 << 27);
pr_debug("%s %s\n", __func__, ok ? "on" : "off");
if (!ok)
saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
return ok;
}
static int mt352_pinnacle_init(struct dvb_frontend* fe)
{
static u8 clock_config [] = { CLOCK_CTL, 0x3d, 0x28 };
static u8 reset [] = { RESET, 0x80 };
static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 };
static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 };
static u8 fsm_ctl_cfg[] = { 0x7b, 0x04 };
static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x0f };
static u8 scan_ctl_cfg [] = { SCAN_CTL, 0x0d };
static u8 irq_cfg [] = { INTERRUPT_EN_0, 0x00, 0x00, 0x00, 0x00 };
pr_debug("%s called\n", __func__);
mt352_write(fe, clock_config, sizeof(clock_config));
udelay(200);
mt352_write(fe, reset, sizeof(reset));
mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
mt352_write(fe, agc_cfg, sizeof(agc_cfg));
mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
mt352_write(fe, fsm_ctl_cfg, sizeof(fsm_ctl_cfg));
mt352_write(fe, scan_ctl_cfg, sizeof(scan_ctl_cfg));
mt352_write(fe, irq_cfg, sizeof(irq_cfg));
return 0;
}
static int mt352_aver777_init(struct dvb_frontend* fe)
{
static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x2d };
static u8 reset [] = { RESET, 0x80 };
static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 };
static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 };
mt352_write(fe, clock_config, sizeof(clock_config));
udelay(200);
mt352_write(fe, reset, sizeof(reset));
mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
mt352_write(fe, agc_cfg, sizeof(agc_cfg));
mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
return 0;
}
static int mt352_avermedia_xc3028_init(struct dvb_frontend *fe)
{
static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x2d };
static u8 reset [] = { RESET, 0x80 };
static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
static u8 agc_cfg [] = { AGC_TARGET, 0xe };
static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 };
mt352_write(fe, clock_config, sizeof(clock_config));
udelay(200);
mt352_write(fe, reset, sizeof(reset));
mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
mt352_write(fe, agc_cfg, sizeof(agc_cfg));
mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
return 0;
}
static int mt352_pinnacle_tuner_set_params(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 off[] = { 0x00, 0xf1};
u8 on[] = { 0x00, 0x71};
struct i2c_msg msg = {.addr=0x43, .flags=0, .buf=off, .len = sizeof(off)};
struct saa7134_dev *dev = fe->dvb->priv;
struct v4l2_frequency f;
/* set frequency (mt2050) */
f.tuner = 0;
f.type = V4L2_TUNER_DIGITAL_TV;
f.frequency = c->frequency / 1000 * 16 / 1000;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
i2c_transfer(&dev->i2c_adap, &msg, 1);
saa_call_all(dev, tuner, s_frequency, &f);
msg.buf = on;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
i2c_transfer(&dev->i2c_adap, &msg, 1);
pinnacle_antenna_pwr(dev, antenna_pwr);
/* mt352 setup */
return mt352_pinnacle_init(fe);
}
static struct mt352_config pinnacle_300i = {
.demod_address = 0x3c >> 1,
.adc_clock = 20333,
.if2 = 36150,
.no_tuner = 1,
.demod_init = mt352_pinnacle_init,
};
static struct mt352_config avermedia_777 = {
.demod_address = 0xf,
.demod_init = mt352_aver777_init,
};
static struct mt352_config avermedia_xc3028_mt352_dev = {
.demod_address = (0x1e >> 1),
.no_tuner = 1,
.demod_init = mt352_avermedia_xc3028_init,
};
static struct tda18271_std_map mb86a20s_tda18271_std_map = {
.dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
.if_lvl = 7, .rfagc_top = 0x37, },
};
static struct tda18271_config kworld_tda18271_config = {
.std_map = &mb86a20s_tda18271_std_map,
.gate = TDA18271_GATE_DIGITAL,
.config = 3, /* Use tuner callback for AGC */
};
static const struct mb86a20s_config kworld_mb86a20s_config = {
.demod_address = 0x10,
};
static int kworld_sbtvd_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct saa7134_dev *dev = fe->dvb->priv;
unsigned char initmsg[] = {0x45, 0x97};
unsigned char msg_enable[] = {0x45, 0xc1};
unsigned char msg_disable[] = {0x45, 0x81};
struct i2c_msg msg = {.addr = 0x4b, .flags = 0, .buf = initmsg, .len = 2};
if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1) {
pr_warn("could not access the I2C gate\n");
return -EIO;
}
if (enable)
msg.buf = msg_enable;
else
msg.buf = msg_disable;
if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1) {
pr_warn("could not access the I2C gate\n");
return -EIO;
}
msleep(20);
return 0;
}
/* ==================================================================
* tda1004x based DVB-T cards, helper functions
*/
static int philips_tda1004x_request_firmware(struct dvb_frontend *fe,
const struct firmware **fw, char *name)
{
struct saa7134_dev *dev = fe->dvb->priv;
return request_firmware(fw, name, &dev->pci->dev);
}
/* ------------------------------------------------------------------
* these tuners are tu1216, td1316(a)
*/
static int philips_tda6651_pll_set(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct saa7134_dev *dev = fe->dvb->priv;
struct tda1004x_state *state = fe->demodulator_priv;
u8 addr = state->config->tuner_address;
u8 tuner_buf[4];
struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tuner_buf,.len =
sizeof(tuner_buf) };
int tuner_frequency = 0;
u8 band, cp, filter;
/* determine charge pump */
tuner_frequency = c->frequency + 36166000;
if (tuner_frequency < 87000000)
return -EINVAL;
else if (tuner_frequency < 130000000)
cp = 3;
else if (tuner_frequency < 160000000)
cp = 5;
else if (tuner_frequency < 200000000)
cp = 6;
else if (tuner_frequency < 290000000)
cp = 3;
else if (tuner_frequency < 420000000)
cp = 5;
else if (tuner_frequency < 480000000)
cp = 6;
else if (tuner_frequency < 620000000)
cp = 3;
else if (tuner_frequency < 830000000)
cp = 5;
else if (tuner_frequency < 895000000)
cp = 7;
else
return -EINVAL;
/* determine band */
if (c->frequency < 49000000)
return -EINVAL;
else if (c->frequency < 161000000)
band = 1;
else if (c->frequency < 444000000)
band = 2;
else if (c->frequency < 861000000)
band = 4;
else
return -EINVAL;
/* setup PLL filter */
switch (c->bandwidth_hz) {
case 6000000:
filter = 0;
break;
case 7000000:
filter = 0;
break;
case 8000000:
filter = 1;
break;
default:
return -EINVAL;
}
/* calculate divisor
* ((36166000+((1000000/6)/2)) + Finput)/(1000000/6)
*/
tuner_frequency = (((c->frequency / 1000) * 6) + 217496) / 1000;
/* setup tuner buffer */
tuner_buf[0] = (tuner_frequency >> 8) & 0x7f;
tuner_buf[1] = tuner_frequency & 0xff;
tuner_buf[2] = 0xca;
tuner_buf[3] = (cp << 5) | (filter << 3) | band;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1) {
pr_warn("could not write to tuner at addr: 0x%02x\n",
addr << 1);
return -EIO;
}
msleep(1);
return 0;
}
static int philips_tu1216_init(struct dvb_frontend *fe)
{
struct saa7134_dev *dev = fe->dvb->priv;
struct tda1004x_state *state = fe->demodulator_priv;
u8 addr = state->config->tuner_address;
static u8 tu1216_init[] = { 0x0b, 0xf5, 0x85, 0xab };
struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tu1216_init,.len = sizeof(tu1216_init) };
/* setup PLL configuration */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
return -EIO;
msleep(1);
return 0;
}
/* ------------------------------------------------------------------ */
static struct tda1004x_config philips_tu1216_60_config = {
.demod_address = 0x8,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_4M,
.agc_config = TDA10046_AGC_DEFAULT,
.if_freq = TDA10046_FREQ_3617,
.tuner_address = 0x60,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config philips_tu1216_61_config = {
.demod_address = 0x8,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_4M,
.agc_config = TDA10046_AGC_DEFAULT,
.if_freq = TDA10046_FREQ_3617,
.tuner_address = 0x61,
.request_firmware = philips_tda1004x_request_firmware
};
/* ------------------------------------------------------------------ */
static int philips_td1316_tuner_init(struct dvb_frontend *fe)
{
struct saa7134_dev *dev = fe->dvb->priv;
struct tda1004x_state *state = fe->demodulator_priv;
u8 addr = state->config->tuner_address;
static u8 msg[] = { 0x0b, 0xf5, 0x86, 0xab };
struct i2c_msg init_msg = {.addr = addr,.flags = 0,.buf = msg,.len = sizeof(msg) };
/* setup PLL configuration */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1)
return -EIO;
return 0;
}
static int philips_td1316_tuner_set_params(struct dvb_frontend *fe)
{
return philips_tda6651_pll_set(fe);
}
static int philips_td1316_tuner_sleep(struct dvb_frontend *fe)
{
struct saa7134_dev *dev = fe->dvb->priv;
struct tda1004x_state *state = fe->demodulator_priv;
u8 addr = state->config->tuner_address;
static u8 msg[] = { 0x0b, 0xdc, 0x86, 0xa4 };
struct i2c_msg analog_msg = {.addr = addr,.flags = 0,.buf = msg,.len = sizeof(msg) };
/* switch the tuner to analog mode */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
if (i2c_transfer(&dev->i2c_adap, &analog_msg, 1) != 1)
return -EIO;
return 0;
}
/* ------------------------------------------------------------------ */
static int philips_europa_tuner_init(struct dvb_frontend *fe)
{
struct saa7134_dev *dev = fe->dvb->priv;
static u8 msg[] = { 0x00, 0x40};
struct i2c_msg init_msg = {.addr = 0x43,.flags = 0,.buf = msg,.len = sizeof(msg) };
if (philips_td1316_tuner_init(fe))
return -EIO;
msleep(1);
if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1)
return -EIO;
return 0;
}
static int philips_europa_tuner_sleep(struct dvb_frontend *fe)
{
struct saa7134_dev *dev = fe->dvb->priv;
static u8 msg[] = { 0x00, 0x14 };
struct i2c_msg analog_msg = {.addr = 0x43,.flags = 0,.buf = msg,.len = sizeof(msg) };
if (philips_td1316_tuner_sleep(fe))
return -EIO;
/* switch the board to analog mode */
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
i2c_transfer(&dev->i2c_adap, &analog_msg, 1);
return 0;
}
static int philips_europa_demod_sleep(struct dvb_frontend *fe)
{
struct saa7134_dev *dev = fe->dvb->priv;
if (dev->original_demod_sleep)
dev->original_demod_sleep(fe);
fe->ops.i2c_gate_ctrl(fe, 1);
return 0;
}
static struct tda1004x_config philips_europa_config = {
.demod_address = 0x8,
.invert = 0,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_4M,
.agc_config = TDA10046_AGC_IFO_AUTO_POS,
.if_freq = TDA10046_FREQ_052,
.tuner_address = 0x61,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config medion_cardbus = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_IFO_AUTO_NEG,
.if_freq = TDA10046_FREQ_3613,
.tuner_address = 0x61,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config technotrend_budget_t3000_config = {
.demod_address = 0x8,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_4M,
.agc_config = TDA10046_AGC_DEFAULT,
.if_freq = TDA10046_FREQ_3617,
.tuner_address = 0x63,
.request_firmware = philips_tda1004x_request_firmware
};
/* ------------------------------------------------------------------
* tda 1004x based cards with philips silicon tuner
*/
static int tda8290_i2c_gate_ctrl( struct dvb_frontend* fe, int enable)
{
struct tda1004x_state *state = fe->demodulator_priv;
u8 addr = state->config->i2c_gate;
static u8 tda8290_close[] = { 0x21, 0xc0};
static u8 tda8290_open[] = { 0x21, 0x80};
struct i2c_msg tda8290_msg = {.addr = addr,.flags = 0, .len = 2};
if (enable) {
tda8290_msg.buf = tda8290_close;
} else {
tda8290_msg.buf = tda8290_open;
}
if (i2c_transfer(state->i2c, &tda8290_msg, 1) != 1) {
pr_warn("could not access tda8290 I2C gate\n");
return -EIO;
}
msleep(20);
return 0;
}
static int philips_tda827x_tuner_init(struct dvb_frontend *fe)
{
struct saa7134_dev *dev = fe->dvb->priv;
struct tda1004x_state *state = fe->demodulator_priv;
switch (state->config->antenna_switch) {
case 0:
break;
case 1:
pr_debug("setting GPIO21 to 0 (TV antenna?)\n");
saa7134_set_gpio(dev, 21, 0);
break;
case 2:
pr_debug("setting GPIO21 to 1 (Radio antenna?)\n");
saa7134_set_gpio(dev, 21, 1);
break;
}
return 0;
}
static int philips_tda827x_tuner_sleep(struct dvb_frontend *fe)
{
struct saa7134_dev *dev = fe->dvb->priv;
struct tda1004x_state *state = fe->demodulator_priv;
switch (state->config->antenna_switch) {
case 0:
break;
case 1:
pr_debug("setting GPIO21 to 1 (Radio antenna?)\n");
saa7134_set_gpio(dev, 21, 1);
break;
case 2:
pr_debug("setting GPIO21 to 0 (TV antenna?)\n");
saa7134_set_gpio(dev, 21, 0);
break;
}
return 0;
}
static int configure_tda827x_fe(struct saa7134_dev *dev,
struct tda1004x_config *cdec_conf,
struct tda827x_config *tuner_conf)
{
struct vb2_dvb_frontend *fe0;
/* Get the first frontend */
fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
if (!fe0)
return -EINVAL;
fe0->dvb.frontend = dvb_attach(tda10046_attach, cdec_conf, &dev->i2c_adap);
if (fe0->dvb.frontend) {
if (cdec_conf->i2c_gate)
fe0->dvb.frontend->ops.i2c_gate_ctrl = tda8290_i2c_gate_ctrl;
if (dvb_attach(tda827x_attach, fe0->dvb.frontend,
cdec_conf->tuner_address,
&dev->i2c_adap, tuner_conf))
return 0;
pr_warn("no tda827x tuner found at addr: %02x\n",
cdec_conf->tuner_address);
}
return -EINVAL;
}
/* ------------------------------------------------------------------ */
static struct tda827x_config tda827x_cfg_0 = {
.init = philips_tda827x_tuner_init,
.sleep = philips_tda827x_tuner_sleep,
.config = 0,
.switch_addr = 0
};
static struct tda827x_config tda827x_cfg_1 = {
.init = philips_tda827x_tuner_init,
.sleep = philips_tda827x_tuner_sleep,
.config = 1,
.switch_addr = 0x4b
};
static struct tda827x_config tda827x_cfg_2 = {
.init = philips_tda827x_tuner_init,
.sleep = philips_tda827x_tuner_sleep,
.config = 2,
.switch_addr = 0x4b
};
static struct tda827x_config tda827x_cfg_2_sw42 = {
.init = philips_tda827x_tuner_init,
.sleep = philips_tda827x_tuner_sleep,
.config = 2,
.switch_addr = 0x42
};
/* ------------------------------------------------------------------ */
static struct tda1004x_config tda827x_lifeview_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP11_I,
.if_freq = TDA10046_FREQ_045,
.tuner_address = 0x60,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config philips_tiger_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP11_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x61,
.antenna_switch= 1,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config cinergy_ht_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP01_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x61,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config cinergy_ht_pci_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP01_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x60,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config philips_tiger_s_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP01_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x61,
.antenna_switch= 1,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config pinnacle_pctv_310i_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP11_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x61,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config hauppauge_hvr_1110_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP11_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x61,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config asus_p7131_dual_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP11_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x61,
.antenna_switch= 2,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config lifeview_trio_config = {
.demod_address = 0x09,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP00_I,
.if_freq = TDA10046_FREQ_045,
.tuner_address = 0x60,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config tevion_dvbt220rf_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP11_I,
.if_freq = TDA10046_FREQ_045,
.tuner_address = 0x60,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config md8800_dvbt_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP01_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x60,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config asus_p7131_4871_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP01_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x61,
.antenna_switch= 2,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config asus_p7131_hybrid_lna_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP11_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x61,
.antenna_switch= 2,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config kworld_dvb_t_210_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP11_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x61,
.antenna_switch= 1,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config avermedia_super_007_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP01_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x60,
.antenna_switch= 1,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config twinhan_dtv_dvb_3056_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP01_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x42,
.tuner_address = 0x61,
.antenna_switch = 1,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config asus_tiger_3in1_config = {
.demod_address = 0x0b,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP11_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x61,
.antenna_switch = 1,
.request_firmware = philips_tda1004x_request_firmware
};
static struct tda1004x_config asus_ps3_100_config = {
.demod_address = 0x0b,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP11_I,
.if_freq = TDA10046_FREQ_045,
.i2c_gate = 0x4b,
.tuner_address = 0x61,
.antenna_switch = 1,
.request_firmware = philips_tda1004x_request_firmware
};
/* ------------------------------------------------------------------
* special case: this card uses saa713x GPIO22 for the mode switch
*/
static int ads_duo_tuner_init(struct dvb_frontend *fe)
{
struct saa7134_dev *dev = fe->dvb->priv;
philips_tda827x_tuner_init(fe);
/* route TDA8275a AGC input to the channel decoder */
saa7134_set_gpio(dev, 22, 1);
return 0;
}
static int ads_duo_tuner_sleep(struct dvb_frontend *fe)
{
struct saa7134_dev *dev = fe->dvb->priv;
/* route TDA8275a AGC input to the analog IF chip*/
saa7134_set_gpio(dev, 22, 0);
philips_tda827x_tuner_sleep(fe);
return 0;
}
static struct tda827x_config ads_duo_cfg = {
.init = ads_duo_tuner_init,
.sleep = ads_duo_tuner_sleep,
.config = 0
};
static struct tda1004x_config ads_tech_duo_config = {
.demod_address = 0x08,
.invert = 1,
.invert_oclk = 0,
.xtal_freq = TDA10046_XTAL_16M,
.agc_config = TDA10046_AGC_TDA827X,
.gpio_config = TDA10046_GP00_I,
.if_freq = TDA10046_FREQ_045,
.tuner_address = 0x61,
.request_firmware = philips_tda1004x_request_firmware
};
static struct zl10353_config behold_h6_config = {
.demod_address = 0x1e>>1,
.no_tuner = 1,
.parallel_ts = 1,
.disable_i2c_gate_ctrl = 1,
};
static struct xc5000_config behold_x7_tunerconfig = {
.i2c_address = 0xc2>>1,
.if_khz = 4560,
.radio_input = XC5000_RADIO_FM1,
};
static struct zl10353_config behold_x7_config = {
.demod_address = 0x1e>>1,
.if2 = 45600,
.no_tuner = 1,
.parallel_ts = 1,
.disable_i2c_gate_ctrl = 1,
};
static struct zl10353_config videomate_t750_zl10353_config = {
.demod_address = 0x0f,
.no_tuner = 1,
.parallel_ts = 1,
.disable_i2c_gate_ctrl = 1,
};
static struct qt1010_config videomate_t750_qt1010_config = {
.i2c_address = 0x62
};
/* ==================================================================
* tda10086 based DVB-S cards, helper functions
*/
static struct tda10086_config flydvbs = {
.demod_address = 0x0e,
.invert = 0,
.diseqc_tone = 0,
.xtal_freq = TDA10086_XTAL_16M,
};
static struct tda10086_config sd1878_4m = {
.demod_address = 0x0e,
.invert = 0,
.diseqc_tone = 0,
.xtal_freq = TDA10086_XTAL_4M,
};
/* ------------------------------------------------------------------
* special case: lnb supply is connected to the gated i2c
*/
static int md8800_set_voltage(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
int res = -EIO;
struct saa7134_dev *dev = fe->dvb->priv;
if (fe->ops.i2c_gate_ctrl) {
fe->ops.i2c_gate_ctrl(fe, 1);
if (dev->original_set_voltage)
res = dev->original_set_voltage(fe, voltage);
fe->ops.i2c_gate_ctrl(fe, 0);
}
return res;
};
static int md8800_set_high_voltage(struct dvb_frontend *fe, long arg)
{
int res = -EIO;
struct saa7134_dev *dev = fe->dvb->priv;
if (fe->ops.i2c_gate_ctrl) {
fe->ops.i2c_gate_ctrl(fe, 1);
if (dev->original_set_high_voltage)
res = dev->original_set_high_voltage(fe, arg);
fe->ops.i2c_gate_ctrl(fe, 0);
}
return res;
};
static int md8800_set_voltage2(struct dvb_frontend *fe,
enum fe_sec_voltage voltage)
{
struct saa7134_dev *dev = fe->dvb->priv;
u8 wbuf[2] = { 0x1f, 00 };
u8 rbuf;
struct i2c_msg msg[] = { { .addr = 0x08, .flags = 0, .buf = wbuf, .len = 1 },
{ .addr = 0x08, .flags = I2C_M_RD, .buf = &rbuf, .len = 1 } };
if (i2c_transfer(&dev->i2c_adap, msg, 2) != 2)
return -EIO;
/* NOTE: this assumes that gpo1 is used, it might be bit 5 (gpo2) */
if (voltage == SEC_VOLTAGE_18)
wbuf[1] = rbuf | 0x10;
else
wbuf[1] = rbuf & 0xef;
msg[0].len = 2;
i2c_transfer(&dev->i2c_adap, msg, 1);
return 0;
}
static int md8800_set_high_voltage2(struct dvb_frontend *fe, long arg)
{
pr_warn("%s: sorry can't set high LNB supply voltage from here\n",
__func__);
return -EIO;
}
/* ==================================================================
* nxt200x based ATSC cards, helper functions
*/
static const struct nxt200x_config avertvhda180 = {
.demod_address = 0x0a,
};
static const struct nxt200x_config kworldatsc110 = {
.demod_address = 0x0a,
};
/* ------------------------------------------------------------------ */
static struct mt312_config avertv_a700_mt312 = {
.demod_address = 0x0e,
.voltage_inverted = 1,
};
static struct zl10036_config avertv_a700_tuner = {
.tuner_address = 0x60,
};
static struct mt312_config zl10313_compro_s350_config = {
.demod_address = 0x0e,
};
static struct mt312_config zl10313_avermedia_a706_config = {
.demod_address = 0x0e,
};
static struct lgdt3305_config hcw_lgdt3305_config = {
.i2c_addr = 0x0e,
.mpeg_mode = LGDT3305_MPEG_SERIAL,
.tpclk_edge = LGDT3305_TPCLK_RISING_EDGE,
.tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
.deny_i2c_rptr = 1,
.spectral_inversion = 1,
.qam_if_khz = 4000,
.vsb_if_khz = 3250,
};
static struct tda10048_config hcw_tda10048_config = {
.demod_address = 0x10 >> 1,
.output_mode = TDA10048_SERIAL_OUTPUT,
.fwbulkwritelen = TDA10048_BULKWRITE_200,
.inversion = TDA10048_INVERSION_ON,
.dtv6_if_freq_khz = TDA10048_IF_3300,
.dtv7_if_freq_khz = TDA10048_IF_3500,
.dtv8_if_freq_khz = TDA10048_IF_4000,
.clk_freq_khz = TDA10048_CLK_16000,
.disable_gate_access = 1,
};
static struct tda18271_std_map hauppauge_tda18271_std_map = {
.atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
.if_lvl = 1, .rfagc_top = 0x58, },
.qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
.if_lvl = 1, .rfagc_top = 0x58, },
};
static struct tda18271_config hcw_tda18271_config = {
.std_map = &hauppauge_tda18271_std_map,
.gate = TDA18271_GATE_ANALOG,
.config = 3,
.output_opt = TDA18271_OUTPUT_LT_OFF,
};
static struct tda829x_config tda829x_no_probe = {
.probe_tuner = TDA829X_DONT_PROBE,
};
static struct tda10048_config zolid_tda10048_config = {
.demod_address = 0x10 >> 1,
.output_mode = TDA10048_PARALLEL_OUTPUT,
.fwbulkwritelen = TDA10048_BULKWRITE_200,
.inversion = TDA10048_INVERSION_ON,
.dtv6_if_freq_khz = TDA10048_IF_3300,
.dtv7_if_freq_khz = TDA10048_IF_3500,
.dtv8_if_freq_khz = TDA10048_IF_4000,
.clk_freq_khz = TDA10048_CLK_16000,
.disable_gate_access = 1,
};
static struct tda18271_config zolid_tda18271_config = {
.gate = TDA18271_GATE_ANALOG,
};
static struct tda10048_config dtv1000s_tda10048_config = {
.demod_address = 0x10 >> 1,
.output_mode = TDA10048_PARALLEL_OUTPUT,
.fwbulkwritelen = TDA10048_BULKWRITE_200,
.inversion = TDA10048_INVERSION_ON,
.dtv6_if_freq_khz = TDA10048_IF_3300,
.dtv7_if_freq_khz = TDA10048_IF_3800,
.dtv8_if_freq_khz = TDA10048_IF_4300,
.clk_freq_khz = TDA10048_CLK_16000,
.disable_gate_access = 1,
};
static struct tda18271_std_map dtv1000s_tda18271_std_map = {
.dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
.if_lvl = 1, .rfagc_top = 0x37, },
.dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
.if_lvl = 1, .rfagc_top = 0x37, },
.dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
.if_lvl = 1, .rfagc_top = 0x37, },
};
static struct tda18271_config dtv1000s_tda18271_config = {
.std_map = &dtv1000s_tda18271_std_map,
.gate = TDA18271_GATE_ANALOG,
};
static struct lgs8gxx_config prohdtv_pro2_lgs8g75_config = {
.prod = LGS8GXX_PROD_LGS8G75,
.demod_address = 0x1d,
.serial_ts = 0,
.ts_clk_pol = 1,
.ts_clk_gated = 0,
.if_clk_freq = 30400, /* 30.4 MHz */
.if_freq = 4000, /* 4.00 MHz */
.if_neg_center = 0,
.ext_adc = 0,
.adc_signed = 1,
.adc_vpp = 3, /* 2.0 Vpp */
.if_neg_edge = 1,
};
static struct tda18271_config prohdtv_pro2_tda18271_config = {
.gate = TDA18271_GATE_ANALOG,
.output_opt = TDA18271_OUTPUT_LT_OFF,
};
static struct tda18271_std_map kworld_tda18271_std_map = {
.atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 3,
.if_lvl = 6, .rfagc_top = 0x37 },
.qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
.if_lvl = 6, .rfagc_top = 0x37 },
};
static struct tda18271_config kworld_pc150u_tda18271_config = {
.std_map = &kworld_tda18271_std_map,
.gate = TDA18271_GATE_ANALOG,
.output_opt = TDA18271_OUTPUT_LT_OFF,
.config = 3, /* Use tuner callback for AGC */
.rf_cal_on_startup = 1
};
static struct s5h1411_config kworld_s5h1411_config = {
.output_mode = S5H1411_PARALLEL_OUTPUT,
.gpio = S5H1411_GPIO_OFF,
.qam_if = S5H1411_IF_4000,
.vsb_if = S5H1411_IF_3250,
.inversion = S5H1411_INVERSION_ON,
.status_mode = S5H1411_DEMODLOCKING,
.mpeg_timing =
S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
static struct tda18271_config hdtv200h_tda18271_config = {
.gate = TDA18271_GATE_ANALOG,
.config = 3 /* Use tuner callback for AGC */
};
static struct s5h1411_config hdtv200h_s5h1411_config = {
.output_mode = S5H1411_PARALLEL_OUTPUT,
.gpio = S5H1411_GPIO_OFF,
.qam_if = S5H1411_IF_4000,
.vsb_if = S5H1411_IF_3250,
.inversion = S5H1411_INVERSION_ON,
.status_mode = S5H1411_DEMODLOCKING,
.mpeg_timing =
S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
};
/* ==================================================================
* Core code
*/
static int dvb_init(struct saa7134_dev *dev)
{
int ret;
int attach_xc3028 = 0;
struct vb2_dvb_frontend *fe0;
struct vb2_queue *q;
/* FIXME: add support for multi-frontend */
mutex_init(&dev->frontends.lock);
INIT_LIST_HEAD(&dev->frontends.felist);
pr_info("%s() allocating 1 frontend\n", __func__);
fe0 = vb2_dvb_alloc_frontend(&dev->frontends, 1);
if (!fe0) {
pr_err("%s() failed to alloc\n", __func__);
return -ENOMEM;
}
/* init struct vb2_dvb */
dev->ts.nr_bufs = 32;
dev->ts.nr_packets = 32*4;
fe0->dvb.name = dev->name;
q = &fe0->dvb.dvbq;
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
q->io_modes = VB2_MMAP | VB2_READ;
q->drv_priv = &dev->ts_q;
q->ops = &saa7134_ts_qops;
q->mem_ops = &vb2_dma_sg_memops;
q->buf_struct_size = sizeof(struct saa7134_buf);
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &dev->lock;
q->dev = &dev->pci->dev;
ret = vb2_queue_init(q);
if (ret) {
vb2_dvb_dealloc_frontends(&dev->frontends);
return ret;
}
switch (dev->board) {
case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL:
pr_debug("pinnacle 300i dvb setup\n");
fe0->dvb.frontend = dvb_attach(mt352_attach, &pinnacle_300i,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
fe0->dvb.frontend->ops.tuner_ops.set_params = mt352_pinnacle_tuner_set_params;
}
break;
case SAA7134_BOARD_AVERMEDIA_777:
case SAA7134_BOARD_AVERMEDIA_A16AR:
pr_debug("avertv 777 dvb setup\n");
fe0->dvb.frontend = dvb_attach(mt352_attach, &avermedia_777,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0x61,
TUNER_PHILIPS_TD1316);
}
break;
case SAA7134_BOARD_AVERMEDIA_A16D:
pr_debug("AverMedia A16D dvb setup\n");
fe0->dvb.frontend = dvb_attach(mt352_attach,
&avermedia_xc3028_mt352_dev,
&dev->i2c_adap);
attach_xc3028 = 1;
break;
case SAA7134_BOARD_MD7134:
fe0->dvb.frontend = dvb_attach(tda10046_attach,
&medion_cardbus,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
/*
* The TV tuner on this board is actually NOT
* behind the demod i2c gate.
* However, the demod EEPROM is indeed there and it
* conflicts with the SAA7134 chip config EEPROM
* if the i2c gate is open (since they have same
* bus addresses) resulting in card PCI SVID / SSID
* being garbage after a reboot from time to time.
*
* Let's just leave the gate permanently closed -
* saa7134_i2c_eeprom_md7134_gate() will close it for
* us at probe time if it was open for some reason.
*/
fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&dev->i2c_adap, medion_cardbus.tuner_address,
TUNER_PHILIPS_FMD1216ME_MK3);
}
break;
case SAA7134_BOARD_PHILIPS_TOUGH:
fe0->dvb.frontend = dvb_attach(tda10046_attach,
&philips_tu1216_60_config,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
fe0->dvb.frontend->ops.tuner_ops.init = philips_tu1216_init;
fe0->dvb.frontend->ops.tuner_ops.set_params = philips_tda6651_pll_set;
}
break;
case SAA7134_BOARD_FLYDVBTDUO:
case SAA7134_BOARD_FLYDVBT_DUO_CARDBUS:
if (configure_tda827x_fe(dev, &tda827x_lifeview_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_PHILIPS_EUROPA:
case SAA7134_BOARD_VIDEOMATE_DVBT_300:
case SAA7134_BOARD_ASUS_EUROPA_HYBRID:
fe0->dvb.frontend = dvb_attach(tda10046_attach,
&philips_europa_config,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
dev->original_demod_sleep = fe0->dvb.frontend->ops.sleep;
fe0->dvb.frontend->ops.sleep = philips_europa_demod_sleep;
fe0->dvb.frontend->ops.tuner_ops.init = philips_europa_tuner_init;
fe0->dvb.frontend->ops.tuner_ops.sleep = philips_europa_tuner_sleep;
fe0->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params;
}
break;
case SAA7134_BOARD_TECHNOTREND_BUDGET_T3000:
fe0->dvb.frontend = dvb_attach(tda10046_attach,
&technotrend_budget_t3000_config,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
dev->original_demod_sleep = fe0->dvb.frontend->ops.sleep;
fe0->dvb.frontend->ops.sleep = philips_europa_demod_sleep;
fe0->dvb.frontend->ops.tuner_ops.init = philips_europa_tuner_init;
fe0->dvb.frontend->ops.tuner_ops.sleep = philips_europa_tuner_sleep;
fe0->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params;
}
break;
case SAA7134_BOARD_VIDEOMATE_DVBT_200:
fe0->dvb.frontend = dvb_attach(tda10046_attach,
&philips_tu1216_61_config,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
fe0->dvb.frontend->ops.tuner_ops.init = philips_tu1216_init;
fe0->dvb.frontend->ops.tuner_ops.set_params = philips_tda6651_pll_set;
}
break;
case SAA7134_BOARD_KWORLD_DVBT_210:
if (configure_tda827x_fe(dev, &kworld_dvb_t_210_config,
&tda827x_cfg_2) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_HAUPPAUGE_HVR1120:
fe0->dvb.frontend = dvb_attach(tda10048_attach,
&hcw_tda10048_config,
&dev->i2c_adap);
if (fe0->dvb.frontend != NULL) {
dvb_attach(tda829x_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0x4b,
&tda829x_no_probe);
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_adap,
&hcw_tda18271_config);
}
break;
case SAA7134_BOARD_PHILIPS_TIGER:
if (configure_tda827x_fe(dev, &philips_tiger_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_PINNACLE_PCTV_310i:
if (configure_tda827x_fe(dev, &pinnacle_pctv_310i_config,
&tda827x_cfg_1) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_HAUPPAUGE_HVR1110:
if (configure_tda827x_fe(dev, &hauppauge_hvr_1110_config,
&tda827x_cfg_1) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_HAUPPAUGE_HVR1150:
fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
&hcw_lgdt3305_config,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
dvb_attach(tda829x_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0x4b,
&tda829x_no_probe);
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_adap,
&hcw_tda18271_config);
}
break;
case SAA7134_BOARD_ASUSTeK_P7131_DUAL:
if (configure_tda827x_fe(dev, &asus_p7131_dual_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_FLYDVBT_LR301:
if (configure_tda827x_fe(dev, &tda827x_lifeview_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_FLYDVB_TRIO:
if (!use_frontend) { /* terrestrial */
if (configure_tda827x_fe(dev, &lifeview_trio_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
} else { /* satellite */
fe0->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, &dev->i2c_adap);
if (fe0->dvb.frontend) {
if (dvb_attach(tda826x_attach, fe0->dvb.frontend, 0x63,
&dev->i2c_adap, 0) == NULL) {
pr_warn("%s: Lifeview Trio, No tda826x found!\n",
__func__);
goto detach_frontend;
}
if (dvb_attach(isl6421_attach, fe0->dvb.frontend,
&dev->i2c_adap,
0x08, 0, 0, false) == NULL) {
pr_warn("%s: Lifeview Trio, No ISL6421 found!\n",
__func__);
goto detach_frontend;
}
}
}
break;
case SAA7134_BOARD_ADS_DUO_CARDBUS_PTV331:
case SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS:
fe0->dvb.frontend = dvb_attach(tda10046_attach,
&ads_tech_duo_config,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
if (dvb_attach(tda827x_attach,fe0->dvb.frontend,
ads_tech_duo_config.tuner_address, &dev->i2c_adap,
&ads_duo_cfg) == NULL) {
pr_warn("no tda827x tuner found at addr: %02x\n",
ads_tech_duo_config.tuner_address);
goto detach_frontend;
}
} else
pr_warn("failed to attach tda10046\n");
break;
case SAA7134_BOARD_TEVION_DVBT_220RF:
if (configure_tda827x_fe(dev, &tevion_dvbt220rf_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_MEDION_MD8800_QUADRO:
if (!use_frontend) { /* terrestrial */
if (configure_tda827x_fe(dev, &md8800_dvbt_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
} else { /* satellite */
fe0->dvb.frontend = dvb_attach(tda10086_attach,
&flydvbs, &dev->i2c_adap);
if (fe0->dvb.frontend) {
struct dvb_frontend *fe = fe0->dvb.frontend;
u8 dev_id = dev->eedata[2];
u8 data = 0xc4;
struct i2c_msg msg = {.addr = 0x08, .flags = 0, .len = 1};
if (dvb_attach(tda826x_attach, fe0->dvb.frontend,
0x60, &dev->i2c_adap, 0) == NULL) {
pr_warn("%s: Medion Quadro, no tda826x found !\n",
__func__);
goto detach_frontend;
}
if (dev_id != 0x08) {
/* we need to open the i2c gate (we know it exists) */
fe->ops.i2c_gate_ctrl(fe, 1);
if (dvb_attach(isl6405_attach, fe,
&dev->i2c_adap, 0x08, 0, 0) == NULL) {
pr_warn("%s: Medion Quadro, no ISL6405 found !\n",
__func__);
goto detach_frontend;
}
if (dev_id == 0x07) {
/* fire up the 2nd section of the LNB supply since
we can't do this from the other section */
msg.buf = &data;
i2c_transfer(&dev->i2c_adap, &msg, 1);
}
fe->ops.i2c_gate_ctrl(fe, 0);
dev->original_set_voltage = fe->ops.set_voltage;
fe->ops.set_voltage = md8800_set_voltage;
dev->original_set_high_voltage = fe->ops.enable_high_lnb_voltage;
fe->ops.enable_high_lnb_voltage = md8800_set_high_voltage;
} else {
fe->ops.set_voltage = md8800_set_voltage2;
fe->ops.enable_high_lnb_voltage = md8800_set_high_voltage2;
}
}
}
break;
case SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180:
fe0->dvb.frontend = dvb_attach(nxt200x_attach, &avertvhda180,
&dev->i2c_adap);
if (fe0->dvb.frontend)
dvb_attach(dvb_pll_attach, fe0->dvb.frontend, 0x61,
NULL, DVB_PLL_TDHU2);
break;
case SAA7134_BOARD_ADS_INSTANT_HDTV_PCI:
case SAA7134_BOARD_KWORLD_ATSC110:
fe0->dvb.frontend = dvb_attach(nxt200x_attach, &kworldatsc110,
&dev->i2c_adap);
if (fe0->dvb.frontend)
dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0x61,
TUNER_PHILIPS_TUV1236D);
break;
case SAA7134_BOARD_KWORLD_PC150U:
saa7134_set_gpio(dev, 18, 1); /* Switch to digital mode */
saa7134_tuner_callback(dev, 0,
TDA18271_CALLBACK_CMD_AGC_ENABLE, 1);
fe0->dvb.frontend = dvb_attach(s5h1411_attach,
&kworld_s5h1411_config,
&dev->i2c_adap);
if (fe0->dvb.frontend != NULL) {
dvb_attach(tda829x_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0x4b,
&tda829x_no_probe);
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_adap,
&kworld_pc150u_tda18271_config);
}
break;
case SAA7134_BOARD_FLYDVBS_LR300:
fe0->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
if (dvb_attach(tda826x_attach, fe0->dvb.frontend, 0x60,
&dev->i2c_adap, 0) == NULL) {
pr_warn("%s: No tda826x found!\n", __func__);
goto detach_frontend;
}
if (dvb_attach(isl6421_attach, fe0->dvb.frontend,
&dev->i2c_adap,
0x08, 0, 0, false) == NULL) {
pr_warn("%s: No ISL6421 found!\n", __func__);
goto detach_frontend;
}
}
break;
case SAA7134_BOARD_ASUS_EUROPA2_HYBRID:
fe0->dvb.frontend = dvb_attach(tda10046_attach,
&medion_cardbus,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
dev->original_demod_sleep = fe0->dvb.frontend->ops.sleep;
fe0->dvb.frontend->ops.sleep = philips_europa_demod_sleep;
dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&dev->i2c_adap, medion_cardbus.tuner_address,
TUNER_PHILIPS_FMD1216ME_MK3);
}
break;
case SAA7134_BOARD_VIDEOMATE_DVBT_200A:
fe0->dvb.frontend = dvb_attach(tda10046_attach,
&philips_europa_config,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
fe0->dvb.frontend->ops.tuner_ops.init = philips_td1316_tuner_init;
fe0->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params;
}
break;
case SAA7134_BOARD_CINERGY_HT_PCMCIA:
if (configure_tda827x_fe(dev, &cinergy_ht_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_CINERGY_HT_PCI:
if (configure_tda827x_fe(dev, &cinergy_ht_pci_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_PHILIPS_TIGER_S:
if (configure_tda827x_fe(dev, &philips_tiger_s_config,
&tda827x_cfg_2) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_ASUS_P7131_4871:
if (configure_tda827x_fe(dev, &asus_p7131_4871_config,
&tda827x_cfg_2) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_ASUSTeK_P7131_HYBRID_LNA:
if (configure_tda827x_fe(dev, &asus_p7131_hybrid_lna_config,
&tda827x_cfg_2) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_AVERMEDIA_SUPER_007:
if (configure_tda827x_fe(dev, &avermedia_super_007_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_TWINHAN_DTV_DVB_3056:
if (configure_tda827x_fe(dev, &twinhan_dtv_dvb_3056_config,
&tda827x_cfg_2_sw42) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_PHILIPS_SNAKE:
fe0->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
if (dvb_attach(tda826x_attach, fe0->dvb.frontend, 0x60,
&dev->i2c_adap, 0) == NULL) {
pr_warn("%s: No tda826x found!\n", __func__);
goto detach_frontend;
}
if (dvb_attach(lnbp21_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0, 0) == NULL) {
pr_warn("%s: No lnbp21 found!\n", __func__);
goto detach_frontend;
}
}
break;
case SAA7134_BOARD_CREATIX_CTX953:
if (configure_tda827x_fe(dev, &md8800_dvbt_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_MSI_TVANYWHERE_AD11:
if (configure_tda827x_fe(dev, &philips_tiger_s_config,
&tda827x_cfg_2) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_AVERMEDIA_CARDBUS_506:
pr_debug("AverMedia E506R dvb setup\n");
saa7134_set_gpio(dev, 25, 0);
msleep(10);
saa7134_set_gpio(dev, 25, 1);
fe0->dvb.frontend = dvb_attach(mt352_attach,
&avermedia_xc3028_mt352_dev,
&dev->i2c_adap);
attach_xc3028 = 1;
break;
case SAA7134_BOARD_MD7134_BRIDGE_2:
fe0->dvb.frontend = dvb_attach(tda10086_attach,
&sd1878_4m, &dev->i2c_adap);
if (fe0->dvb.frontend) {
struct dvb_frontend *fe;
if (dvb_attach(dvb_pll_attach, fe0->dvb.frontend, 0x60,
&dev->i2c_adap, DVB_PLL_PHILIPS_SD1878_TDA8261) == NULL) {
pr_warn("%s: MD7134 DVB-S, no SD1878 found !\n",
__func__);
goto detach_frontend;
}
/* we need to open the i2c gate (we know it exists) */
fe = fe0->dvb.frontend;
fe->ops.i2c_gate_ctrl(fe, 1);
if (dvb_attach(isl6405_attach, fe,
&dev->i2c_adap, 0x08, 0, 0) == NULL) {
pr_warn("%s: MD7134 DVB-S, no ISL6405 found !\n",
__func__);
goto detach_frontend;
}
fe->ops.i2c_gate_ctrl(fe, 0);
dev->original_set_voltage = fe->ops.set_voltage;
fe->ops.set_voltage = md8800_set_voltage;
dev->original_set_high_voltage = fe->ops.enable_high_lnb_voltage;
fe->ops.enable_high_lnb_voltage = md8800_set_high_voltage;
}
break;
case SAA7134_BOARD_AVERMEDIA_M103:
saa7134_set_gpio(dev, 25, 0);
msleep(10);
saa7134_set_gpio(dev, 25, 1);
fe0->dvb.frontend = dvb_attach(mt352_attach,
&avermedia_xc3028_mt352_dev,
&dev->i2c_adap);
attach_xc3028 = 1;
break;
case SAA7134_BOARD_ASUSTeK_TIGER_3IN1:
if (!use_frontend) { /* terrestrial */
if (configure_tda827x_fe(dev, &asus_tiger_3in1_config,
&tda827x_cfg_2) < 0)
goto detach_frontend;
} else { /* satellite */
fe0->dvb.frontend = dvb_attach(tda10086_attach,
&flydvbs, &dev->i2c_adap);
if (fe0->dvb.frontend) {
if (dvb_attach(tda826x_attach,
fe0->dvb.frontend, 0x60,
&dev->i2c_adap, 0) == NULL) {
pr_warn("%s: Asus Tiger 3in1, no tda826x found!\n",
__func__);
goto detach_frontend;
}
if (dvb_attach(lnbp21_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0, 0) == NULL) {
pr_warn("%s: Asus Tiger 3in1, no lnbp21 found!\n",
__func__);
goto detach_frontend;
}
}
}
break;
case SAA7134_BOARD_ASUSTeK_PS3_100:
if (!use_frontend) { /* terrestrial */
if (configure_tda827x_fe(dev, &asus_ps3_100_config,
&tda827x_cfg_2) < 0)
goto detach_frontend;
} else { /* satellite */
fe0->dvb.frontend = dvb_attach(tda10086_attach,
&flydvbs, &dev->i2c_adap);
if (fe0->dvb.frontend) {
if (dvb_attach(tda826x_attach,
fe0->dvb.frontend, 0x60,
&dev->i2c_adap, 0) == NULL) {
pr_warn("%s: Asus My Cinema PS3-100, no tda826x found!\n",
__func__);
goto detach_frontend;
}
if (dvb_attach(lnbp21_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0, 0) == NULL) {
pr_warn("%s: Asus My Cinema PS3-100, no lnbp21 found!\n",
__func__);
goto detach_frontend;
}
}
}
break;
case SAA7134_BOARD_ASUSTeK_TIGER:
if (configure_tda827x_fe(dev, &philips_tiger_config,
&tda827x_cfg_0) < 0)
goto detach_frontend;
break;
case SAA7134_BOARD_BEHOLD_H6:
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&behold_h6_config,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0x61,
TUNER_PHILIPS_FMD1216MEX_MK3);
}
break;
case SAA7134_BOARD_BEHOLD_X7:
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&behold_x7_config,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
dvb_attach(xc5000_attach, fe0->dvb.frontend,
&dev->i2c_adap, &behold_x7_tunerconfig);
}
break;
case SAA7134_BOARD_BEHOLD_H7:
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&behold_x7_config,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
dvb_attach(xc5000_attach, fe0->dvb.frontend,
&dev->i2c_adap, &behold_x7_tunerconfig);
}
break;
case SAA7134_BOARD_AVERMEDIA_A700_PRO:
case SAA7134_BOARD_AVERMEDIA_A700_HYBRID:
/* Zarlink ZL10313 */
fe0->dvb.frontend = dvb_attach(mt312_attach,
&avertv_a700_mt312, &dev->i2c_adap);
if (fe0->dvb.frontend) {
if (dvb_attach(zl10036_attach, fe0->dvb.frontend,
&avertv_a700_tuner, &dev->i2c_adap) == NULL) {
pr_warn("%s: No zl10036 found!\n",
__func__);
}
}
break;
case SAA7134_BOARD_VIDEOMATE_S350:
fe0->dvb.frontend = dvb_attach(mt312_attach,
&zl10313_compro_s350_config, &dev->i2c_adap);
if (fe0->dvb.frontend)
if (dvb_attach(zl10039_attach, fe0->dvb.frontend,
0x60, &dev->i2c_adap) == NULL)
pr_warn("%s: No zl10039 found!\n",
__func__);
break;
case SAA7134_BOARD_VIDEOMATE_T750:
fe0->dvb.frontend = dvb_attach(zl10353_attach,
&videomate_t750_zl10353_config,
&dev->i2c_adap);
if (fe0->dvb.frontend != NULL) {
if (dvb_attach(qt1010_attach,
fe0->dvb.frontend,
&dev->i2c_adap,
&videomate_t750_qt1010_config) == NULL)
pr_warn("error attaching QT1010\n");
}
break;
case SAA7134_BOARD_ZOLID_HYBRID_PCI:
fe0->dvb.frontend = dvb_attach(tda10048_attach,
&zolid_tda10048_config,
&dev->i2c_adap);
if (fe0->dvb.frontend != NULL) {
dvb_attach(tda829x_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0x4b,
&tda829x_no_probe);
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_adap,
&zolid_tda18271_config);
}
break;
case SAA7134_BOARD_LEADTEK_WINFAST_DTV1000S:
fe0->dvb.frontend = dvb_attach(tda10048_attach,
&dtv1000s_tda10048_config,
&dev->i2c_adap);
if (fe0->dvb.frontend != NULL) {
dvb_attach(tda829x_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0x4b,
&tda829x_no_probe);
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_adap,
&dtv1000s_tda18271_config);
}
break;
case SAA7134_BOARD_KWORLD_PCI_SBTVD_FULLSEG:
/* Switch to digital mode */
saa7134_tuner_callback(dev, 0,
TDA18271_CALLBACK_CMD_AGC_ENABLE, 1);
fe0->dvb.frontend = dvb_attach(mb86a20s_attach,
&kworld_mb86a20s_config,
&dev->i2c_adap);
if (fe0->dvb.frontend != NULL) {
dvb_attach(tda829x_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0x4b,
&tda829x_no_probe);
fe0->dvb.frontend->ops.i2c_gate_ctrl = kworld_sbtvd_gate_ctrl;
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_adap,
&kworld_tda18271_config);
}
/* mb86a20s need to use the I2C gateway */
break;
case SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2:
fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
&prohdtv_pro2_lgs8g75_config,
&dev->i2c_adap);
if (fe0->dvb.frontend != NULL) {
dvb_attach(tda829x_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0x4b,
&tda829x_no_probe);
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_adap,
&prohdtv_pro2_tda18271_config);
}
break;
case SAA7134_BOARD_AVERMEDIA_A706:
/* Enable all DVB-S devices now */
/* CE5039 DVB-S tuner SLEEP pin low */
saa7134_set_gpio(dev, 23, 0);
/* CE6313 DVB-S demod SLEEP pin low */
saa7134_set_gpio(dev, 9, 0);
/* CE6313 DVB-S demod RESET# pin high */
saa7134_set_gpio(dev, 25, 1);
msleep(1);
fe0->dvb.frontend = dvb_attach(mt312_attach,
&zl10313_avermedia_a706_config, &dev->i2c_adap);
if (fe0->dvb.frontend) {
fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
if (dvb_attach(zl10039_attach, fe0->dvb.frontend,
0x60, &dev->i2c_adap) == NULL)
pr_warn("%s: No zl10039 found!\n",
__func__);
}
break;
case SAA7134_BOARD_LEADTEK_WINFAST_HDTV200_H:
fe0->dvb.frontend = dvb_attach(s5h1411_attach,
&hdtv200h_s5h1411_config,
&dev->i2c_adap);
if (fe0->dvb.frontend) {
dvb_attach(tda829x_attach, fe0->dvb.frontend,
&dev->i2c_adap, 0x4b,
&tda829x_no_probe);
dvb_attach(tda18271_attach, fe0->dvb.frontend,
0x60, &dev->i2c_adap,
&hdtv200h_tda18271_config);
}
break;
default:
pr_warn("Huh? unknown DVB card?\n");
break;
}
if (attach_xc3028) {
struct dvb_frontend *fe;
struct xc2028_config cfg = {
.i2c_adap = &dev->i2c_adap,
.i2c_addr = 0x61,
};
if (!fe0->dvb.frontend)
goto detach_frontend;
fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, &cfg);
if (!fe) {
pr_err("%s/2: xc3028 attach failed\n",
dev->name);
goto detach_frontend;
}
}
if (NULL == fe0->dvb.frontend) {
pr_err("%s/dvb: frontend initialization failed\n", dev->name);
goto detach_frontend;
}
/* define general-purpose callback pointer */
fe0->dvb.frontend->callback = saa7134_tuner_callback;
/* register everything else */
#ifndef CONFIG_MEDIA_CONTROLLER_DVB
ret = vb2_dvb_register_bus(&dev->frontends, THIS_MODULE, dev,
&dev->pci->dev, NULL,
adapter_nr, 0);
#else
ret = vb2_dvb_register_bus(&dev->frontends, THIS_MODULE, dev,
&dev->pci->dev, dev->media_dev,
adapter_nr, 0);
#endif
/* this sequence is necessary to make the tda1004x load its firmware
* and to enter analog mode of hybrid boards
*/
if (!ret) {
if (fe0->dvb.frontend->ops.init)
fe0->dvb.frontend->ops.init(fe0->dvb.frontend);
if (fe0->dvb.frontend->ops.sleep)
fe0->dvb.frontend->ops.sleep(fe0->dvb.frontend);
if (fe0->dvb.frontend->ops.tuner_ops.sleep)
fe0->dvb.frontend->ops.tuner_ops.sleep(fe0->dvb.frontend);
}
return ret;
detach_frontend:
vb2_dvb_dealloc_frontends(&dev->frontends);
vb2_queue_release(&fe0->dvb.dvbq);
return -EINVAL;
}
static int dvb_fini(struct saa7134_dev *dev)
{
struct vb2_dvb_frontend *fe0;
/* Get the first frontend */
fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
if (!fe0)
return -EINVAL;
/* FIXME: I suspect that this code is bogus, since the entry for
Pinnacle 300I DVB-T PAL already defines the proper init to allow
the detection of mt2032 (TDA9887_PORT2_INACTIVE)
*/
if (dev->board == SAA7134_BOARD_PINNACLE_300I_DVBT_PAL) {
struct v4l2_priv_tun_config tda9887_cfg;
static int on = TDA9887_PRESENT | TDA9887_PORT2_INACTIVE;
tda9887_cfg.tuner = TUNER_TDA9887;
tda9887_cfg.priv = &on;
/* otherwise we don't detect the tuner on next insmod */
saa_call_all(dev, tuner, s_config, &tda9887_cfg);
} else if (dev->board == SAA7134_BOARD_MEDION_MD8800_QUADRO) {
if ((dev->eedata[2] == 0x07) && use_frontend) {
/* turn off the 2nd lnb supply */
u8 data = 0x80;
struct i2c_msg msg = {.addr = 0x08, .buf = &data, .flags = 0, .len = 1};
struct dvb_frontend *fe;
fe = fe0->dvb.frontend;
if (fe->ops.i2c_gate_ctrl) {
fe->ops.i2c_gate_ctrl(fe, 1);
i2c_transfer(&dev->i2c_adap, &msg, 1);
fe->ops.i2c_gate_ctrl(fe, 0);
}
}
}
vb2_dvb_unregister_bus(&dev->frontends);
vb2_queue_release(&fe0->dvb.dvbq);
return 0;
}
static struct saa7134_mpeg_ops dvb_ops = {
.type = SAA7134_MPEG_DVB,
.init = dvb_init,
.fini = dvb_fini,
};
static int __init dvb_register(void)
{
return saa7134_ts_register(&dvb_ops);
}
static void __exit dvb_unregister(void)
{
saa7134_ts_unregister(&dvb_ops);
}
module_init(dvb_register);
module_exit(dvb_unregister);
| linux-master | drivers/media/pci/saa7134/saa7134-dvb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* device driver for philips saa7134 based TV cards
* video4linux video interface
*
* (c) 2001,02 Gerd Knorr <[email protected]> [SuSE Labs]
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
/* ------------------------------------------------------------------ */
static unsigned int vbi_debug;
module_param(vbi_debug, int, 0644);
MODULE_PARM_DESC(vbi_debug,"enable debug messages [vbi]");
static unsigned int vbibufs = 4;
module_param(vbibufs, int, 0444);
MODULE_PARM_DESC(vbibufs,"number of vbi buffers, range 2-32");
#define vbi_dbg(fmt, arg...) do { \
if (vbi_debug) \
printk(KERN_DEBUG pr_fmt("vbi: " fmt), ## arg); \
} while (0)
/* ------------------------------------------------------------------ */
#define VBI_LINE_COUNT 17
#define VBI_LINE_LENGTH 2048
#define VBI_SCALE 0x200
static void task_init(struct saa7134_dev *dev, struct saa7134_buf *buf,
int task)
{
struct saa7134_tvnorm *norm = dev->tvnorm;
/* setup video scaler */
saa_writeb(SAA7134_VBI_H_START1(task), norm->h_start & 0xff);
saa_writeb(SAA7134_VBI_H_START2(task), norm->h_start >> 8);
saa_writeb(SAA7134_VBI_H_STOP1(task), norm->h_stop & 0xff);
saa_writeb(SAA7134_VBI_H_STOP2(task), norm->h_stop >> 8);
saa_writeb(SAA7134_VBI_V_START1(task), norm->vbi_v_start_0 & 0xff);
saa_writeb(SAA7134_VBI_V_START2(task), norm->vbi_v_start_0 >> 8);
saa_writeb(SAA7134_VBI_V_STOP1(task), norm->vbi_v_stop_0 & 0xff);
saa_writeb(SAA7134_VBI_V_STOP2(task), norm->vbi_v_stop_0 >> 8);
saa_writeb(SAA7134_VBI_H_SCALE_INC1(task), VBI_SCALE & 0xff);
saa_writeb(SAA7134_VBI_H_SCALE_INC2(task), VBI_SCALE >> 8);
saa_writeb(SAA7134_VBI_PHASE_OFFSET_LUMA(task), 0x00);
saa_writeb(SAA7134_VBI_PHASE_OFFSET_CHROMA(task), 0x00);
saa_writeb(SAA7134_VBI_H_LEN1(task), dev->vbi_hlen & 0xff);
saa_writeb(SAA7134_VBI_H_LEN2(task), dev->vbi_hlen >> 8);
saa_writeb(SAA7134_VBI_V_LEN1(task), dev->vbi_vlen & 0xff);
saa_writeb(SAA7134_VBI_V_LEN2(task), dev->vbi_vlen >> 8);
saa_andorb(SAA7134_DATA_PATH(task), 0xc0, 0x00);
}
/* ------------------------------------------------------------------ */
static int buffer_activate(struct saa7134_dev *dev,
struct saa7134_buf *buf,
struct saa7134_buf *next)
{
struct saa7134_dmaqueue *dmaq = buf->vb2.vb2_buf.vb2_queue->drv_priv;
unsigned long control, base;
vbi_dbg("buffer_activate [%p]\n", buf);
buf->top_seen = 0;
task_init(dev, buf, TASK_A);
task_init(dev, buf, TASK_B);
saa_writeb(SAA7134_OFMT_DATA_A, 0x06);
saa_writeb(SAA7134_OFMT_DATA_B, 0x06);
/* DMA: setup channel 2+3 (= VBI Task A+B) */
base = saa7134_buffer_base(buf);
control = SAA7134_RS_CONTROL_BURST_16 |
SAA7134_RS_CONTROL_ME |
(dmaq->pt.dma >> 12);
saa_writel(SAA7134_RS_BA1(2), base);
saa_writel(SAA7134_RS_BA2(2), base + dev->vbi_hlen * dev->vbi_vlen);
saa_writel(SAA7134_RS_PITCH(2), dev->vbi_hlen);
saa_writel(SAA7134_RS_CONTROL(2), control);
saa_writel(SAA7134_RS_BA1(3), base);
saa_writel(SAA7134_RS_BA2(3), base + dev->vbi_hlen * dev->vbi_vlen);
saa_writel(SAA7134_RS_PITCH(3), dev->vbi_hlen);
saa_writel(SAA7134_RS_CONTROL(3), control);
/* start DMA */
saa7134_set_dmabits(dev);
mod_timer(&dmaq->timeout, jiffies + BUFFER_TIMEOUT);
return 0;
}
static int buffer_prepare(struct vb2_buffer *vb2)
{
struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2);
struct sg_table *dma = vb2_dma_sg_plane_desc(vb2, 0);
unsigned int size;
if (dma->sgl->offset) {
pr_err("The buffer is not page-aligned\n");
return -EINVAL;
}
size = dev->vbi_hlen * dev->vbi_vlen * 2;
if (vb2_plane_size(vb2, 0) < size)
return -EINVAL;
vb2_set_plane_payload(vb2, 0, size);
return saa7134_pgtable_build(dev->pci, &dmaq->pt, dma->sgl, dma->nents,
saa7134_buffer_startpage(buf));
}
static int queue_setup(struct vb2_queue *q,
unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct saa7134_dmaqueue *dmaq = q->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
unsigned int size;
dev->vbi_vlen = dev->tvnorm->vbi_v_stop_0 - dev->tvnorm->vbi_v_start_0 + 1;
if (dev->vbi_vlen > VBI_LINE_COUNT)
dev->vbi_vlen = VBI_LINE_COUNT;
dev->vbi_hlen = VBI_LINE_LENGTH;
size = dev->vbi_hlen * dev->vbi_vlen * 2;
*nbuffers = saa7134_buffer_count(size, *nbuffers);
*nplanes = 1;
sizes[0] = size;
return 0;
}
static int buffer_init(struct vb2_buffer *vb2)
{
struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2);
dmaq->curr = NULL;
buf->activate = buffer_activate;
return 0;
}
const struct vb2_ops saa7134_vbi_qops = {
.queue_setup = queue_setup,
.buf_init = buffer_init,
.buf_prepare = buffer_prepare,
.buf_queue = saa7134_vb2_buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = saa7134_vb2_start_streaming,
.stop_streaming = saa7134_vb2_stop_streaming,
};
/* ------------------------------------------------------------------ */
int saa7134_vbi_init1(struct saa7134_dev *dev)
{
INIT_LIST_HEAD(&dev->vbi_q.queue);
timer_setup(&dev->vbi_q.timeout, saa7134_buffer_timeout, 0);
dev->vbi_q.dev = dev;
if (vbibufs < 2)
vbibufs = 2;
if (vbibufs > VIDEO_MAX_FRAME)
vbibufs = VIDEO_MAX_FRAME;
return 0;
}
int saa7134_vbi_fini(struct saa7134_dev *dev)
{
/* nothing */
del_timer_sync(&dev->vbi_q.timeout);
return 0;
}
void saa7134_irq_vbi_done(struct saa7134_dev *dev, unsigned long status)
{
spin_lock(&dev->slock);
if (dev->vbi_q.curr) {
/* make sure we have seen both fields */
if ((status & 0x10) == 0x00) {
dev->vbi_q.curr->top_seen = 1;
goto done;
}
if (!dev->vbi_q.curr->top_seen)
goto done;
saa7134_buffer_finish(dev, &dev->vbi_q, VB2_BUF_STATE_DONE);
}
saa7134_buffer_next(dev, &dev->vbi_q);
done:
spin_unlock(&dev->slock);
}
| linux-master | drivers/media/pci/saa7134/saa7134-vbi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* device driver for philips saa7134 based TV cards
* tv audio decoder (fm stereo, nicam, ...)
*
* (c) 2001-03 Gerd Knorr <[email protected]> [SuSE Labs]
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/delay.h>
#include <linux/freezer.h>
#include <asm/div64.h>
/* ------------------------------------------------------------------ */
static unsigned int audio_debug;
module_param(audio_debug, int, 0644);
MODULE_PARM_DESC(audio_debug,"enable debug messages [tv audio]");
static unsigned int audio_ddep;
module_param(audio_ddep, int, 0644);
MODULE_PARM_DESC(audio_ddep,"audio ddep overwrite");
static int audio_clock_override = UNSET;
module_param(audio_clock_override, int, 0644);
static int audio_clock_tweak;
module_param(audio_clock_tweak, int, 0644);
MODULE_PARM_DESC(audio_clock_tweak, "Audio clock tick fine tuning for cards with audio crystal that's slightly off (range [-1024 .. 1024])");
#define audio_dbg(level, fmt, arg...) do { \
if (audio_debug >= level) \
printk(KERN_DEBUG pr_fmt("audio: " fmt), ## arg); \
} while (0)
/* msecs */
#define SCAN_INITIAL_DELAY 1000
#define SCAN_SAMPLE_DELAY 200
#define SCAN_SUBCARRIER_DELAY 2000
/* ------------------------------------------------------------------ */
/* saa7134 code */
static struct mainscan {
char *name;
v4l2_std_id std;
int carr;
} mainscan[] = {
{
.name = "MN",
.std = V4L2_STD_MN,
.carr = 4500,
},{
.name = "BGH",
.std = V4L2_STD_B | V4L2_STD_GH,
.carr = 5500,
},{
.name = "I",
.std = V4L2_STD_PAL_I,
.carr = 6000,
},{
.name = "DKL",
.std = V4L2_STD_DK | V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC,
.carr = 6500,
}
};
static struct saa7134_tvaudio tvaudio[] = {
{
.name = "PAL-B/G FM-stereo",
.std = V4L2_STD_PAL_BG,
.mode = TVAUDIO_FM_BG_STEREO,
.carr1 = 5500,
.carr2 = 5742,
},{
.name = "PAL-D/K1 FM-stereo",
.std = V4L2_STD_PAL_DK,
.carr1 = 6500,
.carr2 = 6258,
.mode = TVAUDIO_FM_BG_STEREO,
},{
.name = "PAL-D/K2 FM-stereo",
.std = V4L2_STD_PAL_DK,
.carr1 = 6500,
.carr2 = 6742,
.mode = TVAUDIO_FM_BG_STEREO,
},{
.name = "PAL-D/K3 FM-stereo",
.std = V4L2_STD_PAL_DK,
.carr1 = 6500,
.carr2 = 5742,
.mode = TVAUDIO_FM_BG_STEREO,
},{
.name = "PAL-B/G NICAM",
.std = V4L2_STD_PAL_BG,
.carr1 = 5500,
.carr2 = 5850,
.mode = TVAUDIO_NICAM_FM,
},{
.name = "PAL-I NICAM",
.std = V4L2_STD_PAL_I,
.carr1 = 6000,
.carr2 = 6552,
.mode = TVAUDIO_NICAM_FM,
},{
.name = "PAL-D/K NICAM",
.std = V4L2_STD_PAL_DK,
.carr1 = 6500,
.carr2 = 5850,
.mode = TVAUDIO_NICAM_FM,
},{
.name = "SECAM-L NICAM",
.std = V4L2_STD_SECAM_L,
.carr1 = 6500,
.carr2 = 5850,
.mode = TVAUDIO_NICAM_AM,
},{
.name = "SECAM-D/K NICAM",
.std = V4L2_STD_SECAM_DK,
.carr1 = 6500,
.carr2 = 5850,
.mode = TVAUDIO_NICAM_FM,
},{
.name = "NTSC-A2 FM-stereo",
.std = V4L2_STD_NTSC,
.carr1 = 4500,
.carr2 = 4724,
.mode = TVAUDIO_FM_K_STEREO,
},{
.name = "NTSC-M",
.std = V4L2_STD_NTSC,
.carr1 = 4500,
.carr2 = -1,
.mode = TVAUDIO_FM_MONO,
}
};
#define TVAUDIO ARRAY_SIZE(tvaudio)
/* ------------------------------------------------------------------ */
static u32 tvaudio_carr2reg(u32 carrier)
{
u64 a = carrier;
a <<= 24;
do_div(a,12288);
return a;
}
static void tvaudio_setcarrier(struct saa7134_dev *dev,
int primary, int secondary)
{
if (-1 == secondary)
secondary = primary;
saa_writel(SAA7134_CARRIER1_FREQ0 >> 2, tvaudio_carr2reg(primary));
saa_writel(SAA7134_CARRIER2_FREQ0 >> 2, tvaudio_carr2reg(secondary));
}
#define SAA7134_MUTE_MASK 0xbb
#define SAA7134_MUTE_ANALOG 0x04
#define SAA7134_MUTE_I2S 0x40
static void mute_input_7134(struct saa7134_dev *dev)
{
unsigned int mute;
struct saa7134_input *in;
int ausel=0, ics=0, ocs=0;
int mask;
/* look what is to do ... */
in = dev->input;
mute = (dev->ctl_mute ||
(dev->automute && (&card(dev).radio) != in));
if (card(dev).mute.type) {
/*
* 7130 - we'll mute using some unconnected audio input
* 7134 - we'll probably should switch external mux with gpio
*/
if (mute)
in = &card(dev).mute;
}
if (dev->hw_mute == mute &&
dev->hw_input == in && !dev->insuspend) {
audio_dbg(1, "mute/input: nothing to do [mute=%d,input=%s]\n",
mute, saa7134_input_name[in->type]);
return;
}
audio_dbg(1, "ctl_mute=%d automute=%d input=%s => mute=%d input=%s\n",
dev->ctl_mute, dev->automute,
saa7134_input_name[dev->input->type], mute,
saa7134_input_name[in->type]);
dev->hw_mute = mute;
dev->hw_input = in;
if (PCI_DEVICE_ID_PHILIPS_SAA7134 == dev->pci->device)
/* 7134 mute */
saa_writeb(SAA7134_AUDIO_MUTE_CTRL, mute ?
SAA7134_MUTE_MASK |
SAA7134_MUTE_ANALOG |
SAA7134_MUTE_I2S :
SAA7134_MUTE_MASK);
/* switch internal audio mux */
switch (in->amux) {
case TV: ausel=0xc0; ics=0x00; ocs=0x02; break;
case LINE1: ausel=0x80; ics=0x00; ocs=0x00; break;
case LINE2: ausel=0x80; ics=0x08; ocs=0x01; break;
case LINE2_LEFT: ausel=0x80; ics=0x08; ocs=0x05; break;
}
saa_andorb(SAA7134_AUDIO_FORMAT_CTRL, 0xc0, ausel);
saa_andorb(SAA7134_ANALOG_IO_SELECT, 0x08, ics);
saa_andorb(SAA7134_ANALOG_IO_SELECT, 0x07, ocs);
// for oss, we need to change the clock configuration
if (in->amux == TV)
saa_andorb(SAA7134_SIF_SAMPLE_FREQ, 0x03, 0x00);
else
saa_andorb(SAA7134_SIF_SAMPLE_FREQ, 0x03, 0x01);
/* switch gpio-connected external audio mux */
if (0 == card(dev).gpiomask)
return;
mask = card(dev).gpiomask;
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, mask, mask);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, mask, in->gpio);
saa7134_track_gpio(dev, saa7134_input_name[in->type]);
}
static void tvaudio_setmode(struct saa7134_dev *dev,
struct saa7134_tvaudio *audio,
char *note)
{
int acpf, tweak = 0;
if (dev->tvnorm->id == V4L2_STD_NTSC) {
acpf = 0x19066;
} else {
acpf = 0x1e000;
}
if (audio_clock_tweak > -1024 && audio_clock_tweak < 1024)
tweak = audio_clock_tweak;
if (note)
audio_dbg(1, "tvaudio_setmode: %s %s [%d.%03d/%d.%03d MHz] acpf=%d%+d\n",
note, audio->name,
audio->carr1 / 1000, audio->carr1 % 1000,
audio->carr2 / 1000, audio->carr2 % 1000,
acpf, tweak);
acpf += tweak;
saa_writeb(SAA7134_AUDIO_CLOCKS_PER_FIELD0, (acpf & 0x0000ff) >> 0);
saa_writeb(SAA7134_AUDIO_CLOCKS_PER_FIELD1, (acpf & 0x00ff00) >> 8);
saa_writeb(SAA7134_AUDIO_CLOCKS_PER_FIELD2, (acpf & 0x030000) >> 16);
tvaudio_setcarrier(dev,audio->carr1,audio->carr2);
switch (audio->mode) {
case TVAUDIO_FM_MONO:
case TVAUDIO_FM_BG_STEREO:
saa_writeb(SAA7134_DEMODULATOR, 0x00);
saa_writeb(SAA7134_DCXO_IDENT_CTRL, 0x00);
saa_writeb(SAA7134_FM_DEEMPHASIS, 0x22);
saa_writeb(SAA7134_FM_DEMATRIX, 0x80);
saa_writeb(SAA7134_STEREO_DAC_OUTPUT_SELECT, 0xa0);
break;
case TVAUDIO_FM_K_STEREO:
saa_writeb(SAA7134_DEMODULATOR, 0x00);
saa_writeb(SAA7134_DCXO_IDENT_CTRL, 0x01);
saa_writeb(SAA7134_FM_DEEMPHASIS, 0x22);
saa_writeb(SAA7134_FM_DEMATRIX, 0x80);
saa_writeb(SAA7134_STEREO_DAC_OUTPUT_SELECT, 0xa0);
break;
case TVAUDIO_NICAM_FM:
saa_writeb(SAA7134_DEMODULATOR, 0x10);
saa_writeb(SAA7134_DCXO_IDENT_CTRL, 0x00);
saa_writeb(SAA7134_FM_DEEMPHASIS, 0x44);
saa_writeb(SAA7134_STEREO_DAC_OUTPUT_SELECT, 0xa1);
saa_writeb(SAA7134_NICAM_CONFIG, 0x00);
break;
case TVAUDIO_NICAM_AM:
saa_writeb(SAA7134_DEMODULATOR, 0x12);
saa_writeb(SAA7134_DCXO_IDENT_CTRL, 0x00);
saa_writeb(SAA7134_FM_DEEMPHASIS, 0x44);
saa_writeb(SAA7134_STEREO_DAC_OUTPUT_SELECT, 0xa1);
saa_writeb(SAA7134_NICAM_CONFIG, 0x00);
break;
case TVAUDIO_FM_SAT_STEREO:
/* not implemented (yet) */
break;
}
}
static int tvaudio_sleep(struct saa7134_dev *dev, int timeout)
{
if (dev->thread.scan1 == dev->thread.scan2 &&
!kthread_should_stop()) {
if (timeout < 0) {
set_current_state(TASK_INTERRUPTIBLE);
schedule();
} else {
schedule_timeout_interruptible
(msecs_to_jiffies(timeout));
}
}
return dev->thread.scan1 != dev->thread.scan2;
}
static int tvaudio_checkcarrier(struct saa7134_dev *dev, struct mainscan *scan)
{
__s32 left,right,value;
if (!(dev->tvnorm->id & scan->std)) {
audio_dbg(1, "skipping %d.%03d MHz [%4s]\n",
scan->carr / 1000, scan->carr % 1000, scan->name);
return 0;
}
if (audio_debug > 1) {
int i;
audio_dbg(1, "debug %d:", scan->carr);
for (i = -150; i <= 150; i += 30) {
tvaudio_setcarrier(dev,scan->carr+i,scan->carr+i);
saa_readl(SAA7134_LEVEL_READOUT1 >> 2);
if (tvaudio_sleep(dev,SCAN_SAMPLE_DELAY))
return -1;
value = saa_readl(SAA7134_LEVEL_READOUT1 >> 2);
if (0 == i)
pr_cont(" # %6d # ", value >> 16);
else
pr_cont(" %6d", value >> 16);
}
pr_cont("\n");
}
tvaudio_setcarrier(dev,scan->carr-90,scan->carr-90);
saa_readl(SAA7134_LEVEL_READOUT1 >> 2);
if (tvaudio_sleep(dev,SCAN_SAMPLE_DELAY))
return -1;
left = saa_readl(SAA7134_LEVEL_READOUT1 >> 2);
tvaudio_setcarrier(dev,scan->carr+90,scan->carr+90);
saa_readl(SAA7134_LEVEL_READOUT1 >> 2);
if (tvaudio_sleep(dev,SCAN_SAMPLE_DELAY))
return -1;
right = saa_readl(SAA7134_LEVEL_READOUT1 >> 2);
left >>= 16;
right >>= 16;
value = left > right ? left - right : right - left;
audio_dbg(1, "scanning %d.%03d MHz [%4s] => dc is %5d [%d/%d]\n",
scan->carr / 1000, scan->carr % 1000,
scan->name, value, left, right);
return value;
}
static int tvaudio_getstereo(struct saa7134_dev *dev, struct saa7134_tvaudio *audio)
{
__u32 idp, nicam, nicam_status;
int retval = -1;
switch (audio->mode) {
case TVAUDIO_FM_MONO:
return V4L2_TUNER_SUB_MONO;
case TVAUDIO_FM_K_STEREO:
case TVAUDIO_FM_BG_STEREO:
idp = (saa_readb(SAA7134_IDENT_SIF) & 0xe0) >> 5;
audio_dbg(1, "getstereo: fm/stereo: idp=0x%x\n", idp);
if (0x03 == (idp & 0x03))
retval = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
else if (0x05 == (idp & 0x05))
retval = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
else if (0x01 == (idp & 0x01))
retval = V4L2_TUNER_SUB_MONO;
break;
case TVAUDIO_FM_SAT_STEREO:
/* not implemented (yet) */
break;
case TVAUDIO_NICAM_FM:
case TVAUDIO_NICAM_AM:
nicam = saa_readb(SAA7134_AUDIO_STATUS);
audio_dbg(1, "getstereo: nicam=0x%x\n", nicam);
if (nicam & 0x1) {
nicam_status = saa_readb(SAA7134_NICAM_STATUS);
audio_dbg(1, "getstereo: nicam_status=0x%x\n",
nicam_status);
switch (nicam_status & 0x03) {
case 0x01:
retval = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
break;
case 0x02:
retval = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
break;
default:
retval = V4L2_TUNER_SUB_MONO;
}
} else {
/* No nicam detected */
}
break;
}
if (retval != -1)
audio_dbg(1, "found audio subchannels:%s%s%s%s\n",
(retval & V4L2_TUNER_SUB_MONO) ? " mono" : "",
(retval & V4L2_TUNER_SUB_STEREO) ? " stereo" : "",
(retval & V4L2_TUNER_SUB_LANG1) ? " lang1" : "",
(retval & V4L2_TUNER_SUB_LANG2) ? " lang2" : "");
return retval;
}
static int tvaudio_setstereo(struct saa7134_dev *dev, struct saa7134_tvaudio *audio,
u32 mode)
{
static char *name[] = {
[ V4L2_TUNER_MODE_MONO ] = "mono",
[ V4L2_TUNER_MODE_STEREO ] = "stereo",
[ V4L2_TUNER_MODE_LANG1 ] = "lang1",
[ V4L2_TUNER_MODE_LANG2 ] = "lang2",
[ V4L2_TUNER_MODE_LANG1_LANG2 ] = "lang1+lang2",
};
static u32 fm[] = {
[ V4L2_TUNER_MODE_MONO ] = 0x00, /* ch1 */
[ V4L2_TUNER_MODE_STEREO ] = 0x80, /* auto */
[ V4L2_TUNER_MODE_LANG1 ] = 0x00, /* ch1 */
[ V4L2_TUNER_MODE_LANG2 ] = 0x01, /* ch2 */
[ V4L2_TUNER_MODE_LANG1_LANG2 ] = 0x80, /* auto */
};
u32 reg;
switch (audio->mode) {
case TVAUDIO_FM_MONO:
/* nothing to do ... */
break;
case TVAUDIO_FM_K_STEREO:
case TVAUDIO_FM_BG_STEREO:
case TVAUDIO_NICAM_AM:
case TVAUDIO_NICAM_FM:
audio_dbg(1, "setstereo [fm] => %s\n",
name[mode % ARRAY_SIZE(name)]);
reg = fm[ mode % ARRAY_SIZE(fm) ];
saa_writeb(SAA7134_FM_DEMATRIX, reg);
break;
case TVAUDIO_FM_SAT_STEREO:
/* Not implemented */
break;
}
return 0;
}
static int tvaudio_thread(void *data)
{
struct saa7134_dev *dev = data;
int carr_vals[ARRAY_SIZE(mainscan)];
unsigned int i, audio, nscan;
int max1,max2,carrier,rx,mode,lastmode,default_carrier;
set_freezable();
for (;;) {
tvaudio_sleep(dev,-1);
if (kthread_should_stop())
goto done;
restart:
try_to_freeze();
dev->thread.scan1 = dev->thread.scan2;
audio_dbg(1, "tvaudio thread scan start [%d]\n",
dev->thread.scan1);
dev->tvaudio = NULL;
saa_writeb(SAA7134_MONITOR_SELECT, 0xa0);
saa_writeb(SAA7134_FM_DEMATRIX, 0x80);
if (dev->ctl_automute)
dev->automute = 1;
mute_input_7134(dev);
/* give the tuner some time */
if (tvaudio_sleep(dev,SCAN_INITIAL_DELAY))
goto restart;
max1 = 0;
max2 = 0;
nscan = 0;
carrier = 0;
default_carrier = 0;
for (i = 0; i < ARRAY_SIZE(mainscan); i++) {
if (!(dev->tvnorm->id & mainscan[i].std))
continue;
if (!default_carrier)
default_carrier = mainscan[i].carr;
nscan++;
}
if (1 == nscan) {
/* only one candidate -- skip scan ;) */
audio_dbg(1, "only one main carrier candidate - skipping scan\n");
max1 = 12345;
carrier = default_carrier;
} else {
/* scan for the main carrier */
saa_writeb(SAA7134_MONITOR_SELECT,0x00);
tvaudio_setmode(dev,&tvaudio[0],NULL);
for (i = 0; i < ARRAY_SIZE(mainscan); i++) {
carr_vals[i] = tvaudio_checkcarrier(dev, mainscan+i);
if (dev->thread.scan1 != dev->thread.scan2)
goto restart;
}
for (max1 = 0, max2 = 0, i = 0; i < ARRAY_SIZE(mainscan); i++) {
if (max1 < carr_vals[i]) {
max2 = max1;
max1 = carr_vals[i];
carrier = mainscan[i].carr;
} else if (max2 < carr_vals[i]) {
max2 = carr_vals[i];
}
}
}
if (0 != carrier && max1 > 2000 && max1 > max2*3) {
/* found good carrier */
audio_dbg(1, "found %s main sound carrier @ %d.%03d MHz [%d/%d]\n",
dev->tvnorm->name, carrier/1000, carrier%1000,
max1, max2);
dev->last_carrier = carrier;
dev->automute = 0;
} else if (0 != dev->last_carrier) {
/* no carrier -- try last detected one as fallback */
carrier = dev->last_carrier;
audio_dbg(1, "audio carrier scan failed, using %d.%03d MHz [last detected]\n",
carrier/1000, carrier%1000);
dev->automute = 1;
} else {
/* no carrier + no fallback -- use default */
carrier = default_carrier;
audio_dbg(1, "audio carrier scan failed, using %d.%03d MHz [default]\n",
carrier/1000, carrier%1000);
dev->automute = 1;
}
tvaudio_setcarrier(dev,carrier,carrier);
saa_andorb(SAA7134_STEREO_DAC_OUTPUT_SELECT, 0x30, 0x00);
saa7134_tvaudio_setmute(dev);
/* find the exact tv audio norm */
for (audio = UNSET, i = 0; i < TVAUDIO; i++) {
if (dev->tvnorm->id != UNSET &&
!(dev->tvnorm->id & tvaudio[i].std))
continue;
if (tvaudio[i].carr1 != carrier)
continue;
/* Note: at least the primary carrier is right here */
if (UNSET == audio)
audio = i;
tvaudio_setmode(dev,&tvaudio[i],"trying");
if (tvaudio_sleep(dev,SCAN_SUBCARRIER_DELAY))
goto restart;
if (-1 != tvaudio_getstereo(dev,&tvaudio[i])) {
audio = i;
break;
}
}
saa_andorb(SAA7134_STEREO_DAC_OUTPUT_SELECT, 0x30, 0x30);
if (UNSET == audio)
continue;
tvaudio_setmode(dev,&tvaudio[audio],"using");
tvaudio_setstereo(dev,&tvaudio[audio],V4L2_TUNER_MODE_MONO);
dev->tvaudio = &tvaudio[audio];
lastmode = 42;
for (;;) {
try_to_freeze();
if (tvaudio_sleep(dev,5000))
goto restart;
if (kthread_should_stop())
break;
if (UNSET == dev->thread.mode) {
rx = tvaudio_getstereo(dev, &tvaudio[audio]);
mode = saa7134_tvaudio_rx2mode(rx);
} else {
mode = dev->thread.mode;
}
if (lastmode != mode) {
tvaudio_setstereo(dev,&tvaudio[audio],mode);
lastmode = mode;
}
}
}
done:
dev->thread.stopped = 1;
return 0;
}
/* ------------------------------------------------------------------ */
/* saa7133 / saa7135 code */
static char *stdres[0x20] = {
[0x00] = "no standard detected",
[0x01] = "B/G (in progress)",
[0x02] = "D/K (in progress)",
[0x03] = "M (in progress)",
[0x04] = "B/G A2",
[0x05] = "B/G NICAM",
[0x06] = "D/K A2 (1)",
[0x07] = "D/K A2 (2)",
[0x08] = "D/K A2 (3)",
[0x09] = "D/K NICAM",
[0x0a] = "L NICAM",
[0x0b] = "I NICAM",
[0x0c] = "M Korea",
[0x0d] = "M BTSC ",
[0x0e] = "M EIAJ",
[0x0f] = "FM radio / IF 10.7 / 50 deemp",
[0x10] = "FM radio / IF 10.7 / 75 deemp",
[0x11] = "FM radio / IF sel / 50 deemp",
[0x12] = "FM radio / IF sel / 75 deemp",
[0x13 ... 0x1e ] = "unknown",
[0x1f] = "??? [in progress]",
};
#define DSP_RETRY 32
#define DSP_DELAY 16
#define SAA7135_DSP_RWCLEAR_RERR 1
static inline int saa_dsp_reset_error_bit(struct saa7134_dev *dev)
{
int state = saa_readb(SAA7135_DSP_RWSTATE);
if (unlikely(state & SAA7135_DSP_RWSTATE_ERR)) {
audio_dbg(2, "%s: resetting error bit\n", dev->name);
saa_writeb(SAA7135_DSP_RWCLEAR, SAA7135_DSP_RWCLEAR_RERR);
}
return 0;
}
static inline int saa_dsp_wait_bit(struct saa7134_dev *dev, int bit)
{
int state, count = DSP_RETRY;
state = saa_readb(SAA7135_DSP_RWSTATE);
if (unlikely(state & SAA7135_DSP_RWSTATE_ERR)) {
pr_warn("%s: dsp access error\n", dev->name);
saa_dsp_reset_error_bit(dev);
return -EIO;
}
while (0 == (state & bit)) {
if (unlikely(0 == count)) {
pr_err("dsp access wait timeout [bit=%s]\n",
(bit & SAA7135_DSP_RWSTATE_WRR) ? "WRR" :
(bit & SAA7135_DSP_RWSTATE_RDB) ? "RDB" :
(bit & SAA7135_DSP_RWSTATE_IDA) ? "IDA" :
"???");
return -EIO;
}
saa_wait(DSP_DELAY);
state = saa_readb(SAA7135_DSP_RWSTATE);
count--;
}
return 0;
}
int saa_dsp_writel(struct saa7134_dev *dev, int reg, u32 value)
{
int err;
audio_dbg(2, "dsp write reg 0x%x = 0x%06x\n",
(reg << 2) & 0xffffffff, value);
err = saa_dsp_wait_bit(dev,SAA7135_DSP_RWSTATE_WRR);
if (err < 0)
return err;
saa_writel(reg,value);
err = saa_dsp_wait_bit(dev,SAA7135_DSP_RWSTATE_WRR);
if (err < 0)
return err;
return 0;
}
static int getstereo_7133(struct saa7134_dev *dev)
{
int retval = V4L2_TUNER_SUB_MONO;
u32 value;
value = saa_readl(0x528 >> 2);
if (value & 0x20)
retval = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
if (value & 0x40)
retval = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
return retval;
}
static int mute_input_7133(struct saa7134_dev *dev)
{
u32 reg = 0;
u32 xbarin, xbarout;
int mask;
struct saa7134_input *in;
xbarin = 0x03;
switch (dev->input->amux) {
case TV:
reg = 0x02;
xbarin = 0;
break;
case LINE1:
reg = 0x00;
break;
case LINE2:
case LINE2_LEFT:
reg = 0x09;
break;
}
saa_dsp_writel(dev, 0x464 >> 2, xbarin);
if (dev->ctl_mute) {
reg = 0x07;
xbarout = 0xbbbbbb;
} else
xbarout = 0xbbbb10;
saa_dsp_writel(dev, 0x46c >> 2, xbarout);
saa_writel(0x594 >> 2, reg);
/* switch gpio-connected external audio mux */
if (0 != card(dev).gpiomask) {
mask = card(dev).gpiomask;
if (card(dev).mute.type && dev->ctl_mute)
in = &card(dev).mute;
else
in = dev->input;
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, mask, mask);
saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, mask, in->gpio);
saa7134_track_gpio(dev, saa7134_input_name[in->type]);
}
return 0;
}
static int tvaudio_thread_ddep(void *data)
{
struct saa7134_dev *dev = data;
u32 value, norms;
set_freezable();
for (;;) {
tvaudio_sleep(dev,-1);
if (kthread_should_stop())
goto done;
restart:
try_to_freeze();
dev->thread.scan1 = dev->thread.scan2;
audio_dbg(1, "tvaudio thread scan start [%d]\n",
dev->thread.scan1);
if (audio_ddep >= 0x04 && audio_ddep <= 0x0e) {
/* insmod option override */
norms = (audio_ddep << 2) | 0x01;
audio_dbg(1, "ddep override: %s\n",
stdres[audio_ddep]);
} else if (&card(dev).radio == dev->input) {
audio_dbg(1, "FM Radio\n");
if (dev->tuner_type == TUNER_PHILIPS_TDA8290) {
norms = (0x11 << 2) | 0x01;
/* set IF frequency to 5.5 MHz */
saa_dsp_writel(dev, 0x42c >> 2, 0x729555);
} else {
norms = (0x0f << 2) | 0x01;
}
} else {
/* (let chip) scan for sound carrier */
norms = 0;
if (dev->tvnorm->id & (V4L2_STD_B | V4L2_STD_GH))
norms |= 0x04;
if (dev->tvnorm->id & V4L2_STD_PAL_I)
norms |= 0x20;
if (dev->tvnorm->id & V4L2_STD_DK)
norms |= 0x08;
if (dev->tvnorm->id & V4L2_STD_MN)
norms |= 0x40;
if (dev->tvnorm->id & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))
norms |= 0x10;
if (0 == norms)
norms = 0x7c; /* all */
audio_dbg(1, "scanning:%s%s%s%s%s\n",
(norms & 0x04) ? " B/G" : "",
(norms & 0x08) ? " D/K" : "",
(norms & 0x10) ? " L/L'" : "",
(norms & 0x20) ? " I" : "",
(norms & 0x40) ? " M" : "");
}
/* kick automatic standard detection */
saa_dsp_writel(dev, 0x454 >> 2, 0);
saa_dsp_writel(dev, 0x454 >> 2, norms | 0x80);
/* setup crossbars */
saa_dsp_writel(dev, 0x464 >> 2, 0x000000);
saa_dsp_writel(dev, 0x470 >> 2, 0x101010);
if (tvaudio_sleep(dev,3000))
goto restart;
value = saa_readl(0x528 >> 2) & 0xffffff;
audio_dbg(1, "tvaudio thread status: 0x%x [%s%s%s]\n",
value, stdres[value & 0x1f],
(value & 0x000020) ? ",stereo" : "",
(value & 0x000040) ? ",dual" : "");
audio_dbg(1, "detailed status: %s#%s#%s#%s#%s#%s#%s#%s#%s#%s#%s#%s#%s#%s\n",
(value & 0x000080) ? " A2/EIAJ pilot tone " : "",
(value & 0x000100) ? " A2/EIAJ dual " : "",
(value & 0x000200) ? " A2/EIAJ stereo " : "",
(value & 0x000400) ? " A2/EIAJ noise mute " : "",
(value & 0x000800) ? " BTSC/FM radio pilot " : "",
(value & 0x001000) ? " SAP carrier " : "",
(value & 0x002000) ? " BTSC stereo noise mute " : "",
(value & 0x004000) ? " SAP noise mute " : "",
(value & 0x008000) ? " VDSP " : "",
(value & 0x010000) ? " NICST " : "",
(value & 0x020000) ? " NICDU " : "",
(value & 0x040000) ? " NICAM muted " : "",
(value & 0x080000) ? " NICAM reserve sound " : "",
(value & 0x100000) ? " init done " : "");
}
done:
dev->thread.stopped = 1;
return 0;
}
/* ------------------------------------------------------------------ */
/* common stuff + external entry points */
void saa7134_enable_i2s(struct saa7134_dev *dev)
{
int i2s_format;
if (!card_is_empress(dev))
return;
if (dev->pci->device == PCI_DEVICE_ID_PHILIPS_SAA7130)
return;
/* configure GPIO for out */
saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x0E000000, 0x00000000);
switch (dev->pci->device) {
case PCI_DEVICE_ID_PHILIPS_SAA7133:
case PCI_DEVICE_ID_PHILIPS_SAA7135:
/* Set I2S format (SONY) */
saa_writeb(SAA7133_I2S_AUDIO_CONTROL, 0x00);
/* Start I2S */
saa_writeb(SAA7134_I2S_AUDIO_OUTPUT, 0x11);
break;
case PCI_DEVICE_ID_PHILIPS_SAA7134:
i2s_format = (dev->input->amux == TV) ? 0x00 : 0x01;
/* enable I2S audio output for the mpeg encoder */
saa_writeb(SAA7134_I2S_OUTPUT_SELECT, 0x80);
saa_writeb(SAA7134_I2S_OUTPUT_FORMAT, i2s_format);
saa_writeb(SAA7134_I2S_OUTPUT_LEVEL, 0x0F);
saa_writeb(SAA7134_I2S_AUDIO_OUTPUT, 0x01);
break;
default:
break;
}
}
int saa7134_tvaudio_rx2mode(u32 rx)
{
u32 mode;
mode = V4L2_TUNER_MODE_MONO;
if (rx & V4L2_TUNER_SUB_STEREO)
mode = V4L2_TUNER_MODE_STEREO;
else if (rx & V4L2_TUNER_SUB_LANG1)
mode = V4L2_TUNER_MODE_LANG1;
else if (rx & V4L2_TUNER_SUB_LANG2)
mode = V4L2_TUNER_MODE_LANG2;
return mode;
}
void saa7134_tvaudio_setmute(struct saa7134_dev *dev)
{
switch (dev->pci->device) {
case PCI_DEVICE_ID_PHILIPS_SAA7130:
case PCI_DEVICE_ID_PHILIPS_SAA7134:
mute_input_7134(dev);
break;
case PCI_DEVICE_ID_PHILIPS_SAA7133:
case PCI_DEVICE_ID_PHILIPS_SAA7135:
mute_input_7133(dev);
break;
}
}
void saa7134_tvaudio_setinput(struct saa7134_dev *dev,
struct saa7134_input *in)
{
dev->input = in;
switch (dev->pci->device) {
case PCI_DEVICE_ID_PHILIPS_SAA7130:
case PCI_DEVICE_ID_PHILIPS_SAA7134:
mute_input_7134(dev);
break;
case PCI_DEVICE_ID_PHILIPS_SAA7133:
case PCI_DEVICE_ID_PHILIPS_SAA7135:
mute_input_7133(dev);
break;
}
saa7134_enable_i2s(dev);
}
void saa7134_tvaudio_setvolume(struct saa7134_dev *dev, int level)
{
switch (dev->pci->device) {
case PCI_DEVICE_ID_PHILIPS_SAA7134:
saa_writeb(SAA7134_CHANNEL1_LEVEL, level & 0x1f);
saa_writeb(SAA7134_CHANNEL2_LEVEL, level & 0x1f);
saa_writeb(SAA7134_NICAM_LEVEL_ADJUST, level & 0x1f);
break;
}
}
int saa7134_tvaudio_getstereo(struct saa7134_dev *dev)
{
int retval = V4L2_TUNER_SUB_MONO;
switch (dev->pci->device) {
case PCI_DEVICE_ID_PHILIPS_SAA7134:
if (dev->tvaudio)
retval = tvaudio_getstereo(dev,dev->tvaudio);
break;
case PCI_DEVICE_ID_PHILIPS_SAA7133:
case PCI_DEVICE_ID_PHILIPS_SAA7135:
retval = getstereo_7133(dev);
break;
}
return retval;
}
void saa7134_tvaudio_init(struct saa7134_dev *dev)
{
int clock = saa7134_boards[dev->board].audio_clock;
if (UNSET != audio_clock_override)
clock = audio_clock_override;
switch (dev->pci->device) {
case PCI_DEVICE_ID_PHILIPS_SAA7134:
/* init all audio registers */
saa_writeb(SAA7134_AUDIO_PLL_CTRL, 0x00);
if (need_resched())
schedule();
else
udelay(10);
saa_writeb(SAA7134_AUDIO_CLOCK0, clock & 0xff);
saa_writeb(SAA7134_AUDIO_CLOCK1, (clock >> 8) & 0xff);
saa_writeb(SAA7134_AUDIO_CLOCK2, (clock >> 16) & 0xff);
/* frame locked audio is mandatory for NICAM */
saa_writeb(SAA7134_AUDIO_PLL_CTRL, 0x01);
saa_writeb(SAA7134_NICAM_ERROR_LOW, 0x14);
saa_writeb(SAA7134_NICAM_ERROR_HIGH, 0x50);
break;
case PCI_DEVICE_ID_PHILIPS_SAA7133:
case PCI_DEVICE_ID_PHILIPS_SAA7135:
saa_writel(0x598 >> 2, clock);
saa_dsp_writel(dev, 0x474 >> 2, 0x00);
saa_dsp_writel(dev, 0x450 >> 2, 0x00);
}
}
int saa7134_tvaudio_init2(struct saa7134_dev *dev)
{
int (*my_thread)(void *data) = NULL;
switch (dev->pci->device) {
case PCI_DEVICE_ID_PHILIPS_SAA7134:
my_thread = tvaudio_thread;
break;
case PCI_DEVICE_ID_PHILIPS_SAA7133:
case PCI_DEVICE_ID_PHILIPS_SAA7135:
my_thread = tvaudio_thread_ddep;
break;
}
dev->thread.thread = NULL;
dev->thread.scan1 = dev->thread.scan2 = 0;
if (my_thread) {
saa7134_tvaudio_init(dev);
/* start tvaudio thread */
dev->thread.thread = kthread_run(my_thread, dev, "%s", dev->name);
if (IS_ERR(dev->thread.thread)) {
pr_warn("%s: kernel_thread() failed\n",
dev->name);
/* XXX: missing error handling here */
}
}
saa7134_enable_i2s(dev);
return 0;
}
int saa7134_tvaudio_close(struct saa7134_dev *dev)
{
dev->automute = 1;
/* anything else to undo? */
return 0;
}
int saa7134_tvaudio_fini(struct saa7134_dev *dev)
{
/* shutdown tvaudio thread */
if (dev->thread.thread && !dev->thread.stopped)
kthread_stop(dev->thread.thread);
saa_andorb(SAA7134_ANALOG_IO_SELECT, 0x07, 0x00); /* LINE1 */
return 0;
}
int saa7134_tvaudio_do_scan(struct saa7134_dev *dev)
{
if (dev->input->amux != TV) {
audio_dbg(1, "sound IF not in use, skipping scan\n");
dev->automute = 0;
saa7134_tvaudio_setmute(dev);
} else if (dev->thread.thread) {
dev->thread.mode = UNSET;
dev->thread.scan2++;
if (!dev->insuspend && !dev->thread.stopped)
wake_up_process(dev->thread.thread);
} else {
dev->automute = 0;
saa7134_tvaudio_setmute(dev);
}
return 0;
}
EXPORT_SYMBOL(saa_dsp_writel);
EXPORT_SYMBOL(saa7134_tvaudio_setmute);
| linux-master | drivers/media/pci/saa7134/saa7134-tvaudio.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* device driver for philips saa7134 based TV cards
* video4linux video interface
*
* (c) 2001-03 Gerd Knorr <[email protected]> [SuSE Labs]
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sort.h>
#include <media/v4l2-common.h>
#include <media/v4l2-event.h>
#include <media/i2c/saa6588.h>
/* ------------------------------------------------------------------ */
unsigned int video_debug;
static unsigned int gbuffers = 8;
static unsigned int noninterlaced; /* 0 */
static unsigned int gbufsize = 720*576*4;
static unsigned int gbufsize_max = 720*576*4;
static char secam[] = "--";
module_param(video_debug, int, 0644);
MODULE_PARM_DESC(video_debug,"enable debug messages [video]");
module_param(gbuffers, int, 0444);
MODULE_PARM_DESC(gbuffers,"number of capture buffers, range 2-32");
module_param(noninterlaced, int, 0644);
MODULE_PARM_DESC(noninterlaced,"capture non interlaced video");
module_param_string(secam, secam, sizeof(secam), 0644);
MODULE_PARM_DESC(secam, "force SECAM variant, either DK,L or Lc");
#define video_dbg(fmt, arg...) do { \
if (video_debug & 0x04) \
printk(KERN_DEBUG pr_fmt("video: " fmt), ## arg); \
} while (0)
/* ------------------------------------------------------------------ */
/* Defines for Video Output Port Register at address 0x191 */
/* Bit 0: VIP code T bit polarity */
#define VP_T_CODE_P_NON_INVERTED 0x00
#define VP_T_CODE_P_INVERTED 0x01
/* ------------------------------------------------------------------ */
/* Defines for Video Output Port Register at address 0x195 */
/* Bit 2: Video output clock delay control */
#define VP_CLK_CTRL2_NOT_DELAYED 0x00
#define VP_CLK_CTRL2_DELAYED 0x04
/* Bit 1: Video output clock invert control */
#define VP_CLK_CTRL1_NON_INVERTED 0x00
#define VP_CLK_CTRL1_INVERTED 0x02
/* ------------------------------------------------------------------ */
/* Defines for Video Output Port Register at address 0x196 */
/* Bits 2 to 0: VSYNC pin video vertical sync type */
#define VP_VS_TYPE_MASK 0x07
#define VP_VS_TYPE_OFF 0x00
#define VP_VS_TYPE_V123 0x01
#define VP_VS_TYPE_V_ITU 0x02
#define VP_VS_TYPE_VGATE_L 0x03
#define VP_VS_TYPE_RESERVED1 0x04
#define VP_VS_TYPE_RESERVED2 0x05
#define VP_VS_TYPE_F_ITU 0x06
#define VP_VS_TYPE_SC_FID 0x07
/* ------------------------------------------------------------------ */
/* data structs for video */
static int video_out[][9] = {
[CCIR656] = { 0x00, 0xb1, 0x00, 0xa1, 0x00, 0x04, 0x06, 0x00, 0x00 },
};
static struct saa7134_format formats[] = {
{
.fourcc = V4L2_PIX_FMT_GREY,
.depth = 8,
.pm = 0x06,
},{
.fourcc = V4L2_PIX_FMT_RGB555,
.depth = 16,
.pm = 0x13 | 0x80,
},{
.fourcc = V4L2_PIX_FMT_RGB555X,
.depth = 16,
.pm = 0x13 | 0x80,
.bswap = 1,
},{
.fourcc = V4L2_PIX_FMT_RGB565,
.depth = 16,
.pm = 0x10 | 0x80,
},{
.fourcc = V4L2_PIX_FMT_RGB565X,
.depth = 16,
.pm = 0x10 | 0x80,
.bswap = 1,
},{
.fourcc = V4L2_PIX_FMT_BGR24,
.depth = 24,
.pm = 0x11,
},{
.fourcc = V4L2_PIX_FMT_RGB24,
.depth = 24,
.pm = 0x11,
.bswap = 1,
},{
.fourcc = V4L2_PIX_FMT_BGR32,
.depth = 32,
.pm = 0x12,
},{
.fourcc = V4L2_PIX_FMT_RGB32,
.depth = 32,
.pm = 0x12,
.bswap = 1,
.wswap = 1,
},{
.fourcc = V4L2_PIX_FMT_YUYV,
.depth = 16,
.pm = 0x00,
.bswap = 1,
.yuv = 1,
},{
.fourcc = V4L2_PIX_FMT_UYVY,
.depth = 16,
.pm = 0x00,
.yuv = 1,
},{
.fourcc = V4L2_PIX_FMT_YUV422P,
.depth = 16,
.pm = 0x09,
.yuv = 1,
.planar = 1,
.hshift = 1,
.vshift = 0,
},{
.fourcc = V4L2_PIX_FMT_YUV420,
.depth = 12,
.pm = 0x0a,
.yuv = 1,
.planar = 1,
.hshift = 1,
.vshift = 1,
},{
.fourcc = V4L2_PIX_FMT_YVU420,
.depth = 12,
.pm = 0x0a,
.yuv = 1,
.planar = 1,
.uvswap = 1,
.hshift = 1,
.vshift = 1,
}
};
#define FORMATS ARRAY_SIZE(formats)
#define NORM_625_50 \
.h_start = 0, \
.h_stop = 719, \
.video_v_start = 24, \
.video_v_stop = 311, \
.vbi_v_start_0 = 7, \
.vbi_v_stop_0 = 23, \
.vbi_v_start_1 = 319, \
.src_timing = 4
#define NORM_525_60 \
.h_start = 0, \
.h_stop = 719, \
.video_v_start = 23, \
.video_v_stop = 262, \
.vbi_v_start_0 = 10, \
.vbi_v_stop_0 = 21, \
.vbi_v_start_1 = 273, \
.src_timing = 7
static struct saa7134_tvnorm tvnorms[] = {
{
.name = "PAL", /* autodetect */
.id = V4L2_STD_PAL,
NORM_625_50,
.sync_control = 0x18,
.luma_control = 0x40,
.chroma_ctrl1 = 0x81,
.chroma_gain = 0x2a,
.chroma_ctrl2 = 0x06,
.vgate_misc = 0x1c,
},{
.name = "PAL-BG",
.id = V4L2_STD_PAL_BG,
NORM_625_50,
.sync_control = 0x18,
.luma_control = 0x40,
.chroma_ctrl1 = 0x81,
.chroma_gain = 0x2a,
.chroma_ctrl2 = 0x06,
.vgate_misc = 0x1c,
},{
.name = "PAL-I",
.id = V4L2_STD_PAL_I,
NORM_625_50,
.sync_control = 0x18,
.luma_control = 0x40,
.chroma_ctrl1 = 0x81,
.chroma_gain = 0x2a,
.chroma_ctrl2 = 0x06,
.vgate_misc = 0x1c,
},{
.name = "PAL-DK",
.id = V4L2_STD_PAL_DK,
NORM_625_50,
.sync_control = 0x18,
.luma_control = 0x40,
.chroma_ctrl1 = 0x81,
.chroma_gain = 0x2a,
.chroma_ctrl2 = 0x06,
.vgate_misc = 0x1c,
},{
.name = "NTSC",
.id = V4L2_STD_NTSC,
NORM_525_60,
.sync_control = 0x59,
.luma_control = 0x40,
.chroma_ctrl1 = 0x89,
.chroma_gain = 0x2a,
.chroma_ctrl2 = 0x0e,
.vgate_misc = 0x18,
},{
.name = "SECAM",
.id = V4L2_STD_SECAM,
NORM_625_50,
.sync_control = 0x18,
.luma_control = 0x1b,
.chroma_ctrl1 = 0xd1,
.chroma_gain = 0x80,
.chroma_ctrl2 = 0x00,
.vgate_misc = 0x1c,
},{
.name = "SECAM-DK",
.id = V4L2_STD_SECAM_DK,
NORM_625_50,
.sync_control = 0x18,
.luma_control = 0x1b,
.chroma_ctrl1 = 0xd1,
.chroma_gain = 0x80,
.chroma_ctrl2 = 0x00,
.vgate_misc = 0x1c,
},{
.name = "SECAM-L",
.id = V4L2_STD_SECAM_L,
NORM_625_50,
.sync_control = 0x18,
.luma_control = 0x1b,
.chroma_ctrl1 = 0xd1,
.chroma_gain = 0x80,
.chroma_ctrl2 = 0x00,
.vgate_misc = 0x1c,
},{
.name = "SECAM-Lc",
.id = V4L2_STD_SECAM_LC,
NORM_625_50,
.sync_control = 0x18,
.luma_control = 0x1b,
.chroma_ctrl1 = 0xd1,
.chroma_gain = 0x80,
.chroma_ctrl2 = 0x00,
.vgate_misc = 0x1c,
},{
.name = "PAL-M",
.id = V4L2_STD_PAL_M,
NORM_525_60,
.sync_control = 0x59,
.luma_control = 0x40,
.chroma_ctrl1 = 0xb9,
.chroma_gain = 0x2a,
.chroma_ctrl2 = 0x0e,
.vgate_misc = 0x18,
},{
.name = "PAL-Nc",
.id = V4L2_STD_PAL_Nc,
NORM_625_50,
.sync_control = 0x18,
.luma_control = 0x40,
.chroma_ctrl1 = 0xa1,
.chroma_gain = 0x2a,
.chroma_ctrl2 = 0x06,
.vgate_misc = 0x1c,
},{
.name = "PAL-60",
.id = V4L2_STD_PAL_60,
.h_start = 0,
.h_stop = 719,
.video_v_start = 23,
.video_v_stop = 262,
.vbi_v_start_0 = 10,
.vbi_v_stop_0 = 21,
.vbi_v_start_1 = 273,
.src_timing = 7,
.sync_control = 0x18,
.luma_control = 0x40,
.chroma_ctrl1 = 0x81,
.chroma_gain = 0x2a,
.chroma_ctrl2 = 0x06,
.vgate_misc = 0x1c,
}
};
#define TVNORMS ARRAY_SIZE(tvnorms)
static struct saa7134_format* format_by_fourcc(unsigned int fourcc)
{
unsigned int i;
for (i = 0; i < FORMATS; i++)
if (formats[i].fourcc == fourcc)
return formats+i;
return NULL;
}
/* ------------------------------------------------------------------ */
static void set_tvnorm(struct saa7134_dev *dev, struct saa7134_tvnorm *norm)
{
video_dbg("set tv norm = %s\n", norm->name);
dev->tvnorm = norm;
/* setup cropping */
dev->crop_bounds.left = norm->h_start;
dev->crop_defrect.left = norm->h_start;
dev->crop_bounds.width = norm->h_stop - norm->h_start +1;
dev->crop_defrect.width = norm->h_stop - norm->h_start +1;
dev->crop_bounds.top = (norm->vbi_v_stop_0+1)*2;
dev->crop_defrect.top = norm->video_v_start*2;
dev->crop_bounds.height = ((norm->id & V4L2_STD_525_60) ? 524 : 624)
- dev->crop_bounds.top;
dev->crop_defrect.height = (norm->video_v_stop - norm->video_v_start +1)*2;
dev->crop_current = dev->crop_defrect;
saa7134_set_tvnorm_hw(dev);
}
static void video_mux(struct saa7134_dev *dev, int input)
{
video_dbg("video input = %d [%s]\n",
input, saa7134_input_name[card_in(dev, input).type]);
dev->ctl_input = input;
set_tvnorm(dev, dev->tvnorm);
saa7134_tvaudio_setinput(dev, &card_in(dev, input));
}
static void saa7134_set_decoder(struct saa7134_dev *dev)
{
int luma_control, sync_control, chroma_ctrl1, mux;
struct saa7134_tvnorm *norm = dev->tvnorm;
mux = card_in(dev, dev->ctl_input).vmux;
luma_control = norm->luma_control;
sync_control = norm->sync_control;
chroma_ctrl1 = norm->chroma_ctrl1;
if (mux > 5)
luma_control |= 0x80; /* svideo */
if (noninterlaced || dev->nosignal)
sync_control |= 0x20;
/* switch on auto standard detection */
sync_control |= SAA7134_SYNC_CTRL_AUFD;
chroma_ctrl1 |= SAA7134_CHROMA_CTRL1_AUTO0;
chroma_ctrl1 &= ~SAA7134_CHROMA_CTRL1_FCTC;
luma_control &= ~SAA7134_LUMA_CTRL_LDEL;
/* setup video decoder */
saa_writeb(SAA7134_INCR_DELAY, 0x08);
saa_writeb(SAA7134_ANALOG_IN_CTRL1, 0xc0 | mux);
saa_writeb(SAA7134_ANALOG_IN_CTRL2, 0x00);
saa_writeb(SAA7134_ANALOG_IN_CTRL3, 0x90);
saa_writeb(SAA7134_ANALOG_IN_CTRL4, 0x90);
saa_writeb(SAA7134_HSYNC_START, 0xeb);
saa_writeb(SAA7134_HSYNC_STOP, 0xe0);
saa_writeb(SAA7134_SOURCE_TIMING1, norm->src_timing);
saa_writeb(SAA7134_SYNC_CTRL, sync_control);
saa_writeb(SAA7134_LUMA_CTRL, luma_control);
saa_writeb(SAA7134_DEC_LUMA_BRIGHT, dev->ctl_bright);
saa_writeb(SAA7134_DEC_LUMA_CONTRAST,
dev->ctl_invert ? -dev->ctl_contrast : dev->ctl_contrast);
saa_writeb(SAA7134_DEC_CHROMA_SATURATION,
dev->ctl_invert ? -dev->ctl_saturation : dev->ctl_saturation);
saa_writeb(SAA7134_DEC_CHROMA_HUE, dev->ctl_hue);
saa_writeb(SAA7134_CHROMA_CTRL1, chroma_ctrl1);
saa_writeb(SAA7134_CHROMA_GAIN, norm->chroma_gain);
saa_writeb(SAA7134_CHROMA_CTRL2, norm->chroma_ctrl2);
saa_writeb(SAA7134_MODE_DELAY_CTRL, 0x00);
saa_writeb(SAA7134_ANALOG_ADC, 0x01);
saa_writeb(SAA7134_VGATE_START, 0x11);
saa_writeb(SAA7134_VGATE_STOP, 0xfe);
saa_writeb(SAA7134_MISC_VGATE_MSB, norm->vgate_misc);
saa_writeb(SAA7134_RAW_DATA_GAIN, 0x40);
saa_writeb(SAA7134_RAW_DATA_OFFSET, 0x80);
}
void saa7134_set_tvnorm_hw(struct saa7134_dev *dev)
{
saa7134_set_decoder(dev);
saa_call_all(dev, video, s_std, dev->tvnorm->id);
/* Set the correct norm for the saa6752hs. This function
does nothing if there is no saa6752hs. */
saa_call_empress(dev, video, s_std, dev->tvnorm->id);
}
static void set_h_prescale(struct saa7134_dev *dev, int task, int prescale)
{
static const struct {
int xpsc;
int xacl;
int xc2_1;
int xdcg;
int vpfy;
} vals[] = {
/* XPSC XACL XC2_1 XDCG VPFY */
{ 1, 0, 0, 0, 0 },
{ 2, 2, 1, 2, 2 },
{ 3, 4, 1, 3, 2 },
{ 4, 8, 1, 4, 2 },
{ 5, 8, 1, 4, 2 },
{ 6, 8, 1, 4, 3 },
{ 7, 8, 1, 4, 3 },
{ 8, 15, 0, 4, 3 },
{ 9, 15, 0, 4, 3 },
{ 10, 16, 1, 5, 3 },
};
static const int count = ARRAY_SIZE(vals);
int i;
for (i = 0; i < count; i++)
if (vals[i].xpsc == prescale)
break;
if (i == count)
return;
saa_writeb(SAA7134_H_PRESCALE(task), vals[i].xpsc);
saa_writeb(SAA7134_ACC_LENGTH(task), vals[i].xacl);
saa_writeb(SAA7134_LEVEL_CTRL(task),
(vals[i].xc2_1 << 3) | (vals[i].xdcg));
saa_andorb(SAA7134_FIR_PREFILTER_CTRL(task), 0x0f,
(vals[i].vpfy << 2) | vals[i].vpfy);
}
static void set_v_scale(struct saa7134_dev *dev, int task, int yscale)
{
int val,mirror;
saa_writeb(SAA7134_V_SCALE_RATIO1(task), yscale & 0xff);
saa_writeb(SAA7134_V_SCALE_RATIO2(task), yscale >> 8);
mirror = (dev->ctl_mirror) ? 0x02 : 0x00;
if (yscale < 2048) {
/* LPI */
video_dbg("yscale LPI yscale=%d\n", yscale);
saa_writeb(SAA7134_V_FILTER(task), 0x00 | mirror);
saa_writeb(SAA7134_LUMA_CONTRAST(task), 0x40);
saa_writeb(SAA7134_CHROMA_SATURATION(task), 0x40);
} else {
/* ACM */
val = 0x40 * 1024 / yscale;
video_dbg("yscale ACM yscale=%d val=0x%x\n", yscale, val);
saa_writeb(SAA7134_V_FILTER(task), 0x01 | mirror);
saa_writeb(SAA7134_LUMA_CONTRAST(task), val);
saa_writeb(SAA7134_CHROMA_SATURATION(task), val);
}
saa_writeb(SAA7134_LUMA_BRIGHT(task), 0x80);
}
static void set_size(struct saa7134_dev *dev, int task,
int width, int height, int interlace)
{
int prescale,xscale,yscale,y_even,y_odd;
int h_start, h_stop, v_start, v_stop;
int div = interlace ? 2 : 1;
/* setup video scaler */
h_start = dev->crop_current.left;
v_start = dev->crop_current.top/2;
h_stop = (dev->crop_current.left + dev->crop_current.width -1);
v_stop = (dev->crop_current.top + dev->crop_current.height -1)/2;
saa_writeb(SAA7134_VIDEO_H_START1(task), h_start & 0xff);
saa_writeb(SAA7134_VIDEO_H_START2(task), h_start >> 8);
saa_writeb(SAA7134_VIDEO_H_STOP1(task), h_stop & 0xff);
saa_writeb(SAA7134_VIDEO_H_STOP2(task), h_stop >> 8);
saa_writeb(SAA7134_VIDEO_V_START1(task), v_start & 0xff);
saa_writeb(SAA7134_VIDEO_V_START2(task), v_start >> 8);
saa_writeb(SAA7134_VIDEO_V_STOP1(task), v_stop & 0xff);
saa_writeb(SAA7134_VIDEO_V_STOP2(task), v_stop >> 8);
prescale = dev->crop_current.width / width;
if (0 == prescale)
prescale = 1;
xscale = 1024 * dev->crop_current.width / prescale / width;
yscale = 512 * div * dev->crop_current.height / height;
video_dbg("prescale=%d xscale=%d yscale=%d\n",
prescale, xscale, yscale);
set_h_prescale(dev,task,prescale);
saa_writeb(SAA7134_H_SCALE_INC1(task), xscale & 0xff);
saa_writeb(SAA7134_H_SCALE_INC2(task), xscale >> 8);
set_v_scale(dev,task,yscale);
saa_writeb(SAA7134_VIDEO_PIXELS1(task), width & 0xff);
saa_writeb(SAA7134_VIDEO_PIXELS2(task), width >> 8);
saa_writeb(SAA7134_VIDEO_LINES1(task), height/div & 0xff);
saa_writeb(SAA7134_VIDEO_LINES2(task), height/div >> 8);
/* deinterlace y offsets */
y_odd = dev->ctl_y_odd;
y_even = dev->ctl_y_even;
saa_writeb(SAA7134_V_PHASE_OFFSET0(task), y_odd);
saa_writeb(SAA7134_V_PHASE_OFFSET1(task), y_even);
saa_writeb(SAA7134_V_PHASE_OFFSET2(task), y_odd);
saa_writeb(SAA7134_V_PHASE_OFFSET3(task), y_even);
}
/* ------------------------------------------------------------------ */
/*
* Media Controller helper functions
*/
static int saa7134_enable_analog_tuner(struct saa7134_dev *dev)
{
#ifdef CONFIG_MEDIA_CONTROLLER
struct media_device *mdev = dev->media_dev;
struct media_entity *source;
struct media_link *link, *found_link = NULL;
int ret, active_links = 0;
if (!mdev || !dev->decoder)
return 0;
/*
* This will find the tuner that is connected into the decoder.
* Technically, this is not 100% correct, as the device may be
* using an analog input instead of the tuner. However, as we can't
* do DVB streaming while the DMA engine is being used for V4L2,
* this should be enough for the actual needs.
*/
list_for_each_entry(link, &dev->decoder->links, list) {
if (link->sink->entity == dev->decoder) {
found_link = link;
if (link->flags & MEDIA_LNK_FL_ENABLED)
active_links++;
break;
}
}
if (active_links == 1 || !found_link)
return 0;
source = found_link->source->entity;
list_for_each_entry(link, &source->links, list) {
struct media_entity *sink;
int flags = 0;
sink = link->sink->entity;
if (sink == dev->decoder)
flags = MEDIA_LNK_FL_ENABLED;
ret = media_entity_setup_link(link, flags);
if (ret) {
pr_err("Couldn't change link %s->%s to %s. Error %d\n",
source->name, sink->name,
flags ? "enabled" : "disabled",
ret);
return ret;
}
}
#endif
return 0;
}
/* ------------------------------------------------------------------ */
static int buffer_activate(struct saa7134_dev *dev,
struct saa7134_buf *buf,
struct saa7134_buf *next)
{
struct saa7134_dmaqueue *dmaq = buf->vb2.vb2_buf.vb2_queue->drv_priv;
unsigned long base,control,bpl;
unsigned long bpl_uv, lines_uv, base2, base3; /* planar */
video_dbg("buffer_activate buf=%p\n", buf);
buf->top_seen = 0;
set_size(dev, TASK_A, dev->width, dev->height,
V4L2_FIELD_HAS_BOTH(dev->field));
if (dev->fmt->yuv)
saa_andorb(SAA7134_DATA_PATH(TASK_A), 0x3f, 0x03);
else
saa_andorb(SAA7134_DATA_PATH(TASK_A), 0x3f, 0x01);
saa_writeb(SAA7134_OFMT_VIDEO_A, dev->fmt->pm);
/* DMA: setup channel 0 (= Video Task A0) */
base = saa7134_buffer_base(buf);
if (dev->fmt->planar)
bpl = dev->width;
else
bpl = (dev->width * dev->fmt->depth) / 8;
control = SAA7134_RS_CONTROL_BURST_16 |
SAA7134_RS_CONTROL_ME |
(dmaq->pt.dma >> 12);
if (dev->fmt->bswap)
control |= SAA7134_RS_CONTROL_BSWAP;
if (dev->fmt->wswap)
control |= SAA7134_RS_CONTROL_WSWAP;
if (V4L2_FIELD_HAS_BOTH(dev->field)) {
/* interlaced */
saa_writel(SAA7134_RS_BA1(0),base);
saa_writel(SAA7134_RS_BA2(0),base+bpl);
saa_writel(SAA7134_RS_PITCH(0),bpl*2);
} else {
/* non-interlaced */
saa_writel(SAA7134_RS_BA1(0),base);
saa_writel(SAA7134_RS_BA2(0),base);
saa_writel(SAA7134_RS_PITCH(0),bpl);
}
saa_writel(SAA7134_RS_CONTROL(0),control);
if (dev->fmt->planar) {
/* DMA: setup channel 4+5 (= planar task A) */
bpl_uv = bpl >> dev->fmt->hshift;
lines_uv = dev->height >> dev->fmt->vshift;
base2 = base + bpl * dev->height;
base3 = base2 + bpl_uv * lines_uv;
if (dev->fmt->uvswap)
swap(base2, base3);
video_dbg("uv: bpl=%ld lines=%ld base2/3=%ld/%ld\n",
bpl_uv,lines_uv,base2,base3);
if (V4L2_FIELD_HAS_BOTH(dev->field)) {
/* interlaced */
saa_writel(SAA7134_RS_BA1(4),base2);
saa_writel(SAA7134_RS_BA2(4),base2+bpl_uv);
saa_writel(SAA7134_RS_PITCH(4),bpl_uv*2);
saa_writel(SAA7134_RS_BA1(5),base3);
saa_writel(SAA7134_RS_BA2(5),base3+bpl_uv);
saa_writel(SAA7134_RS_PITCH(5),bpl_uv*2);
} else {
/* non-interlaced */
saa_writel(SAA7134_RS_BA1(4),base2);
saa_writel(SAA7134_RS_BA2(4),base2);
saa_writel(SAA7134_RS_PITCH(4),bpl_uv);
saa_writel(SAA7134_RS_BA1(5),base3);
saa_writel(SAA7134_RS_BA2(5),base3);
saa_writel(SAA7134_RS_PITCH(5),bpl_uv);
}
saa_writel(SAA7134_RS_CONTROL(4),control);
saa_writel(SAA7134_RS_CONTROL(5),control);
}
/* start DMA */
saa7134_set_dmabits(dev);
mod_timer(&dmaq->timeout, jiffies + BUFFER_TIMEOUT);
return 0;
}
static int buffer_init(struct vb2_buffer *vb2)
{
struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2);
dmaq->curr = NULL;
buf->activate = buffer_activate;
return 0;
}
static int buffer_prepare(struct vb2_buffer *vb2)
{
struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2);
struct sg_table *dma = vb2_dma_sg_plane_desc(vb2, 0);
unsigned int size;
if (dma->sgl->offset) {
pr_err("The buffer is not page-aligned\n");
return -EINVAL;
}
size = (dev->width * dev->height * dev->fmt->depth) >> 3;
if (vb2_plane_size(vb2, 0) < size)
return -EINVAL;
vb2_set_plane_payload(vb2, 0, size);
vbuf->field = dev->field;
return saa7134_pgtable_build(dev->pci, &dmaq->pt, dma->sgl, dma->nents,
saa7134_buffer_startpage(buf));
}
static int queue_setup(struct vb2_queue *q,
unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct saa7134_dmaqueue *dmaq = q->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
int size = dev->fmt->depth * dev->width * dev->height >> 3;
if (dev->width < 48 ||
dev->height < 32 ||
dev->width/4 > dev->crop_current.width ||
dev->height/4 > dev->crop_current.height ||
dev->width > dev->crop_bounds.width ||
dev->height > dev->crop_bounds.height)
return -EINVAL;
*nbuffers = saa7134_buffer_count(size, *nbuffers);
*nplanes = 1;
sizes[0] = size;
saa7134_enable_analog_tuner(dev);
return 0;
}
/*
* move buffer to hardware queue
*/
void saa7134_vb2_buffer_queue(struct vb2_buffer *vb)
{
struct saa7134_dmaqueue *dmaq = vb->vb2_queue->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2);
saa7134_buffer_queue(dev, dmaq, buf);
}
EXPORT_SYMBOL_GPL(saa7134_vb2_buffer_queue);
int saa7134_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
{
struct saa7134_dmaqueue *dmaq = vq->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
/*
* Planar video capture and TS share the same DMA channel,
* so only one can be active at a time.
*/
if (card_is_empress(dev) && vb2_is_busy(&dev->empress_vbq) &&
dmaq == &dev->video_q && dev->fmt->planar) {
struct saa7134_buf *buf, *tmp;
list_for_each_entry_safe(buf, tmp, &dmaq->queue, entry) {
list_del(&buf->entry);
vb2_buffer_done(&buf->vb2.vb2_buf,
VB2_BUF_STATE_QUEUED);
}
if (dmaq->curr) {
vb2_buffer_done(&dmaq->curr->vb2.vb2_buf,
VB2_BUF_STATE_QUEUED);
dmaq->curr = NULL;
}
return -EBUSY;
}
/* The SAA7134 has a 1K FIFO; the datasheet suggests that when
* configured conservatively, there's 22 usec of buffering for video.
* We therefore request a DMA latency of 20 usec, giving us 2 usec of
* margin in case the FIFO is configured differently to the datasheet.
* Unfortunately, I lack register-level documentation to check the
* Linux FIFO setup and confirm the perfect value.
*/
if ((dmaq == &dev->video_q && !vb2_is_streaming(&dev->vbi_vbq)) ||
(dmaq == &dev->vbi_q && !vb2_is_streaming(&dev->video_vbq)))
cpu_latency_qos_add_request(&dev->qos_request, 20);
dmaq->seq_nr = 0;
return 0;
}
void saa7134_vb2_stop_streaming(struct vb2_queue *vq)
{
struct saa7134_dmaqueue *dmaq = vq->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
saa7134_stop_streaming(dev, dmaq);
if ((dmaq == &dev->video_q && !vb2_is_streaming(&dev->vbi_vbq)) ||
(dmaq == &dev->vbi_q && !vb2_is_streaming(&dev->video_vbq)))
cpu_latency_qos_remove_request(&dev->qos_request);
}
static const struct vb2_ops vb2_qops = {
.queue_setup = queue_setup,
.buf_init = buffer_init,
.buf_prepare = buffer_prepare,
.buf_queue = saa7134_vb2_buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = saa7134_vb2_start_streaming,
.stop_streaming = saa7134_vb2_stop_streaming,
};
/* ------------------------------------------------------------------ */
static int saa7134_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct saa7134_dev *dev = container_of(ctrl->handler, struct saa7134_dev, ctrl_handler);
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
dev->ctl_bright = ctrl->val;
saa_writeb(SAA7134_DEC_LUMA_BRIGHT, ctrl->val);
break;
case V4L2_CID_HUE:
dev->ctl_hue = ctrl->val;
saa_writeb(SAA7134_DEC_CHROMA_HUE, ctrl->val);
break;
case V4L2_CID_CONTRAST:
dev->ctl_contrast = ctrl->val;
saa_writeb(SAA7134_DEC_LUMA_CONTRAST,
dev->ctl_invert ? -dev->ctl_contrast : dev->ctl_contrast);
break;
case V4L2_CID_SATURATION:
dev->ctl_saturation = ctrl->val;
saa_writeb(SAA7134_DEC_CHROMA_SATURATION,
dev->ctl_invert ? -dev->ctl_saturation : dev->ctl_saturation);
break;
case V4L2_CID_AUDIO_MUTE:
dev->ctl_mute = ctrl->val;
saa7134_tvaudio_setmute(dev);
break;
case V4L2_CID_AUDIO_VOLUME:
dev->ctl_volume = ctrl->val;
saa7134_tvaudio_setvolume(dev,dev->ctl_volume);
break;
case V4L2_CID_PRIVATE_INVERT:
dev->ctl_invert = ctrl->val;
saa_writeb(SAA7134_DEC_LUMA_CONTRAST,
dev->ctl_invert ? -dev->ctl_contrast : dev->ctl_contrast);
saa_writeb(SAA7134_DEC_CHROMA_SATURATION,
dev->ctl_invert ? -dev->ctl_saturation : dev->ctl_saturation);
break;
case V4L2_CID_HFLIP:
dev->ctl_mirror = ctrl->val;
break;
case V4L2_CID_PRIVATE_Y_EVEN:
dev->ctl_y_even = ctrl->val;
break;
case V4L2_CID_PRIVATE_Y_ODD:
dev->ctl_y_odd = ctrl->val;
break;
case V4L2_CID_PRIVATE_AUTOMUTE:
{
struct v4l2_priv_tun_config tda9887_cfg;
tda9887_cfg.tuner = TUNER_TDA9887;
tda9887_cfg.priv = &dev->tda9887_conf;
dev->ctl_automute = ctrl->val;
if (dev->tda9887_conf) {
if (dev->ctl_automute)
dev->tda9887_conf |= TDA9887_AUTOMUTE;
else
dev->tda9887_conf &= ~TDA9887_AUTOMUTE;
saa_call_all(dev, tuner, s_config, &tda9887_cfg);
}
break;
}
default:
return -EINVAL;
}
return 0;
}
/* ------------------------------------------------------------------ */
static int video_open(struct file *file)
{
struct video_device *vdev = video_devdata(file);
struct saa7134_dev *dev = video_drvdata(file);
int ret = v4l2_fh_open(file);
if (ret < 0)
return ret;
mutex_lock(&dev->lock);
if (vdev->vfl_type == VFL_TYPE_RADIO) {
/* switch to radio mode */
saa7134_tvaudio_setinput(dev, &card(dev).radio);
saa_call_all(dev, tuner, s_radio);
} else {
/* switch to video/vbi mode */
video_mux(dev, dev->ctl_input);
}
mutex_unlock(&dev->lock);
return 0;
}
static int video_release(struct file *file)
{
struct video_device *vdev = video_devdata(file);
struct saa7134_dev *dev = video_drvdata(file);
struct saa6588_command cmd;
mutex_lock(&dev->lock);
saa7134_tvaudio_close(dev);
if (vdev->vfl_type == VFL_TYPE_RADIO)
v4l2_fh_release(file);
else
_vb2_fop_release(file, NULL);
/* ts-capture will not work in planar mode, so turn it off Hac: 04.05*/
saa_andorb(SAA7134_OFMT_VIDEO_A, 0x1f, 0);
saa_andorb(SAA7134_OFMT_VIDEO_B, 0x1f, 0);
saa_andorb(SAA7134_OFMT_DATA_A, 0x1f, 0);
saa_andorb(SAA7134_OFMT_DATA_B, 0x1f, 0);
saa_call_all(dev, tuner, standby);
if (vdev->vfl_type == VFL_TYPE_RADIO)
saa_call_all(dev, core, command, SAA6588_CMD_CLOSE, &cmd);
mutex_unlock(&dev->lock);
return 0;
}
static ssize_t radio_read(struct file *file, char __user *data,
size_t count, loff_t *ppos)
{
struct saa7134_dev *dev = video_drvdata(file);
struct saa6588_command cmd;
cmd.block_count = count/3;
cmd.nonblocking = file->f_flags & O_NONBLOCK;
cmd.buffer = data;
cmd.instance = file;
cmd.result = -ENODEV;
mutex_lock(&dev->lock);
saa_call_all(dev, core, command, SAA6588_CMD_READ, &cmd);
mutex_unlock(&dev->lock);
return cmd.result;
}
static __poll_t radio_poll(struct file *file, poll_table *wait)
{
struct saa7134_dev *dev = video_drvdata(file);
struct saa6588_command cmd;
__poll_t rc = v4l2_ctrl_poll(file, wait);
cmd.instance = file;
cmd.event_list = wait;
cmd.poll_mask = 0;
mutex_lock(&dev->lock);
saa_call_all(dev, core, command, SAA6588_CMD_POLL, &cmd);
mutex_unlock(&dev->lock);
return rc | cmd.poll_mask;
}
/* ------------------------------------------------------------------ */
static int saa7134_try_get_set_fmt_vbi_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct saa7134_dev *dev = video_drvdata(file);
struct saa7134_tvnorm *norm = dev->tvnorm;
memset(&f->fmt.vbi.reserved, 0, sizeof(f->fmt.vbi.reserved));
f->fmt.vbi.sampling_rate = 6750000 * 4;
f->fmt.vbi.samples_per_line = 2048 /* VBI_LINE_LENGTH */;
f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
f->fmt.vbi.offset = 64 * 4;
f->fmt.vbi.start[0] = norm->vbi_v_start_0;
f->fmt.vbi.count[0] = norm->vbi_v_stop_0 - norm->vbi_v_start_0 +1;
f->fmt.vbi.start[1] = norm->vbi_v_start_1;
f->fmt.vbi.count[1] = f->fmt.vbi.count[0];
f->fmt.vbi.flags = 0; /* VBI_UNSYNC VBI_INTERLACED */
return 0;
}
static int saa7134_g_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct saa7134_dev *dev = video_drvdata(file);
f->fmt.pix.width = dev->width;
f->fmt.pix.height = dev->height;
f->fmt.pix.field = dev->field;
f->fmt.pix.pixelformat = dev->fmt->fourcc;
if (dev->fmt->planar)
f->fmt.pix.bytesperline = f->fmt.pix.width;
else
f->fmt.pix.bytesperline =
(f->fmt.pix.width * dev->fmt->depth) / 8;
f->fmt.pix.sizeimage =
(f->fmt.pix.height * f->fmt.pix.width * dev->fmt->depth) / 8;
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
return 0;
}
static int saa7134_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct saa7134_dev *dev = video_drvdata(file);
struct saa7134_format *fmt;
enum v4l2_field field;
unsigned int maxw, maxh;
fmt = format_by_fourcc(f->fmt.pix.pixelformat);
if (NULL == fmt)
return -EINVAL;
field = f->fmt.pix.field;
maxw = min(dev->crop_current.width*4, dev->crop_bounds.width);
maxh = min(dev->crop_current.height*4, dev->crop_bounds.height);
if (V4L2_FIELD_ANY == field) {
field = (f->fmt.pix.height > maxh/2)
? V4L2_FIELD_INTERLACED
: V4L2_FIELD_BOTTOM;
}
switch (field) {
case V4L2_FIELD_TOP:
case V4L2_FIELD_BOTTOM:
maxh = maxh / 2;
break;
default:
field = V4L2_FIELD_INTERLACED;
break;
}
f->fmt.pix.field = field;
if (f->fmt.pix.width < 48)
f->fmt.pix.width = 48;
if (f->fmt.pix.height < 32)
f->fmt.pix.height = 32;
if (f->fmt.pix.width > maxw)
f->fmt.pix.width = maxw;
if (f->fmt.pix.height > maxh)
f->fmt.pix.height = maxh;
f->fmt.pix.width &= ~0x03;
if (fmt->planar)
f->fmt.pix.bytesperline = f->fmt.pix.width;
else
f->fmt.pix.bytesperline =
(f->fmt.pix.width * fmt->depth) / 8;
f->fmt.pix.sizeimage =
(f->fmt.pix.height * f->fmt.pix.width * fmt->depth) / 8;
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
return 0;
}
static int saa7134_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct saa7134_dev *dev = video_drvdata(file);
int err;
err = saa7134_try_fmt_vid_cap(file, priv, f);
if (0 != err)
return err;
dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
dev->width = f->fmt.pix.width;
dev->height = f->fmt.pix.height;
dev->field = f->fmt.pix.field;
return 0;
}
int saa7134_enum_input(struct file *file, void *priv, struct v4l2_input *i)
{
struct saa7134_dev *dev = video_drvdata(file);
unsigned int n;
n = i->index;
if (n >= SAA7134_INPUT_MAX)
return -EINVAL;
if (card_in(dev, i->index).type == SAA7134_NO_INPUT)
return -EINVAL;
i->index = n;
strscpy(i->name, saa7134_input_name[card_in(dev, n).type],
sizeof(i->name));
switch (card_in(dev, n).type) {
case SAA7134_INPUT_TV:
case SAA7134_INPUT_TV_MONO:
i->type = V4L2_INPUT_TYPE_TUNER;
break;
default:
i->type = V4L2_INPUT_TYPE_CAMERA;
break;
}
if (n == dev->ctl_input) {
int v1 = saa_readb(SAA7134_STATUS_VIDEO1);
int v2 = saa_readb(SAA7134_STATUS_VIDEO2);
if (0 != (v1 & 0x40))
i->status |= V4L2_IN_ST_NO_H_LOCK;
if (0 != (v2 & 0x40))
i->status |= V4L2_IN_ST_NO_SIGNAL;
if (0 != (v2 & 0x0e))
i->status |= V4L2_IN_ST_MACROVISION;
}
i->std = SAA7134_NORMS;
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_enum_input);
int saa7134_g_input(struct file *file, void *priv, unsigned int *i)
{
struct saa7134_dev *dev = video_drvdata(file);
*i = dev->ctl_input;
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_g_input);
int saa7134_s_input(struct file *file, void *priv, unsigned int i)
{
struct saa7134_dev *dev = video_drvdata(file);
if (i >= SAA7134_INPUT_MAX)
return -EINVAL;
if (card_in(dev, i).type == SAA7134_NO_INPUT)
return -EINVAL;
video_mux(dev, i);
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_s_input);
int saa7134_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
struct saa7134_dev *dev = video_drvdata(file);
strscpy(cap->driver, "saa7134", sizeof(cap->driver));
strscpy(cap->card, saa7134_boards[dev->board].name,
sizeof(cap->card));
cap->capabilities = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
V4L2_CAP_RADIO | V4L2_CAP_VIDEO_CAPTURE |
V4L2_CAP_VBI_CAPTURE | V4L2_CAP_DEVICE_CAPS;
if (dev->tuner_type != TUNER_ABSENT && dev->tuner_type != UNSET)
cap->capabilities |= V4L2_CAP_TUNER;
if (dev->has_rds)
cap->capabilities |= V4L2_CAP_RDS_CAPTURE;
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_querycap);
int saa7134_s_std(struct file *file, void *priv, v4l2_std_id id)
{
struct saa7134_dev *dev = video_drvdata(file);
unsigned int i;
v4l2_std_id fixup;
for (i = 0; i < TVNORMS; i++)
if (id == tvnorms[i].id)
break;
if (i == TVNORMS)
for (i = 0; i < TVNORMS; i++)
if (id & tvnorms[i].id)
break;
if (i == TVNORMS)
return -EINVAL;
if ((id & V4L2_STD_SECAM) && (secam[0] != '-')) {
if (secam[0] == 'L' || secam[0] == 'l') {
if (secam[1] == 'C' || secam[1] == 'c')
fixup = V4L2_STD_SECAM_LC;
else
fixup = V4L2_STD_SECAM_L;
} else {
if (secam[0] == 'D' || secam[0] == 'd')
fixup = V4L2_STD_SECAM_DK;
else
fixup = V4L2_STD_SECAM;
}
for (i = 0; i < TVNORMS; i++) {
if (fixup == tvnorms[i].id)
break;
}
if (i == TVNORMS)
return -EINVAL;
}
set_tvnorm(dev, &tvnorms[i]);
saa7134_tvaudio_do_scan(dev);
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_s_std);
int saa7134_g_std(struct file *file, void *priv, v4l2_std_id *id)
{
struct saa7134_dev *dev = video_drvdata(file);
*id = dev->tvnorm->id;
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_g_std);
static v4l2_std_id saa7134_read_std(struct saa7134_dev *dev)
{
static v4l2_std_id stds[] = {
V4L2_STD_UNKNOWN,
V4L2_STD_NTSC,
V4L2_STD_PAL,
V4L2_STD_SECAM };
v4l2_std_id result = 0;
u8 st1 = saa_readb(SAA7134_STATUS_VIDEO1);
u8 st2 = saa_readb(SAA7134_STATUS_VIDEO2);
if (!(st2 & 0x1)) /* RDCAP == 0 */
result = V4L2_STD_UNKNOWN;
else
result = stds[st1 & 0x03];
return result;
}
int saa7134_querystd(struct file *file, void *priv, v4l2_std_id *std)
{
struct saa7134_dev *dev = video_drvdata(file);
*std &= saa7134_read_std(dev);
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_querystd);
static int saa7134_g_pixelaspect(struct file *file, void *priv,
int type, struct v4l2_fract *f)
{
struct saa7134_dev *dev = video_drvdata(file);
if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
if (dev->tvnorm->id & V4L2_STD_525_60) {
f->numerator = 11;
f->denominator = 10;
}
if (dev->tvnorm->id & V4L2_STD_625_50) {
f->numerator = 54;
f->denominator = 59;
}
return 0;
}
static int saa7134_g_selection(struct file *file, void *f, struct v4l2_selection *sel)
{
struct saa7134_dev *dev = video_drvdata(file);
if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
switch (sel->target) {
case V4L2_SEL_TGT_CROP:
sel->r = dev->crop_current;
break;
case V4L2_SEL_TGT_CROP_DEFAULT:
sel->r = dev->crop_defrect;
break;
case V4L2_SEL_TGT_CROP_BOUNDS:
sel->r = dev->crop_bounds;
break;
default:
return -EINVAL;
}
return 0;
}
static int saa7134_s_selection(struct file *file, void *f, struct v4l2_selection *sel)
{
struct saa7134_dev *dev = video_drvdata(file);
struct v4l2_rect *b = &dev->crop_bounds;
struct v4l2_rect *c = &dev->crop_current;
if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
if (sel->target != V4L2_SEL_TGT_CROP)
return -EINVAL;
if (vb2_is_streaming(&dev->video_vbq))
return -EBUSY;
*c = sel->r;
if (c->top < b->top)
c->top = b->top;
if (c->top > b->top + b->height)
c->top = b->top + b->height;
if (c->height > b->top - c->top + b->height)
c->height = b->top - c->top + b->height;
if (c->left < b->left)
c->left = b->left;
if (c->left > b->left + b->width)
c->left = b->left + b->width;
if (c->width > b->left - c->left + b->width)
c->width = b->left - c->left + b->width;
sel->r = *c;
return 0;
}
int saa7134_g_tuner(struct file *file, void *priv,
struct v4l2_tuner *t)
{
struct saa7134_dev *dev = video_drvdata(file);
int n;
if (0 != t->index)
return -EINVAL;
memset(t, 0, sizeof(*t));
for (n = 0; n < SAA7134_INPUT_MAX; n++) {
if (card_in(dev, n).type == SAA7134_INPUT_TV ||
card_in(dev, n).type == SAA7134_INPUT_TV_MONO)
break;
}
if (n == SAA7134_INPUT_MAX)
return -EINVAL;
if (card_in(dev, n).type != SAA7134_NO_INPUT) {
strscpy(t->name, "Television", sizeof(t->name));
t->type = V4L2_TUNER_ANALOG_TV;
saa_call_all(dev, tuner, g_tuner, t);
t->capability = V4L2_TUNER_CAP_NORM |
V4L2_TUNER_CAP_STEREO |
V4L2_TUNER_CAP_LANG1 |
V4L2_TUNER_CAP_LANG2;
t->rxsubchans = saa7134_tvaudio_getstereo(dev);
t->audmode = saa7134_tvaudio_rx2mode(t->rxsubchans);
}
if (0 != (saa_readb(SAA7134_STATUS_VIDEO1) & 0x03))
t->signal = 0xffff;
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_g_tuner);
int saa7134_s_tuner(struct file *file, void *priv,
const struct v4l2_tuner *t)
{
struct saa7134_dev *dev = video_drvdata(file);
int rx, mode;
if (0 != t->index)
return -EINVAL;
mode = dev->thread.mode;
if (UNSET == mode) {
rx = saa7134_tvaudio_getstereo(dev);
mode = saa7134_tvaudio_rx2mode(rx);
}
if (mode != t->audmode)
dev->thread.mode = t->audmode;
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_s_tuner);
int saa7134_g_frequency(struct file *file, void *priv,
struct v4l2_frequency *f)
{
struct saa7134_dev *dev = video_drvdata(file);
if (0 != f->tuner)
return -EINVAL;
saa_call_all(dev, tuner, g_frequency, f);
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_g_frequency);
int saa7134_s_frequency(struct file *file, void *priv,
const struct v4l2_frequency *f)
{
struct saa7134_dev *dev = video_drvdata(file);
if (0 != f->tuner)
return -EINVAL;
saa_call_all(dev, tuner, s_frequency, f);
saa7134_tvaudio_do_scan(dev);
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_s_frequency);
static int saa7134_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
if (f->index >= FORMATS)
return -EINVAL;
f->pixelformat = formats[f->index].fourcc;
return 0;
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int vidioc_g_register (struct file *file, void *priv,
struct v4l2_dbg_register *reg)
{
struct saa7134_dev *dev = video_drvdata(file);
reg->val = saa_readb(reg->reg & 0xffffff);
reg->size = 1;
return 0;
}
static int vidioc_s_register (struct file *file, void *priv,
const struct v4l2_dbg_register *reg)
{
struct saa7134_dev *dev = video_drvdata(file);
saa_writeb(reg->reg & 0xffffff, reg->val);
return 0;
}
#endif
static int radio_g_tuner(struct file *file, void *priv,
struct v4l2_tuner *t)
{
struct saa7134_dev *dev = video_drvdata(file);
if (0 != t->index)
return -EINVAL;
strscpy(t->name, "Radio", sizeof(t->name));
saa_call_all(dev, tuner, g_tuner, t);
t->audmode &= V4L2_TUNER_MODE_MONO | V4L2_TUNER_MODE_STEREO;
if (dev->input->amux == TV) {
t->signal = 0xf800 - ((saa_readb(0x581) & 0x1f) << 11);
t->rxsubchans = (saa_readb(0x529) & 0x08) ?
V4L2_TUNER_SUB_STEREO : V4L2_TUNER_SUB_MONO;
}
return 0;
}
static int radio_s_tuner(struct file *file, void *priv,
const struct v4l2_tuner *t)
{
struct saa7134_dev *dev = video_drvdata(file);
if (0 != t->index)
return -EINVAL;
saa_call_all(dev, tuner, s_tuner, t);
return 0;
}
static const struct v4l2_file_operations video_fops =
{
.owner = THIS_MODULE,
.open = video_open,
.release = video_release,
.read = vb2_fop_read,
.poll = vb2_fop_poll,
.mmap = vb2_fop_mmap,
.unlocked_ioctl = video_ioctl2,
};
static const struct v4l2_ioctl_ops video_ioctl_ops = {
.vidioc_querycap = saa7134_querycap,
.vidioc_enum_fmt_vid_cap = saa7134_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = saa7134_g_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = saa7134_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = saa7134_s_fmt_vid_cap,
.vidioc_g_fmt_vbi_cap = saa7134_try_get_set_fmt_vbi_cap,
.vidioc_try_fmt_vbi_cap = saa7134_try_get_set_fmt_vbi_cap,
.vidioc_s_fmt_vbi_cap = saa7134_try_get_set_fmt_vbi_cap,
.vidioc_g_pixelaspect = saa7134_g_pixelaspect,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_expbuf = vb2_ioctl_expbuf,
.vidioc_s_std = saa7134_s_std,
.vidioc_g_std = saa7134_g_std,
.vidioc_querystd = saa7134_querystd,
.vidioc_enum_input = saa7134_enum_input,
.vidioc_g_input = saa7134_g_input,
.vidioc_s_input = saa7134_s_input,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_g_tuner = saa7134_g_tuner,
.vidioc_s_tuner = saa7134_s_tuner,
.vidioc_g_selection = saa7134_g_selection,
.vidioc_s_selection = saa7134_s_selection,
.vidioc_g_frequency = saa7134_g_frequency,
.vidioc_s_frequency = saa7134_s_frequency,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.vidioc_g_register = vidioc_g_register,
.vidioc_s_register = vidioc_s_register,
#endif
.vidioc_log_status = v4l2_ctrl_log_status,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
static const struct v4l2_file_operations radio_fops = {
.owner = THIS_MODULE,
.open = video_open,
.read = radio_read,
.release = video_release,
.unlocked_ioctl = video_ioctl2,
.poll = radio_poll,
};
static const struct v4l2_ioctl_ops radio_ioctl_ops = {
.vidioc_querycap = saa7134_querycap,
.vidioc_g_tuner = radio_g_tuner,
.vidioc_s_tuner = radio_s_tuner,
.vidioc_g_frequency = saa7134_g_frequency,
.vidioc_s_frequency = saa7134_s_frequency,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
/* ----------------------------------------------------------- */
/* exported stuff */
struct video_device saa7134_video_template = {
.name = "saa7134-video",
.fops = &video_fops,
.ioctl_ops = &video_ioctl_ops,
.tvnorms = SAA7134_NORMS,
};
struct video_device saa7134_radio_template = {
.name = "saa7134-radio",
.fops = &radio_fops,
.ioctl_ops = &radio_ioctl_ops,
};
static const struct v4l2_ctrl_ops saa7134_ctrl_ops = {
.s_ctrl = saa7134_s_ctrl,
};
static const struct v4l2_ctrl_config saa7134_ctrl_invert = {
.ops = &saa7134_ctrl_ops,
.id = V4L2_CID_PRIVATE_INVERT,
.name = "Invert",
.type = V4L2_CTRL_TYPE_BOOLEAN,
.min = 0,
.max = 1,
.step = 1,
};
static const struct v4l2_ctrl_config saa7134_ctrl_y_odd = {
.ops = &saa7134_ctrl_ops,
.id = V4L2_CID_PRIVATE_Y_ODD,
.name = "Y Offset Odd Field",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = 128,
.step = 1,
};
static const struct v4l2_ctrl_config saa7134_ctrl_y_even = {
.ops = &saa7134_ctrl_ops,
.id = V4L2_CID_PRIVATE_Y_EVEN,
.name = "Y Offset Even Field",
.type = V4L2_CTRL_TYPE_INTEGER,
.min = 0,
.max = 128,
.step = 1,
};
static const struct v4l2_ctrl_config saa7134_ctrl_automute = {
.ops = &saa7134_ctrl_ops,
.id = V4L2_CID_PRIVATE_AUTOMUTE,
.name = "Automute",
.type = V4L2_CTRL_TYPE_BOOLEAN,
.min = 0,
.max = 1,
.step = 1,
.def = 1,
};
int saa7134_video_init1(struct saa7134_dev *dev)
{
struct v4l2_ctrl_handler *hdl = &dev->ctrl_handler;
struct vb2_queue *q;
int ret;
/* sanitycheck insmod options */
if (gbuffers < 2 || gbuffers > VIDEO_MAX_FRAME)
gbuffers = 2;
if (gbufsize > gbufsize_max)
gbufsize = gbufsize_max;
gbufsize = (gbufsize + PAGE_SIZE - 1) & PAGE_MASK;
v4l2_ctrl_handler_init(hdl, 11);
v4l2_ctrl_new_std(hdl, &saa7134_ctrl_ops,
V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
v4l2_ctrl_new_std(hdl, &saa7134_ctrl_ops,
V4L2_CID_CONTRAST, 0, 127, 1, 68);
v4l2_ctrl_new_std(hdl, &saa7134_ctrl_ops,
V4L2_CID_SATURATION, 0, 127, 1, 64);
v4l2_ctrl_new_std(hdl, &saa7134_ctrl_ops,
V4L2_CID_HUE, -128, 127, 1, 0);
v4l2_ctrl_new_std(hdl, &saa7134_ctrl_ops,
V4L2_CID_HFLIP, 0, 1, 1, 0);
v4l2_ctrl_new_std(hdl, &saa7134_ctrl_ops,
V4L2_CID_AUDIO_MUTE, 0, 1, 1, 0);
v4l2_ctrl_new_std(hdl, &saa7134_ctrl_ops,
V4L2_CID_AUDIO_VOLUME, -15, 15, 1, 0);
v4l2_ctrl_new_custom(hdl, &saa7134_ctrl_invert, NULL);
v4l2_ctrl_new_custom(hdl, &saa7134_ctrl_y_odd, NULL);
v4l2_ctrl_new_custom(hdl, &saa7134_ctrl_y_even, NULL);
v4l2_ctrl_new_custom(hdl, &saa7134_ctrl_automute, NULL);
if (hdl->error)
return hdl->error;
if (card_has_radio(dev)) {
hdl = &dev->radio_ctrl_handler;
v4l2_ctrl_handler_init(hdl, 2);
v4l2_ctrl_add_handler(hdl, &dev->ctrl_handler,
v4l2_ctrl_radio_filter, false);
if (hdl->error)
return hdl->error;
}
dev->ctl_mute = 1;
if (dev->tda9887_conf && saa7134_ctrl_automute.def)
dev->tda9887_conf |= TDA9887_AUTOMUTE;
dev->automute = 0;
INIT_LIST_HEAD(&dev->video_q.queue);
timer_setup(&dev->video_q.timeout, saa7134_buffer_timeout, 0);
dev->video_q.dev = dev;
dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24);
dev->width = 720;
dev->height = 576;
dev->field = V4L2_FIELD_INTERLACED;
if (saa7134_boards[dev->board].video_out)
saa7134_videoport_init(dev);
q = &dev->video_vbq;
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
/*
* Do not add VB2_USERPTR unless explicitly requested: the saa7134 DMA
* engine cannot handle transfers that do not start at the beginning
* of a page. A user-provided pointer can start anywhere in a page, so
* USERPTR support is a no-go unless the application knows about these
* limitations and has special support for this.
*/
q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
if (saa7134_userptr)
q->io_modes |= VB2_USERPTR;
q->drv_priv = &dev->video_q;
q->ops = &vb2_qops;
q->gfp_flags = GFP_DMA32;
q->mem_ops = &vb2_dma_sg_memops;
q->buf_struct_size = sizeof(struct saa7134_buf);
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &dev->lock;
q->dev = &dev->pci->dev;
ret = vb2_queue_init(q);
if (ret)
return ret;
saa7134_pgtable_alloc(dev->pci, &dev->video_q.pt);
q = &dev->vbi_vbq;
q->type = V4L2_BUF_TYPE_VBI_CAPTURE;
/* Don't add VB2_USERPTR, see comment above */
q->io_modes = VB2_MMAP | VB2_READ;
if (saa7134_userptr)
q->io_modes |= VB2_USERPTR;
q->drv_priv = &dev->vbi_q;
q->ops = &saa7134_vbi_qops;
q->gfp_flags = GFP_DMA32;
q->mem_ops = &vb2_dma_sg_memops;
q->buf_struct_size = sizeof(struct saa7134_buf);
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &dev->lock;
q->dev = &dev->pci->dev;
ret = vb2_queue_init(q);
if (ret)
return ret;
saa7134_pgtable_alloc(dev->pci, &dev->vbi_q.pt);
return 0;
}
void saa7134_video_fini(struct saa7134_dev *dev)
{
del_timer_sync(&dev->video_q.timeout);
/* free stuff */
saa7134_pgtable_free(dev->pci, &dev->video_q.pt);
saa7134_pgtable_free(dev->pci, &dev->vbi_q.pt);
v4l2_ctrl_handler_free(&dev->ctrl_handler);
if (card_has_radio(dev))
v4l2_ctrl_handler_free(&dev->radio_ctrl_handler);
}
int saa7134_videoport_init(struct saa7134_dev *dev)
{
/* enable video output */
int vo = saa7134_boards[dev->board].video_out;
int video_reg;
unsigned int vid_port_opts = saa7134_boards[dev->board].vid_port_opts;
/* Configure videoport */
saa_writeb(SAA7134_VIDEO_PORT_CTRL0, video_out[vo][0]);
video_reg = video_out[vo][1];
if (vid_port_opts & SET_T_CODE_POLARITY_NON_INVERTED)
video_reg &= ~VP_T_CODE_P_INVERTED;
saa_writeb(SAA7134_VIDEO_PORT_CTRL1, video_reg);
saa_writeb(SAA7134_VIDEO_PORT_CTRL2, video_out[vo][2]);
saa_writeb(SAA7134_VIDEO_PORT_CTRL4, video_out[vo][4]);
video_reg = video_out[vo][5];
if (vid_port_opts & SET_CLOCK_NOT_DELAYED)
video_reg &= ~VP_CLK_CTRL2_DELAYED;
if (vid_port_opts & SET_CLOCK_INVERTED)
video_reg |= VP_CLK_CTRL1_INVERTED;
saa_writeb(SAA7134_VIDEO_PORT_CTRL5, video_reg);
video_reg = video_out[vo][6];
if (vid_port_opts & SET_VSYNC_OFF) {
video_reg &= ~VP_VS_TYPE_MASK;
video_reg |= VP_VS_TYPE_OFF;
}
saa_writeb(SAA7134_VIDEO_PORT_CTRL6, video_reg);
saa_writeb(SAA7134_VIDEO_PORT_CTRL7, video_out[vo][7]);
saa_writeb(SAA7134_VIDEO_PORT_CTRL8, video_out[vo][8]);
/* Start videoport */
saa_writeb(SAA7134_VIDEO_PORT_CTRL3, video_out[vo][3]);
return 0;
}
int saa7134_video_init2(struct saa7134_dev *dev)
{
/* init video hw */
set_tvnorm(dev,&tvnorms[0]);
video_mux(dev,0);
v4l2_ctrl_handler_setup(&dev->ctrl_handler);
saa7134_tvaudio_setmute(dev);
saa7134_tvaudio_setvolume(dev,dev->ctl_volume);
return 0;
}
void saa7134_irq_video_signalchange(struct saa7134_dev *dev)
{
static const char *st[] = {
"(no signal)", "NTSC", "PAL", "SECAM" };
u32 st1,st2;
st1 = saa_readb(SAA7134_STATUS_VIDEO1);
st2 = saa_readb(SAA7134_STATUS_VIDEO2);
video_dbg("DCSDT: pll: %s, sync: %s, norm: %s\n",
(st1 & 0x40) ? "not locked" : "locked",
(st2 & 0x40) ? "no" : "yes",
st[st1 & 0x03]);
dev->nosignal = (st1 & 0x40) || (st2 & 0x40) || !(st2 & 0x1);
if (dev->nosignal) {
/* no video signal -> mute audio */
if (dev->ctl_automute)
dev->automute = 1;
saa7134_tvaudio_setmute(dev);
} else {
/* wake up tvaudio audio carrier scan thread */
saa7134_tvaudio_do_scan(dev);
}
if ((st2 & 0x80) && !noninterlaced && !dev->nosignal)
saa_clearb(SAA7134_SYNC_CTRL, 0x20);
else
saa_setb(SAA7134_SYNC_CTRL, 0x20);
if (dev->mops && dev->mops->signal_change)
dev->mops->signal_change(dev);
}
void saa7134_irq_video_done(struct saa7134_dev *dev, unsigned long status)
{
enum v4l2_field field;
spin_lock(&dev->slock);
if (dev->video_q.curr) {
field = dev->field;
if (V4L2_FIELD_HAS_BOTH(field)) {
/* make sure we have seen both fields */
if ((status & 0x10) == 0x00) {
dev->video_q.curr->top_seen = 1;
goto done;
}
if (!dev->video_q.curr->top_seen)
goto done;
} else if (field == V4L2_FIELD_TOP) {
if ((status & 0x10) != 0x10)
goto done;
} else if (field == V4L2_FIELD_BOTTOM) {
if ((status & 0x10) != 0x00)
goto done;
}
saa7134_buffer_finish(dev, &dev->video_q, VB2_BUF_STATE_DONE);
}
saa7134_buffer_next(dev, &dev->video_q);
done:
spin_unlock(&dev->slock);
}
| linux-master | drivers/media/pci/saa7134/saa7134-video.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* device driver for philips saa7134 based TV cards
* video4linux video interface
*
* (c) 2001,02 Gerd Knorr <[email protected]> [SuSE Labs]
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
/* ------------------------------------------------------------------ */
static unsigned int ts_debug;
module_param(ts_debug, int, 0644);
MODULE_PARM_DESC(ts_debug,"enable debug messages [ts]");
#define ts_dbg(fmt, arg...) do { \
if (ts_debug) \
printk(KERN_DEBUG pr_fmt("ts: " fmt), ## arg); \
} while (0)
/* ------------------------------------------------------------------ */
static int buffer_activate(struct saa7134_dev *dev,
struct saa7134_buf *buf,
struct saa7134_buf *next)
{
ts_dbg("buffer_activate [%p]", buf);
buf->top_seen = 0;
if (!dev->ts_started)
dev->ts_field = V4L2_FIELD_TOP;
if (NULL == next)
next = buf;
if (V4L2_FIELD_TOP == dev->ts_field) {
ts_dbg("- [top] buf=%p next=%p\n", buf, next);
saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(buf));
saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(next));
dev->ts_field = V4L2_FIELD_BOTTOM;
} else {
ts_dbg("- [bottom] buf=%p next=%p\n", buf, next);
saa_writel(SAA7134_RS_BA1(5),saa7134_buffer_base(next));
saa_writel(SAA7134_RS_BA2(5),saa7134_buffer_base(buf));
dev->ts_field = V4L2_FIELD_TOP;
}
/* start DMA */
saa7134_set_dmabits(dev);
mod_timer(&dev->ts_q.timeout, jiffies+TS_BUFFER_TIMEOUT);
if (!dev->ts_started)
saa7134_ts_start(dev);
return 0;
}
int saa7134_ts_buffer_init(struct vb2_buffer *vb2)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2);
dmaq->curr = NULL;
buf->activate = buffer_activate;
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_ts_buffer_init);
int saa7134_ts_buffer_prepare(struct vb2_buffer *vb2)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2);
struct saa7134_dmaqueue *dmaq = vb2->vb2_queue->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
struct saa7134_buf *buf = container_of(vbuf, struct saa7134_buf, vb2);
struct sg_table *dma = vb2_dma_sg_plane_desc(vb2, 0);
unsigned int lines, llength, size;
ts_dbg("buffer_prepare [%p]\n", buf);
llength = TS_PACKET_SIZE;
lines = dev->ts.nr_packets;
size = lines * llength;
if (vb2_plane_size(vb2, 0) < size)
return -EINVAL;
vb2_set_plane_payload(vb2, 0, size);
vbuf->field = dev->field;
return saa7134_pgtable_build(dev->pci, &dmaq->pt, dma->sgl, dma->nents,
saa7134_buffer_startpage(buf));
}
EXPORT_SYMBOL_GPL(saa7134_ts_buffer_prepare);
int saa7134_ts_queue_setup(struct vb2_queue *q,
unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct saa7134_dmaqueue *dmaq = q->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
int size = TS_PACKET_SIZE * dev->ts.nr_packets;
if (0 == *nbuffers)
*nbuffers = dev->ts.nr_bufs;
*nbuffers = saa7134_buffer_count(size, *nbuffers);
if (*nbuffers < 3)
*nbuffers = 3;
*nplanes = 1;
sizes[0] = size;
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_ts_queue_setup);
int saa7134_ts_start_streaming(struct vb2_queue *vq, unsigned int count)
{
struct saa7134_dmaqueue *dmaq = vq->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
/*
* Planar video capture and TS share the same DMA channel,
* so only one can be active at a time.
*/
if (vb2_is_busy(&dev->video_vbq) && dev->fmt->planar) {
struct saa7134_buf *buf, *tmp;
list_for_each_entry_safe(buf, tmp, &dmaq->queue, entry) {
list_del(&buf->entry);
vb2_buffer_done(&buf->vb2.vb2_buf,
VB2_BUF_STATE_QUEUED);
}
if (dmaq->curr) {
vb2_buffer_done(&dmaq->curr->vb2.vb2_buf,
VB2_BUF_STATE_QUEUED);
dmaq->curr = NULL;
}
return -EBUSY;
}
dmaq->seq_nr = 0;
return 0;
}
EXPORT_SYMBOL_GPL(saa7134_ts_start_streaming);
void saa7134_ts_stop_streaming(struct vb2_queue *vq)
{
struct saa7134_dmaqueue *dmaq = vq->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
saa7134_ts_stop(dev);
saa7134_stop_streaming(dev, dmaq);
}
EXPORT_SYMBOL_GPL(saa7134_ts_stop_streaming);
struct vb2_ops saa7134_ts_qops = {
.queue_setup = saa7134_ts_queue_setup,
.buf_init = saa7134_ts_buffer_init,
.buf_prepare = saa7134_ts_buffer_prepare,
.buf_queue = saa7134_vb2_buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.stop_streaming = saa7134_ts_stop_streaming,
};
EXPORT_SYMBOL_GPL(saa7134_ts_qops);
/* ----------------------------------------------------------- */
/* exported stuff */
static unsigned int tsbufs = 8;
module_param(tsbufs, int, 0444);
MODULE_PARM_DESC(tsbufs, "number of ts buffers for read/write IO, range 2-32");
static unsigned int ts_nr_packets = 64;
module_param(ts_nr_packets, int, 0444);
MODULE_PARM_DESC(ts_nr_packets,"size of a ts buffers (in ts packets)");
int saa7134_ts_init_hw(struct saa7134_dev *dev)
{
/* deactivate TS softreset */
saa_writeb(SAA7134_TS_SERIAL1, 0x00);
/* TSSOP high active, TSVAL high active, TSLOCK ignored */
saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
saa_writeb(SAA7134_TS_PARALLEL_SERIAL, (TS_PACKET_SIZE-1));
saa_writeb(SAA7134_TS_DMA0, ((dev->ts.nr_packets-1)&0xff));
saa_writeb(SAA7134_TS_DMA1, (((dev->ts.nr_packets-1)>>8)&0xff));
/* TSNOPIT=0, TSCOLAP=0 */
saa_writeb(SAA7134_TS_DMA2,
((((dev->ts.nr_packets-1)>>16)&0x3f) | 0x00));
return 0;
}
int saa7134_ts_init1(struct saa7134_dev *dev)
{
/* sanitycheck insmod options */
if (tsbufs < 2)
tsbufs = 2;
if (tsbufs > VIDEO_MAX_FRAME)
tsbufs = VIDEO_MAX_FRAME;
if (ts_nr_packets < 4)
ts_nr_packets = 4;
if (ts_nr_packets > 312)
ts_nr_packets = 312;
dev->ts.nr_bufs = tsbufs;
dev->ts.nr_packets = ts_nr_packets;
INIT_LIST_HEAD(&dev->ts_q.queue);
timer_setup(&dev->ts_q.timeout, saa7134_buffer_timeout, 0);
dev->ts_q.dev = dev;
dev->ts_q.need_two = 1;
dev->ts_started = 0;
saa7134_pgtable_alloc(dev->pci, &dev->ts_q.pt);
/* init TS hw */
saa7134_ts_init_hw(dev);
return 0;
}
/* Function for stop TS */
int saa7134_ts_stop(struct saa7134_dev *dev)
{
ts_dbg("TS stop\n");
if (!dev->ts_started)
return 0;
/* Stop TS stream */
switch (saa7134_boards[dev->board].ts_type) {
case SAA7134_MPEG_TS_PARALLEL:
saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
dev->ts_started = 0;
break;
case SAA7134_MPEG_TS_SERIAL:
saa_writeb(SAA7134_TS_SERIAL0, 0x40);
dev->ts_started = 0;
break;
}
return 0;
}
/* Function for start TS */
int saa7134_ts_start(struct saa7134_dev *dev)
{
ts_dbg("TS start\n");
if (WARN_ON(dev->ts_started))
return 0;
/* dma: setup channel 5 (= TS) */
saa_writeb(SAA7134_TS_DMA0, (dev->ts.nr_packets - 1) & 0xff);
saa_writeb(SAA7134_TS_DMA1,
((dev->ts.nr_packets - 1) >> 8) & 0xff);
/* TSNOPIT=0, TSCOLAP=0 */
saa_writeb(SAA7134_TS_DMA2,
(((dev->ts.nr_packets - 1) >> 16) & 0x3f) | 0x00);
saa_writel(SAA7134_RS_PITCH(5), TS_PACKET_SIZE);
saa_writel(SAA7134_RS_CONTROL(5), SAA7134_RS_CONTROL_BURST_16 |
SAA7134_RS_CONTROL_ME |
(dev->ts_q.pt.dma >> 12));
/* reset hardware TS buffers */
saa_writeb(SAA7134_TS_SERIAL1, 0x00);
saa_writeb(SAA7134_TS_SERIAL1, 0x03);
saa_writeb(SAA7134_TS_SERIAL1, 0x00);
saa_writeb(SAA7134_TS_SERIAL1, 0x01);
/* TS clock non-inverted */
saa_writeb(SAA7134_TS_SERIAL1, 0x00);
/* Start TS stream */
switch (saa7134_boards[dev->board].ts_type) {
case SAA7134_MPEG_TS_PARALLEL:
saa_writeb(SAA7134_TS_SERIAL0, 0x40);
saa_writeb(SAA7134_TS_PARALLEL, 0xec |
(saa7134_boards[dev->board].ts_force_val << 4));
break;
case SAA7134_MPEG_TS_SERIAL:
saa_writeb(SAA7134_TS_SERIAL0, 0xd8);
saa_writeb(SAA7134_TS_PARALLEL, 0x6c |
(saa7134_boards[dev->board].ts_force_val << 4));
saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 0xbc);
saa_writeb(SAA7134_TS_SERIAL1, 0x02);
break;
}
dev->ts_started = 1;
return 0;
}
int saa7134_ts_fini(struct saa7134_dev *dev)
{
del_timer_sync(&dev->ts_q.timeout);
saa7134_pgtable_free(dev->pci, &dev->ts_q.pt);
return 0;
}
void saa7134_irq_ts_done(struct saa7134_dev *dev, unsigned long status)
{
enum v4l2_field field;
spin_lock(&dev->slock);
if (dev->ts_q.curr) {
field = dev->ts_field;
if (field != V4L2_FIELD_TOP) {
if ((status & 0x100000) != 0x000000)
goto done;
} else {
if ((status & 0x100000) != 0x100000)
goto done;
}
saa7134_buffer_finish(dev, &dev->ts_q, VB2_BUF_STATE_DONE);
}
saa7134_buffer_next(dev,&dev->ts_q);
done:
spin_unlock(&dev->slock);
}
| linux-master | drivers/media/pci/saa7134/saa7134-ts.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* device driver for philips saa7134 based TV cards
* i2c interface support
*
* (c) 2001,02 Gerd Knorr <[email protected]> [SuSE Labs]
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <media/v4l2-common.h>
/* ----------------------------------------------------------- */
static unsigned int i2c_debug;
module_param(i2c_debug, int, 0644);
MODULE_PARM_DESC(i2c_debug,"enable debug messages [i2c]");
static unsigned int i2c_scan;
module_param(i2c_scan, int, 0444);
MODULE_PARM_DESC(i2c_scan,"scan i2c bus at insmod time");
#define i2c_dbg(level, fmt, arg...) do { \
if (i2c_debug == level) \
printk(KERN_DEBUG pr_fmt("i2c: " fmt), ## arg); \
} while (0)
#define i2c_cont(level, fmt, arg...) do { \
if (i2c_debug == level) \
pr_cont(fmt, ## arg); \
} while (0)
#define I2C_WAIT_DELAY 32
#define I2C_WAIT_RETRY 16
/* ----------------------------------------------------------- */
static char *str_i2c_status[] = {
"IDLE", "DONE_STOP", "BUSY", "TO_SCL", "TO_ARB", "DONE_WRITE",
"DONE_READ", "DONE_WRITE_TO", "DONE_READ_TO", "NO_DEVICE",
"NO_ACKN", "BUS_ERR", "ARB_LOST", "SEQ_ERR", "ST_ERR", "SW_ERR"
};
enum i2c_status {
IDLE = 0, // no I2C command pending
DONE_STOP = 1, // I2C command done and STOP executed
BUSY = 2, // executing I2C command
TO_SCL = 3, // executing I2C command, time out on clock stretching
TO_ARB = 4, // time out on arbitration trial, still trying
DONE_WRITE = 5, // I2C command done and awaiting next write command
DONE_READ = 6, // I2C command done and awaiting next read command
DONE_WRITE_TO = 7, // see 5, and time out on status echo
DONE_READ_TO = 8, // see 6, and time out on status echo
NO_DEVICE = 9, // no acknowledge on device slave address
NO_ACKN = 10, // no acknowledge after data byte transfer
BUS_ERR = 11, // bus error
ARB_LOST = 12, // arbitration lost during transfer
SEQ_ERR = 13, // erroneous programming sequence
ST_ERR = 14, // wrong status echoing
SW_ERR = 15 // software error
};
static char *str_i2c_attr[] = {
"NOP", "STOP", "CONTINUE", "START"
};
enum i2c_attr {
NOP = 0, // no operation on I2C bus
STOP = 1, // stop condition, no associated byte transfer
CONTINUE = 2, // continue with byte transfer
START = 3 // start condition with byte transfer
};
static inline enum i2c_status i2c_get_status(struct saa7134_dev *dev)
{
enum i2c_status status;
status = saa_readb(SAA7134_I2C_ATTR_STATUS) & 0x0f;
i2c_dbg(2, "i2c stat <= %s\n", str_i2c_status[status]);
return status;
}
static inline void i2c_set_status(struct saa7134_dev *dev,
enum i2c_status status)
{
i2c_dbg(2, "i2c stat => %s\n", str_i2c_status[status]);
saa_andorb(SAA7134_I2C_ATTR_STATUS,0x0f,status);
}
static inline void i2c_set_attr(struct saa7134_dev *dev, enum i2c_attr attr)
{
i2c_dbg(2, "i2c attr => %s\n", str_i2c_attr[attr]);
saa_andorb(SAA7134_I2C_ATTR_STATUS,0xc0,attr << 6);
}
static inline int i2c_is_error(enum i2c_status status)
{
switch (status) {
case NO_DEVICE:
case NO_ACKN:
case BUS_ERR:
case ARB_LOST:
case SEQ_ERR:
case ST_ERR:
return true;
default:
return false;
}
}
static inline int i2c_is_idle(enum i2c_status status)
{
switch (status) {
case IDLE:
case DONE_STOP:
return true;
default:
return false;
}
}
static inline int i2c_is_busy(enum i2c_status status)
{
switch (status) {
case BUSY:
case TO_SCL:
case TO_ARB:
return true;
default:
return false;
}
}
static int i2c_is_busy_wait(struct saa7134_dev *dev)
{
enum i2c_status status;
int count;
for (count = 0; count < I2C_WAIT_RETRY; count++) {
status = i2c_get_status(dev);
if (!i2c_is_busy(status))
break;
saa_wait(I2C_WAIT_DELAY);
}
if (I2C_WAIT_RETRY == count)
return false;
return true;
}
static int i2c_reset(struct saa7134_dev *dev)
{
enum i2c_status status;
int count;
i2c_dbg(2, "i2c reset\n");
status = i2c_get_status(dev);
if (!i2c_is_error(status))
return true;
i2c_set_status(dev,status);
for (count = 0; count < I2C_WAIT_RETRY; count++) {
status = i2c_get_status(dev);
if (!i2c_is_error(status))
break;
udelay(I2C_WAIT_DELAY);
}
if (I2C_WAIT_RETRY == count)
return false;
if (!i2c_is_idle(status))
return false;
i2c_set_attr(dev,NOP);
return true;
}
static inline int i2c_send_byte(struct saa7134_dev *dev,
enum i2c_attr attr,
unsigned char data)
{
enum i2c_status status;
__u32 dword;
/* have to write both attr + data in one 32bit word */
dword = saa_readl(SAA7134_I2C_ATTR_STATUS >> 2);
dword &= 0x0f;
dword |= (attr << 6);
dword |= ((__u32)data << 8);
dword |= 0x00 << 16; /* 100 kHz */
// dword |= 0x40 << 16; /* 400 kHz */
dword |= 0xf0 << 24;
saa_writel(SAA7134_I2C_ATTR_STATUS >> 2, dword);
i2c_dbg(2, "i2c data => 0x%x\n", data);
if (!i2c_is_busy_wait(dev))
return -EIO;
status = i2c_get_status(dev);
if (i2c_is_error(status))
return -EIO;
return 0;
}
static inline int i2c_recv_byte(struct saa7134_dev *dev)
{
enum i2c_status status;
unsigned char data;
i2c_set_attr(dev,CONTINUE);
if (!i2c_is_busy_wait(dev))
return -EIO;
status = i2c_get_status(dev);
if (i2c_is_error(status))
return -EIO;
data = saa_readb(SAA7134_I2C_DATA);
i2c_dbg(2, "i2c data <= 0x%x\n", data);
return data;
}
static int saa7134_i2c_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg *msgs, int num)
{
struct saa7134_dev *dev = i2c_adap->algo_data;
enum i2c_status status;
unsigned char data;
int addr,rc,i,byte;
status = i2c_get_status(dev);
if (!i2c_is_idle(status))
if (!i2c_reset(dev))
return -EIO;
i2c_dbg(2, "start xfer\n");
i2c_dbg(1, "i2c xfer:");
for (i = 0; i < num; i++) {
if (!(msgs[i].flags & I2C_M_NOSTART) || 0 == i) {
/* send address */
i2c_dbg(2, "send address\n");
addr = msgs[i].addr << 1;
if (msgs[i].flags & I2C_M_RD)
addr |= 1;
if (i > 0 && msgs[i].flags &
I2C_M_RD && msgs[i].addr != 0x40 &&
msgs[i].addr != 0x41 &&
msgs[i].addr != 0x19) {
/* workaround for a saa7134 i2c bug
* needed to talk to the mt352 demux
* thanks to pinnacle for the hint */
int quirk = 0xfe;
i2c_cont(1, " [%02x quirk]", quirk);
i2c_send_byte(dev,START,quirk);
i2c_recv_byte(dev);
}
i2c_cont(1, " < %02x", addr);
rc = i2c_send_byte(dev,START,addr);
if (rc < 0)
goto err;
}
if (msgs[i].flags & I2C_M_RD) {
/* read bytes */
i2c_dbg(2, "read bytes\n");
for (byte = 0; byte < msgs[i].len; byte++) {
i2c_cont(1, " =");
rc = i2c_recv_byte(dev);
if (rc < 0)
goto err;
i2c_cont(1, "%02x", rc);
msgs[i].buf[byte] = rc;
}
/* discard mysterious extra byte when reading
from Samsung S5H1411. i2c bus gets error
if we do not. */
if (0x19 == msgs[i].addr) {
i2c_cont(1, " ?");
rc = i2c_recv_byte(dev);
if (rc < 0)
goto err;
i2c_cont(1, "%02x", rc);
}
} else {
/* write bytes */
i2c_dbg(2, "write bytes\n");
for (byte = 0; byte < msgs[i].len; byte++) {
data = msgs[i].buf[byte];
i2c_cont(1, " %02x", data);
rc = i2c_send_byte(dev,CONTINUE,data);
if (rc < 0)
goto err;
}
}
}
i2c_dbg(2, "xfer done\n");
i2c_cont(1, " >");
i2c_set_attr(dev,STOP);
rc = -EIO;
if (!i2c_is_busy_wait(dev))
goto err;
status = i2c_get_status(dev);
if (i2c_is_error(status))
goto err;
/* ensure that the bus is idle for at least one bit slot */
msleep(1);
i2c_cont(1, "\n");
return num;
err:
if (1 == i2c_debug) {
status = i2c_get_status(dev);
i2c_cont(1, " ERROR: %s\n", str_i2c_status[status]);
}
return rc;
}
/* ----------------------------------------------------------- */
static u32 functionality(struct i2c_adapter *adap)
{
return I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm saa7134_algo = {
.master_xfer = saa7134_i2c_xfer,
.functionality = functionality,
};
static const struct i2c_adapter saa7134_adap_template = {
.owner = THIS_MODULE,
.name = "saa7134",
.algo = &saa7134_algo,
};
static const struct i2c_client saa7134_client_template = {
.name = "saa7134 internal",
};
/* ----------------------------------------------------------- */
/*
* On Medion 7134 reading the SAA7134 chip config EEPROM needs DVB-T
* demod i2c gate closed due to an address clash between this EEPROM
* and the demod one.
*/
static void saa7134_i2c_eeprom_md7134_gate(struct saa7134_dev *dev)
{
u8 subaddr = 0x7, dmdregval;
u8 data[2];
int ret;
struct i2c_msg i2cgatemsg_r[] = { {.addr = 0x08, .flags = 0,
.buf = &subaddr, .len = 1},
{.addr = 0x08,
.flags = I2C_M_RD,
.buf = &dmdregval, .len = 1}
};
struct i2c_msg i2cgatemsg_w[] = { {.addr = 0x08, .flags = 0,
.buf = data, .len = 2} };
ret = i2c_transfer(&dev->i2c_adap, i2cgatemsg_r, 2);
if ((ret == 2) && (dmdregval & 0x2)) {
pr_debug("%s: DVB-T demod i2c gate was left open\n",
dev->name);
data[0] = subaddr;
data[1] = (dmdregval & ~0x2);
if (i2c_transfer(&dev->i2c_adap, i2cgatemsg_w, 1) != 1)
pr_err("%s: EEPROM i2c gate close failure\n",
dev->name);
}
}
static int
saa7134_i2c_eeprom(struct saa7134_dev *dev, unsigned char *eedata, int len)
{
unsigned char buf;
int i,err;
if (dev->board == SAA7134_BOARD_MD7134)
saa7134_i2c_eeprom_md7134_gate(dev);
dev->i2c_client.addr = 0xa0 >> 1;
buf = 0;
if (1 != (err = i2c_master_send(&dev->i2c_client,&buf,1))) {
pr_info("%s: Huh, no eeprom present (err=%d)?\n",
dev->name,err);
return -1;
}
if (len != (err = i2c_master_recv(&dev->i2c_client,eedata,len))) {
pr_warn("%s: i2c eeprom read error (err=%d)\n",
dev->name,err);
return -1;
}
for (i = 0; i < len; i += 16) {
int size = (len - i) > 16 ? 16 : len - i;
pr_info("i2c eeprom %02x: %*ph\n", i, size, &eedata[i]);
}
return 0;
}
static char *i2c_devs[128] = {
[ 0x20 ] = "mpeg encoder (saa6752hs)",
[ 0xa0 >> 1 ] = "eeprom",
[ 0xc0 >> 1 ] = "tuner (analog)",
[ 0x86 >> 1 ] = "tda9887",
[ 0x5a >> 1 ] = "remote control",
};
static void do_i2c_scan(struct i2c_client *c)
{
unsigned char buf;
int i,rc;
for (i = 0; i < ARRAY_SIZE(i2c_devs); i++) {
c->addr = i;
rc = i2c_master_recv(c,&buf,0);
if (rc < 0)
continue;
pr_info("i2c scan: found device @ 0x%x [%s]\n",
i << 1, i2c_devs[i] ? i2c_devs[i] : "???");
}
}
int saa7134_i2c_register(struct saa7134_dev *dev)
{
dev->i2c_adap = saa7134_adap_template;
dev->i2c_adap.dev.parent = &dev->pci->dev;
strscpy(dev->i2c_adap.name, dev->name, sizeof(dev->i2c_adap.name));
dev->i2c_adap.algo_data = dev;
i2c_set_adapdata(&dev->i2c_adap, &dev->v4l2_dev);
i2c_add_adapter(&dev->i2c_adap);
dev->i2c_client = saa7134_client_template;
dev->i2c_client.adapter = &dev->i2c_adap;
saa7134_i2c_eeprom(dev,dev->eedata,sizeof(dev->eedata));
if (i2c_scan)
do_i2c_scan(&dev->i2c_client);
/* Instantiate the IR receiver device, if present */
saa7134_probe_i2c_ir(dev);
return 0;
}
int saa7134_i2c_unregister(struct saa7134_dev *dev)
{
i2c_del_adapter(&dev->i2c_adap);
return 0;
}
| linux-master | drivers/media/pci/saa7134/saa7134-i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* (c) 2004 Gerd Knorr <[email protected]> [SuSE Labs]
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <media/v4l2-common.h>
#include <media/v4l2-event.h>
/* ------------------------------------------------------------------ */
MODULE_AUTHOR("Gerd Knorr <[email protected]> [SuSE Labs]");
MODULE_LICENSE("GPL");
static unsigned int empress_nr[] = {[0 ... (SAA7134_MAXBOARDS - 1)] = UNSET };
module_param_array(empress_nr, int, NULL, 0444);
MODULE_PARM_DESC(empress_nr,"ts device number");
/* ------------------------------------------------------------------ */
static int start_streaming(struct vb2_queue *vq, unsigned int count)
{
struct saa7134_dmaqueue *dmaq = vq->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
u32 leading_null_bytes = 0;
int err;
err = saa7134_ts_start_streaming(vq, count);
if (err)
return err;
/* If more cards start to need this, then this
should probably be added to the card definitions. */
switch (dev->board) {
case SAA7134_BOARD_BEHOLD_M6:
case SAA7134_BOARD_BEHOLD_M63:
case SAA7134_BOARD_BEHOLD_M6_EXTRA:
leading_null_bytes = 1;
break;
}
saa_call_all(dev, core, init, leading_null_bytes);
/* Unmute audio */
saa_writeb(SAA7134_AUDIO_MUTE_CTRL,
saa_readb(SAA7134_AUDIO_MUTE_CTRL) & ~(1 << 6));
dev->empress_started = 1;
return 0;
}
static void stop_streaming(struct vb2_queue *vq)
{
struct saa7134_dmaqueue *dmaq = vq->drv_priv;
struct saa7134_dev *dev = dmaq->dev;
saa7134_ts_stop_streaming(vq);
saa_writeb(SAA7134_SPECIAL_MODE, 0x00);
msleep(20);
saa_writeb(SAA7134_SPECIAL_MODE, 0x01);
msleep(100);
/* Mute audio */
saa_writeb(SAA7134_AUDIO_MUTE_CTRL,
saa_readb(SAA7134_AUDIO_MUTE_CTRL) | (1 << 6));
dev->empress_started = 0;
}
static const struct vb2_ops saa7134_empress_qops = {
.queue_setup = saa7134_ts_queue_setup,
.buf_init = saa7134_ts_buffer_init,
.buf_prepare = saa7134_ts_buffer_prepare,
.buf_queue = saa7134_vb2_buffer_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.start_streaming = start_streaming,
.stop_streaming = stop_streaming,
};
/* ------------------------------------------------------------------ */
static int empress_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
if (f->index != 0)
return -EINVAL;
f->pixelformat = V4L2_PIX_FMT_MPEG;
return 0;
}
static int empress_g_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct saa7134_dev *dev = video_drvdata(file);
struct v4l2_subdev_format fmt = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
struct v4l2_mbus_framefmt *mbus_fmt = &fmt.format;
saa_call_all(dev, pad, get_fmt, NULL, &fmt);
v4l2_fill_pix_format(&f->fmt.pix, mbus_fmt);
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
f->fmt.pix.sizeimage = TS_PACKET_SIZE * dev->ts.nr_packets;
f->fmt.pix.bytesperline = 0;
return 0;
}
static int empress_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct saa7134_dev *dev = video_drvdata(file);
struct v4l2_subdev_format format = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
v4l2_fill_mbus_format(&format.format, &f->fmt.pix, MEDIA_BUS_FMT_FIXED);
saa_call_all(dev, pad, set_fmt, NULL, &format);
v4l2_fill_pix_format(&f->fmt.pix, &format.format);
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
f->fmt.pix.sizeimage = TS_PACKET_SIZE * dev->ts.nr_packets;
f->fmt.pix.bytesperline = 0;
return 0;
}
static int empress_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct saa7134_dev *dev = video_drvdata(file);
struct v4l2_subdev_pad_config pad_cfg;
struct v4l2_subdev_state pad_state = {
.pads = &pad_cfg,
};
struct v4l2_subdev_format format = {
.which = V4L2_SUBDEV_FORMAT_TRY,
};
v4l2_fill_mbus_format(&format.format, &f->fmt.pix, MEDIA_BUS_FMT_FIXED);
saa_call_all(dev, pad, set_fmt, &pad_state, &format);
v4l2_fill_pix_format(&f->fmt.pix, &format.format);
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
f->fmt.pix.sizeimage = TS_PACKET_SIZE * dev->ts.nr_packets;
f->fmt.pix.bytesperline = 0;
return 0;
}
static const struct v4l2_file_operations ts_fops =
{
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.release = vb2_fop_release,
.read = vb2_fop_read,
.poll = vb2_fop_poll,
.mmap = vb2_fop_mmap,
.unlocked_ioctl = video_ioctl2,
};
static const struct v4l2_ioctl_ops ts_ioctl_ops = {
.vidioc_querycap = saa7134_querycap,
.vidioc_enum_fmt_vid_cap = empress_enum_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = empress_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = empress_s_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = empress_g_fmt_vid_cap,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_expbuf = vb2_ioctl_expbuf,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_g_frequency = saa7134_g_frequency,
.vidioc_s_frequency = saa7134_s_frequency,
.vidioc_g_tuner = saa7134_g_tuner,
.vidioc_s_tuner = saa7134_s_tuner,
.vidioc_enum_input = saa7134_enum_input,
.vidioc_g_input = saa7134_g_input,
.vidioc_s_input = saa7134_s_input,
.vidioc_s_std = saa7134_s_std,
.vidioc_g_std = saa7134_g_std,
.vidioc_querystd = saa7134_querystd,
.vidioc_log_status = v4l2_ctrl_log_status,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
/* ----------------------------------------------------------- */
static const struct video_device saa7134_empress_template = {
.name = "saa7134-empress",
.fops = &ts_fops,
.ioctl_ops = &ts_ioctl_ops,
.tvnorms = SAA7134_NORMS,
};
static void empress_signal_update(struct work_struct *work)
{
struct saa7134_dev* dev =
container_of(work, struct saa7134_dev, empress_workqueue);
if (dev->nosignal) {
pr_debug("no video signal\n");
} else {
pr_debug("video signal acquired\n");
}
}
static void empress_signal_change(struct saa7134_dev *dev)
{
schedule_work(&dev->empress_workqueue);
}
static bool empress_ctrl_filter(const struct v4l2_ctrl *ctrl)
{
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
case V4L2_CID_HUE:
case V4L2_CID_CONTRAST:
case V4L2_CID_SATURATION:
case V4L2_CID_AUDIO_MUTE:
case V4L2_CID_AUDIO_VOLUME:
case V4L2_CID_PRIVATE_INVERT:
case V4L2_CID_PRIVATE_AUTOMUTE:
return true;
default:
return false;
}
}
static int empress_init(struct saa7134_dev *dev)
{
struct v4l2_ctrl_handler *hdl = &dev->empress_ctrl_handler;
struct vb2_queue *q;
int err;
pr_debug("%s: %s\n", dev->name, __func__);
dev->empress_dev = video_device_alloc();
if (NULL == dev->empress_dev)
return -ENOMEM;
*(dev->empress_dev) = saa7134_empress_template;
dev->empress_dev->v4l2_dev = &dev->v4l2_dev;
dev->empress_dev->release = video_device_release;
dev->empress_dev->lock = &dev->lock;
snprintf(dev->empress_dev->name, sizeof(dev->empress_dev->name),
"%s empress (%s)", dev->name,
saa7134_boards[dev->board].name);
v4l2_ctrl_handler_init(hdl, 21);
v4l2_ctrl_add_handler(hdl, &dev->ctrl_handler, empress_ctrl_filter, false);
if (dev->empress_sd)
v4l2_ctrl_add_handler(hdl, dev->empress_sd->ctrl_handler, NULL, true);
if (hdl->error) {
video_device_release(dev->empress_dev);
return hdl->error;
}
dev->empress_dev->ctrl_handler = hdl;
INIT_WORK(&dev->empress_workqueue, empress_signal_update);
q = &dev->empress_vbq;
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
/*
* Do not add VB2_USERPTR: the saa7134 DMA engine cannot handle
* transfers that do not start at the beginning of a page. A USERPTR
* can start anywhere in a page, so USERPTR support is a no-go.
*/
q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
q->drv_priv = &dev->ts_q;
q->ops = &saa7134_empress_qops;
q->gfp_flags = GFP_DMA32;
q->mem_ops = &vb2_dma_sg_memops;
q->buf_struct_size = sizeof(struct saa7134_buf);
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &dev->lock;
q->dev = &dev->pci->dev;
err = vb2_queue_init(q);
if (err) {
video_device_release(dev->empress_dev);
dev->empress_dev = NULL;
return err;
}
dev->empress_dev->queue = q;
dev->empress_dev->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
V4L2_CAP_VIDEO_CAPTURE;
if (dev->tuner_type != TUNER_ABSENT && dev->tuner_type != UNSET)
dev->empress_dev->device_caps |= V4L2_CAP_TUNER;
video_set_drvdata(dev->empress_dev, dev);
err = video_register_device(dev->empress_dev,VFL_TYPE_VIDEO,
empress_nr[dev->nr]);
if (err < 0) {
pr_info("%s: can't register video device\n",
dev->name);
video_device_release(dev->empress_dev);
dev->empress_dev = NULL;
return err;
}
pr_info("%s: registered device %s [mpeg]\n",
dev->name, video_device_node_name(dev->empress_dev));
empress_signal_update(&dev->empress_workqueue);
return 0;
}
static int empress_fini(struct saa7134_dev *dev)
{
pr_debug("%s: %s\n", dev->name, __func__);
if (NULL == dev->empress_dev)
return 0;
flush_work(&dev->empress_workqueue);
vb2_video_unregister_device(dev->empress_dev);
v4l2_ctrl_handler_free(&dev->empress_ctrl_handler);
dev->empress_dev = NULL;
return 0;
}
static struct saa7134_mpeg_ops empress_ops = {
.type = SAA7134_MPEG_EMPRESS,
.init = empress_init,
.fini = empress_fini,
.signal_change = empress_signal_change,
};
static int __init empress_register(void)
{
return saa7134_ts_register(&empress_ops);
}
static void __exit empress_unregister(void)
{
saa7134_ts_unregister(&empress_ops);
}
module_init(empress_register);
module_exit(empress_unregister);
| linux-master | drivers/media/pci/saa7134/saa7134-empress.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* handle saa7134 IR remotes via linux kernel input layer.
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#define MODULE_NAME "saa7134"
static unsigned int disable_ir;
module_param(disable_ir, int, 0444);
MODULE_PARM_DESC(disable_ir,"disable infrared remote support");
static unsigned int ir_debug;
module_param(ir_debug, int, 0644);
MODULE_PARM_DESC(ir_debug,"enable debug messages [IR]");
static int pinnacle_remote;
module_param(pinnacle_remote, int, 0644); /* Choose Pinnacle PCTV remote */
MODULE_PARM_DESC(pinnacle_remote, "Specify Pinnacle PCTV remote: 0=coloured, 1=grey (defaults to 0)");
#define input_dbg(fmt, arg...) do { \
if (ir_debug) \
printk(KERN_DEBUG pr_fmt("input: " fmt), ## arg); \
} while (0)
#define ir_dbg(ir, fmt, arg...) do { \
if (ir_debug) \
printk(KERN_DEBUG pr_fmt("ir %s: " fmt), ir->rc->device_name, \
## arg); \
} while (0)
/* Helper function for raw decoding at GPIO16 or GPIO18 */
static int saa7134_raw_decode_irq(struct saa7134_dev *dev);
/* -------------------- GPIO generic keycode builder -------------------- */
static int build_key(struct saa7134_dev *dev)
{
struct saa7134_card_ir *ir = dev->remote;
u32 gpio, data;
/* here comes the additional handshake steps for some cards */
switch (dev->board) {
case SAA7134_BOARD_GOTVIEW_7135:
saa_setb(SAA7134_GPIO_GPSTATUS1, 0x80);
saa_clearb(SAA7134_GPIO_GPSTATUS1, 0x80);
break;
}
/* rising SAA7134_GPIO_GPRESCAN reads the status */
saa_clearb(SAA7134_GPIO_GPMODE3,SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3,SAA7134_GPIO_GPRESCAN);
gpio = saa_readl(SAA7134_GPIO_GPSTATUS0 >> 2);
if (ir->polling) {
if (ir->last_gpio == gpio)
return 0;
ir->last_gpio = gpio;
}
data = ir_extract_bits(gpio, ir->mask_keycode);
input_dbg("build_key gpio=0x%x mask=0x%x data=%d\n",
gpio, ir->mask_keycode, data);
switch (dev->board) {
case SAA7134_BOARD_KWORLD_PLUS_TV_ANALOG:
if (data == ir->mask_keycode)
rc_keyup(ir->dev);
else
rc_keydown_notimeout(ir->dev, RC_PROTO_UNKNOWN, data,
0);
return 0;
}
if (ir->polling) {
if ((ir->mask_keydown && (0 != (gpio & ir->mask_keydown))) ||
(ir->mask_keyup && (0 == (gpio & ir->mask_keyup)))) {
rc_keydown_notimeout(ir->dev, RC_PROTO_UNKNOWN, data,
0);
} else {
rc_keyup(ir->dev);
}
}
else { /* IRQ driven mode - handle key press and release in one go */
if ((ir->mask_keydown && (0 != (gpio & ir->mask_keydown))) ||
(ir->mask_keyup && (0 == (gpio & ir->mask_keyup)))) {
rc_keydown_notimeout(ir->dev, RC_PROTO_UNKNOWN, data,
0);
rc_keyup(ir->dev);
}
}
return 0;
}
/* --------------------- Chip specific I2C key builders ----------------- */
static int get_key_flydvb_trio(struct IR_i2c *ir, enum rc_proto *protocol,
u32 *scancode, u8 *toggle)
{
int gpio, rc;
int attempt = 0;
unsigned char b;
/* We need this to access GPI Used by the saa_readl macro. */
struct saa7134_dev *dev = ir->c->adapter->algo_data;
if (dev == NULL) {
ir_dbg(ir, "get_key_flydvb_trio: ir->c->adapter->algo_data is NULL!\n");
return -EIO;
}
/* rising SAA7134_GPIGPRESCAN reads the status */
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
gpio = saa_readl(SAA7134_GPIO_GPSTATUS0 >> 2);
if (0x40000 & ~gpio)
return 0; /* No button press */
/* poll IR chip */
/* weak up the IR chip */
b = 0;
while (1 != i2c_master_send(ir->c, &b, 1)) {
if ((attempt++) < 10) {
/*
* wait a bit for next attempt -
* I don't know how make it better
*/
msleep(10);
continue;
}
ir_dbg(ir, "send wake up byte to pic16C505 (IR chip)failed %dx\n",
attempt);
return -EIO;
}
rc = i2c_master_recv(ir->c, &b, 1);
if (rc != 1) {
ir_dbg(ir, "read error\n");
if (rc < 0)
return rc;
return -EIO;
}
*protocol = RC_PROTO_UNKNOWN;
*scancode = b;
*toggle = 0;
return 1;
}
static int get_key_msi_tvanywhere_plus(struct IR_i2c *ir,
enum rc_proto *protocol,
u32 *scancode, u8 *toggle)
{
unsigned char b;
int gpio, rc;
/* <dev> is needed to access GPIO. Used by the saa_readl macro. */
struct saa7134_dev *dev = ir->c->adapter->algo_data;
if (dev == NULL) {
ir_dbg(ir, "get_key_msi_tvanywhere_plus: ir->c->adapter->algo_data is NULL!\n");
return -EIO;
}
/* rising SAA7134_GPIO_GPRESCAN reads the status */
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
gpio = saa_readl(SAA7134_GPIO_GPSTATUS0 >> 2);
/* GPIO&0x40 is pulsed low when a button is pressed. Don't do
I2C receive if gpio&0x40 is not low. */
if (gpio & 0x40)
return 0; /* No button press */
/* GPIO says there is a button press. Get it. */
rc = i2c_master_recv(ir->c, &b, 1);
if (rc != 1) {
ir_dbg(ir, "read error\n");
if (rc < 0)
return rc;
return -EIO;
}
/* No button press */
if (b == 0xff)
return 0;
/* Button pressed */
input_dbg("get_key_msi_tvanywhere_plus: Key = 0x%02X\n", b);
*protocol = RC_PROTO_UNKNOWN;
*scancode = b;
*toggle = 0;
return 1;
}
/* copied and modified from get_key_msi_tvanywhere_plus() */
static int get_key_kworld_pc150u(struct IR_i2c *ir, enum rc_proto *protocol,
u32 *scancode, u8 *toggle)
{
unsigned char b;
unsigned int gpio;
int rc;
/* <dev> is needed to access GPIO. Used by the saa_readl macro. */
struct saa7134_dev *dev = ir->c->adapter->algo_data;
if (dev == NULL) {
ir_dbg(ir, "get_key_kworld_pc150u: ir->c->adapter->algo_data is NULL!\n");
return -EIO;
}
/* rising SAA7134_GPIO_GPRESCAN reads the status */
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
gpio = saa_readl(SAA7134_GPIO_GPSTATUS0 >> 2);
/* GPIO&0x100 is pulsed low when a button is pressed. Don't do
I2C receive if gpio&0x100 is not low. */
if (gpio & 0x100)
return 0; /* No button press */
/* GPIO says there is a button press. Get it. */
rc = i2c_master_recv(ir->c, &b, 1);
if (rc != 1) {
ir_dbg(ir, "read error\n");
if (rc < 0)
return rc;
return -EIO;
}
/* No button press */
if (b == 0xff)
return 0;
/* Button pressed */
input_dbg("get_key_kworld_pc150u: Key = 0x%02X\n", b);
*protocol = RC_PROTO_UNKNOWN;
*scancode = b;
*toggle = 0;
return 1;
}
static int get_key_purpletv(struct IR_i2c *ir, enum rc_proto *protocol,
u32 *scancode, u8 *toggle)
{
int rc;
unsigned char b;
/* poll IR chip */
rc = i2c_master_recv(ir->c, &b, 1);
if (rc != 1) {
ir_dbg(ir, "read error\n");
if (rc < 0)
return rc;
return -EIO;
}
/* no button press */
if (b==0)
return 0;
/* repeating */
if (b & 0x80)
return 1;
*protocol = RC_PROTO_UNKNOWN;
*scancode = b;
*toggle = 0;
return 1;
}
static int get_key_beholdm6xx(struct IR_i2c *ir, enum rc_proto *protocol,
u32 *scancode, u8 *toggle)
{
int rc;
unsigned char data[12];
u32 gpio;
struct saa7134_dev *dev = ir->c->adapter->algo_data;
/* rising SAA7134_GPIO_GPRESCAN reads the status */
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
gpio = saa_readl(SAA7134_GPIO_GPSTATUS0 >> 2);
if (0x400000 & ~gpio)
return 0; /* No button press */
ir->c->addr = 0x5a >> 1;
rc = i2c_master_recv(ir->c, data, 12);
if (rc != 12) {
ir_dbg(ir, "read error\n");
if (rc < 0)
return rc;
return -EIO;
}
if (data[9] != (unsigned char)(~data[8]))
return 0;
*protocol = RC_PROTO_NECX;
*scancode = RC_SCANCODE_NECX(data[11] << 8 | data[10], data[9]);
*toggle = 0;
return 1;
}
/* Common (grey or coloured) pinnacle PCTV remote handling
*
*/
static int get_key_pinnacle(struct IR_i2c *ir, enum rc_proto *protocol,
u32 *scancode, u8 *toggle, int parity_offset,
int marker, int code_modulo)
{
int rc;
unsigned char b[4];
unsigned int start = 0,parity = 0,code = 0;
/* poll IR chip */
rc = i2c_master_recv(ir->c, b, 4);
if (rc != 4) {
ir_dbg(ir, "read error\n");
if (rc < 0)
return rc;
return -EIO;
}
for (start = 0; start < ARRAY_SIZE(b); start++) {
if (b[start] == marker) {
code=b[(start+parity_offset + 1) % 4];
parity=b[(start+parity_offset) % 4];
}
}
/* Empty Request */
if (parity == 0)
return 0;
/* Repeating... */
if (ir->old == parity)
return 0;
ir->old = parity;
/* drop special codes when a key is held down a long time for the grey controller
In this case, the second bit of the code is asserted */
if (marker == 0xfe && (code & 0x40))
return 0;
code %= code_modulo;
*protocol = RC_PROTO_UNKNOWN;
*scancode = code;
*toggle = 0;
ir_dbg(ir, "Pinnacle PCTV key %02x\n", code);
return 1;
}
/* The grey pinnacle PCTV remote
*
* There are one issue with this remote:
* - I2c packet does not change when the same key is pressed quickly. The workaround
* is to hold down each key for about half a second, so that another code is generated
* in the i2c packet, and the function can distinguish key presses.
*
* Sylvain Pasche <[email protected]>
*/
static int get_key_pinnacle_grey(struct IR_i2c *ir, enum rc_proto *protocol,
u32 *scancode, u8 *toggle)
{
return get_key_pinnacle(ir, protocol, scancode, toggle, 1, 0xfe, 0xff);
}
/* The new pinnacle PCTV remote (with the colored buttons)
*
* Ricardo Cerqueira <[email protected]>
*/
static int get_key_pinnacle_color(struct IR_i2c *ir, enum rc_proto *protocol,
u32 *scancode, u8 *toggle)
{
/* code_modulo parameter (0x88) is used to reduce code value to fit inside IR_KEYTAB_SIZE
*
* this is the only value that results in 42 unique
* codes < 128
*/
return get_key_pinnacle(ir, protocol, scancode, toggle, 2, 0x80, 0x88);
}
void saa7134_input_irq(struct saa7134_dev *dev)
{
struct saa7134_card_ir *ir;
if (!dev || !dev->remote)
return;
ir = dev->remote;
if (!ir->running)
return;
if (!ir->polling && !ir->raw_decode) {
build_key(dev);
} else if (ir->raw_decode) {
saa7134_raw_decode_irq(dev);
}
}
static void saa7134_input_timer(struct timer_list *t)
{
struct saa7134_card_ir *ir = from_timer(ir, t, timer);
struct saa7134_dev *dev = ir->dev->priv;
build_key(dev);
mod_timer(&ir->timer, jiffies + msecs_to_jiffies(ir->polling));
}
int saa7134_ir_open(struct rc_dev *rc)
{
struct saa7134_dev *dev = rc->priv;
struct saa7134_card_ir *ir = dev->remote;
/* Moved here from saa7134_input_init1() because the latter
* is not called on device resume */
switch (dev->board) {
case SAA7134_BOARD_MD2819:
case SAA7134_BOARD_KWORLD_VSTREAM_XPERT:
case SAA7134_BOARD_AVERMEDIA_305:
case SAA7134_BOARD_AVERMEDIA_307:
case SAA7134_BOARD_AVERMEDIA_505:
case SAA7134_BOARD_AVERMEDIA_STUDIO_305:
case SAA7134_BOARD_AVERMEDIA_STUDIO_505:
case SAA7134_BOARD_AVERMEDIA_STUDIO_307:
case SAA7134_BOARD_AVERMEDIA_STUDIO_507:
case SAA7134_BOARD_AVERMEDIA_STUDIO_507UA:
case SAA7134_BOARD_AVERMEDIA_GO_007_FM:
case SAA7134_BOARD_AVERMEDIA_M102:
case SAA7134_BOARD_AVERMEDIA_GO_007_FM_PLUS:
/* Without this we won't receive key up events */
saa_setb(SAA7134_GPIO_GPMODE0, 0x4);
saa_setb(SAA7134_GPIO_GPSTATUS0, 0x4);
break;
case SAA7134_BOARD_AVERMEDIA_777:
case SAA7134_BOARD_AVERMEDIA_A16AR:
/* Without this we won't receive key up events */
saa_setb(SAA7134_GPIO_GPMODE1, 0x1);
saa_setb(SAA7134_GPIO_GPSTATUS1, 0x1);
break;
case SAA7134_BOARD_AVERMEDIA_A16D:
/* Without this we won't receive key up events */
saa_setb(SAA7134_GPIO_GPMODE1, 0x1);
saa_setb(SAA7134_GPIO_GPSTATUS1, 0x1);
break;
case SAA7134_BOARD_GOTVIEW_7135:
saa_setb(SAA7134_GPIO_GPMODE1, 0x80);
break;
}
ir->running = true;
if (ir->polling) {
timer_setup(&ir->timer, saa7134_input_timer, 0);
ir->timer.expires = jiffies + HZ;
add_timer(&ir->timer);
}
return 0;
}
void saa7134_ir_close(struct rc_dev *rc)
{
struct saa7134_dev *dev = rc->priv;
struct saa7134_card_ir *ir = dev->remote;
if (ir->polling)
del_timer_sync(&ir->timer);
ir->running = false;
}
int saa7134_input_init1(struct saa7134_dev *dev)
{
struct saa7134_card_ir *ir;
struct rc_dev *rc;
char *ir_codes = NULL;
u32 mask_keycode = 0;
u32 mask_keydown = 0;
u32 mask_keyup = 0;
unsigned polling = 0;
bool raw_decode = false;
int err;
if (dev->has_remote != SAA7134_REMOTE_GPIO)
return -ENODEV;
if (disable_ir)
return -ENODEV;
/* detect & configure */
switch (dev->board) {
case SAA7134_BOARD_FLYVIDEO2000:
case SAA7134_BOARD_FLYVIDEO3000:
case SAA7134_BOARD_FLYTVPLATINUM_FM:
case SAA7134_BOARD_FLYTVPLATINUM_MINI2:
case SAA7134_BOARD_ROVERMEDIA_LINK_PRO_FM:
ir_codes = RC_MAP_FLYVIDEO;
mask_keycode = 0xEC00000;
mask_keydown = 0x0040000;
break;
case SAA7134_BOARD_CINERGY400:
case SAA7134_BOARD_CINERGY600:
case SAA7134_BOARD_CINERGY600_MK3:
ir_codes = RC_MAP_CINERGY;
mask_keycode = 0x00003f;
mask_keyup = 0x040000;
break;
case SAA7134_BOARD_ECS_TVP3XP:
case SAA7134_BOARD_ECS_TVP3XP_4CB5:
ir_codes = RC_MAP_EZTV;
mask_keycode = 0x00017c;
mask_keyup = 0x000002;
polling = 50; // ms
break;
case SAA7134_BOARD_KWORLD_XPERT:
case SAA7134_BOARD_AVACSSMARTTV:
ir_codes = RC_MAP_PIXELVIEW;
mask_keycode = 0x00001F;
mask_keyup = 0x000020;
polling = 50; // ms
break;
case SAA7134_BOARD_MD2819:
case SAA7134_BOARD_KWORLD_VSTREAM_XPERT:
case SAA7134_BOARD_AVERMEDIA_305:
case SAA7134_BOARD_AVERMEDIA_307:
case SAA7134_BOARD_AVERMEDIA_505:
case SAA7134_BOARD_AVERMEDIA_STUDIO_305:
case SAA7134_BOARD_AVERMEDIA_STUDIO_505:
case SAA7134_BOARD_AVERMEDIA_STUDIO_307:
case SAA7134_BOARD_AVERMEDIA_STUDIO_507:
case SAA7134_BOARD_AVERMEDIA_STUDIO_507UA:
case SAA7134_BOARD_AVERMEDIA_GO_007_FM:
case SAA7134_BOARD_AVERMEDIA_M102:
case SAA7134_BOARD_AVERMEDIA_GO_007_FM_PLUS:
ir_codes = RC_MAP_AVERMEDIA;
mask_keycode = 0x0007C8;
mask_keydown = 0x000010;
polling = 50; // ms
/* GPIO stuff moved to saa7134_ir_open() */
break;
case SAA7134_BOARD_AVERMEDIA_M135A:
ir_codes = RC_MAP_AVERMEDIA_M135A;
mask_keydown = 0x0040000; /* Enable GPIO18 line on both edges */
mask_keyup = 0x0040000;
mask_keycode = 0xffff;
raw_decode = true;
break;
case SAA7134_BOARD_AVERMEDIA_M733A:
ir_codes = RC_MAP_AVERMEDIA_M733A_RM_K6;
mask_keydown = 0x0040000;
mask_keyup = 0x0040000;
mask_keycode = 0xffff;
raw_decode = true;
break;
case SAA7134_BOARD_AVERMEDIA_777:
case SAA7134_BOARD_AVERMEDIA_A16AR:
ir_codes = RC_MAP_AVERMEDIA;
mask_keycode = 0x02F200;
mask_keydown = 0x000400;
polling = 50; // ms
/* GPIO stuff moved to saa7134_ir_open() */
break;
case SAA7134_BOARD_AVERMEDIA_A16D:
ir_codes = RC_MAP_AVERMEDIA_A16D;
mask_keycode = 0x02F200;
mask_keydown = 0x000400;
polling = 50; /* ms */
/* GPIO stuff moved to saa7134_ir_open() */
break;
case SAA7134_BOARD_KWORLD_TERMINATOR:
ir_codes = RC_MAP_PIXELVIEW;
mask_keycode = 0x00001f;
mask_keyup = 0x000060;
polling = 50; // ms
break;
case SAA7134_BOARD_MANLI_MTV001:
case SAA7134_BOARD_MANLI_MTV002:
ir_codes = RC_MAP_MANLI;
mask_keycode = 0x001f00;
mask_keyup = 0x004000;
polling = 50; /* ms */
break;
case SAA7134_BOARD_BEHOLD_409FM:
case SAA7134_BOARD_BEHOLD_401:
case SAA7134_BOARD_BEHOLD_403:
case SAA7134_BOARD_BEHOLD_403FM:
case SAA7134_BOARD_BEHOLD_405:
case SAA7134_BOARD_BEHOLD_405FM:
case SAA7134_BOARD_BEHOLD_407:
case SAA7134_BOARD_BEHOLD_407FM:
case SAA7134_BOARD_BEHOLD_409:
case SAA7134_BOARD_BEHOLD_505FM:
case SAA7134_BOARD_BEHOLD_505RDS_MK5:
case SAA7134_BOARD_BEHOLD_505RDS_MK3:
case SAA7134_BOARD_BEHOLD_507_9FM:
case SAA7134_BOARD_BEHOLD_507RDS_MK3:
case SAA7134_BOARD_BEHOLD_507RDS_MK5:
ir_codes = RC_MAP_MANLI;
mask_keycode = 0x003f00;
mask_keyup = 0x004000;
polling = 50; /* ms */
break;
case SAA7134_BOARD_BEHOLD_COLUMBUS_TVFM:
ir_codes = RC_MAP_BEHOLD_COLUMBUS;
mask_keycode = 0x003f00;
mask_keyup = 0x004000;
polling = 50; // ms
break;
case SAA7134_BOARD_SEDNA_PC_TV_CARDBUS:
ir_codes = RC_MAP_PCTV_SEDNA;
mask_keycode = 0x001f00;
mask_keyup = 0x004000;
polling = 50; // ms
break;
case SAA7134_BOARD_GOTVIEW_7135:
ir_codes = RC_MAP_GOTVIEW7135;
mask_keycode = 0x0003CC;
mask_keydown = 0x000010;
polling = 5; /* ms */
/* GPIO stuff moved to saa7134_ir_open() */
break;
case SAA7134_BOARD_VIDEOMATE_TV_PVR:
case SAA7134_BOARD_VIDEOMATE_GOLD_PLUS:
case SAA7134_BOARD_VIDEOMATE_TV_GOLD_PLUSII:
ir_codes = RC_MAP_VIDEOMATE_TV_PVR;
mask_keycode = 0x00003F;
mask_keyup = 0x400000;
polling = 50; // ms
break;
case SAA7134_BOARD_PROTEUS_2309:
ir_codes = RC_MAP_PROTEUS_2309;
mask_keycode = 0x00007F;
mask_keyup = 0x000080;
polling = 50; // ms
break;
case SAA7134_BOARD_VIDEOMATE_DVBT_300:
case SAA7134_BOARD_VIDEOMATE_DVBT_200:
ir_codes = RC_MAP_VIDEOMATE_TV_PVR;
mask_keycode = 0x003F00;
mask_keyup = 0x040000;
break;
case SAA7134_BOARD_FLYDVBS_LR300:
case SAA7134_BOARD_FLYDVBT_LR301:
case SAA7134_BOARD_FLYDVBTDUO:
ir_codes = RC_MAP_FLYDVB;
mask_keycode = 0x0001F00;
mask_keydown = 0x0040000;
break;
case SAA7134_BOARD_ASUSTeK_P7131_DUAL:
case SAA7134_BOARD_ASUSTeK_P7131_HYBRID_LNA:
case SAA7134_BOARD_ASUSTeK_P7131_ANALOG:
ir_codes = RC_MAP_ASUS_PC39;
mask_keydown = 0x0040000; /* Enable GPIO18 line on both edges */
mask_keyup = 0x0040000;
mask_keycode = 0xffff;
raw_decode = true;
break;
case SAA7134_BOARD_ASUSTeK_PS3_100:
ir_codes = RC_MAP_ASUS_PS3_100;
mask_keydown = 0x0040000;
mask_keyup = 0x0040000;
mask_keycode = 0xffff;
raw_decode = true;
break;
case SAA7134_BOARD_ENCORE_ENLTV:
case SAA7134_BOARD_ENCORE_ENLTV_FM:
ir_codes = RC_MAP_ENCORE_ENLTV;
mask_keycode = 0x00007f;
mask_keyup = 0x040000;
polling = 50; // ms
break;
case SAA7134_BOARD_ENCORE_ENLTV_FM53:
case SAA7134_BOARD_ENCORE_ENLTV_FM3:
ir_codes = RC_MAP_ENCORE_ENLTV_FM53;
mask_keydown = 0x0040000; /* Enable GPIO18 line on both edges */
mask_keyup = 0x0040000;
mask_keycode = 0xffff;
raw_decode = true;
break;
case SAA7134_BOARD_10MOONSTVMASTER3:
ir_codes = RC_MAP_ENCORE_ENLTV;
mask_keycode = 0x5f80000;
mask_keyup = 0x8000000;
polling = 50; //ms
break;
case SAA7134_BOARD_GENIUS_TVGO_A11MCE:
ir_codes = RC_MAP_GENIUS_TVGO_A11MCE;
mask_keycode = 0xff;
mask_keydown = 0xf00000;
polling = 50; /* ms */
break;
case SAA7134_BOARD_REAL_ANGEL_220:
ir_codes = RC_MAP_REAL_AUDIO_220_32_KEYS;
mask_keycode = 0x3f00;
mask_keyup = 0x4000;
polling = 50; /* ms */
break;
case SAA7134_BOARD_KWORLD_PLUS_TV_ANALOG:
ir_codes = RC_MAP_KWORLD_PLUS_TV_ANALOG;
mask_keycode = 0x7f;
polling = 40; /* ms */
break;
case SAA7134_BOARD_VIDEOMATE_S350:
ir_codes = RC_MAP_VIDEOMATE_S350;
mask_keycode = 0x003f00;
mask_keydown = 0x040000;
break;
case SAA7134_BOARD_LEADTEK_WINFAST_DTV1000S:
ir_codes = RC_MAP_WINFAST;
mask_keycode = 0x5f00;
mask_keyup = 0x020000;
polling = 50; /* ms */
break;
case SAA7134_BOARD_VIDEOMATE_M1F:
ir_codes = RC_MAP_VIDEOMATE_K100;
mask_keycode = 0x0ff00;
mask_keyup = 0x040000;
break;
case SAA7134_BOARD_HAUPPAUGE_HVR1150:
case SAA7134_BOARD_HAUPPAUGE_HVR1120:
ir_codes = RC_MAP_HAUPPAUGE;
mask_keydown = 0x0040000; /* Enable GPIO18 line on both edges */
mask_keyup = 0x0040000;
mask_keycode = 0xffff;
raw_decode = true;
break;
case SAA7134_BOARD_LEADTEK_WINFAST_TV2100_FM:
ir_codes = RC_MAP_LEADTEK_Y04G0051;
mask_keydown = 0x0040000; /* Enable GPIO18 line on both edges */
mask_keyup = 0x0040000;
mask_keycode = 0xffff;
raw_decode = true;
break;
}
if (NULL == ir_codes) {
pr_err("Oops: IR config error [card=%d]\n", dev->board);
return -ENODEV;
}
ir = kzalloc(sizeof(*ir), GFP_KERNEL);
rc = rc_allocate_device(RC_DRIVER_SCANCODE);
if (!ir || !rc) {
err = -ENOMEM;
goto err_out_free;
}
ir->dev = rc;
dev->remote = ir;
/* init hardware-specific stuff */
ir->mask_keycode = mask_keycode;
ir->mask_keydown = mask_keydown;
ir->mask_keyup = mask_keyup;
ir->polling = polling;
ir->raw_decode = raw_decode;
/* init input device */
snprintf(ir->phys, sizeof(ir->phys), "pci-%s/ir0",
pci_name(dev->pci));
rc->priv = dev;
rc->open = saa7134_ir_open;
rc->close = saa7134_ir_close;
if (raw_decode) {
rc->driver_type = RC_DRIVER_IR_RAW;
rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
}
rc->device_name = saa7134_boards[dev->board].name;
rc->input_phys = ir->phys;
rc->input_id.bustype = BUS_PCI;
rc->input_id.version = 1;
if (dev->pci->subsystem_vendor) {
rc->input_id.vendor = dev->pci->subsystem_vendor;
rc->input_id.product = dev->pci->subsystem_device;
} else {
rc->input_id.vendor = dev->pci->vendor;
rc->input_id.product = dev->pci->device;
}
rc->dev.parent = &dev->pci->dev;
rc->map_name = ir_codes;
rc->driver_name = MODULE_NAME;
rc->min_timeout = 1;
rc->timeout = IR_DEFAULT_TIMEOUT;
rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
err = rc_register_device(rc);
if (err)
goto err_out_free;
return 0;
err_out_free:
rc_free_device(rc);
dev->remote = NULL;
kfree(ir);
return err;
}
void saa7134_input_fini(struct saa7134_dev *dev)
{
if (NULL == dev->remote)
return;
rc_unregister_device(dev->remote->dev);
kfree(dev->remote);
dev->remote = NULL;
}
void saa7134_probe_i2c_ir(struct saa7134_dev *dev)
{
struct i2c_board_info info;
struct i2c_msg msg_msi = {
.addr = 0x50,
.flags = I2C_M_RD,
.len = 0,
.buf = NULL,
};
int rc;
if (disable_ir) {
input_dbg("IR has been disabled, not probing for i2c remote\n");
return;
}
memset(&info, 0, sizeof(struct i2c_board_info));
memset(&dev->init_data, 0, sizeof(dev->init_data));
strscpy(info.type, "ir_video", I2C_NAME_SIZE);
switch (dev->board) {
case SAA7134_BOARD_PINNACLE_PCTV_110i:
case SAA7134_BOARD_PINNACLE_PCTV_310i:
dev->init_data.name = "Pinnacle PCTV";
if (pinnacle_remote == 0) {
dev->init_data.get_key = get_key_pinnacle_color;
dev->init_data.ir_codes = RC_MAP_PINNACLE_COLOR;
info.addr = 0x47;
} else {
dev->init_data.get_key = get_key_pinnacle_grey;
dev->init_data.ir_codes = RC_MAP_PINNACLE_GREY;
info.addr = 0x47;
}
break;
case SAA7134_BOARD_UPMOST_PURPLE_TV:
dev->init_data.name = "Purple TV";
dev->init_data.get_key = get_key_purpletv;
dev->init_data.ir_codes = RC_MAP_PURPLETV;
info.addr = 0x7a;
break;
case SAA7134_BOARD_MSI_TVATANYWHERE_PLUS:
dev->init_data.name = "MSI TV@nywhere Plus";
dev->init_data.get_key = get_key_msi_tvanywhere_plus;
dev->init_data.ir_codes = RC_MAP_MSI_TVANYWHERE_PLUS;
/*
* MSI TV@nyware Plus requires more frequent polling
* otherwise it will miss some keypresses
*/
dev->init_data.polling_interval = 50;
info.addr = 0x30;
/* MSI TV@nywhere Plus controller doesn't seem to
respond to probes unless we read something from
an existing device. Weird...
REVISIT: might no longer be needed */
rc = i2c_transfer(&dev->i2c_adap, &msg_msi, 1);
input_dbg("probe 0x%02x @ %s: %s\n",
msg_msi.addr, dev->i2c_adap.name,
(1 == rc) ? "yes" : "no");
break;
case SAA7134_BOARD_SNAZIO_TVPVR_PRO:
dev->init_data.name = "SnaZio* TVPVR PRO";
dev->init_data.get_key = get_key_msi_tvanywhere_plus;
dev->init_data.ir_codes = RC_MAP_MSI_TVANYWHERE_PLUS;
/*
* MSI TV@nyware Plus requires more frequent polling
* otherwise it will miss some keypresses
*/
dev->init_data.polling_interval = 50;
info.addr = 0x30;
/*
* MSI TV@nywhere Plus controller doesn't seem to
* respond to probes unless we read something from
* an existing device. Weird...
* REVISIT: might no longer be needed
*/
rc = i2c_transfer(&dev->i2c_adap, &msg_msi, 1);
input_dbg("probe 0x%02x @ %s: %s\n",
msg_msi.addr, dev->i2c_adap.name,
(rc == 1) ? "yes" : "no");
break;
case SAA7134_BOARD_KWORLD_PC150U:
/* copied and modified from MSI TV@nywhere Plus */
dev->init_data.name = "Kworld PC150-U";
dev->init_data.get_key = get_key_kworld_pc150u;
dev->init_data.ir_codes = RC_MAP_KWORLD_PC150U;
info.addr = 0x30;
/* MSI TV@nywhere Plus controller doesn't seem to
respond to probes unless we read something from
an existing device. Weird...
REVISIT: might no longer be needed */
rc = i2c_transfer(&dev->i2c_adap, &msg_msi, 1);
input_dbg("probe 0x%02x @ %s: %s\n",
msg_msi.addr, dev->i2c_adap.name,
(1 == rc) ? "yes" : "no");
break;
case SAA7134_BOARD_HAUPPAUGE_HVR1110:
dev->init_data.name = saa7134_boards[dev->board].name;
dev->init_data.ir_codes = RC_MAP_HAUPPAUGE;
dev->init_data.type = RC_PROTO_BIT_RC5 |
RC_PROTO_BIT_RC6_MCE | RC_PROTO_BIT_RC6_6A_32;
dev->init_data.internal_get_key_func = IR_KBD_GET_KEY_HAUP_XVR;
info.addr = 0x71;
break;
case SAA7134_BOARD_BEHOLD_607FM_MK3:
case SAA7134_BOARD_BEHOLD_607FM_MK5:
case SAA7134_BOARD_BEHOLD_609FM_MK3:
case SAA7134_BOARD_BEHOLD_609FM_MK5:
case SAA7134_BOARD_BEHOLD_607RDS_MK3:
case SAA7134_BOARD_BEHOLD_607RDS_MK5:
case SAA7134_BOARD_BEHOLD_609RDS_MK3:
case SAA7134_BOARD_BEHOLD_609RDS_MK5:
case SAA7134_BOARD_BEHOLD_M6:
case SAA7134_BOARD_BEHOLD_M63:
case SAA7134_BOARD_BEHOLD_M6_EXTRA:
case SAA7134_BOARD_BEHOLD_H6:
case SAA7134_BOARD_BEHOLD_X7:
case SAA7134_BOARD_BEHOLD_H7:
case SAA7134_BOARD_BEHOLD_A7:
dev->init_data.name = "BeholdTV";
dev->init_data.get_key = get_key_beholdm6xx;
dev->init_data.ir_codes = RC_MAP_BEHOLD;
dev->init_data.type = RC_PROTO_BIT_NECX;
info.addr = 0x2d;
break;
case SAA7134_BOARD_AVERMEDIA_CARDBUS_501:
case SAA7134_BOARD_AVERMEDIA_CARDBUS_506:
info.addr = 0x40;
break;
case SAA7134_BOARD_AVERMEDIA_A706:
info.addr = 0x41;
break;
case SAA7134_BOARD_FLYDVB_TRIO:
dev->init_data.name = "FlyDVB Trio";
dev->init_data.get_key = get_key_flydvb_trio;
dev->init_data.ir_codes = RC_MAP_FLYDVB;
info.addr = 0x0b;
break;
default:
input_dbg("No I2C IR support for board %x\n", dev->board);
return;
}
if (dev->init_data.name)
info.platform_data = &dev->init_data;
i2c_new_client_device(&dev->i2c_adap, &info);
}
static int saa7134_raw_decode_irq(struct saa7134_dev *dev)
{
struct saa7134_card_ir *ir = dev->remote;
int space;
/* Generate initial event */
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
space = saa_readl(SAA7134_GPIO_GPSTATUS0 >> 2) & ir->mask_keydown;
ir_raw_event_store_edge(dev->remote->dev, !space);
return 1;
}
| linux-master | drivers/media/pci/saa7134/saa7134-input.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* SAA713x ALSA support for V4L
*/
#include "saa7134.h"
#include "saa7134-reg.h"
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/wait.h>
#include <linux/module.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <linux/interrupt.h>
#include <linux/vmalloc.h>
/*
* Configuration macros
*/
/* defaults */
#define MIXER_ADDR_UNSELECTED -1
#define MIXER_ADDR_TVTUNER 0
#define MIXER_ADDR_LINE1 1
#define MIXER_ADDR_LINE2 2
#define MIXER_ADDR_LAST 2
static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
static int enable[SNDRV_CARDS] = {1, [1 ... (SNDRV_CARDS - 1)] = 1};
module_param_array(index, int, NULL, 0444);
module_param_array(enable, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for SAA7134 capture interface(s).");
MODULE_PARM_DESC(enable, "Enable (or not) the SAA7134 capture interface(s).");
/*
* Main chip structure
*/
typedef struct snd_card_saa7134 {
struct snd_card *card;
spinlock_t mixer_lock;
int mixer_volume[MIXER_ADDR_LAST+1][2];
int capture_source_addr;
int capture_source[2];
struct snd_kcontrol *capture_ctl[MIXER_ADDR_LAST+1];
struct pci_dev *pci;
struct saa7134_dev *dev;
unsigned long iobase;
s16 irq;
u16 mute_was_on;
spinlock_t lock;
} snd_card_saa7134_t;
/*
* PCM structure
*/
typedef struct snd_card_saa7134_pcm {
struct saa7134_dev *dev;
spinlock_t lock;
struct snd_pcm_substream *substream;
} snd_card_saa7134_pcm_t;
static struct snd_card *snd_saa7134_cards[SNDRV_CARDS];
/*
* saa7134 DMA audio stop
*
* Called when the capture device is released or the buffer overflows
*
* - Copied verbatim from saa7134-oss's dsp_dma_stop.
*
*/
static void saa7134_dma_stop(struct saa7134_dev *dev)
{
dev->dmasound.dma_blk = -1;
dev->dmasound.dma_running = 0;
saa7134_set_dmabits(dev);
}
/*
* saa7134 DMA audio start
*
* Called when preparing the capture device for use
*
* - Copied verbatim from saa7134-oss's dsp_dma_start.
*
*/
static void saa7134_dma_start(struct saa7134_dev *dev)
{
dev->dmasound.dma_blk = 0;
dev->dmasound.dma_running = 1;
saa7134_set_dmabits(dev);
}
/*
* saa7134 audio DMA IRQ handler
*
* Called whenever we get an SAA7134_IRQ_REPORT_DONE_RA3 interrupt
* Handles shifting between the 2 buffers, manages the read counters,
* and notifies ALSA when periods elapse
*
* - Mostly copied from saa7134-oss's saa7134_irq_oss_done.
*
*/
static void saa7134_irq_alsa_done(struct saa7134_dev *dev,
unsigned long status)
{
int next_blk, reg = 0;
spin_lock(&dev->slock);
if (UNSET == dev->dmasound.dma_blk) {
pr_debug("irq: recording stopped\n");
goto done;
}
if (0 != (status & 0x0f000000))
pr_debug("irq: lost %ld\n", (status >> 24) & 0x0f);
if (0 == (status & 0x10000000)) {
/* odd */
if (0 == (dev->dmasound.dma_blk & 0x01))
reg = SAA7134_RS_BA1(6);
} else {
/* even */
if (1 == (dev->dmasound.dma_blk & 0x01))
reg = SAA7134_RS_BA2(6);
}
if (0 == reg) {
pr_debug("irq: field oops [%s]\n",
(status & 0x10000000) ? "even" : "odd");
goto done;
}
if (dev->dmasound.read_count >= dev->dmasound.blksize * (dev->dmasound.blocks-2)) {
pr_debug("irq: overrun [full=%d/%d] - Blocks in %d\n",
dev->dmasound.read_count,
dev->dmasound.bufsize, dev->dmasound.blocks);
spin_unlock(&dev->slock);
snd_pcm_stop_xrun(dev->dmasound.substream);
return;
}
/* next block addr */
next_blk = (dev->dmasound.dma_blk + 2) % dev->dmasound.blocks;
saa_writel(reg,next_blk * dev->dmasound.blksize);
pr_debug("irq: ok, %s, next_blk=%d, addr=%x, blocks=%u, size=%u, read=%u\n",
(status & 0x10000000) ? "even" : "odd ", next_blk,
next_blk * dev->dmasound.blksize, dev->dmasound.blocks,
dev->dmasound.blksize, dev->dmasound.read_count);
/* update status & wake waiting readers */
dev->dmasound.dma_blk = (dev->dmasound.dma_blk + 1) % dev->dmasound.blocks;
dev->dmasound.read_count += dev->dmasound.blksize;
dev->dmasound.recording_on = reg;
if (dev->dmasound.read_count >= snd_pcm_lib_period_bytes(dev->dmasound.substream)) {
spin_unlock(&dev->slock);
snd_pcm_period_elapsed(dev->dmasound.substream);
spin_lock(&dev->slock);
}
done:
spin_unlock(&dev->slock);
}
/*
* IRQ request handler
*
* Runs along with saa7134's IRQ handler, discards anything that isn't
* DMA sound
*
*/
static irqreturn_t saa7134_alsa_irq(int irq, void *dev_id)
{
struct saa7134_dmasound *dmasound = dev_id;
struct saa7134_dev *dev = dmasound->priv_data;
unsigned long report, status;
int loop, handled = 0;
for (loop = 0; loop < 10; loop++) {
report = saa_readl(SAA7134_IRQ_REPORT);
status = saa_readl(SAA7134_IRQ_STATUS);
if (report & SAA7134_IRQ_REPORT_DONE_RA3) {
handled = 1;
saa_writel(SAA7134_IRQ_REPORT,
SAA7134_IRQ_REPORT_DONE_RA3);
saa7134_irq_alsa_done(dev, status);
} else {
goto out;
}
}
if (loop == 10) {
pr_debug("error! looping IRQ!");
}
out:
return IRQ_RETVAL(handled);
}
/*
* ALSA capture trigger
*
* - One of the ALSA capture callbacks.
*
* Called whenever a capture is started or stopped. Must be defined,
* but there's nothing we want to do here
*
*/
static int snd_card_saa7134_capture_trigger(struct snd_pcm_substream * substream,
int cmd)
{
struct snd_pcm_runtime *runtime = substream->runtime;
snd_card_saa7134_pcm_t *pcm = runtime->private_data;
struct saa7134_dev *dev=pcm->dev;
int err = 0;
spin_lock(&dev->slock);
if (cmd == SNDRV_PCM_TRIGGER_START) {
/* start dma */
saa7134_dma_start(dev);
} else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
/* stop dma */
saa7134_dma_stop(dev);
} else {
err = -EINVAL;
}
spin_unlock(&dev->slock);
return err;
}
static int saa7134_alsa_dma_init(struct saa7134_dev *dev,
unsigned long nr_pages)
{
struct saa7134_dmasound *dma = &dev->dmasound;
struct page *pg;
int i;
dma->vaddr = vmalloc_32(nr_pages << PAGE_SHIFT);
if (NULL == dma->vaddr) {
pr_debug("vmalloc_32(%lu pages) failed\n", nr_pages);
return -ENOMEM;
}
pr_debug("vmalloc is at addr %p, size=%lu\n",
dma->vaddr, nr_pages << PAGE_SHIFT);
memset(dma->vaddr, 0, nr_pages << PAGE_SHIFT);
dma->nr_pages = nr_pages;
dma->sglist = vzalloc(array_size(sizeof(*dma->sglist), dma->nr_pages));
if (NULL == dma->sglist)
goto vzalloc_err;
sg_init_table(dma->sglist, dma->nr_pages);
for (i = 0; i < dma->nr_pages; i++) {
pg = vmalloc_to_page(dma->vaddr + i * PAGE_SIZE);
if (NULL == pg)
goto vmalloc_to_page_err;
sg_set_page(&dma->sglist[i], pg, PAGE_SIZE, 0);
}
return 0;
vmalloc_to_page_err:
vfree(dma->sglist);
dma->sglist = NULL;
vzalloc_err:
vfree(dma->vaddr);
dma->vaddr = NULL;
return -ENOMEM;
}
static int saa7134_alsa_dma_map(struct saa7134_dev *dev)
{
struct saa7134_dmasound *dma = &dev->dmasound;
dma->sglen = dma_map_sg(&dev->pci->dev, dma->sglist,
dma->nr_pages, DMA_FROM_DEVICE);
if (0 == dma->sglen) {
pr_warn("%s: saa7134_alsa_map_sg failed\n", __func__);
return -ENOMEM;
}
return 0;
}
static int saa7134_alsa_dma_unmap(struct saa7134_dev *dev)
{
struct saa7134_dmasound *dma = &dev->dmasound;
if (!dma->sglen)
return 0;
dma_unmap_sg(&dev->pci->dev, dma->sglist, dma->nr_pages, DMA_FROM_DEVICE);
dma->sglen = 0;
return 0;
}
static int saa7134_alsa_dma_free(struct saa7134_dmasound *dma)
{
vfree(dma->sglist);
dma->sglist = NULL;
vfree(dma->vaddr);
dma->vaddr = NULL;
return 0;
}
/*
* DMA buffer initialization
*
* Uses V4L functions to initialize the DMA. Shouldn't be necessary in
* ALSA, but I was unable to use ALSA's own DMA, and had to force the
* usage of V4L's
*
* - Copied verbatim from saa7134-oss.
*
*/
static int dsp_buffer_init(struct saa7134_dev *dev)
{
int err;
BUG_ON(!dev->dmasound.bufsize);
err = saa7134_alsa_dma_init(dev,
(dev->dmasound.bufsize + PAGE_SIZE) >> PAGE_SHIFT);
if (0 != err)
return err;
return 0;
}
/*
* DMA buffer release
*
* Called after closing the device, during snd_card_saa7134_capture_close
*
*/
static int dsp_buffer_free(struct saa7134_dev *dev)
{
BUG_ON(!dev->dmasound.blksize);
saa7134_alsa_dma_free(&dev->dmasound);
dev->dmasound.blocks = 0;
dev->dmasound.blksize = 0;
dev->dmasound.bufsize = 0;
return 0;
}
/*
* Setting the capture source and updating the ALSA controls
*/
static int snd_saa7134_capsrc_set(struct snd_kcontrol *kcontrol,
int left, int right, bool force_notify)
{
snd_card_saa7134_t *chip = snd_kcontrol_chip(kcontrol);
int change = 0, addr = kcontrol->private_value;
int active, old_addr;
u32 anabar, xbarin;
int analog_io, rate;
struct saa7134_dev *dev;
dev = chip->dev;
spin_lock_irq(&chip->mixer_lock);
active = left != 0 || right != 0;
old_addr = chip->capture_source_addr;
/* The active capture source cannot be deactivated */
if (active) {
change = old_addr != addr ||
chip->capture_source[0] != left ||
chip->capture_source[1] != right;
chip->capture_source[0] = left;
chip->capture_source[1] = right;
chip->capture_source_addr = addr;
dev->dmasound.input = addr;
}
spin_unlock_irq(&chip->mixer_lock);
if (change) {
switch (dev->pci->device) {
case PCI_DEVICE_ID_PHILIPS_SAA7134:
switch (addr) {
case MIXER_ADDR_TVTUNER:
saa_andorb(SAA7134_AUDIO_FORMAT_CTRL,
0xc0, 0xc0);
saa_andorb(SAA7134_SIF_SAMPLE_FREQ,
0x03, 0x00);
break;
case MIXER_ADDR_LINE1:
case MIXER_ADDR_LINE2:
analog_io = (MIXER_ADDR_LINE1 == addr) ?
0x00 : 0x08;
rate = (32000 == dev->dmasound.rate) ?
0x01 : 0x03;
saa_andorb(SAA7134_ANALOG_IO_SELECT,
0x08, analog_io);
saa_andorb(SAA7134_AUDIO_FORMAT_CTRL,
0xc0, 0x80);
saa_andorb(SAA7134_SIF_SAMPLE_FREQ,
0x03, rate);
break;
}
break;
case PCI_DEVICE_ID_PHILIPS_SAA7133:
case PCI_DEVICE_ID_PHILIPS_SAA7135:
xbarin = 0x03; /* adc */
anabar = 0;
switch (addr) {
case MIXER_ADDR_TVTUNER:
xbarin = 0; /* Demodulator */
anabar = 2; /* DACs */
break;
case MIXER_ADDR_LINE1:
anabar = 0; /* aux1, aux1 */
break;
case MIXER_ADDR_LINE2:
anabar = 9; /* aux2, aux2 */
break;
}
/* output xbar always main channel */
saa_dsp_writel(dev, SAA7133_DIGITAL_OUTPUT_SEL1,
0xbbbb10);
if (left || right) {
/* We've got data, turn the input on */
saa_dsp_writel(dev, SAA7133_DIGITAL_INPUT_XBAR1,
xbarin);
saa_writel(SAA7133_ANALOG_IO_SELECT, anabar);
} else {
saa_dsp_writel(dev, SAA7133_DIGITAL_INPUT_XBAR1,
0);
saa_writel(SAA7133_ANALOG_IO_SELECT, 0);
}
break;
}
}
if (change) {
if (force_notify)
snd_ctl_notify(chip->card,
SNDRV_CTL_EVENT_MASK_VALUE,
&chip->capture_ctl[addr]->id);
if (old_addr != MIXER_ADDR_UNSELECTED && old_addr != addr)
snd_ctl_notify(chip->card,
SNDRV_CTL_EVENT_MASK_VALUE,
&chip->capture_ctl[old_addr]->id);
}
return change;
}
/*
* ALSA PCM preparation
*
* - One of the ALSA capture callbacks.
*
* Called right after the capture device is opened, this function configures
* the buffer using the previously defined functions, allocates the memory,
* sets up the hardware registers, and then starts the DMA. When this function
* returns, the audio should be flowing.
*
*/
static int snd_card_saa7134_capture_prepare(struct snd_pcm_substream * substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
int bswap, sign;
u32 fmt, control;
snd_card_saa7134_t *saa7134 = snd_pcm_substream_chip(substream);
struct saa7134_dev *dev;
snd_card_saa7134_pcm_t *pcm = runtime->private_data;
pcm->dev->dmasound.substream = substream;
dev = saa7134->dev;
if (snd_pcm_format_width(runtime->format) == 8)
fmt = 0x00;
else
fmt = 0x01;
if (snd_pcm_format_signed(runtime->format))
sign = 1;
else
sign = 0;
if (snd_pcm_format_big_endian(runtime->format))
bswap = 1;
else
bswap = 0;
switch (dev->pci->device) {
case PCI_DEVICE_ID_PHILIPS_SAA7134:
if (1 == runtime->channels)
fmt |= (1 << 3);
if (2 == runtime->channels)
fmt |= (3 << 3);
if (sign)
fmt |= 0x04;
fmt |= (MIXER_ADDR_TVTUNER == dev->dmasound.input) ? 0xc0 : 0x80;
saa_writeb(SAA7134_NUM_SAMPLES0, ((dev->dmasound.blksize - 1) & 0x0000ff));
saa_writeb(SAA7134_NUM_SAMPLES1, ((dev->dmasound.blksize - 1) & 0x00ff00) >> 8);
saa_writeb(SAA7134_NUM_SAMPLES2, ((dev->dmasound.blksize - 1) & 0xff0000) >> 16);
saa_writeb(SAA7134_AUDIO_FORMAT_CTRL, fmt);
break;
case PCI_DEVICE_ID_PHILIPS_SAA7133:
case PCI_DEVICE_ID_PHILIPS_SAA7135:
if (1 == runtime->channels)
fmt |= (1 << 4);
if (2 == runtime->channels)
fmt |= (2 << 4);
if (!sign)
fmt |= 0x04;
saa_writel(SAA7133_NUM_SAMPLES, dev->dmasound.blksize -1);
saa_writel(SAA7133_AUDIO_CHANNEL, 0x543210 | (fmt << 24));
break;
}
pr_debug("rec_start: afmt=%d ch=%d => fmt=0x%x swap=%c\n",
runtime->format, runtime->channels, fmt,
bswap ? 'b' : '-');
/* dma: setup channel 6 (= AUDIO) */
control = SAA7134_RS_CONTROL_BURST_16 |
SAA7134_RS_CONTROL_ME |
(dev->dmasound.pt.dma >> 12);
if (bswap)
control |= SAA7134_RS_CONTROL_BSWAP;
saa_writel(SAA7134_RS_BA1(6),0);
saa_writel(SAA7134_RS_BA2(6),dev->dmasound.blksize);
saa_writel(SAA7134_RS_PITCH(6),0);
saa_writel(SAA7134_RS_CONTROL(6),control);
dev->dmasound.rate = runtime->rate;
/* Setup and update the card/ALSA controls */
snd_saa7134_capsrc_set(saa7134->capture_ctl[dev->dmasound.input], 1, 1,
true);
return 0;
}
/*
* ALSA pointer fetching
*
* - One of the ALSA capture callbacks.
*
* Called whenever a period elapses, it must return the current hardware
* position of the buffer.
* Also resets the read counter used to prevent overruns
*
*/
static snd_pcm_uframes_t
snd_card_saa7134_capture_pointer(struct snd_pcm_substream * substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
snd_card_saa7134_pcm_t *pcm = runtime->private_data;
struct saa7134_dev *dev=pcm->dev;
if (dev->dmasound.read_count) {
dev->dmasound.read_count -= snd_pcm_lib_period_bytes(substream);
dev->dmasound.read_offset += snd_pcm_lib_period_bytes(substream);
if (dev->dmasound.read_offset == dev->dmasound.bufsize)
dev->dmasound.read_offset = 0;
}
return bytes_to_frames(runtime, dev->dmasound.read_offset);
}
/*
* ALSA hardware capabilities definition
*
* Report only 32kHz for ALSA:
*
* - SAA7133/35 uses DDEP (DemDec Easy Programming mode), which works in 32kHz
* only
* - SAA7134 for TV mode uses DemDec mode (32kHz)
* - Radio works in 32kHz only
* - When recording 48kHz from Line1/Line2, switching of capture source to TV
* means
* switching to 32kHz without any frequency translation
*/
static const struct snd_pcm_hardware snd_card_saa7134_capture =
{
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID),
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S16_BE | \
SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_U8 | \
SNDRV_PCM_FMTBIT_U16_LE | \
SNDRV_PCM_FMTBIT_U16_BE,
.rates = SNDRV_PCM_RATE_32000,
.rate_min = 32000,
.rate_max = 32000,
.channels_min = 1,
.channels_max = 2,
.buffer_bytes_max = (256*1024),
.period_bytes_min = 64,
.period_bytes_max = (256*1024),
.periods_min = 4,
.periods_max = 1024,
};
static void snd_card_saa7134_runtime_free(struct snd_pcm_runtime *runtime)
{
snd_card_saa7134_pcm_t *pcm = runtime->private_data;
kfree(pcm);
}
/*
* ALSA hardware params
*
* - One of the ALSA capture callbacks.
*
* Called on initialization, right before the PCM preparation
*
*/
static int snd_card_saa7134_hw_params(struct snd_pcm_substream * substream,
struct snd_pcm_hw_params * hw_params)
{
snd_card_saa7134_t *saa7134 = snd_pcm_substream_chip(substream);
struct saa7134_dev *dev;
unsigned int period_size, periods;
int err;
period_size = params_period_bytes(hw_params);
periods = params_periods(hw_params);
if (period_size < 0x100 || period_size > 0x10000)
return -EINVAL;
if (periods < 4)
return -EINVAL;
if (period_size * periods > 1024 * 1024)
return -EINVAL;
dev = saa7134->dev;
if (dev->dmasound.blocks == periods &&
dev->dmasound.blksize == period_size)
return 0;
/* release the old buffer */
if (substream->runtime->dma_area) {
saa7134_pgtable_free(dev->pci, &dev->dmasound.pt);
saa7134_alsa_dma_unmap(dev);
dsp_buffer_free(dev);
substream->runtime->dma_area = NULL;
}
dev->dmasound.blocks = periods;
dev->dmasound.blksize = period_size;
dev->dmasound.bufsize = period_size * periods;
err = dsp_buffer_init(dev);
if (0 != err) {
dev->dmasound.blocks = 0;
dev->dmasound.blksize = 0;
dev->dmasound.bufsize = 0;
return err;
}
err = saa7134_alsa_dma_map(dev);
if (err) {
dsp_buffer_free(dev);
return err;
}
err = saa7134_pgtable_alloc(dev->pci, &dev->dmasound.pt);
if (err) {
saa7134_alsa_dma_unmap(dev);
dsp_buffer_free(dev);
return err;
}
err = saa7134_pgtable_build(dev->pci, &dev->dmasound.pt,
dev->dmasound.sglist, dev->dmasound.sglen, 0);
if (err) {
saa7134_pgtable_free(dev->pci, &dev->dmasound.pt);
saa7134_alsa_dma_unmap(dev);
dsp_buffer_free(dev);
return err;
}
/* I should be able to use runtime->dma_addr in the control
byte, but it doesn't work. So I allocate the DMA using the
V4L functions, and force ALSA to use that as the DMA area */
substream->runtime->dma_area = dev->dmasound.vaddr;
substream->runtime->dma_bytes = dev->dmasound.bufsize;
substream->runtime->dma_addr = 0;
return 0;
}
/*
* ALSA hardware release
*
* - One of the ALSA capture callbacks.
*
* Called after closing the device, but before snd_card_saa7134_capture_close
* It stops the DMA audio and releases the buffers.
*
*/
static int snd_card_saa7134_hw_free(struct snd_pcm_substream * substream)
{
snd_card_saa7134_t *saa7134 = snd_pcm_substream_chip(substream);
struct saa7134_dev *dev;
dev = saa7134->dev;
if (substream->runtime->dma_area) {
saa7134_pgtable_free(dev->pci, &dev->dmasound.pt);
saa7134_alsa_dma_unmap(dev);
dsp_buffer_free(dev);
substream->runtime->dma_area = NULL;
}
return 0;
}
/*
* ALSA capture finish
*
* - One of the ALSA capture callbacks.
*
* Called after closing the device.
*
*/
static int snd_card_saa7134_capture_close(struct snd_pcm_substream * substream)
{
snd_card_saa7134_t *saa7134 = snd_pcm_substream_chip(substream);
struct saa7134_dev *dev = saa7134->dev;
if (saa7134->mute_was_on) {
dev->ctl_mute = 1;
saa7134_tvaudio_setmute(dev);
}
return 0;
}
/*
* ALSA capture start
*
* - One of the ALSA capture callbacks.
*
* Called when opening the device. It creates and populates the PCM
* structure
*
*/
static int snd_card_saa7134_capture_open(struct snd_pcm_substream * substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
snd_card_saa7134_pcm_t *pcm;
snd_card_saa7134_t *saa7134 = snd_pcm_substream_chip(substream);
struct saa7134_dev *dev;
int amux, err;
if (!saa7134) {
pr_err("BUG: saa7134 can't find device struct. Can't proceed with open\n");
return -ENODEV;
}
dev = saa7134->dev;
mutex_lock(&dev->dmasound.lock);
dev->dmasound.read_count = 0;
dev->dmasound.read_offset = 0;
amux = dev->input->amux;
if ((amux < 1) || (amux > 3))
amux = 1;
dev->dmasound.input = amux - 1;
mutex_unlock(&dev->dmasound.lock);
pcm = kzalloc(sizeof(*pcm), GFP_KERNEL);
if (pcm == NULL)
return -ENOMEM;
pcm->dev=saa7134->dev;
spin_lock_init(&pcm->lock);
pcm->substream = substream;
runtime->private_data = pcm;
runtime->private_free = snd_card_saa7134_runtime_free;
runtime->hw = snd_card_saa7134_capture;
if (dev->ctl_mute != 0) {
saa7134->mute_was_on = 1;
dev->ctl_mute = 0;
saa7134_tvaudio_setmute(dev);
}
err = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (err < 0)
return err;
err = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_PERIODS, 2);
if (err < 0)
return err;
return 0;
}
/*
* page callback (needed for mmap)
*/
static struct page *snd_card_saa7134_page(struct snd_pcm_substream *substream,
unsigned long offset)
{
void *pageptr = substream->runtime->dma_area + offset;
return vmalloc_to_page(pageptr);
}
/*
* ALSA capture callbacks definition
*/
static const struct snd_pcm_ops snd_card_saa7134_capture_ops = {
.open = snd_card_saa7134_capture_open,
.close = snd_card_saa7134_capture_close,
.hw_params = snd_card_saa7134_hw_params,
.hw_free = snd_card_saa7134_hw_free,
.prepare = snd_card_saa7134_capture_prepare,
.trigger = snd_card_saa7134_capture_trigger,
.pointer = snd_card_saa7134_capture_pointer,
.page = snd_card_saa7134_page,
};
/*
* ALSA PCM setup
*
* Called when initializing the board. Sets up the name and hooks up
* the callbacks
*
*/
static int snd_card_saa7134_pcm(snd_card_saa7134_t *saa7134, int device)
{
struct snd_pcm *pcm;
int err;
if ((err = snd_pcm_new(saa7134->card, "SAA7134 PCM", device, 0, 1, &pcm)) < 0)
return err;
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_card_saa7134_capture_ops);
pcm->private_data = saa7134;
pcm->info_flags = 0;
strscpy(pcm->name, "SAA7134 PCM", sizeof(pcm->name));
return 0;
}
#define SAA713x_VOLUME(xname, xindex, addr) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
.info = snd_saa7134_volume_info, \
.get = snd_saa7134_volume_get, .put = snd_saa7134_volume_put, \
.private_value = addr }
static int snd_saa7134_volume_info(struct snd_kcontrol * kcontrol,
struct snd_ctl_elem_info * uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 2;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 20;
return 0;
}
static int snd_saa7134_volume_get(struct snd_kcontrol * kcontrol,
struct snd_ctl_elem_value * ucontrol)
{
snd_card_saa7134_t *chip = snd_kcontrol_chip(kcontrol);
int addr = kcontrol->private_value;
ucontrol->value.integer.value[0] = chip->mixer_volume[addr][0];
ucontrol->value.integer.value[1] = chip->mixer_volume[addr][1];
return 0;
}
static int snd_saa7134_volume_put(struct snd_kcontrol * kcontrol,
struct snd_ctl_elem_value * ucontrol)
{
snd_card_saa7134_t *chip = snd_kcontrol_chip(kcontrol);
struct saa7134_dev *dev = chip->dev;
int change, addr = kcontrol->private_value;
int left, right;
left = ucontrol->value.integer.value[0];
if (left < 0)
left = 0;
if (left > 20)
left = 20;
right = ucontrol->value.integer.value[1];
if (right < 0)
right = 0;
if (right > 20)
right = 20;
spin_lock_irq(&chip->mixer_lock);
change = 0;
if (chip->mixer_volume[addr][0] != left) {
change = 1;
right = left;
}
if (chip->mixer_volume[addr][1] != right) {
change = 1;
left = right;
}
if (change) {
switch (dev->pci->device) {
case PCI_DEVICE_ID_PHILIPS_SAA7134:
switch (addr) {
case MIXER_ADDR_TVTUNER:
left = 20;
break;
case MIXER_ADDR_LINE1:
saa_andorb(SAA7134_ANALOG_IO_SELECT, 0x10,
(left > 10) ? 0x00 : 0x10);
break;
case MIXER_ADDR_LINE2:
saa_andorb(SAA7134_ANALOG_IO_SELECT, 0x20,
(left > 10) ? 0x00 : 0x20);
break;
}
break;
case PCI_DEVICE_ID_PHILIPS_SAA7133:
case PCI_DEVICE_ID_PHILIPS_SAA7135:
switch (addr) {
case MIXER_ADDR_TVTUNER:
left = 20;
break;
case MIXER_ADDR_LINE1:
saa_andorb(0x0594, 0x10,
(left > 10) ? 0x00 : 0x10);
break;
case MIXER_ADDR_LINE2:
saa_andorb(0x0594, 0x20,
(left > 10) ? 0x00 : 0x20);
break;
}
break;
}
chip->mixer_volume[addr][0] = left;
chip->mixer_volume[addr][1] = right;
}
spin_unlock_irq(&chip->mixer_lock);
return change;
}
#define SAA713x_CAPSRC(xname, xindex, addr) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
.info = snd_saa7134_capsrc_info, \
.get = snd_saa7134_capsrc_get, .put = snd_saa7134_capsrc_put, \
.private_value = addr }
static int snd_saa7134_capsrc_info(struct snd_kcontrol * kcontrol,
struct snd_ctl_elem_info * uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 2;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int snd_saa7134_capsrc_get(struct snd_kcontrol * kcontrol,
struct snd_ctl_elem_value * ucontrol)
{
snd_card_saa7134_t *chip = snd_kcontrol_chip(kcontrol);
int addr = kcontrol->private_value;
spin_lock_irq(&chip->mixer_lock);
if (chip->capture_source_addr == addr) {
ucontrol->value.integer.value[0] = chip->capture_source[0];
ucontrol->value.integer.value[1] = chip->capture_source[1];
} else {
ucontrol->value.integer.value[0] = 0;
ucontrol->value.integer.value[1] = 0;
}
spin_unlock_irq(&chip->mixer_lock);
return 0;
}
static int snd_saa7134_capsrc_put(struct snd_kcontrol * kcontrol,
struct snd_ctl_elem_value * ucontrol)
{
int left, right;
left = ucontrol->value.integer.value[0] & 1;
right = ucontrol->value.integer.value[1] & 1;
return snd_saa7134_capsrc_set(kcontrol, left, right, false);
}
static struct snd_kcontrol_new snd_saa7134_volume_controls[] = {
SAA713x_VOLUME("Video Volume", 0, MIXER_ADDR_TVTUNER),
SAA713x_VOLUME("Line Volume", 1, MIXER_ADDR_LINE1),
SAA713x_VOLUME("Line Volume", 2, MIXER_ADDR_LINE2),
};
static struct snd_kcontrol_new snd_saa7134_capture_controls[] = {
SAA713x_CAPSRC("Video Capture Switch", 0, MIXER_ADDR_TVTUNER),
SAA713x_CAPSRC("Line Capture Switch", 1, MIXER_ADDR_LINE1),
SAA713x_CAPSRC("Line Capture Switch", 2, MIXER_ADDR_LINE2),
};
/*
* ALSA mixer setup
*
* Called when initializing the board. Sets up the name and hooks up
* the callbacks
*
*/
static int snd_card_saa7134_new_mixer(snd_card_saa7134_t * chip)
{
struct snd_card *card = chip->card;
struct snd_kcontrol *kcontrol;
unsigned int idx;
int err, addr;
strscpy(card->mixername, "SAA7134 Mixer", sizeof(card->mixername));
for (idx = 0; idx < ARRAY_SIZE(snd_saa7134_volume_controls); idx++) {
kcontrol = snd_ctl_new1(&snd_saa7134_volume_controls[idx],
chip);
err = snd_ctl_add(card, kcontrol);
if (err < 0)
return err;
}
for (idx = 0; idx < ARRAY_SIZE(snd_saa7134_capture_controls); idx++) {
kcontrol = snd_ctl_new1(&snd_saa7134_capture_controls[idx],
chip);
addr = snd_saa7134_capture_controls[idx].private_value;
chip->capture_ctl[addr] = kcontrol;
err = snd_ctl_add(card, kcontrol);
if (err < 0)
return err;
}
chip->capture_source_addr = MIXER_ADDR_UNSELECTED;
return 0;
}
static void snd_saa7134_free(struct snd_card * card)
{
snd_card_saa7134_t *chip = card->private_data;
if (chip->dev->dmasound.priv_data == NULL)
return;
if (chip->irq >= 0)
free_irq(chip->irq, &chip->dev->dmasound);
chip->dev->dmasound.priv_data = NULL;
}
/*
* ALSA initialization
*
* Called by the init routine, once for each saa7134 device present,
* it creates the basic structures and registers the ALSA devices
*
*/
static int alsa_card_saa7134_create(struct saa7134_dev *dev, int devnum)
{
struct snd_card *card;
snd_card_saa7134_t *chip;
int err;
if (devnum >= SNDRV_CARDS)
return -ENODEV;
if (!enable[devnum])
return -ENODEV;
err = snd_card_new(&dev->pci->dev, index[devnum], id[devnum],
THIS_MODULE, sizeof(snd_card_saa7134_t), &card);
if (err < 0)
return err;
strscpy(card->driver, "SAA7134", sizeof(card->driver));
/* Card "creation" */
card->private_free = snd_saa7134_free;
chip = card->private_data;
spin_lock_init(&chip->lock);
spin_lock_init(&chip->mixer_lock);
chip->dev = dev;
chip->card = card;
chip->pci = dev->pci;
chip->iobase = pci_resource_start(dev->pci, 0);
err = request_irq(dev->pci->irq, saa7134_alsa_irq,
IRQF_SHARED, dev->name,
(void*) &dev->dmasound);
if (err < 0) {
pr_err("%s: can't get IRQ %d for ALSA\n",
dev->name, dev->pci->irq);
goto __nodev;
}
chip->irq = dev->pci->irq;
mutex_init(&dev->dmasound.lock);
if ((err = snd_card_saa7134_new_mixer(chip)) < 0)
goto __nodev;
if ((err = snd_card_saa7134_pcm(chip, 0)) < 0)
goto __nodev;
/* End of "creation" */
strscpy(card->shortname, "SAA7134", sizeof(card->shortname));
sprintf(card->longname, "%s at 0x%lx irq %d",
chip->dev->name, chip->iobase, chip->irq);
pr_info("%s/alsa: %s registered as card %d\n",
dev->name, card->longname, index[devnum]);
if ((err = snd_card_register(card)) == 0) {
snd_saa7134_cards[devnum] = card;
return 0;
}
__nodev:
snd_card_free(card);
return err;
}
static int alsa_device_init(struct saa7134_dev *dev)
{
dev->dmasound.priv_data = dev;
alsa_card_saa7134_create(dev,dev->nr);
return 1;
}
static int alsa_device_exit(struct saa7134_dev *dev)
{
if (!snd_saa7134_cards[dev->nr])
return 1;
snd_card_free(snd_saa7134_cards[dev->nr]);
snd_saa7134_cards[dev->nr] = NULL;
return 1;
}
/*
* Module initializer
*
* Loops through present saa7134 cards, and assigns an ALSA device
* to each one
*
*/
static int saa7134_alsa_init(void)
{
struct saa7134_dev *dev;
saa7134_dmasound_init = alsa_device_init;
saa7134_dmasound_exit = alsa_device_exit;
pr_info("saa7134 ALSA driver for DMA sound loaded\n");
list_for_each_entry(dev, &saa7134_devlist, devlist) {
if (dev->pci->device == PCI_DEVICE_ID_PHILIPS_SAA7130)
pr_info("%s/alsa: %s doesn't support digital audio\n",
dev->name, saa7134_boards[dev->board].name);
else
alsa_device_init(dev);
}
if (list_empty(&saa7134_devlist))
pr_info("saa7134 ALSA: no saa7134 cards found\n");
return 0;
}
/*
* Module destructor
*/
static void saa7134_alsa_exit(void)
{
int idx;
for (idx = 0; idx < SNDRV_CARDS; idx++) {
if (snd_saa7134_cards[idx])
snd_card_free(snd_saa7134_cards[idx]);
}
saa7134_dmasound_init = NULL;
saa7134_dmasound_exit = NULL;
pr_info("saa7134 ALSA driver for DMA sound unloaded\n");
return;
}
/* We initialize this late, to make sure the sound system is up and running */
late_initcall(saa7134_alsa_init);
module_exit(saa7134_alsa_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Ricardo Cerqueira");
| linux-master | drivers/media/pci/saa7134/saa7134-alsa.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* TW5864 driver - core functions
*
* Copyright (C) 2016 Bluecherry, LLC <[email protected]>
*/
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/kmod.h>
#include <linux/sound.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/pm.h>
#include <linux/pci_ids.h>
#include <linux/jiffies.h>
#include <asm/dma.h>
#include <media/v4l2-dev.h>
#include "tw5864.h"
#include "tw5864-reg.h"
MODULE_DESCRIPTION("V4L2 driver module for tw5864-based multimedia capture & encoding devices");
MODULE_AUTHOR("Bluecherry Maintainers <[email protected]>");
MODULE_AUTHOR("Andrey Utkin <[email protected]>");
MODULE_LICENSE("GPL");
/*
* BEWARE OF KNOWN ISSUES WITH VIDEO QUALITY
*
* This driver was developed by Bluecherry LLC by deducing behaviour of
* original manufacturer's driver, from both source code and execution traces.
* It is known that there are some artifacts on output video with this driver:
* - on all known hardware samples: random pixels of wrong color (mostly
* white, red or blue) appearing and disappearing on sequences of P-frames;
* - on some hardware samples (known with H.264 core version e006:2800):
* total madness on P-frames: blocks of wrong luminance; blocks of wrong
* colors "creeping" across the picture.
* There is a workaround for both issues: avoid P-frames by setting GOP size
* to 1. To do that, run this command on device files created by this driver:
*
* v4l2-ctl --device /dev/videoX --set-ctrl=video_gop_size=1
*
* These issues are not decoding errors; all produced H.264 streams are decoded
* properly. Streams without P-frames don't have these artifacts so it's not
* analog-to-digital conversion issues nor internal memory errors; we conclude
* it's internal H.264 encoder issues.
* We cannot even check the original driver's behaviour because it has never
* worked properly at all in our development environment. So these issues may
* be actually related to firmware or hardware. However it may be that there's
* just some more register settings missing in the driver which would please
* the hardware.
* Manufacturer didn't help much on our inquiries, but feel free to disturb
* again the support of Intersil (owner of former Techwell).
*/
/* take first free /dev/videoX indexes by default */
static unsigned int video_nr[] = {[0 ... (TW5864_INPUTS - 1)] = -1 };
module_param_array(video_nr, int, NULL, 0444);
MODULE_PARM_DESC(video_nr, "video devices numbers array");
/*
* Please add any new PCI IDs to: https://pci-ids.ucw.cz. This keeps
* the PCI ID database up to date. Note that the entries must be
* added under vendor 0x1797 (Techwell Inc.) as subsystem IDs.
*/
static const struct pci_device_id tw5864_pci_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_5864)},
{0,}
};
void tw5864_irqmask_apply(struct tw5864_dev *dev)
{
tw_writel(TW5864_INTR_ENABLE_L, dev->irqmask & 0xffff);
tw_writel(TW5864_INTR_ENABLE_H, (dev->irqmask >> 16));
}
static void tw5864_interrupts_disable(struct tw5864_dev *dev)
{
unsigned long flags;
spin_lock_irqsave(&dev->slock, flags);
dev->irqmask = 0;
tw5864_irqmask_apply(dev);
spin_unlock_irqrestore(&dev->slock, flags);
}
static void tw5864_timer_isr(struct tw5864_dev *dev);
static void tw5864_h264_isr(struct tw5864_dev *dev);
static irqreturn_t tw5864_isr(int irq, void *dev_id)
{
struct tw5864_dev *dev = dev_id;
u32 status;
status = tw_readl(TW5864_INTR_STATUS_L) |
tw_readl(TW5864_INTR_STATUS_H) << 16;
if (!status)
return IRQ_NONE;
tw_writel(TW5864_INTR_CLR_L, 0xffff);
tw_writel(TW5864_INTR_CLR_H, 0xffff);
if (status & TW5864_INTR_VLC_DONE)
tw5864_h264_isr(dev);
if (status & TW5864_INTR_TIMER)
tw5864_timer_isr(dev);
if (!(status & (TW5864_INTR_TIMER | TW5864_INTR_VLC_DONE))) {
dev_dbg(&dev->pci->dev, "Unknown interrupt, status 0x%08X\n",
status);
}
return IRQ_HANDLED;
}
static void tw5864_h264_isr(struct tw5864_dev *dev)
{
int channel = tw_readl(TW5864_DSP) & TW5864_DSP_ENC_CHN;
struct tw5864_input *input = &dev->inputs[channel];
int cur_frame_index, next_frame_index;
struct tw5864_h264_frame *cur_frame, *next_frame;
unsigned long flags;
spin_lock_irqsave(&dev->slock, flags);
cur_frame_index = dev->h264_buf_w_index;
next_frame_index = (cur_frame_index + 1) % H264_BUF_CNT;
cur_frame = &dev->h264_buf[cur_frame_index];
next_frame = &dev->h264_buf[next_frame_index];
if (next_frame_index != dev->h264_buf_r_index) {
cur_frame->vlc_len = tw_readl(TW5864_VLC_LENGTH) << 2;
cur_frame->checksum = tw_readl(TW5864_VLC_CRC_REG);
cur_frame->input = input;
cur_frame->timestamp = ktime_get_ns();
cur_frame->seqno = input->frame_seqno;
cur_frame->gop_seqno = input->frame_gop_seqno;
dev->h264_buf_w_index = next_frame_index;
tasklet_schedule(&dev->tasklet);
cur_frame = next_frame;
spin_lock(&input->slock);
input->frame_seqno++;
input->frame_gop_seqno++;
if (input->frame_gop_seqno >= input->gop)
input->frame_gop_seqno = 0;
spin_unlock(&input->slock);
} else {
dev_err(&dev->pci->dev,
"Skipped frame on input %d because all buffers busy\n",
channel);
}
dev->encoder_busy = 0;
spin_unlock_irqrestore(&dev->slock, flags);
tw_writel(TW5864_VLC_STREAM_BASE_ADDR, cur_frame->vlc.dma_addr);
tw_writel(TW5864_MV_STREAM_BASE_ADDR, cur_frame->mv.dma_addr);
/* Additional ack for this interrupt */
tw_writel(TW5864_VLC_DSP_INTR, 0x00000001);
tw_writel(TW5864_PCI_INTR_STATUS, TW5864_VLC_DONE_INTR);
}
static void tw5864_input_deadline_update(struct tw5864_input *input)
{
input->new_frame_deadline = jiffies + msecs_to_jiffies(1000);
}
static void tw5864_timer_isr(struct tw5864_dev *dev)
{
unsigned long flags;
int i;
int encoder_busy;
/* Additional ack for this interrupt */
tw_writel(TW5864_PCI_INTR_STATUS, TW5864_TIMER_INTR);
spin_lock_irqsave(&dev->slock, flags);
encoder_busy = dev->encoder_busy;
spin_unlock_irqrestore(&dev->slock, flags);
if (encoder_busy)
return;
/*
* Traversing inputs in round-robin fashion, starting from next to the
* last processed one
*/
for (i = 0; i < TW5864_INPUTS; i++) {
int next_input = (i + dev->next_input) % TW5864_INPUTS;
struct tw5864_input *input = &dev->inputs[next_input];
int raw_buf_id; /* id of internal buf with last raw frame */
spin_lock_irqsave(&input->slock, flags);
if (!input->enabled)
goto next;
/* Check if new raw frame is available */
raw_buf_id = tw_mask_shift_readl(TW5864_SENIF_ORG_FRM_PTR1, 0x3,
2 * input->nr);
if (input->buf_id != raw_buf_id) {
input->buf_id = raw_buf_id;
tw5864_input_deadline_update(input);
spin_unlock_irqrestore(&input->slock, flags);
spin_lock_irqsave(&dev->slock, flags);
dev->encoder_busy = 1;
dev->next_input = (next_input + 1) % TW5864_INPUTS;
spin_unlock_irqrestore(&dev->slock, flags);
tw5864_request_encoded_frame(input);
break;
}
/* No new raw frame; check if channel is stuck */
if (time_is_after_jiffies(input->new_frame_deadline)) {
/* If stuck, request new raw frames again */
tw_mask_shift_writel(TW5864_ENC_BUF_PTR_REC1, 0x3,
2 * input->nr, input->buf_id + 3);
tw5864_input_deadline_update(input);
}
next:
spin_unlock_irqrestore(&input->slock, flags);
}
}
static int tw5864_initdev(struct pci_dev *pci_dev,
const struct pci_device_id *pci_id)
{
struct tw5864_dev *dev;
int err;
dev = devm_kzalloc(&pci_dev->dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
snprintf(dev->name, sizeof(dev->name), "tw5864:%s", pci_name(pci_dev));
err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
if (err)
return err;
/* pci init */
dev->pci = pci_dev;
err = pcim_enable_device(pci_dev);
if (err) {
dev_err(&dev->pci->dev, "pcim_enable_device() failed\n");
goto unreg_v4l2;
}
pci_set_master(pci_dev);
err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32));
if (err) {
dev_err(&dev->pci->dev, "32 bit PCI DMA is not supported\n");
goto unreg_v4l2;
}
/* get mmio */
err = pcim_iomap_regions(pci_dev, BIT(0), dev->name);
if (err) {
dev_err(&dev->pci->dev, "Cannot request regions for MMIO\n");
goto unreg_v4l2;
}
dev->mmio = pcim_iomap_table(pci_dev)[0];
spin_lock_init(&dev->slock);
dev_info(&pci_dev->dev, "TW5864 hardware version: %04x\n",
tw_readl(TW5864_HW_VERSION));
dev_info(&pci_dev->dev, "TW5864 H.264 core version: %04x:%04x\n",
tw_readl(TW5864_H264REV),
tw_readl(TW5864_UNDECLARED_H264REV_PART2));
err = tw5864_video_init(dev, video_nr);
if (err)
goto unreg_v4l2;
/* get irq */
err = devm_request_irq(&pci_dev->dev, pci_dev->irq, tw5864_isr,
IRQF_SHARED, "tw5864", dev);
if (err < 0) {
dev_err(&dev->pci->dev, "can't get IRQ %d\n", pci_dev->irq);
goto fini_video;
}
dev_info(&pci_dev->dev, "Note: there are known video quality issues. For details\n");
dev_info(&pci_dev->dev, "see the comment in drivers/media/pci/tw5864/tw5864-core.c.\n");
return 0;
fini_video:
tw5864_video_fini(dev);
unreg_v4l2:
v4l2_device_unregister(&dev->v4l2_dev);
return err;
}
static void tw5864_finidev(struct pci_dev *pci_dev)
{
struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
struct tw5864_dev *dev =
container_of(v4l2_dev, struct tw5864_dev, v4l2_dev);
/* shutdown subsystems */
tw5864_interrupts_disable(dev);
/* unregister */
tw5864_video_fini(dev);
v4l2_device_unregister(&dev->v4l2_dev);
}
static struct pci_driver tw5864_pci_driver = {
.name = "tw5864",
.id_table = tw5864_pci_tbl,
.probe = tw5864_initdev,
.remove = tw5864_finidev,
};
module_pci_driver(tw5864_pci_driver);
| linux-master | drivers/media/pci/tw5864/tw5864-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* TW5864 driver - H.264 headers generation functions
*
* Copyright (C) 2016 Bluecherry, LLC <[email protected]>
*/
#include <linux/log2.h>
#include "tw5864.h"
static u8 marker[] = { 0x00, 0x00, 0x00, 0x01 };
/*
* Exponential-Golomb coding functions
*
* These functions are used for generation of H.264 bitstream headers.
*
* This code is derived from tw5864 reference driver by manufacturers, which
* itself apparently was derived from x264 project.
*/
/* Bitstream writing context */
struct bs {
u8 *buf; /* pointer to buffer beginning */
u8 *buf_end; /* pointer to buffer end */
u8 *ptr; /* pointer to current byte in buffer */
unsigned int bits_left; /* number of available bits in current byte */
};
static void bs_init(struct bs *s, void *buf, int size)
{
s->buf = buf;
s->ptr = buf;
s->buf_end = s->ptr + size;
s->bits_left = 8;
}
static int bs_len(struct bs *s)
{
return s->ptr - s->buf;
}
static void bs_write(struct bs *s, int count, u32 bits)
{
if (s->ptr >= s->buf_end - 4)
return;
while (count > 0) {
if (count < 32)
bits &= (1 << count) - 1;
if (count < s->bits_left) {
*s->ptr = (*s->ptr << count) | bits;
s->bits_left -= count;
break;
}
*s->ptr = (*s->ptr << s->bits_left) |
(bits >> (count - s->bits_left));
count -= s->bits_left;
s->ptr++;
s->bits_left = 8;
}
}
static void bs_write1(struct bs *s, u32 bit)
{
if (s->ptr < s->buf_end) {
*s->ptr <<= 1;
*s->ptr |= bit;
s->bits_left--;
if (s->bits_left == 0) {
s->ptr++;
s->bits_left = 8;
}
}
}
static void bs_write_ue(struct bs *s, u32 val)
{
if (val == 0) {
bs_write1(s, 1);
} else {
val++;
bs_write(s, 2 * fls(val) - 1, val);
}
}
static void bs_write_se(struct bs *s, int val)
{
bs_write_ue(s, val <= 0 ? -val * 2 : val * 2 - 1);
}
static void bs_rbsp_trailing(struct bs *s)
{
bs_write1(s, 1);
if (s->bits_left != 8)
bs_write(s, s->bits_left, 0x00);
}
/* H.264 headers generation functions */
static int tw5864_h264_gen_sps_rbsp(u8 *buf, size_t size, int width, int height)
{
struct bs bs, *s;
s = &bs;
bs_init(s, buf, size);
bs_write(s, 8, 0x42); /* profile_idc, baseline */
bs_write(s, 1, 1); /* constraint_set0_flag */
bs_write(s, 1, 1); /* constraint_set1_flag */
bs_write(s, 1, 0); /* constraint_set2_flag */
bs_write(s, 5, 0); /* reserved_zero_5bits */
bs_write(s, 8, 0x1e); /* level_idc */
bs_write_ue(s, 0); /* seq_parameter_set_id */
bs_write_ue(s, ilog2(MAX_GOP_SIZE) - 4); /* log2_max_frame_num_minus4 */
bs_write_ue(s, 0); /* pic_order_cnt_type */
/* log2_max_pic_order_cnt_lsb_minus4 */
bs_write_ue(s, ilog2(MAX_GOP_SIZE) - 4);
bs_write_ue(s, 1); /* num_ref_frames */
bs_write(s, 1, 0); /* gaps_in_frame_num_value_allowed_flag */
bs_write_ue(s, width / 16 - 1); /* pic_width_in_mbs_minus1 */
bs_write_ue(s, height / 16 - 1); /* pic_height_in_map_units_minus1 */
bs_write(s, 1, 1); /* frame_mbs_only_flag */
bs_write(s, 1, 0); /* direct_8x8_inference_flag */
bs_write(s, 1, 0); /* frame_cropping_flag */
bs_write(s, 1, 0); /* vui_parameters_present_flag */
bs_rbsp_trailing(s);
return bs_len(s);
}
static int tw5864_h264_gen_pps_rbsp(u8 *buf, size_t size, int qp)
{
struct bs bs, *s;
s = &bs;
bs_init(s, buf, size);
bs_write_ue(s, 0); /* pic_parameter_set_id */
bs_write_ue(s, 0); /* seq_parameter_set_id */
bs_write(s, 1, 0); /* entropy_coding_mode_flag */
bs_write(s, 1, 0); /* pic_order_present_flag */
bs_write_ue(s, 0); /* num_slice_groups_minus1 */
bs_write_ue(s, 0); /* i_num_ref_idx_l0_active_minus1 */
bs_write_ue(s, 0); /* i_num_ref_idx_l1_active_minus1 */
bs_write(s, 1, 0); /* weighted_pred_flag */
bs_write(s, 2, 0); /* weighted_bipred_idc */
bs_write_se(s, qp - 26); /* pic_init_qp_minus26 */
bs_write_se(s, qp - 26); /* pic_init_qs_minus26 */
bs_write_se(s, 0); /* chroma_qp_index_offset */
bs_write(s, 1, 0); /* deblocking_filter_control_present_flag */
bs_write(s, 1, 0); /* constrained_intra_pred_flag */
bs_write(s, 1, 0); /* redundant_pic_cnt_present_flag */
bs_rbsp_trailing(s);
return bs_len(s);
}
static int tw5864_h264_gen_slice_head(u8 *buf, size_t size,
unsigned int idr_pic_id,
unsigned int frame_gop_seqno,
int *tail_nb_bits, u8 *tail)
{
struct bs bs, *s;
int is_i_frame = frame_gop_seqno == 0;
s = &bs;
bs_init(s, buf, size);
bs_write_ue(s, 0); /* first_mb_in_slice */
bs_write_ue(s, is_i_frame ? 2 : 5); /* slice_type - I or P */
bs_write_ue(s, 0); /* pic_parameter_set_id */
bs_write(s, ilog2(MAX_GOP_SIZE), frame_gop_seqno); /* frame_num */
if (is_i_frame)
bs_write_ue(s, idr_pic_id);
/* pic_order_cnt_lsb */
bs_write(s, ilog2(MAX_GOP_SIZE), frame_gop_seqno);
if (is_i_frame) {
bs_write1(s, 0); /* no_output_of_prior_pics_flag */
bs_write1(s, 0); /* long_term_reference_flag */
} else {
bs_write1(s, 0); /* num_ref_idx_active_override_flag */
bs_write1(s, 0); /* ref_pic_list_reordering_flag_l0 */
bs_write1(s, 0); /* adaptive_ref_pic_marking_mode_flag */
}
bs_write_se(s, 0); /* slice_qp_delta */
if (s->bits_left != 8) {
*tail = ((s->ptr[0]) << s->bits_left);
*tail_nb_bits = 8 - s->bits_left;
} else {
*tail = 0;
*tail_nb_bits = 0;
}
return bs_len(s);
}
void tw5864_h264_put_stream_header(u8 **buf, size_t *space_left, int qp,
int width, int height)
{
int nal_len;
/* SPS */
memcpy(*buf, marker, sizeof(marker));
*buf += 4;
*space_left -= 4;
**buf = 0x67; /* SPS NAL header */
*buf += 1;
*space_left -= 1;
nal_len = tw5864_h264_gen_sps_rbsp(*buf, *space_left, width, height);
*buf += nal_len;
*space_left -= nal_len;
/* PPS */
memcpy(*buf, marker, sizeof(marker));
*buf += 4;
*space_left -= 4;
**buf = 0x68; /* PPS NAL header */
*buf += 1;
*space_left -= 1;
nal_len = tw5864_h264_gen_pps_rbsp(*buf, *space_left, qp);
*buf += nal_len;
*space_left -= nal_len;
}
void tw5864_h264_put_slice_header(u8 **buf, size_t *space_left,
unsigned int idr_pic_id,
unsigned int frame_gop_seqno,
int *tail_nb_bits, u8 *tail)
{
int nal_len;
memcpy(*buf, marker, sizeof(marker));
*buf += 4;
*space_left -= 4;
/* Frame NAL header */
**buf = (frame_gop_seqno == 0) ? 0x25 : 0x21;
*buf += 1;
*space_left -= 1;
nal_len = tw5864_h264_gen_slice_head(*buf, *space_left, idr_pic_id,
frame_gop_seqno, tail_nb_bits,
tail);
*buf += nal_len;
*space_left -= nal_len;
}
| linux-master | drivers/media/pci/tw5864/tw5864-h264.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* TW5864 driver - video encoding functions
*
* Copyright (C) 2016 Bluecherry, LLC <[email protected]>
*/
#include <linux/module.h>
#include <media/v4l2-common.h>
#include <media/v4l2-event.h>
#include <media/videobuf2-dma-contig.h>
#include "tw5864.h"
#include "tw5864-reg.h"
#define QUANTIZATION_TABLE_LEN 96
#define VLC_LOOKUP_TABLE_LEN 1024
static const u16 forward_quantization_table[QUANTIZATION_TABLE_LEN] = {
0x3333, 0x1f82, 0x3333, 0x1f82, 0x1f82, 0x147b, 0x1f82, 0x147b,
0x3333, 0x1f82, 0x3333, 0x1f82, 0x1f82, 0x147b, 0x1f82, 0x147b,
0x2e8c, 0x1d42, 0x2e8c, 0x1d42, 0x1d42, 0x1234, 0x1d42, 0x1234,
0x2e8c, 0x1d42, 0x2e8c, 0x1d42, 0x1d42, 0x1234, 0x1d42, 0x1234,
0x2762, 0x199a, 0x2762, 0x199a, 0x199a, 0x1062, 0x199a, 0x1062,
0x2762, 0x199a, 0x2762, 0x199a, 0x199a, 0x1062, 0x199a, 0x1062,
0x2492, 0x16c1, 0x2492, 0x16c1, 0x16c1, 0x0e3f, 0x16c1, 0x0e3f,
0x2492, 0x16c1, 0x2492, 0x16c1, 0x16c1, 0x0e3f, 0x16c1, 0x0e3f,
0x2000, 0x147b, 0x2000, 0x147b, 0x147b, 0x0d1b, 0x147b, 0x0d1b,
0x2000, 0x147b, 0x2000, 0x147b, 0x147b, 0x0d1b, 0x147b, 0x0d1b,
0x1c72, 0x11cf, 0x1c72, 0x11cf, 0x11cf, 0x0b4d, 0x11cf, 0x0b4d,
0x1c72, 0x11cf, 0x1c72, 0x11cf, 0x11cf, 0x0b4d, 0x11cf, 0x0b4d
};
static const u16 inverse_quantization_table[QUANTIZATION_TABLE_LEN] = {
0x800a, 0x800d, 0x800a, 0x800d, 0x800d, 0x8010, 0x800d, 0x8010,
0x800a, 0x800d, 0x800a, 0x800d, 0x800d, 0x8010, 0x800d, 0x8010,
0x800b, 0x800e, 0x800b, 0x800e, 0x800e, 0x8012, 0x800e, 0x8012,
0x800b, 0x800e, 0x800b, 0x800e, 0x800e, 0x8012, 0x800e, 0x8012,
0x800d, 0x8010, 0x800d, 0x8010, 0x8010, 0x8014, 0x8010, 0x8014,
0x800d, 0x8010, 0x800d, 0x8010, 0x8010, 0x8014, 0x8010, 0x8014,
0x800e, 0x8012, 0x800e, 0x8012, 0x8012, 0x8017, 0x8012, 0x8017,
0x800e, 0x8012, 0x800e, 0x8012, 0x8012, 0x8017, 0x8012, 0x8017,
0x8010, 0x8014, 0x8010, 0x8014, 0x8014, 0x8019, 0x8014, 0x8019,
0x8010, 0x8014, 0x8010, 0x8014, 0x8014, 0x8019, 0x8014, 0x8019,
0x8012, 0x8017, 0x8012, 0x8017, 0x8017, 0x801d, 0x8017, 0x801d,
0x8012, 0x8017, 0x8012, 0x8017, 0x8017, 0x801d, 0x8017, 0x801d
};
static const u16 encoder_vlc_lookup_table[VLC_LOOKUP_TABLE_LEN] = {
0x011, 0x000, 0x000, 0x000, 0x065, 0x021, 0x000, 0x000, 0x087, 0x064,
0x031, 0x000, 0x097, 0x086, 0x075, 0x053, 0x0a7, 0x096, 0x085, 0x063,
0x0b7, 0x0a6, 0x095, 0x074, 0x0df, 0x0b6, 0x0a5, 0x084, 0x0db, 0x0de,
0x0b5, 0x094, 0x0d8, 0x0da, 0x0dd, 0x0a4, 0x0ef, 0x0ee, 0x0d9, 0x0b4,
0x0eb, 0x0ea, 0x0ed, 0x0dc, 0x0ff, 0x0fe, 0x0e9, 0x0ec, 0x0fb, 0x0fa,
0x0fd, 0x0e8, 0x10f, 0x0f1, 0x0f9, 0x0fc, 0x10b, 0x10e, 0x10d, 0x0f8,
0x107, 0x10a, 0x109, 0x10c, 0x104, 0x106, 0x105, 0x108, 0x023, 0x000,
0x000, 0x000, 0x06b, 0x022, 0x000, 0x000, 0x067, 0x057, 0x033, 0x000,
0x077, 0x06a, 0x069, 0x045, 0x087, 0x066, 0x065, 0x044, 0x084, 0x076,
0x075, 0x056, 0x097, 0x086, 0x085, 0x068, 0x0bf, 0x096, 0x095, 0x064,
0x0bb, 0x0be, 0x0bd, 0x074, 0x0cf, 0x0ba, 0x0b9, 0x094, 0x0cb, 0x0ce,
0x0cd, 0x0bc, 0x0c8, 0x0ca, 0x0c9, 0x0b8, 0x0df, 0x0de, 0x0dd, 0x0cc,
0x0db, 0x0da, 0x0d9, 0x0dc, 0x0d7, 0x0eb, 0x0d6, 0x0d8, 0x0e9, 0x0e8,
0x0ea, 0x0d1, 0x0e7, 0x0e6, 0x0e5, 0x0e4, 0x04f, 0x000, 0x000, 0x000,
0x06f, 0x04e, 0x000, 0x000, 0x06b, 0x05f, 0x04d, 0x000, 0x068, 0x05c,
0x05e, 0x04c, 0x07f, 0x05a, 0x05b, 0x04b, 0x07b, 0x058, 0x059, 0x04a,
0x079, 0x06e, 0x06d, 0x049, 0x078, 0x06a, 0x069, 0x048, 0x08f, 0x07e,
0x07d, 0x05d, 0x08b, 0x08e, 0x07a, 0x06c, 0x09f, 0x08a, 0x08d, 0x07c,
0x09b, 0x09e, 0x089, 0x08c, 0x098, 0x09a, 0x09d, 0x088, 0x0ad, 0x097,
0x099, 0x09c, 0x0a9, 0x0ac, 0x0ab, 0x0aa, 0x0a5, 0x0a8, 0x0a7, 0x0a6,
0x0a1, 0x0a4, 0x0a3, 0x0a2, 0x021, 0x000, 0x000, 0x000, 0x067, 0x011,
0x000, 0x000, 0x064, 0x066, 0x031, 0x000, 0x063, 0x073, 0x072, 0x065,
0x062, 0x083, 0x082, 0x070, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x011, 0x010,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x011, 0x021, 0x020, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x023, 0x022, 0x021, 0x020, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x023, 0x022, 0x021, 0x031,
0x030, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x023, 0x022, 0x033, 0x032, 0x031, 0x030, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x023, 0x030,
0x031, 0x033, 0x032, 0x035, 0x034, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x037, 0x036, 0x035, 0x034, 0x033, 0x032,
0x031, 0x041, 0x051, 0x061, 0x071, 0x081, 0x091, 0x0a1, 0x0b1, 0x000,
0x002, 0x000, 0x0e4, 0x011, 0x0f4, 0x002, 0x024, 0x003, 0x005, 0x012,
0x034, 0x013, 0x065, 0x024, 0x013, 0x063, 0x015, 0x022, 0x075, 0x034,
0x044, 0x023, 0x023, 0x073, 0x054, 0x033, 0x033, 0x004, 0x043, 0x014,
0x011, 0x043, 0x014, 0x001, 0x025, 0x015, 0x035, 0x025, 0x064, 0x055,
0x045, 0x035, 0x074, 0x065, 0x085, 0x0d5, 0x012, 0x095, 0x055, 0x045,
0x095, 0x0e5, 0x084, 0x075, 0x022, 0x0a5, 0x094, 0x085, 0x032, 0x0b5,
0x003, 0x0c5, 0x001, 0x044, 0x0a5, 0x032, 0x0b5, 0x094, 0x0c5, 0x0a4,
0x0a4, 0x054, 0x0d5, 0x0b4, 0x0b4, 0x064, 0x0f5, 0x0f5, 0x053, 0x0d4,
0x0e5, 0x0c4, 0x105, 0x105, 0x0c4, 0x074, 0x063, 0x0e4, 0x0d4, 0x084,
0x073, 0x0f4, 0x004, 0x005, 0x000, 0x053, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x011, 0x021, 0x031, 0x030, 0x011, 0x021, 0x020, 0x000,
0x011, 0x010, 0x000, 0x000, 0x011, 0x033, 0x032, 0x043, 0x042, 0x053,
0x052, 0x063, 0x062, 0x073, 0x072, 0x083, 0x082, 0x093, 0x092, 0x091,
0x037, 0x036, 0x035, 0x034, 0x033, 0x045, 0x044, 0x043, 0x042, 0x053,
0x052, 0x063, 0x062, 0x061, 0x060, 0x000, 0x045, 0x037, 0x036, 0x035,
0x044, 0x043, 0x034, 0x033, 0x042, 0x053, 0x052, 0x061, 0x051, 0x060,
0x000, 0x000, 0x053, 0x037, 0x045, 0x044, 0x036, 0x035, 0x034, 0x043,
0x033, 0x042, 0x052, 0x051, 0x050, 0x000, 0x000, 0x000, 0x045, 0x044,
0x043, 0x037, 0x036, 0x035, 0x034, 0x033, 0x042, 0x051, 0x041, 0x050,
0x000, 0x000, 0x000, 0x000, 0x061, 0x051, 0x037, 0x036, 0x035, 0x034,
0x033, 0x032, 0x041, 0x031, 0x060, 0x000, 0x000, 0x000, 0x000, 0x000,
0x061, 0x051, 0x035, 0x034, 0x033, 0x023, 0x032, 0x041, 0x031, 0x060,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x061, 0x041, 0x051, 0x033,
0x023, 0x022, 0x032, 0x031, 0x060, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x061, 0x060, 0x041, 0x023, 0x022, 0x031, 0x021, 0x051,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x051, 0x050,
0x031, 0x023, 0x022, 0x021, 0x041, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x040, 0x041, 0x031, 0x032, 0x011, 0x033,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x040, 0x041, 0x021, 0x011, 0x031, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x030, 0x031, 0x011, 0x021,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x020, 0x021, 0x011, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x010, 0x011,
0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
0x000, 0x000, 0x000, 0x000
};
static const unsigned int lambda_lookup_table[] = {
0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020,
0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020,
0x0040, 0x0040, 0x0040, 0x0040, 0x0060, 0x0060, 0x0060, 0x0080,
0x0080, 0x0080, 0x00a0, 0x00c0, 0x00c0, 0x00e0, 0x0100, 0x0120,
0x0140, 0x0160, 0x01a0, 0x01c0, 0x0200, 0x0240, 0x0280, 0x02e0,
0x0320, 0x03a0, 0x0400, 0x0480, 0x0500, 0x05a0, 0x0660, 0x0720,
0x0800, 0x0900, 0x0a20, 0x0b60
};
static const unsigned int intra4x4_lambda3[] = {
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
2, 2, 2, 2, 3, 3, 3, 4,
4, 4, 5, 6, 6, 7, 8, 9,
10, 11, 13, 14, 16, 18, 20, 23,
25, 29, 32, 36, 40, 45, 51, 57,
64, 72, 81, 91
};
static v4l2_std_id tw5864_get_v4l2_std(enum tw5864_vid_std std);
static enum tw5864_vid_std tw5864_from_v4l2_std(v4l2_std_id v4l2_std);
static void tw5864_handle_frame_task(struct tasklet_struct *t);
static void tw5864_handle_frame(struct tw5864_h264_frame *frame);
static void tw5864_frame_interval_set(struct tw5864_input *input);
static int tw5864_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
unsigned int *num_planes, unsigned int sizes[],
struct device *alloc_ctxs[])
{
if (*num_planes)
return sizes[0] < H264_VLC_BUF_SIZE ? -EINVAL : 0;
sizes[0] = H264_VLC_BUF_SIZE;
*num_planes = 1;
return 0;
}
static void tw5864_buf_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct vb2_queue *vq = vb->vb2_queue;
struct tw5864_input *dev = vb2_get_drv_priv(vq);
struct tw5864_buf *buf = container_of(vbuf, struct tw5864_buf, vb);
unsigned long flags;
spin_lock_irqsave(&dev->slock, flags);
list_add_tail(&buf->list, &dev->active);
spin_unlock_irqrestore(&dev->slock, flags);
}
static int tw5864_input_std_get(struct tw5864_input *input,
enum tw5864_vid_std *std)
{
struct tw5864_dev *dev = input->root;
u8 std_reg = tw_indir_readb(TW5864_INDIR_VIN_E(input->nr));
*std = (std_reg & 0x70) >> 4;
if (std_reg & 0x80) {
dev_dbg(&dev->pci->dev,
"Video format detection is in progress, please wait\n");
return -EAGAIN;
}
return 0;
}
static int tw5864_enable_input(struct tw5864_input *input)
{
struct tw5864_dev *dev = input->root;
int nr = input->nr;
unsigned long flags;
int d1_width = 720;
int d1_height;
int frame_width_bus_value = 0;
int frame_height_bus_value = 0;
int reg_frame_bus = 0x1c;
int fmt_reg_value = 0;
int downscale_enabled = 0;
dev_dbg(&dev->pci->dev, "Enabling channel %d\n", nr);
input->frame_seqno = 0;
input->frame_gop_seqno = 0;
input->h264_idr_pic_id = 0;
input->reg_dsp_qp = input->qp;
input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp];
input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp];
input->reg_emu = TW5864_EMU_EN_LPF | TW5864_EMU_EN_BHOST
| TW5864_EMU_EN_SEN | TW5864_EMU_EN_ME | TW5864_EMU_EN_DDR;
input->reg_dsp = nr /* channel id */
| TW5864_DSP_CHROM_SW
| ((0xa << 8) & TW5864_DSP_MB_DELAY)
;
input->resolution = D1;
d1_height = (input->std == STD_NTSC) ? 480 : 576;
input->width = d1_width;
input->height = d1_height;
input->reg_interlacing = 0x4;
switch (input->resolution) {
case D1:
frame_width_bus_value = 0x2cf;
frame_height_bus_value = input->height - 1;
reg_frame_bus = 0x1c;
fmt_reg_value = 0;
downscale_enabled = 0;
input->reg_dsp_codec |= TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD;
input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;
input->reg_interlacing = TW5864_DI_EN | TW5864_DSP_INTER_ST;
tw_setl(TW5864_FULL_HALF_FLAG, 1 << nr);
break;
case HD1:
input->height /= 2;
input->width /= 2;
frame_width_bus_value = 0x2cf;
frame_height_bus_value = input->height * 2 - 1;
reg_frame_bus = 0x1c;
fmt_reg_value = 0;
downscale_enabled = 0;
input->reg_dsp_codec |= TW5864_HD1_MAP_MD;
input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;
tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
break;
case CIF:
input->height /= 4;
input->width /= 2;
frame_width_bus_value = 0x15f;
frame_height_bus_value = input->height * 2 - 1;
reg_frame_bus = 0x07;
fmt_reg_value = 1;
downscale_enabled = 1;
input->reg_dsp_codec |= TW5864_CIF_MAP_MD;
tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
break;
case QCIF:
input->height /= 4;
input->width /= 4;
frame_width_bus_value = 0x15f;
frame_height_bus_value = input->height * 2 - 1;
reg_frame_bus = 0x07;
fmt_reg_value = 1;
downscale_enabled = 1;
input->reg_dsp_codec |= TW5864_CIF_MAP_MD;
tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
break;
}
/* analog input width / 4 */
tw_indir_writeb(TW5864_INDIR_IN_PIC_WIDTH(nr), d1_width / 4);
tw_indir_writeb(TW5864_INDIR_IN_PIC_HEIGHT(nr), d1_height / 4);
/* output width / 4 */
tw_indir_writeb(TW5864_INDIR_OUT_PIC_WIDTH(nr), input->width / 4);
tw_indir_writeb(TW5864_INDIR_OUT_PIC_HEIGHT(nr), input->height / 4);
/*
* Crop width from 720 to 704.
* Above register settings need value 720 involved.
*/
input->width = 704;
tw_indir_writeb(TW5864_INDIR_CROP_ETC,
tw_indir_readb(TW5864_INDIR_CROP_ETC) |
TW5864_INDIR_CROP_ETC_CROP_EN);
tw_writel(TW5864_DSP_PIC_MAX_MB,
((input->width / 16) << 8) | (input->height / 16));
tw_writel(TW5864_FRAME_WIDTH_BUS_A(nr),
frame_width_bus_value);
tw_writel(TW5864_FRAME_WIDTH_BUS_B(nr),
frame_width_bus_value);
tw_writel(TW5864_FRAME_HEIGHT_BUS_A(nr),
frame_height_bus_value);
tw_writel(TW5864_FRAME_HEIGHT_BUS_B(nr),
(frame_height_bus_value + 1) / 2 - 1);
tw5864_frame_interval_set(input);
if (downscale_enabled)
tw_setl(TW5864_H264EN_CH_DNS, 1 << nr);
tw_mask_shift_writel(TW5864_H264EN_CH_FMT_REG1, 0x3, 2 * nr,
fmt_reg_value);
tw_mask_shift_writel((nr < 2
? TW5864_H264EN_RATE_MAX_LINE_REG1
: TW5864_H264EN_RATE_MAX_LINE_REG2),
0x1f, 5 * (nr % 2),
input->std == STD_NTSC ? 29 : 24);
tw_mask_shift_writel((nr < 2) ? TW5864_FRAME_BUS1 :
TW5864_FRAME_BUS2, 0xff, (nr % 2) * 8,
reg_frame_bus);
spin_lock_irqsave(&dev->slock, flags);
input->enabled = 1;
spin_unlock_irqrestore(&dev->slock, flags);
return 0;
}
void tw5864_request_encoded_frame(struct tw5864_input *input)
{
struct tw5864_dev *dev = input->root;
u32 enc_buf_id_new;
tw_setl(TW5864_DSP_CODEC, TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD);
tw_writel(TW5864_EMU, input->reg_emu);
tw_writel(TW5864_INTERLACING, input->reg_interlacing);
tw_writel(TW5864_DSP, input->reg_dsp);
tw_writel(TW5864_DSP_QP, input->reg_dsp_qp);
tw_writel(TW5864_DSP_REF_MVP_LAMBDA, input->reg_dsp_ref_mvp_lambda);
tw_writel(TW5864_DSP_I4x4_WEIGHT, input->reg_dsp_i4x4_weight);
tw_mask_shift_writel(TW5864_DSP_INTRA_MODE, TW5864_DSP_INTRA_MODE_MASK,
TW5864_DSP_INTRA_MODE_SHIFT,
TW5864_DSP_INTRA_MODE_16x16);
if (input->frame_gop_seqno == 0) {
/* Produce I-frame */
tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN);
input->h264_idr_pic_id++;
input->h264_idr_pic_id &= TW5864_DSP_REF_FRM;
} else {
/* Produce P-frame */
tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN |
TW5864_ME_EN | BIT(5) /* SRCH_OPT default */);
}
tw5864_prepare_frame_headers(input);
tw_writel(TW5864_VLC,
TW5864_VLC_PCI_SEL |
((input->tail_nb_bits + 24) << TW5864_VLC_BIT_ALIGN_SHIFT) |
input->reg_dsp_qp);
enc_buf_id_new = tw_mask_shift_readl(TW5864_ENC_BUF_PTR_REC1, 0x3,
2 * input->nr);
tw_writel(TW5864_DSP_ENC_ORG_PTR_REG,
enc_buf_id_new << TW5864_DSP_ENC_ORG_PTR_SHIFT);
tw_writel(TW5864_DSP_ENC_REC,
enc_buf_id_new << 12 | ((enc_buf_id_new + 3) & 3));
tw_writel(TW5864_SLICE, TW5864_START_NSLICE);
tw_writel(TW5864_SLICE, 0);
}
static int tw5864_disable_input(struct tw5864_input *input)
{
struct tw5864_dev *dev = input->root;
unsigned long flags;
dev_dbg(&dev->pci->dev, "Disabling channel %d\n", input->nr);
spin_lock_irqsave(&dev->slock, flags);
input->enabled = 0;
spin_unlock_irqrestore(&dev->slock, flags);
return 0;
}
static int tw5864_start_streaming(struct vb2_queue *q, unsigned int count)
{
struct tw5864_input *input = vb2_get_drv_priv(q);
int ret;
ret = tw5864_enable_input(input);
if (!ret)
return 0;
while (!list_empty(&input->active)) {
struct tw5864_buf *buf = list_entry(input->active.next,
struct tw5864_buf, list);
list_del(&buf->list);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
}
return ret;
}
static void tw5864_stop_streaming(struct vb2_queue *q)
{
unsigned long flags;
struct tw5864_input *input = vb2_get_drv_priv(q);
tw5864_disable_input(input);
spin_lock_irqsave(&input->slock, flags);
if (input->vb) {
vb2_buffer_done(&input->vb->vb.vb2_buf, VB2_BUF_STATE_ERROR);
input->vb = NULL;
}
while (!list_empty(&input->active)) {
struct tw5864_buf *buf = list_entry(input->active.next,
struct tw5864_buf, list);
list_del(&buf->list);
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&input->slock, flags);
}
static const struct vb2_ops tw5864_video_qops = {
.queue_setup = tw5864_queue_setup,
.buf_queue = tw5864_buf_queue,
.start_streaming = tw5864_start_streaming,
.stop_streaming = tw5864_stop_streaming,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
static int tw5864_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct tw5864_input *input =
container_of(ctrl->handler, struct tw5864_input, hdl);
struct tw5864_dev *dev = input->root;
unsigned long flags;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
tw_indir_writeb(TW5864_INDIR_VIN_A_BRIGHT(input->nr),
(u8)ctrl->val);
break;
case V4L2_CID_HUE:
tw_indir_writeb(TW5864_INDIR_VIN_7_HUE(input->nr),
(u8)ctrl->val);
break;
case V4L2_CID_CONTRAST:
tw_indir_writeb(TW5864_INDIR_VIN_9_CNTRST(input->nr),
(u8)ctrl->val);
break;
case V4L2_CID_SATURATION:
tw_indir_writeb(TW5864_INDIR_VIN_B_SAT_U(input->nr),
(u8)ctrl->val);
tw_indir_writeb(TW5864_INDIR_VIN_C_SAT_V(input->nr),
(u8)ctrl->val);
break;
case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
input->gop = ctrl->val;
return 0;
case V4L2_CID_MPEG_VIDEO_H264_MIN_QP:
spin_lock_irqsave(&input->slock, flags);
input->qp = ctrl->val;
input->reg_dsp_qp = input->qp;
input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp];
input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp];
spin_unlock_irqrestore(&input->slock, flags);
return 0;
case V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD:
memset(input->md_threshold_grid_values, ctrl->val,
sizeof(input->md_threshold_grid_values));
return 0;
case V4L2_CID_DETECT_MD_MODE:
return 0;
case V4L2_CID_DETECT_MD_THRESHOLD_GRID:
/* input->md_threshold_grid_ctrl->p_new.p_u16 contains data */
memcpy(input->md_threshold_grid_values,
input->md_threshold_grid_ctrl->p_new.p_u16,
sizeof(input->md_threshold_grid_values));
return 0;
}
return 0;
}
static int tw5864_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct tw5864_input *input = video_drvdata(file);
f->fmt.pix.width = 704;
switch (input->std) {
default:
WARN_ON_ONCE(1);
return -EINVAL;
case STD_NTSC:
f->fmt.pix.height = 480;
break;
case STD_PAL:
case STD_SECAM:
f->fmt.pix.height = 576;
break;
}
f->fmt.pix.field = V4L2_FIELD_INTERLACED;
f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
f->fmt.pix.sizeimage = H264_VLC_BUF_SIZE;
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
return 0;
}
static int tw5864_enum_input(struct file *file, void *priv,
struct v4l2_input *i)
{
struct tw5864_input *input = video_drvdata(file);
struct tw5864_dev *dev = input->root;
u8 indir_0x000 = tw_indir_readb(TW5864_INDIR_VIN_0(input->nr));
u8 indir_0x00d = tw_indir_readb(TW5864_INDIR_VIN_D(input->nr));
u8 v1 = indir_0x000;
u8 v2 = indir_0x00d;
if (i->index)
return -EINVAL;
i->type = V4L2_INPUT_TYPE_CAMERA;
snprintf(i->name, sizeof(i->name), "Encoder %d", input->nr);
i->std = TW5864_NORMS;
if (v1 & (1 << 7))
i->status |= V4L2_IN_ST_NO_SYNC;
if (!(v1 & (1 << 6)))
i->status |= V4L2_IN_ST_NO_H_LOCK;
if (v1 & (1 << 2))
i->status |= V4L2_IN_ST_NO_SIGNAL;
if (v1 & (1 << 1))
i->status |= V4L2_IN_ST_NO_COLOR;
if (v2 & (1 << 2))
i->status |= V4L2_IN_ST_MACROVISION;
return 0;
}
static int tw5864_g_input(struct file *file, void *priv, unsigned int *i)
{
*i = 0;
return 0;
}
static int tw5864_s_input(struct file *file, void *priv, unsigned int i)
{
if (i)
return -EINVAL;
return 0;
}
static int tw5864_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
struct tw5864_input *input = video_drvdata(file);
strscpy(cap->driver, "tw5864", sizeof(cap->driver));
snprintf(cap->card, sizeof(cap->card), "TW5864 Encoder %d",
input->nr);
return 0;
}
static int tw5864_querystd(struct file *file, void *priv, v4l2_std_id *std)
{
struct tw5864_input *input = video_drvdata(file);
enum tw5864_vid_std tw_std;
int ret;
ret = tw5864_input_std_get(input, &tw_std);
if (ret)
return ret;
*std = tw5864_get_v4l2_std(tw_std);
return 0;
}
static int tw5864_g_std(struct file *file, void *priv, v4l2_std_id *std)
{
struct tw5864_input *input = video_drvdata(file);
*std = input->v4l2_std;
return 0;
}
static int tw5864_s_std(struct file *file, void *priv, v4l2_std_id std)
{
struct tw5864_input *input = video_drvdata(file);
struct tw5864_dev *dev = input->root;
input->v4l2_std = std;
input->std = tw5864_from_v4l2_std(std);
tw_indir_writeb(TW5864_INDIR_VIN_E(input->nr), input->std);
return 0;
}
static int tw5864_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
if (f->index)
return -EINVAL;
f->pixelformat = V4L2_PIX_FMT_H264;
return 0;
}
static int tw5864_subscribe_event(struct v4l2_fh *fh,
const struct v4l2_event_subscription *sub)
{
switch (sub->type) {
case V4L2_EVENT_MOTION_DET:
/*
* Allow for up to 30 events (1 second for NTSC) to be stored.
*/
return v4l2_event_subscribe(fh, sub, 30, NULL);
default:
return v4l2_ctrl_subscribe_event(fh, sub);
}
}
static void tw5864_frame_interval_set(struct tw5864_input *input)
{
/*
* This register value seems to follow such approach: In each second
* interval, when processing Nth frame, it checks Nth bit of register
* value and, if the bit is 1, it processes the frame, otherwise the
* frame is discarded.
* So unary representation would work, but more or less equal gaps
* between the frames should be preserved.
*
* For 1 FPS - 0x00000001
* 00000000 00000000 00000000 00000001
*
* For max FPS - set all 25/30 lower bits:
* 00111111 11111111 11111111 11111111 (NTSC)
* 00000001 11111111 11111111 11111111 (PAL)
*
* For half of max FPS - use such pattern:
* 00010101 01010101 01010101 01010101 (NTSC)
* 00000001 01010101 01010101 01010101 (PAL)
*
* Et cetera.
*
* The value supplied to hardware is capped by mask of 25/30 lower bits.
*/
struct tw5864_dev *dev = input->root;
u32 unary_framerate = 0;
int shift = 0;
int std_max_fps = input->std == STD_NTSC ? 30 : 25;
for (shift = 0; shift < std_max_fps; shift += input->frame_interval)
unary_framerate |= 0x00000001 << shift;
tw_writel(TW5864_H264EN_RATE_CNTL_LO_WORD(input->nr, 0),
unary_framerate >> 16);
tw_writel(TW5864_H264EN_RATE_CNTL_HI_WORD(input->nr, 0),
unary_framerate & 0xffff);
}
static int tw5864_frameinterval_get(struct tw5864_input *input,
struct v4l2_fract *frameinterval)
{
struct tw5864_dev *dev = input->root;
switch (input->std) {
case STD_NTSC:
frameinterval->numerator = 1001;
frameinterval->denominator = 30000;
break;
case STD_PAL:
case STD_SECAM:
frameinterval->numerator = 1;
frameinterval->denominator = 25;
break;
default:
dev_warn(&dev->pci->dev, "tw5864_frameinterval_get requested for unknown std %d\n",
input->std);
return -EINVAL;
}
return 0;
}
static int tw5864_enum_framesizes(struct file *file, void *priv,
struct v4l2_frmsizeenum *fsize)
{
struct tw5864_input *input = video_drvdata(file);
if (fsize->index > 0)
return -EINVAL;
if (fsize->pixel_format != V4L2_PIX_FMT_H264)
return -EINVAL;
fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
fsize->discrete.width = 704;
fsize->discrete.height = input->std == STD_NTSC ? 480 : 576;
return 0;
}
static int tw5864_enum_frameintervals(struct file *file, void *priv,
struct v4l2_frmivalenum *fintv)
{
struct tw5864_input *input = video_drvdata(file);
struct v4l2_fract frameinterval;
int std_max_fps = input->std == STD_NTSC ? 30 : 25;
struct v4l2_frmsizeenum fsize = { .index = fintv->index,
.pixel_format = fintv->pixel_format };
int ret;
ret = tw5864_enum_framesizes(file, priv, &fsize);
if (ret)
return ret;
if (fintv->width != fsize.discrete.width ||
fintv->height != fsize.discrete.height)
return -EINVAL;
fintv->type = V4L2_FRMIVAL_TYPE_STEPWISE;
ret = tw5864_frameinterval_get(input, &frameinterval);
if (ret)
return ret;
fintv->stepwise.step = frameinterval;
fintv->stepwise.min = frameinterval;
fintv->stepwise.max = frameinterval;
fintv->stepwise.max.numerator *= std_max_fps;
return ret;
}
static int tw5864_g_parm(struct file *file, void *priv,
struct v4l2_streamparm *sp)
{
struct tw5864_input *input = video_drvdata(file);
struct v4l2_captureparm *cp = &sp->parm.capture;
int ret;
cp->capability = V4L2_CAP_TIMEPERFRAME;
ret = tw5864_frameinterval_get(input, &cp->timeperframe);
if (ret)
return ret;
cp->timeperframe.numerator *= input->frame_interval;
cp->capturemode = 0;
cp->readbuffers = 2;
return ret;
}
static int tw5864_s_parm(struct file *file, void *priv,
struct v4l2_streamparm *sp)
{
struct tw5864_input *input = video_drvdata(file);
struct v4l2_fract *t = &sp->parm.capture.timeperframe;
struct v4l2_fract time_base;
int ret;
ret = tw5864_frameinterval_get(input, &time_base);
if (ret)
return ret;
if (!t->numerator || !t->denominator) {
t->numerator = time_base.numerator * input->frame_interval;
t->denominator = time_base.denominator;
} else if (t->denominator != time_base.denominator) {
t->numerator = t->numerator * time_base.denominator /
t->denominator;
t->denominator = time_base.denominator;
}
input->frame_interval = t->numerator / time_base.numerator;
if (input->frame_interval < 1)
input->frame_interval = 1;
tw5864_frame_interval_set(input);
return tw5864_g_parm(file, priv, sp);
}
static const struct v4l2_ctrl_ops tw5864_ctrl_ops = {
.s_ctrl = tw5864_s_ctrl,
};
static const struct v4l2_file_operations video_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.release = vb2_fop_release,
.read = vb2_fop_read,
.poll = vb2_fop_poll,
.mmap = vb2_fop_mmap,
.unlocked_ioctl = video_ioctl2,
};
#ifdef CONFIG_VIDEO_ADV_DEBUG
#define INDIR_SPACE_MAP_SHIFT 0x100000
static int tw5864_g_reg(struct file *file, void *fh,
struct v4l2_dbg_register *reg)
{
struct tw5864_input *input = video_drvdata(file);
struct tw5864_dev *dev = input->root;
if (reg->reg < INDIR_SPACE_MAP_SHIFT) {
if (reg->reg > 0x87fff)
return -EINVAL;
reg->size = 4;
reg->val = tw_readl(reg->reg);
} else {
__u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT;
if (indir_addr > 0xefe)
return -EINVAL;
reg->size = 1;
reg->val = tw_indir_readb(reg->reg);
}
return 0;
}
static int tw5864_s_reg(struct file *file, void *fh,
const struct v4l2_dbg_register *reg)
{
struct tw5864_input *input = video_drvdata(file);
struct tw5864_dev *dev = input->root;
if (reg->reg < INDIR_SPACE_MAP_SHIFT) {
if (reg->reg > 0x87fff)
return -EINVAL;
tw_writel(reg->reg, reg->val);
} else {
__u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT;
if (indir_addr > 0xefe)
return -EINVAL;
tw_indir_writeb(reg->reg, reg->val);
}
return 0;
}
#endif
static const struct v4l2_ioctl_ops video_ioctl_ops = {
.vidioc_querycap = tw5864_querycap,
.vidioc_enum_fmt_vid_cap = tw5864_enum_fmt_vid_cap,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_create_bufs = vb2_ioctl_create_bufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_expbuf = vb2_ioctl_expbuf,
.vidioc_querystd = tw5864_querystd,
.vidioc_s_std = tw5864_s_std,
.vidioc_g_std = tw5864_g_std,
.vidioc_enum_input = tw5864_enum_input,
.vidioc_g_input = tw5864_g_input,
.vidioc_s_input = tw5864_s_input,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_try_fmt_vid_cap = tw5864_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = tw5864_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = tw5864_fmt_vid_cap,
.vidioc_log_status = v4l2_ctrl_log_status,
.vidioc_subscribe_event = tw5864_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
.vidioc_enum_framesizes = tw5864_enum_framesizes,
.vidioc_enum_frameintervals = tw5864_enum_frameintervals,
.vidioc_s_parm = tw5864_s_parm,
.vidioc_g_parm = tw5864_g_parm,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.vidioc_g_register = tw5864_g_reg,
.vidioc_s_register = tw5864_s_reg,
#endif
};
static const struct video_device tw5864_video_template = {
.name = "tw5864_video",
.fops = &video_fops,
.ioctl_ops = &video_ioctl_ops,
.release = video_device_release_empty,
.tvnorms = TW5864_NORMS,
.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
V4L2_CAP_STREAMING,
};
/* Motion Detection Threshold matrix */
static const struct v4l2_ctrl_config tw5864_md_thresholds = {
.ops = &tw5864_ctrl_ops,
.id = V4L2_CID_DETECT_MD_THRESHOLD_GRID,
.dims = {MD_CELLS_HOR, MD_CELLS_VERT},
.def = 14,
/* See tw5864_md_metric_from_mvd() */
.max = 2 * 0x0f,
.step = 1,
};
static int tw5864_video_input_init(struct tw5864_input *dev, int video_nr);
static void tw5864_video_input_fini(struct tw5864_input *dev);
static void tw5864_encoder_tables_upload(struct tw5864_dev *dev);
int tw5864_video_init(struct tw5864_dev *dev, int *video_nr)
{
int i;
int ret;
unsigned long flags;
int last_dma_allocated = -1;
int last_input_nr_registered = -1;
for (i = 0; i < H264_BUF_CNT; i++) {
struct tw5864_h264_frame *frame = &dev->h264_buf[i];
frame->vlc.addr = dma_alloc_coherent(&dev->pci->dev,
H264_VLC_BUF_SIZE,
&frame->vlc.dma_addr,
GFP_KERNEL | GFP_DMA32);
if (!frame->vlc.addr) {
dev_err(&dev->pci->dev, "dma alloc fail\n");
ret = -ENOMEM;
goto free_dma;
}
frame->mv.addr = dma_alloc_coherent(&dev->pci->dev,
H264_MV_BUF_SIZE,
&frame->mv.dma_addr,
GFP_KERNEL | GFP_DMA32);
if (!frame->mv.addr) {
dev_err(&dev->pci->dev, "dma alloc fail\n");
ret = -ENOMEM;
dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
frame->vlc.addr, frame->vlc.dma_addr);
goto free_dma;
}
last_dma_allocated = i;
}
tw5864_encoder_tables_upload(dev);
/* Picture is distorted without this block */
/* use falling edge to sample 54M to 108M */
tw_indir_writeb(TW5864_INDIR_VD_108_POL, TW5864_INDIR_VD_108_POL_BOTH);
tw_indir_writeb(TW5864_INDIR_CLK0_SEL, 0x00);
tw_indir_writeb(TW5864_INDIR_DDRA_DLL_DQS_SEL0, 0x02);
tw_indir_writeb(TW5864_INDIR_DDRA_DLL_DQS_SEL1, 0x02);
tw_indir_writeb(TW5864_INDIR_DDRA_DLL_CLK90_SEL, 0x02);
tw_indir_writeb(TW5864_INDIR_DDRB_DLL_DQS_SEL0, 0x02);
tw_indir_writeb(TW5864_INDIR_DDRB_DLL_DQS_SEL1, 0x02);
tw_indir_writeb(TW5864_INDIR_DDRB_DLL_CLK90_SEL, 0x02);
/* video input reset */
tw_indir_writeb(TW5864_INDIR_RESET, 0);
tw_indir_writeb(TW5864_INDIR_RESET, TW5864_INDIR_RESET_VD |
TW5864_INDIR_RESET_DLL | TW5864_INDIR_RESET_MUX_CORE);
msleep(20);
/*
* Select Part A mode for all channels.
* tw_setl instead of tw_clearl for Part B mode.
*
* I guess "Part B" is primarily for downscaled version of same channel
* which goes in Part A of same bus
*/
tw_writel(TW5864_FULL_HALF_MODE_SEL, 0);
tw_indir_writeb(TW5864_INDIR_PV_VD_CK_POL,
TW5864_INDIR_PV_VD_CK_POL_VD(0) |
TW5864_INDIR_PV_VD_CK_POL_VD(1) |
TW5864_INDIR_PV_VD_CK_POL_VD(2) |
TW5864_INDIR_PV_VD_CK_POL_VD(3));
spin_lock_irqsave(&dev->slock, flags);
dev->encoder_busy = 0;
dev->h264_buf_r_index = 0;
dev->h264_buf_w_index = 0;
tw_writel(TW5864_VLC_STREAM_BASE_ADDR,
dev->h264_buf[dev->h264_buf_w_index].vlc.dma_addr);
tw_writel(TW5864_MV_STREAM_BASE_ADDR,
dev->h264_buf[dev->h264_buf_w_index].mv.dma_addr);
spin_unlock_irqrestore(&dev->slock, flags);
tw_writel(TW5864_SEN_EN_CH, 0x000f);
tw_writel(TW5864_H264EN_CH_EN, 0x000f);
tw_writel(TW5864_H264EN_BUS0_MAP, 0x00000000);
tw_writel(TW5864_H264EN_BUS1_MAP, 0x00001111);
tw_writel(TW5864_H264EN_BUS2_MAP, 0x00002222);
tw_writel(TW5864_H264EN_BUS3_MAP, 0x00003333);
/*
* Quote from Intersil (manufacturer):
* 0x0038 is managed by HW, and by default it won't pass the pointer set
* at 0x0010. So if you don't do encoding, 0x0038 should stay at '3'
* (with 4 frames in buffer). If you encode one frame and then move
* 0x0010 to '1' for example, HW will take one more frame and set it to
* buffer #0, and then you should see 0x0038 is set to '0'. There is
* only one HW encoder engine, so 4 channels cannot get encoded
* simultaneously. But each channel does have its own buffer (for
* original frames and reconstructed frames). So there is no problem to
* manage encoding for 4 channels at same time and no need to force
* I-frames in switching channels.
* End of quote.
*
* If we set 0x0010 (TW5864_ENC_BUF_PTR_REC1) to 0 (for any channel), we
* have no "rolling" (until we change this value).
* If we set 0x0010 (TW5864_ENC_BUF_PTR_REC1) to 0x3, it starts to roll
* continuously together with 0x0038.
*/
tw_writel(TW5864_ENC_BUF_PTR_REC1, 0x00ff);
tw_writel(TW5864_PCI_INTTM_SCALE, 0);
tw_writel(TW5864_INTERLACING, TW5864_DI_EN);
tw_writel(TW5864_MASTER_ENB_REG, TW5864_PCI_VLC_INTR_ENB);
tw_writel(TW5864_PCI_INTR_CTL,
TW5864_TIMER_INTR_ENB | TW5864_PCI_MAST_ENB |
TW5864_MVD_VLC_MAST_ENB);
dev->irqmask |= TW5864_INTR_VLC_DONE | TW5864_INTR_TIMER;
tw5864_irqmask_apply(dev);
tasklet_setup(&dev->tasklet, tw5864_handle_frame_task);
for (i = 0; i < TW5864_INPUTS; i++) {
dev->inputs[i].root = dev;
dev->inputs[i].nr = i;
ret = tw5864_video_input_init(&dev->inputs[i], video_nr[i]);
if (ret)
goto fini_video_inputs;
last_input_nr_registered = i;
}
return 0;
fini_video_inputs:
for (i = last_input_nr_registered; i >= 0; i--)
tw5864_video_input_fini(&dev->inputs[i]);
tasklet_kill(&dev->tasklet);
free_dma:
for (i = last_dma_allocated; i >= 0; i--) {
dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
dev->h264_buf[i].vlc.addr,
dev->h264_buf[i].vlc.dma_addr);
dma_free_coherent(&dev->pci->dev, H264_MV_BUF_SIZE,
dev->h264_buf[i].mv.addr,
dev->h264_buf[i].mv.dma_addr);
}
return ret;
}
static int tw5864_video_input_init(struct tw5864_input *input, int video_nr)
{
struct tw5864_dev *dev = input->root;
int ret;
struct v4l2_ctrl_handler *hdl = &input->hdl;
mutex_init(&input->lock);
spin_lock_init(&input->slock);
/* setup video buffers queue */
INIT_LIST_HEAD(&input->active);
input->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
input->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
input->vidq.io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
input->vidq.ops = &tw5864_video_qops;
input->vidq.mem_ops = &vb2_dma_contig_memops;
input->vidq.drv_priv = input;
input->vidq.gfp_flags = 0;
input->vidq.buf_struct_size = sizeof(struct tw5864_buf);
input->vidq.lock = &input->lock;
input->vidq.min_buffers_needed = 2;
input->vidq.dev = &input->root->pci->dev;
ret = vb2_queue_init(&input->vidq);
if (ret)
goto free_mutex;
input->vdev = tw5864_video_template;
input->vdev.v4l2_dev = &input->root->v4l2_dev;
input->vdev.lock = &input->lock;
input->vdev.queue = &input->vidq;
video_set_drvdata(&input->vdev, input);
/* Initialize the device control structures */
v4l2_ctrl_handler_init(hdl, 6);
v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
V4L2_CID_CONTRAST, 0, 255, 1, 100);
v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
V4L2_CID_SATURATION, 0, 255, 1, 128);
v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, V4L2_CID_HUE, -128, 127, 1, 0);
v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, V4L2_CID_MPEG_VIDEO_GOP_SIZE,
1, MAX_GOP_SIZE, 1, GOP_SIZE);
v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_MIN_QP, 28, 51, 1, QP_VALUE);
v4l2_ctrl_new_std_menu(hdl, &tw5864_ctrl_ops,
V4L2_CID_DETECT_MD_MODE,
V4L2_DETECT_MD_MODE_THRESHOLD_GRID, 0,
V4L2_DETECT_MD_MODE_DISABLED);
v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD,
tw5864_md_thresholds.min, tw5864_md_thresholds.max,
tw5864_md_thresholds.step, tw5864_md_thresholds.def);
input->md_threshold_grid_ctrl =
v4l2_ctrl_new_custom(hdl, &tw5864_md_thresholds, NULL);
if (hdl->error) {
ret = hdl->error;
goto free_v4l2_hdl;
}
input->vdev.ctrl_handler = hdl;
v4l2_ctrl_handler_setup(hdl);
input->qp = QP_VALUE;
input->gop = GOP_SIZE;
input->frame_interval = 1;
ret = video_register_device(&input->vdev, VFL_TYPE_VIDEO, video_nr);
if (ret)
goto free_v4l2_hdl;
dev_info(&input->root->pci->dev, "Registered video device %s\n",
video_device_node_name(&input->vdev));
/*
* Set default video standard. Doesn't matter which, the detected value
* will be found out by VIDIOC_QUERYSTD handler.
*/
input->v4l2_std = V4L2_STD_NTSC_M;
input->std = STD_NTSC;
tw_indir_writeb(TW5864_INDIR_VIN_E(video_nr), 0x07);
/* to initiate auto format recognition */
tw_indir_writeb(TW5864_INDIR_VIN_F(video_nr), 0xff);
return 0;
free_v4l2_hdl:
v4l2_ctrl_handler_free(hdl);
free_mutex:
mutex_destroy(&input->lock);
return ret;
}
static void tw5864_video_input_fini(struct tw5864_input *dev)
{
vb2_video_unregister_device(&dev->vdev);
v4l2_ctrl_handler_free(&dev->hdl);
}
void tw5864_video_fini(struct tw5864_dev *dev)
{
int i;
tasklet_kill(&dev->tasklet);
for (i = 0; i < TW5864_INPUTS; i++)
tw5864_video_input_fini(&dev->inputs[i]);
for (i = 0; i < H264_BUF_CNT; i++) {
dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
dev->h264_buf[i].vlc.addr,
dev->h264_buf[i].vlc.dma_addr);
dma_free_coherent(&dev->pci->dev, H264_MV_BUF_SIZE,
dev->h264_buf[i].mv.addr,
dev->h264_buf[i].mv.dma_addr);
}
}
void tw5864_prepare_frame_headers(struct tw5864_input *input)
{
struct tw5864_buf *vb = input->vb;
u8 *dst;
size_t dst_space;
unsigned long flags;
if (!vb) {
spin_lock_irqsave(&input->slock, flags);
if (list_empty(&input->active)) {
spin_unlock_irqrestore(&input->slock, flags);
input->vb = NULL;
return;
}
vb = list_first_entry(&input->active, struct tw5864_buf, list);
list_del(&vb->list);
spin_unlock_irqrestore(&input->slock, flags);
}
dst = vb2_plane_vaddr(&vb->vb.vb2_buf, 0);
dst_space = vb2_plane_size(&vb->vb.vb2_buf, 0);
/*
* Low-level bitstream writing functions don't have a fine way to say
* correctly that supplied buffer is too small. So we just check there
* and warn, and don't care at lower level.
* Currently all headers take below 32 bytes.
* The buffer is supposed to have plenty of free space at this point,
* anyway.
*/
if (WARN_ON_ONCE(dst_space < 128))
return;
/*
* Generate H264 headers:
* If this is first frame, put SPS and PPS
*/
if (input->frame_gop_seqno == 0)
tw5864_h264_put_stream_header(&dst, &dst_space, input->qp,
input->width, input->height);
/* Put slice header */
tw5864_h264_put_slice_header(&dst, &dst_space, input->h264_idr_pic_id,
input->frame_gop_seqno,
&input->tail_nb_bits, &input->tail);
input->vb = vb;
input->buf_cur_ptr = dst;
input->buf_cur_space_left = dst_space;
}
/*
* Returns heuristic motion detection metric value from known components of
* hardware-provided Motion Vector Data.
*/
static unsigned int tw5864_md_metric_from_mvd(u32 mvd)
{
/*
* Format of motion vector data exposed by tw5864, according to
* manufacturer:
* mv_x 10 bits
* mv_y 10 bits
* non_zero_members 8 bits
* mb_type 3 bits
* reserved 1 bit
*
* non_zero_members: number of non-zero residuals in each macro block
* after quantization
*
* unsigned int reserved = mvd >> 31;
* unsigned int mb_type = (mvd >> 28) & 0x7;
* unsigned int non_zero_members = (mvd >> 20) & 0xff;
*/
unsigned int mv_y = (mvd >> 10) & 0x3ff;
unsigned int mv_x = mvd & 0x3ff;
/* heuristic: */
mv_x &= 0x0f;
mv_y &= 0x0f;
return mv_y + mv_x;
}
static int tw5864_is_motion_triggered(struct tw5864_h264_frame *frame)
{
struct tw5864_input *input = frame->input;
u32 *mv = (u32 *)frame->mv.addr;
int i;
int detected = 0;
for (i = 0; i < MD_CELLS; i++) {
const u16 thresh = input->md_threshold_grid_values[i];
const unsigned int metric = tw5864_md_metric_from_mvd(mv[i]);
if (metric > thresh)
detected = 1;
if (detected)
break;
}
return detected;
}
static void tw5864_handle_frame_task(struct tasklet_struct *t)
{
struct tw5864_dev *dev = from_tasklet(dev, t, tasklet);
unsigned long flags;
int batch_size = H264_BUF_CNT;
spin_lock_irqsave(&dev->slock, flags);
while (dev->h264_buf_r_index != dev->h264_buf_w_index && batch_size--) {
struct tw5864_h264_frame *frame =
&dev->h264_buf[dev->h264_buf_r_index];
spin_unlock_irqrestore(&dev->slock, flags);
dma_sync_single_for_cpu(&dev->pci->dev, frame->vlc.dma_addr,
H264_VLC_BUF_SIZE, DMA_FROM_DEVICE);
dma_sync_single_for_cpu(&dev->pci->dev, frame->mv.dma_addr,
H264_MV_BUF_SIZE, DMA_FROM_DEVICE);
tw5864_handle_frame(frame);
dma_sync_single_for_device(&dev->pci->dev, frame->vlc.dma_addr,
H264_VLC_BUF_SIZE, DMA_FROM_DEVICE);
dma_sync_single_for_device(&dev->pci->dev, frame->mv.dma_addr,
H264_MV_BUF_SIZE, DMA_FROM_DEVICE);
spin_lock_irqsave(&dev->slock, flags);
dev->h264_buf_r_index++;
dev->h264_buf_r_index %= H264_BUF_CNT;
}
spin_unlock_irqrestore(&dev->slock, flags);
}
#ifdef DEBUG
static u32 tw5864_vlc_checksum(u32 *data, int len)
{
u32 val, count_len = len;
val = *data++;
while (((count_len >> 2) - 1) > 0) {
val ^= *data++;
count_len -= 4;
}
val ^= htonl((len >> 2));
return val;
}
#endif
static void tw5864_handle_frame(struct tw5864_h264_frame *frame)
{
#define SKIP_VLCBUF_BYTES 3
struct tw5864_input *input = frame->input;
struct tw5864_dev *dev = input->root;
struct tw5864_buf *vb;
struct vb2_v4l2_buffer *v4l2_buf;
int frame_len = frame->vlc_len - SKIP_VLCBUF_BYTES;
u8 *dst = input->buf_cur_ptr;
u8 tail_mask, vlc_mask = 0;
int i;
u8 vlc_first_byte = ((u8 *)(frame->vlc.addr + SKIP_VLCBUF_BYTES))[0];
unsigned long flags;
int zero_run;
u8 *src;
u8 *src_end;
#ifdef DEBUG
if (frame->checksum !=
tw5864_vlc_checksum((u32 *)frame->vlc.addr, frame_len))
dev_err(&dev->pci->dev,
"Checksum of encoded frame doesn't match!\n");
#endif
spin_lock_irqsave(&input->slock, flags);
vb = input->vb;
input->vb = NULL;
spin_unlock_irqrestore(&input->slock, flags);
if (!vb) { /* Gone because of disabling */
dev_dbg(&dev->pci->dev, "vb is empty, dropping frame\n");
return;
}
v4l2_buf = to_vb2_v4l2_buffer(&vb->vb.vb2_buf);
/*
* Check for space.
* Mind the overhead of startcode emulation prevention.
*/
if (input->buf_cur_space_left < frame_len * 5 / 4) {
dev_err_once(&dev->pci->dev,
"Left space in vb2 buffer, %d bytes, is less than considered safely enough to put frame of length %d. Dropping this frame.\n",
input->buf_cur_space_left, frame_len);
return;
}
for (i = 0; i < 8 - input->tail_nb_bits; i++)
vlc_mask |= 1 << i;
tail_mask = (~vlc_mask) & 0xff;
dst[0] = (input->tail & tail_mask) | (vlc_first_byte & vlc_mask);
frame_len--;
dst++;
/* H.264 startcode emulation prevention */
src = frame->vlc.addr + SKIP_VLCBUF_BYTES + 1;
src_end = src + frame_len;
zero_run = 0;
for (; src < src_end; src++) {
if (zero_run < 2) {
if (*src == 0)
++zero_run;
else
zero_run = 0;
} else {
if ((*src & ~0x03) == 0)
*dst++ = 0x03;
zero_run = *src == 0;
}
*dst++ = *src;
}
vb2_set_plane_payload(&vb->vb.vb2_buf, 0,
dst - (u8 *)vb2_plane_vaddr(&vb->vb.vb2_buf, 0));
vb->vb.vb2_buf.timestamp = frame->timestamp;
v4l2_buf->field = V4L2_FIELD_INTERLACED;
v4l2_buf->sequence = frame->seqno;
/* Check for motion flags */
if (frame->gop_seqno /* P-frame */ &&
tw5864_is_motion_triggered(frame)) {
struct v4l2_event ev = {
.type = V4L2_EVENT_MOTION_DET,
.u.motion_det = {
.flags = V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ,
.frame_sequence = v4l2_buf->sequence,
},
};
v4l2_event_queue(&input->vdev, &ev);
}
vb2_buffer_done(&vb->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
static v4l2_std_id tw5864_get_v4l2_std(enum tw5864_vid_std std)
{
switch (std) {
case STD_NTSC: return V4L2_STD_NTSC_M;
case STD_PAL: return V4L2_STD_PAL_B;
case STD_SECAM: return V4L2_STD_SECAM_B;
case STD_NTSC443: return V4L2_STD_NTSC_443;
case STD_PAL_M: return V4L2_STD_PAL_M;
case STD_PAL_CN: return V4L2_STD_PAL_Nc;
case STD_PAL_60: return V4L2_STD_PAL_60;
case STD_INVALID: return V4L2_STD_UNKNOWN;
}
return 0;
}
static enum tw5864_vid_std tw5864_from_v4l2_std(v4l2_std_id v4l2_std)
{
if (v4l2_std & V4L2_STD_NTSC_M)
return STD_NTSC;
if (v4l2_std & V4L2_STD_PAL_B)
return STD_PAL;
if (v4l2_std & V4L2_STD_SECAM_B)
return STD_SECAM;
if (v4l2_std & V4L2_STD_NTSC_443)
return STD_NTSC443;
if (v4l2_std & V4L2_STD_PAL_M)
return STD_PAL_M;
if (v4l2_std & V4L2_STD_PAL_Nc)
return STD_PAL_CN;
if (v4l2_std & V4L2_STD_PAL_60)
return STD_PAL_60;
return STD_INVALID;
}
static void tw5864_encoder_tables_upload(struct tw5864_dev *dev)
{
int i;
tw_writel(TW5864_VLC_RD, 0x1);
for (i = 0; i < VLC_LOOKUP_TABLE_LEN; i++) {
tw_writel((TW5864_VLC_STREAM_MEM_START + i * 4),
encoder_vlc_lookup_table[i]);
}
tw_writel(TW5864_VLC_RD, 0x0);
for (i = 0; i < QUANTIZATION_TABLE_LEN; i++) {
tw_writel((TW5864_QUAN_TAB + i * 4),
forward_quantization_table[i]);
}
for (i = 0; i < QUANTIZATION_TABLE_LEN; i++) {
tw_writel((TW5864_QUAN_TAB + i * 4),
inverse_quantization_table[i]);
}
}
| linux-master | drivers/media/pci/tw5864/tw5864-video.c |
// SPDX-License-Identifier: GPL-2.0
#include "tw5864.h"
void tw5864_indir_writeb(struct tw5864_dev *dev, u16 addr, u8 data)
{
int retries = 30000;
while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries)
;
if (!retries)
dev_err(&dev->pci->dev,
"tw_indir_writel() retries exhausted before writing\n");
tw_writel(TW5864_IND_DATA, data);
tw_writel(TW5864_IND_CTL, addr << 2 | TW5864_RW | TW5864_ENABLE);
}
u8 tw5864_indir_readb(struct tw5864_dev *dev, u16 addr)
{
int retries = 30000;
while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries)
;
if (!retries)
dev_err(&dev->pci->dev,
"tw_indir_readl() retries exhausted before reading\n");
tw_writel(TW5864_IND_CTL, addr << 2 | TW5864_ENABLE);
retries = 30000;
while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries)
;
if (!retries)
dev_err(&dev->pci->dev,
"tw_indir_readl() retries exhausted at reading\n");
return tw_readl(TW5864_IND_DATA);
}
| linux-master | drivers/media/pci/tw5864/tw5864-util.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SMI PCIe driver for DVBSky cards.
*
* Copyright (C) 2014 Max nibble <[email protected]>
*/
#include "smipcie.h"
#define SMI_SAMPLE_PERIOD 83
#define SMI_SAMPLE_IDLEMIN (10000 / SMI_SAMPLE_PERIOD)
static void smi_ir_enableInterrupt(struct smi_rc *ir)
{
struct smi_dev *dev = ir->dev;
smi_write(MSI_INT_ENA_SET, IR_X_INT);
}
static void smi_ir_disableInterrupt(struct smi_rc *ir)
{
struct smi_dev *dev = ir->dev;
smi_write(MSI_INT_ENA_CLR, IR_X_INT);
}
static void smi_ir_clearInterrupt(struct smi_rc *ir)
{
struct smi_dev *dev = ir->dev;
smi_write(MSI_INT_STATUS_CLR, IR_X_INT);
}
static void smi_ir_stop(struct smi_rc *ir)
{
struct smi_dev *dev = ir->dev;
smi_ir_disableInterrupt(ir);
smi_clear(IR_Init_Reg, rbIRen);
}
static void smi_raw_process(struct rc_dev *rc_dev, const u8 *buffer,
const u8 length)
{
struct ir_raw_event rawir = {};
int cnt;
for (cnt = 0; cnt < length; cnt++) {
if (buffer[cnt] & 0x7f) {
rawir.pulse = (buffer[cnt] & 0x80) == 0;
rawir.duration = ((buffer[cnt] & 0x7f) +
(rawir.pulse ? 0 : -1)) *
rc_dev->rx_resolution;
ir_raw_event_store_with_filter(rc_dev, &rawir);
}
}
}
static void smi_ir_decode(struct smi_rc *ir)
{
struct smi_dev *dev = ir->dev;
struct rc_dev *rc_dev = ir->rc_dev;
u32 control, data;
u8 index, ir_count, read_loop;
control = smi_read(IR_Init_Reg);
dev_dbg(&rc_dev->dev, "ircontrol: 0x%08x\n", control);
if (control & rbIRVld) {
ir_count = (u8)smi_read(IR_Data_Cnt);
dev_dbg(&rc_dev->dev, "ircount %d\n", ir_count);
read_loop = ir_count / 4;
if (ir_count % 4)
read_loop += 1;
for (index = 0; index < read_loop; index++) {
data = smi_read(IR_DATA_BUFFER_BASE + (index * 4));
dev_dbg(&rc_dev->dev, "IRData 0x%08x\n", data);
ir->irData[index * 4 + 0] = (u8)(data);
ir->irData[index * 4 + 1] = (u8)(data >> 8);
ir->irData[index * 4 + 2] = (u8)(data >> 16);
ir->irData[index * 4 + 3] = (u8)(data >> 24);
}
smi_raw_process(rc_dev, ir->irData, ir_count);
}
if (control & rbIRhighidle) {
struct ir_raw_event rawir = {};
dev_dbg(&rc_dev->dev, "high idle\n");
rawir.pulse = 0;
rawir.duration = SMI_SAMPLE_PERIOD * SMI_SAMPLE_IDLEMIN;
ir_raw_event_store_with_filter(rc_dev, &rawir);
}
smi_set(IR_Init_Reg, rbIRVld);
ir_raw_event_handle(rc_dev);
}
/* ir functions call by main driver.*/
int smi_ir_irq(struct smi_rc *ir, u32 int_status)
{
int handled = 0;
if (int_status & IR_X_INT) {
smi_ir_disableInterrupt(ir);
smi_ir_clearInterrupt(ir);
smi_ir_decode(ir);
smi_ir_enableInterrupt(ir);
handled = 1;
}
return handled;
}
void smi_ir_start(struct smi_rc *ir)
{
struct smi_dev *dev = ir->dev;
smi_write(IR_Idle_Cnt_Low,
(((SMI_SAMPLE_PERIOD - 1) & 0xFFFF) << 16) |
(SMI_SAMPLE_IDLEMIN & 0xFFFF));
msleep(20);
smi_set(IR_Init_Reg, rbIRen | rbIRhighidle);
smi_ir_enableInterrupt(ir);
}
int smi_ir_init(struct smi_dev *dev)
{
int ret;
struct rc_dev *rc_dev;
struct smi_rc *ir = &dev->ir;
rc_dev = rc_allocate_device(RC_DRIVER_IR_RAW);
if (!rc_dev)
return -ENOMEM;
/* init input device */
snprintf(ir->device_name, sizeof(ir->device_name), "IR (%s)",
dev->info->name);
snprintf(ir->input_phys, sizeof(ir->input_phys), "pci-%s/ir0",
pci_name(dev->pci_dev));
rc_dev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
rc_dev->driver_name = "SMI_PCIe";
rc_dev->input_phys = ir->input_phys;
rc_dev->device_name = ir->device_name;
rc_dev->input_id.bustype = BUS_PCI;
rc_dev->input_id.version = 1;
rc_dev->input_id.vendor = dev->pci_dev->subsystem_vendor;
rc_dev->input_id.product = dev->pci_dev->subsystem_device;
rc_dev->dev.parent = &dev->pci_dev->dev;
rc_dev->map_name = dev->info->rc_map;
rc_dev->timeout = SMI_SAMPLE_PERIOD * SMI_SAMPLE_IDLEMIN;
rc_dev->rx_resolution = SMI_SAMPLE_PERIOD;
ir->rc_dev = rc_dev;
ir->dev = dev;
smi_ir_disableInterrupt(ir);
ret = rc_register_device(rc_dev);
if (ret)
goto ir_err;
return 0;
ir_err:
rc_free_device(rc_dev);
return ret;
}
void smi_ir_exit(struct smi_dev *dev)
{
struct smi_rc *ir = &dev->ir;
struct rc_dev *rc_dev = ir->rc_dev;
rc_unregister_device(rc_dev);
smi_ir_stop(ir);
ir->rc_dev = NULL;
}
| linux-master | drivers/media/pci/smipcie/smipcie-ir.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SMI PCIe driver for DVBSky cards.
*
* Copyright (C) 2014 Max nibble <[email protected]>
*/
#include "smipcie.h"
#include "m88ds3103.h"
#include "ts2020.h"
#include "m88rs6000t.h"
#include "si2168.h"
#include "si2157.h"
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
static int smi_hw_init(struct smi_dev *dev)
{
u32 port_mux, port_ctrl, int_stat;
/* set port mux.*/
port_mux = smi_read(MUX_MODE_CTRL);
port_mux &= ~(rbPaMSMask);
port_mux |= rbPaMSDtvNoGpio;
port_mux &= ~(rbPbMSMask);
port_mux |= rbPbMSDtvNoGpio;
port_mux &= ~(0x0f0000);
port_mux |= 0x50000;
smi_write(MUX_MODE_CTRL, port_mux);
/* set DTV register.*/
/* Port A */
port_ctrl = smi_read(VIDEO_CTRL_STATUS_A);
port_ctrl &= ~0x01;
smi_write(VIDEO_CTRL_STATUS_A, port_ctrl);
port_ctrl = smi_read(MPEG2_CTRL_A);
port_ctrl &= ~0x40;
port_ctrl |= 0x80;
smi_write(MPEG2_CTRL_A, port_ctrl);
/* Port B */
port_ctrl = smi_read(VIDEO_CTRL_STATUS_B);
port_ctrl &= ~0x01;
smi_write(VIDEO_CTRL_STATUS_B, port_ctrl);
port_ctrl = smi_read(MPEG2_CTRL_B);
port_ctrl &= ~0x40;
port_ctrl |= 0x80;
smi_write(MPEG2_CTRL_B, port_ctrl);
/* disable and clear interrupt.*/
smi_write(MSI_INT_ENA_CLR, ALL_INT);
int_stat = smi_read(MSI_INT_STATUS);
smi_write(MSI_INT_STATUS_CLR, int_stat);
/* reset demod.*/
smi_clear(PERIPHERAL_CTRL, 0x0303);
msleep(50);
smi_set(PERIPHERAL_CTRL, 0x0101);
return 0;
}
/* i2c bit bus.*/
static void smi_i2c_cfg(struct smi_dev *dev, u32 sw_ctl)
{
u32 dwCtrl;
dwCtrl = smi_read(sw_ctl);
dwCtrl &= ~0x18; /* disable output.*/
dwCtrl |= 0x21; /* reset and software mode.*/
dwCtrl &= ~0xff00;
dwCtrl |= 0x6400;
smi_write(sw_ctl, dwCtrl);
msleep(20);
dwCtrl = smi_read(sw_ctl);
dwCtrl &= ~0x20;
smi_write(sw_ctl, dwCtrl);
}
static void smi_i2c_setsda(struct smi_dev *dev, int state, u32 sw_ctl)
{
if (state) {
/* set as input.*/
smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
} else {
smi_clear(sw_ctl, SW_I2C_MSK_DAT_OUT);
/* set as output.*/
smi_set(sw_ctl, SW_I2C_MSK_DAT_EN);
}
}
static void smi_i2c_setscl(void *data, int state, u32 sw_ctl)
{
struct smi_dev *dev = data;
if (state) {
/* set as input.*/
smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
} else {
smi_clear(sw_ctl, SW_I2C_MSK_CLK_OUT);
/* set as output.*/
smi_set(sw_ctl, SW_I2C_MSK_CLK_EN);
}
}
static int smi_i2c_getsda(void *data, u32 sw_ctl)
{
struct smi_dev *dev = data;
/* set as input.*/
smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
udelay(1);
return (smi_read(sw_ctl) & SW_I2C_MSK_DAT_IN) ? 1 : 0;
}
static int smi_i2c_getscl(void *data, u32 sw_ctl)
{
struct smi_dev *dev = data;
/* set as input.*/
smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
udelay(1);
return (smi_read(sw_ctl) & SW_I2C_MSK_CLK_IN) ? 1 : 0;
}
/* i2c 0.*/
static void smi_i2c0_setsda(void *data, int state)
{
struct smi_dev *dev = data;
smi_i2c_setsda(dev, state, I2C_A_SW_CTL);
}
static void smi_i2c0_setscl(void *data, int state)
{
struct smi_dev *dev = data;
smi_i2c_setscl(dev, state, I2C_A_SW_CTL);
}
static int smi_i2c0_getsda(void *data)
{
struct smi_dev *dev = data;
return smi_i2c_getsda(dev, I2C_A_SW_CTL);
}
static int smi_i2c0_getscl(void *data)
{
struct smi_dev *dev = data;
return smi_i2c_getscl(dev, I2C_A_SW_CTL);
}
/* i2c 1.*/
static void smi_i2c1_setsda(void *data, int state)
{
struct smi_dev *dev = data;
smi_i2c_setsda(dev, state, I2C_B_SW_CTL);
}
static void smi_i2c1_setscl(void *data, int state)
{
struct smi_dev *dev = data;
smi_i2c_setscl(dev, state, I2C_B_SW_CTL);
}
static int smi_i2c1_getsda(void *data)
{
struct smi_dev *dev = data;
return smi_i2c_getsda(dev, I2C_B_SW_CTL);
}
static int smi_i2c1_getscl(void *data)
{
struct smi_dev *dev = data;
return smi_i2c_getscl(dev, I2C_B_SW_CTL);
}
static int smi_i2c_init(struct smi_dev *dev)
{
int ret;
/* i2c bus 0 */
smi_i2c_cfg(dev, I2C_A_SW_CTL);
i2c_set_adapdata(&dev->i2c_bus[0], dev);
strscpy(dev->i2c_bus[0].name, "SMI-I2C0", sizeof(dev->i2c_bus[0].name));
dev->i2c_bus[0].owner = THIS_MODULE;
dev->i2c_bus[0].dev.parent = &dev->pci_dev->dev;
dev->i2c_bus[0].algo_data = &dev->i2c_bit[0];
dev->i2c_bit[0].data = dev;
dev->i2c_bit[0].setsda = smi_i2c0_setsda;
dev->i2c_bit[0].setscl = smi_i2c0_setscl;
dev->i2c_bit[0].getsda = smi_i2c0_getsda;
dev->i2c_bit[0].getscl = smi_i2c0_getscl;
dev->i2c_bit[0].udelay = 12;
dev->i2c_bit[0].timeout = 10;
/* Raise SCL and SDA */
smi_i2c0_setsda(dev, 1);
smi_i2c0_setscl(dev, 1);
ret = i2c_bit_add_bus(&dev->i2c_bus[0]);
if (ret < 0)
return ret;
/* i2c bus 1 */
smi_i2c_cfg(dev, I2C_B_SW_CTL);
i2c_set_adapdata(&dev->i2c_bus[1], dev);
strscpy(dev->i2c_bus[1].name, "SMI-I2C1", sizeof(dev->i2c_bus[1].name));
dev->i2c_bus[1].owner = THIS_MODULE;
dev->i2c_bus[1].dev.parent = &dev->pci_dev->dev;
dev->i2c_bus[1].algo_data = &dev->i2c_bit[1];
dev->i2c_bit[1].data = dev;
dev->i2c_bit[1].setsda = smi_i2c1_setsda;
dev->i2c_bit[1].setscl = smi_i2c1_setscl;
dev->i2c_bit[1].getsda = smi_i2c1_getsda;
dev->i2c_bit[1].getscl = smi_i2c1_getscl;
dev->i2c_bit[1].udelay = 12;
dev->i2c_bit[1].timeout = 10;
/* Raise SCL and SDA */
smi_i2c1_setsda(dev, 1);
smi_i2c1_setscl(dev, 1);
ret = i2c_bit_add_bus(&dev->i2c_bus[1]);
if (ret < 0)
i2c_del_adapter(&dev->i2c_bus[0]);
return ret;
}
static void smi_i2c_exit(struct smi_dev *dev)
{
i2c_del_adapter(&dev->i2c_bus[0]);
i2c_del_adapter(&dev->i2c_bus[1]);
}
static int smi_read_eeprom(struct i2c_adapter *i2c, u16 reg, u8 *data, u16 size)
{
int ret;
u8 b0[2] = { (reg >> 8) & 0xff, reg & 0xff };
struct i2c_msg msg[] = {
{ .addr = 0x50, .flags = 0,
.buf = b0, .len = 2 },
{ .addr = 0x50, .flags = I2C_M_RD,
.buf = data, .len = size }
};
ret = i2c_transfer(i2c, msg, 2);
if (ret != 2) {
dev_err(&i2c->dev, "%s: reg=0x%x (error=%d)\n",
__func__, reg, ret);
return ret;
}
return ret;
}
/* ts port interrupt operations */
static void smi_port_disableInterrupt(struct smi_port *port)
{
struct smi_dev *dev = port->dev;
smi_write(MSI_INT_ENA_CLR,
(port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
}
static void smi_port_enableInterrupt(struct smi_port *port)
{
struct smi_dev *dev = port->dev;
smi_write(MSI_INT_ENA_SET,
(port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
}
static void smi_port_clearInterrupt(struct smi_port *port)
{
struct smi_dev *dev = port->dev;
smi_write(MSI_INT_STATUS_CLR,
(port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
}
/* tasklet handler: DMA data to dmx.*/
static void smi_dma_xfer(struct tasklet_struct *t)
{
struct smi_port *port = from_tasklet(port, t, tasklet);
struct smi_dev *dev = port->dev;
u32 intr_status, finishedData, dmaManagement;
u8 dmaChan0State, dmaChan1State;
intr_status = port->_int_status;
dmaManagement = smi_read(port->DMA_MANAGEMENT);
dmaChan0State = (u8)((dmaManagement & 0x00000030) >> 4);
dmaChan1State = (u8)((dmaManagement & 0x00300000) >> 20);
/* CH-0 DMA interrupt.*/
if ((intr_status & port->_dmaInterruptCH0) && (dmaChan0State == 0x01)) {
dev_dbg(&dev->pci_dev->dev,
"Port[%d]-DMA CH0 engine complete successful !\n",
port->idx);
finishedData = smi_read(port->DMA_CHAN0_TRANS_STATE);
finishedData &= 0x003FFFFF;
/* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
* indicate dma total transfer length and
* zero of [21:0] indicate dma total transfer length
* equal to 0x400000 (4MB)*/
if (finishedData == 0)
finishedData = 0x00400000;
if (finishedData != SMI_TS_DMA_BUF_SIZE) {
dev_dbg(&dev->pci_dev->dev,
"DMA CH0 engine complete length mismatched, finish data=%d !\n",
finishedData);
}
dvb_dmx_swfilter_packets(&port->demux,
port->cpu_addr[0], (finishedData / 188));
/*dvb_dmx_swfilter(&port->demux,
port->cpu_addr[0], finishedData);*/
}
/* CH-1 DMA interrupt.*/
if ((intr_status & port->_dmaInterruptCH1) && (dmaChan1State == 0x01)) {
dev_dbg(&dev->pci_dev->dev,
"Port[%d]-DMA CH1 engine complete successful !\n",
port->idx);
finishedData = smi_read(port->DMA_CHAN1_TRANS_STATE);
finishedData &= 0x003FFFFF;
/* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
* indicate dma total transfer length and
* zero of [21:0] indicate dma total transfer length
* equal to 0x400000 (4MB)*/
if (finishedData == 0)
finishedData = 0x00400000;
if (finishedData != SMI_TS_DMA_BUF_SIZE) {
dev_dbg(&dev->pci_dev->dev,
"DMA CH1 engine complete length mismatched, finish data=%d !\n",
finishedData);
}
dvb_dmx_swfilter_packets(&port->demux,
port->cpu_addr[1], (finishedData / 188));
/*dvb_dmx_swfilter(&port->demux,
port->cpu_addr[1], finishedData);*/
}
/* restart DMA.*/
if (intr_status & port->_dmaInterruptCH0)
dmaManagement |= 0x00000002;
if (intr_status & port->_dmaInterruptCH1)
dmaManagement |= 0x00020000;
smi_write(port->DMA_MANAGEMENT, dmaManagement);
/* Re-enable interrupts */
smi_port_enableInterrupt(port);
}
static void smi_port_dma_free(struct smi_port *port)
{
if (port->cpu_addr[0]) {
dma_free_coherent(&port->dev->pci_dev->dev,
SMI_TS_DMA_BUF_SIZE, port->cpu_addr[0],
port->dma_addr[0]);
port->cpu_addr[0] = NULL;
}
if (port->cpu_addr[1]) {
dma_free_coherent(&port->dev->pci_dev->dev,
SMI_TS_DMA_BUF_SIZE, port->cpu_addr[1],
port->dma_addr[1]);
port->cpu_addr[1] = NULL;
}
}
static int smi_port_init(struct smi_port *port, int dmaChanUsed)
{
dev_dbg(&port->dev->pci_dev->dev,
"%s, port %d, dmaused %d\n", __func__, port->idx, dmaChanUsed);
port->enable = 0;
if (port->idx == 0) {
/* Port A */
port->_dmaInterruptCH0 = dmaChanUsed & 0x01;
port->_dmaInterruptCH1 = dmaChanUsed & 0x02;
port->DMA_CHAN0_ADDR_LOW = DMA_PORTA_CHAN0_ADDR_LOW;
port->DMA_CHAN0_ADDR_HI = DMA_PORTA_CHAN0_ADDR_HI;
port->DMA_CHAN0_TRANS_STATE = DMA_PORTA_CHAN0_TRANS_STATE;
port->DMA_CHAN0_CONTROL = DMA_PORTA_CHAN0_CONTROL;
port->DMA_CHAN1_ADDR_LOW = DMA_PORTA_CHAN1_ADDR_LOW;
port->DMA_CHAN1_ADDR_HI = DMA_PORTA_CHAN1_ADDR_HI;
port->DMA_CHAN1_TRANS_STATE = DMA_PORTA_CHAN1_TRANS_STATE;
port->DMA_CHAN1_CONTROL = DMA_PORTA_CHAN1_CONTROL;
port->DMA_MANAGEMENT = DMA_PORTA_MANAGEMENT;
} else {
/* Port B */
port->_dmaInterruptCH0 = (dmaChanUsed << 2) & 0x04;
port->_dmaInterruptCH1 = (dmaChanUsed << 2) & 0x08;
port->DMA_CHAN0_ADDR_LOW = DMA_PORTB_CHAN0_ADDR_LOW;
port->DMA_CHAN0_ADDR_HI = DMA_PORTB_CHAN0_ADDR_HI;
port->DMA_CHAN0_TRANS_STATE = DMA_PORTB_CHAN0_TRANS_STATE;
port->DMA_CHAN0_CONTROL = DMA_PORTB_CHAN0_CONTROL;
port->DMA_CHAN1_ADDR_LOW = DMA_PORTB_CHAN1_ADDR_LOW;
port->DMA_CHAN1_ADDR_HI = DMA_PORTB_CHAN1_ADDR_HI;
port->DMA_CHAN1_TRANS_STATE = DMA_PORTB_CHAN1_TRANS_STATE;
port->DMA_CHAN1_CONTROL = DMA_PORTB_CHAN1_CONTROL;
port->DMA_MANAGEMENT = DMA_PORTB_MANAGEMENT;
}
if (port->_dmaInterruptCH0) {
port->cpu_addr[0] = dma_alloc_coherent(&port->dev->pci_dev->dev,
SMI_TS_DMA_BUF_SIZE,
&port->dma_addr[0],
GFP_KERNEL);
if (!port->cpu_addr[0]) {
dev_err(&port->dev->pci_dev->dev,
"Port[%d] DMA CH0 memory allocation failed!\n",
port->idx);
goto err;
}
}
if (port->_dmaInterruptCH1) {
port->cpu_addr[1] = dma_alloc_coherent(&port->dev->pci_dev->dev,
SMI_TS_DMA_BUF_SIZE,
&port->dma_addr[1],
GFP_KERNEL);
if (!port->cpu_addr[1]) {
dev_err(&port->dev->pci_dev->dev,
"Port[%d] DMA CH1 memory allocation failed!\n",
port->idx);
goto err;
}
}
smi_port_disableInterrupt(port);
tasklet_setup(&port->tasklet, smi_dma_xfer);
tasklet_disable(&port->tasklet);
port->enable = 1;
return 0;
err:
smi_port_dma_free(port);
return -ENOMEM;
}
static void smi_port_exit(struct smi_port *port)
{
smi_port_disableInterrupt(port);
tasklet_kill(&port->tasklet);
smi_port_dma_free(port);
port->enable = 0;
}
static int smi_port_irq(struct smi_port *port, u32 int_status)
{
u32 port_req_irq = port->_dmaInterruptCH0 | port->_dmaInterruptCH1;
int handled = 0;
if (int_status & port_req_irq) {
smi_port_disableInterrupt(port);
port->_int_status = int_status;
smi_port_clearInterrupt(port);
tasklet_schedule(&port->tasklet);
handled = 1;
}
return handled;
}
static irqreturn_t smi_irq_handler(int irq, void *dev_id)
{
struct smi_dev *dev = dev_id;
struct smi_port *port0 = &dev->ts_port[0];
struct smi_port *port1 = &dev->ts_port[1];
struct smi_rc *ir = &dev->ir;
int handled = 0;
u32 intr_status = smi_read(MSI_INT_STATUS);
/* ts0 interrupt.*/
if (dev->info->ts_0)
handled += smi_port_irq(port0, intr_status);
/* ts1 interrupt.*/
if (dev->info->ts_1)
handled += smi_port_irq(port1, intr_status);
/* ir interrupt.*/
handled += smi_ir_irq(ir, intr_status);
return IRQ_RETVAL(handled);
}
static struct i2c_client *smi_add_i2c_client(struct i2c_adapter *adapter,
struct i2c_board_info *info)
{
struct i2c_client *client;
request_module(info->type);
client = i2c_new_client_device(adapter, info);
if (!i2c_client_has_driver(client))
goto err_add_i2c_client;
if (!try_module_get(client->dev.driver->owner)) {
i2c_unregister_device(client);
goto err_add_i2c_client;
}
return client;
err_add_i2c_client:
client = NULL;
return client;
}
static void smi_del_i2c_client(struct i2c_client *client)
{
module_put(client->dev.driver->owner);
i2c_unregister_device(client);
}
static const struct m88ds3103_config smi_dvbsky_m88ds3103_cfg = {
.i2c_addr = 0x68,
.clock = 27000000,
.i2c_wr_max = 33,
.clock_out = 0,
.ts_mode = M88DS3103_TS_PARALLEL,
.ts_clk = 16000,
.ts_clk_pol = 1,
.agc = 0x99,
.lnb_hv_pol = 0,
.lnb_en_pol = 1,
};
static int smi_dvbsky_m88ds3103_fe_attach(struct smi_port *port)
{
int ret = 0;
struct smi_dev *dev = port->dev;
struct i2c_adapter *i2c;
/* tuner I2C module */
struct i2c_adapter *tuner_i2c_adapter;
struct i2c_client *tuner_client;
struct i2c_board_info tuner_info;
struct ts2020_config ts2020_config = {};
memset(&tuner_info, 0, sizeof(struct i2c_board_info));
i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
/* attach demod */
port->fe = dvb_attach(m88ds3103_attach,
&smi_dvbsky_m88ds3103_cfg, i2c, &tuner_i2c_adapter);
if (!port->fe) {
ret = -ENODEV;
return ret;
}
/* attach tuner */
ts2020_config.fe = port->fe;
strscpy(tuner_info.type, "ts2020", I2C_NAME_SIZE);
tuner_info.addr = 0x60;
tuner_info.platform_data = &ts2020_config;
tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
if (!tuner_client) {
ret = -ENODEV;
goto err_tuner_i2c_device;
}
/* delegate signal strength measurement to tuner */
port->fe->ops.read_signal_strength =
port->fe->ops.tuner_ops.get_rf_strength;
port->i2c_client_tuner = tuner_client;
return ret;
err_tuner_i2c_device:
dvb_frontend_detach(port->fe);
return ret;
}
static const struct m88ds3103_config smi_dvbsky_m88rs6000_cfg = {
.i2c_addr = 0x69,
.clock = 27000000,
.i2c_wr_max = 33,
.ts_mode = M88DS3103_TS_PARALLEL,
.ts_clk = 16000,
.ts_clk_pol = 1,
.agc = 0x99,
.lnb_hv_pol = 0,
.lnb_en_pol = 1,
};
static int smi_dvbsky_m88rs6000_fe_attach(struct smi_port *port)
{
int ret = 0;
struct smi_dev *dev = port->dev;
struct i2c_adapter *i2c;
/* tuner I2C module */
struct i2c_adapter *tuner_i2c_adapter;
struct i2c_client *tuner_client;
struct i2c_board_info tuner_info;
struct m88rs6000t_config m88rs6000t_config;
memset(&tuner_info, 0, sizeof(struct i2c_board_info));
i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
/* attach demod */
port->fe = dvb_attach(m88ds3103_attach,
&smi_dvbsky_m88rs6000_cfg, i2c, &tuner_i2c_adapter);
if (!port->fe) {
ret = -ENODEV;
return ret;
}
/* attach tuner */
m88rs6000t_config.fe = port->fe;
strscpy(tuner_info.type, "m88rs6000t", I2C_NAME_SIZE);
tuner_info.addr = 0x21;
tuner_info.platform_data = &m88rs6000t_config;
tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
if (!tuner_client) {
ret = -ENODEV;
goto err_tuner_i2c_device;
}
/* delegate signal strength measurement to tuner */
port->fe->ops.read_signal_strength =
port->fe->ops.tuner_ops.get_rf_strength;
port->i2c_client_tuner = tuner_client;
return ret;
err_tuner_i2c_device:
dvb_frontend_detach(port->fe);
return ret;
}
static int smi_dvbsky_sit2_fe_attach(struct smi_port *port)
{
int ret = 0;
struct smi_dev *dev = port->dev;
struct i2c_adapter *i2c;
struct i2c_adapter *tuner_i2c_adapter;
struct i2c_client *client_tuner, *client_demod;
struct i2c_board_info client_info;
struct si2168_config si2168_config;
struct si2157_config si2157_config;
/* select i2c bus */
i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
/* attach demod */
memset(&si2168_config, 0, sizeof(si2168_config));
si2168_config.i2c_adapter = &tuner_i2c_adapter;
si2168_config.fe = &port->fe;
si2168_config.ts_mode = SI2168_TS_PARALLEL;
memset(&client_info, 0, sizeof(struct i2c_board_info));
strscpy(client_info.type, "si2168", I2C_NAME_SIZE);
client_info.addr = 0x64;
client_info.platform_data = &si2168_config;
client_demod = smi_add_i2c_client(i2c, &client_info);
if (!client_demod) {
ret = -ENODEV;
return ret;
}
port->i2c_client_demod = client_demod;
/* attach tuner */
memset(&si2157_config, 0, sizeof(si2157_config));
si2157_config.fe = port->fe;
si2157_config.if_port = 1;
memset(&client_info, 0, sizeof(struct i2c_board_info));
strscpy(client_info.type, "si2157", I2C_NAME_SIZE);
client_info.addr = 0x60;
client_info.platform_data = &si2157_config;
client_tuner = smi_add_i2c_client(tuner_i2c_adapter, &client_info);
if (!client_tuner) {
smi_del_i2c_client(port->i2c_client_demod);
port->i2c_client_demod = NULL;
ret = -ENODEV;
return ret;
}
port->i2c_client_tuner = client_tuner;
return ret;
}
static int smi_fe_init(struct smi_port *port)
{
int ret = 0;
struct smi_dev *dev = port->dev;
struct dvb_adapter *adap = &port->dvb_adapter;
u8 mac_ee[16];
dev_dbg(&port->dev->pci_dev->dev,
"%s: port %d, fe_type = %d\n",
__func__, port->idx, port->fe_type);
switch (port->fe_type) {
case DVBSKY_FE_M88DS3103:
ret = smi_dvbsky_m88ds3103_fe_attach(port);
break;
case DVBSKY_FE_M88RS6000:
ret = smi_dvbsky_m88rs6000_fe_attach(port);
break;
case DVBSKY_FE_SIT2:
ret = smi_dvbsky_sit2_fe_attach(port);
break;
}
if (ret < 0)
return ret;
/* register dvb frontend */
ret = dvb_register_frontend(adap, port->fe);
if (ret < 0) {
if (port->i2c_client_tuner)
smi_del_i2c_client(port->i2c_client_tuner);
if (port->i2c_client_demod)
smi_del_i2c_client(port->i2c_client_demod);
dvb_frontend_detach(port->fe);
return ret;
}
/* init MAC.*/
ret = smi_read_eeprom(&dev->i2c_bus[0], 0xc0, mac_ee, 16);
dev_info(&port->dev->pci_dev->dev,
"%s port %d MAC: %pM\n", dev->info->name,
port->idx, mac_ee + (port->idx)*8);
memcpy(adap->proposed_mac, mac_ee + (port->idx)*8, 6);
return ret;
}
static void smi_fe_exit(struct smi_port *port)
{
dvb_unregister_frontend(port->fe);
/* remove I2C demod and tuner */
if (port->i2c_client_tuner)
smi_del_i2c_client(port->i2c_client_tuner);
if (port->i2c_client_demod)
smi_del_i2c_client(port->i2c_client_demod);
dvb_frontend_detach(port->fe);
}
static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
int (*start_feed)(struct dvb_demux_feed *),
int (*stop_feed)(struct dvb_demux_feed *),
void *priv)
{
dvbdemux->priv = priv;
dvbdemux->filternum = 256;
dvbdemux->feednum = 256;
dvbdemux->start_feed = start_feed;
dvbdemux->stop_feed = stop_feed;
dvbdemux->write_to_decoder = NULL;
dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
DMX_SECTION_FILTERING |
DMX_MEMORY_BASED_FILTERING);
return dvb_dmx_init(dvbdemux);
}
static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
struct dvb_demux *dvbdemux,
struct dmx_frontend *hw_frontend,
struct dmx_frontend *mem_frontend,
struct dvb_adapter *dvb_adapter)
{
int ret;
dmxdev->filternum = 256;
dmxdev->demux = &dvbdemux->dmx;
dmxdev->capabilities = 0;
ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
if (ret < 0)
return ret;
hw_frontend->source = DMX_FRONTEND_0;
dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
mem_frontend->source = DMX_MEMORY_FE;
dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
}
static u32 smi_config_DMA(struct smi_port *port)
{
struct smi_dev *dev = port->dev;
u32 totalLength = 0, dmaMemPtrLow, dmaMemPtrHi, dmaCtlReg;
u8 chanLatencyTimer = 0, dmaChanEnable = 1, dmaTransStart = 1;
u32 dmaManagement = 0, tlpTransUnit = DMA_TRANS_UNIT_188;
u8 tlpTc = 0, tlpTd = 1, tlpEp = 0, tlpAttr = 0;
u64 mem;
dmaManagement = smi_read(port->DMA_MANAGEMENT);
/* Setup Channel-0 */
if (port->_dmaInterruptCH0) {
totalLength = SMI_TS_DMA_BUF_SIZE;
mem = port->dma_addr[0];
dmaMemPtrLow = mem & 0xffffffff;
dmaMemPtrHi = mem >> 32;
dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
| (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
dmaManagement |= dmaChanEnable | (dmaTransStart << 1)
| (chanLatencyTimer << 8);
/* write DMA register, start DMA engine */
smi_write(port->DMA_CHAN0_ADDR_LOW, dmaMemPtrLow);
smi_write(port->DMA_CHAN0_ADDR_HI, dmaMemPtrHi);
smi_write(port->DMA_CHAN0_CONTROL, dmaCtlReg);
}
/* Setup Channel-1 */
if (port->_dmaInterruptCH1) {
totalLength = SMI_TS_DMA_BUF_SIZE;
mem = port->dma_addr[1];
dmaMemPtrLow = mem & 0xffffffff;
dmaMemPtrHi = mem >> 32;
dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
| (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
dmaManagement |= (dmaChanEnable << 16) | (dmaTransStart << 17)
| (chanLatencyTimer << 24);
/* write DMA register, start DMA engine */
smi_write(port->DMA_CHAN1_ADDR_LOW, dmaMemPtrLow);
smi_write(port->DMA_CHAN1_ADDR_HI, dmaMemPtrHi);
smi_write(port->DMA_CHAN1_CONTROL, dmaCtlReg);
}
return dmaManagement;
}
static int smi_start_feed(struct dvb_demux_feed *dvbdmxfeed)
{
struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
struct smi_port *port = dvbdmx->priv;
struct smi_dev *dev = port->dev;
u32 dmaManagement;
if (port->users++ == 0) {
dmaManagement = smi_config_DMA(port);
smi_port_clearInterrupt(port);
smi_port_enableInterrupt(port);
smi_write(port->DMA_MANAGEMENT, dmaManagement);
tasklet_enable(&port->tasklet);
}
return port->users;
}
static int smi_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
{
struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
struct smi_port *port = dvbdmx->priv;
struct smi_dev *dev = port->dev;
if (--port->users)
return port->users;
tasklet_disable(&port->tasklet);
smi_port_disableInterrupt(port);
smi_clear(port->DMA_MANAGEMENT, 0x30003);
return 0;
}
static int smi_dvb_init(struct smi_port *port)
{
int ret;
struct dvb_adapter *adap = &port->dvb_adapter;
struct dvb_demux *dvbdemux = &port->demux;
dev_dbg(&port->dev->pci_dev->dev,
"%s, port %d\n", __func__, port->idx);
ret = dvb_register_adapter(adap, "SMI_DVB", THIS_MODULE,
&port->dev->pci_dev->dev,
adapter_nr);
if (ret < 0) {
dev_err(&port->dev->pci_dev->dev, "Fail to register DVB adapter.\n");
return ret;
}
ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
smi_start_feed,
smi_stop_feed, port);
if (ret < 0)
goto err_del_dvb_register_adapter;
ret = my_dvb_dmxdev_ts_card_init(&port->dmxdev, &port->demux,
&port->hw_frontend,
&port->mem_frontend, adap);
if (ret < 0)
goto err_del_dvb_dmx;
ret = dvb_net_init(adap, &port->dvbnet, port->dmxdev.demux);
if (ret < 0)
goto err_del_dvb_dmxdev;
return 0;
err_del_dvb_dmxdev:
dvbdemux->dmx.close(&dvbdemux->dmx);
dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
dvb_dmxdev_release(&port->dmxdev);
err_del_dvb_dmx:
dvb_dmx_release(&port->demux);
err_del_dvb_register_adapter:
dvb_unregister_adapter(&port->dvb_adapter);
return ret;
}
static void smi_dvb_exit(struct smi_port *port)
{
struct dvb_demux *dvbdemux = &port->demux;
dvb_net_release(&port->dvbnet);
dvbdemux->dmx.close(&dvbdemux->dmx);
dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
dvb_dmxdev_release(&port->dmxdev);
dvb_dmx_release(&port->demux);
dvb_unregister_adapter(&port->dvb_adapter);
}
static int smi_port_attach(struct smi_dev *dev,
struct smi_port *port, int index)
{
int ret, dmachs;
port->dev = dev;
port->idx = index;
port->fe_type = (index == 0) ? dev->info->fe_0 : dev->info->fe_1;
dmachs = (index == 0) ? dev->info->ts_0 : dev->info->ts_1;
/* port init.*/
ret = smi_port_init(port, dmachs);
if (ret < 0)
return ret;
/* dvb init.*/
ret = smi_dvb_init(port);
if (ret < 0)
goto err_del_port_init;
/* fe init.*/
ret = smi_fe_init(port);
if (ret < 0)
goto err_del_dvb_init;
return 0;
err_del_dvb_init:
smi_dvb_exit(port);
err_del_port_init:
smi_port_exit(port);
return ret;
}
static void smi_port_detach(struct smi_port *port)
{
smi_fe_exit(port);
smi_dvb_exit(port);
smi_port_exit(port);
}
static int smi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct smi_dev *dev;
int ret = -ENOMEM;
if (pci_enable_device(pdev) < 0)
return -ENODEV;
dev = kzalloc(sizeof(struct smi_dev), GFP_KERNEL);
if (!dev) {
ret = -ENOMEM;
goto err_pci_disable_device;
}
dev->pci_dev = pdev;
pci_set_drvdata(pdev, dev);
dev->info = (struct smi_cfg_info *) id->driver_data;
dev_info(&dev->pci_dev->dev,
"card detected: %s\n", dev->info->name);
dev->nr = dev->info->type;
dev->lmmio = ioremap(pci_resource_start(dev->pci_dev, 0),
pci_resource_len(dev->pci_dev, 0));
if (!dev->lmmio) {
ret = -ENOMEM;
goto err_kfree;
}
/* should we set to 32bit DMA? */
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret < 0)
goto err_pci_iounmap;
pci_set_master(pdev);
ret = smi_hw_init(dev);
if (ret < 0)
goto err_pci_iounmap;
ret = smi_i2c_init(dev);
if (ret < 0)
goto err_pci_iounmap;
if (dev->info->ts_0) {
ret = smi_port_attach(dev, &dev->ts_port[0], 0);
if (ret < 0)
goto err_del_i2c_adaptor;
}
if (dev->info->ts_1) {
ret = smi_port_attach(dev, &dev->ts_port[1], 1);
if (ret < 0)
goto err_del_port0_attach;
}
ret = smi_ir_init(dev);
if (ret < 0)
goto err_del_port1_attach;
#ifdef CONFIG_PCI_MSI /* to do msi interrupt.???*/
if (pci_msi_enabled())
ret = pci_enable_msi(dev->pci_dev);
if (ret)
dev_info(&dev->pci_dev->dev, "MSI not available.\n");
#endif
ret = request_irq(dev->pci_dev->irq, smi_irq_handler,
IRQF_SHARED, "SMI_PCIE", dev);
if (ret < 0)
goto err_del_ir;
smi_ir_start(&dev->ir);
return 0;
err_del_ir:
smi_ir_exit(dev);
err_del_port1_attach:
if (dev->info->ts_1)
smi_port_detach(&dev->ts_port[1]);
err_del_port0_attach:
if (dev->info->ts_0)
smi_port_detach(&dev->ts_port[0]);
err_del_i2c_adaptor:
smi_i2c_exit(dev);
err_pci_iounmap:
iounmap(dev->lmmio);
err_kfree:
pci_set_drvdata(pdev, NULL);
kfree(dev);
err_pci_disable_device:
pci_disable_device(pdev);
return ret;
}
static void smi_remove(struct pci_dev *pdev)
{
struct smi_dev *dev = pci_get_drvdata(pdev);
smi_write(MSI_INT_ENA_CLR, ALL_INT);
free_irq(dev->pci_dev->irq, dev);
#ifdef CONFIG_PCI_MSI
pci_disable_msi(dev->pci_dev);
#endif
if (dev->info->ts_1)
smi_port_detach(&dev->ts_port[1]);
if (dev->info->ts_0)
smi_port_detach(&dev->ts_port[0]);
smi_ir_exit(dev);
smi_i2c_exit(dev);
iounmap(dev->lmmio);
pci_set_drvdata(pdev, NULL);
pci_disable_device(pdev);
kfree(dev);
}
/* DVBSky cards */
static const struct smi_cfg_info dvbsky_s950_cfg = {
.type = SMI_DVBSKY_S950,
.name = "DVBSky S950 V3",
.ts_0 = SMI_TS_NULL,
.ts_1 = SMI_TS_DMA_BOTH,
.fe_0 = DVBSKY_FE_NULL,
.fe_1 = DVBSKY_FE_M88DS3103,
.rc_map = RC_MAP_DVBSKY,
};
static const struct smi_cfg_info dvbsky_s952_cfg = {
.type = SMI_DVBSKY_S952,
.name = "DVBSky S952 V3",
.ts_0 = SMI_TS_DMA_BOTH,
.ts_1 = SMI_TS_DMA_BOTH,
.fe_0 = DVBSKY_FE_M88RS6000,
.fe_1 = DVBSKY_FE_M88RS6000,
.rc_map = RC_MAP_DVBSKY,
};
static const struct smi_cfg_info dvbsky_t9580_cfg = {
.type = SMI_DVBSKY_T9580,
.name = "DVBSky T9580 V3",
.ts_0 = SMI_TS_DMA_BOTH,
.ts_1 = SMI_TS_DMA_BOTH,
.fe_0 = DVBSKY_FE_SIT2,
.fe_1 = DVBSKY_FE_M88DS3103,
.rc_map = RC_MAP_DVBSKY,
};
static const struct smi_cfg_info technotrend_s2_4200_cfg = {
.type = SMI_TECHNOTREND_S2_4200,
.name = "TechnoTrend TT-budget S2-4200 Twin",
.ts_0 = SMI_TS_DMA_BOTH,
.ts_1 = SMI_TS_DMA_BOTH,
.fe_0 = DVBSKY_FE_M88RS6000,
.fe_1 = DVBSKY_FE_M88RS6000,
.rc_map = RC_MAP_TT_1500,
};
/* PCI IDs */
#define SMI_ID(_subvend, _subdev, _driverdata) { \
.vendor = SMI_VID, .device = SMI_PID, \
.subvendor = _subvend, .subdevice = _subdev, \
.driver_data = (unsigned long)&_driverdata }
static const struct pci_device_id smi_id_table[] = {
SMI_ID(0x4254, 0x0550, dvbsky_s950_cfg),
SMI_ID(0x4254, 0x0552, dvbsky_s952_cfg),
SMI_ID(0x4254, 0x5580, dvbsky_t9580_cfg),
SMI_ID(0x13c2, 0x3016, technotrend_s2_4200_cfg),
{0}
};
MODULE_DEVICE_TABLE(pci, smi_id_table);
static struct pci_driver smipcie_driver = {
.name = "SMI PCIe driver",
.id_table = smi_id_table,
.probe = smi_probe,
.remove = smi_remove,
};
module_pci_driver(smipcie_driver);
MODULE_AUTHOR("Max nibble <[email protected]>");
MODULE_DESCRIPTION("SMI PCIe driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/media/pci/smipcie/smipcie-main.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Zoran ZR36016 basic configuration functions
*
* Copyright (C) 2001 Wolfgang Scherr <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
/* headerfile of this module */
#include "zr36016.h"
/* codec io API */
#include "videocodec.h"
/*
* it doesn't make sense to have more than 20 or so,
* just to prevent some unwanted loops
*/
#define MAX_CODECS 20
/* amount of chips attached via this driver */
static int zr36016_codecs;
/*
* Local hardware I/O functions: read/write via codec layer
* (registers are located in the master device)
*/
/* read and write functions */
static u8 zr36016_read(struct zr36016 *ptr, u16 reg)
{
u8 value = 0;
struct zoran *zr = videocodec_to_zoran(ptr->codec);
/* just in case something is wrong... */
if (ptr->codec->master_data->readreg)
value = (ptr->codec->master_data->readreg(ptr->codec, reg)) & 0xFF;
else
zrdev_err(zr, "%s: invalid I/O setup, nothing read!\n", ptr->name);
zrdev_dbg(zr, "%s: reading from 0x%04x: %02x\n", ptr->name, reg, value);
return value;
}
static void zr36016_write(struct zr36016 *ptr, u16 reg, u8 value)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
zrdev_dbg(zr, "%s: writing 0x%02x to 0x%04x\n", ptr->name, value, reg);
// just in case something is wrong...
if (ptr->codec->master_data->writereg)
ptr->codec->master_data->writereg(ptr->codec, reg, value);
else
zrdev_err(zr, "%s: invalid I/O setup, nothing written!\n", ptr->name);
}
/*
* indirect read and write functions
*
* the 016 supports auto-addr-increment, but
* writing it all time cost not much and is safer...
*/
static u8 zr36016_readi(struct zr36016 *ptr, u16 reg)
{
u8 value = 0;
struct zoran *zr = videocodec_to_zoran(ptr->codec);
/* just in case something is wrong... */
if ((ptr->codec->master_data->writereg) && (ptr->codec->master_data->readreg)) {
ptr->codec->master_data->writereg(ptr->codec, ZR016_IADDR, reg & 0x0F);
value = (ptr->codec->master_data->readreg(ptr->codec, ZR016_IDATA)) & 0xFF;
} else {
zrdev_err(zr, "%s: invalid I/O setup, nothing read (i)!\n", ptr->name);
}
zrdev_dbg(zr, "%s: reading indirect from 0x%04x: %02x\n",
ptr->name, reg, value);
return value;
}
static void zr36016_writei(struct zr36016 *ptr, u16 reg, u8 value)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
zrdev_dbg(zr, "%s: writing indirect 0x%02x to 0x%04x\n", ptr->name,
value, reg);
/* just in case something is wrong... */
if (ptr->codec->master_data->writereg) {
ptr->codec->master_data->writereg(ptr->codec, ZR016_IADDR, reg & 0x0F);
ptr->codec->master_data->writereg(ptr->codec, ZR016_IDATA, value & 0x0FF);
} else {
zrdev_err(zr, "%s: invalid I/O setup, nothing written (i)!\n", ptr->name);
}
}
/* Local helper function: version read */
/* version kept in datastructure */
static u8 zr36016_read_version(struct zr36016 *ptr)
{
ptr->version = zr36016_read(ptr, 0) >> 4;
return ptr->version;
}
/*
* Local helper function: basic test of "connectivity", writes/reads
* to/from PAX-Lo register
*/
static int zr36016_basic_test(struct zr36016 *ptr)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
if (*KERN_INFO <= CONSOLE_LOGLEVEL_DEFAULT) {
int i;
zr36016_writei(ptr, ZR016I_PAX_LO, 0x55);
zrdev_dbg(zr, "%s: registers: ", ptr->name);
for (i = 0; i <= 0x0b; i++)
zrdev_dbg(zr, "%02x ", zr36016_readi(ptr, i));
zrdev_dbg(zr, "\n");
}
// for testing just write 0, then the default value to a register and read
// it back in both cases
zr36016_writei(ptr, ZR016I_PAX_LO, 0x00);
if (zr36016_readi(ptr, ZR016I_PAX_LO) != 0x0) {
zrdev_err(zr, "%s: attach failed, can't connect to vfe processor!\n", ptr->name);
return -ENXIO;
}
zr36016_writei(ptr, ZR016I_PAX_LO, 0x0d0);
if (zr36016_readi(ptr, ZR016I_PAX_LO) != 0x0d0) {
zrdev_err(zr, "%s: attach failed, can't connect to vfe processor!\n", ptr->name);
return -ENXIO;
}
// we allow version numbers from 0-3, should be enough, though
zr36016_read_version(ptr);
if (ptr->version & 0x0c) {
zrdev_err(zr, "%s: attach failed, suspicious version %d found...\n", ptr->name,
ptr->version);
return -ENXIO;
}
return 0; /* looks good! */
}
/* Basic datasets & init */
static void zr36016_init(struct zr36016 *ptr)
{
// stop any processing
zr36016_write(ptr, ZR016_GOSTOP, 0);
// mode setup (yuv422 in and out, compression/expansuon due to mode)
zr36016_write(ptr, ZR016_MODE,
ZR016_YUV422 | ZR016_YUV422_YUV422 |
(ptr->mode == CODEC_DO_COMPRESSION ?
ZR016_COMPRESSION : ZR016_EXPANSION));
// misc setup
zr36016_writei(ptr, ZR016I_SETUP1,
(ptr->xdec ? (ZR016_HRFL | ZR016_HORZ) : 0) |
(ptr->ydec ? ZR016_VERT : 0) | ZR016_CNTI);
zr36016_writei(ptr, ZR016I_SETUP2, ZR016_CCIR);
// Window setup
// (no extra offset for now, norm defines offset, default width height)
zr36016_writei(ptr, ZR016I_PAX_HI, ptr->width >> 8);
zr36016_writei(ptr, ZR016I_PAX_LO, ptr->width & 0xFF);
zr36016_writei(ptr, ZR016I_PAY_HI, ptr->height >> 8);
zr36016_writei(ptr, ZR016I_PAY_LO, ptr->height & 0xFF);
zr36016_writei(ptr, ZR016I_NAX_HI, ptr->xoff >> 8);
zr36016_writei(ptr, ZR016I_NAX_LO, ptr->xoff & 0xFF);
zr36016_writei(ptr, ZR016I_NAY_HI, ptr->yoff >> 8);
zr36016_writei(ptr, ZR016I_NAY_LO, ptr->yoff & 0xFF);
/* shall we continue now, please? */
zr36016_write(ptr, ZR016_GOSTOP, 1);
}
/*
* CODEC API FUNCTIONS
*
* These functions are accessed by the master via the API structure
*/
/*
* set compression/expansion mode and launches codec -
* this should be the last call from the master before starting processing
*/
static int zr36016_set_mode(struct videocodec *codec, int mode)
{
struct zr36016 *ptr = (struct zr36016 *)codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
zrdev_dbg(zr, "%s: set_mode %d call\n", ptr->name, mode);
if ((mode != CODEC_DO_EXPANSION) && (mode != CODEC_DO_COMPRESSION))
return -EINVAL;
ptr->mode = mode;
zr36016_init(ptr);
return 0;
}
/* set picture size */
static int zr36016_set_video(struct videocodec *codec, const struct tvnorm *norm,
struct vfe_settings *cap, struct vfe_polarity *pol)
{
struct zr36016 *ptr = (struct zr36016 *)codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
zrdev_dbg(zr, "%s: set_video %d.%d, %d/%d-%dx%d (0x%x) call\n",
ptr->name, norm->h_start, norm->v_start,
cap->x, cap->y, cap->width, cap->height,
cap->decimation);
/*
* if () return -EINVAL;
* trust the master driver that it knows what it does - so
* we allow invalid startx/y for now ...
*/
ptr->width = cap->width;
ptr->height = cap->height;
/*
* (Ronald) This is ugly. zoran_device.c, line 387
* already mentions what happens if h_start is even
* (blue faces, etc., cr/cb inversed). There's probably
* some good reason why h_start is 0 instead of 1, so I'm
* leaving it to this for now, but really... This can be
* done a lot simpler
*/
ptr->xoff = (norm->h_start ? norm->h_start : 1) + cap->x;
/*
* Something to note here (I don't understand it), setting
* v_start too high will cause the codec to 'not work'. I
* really don't get it. values of 16 (v_start) already break
* it here. Just '0' seems to work. More testing needed!
*/
ptr->yoff = norm->v_start + cap->y;
/* (Ronald) dzjeeh, can't this thing do hor_decimation = 4? */
ptr->xdec = ((cap->decimation & 0xff) == 1) ? 0 : 1;
ptr->ydec = (((cap->decimation >> 8) & 0xff) == 1) ? 0 : 1;
return 0;
}
/* additional control functions */
static int zr36016_control(struct videocodec *codec, int type, int size, void *data)
{
struct zr36016 *ptr = (struct zr36016 *)codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
int *ival = (int *)data;
zrdev_dbg(zr, "%s: control %d call with %d byte\n",
ptr->name, type, size);
switch (type) {
case CODEC_G_STATUS: /* get last status - we don't know it ... */
if (size != sizeof(int))
return -EFAULT;
*ival = 0;
break;
case CODEC_G_CODEC_MODE:
if (size != sizeof(int))
return -EFAULT;
*ival = 0;
break;
case CODEC_S_CODEC_MODE:
if (size != sizeof(int))
return -EFAULT;
if (*ival != 0)
return -EINVAL;
/* not needed, do nothing */
return 0;
case CODEC_G_VFE:
case CODEC_S_VFE:
return 0;
case CODEC_S_MMAP:
/* not available, give an error */
return -ENXIO;
default:
return -EINVAL;
}
return size;
}
/*
* Exit and unregister function:
*
* Deinitializes Zoran's JPEG processor
*/
static int zr36016_unset(struct videocodec *codec)
{
struct zr36016 *ptr = codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
if (ptr) {
/* do wee need some codec deinit here, too ???? */
zrdev_dbg(zr, "%s: finished codec #%d\n", ptr->name, ptr->num);
kfree(ptr);
codec->data = NULL;
zr36016_codecs--;
return 0;
}
return -EFAULT;
}
/*
* Setup and registry function:
*
* Initializes Zoran's JPEG processor
*
* Also sets pixel size, average code size, mode (compr./decompr.)
* (the given size is determined by the processor with the video interface)
*/
static int zr36016_setup(struct videocodec *codec)
{
struct zr36016 *ptr;
struct zoran *zr = videocodec_to_zoran(codec);
int res;
zrdev_dbg(zr, "zr36016: initializing VFE subsystem #%d.\n", zr36016_codecs);
if (zr36016_codecs == MAX_CODECS) {
zrdev_err(zr, "zr36016: Can't attach more codecs!\n");
return -ENOSPC;
}
//mem structure init
ptr = kzalloc(sizeof(*ptr), GFP_KERNEL);
codec->data = ptr;
if (!ptr)
return -ENOMEM;
snprintf(ptr->name, sizeof(ptr->name), "zr36016[%d]", zr36016_codecs);
ptr->num = zr36016_codecs++;
ptr->codec = codec;
//testing
res = zr36016_basic_test(ptr);
if (res < 0) {
zr36016_unset(codec);
return res;
}
//final setup
ptr->mode = CODEC_DO_COMPRESSION;
ptr->width = 768;
ptr->height = 288;
ptr->xdec = 1;
ptr->ydec = 0;
zr36016_init(ptr);
zrdev_dbg(zr, "%s: codec v%d attached and running\n",
ptr->name, ptr->version);
return 0;
}
static const struct videocodec zr36016_codec = {
.name = "zr36016",
.magic = 0L, /* magic not used */
.flags =
CODEC_FLAG_HARDWARE | CODEC_FLAG_VFE | CODEC_FLAG_ENCODER |
CODEC_FLAG_DECODER,
.type = CODEC_TYPE_ZR36016,
.setup = zr36016_setup, /* functionality */
.unset = zr36016_unset,
.set_mode = zr36016_set_mode,
.set_video = zr36016_set_video,
.control = zr36016_control,
/* others are not used */
};
/* HOOK IN DRIVER AS KERNEL MODULE */
int zr36016_init_module(void)
{
zr36016_codecs = 0;
return videocodec_register(&zr36016_codec);
}
void zr36016_cleanup_module(void)
{
if (zr36016_codecs) {
pr_debug("zr36016: something's wrong - %d codecs left somehow.\n",
zr36016_codecs);
}
videocodec_unregister(&zr36016_codec);
}
| linux-master | drivers/media/pci/zoran/zr36016.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Zoran zr36057/zr36067 PCI controller driver, for the
* Pinnacle/Miro DC10/DC10+/DC30/DC30+, Iomega Buz, Linux
* Media Labs LML33/LML33R10.
*
* This part handles card-specific data and detection
*
* Copyright (C) 2000 Serguei Miridonov <[email protected]>
*/
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/videodev2.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <media/v4l2-common.h>
#include <media/i2c/bt819.h>
#include "videocodec.h"
#include "zoran.h"
#include "zoran_card.h"
#include "zoran_device.h"
#include "zr36016.h"
#include "zr36050.h"
#include "zr36060.h"
extern const struct zoran_format zoran_formats[];
static int card[BUZ_MAX] = { [0 ... (BUZ_MAX - 1)] = -1 };
module_param_array(card, int, NULL, 0444);
MODULE_PARM_DESC(card, "Card type");
/* Default input and video norm at startup of the driver. */
static unsigned int default_input; /* default 0 = Composite, 1 = S-Video */
module_param(default_input, uint, 0444);
MODULE_PARM_DESC(default_input,
"Default input (0=Composite, 1=S-Video, 2=Internal)");
static int default_mux = 1; /* 6 Eyes input selection */
module_param(default_mux, int, 0644);
MODULE_PARM_DESC(default_mux,
"Default 6 Eyes mux setting (Input selection)");
static int default_norm; /* default 0 = PAL, 1 = NTSC 2 = SECAM */
module_param(default_norm, int, 0444);
MODULE_PARM_DESC(default_norm, "Default norm (0=PAL, 1=NTSC, 2=SECAM)");
/* /dev/videoN, -1 for autodetect */
static int video_nr[BUZ_MAX] = { [0 ... (BUZ_MAX - 1)] = -1 };
module_param_array(video_nr, int, NULL, 0444);
MODULE_PARM_DESC(video_nr, "Video device number (-1=Auto)");
/* 1=Pass through TV signal when device is not used */
/* 0=Show color bar when device is not used (LML33: only if lml33dpath=1) */
int pass_through;
module_param(pass_through, int, 0644);
MODULE_PARM_DESC(pass_through,
"Pass TV signal through to TV-out when idling");
int zr36067_debug = 1;
module_param_named(debug, zr36067_debug, int, 0644);
MODULE_PARM_DESC(debug, "Debug level (0-5)");
#define ZORAN_VERSION "0.10.1"
MODULE_DESCRIPTION("Zoran-36057/36067 JPEG codec driver");
MODULE_AUTHOR("Serguei Miridonov");
MODULE_LICENSE("GPL");
MODULE_VERSION(ZORAN_VERSION);
#define ZR_DEVICE(subven, subdev, data) { \
.vendor = PCI_VENDOR_ID_ZORAN, .device = PCI_DEVICE_ID_ZORAN_36057, \
.subvendor = (subven), .subdevice = (subdev), .driver_data = (data) }
static const struct pci_device_id zr36067_pci_tbl[] = {
ZR_DEVICE(PCI_VENDOR_ID_MIRO, PCI_DEVICE_ID_MIRO_DC10PLUS, DC10_PLUS),
ZR_DEVICE(PCI_VENDOR_ID_MIRO, PCI_DEVICE_ID_MIRO_DC30PLUS, DC30_PLUS),
ZR_DEVICE(PCI_VENDOR_ID_ELECTRONICDESIGNGMBH, PCI_DEVICE_ID_LML_33R10, LML33R10),
ZR_DEVICE(PCI_VENDOR_ID_IOMEGA, PCI_DEVICE_ID_IOMEGA_BUZ, BUZ),
ZR_DEVICE(PCI_ANY_ID, PCI_ANY_ID, NUM_CARDS),
{0}
};
MODULE_DEVICE_TABLE(pci, zr36067_pci_tbl);
static unsigned int zoran_num; /* number of cards found */
/* videocodec bus functions ZR36060 */
static u32 zr36060_read(struct videocodec *codec, u16 reg)
{
struct zoran *zr = (struct zoran *)codec->master_data->data;
__u32 data;
if (post_office_wait(zr) || post_office_write(zr, 0, 1, reg >> 8) ||
post_office_write(zr, 0, 2, reg & 0xff))
return -1;
data = post_office_read(zr, 0, 3) & 0xff;
return data;
}
static void zr36060_write(struct videocodec *codec, u16 reg, u32 val)
{
struct zoran *zr = (struct zoran *)codec->master_data->data;
if (post_office_wait(zr) || post_office_write(zr, 0, 1, reg >> 8) ||
post_office_write(zr, 0, 2, reg & 0xff))
return;
post_office_write(zr, 0, 3, val & 0xff);
}
/* videocodec bus functions ZR36050 */
static u32 zr36050_read(struct videocodec *codec, u16 reg)
{
struct zoran *zr = (struct zoran *)codec->master_data->data;
__u32 data;
if (post_office_wait(zr) || post_office_write(zr, 1, 0, reg >> 2)) // reg. HIGHBYTES
return -1;
data = post_office_read(zr, 0, reg & 0x03) & 0xff; // reg. LOWBYTES + read
return data;
}
static void zr36050_write(struct videocodec *codec, u16 reg, u32 val)
{
struct zoran *zr = (struct zoran *)codec->master_data->data;
if (post_office_wait(zr) || post_office_write(zr, 1, 0, reg >> 2)) // reg. HIGHBYTES
return;
post_office_write(zr, 0, reg & 0x03, val & 0xff); // reg. LOWBYTES + wr. data
}
/* videocodec bus functions ZR36016 */
static u32 zr36016_read(struct videocodec *codec, u16 reg)
{
struct zoran *zr = (struct zoran *)codec->master_data->data;
__u32 data;
if (post_office_wait(zr))
return -1;
data = post_office_read(zr, 2, reg & 0x03) & 0xff; // read
return data;
}
/* hack for in zoran_device.c */
void zr36016_write(struct videocodec *codec, u16 reg, u32 val)
{
struct zoran *zr = (struct zoran *)codec->master_data->data;
if (post_office_wait(zr))
return;
post_office_write(zr, 2, reg & 0x03, val & 0x0ff); // wr. data
}
/*
* Board specific information
*/
static void dc10_init(struct zoran *zr)
{
/* Pixel clock selection */
GPIO(zr, 4, 0);
GPIO(zr, 5, 1);
/* Enable the video bus sync signals */
GPIO(zr, 7, 0);
}
static void dc10plus_init(struct zoran *zr)
{
}
static void buz_init(struct zoran *zr)
{
/* some stuff from Iomega */
pci_write_config_dword(zr->pci_dev, 0xfc, 0x90680f15);
pci_write_config_dword(zr->pci_dev, 0x0c, 0x00012020);
pci_write_config_dword(zr->pci_dev, 0xe8, 0xc0200000);
}
static void lml33_init(struct zoran *zr)
{
GPIO(zr, 2, 1); // Set Composite input/output
}
static void avs6eyes_init(struct zoran *zr)
{
// AverMedia 6-Eyes original driver by Christer Weinigel
// Lifted straight from Christer's old driver and
// modified slightly by Martin Samuelsson.
int mux = default_mux; /* 1 = BT866, 7 = VID1 */
GPIO(zr, 4, 1); /* Bt866 SLEEP on */
udelay(2);
GPIO(zr, 0, 1); /* ZR36060 /RESET on */
GPIO(zr, 1, 0); /* ZR36060 /SLEEP on */
GPIO(zr, 2, mux & 1); /* MUX S0 */
GPIO(zr, 3, 0); /* /FRAME on */
GPIO(zr, 4, 0); /* Bt866 SLEEP off */
GPIO(zr, 5, mux & 2); /* MUX S1 */
GPIO(zr, 6, 0); /* ? */
GPIO(zr, 7, mux & 4); /* MUX S2 */
}
static const char *codecid_to_modulename(u16 codecid)
{
const char *name = NULL;
switch (codecid) {
case CODEC_TYPE_ZR36060:
name = "zr36060";
break;
case CODEC_TYPE_ZR36050:
name = "zr36050";
break;
case CODEC_TYPE_ZR36016:
name = "zr36016";
break;
}
return name;
}
static int codec_init(struct zoran *zr, u16 codecid)
{
switch (codecid) {
case CODEC_TYPE_ZR36060:
#ifdef CONFIG_VIDEO_ZORAN_ZR36060
return zr36060_init_module();
#else
pci_err(zr->pci_dev, "ZR36060 support is not enabled\n");
return -EINVAL;
#endif
break;
case CODEC_TYPE_ZR36050:
#ifdef CONFIG_VIDEO_ZORAN_DC30
return zr36050_init_module();
#else
pci_err(zr->pci_dev, "ZR36050 support is not enabled\n");
return -EINVAL;
#endif
break;
case CODEC_TYPE_ZR36016:
#ifdef CONFIG_VIDEO_ZORAN_DC30
return zr36016_init_module();
#else
pci_err(zr->pci_dev, "ZR36016 support is not enabled\n");
return -EINVAL;
#endif
break;
}
pci_err(zr->pci_dev, "unknown codec id %x\n", codecid);
return -EINVAL;
}
static void codec_exit(struct zoran *zr, u16 codecid)
{
switch (codecid) {
case CODEC_TYPE_ZR36060:
#ifdef CONFIG_VIDEO_ZORAN_ZR36060
zr36060_cleanup_module();
#endif
break;
case CODEC_TYPE_ZR36050:
#ifdef CONFIG_VIDEO_ZORAN_DC30
zr36050_cleanup_module();
#endif
break;
case CODEC_TYPE_ZR36016:
#ifdef CONFIG_VIDEO_ZORAN_DC30
zr36016_cleanup_module();
#endif
break;
}
}
static int videocodec_init(struct zoran *zr)
{
const char *codec_name, *vfe_name;
int result;
codec_name = codecid_to_modulename(zr->card.video_codec);
if (codec_name) {
result = codec_init(zr, zr->card.video_codec);
if (result < 0) {
pci_err(zr->pci_dev, "failed to load video codec %s: %d\n",
codec_name, result);
return result;
}
}
vfe_name = codecid_to_modulename(zr->card.video_vfe);
if (vfe_name) {
result = codec_init(zr, zr->card.video_vfe);
if (result < 0) {
pci_err(zr->pci_dev, "failed to load video vfe %s: %d\n",
vfe_name, result);
if (codec_name)
codec_exit(zr, zr->card.video_codec);
return result;
}
}
return 0;
}
static void videocodec_exit(struct zoran *zr)
{
if (zr->card.video_codec != CODEC_TYPE_NONE)
codec_exit(zr, zr->card.video_codec);
if (zr->card.video_vfe != CODEC_TYPE_NONE)
codec_exit(zr, zr->card.video_vfe);
}
static const struct tvnorm f50sqpixel = { 944, 768, 83, 880, 625, 576, 16 };
static const struct tvnorm f60sqpixel = { 780, 640, 51, 716, 525, 480, 12 };
static const struct tvnorm f50ccir601 = { 864, 720, 75, 804, 625, 576, 18 };
static const struct tvnorm f60ccir601 = { 858, 720, 57, 788, 525, 480, 16 };
static const struct tvnorm f50ccir601_lml33 = { 864, 720, 75 + 34, 804, 625, 576, 18 };
static const struct tvnorm f60ccir601_lml33 = { 858, 720, 57 + 34, 788, 525, 480, 16 };
/* The DC10 (57/16/50) uses VActive as HSync, so h_start must be 0 */
static const struct tvnorm f50sqpixel_dc10 = { 944, 768, 0, 880, 625, 576, 0 };
static const struct tvnorm f60sqpixel_dc10 = { 780, 640, 0, 716, 525, 480, 12 };
/*
* FIXME: I cannot swap U and V in saa7114, so i do one pixel left shift in zoran (75 -> 74)
* (Maxim Yevtyushkin <[email protected]>)
*/
static const struct tvnorm f50ccir601_lm33r10 = { 864, 720, 74 + 54, 804, 625, 576, 18 };
static const struct tvnorm f60ccir601_lm33r10 = { 858, 720, 56 + 54, 788, 525, 480, 16 };
/*
* FIXME: The ks0127 seem incapable of swapping U and V, too, which is why I copy Maxim's left
* shift hack for the 6 Eyes.
*
* Christer's driver used the unshifted norms, though...
* /Sam
*/
static const struct tvnorm f50ccir601_avs6eyes = { 864, 720, 74, 804, 625, 576, 18 };
static const struct tvnorm f60ccir601_avs6eyes = { 858, 720, 56, 788, 525, 480, 16 };
static const unsigned short vpx3220_addrs[] = { 0x43, 0x47, I2C_CLIENT_END };
static const unsigned short saa7110_addrs[] = { 0x4e, 0x4f, I2C_CLIENT_END };
static const unsigned short saa7111_addrs[] = { 0x25, 0x24, I2C_CLIENT_END };
static const unsigned short saa7114_addrs[] = { 0x21, 0x20, I2C_CLIENT_END };
static const unsigned short adv717x_addrs[] = { 0x6a, 0x6b, 0x2a, 0x2b, I2C_CLIENT_END };
static const unsigned short ks0127_addrs[] = { 0x6c, 0x6d, I2C_CLIENT_END };
static const unsigned short saa7185_addrs[] = { 0x44, I2C_CLIENT_END };
static const unsigned short bt819_addrs[] = { 0x45, I2C_CLIENT_END };
static const unsigned short bt856_addrs[] = { 0x44, I2C_CLIENT_END };
static const unsigned short bt866_addrs[] = { 0x44, I2C_CLIENT_END };
static struct card_info zoran_cards[NUM_CARDS] = {
{
.type = DC10_OLD,
.name = "DC10(old)",
.i2c_decoder = "vpx3220a",
.addrs_decoder = vpx3220_addrs,
.video_codec = CODEC_TYPE_ZR36050,
.video_vfe = CODEC_TYPE_ZR36016,
.inputs = 3,
.input = {
{ 1, "Composite" },
{ 2, "S-Video" },
{ 0, "Internal/comp" }
},
.norms = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM,
.tvn = {
&f50sqpixel_dc10,
&f60sqpixel_dc10,
&f50sqpixel_dc10
},
.jpeg_int = 0,
.vsync_int = ZR36057_ISR_GIRQ1,
.gpio = { 2, 1, -1, 3, 7, 0, 4, 5 },
.gpio_pol = { 0, 0, 0, 1, 0, 0, 0, 0 },
.gpcs = { -1, 0 },
.vfe_pol = { 0, 0, 0, 0, 0, 0, 0, 0 },
.gws_not_connected = 0,
.input_mux = 0,
.init = &dc10_init,
}, {
.type = DC10_NEW,
.name = "DC10(new)",
.i2c_decoder = "saa7110",
.addrs_decoder = saa7110_addrs,
.i2c_encoder = "adv7175",
.addrs_encoder = adv717x_addrs,
.video_codec = CODEC_TYPE_ZR36060,
.inputs = 3,
.input = {
{ 0, "Composite" },
{ 7, "S-Video" },
{ 5, "Internal/comp" }
},
.norms = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM,
.tvn = {
&f50sqpixel,
&f60sqpixel,
&f50sqpixel},
.jpeg_int = ZR36057_ISR_GIRQ0,
.vsync_int = ZR36057_ISR_GIRQ1,
.gpio = { 3, 0, 6, 1, 2, -1, 4, 5 },
.gpio_pol = { 0, 0, 0, 0, 0, 0, 0, 0 },
.gpcs = { -1, 1},
.vfe_pol = { 1, 1, 1, 1, 0, 0, 0, 0 },
.gws_not_connected = 0,
.input_mux = 0,
.init = &dc10plus_init,
}, {
.type = DC10_PLUS,
.name = "DC10_PLUS",
.i2c_decoder = "saa7110",
.addrs_decoder = saa7110_addrs,
.i2c_encoder = "adv7175",
.addrs_encoder = adv717x_addrs,
.video_codec = CODEC_TYPE_ZR36060,
.inputs = 3,
.input = {
{ 0, "Composite" },
{ 7, "S-Video" },
{ 5, "Internal/comp" }
},
.norms = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM,
.tvn = {
&f50sqpixel,
&f60sqpixel,
&f50sqpixel
},
.jpeg_int = ZR36057_ISR_GIRQ0,
.vsync_int = ZR36057_ISR_GIRQ1,
.gpio = { 3, 0, 6, 1, 2, -1, 4, 5 },
.gpio_pol = { 0, 0, 0, 0, 0, 0, 0, 0 },
.gpcs = { -1, 1 },
.vfe_pol = { 1, 1, 1, 1, 0, 0, 0, 0 },
.gws_not_connected = 0,
.input_mux = 0,
.init = &dc10plus_init,
}, {
.type = DC30,
.name = "DC30",
.i2c_decoder = "vpx3220a",
.addrs_decoder = vpx3220_addrs,
.i2c_encoder = "adv7175",
.addrs_encoder = adv717x_addrs,
.video_codec = CODEC_TYPE_ZR36050,
.video_vfe = CODEC_TYPE_ZR36016,
.inputs = 3,
.input = {
{ 1, "Composite" },
{ 2, "S-Video" },
{ 0, "Internal/comp" }
},
.norms = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM,
.tvn = {
&f50sqpixel_dc10,
&f60sqpixel_dc10,
&f50sqpixel_dc10
},
.jpeg_int = 0,
.vsync_int = ZR36057_ISR_GIRQ1,
.gpio = { 2, 1, -1, 3, 7, 0, 4, 5 },
.gpio_pol = { 0, 0, 0, 1, 0, 0, 0, 0 },
.gpcs = { -1, 0 },
.vfe_pol = { 0, 0, 0, 0, 0, 0, 0, 0 },
.gws_not_connected = 0,
.input_mux = 0,
.init = &dc10_init,
}, {
.type = DC30_PLUS,
.name = "DC30_PLUS",
.i2c_decoder = "vpx3220a",
.addrs_decoder = vpx3220_addrs,
.i2c_encoder = "adv7175",
.addrs_encoder = adv717x_addrs,
.video_codec = CODEC_TYPE_ZR36050,
.video_vfe = CODEC_TYPE_ZR36016,
.inputs = 3,
.input = {
{ 1, "Composite" },
{ 2, "S-Video" },
{ 0, "Internal/comp" }
},
.norms = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM,
.tvn = {
&f50sqpixel_dc10,
&f60sqpixel_dc10,
&f50sqpixel_dc10
},
.jpeg_int = 0,
.vsync_int = ZR36057_ISR_GIRQ1,
.gpio = { 2, 1, -1, 3, 7, 0, 4, 5 },
.gpio_pol = { 0, 0, 0, 1, 0, 0, 0, 0 },
.gpcs = { -1, 0 },
.vfe_pol = { 0, 0, 0, 0, 0, 0, 0, 0 },
.gws_not_connected = 0,
.input_mux = 0,
.init = &dc10_init,
}, {
.type = LML33,
.name = "LML33",
.i2c_decoder = "bt819a",
.addrs_decoder = bt819_addrs,
.i2c_encoder = "bt856",
.addrs_encoder = bt856_addrs,
.video_codec = CODEC_TYPE_ZR36060,
.inputs = 2,
.input = {
{ 0, "Composite" },
{ 7, "S-Video" }
},
.norms = V4L2_STD_NTSC | V4L2_STD_PAL,
.tvn = {
&f50ccir601_lml33,
&f60ccir601_lml33,
NULL
},
.jpeg_int = ZR36057_ISR_GIRQ1,
.vsync_int = ZR36057_ISR_GIRQ0,
.gpio = { 1, -1, 3, 5, 7, -1, -1, -1 },
.gpio_pol = { 0, 0, 0, 0, 1, 0, 0, 0 },
.gpcs = { 3, 1 },
.vfe_pol = { 1, 1, 0, 0, 0, 1, 0, 0 },
.gws_not_connected = 1,
.input_mux = 0,
.init = &lml33_init,
}, {
.type = LML33R10,
.name = "LML33R10",
.i2c_decoder = "saa7114",
.addrs_decoder = saa7114_addrs,
.i2c_encoder = "adv7170",
.addrs_encoder = adv717x_addrs,
.video_codec = CODEC_TYPE_ZR36060,
.inputs = 2,
.input = {
{ 0, "Composite" },
{ 7, "S-Video" }
},
.norms = V4L2_STD_NTSC | V4L2_STD_PAL,
.tvn = {
&f50ccir601_lm33r10,
&f60ccir601_lm33r10,
NULL
},
.jpeg_int = ZR36057_ISR_GIRQ1,
.vsync_int = ZR36057_ISR_GIRQ0,
.gpio = { 1, -1, 3, 5, 7, -1, -1, -1 },
.gpio_pol = { 0, 0, 0, 0, 1, 0, 0, 0 },
.gpcs = { 3, 1 },
.vfe_pol = { 1, 1, 0, 0, 0, 1, 0, 0 },
.gws_not_connected = 1,
.input_mux = 0,
.init = &lml33_init,
}, {
.type = BUZ,
.name = "Buz",
.i2c_decoder = "saa7111",
.addrs_decoder = saa7111_addrs,
.i2c_encoder = "saa7185",
.addrs_encoder = saa7185_addrs,
.video_codec = CODEC_TYPE_ZR36060,
.inputs = 2,
.input = {
{ 3, "Composite" },
{ 7, "S-Video" }
},
.norms = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM,
.tvn = {
&f50ccir601,
&f60ccir601,
&f50ccir601
},
.jpeg_int = ZR36057_ISR_GIRQ1,
.vsync_int = ZR36057_ISR_GIRQ0,
.gpio = { 1, -1, 3, -1, -1, -1, -1, -1 },
.gpio_pol = { 0, 0, 0, 0, 0, 0, 0, 0 },
.gpcs = { 3, 1 },
.vfe_pol = { 1, 1, 0, 0, 0, 1, 0, 0 },
.gws_not_connected = 1,
.input_mux = 0,
.init = &buz_init,
}, {
.type = AVS6EYES,
.name = "6-Eyes",
/*
* AverMedia chose not to brand the 6-Eyes. Thus it can't be
* autodetected, and requires card=x.
*/
.i2c_decoder = "ks0127",
.addrs_decoder = ks0127_addrs,
.i2c_encoder = "bt866",
.addrs_encoder = bt866_addrs,
.video_codec = CODEC_TYPE_ZR36060,
.inputs = 10,
.input = {
{ 0, "Composite 1" },
{ 1, "Composite 2" },
{ 2, "Composite 3" },
{ 4, "Composite 4" },
{ 5, "Composite 5" },
{ 6, "Composite 6" },
{ 8, "S-Video 1" },
{ 9, "S-Video 2" },
{10, "S-Video 3" },
{15, "YCbCr" }
},
.norms = V4L2_STD_NTSC | V4L2_STD_PAL,
.tvn = {
&f50ccir601_avs6eyes,
&f60ccir601_avs6eyes,
NULL
},
.jpeg_int = ZR36057_ISR_GIRQ1,
.vsync_int = ZR36057_ISR_GIRQ0,
.gpio = { 1, 0, 3, -1, -1, -1, -1, -1 },// Validity unknown /Sam
.gpio_pol = { 0, 0, 0, 0, 0, 0, 0, 0 }, // Validity unknown /Sam
.gpcs = { 3, 1 }, // Validity unknown /Sam
.vfe_pol = { 1, 0, 0, 0, 0, 1, 0, 0 }, // Validity unknown /Sam
.gws_not_connected = 1,
.input_mux = 1,
.init = &avs6eyes_init,
}
};
/*
* I2C functions
*/
/* software I2C functions */
static int zoran_i2c_getsda(void *data)
{
struct zoran *zr = (struct zoran *)data;
return (btread(ZR36057_I2CBR) >> 1) & 1;
}
static int zoran_i2c_getscl(void *data)
{
struct zoran *zr = (struct zoran *)data;
return btread(ZR36057_I2CBR) & 1;
}
static void zoran_i2c_setsda(void *data, int state)
{
struct zoran *zr = (struct zoran *)data;
if (state)
zr->i2cbr |= 2;
else
zr->i2cbr &= ~2;
btwrite(zr->i2cbr, ZR36057_I2CBR);
}
static void zoran_i2c_setscl(void *data, int state)
{
struct zoran *zr = (struct zoran *)data;
if (state)
zr->i2cbr |= 1;
else
zr->i2cbr &= ~1;
btwrite(zr->i2cbr, ZR36057_I2CBR);
}
static const struct i2c_algo_bit_data zoran_i2c_bit_data_template = {
.setsda = zoran_i2c_setsda,
.setscl = zoran_i2c_setscl,
.getsda = zoran_i2c_getsda,
.getscl = zoran_i2c_getscl,
.udelay = 10,
.timeout = 100,
};
static int zoran_register_i2c(struct zoran *zr)
{
zr->i2c_algo = zoran_i2c_bit_data_template;
zr->i2c_algo.data = zr;
strscpy(zr->i2c_adapter.name, ZR_DEVNAME(zr),
sizeof(zr->i2c_adapter.name));
i2c_set_adapdata(&zr->i2c_adapter, &zr->v4l2_dev);
zr->i2c_adapter.algo_data = &zr->i2c_algo;
zr->i2c_adapter.dev.parent = &zr->pci_dev->dev;
return i2c_bit_add_bus(&zr->i2c_adapter);
}
static void zoran_unregister_i2c(struct zoran *zr)
{
i2c_del_adapter(&zr->i2c_adapter);
}
/* Check a zoran_params struct for correctness, insert default params */
int zoran_check_jpg_settings(struct zoran *zr,
struct zoran_jpg_settings *settings, int try)
{
int err = 0, err0 = 0;
pci_dbg(zr->pci_dev, "%s - dec: %d, Hdcm: %d, Vdcm: %d, Tdcm: %d\n",
__func__, settings->decimation, settings->hor_dcm,
settings->ver_dcm, settings->tmp_dcm);
pci_dbg(zr->pci_dev, "%s - x: %d, y: %d, w: %d, y: %d\n", __func__,
settings->img_x, settings->img_y,
settings->img_width, settings->img_height);
/* Check decimation, set default values for decimation = 1, 2, 4 */
switch (settings->decimation) {
case 1:
settings->hor_dcm = 1;
settings->ver_dcm = 1;
settings->tmp_dcm = 1;
settings->field_per_buff = 2;
settings->img_x = 0;
settings->img_y = 0;
settings->img_width = BUZ_MAX_WIDTH;
settings->img_height = BUZ_MAX_HEIGHT / 2;
break;
case 2:
settings->hor_dcm = 2;
settings->ver_dcm = 1;
settings->tmp_dcm = 2;
settings->field_per_buff = 1;
settings->img_x = (BUZ_MAX_WIDTH == 720) ? 8 : 0;
settings->img_y = 0;
settings->img_width =
(BUZ_MAX_WIDTH == 720) ? 704 : BUZ_MAX_WIDTH;
settings->img_height = BUZ_MAX_HEIGHT / 2;
break;
case 4:
if (zr->card.type == DC10_NEW) {
pci_dbg(zr->pci_dev,
"%s - HDec by 4 is not supported on the DC10\n",
__func__);
err0++;
break;
}
settings->hor_dcm = 4;
settings->ver_dcm = 2;
settings->tmp_dcm = 2;
settings->field_per_buff = 1;
settings->img_x = (BUZ_MAX_WIDTH == 720) ? 8 : 0;
settings->img_y = 0;
settings->img_width =
(BUZ_MAX_WIDTH == 720) ? 704 : BUZ_MAX_WIDTH;
settings->img_height = BUZ_MAX_HEIGHT / 2;
break;
case 0:
/* We have to check the data the user has set */
if (settings->hor_dcm != 1 && settings->hor_dcm != 2 &&
(zr->card.type == DC10_NEW || settings->hor_dcm != 4)) {
settings->hor_dcm = clamp(settings->hor_dcm, 1, 2);
err0++;
}
if (settings->ver_dcm != 1 && settings->ver_dcm != 2) {
settings->ver_dcm = clamp(settings->ver_dcm, 1, 2);
err0++;
}
if (settings->tmp_dcm != 1 && settings->tmp_dcm != 2) {
settings->tmp_dcm = clamp(settings->tmp_dcm, 1, 2);
err0++;
}
if (settings->field_per_buff != 1 &&
settings->field_per_buff != 2) {
settings->field_per_buff = clamp(settings->field_per_buff, 1, 2);
err0++;
}
if (settings->img_x < 0) {
settings->img_x = 0;
err0++;
}
if (settings->img_y < 0) {
settings->img_y = 0;
err0++;
}
if (settings->img_width < 0 || settings->img_width > BUZ_MAX_WIDTH) {
settings->img_width = clamp(settings->img_width, 0, (int)BUZ_MAX_WIDTH);
err0++;
}
if (settings->img_height < 0 || settings->img_height > BUZ_MAX_HEIGHT / 2) {
settings->img_height = clamp(settings->img_height, 0, BUZ_MAX_HEIGHT / 2);
err0++;
}
if (settings->img_x + settings->img_width > BUZ_MAX_WIDTH) {
settings->img_x = BUZ_MAX_WIDTH - settings->img_width;
err0++;
}
if (settings->img_y + settings->img_height > BUZ_MAX_HEIGHT / 2) {
settings->img_y = BUZ_MAX_HEIGHT / 2 - settings->img_height;
err0++;
}
if (settings->img_width % (16 * settings->hor_dcm) != 0) {
settings->img_width -= settings->img_width % (16 * settings->hor_dcm);
if (settings->img_width == 0)
settings->img_width = 16 * settings->hor_dcm;
err0++;
}
if (settings->img_height % (8 * settings->ver_dcm) != 0) {
settings->img_height -= settings->img_height % (8 * settings->ver_dcm);
if (settings->img_height == 0)
settings->img_height = 8 * settings->ver_dcm;
err0++;
}
if (!try && err0) {
pci_err(zr->pci_dev, "%s - error in params for decimation = 0\n", __func__);
err++;
}
break;
default:
pci_err(zr->pci_dev, "%s - decimation = %d, must be 0, 1, 2 or 4\n",
__func__, settings->decimation);
err++;
break;
}
if (settings->jpg_comp.quality > 100)
settings->jpg_comp.quality = 100;
if (settings->jpg_comp.quality < 5)
settings->jpg_comp.quality = 5;
if (settings->jpg_comp.APPn < 0)
settings->jpg_comp.APPn = 0;
if (settings->jpg_comp.APPn > 15)
settings->jpg_comp.APPn = 15;
if (settings->jpg_comp.APP_len < 0)
settings->jpg_comp.APP_len = 0;
if (settings->jpg_comp.APP_len > 60)
settings->jpg_comp.APP_len = 60;
if (settings->jpg_comp.COM_len < 0)
settings->jpg_comp.COM_len = 0;
if (settings->jpg_comp.COM_len > 60)
settings->jpg_comp.COM_len = 60;
if (err)
return -EINVAL;
return 0;
}
static int zoran_init_video_device(struct zoran *zr, struct video_device *video_dev, int dir)
{
int err;
/* Now add the template and register the device unit. */
*video_dev = zoran_template;
video_dev->v4l2_dev = &zr->v4l2_dev;
video_dev->lock = &zr->lock;
video_dev->device_caps = V4L2_CAP_STREAMING | dir;
strscpy(video_dev->name, ZR_DEVNAME(zr), sizeof(video_dev->name));
video_dev->vfl_dir = VFL_DIR_RX;
zoran_queue_init(zr, &zr->vq, V4L2_BUF_TYPE_VIDEO_CAPTURE);
err = video_register_device(video_dev, VFL_TYPE_VIDEO, video_nr[zr->id]);
if (err < 0)
return err;
video_set_drvdata(video_dev, zr);
return 0;
}
static void zoran_exit_video_devices(struct zoran *zr)
{
video_unregister_device(zr->video_dev);
kfree(zr->video_dev);
}
static int zoran_init_video_devices(struct zoran *zr)
{
int err;
zr->video_dev = video_device_alloc();
if (!zr->video_dev)
return -ENOMEM;
err = zoran_init_video_device(zr, zr->video_dev, V4L2_CAP_VIDEO_CAPTURE);
if (err)
kfree(zr->video_dev);
return err;
}
/*
* v4l2_device_unregister() will care about removing zr->encoder/zr->decoder
* via v4l2_i2c_subdev_unregister()
*/
static int zoran_i2c_init(struct zoran *zr)
{
int err;
pci_info(zr->pci_dev, "Initializing i2c bus...\n");
err = zoran_register_i2c(zr);
if (err) {
pci_err(zr->pci_dev, "%s - cannot initialize i2c bus\n", __func__);
return err;
}
zr->decoder = v4l2_i2c_new_subdev(&zr->v4l2_dev, &zr->i2c_adapter,
zr->card.i2c_decoder, 0,
zr->card.addrs_decoder);
if (!zr->decoder) {
pci_err(zr->pci_dev, "Fail to get decoder %s\n", zr->card.i2c_decoder);
err = -EINVAL;
goto error_decoder;
}
if (zr->card.i2c_encoder) {
zr->encoder = v4l2_i2c_new_subdev(&zr->v4l2_dev, &zr->i2c_adapter,
zr->card.i2c_encoder, 0,
zr->card.addrs_encoder);
if (!zr->encoder) {
pci_err(zr->pci_dev, "Fail to get encoder %s\n", zr->card.i2c_encoder);
err = -EINVAL;
goto error_decoder;
}
}
return 0;
error_decoder:
zoran_unregister_i2c(zr);
return err;
}
static void zoran_i2c_exit(struct zoran *zr)
{
zoran_unregister_i2c(zr);
}
void zoran_open_init_params(struct zoran *zr)
{
int i;
zr->v4l_settings.width = 192;
zr->v4l_settings.height = 144;
zr->v4l_settings.format = &zoran_formats[7]; /* YUY2 - YUV-4:2:2 packed */
zr->v4l_settings.bytesperline = zr->v4l_settings.width *
((zr->v4l_settings.format->depth + 7) / 8);
/* Set necessary params and call zoran_check_jpg_settings to set the defaults */
zr->jpg_settings.decimation = 1;
zr->jpg_settings.jpg_comp.quality = 50; /* default compression factor 8 */
if (zr->card.type != BUZ)
zr->jpg_settings.odd_even = 1;
else
zr->jpg_settings.odd_even = 0;
zr->jpg_settings.jpg_comp.APPn = 0;
zr->jpg_settings.jpg_comp.APP_len = 0; /* No APPn marker */
memset(zr->jpg_settings.jpg_comp.APP_data, 0,
sizeof(zr->jpg_settings.jpg_comp.APP_data));
zr->jpg_settings.jpg_comp.COM_len = 0; /* No COM marker */
memset(zr->jpg_settings.jpg_comp.COM_data, 0,
sizeof(zr->jpg_settings.jpg_comp.COM_data));
zr->jpg_settings.jpg_comp.jpeg_markers =
V4L2_JPEG_MARKER_DHT | V4L2_JPEG_MARKER_DQT;
i = zoran_check_jpg_settings(zr, &zr->jpg_settings, 0);
if (i)
pci_err(zr->pci_dev, "%s internal error\n", __func__);
zr->buffer_size = zr->v4l_settings.bytesperline * zr->v4l_settings.height;
clear_interrupt_counters(zr);
}
static int zr36057_init(struct zoran *zr)
{
int j, err;
pci_info(zr->pci_dev, "initializing card[%d]\n", zr->id);
/* Avoid nonsense settings from user for default input/norm */
if (default_norm < 0 || default_norm > 2)
default_norm = 0;
if (default_norm == 0) {
zr->norm = V4L2_STD_PAL;
zr->timing = zr->card.tvn[ZR_NORM_PAL];
} else if (default_norm == 1) {
zr->norm = V4L2_STD_NTSC;
zr->timing = zr->card.tvn[ZR_NORM_NTSC];
} else {
zr->norm = V4L2_STD_SECAM;
zr->timing = zr->card.tvn[ZR_NORM_SECAM];
}
if (!zr->timing) {
pci_warn(zr->pci_dev,
"%s - default TV standard not supported by hardware. PAL will be used.\n",
__func__);
zr->norm = V4L2_STD_PAL;
zr->timing = zr->card.tvn[ZR_NORM_PAL];
}
if (default_input > zr->card.inputs - 1) {
pci_warn(zr->pci_dev, "default_input value %d out of range (0-%d)\n",
default_input, zr->card.inputs - 1);
default_input = 0;
}
zr->input = default_input;
/* default setup (will be repeated at every open) */
zoran_open_init_params(zr);
/* allocate memory *before* doing anything to the hardware in case allocation fails */
zr->stat_com = dma_alloc_coherent(&zr->pci_dev->dev,
BUZ_NUM_STAT_COM * sizeof(u32),
&zr->p_sc, GFP_KERNEL);
if (!zr->stat_com)
return -ENOMEM;
for (j = 0; j < BUZ_NUM_STAT_COM; j++)
zr->stat_com[j] = cpu_to_le32(1); /* mark as unavailable to zr36057 */
zr->stat_comb = dma_alloc_coherent(&zr->pci_dev->dev,
BUZ_NUM_STAT_COM * sizeof(u32) * 2,
&zr->p_scb, GFP_KERNEL);
if (!zr->stat_comb) {
err = -ENOMEM;
goto exit_statcom;
}
err = zoran_init_video_devices(zr);
if (err)
goto exit_statcomb;
zoran_init_hardware(zr);
if (!pass_through) {
decoder_call(zr, video, s_stream, 0);
encoder_call(zr, video, s_routing, 2, 0, 0);
}
zr->initialized = 1;
return 0;
exit_statcomb:
dma_free_coherent(&zr->pci_dev->dev, BUZ_NUM_STAT_COM * sizeof(u32) * 2,
zr->stat_comb, zr->p_scb);
exit_statcom:
dma_free_coherent(&zr->pci_dev->dev, BUZ_NUM_STAT_COM * sizeof(u32),
zr->stat_com, zr->p_sc);
return err;
}
static void zoran_remove(struct pci_dev *pdev)
{
struct v4l2_device *v4l2_dev = dev_get_drvdata(&pdev->dev);
struct zoran *zr = to_zoran(v4l2_dev);
if (!zr->initialized)
goto exit_free;
debugfs_remove_recursive(zr->dbgfs_dir);
zoran_queue_exit(zr);
/* unregister videocodec bus */
if (zr->codec)
videocodec_detach(zr->codec);
if (zr->vfe)
videocodec_detach(zr->vfe);
videocodec_exit(zr);
/* unregister i2c bus */
zoran_i2c_exit(zr);
/* disable PCI bus-mastering */
zoran_set_pci_master(zr, 0);
/* put chip into reset */
btwrite(0, ZR36057_SPGPPCR);
pci_free_irq(zr->pci_dev, 0, zr);
/* unmap and free memory */
dma_free_coherent(&zr->pci_dev->dev, BUZ_NUM_STAT_COM * sizeof(u32),
zr->stat_com, zr->p_sc);
dma_free_coherent(&zr->pci_dev->dev, BUZ_NUM_STAT_COM * sizeof(u32) * 2,
zr->stat_comb, zr->p_scb);
pci_release_regions(pdev);
pci_disable_device(zr->pci_dev);
zoran_exit_video_devices(zr);
exit_free:
v4l2_ctrl_handler_free(&zr->hdl);
v4l2_device_unregister(&zr->v4l2_dev);
}
void zoran_vdev_release(struct video_device *vdev)
{
kfree(vdev);
}
static struct videocodec_master *zoran_setup_videocodec(struct zoran *zr,
int type)
{
struct videocodec_master *m = NULL;
m = devm_kmalloc(&zr->pci_dev->dev, sizeof(*m), GFP_KERNEL);
if (!m)
return m;
/*
* magic and type are unused for master struct. Makes sense only at codec structs.
* In the past, .type were initialized to the old V4L1 .hardware value,
* as VID_HARDWARE_ZR36067
*/
m->magic = 0L;
m->type = 0;
m->flags = CODEC_FLAG_ENCODER | CODEC_FLAG_DECODER;
strscpy(m->name, ZR_DEVNAME(zr), sizeof(m->name));
m->data = zr;
switch (type) {
case CODEC_TYPE_ZR36060:
m->readreg = zr36060_read;
m->writereg = zr36060_write;
m->flags |= CODEC_FLAG_JPEG | CODEC_FLAG_VFE;
break;
case CODEC_TYPE_ZR36050:
m->readreg = zr36050_read;
m->writereg = zr36050_write;
m->flags |= CODEC_FLAG_JPEG;
break;
case CODEC_TYPE_ZR36016:
m->readreg = zr36016_read;
m->writereg = zr36016_write;
m->flags |= CODEC_FLAG_VFE;
break;
}
return m;
}
static void zoran_subdev_notify(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
struct zoran *zr = to_zoran(sd->v4l2_dev);
/*
* Bt819 needs to reset its FIFO buffer using #FRST pin and
* LML33 card uses GPIO(7) for that.
*/
if (cmd == BT819_FIFO_RESET_LOW)
GPIO(zr, 7, 0);
else if (cmd == BT819_FIFO_RESET_HIGH)
GPIO(zr, 7, 1);
}
static int zoran_video_set_ctrl(struct v4l2_ctrl *ctrl)
{
struct zoran *zr = container_of(ctrl->handler, struct zoran, hdl);
switch (ctrl->id) {
case V4L2_CID_JPEG_COMPRESSION_QUALITY:
zr->jpg_settings.jpg_comp.quality = ctrl->val;
return zoran_check_jpg_settings(zr, &zr->jpg_settings, 0);
default:
return -EINVAL;
}
return 0;
}
static const struct v4l2_ctrl_ops zoran_video_ctrl_ops = {
.s_ctrl = zoran_video_set_ctrl,
};
static int zoran_debugfs_show(struct seq_file *seq, void *v)
{
struct zoran *zr = seq->private;
seq_printf(seq, "Running mode %x\n", zr->running);
seq_printf(seq, "Codec mode %x\n", zr->codec_mode);
seq_printf(seq, "Norm %llx\n", zr->norm);
seq_printf(seq, "Input %d\n", zr->input);
seq_printf(seq, "Buffersize %d\n", zr->buffer_size);
seq_printf(seq, "V4L width %dx%d\n", zr->v4l_settings.width, zr->v4l_settings.height);
seq_printf(seq, "V4L bytesperline %d\n", zr->v4l_settings.bytesperline);
seq_printf(seq, "JPG decimation %u\n", zr->jpg_settings.decimation);
seq_printf(seq, "JPG hor_dcm %u\n", zr->jpg_settings.hor_dcm);
seq_printf(seq, "JPG ver_dcm %u\n", zr->jpg_settings.ver_dcm);
seq_printf(seq, "JPG tmp_dcm %u\n", zr->jpg_settings.tmp_dcm);
seq_printf(seq, "JPG odd_even %u\n", zr->jpg_settings.odd_even);
seq_printf(seq, "JPG crop %dx%d %d %d\n",
zr->jpg_settings.img_x,
zr->jpg_settings.img_y,
zr->jpg_settings.img_width,
zr->jpg_settings.img_height);
seq_printf(seq, "Prepared %u\n", zr->prepared);
seq_printf(seq, "Queued %u\n", zr->queued);
videocodec_debugfs_show(seq);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(zoran_debugfs);
/*
* Scan for a Buz card (actually for the PCI controller ZR36057),
* request the irq and map the io memory
*/
static int zoran_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
unsigned char latency, need_latency;
struct zoran *zr;
int result;
struct videocodec_master *master_vfe = NULL;
struct videocodec_master *master_codec = NULL;
int card_num;
unsigned int nr;
int err;
pci_info(pdev, "Zoran MJPEG board driver version %s\n", ZORAN_VERSION);
/* some mainboards might not do PCI-PCI data transfer well */
if (pci_pci_problems & (PCIPCI_FAIL | PCIAGP_FAIL | PCIPCI_ALIMAGIK))
pci_warn(pdev, "%s: chipset does not support reliable PCI-PCI DMA\n",
ZORAN_NAME);
err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (err)
return err;
err = vb2_dma_contig_set_max_seg_size(&pdev->dev, U32_MAX);
if (err)
return err;
nr = zoran_num++;
if (nr >= BUZ_MAX) {
pci_err(pdev, "driver limited to %d card(s) maximum\n", BUZ_MAX);
return -ENOENT;
}
zr = devm_kzalloc(&pdev->dev, sizeof(*zr), GFP_KERNEL);
if (!zr)
return -ENOMEM;
zr->v4l2_dev.notify = zoran_subdev_notify;
if (v4l2_device_register(&pdev->dev, &zr->v4l2_dev))
goto zr_free_mem;
zr->pci_dev = pdev;
zr->id = nr;
snprintf(ZR_DEVNAME(zr), sizeof(ZR_DEVNAME(zr)), "MJPEG[%u]", zr->id);
if (v4l2_ctrl_handler_init(&zr->hdl, 10))
goto zr_unreg;
zr->v4l2_dev.ctrl_handler = &zr->hdl;
v4l2_ctrl_new_std(&zr->hdl, &zoran_video_ctrl_ops,
V4L2_CID_JPEG_COMPRESSION_QUALITY, 0,
100, 1, 50);
spin_lock_init(&zr->spinlock);
mutex_init(&zr->lock);
if (pci_enable_device(pdev))
goto zr_unreg;
zr->revision = zr->pci_dev->revision;
pci_info(zr->pci_dev, "Zoran ZR360%c7 (rev %d), irq: %d, memory: 0x%08llx\n",
zr->revision < 2 ? '5' : '6', zr->revision,
zr->pci_dev->irq, (uint64_t)pci_resource_start(zr->pci_dev, 0));
if (zr->revision >= 2)
pci_info(zr->pci_dev, "Subsystem vendor=0x%04x id=0x%04x\n",
zr->pci_dev->subsystem_vendor, zr->pci_dev->subsystem_device);
/* Use auto-detected card type? */
if (card[nr] == -1) {
if (zr->revision < 2) {
pci_err(pdev, "No card type specified, please use the card=X module parameter\n");
pci_err(pdev, "It is not possible to auto-detect ZR36057 based cards\n");
goto zr_unreg;
}
card_num = ent->driver_data;
if (card_num >= NUM_CARDS) {
pci_err(pdev, "Unknown card, try specifying card=X module parameter\n");
goto zr_unreg;
}
pci_info(zr->pci_dev, "%s() - card %s detected\n", __func__,
zoran_cards[card_num].name);
} else {
card_num = card[nr];
if (card_num >= NUM_CARDS || card_num < 0) {
pci_err(pdev, "User specified card type %d out of range (0 .. %d)\n",
card_num, NUM_CARDS - 1);
goto zr_unreg;
}
}
/*
* even though we make this a non pointer and thus
* theoretically allow for making changes to this struct
* on a per-individual card basis at runtime, this is
* strongly discouraged. This structure is intended to
* keep general card information, no settings or anything
*/
zr->card = zoran_cards[card_num];
snprintf(ZR_DEVNAME(zr), sizeof(ZR_DEVNAME(zr)), "%s[%u]",
zr->card.name, zr->id);
err = pci_request_regions(pdev, ZR_DEVNAME(zr));
if (err)
goto zr_unreg;
zr->zr36057_mem = devm_ioremap(&pdev->dev, pci_resource_start(pdev, 0),
pci_resource_len(pdev, 0));
if (!zr->zr36057_mem) {
pci_err(pdev, "%s() - ioremap failed\n", __func__);
goto zr_pci_release;
}
result = pci_request_irq(pdev, 0, zoran_irq, NULL, zr, ZR_DEVNAME(zr));
if (result < 0) {
if (result == -EINVAL) {
pci_err(pdev, "%s - bad IRQ number or handler\n", __func__);
} else if (result == -EBUSY) {
pci_err(pdev, "%s - IRQ %d busy, change your PnP config in BIOS\n",
__func__, zr->pci_dev->irq);
} else {
pci_err(pdev, "%s - cannot assign IRQ, error code %d\n", __func__, result);
}
goto zr_pci_release;
}
/* set PCI latency timer */
pci_read_config_byte(zr->pci_dev, PCI_LATENCY_TIMER,
&latency);
need_latency = zr->revision > 1 ? 32 : 48;
if (latency != need_latency) {
pci_info(zr->pci_dev, "Changing PCI latency from %d to %d\n",
latency, need_latency);
pci_write_config_byte(zr->pci_dev, PCI_LATENCY_TIMER, need_latency);
}
zr36057_restart(zr);
err = zoran_i2c_init(zr);
if (err)
goto zr_free_irq;
pci_info(zr->pci_dev, "Initializing videocodec bus...\n");
err = videocodec_init(zr);
if (err)
goto zr_unreg_i2c;
/* reset JPEG codec */
jpeg_codec_sleep(zr, 1);
jpeg_codec_reset(zr);
/* video bus enabled */
/* display codec revision */
if (zr->card.video_codec != 0) {
master_codec = zoran_setup_videocodec(zr, zr->card.video_codec);
if (!master_codec)
goto zr_unreg_videocodec;
zr->codec = videocodec_attach(master_codec);
if (!zr->codec) {
pci_err(pdev, "%s - no codec found\n", __func__);
goto zr_unreg_videocodec;
}
if (zr->codec->type != zr->card.video_codec) {
pci_err(pdev, "%s - wrong codec\n", __func__);
goto zr_unreg_videocodec;
}
}
if (zr->card.video_vfe != 0) {
master_vfe = zoran_setup_videocodec(zr, zr->card.video_vfe);
if (!master_vfe)
goto zr_detach_codec;
zr->vfe = videocodec_attach(master_vfe);
if (!zr->vfe) {
pci_err(pdev, "%s - no VFE found\n", __func__);
goto zr_detach_codec;
}
if (zr->vfe->type != zr->card.video_vfe) {
pci_err(pdev, "%s = wrong VFE\n", __func__);
goto zr_detach_vfe;
}
}
/* take care of Natoma chipset and a revision 1 zr36057 */
if ((pci_pci_problems & PCIPCI_NATOMA) && zr->revision <= 1)
pci_info(zr->pci_dev, "ZR36057/Natoma bug, max. buffer size is 128K\n");
if (zr36057_init(zr) < 0)
goto zr_detach_vfe;
zr->map_mode = ZORAN_MAP_MODE_RAW;
zr->dbgfs_dir = debugfs_create_dir(ZR_DEVNAME(zr), NULL);
debugfs_create_file("debug", 0444, zr->dbgfs_dir, zr,
&zoran_debugfs_fops);
return 0;
zr_detach_vfe:
videocodec_detach(zr->vfe);
zr_detach_codec:
videocodec_detach(zr->codec);
zr_unreg_videocodec:
videocodec_exit(zr);
zr_unreg_i2c:
zoran_i2c_exit(zr);
zr_free_irq:
btwrite(0, ZR36057_SPGPPCR);
pci_free_irq(zr->pci_dev, 0, zr);
zr_pci_release:
pci_release_regions(pdev);
zr_unreg:
v4l2_ctrl_handler_free(&zr->hdl);
v4l2_device_unregister(&zr->v4l2_dev);
zr_free_mem:
return -ENODEV;
}
static struct pci_driver zoran_driver = {
.name = "zr36067",
.id_table = zr36067_pci_tbl,
.probe = zoran_probe,
.remove = zoran_remove,
};
module_pci_driver(zoran_driver);
| linux-master | drivers/media/pci/zoran/zoran_card.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* VIDEO MOTION CODECs internal API for video devices
*
* Interface for MJPEG (and maybe later MPEG/WAVELETS) codec's
* bound to a master device.
*
* (c) 2002 Wolfgang Scherr <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/slab.h>
#include "videocodec.h"
struct attached_list {
struct videocodec *codec;
struct attached_list *next;
};
struct codec_list {
const struct videocodec *codec;
int attached;
struct attached_list *list;
struct codec_list *next;
};
static struct codec_list *codeclist_top;
/* ================================================= */
/* function prototypes of the master/slave interface */
/* ================================================= */
struct videocodec *videocodec_attach(struct videocodec_master *master)
{
struct codec_list *h = codeclist_top;
struct zoran *zr;
struct attached_list *a, *ptr;
struct videocodec *codec;
int res;
if (!master) {
pr_err("%s: no data\n", __func__);
return NULL;
}
zr = videocodec_master_to_zoran(master);
zrdev_dbg(zr, "%s: '%s', flags %lx, magic %lx\n", __func__,
master->name, master->flags, master->magic);
if (!h) {
zrdev_err(zr, "%s: no device available\n", __func__);
return NULL;
}
while (h) {
// attach only if the slave has at least the flags
// expected by the master
if ((master->flags & h->codec->flags) == master->flags) {
zrdev_dbg(zr, "%s: try '%s'\n", __func__, h->codec->name);
codec = kmemdup(h->codec, sizeof(struct videocodec), GFP_KERNEL);
if (!codec)
goto out_kfree;
res = strlen(codec->name);
snprintf(codec->name + res, sizeof(codec->name) - res, "[%d]", h->attached);
codec->master_data = master;
res = codec->setup(codec);
if (res == 0) {
zrdev_dbg(zr, "%s: '%s'\n", __func__, codec->name);
ptr = kzalloc(sizeof(*ptr), GFP_KERNEL);
if (!ptr)
goto out_kfree;
ptr->codec = codec;
a = h->list;
if (!a) {
h->list = ptr;
zrdev_dbg(zr, "videocodec: first element\n");
} else {
while (a->next)
a = a->next; // find end
a->next = ptr;
zrdev_dbg(zr, "videocodec: in after '%s'\n",
h->codec->name);
}
h->attached += 1;
return codec;
}
kfree(codec);
}
h = h->next;
}
zrdev_err(zr, "%s: no codec found!\n", __func__);
return NULL;
out_kfree:
kfree(codec);
return NULL;
}
int videocodec_detach(struct videocodec *codec)
{
struct codec_list *h = codeclist_top;
struct zoran *zr;
struct attached_list *a, *prev;
int res;
if (!codec) {
pr_err("%s: no data\n", __func__);
return -EINVAL;
}
zr = videocodec_to_zoran(codec);
zrdev_dbg(zr, "%s: '%s', type: %x, flags %lx, magic %lx\n", __func__,
codec->name, codec->type, codec->flags, codec->magic);
if (!h) {
zrdev_err(zr, "%s: no device left...\n", __func__);
return -ENXIO;
}
while (h) {
a = h->list;
prev = NULL;
while (a) {
if (codec == a->codec) {
res = a->codec->unset(a->codec);
if (res >= 0) {
zrdev_dbg(zr, "%s: '%s'\n", __func__,
a->codec->name);
a->codec->master_data = NULL;
} else {
zrdev_err(zr, "%s: '%s'\n", __func__, a->codec->name);
a->codec->master_data = NULL;
}
if (!prev) {
h->list = a->next;
zrdev_dbg(zr, "videocodec: delete first\n");
} else {
prev->next = a->next;
zrdev_dbg(zr, "videocodec: delete middle\n");
}
kfree(a->codec);
kfree(a);
h->attached -= 1;
return 0;
}
prev = a;
a = a->next;
}
h = h->next;
}
zrdev_err(zr, "%s: given codec not found!\n", __func__);
return -EINVAL;
}
int videocodec_register(const struct videocodec *codec)
{
struct codec_list *ptr, *h = codeclist_top;
struct zoran *zr;
if (!codec) {
pr_err("%s: no data!\n", __func__);
return -EINVAL;
}
zr = videocodec_to_zoran((struct videocodec *)codec);
zrdev_dbg(zr,
"videocodec: register '%s', type: %x, flags %lx, magic %lx\n",
codec->name, codec->type, codec->flags, codec->magic);
ptr = kzalloc(sizeof(*ptr), GFP_KERNEL);
if (!ptr)
return -ENOMEM;
ptr->codec = codec;
if (!h) {
codeclist_top = ptr;
zrdev_dbg(zr, "videocodec: hooked in as first element\n");
} else {
while (h->next)
h = h->next; // find the end
h->next = ptr;
zrdev_dbg(zr, "videocodec: hooked in after '%s'\n",
h->codec->name);
}
return 0;
}
int videocodec_unregister(const struct videocodec *codec)
{
struct codec_list *prev = NULL, *h = codeclist_top;
struct zoran *zr;
if (!codec) {
pr_err("%s: no data!\n", __func__);
return -EINVAL;
}
zr = videocodec_to_zoran((struct videocodec *)codec);
zrdev_dbg(zr,
"videocodec: unregister '%s', type: %x, flags %lx, magic %lx\n",
codec->name, codec->type, codec->flags, codec->magic);
if (!h) {
zrdev_err(zr, "%s: no device left...\n", __func__);
return -ENXIO;
}
while (h) {
if (codec == h->codec) {
if (h->attached) {
zrdev_err(zr, "videocodec: '%s' is used\n",
h->codec->name);
return -EBUSY;
}
zrdev_dbg(zr, "videocodec: unregister '%s' is ok.\n",
h->codec->name);
if (!prev) {
codeclist_top = h->next;
zrdev_dbg(zr,
"videocodec: delete first element\n");
} else {
prev->next = h->next;
zrdev_dbg(zr,
"videocodec: delete middle element\n");
}
kfree(h);
return 0;
}
prev = h;
h = h->next;
}
zrdev_err(zr, "%s: given codec not found!\n", __func__);
return -EINVAL;
}
int videocodec_debugfs_show(struct seq_file *m)
{
struct codec_list *h = codeclist_top;
struct attached_list *a;
seq_puts(m, "<S>lave or attached <M>aster name type flags magic ");
seq_puts(m, "(connected as)\n");
while (h) {
seq_printf(m, "S %32s %04x %08lx %08lx (TEMPLATE)\n",
h->codec->name, h->codec->type,
h->codec->flags, h->codec->magic);
a = h->list;
while (a) {
seq_printf(m, "M %32s %04x %08lx %08lx (%s)\n",
a->codec->master_data->name,
a->codec->master_data->type,
a->codec->master_data->flags,
a->codec->master_data->magic,
a->codec->name);
a = a->next;
}
h = h->next;
}
return 0;
}
| linux-master | drivers/media/pci/zoran/videocodec.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Zoran ZR36060 basic configuration functions
*
* Copyright (C) 2002 Laurent Pinchart <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/wait.h>
/* I/O commands, error codes */
#include <linux/io.h>
/* headerfile of this module */
#include "zr36060.h"
/* codec io API */
#include "videocodec.h"
/* it doesn't make sense to have more than 20 or so, just to prevent some unwanted loops */
#define MAX_CODECS 20
/* amount of chips attached via this driver */
static int zr36060_codecs;
static bool low_bitrate;
module_param(low_bitrate, bool, 0);
MODULE_PARM_DESC(low_bitrate, "Buz compatibility option, halves bitrate");
/* =========================================================================
* Local hardware I/O functions:
* read/write via codec layer (registers are located in the master device)
* =========================================================================
*/
static u8 zr36060_read(struct zr36060 *ptr, u16 reg)
{
u8 value = 0;
struct zoran *zr = videocodec_to_zoran(ptr->codec);
// just in case something is wrong...
if (ptr->codec->master_data->readreg)
value = (ptr->codec->master_data->readreg(ptr->codec, reg)) & 0xff;
else
zrdev_err(zr, "%s: invalid I/O setup, nothing read!\n", ptr->name);
return value;
}
static void zr36060_write(struct zr36060 *ptr, u16 reg, u8 value)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
zrdev_dbg(zr, "0x%02x @0x%04x\n", value, reg);
// just in case something is wrong...
if (ptr->codec->master_data->writereg)
ptr->codec->master_data->writereg(ptr->codec, reg, value);
else
zrdev_err(zr, "%s: invalid I/O setup, nothing written!\n", ptr->name);
}
/* =========================================================================
* Local helper function:
* status read
* =========================================================================
*/
/* status is kept in datastructure */
static u8 zr36060_read_status(struct zr36060 *ptr)
{
ptr->status = zr36060_read(ptr, ZR060_CFSR);
zr36060_read(ptr, 0);
return ptr->status;
}
/* scale factor is kept in datastructure */
static u16 zr36060_read_scalefactor(struct zr36060 *ptr)
{
ptr->scalefact = (zr36060_read(ptr, ZR060_SF_HI) << 8) |
(zr36060_read(ptr, ZR060_SF_LO) & 0xFF);
/* leave 0 selected for an eventually GO from master */
zr36060_read(ptr, 0);
return ptr->scalefact;
}
/* wait if codec is ready to proceed (end of processing) or time is over */
static void zr36060_wait_end(struct zr36060 *ptr)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
int i = 0;
while (zr36060_read_status(ptr) & ZR060_CFSR_BUSY) {
udelay(1);
if (i++ > 200000) { // 200ms, there is for sure something wrong!!!
zrdev_dbg(zr,
"%s: timeout at wait_end (last status: 0x%02x)\n",
ptr->name, ptr->status);
break;
}
}
}
/* Basic test of "connectivity", writes/reads to/from memory the SOF marker */
static int zr36060_basic_test(struct zr36060 *ptr)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
if ((zr36060_read(ptr, ZR060_IDR_DEV) != 0x33) &&
(zr36060_read(ptr, ZR060_IDR_REV) != 0x01)) {
zrdev_err(zr, "%s: attach failed, can't connect to jpeg processor!\n", ptr->name);
return -ENXIO;
}
zr36060_wait_end(ptr);
if (ptr->status & ZR060_CFSR_BUSY) {
zrdev_err(zr, "%s: attach failed, jpeg processor failed (end flag)!\n", ptr->name);
return -EBUSY;
}
return 0; /* looks good! */
}
/* simple loop for pushing the init datasets */
static int zr36060_pushit(struct zr36060 *ptr, u16 startreg, u16 len, const char *data)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
int i = 0;
zrdev_dbg(zr, "%s: write data block to 0x%04x (len=%d)\n", ptr->name,
startreg, len);
while (i < len)
zr36060_write(ptr, startreg++, data[i++]);
return i;
}
/* =========================================================================
* Basic datasets:
* jpeg baseline setup data (you find it on lots places in internet, or just
* extract it from any regular .jpg image...)
*
* Could be variable, but until it's not needed it they are just fixed to save
* memory. Otherwise expand zr36060 structure with arrays, push the values to
* it and initialize from there, as e.g. the linux zr36057/60 driver does it.
* =========================================================================
*/
static const char zr36060_dqt[0x86] = {
0xff, 0xdb, //Marker: DQT
0x00, 0x84, //Length: 2*65+2
0x00, //Pq,Tq first table
0x10, 0x0b, 0x0c, 0x0e, 0x0c, 0x0a, 0x10, 0x0e,
0x0d, 0x0e, 0x12, 0x11, 0x10, 0x13, 0x18, 0x28,
0x1a, 0x18, 0x16, 0x16, 0x18, 0x31, 0x23, 0x25,
0x1d, 0x28, 0x3a, 0x33, 0x3d, 0x3c, 0x39, 0x33,
0x38, 0x37, 0x40, 0x48, 0x5c, 0x4e, 0x40, 0x44,
0x57, 0x45, 0x37, 0x38, 0x50, 0x6d, 0x51, 0x57,
0x5f, 0x62, 0x67, 0x68, 0x67, 0x3e, 0x4d, 0x71,
0x79, 0x70, 0x64, 0x78, 0x5c, 0x65, 0x67, 0x63,
0x01, //Pq,Tq second table
0x11, 0x12, 0x12, 0x18, 0x15, 0x18, 0x2f, 0x1a,
0x1a, 0x2f, 0x63, 0x42, 0x38, 0x42, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63
};
static const char zr36060_dht[0x1a4] = {
0xff, 0xc4, //Marker: DHT
0x01, 0xa2, //Length: 2*AC, 2*DC
0x00, //DC first table
0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x01, //DC second table
0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x10, //AC first table
0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03,
0x05, 0x05, 0x04, 0x04, 0x00, 0x00,
0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04, 0x11,
0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61,
0x07, 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1,
0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24,
0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17,
0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34,
0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44,
0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66,
0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88,
0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99,
0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8,
0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9,
0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8,
0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9,
0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
0xF8, 0xF9, 0xFA,
0x11, //AC second table
0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04,
0x07, 0x05, 0x04, 0x04, 0x00, 0x01,
0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04,
0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
0xA1, 0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0, 0x15, 0x62,
0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25,
0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A,
0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44,
0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66,
0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
0x79, 0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7,
0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8,
0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8,
0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8,
0xF9, 0xFA
};
/* jpeg baseline setup, this is just fixed in this driver (YUV pictures) */
#define NO_OF_COMPONENTS 0x3 //Y,U,V
#define BASELINE_PRECISION 0x8 //MCU size (?)
static const char zr36060_tq[8] = { 0, 1, 1, 0, 0, 0, 0, 0 }; //table idx's QT
static const char zr36060_td[8] = { 0, 1, 1, 0, 0, 0, 0, 0 }; //table idx's DC
static const char zr36060_ta[8] = { 0, 1, 1, 0, 0, 0, 0, 0 }; //table idx's AC
/* horizontal 422 decimation setup (maybe we support 411 or so later, too) */
static const char zr36060_decimation_h[8] = { 2, 1, 1, 0, 0, 0, 0, 0 };
static const char zr36060_decimation_v[8] = { 1, 1, 1, 0, 0, 0, 0, 0 };
/*
* SOF (start of frame) segment depends on width, height and sampling ratio
* of each color component
*/
static int zr36060_set_sof(struct zr36060 *ptr)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
char sof_data[34]; // max. size of register set
int i;
zrdev_dbg(zr, "%s: write SOF (%dx%d, %d components)\n", ptr->name,
ptr->width, ptr->height, NO_OF_COMPONENTS);
sof_data[0] = 0xff;
sof_data[1] = 0xc0;
sof_data[2] = 0x00;
sof_data[3] = (3 * NO_OF_COMPONENTS) + 8;
sof_data[4] = BASELINE_PRECISION; // only '8' possible with zr36060
sof_data[5] = (ptr->height) >> 8;
sof_data[6] = (ptr->height) & 0xff;
sof_data[7] = (ptr->width) >> 8;
sof_data[8] = (ptr->width) & 0xff;
sof_data[9] = NO_OF_COMPONENTS;
for (i = 0; i < NO_OF_COMPONENTS; i++) {
sof_data[10 + (i * 3)] = i; // index identifier
sof_data[11 + (i * 3)] = (ptr->h_samp_ratio[i] << 4) |
(ptr->v_samp_ratio[i]); // sampling ratios
sof_data[12 + (i * 3)] = zr36060_tq[i]; // Q table selection
}
return zr36060_pushit(ptr, ZR060_SOF_IDX,
(3 * NO_OF_COMPONENTS) + 10, sof_data);
}
/* SOS (start of scan) segment depends on the used scan components of each color component */
static int zr36060_set_sos(struct zr36060 *ptr)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
char sos_data[16]; // max. size of register set
int i;
zrdev_dbg(zr, "%s: write SOS\n", ptr->name);
sos_data[0] = 0xff;
sos_data[1] = 0xda;
sos_data[2] = 0x00;
sos_data[3] = 2 + 1 + (2 * NO_OF_COMPONENTS) + 3;
sos_data[4] = NO_OF_COMPONENTS;
for (i = 0; i < NO_OF_COMPONENTS; i++) {
sos_data[5 + (i * 2)] = i; // index
sos_data[6 + (i * 2)] = (zr36060_td[i] << 4) |
zr36060_ta[i]; // AC/DC tbl.sel.
}
sos_data[2 + 1 + (2 * NO_OF_COMPONENTS) + 2] = 00; // scan start
sos_data[2 + 1 + (2 * NO_OF_COMPONENTS) + 3] = 0x3f;
sos_data[2 + 1 + (2 * NO_OF_COMPONENTS) + 4] = 00;
return zr36060_pushit(ptr, ZR060_SOS_IDX,
4 + 1 + (2 * NO_OF_COMPONENTS) + 3,
sos_data);
}
/* DRI (define restart interval) */
static int zr36060_set_dri(struct zr36060 *ptr)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
char dri_data[6]; // max. size of register set
zrdev_dbg(zr, "%s: write DRI\n", ptr->name);
dri_data[0] = 0xff;
dri_data[1] = 0xdd;
dri_data[2] = 0x00;
dri_data[3] = 0x04;
dri_data[4] = (ptr->dri) >> 8;
dri_data[5] = (ptr->dri) & 0xff;
return zr36060_pushit(ptr, ZR060_DRI_IDX, 6, dri_data);
}
/* Setup compression/decompression of Zoran's JPEG processor ( see also zoran 36060 manual )
* ... sorry for the spaghetti code ...
*/
static void zr36060_init(struct zr36060 *ptr)
{
int sum = 0;
long bitcnt, tmp;
struct zoran *zr = videocodec_to_zoran(ptr->codec);
if (ptr->mode == CODEC_DO_COMPRESSION) {
zrdev_dbg(zr, "%s: COMPRESSION SETUP\n", ptr->name);
zr36060_write(ptr, ZR060_LOAD, ZR060_LOAD_SYNC_RST);
/* 060 communicates with 067 in master mode */
zr36060_write(ptr, ZR060_CIR, ZR060_CIR_CODE_MSTR);
/* Compression with or without variable scale factor */
/*FIXME: What about ptr->bitrate_ctrl? */
zr36060_write(ptr, ZR060_CMR, ZR060_CMR_COMP | ZR060_CMR_PASS2 | ZR060_CMR_BRB);
/* Must be zero */
zr36060_write(ptr, ZR060_MBZ, 0x00);
zr36060_write(ptr, ZR060_TCR_HI, 0x00);
zr36060_write(ptr, ZR060_TCR_LO, 0x00);
/* Disable all IRQs - no DataErr means autoreset */
zr36060_write(ptr, ZR060_IMR, 0);
/* volume control settings */
zr36060_write(ptr, ZR060_SF_HI, ptr->scalefact >> 8);
zr36060_write(ptr, ZR060_SF_LO, ptr->scalefact & 0xff);
zr36060_write(ptr, ZR060_AF_HI, 0xff);
zr36060_write(ptr, ZR060_AF_M, 0xff);
zr36060_write(ptr, ZR060_AF_LO, 0xff);
/* setup the variable jpeg tables */
sum += zr36060_set_sof(ptr);
sum += zr36060_set_sos(ptr);
sum += zr36060_set_dri(ptr);
/* setup the fixed jpeg tables - maybe variable, though - (see table init section above) */
sum += zr36060_pushit(ptr, ZR060_DQT_IDX, sizeof(zr36060_dqt), zr36060_dqt);
sum += zr36060_pushit(ptr, ZR060_DHT_IDX, sizeof(zr36060_dht), zr36060_dht);
zr36060_write(ptr, ZR060_APP_IDX, 0xff);
zr36060_write(ptr, ZR060_APP_IDX + 1, 0xe0 + ptr->app.appn);
zr36060_write(ptr, ZR060_APP_IDX + 2, 0x00);
zr36060_write(ptr, ZR060_APP_IDX + 3, ptr->app.len + 2);
sum += zr36060_pushit(ptr, ZR060_APP_IDX + 4, 60, ptr->app.data) + 4;
zr36060_write(ptr, ZR060_COM_IDX, 0xff);
zr36060_write(ptr, ZR060_COM_IDX + 1, 0xfe);
zr36060_write(ptr, ZR060_COM_IDX + 2, 0x00);
zr36060_write(ptr, ZR060_COM_IDX + 3, ptr->com.len + 2);
sum += zr36060_pushit(ptr, ZR060_COM_IDX + 4, 60, ptr->com.data) + 4;
/* setup misc. data for compression (target code sizes) */
/* size of compressed code to reach without header data */
sum = ptr->real_code_vol - sum;
bitcnt = sum << 3; /* need the size in bits */
tmp = bitcnt >> 16;
zrdev_dbg(zr,
"%s: code: csize=%d, tot=%d, bit=%ld, highbits=%ld\n",
ptr->name, sum, ptr->real_code_vol, bitcnt, tmp);
zr36060_write(ptr, ZR060_TCV_NET_HI, tmp >> 8);
zr36060_write(ptr, ZR060_TCV_NET_MH, tmp & 0xff);
tmp = bitcnt & 0xffff;
zr36060_write(ptr, ZR060_TCV_NET_ML, tmp >> 8);
zr36060_write(ptr, ZR060_TCV_NET_LO, tmp & 0xff);
bitcnt -= bitcnt >> 7; // bits without stuffing
bitcnt -= ((bitcnt * 5) >> 6); // bits without eob
tmp = bitcnt >> 16;
zrdev_dbg(zr, "%s: code: nettobit=%ld, highnettobits=%ld\n",
ptr->name, bitcnt, tmp);
zr36060_write(ptr, ZR060_TCV_DATA_HI, tmp >> 8);
zr36060_write(ptr, ZR060_TCV_DATA_MH, tmp & 0xff);
tmp = bitcnt & 0xffff;
zr36060_write(ptr, ZR060_TCV_DATA_ML, tmp >> 8);
zr36060_write(ptr, ZR060_TCV_DATA_LO, tmp & 0xff);
/* JPEG markers to be included in the compressed stream */
zr36060_write(ptr, ZR060_MER,
ZR060_MER_DQT | ZR060_MER_DHT |
((ptr->com.len > 0) ? ZR060_MER_COM : 0) |
((ptr->app.len > 0) ? ZR060_MER_APP : 0));
/* Setup the Video Frontend */
/* Limit pixel range to 16..235 as per CCIR-601 */
zr36060_write(ptr, ZR060_VCR, ZR060_VCR_RANGE);
} else {
zrdev_dbg(zr, "%s: EXPANSION SETUP\n", ptr->name);
zr36060_write(ptr, ZR060_LOAD, ZR060_LOAD_SYNC_RST);
/* 060 communicates with 067 in master mode */
zr36060_write(ptr, ZR060_CIR, ZR060_CIR_CODE_MSTR);
/* Decompression */
zr36060_write(ptr, ZR060_CMR, 0);
/* Must be zero */
zr36060_write(ptr, ZR060_MBZ, 0x00);
zr36060_write(ptr, ZR060_TCR_HI, 0x00);
zr36060_write(ptr, ZR060_TCR_LO, 0x00);
/* Disable all IRQs - no DataErr means autoreset */
zr36060_write(ptr, ZR060_IMR, 0);
/* setup misc. data for expansion */
zr36060_write(ptr, ZR060_MER, 0);
/* setup the fixed jpeg tables - maybe variable, though - (see table init section above) */
zr36060_pushit(ptr, ZR060_DHT_IDX, sizeof(zr36060_dht), zr36060_dht);
/* Setup the Video Frontend */
//zr36060_write(ptr, ZR060_VCR, ZR060_VCR_FI_EXT);
//this doesn't seem right and doesn't work...
zr36060_write(ptr, ZR060_VCR, ZR060_VCR_RANGE);
}
/* Load the tables */
zr36060_write(ptr, ZR060_LOAD, ZR060_LOAD_SYNC_RST | ZR060_LOAD_LOAD);
zr36060_wait_end(ptr);
zrdev_dbg(zr, "%s: Status after table preload: 0x%02x\n",
ptr->name, ptr->status);
if (ptr->status & ZR060_CFSR_BUSY) {
zrdev_err(zr, "%s: init aborted!\n", ptr->name);
return; // something is wrong, its timed out!!!!
}
}
/* =========================================================================
* CODEC API FUNCTIONS
* this functions are accessed by the master via the API structure
* =========================================================================
*/
/* set compressiion/expansion mode and launches codec -
* this should be the last call from the master before starting processing
*/
static int zr36060_set_mode(struct videocodec *codec, int mode)
{
struct zr36060 *ptr = (struct zr36060 *)codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
zrdev_dbg(zr, "%s: set_mode %d call\n", ptr->name, mode);
if (mode != CODEC_DO_EXPANSION && mode != CODEC_DO_COMPRESSION)
return -EINVAL;
ptr->mode = mode;
zr36060_init(ptr);
return 0;
}
/* set picture size (norm is ignored as the codec doesn't know about it) */
static int zr36060_set_video(struct videocodec *codec, const struct tvnorm *norm,
struct vfe_settings *cap, struct vfe_polarity *pol)
{
struct zr36060 *ptr = (struct zr36060 *)codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
u32 reg;
int size;
zrdev_dbg(zr, "%s: set_video %d/%d-%dx%d (%%%d) call\n", ptr->name,
cap->x, cap->y, cap->width, cap->height, cap->decimation);
/* if () return -EINVAL;
* trust the master driver that it knows what it does - so
* we allow invalid startx/y and norm for now ...
*/
ptr->width = cap->width / (cap->decimation & 0xff);
ptr->height = cap->height / (cap->decimation >> 8);
zr36060_write(ptr, ZR060_LOAD, ZR060_LOAD_SYNC_RST);
/* Note that VSPol/HSPol bits in zr36060 have the opposite
* meaning of their zr360x7 counterparts with the same names
* N.b. for VSPol this is only true if FIVEdge = 0 (default,
* left unchanged here - in accordance with datasheet).
*/
reg = (!pol->vsync_pol ? ZR060_VPR_VS_POL : 0)
| (!pol->hsync_pol ? ZR060_VPR_HS_POL : 0)
| (pol->field_pol ? ZR060_VPR_FI_POL : 0)
| (pol->blank_pol ? ZR060_VPR_BL_POL : 0)
| (pol->subimg_pol ? ZR060_VPR_S_IMG_POL : 0)
| (pol->poe_pol ? ZR060_VPR_POE_POL : 0)
| (pol->pvalid_pol ? ZR060_VPR_P_VAL_POL : 0)
| (pol->vclk_pol ? ZR060_VPR_VCLK_POL : 0);
zr36060_write(ptr, ZR060_VPR, reg);
reg = 0;
switch (cap->decimation & 0xff) {
default:
case 1:
break;
case 2:
reg |= ZR060_SR_H_SCALE2;
break;
case 4:
reg |= ZR060_SR_H_SCALE4;
break;
}
switch (cap->decimation >> 8) {
default:
case 1:
break;
case 2:
reg |= ZR060_SR_V_SCALE;
break;
}
zr36060_write(ptr, ZR060_SR, reg);
zr36060_write(ptr, ZR060_BCR_Y, 0x00);
zr36060_write(ptr, ZR060_BCR_U, 0x80);
zr36060_write(ptr, ZR060_BCR_V, 0x80);
/* sync generator */
reg = norm->ht - 1; /* Vtotal */
zr36060_write(ptr, ZR060_SGR_VTOTAL_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SGR_VTOTAL_LO, (reg >> 0) & 0xff);
reg = norm->wt - 1; /* Htotal */
zr36060_write(ptr, ZR060_SGR_HTOTAL_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SGR_HTOTAL_LO, (reg >> 0) & 0xff);
reg = 6 - 1; /* VsyncSize */
zr36060_write(ptr, ZR060_SGR_VSYNC, reg);
reg = 68;
zr36060_write(ptr, ZR060_SGR_HSYNC, reg);
reg = norm->v_start - 1; /* BVstart */
zr36060_write(ptr, ZR060_SGR_BVSTART, reg);
reg += norm->ha / 2; /* BVend */
zr36060_write(ptr, ZR060_SGR_BVEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SGR_BVEND_LO, (reg >> 0) & 0xff);
reg = norm->h_start - 1; /* BHstart */
zr36060_write(ptr, ZR060_SGR_BHSTART, reg);
reg += norm->wa; /* BHend */
zr36060_write(ptr, ZR060_SGR_BHEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SGR_BHEND_LO, (reg >> 0) & 0xff);
/* active area */
reg = cap->y + norm->v_start; /* Vstart */
zr36060_write(ptr, ZR060_AAR_VSTART_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_AAR_VSTART_LO, (reg >> 0) & 0xff);
reg += cap->height; /* Vend */
zr36060_write(ptr, ZR060_AAR_VEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_AAR_VEND_LO, (reg >> 0) & 0xff);
reg = cap->x + norm->h_start; /* Hstart */
zr36060_write(ptr, ZR060_AAR_HSTART_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_AAR_HSTART_LO, (reg >> 0) & 0xff);
reg += cap->width; /* Hend */
zr36060_write(ptr, ZR060_AAR_HEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_AAR_HEND_LO, (reg >> 0) & 0xff);
/* subimage area */
reg = norm->v_start - 4; /* SVstart */
zr36060_write(ptr, ZR060_SWR_VSTART_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SWR_VSTART_LO, (reg >> 0) & 0xff);
reg += norm->ha / 2 + 8; /* SVend */
zr36060_write(ptr, ZR060_SWR_VEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SWR_VEND_LO, (reg >> 0) & 0xff);
reg = norm->h_start /*+ 64 */ - 4; /* SHstart */
zr36060_write(ptr, ZR060_SWR_HSTART_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SWR_HSTART_LO, (reg >> 0) & 0xff);
reg += norm->wa + 8; /* SHend */
zr36060_write(ptr, ZR060_SWR_HEND_HI, (reg >> 8) & 0xff);
zr36060_write(ptr, ZR060_SWR_HEND_LO, (reg >> 0) & 0xff);
size = ptr->width * ptr->height;
/* Target compressed field size in bits: */
size = size * 16; /* uncompressed size in bits */
/* (Ronald) by default, quality = 100 is a compression
* ratio 1:2. Setting low_bitrate (insmod option) sets
* it to 1:4 (instead of 1:2, zr36060 max) as limit because the
* buz can't handle more at decimation=1... Use low_bitrate if
* you have a Buz, unless you know what you're doing
*/
size = size * cap->quality / (low_bitrate ? 400 : 200);
/* Lower limit (arbitrary, 1 KB) */
if (size < 8192)
size = 8192;
/* Upper limit: 7/8 of the code buffers */
if (size > ptr->total_code_vol * 7)
size = ptr->total_code_vol * 7;
ptr->real_code_vol = size >> 3; /* in bytes */
/* the MBCVR is the *maximum* block volume, according to the
* JPEG ISO specs, this shouldn't be used, since that allows
* for the best encoding quality. So set it to it's max value
*/
reg = ptr->max_block_vol;
zr36060_write(ptr, ZR060_MBCVR, reg);
return 0;
}
/* additional control functions */
static int zr36060_control(struct videocodec *codec, int type, int size, void *data)
{
struct zr36060 *ptr = (struct zr36060 *)codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
int *ival = (int *)data;
zrdev_dbg(zr, "%s: control %d call with %d byte\n", ptr->name, type,
size);
switch (type) {
case CODEC_G_STATUS: /* get last status */
if (size != sizeof(int))
return -EFAULT;
zr36060_read_status(ptr);
*ival = ptr->status;
break;
case CODEC_G_CODEC_MODE:
if (size != sizeof(int))
return -EFAULT;
*ival = CODEC_MODE_BJPG;
break;
case CODEC_S_CODEC_MODE:
if (size != sizeof(int))
return -EFAULT;
if (*ival != CODEC_MODE_BJPG)
return -EINVAL;
/* not needed, do nothing */
return 0;
case CODEC_G_VFE:
case CODEC_S_VFE:
/* not needed, do nothing */
return 0;
case CODEC_S_MMAP:
/* not available, give an error */
return -ENXIO;
case CODEC_G_JPEG_TDS_BYTE: /* get target volume in byte */
if (size != sizeof(int))
return -EFAULT;
*ival = ptr->total_code_vol;
break;
case CODEC_S_JPEG_TDS_BYTE: /* get target volume in byte */
if (size != sizeof(int))
return -EFAULT;
ptr->total_code_vol = *ival;
ptr->real_code_vol = (ptr->total_code_vol * 6) >> 3;
break;
case CODEC_G_JPEG_SCALE: /* get scaling factor */
if (size != sizeof(int))
return -EFAULT;
*ival = zr36060_read_scalefactor(ptr);
break;
case CODEC_S_JPEG_SCALE: /* set scaling factor */
if (size != sizeof(int))
return -EFAULT;
ptr->scalefact = *ival;
break;
case CODEC_G_JPEG_APP_DATA: { /* get appn marker data */
struct jpeg_app_marker *app = data;
if (size != sizeof(struct jpeg_app_marker))
return -EFAULT;
*app = ptr->app;
break;
}
case CODEC_S_JPEG_APP_DATA: { /* set appn marker data */
struct jpeg_app_marker *app = data;
if (size != sizeof(struct jpeg_app_marker))
return -EFAULT;
ptr->app = *app;
break;
}
case CODEC_G_JPEG_COM_DATA: { /* get comment marker data */
struct jpeg_com_marker *com = data;
if (size != sizeof(struct jpeg_com_marker))
return -EFAULT;
*com = ptr->com;
break;
}
case CODEC_S_JPEG_COM_DATA: { /* set comment marker data */
struct jpeg_com_marker *com = data;
if (size != sizeof(struct jpeg_com_marker))
return -EFAULT;
ptr->com = *com;
break;
}
default:
return -EINVAL;
}
return size;
}
/* =========================================================================
* Exit and unregister function:
* Deinitializes Zoran's JPEG processor
* =========================================================================
*/
static int zr36060_unset(struct videocodec *codec)
{
struct zr36060 *ptr = codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
if (ptr) {
/* do wee need some codec deinit here, too ???? */
zrdev_dbg(zr, "%s: finished codec #%d\n", ptr->name, ptr->num);
kfree(ptr);
codec->data = NULL;
zr36060_codecs--;
return 0;
}
return -EFAULT;
}
/* =========================================================================
* Setup and registry function:
* Initializes Zoran's JPEG processor
* Also sets pixel size, average code size, mode (compr./decompr.)
* (the given size is determined by the processor with the video interface)
* =========================================================================
*/
static int zr36060_setup(struct videocodec *codec)
{
struct zr36060 *ptr;
struct zoran *zr = videocodec_to_zoran(codec);
int res;
zrdev_dbg(zr, "zr36060: initializing MJPEG subsystem #%d.\n",
zr36060_codecs);
if (zr36060_codecs == MAX_CODECS) {
zrdev_err(zr, "zr36060: Can't attach more codecs!\n");
return -ENOSPC;
}
//mem structure init
ptr = kzalloc(sizeof(*ptr), GFP_KERNEL);
codec->data = ptr;
if (!ptr)
return -ENOMEM;
snprintf(ptr->name, sizeof(ptr->name), "zr36060[%d]", zr36060_codecs);
ptr->num = zr36060_codecs++;
ptr->codec = codec;
//testing
res = zr36060_basic_test(ptr);
if (res < 0) {
zr36060_unset(codec);
return res;
}
//final setup
memcpy(ptr->h_samp_ratio, zr36060_decimation_h, 8);
memcpy(ptr->v_samp_ratio, zr36060_decimation_v, 8);
ptr->bitrate_ctrl = 0; /* 0 or 1 - fixed file size flag (what is the difference?) */
ptr->mode = CODEC_DO_COMPRESSION;
ptr->width = 384;
ptr->height = 288;
ptr->total_code_vol = 16000; /* CHECKME */
ptr->real_code_vol = (ptr->total_code_vol * 6) >> 3;
ptr->max_block_vol = 240; /* CHECKME, was 120 is 240 */
ptr->scalefact = 0x100;
ptr->dri = 1; /* CHECKME, was 8 is 1 */
/* by default, no COM or APP markers - app should set those */
ptr->com.len = 0;
ptr->app.appn = 0;
ptr->app.len = 0;
zr36060_init(ptr);
zrdev_info(zr, "%s: codec attached and running\n", ptr->name);
return 0;
}
static const struct videocodec zr36060_codec = {
.name = "zr36060",
.magic = 0L, // magic not used
.flags =
CODEC_FLAG_JPEG | CODEC_FLAG_HARDWARE | CODEC_FLAG_ENCODER |
CODEC_FLAG_DECODER | CODEC_FLAG_VFE,
.type = CODEC_TYPE_ZR36060,
.setup = zr36060_setup, // functionality
.unset = zr36060_unset,
.set_mode = zr36060_set_mode,
.set_video = zr36060_set_video,
.control = zr36060_control,
// others are not used
};
int zr36060_init_module(void)
{
zr36060_codecs = 0;
return videocodec_register(&zr36060_codec);
}
void zr36060_cleanup_module(void)
{
if (zr36060_codecs) {
pr_debug("zr36060: something's wrong - %d codecs left somehow.\n",
zr36060_codecs);
}
/* however, we can't just stay alive */
videocodec_unregister(&zr36060_codec);
}
| linux-master | drivers/media/pci/zoran/zr36060.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Zoran zr36057/zr36067 PCI controller driver, for the
* Pinnacle/Miro DC10/DC10+/DC30/DC30+, Iomega Buz, Linux
* Media Labs LML33/LML33R10.
*
* This part handles device access (PCI/I2C/codec/...)
*
* Copyright (C) 2000 Serguei Miridonov <[email protected]>
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/wait.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include "videocodec.h"
#include "zoran.h"
#include "zoran_device.h"
#include "zoran_card.h"
#define IRQ_MASK (ZR36057_ISR_GIRQ0 | \
ZR36057_ISR_GIRQ1 | \
ZR36057_ISR_JPEG_REP_IRQ)
static bool lml33dpath; /* default = 0
* 1 will use digital path in capture
* mode instead of analog. It can be
* used for picture adjustments using
* tool like xawtv while watching image
* on TV monitor connected to the output.
* However, due to absence of 75 Ohm
* load on Bt819 input, there will be
* some image imperfections
*/
module_param(lml33dpath, bool, 0644);
MODULE_PARM_DESC(lml33dpath, "Use digital path capture mode (on LML33 cards)");
/*
* initialize video front end
*/
static void zr36057_init_vfe(struct zoran *zr)
{
u32 reg;
reg = btread(ZR36057_VFESPFR);
reg |= ZR36057_VFESPFR_LITTLE_ENDIAN;
reg &= ~ZR36057_VFESPFR_VCLK_POL;
reg |= ZR36057_VFESPFR_EXT_FL;
reg |= ZR36057_VFESPFR_TOP_FIELD;
btwrite(reg, ZR36057_VFESPFR);
reg = btread(ZR36057_VDCR);
if (pci_pci_problems & PCIPCI_TRITON)
// || zr->revision < 1) // Revision 1 has also Triton support
reg &= ~ZR36057_VDCR_TRITON;
else
reg |= ZR36057_VDCR_TRITON;
btwrite(reg, ZR36057_VDCR);
}
/*
* General Purpose I/O and Guest bus access
*/
/*
* This is a bit tricky. When a board lacks a GPIO function, the corresponding
* GPIO bit number in the card_info structure is set to 0.
*/
void GPIO(struct zoran *zr, int bit, unsigned int value)
{
u32 reg;
u32 mask;
/* Make sure the bit number is legal
* A bit number of -1 (lacking) gives a mask of 0,
* making it harmless
*/
mask = (1 << (24 + bit)) & 0xff000000;
reg = btread(ZR36057_GPPGCR1) & ~mask;
if (value)
reg |= mask;
btwrite(reg, ZR36057_GPPGCR1);
udelay(1);
}
/*
* Wait til post office is no longer busy
*/
int post_office_wait(struct zoran *zr)
{
u32 por;
while ((por = btread(ZR36057_POR)) & ZR36057_POR_PO_PEN) {
/* wait for something to happen */
/* TODO add timeout */
}
if ((por & ZR36057_POR_PO_TIME) && !zr->card.gws_not_connected) {
/* In LML33/BUZ \GWS line is not connected, so it has always timeout set */
pci_info(zr->pci_dev, "pop timeout %08x\n", por);
return -1;
}
return 0;
}
int post_office_write(struct zoran *zr, unsigned int guest,
unsigned int reg, unsigned int value)
{
u32 por;
por =
ZR36057_POR_PO_DIR | ZR36057_POR_PO_TIME | ((guest & 7) << 20) |
((reg & 7) << 16) | (value & 0xFF);
btwrite(por, ZR36057_POR);
return post_office_wait(zr);
}
int post_office_read(struct zoran *zr, unsigned int guest, unsigned int reg)
{
u32 por;
por = ZR36057_POR_PO_TIME | ((guest & 7) << 20) | ((reg & 7) << 16);
btwrite(por, ZR36057_POR);
if (post_office_wait(zr) < 0)
return -1;
return btread(ZR36057_POR) & 0xFF;
}
/*
* JPEG Codec access
*/
void jpeg_codec_sleep(struct zoran *zr, int sleep)
{
GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_SLEEP], !sleep);
if (!sleep) {
pci_dbg(zr->pci_dev, "%s() - wake GPIO=0x%08x\n",
__func__, btread(ZR36057_GPPGCR1));
usleep_range(500, 1000);
} else {
pci_dbg(zr->pci_dev, "%s() - sleep GPIO=0x%08x\n",
__func__, btread(ZR36057_GPPGCR1));
udelay(2);
}
}
int jpeg_codec_reset(struct zoran *zr)
{
/* Take the codec out of sleep */
jpeg_codec_sleep(zr, 0);
if (zr->card.gpcs[GPCS_JPEG_RESET] != 0xff) {
post_office_write(zr, zr->card.gpcs[GPCS_JPEG_RESET], 0,
0);
udelay(2);
} else {
GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_RESET], 0);
udelay(2);
GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_RESET], 1);
udelay(2);
}
return 0;
}
/*
* Set the registers for the size we have specified. Don't bother
* trying to understand this without the ZR36057 manual in front of
* you [AC].
*/
static void zr36057_adjust_vfe(struct zoran *zr, enum zoran_codec_mode mode)
{
u32 reg;
switch (mode) {
case BUZ_MODE_MOTION_DECOMPRESS:
btand(~ZR36057_VFESPFR_EXT_FL, ZR36057_VFESPFR);
reg = btread(ZR36057_VFEHCR);
if ((reg & (1 << 10)) && zr->card.type != LML33R10)
reg += ((1 << 10) | 1);
btwrite(reg, ZR36057_VFEHCR);
break;
case BUZ_MODE_MOTION_COMPRESS:
case BUZ_MODE_IDLE:
default:
if ((zr->norm & V4L2_STD_NTSC) ||
(zr->card.type == LML33R10 &&
(zr->norm & V4L2_STD_PAL)))
btand(~ZR36057_VFESPFR_EXT_FL, ZR36057_VFESPFR);
else
btor(ZR36057_VFESPFR_EXT_FL, ZR36057_VFESPFR);
reg = btread(ZR36057_VFEHCR);
if (!(reg & (1 << 10)) && zr->card.type != LML33R10)
reg -= ((1 << 10) | 1);
btwrite(reg, ZR36057_VFEHCR);
break;
}
}
/*
* set geometry
*/
static void zr36057_set_vfe(struct zoran *zr, int video_width, int video_height,
const struct zoran_format *format)
{
const struct tvnorm *tvn;
unsigned int h_start, h_end, v_start, v_end;
unsigned int disp_mode;
unsigned int vid_win_wid, vid_win_ht;
unsigned int hcrop1, hcrop2, vcrop1, vcrop2;
unsigned int wa, we, ha, he;
unsigned int X, Y, hor_dcm, ver_dcm;
u32 reg;
tvn = zr->timing;
wa = tvn->wa;
ha = tvn->ha;
pci_dbg(zr->pci_dev, "set_vfe() - width = %d, height = %d\n", video_width, video_height);
if (video_width < BUZ_MIN_WIDTH ||
video_height < BUZ_MIN_HEIGHT ||
video_width > wa || video_height > ha) {
pci_err(zr->pci_dev, "set_vfe: w=%d h=%d not valid\n", video_width, video_height);
return;
}
/**** zr36057 ****/
/* horizontal */
vid_win_wid = video_width;
X = DIV_ROUND_UP(vid_win_wid * 64, tvn->wa);
we = (vid_win_wid * 64) / X;
hor_dcm = 64 - X;
hcrop1 = 2 * ((tvn->wa - we) / 4);
hcrop2 = tvn->wa - we - hcrop1;
h_start = tvn->h_start ? tvn->h_start : 1;
/* (Ronald) Original comment:
* "| 1 Doesn't have any effect, tested on both a DC10 and a DC10+"
* this is false. It inverses chroma values on the LML33R10 (so Cr
* suddenly is shown as Cb and reverse, really cool effect if you
* want to see blue faces, not useful otherwise). So don't use |1.
* However, the DC10 has '0' as h_start, but does need |1, so we
* use a dirty check...
*/
h_end = h_start + tvn->wa - 1;
h_start += hcrop1;
h_end -= hcrop2;
reg = ((h_start & ZR36057_VFEHCR_HMASK) << ZR36057_VFEHCR_H_START)
| ((h_end & ZR36057_VFEHCR_HMASK) << ZR36057_VFEHCR_H_END);
if (zr->card.vfe_pol.hsync_pol)
reg |= ZR36057_VFEHCR_HS_POL;
btwrite(reg, ZR36057_VFEHCR);
/* Vertical */
disp_mode = !(video_height > BUZ_MAX_HEIGHT / 2);
vid_win_ht = disp_mode ? video_height : video_height / 2;
Y = DIV_ROUND_UP(vid_win_ht * 64 * 2, tvn->ha);
he = (vid_win_ht * 64) / Y;
ver_dcm = 64 - Y;
vcrop1 = (tvn->ha / 2 - he) / 2;
vcrop2 = tvn->ha / 2 - he - vcrop1;
v_start = tvn->v_start;
// FIXME SnapShot times out with -1 in 768*576 on the DC10 - LP
v_end = v_start + tvn->ha / 2; // - 1;
v_start += vcrop1;
v_end -= vcrop2;
reg = ((v_start & ZR36057_VFEVCR_VMASK) << ZR36057_VFEVCR_V_START)
| ((v_end & ZR36057_VFEVCR_VMASK) << ZR36057_VFEVCR_V_END);
if (zr->card.vfe_pol.vsync_pol)
reg |= ZR36057_VFEVCR_VS_POL;
btwrite(reg, ZR36057_VFEVCR);
/* scaler and pixel format */
reg = 0;
reg |= (hor_dcm << ZR36057_VFESPFR_HOR_DCM);
reg |= (ver_dcm << ZR36057_VFESPFR_VER_DCM);
reg |= (disp_mode << ZR36057_VFESPFR_DISP_MODE);
/*
* RJ: I don't know, why the following has to be the opposite
* of the corresponding ZR36060 setting, but only this way
* we get the correct colors when uncompressing to the screen
*/
//reg |= ZR36057_VFESPFR_VCLK_POL;
/* RJ: Don't know if that is needed for NTSC also */
if (!(zr->norm & V4L2_STD_NTSC))
reg |= ZR36057_VFESPFR_EXT_FL; // NEEDED!!!!!!! Wolfgang
reg |= ZR36057_VFESPFR_TOP_FIELD;
if (hor_dcm >= 48)
reg |= 3 << ZR36057_VFESPFR_H_FILTER; /* 5 tap filter */
else if (hor_dcm >= 32)
reg |= 2 << ZR36057_VFESPFR_H_FILTER; /* 4 tap filter */
else if (hor_dcm >= 16)
reg |= 1 << ZR36057_VFESPFR_H_FILTER; /* 3 tap filter */
reg |= format->vfespfr;
btwrite(reg, ZR36057_VFESPFR);
/* display configuration */
reg = (16 << ZR36057_VDCR_MIN_PIX)
| (vid_win_ht << ZR36057_VDCR_VID_WIN_HT)
| (vid_win_wid << ZR36057_VDCR_VID_WIN_WID);
if (pci_pci_problems & PCIPCI_TRITON)
// || zr->revision < 1) // Revision 1 has also Triton support
reg &= ~ZR36057_VDCR_TRITON;
else
reg |= ZR36057_VDCR_TRITON;
btwrite(reg, ZR36057_VDCR);
zr36057_adjust_vfe(zr, zr->codec_mode);
}
/* Enable/Disable uncompressed memory grabbing of the 36057 */
void zr36057_set_memgrab(struct zoran *zr, int mode)
{
if (mode) {
/* We only check SnapShot and not FrameGrab here. SnapShot==1
* means a capture is already in progress, but FrameGrab==1
* doesn't necessary mean that. It's more correct to say a 1
* to 0 transition indicates a capture completed. If a
* capture is pending when capturing is tuned off, FrameGrab
* will be stuck at 1 until capturing is turned back on.
*/
if (btread(ZR36057_VSSFGR) & ZR36057_VSSFGR_SNAP_SHOT)
pci_warn(zr->pci_dev, "%s(1) with SnapShot on!?\n", __func__);
/* switch on VSync interrupts */
btwrite(IRQ_MASK, ZR36057_ISR); // Clear Interrupts
btor(zr->card.vsync_int, ZR36057_ICR); // SW
/* enable SnapShot */
btor(ZR36057_VSSFGR_SNAP_SHOT, ZR36057_VSSFGR);
/* Set zr36057 video front end and enable video */
zr36057_set_vfe(zr, zr->v4l_settings.width,
zr->v4l_settings.height,
zr->v4l_settings.format);
} else {
/* switch off VSync interrupts */
btand(~zr->card.vsync_int, ZR36057_ICR); // SW
/* re-enable grabbing to screen if it was running */
btand(~ZR36057_VDCR_VID_EN, ZR36057_VDCR);
btand(~ZR36057_VSSFGR_SNAP_SHOT, ZR36057_VSSFGR);
}
}
/*****************************************************************************
* *
* Set up the Buz-specific MJPEG part *
* *
*****************************************************************************/
static inline void set_frame(struct zoran *zr, int val)
{
GPIO(zr, zr->card.gpio[ZR_GPIO_JPEG_FRAME], val);
}
static void set_videobus_dir(struct zoran *zr, int val)
{
switch (zr->card.type) {
case LML33:
case LML33R10:
if (!lml33dpath)
GPIO(zr, 5, val);
else
GPIO(zr, 5, 1);
break;
default:
GPIO(zr, zr->card.gpio[ZR_GPIO_VID_DIR],
zr->card.gpio_pol[ZR_GPIO_VID_DIR] ? !val : val);
break;
}
}
static void init_jpeg_queue(struct zoran *zr)
{
int i;
/* re-initialize DMA ring stuff */
zr->jpg_que_head = 0;
zr->jpg_dma_head = 0;
zr->jpg_dma_tail = 0;
zr->jpg_que_tail = 0;
zr->jpg_seq_num = 0;
zr->jpeg_error = 0;
zr->num_errors = 0;
zr->jpg_err_seq = 0;
zr->jpg_err_shift = 0;
zr->jpg_queued_num = 0;
for (i = 0; i < BUZ_NUM_STAT_COM; i++)
zr->stat_com[i] = cpu_to_le32(1); /* mark as unavailable to zr36057 */
}
static void zr36057_set_jpg(struct zoran *zr, enum zoran_codec_mode mode)
{
const struct tvnorm *tvn;
u32 reg;
tvn = zr->timing;
/* assert P_Reset, disable code transfer, deassert Active */
btwrite(0, ZR36057_JPC);
/* MJPEG compression mode */
switch (mode) {
case BUZ_MODE_MOTION_COMPRESS:
default:
reg = ZR36057_JMC_MJPG_CMP_MODE;
break;
case BUZ_MODE_MOTION_DECOMPRESS:
reg = ZR36057_JMC_MJPG_EXP_MODE;
reg |= ZR36057_JMC_SYNC_MSTR;
/* RJ: The following is experimental - improves the output to screen */
//if(zr->jpg_settings.VFIFO_FB) reg |= ZR36057_JMC_VFIFO_FB; // No, it doesn't. SM
break;
case BUZ_MODE_STILL_COMPRESS:
reg = ZR36057_JMC_JPG_CMP_MODE;
break;
case BUZ_MODE_STILL_DECOMPRESS:
reg = ZR36057_JMC_JPG_EXP_MODE;
break;
}
reg |= ZR36057_JMC_JPG;
if (zr->jpg_settings.field_per_buff == 1)
reg |= ZR36057_JMC_FLD_PER_BUFF;
btwrite(reg, ZR36057_JMC);
/* vertical */
btor(ZR36057_VFEVCR_VS_POL, ZR36057_VFEVCR);
reg = (6 << ZR36057_VSP_VSYNC_SIZE) |
(tvn->ht << ZR36057_VSP_FRM_TOT);
btwrite(reg, ZR36057_VSP);
reg = ((zr->jpg_settings.img_y + tvn->v_start) << ZR36057_FVAP_NAY) |
(zr->jpg_settings.img_height << ZR36057_FVAP_PAY);
btwrite(reg, ZR36057_FVAP);
/* horizontal */
if (zr->card.vfe_pol.hsync_pol)
btor(ZR36057_VFEHCR_HS_POL, ZR36057_VFEHCR);
else
btand(~ZR36057_VFEHCR_HS_POL, ZR36057_VFEHCR);
reg = ((tvn->h_sync_start) << ZR36057_HSP_HSYNC_START) |
(tvn->wt << ZR36057_HSP_LINE_TOT);
btwrite(reg, ZR36057_HSP);
reg = ((zr->jpg_settings.img_x +
tvn->h_start + 4) << ZR36057_FHAP_NAX) |
(zr->jpg_settings.img_width << ZR36057_FHAP_PAX);
btwrite(reg, ZR36057_FHAP);
/* field process parameters */
if (zr->jpg_settings.odd_even)
reg = ZR36057_FPP_ODD_EVEN;
else
reg = 0;
btwrite(reg, ZR36057_FPP);
/* Set proper VCLK Polarity, else colors will be wrong during playback */
//btor(ZR36057_VFESPFR_VCLK_POL, ZR36057_VFESPFR);
/* code base address */
btwrite(zr->p_sc, ZR36057_JCBA);
/* FIFO threshold (FIFO is 160. double words) */
/* NOTE: decimal values here */
switch (mode) {
case BUZ_MODE_STILL_COMPRESS:
case BUZ_MODE_MOTION_COMPRESS:
if (zr->card.type != BUZ)
reg = 140;
else
reg = 60;
break;
case BUZ_MODE_STILL_DECOMPRESS:
case BUZ_MODE_MOTION_DECOMPRESS:
reg = 20;
break;
default:
reg = 80;
break;
}
btwrite(reg, ZR36057_JCFT);
zr36057_adjust_vfe(zr, mode);
}
void clear_interrupt_counters(struct zoran *zr)
{
zr->intr_counter_GIRQ1 = 0;
zr->intr_counter_GIRQ0 = 0;
zr->intr_counter_cod_rep_irq = 0;
zr->intr_counter_jpeg_rep_irq = 0;
zr->field_counter = 0;
zr->irq1_in = 0;
zr->irq1_out = 0;
zr->jpeg_in = 0;
zr->jpeg_out = 0;
zr->JPEG_0 = 0;
zr->JPEG_1 = 0;
zr->end_event_missed = 0;
zr->jpeg_missed = 0;
zr->jpeg_max_missed = 0;
zr->jpeg_min_missed = 0x7fffffff;
}
static u32 count_reset_interrupt(struct zoran *zr)
{
u32 isr;
isr = btread(ZR36057_ISR) & 0x78000000;
if (isr) {
if (isr & ZR36057_ISR_GIRQ1) {
btwrite(ZR36057_ISR_GIRQ1, ZR36057_ISR);
zr->intr_counter_GIRQ1++;
}
if (isr & ZR36057_ISR_GIRQ0) {
btwrite(ZR36057_ISR_GIRQ0, ZR36057_ISR);
zr->intr_counter_GIRQ0++;
}
if (isr & ZR36057_ISR_COD_REP_IRQ) {
btwrite(ZR36057_ISR_COD_REP_IRQ, ZR36057_ISR);
zr->intr_counter_cod_rep_irq++;
}
if (isr & ZR36057_ISR_JPEG_REP_IRQ) {
btwrite(ZR36057_ISR_JPEG_REP_IRQ, ZR36057_ISR);
zr->intr_counter_jpeg_rep_irq++;
}
}
return isr;
}
void jpeg_start(struct zoran *zr)
{
int reg;
zr->frame_num = 0;
/* deassert P_reset, disable code transfer, deassert Active */
btwrite(ZR36057_JPC_P_RESET, ZR36057_JPC);
/* stop flushing the internal code buffer */
btand(~ZR36057_MCTCR_C_FLUSH, ZR36057_MCTCR);
/* enable code transfer */
btor(ZR36057_JPC_COD_TRNS_EN, ZR36057_JPC);
/* clear IRQs */
btwrite(IRQ_MASK, ZR36057_ISR);
/* enable the JPEG IRQs */
btwrite(zr->card.jpeg_int | ZR36057_ICR_JPEG_REP_IRQ | ZR36057_ICR_INT_PIN_EN,
ZR36057_ICR);
set_frame(zr, 0); // \FRAME
/* set the JPEG codec guest ID */
reg = (zr->card.gpcs[1] << ZR36057_JCGI_JPE_GUEST_ID) |
(0 << ZR36057_JCGI_JPE_GUEST_REG);
btwrite(reg, ZR36057_JCGI);
if (zr->card.video_vfe == CODEC_TYPE_ZR36016 &&
zr->card.video_codec == CODEC_TYPE_ZR36050) {
/* Enable processing on the ZR36016 */
if (zr->vfe)
zr36016_write(zr->vfe, 0, 1);
/* load the address of the GO register in the ZR36050 latch */
post_office_write(zr, 0, 0, 0);
}
/* assert Active */
btor(ZR36057_JPC_ACTIVE, ZR36057_JPC);
/* enable the Go generation */
btor(ZR36057_JMC_GO_EN, ZR36057_JMC);
usleep_range(30, 100);
set_frame(zr, 1); // /FRAME
}
void zr36057_enable_jpg(struct zoran *zr, enum zoran_codec_mode mode)
{
struct vfe_settings cap;
int field_size = zr->buffer_size / zr->jpg_settings.field_per_buff;
zr->codec_mode = mode;
cap.x = zr->jpg_settings.img_x;
cap.y = zr->jpg_settings.img_y;
cap.width = zr->jpg_settings.img_width;
cap.height = zr->jpg_settings.img_height;
cap.decimation =
zr->jpg_settings.hor_dcm | (zr->jpg_settings.ver_dcm << 8);
cap.quality = zr->jpg_settings.jpg_comp.quality;
switch (mode) {
case BUZ_MODE_MOTION_COMPRESS: {
struct jpeg_app_marker app;
struct jpeg_com_marker com;
/* In motion compress mode, the decoder output must be enabled, and
* the video bus direction set to input.
*/
set_videobus_dir(zr, 0);
decoder_call(zr, video, s_stream, 1);
encoder_call(zr, video, s_routing, 0, 0, 0);
/* Take the JPEG codec and the VFE out of sleep */
jpeg_codec_sleep(zr, 0);
/* set JPEG app/com marker */
app.appn = zr->jpg_settings.jpg_comp.APPn;
app.len = zr->jpg_settings.jpg_comp.APP_len;
memcpy(app.data, zr->jpg_settings.jpg_comp.APP_data, 60);
zr->codec->control(zr->codec, CODEC_S_JPEG_APP_DATA,
sizeof(struct jpeg_app_marker), &app);
com.len = zr->jpg_settings.jpg_comp.COM_len;
memcpy(com.data, zr->jpg_settings.jpg_comp.COM_data, 60);
zr->codec->control(zr->codec, CODEC_S_JPEG_COM_DATA,
sizeof(struct jpeg_com_marker), &com);
/* Setup the JPEG codec */
zr->codec->control(zr->codec, CODEC_S_JPEG_TDS_BYTE,
sizeof(int), &field_size);
zr->codec->set_video(zr->codec, zr->timing, &cap,
&zr->card.vfe_pol);
zr->codec->set_mode(zr->codec, CODEC_DO_COMPRESSION);
/* Setup the VFE */
if (zr->vfe) {
zr->vfe->control(zr->vfe, CODEC_S_JPEG_TDS_BYTE,
sizeof(int), &field_size);
zr->vfe->set_video(zr->vfe, zr->timing, &cap,
&zr->card.vfe_pol);
zr->vfe->set_mode(zr->vfe, CODEC_DO_COMPRESSION);
}
init_jpeg_queue(zr);
zr36057_set_jpg(zr, mode); // \P_Reset, ... Video param, FIFO
clear_interrupt_counters(zr);
pci_dbg(zr->pci_dev, "enable_jpg(MOTION_COMPRESS)\n");
break;
}
case BUZ_MODE_MOTION_DECOMPRESS:
/* In motion decompression mode, the decoder output must be disabled, and
* the video bus direction set to output.
*/
decoder_call(zr, video, s_stream, 0);
set_videobus_dir(zr, 1);
encoder_call(zr, video, s_routing, 1, 0, 0);
/* Take the JPEG codec and the VFE out of sleep */
jpeg_codec_sleep(zr, 0);
/* Setup the VFE */
if (zr->vfe) {
zr->vfe->set_video(zr->vfe, zr->timing, &cap,
&zr->card.vfe_pol);
zr->vfe->set_mode(zr->vfe, CODEC_DO_EXPANSION);
}
/* Setup the JPEG codec */
zr->codec->set_video(zr->codec, zr->timing, &cap,
&zr->card.vfe_pol);
zr->codec->set_mode(zr->codec, CODEC_DO_EXPANSION);
init_jpeg_queue(zr);
zr36057_set_jpg(zr, mode); // \P_Reset, ... Video param, FIFO
clear_interrupt_counters(zr);
pci_dbg(zr->pci_dev, "enable_jpg(MOTION_DECOMPRESS)\n");
break;
case BUZ_MODE_IDLE:
default:
/* shut down processing */
btand(~(zr->card.jpeg_int | ZR36057_ICR_JPEG_REP_IRQ),
ZR36057_ICR);
btwrite(zr->card.jpeg_int | ZR36057_ICR_JPEG_REP_IRQ,
ZR36057_ISR);
btand(~ZR36057_JMC_GO_EN, ZR36057_JMC); // \Go_en
msleep(50);
set_videobus_dir(zr, 0);
set_frame(zr, 1); // /FRAME
btor(ZR36057_MCTCR_C_FLUSH, ZR36057_MCTCR); // /CFlush
btwrite(0, ZR36057_JPC); // \P_Reset,\CodTrnsEn,\Active
btand(~ZR36057_JMC_VFIFO_FB, ZR36057_JMC);
btand(~ZR36057_JMC_SYNC_MSTR, ZR36057_JMC);
jpeg_codec_reset(zr);
jpeg_codec_sleep(zr, 1);
zr36057_adjust_vfe(zr, mode);
decoder_call(zr, video, s_stream, 1);
encoder_call(zr, video, s_routing, 0, 0, 0);
pci_dbg(zr->pci_dev, "enable_jpg(IDLE)\n");
break;
}
}
/* when this is called the spinlock must be held */
void zoran_feed_stat_com(struct zoran *zr)
{
/* move frames from pending queue to DMA */
int i, max_stat_com;
struct zr_buffer *buf;
struct vb2_v4l2_buffer *vbuf;
dma_addr_t phys_addr = 0;
unsigned long flags;
unsigned long payload;
max_stat_com =
(zr->jpg_settings.tmp_dcm ==
1) ? BUZ_NUM_STAT_COM : (BUZ_NUM_STAT_COM >> 1);
spin_lock_irqsave(&zr->queued_bufs_lock, flags);
while ((zr->jpg_dma_head - zr->jpg_dma_tail) < max_stat_com) {
buf = list_first_entry_or_null(&zr->queued_bufs, struct zr_buffer, queue);
if (!buf) {
pci_err(zr->pci_dev, "No buffer available to queue\n");
spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
return;
}
list_del(&buf->queue);
zr->buf_in_reserve--;
vbuf = &buf->vbuf;
vbuf->vb2_buf.state = VB2_BUF_STATE_ACTIVE;
phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
payload = vb2_get_plane_payload(&vbuf->vb2_buf, 0);
if (payload == 0)
payload = zr->buffer_size;
if (zr->jpg_settings.tmp_dcm == 1) {
/* fill 1 stat_com entry */
i = (zr->jpg_dma_head -
zr->jpg_err_shift) & BUZ_MASK_STAT_COM;
if (!(zr->stat_com[i] & cpu_to_le32(1)))
break;
zr->stat_comb[i * 2] = cpu_to_le32(phys_addr);
zr->stat_comb[i * 2 + 1] = cpu_to_le32((payload >> 1) | 1);
zr->inuse[i] = buf;
zr->stat_com[i] = cpu_to_le32(zr->p_scb + i * 2 * 4);
} else {
/* fill 2 stat_com entries */
i = ((zr->jpg_dma_head -
zr->jpg_err_shift) & 1) * 2;
if (!(zr->stat_com[i] & cpu_to_le32(1)))
break;
zr->stat_com[i] = cpu_to_le32(zr->p_scb + i * 2 * 4);
zr->stat_com[i + 1] = cpu_to_le32(zr->p_scb + i * 2 * 4);
zr->stat_comb[i * 2] = cpu_to_le32(phys_addr);
zr->stat_comb[i * 2 + 1] = cpu_to_le32((payload >> 1) | 1);
zr->inuse[i] = buf;
zr->inuse[i + 1] = NULL;
}
zr->jpg_dma_head++;
}
spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
if (zr->codec_mode == BUZ_MODE_MOTION_DECOMPRESS)
zr->jpg_queued_num++;
}
/* when this is called the spinlock must be held */
static void zoran_reap_stat_com(struct zoran *zr)
{
/* move frames from DMA queue to done queue */
int i;
u32 stat_com;
unsigned int seq;
unsigned int dif;
unsigned long flags;
struct zr_buffer *buf;
unsigned int size = 0;
u32 fcnt;
/*
* In motion decompress we don't have a hardware frame counter,
* we just count the interrupts here
*/
if (zr->codec_mode == BUZ_MODE_MOTION_DECOMPRESS)
zr->jpg_seq_num++;
spin_lock_irqsave(&zr->queued_bufs_lock, flags);
while (zr->jpg_dma_tail < zr->jpg_dma_head) {
if (zr->jpg_settings.tmp_dcm == 1)
i = (zr->jpg_dma_tail - zr->jpg_err_shift) & BUZ_MASK_STAT_COM;
else
i = ((zr->jpg_dma_tail - zr->jpg_err_shift) & 1) * 2;
stat_com = le32_to_cpu(zr->stat_com[i]);
if ((stat_com & 1) == 0) {
spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
return;
}
fcnt = (stat_com & GENMASK(31, 24)) >> 24;
size = (stat_com & GENMASK(22, 1)) >> 1;
buf = zr->inuse[i];
if (!buf) {
spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
pci_err(zr->pci_dev, "No buffer at slot %d\n", i);
return;
}
buf->vbuf.vb2_buf.timestamp = ktime_get_ns();
if (zr->codec_mode == BUZ_MODE_MOTION_COMPRESS) {
vb2_set_plane_payload(&buf->vbuf.vb2_buf, 0, size);
/* update sequence number with the help of the counter in stat_com */
seq = (fcnt + zr->jpg_err_seq) & 0xff;
dif = (seq - zr->jpg_seq_num) & 0xff;
zr->jpg_seq_num += dif;
}
buf->vbuf.sequence = zr->jpg_settings.tmp_dcm ==
2 ? (zr->jpg_seq_num >> 1) : zr->jpg_seq_num;
zr->inuse[i] = NULL;
if (zr->jpg_settings.tmp_dcm != 1)
buf->vbuf.field = zr->jpg_settings.odd_even ?
V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM;
else
buf->vbuf.field = zr->jpg_settings.odd_even ?
V4L2_FIELD_SEQ_TB : V4L2_FIELD_SEQ_BT;
vb2_buffer_done(&buf->vbuf.vb2_buf, VB2_BUF_STATE_DONE);
zr->jpg_dma_tail++;
}
spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
}
irqreturn_t zoran_irq(int irq, void *dev_id)
{
struct zoran *zr = dev_id;
u32 stat, astat;
stat = count_reset_interrupt(zr);
astat = stat & IRQ_MASK;
if (astat & zr->card.vsync_int) {
if (zr->running == ZORAN_MAP_MODE_RAW) {
if ((btread(ZR36057_VSSFGR) & ZR36057_VSSFGR_SNAP_SHOT) == 0)
pci_warn(zr->pci_dev, "BuzIRQ with SnapShot off ???\n");
if ((btread(ZR36057_VSSFGR) & ZR36057_VSSFGR_FRAME_GRAB) == 0)
zr_set_buf(zr);
return IRQ_HANDLED;
}
if (astat & ZR36057_ISR_JPEG_REP_IRQ) {
if (zr->codec_mode != BUZ_MODE_MOTION_DECOMPRESS &&
zr->codec_mode != BUZ_MODE_MOTION_COMPRESS) {
pci_err(zr->pci_dev, "JPG IRQ when not in good mode\n");
return IRQ_HANDLED;
}
zr->frame_num++;
zoran_reap_stat_com(zr);
zoran_feed_stat_com(zr);
return IRQ_HANDLED;
}
/* unused interrupts */
}
zr->ghost_int++;
return IRQ_HANDLED;
}
void zoran_set_pci_master(struct zoran *zr, int set_master)
{
if (set_master) {
pci_set_master(zr->pci_dev);
} else {
u16 command;
pci_read_config_word(zr->pci_dev, PCI_COMMAND, &command);
command &= ~PCI_COMMAND_MASTER;
pci_write_config_word(zr->pci_dev, PCI_COMMAND, command);
}
}
void zoran_init_hardware(struct zoran *zr)
{
/* Enable bus-mastering */
zoran_set_pci_master(zr, 1);
/* Initialize the board */
if (zr->card.init)
zr->card.init(zr);
decoder_call(zr, core, init, 0);
decoder_call(zr, video, s_std, zr->norm);
decoder_call(zr, video, s_routing,
zr->card.input[zr->input].muxsel, 0, 0);
encoder_call(zr, core, init, 0);
encoder_call(zr, video, s_std_output, zr->norm);
encoder_call(zr, video, s_routing, 0, 0, 0);
/* toggle JPEG codec sleep to sync PLL */
jpeg_codec_sleep(zr, 1);
jpeg_codec_sleep(zr, 0);
/*
* set individual interrupt enables (without GIRQ1)
* but don't global enable until zoran_open()
*/
zr36057_init_vfe(zr);
zr36057_enable_jpg(zr, BUZ_MODE_IDLE);
btwrite(IRQ_MASK, ZR36057_ISR); // Clears interrupts
}
void zr36057_restart(struct zoran *zr)
{
btwrite(0, ZR36057_SPGPPCR);
usleep_range(1000, 2000);
btor(ZR36057_SPGPPCR_SOFT_RESET, ZR36057_SPGPPCR);
usleep_range(1000, 2000);
/* assert P_Reset */
btwrite(0, ZR36057_JPC);
/* set up GPIO direction - all output */
btwrite(ZR36057_SPGPPCR_SOFT_RESET | 0, ZR36057_SPGPPCR);
/* set up GPIO pins and guest bus timing */
btwrite((0x81 << 24) | 0x8888, ZR36057_GPPGCR1);
}
| linux-master | drivers/media/pci/zoran/zoran_device.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Zoran ZR36050 basic configuration functions
*
* Copyright (C) 2001 Wolfgang Scherr <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/wait.h>
/* I/O commands, error codes */
#include <linux/io.h>
/* headerfile of this module */
#include "zr36050.h"
/* codec io API */
#include "videocodec.h"
/*
* it doesn't make sense to have more than 20 or so,
* just to prevent some unwanted loops
*/
#define MAX_CODECS 20
/* amount of chips attached via this driver */
static int zr36050_codecs;
/*
* Local hardware I/O functions:
*
* read/write via codec layer (registers are located in the master device)
*/
/* read and write functions */
static u8 zr36050_read(struct zr36050 *ptr, u16 reg)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
u8 value = 0;
/* just in case something is wrong... */
if (ptr->codec->master_data->readreg)
value = (ptr->codec->master_data->readreg(ptr->codec, reg)) & 0xFF;
else
zrdev_err(zr, "%s: invalid I/O setup, nothing read!\n", ptr->name);
zrdev_dbg(zr, "%s: reading from 0x%04x: %02x\n", ptr->name, reg, value);
return value;
}
static void zr36050_write(struct zr36050 *ptr, u16 reg, u8 value)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
zrdev_dbg(zr, "%s: writing 0x%02x to 0x%04x\n", ptr->name, value, reg);
/* just in case something is wrong... */
if (ptr->codec->master_data->writereg)
ptr->codec->master_data->writereg(ptr->codec, reg, value);
else
zrdev_err(zr, "%s: invalid I/O setup, nothing written!\n",
ptr->name);
}
/* status is kept in datastructure */
static u8 zr36050_read_status1(struct zr36050 *ptr)
{
ptr->status1 = zr36050_read(ptr, ZR050_STATUS_1);
zr36050_read(ptr, 0);
return ptr->status1;
}
/* scale factor is kept in datastructure */
static u16 zr36050_read_scalefactor(struct zr36050 *ptr)
{
ptr->scalefact = (zr36050_read(ptr, ZR050_SF_HI) << 8) |
(zr36050_read(ptr, ZR050_SF_LO) & 0xFF);
/* leave 0 selected for an eventually GO from master */
zr36050_read(ptr, 0);
return ptr->scalefact;
}
/*
* Local helper function:
*
* wait if codec is ready to proceed (end of processing) or time is over
*/
static void zr36050_wait_end(struct zr36050 *ptr)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
int i = 0;
while (!(zr36050_read_status1(ptr) & 0x4)) {
udelay(1);
if (i++ > 200000) { // 200ms, there is for sure something wrong!!!
zrdev_err(zr,
"%s: timeout at wait_end (last status: 0x%02x)\n",
ptr->name, ptr->status1);
break;
}
}
}
/*
* Local helper function: basic test of "connectivity", writes/reads
* to/from memory the SOF marker
*/
static int zr36050_basic_test(struct zr36050 *ptr)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
zr36050_write(ptr, ZR050_SOF_IDX, 0x00);
zr36050_write(ptr, ZR050_SOF_IDX + 1, 0x00);
if ((zr36050_read(ptr, ZR050_SOF_IDX) |
zr36050_read(ptr, ZR050_SOF_IDX + 1)) != 0x0000) {
zrdev_err(zr,
"%s: attach failed, can't connect to jpeg processor!\n",
ptr->name);
return -ENXIO;
}
zr36050_write(ptr, ZR050_SOF_IDX, 0xff);
zr36050_write(ptr, ZR050_SOF_IDX + 1, 0xc0);
if (((zr36050_read(ptr, ZR050_SOF_IDX) << 8) |
zr36050_read(ptr, ZR050_SOF_IDX + 1)) != 0xffc0) {
zrdev_err(zr,
"%s: attach failed, can't connect to jpeg processor!\n",
ptr->name);
return -ENXIO;
}
zr36050_wait_end(ptr);
if ((ptr->status1 & 0x4) == 0) {
zrdev_err(zr,
"%s: attach failed, jpeg processor failed (end flag)!\n",
ptr->name);
return -EBUSY;
}
return 0; /* looks good! */
}
/* Local helper function: simple loop for pushing the init datasets */
static int zr36050_pushit(struct zr36050 *ptr, u16 startreg, u16 len, const char *data)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
int i = 0;
zrdev_dbg(zr, "%s: write data block to 0x%04x (len=%d)\n", ptr->name,
startreg, len);
while (i < len)
zr36050_write(ptr, startreg++, data[i++]);
return i;
}
/*
* Basic datasets:
*
* jpeg baseline setup data (you find it on lots places in internet, or just
* extract it from any regular .jpg image...)
*
* Could be variable, but until it's not needed it they are just fixed to save
* memory. Otherwise expand zr36050 structure with arrays, push the values to
* it and initialize from there, as e.g. the linux zr36057/60 driver does it.
*/
static const char zr36050_dqt[0x86] = {
0xff, 0xdb, //Marker: DQT
0x00, 0x84, //Length: 2*65+2
0x00, //Pq,Tq first table
0x10, 0x0b, 0x0c, 0x0e, 0x0c, 0x0a, 0x10, 0x0e,
0x0d, 0x0e, 0x12, 0x11, 0x10, 0x13, 0x18, 0x28,
0x1a, 0x18, 0x16, 0x16, 0x18, 0x31, 0x23, 0x25,
0x1d, 0x28, 0x3a, 0x33, 0x3d, 0x3c, 0x39, 0x33,
0x38, 0x37, 0x40, 0x48, 0x5c, 0x4e, 0x40, 0x44,
0x57, 0x45, 0x37, 0x38, 0x50, 0x6d, 0x51, 0x57,
0x5f, 0x62, 0x67, 0x68, 0x67, 0x3e, 0x4d, 0x71,
0x79, 0x70, 0x64, 0x78, 0x5c, 0x65, 0x67, 0x63,
0x01, //Pq,Tq second table
0x11, 0x12, 0x12, 0x18, 0x15, 0x18, 0x2f, 0x1a,
0x1a, 0x2f, 0x63, 0x42, 0x38, 0x42, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63
};
static const char zr36050_dht[0x1a4] = {
0xff, 0xc4, //Marker: DHT
0x01, 0xa2, //Length: 2*AC, 2*DC
0x00, //DC first table
0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x01, //DC second table
0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
0x10, //AC first table
0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03,
0x05, 0x05, 0x04, 0x04, 0x00, 0x00,
0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04, 0x11,
0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61,
0x07, 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1,
0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24,
0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17,
0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34,
0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44,
0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66,
0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88,
0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99,
0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8,
0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9,
0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8,
0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9,
0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
0xF8, 0xF9, 0xFA,
0x11, //AC second table
0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04,
0x07, 0x05, 0x04, 0x04, 0x00, 0x01,
0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04,
0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
0xA1, 0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0, 0x15, 0x62,
0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25,
0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A,
0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44,
0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66,
0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
0x79, 0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7,
0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8,
0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8,
0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8,
0xF9, 0xFA
};
/* jpeg baseline setup, this is just fixed in this driver (YUV pictures) */
#define NO_OF_COMPONENTS 0x3 //Y,U,V
#define BASELINE_PRECISION 0x8 //MCU size (?)
static const char zr36050_tq[8] = { 0, 1, 1, 0, 0, 0, 0, 0 }; //table idx's QT
static const char zr36050_td[8] = { 0, 1, 1, 0, 0, 0, 0, 0 }; //table idx's DC
static const char zr36050_ta[8] = { 0, 1, 1, 0, 0, 0, 0, 0 }; //table idx's AC
/* horizontal 422 decimation setup (maybe we support 411 or so later, too) */
static const char zr36050_decimation_h[8] = { 2, 1, 1, 0, 0, 0, 0, 0 };
static const char zr36050_decimation_v[8] = { 1, 1, 1, 0, 0, 0, 0, 0 };
/*
* Local helper functions:
*
* calculation and setup of parameter-dependent JPEG baseline segments
* (needed for compression only)
*/
/* ------------------------------------------------------------------------- */
/*
* SOF (start of frame) segment depends on width, height and sampling ratio
* of each color component
*/
static int zr36050_set_sof(struct zr36050 *ptr)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
char sof_data[34]; // max. size of register set
int i;
zrdev_dbg(zr, "%s: write SOF (%dx%d, %d components)\n", ptr->name,
ptr->width, ptr->height, NO_OF_COMPONENTS);
sof_data[0] = 0xff;
sof_data[1] = 0xc0;
sof_data[2] = 0x00;
sof_data[3] = (3 * NO_OF_COMPONENTS) + 8;
sof_data[4] = BASELINE_PRECISION; // only '8' possible with zr36050
sof_data[5] = (ptr->height) >> 8;
sof_data[6] = (ptr->height) & 0xff;
sof_data[7] = (ptr->width) >> 8;
sof_data[8] = (ptr->width) & 0xff;
sof_data[9] = NO_OF_COMPONENTS;
for (i = 0; i < NO_OF_COMPONENTS; i++) {
sof_data[10 + (i * 3)] = i; // index identifier
sof_data[11 + (i * 3)] = (ptr->h_samp_ratio[i] << 4) |
(ptr->v_samp_ratio[i]); // sampling ratios
sof_data[12 + (i * 3)] = zr36050_tq[i]; // Q table selection
}
return zr36050_pushit(ptr, ZR050_SOF_IDX,
(3 * NO_OF_COMPONENTS) + 10, sof_data);
}
/* ------------------------------------------------------------------------- */
/*
* SOS (start of scan) segment depends on the used scan components
* of each color component
*/
static int zr36050_set_sos(struct zr36050 *ptr)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
char sos_data[16]; // max. size of register set
int i;
zrdev_dbg(zr, "%s: write SOS\n", ptr->name);
sos_data[0] = 0xff;
sos_data[1] = 0xda;
sos_data[2] = 0x00;
sos_data[3] = 2 + 1 + (2 * NO_OF_COMPONENTS) + 3;
sos_data[4] = NO_OF_COMPONENTS;
for (i = 0; i < NO_OF_COMPONENTS; i++) {
sos_data[5 + (i * 2)] = i; // index
sos_data[6 + (i * 2)] = (zr36050_td[i] << 4) | zr36050_ta[i]; // AC/DC tbl.sel.
}
sos_data[2 + 1 + (2 * NO_OF_COMPONENTS) + 2] = 00; // scan start
sos_data[2 + 1 + (2 * NO_OF_COMPONENTS) + 3] = 0x3F;
sos_data[2 + 1 + (2 * NO_OF_COMPONENTS) + 4] = 00;
return zr36050_pushit(ptr, ZR050_SOS1_IDX,
4 + 1 + (2 * NO_OF_COMPONENTS) + 3,
sos_data);
}
/* ------------------------------------------------------------------------- */
/* DRI (define restart interval) */
static int zr36050_set_dri(struct zr36050 *ptr)
{
struct zoran *zr = videocodec_to_zoran(ptr->codec);
char dri_data[6]; // max. size of register set
zrdev_dbg(zr, "%s: write DRI\n", ptr->name);
dri_data[0] = 0xff;
dri_data[1] = 0xdd;
dri_data[2] = 0x00;
dri_data[3] = 0x04;
dri_data[4] = ptr->dri >> 8;
dri_data[5] = ptr->dri & 0xff;
return zr36050_pushit(ptr, ZR050_DRI_IDX, 6, dri_data);
}
/*
* Setup function:
*
* Setup compression/decompression of Zoran's JPEG processor
* ( see also zoran 36050 manual )
*
* ... sorry for the spaghetti code ...
*/
static void zr36050_init(struct zr36050 *ptr)
{
int sum = 0;
long bitcnt, tmp;
struct zoran *zr = videocodec_to_zoran(ptr->codec);
if (ptr->mode == CODEC_DO_COMPRESSION) {
zrdev_dbg(zr, "%s: COMPRESSION SETUP\n", ptr->name);
/* 050 communicates with 057 in master mode */
zr36050_write(ptr, ZR050_HARDWARE, ZR050_HW_MSTR);
/* encoding table preload for compression */
zr36050_write(ptr, ZR050_MODE,
ZR050_MO_COMP | ZR050_MO_TLM);
zr36050_write(ptr, ZR050_OPTIONS, 0);
/* disable all IRQs */
zr36050_write(ptr, ZR050_INT_REQ_0, 0);
zr36050_write(ptr, ZR050_INT_REQ_1, 3); // low 2 bits always 1
/* volume control settings */
/*zr36050_write(ptr, ZR050_MBCV, ptr->max_block_vol);*/
zr36050_write(ptr, ZR050_SF_HI, ptr->scalefact >> 8);
zr36050_write(ptr, ZR050_SF_LO, ptr->scalefact & 0xff);
zr36050_write(ptr, ZR050_AF_HI, 0xff);
zr36050_write(ptr, ZR050_AF_M, 0xff);
zr36050_write(ptr, ZR050_AF_LO, 0xff);
/* setup the variable jpeg tables */
sum += zr36050_set_sof(ptr);
sum += zr36050_set_sos(ptr);
sum += zr36050_set_dri(ptr);
/*
* setup the fixed jpeg tables - maybe variable, though -
* (see table init section above)
*/
zrdev_dbg(zr, "%s: write DQT, DHT, APP\n", ptr->name);
sum += zr36050_pushit(ptr, ZR050_DQT_IDX,
sizeof(zr36050_dqt), zr36050_dqt);
sum += zr36050_pushit(ptr, ZR050_DHT_IDX,
sizeof(zr36050_dht), zr36050_dht);
zr36050_write(ptr, ZR050_APP_IDX, 0xff);
zr36050_write(ptr, ZR050_APP_IDX + 1, 0xe0 + ptr->app.appn);
zr36050_write(ptr, ZR050_APP_IDX + 2, 0x00);
zr36050_write(ptr, ZR050_APP_IDX + 3, ptr->app.len + 2);
sum += zr36050_pushit(ptr, ZR050_APP_IDX + 4, 60,
ptr->app.data) + 4;
zr36050_write(ptr, ZR050_COM_IDX, 0xff);
zr36050_write(ptr, ZR050_COM_IDX + 1, 0xfe);
zr36050_write(ptr, ZR050_COM_IDX + 2, 0x00);
zr36050_write(ptr, ZR050_COM_IDX + 3, ptr->com.len + 2);
sum += zr36050_pushit(ptr, ZR050_COM_IDX + 4, 60,
ptr->com.data) + 4;
/* do the internal huffman table preload */
zr36050_write(ptr, ZR050_MARKERS_EN, ZR050_ME_DHTI);
zr36050_write(ptr, ZR050_GO, 1); // launch codec
zr36050_wait_end(ptr);
zrdev_dbg(zr, "%s: Status after table preload: 0x%02x\n",
ptr->name, ptr->status1);
if ((ptr->status1 & 0x4) == 0) {
zrdev_err(zr, "%s: init aborted!\n", ptr->name);
return; // something is wrong, its timed out!!!!
}
/* setup misc. data for compression (target code sizes) */
/* size of compressed code to reach without header data */
sum = ptr->real_code_vol - sum;
bitcnt = sum << 3; /* need the size in bits */
tmp = bitcnt >> 16;
zrdev_dbg(zr,
"%s: code: csize=%d, tot=%d, bit=%ld, highbits=%ld\n",
ptr->name, sum, ptr->real_code_vol, bitcnt, tmp);
zr36050_write(ptr, ZR050_TCV_NET_HI, tmp >> 8);
zr36050_write(ptr, ZR050_TCV_NET_MH, tmp & 0xff);
tmp = bitcnt & 0xffff;
zr36050_write(ptr, ZR050_TCV_NET_ML, tmp >> 8);
zr36050_write(ptr, ZR050_TCV_NET_LO, tmp & 0xff);
bitcnt -= bitcnt >> 7; // bits without stuffing
bitcnt -= ((bitcnt * 5) >> 6); // bits without eob
tmp = bitcnt >> 16;
zrdev_dbg(zr, "%s: code: nettobit=%ld, highnettobits=%ld\n",
ptr->name, bitcnt, tmp);
zr36050_write(ptr, ZR050_TCV_DATA_HI, tmp >> 8);
zr36050_write(ptr, ZR050_TCV_DATA_MH, tmp & 0xff);
tmp = bitcnt & 0xffff;
zr36050_write(ptr, ZR050_TCV_DATA_ML, tmp >> 8);
zr36050_write(ptr, ZR050_TCV_DATA_LO, tmp & 0xff);
/* compression setup with or without bitrate control */
zr36050_write(ptr, ZR050_MODE,
ZR050_MO_COMP | ZR050_MO_PASS2 |
(ptr->bitrate_ctrl ? ZR050_MO_BRC : 0));
/* this headers seem to deliver "valid AVI" jpeg frames */
zr36050_write(ptr, ZR050_MARKERS_EN,
ZR050_ME_DQT | ZR050_ME_DHT |
((ptr->app.len > 0) ? ZR050_ME_APP : 0) |
((ptr->com.len > 0) ? ZR050_ME_COM : 0));
} else {
zrdev_dbg(zr, "%s: EXPANSION SETUP\n", ptr->name);
/* 050 communicates with 055 in master mode */
zr36050_write(ptr, ZR050_HARDWARE,
ZR050_HW_MSTR | ZR050_HW_CFIS_2_CLK);
/* encoding table preload */
zr36050_write(ptr, ZR050_MODE, ZR050_MO_TLM);
/* disable all IRQs */
zr36050_write(ptr, ZR050_INT_REQ_0, 0);
zr36050_write(ptr, ZR050_INT_REQ_1, 3); // low 2 bits always 1
zrdev_dbg(zr, "%s: write DHT\n", ptr->name);
zr36050_pushit(ptr, ZR050_DHT_IDX, sizeof(zr36050_dht),
zr36050_dht);
/* do the internal huffman table preload */
zr36050_write(ptr, ZR050_MARKERS_EN, ZR050_ME_DHTI);
zr36050_write(ptr, ZR050_GO, 1); // launch codec
zr36050_wait_end(ptr);
zrdev_dbg(zr, "%s: Status after table preload: 0x%02x\n",
ptr->name, ptr->status1);
if ((ptr->status1 & 0x4) == 0) {
zrdev_err(zr, "%s: init aborted!\n", ptr->name);
return; // something is wrong, its timed out!!!!
}
/* setup misc. data for expansion */
zr36050_write(ptr, ZR050_MODE, 0);
zr36050_write(ptr, ZR050_MARKERS_EN, 0);
}
/* adr on selected, to allow GO from master */
zr36050_read(ptr, 0);
}
/*
* CODEC API FUNCTIONS
*
* this functions are accessed by the master via the API structure
*/
/*
* set compression/expansion mode and launches codec -
* this should be the last call from the master before starting processing
*/
static int zr36050_set_mode(struct videocodec *codec, int mode)
{
struct zr36050 *ptr = (struct zr36050 *)codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
zrdev_dbg(zr, "%s: set_mode %d call\n", ptr->name, mode);
if ((mode != CODEC_DO_EXPANSION) && (mode != CODEC_DO_COMPRESSION))
return -EINVAL;
ptr->mode = mode;
zr36050_init(ptr);
return 0;
}
/* set picture size (norm is ignored as the codec doesn't know about it) */
static int zr36050_set_video(struct videocodec *codec, const struct tvnorm *norm,
struct vfe_settings *cap, struct vfe_polarity *pol)
{
struct zr36050 *ptr = (struct zr36050 *)codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
int size;
zrdev_dbg(zr, "%s: set_video %d.%d, %d/%d-%dx%d (0x%x) q%d call\n",
ptr->name, norm->h_start, norm->v_start,
cap->x, cap->y, cap->width, cap->height,
cap->decimation, cap->quality);
/*
* trust the master driver that it knows what it does - so
* we allow invalid startx/y and norm for now ...
*/
ptr->width = cap->width / (cap->decimation & 0xff);
ptr->height = cap->height / ((cap->decimation >> 8) & 0xff);
/* (KM) JPEG quality */
size = ptr->width * ptr->height;
size *= 16; /* size in bits */
/* apply quality setting */
size = size * cap->quality / 200;
/* Minimum: 1kb */
if (size < 8192)
size = 8192;
/* Maximum: 7/8 of code buffer */
if (size > ptr->total_code_vol * 7)
size = ptr->total_code_vol * 7;
ptr->real_code_vol = size >> 3; /* in bytes */
/*
* Set max_block_vol here (previously in zr36050_init, moved
* here for consistency with zr36060 code
*/
zr36050_write(ptr, ZR050_MBCV, ptr->max_block_vol);
return 0;
}
/* additional control functions */
static int zr36050_control(struct videocodec *codec, int type, int size, void *data)
{
struct zr36050 *ptr = (struct zr36050 *)codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
int *ival = (int *)data;
zrdev_dbg(zr, "%s: control %d call with %d byte\n", ptr->name, type,
size);
switch (type) {
case CODEC_G_STATUS: /* get last status */
if (size != sizeof(int))
return -EFAULT;
zr36050_read_status1(ptr);
*ival = ptr->status1;
break;
case CODEC_G_CODEC_MODE:
if (size != sizeof(int))
return -EFAULT;
*ival = CODEC_MODE_BJPG;
break;
case CODEC_S_CODEC_MODE:
if (size != sizeof(int))
return -EFAULT;
if (*ival != CODEC_MODE_BJPG)
return -EINVAL;
/* not needed, do nothing */
return 0;
case CODEC_G_VFE:
case CODEC_S_VFE:
/* not needed, do nothing */
return 0;
case CODEC_S_MMAP:
/* not available, give an error */
return -ENXIO;
case CODEC_G_JPEG_TDS_BYTE: /* get target volume in byte */
if (size != sizeof(int))
return -EFAULT;
*ival = ptr->total_code_vol;
break;
case CODEC_S_JPEG_TDS_BYTE: /* get target volume in byte */
if (size != sizeof(int))
return -EFAULT;
ptr->total_code_vol = *ival;
ptr->real_code_vol = (ptr->total_code_vol * 6) >> 3;
break;
case CODEC_G_JPEG_SCALE: /* get scaling factor */
if (size != sizeof(int))
return -EFAULT;
*ival = zr36050_read_scalefactor(ptr);
break;
case CODEC_S_JPEG_SCALE: /* set scaling factor */
if (size != sizeof(int))
return -EFAULT;
ptr->scalefact = *ival;
break;
case CODEC_G_JPEG_APP_DATA: { /* get appn marker data */
struct jpeg_app_marker *app = data;
if (size != sizeof(struct jpeg_app_marker))
return -EFAULT;
*app = ptr->app;
break;
}
case CODEC_S_JPEG_APP_DATA: { /* set appn marker data */
struct jpeg_app_marker *app = data;
if (size != sizeof(struct jpeg_app_marker))
return -EFAULT;
ptr->app = *app;
break;
}
case CODEC_G_JPEG_COM_DATA: { /* get comment marker data */
struct jpeg_com_marker *com = data;
if (size != sizeof(struct jpeg_com_marker))
return -EFAULT;
*com = ptr->com;
break;
}
case CODEC_S_JPEG_COM_DATA: { /* set comment marker data */
struct jpeg_com_marker *com = data;
if (size != sizeof(struct jpeg_com_marker))
return -EFAULT;
ptr->com = *com;
break;
}
default:
return -EINVAL;
}
return size;
}
/* Exit and unregister function: Deinitializes Zoran's JPEG processor */
static int zr36050_unset(struct videocodec *codec)
{
struct zr36050 *ptr = codec->data;
struct zoran *zr = videocodec_to_zoran(codec);
if (ptr) {
/* do wee need some codec deinit here, too ???? */
zrdev_dbg(zr, "%s: finished codec #%d\n", ptr->name,
ptr->num);
kfree(ptr);
codec->data = NULL;
zr36050_codecs--;
return 0;
}
return -EFAULT;
}
/*
* Setup and registry function:
*
* Initializes Zoran's JPEG processor
*
* Also sets pixel size, average code size, mode (compr./decompr.)
* (the given size is determined by the processor with the video interface)
*/
static int zr36050_setup(struct videocodec *codec)
{
struct zr36050 *ptr;
struct zoran *zr = videocodec_to_zoran(codec);
int res;
zrdev_dbg(zr, "zr36050: initializing MJPEG subsystem #%d.\n",
zr36050_codecs);
if (zr36050_codecs == MAX_CODECS) {
zrdev_err(zr,
"zr36050: Can't attach more codecs!\n");
return -ENOSPC;
}
//mem structure init
ptr = kzalloc(sizeof(*ptr), GFP_KERNEL);
codec->data = ptr;
if (!ptr)
return -ENOMEM;
snprintf(ptr->name, sizeof(ptr->name), "zr36050[%d]",
zr36050_codecs);
ptr->num = zr36050_codecs++;
ptr->codec = codec;
//testing
res = zr36050_basic_test(ptr);
if (res < 0) {
zr36050_unset(codec);
return res;
}
//final setup
memcpy(ptr->h_samp_ratio, zr36050_decimation_h, 8);
memcpy(ptr->v_samp_ratio, zr36050_decimation_v, 8);
/* 0 or 1 - fixed file size flag (what is the difference?) */
ptr->bitrate_ctrl = 0;
ptr->mode = CODEC_DO_COMPRESSION;
ptr->width = 384;
ptr->height = 288;
ptr->total_code_vol = 16000;
ptr->max_block_vol = 240;
ptr->scalefact = 0x100;
ptr->dri = 1;
/* no app/com marker by default */
ptr->app.appn = 0;
ptr->app.len = 0;
ptr->com.len = 0;
zr36050_init(ptr);
zrdev_info(zr, "%s: codec attached and running\n",
ptr->name);
return 0;
}
static const struct videocodec zr36050_codec = {
.name = "zr36050",
.magic = 0L, // magic not used
.flags =
CODEC_FLAG_JPEG | CODEC_FLAG_HARDWARE | CODEC_FLAG_ENCODER |
CODEC_FLAG_DECODER,
.type = CODEC_TYPE_ZR36050,
.setup = zr36050_setup, // functionality
.unset = zr36050_unset,
.set_mode = zr36050_set_mode,
.set_video = zr36050_set_video,
.control = zr36050_control,
// others are not used
};
/* HOOK IN DRIVER AS KERNEL MODULE */
int zr36050_init_module(void)
{
zr36050_codecs = 0;
return videocodec_register(&zr36050_codec);
}
void zr36050_cleanup_module(void)
{
if (zr36050_codecs) {
pr_debug("zr36050: something's wrong - %d codecs left somehow.\n",
zr36050_codecs);
}
videocodec_unregister(&zr36050_codec);
}
| linux-master | drivers/media/pci/zoran/zr36050.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Zoran zr36057/zr36067 PCI controller driver, for the
* Pinnacle/Miro DC10/DC10+/DC30/DC30+, Iomega Buz, Linux
* Media Labs LML33/LML33R10.
*
* Copyright (C) 2000 Serguei Miridonov <[email protected]>
*
* Changes for BUZ by Wolfgang Scherr <[email protected]>
*
* Changes for DC10/DC30 by Laurent Pinchart <[email protected]>
*
* Changes for LML33R10 by Maxim Yevtyushkin <[email protected]>
*
* Changes for videodev2/v4l2 by Ronald Bultje <[email protected]>
*
* Based on
*
* Miro DC10 driver
* Copyright (C) 1999 Wolfgang Scherr <[email protected]>
*
* Iomega Buz driver version 1.0
* Copyright (C) 1999 Rainer Johanni <[email protected]>
*
* buz.0.0.3
* Copyright (C) 1998 Dave Perks <[email protected]>
*
* bttv - Bt848 frame grabber driver
* Copyright (C) 1996,97,98 Ralph Metzler ([email protected])
* & Marcus Metzler ([email protected])
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/wait.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/spinlock.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-event.h>
#include "videocodec.h"
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/mutex.h>
#include "zoran.h"
#include "zoran_device.h"
#include "zoran_card.h"
const struct zoran_format zoran_formats[] = {
{
.name = "15-bit RGB LE",
.fourcc = V4L2_PIX_FMT_RGB555,
.colorspace = V4L2_COLORSPACE_SRGB,
.depth = 15,
.flags = ZORAN_FORMAT_CAPTURE,
.vfespfr = ZR36057_VFESPFR_RGB555 | ZR36057_VFESPFR_ERR_DIF |
ZR36057_VFESPFR_LITTLE_ENDIAN,
}, {
.name = "15-bit RGB BE",
.fourcc = V4L2_PIX_FMT_RGB555X,
.colorspace = V4L2_COLORSPACE_SRGB,
.depth = 15,
.flags = ZORAN_FORMAT_CAPTURE,
.vfespfr = ZR36057_VFESPFR_RGB555 | ZR36057_VFESPFR_ERR_DIF,
}, {
.name = "16-bit RGB LE",
.fourcc = V4L2_PIX_FMT_RGB565,
.colorspace = V4L2_COLORSPACE_SRGB,
.depth = 16,
.flags = ZORAN_FORMAT_CAPTURE,
.vfespfr = ZR36057_VFESPFR_RGB565 | ZR36057_VFESPFR_ERR_DIF |
ZR36057_VFESPFR_LITTLE_ENDIAN,
}, {
.name = "16-bit RGB BE",
.fourcc = V4L2_PIX_FMT_RGB565X,
.colorspace = V4L2_COLORSPACE_SRGB,
.depth = 16,
.flags = ZORAN_FORMAT_CAPTURE,
.vfespfr = ZR36057_VFESPFR_RGB565 | ZR36057_VFESPFR_ERR_DIF,
}, {
.name = "24-bit RGB",
.fourcc = V4L2_PIX_FMT_BGR24,
.colorspace = V4L2_COLORSPACE_SRGB,
.depth = 24,
.flags = ZORAN_FORMAT_CAPTURE,
.vfespfr = ZR36057_VFESPFR_RGB888 | ZR36057_VFESPFR_PACK24,
}, {
.name = "32-bit RGB LE",
.fourcc = V4L2_PIX_FMT_BGR32,
.colorspace = V4L2_COLORSPACE_SRGB,
.depth = 32,
.flags = ZORAN_FORMAT_CAPTURE,
.vfespfr = ZR36057_VFESPFR_RGB888 | ZR36057_VFESPFR_LITTLE_ENDIAN,
}, {
.name = "32-bit RGB BE",
.fourcc = V4L2_PIX_FMT_RGB32,
.colorspace = V4L2_COLORSPACE_SRGB,
.depth = 32,
.flags = ZORAN_FORMAT_CAPTURE,
.vfespfr = ZR36057_VFESPFR_RGB888,
}, {
.name = "4:2:2, packed, YUYV",
.fourcc = V4L2_PIX_FMT_YUYV,
.colorspace = V4L2_COLORSPACE_SMPTE170M,
.depth = 16,
.flags = ZORAN_FORMAT_CAPTURE,
.vfespfr = ZR36057_VFESPFR_YUV422,
}, {
.name = "4:2:2, packed, UYVY",
.fourcc = V4L2_PIX_FMT_UYVY,
.colorspace = V4L2_COLORSPACE_SMPTE170M,
.depth = 16,
.flags = ZORAN_FORMAT_CAPTURE,
.vfespfr = ZR36057_VFESPFR_YUV422 | ZR36057_VFESPFR_LITTLE_ENDIAN,
}, {
.name = "Hardware-encoded Motion-JPEG",
.fourcc = V4L2_PIX_FMT_MJPEG,
.colorspace = V4L2_COLORSPACE_SMPTE170M,
.depth = 0,
.flags = ZORAN_FORMAT_CAPTURE |
ZORAN_FORMAT_PLAYBACK |
ZORAN_FORMAT_COMPRESSED,
}
};
#define NUM_FORMATS ARRAY_SIZE(zoran_formats)
/*
* small helper function for calculating buffersizes for v4l2
* we calculate the nearest higher power-of-two, which
* will be the recommended buffersize
*/
static __u32 zoran_v4l2_calc_bufsize(struct zoran_jpg_settings *settings)
{
__u8 div = settings->ver_dcm * settings->hor_dcm * settings->tmp_dcm;
__u32 num = (1024 * 512) / (div);
__u32 result = 2;
num--;
while (num) {
num >>= 1;
result <<= 1;
}
if (result < 8192)
return 8192;
return result;
}
/*
* V4L Buffer grabbing
*/
static int zoran_v4l_set_format(struct zoran *zr, int width, int height,
const struct zoran_format *format)
{
int bpp;
/* Check size and format of the grab wanted */
if (height < BUZ_MIN_HEIGHT || width < BUZ_MIN_WIDTH ||
height > BUZ_MAX_HEIGHT || width > BUZ_MAX_WIDTH) {
pci_dbg(zr->pci_dev, "%s - wrong frame size (%dx%d)\n", __func__, width, height);
return -EINVAL;
}
bpp = (format->depth + 7) / 8;
zr->buffer_size = height * width * bpp;
/* Check against available buffer size */
if (height * width * bpp > zr->buffer_size) {
pci_dbg(zr->pci_dev, "%s - video buffer size (%d kB) is too small\n",
__func__, zr->buffer_size >> 10);
return -EINVAL;
}
/* The video front end needs 4-byte alinged line sizes */
if ((bpp == 2 && (width & 1)) || (bpp == 3 && (width & 3))) {
pci_dbg(zr->pci_dev, "%s - wrong frame alignment\n", __func__);
return -EINVAL;
}
zr->v4l_settings.width = width;
zr->v4l_settings.height = height;
zr->v4l_settings.format = format;
zr->v4l_settings.bytesperline = bpp * zr->v4l_settings.width;
return 0;
}
static int zoran_set_norm(struct zoran *zr, v4l2_std_id norm)
{
if (!(norm & zr->card.norms)) {
pci_dbg(zr->pci_dev, "%s - unsupported norm %llx\n", __func__, norm);
return -EINVAL;
}
if (norm & V4L2_STD_SECAM)
zr->timing = zr->card.tvn[ZR_NORM_SECAM];
else if (norm & V4L2_STD_NTSC)
zr->timing = zr->card.tvn[ZR_NORM_NTSC];
else
zr->timing = zr->card.tvn[ZR_NORM_PAL];
decoder_call(zr, video, s_std, norm);
encoder_call(zr, video, s_std_output, norm);
/* Make sure the changes come into effect */
zr->norm = norm;
return 0;
}
static int zoran_set_input(struct zoran *zr, int input)
{
if (input == zr->input)
return 0;
if (input < 0 || input >= zr->card.inputs) {
pci_dbg(zr->pci_dev, "%s - unsupported input %d\n", __func__, input);
return -EINVAL;
}
zr->input = input;
decoder_call(zr, video, s_routing, zr->card.input[input].muxsel, 0, 0);
return 0;
}
/*
* ioctl routine
*/
static int zoran_querycap(struct file *file, void *__fh, struct v4l2_capability *cap)
{
struct zoran *zr = video_drvdata(file);
strscpy(cap->card, ZR_DEVNAME(zr), sizeof(cap->card));
strscpy(cap->driver, "zoran", sizeof(cap->driver));
snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s", pci_name(zr->pci_dev));
return 0;
}
static int zoran_enum_fmt(struct zoran *zr, struct v4l2_fmtdesc *fmt, int flag)
{
unsigned int num, i;
if (fmt->index >= ARRAY_SIZE(zoran_formats))
return -EINVAL;
if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
for (num = i = 0; i < NUM_FORMATS; i++) {
if (zoran_formats[i].flags & flag && num++ == fmt->index) {
strscpy(fmt->description, zoran_formats[i].name,
sizeof(fmt->description));
/* fmt struct pre-zeroed, so adding '\0' not needed */
fmt->pixelformat = zoran_formats[i].fourcc;
if (zoran_formats[i].flags & ZORAN_FORMAT_COMPRESSED)
fmt->flags |= V4L2_FMT_FLAG_COMPRESSED;
return 0;
}
}
return -EINVAL;
}
static int zoran_enum_fmt_vid_cap(struct file *file, void *__fh,
struct v4l2_fmtdesc *f)
{
struct zoran *zr = video_drvdata(file);
return zoran_enum_fmt(zr, f, ZORAN_FORMAT_CAPTURE);
}
static int zoran_g_fmt_vid_out(struct file *file, void *__fh,
struct v4l2_format *fmt)
{
struct zoran *zr = video_drvdata(file);
fmt->fmt.pix.width = zr->jpg_settings.img_width / zr->jpg_settings.hor_dcm;
fmt->fmt.pix.height = zr->jpg_settings.img_height * 2 /
(zr->jpg_settings.ver_dcm * zr->jpg_settings.tmp_dcm);
fmt->fmt.pix.sizeimage = zr->buffer_size;
fmt->fmt.pix.pixelformat = V4L2_PIX_FMT_MJPEG;
if (zr->jpg_settings.tmp_dcm == 1)
fmt->fmt.pix.field = (zr->jpg_settings.odd_even ?
V4L2_FIELD_SEQ_TB : V4L2_FIELD_SEQ_BT);
else
fmt->fmt.pix.field = (zr->jpg_settings.odd_even ?
V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM);
fmt->fmt.pix.bytesperline = 0;
fmt->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
return 0;
}
static int zoran_g_fmt_vid_cap(struct file *file, void *__fh,
struct v4l2_format *fmt)
{
struct zoran *zr = video_drvdata(file);
if (zr->map_mode != ZORAN_MAP_MODE_RAW)
return zoran_g_fmt_vid_out(file, __fh, fmt);
fmt->fmt.pix.width = zr->v4l_settings.width;
fmt->fmt.pix.height = zr->v4l_settings.height;
fmt->fmt.pix.sizeimage = zr->buffer_size;
fmt->fmt.pix.pixelformat = zr->v4l_settings.format->fourcc;
fmt->fmt.pix.colorspace = zr->v4l_settings.format->colorspace;
fmt->fmt.pix.bytesperline = zr->v4l_settings.bytesperline;
if (BUZ_MAX_HEIGHT < (zr->v4l_settings.height * 2))
fmt->fmt.pix.field = V4L2_FIELD_INTERLACED;
else
fmt->fmt.pix.field = V4L2_FIELD_TOP;
return 0;
}
static int zoran_try_fmt_vid_out(struct file *file, void *__fh,
struct v4l2_format *fmt)
{
struct zoran *zr = video_drvdata(file);
struct zoran_jpg_settings settings;
int res = 0;
if (fmt->fmt.pix.pixelformat != V4L2_PIX_FMT_MJPEG)
return -EINVAL;
settings = zr->jpg_settings;
/* we actually need to set 'real' parameters now */
if ((fmt->fmt.pix.height * 2) > BUZ_MAX_HEIGHT)
settings.tmp_dcm = 1;
else
settings.tmp_dcm = 2;
settings.decimation = 0;
if (fmt->fmt.pix.height <= zr->jpg_settings.img_height / 2)
settings.ver_dcm = 2;
else
settings.ver_dcm = 1;
if (fmt->fmt.pix.width <= zr->jpg_settings.img_width / 4)
settings.hor_dcm = 4;
else if (fmt->fmt.pix.width <= zr->jpg_settings.img_width / 2)
settings.hor_dcm = 2;
else
settings.hor_dcm = 1;
if (settings.tmp_dcm == 1)
settings.field_per_buff = 2;
else
settings.field_per_buff = 1;
if (settings.hor_dcm > 1) {
settings.img_x = (BUZ_MAX_WIDTH == 720) ? 8 : 0;
settings.img_width = (BUZ_MAX_WIDTH == 720) ? 704 : BUZ_MAX_WIDTH;
} else {
settings.img_x = 0;
settings.img_width = BUZ_MAX_WIDTH;
}
/* check */
res = zoran_check_jpg_settings(zr, &settings, 1);
if (res)
return res;
/* tell the user what we actually did */
fmt->fmt.pix.width = settings.img_width / settings.hor_dcm;
fmt->fmt.pix.height = settings.img_height * 2 /
(settings.tmp_dcm * settings.ver_dcm);
if (settings.tmp_dcm == 1)
fmt->fmt.pix.field = (zr->jpg_settings.odd_even ?
V4L2_FIELD_SEQ_TB : V4L2_FIELD_SEQ_BT);
else
fmt->fmt.pix.field = (zr->jpg_settings.odd_even ?
V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM);
fmt->fmt.pix.sizeimage = zoran_v4l2_calc_bufsize(&settings);
fmt->fmt.pix.bytesperline = 0;
fmt->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
return res;
}
static int zoran_try_fmt_vid_cap(struct file *file, void *__fh,
struct v4l2_format *fmt)
{
struct zoran *zr = video_drvdata(file);
int bpp;
int i;
if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_MJPEG)
return zoran_try_fmt_vid_out(file, __fh, fmt);
for (i = 0; i < NUM_FORMATS; i++)
if (zoran_formats[i].fourcc == fmt->fmt.pix.pixelformat)
break;
if (i == NUM_FORMATS) {
/* TODO do not return here to fix the TRY_FMT cannot handle an invalid pixelformat*/
return -EINVAL;
}
fmt->fmt.pix.pixelformat = zoran_formats[i].fourcc;
fmt->fmt.pix.colorspace = zoran_formats[i].colorspace;
if (BUZ_MAX_HEIGHT < (fmt->fmt.pix.height * 2))
fmt->fmt.pix.field = V4L2_FIELD_INTERLACED;
else
fmt->fmt.pix.field = V4L2_FIELD_TOP;
bpp = DIV_ROUND_UP(zoran_formats[i].depth, 8);
v4l_bound_align_image(&fmt->fmt.pix.width, BUZ_MIN_WIDTH, BUZ_MAX_WIDTH,
bpp == 2 ? 1 : 2,
&fmt->fmt.pix.height, BUZ_MIN_HEIGHT, BUZ_MAX_HEIGHT,
0, 0);
fmt->fmt.pix.bytesperline = fmt->fmt.pix.width * bpp;
fmt->fmt.pix.sizeimage = fmt->fmt.pix.bytesperline * fmt->fmt.pix.height;
return 0;
}
static int zoran_s_fmt_vid_out(struct file *file, void *__fh,
struct v4l2_format *fmt)
{
struct zoran *zr = video_drvdata(file);
__le32 printformat = __cpu_to_le32(fmt->fmt.pix.pixelformat);
struct zoran_jpg_settings settings;
int res = 0;
pci_dbg(zr->pci_dev, "size=%dx%d, fmt=0x%x (%4.4s)\n",
fmt->fmt.pix.width, fmt->fmt.pix.height,
fmt->fmt.pix.pixelformat,
(char *)&printformat);
if (fmt->fmt.pix.pixelformat != V4L2_PIX_FMT_MJPEG)
return -EINVAL;
if (!fmt->fmt.pix.height || !fmt->fmt.pix.width)
return -EINVAL;
settings = zr->jpg_settings;
/* we actually need to set 'real' parameters now */
if (fmt->fmt.pix.height * 2 > BUZ_MAX_HEIGHT)
settings.tmp_dcm = 1;
else
settings.tmp_dcm = 2;
settings.decimation = 0;
if (fmt->fmt.pix.height <= zr->jpg_settings.img_height / 2)
settings.ver_dcm = 2;
else
settings.ver_dcm = 1;
if (fmt->fmt.pix.width <= zr->jpg_settings.img_width / 4)
settings.hor_dcm = 4;
else if (fmt->fmt.pix.width <= zr->jpg_settings.img_width / 2)
settings.hor_dcm = 2;
else
settings.hor_dcm = 1;
if (settings.tmp_dcm == 1)
settings.field_per_buff = 2;
else
settings.field_per_buff = 1;
if (settings.hor_dcm > 1) {
settings.img_x = (BUZ_MAX_WIDTH == 720) ? 8 : 0;
settings.img_width = (BUZ_MAX_WIDTH == 720) ? 704 : BUZ_MAX_WIDTH;
} else {
settings.img_x = 0;
settings.img_width = BUZ_MAX_WIDTH;
}
/* check */
res = zoran_check_jpg_settings(zr, &settings, 0);
if (res)
return res;
/* it's ok, so set them */
zr->jpg_settings = settings;
if (fmt->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
zr->map_mode = ZORAN_MAP_MODE_JPG_REC;
else
zr->map_mode = ZORAN_MAP_MODE_JPG_PLAY;
zr->buffer_size = zoran_v4l2_calc_bufsize(&zr->jpg_settings);
/* tell the user what we actually did */
fmt->fmt.pix.width = settings.img_width / settings.hor_dcm;
fmt->fmt.pix.height = settings.img_height * 2 /
(settings.tmp_dcm * settings.ver_dcm);
if (settings.tmp_dcm == 1)
fmt->fmt.pix.field = (zr->jpg_settings.odd_even ?
V4L2_FIELD_SEQ_TB : V4L2_FIELD_SEQ_BT);
else
fmt->fmt.pix.field = (zr->jpg_settings.odd_even ?
V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM);
fmt->fmt.pix.bytesperline = 0;
fmt->fmt.pix.sizeimage = zr->buffer_size;
fmt->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
return res;
}
static int zoran_s_fmt_vid_cap(struct file *file, void *__fh,
struct v4l2_format *fmt)
{
struct zoran *zr = video_drvdata(file);
struct zoran_fh *fh = __fh;
int i;
int res = 0;
if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_MJPEG)
return zoran_s_fmt_vid_out(file, fh, fmt);
for (i = 0; i < NUM_FORMATS; i++)
if (fmt->fmt.pix.pixelformat == zoran_formats[i].fourcc)
break;
if (i == NUM_FORMATS) {
pci_dbg(zr->pci_dev, "VIDIOC_S_FMT - unknown/unsupported format 0x%x\n",
fmt->fmt.pix.pixelformat);
/* TODO do not return here to fix the TRY_FMT cannot handle an invalid pixelformat*/
return -EINVAL;
}
fmt->fmt.pix.pixelformat = zoran_formats[i].fourcc;
if (fmt->fmt.pix.height > BUZ_MAX_HEIGHT)
fmt->fmt.pix.height = BUZ_MAX_HEIGHT;
if (fmt->fmt.pix.width > BUZ_MAX_WIDTH)
fmt->fmt.pix.width = BUZ_MAX_WIDTH;
if (fmt->fmt.pix.height < BUZ_MIN_HEIGHT)
fmt->fmt.pix.height = BUZ_MIN_HEIGHT;
if (fmt->fmt.pix.width < BUZ_MIN_WIDTH)
fmt->fmt.pix.width = BUZ_MIN_WIDTH;
zr->map_mode = ZORAN_MAP_MODE_RAW;
res = zoran_v4l_set_format(zr, fmt->fmt.pix.width, fmt->fmt.pix.height,
&zoran_formats[i]);
if (res)
return res;
/* tell the user the results/missing stuff */
fmt->fmt.pix.bytesperline = zr->v4l_settings.bytesperline;
fmt->fmt.pix.sizeimage = zr->buffer_size;
fmt->fmt.pix.colorspace = zr->v4l_settings.format->colorspace;
if (BUZ_MAX_HEIGHT < (zr->v4l_settings.height * 2))
fmt->fmt.pix.field = V4L2_FIELD_INTERLACED;
else
fmt->fmt.pix.field = V4L2_FIELD_TOP;
return res;
}
static int zoran_g_std(struct file *file, void *__fh, v4l2_std_id *std)
{
struct zoran *zr = video_drvdata(file);
*std = zr->norm;
return 0;
}
static int zoran_s_std(struct file *file, void *__fh, v4l2_std_id std)
{
struct zoran *zr = video_drvdata(file);
int res = 0;
if (zr->norm == std)
return 0;
if (zr->running != ZORAN_MAP_MODE_NONE)
return -EBUSY;
res = zoran_set_norm(zr, std);
return res;
}
static int zoran_enum_input(struct file *file, void *__fh,
struct v4l2_input *inp)
{
struct zoran *zr = video_drvdata(file);
if (inp->index >= zr->card.inputs)
return -EINVAL;
strscpy(inp->name, zr->card.input[inp->index].name, sizeof(inp->name));
inp->type = V4L2_INPUT_TYPE_CAMERA;
inp->std = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM;
/* Get status of video decoder */
decoder_call(zr, video, g_input_status, &inp->status);
return 0;
}
static int zoran_g_input(struct file *file, void *__fh, unsigned int *input)
{
struct zoran *zr = video_drvdata(file);
*input = zr->input;
return 0;
}
static int zoran_s_input(struct file *file, void *__fh, unsigned int input)
{
struct zoran *zr = video_drvdata(file);
int res;
if (zr->running != ZORAN_MAP_MODE_NONE)
return -EBUSY;
res = zoran_set_input(zr, input);
return res;
}
/* cropping (sub-frame capture) */
static int zoran_g_selection(struct file *file, void *__fh, struct v4l2_selection *sel)
{
struct zoran *zr = video_drvdata(file);
if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT &&
sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
pci_dbg(zr->pci_dev, "%s invalid selection type combination\n", __func__);
return -EINVAL;
}
switch (sel->target) {
case V4L2_SEL_TGT_CROP:
sel->r.top = zr->jpg_settings.img_y;
sel->r.left = zr->jpg_settings.img_x;
sel->r.width = zr->jpg_settings.img_width;
sel->r.height = zr->jpg_settings.img_height;
break;
case V4L2_SEL_TGT_CROP_DEFAULT:
sel->r.top = 0;
sel->r.left = 0;
sel->r.width = BUZ_MIN_WIDTH;
sel->r.height = BUZ_MIN_HEIGHT;
break;
case V4L2_SEL_TGT_CROP_BOUNDS:
sel->r.top = 0;
sel->r.left = 0;
sel->r.width = BUZ_MAX_WIDTH;
sel->r.height = BUZ_MAX_HEIGHT;
break;
default:
return -EINVAL;
}
return 0;
}
static int zoran_s_selection(struct file *file, void *__fh, struct v4l2_selection *sel)
{
struct zoran *zr = video_drvdata(file);
struct zoran_jpg_settings settings;
int res;
if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT &&
sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
if (!sel->r.width || !sel->r.height)
return -EINVAL;
if (sel->target != V4L2_SEL_TGT_CROP)
return -EINVAL;
if (zr->map_mode == ZORAN_MAP_MODE_RAW) {
pci_dbg(zr->pci_dev, "VIDIOC_S_SELECTION - subcapture only supported for compressed capture\n");
return -EINVAL;
}
settings = zr->jpg_settings;
/* move into a form that we understand */
settings.img_x = sel->r.left;
settings.img_y = sel->r.top;
settings.img_width = sel->r.width;
settings.img_height = sel->r.height;
/* check validity */
res = zoran_check_jpg_settings(zr, &settings, 0);
if (res)
return res;
/* accept */
zr->jpg_settings = settings;
return res;
}
/*
* Output is disabled temporarily
* Zoran is picky about jpeg data it accepts. At least it seems to unsupport COM and APPn.
* So until a way to filter data will be done, disable output.
*/
static const struct v4l2_ioctl_ops zoran_ioctl_ops = {
.vidioc_querycap = zoran_querycap,
.vidioc_s_selection = zoran_s_selection,
.vidioc_g_selection = zoran_g_selection,
.vidioc_enum_input = zoran_enum_input,
.vidioc_g_input = zoran_g_input,
.vidioc_s_input = zoran_s_input,
.vidioc_g_std = zoran_g_std,
.vidioc_s_std = zoran_s_std,
.vidioc_create_bufs = vb2_ioctl_create_bufs,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_expbuf = vb2_ioctl_expbuf,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_enum_fmt_vid_cap = zoran_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = zoran_g_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = zoran_s_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = zoran_try_fmt_vid_cap,
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
static const struct v4l2_file_operations zoran_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = video_ioctl2,
.open = v4l2_fh_open,
.release = vb2_fop_release,
.mmap = vb2_fop_mmap,
.poll = vb2_fop_poll,
};
const struct video_device zoran_template = {
.name = ZORAN_NAME,
.fops = &zoran_fops,
.ioctl_ops = &zoran_ioctl_ops,
.release = &zoran_vdev_release,
.tvnorms = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM,
};
static int zr_vb2_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, unsigned int *nplanes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct zoran *zr = vb2_get_drv_priv(vq);
unsigned int size = zr->buffer_size;
pci_dbg(zr->pci_dev, "%s nbuf=%u nplanes=%u", __func__, *nbuffers, *nplanes);
zr->buf_in_reserve = 0;
if (*nbuffers < vq->min_buffers_needed)
*nbuffers = vq->min_buffers_needed;
if (*nplanes) {
if (sizes[0] < size)
return -EINVAL;
else
return 0;
}
*nplanes = 1;
sizes[0] = size;
return 0;
}
static void zr_vb2_queue(struct vb2_buffer *vb)
{
struct zoran *zr = vb2_get_drv_priv(vb->vb2_queue);
struct zr_buffer *buf = vb2_to_zr_buffer(vb);
unsigned long flags;
spin_lock_irqsave(&zr->queued_bufs_lock, flags);
list_add_tail(&buf->queue, &zr->queued_bufs);
zr->buf_in_reserve++;
spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
if (zr->running == ZORAN_MAP_MODE_JPG_REC)
zoran_feed_stat_com(zr);
zr->queued++;
}
static int zr_vb2_prepare(struct vb2_buffer *vb)
{
struct zoran *zr = vb2_get_drv_priv(vb->vb2_queue);
if (vb2_plane_size(vb, 0) < zr->buffer_size)
return -EINVAL;
zr->prepared++;
return 0;
}
int zr_set_buf(struct zoran *zr)
{
struct zr_buffer *buf;
struct vb2_v4l2_buffer *vbuf;
dma_addr_t phys_addr;
unsigned long flags;
u32 reg;
if (zr->running == ZORAN_MAP_MODE_NONE)
return 0;
if (zr->inuse[0]) {
buf = zr->inuse[0];
buf->vbuf.vb2_buf.timestamp = ktime_get_ns();
buf->vbuf.sequence = zr->vbseq++;
vbuf = &buf->vbuf;
buf->vbuf.field = V4L2_FIELD_INTERLACED;
if (BUZ_MAX_HEIGHT < (zr->v4l_settings.height * 2))
buf->vbuf.field = V4L2_FIELD_INTERLACED;
else
buf->vbuf.field = V4L2_FIELD_TOP;
vb2_set_plane_payload(&buf->vbuf.vb2_buf, 0, zr->buffer_size);
vb2_buffer_done(&buf->vbuf.vb2_buf, VB2_BUF_STATE_DONE);
zr->inuse[0] = NULL;
}
spin_lock_irqsave(&zr->queued_bufs_lock, flags);
if (list_empty(&zr->queued_bufs)) {
btand(~ZR36057_ICR_INT_PIN_EN, ZR36057_ICR);
vb2_queue_error(zr->video_dev->queue);
spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
return -EINVAL;
}
buf = list_first_entry_or_null(&zr->queued_bufs, struct zr_buffer, queue);
if (!buf) {
btand(~ZR36057_ICR_INT_PIN_EN, ZR36057_ICR);
vb2_queue_error(zr->video_dev->queue);
spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
return -EINVAL;
}
list_del(&buf->queue);
zr->buf_in_reserve--;
spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
vbuf = &buf->vbuf;
vbuf->vb2_buf.state = VB2_BUF_STATE_ACTIVE;
phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
if (!phys_addr)
return -EINVAL;
zr->inuse[0] = buf;
reg = phys_addr;
btwrite(reg, ZR36057_VDTR);
if (zr->v4l_settings.height > BUZ_MAX_HEIGHT / 2)
reg += zr->v4l_settings.bytesperline;
btwrite(reg, ZR36057_VDBR);
reg = 0;
if (zr->v4l_settings.height > BUZ_MAX_HEIGHT / 2)
reg += zr->v4l_settings.bytesperline;
reg = (reg << ZR36057_VSSFGR_DISP_STRIDE);
reg |= ZR36057_VSSFGR_VID_OVF;
reg |= ZR36057_VSSFGR_SNAP_SHOT;
reg |= ZR36057_VSSFGR_FRAME_GRAB;
btwrite(reg, ZR36057_VSSFGR);
btor(ZR36057_VDCR_VID_EN, ZR36057_VDCR);
return 0;
}
static int zr_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
{
struct zoran *zr = vq->drv_priv;
int j;
for (j = 0; j < BUZ_NUM_STAT_COM; j++) {
zr->stat_com[j] = cpu_to_le32(1);
zr->inuse[j] = NULL;
}
zr->vbseq = 0;
if (zr->map_mode != ZORAN_MAP_MODE_RAW) {
pci_dbg(zr->pci_dev, "START JPG\n");
zr36057_restart(zr);
zoran_init_hardware(zr);
if (zr->map_mode == ZORAN_MAP_MODE_JPG_REC)
zr36057_enable_jpg(zr, BUZ_MODE_MOTION_DECOMPRESS);
else
zr36057_enable_jpg(zr, BUZ_MODE_MOTION_COMPRESS);
zoran_feed_stat_com(zr);
jpeg_start(zr);
zr->running = zr->map_mode;
btor(ZR36057_ICR_INT_PIN_EN, ZR36057_ICR);
return 0;
}
pci_dbg(zr->pci_dev, "START RAW\n");
zr36057_restart(zr);
zoran_init_hardware(zr);
zr36057_enable_jpg(zr, BUZ_MODE_IDLE);
zr36057_set_memgrab(zr, 1);
zr->running = zr->map_mode;
btor(ZR36057_ICR_INT_PIN_EN, ZR36057_ICR);
return 0;
}
static void zr_vb2_stop_streaming(struct vb2_queue *vq)
{
struct zoran *zr = vq->drv_priv;
struct zr_buffer *buf;
unsigned long flags;
int j;
btand(~ZR36057_ICR_INT_PIN_EN, ZR36057_ICR);
if (zr->map_mode != ZORAN_MAP_MODE_RAW)
zr36057_enable_jpg(zr, BUZ_MODE_IDLE);
zr36057_set_memgrab(zr, 0);
zr->running = ZORAN_MAP_MODE_NONE;
zoran_set_pci_master(zr, 0);
if (!pass_through) { /* Switch to color bar */
decoder_call(zr, video, s_stream, 0);
encoder_call(zr, video, s_routing, 2, 0, 0);
}
for (j = 0; j < BUZ_NUM_STAT_COM; j++) {
zr->stat_com[j] = cpu_to_le32(1);
if (!zr->inuse[j])
continue;
buf = zr->inuse[j];
pci_dbg(zr->pci_dev, "%s clean buf %d\n", __func__, j);
vb2_buffer_done(&buf->vbuf.vb2_buf, VB2_BUF_STATE_ERROR);
zr->inuse[j] = NULL;
}
spin_lock_irqsave(&zr->queued_bufs_lock, flags);
while (!list_empty(&zr->queued_bufs)) {
buf = list_entry(zr->queued_bufs.next, struct zr_buffer, queue);
list_del(&buf->queue);
vb2_buffer_done(&buf->vbuf.vb2_buf, VB2_BUF_STATE_ERROR);
zr->buf_in_reserve--;
}
spin_unlock_irqrestore(&zr->queued_bufs_lock, flags);
if (zr->buf_in_reserve)
pci_dbg(zr->pci_dev, "Buffer remaining %d\n", zr->buf_in_reserve);
zr->map_mode = ZORAN_MAP_MODE_RAW;
}
static const struct vb2_ops zr_video_qops = {
.queue_setup = zr_vb2_queue_setup,
.buf_queue = zr_vb2_queue,
.buf_prepare = zr_vb2_prepare,
.start_streaming = zr_vb2_start_streaming,
.stop_streaming = zr_vb2_stop_streaming,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
int zoran_queue_init(struct zoran *zr, struct vb2_queue *vq, int dir)
{
int err;
spin_lock_init(&zr->queued_bufs_lock);
INIT_LIST_HEAD(&zr->queued_bufs);
vq->dev = &zr->pci_dev->dev;
vq->type = dir;
vq->io_modes = VB2_DMABUF | VB2_MMAP;
vq->drv_priv = zr;
vq->buf_struct_size = sizeof(struct zr_buffer);
vq->ops = &zr_video_qops;
vq->mem_ops = &vb2_dma_contig_memops;
vq->gfp_flags = GFP_DMA32;
vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
vq->min_buffers_needed = 9;
vq->lock = &zr->lock;
err = vb2_queue_init(vq);
if (err)
return err;
zr->video_dev->queue = vq;
return 0;
}
void zoran_queue_exit(struct zoran *zr)
{
vb2_queue_release(zr->video_dev->queue);
}
| linux-master | drivers/media/pci/zoran/zoran_driver.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA interface to cobalt PCM capture streams
*
* Copyright 2014-2015 Cisco Systems, Inc. and/or its affiliates.
* All rights reserved.
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/spinlock.h>
#include <media/v4l2-device.h>
#include <sound/core.h>
#include <sound/initval.h>
#include "cobalt-driver.h"
#include "cobalt-alsa.h"
#include "cobalt-alsa-pcm.h"
static void snd_cobalt_card_free(struct snd_cobalt_card *cobsc)
{
if (cobsc == NULL)
return;
cobsc->s->alsa = NULL;
kfree(cobsc);
}
static void snd_cobalt_card_private_free(struct snd_card *sc)
{
if (sc == NULL)
return;
snd_cobalt_card_free(sc->private_data);
sc->private_data = NULL;
sc->private_free = NULL;
}
static int snd_cobalt_card_create(struct cobalt_stream *s,
struct snd_card *sc,
struct snd_cobalt_card **cobsc)
{
*cobsc = kzalloc(sizeof(struct snd_cobalt_card), GFP_KERNEL);
if (*cobsc == NULL)
return -ENOMEM;
(*cobsc)->s = s;
(*cobsc)->sc = sc;
sc->private_data = *cobsc;
sc->private_free = snd_cobalt_card_private_free;
return 0;
}
static int snd_cobalt_card_set_names(struct snd_cobalt_card *cobsc)
{
struct cobalt_stream *s = cobsc->s;
struct cobalt *cobalt = s->cobalt;
struct snd_card *sc = cobsc->sc;
/* sc->driver is used by alsa-lib's configurator: simple, unique */
strscpy(sc->driver, "cobalt", sizeof(sc->driver));
/* sc->shortname is a symlink in /proc/asound: COBALT-M -> cardN */
snprintf(sc->shortname, sizeof(sc->shortname), "cobalt-%d-%d",
cobalt->instance, s->video_channel);
/* sc->longname is read from /proc/asound/cards */
snprintf(sc->longname, sizeof(sc->longname),
"Cobalt %d HDMI %d",
cobalt->instance, s->video_channel);
return 0;
}
int cobalt_alsa_init(struct cobalt_stream *s)
{
struct cobalt *cobalt = s->cobalt;
struct snd_card *sc = NULL;
struct snd_cobalt_card *cobsc;
int ret;
/* Numbrs steps from "Writing an ALSA Driver" by Takashi Iwai */
/* (1) Check and increment the device index */
/* This is a no-op for us. We'll use the cobalt->instance */
/* (2) Create a card instance */
ret = snd_card_new(&cobalt->pci_dev->dev, SNDRV_DEFAULT_IDX1,
SNDRV_DEFAULT_STR1, THIS_MODULE, 0, &sc);
if (ret) {
cobalt_err("snd_card_new() failed with err %d\n", ret);
goto err_exit;
}
/* (3) Create a main component */
ret = snd_cobalt_card_create(s, sc, &cobsc);
if (ret) {
cobalt_err("snd_cobalt_card_create() failed with err %d\n",
ret);
goto err_exit_free;
}
/* (4) Set the driver ID and name strings */
snd_cobalt_card_set_names(cobsc);
ret = snd_cobalt_pcm_create(cobsc);
if (ret) {
cobalt_err("snd_cobalt_pcm_create() failed with err %d\n",
ret);
goto err_exit_free;
}
/* FIXME - proc files */
/* (7) Set the driver data and return 0 */
/* We do this out of normal order for PCI drivers to avoid races */
s->alsa = cobsc;
/* (6) Register the card instance */
ret = snd_card_register(sc);
if (ret) {
s->alsa = NULL;
cobalt_err("snd_card_register() failed with err %d\n", ret);
goto err_exit_free;
}
return 0;
err_exit_free:
if (sc != NULL)
snd_card_free(sc);
kfree(cobsc);
err_exit:
return ret;
}
void cobalt_alsa_exit(struct cobalt_stream *s)
{
struct snd_cobalt_card *cobsc = s->alsa;
if (cobsc)
snd_card_free(cobsc->sc);
s->alsa = NULL;
}
| linux-master | drivers/media/pci/cobalt/cobalt-alsa-main.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cobalt V4L2 API
*
* Derived from ivtv-ioctl.c and cx18-fileops.c
*
* Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
* All rights reserved.
*/
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/math64.h>
#include <linux/pci.h>
#include <linux/v4l2-dv-timings.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-event.h>
#include <media/v4l2-dv-timings.h>
#include <media/i2c/adv7604.h>
#include <media/i2c/adv7842.h>
#include "cobalt-alsa.h"
#include "cobalt-cpld.h"
#include "cobalt-driver.h"
#include "cobalt-v4l2.h"
#include "cobalt-irq.h"
#include "cobalt-omnitek.h"
static const struct v4l2_dv_timings cea1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
/* vb2 DMA streaming ops */
static int cobalt_queue_setup(struct vb2_queue *q,
unsigned int *num_buffers, unsigned int *num_planes,
unsigned int sizes[], struct device *alloc_devs[])
{
struct cobalt_stream *s = q->drv_priv;
unsigned size = s->stride * s->height;
if (*num_buffers < 3)
*num_buffers = 3;
if (*num_buffers > NR_BUFS)
*num_buffers = NR_BUFS;
if (*num_planes)
return sizes[0] < size ? -EINVAL : 0;
*num_planes = 1;
sizes[0] = size;
return 0;
}
static int cobalt_buf_init(struct vb2_buffer *vb)
{
struct cobalt_stream *s = vb->vb2_queue->drv_priv;
struct cobalt *cobalt = s->cobalt;
const size_t max_pages_per_line =
(COBALT_MAX_WIDTH * COBALT_MAX_BPP) / PAGE_SIZE + 2;
const size_t bytes =
COBALT_MAX_HEIGHT * max_pages_per_line * 0x20;
const size_t audio_bytes = ((1920 * 4) / PAGE_SIZE + 1) * 0x20;
struct sg_dma_desc_info *desc = &s->dma_desc_info[vb->index];
struct sg_table *sg_desc = vb2_dma_sg_plane_desc(vb, 0);
unsigned size;
int ret;
size = s->stride * s->height;
if (vb2_plane_size(vb, 0) < size) {
cobalt_info("data will not fit into plane (%lu < %u)\n",
vb2_plane_size(vb, 0), size);
return -EINVAL;
}
if (desc->virt == NULL) {
desc->dev = &cobalt->pci_dev->dev;
descriptor_list_allocate(desc,
s->is_audio ? audio_bytes : bytes);
if (desc->virt == NULL)
return -ENOMEM;
}
ret = descriptor_list_create(cobalt, sg_desc->sgl,
!s->is_output, sg_desc->nents, size,
s->width * s->bpp, s->stride, desc);
if (ret)
descriptor_list_free(desc);
return ret;
}
static void cobalt_buf_cleanup(struct vb2_buffer *vb)
{
struct cobalt_stream *s = vb->vb2_queue->drv_priv;
struct sg_dma_desc_info *desc = &s->dma_desc_info[vb->index];
descriptor_list_free(desc);
}
static int cobalt_buf_prepare(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct cobalt_stream *s = vb->vb2_queue->drv_priv;
vb2_set_plane_payload(vb, 0, s->stride * s->height);
vbuf->field = V4L2_FIELD_NONE;
return 0;
}
static void chain_all_buffers(struct cobalt_stream *s)
{
struct sg_dma_desc_info *desc[NR_BUFS];
struct cobalt_buffer *cb;
struct list_head *p;
int i = 0;
list_for_each(p, &s->bufs) {
cb = list_entry(p, struct cobalt_buffer, list);
desc[i] = &s->dma_desc_info[cb->vb.vb2_buf.index];
if (i > 0)
descriptor_list_chain(desc[i-1], desc[i]);
i++;
}
}
static void cobalt_buf_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct vb2_queue *q = vb->vb2_queue;
struct cobalt_stream *s = q->drv_priv;
struct cobalt_buffer *cb = to_cobalt_buffer(vbuf);
struct sg_dma_desc_info *desc = &s->dma_desc_info[vb->index];
unsigned long flags;
/* Prepare new buffer */
descriptor_list_loopback(desc);
descriptor_list_interrupt_disable(desc);
spin_lock_irqsave(&s->irqlock, flags);
list_add_tail(&cb->list, &s->bufs);
chain_all_buffers(s);
spin_unlock_irqrestore(&s->irqlock, flags);
}
static void cobalt_enable_output(struct cobalt_stream *s)
{
struct cobalt *cobalt = s->cobalt;
struct v4l2_bt_timings *bt = &s->timings.bt;
struct m00514_syncgen_flow_evcnt_regmap __iomem *vo =
COBALT_TX_BASE(cobalt);
unsigned fmt = s->pixfmt != V4L2_PIX_FMT_BGR32 ?
M00514_CONTROL_BITMAP_FORMAT_16_BPP_MSK : 0;
struct v4l2_subdev_format sd_fmt = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
u64 clk = bt->pixelclock;
if (bt->flags & V4L2_DV_FL_REDUCED_FPS)
clk = div_u64(clk * 1000ULL, 1001);
if (!cobalt_cpld_set_freq(cobalt, clk)) {
cobalt_err("pixelclock out of range\n");
return;
}
sd_fmt.format.colorspace = s->colorspace;
sd_fmt.format.xfer_func = s->xfer_func;
sd_fmt.format.ycbcr_enc = s->ycbcr_enc;
sd_fmt.format.quantization = s->quantization;
sd_fmt.format.width = bt->width;
sd_fmt.format.height = bt->height;
/* Set up FDMA packer */
switch (s->pixfmt) {
case V4L2_PIX_FMT_YUYV:
sd_fmt.format.code = MEDIA_BUS_FMT_UYVY8_1X16;
break;
case V4L2_PIX_FMT_BGR32:
sd_fmt.format.code = MEDIA_BUS_FMT_RGB888_1X24;
break;
}
v4l2_subdev_call(s->sd, pad, set_fmt, NULL, &sd_fmt);
iowrite32(0, &vo->control);
/* 1080p60 */
iowrite32(bt->hsync, &vo->sync_generator_h_sync_length);
iowrite32(bt->hbackporch, &vo->sync_generator_h_backporch_length);
iowrite32(bt->width, &vo->sync_generator_h_active_length);
iowrite32(bt->hfrontporch, &vo->sync_generator_h_frontporch_length);
iowrite32(bt->vsync, &vo->sync_generator_v_sync_length);
iowrite32(bt->vbackporch, &vo->sync_generator_v_backporch_length);
iowrite32(bt->height, &vo->sync_generator_v_active_length);
iowrite32(bt->vfrontporch, &vo->sync_generator_v_frontporch_length);
iowrite32(0x9900c1, &vo->error_color);
iowrite32(M00514_CONTROL_BITMAP_SYNC_GENERATOR_LOAD_PARAM_MSK | fmt,
&vo->control);
iowrite32(M00514_CONTROL_BITMAP_EVCNT_CLEAR_MSK | fmt, &vo->control);
iowrite32(M00514_CONTROL_BITMAP_SYNC_GENERATOR_ENABLE_MSK |
M00514_CONTROL_BITMAP_FLOW_CTRL_OUTPUT_ENABLE_MSK |
fmt, &vo->control);
}
static void cobalt_enable_input(struct cobalt_stream *s)
{
struct cobalt *cobalt = s->cobalt;
int ch = (int)s->video_channel;
struct m00235_fdma_packer_regmap __iomem *packer;
struct v4l2_subdev_format sd_fmt_yuyv = {
.pad = s->pad_source,
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
.format.code = MEDIA_BUS_FMT_YUYV8_1X16,
};
struct v4l2_subdev_format sd_fmt_rgb = {
.pad = s->pad_source,
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
.format.code = MEDIA_BUS_FMT_RGB888_1X24,
};
cobalt_dbg(1, "video_channel %d (%s, %s)\n",
s->video_channel,
s->input == 0 ? "hdmi" : "generator",
"YUYV");
packer = COBALT_CVI_PACKER(cobalt, ch);
/* Set up FDMA packer */
switch (s->pixfmt) {
case V4L2_PIX_FMT_YUYV:
iowrite32(M00235_CONTROL_BITMAP_ENABLE_MSK |
(1 << M00235_CONTROL_BITMAP_PACK_FORMAT_OFST),
&packer->control);
v4l2_subdev_call(s->sd, pad, set_fmt, NULL,
&sd_fmt_yuyv);
break;
case V4L2_PIX_FMT_RGB24:
iowrite32(M00235_CONTROL_BITMAP_ENABLE_MSK |
(2 << M00235_CONTROL_BITMAP_PACK_FORMAT_OFST),
&packer->control);
v4l2_subdev_call(s->sd, pad, set_fmt, NULL,
&sd_fmt_rgb);
break;
case V4L2_PIX_FMT_BGR32:
iowrite32(M00235_CONTROL_BITMAP_ENABLE_MSK |
M00235_CONTROL_BITMAP_ENDIAN_FORMAT_MSK |
(3 << M00235_CONTROL_BITMAP_PACK_FORMAT_OFST),
&packer->control);
v4l2_subdev_call(s->sd, pad, set_fmt, NULL,
&sd_fmt_rgb);
break;
}
}
static void cobalt_dma_start_streaming(struct cobalt_stream *s)
{
struct cobalt *cobalt = s->cobalt;
int rx = s->video_channel;
struct m00460_evcnt_regmap __iomem *evcnt =
COBALT_CVI_EVCNT(cobalt, rx);
struct cobalt_buffer *cb;
unsigned long flags;
spin_lock_irqsave(&s->irqlock, flags);
if (!s->is_output) {
iowrite32(M00460_CONTROL_BITMAP_CLEAR_MSK, &evcnt->control);
iowrite32(M00460_CONTROL_BITMAP_ENABLE_MSK, &evcnt->control);
} else {
struct m00514_syncgen_flow_evcnt_regmap __iomem *vo =
COBALT_TX_BASE(cobalt);
u32 ctrl = ioread32(&vo->control);
ctrl &= ~(M00514_CONTROL_BITMAP_EVCNT_ENABLE_MSK |
M00514_CONTROL_BITMAP_EVCNT_CLEAR_MSK);
iowrite32(ctrl | M00514_CONTROL_BITMAP_EVCNT_CLEAR_MSK,
&vo->control);
iowrite32(ctrl | M00514_CONTROL_BITMAP_EVCNT_ENABLE_MSK,
&vo->control);
}
cb = list_first_entry(&s->bufs, struct cobalt_buffer, list);
omni_sg_dma_start(s, &s->dma_desc_info[cb->vb.vb2_buf.index]);
spin_unlock_irqrestore(&s->irqlock, flags);
}
static int cobalt_start_streaming(struct vb2_queue *q, unsigned int count)
{
struct cobalt_stream *s = q->drv_priv;
struct cobalt *cobalt = s->cobalt;
struct m00233_video_measure_regmap __iomem *vmr;
struct m00473_freewheel_regmap __iomem *fw;
struct m00479_clk_loss_detector_regmap __iomem *clkloss;
int rx = s->video_channel;
struct m00389_cvi_regmap __iomem *cvi = COBALT_CVI(cobalt, rx);
struct m00460_evcnt_regmap __iomem *evcnt = COBALT_CVI_EVCNT(cobalt, rx);
struct v4l2_bt_timings *bt = &s->timings.bt;
u64 tot_size;
u32 clk_freq;
if (s->is_audio)
goto done;
if (s->is_output) {
s->unstable_frame = false;
cobalt_enable_output(s);
goto done;
}
cobalt_enable_input(s);
fw = COBALT_CVI_FREEWHEEL(cobalt, rx);
vmr = COBALT_CVI_VMR(cobalt, rx);
clkloss = COBALT_CVI_CLK_LOSS(cobalt, rx);
iowrite32(M00460_CONTROL_BITMAP_CLEAR_MSK, &evcnt->control);
iowrite32(M00460_CONTROL_BITMAP_ENABLE_MSK, &evcnt->control);
iowrite32(bt->width, &cvi->frame_width);
iowrite32(bt->height, &cvi->frame_height);
tot_size = V4L2_DV_BT_FRAME_WIDTH(bt) * V4L2_DV_BT_FRAME_HEIGHT(bt);
iowrite32(div_u64((u64)V4L2_DV_BT_FRAME_WIDTH(bt) * COBALT_CLK * 4,
bt->pixelclock), &vmr->hsync_timeout_val);
iowrite32(M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK, &vmr->control);
clk_freq = ioread32(&fw->clk_freq);
iowrite32(clk_freq / 1000000, &clkloss->ref_clk_cnt_val);
/* The lower bound for the clock frequency is 0.5% lower as is
* allowed by the spec */
iowrite32(div_u64(bt->pixelclock * 995, 1000000000),
&clkloss->test_clk_cnt_val);
/* will be enabled after the first frame has been received */
iowrite32(bt->width * bt->height, &fw->active_length);
iowrite32(div_u64((u64)clk_freq * tot_size, bt->pixelclock),
&fw->total_length);
iowrite32(M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_MSK |
M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_MSK,
&vmr->irq_triggers);
iowrite32(0, &cvi->control);
iowrite32(M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK, &vmr->control);
iowrite32(0xff, &fw->output_color);
iowrite32(M00479_CTRL_BITMAP_ENABLE_MSK, &clkloss->ctrl);
iowrite32(M00473_CTRL_BITMAP_ENABLE_MSK |
M00473_CTRL_BITMAP_FORCE_FREEWHEEL_MODE_MSK, &fw->ctrl);
s->unstable_frame = true;
s->enable_freewheel = false;
s->enable_cvi = false;
s->skip_first_frames = 0;
done:
s->sequence = 0;
cobalt_dma_start_streaming(s);
return 0;
}
static void cobalt_dma_stop_streaming(struct cobalt_stream *s)
{
struct cobalt *cobalt = s->cobalt;
struct sg_dma_desc_info *desc;
struct cobalt_buffer *cb;
struct list_head *p;
unsigned long flags;
int timeout_msec = 100;
int rx = s->video_channel;
struct m00460_evcnt_regmap __iomem *evcnt =
COBALT_CVI_EVCNT(cobalt, rx);
if (!s->is_output) {
iowrite32(0, &evcnt->control);
} else if (!s->is_audio) {
struct m00514_syncgen_flow_evcnt_regmap __iomem *vo =
COBALT_TX_BASE(cobalt);
iowrite32(M00514_CONTROL_BITMAP_EVCNT_CLEAR_MSK, &vo->control);
iowrite32(0, &vo->control);
}
/* Try to stop the DMA engine gracefully */
spin_lock_irqsave(&s->irqlock, flags);
list_for_each(p, &s->bufs) {
cb = list_entry(p, struct cobalt_buffer, list);
desc = &s->dma_desc_info[cb->vb.vb2_buf.index];
/* Stop DMA after this descriptor chain */
descriptor_list_end_of_chain(desc);
}
spin_unlock_irqrestore(&s->irqlock, flags);
/* Wait 100 millisecond for DMA to finish, abort on timeout. */
if (!wait_event_timeout(s->q.done_wq, is_dma_done(s),
msecs_to_jiffies(timeout_msec))) {
omni_sg_dma_abort_channel(s);
pr_warn("aborted\n");
}
cobalt_write_bar0(cobalt, DMA_INTERRUPT_STATUS_REG,
1 << s->dma_channel);
}
static void cobalt_stop_streaming(struct vb2_queue *q)
{
struct cobalt_stream *s = q->drv_priv;
struct cobalt *cobalt = s->cobalt;
int rx = s->video_channel;
struct m00233_video_measure_regmap __iomem *vmr;
struct m00473_freewheel_regmap __iomem *fw;
struct m00479_clk_loss_detector_regmap __iomem *clkloss;
struct cobalt_buffer *cb;
struct list_head *p, *safe;
unsigned long flags;
cobalt_dma_stop_streaming(s);
/* Return all buffers to user space */
spin_lock_irqsave(&s->irqlock, flags);
list_for_each_safe(p, safe, &s->bufs) {
cb = list_entry(p, struct cobalt_buffer, list);
list_del(&cb->list);
vb2_buffer_done(&cb->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&s->irqlock, flags);
if (s->is_audio || s->is_output)
return;
fw = COBALT_CVI_FREEWHEEL(cobalt, rx);
vmr = COBALT_CVI_VMR(cobalt, rx);
clkloss = COBALT_CVI_CLK_LOSS(cobalt, rx);
iowrite32(0, &vmr->control);
iowrite32(M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK, &vmr->control);
iowrite32(0, &fw->ctrl);
iowrite32(0, &clkloss->ctrl);
}
static const struct vb2_ops cobalt_qops = {
.queue_setup = cobalt_queue_setup,
.buf_init = cobalt_buf_init,
.buf_cleanup = cobalt_buf_cleanup,
.buf_prepare = cobalt_buf_prepare,
.buf_queue = cobalt_buf_queue,
.start_streaming = cobalt_start_streaming,
.stop_streaming = cobalt_stop_streaming,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
/* V4L2 ioctls */
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int cobalt_cobaltc(struct cobalt *cobalt, unsigned int cmd, void *arg)
{
struct v4l2_dbg_register *regs = arg;
void __iomem *adrs = cobalt->bar1 + regs->reg;
cobalt_info("cobalt_cobaltc: adrs = %p\n", adrs);
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
regs->size = 4;
if (cmd == VIDIOC_DBG_S_REGISTER)
iowrite32(regs->val, adrs);
else
regs->val = ioread32(adrs);
return 0;
}
static int cobalt_g_register(struct file *file, void *priv_fh,
struct v4l2_dbg_register *reg)
{
struct cobalt_stream *s = video_drvdata(file);
struct cobalt *cobalt = s->cobalt;
return cobalt_cobaltc(cobalt, VIDIOC_DBG_G_REGISTER, reg);
}
static int cobalt_s_register(struct file *file, void *priv_fh,
const struct v4l2_dbg_register *reg)
{
struct cobalt_stream *s = video_drvdata(file);
struct cobalt *cobalt = s->cobalt;
return cobalt_cobaltc(cobalt, VIDIOC_DBG_S_REGISTER,
(struct v4l2_dbg_register *)reg);
}
#endif
static int cobalt_querycap(struct file *file, void *priv_fh,
struct v4l2_capability *vcap)
{
struct cobalt_stream *s = video_drvdata(file);
struct cobalt *cobalt = s->cobalt;
strscpy(vcap->driver, "cobalt", sizeof(vcap->driver));
strscpy(vcap->card, "cobalt", sizeof(vcap->card));
snprintf(vcap->bus_info, sizeof(vcap->bus_info),
"PCIe:%s", pci_name(cobalt->pci_dev));
vcap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_READWRITE |
V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_DEVICE_CAPS;
if (cobalt->have_hsma_tx)
vcap->capabilities |= V4L2_CAP_VIDEO_OUTPUT;
return 0;
}
static void cobalt_video_input_status_show(struct cobalt_stream *s)
{
struct m00389_cvi_regmap __iomem *cvi;
struct m00233_video_measure_regmap __iomem *vmr;
struct m00473_freewheel_regmap __iomem *fw;
struct m00479_clk_loss_detector_regmap __iomem *clkloss;
struct m00235_fdma_packer_regmap __iomem *packer;
int rx = s->video_channel;
struct cobalt *cobalt = s->cobalt;
u32 cvi_ctrl, cvi_stat;
u32 vmr_ctrl, vmr_stat;
cvi = COBALT_CVI(cobalt, rx);
vmr = COBALT_CVI_VMR(cobalt, rx);
fw = COBALT_CVI_FREEWHEEL(cobalt, rx);
clkloss = COBALT_CVI_CLK_LOSS(cobalt, rx);
packer = COBALT_CVI_PACKER(cobalt, rx);
cvi_ctrl = ioread32(&cvi->control);
cvi_stat = ioread32(&cvi->status);
vmr_ctrl = ioread32(&vmr->control);
vmr_stat = ioread32(&vmr->status);
cobalt_info("rx%d: cvi resolution: %dx%d\n", rx,
ioread32(&cvi->frame_width), ioread32(&cvi->frame_height));
cobalt_info("rx%d: cvi control: %s%s%s\n", rx,
(cvi_ctrl & M00389_CONTROL_BITMAP_ENABLE_MSK) ?
"enable " : "disable ",
(cvi_ctrl & M00389_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK) ?
"HSync- " : "HSync+ ",
(cvi_ctrl & M00389_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK) ?
"VSync- " : "VSync+ ");
cobalt_info("rx%d: cvi status: %s%s\n", rx,
(cvi_stat & M00389_STATUS_BITMAP_LOCK_MSK) ?
"lock " : "no-lock ",
(cvi_stat & M00389_STATUS_BITMAP_ERROR_MSK) ?
"error " : "no-error ");
cobalt_info("rx%d: Measurements: %s%s%s%s%s%s%s\n", rx,
(vmr_ctrl & M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK) ?
"HSync- " : "HSync+ ",
(vmr_ctrl & M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK) ?
"VSync- " : "VSync+ ",
(vmr_ctrl & M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK) ?
"enabled " : "disabled ",
(vmr_ctrl & M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_MSK) ?
"irq-enabled " : "irq-disabled ",
(vmr_ctrl & M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_MSK) ?
"update-on-hsync " : "",
(vmr_stat & M00233_STATUS_BITMAP_HSYNC_TIMEOUT_MSK) ?
"hsync-timeout " : "",
(vmr_stat & M00233_STATUS_BITMAP_INIT_DONE_MSK) ?
"init-done" : "");
cobalt_info("rx%d: irq_status: 0x%02x irq_triggers: 0x%02x\n", rx,
ioread32(&vmr->irq_status) & 0xff,
ioread32(&vmr->irq_triggers) & 0xff);
cobalt_info("rx%d: vsync: %d\n", rx, ioread32(&vmr->vsync_time));
cobalt_info("rx%d: vbp: %d\n", rx, ioread32(&vmr->vback_porch));
cobalt_info("rx%d: vact: %d\n", rx, ioread32(&vmr->vactive_area));
cobalt_info("rx%d: vfb: %d\n", rx, ioread32(&vmr->vfront_porch));
cobalt_info("rx%d: hsync: %d\n", rx, ioread32(&vmr->hsync_time));
cobalt_info("rx%d: hbp: %d\n", rx, ioread32(&vmr->hback_porch));
cobalt_info("rx%d: hact: %d\n", rx, ioread32(&vmr->hactive_area));
cobalt_info("rx%d: hfb: %d\n", rx, ioread32(&vmr->hfront_porch));
cobalt_info("rx%d: Freewheeling: %s%s%s\n", rx,
(ioread32(&fw->ctrl) & M00473_CTRL_BITMAP_ENABLE_MSK) ?
"enabled " : "disabled ",
(ioread32(&fw->ctrl) & M00473_CTRL_BITMAP_FORCE_FREEWHEEL_MODE_MSK) ?
"forced " : "",
(ioread32(&fw->status) & M00473_STATUS_BITMAP_FREEWHEEL_MODE_MSK) ?
"freewheeling " : "video-passthrough ");
iowrite32(0xff, &vmr->irq_status);
cobalt_info("rx%d: Clock Loss Detection: %s%s\n", rx,
(ioread32(&clkloss->ctrl) & M00479_CTRL_BITMAP_ENABLE_MSK) ?
"enabled " : "disabled ",
(ioread32(&clkloss->status) & M00479_STATUS_BITMAP_CLOCK_MISSING_MSK) ?
"clock-missing " : "found-clock ");
cobalt_info("rx%d: Packer: %x\n", rx, ioread32(&packer->control));
}
static int cobalt_log_status(struct file *file, void *priv_fh)
{
struct cobalt_stream *s = video_drvdata(file);
struct cobalt *cobalt = s->cobalt;
struct m00514_syncgen_flow_evcnt_regmap __iomem *vo =
COBALT_TX_BASE(cobalt);
u8 stat;
cobalt_info("%s", cobalt->hdl_info);
cobalt_info("sysctrl: %08x, sysstat: %08x\n",
cobalt_g_sysctrl(cobalt),
cobalt_g_sysstat(cobalt));
cobalt_info("dma channel: %d, video channel: %d\n",
s->dma_channel, s->video_channel);
cobalt_pcie_status_show(cobalt);
cobalt_cpld_status(cobalt);
cobalt_irq_log_status(cobalt);
v4l2_subdev_call(s->sd, core, log_status);
if (!s->is_output) {
cobalt_video_input_status_show(s);
return 0;
}
stat = ioread32(&vo->rd_status);
cobalt_info("tx: status: %s%s\n",
(stat & M00514_RD_STATUS_BITMAP_FLOW_CTRL_NO_DATA_ERROR_MSK) ?
"no_data " : "",
(stat & M00514_RD_STATUS_BITMAP_READY_BUFFER_FULL_MSK) ?
"ready_buffer_full " : "");
cobalt_info("tx: evcnt: %d\n", ioread32(&vo->rd_evcnt_count));
return 0;
}
static int cobalt_enum_dv_timings(struct file *file, void *priv_fh,
struct v4l2_enum_dv_timings *timings)
{
struct cobalt_stream *s = video_drvdata(file);
if (s->input == 1) {
if (timings->index)
return -EINVAL;
memset(timings->reserved, 0, sizeof(timings->reserved));
timings->timings = cea1080p60;
return 0;
}
timings->pad = 0;
return v4l2_subdev_call(s->sd,
pad, enum_dv_timings, timings);
}
static int cobalt_s_dv_timings(struct file *file, void *priv_fh,
struct v4l2_dv_timings *timings)
{
struct cobalt_stream *s = video_drvdata(file);
int err;
if (s->input == 1) {
*timings = cea1080p60;
return 0;
}
if (v4l2_match_dv_timings(timings, &s->timings, 0, true))
return 0;
if (vb2_is_busy(&s->q))
return -EBUSY;
err = v4l2_subdev_call(s->sd,
video, s_dv_timings, timings);
if (!err) {
s->timings = *timings;
s->width = timings->bt.width;
s->height = timings->bt.height;
s->stride = timings->bt.width * s->bpp;
}
return err;
}
static int cobalt_g_dv_timings(struct file *file, void *priv_fh,
struct v4l2_dv_timings *timings)
{
struct cobalt_stream *s = video_drvdata(file);
if (s->input == 1) {
*timings = cea1080p60;
return 0;
}
return v4l2_subdev_call(s->sd,
video, g_dv_timings, timings);
}
static int cobalt_query_dv_timings(struct file *file, void *priv_fh,
struct v4l2_dv_timings *timings)
{
struct cobalt_stream *s = video_drvdata(file);
if (s->input == 1) {
*timings = cea1080p60;
return 0;
}
return v4l2_subdev_call(s->sd,
video, query_dv_timings, timings);
}
static int cobalt_dv_timings_cap(struct file *file, void *priv_fh,
struct v4l2_dv_timings_cap *cap)
{
struct cobalt_stream *s = video_drvdata(file);
cap->pad = 0;
return v4l2_subdev_call(s->sd,
pad, dv_timings_cap, cap);
}
static int cobalt_enum_fmt_vid_cap(struct file *file, void *priv_fh,
struct v4l2_fmtdesc *f)
{
switch (f->index) {
case 0:
f->pixelformat = V4L2_PIX_FMT_YUYV;
break;
case 1:
f->pixelformat = V4L2_PIX_FMT_RGB24;
break;
case 2:
f->pixelformat = V4L2_PIX_FMT_BGR32;
break;
default:
return -EINVAL;
}
return 0;
}
static int cobalt_g_fmt_vid_cap(struct file *file, void *priv_fh,
struct v4l2_format *f)
{
struct cobalt_stream *s = video_drvdata(file);
struct v4l2_pix_format *pix = &f->fmt.pix;
pix->width = s->width;
pix->height = s->height;
pix->bytesperline = s->stride;
pix->field = V4L2_FIELD_NONE;
if (s->input == 1) {
pix->colorspace = V4L2_COLORSPACE_SRGB;
} else {
struct v4l2_subdev_format sd_fmt = {
.pad = s->pad_source,
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
v4l2_subdev_call(s->sd, pad, get_fmt, NULL, &sd_fmt);
v4l2_fill_pix_format(pix, &sd_fmt.format);
}
pix->pixelformat = s->pixfmt;
pix->sizeimage = pix->bytesperline * pix->height;
return 0;
}
static int cobalt_try_fmt_vid_cap(struct file *file, void *priv_fh,
struct v4l2_format *f)
{
struct cobalt_stream *s = video_drvdata(file);
struct v4l2_pix_format *pix = &f->fmt.pix;
/* Check for min (QCIF) and max (Full HD) size */
if ((pix->width < 176) || (pix->height < 144)) {
pix->width = 176;
pix->height = 144;
}
if ((pix->width > 1920) || (pix->height > 1080)) {
pix->width = 1920;
pix->height = 1080;
}
/* Make width multiple of 4 */
pix->width &= ~0x3;
/* Make height multiple of 2 */
pix->height &= ~0x1;
if (s->input == 1) {
/* Generator => fixed format only */
pix->width = 1920;
pix->height = 1080;
pix->colorspace = V4L2_COLORSPACE_SRGB;
} else {
struct v4l2_subdev_format sd_fmt = {
.pad = s->pad_source,
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
v4l2_subdev_call(s->sd, pad, get_fmt, NULL, &sd_fmt);
v4l2_fill_pix_format(pix, &sd_fmt.format);
}
switch (pix->pixelformat) {
case V4L2_PIX_FMT_YUYV:
default:
pix->bytesperline = max(pix->bytesperline & ~0x3,
pix->width * COBALT_BYTES_PER_PIXEL_YUYV);
pix->pixelformat = V4L2_PIX_FMT_YUYV;
break;
case V4L2_PIX_FMT_RGB24:
pix->bytesperline = max(pix->bytesperline & ~0x3,
pix->width * COBALT_BYTES_PER_PIXEL_RGB24);
break;
case V4L2_PIX_FMT_BGR32:
pix->bytesperline = max(pix->bytesperline & ~0x3,
pix->width * COBALT_BYTES_PER_PIXEL_RGB32);
break;
}
pix->sizeimage = pix->bytesperline * pix->height;
pix->field = V4L2_FIELD_NONE;
return 0;
}
static int cobalt_s_fmt_vid_cap(struct file *file, void *priv_fh,
struct v4l2_format *f)
{
struct cobalt_stream *s = video_drvdata(file);
struct v4l2_pix_format *pix = &f->fmt.pix;
if (vb2_is_busy(&s->q))
return -EBUSY;
if (cobalt_try_fmt_vid_cap(file, priv_fh, f))
return -EINVAL;
s->width = pix->width;
s->height = pix->height;
s->stride = pix->bytesperline;
switch (pix->pixelformat) {
case V4L2_PIX_FMT_YUYV:
s->bpp = COBALT_BYTES_PER_PIXEL_YUYV;
break;
case V4L2_PIX_FMT_RGB24:
s->bpp = COBALT_BYTES_PER_PIXEL_RGB24;
break;
case V4L2_PIX_FMT_BGR32:
s->bpp = COBALT_BYTES_PER_PIXEL_RGB32;
break;
default:
return -EINVAL;
}
s->pixfmt = pix->pixelformat;
cobalt_enable_input(s);
return 0;
}
static int cobalt_try_fmt_vid_out(struct file *file, void *priv_fh,
struct v4l2_format *f)
{
struct v4l2_pix_format *pix = &f->fmt.pix;
/* Check for min (QCIF) and max (Full HD) size */
if ((pix->width < 176) || (pix->height < 144)) {
pix->width = 176;
pix->height = 144;
}
if ((pix->width > 1920) || (pix->height > 1080)) {
pix->width = 1920;
pix->height = 1080;
}
/* Make width multiple of 4 */
pix->width &= ~0x3;
/* Make height multiple of 2 */
pix->height &= ~0x1;
switch (pix->pixelformat) {
case V4L2_PIX_FMT_YUYV:
default:
pix->bytesperline = max(pix->bytesperline & ~0x3,
pix->width * COBALT_BYTES_PER_PIXEL_YUYV);
pix->pixelformat = V4L2_PIX_FMT_YUYV;
break;
case V4L2_PIX_FMT_BGR32:
pix->bytesperline = max(pix->bytesperline & ~0x3,
pix->width * COBALT_BYTES_PER_PIXEL_RGB32);
break;
}
pix->sizeimage = pix->bytesperline * pix->height;
pix->field = V4L2_FIELD_NONE;
return 0;
}
static int cobalt_g_fmt_vid_out(struct file *file, void *priv_fh,
struct v4l2_format *f)
{
struct cobalt_stream *s = video_drvdata(file);
struct v4l2_pix_format *pix = &f->fmt.pix;
pix->width = s->width;
pix->height = s->height;
pix->bytesperline = s->stride;
pix->field = V4L2_FIELD_NONE;
pix->pixelformat = s->pixfmt;
pix->colorspace = s->colorspace;
pix->xfer_func = s->xfer_func;
pix->ycbcr_enc = s->ycbcr_enc;
pix->quantization = s->quantization;
pix->sizeimage = pix->bytesperline * pix->height;
return 0;
}
static int cobalt_enum_fmt_vid_out(struct file *file, void *priv_fh,
struct v4l2_fmtdesc *f)
{
switch (f->index) {
case 0:
f->pixelformat = V4L2_PIX_FMT_YUYV;
break;
case 1:
f->pixelformat = V4L2_PIX_FMT_BGR32;
break;
default:
return -EINVAL;
}
return 0;
}
static int cobalt_s_fmt_vid_out(struct file *file, void *priv_fh,
struct v4l2_format *f)
{
struct cobalt_stream *s = video_drvdata(file);
struct v4l2_pix_format *pix = &f->fmt.pix;
struct v4l2_subdev_format sd_fmt = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
u32 code;
if (cobalt_try_fmt_vid_out(file, priv_fh, f))
return -EINVAL;
if (vb2_is_busy(&s->q) && (pix->pixelformat != s->pixfmt ||
pix->width != s->width || pix->height != s->height ||
pix->bytesperline != s->stride))
return -EBUSY;
switch (pix->pixelformat) {
case V4L2_PIX_FMT_YUYV:
s->bpp = COBALT_BYTES_PER_PIXEL_YUYV;
code = MEDIA_BUS_FMT_UYVY8_1X16;
break;
case V4L2_PIX_FMT_BGR32:
s->bpp = COBALT_BYTES_PER_PIXEL_RGB32;
code = MEDIA_BUS_FMT_RGB888_1X24;
break;
default:
return -EINVAL;
}
s->width = pix->width;
s->height = pix->height;
s->stride = pix->bytesperline;
s->pixfmt = pix->pixelformat;
s->colorspace = pix->colorspace;
s->xfer_func = pix->xfer_func;
s->ycbcr_enc = pix->ycbcr_enc;
s->quantization = pix->quantization;
v4l2_fill_mbus_format(&sd_fmt.format, pix, code);
v4l2_subdev_call(s->sd, pad, set_fmt, NULL, &sd_fmt);
return 0;
}
static int cobalt_enum_input(struct file *file, void *priv_fh,
struct v4l2_input *inp)
{
struct cobalt_stream *s = video_drvdata(file);
if (inp->index > 1)
return -EINVAL;
if (inp->index == 0)
snprintf(inp->name, sizeof(inp->name),
"HDMI-%d", s->video_channel);
else
snprintf(inp->name, sizeof(inp->name),
"Generator-%d", s->video_channel);
inp->type = V4L2_INPUT_TYPE_CAMERA;
inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
if (inp->index == 1)
return 0;
return v4l2_subdev_call(s->sd,
video, g_input_status, &inp->status);
}
static int cobalt_g_input(struct file *file, void *priv_fh, unsigned int *i)
{
struct cobalt_stream *s = video_drvdata(file);
*i = s->input;
return 0;
}
static int cobalt_s_input(struct file *file, void *priv_fh, unsigned int i)
{
struct cobalt_stream *s = video_drvdata(file);
if (i >= 2)
return -EINVAL;
if (vb2_is_busy(&s->q))
return -EBUSY;
s->input = i;
cobalt_enable_input(s);
if (s->input == 1) /* Test Pattern Generator */
return 0;
return v4l2_subdev_call(s->sd, video, s_routing,
ADV76XX_PAD_HDMI_PORT_A, 0, 0);
}
static int cobalt_enum_output(struct file *file, void *priv_fh,
struct v4l2_output *out)
{
if (out->index)
return -EINVAL;
snprintf(out->name, sizeof(out->name), "HDMI-%d", out->index);
out->type = V4L2_OUTPUT_TYPE_ANALOG;
out->capabilities = V4L2_OUT_CAP_DV_TIMINGS;
return 0;
}
static int cobalt_g_output(struct file *file, void *priv_fh, unsigned int *i)
{
*i = 0;
return 0;
}
static int cobalt_s_output(struct file *file, void *priv_fh, unsigned int i)
{
return i ? -EINVAL : 0;
}
static int cobalt_g_edid(struct file *file, void *fh, struct v4l2_edid *edid)
{
struct cobalt_stream *s = video_drvdata(file);
u32 pad = edid->pad;
int ret;
if (edid->pad >= (s->is_output ? 1 : 2))
return -EINVAL;
edid->pad = 0;
ret = v4l2_subdev_call(s->sd, pad, get_edid, edid);
edid->pad = pad;
return ret;
}
static int cobalt_s_edid(struct file *file, void *fh, struct v4l2_edid *edid)
{
struct cobalt_stream *s = video_drvdata(file);
u32 pad = edid->pad;
int ret;
if (edid->pad >= 2)
return -EINVAL;
edid->pad = 0;
ret = v4l2_subdev_call(s->sd, pad, set_edid, edid);
edid->pad = pad;
return ret;
}
static int cobalt_subscribe_event(struct v4l2_fh *fh,
const struct v4l2_event_subscription *sub)
{
switch (sub->type) {
case V4L2_EVENT_SOURCE_CHANGE:
return v4l2_event_subscribe(fh, sub, 4, NULL);
}
return v4l2_ctrl_subscribe_event(fh, sub);
}
static int cobalt_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
{
struct cobalt_stream *s = video_drvdata(file);
struct v4l2_fract fps;
if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
fps = v4l2_calc_timeperframe(&s->timings);
a->parm.capture.timeperframe.numerator = fps.numerator;
a->parm.capture.timeperframe.denominator = fps.denominator;
a->parm.capture.readbuffers = 3;
return 0;
}
static int cobalt_g_pixelaspect(struct file *file, void *fh,
int type, struct v4l2_fract *f)
{
struct cobalt_stream *s = video_drvdata(file);
struct v4l2_dv_timings timings;
int err = 0;
if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
if (s->input == 1)
timings = cea1080p60;
else
err = v4l2_subdev_call(s->sd, video, g_dv_timings, &timings);
if (!err)
*f = v4l2_dv_timings_aspect_ratio(&timings);
return err;
}
static int cobalt_g_selection(struct file *file, void *fh,
struct v4l2_selection *sel)
{
struct cobalt_stream *s = video_drvdata(file);
struct v4l2_dv_timings timings;
int err = 0;
if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
if (s->input == 1)
timings = cea1080p60;
else
err = v4l2_subdev_call(s->sd, video, g_dv_timings, &timings);
if (err)
return err;
switch (sel->target) {
case V4L2_SEL_TGT_CROP_BOUNDS:
case V4L2_SEL_TGT_CROP_DEFAULT:
sel->r.top = 0;
sel->r.left = 0;
sel->r.width = timings.bt.width;
sel->r.height = timings.bt.height;
break;
default:
return -EINVAL;
}
return 0;
}
static const struct v4l2_ioctl_ops cobalt_ioctl_ops = {
.vidioc_querycap = cobalt_querycap,
.vidioc_g_parm = cobalt_g_parm,
.vidioc_log_status = cobalt_log_status,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_g_pixelaspect = cobalt_g_pixelaspect,
.vidioc_g_selection = cobalt_g_selection,
.vidioc_enum_input = cobalt_enum_input,
.vidioc_g_input = cobalt_g_input,
.vidioc_s_input = cobalt_s_input,
.vidioc_enum_fmt_vid_cap = cobalt_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = cobalt_g_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = cobalt_s_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = cobalt_try_fmt_vid_cap,
.vidioc_enum_output = cobalt_enum_output,
.vidioc_g_output = cobalt_g_output,
.vidioc_s_output = cobalt_s_output,
.vidioc_enum_fmt_vid_out = cobalt_enum_fmt_vid_out,
.vidioc_g_fmt_vid_out = cobalt_g_fmt_vid_out,
.vidioc_s_fmt_vid_out = cobalt_s_fmt_vid_out,
.vidioc_try_fmt_vid_out = cobalt_try_fmt_vid_out,
.vidioc_s_dv_timings = cobalt_s_dv_timings,
.vidioc_g_dv_timings = cobalt_g_dv_timings,
.vidioc_query_dv_timings = cobalt_query_dv_timings,
.vidioc_enum_dv_timings = cobalt_enum_dv_timings,
.vidioc_dv_timings_cap = cobalt_dv_timings_cap,
.vidioc_g_edid = cobalt_g_edid,
.vidioc_s_edid = cobalt_s_edid,
.vidioc_subscribe_event = cobalt_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_create_bufs = vb2_ioctl_create_bufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_expbuf = vb2_ioctl_expbuf,
#ifdef CONFIG_VIDEO_ADV_DEBUG
.vidioc_g_register = cobalt_g_register,
.vidioc_s_register = cobalt_s_register,
#endif
};
static const struct v4l2_ioctl_ops cobalt_ioctl_empty_ops = {
#ifdef CONFIG_VIDEO_ADV_DEBUG
.vidioc_g_register = cobalt_g_register,
.vidioc_s_register = cobalt_s_register,
#endif
};
/* Register device nodes */
static const struct v4l2_file_operations cobalt_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.unlocked_ioctl = video_ioctl2,
.release = vb2_fop_release,
.poll = vb2_fop_poll,
.mmap = vb2_fop_mmap,
.read = vb2_fop_read,
};
static const struct v4l2_file_operations cobalt_out_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.unlocked_ioctl = video_ioctl2,
.release = vb2_fop_release,
.poll = vb2_fop_poll,
.mmap = vb2_fop_mmap,
.write = vb2_fop_write,
};
static const struct v4l2_file_operations cobalt_empty_fops = {
.owner = THIS_MODULE,
.open = v4l2_fh_open,
.unlocked_ioctl = video_ioctl2,
.release = v4l2_fh_release,
};
static int cobalt_node_register(struct cobalt *cobalt, int node)
{
static const struct v4l2_dv_timings dv1080p60 =
V4L2_DV_BT_CEA_1920X1080P60;
struct cobalt_stream *s = cobalt->streams + node;
struct video_device *vdev = &s->vdev;
struct vb2_queue *q = &s->q;
int ret;
mutex_init(&s->lock);
spin_lock_init(&s->irqlock);
snprintf(vdev->name, sizeof(vdev->name),
"%s-%d", cobalt->v4l2_dev.name, node);
s->width = 1920;
/* Audio frames are just 4 lines of 1920 bytes */
s->height = s->is_audio ? 4 : 1080;
if (s->is_audio) {
s->bpp = 1;
s->pixfmt = V4L2_PIX_FMT_GREY;
} else if (s->is_output) {
s->bpp = COBALT_BYTES_PER_PIXEL_RGB32;
s->pixfmt = V4L2_PIX_FMT_BGR32;
} else {
s->bpp = COBALT_BYTES_PER_PIXEL_YUYV;
s->pixfmt = V4L2_PIX_FMT_YUYV;
}
s->colorspace = V4L2_COLORSPACE_SRGB;
s->stride = s->width * s->bpp;
if (!s->is_audio) {
if (s->is_dummy)
cobalt_warn("Setting up dummy video node %d\n", node);
vdev->v4l2_dev = &cobalt->v4l2_dev;
if (s->is_dummy)
vdev->fops = &cobalt_empty_fops;
else
vdev->fops = s->is_output ? &cobalt_out_fops :
&cobalt_fops;
vdev->release = video_device_release_empty;
vdev->vfl_dir = s->is_output ? VFL_DIR_TX : VFL_DIR_RX;
vdev->lock = &s->lock;
if (s->sd)
vdev->ctrl_handler = s->sd->ctrl_handler;
s->timings = dv1080p60;
v4l2_subdev_call(s->sd, video, s_dv_timings, &s->timings);
if (!s->is_output && s->sd)
cobalt_enable_input(s);
vdev->ioctl_ops = s->is_dummy ? &cobalt_ioctl_empty_ops :
&cobalt_ioctl_ops;
}
INIT_LIST_HEAD(&s->bufs);
q->type = s->is_output ? V4L2_BUF_TYPE_VIDEO_OUTPUT :
V4L2_BUF_TYPE_VIDEO_CAPTURE;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
q->io_modes |= s->is_output ? VB2_WRITE : VB2_READ;
q->drv_priv = s;
q->buf_struct_size = sizeof(struct cobalt_buffer);
q->ops = &cobalt_qops;
q->mem_ops = &vb2_dma_sg_memops;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->min_buffers_needed = 2;
q->lock = &s->lock;
q->dev = &cobalt->pci_dev->dev;
vdev->queue = q;
vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
if (s->is_output)
vdev->device_caps |= V4L2_CAP_VIDEO_OUTPUT;
else
vdev->device_caps |= V4L2_CAP_VIDEO_CAPTURE;
video_set_drvdata(vdev, s);
ret = vb2_queue_init(q);
if (!s->is_audio && ret == 0)
ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
else if (!s->is_dummy)
ret = cobalt_alsa_init(s);
if (ret < 0) {
if (!s->is_audio)
cobalt_err("couldn't register v4l2 device node %d\n",
node);
return ret;
}
cobalt_info("registered node %d\n", node);
return 0;
}
/* Initialize v4l2 variables and register v4l2 devices */
int cobalt_nodes_register(struct cobalt *cobalt)
{
int node, ret;
/* Setup V4L2 Devices */
for (node = 0; node < COBALT_NUM_STREAMS; node++) {
ret = cobalt_node_register(cobalt, node);
if (ret)
return ret;
}
return 0;
}
/* Unregister v4l2 devices */
void cobalt_nodes_unregister(struct cobalt *cobalt)
{
int node;
/* Teardown all streams */
for (node = 0; node < COBALT_NUM_STREAMS; node++) {
struct cobalt_stream *s = cobalt->streams + node;
struct video_device *vdev = &s->vdev;
if (!s->is_audio)
video_unregister_device(vdev);
else if (!s->is_dummy)
cobalt_alsa_exit(s);
}
}
| linux-master | drivers/media/pci/cobalt/cobalt-v4l2.c |
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