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// SPDX-License-Identifier: GPL-2.0+
/*
* Nano River Technologies viperboard GPIO lib driver
*
* (C) 2012 by Lemonage GmbH
* Author: Lars Poeschel <[email protected]>
* All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/usb.h>
#include <linux/gpio/driver.h>
#include <linux/mfd/viperboard.h>
#define VPRBRD_GPIOA_CLK_1MHZ 0
#define VPRBRD_GPIOA_CLK_100KHZ 1
#define VPRBRD_GPIOA_CLK_10KHZ 2
#define VPRBRD_GPIOA_CLK_1KHZ 3
#define VPRBRD_GPIOA_CLK_100HZ 4
#define VPRBRD_GPIOA_CLK_10HZ 5
#define VPRBRD_GPIOA_FREQ_DEFAULT 1000
#define VPRBRD_GPIOA_CMD_CONT 0x00
#define VPRBRD_GPIOA_CMD_PULSE 0x01
#define VPRBRD_GPIOA_CMD_PWM 0x02
#define VPRBRD_GPIOA_CMD_SETOUT 0x03
#define VPRBRD_GPIOA_CMD_SETIN 0x04
#define VPRBRD_GPIOA_CMD_SETINT 0x05
#define VPRBRD_GPIOA_CMD_GETIN 0x06
#define VPRBRD_GPIOB_CMD_SETDIR 0x00
#define VPRBRD_GPIOB_CMD_SETVAL 0x01
struct vprbrd_gpioa_msg {
u8 cmd;
u8 clk;
u8 offset;
u8 t1;
u8 t2;
u8 invert;
u8 pwmlevel;
u8 outval;
u8 risefall;
u8 answer;
u8 __fill;
} __packed;
struct vprbrd_gpiob_msg {
u8 cmd;
u16 val;
u16 mask;
} __packed;
struct vprbrd_gpio {
struct gpio_chip gpioa; /* gpio a related things */
u32 gpioa_out;
u32 gpioa_val;
struct gpio_chip gpiob; /* gpio b related things */
u32 gpiob_out;
u32 gpiob_val;
struct vprbrd *vb;
};
/* gpioa sampling clock module parameter */
static unsigned char gpioa_clk;
static unsigned int gpioa_freq = VPRBRD_GPIOA_FREQ_DEFAULT;
module_param(gpioa_freq, uint, 0);
MODULE_PARM_DESC(gpioa_freq,
"gpio-a sampling freq in Hz (default is 1000Hz) valid values: 10, 100, 1000, 10000, 100000, 1000000");
/* ----- begin of gipo a chip -------------------------------------------- */
static int vprbrd_gpioa_get(struct gpio_chip *chip,
unsigned int offset)
{
int ret, answer, error = 0;
struct vprbrd_gpio *gpio = gpiochip_get_data(chip);
struct vprbrd *vb = gpio->vb;
struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf;
/* if io is set to output, just return the saved value */
if (gpio->gpioa_out & (1 << offset))
return !!(gpio->gpioa_val & (1 << offset));
mutex_lock(&vb->lock);
gamsg->cmd = VPRBRD_GPIOA_CMD_GETIN;
gamsg->clk = 0x00;
gamsg->offset = offset;
gamsg->t1 = 0x00;
gamsg->t2 = 0x00;
gamsg->invert = 0x00;
gamsg->pwmlevel = 0x00;
gamsg->outval = 0x00;
gamsg->risefall = 0x00;
gamsg->answer = 0x00;
gamsg->__fill = 0x00;
ret = usb_control_msg(vb->usb_dev, usb_sndctrlpipe(vb->usb_dev, 0),
VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_OUT, 0x0000,
0x0000, gamsg, sizeof(struct vprbrd_gpioa_msg),
VPRBRD_USB_TIMEOUT_MS);
if (ret != sizeof(struct vprbrd_gpioa_msg))
error = -EREMOTEIO;
ret = usb_control_msg(vb->usb_dev, usb_rcvctrlpipe(vb->usb_dev, 0),
VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_IN, 0x0000,
0x0000, gamsg, sizeof(struct vprbrd_gpioa_msg),
VPRBRD_USB_TIMEOUT_MS);
answer = gamsg->answer & 0x01;
mutex_unlock(&vb->lock);
if (ret != sizeof(struct vprbrd_gpioa_msg))
error = -EREMOTEIO;
if (error)
return error;
return answer;
}
static void vprbrd_gpioa_set(struct gpio_chip *chip,
unsigned int offset, int value)
{
int ret;
struct vprbrd_gpio *gpio = gpiochip_get_data(chip);
struct vprbrd *vb = gpio->vb;
struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf;
if (gpio->gpioa_out & (1 << offset)) {
if (value)
gpio->gpioa_val |= (1 << offset);
else
gpio->gpioa_val &= ~(1 << offset);
mutex_lock(&vb->lock);
gamsg->cmd = VPRBRD_GPIOA_CMD_SETOUT;
gamsg->clk = 0x00;
gamsg->offset = offset;
gamsg->t1 = 0x00;
gamsg->t2 = 0x00;
gamsg->invert = 0x00;
gamsg->pwmlevel = 0x00;
gamsg->outval = value;
gamsg->risefall = 0x00;
gamsg->answer = 0x00;
gamsg->__fill = 0x00;
ret = usb_control_msg(vb->usb_dev,
usb_sndctrlpipe(vb->usb_dev, 0),
VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_OUT,
0x0000, 0x0000, gamsg,
sizeof(struct vprbrd_gpioa_msg), VPRBRD_USB_TIMEOUT_MS);
mutex_unlock(&vb->lock);
if (ret != sizeof(struct vprbrd_gpioa_msg))
dev_err(chip->parent, "usb error setting pin value\n");
}
}
static int vprbrd_gpioa_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
int ret;
struct vprbrd_gpio *gpio = gpiochip_get_data(chip);
struct vprbrd *vb = gpio->vb;
struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf;
gpio->gpioa_out &= ~(1 << offset);
mutex_lock(&vb->lock);
gamsg->cmd = VPRBRD_GPIOA_CMD_SETIN;
gamsg->clk = gpioa_clk;
gamsg->offset = offset;
gamsg->t1 = 0x00;
gamsg->t2 = 0x00;
gamsg->invert = 0x00;
gamsg->pwmlevel = 0x00;
gamsg->outval = 0x00;
gamsg->risefall = 0x00;
gamsg->answer = 0x00;
gamsg->__fill = 0x00;
ret = usb_control_msg(vb->usb_dev, usb_sndctrlpipe(vb->usb_dev, 0),
VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_OUT, 0x0000,
0x0000, gamsg, sizeof(struct vprbrd_gpioa_msg),
VPRBRD_USB_TIMEOUT_MS);
mutex_unlock(&vb->lock);
if (ret != sizeof(struct vprbrd_gpioa_msg))
return -EREMOTEIO;
return 0;
}
static int vprbrd_gpioa_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
int ret;
struct vprbrd_gpio *gpio = gpiochip_get_data(chip);
struct vprbrd *vb = gpio->vb;
struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf;
gpio->gpioa_out |= (1 << offset);
if (value)
gpio->gpioa_val |= (1 << offset);
else
gpio->gpioa_val &= ~(1 << offset);
mutex_lock(&vb->lock);
gamsg->cmd = VPRBRD_GPIOA_CMD_SETOUT;
gamsg->clk = 0x00;
gamsg->offset = offset;
gamsg->t1 = 0x00;
gamsg->t2 = 0x00;
gamsg->invert = 0x00;
gamsg->pwmlevel = 0x00;
gamsg->outval = value;
gamsg->risefall = 0x00;
gamsg->answer = 0x00;
gamsg->__fill = 0x00;
ret = usb_control_msg(vb->usb_dev, usb_sndctrlpipe(vb->usb_dev, 0),
VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_OUT, 0x0000,
0x0000, gamsg, sizeof(struct vprbrd_gpioa_msg),
VPRBRD_USB_TIMEOUT_MS);
mutex_unlock(&vb->lock);
if (ret != sizeof(struct vprbrd_gpioa_msg))
return -EREMOTEIO;
return 0;
}
/* ----- end of gpio a chip ---------------------------------------------- */
/* ----- begin of gipo b chip -------------------------------------------- */
static int vprbrd_gpiob_setdir(struct vprbrd *vb, unsigned int offset,
unsigned int dir)
{
struct vprbrd_gpiob_msg *gbmsg = (struct vprbrd_gpiob_msg *)vb->buf;
int ret;
gbmsg->cmd = VPRBRD_GPIOB_CMD_SETDIR;
gbmsg->val = cpu_to_be16(dir << offset);
gbmsg->mask = cpu_to_be16(0x0001 << offset);
ret = usb_control_msg(vb->usb_dev, usb_sndctrlpipe(vb->usb_dev, 0),
VPRBRD_USB_REQUEST_GPIOB, VPRBRD_USB_TYPE_OUT, 0x0000,
0x0000, gbmsg, sizeof(struct vprbrd_gpiob_msg),
VPRBRD_USB_TIMEOUT_MS);
if (ret != sizeof(struct vprbrd_gpiob_msg))
return -EREMOTEIO;
return 0;
}
static int vprbrd_gpiob_get(struct gpio_chip *chip,
unsigned int offset)
{
int ret;
u16 val;
struct vprbrd_gpio *gpio = gpiochip_get_data(chip);
struct vprbrd *vb = gpio->vb;
struct vprbrd_gpiob_msg *gbmsg = (struct vprbrd_gpiob_msg *)vb->buf;
/* if io is set to output, just return the saved value */
if (gpio->gpiob_out & (1 << offset))
return gpio->gpiob_val & (1 << offset);
mutex_lock(&vb->lock);
ret = usb_control_msg(vb->usb_dev, usb_rcvctrlpipe(vb->usb_dev, 0),
VPRBRD_USB_REQUEST_GPIOB, VPRBRD_USB_TYPE_IN, 0x0000,
0x0000, gbmsg, sizeof(struct vprbrd_gpiob_msg),
VPRBRD_USB_TIMEOUT_MS);
val = gbmsg->val;
mutex_unlock(&vb->lock);
if (ret != sizeof(struct vprbrd_gpiob_msg))
return ret;
/* cache the read values */
gpio->gpiob_val = be16_to_cpu(val);
return (gpio->gpiob_val >> offset) & 0x1;
}
static void vprbrd_gpiob_set(struct gpio_chip *chip,
unsigned int offset, int value)
{
int ret;
struct vprbrd_gpio *gpio = gpiochip_get_data(chip);
struct vprbrd *vb = gpio->vb;
struct vprbrd_gpiob_msg *gbmsg = (struct vprbrd_gpiob_msg *)vb->buf;
if (gpio->gpiob_out & (1 << offset)) {
if (value)
gpio->gpiob_val |= (1 << offset);
else
gpio->gpiob_val &= ~(1 << offset);
mutex_lock(&vb->lock);
gbmsg->cmd = VPRBRD_GPIOB_CMD_SETVAL;
gbmsg->val = cpu_to_be16(value << offset);
gbmsg->mask = cpu_to_be16(0x0001 << offset);
ret = usb_control_msg(vb->usb_dev,
usb_sndctrlpipe(vb->usb_dev, 0),
VPRBRD_USB_REQUEST_GPIOB, VPRBRD_USB_TYPE_OUT,
0x0000, 0x0000, gbmsg,
sizeof(struct vprbrd_gpiob_msg), VPRBRD_USB_TIMEOUT_MS);
mutex_unlock(&vb->lock);
if (ret != sizeof(struct vprbrd_gpiob_msg))
dev_err(chip->parent, "usb error setting pin value\n");
}
}
static int vprbrd_gpiob_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
int ret;
struct vprbrd_gpio *gpio = gpiochip_get_data(chip);
struct vprbrd *vb = gpio->vb;
gpio->gpiob_out &= ~(1 << offset);
mutex_lock(&vb->lock);
ret = vprbrd_gpiob_setdir(vb, offset, 0);
mutex_unlock(&vb->lock);
if (ret)
dev_err(chip->parent, "usb error setting pin to input\n");
return ret;
}
static int vprbrd_gpiob_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
int ret;
struct vprbrd_gpio *gpio = gpiochip_get_data(chip);
struct vprbrd *vb = gpio->vb;
gpio->gpiob_out |= (1 << offset);
mutex_lock(&vb->lock);
ret = vprbrd_gpiob_setdir(vb, offset, 1);
if (ret)
dev_err(chip->parent, "usb error setting pin to output\n");
mutex_unlock(&vb->lock);
vprbrd_gpiob_set(chip, offset, value);
return ret;
}
/* ----- end of gpio b chip ---------------------------------------------- */
static int vprbrd_gpio_probe(struct platform_device *pdev)
{
struct vprbrd *vb = dev_get_drvdata(pdev->dev.parent);
struct vprbrd_gpio *vb_gpio;
int ret;
vb_gpio = devm_kzalloc(&pdev->dev, sizeof(*vb_gpio), GFP_KERNEL);
if (vb_gpio == NULL)
return -ENOMEM;
vb_gpio->vb = vb;
/* registering gpio a */
vb_gpio->gpioa.label = "viperboard gpio a";
vb_gpio->gpioa.parent = &pdev->dev;
vb_gpio->gpioa.owner = THIS_MODULE;
vb_gpio->gpioa.base = -1;
vb_gpio->gpioa.ngpio = 16;
vb_gpio->gpioa.can_sleep = true;
vb_gpio->gpioa.set = vprbrd_gpioa_set;
vb_gpio->gpioa.get = vprbrd_gpioa_get;
vb_gpio->gpioa.direction_input = vprbrd_gpioa_direction_input;
vb_gpio->gpioa.direction_output = vprbrd_gpioa_direction_output;
ret = devm_gpiochip_add_data(&pdev->dev, &vb_gpio->gpioa, vb_gpio);
if (ret < 0)
return ret;
/* registering gpio b */
vb_gpio->gpiob.label = "viperboard gpio b";
vb_gpio->gpiob.parent = &pdev->dev;
vb_gpio->gpiob.owner = THIS_MODULE;
vb_gpio->gpiob.base = -1;
vb_gpio->gpiob.ngpio = 16;
vb_gpio->gpiob.can_sleep = true;
vb_gpio->gpiob.set = vprbrd_gpiob_set;
vb_gpio->gpiob.get = vprbrd_gpiob_get;
vb_gpio->gpiob.direction_input = vprbrd_gpiob_direction_input;
vb_gpio->gpiob.direction_output = vprbrd_gpiob_direction_output;
return devm_gpiochip_add_data(&pdev->dev, &vb_gpio->gpiob, vb_gpio);
}
static struct platform_driver vprbrd_gpio_driver = {
.driver.name = "viperboard-gpio",
.probe = vprbrd_gpio_probe,
};
static int __init vprbrd_gpio_init(void)
{
switch (gpioa_freq) {
case 1000000:
gpioa_clk = VPRBRD_GPIOA_CLK_1MHZ;
break;
case 100000:
gpioa_clk = VPRBRD_GPIOA_CLK_100KHZ;
break;
case 10000:
gpioa_clk = VPRBRD_GPIOA_CLK_10KHZ;
break;
case 1000:
gpioa_clk = VPRBRD_GPIOA_CLK_1KHZ;
break;
case 100:
gpioa_clk = VPRBRD_GPIOA_CLK_100HZ;
break;
case 10:
gpioa_clk = VPRBRD_GPIOA_CLK_10HZ;
break;
default:
pr_warn("invalid gpioa_freq (%d)\n", gpioa_freq);
gpioa_clk = VPRBRD_GPIOA_CLK_1KHZ;
}
return platform_driver_register(&vprbrd_gpio_driver);
}
subsys_initcall(vprbrd_gpio_init);
static void __exit vprbrd_gpio_exit(void)
{
platform_driver_unregister(&vprbrd_gpio_driver);
}
module_exit(vprbrd_gpio_exit);
MODULE_AUTHOR("Lars Poeschel <[email protected]>");
MODULE_DESCRIPTION("GPIO driver for Nano River Techs Viperboard");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:viperboard-gpio");
| linux-master | drivers/gpio/gpio-viperboard.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* PCA953x 4/8/16/24/40 bit I/O ports
*
* Copyright (C) 2005 Ben Gardner <[email protected]>
* Copyright (C) 2007 Marvell International Ltd.
*
* Derived from drivers/i2c/chips/pca9539.c
*/
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_data/pca953x.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <asm/unaligned.h>
#define PCA953X_INPUT 0x00
#define PCA953X_OUTPUT 0x01
#define PCA953X_INVERT 0x02
#define PCA953X_DIRECTION 0x03
#define REG_ADDR_MASK GENMASK(5, 0)
#define REG_ADDR_EXT BIT(6)
#define REG_ADDR_AI BIT(7)
#define PCA957X_IN 0x00
#define PCA957X_INVRT 0x01
#define PCA957X_BKEN 0x02
#define PCA957X_PUPD 0x03
#define PCA957X_CFG 0x04
#define PCA957X_OUT 0x05
#define PCA957X_MSK 0x06
#define PCA957X_INTS 0x07
#define PCAL953X_OUT_STRENGTH 0x20
#define PCAL953X_IN_LATCH 0x22
#define PCAL953X_PULL_EN 0x23
#define PCAL953X_PULL_SEL 0x24
#define PCAL953X_INT_MASK 0x25
#define PCAL953X_INT_STAT 0x26
#define PCAL953X_OUT_CONF 0x27
#define PCAL6524_INT_EDGE 0x28
#define PCAL6524_INT_CLR 0x2a
#define PCAL6524_IN_STATUS 0x2b
#define PCAL6524_OUT_INDCONF 0x2c
#define PCAL6524_DEBOUNCE 0x2d
#define PCA_GPIO_MASK GENMASK(7, 0)
#define PCAL_GPIO_MASK GENMASK(4, 0)
#define PCAL_PINCTRL_MASK GENMASK(6, 5)
#define PCA_INT BIT(8)
#define PCA_PCAL BIT(9)
#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
#define PCA953X_TYPE BIT(12)
#define PCA957X_TYPE BIT(13)
#define PCAL653X_TYPE BIT(14)
#define PCA_TYPE_MASK GENMASK(15, 12)
#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
static const struct i2c_device_id pca953x_id[] = {
{ "pca6408", 8 | PCA953X_TYPE | PCA_INT, },
{ "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
{ "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
{ "pca9506", 40 | PCA953X_TYPE | PCA_INT, },
{ "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
{ "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
{ "pca9536", 4 | PCA953X_TYPE, },
{ "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
{ "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
{ "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
{ "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
{ "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
{ "pca9556", 8 | PCA953X_TYPE, },
{ "pca9557", 8 | PCA953X_TYPE, },
{ "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
{ "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
{ "pca9698", 40 | PCA953X_TYPE, },
{ "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
{ "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
{ "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
{ "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, },
{ "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
{ "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
{ "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
{ "max7310", 8 | PCA953X_TYPE, },
{ "max7312", 16 | PCA953X_TYPE | PCA_INT, },
{ "max7313", 16 | PCA953X_TYPE | PCA_INT, },
{ "max7315", 8 | PCA953X_TYPE | PCA_INT, },
{ "max7318", 16 | PCA953X_TYPE | PCA_INT, },
{ "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
{ "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
{ "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
{ "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
{ "tca9538", 8 | PCA953X_TYPE | PCA_INT, },
{ "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
{ "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
{ "xra1202", 8 | PCA953X_TYPE },
{ }
};
MODULE_DEVICE_TABLE(i2c, pca953x_id);
#ifdef CONFIG_GPIO_PCA953X_IRQ
#include <linux/dmi.h>
static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true };
static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = {
{ "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
{ }
};
static int pca953x_acpi_get_irq(struct device *dev)
{
int ret;
ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios);
if (ret)
dev_warn(dev, "can't add GPIO ACPI mapping\n");
ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
if (ret < 0)
return ret;
dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
return ret;
}
static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
{
/*
* On Intel Galileo Gen 2 board the IRQ pin of one of
* the I²C GPIO expanders, which has GpioInt() resource,
* is provided as an absolute number instead of being
* relative. Since first controller (gpio-sch.c) and
* second (gpio-dwapb.c) are at the fixed bases, we may
* safely refer to the number in the global space to get
* an IRQ out of it.
*/
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
},
},
{}
};
#endif
static const struct acpi_device_id pca953x_acpi_ids[] = {
{ "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
{ }
};
MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
#define MAX_BANK 5
#define BANK_SZ 8
#define MAX_LINE (MAX_BANK * BANK_SZ)
#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
struct pca953x_reg_config {
int direction;
int output;
int input;
int invert;
};
static const struct pca953x_reg_config pca953x_regs = {
.direction = PCA953X_DIRECTION,
.output = PCA953X_OUTPUT,
.input = PCA953X_INPUT,
.invert = PCA953X_INVERT,
};
static const struct pca953x_reg_config pca957x_regs = {
.direction = PCA957X_CFG,
.output = PCA957X_OUT,
.input = PCA957X_IN,
.invert = PCA957X_INVRT,
};
struct pca953x_chip {
unsigned gpio_start;
struct mutex i2c_lock;
struct regmap *regmap;
#ifdef CONFIG_GPIO_PCA953X_IRQ
struct mutex irq_lock;
DECLARE_BITMAP(irq_mask, MAX_LINE);
DECLARE_BITMAP(irq_stat, MAX_LINE);
DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
#endif
atomic_t wakeup_path;
struct i2c_client *client;
struct gpio_chip gpio_chip;
const char *const *names;
unsigned long driver_data;
struct regulator *regulator;
const struct pca953x_reg_config *regs;
u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off);
bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg,
u32 checkbank);
};
static int pca953x_bank_shift(struct pca953x_chip *chip)
{
return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
}
#define PCA953x_BANK_INPUT BIT(0)
#define PCA953x_BANK_OUTPUT BIT(1)
#define PCA953x_BANK_POLARITY BIT(2)
#define PCA953x_BANK_CONFIG BIT(3)
#define PCA957x_BANK_INPUT BIT(0)
#define PCA957x_BANK_POLARITY BIT(1)
#define PCA957x_BANK_BUSHOLD BIT(2)
#define PCA957x_BANK_CONFIG BIT(4)
#define PCA957x_BANK_OUTPUT BIT(5)
#define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
#define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
#define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
#define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
#define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
/*
* We care about the following registers:
* - Standard set, below 0x40, each port can be replicated up to 8 times
* - PCA953x standard
* Input port 0x00 + 0 * bank_size R
* Output port 0x00 + 1 * bank_size RW
* Polarity Inversion port 0x00 + 2 * bank_size RW
* Configuration port 0x00 + 3 * bank_size RW
* - PCA957x with mixed up registers
* Input port 0x00 + 0 * bank_size R
* Polarity Inversion port 0x00 + 1 * bank_size RW
* Bus hold port 0x00 + 2 * bank_size RW
* Configuration port 0x00 + 4 * bank_size RW
* Output port 0x00 + 5 * bank_size RW
*
* - Extended set, above 0x40, often chip specific.
* - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
* Input latch register 0x40 + 2 * bank_size RW
* Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
* Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
* Interrupt mask register 0x40 + 5 * bank_size RW
* Interrupt status register 0x40 + 6 * bank_size R
*
* - Registers with bit 0x80 set, the AI bit
* The bit is cleared and the registers fall into one of the
* categories above.
*/
static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
u32 checkbank)
{
int bank_shift = pca953x_bank_shift(chip);
int bank = (reg & REG_ADDR_MASK) >> bank_shift;
int offset = reg & (BIT(bank_shift) - 1);
/* Special PCAL extended register check. */
if (reg & REG_ADDR_EXT) {
if (!(chip->driver_data & PCA_PCAL))
return false;
bank += 8;
}
/* Register is not in the matching bank. */
if (!(BIT(bank) & checkbank))
return false;
/* Register is not within allowed range of bank. */
if (offset >= NBANK(chip))
return false;
return true;
}
/*
* Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the
* same register layout as the PCAL6524, the spacing of the registers has been
* fundamentally altered by compacting them and thus does not obey the same
* rules, including being able to use bit shifting to determine bank. These
* chips hence need special handling here.
*/
static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg,
u32 checkbank)
{
int bank_shift;
int bank;
int offset;
if (reg >= 0x54) {
/*
* Handle lack of reserved registers after output port
* configuration register to form a bank.
*/
reg -= 0x54;
bank_shift = 16;
} else if (reg >= 0x30) {
/*
* Reserved block between 14h and 2Fh does not align on
* expected bank boundaries like other devices.
*/
reg -= 0x30;
bank_shift = 8;
} else {
bank_shift = 0;
}
bank = bank_shift + reg / NBANK(chip);
offset = reg % NBANK(chip);
/* Register is not in the matching bank. */
if (!(BIT(bank) & checkbank))
return false;
/* Register is not within allowed range of bank. */
if (offset >= NBANK(chip))
return false;
return true;
}
static bool pca953x_readable_register(struct device *dev, unsigned int reg)
{
struct pca953x_chip *chip = dev_get_drvdata(dev);
u32 bank;
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
PCA957x_BANK_BUSHOLD;
} else {
bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
}
if (chip->driver_data & PCA_PCAL) {
bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
PCAL9xxx_BANK_IRQ_STAT;
}
return chip->check_reg(chip, reg, bank);
}
static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
{
struct pca953x_chip *chip = dev_get_drvdata(dev);
u32 bank;
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
} else {
bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
PCA953x_BANK_CONFIG;
}
if (chip->driver_data & PCA_PCAL)
bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
return chip->check_reg(chip, reg, bank);
}
static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
{
struct pca953x_chip *chip = dev_get_drvdata(dev);
u32 bank;
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
bank = PCA957x_BANK_INPUT;
else
bank = PCA953x_BANK_INPUT;
if (chip->driver_data & PCA_PCAL)
bank |= PCAL9xxx_BANK_IRQ_STAT;
return chip->check_reg(chip, reg, bank);
}
static const struct regmap_config pca953x_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.use_single_read = true,
.use_single_write = true,
.readable_reg = pca953x_readable_register,
.writeable_reg = pca953x_writeable_register,
.volatile_reg = pca953x_volatile_register,
.disable_locking = true,
.cache_type = REGCACHE_RBTREE,
.max_register = 0x7f,
};
static const struct regmap_config pca953x_ai_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.read_flag_mask = REG_ADDR_AI,
.write_flag_mask = REG_ADDR_AI,
.readable_reg = pca953x_readable_register,
.writeable_reg = pca953x_writeable_register,
.volatile_reg = pca953x_volatile_register,
.disable_locking = true,
.cache_type = REGCACHE_RBTREE,
.max_register = 0x7f,
};
static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
{
int bank_shift = pca953x_bank_shift(chip);
int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
u8 regaddr = pinctrl | addr | (off / BANK_SZ);
return regaddr;
}
/*
* The PCAL6534 and compatible chips have altered bank alignment that doesn't
* fit within the bit shifting scheme used for other devices.
*/
static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off)
{
int addr;
int pinctrl;
addr = (reg & PCAL_GPIO_MASK) * NBANK(chip);
switch (reg) {
case PCAL953X_OUT_STRENGTH:
case PCAL953X_IN_LATCH:
case PCAL953X_PULL_EN:
case PCAL953X_PULL_SEL:
case PCAL953X_INT_MASK:
case PCAL953X_INT_STAT:
pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20;
break;
case PCAL6524_INT_EDGE:
case PCAL6524_INT_CLR:
case PCAL6524_IN_STATUS:
case PCAL6524_OUT_INDCONF:
case PCAL6524_DEBOUNCE:
pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c;
break;
default:
pinctrl = 0;
break;
}
return pinctrl + addr + (off / BANK_SZ);
}
static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
{
u8 regaddr = chip->recalc_addr(chip, reg, 0);
u8 value[MAX_BANK];
int i, ret;
for (i = 0; i < NBANK(chip); i++)
value[i] = bitmap_get_value8(val, i * BANK_SZ);
ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
if (ret < 0) {
dev_err(&chip->client->dev, "failed writing register\n");
return ret;
}
return 0;
}
static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
{
u8 regaddr = chip->recalc_addr(chip, reg, 0);
u8 value[MAX_BANK];
int i, ret;
ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
if (ret < 0) {
dev_err(&chip->client->dev, "failed reading register\n");
return ret;
}
for (i = 0; i < NBANK(chip); i++)
bitmap_set_value8(val, value[i], i * BANK_SZ);
return 0;
}
static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
{
struct pca953x_chip *chip = gpiochip_get_data(gc);
u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
u8 bit = BIT(off % BANK_SZ);
int ret;
mutex_lock(&chip->i2c_lock);
ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
mutex_unlock(&chip->i2c_lock);
return ret;
}
static int pca953x_gpio_direction_output(struct gpio_chip *gc,
unsigned off, int val)
{
struct pca953x_chip *chip = gpiochip_get_data(gc);
u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
u8 bit = BIT(off % BANK_SZ);
int ret;
mutex_lock(&chip->i2c_lock);
/* set output level */
ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
if (ret)
goto exit;
/* then direction */
ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
exit:
mutex_unlock(&chip->i2c_lock);
return ret;
}
static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
{
struct pca953x_chip *chip = gpiochip_get_data(gc);
u8 inreg = chip->recalc_addr(chip, chip->regs->input, off);
u8 bit = BIT(off % BANK_SZ);
u32 reg_val;
int ret;
mutex_lock(&chip->i2c_lock);
ret = regmap_read(chip->regmap, inreg, ®_val);
mutex_unlock(&chip->i2c_lock);
if (ret < 0)
return ret;
return !!(reg_val & bit);
}
static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
{
struct pca953x_chip *chip = gpiochip_get_data(gc);
u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
u8 bit = BIT(off % BANK_SZ);
mutex_lock(&chip->i2c_lock);
regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
mutex_unlock(&chip->i2c_lock);
}
static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
{
struct pca953x_chip *chip = gpiochip_get_data(gc);
u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
u8 bit = BIT(off % BANK_SZ);
u32 reg_val;
int ret;
mutex_lock(&chip->i2c_lock);
ret = regmap_read(chip->regmap, dirreg, ®_val);
mutex_unlock(&chip->i2c_lock);
if (ret < 0)
return ret;
if (reg_val & bit)
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
unsigned long *mask, unsigned long *bits)
{
struct pca953x_chip *chip = gpiochip_get_data(gc);
DECLARE_BITMAP(reg_val, MAX_LINE);
int ret;
mutex_lock(&chip->i2c_lock);
ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
mutex_unlock(&chip->i2c_lock);
if (ret)
return ret;
bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
return 0;
}
static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
unsigned long *mask, unsigned long *bits)
{
struct pca953x_chip *chip = gpiochip_get_data(gc);
DECLARE_BITMAP(reg_val, MAX_LINE);
int ret;
mutex_lock(&chip->i2c_lock);
ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
if (ret)
goto exit;
bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);
pca953x_write_regs(chip, chip->regs->output, reg_val);
exit:
mutex_unlock(&chip->i2c_lock);
}
static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
unsigned int offset,
unsigned long config)
{
enum pin_config_param param = pinconf_to_config_param(config);
u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset);
u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset);
u8 bit = BIT(offset % BANK_SZ);
int ret;
/*
* pull-up/pull-down configuration requires PCAL extended
* registers
*/
if (!(chip->driver_data & PCA_PCAL))
return -ENOTSUPP;
mutex_lock(&chip->i2c_lock);
/* Configure pull-up/pull-down */
if (param == PIN_CONFIG_BIAS_PULL_UP)
ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
else
ret = 0;
if (ret)
goto exit;
/* Disable/Enable pull-up/pull-down */
if (param == PIN_CONFIG_BIAS_DISABLE)
ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
else
ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
exit:
mutex_unlock(&chip->i2c_lock);
return ret;
}
static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
unsigned long config)
{
struct pca953x_chip *chip = gpiochip_get_data(gc);
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_DISABLE:
return pca953x_gpio_set_pull_up_down(chip, offset, config);
default:
return -ENOTSUPP;
}
}
static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
{
struct gpio_chip *gc;
gc = &chip->gpio_chip;
gc->direction_input = pca953x_gpio_direction_input;
gc->direction_output = pca953x_gpio_direction_output;
gc->get = pca953x_gpio_get_value;
gc->set = pca953x_gpio_set_value;
gc->get_direction = pca953x_gpio_get_direction;
gc->get_multiple = pca953x_gpio_get_multiple;
gc->set_multiple = pca953x_gpio_set_multiple;
gc->set_config = pca953x_gpio_set_config;
gc->can_sleep = true;
gc->base = chip->gpio_start;
gc->ngpio = gpios;
gc->label = dev_name(&chip->client->dev);
gc->parent = &chip->client->dev;
gc->owner = THIS_MODULE;
gc->names = chip->names;
}
#ifdef CONFIG_GPIO_PCA953X_IRQ
static void pca953x_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pca953x_chip *chip = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
clear_bit(hwirq, chip->irq_mask);
gpiochip_disable_irq(gc, hwirq);
}
static void pca953x_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pca953x_chip *chip = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
gpiochip_enable_irq(gc, hwirq);
set_bit(hwirq, chip->irq_mask);
}
static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pca953x_chip *chip = gpiochip_get_data(gc);
if (on)
atomic_inc(&chip->wakeup_path);
else
atomic_dec(&chip->wakeup_path);
return irq_set_irq_wake(chip->client->irq, on);
}
static void pca953x_irq_bus_lock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pca953x_chip *chip = gpiochip_get_data(gc);
mutex_lock(&chip->irq_lock);
}
static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pca953x_chip *chip = gpiochip_get_data(gc);
DECLARE_BITMAP(irq_mask, MAX_LINE);
DECLARE_BITMAP(reg_direction, MAX_LINE);
int level;
if (chip->driver_data & PCA_PCAL) {
/* Enable latch on interrupt-enabled inputs */
pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
/* Unmask enabled interrupts */
pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);
}
/* Switch direction to input if needed */
pca953x_read_regs(chip, chip->regs->direction, reg_direction);
bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
bitmap_complement(reg_direction, reg_direction, gc->ngpio);
bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
/* Look for any newly setup interrupt */
for_each_set_bit(level, irq_mask, gc->ngpio)
pca953x_gpio_direction_input(&chip->gpio_chip, level);
mutex_unlock(&chip->irq_lock);
}
static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pca953x_chip *chip = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
if (!(type & IRQ_TYPE_EDGE_BOTH)) {
dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
d->irq, type);
return -EINVAL;
}
assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
return 0;
}
static void pca953x_irq_shutdown(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pca953x_chip *chip = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
clear_bit(hwirq, chip->irq_trig_raise);
clear_bit(hwirq, chip->irq_trig_fall);
}
static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
seq_printf(p, dev_name(gc->parent));
}
static const struct irq_chip pca953x_irq_chip = {
.irq_mask = pca953x_irq_mask,
.irq_unmask = pca953x_irq_unmask,
.irq_set_wake = pca953x_irq_set_wake,
.irq_bus_lock = pca953x_irq_bus_lock,
.irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
.irq_set_type = pca953x_irq_set_type,
.irq_shutdown = pca953x_irq_shutdown,
.irq_print_chip = pca953x_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
{
struct gpio_chip *gc = &chip->gpio_chip;
DECLARE_BITMAP(reg_direction, MAX_LINE);
DECLARE_BITMAP(old_stat, MAX_LINE);
DECLARE_BITMAP(cur_stat, MAX_LINE);
DECLARE_BITMAP(new_stat, MAX_LINE);
DECLARE_BITMAP(trigger, MAX_LINE);
int ret;
if (chip->driver_data & PCA_PCAL) {
/* Read the current interrupt status from the device */
ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
if (ret)
return false;
/* Check latched inputs and clear interrupt status */
ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
if (ret)
return false;
/* Apply filter for rising/falling edge selection */
bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);
bitmap_and(pending, new_stat, trigger, gc->ngpio);
return !bitmap_empty(pending, gc->ngpio);
}
ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
if (ret)
return false;
/* Remove output pins from the equation */
pca953x_read_regs(chip, chip->regs->direction, reg_direction);
bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);
bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
if (bitmap_empty(trigger, gc->ngpio))
return false;
bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);
bitmap_and(pending, new_stat, trigger, gc->ngpio);
return !bitmap_empty(pending, gc->ngpio);
}
static irqreturn_t pca953x_irq_handler(int irq, void *devid)
{
struct pca953x_chip *chip = devid;
struct gpio_chip *gc = &chip->gpio_chip;
DECLARE_BITMAP(pending, MAX_LINE);
int level;
bool ret;
bitmap_zero(pending, MAX_LINE);
mutex_lock(&chip->i2c_lock);
ret = pca953x_irq_pending(chip, pending);
mutex_unlock(&chip->i2c_lock);
if (ret) {
ret = 0;
for_each_set_bit(level, pending, gc->ngpio) {
int nested_irq = irq_find_mapping(gc->irq.domain, level);
if (unlikely(nested_irq <= 0)) {
dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
continue;
}
handle_nested_irq(nested_irq);
ret = 1;
}
}
return IRQ_RETVAL(ret);
}
static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
{
struct i2c_client *client = chip->client;
DECLARE_BITMAP(reg_direction, MAX_LINE);
DECLARE_BITMAP(irq_stat, MAX_LINE);
struct gpio_irq_chip *girq;
int ret;
if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {
ret = pca953x_acpi_get_irq(&client->dev);
if (ret > 0)
client->irq = ret;
}
if (!client->irq)
return 0;
if (irq_base == -1)
return 0;
if (!(chip->driver_data & PCA_INT))
return 0;
ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
if (ret)
return ret;
/*
* There is no way to know which GPIO line generated the
* interrupt. We have to rely on the previous read for
* this purpose.
*/
pca953x_read_regs(chip, chip->regs->direction, reg_direction);
bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio);
mutex_init(&chip->irq_lock);
girq = &chip->gpio_chip.irq;
gpio_irq_chip_set_chip(girq, &pca953x_irq_chip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
girq->threaded = true;
girq->first = irq_base; /* FIXME: get rid of this */
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, pca953x_irq_handler,
IRQF_ONESHOT | IRQF_SHARED,
dev_name(&client->dev), chip);
if (ret) {
dev_err(&client->dev, "failed to request irq %d\n",
client->irq);
return ret;
}
return 0;
}
#else /* CONFIG_GPIO_PCA953X_IRQ */
static int pca953x_irq_setup(struct pca953x_chip *chip,
int irq_base)
{
struct i2c_client *client = chip->client;
if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
dev_warn(&client->dev, "interrupt support not compiled in\n");
return 0;
}
#endif
static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert)
{
DECLARE_BITMAP(val, MAX_LINE);
u8 regaddr;
int ret;
regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
ret = regcache_sync_region(chip->regmap, regaddr,
regaddr + NBANK(chip) - 1);
if (ret)
goto out;
regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
ret = regcache_sync_region(chip->regmap, regaddr,
regaddr + NBANK(chip) - 1);
if (ret)
goto out;
/* set platform specific polarity inversion */
if (invert)
bitmap_fill(val, MAX_LINE);
else
bitmap_zero(val, MAX_LINE);
ret = pca953x_write_regs(chip, chip->regs->invert, val);
out:
return ret;
}
static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
{
DECLARE_BITMAP(val, MAX_LINE);
unsigned int i;
int ret;
ret = device_pca95xx_init(chip, invert);
if (ret)
goto out;
/* To enable register 6, 7 to control pull up and pull down */
for (i = 0; i < NBANK(chip); i++)
bitmap_set_value8(val, 0x02, i * BANK_SZ);
ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
if (ret)
goto out;
return 0;
out:
return ret;
}
static int pca953x_probe(struct i2c_client *client)
{
struct pca953x_platform_data *pdata;
struct pca953x_chip *chip;
int irq_base = 0;
int ret;
u32 invert = 0;
struct regulator *reg;
const struct regmap_config *regmap_config;
chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
if (chip == NULL)
return -ENOMEM;
pdata = dev_get_platdata(&client->dev);
if (pdata) {
irq_base = pdata->irq_base;
chip->gpio_start = pdata->gpio_base;
invert = pdata->invert;
chip->names = pdata->names;
} else {
struct gpio_desc *reset_gpio;
chip->gpio_start = -1;
irq_base = 0;
/*
* See if we need to de-assert a reset pin.
*
* There is no known ACPI-enabled platforms that are
* using "reset" GPIO. Otherwise any of those platform
* must use _DSD method with corresponding property.
*/
reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(reset_gpio))
return PTR_ERR(reset_gpio);
}
chip->client = client;
chip->driver_data = (uintptr_t)i2c_get_match_data(client);
if (!chip->driver_data)
return -ENODEV;
reg = devm_regulator_get(&client->dev, "vcc");
if (IS_ERR(reg))
return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n");
ret = regulator_enable(reg);
if (ret) {
dev_err(&client->dev, "reg en err: %d\n", ret);
return ret;
}
chip->regulator = reg;
i2c_set_clientdata(client, chip);
pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
dev_info(&client->dev, "using AI\n");
regmap_config = &pca953x_ai_i2c_regmap;
} else {
dev_info(&client->dev, "using no AI\n");
regmap_config = &pca953x_i2c_regmap;
}
if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) {
chip->recalc_addr = pcal6534_recalc_addr;
chip->check_reg = pcal6534_check_register;
} else {
chip->recalc_addr = pca953x_recalc_addr;
chip->check_reg = pca953x_check_register;
}
chip->regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(chip->regmap)) {
ret = PTR_ERR(chip->regmap);
goto err_exit;
}
regcache_mark_dirty(chip->regmap);
mutex_init(&chip->i2c_lock);
/*
* In case we have an i2c-mux controlled by a GPIO provided by an
* expander using the same driver higher on the device tree, read the
* i2c adapter nesting depth and use the retrieved value as lockdep
* subclass for chip->i2c_lock.
*
* REVISIT: This solution is not complete. It protects us from lockdep
* false positives when the expander controlling the i2c-mux is on
* a different level on the device tree, but not when it's on the same
* level on a different branch (in which case the subclass number
* would be the same).
*
* TODO: Once a correct solution is developed, a similar fix should be
* applied to all other i2c-controlled GPIO expanders (and potentially
* regmap-i2c).
*/
lockdep_set_subclass(&chip->i2c_lock,
i2c_adapter_depth(client->adapter));
/* initialize cached registers from their original values.
* we can't share this chip with another i2c master.
*/
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
chip->regs = &pca957x_regs;
ret = device_pca957x_init(chip, invert);
} else {
chip->regs = &pca953x_regs;
ret = device_pca95xx_init(chip, invert);
}
if (ret)
goto err_exit;
ret = pca953x_irq_setup(chip, irq_base);
if (ret)
goto err_exit;
ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
if (ret)
goto err_exit;
if (pdata && pdata->setup) {
ret = pdata->setup(client, chip->gpio_chip.base,
chip->gpio_chip.ngpio, pdata->context);
if (ret < 0)
dev_warn(&client->dev, "setup failed, %d\n", ret);
}
return 0;
err_exit:
regulator_disable(chip->regulator);
return ret;
}
static void pca953x_remove(struct i2c_client *client)
{
struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
struct pca953x_chip *chip = i2c_get_clientdata(client);
if (pdata && pdata->teardown) {
pdata->teardown(client, chip->gpio_chip.base,
chip->gpio_chip.ngpio, pdata->context);
}
regulator_disable(chip->regulator);
}
#ifdef CONFIG_PM_SLEEP
static int pca953x_regcache_sync(struct device *dev)
{
struct pca953x_chip *chip = dev_get_drvdata(dev);
int ret;
u8 regaddr;
/*
* The ordering between direction and output is important,
* sync these registers first and only then sync the rest.
*/
regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
if (ret) {
dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
return ret;
}
regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
if (ret) {
dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
return ret;
}
#ifdef CONFIG_GPIO_PCA953X_IRQ
if (chip->driver_data & PCA_PCAL) {
regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0);
ret = regcache_sync_region(chip->regmap, regaddr,
regaddr + NBANK(chip) - 1);
if (ret) {
dev_err(dev, "Failed to sync INT latch registers: %d\n",
ret);
return ret;
}
regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0);
ret = regcache_sync_region(chip->regmap, regaddr,
regaddr + NBANK(chip) - 1);
if (ret) {
dev_err(dev, "Failed to sync INT mask registers: %d\n",
ret);
return ret;
}
}
#endif
return 0;
}
static int pca953x_suspend(struct device *dev)
{
struct pca953x_chip *chip = dev_get_drvdata(dev);
mutex_lock(&chip->i2c_lock);
regcache_cache_only(chip->regmap, true);
mutex_unlock(&chip->i2c_lock);
if (atomic_read(&chip->wakeup_path))
device_set_wakeup_path(dev);
else
regulator_disable(chip->regulator);
return 0;
}
static int pca953x_resume(struct device *dev)
{
struct pca953x_chip *chip = dev_get_drvdata(dev);
int ret;
if (!atomic_read(&chip->wakeup_path)) {
ret = regulator_enable(chip->regulator);
if (ret) {
dev_err(dev, "Failed to enable regulator: %d\n", ret);
return 0;
}
}
mutex_lock(&chip->i2c_lock);
regcache_cache_only(chip->regmap, false);
regcache_mark_dirty(chip->regmap);
ret = pca953x_regcache_sync(dev);
if (ret) {
mutex_unlock(&chip->i2c_lock);
return ret;
}
ret = regcache_sync(chip->regmap);
mutex_unlock(&chip->i2c_lock);
if (ret) {
dev_err(dev, "Failed to restore register map: %d\n", ret);
return ret;
}
return 0;
}
#endif
/* convenience to stop overlong match-table lines */
#define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int))
#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
static const struct of_device_id pca953x_dt_ids[] = {
{ .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), },
{ .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
{ .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
{ .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), },
{ .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
{ .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
{ .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
{ .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
{ .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
{ .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
{ .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
{ .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
{ .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
{ .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
{ .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
{ .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), },
{ .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
{ .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
{ .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), },
{ .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
{ .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },
{ .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
{ .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
{ .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
{ .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
{ .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
{ .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
{ .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
{ .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), },
{ .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
{ .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
{ .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
{ .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), },
{ .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
{ }
};
MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
static struct i2c_driver pca953x_driver = {
.driver = {
.name = "pca953x",
.pm = &pca953x_pm_ops,
.of_match_table = pca953x_dt_ids,
.acpi_match_table = pca953x_acpi_ids,
},
.probe = pca953x_probe,
.remove = pca953x_remove,
.id_table = pca953x_id,
};
static int __init pca953x_init(void)
{
return i2c_add_driver(&pca953x_driver);
}
/* register after i2c postcore initcall and before
* subsys initcalls that may rely on these GPIOs
*/
subsys_initcall(pca953x_init);
static void __exit pca953x_exit(void)
{
i2c_del_driver(&pca953x_driver);
}
module_exit(pca953x_exit);
MODULE_AUTHOR("eric miao <[email protected]>");
MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-pca953x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Timberdale FPGA GPIO driver
* Author: Mocean Laboratories
* Copyright (c) 2009 Intel Corporation
*/
/* Supports:
* Timberdale FPGA GPIO
*/
#include <linux/init.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/timb_gpio.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#define DRIVER_NAME "timb-gpio"
#define TGPIOVAL 0x00
#define TGPIODIR 0x04
#define TGPIO_IER 0x08
#define TGPIO_ISR 0x0c
#define TGPIO_IPR 0x10
#define TGPIO_ICR 0x14
#define TGPIO_FLR 0x18
#define TGPIO_LVR 0x1c
#define TGPIO_VER 0x20
#define TGPIO_BFLR 0x24
struct timbgpio {
void __iomem *membase;
spinlock_t lock; /* mutual exclusion */
struct gpio_chip gpio;
int irq_base;
unsigned long last_ier;
};
static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
unsigned offset, bool enabled)
{
struct timbgpio *tgpio = gpiochip_get_data(gpio);
u32 reg;
spin_lock(&tgpio->lock);
reg = ioread32(tgpio->membase + offset);
if (enabled)
reg |= (1 << index);
else
reg &= ~(1 << index);
iowrite32(reg, tgpio->membase + offset);
spin_unlock(&tgpio->lock);
return 0;
}
static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
}
static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
struct timbgpio *tgpio = gpiochip_get_data(gpio);
u32 value;
value = ioread32(tgpio->membase + TGPIOVAL);
return (value & (1 << nr)) ? 1 : 0;
}
static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
unsigned nr, int val)
{
return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
}
static void timbgpio_gpio_set(struct gpio_chip *gpio,
unsigned nr, int val)
{
timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
}
static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
struct timbgpio *tgpio = gpiochip_get_data(gpio);
if (tgpio->irq_base <= 0)
return -EINVAL;
return tgpio->irq_base + offset;
}
/*
* GPIO IRQ
*/
static void timbgpio_irq_disable(struct irq_data *d)
{
struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
int offset = d->irq - tgpio->irq_base;
unsigned long flags;
spin_lock_irqsave(&tgpio->lock, flags);
tgpio->last_ier &= ~(1UL << offset);
iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
spin_unlock_irqrestore(&tgpio->lock, flags);
}
static void timbgpio_irq_enable(struct irq_data *d)
{
struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
int offset = d->irq - tgpio->irq_base;
unsigned long flags;
spin_lock_irqsave(&tgpio->lock, flags);
tgpio->last_ier |= 1UL << offset;
iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
spin_unlock_irqrestore(&tgpio->lock, flags);
}
static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
{
struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
int offset = d->irq - tgpio->irq_base;
unsigned long flags;
u32 lvr, flr, bflr = 0;
u32 ver;
int ret = 0;
if (offset < 0 || offset > tgpio->gpio.ngpio)
return -EINVAL;
ver = ioread32(tgpio->membase + TGPIO_VER);
spin_lock_irqsave(&tgpio->lock, flags);
lvr = ioread32(tgpio->membase + TGPIO_LVR);
flr = ioread32(tgpio->membase + TGPIO_FLR);
if (ver > 2)
bflr = ioread32(tgpio->membase + TGPIO_BFLR);
if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
bflr &= ~(1 << offset);
flr &= ~(1 << offset);
if (trigger & IRQ_TYPE_LEVEL_HIGH)
lvr |= 1 << offset;
else
lvr &= ~(1 << offset);
}
if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
if (ver < 3) {
ret = -EINVAL;
goto out;
} else {
flr |= 1 << offset;
bflr |= 1 << offset;
}
} else {
bflr &= ~(1 << offset);
flr |= 1 << offset;
if (trigger & IRQ_TYPE_EDGE_FALLING)
lvr &= ~(1 << offset);
else
lvr |= 1 << offset;
}
iowrite32(lvr, tgpio->membase + TGPIO_LVR);
iowrite32(flr, tgpio->membase + TGPIO_FLR);
if (ver > 2)
iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
out:
spin_unlock_irqrestore(&tgpio->lock, flags);
return ret;
}
static void timbgpio_irq(struct irq_desc *desc)
{
struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
struct irq_data *data = irq_desc_get_irq_data(desc);
unsigned long ipr;
int offset;
data->chip->irq_ack(data);
ipr = ioread32(tgpio->membase + TGPIO_IPR);
iowrite32(ipr, tgpio->membase + TGPIO_ICR);
/*
* Some versions of the hardware trash the IER register if more than
* one interrupt is received simultaneously.
*/
iowrite32(0, tgpio->membase + TGPIO_IER);
for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
}
static struct irq_chip timbgpio_irqchip = {
.name = "GPIO",
.irq_enable = timbgpio_irq_enable,
.irq_disable = timbgpio_irq_disable,
.irq_set_type = timbgpio_irq_type,
};
static int timbgpio_probe(struct platform_device *pdev)
{
int err, i;
struct device *dev = &pdev->dev;
struct gpio_chip *gc;
struct timbgpio *tgpio;
struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
int irq = platform_get_irq(pdev, 0);
if (!pdata || pdata->nr_pins > 32) {
dev_err(dev, "Invalid platform data\n");
return -EINVAL;
}
tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL);
if (!tgpio)
return -EINVAL;
tgpio->irq_base = pdata->irq_base;
spin_lock_init(&tgpio->lock);
tgpio->membase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(tgpio->membase))
return PTR_ERR(tgpio->membase);
gc = &tgpio->gpio;
gc->label = dev_name(&pdev->dev);
gc->owner = THIS_MODULE;
gc->parent = &pdev->dev;
gc->direction_input = timbgpio_gpio_direction_input;
gc->get = timbgpio_gpio_get;
gc->direction_output = timbgpio_gpio_direction_output;
gc->set = timbgpio_gpio_set;
gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
gc->dbg_show = NULL;
gc->base = pdata->gpio_base;
gc->ngpio = pdata->nr_pins;
gc->can_sleep = false;
err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
if (err)
return err;
/* make sure to disable interrupts */
iowrite32(0x0, tgpio->membase + TGPIO_IER);
if (irq < 0 || tgpio->irq_base <= 0)
return 0;
for (i = 0; i < pdata->nr_pins; i++) {
irq_set_chip_and_handler(tgpio->irq_base + i,
&timbgpio_irqchip, handle_simple_irq);
irq_set_chip_data(tgpio->irq_base + i, tgpio);
irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
}
irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
return 0;
}
static struct platform_driver timbgpio_platform_driver = {
.driver = {
.name = DRIVER_NAME,
.suppress_bind_attrs = true,
},
.probe = timbgpio_probe,
};
/*--------------------------------------------------------------------------*/
builtin_platform_driver(timbgpio_platform_driver);
| linux-master | drivers/gpio/gpio-timberdale.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* gpiolib support for Wolfson WM8994
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/gpio/driver.h>
#include <linux/mfd/core.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/regmap.h>
#include <linux/mfd/wm8994/core.h>
#include <linux/mfd/wm8994/pdata.h>
#include <linux/mfd/wm8994/gpio.h>
#include <linux/mfd/wm8994/registers.h>
struct wm8994_gpio {
struct wm8994 *wm8994;
struct gpio_chip gpio_chip;
};
static int wm8994_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct wm8994_gpio *wm8994_gpio = gpiochip_get_data(chip);
struct wm8994 *wm8994 = wm8994_gpio->wm8994;
switch (wm8994->type) {
case WM8958:
switch (offset) {
case 1:
case 2:
case 3:
case 4:
case 6:
return -EINVAL;
}
break;
default:
break;
}
return 0;
}
static int wm8994_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
struct wm8994_gpio *wm8994_gpio = gpiochip_get_data(chip);
struct wm8994 *wm8994 = wm8994_gpio->wm8994;
return wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset,
WM8994_GPN_DIR, WM8994_GPN_DIR);
}
static int wm8994_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct wm8994_gpio *wm8994_gpio = gpiochip_get_data(chip);
struct wm8994 *wm8994 = wm8994_gpio->wm8994;
int ret;
ret = wm8994_reg_read(wm8994, WM8994_GPIO_1 + offset);
if (ret < 0)
return ret;
if (ret & WM8994_GPN_LVL)
return 1;
else
return 0;
}
static int wm8994_gpio_direction_out(struct gpio_chip *chip,
unsigned offset, int value)
{
struct wm8994_gpio *wm8994_gpio = gpiochip_get_data(chip);
struct wm8994 *wm8994 = wm8994_gpio->wm8994;
if (value)
value = WM8994_GPN_LVL;
return wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset,
WM8994_GPN_DIR | WM8994_GPN_LVL, value);
}
static void wm8994_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct wm8994_gpio *wm8994_gpio = gpiochip_get_data(chip);
struct wm8994 *wm8994 = wm8994_gpio->wm8994;
if (value)
value = WM8994_GPN_LVL;
wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset, WM8994_GPN_LVL, value);
}
static int wm8994_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
struct wm8994_gpio *wm8994_gpio = gpiochip_get_data(chip);
struct wm8994 *wm8994 = wm8994_gpio->wm8994;
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
return wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset,
WM8994_GPN_OP_CFG_MASK,
WM8994_GPN_OP_CFG);
case PIN_CONFIG_DRIVE_PUSH_PULL:
return wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset,
WM8994_GPN_OP_CFG_MASK, 0);
default:
break;
}
return -ENOTSUPP;
}
static int wm8994_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
struct wm8994_gpio *wm8994_gpio = gpiochip_get_data(chip);
struct wm8994 *wm8994 = wm8994_gpio->wm8994;
return regmap_irq_get_virq(wm8994->irq_data, offset);
}
#ifdef CONFIG_DEBUG_FS
static const char *wm8994_gpio_fn(u16 fn)
{
switch (fn) {
case WM8994_GP_FN_PIN_SPECIFIC:
return "pin-specific";
case WM8994_GP_FN_GPIO:
return "GPIO";
case WM8994_GP_FN_SDOUT:
return "SDOUT";
case WM8994_GP_FN_IRQ:
return "IRQ";
case WM8994_GP_FN_TEMPERATURE:
return "Temperature";
case WM8994_GP_FN_MICBIAS1_DET:
return "MICBIAS1 detect";
case WM8994_GP_FN_MICBIAS1_SHORT:
return "MICBIAS1 short";
case WM8994_GP_FN_MICBIAS2_DET:
return "MICBIAS2 detect";
case WM8994_GP_FN_MICBIAS2_SHORT:
return "MICBIAS2 short";
case WM8994_GP_FN_FLL1_LOCK:
return "FLL1 lock";
case WM8994_GP_FN_FLL2_LOCK:
return "FLL2 lock";
case WM8994_GP_FN_SRC1_LOCK:
return "SRC1 lock";
case WM8994_GP_FN_SRC2_LOCK:
return "SRC2 lock";
case WM8994_GP_FN_DRC1_ACT:
return "DRC1 activity";
case WM8994_GP_FN_DRC2_ACT:
return "DRC2 activity";
case WM8994_GP_FN_DRC3_ACT:
return "DRC3 activity";
case WM8994_GP_FN_WSEQ_STATUS:
return "Write sequencer";
case WM8994_GP_FN_FIFO_ERROR:
return "FIFO error";
case WM8994_GP_FN_OPCLK:
return "OPCLK";
case WM8994_GP_FN_THW:
return "Thermal warning";
case WM8994_GP_FN_DCS_DONE:
return "DC servo";
case WM8994_GP_FN_FLL1_OUT:
return "FLL1 output";
case WM8994_GP_FN_FLL2_OUT:
return "FLL1 output";
default:
return "Unknown";
}
}
static void wm8994_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
struct wm8994_gpio *wm8994_gpio = gpiochip_get_data(chip);
struct wm8994 *wm8994 = wm8994_gpio->wm8994;
int i;
for (i = 0; i < chip->ngpio; i++) {
int gpio = i + chip->base;
int reg;
const char *label;
/* We report the GPIO even if it's not requested since
* we're also reporting things like alternate
* functions which apply even when the GPIO is not in
* use as a GPIO.
*/
label = gpiochip_is_requested(chip, i);
if (!label)
label = "Unrequested";
seq_printf(s, " gpio-%-3d (%-20.20s) ", gpio, label);
reg = wm8994_reg_read(wm8994, WM8994_GPIO_1 + i);
if (reg < 0) {
dev_err(wm8994->dev,
"GPIO control %d read failed: %d\n",
gpio, reg);
seq_printf(s, "\n");
continue;
}
if (reg & WM8994_GPN_DIR)
seq_printf(s, "in ");
else
seq_printf(s, "out ");
if (reg & WM8994_GPN_PU)
seq_printf(s, "pull up ");
if (reg & WM8994_GPN_PD)
seq_printf(s, "pull down ");
if (reg & WM8994_GPN_POL)
seq_printf(s, "inverted ");
else
seq_printf(s, "noninverted ");
if (reg & WM8994_GPN_OP_CFG)
seq_printf(s, "open drain ");
else
seq_printf(s, "push-pull ");
seq_printf(s, "%s (%x)\n",
wm8994_gpio_fn(reg & WM8994_GPN_FN_MASK), reg);
}
}
#else
#define wm8994_gpio_dbg_show NULL
#endif
static const struct gpio_chip template_chip = {
.label = "wm8994",
.owner = THIS_MODULE,
.request = wm8994_gpio_request,
.direction_input = wm8994_gpio_direction_in,
.get = wm8994_gpio_get,
.direction_output = wm8994_gpio_direction_out,
.set = wm8994_gpio_set,
.set_config = wm8994_gpio_set_config,
.to_irq = wm8994_gpio_to_irq,
.dbg_show = wm8994_gpio_dbg_show,
.can_sleep = true,
};
static int wm8994_gpio_probe(struct platform_device *pdev)
{
struct wm8994 *wm8994 = dev_get_drvdata(pdev->dev.parent);
struct wm8994_pdata *pdata = dev_get_platdata(wm8994->dev);
struct wm8994_gpio *wm8994_gpio;
wm8994_gpio = devm_kzalloc(&pdev->dev, sizeof(*wm8994_gpio),
GFP_KERNEL);
if (wm8994_gpio == NULL)
return -ENOMEM;
wm8994_gpio->wm8994 = wm8994;
wm8994_gpio->gpio_chip = template_chip;
wm8994_gpio->gpio_chip.ngpio = WM8994_GPIO_MAX;
wm8994_gpio->gpio_chip.parent = &pdev->dev;
if (pdata && pdata->gpio_base)
wm8994_gpio->gpio_chip.base = pdata->gpio_base;
else
wm8994_gpio->gpio_chip.base = -1;
return devm_gpiochip_add_data(&pdev->dev, &wm8994_gpio->gpio_chip, wm8994_gpio);
}
static struct platform_driver wm8994_gpio_driver = {
.driver.name = "wm8994-gpio",
.probe = wm8994_gpio_probe,
};
static int __init wm8994_gpio_init(void)
{
return platform_driver_register(&wm8994_gpio_driver);
}
subsys_initcall(wm8994_gpio_init);
static void __exit wm8994_gpio_exit(void)
{
platform_driver_unregister(&wm8994_gpio_driver);
}
module_exit(wm8994_gpio_exit);
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_DESCRIPTION("GPIO interface for WM8994");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:wm8994-gpio");
| linux-master | drivers/gpio/gpio-wm8994.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AppliedMicro X-Gene SoC GPIO Driver
*
* Copyright (c) 2014, Applied Micro Circuits Corporation
* Author: Feng Kan <[email protected]>.
*/
#include <linux/acpi.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>
#include <linux/types.h>
#include <linux/bitops.h>
#define GPIO_SET_DR_OFFSET 0x0C
#define GPIO_DATA_OFFSET 0x14
#define GPIO_BANK_STRIDE 0x0C
#define XGENE_GPIOS_PER_BANK 16
#define XGENE_MAX_GPIO_BANKS 3
#define XGENE_MAX_GPIOS (XGENE_GPIOS_PER_BANK * XGENE_MAX_GPIO_BANKS)
#define GPIO_BIT_OFFSET(x) (x % XGENE_GPIOS_PER_BANK)
#define GPIO_BANK_OFFSET(x) ((x / XGENE_GPIOS_PER_BANK) * GPIO_BANK_STRIDE)
struct xgene_gpio {
struct gpio_chip chip;
void __iomem *base;
spinlock_t lock;
u32 set_dr_val[XGENE_MAX_GPIO_BANKS];
};
static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct xgene_gpio *chip = gpiochip_get_data(gc);
unsigned long bank_offset;
u32 bit_offset;
bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset);
bit_offset = GPIO_BIT_OFFSET(offset);
return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
}
static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
{
struct xgene_gpio *chip = gpiochip_get_data(gc);
unsigned long bank_offset;
u32 setval, bit_offset;
bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK;
setval = ioread32(chip->base + bank_offset);
if (val)
setval |= BIT(bit_offset);
else
setval &= ~BIT(bit_offset);
iowrite32(setval, chip->base + bank_offset);
}
static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
{
struct xgene_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
__xgene_gpio_set(gc, offset, val);
spin_unlock_irqrestore(&chip->lock, flags);
}
static int xgene_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
struct xgene_gpio *chip = gpiochip_get_data(gc);
unsigned long bank_offset, bit_offset;
bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
bit_offset = GPIO_BIT_OFFSET(offset);
if (ioread32(chip->base + bank_offset) & BIT(bit_offset))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static int xgene_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
{
struct xgene_gpio *chip = gpiochip_get_data(gc);
unsigned long flags, bank_offset;
u32 dirval, bit_offset;
bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
bit_offset = GPIO_BIT_OFFSET(offset);
spin_lock_irqsave(&chip->lock, flags);
dirval = ioread32(chip->base + bank_offset);
dirval |= BIT(bit_offset);
iowrite32(dirval, chip->base + bank_offset);
spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
static int xgene_gpio_dir_out(struct gpio_chip *gc,
unsigned int offset, int val)
{
struct xgene_gpio *chip = gpiochip_get_data(gc);
unsigned long flags, bank_offset;
u32 dirval, bit_offset;
bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
bit_offset = GPIO_BIT_OFFSET(offset);
spin_lock_irqsave(&chip->lock, flags);
dirval = ioread32(chip->base + bank_offset);
dirval &= ~BIT(bit_offset);
iowrite32(dirval, chip->base + bank_offset);
__xgene_gpio_set(gc, offset, val);
spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
static __maybe_unused int xgene_gpio_suspend(struct device *dev)
{
struct xgene_gpio *gpio = dev_get_drvdata(dev);
unsigned long bank_offset;
unsigned int bank;
for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
}
return 0;
}
static __maybe_unused int xgene_gpio_resume(struct device *dev)
{
struct xgene_gpio *gpio = dev_get_drvdata(dev);
unsigned long bank_offset;
unsigned int bank;
for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset);
}
return 0;
}
static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume);
static int xgene_gpio_probe(struct platform_device *pdev)
{
struct xgene_gpio *gpio;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
gpio->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(gpio->base))
return PTR_ERR(gpio->base);
gpio->chip.ngpio = XGENE_MAX_GPIOS;
spin_lock_init(&gpio->lock);
gpio->chip.parent = &pdev->dev;
gpio->chip.get_direction = xgene_gpio_get_direction;
gpio->chip.direction_input = xgene_gpio_dir_in;
gpio->chip.direction_output = xgene_gpio_dir_out;
gpio->chip.get = xgene_gpio_get;
gpio->chip.set = xgene_gpio_set;
gpio->chip.label = dev_name(&pdev->dev);
gpio->chip.base = -1;
platform_set_drvdata(pdev, gpio);
return devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
}
static const struct of_device_id xgene_gpio_of_match[] = {
{ .compatible = "apm,xgene-gpio", },
{},
};
#ifdef CONFIG_ACPI
static const struct acpi_device_id xgene_gpio_acpi_match[] = {
{ "APMC0D14", 0 },
{ },
};
#endif
static struct platform_driver xgene_gpio_driver = {
.driver = {
.name = "xgene-gpio",
.of_match_table = xgene_gpio_of_match,
.acpi_match_table = ACPI_PTR(xgene_gpio_acpi_match),
.pm = &xgene_gpio_pm,
},
.probe = xgene_gpio_probe,
};
builtin_platform_driver(xgene_gpio_driver);
| linux-master | drivers/gpio/gpio-xgene.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 Broadcom
*/
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#define IPROC_CCA_INT_F_GPIOINT BIT(0)
#define IPROC_CCA_INT_STS 0x20
#define IPROC_CCA_INT_MASK 0x24
#define IPROC_GPIO_CCA_DIN 0x0
#define IPROC_GPIO_CCA_DOUT 0x4
#define IPROC_GPIO_CCA_OUT_EN 0x8
#define IPROC_GPIO_CCA_INT_LEVEL 0x10
#define IPROC_GPIO_CCA_INT_LEVEL_MASK 0x14
#define IPROC_GPIO_CCA_INT_EVENT 0x18
#define IPROC_GPIO_CCA_INT_EVENT_MASK 0x1C
#define IPROC_GPIO_CCA_INT_EDGE 0x24
struct iproc_gpio_chip {
struct gpio_chip gc;
spinlock_t lock;
struct device *dev;
void __iomem *base;
void __iomem *intr;
};
static inline struct iproc_gpio_chip *
to_iproc_gpio(struct gpio_chip *gc)
{
return container_of(gc, struct iproc_gpio_chip, gc);
}
static void iproc_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
int pin = d->hwirq;
unsigned long flags;
u32 irq = d->irq;
u32 irq_type, event_status = 0;
spin_lock_irqsave(&chip->lock, flags);
irq_type = irq_get_trigger_type(irq);
if (irq_type & IRQ_TYPE_EDGE_BOTH) {
event_status |= BIT(pin);
writel_relaxed(event_status,
chip->base + IPROC_GPIO_CCA_INT_EVENT);
}
spin_unlock_irqrestore(&chip->lock, flags);
}
static void iproc_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
int pin = d->hwirq;
unsigned long flags;
u32 irq = d->irq;
u32 int_mask, irq_type, event_mask;
gpiochip_enable_irq(gc, pin);
spin_lock_irqsave(&chip->lock, flags);
irq_type = irq_get_trigger_type(irq);
event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
if (irq_type & IRQ_TYPE_EDGE_BOTH) {
event_mask |= 1 << pin;
writel_relaxed(event_mask,
chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
} else {
int_mask |= 1 << pin;
writel_relaxed(int_mask,
chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
}
spin_unlock_irqrestore(&chip->lock, flags);
}
static void iproc_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
int pin = d->hwirq;
unsigned long flags;
u32 irq = d->irq;
u32 irq_type, int_mask, event_mask;
spin_lock_irqsave(&chip->lock, flags);
irq_type = irq_get_trigger_type(irq);
event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
if (irq_type & IRQ_TYPE_EDGE_BOTH) {
event_mask &= ~BIT(pin);
writel_relaxed(event_mask,
chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
} else {
int_mask &= ~BIT(pin);
writel_relaxed(int_mask,
chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
}
spin_unlock_irqrestore(&chip->lock, flags);
gpiochip_disable_irq(gc, pin);
}
static int iproc_gpio_irq_set_type(struct irq_data *d, u32 type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
int pin = d->hwirq;
unsigned long flags;
u32 irq = d->irq;
u32 event_pol, int_pol;
int ret = 0;
spin_lock_irqsave(&chip->lock, flags);
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE);
event_pol &= ~BIT(pin);
writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
break;
case IRQ_TYPE_EDGE_FALLING:
event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE);
event_pol |= BIT(pin);
writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
break;
case IRQ_TYPE_LEVEL_HIGH:
int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
int_pol &= ~BIT(pin);
writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
break;
case IRQ_TYPE_LEVEL_LOW:
int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
int_pol |= BIT(pin);
writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
break;
default:
/* should not come here */
ret = -EINVAL;
goto out_unlock;
}
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(irq_get_irq_data(irq), handle_level_irq);
else if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(irq_get_irq_data(irq), handle_edge_irq);
out_unlock:
spin_unlock_irqrestore(&chip->lock, flags);
return ret;
}
static irqreturn_t iproc_gpio_irq_handler(int irq, void *data)
{
struct gpio_chip *gc = (struct gpio_chip *)data;
struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
int bit;
unsigned long int_bits = 0;
u32 int_status;
/* go through the entire GPIOs and handle all interrupts */
int_status = readl_relaxed(chip->intr + IPROC_CCA_INT_STS);
if (int_status & IPROC_CCA_INT_F_GPIOINT) {
u32 event, level;
/* Get level and edge interrupts */
event =
readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
event &= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT);
level = readl_relaxed(chip->base + IPROC_GPIO_CCA_DIN);
level ^= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
level &=
readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
int_bits = level | event;
for_each_set_bit(bit, &int_bits, gc->ngpio)
generic_handle_domain_irq(gc->irq.domain, bit);
}
return int_bits ? IRQ_HANDLED : IRQ_NONE;
}
static void iproc_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
seq_printf(p, dev_name(chip->dev));
}
static const struct irq_chip iproc_gpio_irq_chip = {
.irq_ack = iproc_gpio_irq_ack,
.irq_mask = iproc_gpio_irq_mask,
.irq_unmask = iproc_gpio_irq_unmask,
.irq_set_type = iproc_gpio_irq_set_type,
.irq_print_chip = iproc_gpio_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int iproc_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *dn = pdev->dev.of_node;
struct iproc_gpio_chip *chip;
u32 num_gpios;
int irq, ret;
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->dev = dev;
platform_set_drvdata(pdev, chip);
spin_lock_init(&chip->lock);
chip->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(chip->base))
return PTR_ERR(chip->base);
ret = bgpio_init(&chip->gc, dev, 4,
chip->base + IPROC_GPIO_CCA_DIN,
chip->base + IPROC_GPIO_CCA_DOUT,
NULL,
chip->base + IPROC_GPIO_CCA_OUT_EN,
NULL,
0);
if (ret) {
dev_err(dev, "unable to init GPIO chip\n");
return ret;
}
chip->gc.label = dev_name(dev);
if (!of_property_read_u32(dn, "ngpios", &num_gpios))
chip->gc.ngpio = num_gpios;
irq = platform_get_irq(pdev, 0);
if (irq > 0) {
struct gpio_irq_chip *girq;
u32 val;
chip->intr = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(chip->intr))
return PTR_ERR(chip->intr);
/* Enable GPIO interrupts for CCA GPIO */
val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
val |= IPROC_CCA_INT_F_GPIOINT;
writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
/*
* Directly request the irq here instead of passing
* a flow-handler because the irq is shared.
*/
ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler,
IRQF_SHARED, chip->gc.label, &chip->gc);
if (ret) {
dev_err(dev, "Fail to request IRQ%d: %d\n", irq, ret);
return ret;
}
girq = &chip->gc.irq;
gpio_irq_chip_set_chip(girq, &iproc_gpio_irq_chip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
}
ret = devm_gpiochip_add_data(dev, &chip->gc, chip);
if (ret) {
dev_err(dev, "unable to add GPIO chip\n");
return ret;
}
return 0;
}
static int iproc_gpio_remove(struct platform_device *pdev)
{
struct iproc_gpio_chip *chip = platform_get_drvdata(pdev);
if (chip->intr) {
u32 val;
val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
val &= ~IPROC_CCA_INT_F_GPIOINT;
writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
}
return 0;
}
static const struct of_device_id bcm_iproc_gpio_of_match[] = {
{ .compatible = "brcm,iproc-gpio-cca" },
{}
};
MODULE_DEVICE_TABLE(of, bcm_iproc_gpio_of_match);
static struct platform_driver bcm_iproc_gpio_driver = {
.driver = {
.name = "iproc-xgs-gpio",
.of_match_table = bcm_iproc_gpio_of_match,
},
.probe = iproc_gpio_probe,
.remove = iproc_gpio_remove,
};
module_platform_driver(bcm_iproc_gpio_driver);
MODULE_DESCRIPTION("XGS IPROC GPIO driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-xgs-iproc.c |
// SPDX-License-Identifier: GPL-2.0-only
/**
* Copyright (C) 2006 Juergen Beisert, Pengutronix
* Copyright (C) 2008 Guennadi Liakhovetski, Pengutronix
* Copyright (C) 2009 Wolfram Sang, Pengutronix
*
* The Maxim MAX7300/1 device is an I2C/SPI driven GPIO expander. There are
* 28 GPIOs. 8 of them can trigger an interrupt. See datasheet for more
* details
* Note:
* - DIN must be stable at the rising edge of clock.
* - when writing:
* - always clock in 16 clocks at once
* - at DIN: D15 first, D0 last
* - D0..D7 = databyte, D8..D14 = commandbyte
* - D15 = low -> write command
* - when reading
* - always clock in 16 clocks at once
* - at DIN: D15 first, D0 last
* - D0..D7 = dummy, D8..D14 = register address
* - D15 = high -> read command
* - raise CS and assert it again
* - always clock in 16 clocks at once
* - at DOUT: D15 first, D0 last
* - D0..D7 contains the data from the first cycle
*
* The driver exports a standard gpiochip interface
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/spi/max7301.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
/*
* Pin configurations, see MAX7301 datasheet page 6
*/
#define PIN_CONFIG_MASK 0x03
#define PIN_CONFIG_IN_PULLUP 0x03
#define PIN_CONFIG_IN_WO_PULLUP 0x02
#define PIN_CONFIG_OUT 0x01
#define PIN_NUMBER 28
static int max7301_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct max7301 *ts = container_of(chip, struct max7301, chip);
u8 *config;
u8 offset_bits, pin_config;
int ret;
/* First 4 pins are unused in the controller */
offset += 4;
offset_bits = (offset & 3) << 1;
config = &ts->port_config[offset >> 2];
if (ts->input_pullup_active & BIT(offset))
pin_config = PIN_CONFIG_IN_PULLUP;
else
pin_config = PIN_CONFIG_IN_WO_PULLUP;
mutex_lock(&ts->lock);
*config = (*config & ~(PIN_CONFIG_MASK << offset_bits))
| (pin_config << offset_bits);
ret = ts->write(ts->dev, 0x08 + (offset >> 2), *config);
mutex_unlock(&ts->lock);
return ret;
}
static int __max7301_set(struct max7301 *ts, unsigned offset, int value)
{
if (value) {
ts->out_level |= 1 << offset;
return ts->write(ts->dev, 0x20 + offset, 0x01);
} else {
ts->out_level &= ~(1 << offset);
return ts->write(ts->dev, 0x20 + offset, 0x00);
}
}
static int max7301_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
struct max7301 *ts = container_of(chip, struct max7301, chip);
u8 *config;
u8 offset_bits;
int ret;
/* First 4 pins are unused in the controller */
offset += 4;
offset_bits = (offset & 3) << 1;
config = &ts->port_config[offset >> 2];
mutex_lock(&ts->lock);
*config = (*config & ~(PIN_CONFIG_MASK << offset_bits))
| (PIN_CONFIG_OUT << offset_bits);
ret = __max7301_set(ts, offset, value);
if (!ret)
ret = ts->write(ts->dev, 0x08 + (offset >> 2), *config);
mutex_unlock(&ts->lock);
return ret;
}
static int max7301_get(struct gpio_chip *chip, unsigned offset)
{
struct max7301 *ts = gpiochip_get_data(chip);
int config, level = -EINVAL;
/* First 4 pins are unused in the controller */
offset += 4;
mutex_lock(&ts->lock);
config = (ts->port_config[offset >> 2] >> ((offset & 3) << 1))
& PIN_CONFIG_MASK;
switch (config) {
case PIN_CONFIG_OUT:
/* Output: return cached level */
level = !!(ts->out_level & (1 << offset));
break;
case PIN_CONFIG_IN_WO_PULLUP:
case PIN_CONFIG_IN_PULLUP:
/* Input: read out */
level = ts->read(ts->dev, 0x20 + offset) & 0x01;
}
mutex_unlock(&ts->lock);
return level;
}
static void max7301_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct max7301 *ts = gpiochip_get_data(chip);
/* First 4 pins are unused in the controller */
offset += 4;
mutex_lock(&ts->lock);
__max7301_set(ts, offset, value);
mutex_unlock(&ts->lock);
}
int __max730x_probe(struct max7301 *ts)
{
struct device *dev = ts->dev;
struct max7301_platform_data *pdata;
int i, ret;
pdata = dev_get_platdata(dev);
mutex_init(&ts->lock);
dev_set_drvdata(dev, ts);
/* Power up the chip and disable IRQ output */
ts->write(dev, 0x04, 0x01);
if (pdata) {
ts->input_pullup_active = pdata->input_pullup_active;
ts->chip.base = pdata->base;
} else {
ts->chip.base = -1;
}
ts->chip.label = dev->driver->name;
ts->chip.direction_input = max7301_direction_input;
ts->chip.get = max7301_get;
ts->chip.direction_output = max7301_direction_output;
ts->chip.set = max7301_set;
ts->chip.ngpio = PIN_NUMBER;
ts->chip.can_sleep = true;
ts->chip.parent = dev;
ts->chip.owner = THIS_MODULE;
/*
* initialize pullups according to platform data and cache the
* register values for later use.
*/
for (i = 1; i < 8; i++) {
int j;
/*
* initialize port_config with "0xAA", which means
* input with internal pullup disabled. This is needed
* to avoid writing zeros (in the inner for loop),
* which is not allowed according to the datasheet.
*/
ts->port_config[i] = 0xAA;
for (j = 0; j < 4; j++) {
int offset = (i - 1) * 4 + j;
ret = max7301_direction_input(&ts->chip, offset);
if (ret)
goto exit_destroy;
}
}
ret = gpiochip_add_data(&ts->chip, ts);
if (!ret)
return ret;
exit_destroy:
mutex_destroy(&ts->lock);
return ret;
}
EXPORT_SYMBOL_GPL(__max730x_probe);
void __max730x_remove(struct device *dev)
{
struct max7301 *ts = dev_get_drvdata(dev);
/* Power down the chip and disable IRQ output */
ts->write(dev, 0x04, 0x00);
gpiochip_remove(&ts->chip);
mutex_destroy(&ts->lock);
}
EXPORT_SYMBOL_GPL(__max730x_remove);
MODULE_AUTHOR("Juergen Beisert, Wolfram Sang");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MAX730x GPIO-Expanders, generic parts");
| linux-master | drivers/gpio/gpio-max730x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
*
* GPIO driver for Altera Arria10 MAX5 System Resource Chip
*
* Adapted from gpio-tps65910.c
*/
#include <linux/gpio/driver.h>
#include <linux/mfd/altera-a10sr.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/property.h>
/**
* struct altr_a10sr_gpio - Altera Max5 GPIO device private data structure
* @gp: : instance of the gpio_chip
* @regmap: the regmap from the parent device.
*/
struct altr_a10sr_gpio {
struct gpio_chip gp;
struct regmap *regmap;
};
static int altr_a10sr_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct altr_a10sr_gpio *gpio = gpiochip_get_data(chip);
int ret, val;
ret = regmap_read(gpio->regmap, ALTR_A10SR_PBDSW_REG, &val);
if (ret < 0)
return ret;
return !!(val & BIT(offset - ALTR_A10SR_LED_VALID_SHIFT));
}
static void altr_a10sr_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct altr_a10sr_gpio *gpio = gpiochip_get_data(chip);
regmap_update_bits(gpio->regmap, ALTR_A10SR_LED_REG,
BIT(ALTR_A10SR_LED_VALID_SHIFT + offset),
value ? BIT(ALTR_A10SR_LED_VALID_SHIFT + offset)
: 0);
}
static int altr_a10sr_gpio_direction_input(struct gpio_chip *gc,
unsigned int nr)
{
if (nr < (ALTR_A10SR_IN_VALID_RANGE_LO - ALTR_A10SR_LED_VALID_SHIFT))
return -EINVAL;
return 0;
}
static int altr_a10sr_gpio_direction_output(struct gpio_chip *gc,
unsigned int nr, int value)
{
if (nr > (ALTR_A10SR_OUT_VALID_RANGE_HI - ALTR_A10SR_LED_VALID_SHIFT))
return -EINVAL;
altr_a10sr_gpio_set(gc, nr, value);
return 0;
}
static const struct gpio_chip altr_a10sr_gc = {
.label = "altr_a10sr_gpio",
.owner = THIS_MODULE,
.get = altr_a10sr_gpio_get,
.set = altr_a10sr_gpio_set,
.direction_input = altr_a10sr_gpio_direction_input,
.direction_output = altr_a10sr_gpio_direction_output,
.can_sleep = true,
.ngpio = 12,
.base = -1,
};
static int altr_a10sr_gpio_probe(struct platform_device *pdev)
{
struct altr_a10sr_gpio *gpio;
struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
gpio->regmap = a10sr->regmap;
gpio->gp = altr_a10sr_gc;
gpio->gp.parent = pdev->dev.parent;
gpio->gp.fwnode = dev_fwnode(&pdev->dev);
return devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio);
}
static const struct of_device_id altr_a10sr_gpio_of_match[] = {
{ .compatible = "altr,a10sr-gpio" },
{ },
};
MODULE_DEVICE_TABLE(of, altr_a10sr_gpio_of_match);
static struct platform_driver altr_a10sr_gpio_driver = {
.probe = altr_a10sr_gpio_probe,
.driver = {
.name = "altr_a10sr_gpio",
.of_match_table = altr_a10sr_gpio_of_match,
},
};
module_platform_driver(altr_a10sr_gpio_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Thor Thayer <[email protected]>");
MODULE_DESCRIPTION("Altera Arria10 System Resource Chip GPIO");
| linux-master | drivers/gpio/gpio-altera-a10sr.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
*
* 2013 (c) Aeroflex Gaisler AB
*
* This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
* IP core library.
*
* Full documentation of the GRGPIO core can be found here:
* http://www.gaisler.com/products/grlib/grip.pdf
*
* See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
* information on open firmware properties.
*
* Contributors: Andreas Larsson <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/bitops.h>
#define GRGPIO_MAX_NGPIO 32
#define GRGPIO_DATA 0x00
#define GRGPIO_OUTPUT 0x04
#define GRGPIO_DIR 0x08
#define GRGPIO_IMASK 0x0c
#define GRGPIO_IPOL 0x10
#define GRGPIO_IEDGE 0x14
#define GRGPIO_BYPASS 0x18
#define GRGPIO_IMAP_BASE 0x20
/* Structure for an irq of the core - called an underlying irq */
struct grgpio_uirq {
u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
u8 uirq; /* Underlying irq of the gpio driver */
};
/*
* Structure for an irq of a gpio line handed out by this driver. The index is
* used to map to the corresponding underlying irq.
*/
struct grgpio_lirq {
s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
u8 irq; /* irq for the gpio line */
};
struct grgpio_priv {
struct gpio_chip gc;
void __iomem *regs;
struct device *dev;
u32 imask; /* irq mask shadow register */
/*
* The grgpio core can have multiple "underlying" irqs. The gpio lines
* can be mapped to any one or none of these underlying irqs
* independently of each other. This driver sets up an irq domain and
* hands out separate irqs to each gpio line
*/
struct irq_domain *domain;
/*
* This array contains information on each underlying irq, each
* irq of the grgpio core itself.
*/
struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
/*
* This array contains information for each gpio line on the irqs
* obtains from this driver. An index value of -1 for a certain gpio
* line indicates that the line has no irq. Otherwise the index connects
* the irq to the underlying irq by pointing into the uirqs array.
*/
struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
};
static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
int val)
{
struct gpio_chip *gc = &priv->gc;
if (val)
priv->imask |= BIT(offset);
else
priv->imask &= ~BIT(offset);
gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
}
static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct grgpio_priv *priv = gpiochip_get_data(gc);
if (offset >= gc->ngpio)
return -ENXIO;
if (priv->lirqs[offset].index < 0)
return -ENXIO;
return irq_create_mapping(priv->domain, offset);
}
/* -------------------- IRQ chip functions -------------------- */
static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
unsigned long flags;
u32 mask = BIT(d->hwirq);
u32 ipol;
u32 iedge;
u32 pol;
u32 edge;
switch (type) {
case IRQ_TYPE_LEVEL_LOW:
pol = 0;
edge = 0;
break;
case IRQ_TYPE_LEVEL_HIGH:
pol = mask;
edge = 0;
break;
case IRQ_TYPE_EDGE_FALLING:
pol = 0;
edge = mask;
break;
case IRQ_TYPE_EDGE_RISING:
pol = mask;
edge = mask;
break;
default:
return -EINVAL;
}
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
return 0;
}
static void grgpio_irq_mask(struct irq_data *d)
{
struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
int offset = d->hwirq;
unsigned long flags;
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
grgpio_set_imask(priv, offset, 0);
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
}
static void grgpio_irq_unmask(struct irq_data *d)
{
struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
int offset = d->hwirq;
unsigned long flags;
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
grgpio_set_imask(priv, offset, 1);
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
}
static struct irq_chip grgpio_irq_chip = {
.name = "grgpio",
.irq_mask = grgpio_irq_mask,
.irq_unmask = grgpio_irq_unmask,
.irq_set_type = grgpio_irq_set_type,
};
static irqreturn_t grgpio_irq_handler(int irq, void *dev)
{
struct grgpio_priv *priv = dev;
int ngpio = priv->gc.ngpio;
unsigned long flags;
int i;
int match = 0;
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
/*
* For each gpio line, call its interrupt handler if it its underlying
* irq matches the current irq that is handled.
*/
for (i = 0; i < ngpio; i++) {
struct grgpio_lirq *lirq = &priv->lirqs[i];
if (priv->imask & BIT(i) && lirq->index >= 0 &&
priv->uirqs[lirq->index].uirq == irq) {
generic_handle_irq(lirq->irq);
match = 1;
}
}
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
if (!match)
dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
return IRQ_HANDLED;
}
/*
* This function will be called as a consequence of the call to
* irq_create_mapping in grgpio_to_irq
*/
static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
struct grgpio_priv *priv = d->host_data;
struct grgpio_lirq *lirq;
struct grgpio_uirq *uirq;
unsigned long flags;
int offset = hwirq;
int ret = 0;
if (!priv)
return -EINVAL;
lirq = &priv->lirqs[offset];
if (lirq->index < 0)
return -EINVAL;
dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
irq, offset);
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
/* Request underlying irq if not already requested */
lirq->irq = irq;
uirq = &priv->uirqs[lirq->index];
if (uirq->refcnt == 0) {
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
dev_name(priv->dev), priv);
if (ret) {
dev_err(priv->dev,
"Could not request underlying irq %d\n",
uirq->uirq);
return ret;
}
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
}
uirq->refcnt++;
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
/* Setup irq */
irq_set_chip_data(irq, priv);
irq_set_chip_and_handler(irq, &grgpio_irq_chip,
handle_simple_irq);
irq_set_noprobe(irq);
return ret;
}
static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
{
struct grgpio_priv *priv = d->host_data;
int index;
struct grgpio_lirq *lirq;
struct grgpio_uirq *uirq;
unsigned long flags;
int ngpio = priv->gc.ngpio;
int i;
irq_set_chip_and_handler(irq, NULL, NULL);
irq_set_chip_data(irq, NULL);
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
/* Free underlying irq if last user unmapped */
index = -1;
for (i = 0; i < ngpio; i++) {
lirq = &priv->lirqs[i];
if (lirq->irq == irq) {
grgpio_set_imask(priv, i, 0);
lirq->irq = 0;
index = lirq->index;
break;
}
}
WARN_ON(index < 0);
if (index >= 0) {
uirq = &priv->uirqs[lirq->index];
uirq->refcnt--;
if (uirq->refcnt == 0) {
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
free_irq(uirq->uirq, priv);
return;
}
}
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
}
static const struct irq_domain_ops grgpio_irq_domain_ops = {
.map = grgpio_irq_map,
.unmap = grgpio_irq_unmap,
};
/* ------------------------------------------------------------ */
static int grgpio_probe(struct platform_device *ofdev)
{
struct device_node *np = ofdev->dev.of_node;
void __iomem *regs;
struct gpio_chip *gc;
struct grgpio_priv *priv;
int err;
u32 prop;
s32 *irqmap;
int size;
int i;
priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
regs = devm_platform_ioremap_resource(ofdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
gc = &priv->gc;
err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
BGPIOF_BIG_ENDIAN_BYTE_ORDER);
if (err) {
dev_err(&ofdev->dev, "bgpio_init() failed\n");
return err;
}
priv->regs = regs;
priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
priv->dev = &ofdev->dev;
gc->owner = THIS_MODULE;
gc->to_irq = grgpio_to_irq;
gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
gc->base = -1;
err = of_property_read_u32(np, "nbits", &prop);
if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
gc->ngpio = GRGPIO_MAX_NGPIO;
dev_dbg(&ofdev->dev,
"No or invalid nbits property: assume %d\n", gc->ngpio);
} else {
gc->ngpio = prop;
}
/*
* The irqmap contains the index values indicating which underlying irq,
* if anyone, is connected to that line
*/
irqmap = (s32 *)of_get_property(np, "irqmap", &size);
if (irqmap) {
if (size < gc->ngpio) {
dev_err(&ofdev->dev,
"irqmap shorter than ngpio (%d < %d)\n",
size, gc->ngpio);
return -EINVAL;
}
priv->domain = irq_domain_add_linear(np, gc->ngpio,
&grgpio_irq_domain_ops,
priv);
if (!priv->domain) {
dev_err(&ofdev->dev, "Could not add irq domain\n");
return -EINVAL;
}
for (i = 0; i < gc->ngpio; i++) {
struct grgpio_lirq *lirq;
int ret;
lirq = &priv->lirqs[i];
lirq->index = irqmap[i];
if (lirq->index < 0)
continue;
ret = platform_get_irq(ofdev, lirq->index);
if (ret <= 0) {
/*
* Continue without irq functionality for that
* gpio line
*/
continue;
}
priv->uirqs[lirq->index].uirq = ret;
}
}
platform_set_drvdata(ofdev, priv);
err = gpiochip_add_data(gc, priv);
if (err) {
dev_err(&ofdev->dev, "Could not add gpiochip\n");
if (priv->domain)
irq_domain_remove(priv->domain);
return err;
}
dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
return 0;
}
static int grgpio_remove(struct platform_device *ofdev)
{
struct grgpio_priv *priv = platform_get_drvdata(ofdev);
gpiochip_remove(&priv->gc);
if (priv->domain)
irq_domain_remove(priv->domain);
return 0;
}
static const struct of_device_id grgpio_match[] = {
{.name = "GAISLER_GPIO"},
{.name = "01_01a"},
{},
};
MODULE_DEVICE_TABLE(of, grgpio_match);
static struct platform_driver grgpio_driver = {
.driver = {
.name = "grgpio",
.of_match_table = grgpio_match,
},
.probe = grgpio_probe,
.remove = grgpio_remove,
};
module_platform_driver(grgpio_driver);
MODULE_AUTHOR("Aeroflex Gaisler AB.");
MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-grgpio.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2018 ROHM Semiconductors
#include <linux/gpio/driver.h>
#include <linux/mfd/rohm-bd71828.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define GPIO_OUT_REG(off) (BD71828_REG_GPIO_CTRL1 + (off))
#define HALL_GPIO_OFFSET 3
struct bd71828_gpio {
struct regmap *regmap;
struct device *dev;
struct gpio_chip gpio;
};
static void bd71828_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
int ret;
struct bd71828_gpio *bdgpio = gpiochip_get_data(chip);
u8 val = (value) ? BD71828_GPIO_OUT_HI : BD71828_GPIO_OUT_LO;
/*
* The HALL input pin can only be used as input. If this is the pin
* we are dealing with - then we are done
*/
if (offset == HALL_GPIO_OFFSET)
return;
ret = regmap_update_bits(bdgpio->regmap, GPIO_OUT_REG(offset),
BD71828_GPIO_OUT_MASK, val);
if (ret)
dev_err(bdgpio->dev, "Could not set gpio to %d\n", value);
}
static int bd71828_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
int ret;
unsigned int val;
struct bd71828_gpio *bdgpio = gpiochip_get_data(chip);
if (offset == HALL_GPIO_OFFSET)
ret = regmap_read(bdgpio->regmap, BD71828_REG_IO_STAT,
&val);
else
ret = regmap_read(bdgpio->regmap, GPIO_OUT_REG(offset),
&val);
if (!ret)
ret = (val & BD71828_GPIO_OUT_MASK);
return ret;
}
static int bd71828_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
struct bd71828_gpio *bdgpio = gpiochip_get_data(chip);
if (offset == HALL_GPIO_OFFSET)
return -ENOTSUPP;
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
return regmap_update_bits(bdgpio->regmap,
GPIO_OUT_REG(offset),
BD71828_GPIO_DRIVE_MASK,
BD71828_GPIO_OPEN_DRAIN);
case PIN_CONFIG_DRIVE_PUSH_PULL:
return regmap_update_bits(bdgpio->regmap,
GPIO_OUT_REG(offset),
BD71828_GPIO_DRIVE_MASK,
BD71828_GPIO_PUSH_PULL);
default:
break;
}
return -ENOTSUPP;
}
static int bd71828_get_direction(struct gpio_chip *chip, unsigned int offset)
{
/*
* Pin usage is selected by OTP data. We can't read it runtime. Hence
* we trust that if the pin is not excluded by "gpio-reserved-ranges"
* the OTP configuration is set to OUT. (Other pins but HALL input pin
* on BD71828 can't really be used for general purpose input - input
* states are used for specific cases like regulator control or
* PMIC_ON_REQ.
*/
if (offset == HALL_GPIO_OFFSET)
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static int bd71828_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct bd71828_gpio *bdgpio;
bdgpio = devm_kzalloc(dev, sizeof(*bdgpio), GFP_KERNEL);
if (!bdgpio)
return -ENOMEM;
bdgpio->dev = dev;
bdgpio->gpio.parent = dev->parent;
bdgpio->gpio.label = "bd71828-gpio";
bdgpio->gpio.owner = THIS_MODULE;
bdgpio->gpio.get_direction = bd71828_get_direction;
bdgpio->gpio.set_config = bd71828_gpio_set_config;
bdgpio->gpio.can_sleep = true;
bdgpio->gpio.get = bd71828_gpio_get;
bdgpio->gpio.set = bd71828_gpio_set;
bdgpio->gpio.base = -1;
/*
* See if we need some implementation to mark some PINs as
* not controllable based on DT info or if core can handle
* "gpio-reserved-ranges" and exclude them from control
*/
bdgpio->gpio.ngpio = 4;
bdgpio->regmap = dev_get_regmap(dev->parent, NULL);
if (!bdgpio->regmap)
return -ENODEV;
return devm_gpiochip_add_data(dev, &bdgpio->gpio, bdgpio);
}
static struct platform_driver bd71828_gpio = {
.driver = {
.name = "bd71828-gpio"
},
.probe = bd71828_probe,
};
module_platform_driver(bd71828_gpio);
MODULE_AUTHOR("Matti Vaittinen <[email protected]>");
MODULE_DESCRIPTION("BD71828 voltage regulator driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:bd71828-gpio");
| linux-master | drivers/gpio/gpio-bd71828.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Copyright (C) 2012 John Crispin <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/legacy-of-mm-gpiochip.h>
#include <linux/of.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <lantiq_soc.h>
/*
* By attaching hardware latches to the EBU it is possible to create output
* only gpios. This driver configures a special memory address, which when
* written to outputs 16 bit to the latches.
*/
#define LTQ_EBU_BUSCON 0x1e7ff /* 16 bit access, slowest timing */
#define LTQ_EBU_WP 0x80000000 /* write protect bit */
struct ltq_mm {
struct of_mm_gpio_chip mmchip;
u16 shadow; /* shadow the latches state */
};
/**
* ltq_mm_apply() - write the shadow value to the ebu address.
* @chip: Pointer to our private data structure.
*
* Write the shadow value to the EBU to set the gpios. We need to set the
* global EBU lock to make sure that PCI/MTD don't break.
*/
static void ltq_mm_apply(struct ltq_mm *chip)
{
unsigned long flags;
spin_lock_irqsave(&ebu_lock, flags);
ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1);
__raw_writew(chip->shadow, chip->mmchip.regs);
ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
spin_unlock_irqrestore(&ebu_lock, flags);
}
/**
* ltq_mm_set() - gpio_chip->set - set gpios.
* @gc: Pointer to gpio_chip device structure.
* @gpio: GPIO signal number.
* @val: Value to be written to specified signal.
*
* Set the shadow value and call ltq_mm_apply.
*/
static void ltq_mm_set(struct gpio_chip *gc, unsigned offset, int value)
{
struct ltq_mm *chip = gpiochip_get_data(gc);
if (value)
chip->shadow |= (1 << offset);
else
chip->shadow &= ~(1 << offset);
ltq_mm_apply(chip);
}
/**
* ltq_mm_dir_out() - gpio_chip->dir_out - set gpio direction.
* @gc: Pointer to gpio_chip device structure.
* @gpio: GPIO signal number.
* @val: Value to be written to specified signal.
*
* Same as ltq_mm_set, always returns 0.
*/
static int ltq_mm_dir_out(struct gpio_chip *gc, unsigned offset, int value)
{
ltq_mm_set(gc, offset, value);
return 0;
}
/**
* ltq_mm_save_regs() - Set initial values of GPIO pins
* @mm_gc: pointer to memory mapped GPIO chip structure
*/
static void ltq_mm_save_regs(struct of_mm_gpio_chip *mm_gc)
{
struct ltq_mm *chip =
container_of(mm_gc, struct ltq_mm, mmchip);
/* tell the ebu controller which memory address we will be using */
ltq_ebu_w32(CPHYSADDR(chip->mmchip.regs) | 0x1, LTQ_EBU_ADDRSEL1);
ltq_mm_apply(chip);
}
static int ltq_mm_probe(struct platform_device *pdev)
{
struct ltq_mm *chip;
u32 shadow;
chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
platform_set_drvdata(pdev, chip);
chip->mmchip.gc.ngpio = 16;
chip->mmchip.gc.direction_output = ltq_mm_dir_out;
chip->mmchip.gc.set = ltq_mm_set;
chip->mmchip.save_regs = ltq_mm_save_regs;
/* store the shadow value if one was passed by the devicetree */
if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
chip->shadow = shadow;
return of_mm_gpiochip_add_data(pdev->dev.of_node, &chip->mmchip, chip);
}
static int ltq_mm_remove(struct platform_device *pdev)
{
struct ltq_mm *chip = platform_get_drvdata(pdev);
of_mm_gpiochip_remove(&chip->mmchip);
return 0;
}
static const struct of_device_id ltq_mm_match[] = {
{ .compatible = "lantiq,gpio-mm" },
{},
};
MODULE_DEVICE_TABLE(of, ltq_mm_match);
static struct platform_driver ltq_mm_driver = {
.probe = ltq_mm_probe,
.remove = ltq_mm_remove,
.driver = {
.name = "gpio-mm-ltq",
.of_match_table = ltq_mm_match,
},
};
static int __init ltq_mm_init(void)
{
return platform_driver_register(<q_mm_driver);
}
subsys_initcall(ltq_mm_init);
static void __exit ltq_mm_exit(void)
{
platform_driver_unregister(<q_mm_driver);
}
module_exit(ltq_mm_exit);
| linux-master | drivers/gpio/gpio-mm-lantiq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
*
* Copyright (C) 2008 Peter Korsgaard <[email protected]>
* Copyright (C) 2016 Freescale Semiconductor Inc.
*/
#include <linux/acpi.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/property.h>
#include <linux/mod_devicetable.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#define MPC8XXX_GPIO_PINS 32
#define GPIO_DIR 0x00
#define GPIO_ODR 0x04
#define GPIO_DAT 0x08
#define GPIO_IER 0x0c
#define GPIO_IMR 0x10
#define GPIO_ICR 0x14
#define GPIO_ICR2 0x18
#define GPIO_IBE 0x18
struct mpc8xxx_gpio_chip {
struct gpio_chip gc;
void __iomem *regs;
raw_spinlock_t lock;
int (*direction_output)(struct gpio_chip *chip,
unsigned offset, int value);
struct irq_domain *irq;
int irqn;
};
/*
* This hardware has a big endian bit assignment such that GPIO line 0 is
* connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
* This inline helper give the right bitmask for a certain line.
*/
static inline u32 mpc_pin2mask(unsigned int offset)
{
return BIT(31 - offset);
}
/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
* defined as output cannot be determined by reading GPDAT register,
* so we use shadow data register instead. The status of input pins
* is determined by reading GPDAT register.
*/
static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
u32 val;
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
u32 out_mask, out_shadow;
out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
out_shadow = gc->bgpio_data & out_mask;
return !!((val | out_shadow) & mpc_pin2mask(gpio));
}
static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
unsigned int gpio, int val)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
/* GPIO 28..31 are input only on MPC5121 */
if (gpio >= 28)
return -EINVAL;
return mpc8xxx_gc->direction_output(gc, gpio, val);
}
static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
unsigned int gpio, int val)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
/* GPIO 0..3 are input only on MPC5125 */
if (gpio <= 3)
return -EINVAL;
return mpc8xxx_gc->direction_output(gc, gpio, val);
}
static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
return irq_create_mapping(mpc8xxx_gc->irq, offset);
else
return -ENXIO;
}
static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
struct gpio_chip *gc = &mpc8xxx_gc->gc;
unsigned long mask;
int i;
mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
for_each_set_bit(i, &mask, 32)
generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
return IRQ_HANDLED;
}
static void mpc8xxx_irq_unmask(struct irq_data *d)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
struct gpio_chip *gc = &mpc8xxx_gc->gc;
unsigned long flags;
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
| mpc_pin2mask(irqd_to_hwirq(d)));
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}
static void mpc8xxx_irq_mask(struct irq_data *d)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
struct gpio_chip *gc = &mpc8xxx_gc->gc;
unsigned long flags;
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
& ~mpc_pin2mask(irqd_to_hwirq(d)));
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}
static void mpc8xxx_irq_ack(struct irq_data *d)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
struct gpio_chip *gc = &mpc8xxx_gc->gc;
gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
mpc_pin2mask(irqd_to_hwirq(d)));
}
static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
struct gpio_chip *gc = &mpc8xxx_gc->gc;
unsigned long flags;
switch (flow_type) {
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_LEVEL_LOW:
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
| mpc_pin2mask(irqd_to_hwirq(d)));
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
break;
case IRQ_TYPE_EDGE_BOTH:
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
& ~mpc_pin2mask(irqd_to_hwirq(d)));
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
break;
default:
return -EINVAL;
}
return 0;
}
static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
struct gpio_chip *gc = &mpc8xxx_gc->gc;
unsigned long gpio = irqd_to_hwirq(d);
void __iomem *reg;
unsigned int shift;
unsigned long flags;
if (gpio < 16) {
reg = mpc8xxx_gc->regs + GPIO_ICR;
shift = (15 - gpio) * 2;
} else {
reg = mpc8xxx_gc->regs + GPIO_ICR2;
shift = (15 - (gpio % 16)) * 2;
}
switch (flow_type) {
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_LEVEL_LOW:
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
| (2 << shift));
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
break;
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_LEVEL_HIGH:
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
| (1 << shift));
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
break;
case IRQ_TYPE_EDGE_BOTH:
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
break;
default:
return -EINVAL;
}
return 0;
}
static struct irq_chip mpc8xxx_irq_chip = {
.name = "mpc8xxx-gpio",
.irq_unmask = mpc8xxx_irq_unmask,
.irq_mask = mpc8xxx_irq_mask,
.irq_ack = mpc8xxx_irq_ack,
/* this might get overwritten in mpc8xxx_probe() */
.irq_set_type = mpc8xxx_irq_set_type,
};
static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
irq_hw_number_t hwirq)
{
irq_set_chip_data(irq, h->host_data);
irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
return 0;
}
static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
.map = mpc8xxx_gpio_irq_map,
.xlate = irq_domain_xlate_twocell,
};
struct mpc8xxx_gpio_devtype {
int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
int (*gpio_get)(struct gpio_chip *, unsigned int);
int (*irq_set_type)(struct irq_data *, unsigned int);
};
static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
.gpio_dir_out = mpc5121_gpio_dir_out,
.irq_set_type = mpc512x_irq_set_type,
};
static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
.gpio_dir_out = mpc5125_gpio_dir_out,
.irq_set_type = mpc512x_irq_set_type,
};
static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
.gpio_get = mpc8572_gpio_get,
};
static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
.irq_set_type = mpc8xxx_irq_set_type,
};
static const struct of_device_id mpc8xxx_gpio_ids[] = {
{ .compatible = "fsl,mpc8349-gpio", },
{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
{ .compatible = "fsl,mpc8610-gpio", },
{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
{ .compatible = "fsl,pq3-gpio", },
{ .compatible = "fsl,ls1028a-gpio", },
{ .compatible = "fsl,ls1088a-gpio", },
{ .compatible = "fsl,qoriq-gpio", },
{}
};
static int mpc8xxx_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct mpc8xxx_gpio_chip *mpc8xxx_gc;
struct gpio_chip *gc;
const struct mpc8xxx_gpio_devtype *devtype = NULL;
struct fwnode_handle *fwnode;
int ret;
mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
if (!mpc8xxx_gc)
return -ENOMEM;
platform_set_drvdata(pdev, mpc8xxx_gc);
raw_spin_lock_init(&mpc8xxx_gc->lock);
mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(mpc8xxx_gc->regs))
return PTR_ERR(mpc8xxx_gc->regs);
gc = &mpc8xxx_gc->gc;
gc->parent = &pdev->dev;
if (device_property_read_bool(&pdev->dev, "little-endian")) {
ret = bgpio_init(gc, &pdev->dev, 4,
mpc8xxx_gc->regs + GPIO_DAT,
NULL, NULL,
mpc8xxx_gc->regs + GPIO_DIR, NULL,
BGPIOF_BIG_ENDIAN);
if (ret)
return ret;
dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
} else {
ret = bgpio_init(gc, &pdev->dev, 4,
mpc8xxx_gc->regs + GPIO_DAT,
NULL, NULL,
mpc8xxx_gc->regs + GPIO_DIR, NULL,
BGPIOF_BIG_ENDIAN
| BGPIOF_BIG_ENDIAN_BYTE_ORDER);
if (ret)
return ret;
dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
}
mpc8xxx_gc->direction_output = gc->direction_output;
devtype = device_get_match_data(&pdev->dev);
if (!devtype)
devtype = &mpc8xxx_gpio_devtype_default;
/*
* It's assumed that only a single type of gpio controller is available
* on the current machine, so overwriting global data is fine.
*/
if (devtype->irq_set_type)
mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
if (devtype->gpio_dir_out)
gc->direction_output = devtype->gpio_dir_out;
if (devtype->gpio_get)
gc->get = devtype->gpio_get;
gc->to_irq = mpc8xxx_gpio_to_irq;
/*
* The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
* the input enable of each individual GPIO port. When an individual
* GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
* associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
* the port value to the GPIO Data Register.
*/
fwnode = dev_fwnode(&pdev->dev);
if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
is_acpi_node(fwnode)) {
gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
/* Also, latch state of GPIOs configured as output by bootloader. */
gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) &
gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
}
ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
if (ret) {
dev_err(&pdev->dev,
"GPIO chip registration failed with status %d\n", ret);
return ret;
}
mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
if (mpc8xxx_gc->irqn < 0)
return mpc8xxx_gc->irqn;
mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
MPC8XXX_GPIO_PINS,
&mpc8xxx_gpio_irq_ops,
mpc8xxx_gc);
if (!mpc8xxx_gc->irq)
return 0;
/* ack and mask all irqs */
gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
mpc8xxx_gpio_irq_cascade,
IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
mpc8xxx_gc);
if (ret) {
dev_err(&pdev->dev,
"failed to devm_request_irq(%d), ret = %d\n",
mpc8xxx_gc->irqn, ret);
goto err;
}
return 0;
err:
irq_domain_remove(mpc8xxx_gc->irq);
return ret;
}
static int mpc8xxx_remove(struct platform_device *pdev)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
if (mpc8xxx_gc->irq) {
irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
irq_domain_remove(mpc8xxx_gc->irq);
}
return 0;
}
#ifdef CONFIG_ACPI
static const struct acpi_device_id gpio_acpi_ids[] = {
{"NXP0031",},
{ }
};
MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
#endif
static struct platform_driver mpc8xxx_plat_driver = {
.probe = mpc8xxx_probe,
.remove = mpc8xxx_remove,
.driver = {
.name = "gpio-mpc8xxx",
.of_match_table = mpc8xxx_gpio_ids,
.acpi_match_table = ACPI_PTR(gpio_acpi_ids),
},
};
static int __init mpc8xxx_init(void)
{
return platform_driver_register(&mpc8xxx_plat_driver);
}
arch_initcall(mpc8xxx_init);
| linux-master | drivers/gpio/gpio-mpc8xxx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Emma Mobile GPIO Support - GIO
*
* Copyright (C) 2012 Magnus Damm
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
struct em_gio_priv {
void __iomem *base0;
void __iomem *base1;
spinlock_t sense_lock;
struct platform_device *pdev;
struct gpio_chip gpio_chip;
struct irq_chip irq_chip;
struct irq_domain *irq_domain;
};
#define GIO_E1 0x00
#define GIO_E0 0x04
#define GIO_EM 0x04
#define GIO_OL 0x08
#define GIO_OH 0x0c
#define GIO_I 0x10
#define GIO_IIA 0x14
#define GIO_IEN 0x18
#define GIO_IDS 0x1c
#define GIO_IIM 0x1c
#define GIO_RAW 0x20
#define GIO_MST 0x24
#define GIO_IIR 0x28
#define GIO_IDT0 0x40
#define GIO_IDT1 0x44
#define GIO_IDT2 0x48
#define GIO_IDT3 0x4c
#define GIO_RAWBL 0x50
#define GIO_RAWBH 0x54
#define GIO_IRBL 0x58
#define GIO_IRBH 0x5c
#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
{
if (offs < GIO_IDT0)
return ioread32(p->base0 + offs);
else
return ioread32(p->base1 + (offs - GIO_IDT0));
}
static inline void em_gio_write(struct em_gio_priv *p, int offs,
unsigned long value)
{
if (offs < GIO_IDT0)
iowrite32(value, p->base0 + offs);
else
iowrite32(value, p->base1 + (offs - GIO_IDT0));
}
static void em_gio_irq_disable(struct irq_data *d)
{
struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
}
static void em_gio_irq_enable(struct irq_data *d)
{
struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
}
static int em_gio_irq_reqres(struct irq_data *d)
{
struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
int ret;
ret = gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
if (ret) {
dev_err(p->gpio_chip.parent,
"unable to lock HW IRQ %lu for IRQ\n",
irqd_to_hwirq(d));
return ret;
}
return 0;
}
static void em_gio_irq_relres(struct irq_data *d)
{
struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
}
#define GIO_ASYNC(x) (x + 8)
static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
[IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
[IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
[IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
[IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
[IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
};
static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
{
unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
unsigned int reg, offset, shift;
unsigned long flags;
unsigned long tmp;
if (!value)
return -EINVAL;
offset = irqd_to_hwirq(d);
pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
/* 8 x 4 bit fields in 4 IDT registers */
reg = GIO_IDT(offset >> 3);
shift = (offset & 0x07) << 4;
spin_lock_irqsave(&p->sense_lock, flags);
/* disable the interrupt in IIA */
tmp = em_gio_read(p, GIO_IIA);
tmp &= ~BIT(offset);
em_gio_write(p, GIO_IIA, tmp);
/* change the sense setting in IDT */
tmp = em_gio_read(p, reg);
tmp &= ~(0xf << shift);
tmp |= value << shift;
em_gio_write(p, reg, tmp);
/* clear pending interrupts */
em_gio_write(p, GIO_IIR, BIT(offset));
/* enable the interrupt in IIA */
tmp = em_gio_read(p, GIO_IIA);
tmp |= BIT(offset);
em_gio_write(p, GIO_IIA, tmp);
spin_unlock_irqrestore(&p->sense_lock, flags);
return 0;
}
static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
{
struct em_gio_priv *p = dev_id;
unsigned long pending;
unsigned int offset, irqs_handled = 0;
while ((pending = em_gio_read(p, GIO_MST))) {
offset = __ffs(pending);
em_gio_write(p, GIO_IIR, BIT(offset));
generic_handle_domain_irq(p->irq_domain, offset);
irqs_handled++;
}
return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}
static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
{
return gpiochip_get_data(chip);
}
static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
{
em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
return 0;
}
static int em_gio_get(struct gpio_chip *chip, unsigned offset)
{
return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
}
static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
unsigned shift, int value)
{
/* upper 16 bits contains mask and lower 16 actual value */
em_gio_write(gpio_to_priv(chip), reg,
(BIT(shift + 16)) | (value << shift));
}
static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
{
/* output is split into two registers */
if (offset < 16)
__em_gio_set(chip, GIO_OL, offset, value);
else
__em_gio_set(chip, GIO_OH, offset - 16, value);
}
static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
/* write GPIO value to output before selecting output mode of pin */
em_gio_set(chip, offset, value);
em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
return 0;
}
static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
{
return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
}
static int em_gio_request(struct gpio_chip *chip, unsigned offset)
{
return pinctrl_gpio_request(chip->base + offset);
}
static void em_gio_free(struct gpio_chip *chip, unsigned offset)
{
pinctrl_gpio_free(chip->base + offset);
/* Set the GPIO as an input to ensure that the next GPIO request won't
* drive the GPIO pin as an output.
*/
em_gio_direction_input(chip, offset);
}
static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
irq_hw_number_t hwirq)
{
struct em_gio_priv *p = h->host_data;
pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
irq_set_chip_data(irq, h->host_data);
irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
return 0;
}
static const struct irq_domain_ops em_gio_irq_domain_ops = {
.map = em_gio_irq_domain_map,
.xlate = irq_domain_xlate_twocell,
};
static void em_gio_irq_domain_remove(void *data)
{
struct irq_domain *domain = data;
irq_domain_remove(domain);
}
static int em_gio_probe(struct platform_device *pdev)
{
struct em_gio_priv *p;
struct gpio_chip *gpio_chip;
struct irq_chip *irq_chip;
struct device *dev = &pdev->dev;
const char *name = dev_name(dev);
unsigned int ngpios;
int irq[2], ret;
p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
if (!p)
return -ENOMEM;
p->pdev = pdev;
platform_set_drvdata(pdev, p);
spin_lock_init(&p->sense_lock);
irq[0] = platform_get_irq(pdev, 0);
if (irq[0] < 0)
return irq[0];
irq[1] = platform_get_irq(pdev, 1);
if (irq[1] < 0)
return irq[1];
p->base0 = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(p->base0))
return PTR_ERR(p->base0);
p->base1 = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(p->base1))
return PTR_ERR(p->base1);
if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
dev_err(dev, "Missing ngpios OF property\n");
return -EINVAL;
}
gpio_chip = &p->gpio_chip;
gpio_chip->direction_input = em_gio_direction_input;
gpio_chip->get = em_gio_get;
gpio_chip->direction_output = em_gio_direction_output;
gpio_chip->set = em_gio_set;
gpio_chip->to_irq = em_gio_to_irq;
gpio_chip->request = em_gio_request;
gpio_chip->free = em_gio_free;
gpio_chip->label = name;
gpio_chip->parent = dev;
gpio_chip->owner = THIS_MODULE;
gpio_chip->base = -1;
gpio_chip->ngpio = ngpios;
irq_chip = &p->irq_chip;
irq_chip->name = "gpio-em";
irq_chip->irq_mask = em_gio_irq_disable;
irq_chip->irq_unmask = em_gio_irq_enable;
irq_chip->irq_set_type = em_gio_irq_set_type;
irq_chip->irq_request_resources = em_gio_irq_reqres;
irq_chip->irq_release_resources = em_gio_irq_relres;
irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
p->irq_domain = irq_domain_add_simple(dev->of_node, ngpios, 0,
&em_gio_irq_domain_ops, p);
if (!p->irq_domain) {
dev_err(dev, "cannot initialize irq domain\n");
return -ENXIO;
}
ret = devm_add_action_or_reset(dev, em_gio_irq_domain_remove,
p->irq_domain);
if (ret)
return ret;
if (devm_request_irq(dev, irq[0], em_gio_irq_handler, 0, name, p)) {
dev_err(dev, "failed to request low IRQ\n");
return -ENOENT;
}
if (devm_request_irq(dev, irq[1], em_gio_irq_handler, 0, name, p)) {
dev_err(dev, "failed to request high IRQ\n");
return -ENOENT;
}
ret = devm_gpiochip_add_data(dev, gpio_chip, p);
if (ret) {
dev_err(dev, "failed to add GPIO controller\n");
return ret;
}
return 0;
}
static const struct of_device_id em_gio_dt_ids[] = {
{ .compatible = "renesas,em-gio", },
{},
};
MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
static struct platform_driver em_gio_device_driver = {
.probe = em_gio_probe,
.driver = {
.name = "em_gio",
.of_match_table = em_gio_dt_ids,
}
};
static int __init em_gio_init(void)
{
return platform_driver_register(&em_gio_device_driver);
}
postcore_initcall(em_gio_init);
static void __exit em_gio_exit(void)
{
platform_driver_unregister(&em_gio_device_driver);
}
module_exit(em_gio_exit);
MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-em.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AMD CS5535/CS5536 GPIO driver
* Copyright (C) 2006 Advanced Micro Devices, Inc.
* Copyright (C) 2007-2009 Andres Salomon <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/cs5535.h>
#include <asm/msr.h>
#define DRV_NAME "cs5535-gpio"
/*
* Some GPIO pins
* 31-29,23 : reserved (always mask out)
* 28 : Power Button
* 26 : PME#
* 22-16 : LPC
* 14,15 : SMBus
* 9,8 : UART1
* 7 : PCI INTB
* 3,4 : UART2/DDC
* 2 : IDE_IRQ0
* 1 : AC_BEEP
* 0 : PCI INTA
*
* If a mask was not specified, allow all except
* reserved and Power Button
*/
#define GPIO_DEFAULT_MASK 0x0F7FFFFF
static ulong mask = GPIO_DEFAULT_MASK;
module_param_named(mask, mask, ulong, 0444);
MODULE_PARM_DESC(mask, "GPIO channel mask.");
/*
* FIXME: convert this singleton driver to use the state container
* design pattern, see Documentation/driver-api/driver-model/design-patterns.rst
*/
static struct cs5535_gpio_chip {
struct gpio_chip chip;
resource_size_t base;
struct platform_device *pdev;
spinlock_t lock;
} cs5535_gpio_chip;
/*
* The CS5535/CS5536 GPIOs support a number of extra features not defined
* by the gpio_chip API, so these are exported. For a full list of the
* registers, see include/linux/cs5535.h.
*/
static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
unsigned int reg)
{
unsigned long addr = chip->base + 0x80 + reg;
/*
* According to the CS5536 errata (#36), after suspend
* a write to the high bank GPIO register will clear all
* non-selected bits; the recommended workaround is a
* read-modify-write operation.
*
* Don't apply this errata to the edge status GPIOs, as writing
* to their lower bits will clear them.
*/
if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) {
if (val & 0xffff)
val |= (inl(addr) & 0xffff); /* ignore the high bits */
else
val |= (inl(addr) ^ (val >> 16));
}
outl(val, addr);
}
static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
unsigned int reg)
{
if (offset < 16)
/* low bank register */
outl(1 << offset, chip->base + reg);
else
/* high bank register */
errata_outl(chip, 1 << (offset - 16), reg);
}
void cs5535_gpio_set(unsigned offset, unsigned int reg)
{
struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
__cs5535_gpio_set(chip, offset, reg);
spin_unlock_irqrestore(&chip->lock, flags);
}
EXPORT_SYMBOL_GPL(cs5535_gpio_set);
static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
unsigned int reg)
{
if (offset < 16)
/* low bank register */
outl(1 << (offset + 16), chip->base + reg);
else
/* high bank register */
errata_outl(chip, 1 << offset, reg);
}
void cs5535_gpio_clear(unsigned offset, unsigned int reg)
{
struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
__cs5535_gpio_clear(chip, offset, reg);
spin_unlock_irqrestore(&chip->lock, flags);
}
EXPORT_SYMBOL_GPL(cs5535_gpio_clear);
int cs5535_gpio_isset(unsigned offset, unsigned int reg)
{
struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
unsigned long flags;
long val;
spin_lock_irqsave(&chip->lock, flags);
if (offset < 16)
/* low bank register */
val = inl(chip->base + reg);
else {
/* high bank register */
val = inl(chip->base + 0x80 + reg);
offset -= 16;
}
spin_unlock_irqrestore(&chip->lock, flags);
return (val & (1 << offset)) ? 1 : 0;
}
EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
int cs5535_gpio_set_irq(unsigned group, unsigned irq)
{
uint32_t lo, hi;
if (group > 7 || irq > 15)
return -EINVAL;
rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
lo &= ~(0xF << (group * 4));
lo |= (irq & 0xF) << (group * 4);
wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
return 0;
}
EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
void cs5535_gpio_setup_event(unsigned offset, int pair, int pme)
{
struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
uint32_t shift = (offset % 8) * 4;
unsigned long flags;
uint32_t val;
if (offset >= 24)
offset = GPIO_MAP_W;
else if (offset >= 16)
offset = GPIO_MAP_Z;
else if (offset >= 8)
offset = GPIO_MAP_Y;
else
offset = GPIO_MAP_X;
spin_lock_irqsave(&chip->lock, flags);
val = inl(chip->base + offset);
/* Clear whatever was there before */
val &= ~(0xF << shift);
/* Set the new value */
val |= ((pair & 7) << shift);
/* Set the PME bit if this is a PME event */
if (pme)
val |= (1 << (shift + 3));
outl(val, chip->base + offset);
spin_unlock_irqrestore(&chip->lock, flags);
}
EXPORT_SYMBOL_GPL(cs5535_gpio_setup_event);
/*
* Generic gpio_chip API support.
*/
static int chip_gpio_request(struct gpio_chip *c, unsigned offset)
{
struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
/* check if this pin is available */
if ((mask & (1 << offset)) == 0) {
dev_info(&chip->pdev->dev,
"pin %u is not available (check mask)\n", offset);
spin_unlock_irqrestore(&chip->lock, flags);
return -EINVAL;
}
/* disable output aux 1 & 2 on this pin */
__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX1);
__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX2);
/* disable input aux 1 on this pin */
__cs5535_gpio_clear(chip, offset, GPIO_INPUT_AUX1);
spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
static int chip_gpio_get(struct gpio_chip *chip, unsigned offset)
{
return cs5535_gpio_isset(offset, GPIO_READ_BACK);
}
static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
if (val)
cs5535_gpio_set(offset, GPIO_OUTPUT_VAL);
else
cs5535_gpio_clear(offset, GPIO_OUTPUT_VAL);
}
static int chip_direction_input(struct gpio_chip *c, unsigned offset)
{
struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
__cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_ENABLE);
spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
{
struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
__cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_ENABLE);
if (val)
__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_VAL);
else
__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_VAL);
spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
static const char * const cs5535_gpio_names[] = {
"GPIO0", "GPIO1", "GPIO2", "GPIO3",
"GPIO4", "GPIO5", "GPIO6", "GPIO7",
"GPIO8", "GPIO9", "GPIO10", "GPIO11",
"GPIO12", "GPIO13", "GPIO14", "GPIO15",
"GPIO16", "GPIO17", "GPIO18", "GPIO19",
"GPIO20", "GPIO21", "GPIO22", NULL,
"GPIO24", "GPIO25", "GPIO26", "GPIO27",
"GPIO28", NULL, NULL, NULL,
};
static struct cs5535_gpio_chip cs5535_gpio_chip = {
.chip = {
.owner = THIS_MODULE,
.label = DRV_NAME,
.base = 0,
.ngpio = 32,
.names = cs5535_gpio_names,
.request = chip_gpio_request,
.get = chip_gpio_get,
.set = chip_gpio_set,
.direction_input = chip_direction_input,
.direction_output = chip_direction_output,
},
};
static int cs5535_gpio_probe(struct platform_device *pdev)
{
struct resource *res;
int err = -EIO;
ulong mask_orig = mask;
/* There are two ways to get the GPIO base address; one is by
* fetching it from MSR_LBAR_GPIO, the other is by reading the
* PCI BAR info. The latter method is easier (especially across
* different architectures), so we'll stick with that for now. If
* it turns out to be unreliable in the face of crappy BIOSes, we
* can always go back to using MSRs.. */
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!res) {
dev_err(&pdev->dev, "can't fetch device resource info\n");
return err;
}
if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
pdev->name)) {
dev_err(&pdev->dev, "can't request region\n");
return err;
}
/* set up the driver-specific struct */
cs5535_gpio_chip.base = res->start;
cs5535_gpio_chip.pdev = pdev;
spin_lock_init(&cs5535_gpio_chip.lock);
dev_info(&pdev->dev, "reserved resource region %pR\n", res);
/* mask out reserved pins */
mask &= 0x1F7FFFFF;
/* do not allow pin 28, Power Button, as there's special handling
* in the PMC needed. (note 12, p. 48) */
mask &= ~(1 << 28);
if (mask_orig != mask)
dev_info(&pdev->dev, "mask changed from 0x%08lX to 0x%08lX\n",
mask_orig, mask);
/* finally, register with the generic GPIO API */
return devm_gpiochip_add_data(&pdev->dev, &cs5535_gpio_chip.chip,
&cs5535_gpio_chip);
}
static struct platform_driver cs5535_gpio_driver = {
.driver = {
.name = DRV_NAME,
},
.probe = cs5535_gpio_probe,
};
module_platform_driver(cs5535_gpio_driver);
MODULE_AUTHOR("Andres Salomon <[email protected]>");
MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | drivers/gpio/gpio-cs5535.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Support functions for OMAP GPIO
*
* Copyright (C) 2003-2005 Nokia Corporation
* Written by Juha Yrjölä <[email protected]>
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/seq_file.h>
#include <linux/syscore_ops.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/cpu_pm.h>
#include <linux/device.h>
#include <linux/pm_runtime.h>
#include <linux/pm.h>
#include <linux/of.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>
#include <linux/platform_data/gpio-omap.h>
#define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
struct gpio_regs {
u32 sysconfig;
u32 irqenable1;
u32 irqenable2;
u32 wake_en;
u32 ctrl;
u32 oe;
u32 leveldetect0;
u32 leveldetect1;
u32 risingdetect;
u32 fallingdetect;
u32 dataout;
u32 debounce;
u32 debounce_en;
};
struct gpio_bank {
void __iomem *base;
const struct omap_gpio_reg_offs *regs;
struct device *dev;
int irq;
u32 non_wakeup_gpios;
u32 enabled_non_wakeup_gpios;
struct gpio_regs context;
u32 saved_datain;
u32 level_mask;
u32 toggle_mask;
raw_spinlock_t lock;
raw_spinlock_t wa_lock;
struct gpio_chip chip;
struct clk *dbck;
struct notifier_block nb;
unsigned int is_suspended:1;
unsigned int needs_resume:1;
u32 mod_usage;
u32 irq_usage;
u32 dbck_enable_mask;
bool dbck_enabled;
bool is_mpuio;
bool dbck_flag;
bool loses_context;
bool context_valid;
int stride;
u32 width;
int context_loss_count;
void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
int (*get_context_loss_count)(struct device *dev);
};
#define GPIO_MOD_CTRL_BIT BIT(0)
#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
#define LINE_USED(line, offset) (line & (BIT(offset)))
static void omap_gpio_unmask_irq(struct irq_data *d);
static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
return gpiochip_get_data(chip);
}
static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
{
u32 val = readl_relaxed(reg);
if (set)
val |= mask;
else
val &= ~mask;
writel_relaxed(val, reg);
return val;
}
static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
int is_input)
{
bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
BIT(gpio), is_input);
}
/* set data out value using dedicate set/clear register */
static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
int enable)
{
void __iomem *reg = bank->base;
u32 l = BIT(offset);
if (enable) {
reg += bank->regs->set_dataout;
bank->context.dataout |= l;
} else {
reg += bank->regs->clr_dataout;
bank->context.dataout &= ~l;
}
writel_relaxed(l, reg);
}
/* set data out value using mask register */
static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
int enable)
{
bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
BIT(offset), enable);
}
static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
{
if (bank->dbck_enable_mask && !bank->dbck_enabled) {
clk_enable(bank->dbck);
bank->dbck_enabled = true;
writel_relaxed(bank->dbck_enable_mask,
bank->base + bank->regs->debounce_en);
}
}
static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
{
if (bank->dbck_enable_mask && bank->dbck_enabled) {
/*
* Disable debounce before cutting it's clock. If debounce is
* enabled but the clock is not, GPIO module seems to be unable
* to detect events and generate interrupts at least on OMAP3.
*/
writel_relaxed(0, bank->base + bank->regs->debounce_en);
clk_disable(bank->dbck);
bank->dbck_enabled = false;
}
}
/**
* omap2_set_gpio_debounce - low level gpio debounce time
* @bank: the gpio bank we're acting upon
* @offset: the gpio number on this @bank
* @debounce: debounce time to use
*
* OMAP's debounce time is in 31us steps
* <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
* so we need to convert and round up to the closest unit.
*
* Return: 0 on success, negative error otherwise.
*/
static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
unsigned debounce)
{
u32 val;
u32 l;
bool enable = !!debounce;
if (!bank->dbck_flag)
return -ENOTSUPP;
if (enable) {
debounce = DIV_ROUND_UP(debounce, 31) - 1;
if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
return -EINVAL;
}
l = BIT(offset);
clk_enable(bank->dbck);
writel_relaxed(debounce, bank->base + bank->regs->debounce);
val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
bank->dbck_enable_mask = val;
clk_disable(bank->dbck);
/*
* Enable debounce clock per module.
* This call is mandatory because in omap_gpio_request() when
* *_runtime_get_sync() is called, _gpio_dbck_enable() within
* runtime callbck fails to turn on dbck because dbck_enable_mask
* used within _gpio_dbck_enable() is still not initialized at
* that point. Therefore we have to enable dbck here.
*/
omap_gpio_dbck_enable(bank);
if (bank->dbck_enable_mask) {
bank->context.debounce = debounce;
bank->context.debounce_en = val;
}
return 0;
}
/**
* omap_clear_gpio_debounce - clear debounce settings for a gpio
* @bank: the gpio bank we're acting upon
* @offset: the gpio number on this @bank
*
* If a gpio is using debounce, then clear the debounce enable bit and if
* this is the only gpio in this bank using debounce, then clear the debounce
* time too. The debounce clock will also be disabled when calling this function
* if this is the only gpio in the bank using debounce.
*/
static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
{
u32 gpio_bit = BIT(offset);
if (!bank->dbck_flag)
return;
if (!(bank->dbck_enable_mask & gpio_bit))
return;
bank->dbck_enable_mask &= ~gpio_bit;
bank->context.debounce_en &= ~gpio_bit;
writel_relaxed(bank->context.debounce_en,
bank->base + bank->regs->debounce_en);
if (!bank->dbck_enable_mask) {
bank->context.debounce = 0;
writel_relaxed(bank->context.debounce, bank->base +
bank->regs->debounce);
clk_disable(bank->dbck);
bank->dbck_enabled = false;
}
}
/*
* Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
* See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
* in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
* are capable waking up the system from off mode.
*/
static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
{
u32 no_wake = bank->non_wakeup_gpios;
if (no_wake)
return !!(~no_wake & gpio_mask);
return false;
}
static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
unsigned trigger)
{
void __iomem *base = bank->base;
u32 gpio_bit = BIT(gpio);
omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
trigger & IRQ_TYPE_LEVEL_LOW);
omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
trigger & IRQ_TYPE_LEVEL_HIGH);
/*
* We need the edge detection enabled for to allow the GPIO block
* to be woken from idle state. Set the appropriate edge detection
* in addition to the level detection.
*/
omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
bank->context.leveldetect0 =
readl_relaxed(bank->base + bank->regs->leveldetect0);
bank->context.leveldetect1 =
readl_relaxed(bank->base + bank->regs->leveldetect1);
bank->context.risingdetect =
readl_relaxed(bank->base + bank->regs->risingdetect);
bank->context.fallingdetect =
readl_relaxed(bank->base + bank->regs->fallingdetect);
bank->level_mask = bank->context.leveldetect0 |
bank->context.leveldetect1;
/* This part needs to be executed always for OMAP{34xx, 44xx} */
if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
/*
* Log the edge gpio and manually trigger the IRQ
* after resume if the input level changes
* to avoid irq lost during PER RET/OFF mode
* Applies for omap2 non-wakeup gpio and all omap3 gpios
*/
if (trigger & IRQ_TYPE_EDGE_BOTH)
bank->enabled_non_wakeup_gpios |= gpio_bit;
else
bank->enabled_non_wakeup_gpios &= ~gpio_bit;
}
}
/*
* This only applies to chips that can't do both rising and falling edge
* detection at once. For all other chips, this function is a noop.
*/
static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
{
if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
void __iomem *reg = bank->base + bank->regs->irqctrl;
writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
}
}
static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
unsigned trigger)
{
void __iomem *reg = bank->base;
u32 l = 0;
if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
omap_set_gpio_trigger(bank, gpio, trigger);
} else if (bank->regs->irqctrl) {
reg += bank->regs->irqctrl;
l = readl_relaxed(reg);
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
bank->toggle_mask |= BIT(gpio);
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= BIT(gpio);
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(BIT(gpio));
else
return -EINVAL;
writel_relaxed(l, reg);
} else if (bank->regs->edgectrl1) {
if (gpio & 0x08)
reg += bank->regs->edgectrl2;
else
reg += bank->regs->edgectrl1;
gpio &= 0x07;
l = readl_relaxed(reg);
l &= ~(3 << (gpio << 1));
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 2 << (gpio << 1);
if (trigger & IRQ_TYPE_EDGE_FALLING)
l |= BIT(gpio << 1);
writel_relaxed(l, reg);
}
return 0;
}
static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
{
if (bank->regs->pinctrl) {
void __iomem *reg = bank->base + bank->regs->pinctrl;
/* Claim the pin for MPU */
writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
}
if (bank->regs->ctrl && !BANK_USED(bank)) {
void __iomem *reg = bank->base + bank->regs->ctrl;
u32 ctrl;
ctrl = readl_relaxed(reg);
/* Module is enabled, clocks are not gated */
ctrl &= ~GPIO_MOD_CTRL_BIT;
writel_relaxed(ctrl, reg);
bank->context.ctrl = ctrl;
}
}
static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
{
if (bank->regs->ctrl && !BANK_USED(bank)) {
void __iomem *reg = bank->base + bank->regs->ctrl;
u32 ctrl;
ctrl = readl_relaxed(reg);
/* Module is disabled, clocks are gated */
ctrl |= GPIO_MOD_CTRL_BIT;
writel_relaxed(ctrl, reg);
bank->context.ctrl = ctrl;
}
}
static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
{
void __iomem *reg = bank->base + bank->regs->direction;
return readl_relaxed(reg) & BIT(offset);
}
static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
{
if (!LINE_USED(bank->mod_usage, offset)) {
omap_enable_gpio_module(bank, offset);
omap_set_gpio_direction(bank, offset, 1);
}
bank->irq_usage |= BIT(offset);
}
static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
{
struct gpio_bank *bank = omap_irq_data_get_bank(d);
int retval;
unsigned long flags;
unsigned offset = d->hwirq;
if (type & ~IRQ_TYPE_SENSE_MASK)
return -EINVAL;
if (!bank->regs->leveldetect0 &&
(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
return -EINVAL;
raw_spin_lock_irqsave(&bank->lock, flags);
retval = omap_set_gpio_triggering(bank, offset, type);
if (retval) {
raw_spin_unlock_irqrestore(&bank->lock, flags);
goto error;
}
omap_gpio_init_irq(bank, offset);
if (!omap_gpio_is_input(bank, offset)) {
raw_spin_unlock_irqrestore(&bank->lock, flags);
retval = -EINVAL;
goto error;
}
raw_spin_unlock_irqrestore(&bank->lock, flags);
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
irq_set_handler_locked(d, handle_level_irq);
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
/*
* Edge IRQs are already cleared/acked in irq_handler and
* not need to be masked, as result handle_edge_irq()
* logic is excessed here and may cause lose of interrupts.
* So just use handle_simple_irq.
*/
irq_set_handler_locked(d, handle_simple_irq);
return 0;
error:
return retval;
}
static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
{
void __iomem *reg = bank->base;
reg += bank->regs->irqstatus;
writel_relaxed(gpio_mask, reg);
/* Workaround for clearing DSP GPIO interrupts to allow retention */
if (bank->regs->irqstatus2) {
reg = bank->base + bank->regs->irqstatus2;
writel_relaxed(gpio_mask, reg);
}
/* Flush posted write for the irq status to avoid spurious interrupts */
readl_relaxed(reg);
}
static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
unsigned offset)
{
omap_clear_gpio_irqbank(bank, BIT(offset));
}
static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
{
void __iomem *reg = bank->base;
u32 l;
u32 mask = (BIT(bank->width)) - 1;
reg += bank->regs->irqenable;
l = readl_relaxed(reg);
if (bank->regs->irqenable_inv)
l = ~l;
l &= mask;
return l;
}
static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
unsigned offset, int enable)
{
void __iomem *reg = bank->base;
u32 gpio_mask = BIT(offset);
if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
if (enable) {
reg += bank->regs->set_irqenable;
bank->context.irqenable1 |= gpio_mask;
} else {
reg += bank->regs->clr_irqenable;
bank->context.irqenable1 &= ~gpio_mask;
}
writel_relaxed(gpio_mask, reg);
} else {
bank->context.irqenable1 =
omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
enable ^ bank->regs->irqenable_inv);
}
/*
* Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM
* note requiring correlation between the IRQ enable registers and
* the wakeup registers. In any case, we want wakeup from idle
* enabled for the GPIOs which support this feature.
*/
if (bank->regs->wkup_en &&
(bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {
bank->context.wake_en =
omap_gpio_rmw(bank->base + bank->regs->wkup_en,
gpio_mask, enable);
}
}
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
{
struct gpio_bank *bank = omap_irq_data_get_bank(d);
return irq_set_irq_wake(bank->irq, enable);
}
/*
* We need to unmask the GPIO bank interrupt as soon as possible to
* avoid missing GPIO interrupts for other lines in the bank.
* Then we need to mask-read-clear-unmask the triggered GPIO lines
* in the bank to avoid missing nested interrupts for a GPIO line.
* If we wait to unmask individual GPIO lines in the bank after the
* line's interrupt handler has been run, we may miss some nested
* interrupts.
*/
static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
{
void __iomem *isr_reg = NULL;
u32 enabled, isr, edge;
unsigned int bit;
struct gpio_bank *bank = gpiobank;
unsigned long wa_lock_flags;
unsigned long lock_flags;
isr_reg = bank->base + bank->regs->irqstatus;
if (WARN_ON(!isr_reg))
goto exit;
if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
"gpio irq%i while runtime suspended?\n", irq))
return IRQ_NONE;
while (1) {
raw_spin_lock_irqsave(&bank->lock, lock_flags);
enabled = omap_get_gpio_irqbank_mask(bank);
isr = readl_relaxed(isr_reg) & enabled;
/*
* Clear edge sensitive interrupts before calling handler(s)
* so subsequent edge transitions are not missed while the
* handlers are running.
*/
edge = isr & ~bank->level_mask;
if (edge)
omap_clear_gpio_irqbank(bank, edge);
raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
if (!isr)
break;
while (isr) {
bit = __ffs(isr);
isr &= ~(BIT(bit));
raw_spin_lock_irqsave(&bank->lock, lock_flags);
/*
* Some chips can't respond to both rising and falling
* at the same time. If this irq was requested with
* both flags, we need to flip the ICR data for the IRQ
* to respond to the IRQ for the opposite direction.
* This will be indicated in the bank toggle_mask.
*/
if (bank->toggle_mask & (BIT(bit)))
omap_toggle_gpio_edge_triggering(bank, bit);
raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
generic_handle_domain_irq(bank->chip.irq.domain, bit);
raw_spin_unlock_irqrestore(&bank->wa_lock,
wa_lock_flags);
}
}
exit:
return IRQ_HANDLED;
}
static unsigned int omap_gpio_irq_startup(struct irq_data *d)
{
struct gpio_bank *bank = omap_irq_data_get_bank(d);
unsigned long flags;
unsigned offset = d->hwirq;
raw_spin_lock_irqsave(&bank->lock, flags);
if (!LINE_USED(bank->mod_usage, offset))
omap_set_gpio_direction(bank, offset, 1);
omap_enable_gpio_module(bank, offset);
bank->irq_usage |= BIT(offset);
raw_spin_unlock_irqrestore(&bank->lock, flags);
omap_gpio_unmask_irq(d);
return 0;
}
static void omap_gpio_irq_shutdown(struct irq_data *d)
{
struct gpio_bank *bank = omap_irq_data_get_bank(d);
unsigned long flags;
unsigned offset = d->hwirq;
raw_spin_lock_irqsave(&bank->lock, flags);
bank->irq_usage &= ~(BIT(offset));
omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
omap_clear_gpio_irqstatus(bank, offset);
omap_set_gpio_irqenable(bank, offset, 0);
if (!LINE_USED(bank->mod_usage, offset))
omap_clear_gpio_debounce(bank, offset);
omap_disable_gpio_module(bank, offset);
raw_spin_unlock_irqrestore(&bank->lock, flags);
}
static void omap_gpio_irq_bus_lock(struct irq_data *data)
{
struct gpio_bank *bank = omap_irq_data_get_bank(data);
pm_runtime_get_sync(bank->chip.parent);
}
static void gpio_irq_bus_sync_unlock(struct irq_data *data)
{
struct gpio_bank *bank = omap_irq_data_get_bank(data);
pm_runtime_put(bank->chip.parent);
}
static void omap_gpio_mask_irq(struct irq_data *d)
{
struct gpio_bank *bank = omap_irq_data_get_bank(d);
unsigned offset = d->hwirq;
unsigned long flags;
raw_spin_lock_irqsave(&bank->lock, flags);
omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
omap_set_gpio_irqenable(bank, offset, 0);
raw_spin_unlock_irqrestore(&bank->lock, flags);
gpiochip_disable_irq(&bank->chip, offset);
}
static void omap_gpio_unmask_irq(struct irq_data *d)
{
struct gpio_bank *bank = omap_irq_data_get_bank(d);
unsigned offset = d->hwirq;
u32 trigger = irqd_get_trigger_type(d);
unsigned long flags;
gpiochip_enable_irq(&bank->chip, offset);
raw_spin_lock_irqsave(&bank->lock, flags);
omap_set_gpio_irqenable(bank, offset, 1);
/*
* For level-triggered GPIOs, clearing must be done after the source
* is cleared, thus after the handler has run. OMAP4 needs this done
* after enabing the interrupt to clear the wakeup status.
*/
if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
omap_clear_gpio_irqstatus(bank, offset);
if (trigger)
omap_set_gpio_triggering(bank, offset, trigger);
raw_spin_unlock_irqrestore(&bank->lock, flags);
}
static void omap_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
{
struct gpio_bank *bank = omap_irq_data_get_bank(d);
seq_printf(p, dev_name(bank->dev));
}
static const struct irq_chip omap_gpio_irq_chip = {
.irq_startup = omap_gpio_irq_startup,
.irq_shutdown = omap_gpio_irq_shutdown,
.irq_mask = omap_gpio_mask_irq,
.irq_unmask = omap_gpio_unmask_irq,
.irq_set_type = omap_gpio_irq_type,
.irq_set_wake = omap_gpio_wake_enable,
.irq_bus_lock = omap_gpio_irq_bus_lock,
.irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
.irq_print_chip = omap_gpio_irq_print_chip,
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static const struct irq_chip omap_gpio_irq_chip_nowake = {
.irq_startup = omap_gpio_irq_startup,
.irq_shutdown = omap_gpio_irq_shutdown,
.irq_mask = omap_gpio_mask_irq,
.irq_unmask = omap_gpio_unmask_irq,
.irq_set_type = omap_gpio_irq_type,
.irq_bus_lock = omap_gpio_irq_bus_lock,
.irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
.irq_print_chip = omap_gpio_irq_print_chip,
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
/*---------------------------------------------------------------------*/
static int omap_mpuio_suspend_noirq(struct device *dev)
{
struct gpio_bank *bank = dev_get_drvdata(dev);
void __iomem *mask_reg = bank->base +
OMAP_MPUIO_GPIO_MASKIT / bank->stride;
unsigned long flags;
raw_spin_lock_irqsave(&bank->lock, flags);
writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
raw_spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
static int omap_mpuio_resume_noirq(struct device *dev)
{
struct gpio_bank *bank = dev_get_drvdata(dev);
void __iomem *mask_reg = bank->base +
OMAP_MPUIO_GPIO_MASKIT / bank->stride;
unsigned long flags;
raw_spin_lock_irqsave(&bank->lock, flags);
writel_relaxed(bank->context.wake_en, mask_reg);
raw_spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
.suspend_noirq = omap_mpuio_suspend_noirq,
.resume_noirq = omap_mpuio_resume_noirq,
};
/* use platform_driver for this. */
static struct platform_driver omap_mpuio_driver = {
.driver = {
.name = "mpuio",
.pm = &omap_mpuio_dev_pm_ops,
},
};
static struct platform_device omap_mpuio_device = {
.name = "mpuio",
.id = -1,
.dev = {
.driver = &omap_mpuio_driver.driver,
}
/* could list the /proc/iomem resources */
};
static inline void omap_mpuio_init(struct gpio_bank *bank)
{
platform_set_drvdata(&omap_mpuio_device, bank);
if (platform_driver_register(&omap_mpuio_driver) == 0)
(void) platform_device_register(&omap_mpuio_device);
}
/*---------------------------------------------------------------------*/
static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = gpiochip_get_data(chip);
unsigned long flags;
pm_runtime_get_sync(chip->parent);
raw_spin_lock_irqsave(&bank->lock, flags);
omap_enable_gpio_module(bank, offset);
bank->mod_usage |= BIT(offset);
raw_spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = gpiochip_get_data(chip);
unsigned long flags;
raw_spin_lock_irqsave(&bank->lock, flags);
bank->mod_usage &= ~(BIT(offset));
if (!LINE_USED(bank->irq_usage, offset)) {
omap_set_gpio_direction(bank, offset, 1);
omap_clear_gpio_debounce(bank, offset);
}
omap_disable_gpio_module(bank, offset);
raw_spin_unlock_irqrestore(&bank->lock, flags);
pm_runtime_put(chip->parent);
}
static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = gpiochip_get_data(chip);
if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank;
unsigned long flags;
bank = gpiochip_get_data(chip);
raw_spin_lock_irqsave(&bank->lock, flags);
omap_set_gpio_direction(bank, offset, 1);
raw_spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = gpiochip_get_data(chip);
void __iomem *reg;
if (omap_gpio_is_input(bank, offset))
reg = bank->base + bank->regs->datain;
else
reg = bank->base + bank->regs->dataout;
return (readl_relaxed(reg) & BIT(offset)) != 0;
}
static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
{
struct gpio_bank *bank;
unsigned long flags;
bank = gpiochip_get_data(chip);
raw_spin_lock_irqsave(&bank->lock, flags);
bank->set_dataout(bank, offset, value);
omap_set_gpio_direction(bank, offset, 0);
raw_spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
unsigned long *bits)
{
struct gpio_bank *bank = gpiochip_get_data(chip);
void __iomem *base = bank->base;
u32 direction, m, val = 0;
direction = readl_relaxed(base + bank->regs->direction);
m = direction & *mask;
if (m)
val |= readl_relaxed(base + bank->regs->datain) & m;
m = ~direction & *mask;
if (m)
val |= readl_relaxed(base + bank->regs->dataout) & m;
*bits = val;
return 0;
}
static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
unsigned debounce)
{
struct gpio_bank *bank;
unsigned long flags;
int ret;
bank = gpiochip_get_data(chip);
raw_spin_lock_irqsave(&bank->lock, flags);
ret = omap2_set_gpio_debounce(bank, offset, debounce);
raw_spin_unlock_irqrestore(&bank->lock, flags);
if (ret)
dev_info(chip->parent,
"Could not set line %u debounce to %u microseconds (%d)",
offset, debounce, ret);
return ret;
}
static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
unsigned long config)
{
u32 debounce;
int ret = -ENOTSUPP;
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = gpiochip_generic_config(chip, offset, config);
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
debounce = pinconf_to_config_argument(config);
ret = omap_gpio_debounce(chip, offset, debounce);
break;
default:
break;
}
return ret;
}
static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct gpio_bank *bank;
unsigned long flags;
bank = gpiochip_get_data(chip);
raw_spin_lock_irqsave(&bank->lock, flags);
bank->set_dataout(bank, offset, value);
raw_spin_unlock_irqrestore(&bank->lock, flags);
}
static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
unsigned long *bits)
{
struct gpio_bank *bank = gpiochip_get_data(chip);
void __iomem *reg = bank->base + bank->regs->dataout;
unsigned long flags;
u32 l;
raw_spin_lock_irqsave(&bank->lock, flags);
l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
writel_relaxed(l, reg);
bank->context.dataout = l;
raw_spin_unlock_irqrestore(&bank->lock, flags);
}
/*---------------------------------------------------------------------*/
static void omap_gpio_show_rev(struct gpio_bank *bank)
{
static bool called;
u32 rev;
if (called || bank->regs->revision == USHRT_MAX)
return;
rev = readw_relaxed(bank->base + bank->regs->revision);
pr_info("OMAP GPIO hardware version %d.%d\n",
(rev >> 4) & 0x0f, rev & 0x0f);
called = true;
}
static void omap_gpio_mod_init(struct gpio_bank *bank)
{
void __iomem *base = bank->base;
u32 l = 0xffffffff;
if (bank->width == 16)
l = 0xffff;
if (bank->is_mpuio) {
writel_relaxed(l, bank->base + bank->regs->irqenable);
return;
}
omap_gpio_rmw(base + bank->regs->irqenable, l,
bank->regs->irqenable_inv);
omap_gpio_rmw(base + bank->regs->irqstatus, l,
!bank->regs->irqenable_inv);
if (bank->regs->debounce_en)
writel_relaxed(0, base + bank->regs->debounce_en);
/* Save OE default value (0xffffffff) in the context */
bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
/* Initialize interface clk ungated, module enabled */
if (bank->regs->ctrl)
writel_relaxed(0, base + bank->regs->ctrl);
}
static int omap_gpio_chip_init(struct gpio_bank *bank, struct device *pm_dev)
{
struct gpio_irq_chip *irq;
static int gpio;
const char *label;
int ret;
/*
* REVISIT eventually switch from OMAP-specific gpio structs
* over to the generic ones
*/
bank->chip.request = omap_gpio_request;
bank->chip.free = omap_gpio_free;
bank->chip.get_direction = omap_gpio_get_direction;
bank->chip.direction_input = omap_gpio_input;
bank->chip.get = omap_gpio_get;
bank->chip.get_multiple = omap_gpio_get_multiple;
bank->chip.direction_output = omap_gpio_output;
bank->chip.set_config = omap_gpio_set_config;
bank->chip.set = omap_gpio_set;
bank->chip.set_multiple = omap_gpio_set_multiple;
if (bank->is_mpuio) {
bank->chip.label = "mpuio";
if (bank->regs->wkup_en)
bank->chip.parent = &omap_mpuio_device.dev;
bank->chip.base = OMAP_MPUIO(0);
} else {
label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
gpio, gpio + bank->width - 1);
if (!label)
return -ENOMEM;
bank->chip.label = label;
bank->chip.base = -1;
}
bank->chip.ngpio = bank->width;
irq = &bank->chip.irq;
/* MPUIO is a bit different, reading IRQ status clears it */
if (bank->is_mpuio && !bank->regs->wkup_en)
gpio_irq_chip_set_chip(irq, &omap_gpio_irq_chip_nowake);
else
gpio_irq_chip_set_chip(irq, &omap_gpio_irq_chip);
irq->handler = handle_bad_irq;
irq->default_type = IRQ_TYPE_NONE;
irq->num_parents = 1;
irq->parents = &bank->irq;
ret = gpiochip_add_data(&bank->chip, bank);
if (ret)
return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n");
irq_domain_set_pm_device(bank->chip.irq.domain, pm_dev);
ret = devm_request_irq(bank->chip.parent, bank->irq,
omap_gpio_irq_handler,
0, dev_name(bank->chip.parent), bank);
if (ret)
gpiochip_remove(&bank->chip);
if (!bank->is_mpuio)
gpio += bank->width;
return ret;
}
static void omap_gpio_init_context(struct gpio_bank *p)
{
const struct omap_gpio_reg_offs *regs = p->regs;
void __iomem *base = p->base;
p->context.sysconfig = readl_relaxed(base + regs->sysconfig);
p->context.ctrl = readl_relaxed(base + regs->ctrl);
p->context.oe = readl_relaxed(base + regs->direction);
p->context.wake_en = readl_relaxed(base + regs->wkup_en);
p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
p->context.dataout = readl_relaxed(base + regs->dataout);
p->context_valid = true;
}
static void omap_gpio_restore_context(struct gpio_bank *bank)
{
const struct omap_gpio_reg_offs *regs = bank->regs;
void __iomem *base = bank->base;
writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
writel_relaxed(bank->context.ctrl, base + regs->ctrl);
writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
writel_relaxed(bank->context.dataout, base + regs->dataout);
writel_relaxed(bank->context.oe, base + regs->direction);
if (bank->dbck_enable_mask) {
writel_relaxed(bank->context.debounce, base + regs->debounce);
writel_relaxed(bank->context.debounce_en,
base + regs->debounce_en);
}
writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
}
static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
{
struct device *dev = bank->chip.parent;
void __iomem *base = bank->base;
u32 mask, nowake;
bank->saved_datain = readl_relaxed(base + bank->regs->datain);
/* Save syconfig, it's runtime value can be different from init value */
if (bank->loses_context)
bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
if (!bank->enabled_non_wakeup_gpios)
goto update_gpio_context_count;
/* Check for pending EDGE_FALLING, ignore EDGE_BOTH */
mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
mask &= ~bank->context.risingdetect;
bank->saved_datain |= mask;
/* Check for pending EDGE_RISING, ignore EDGE_BOTH */
mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
mask &= ~bank->context.fallingdetect;
bank->saved_datain &= ~mask;
if (!may_lose_context)
goto update_gpio_context_count;
/*
* If going to OFF, remove triggering for all wkup domain
* non-wakeup GPIOs. Otherwise spurious IRQs will be
* generated. See OMAP2420 Errata item 1.101.
*/
if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
nowake = bank->enabled_non_wakeup_gpios;
omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
}
update_gpio_context_count:
if (bank->get_context_loss_count)
bank->context_loss_count =
bank->get_context_loss_count(dev);
omap_gpio_dbck_disable(bank);
}
static void omap_gpio_unidle(struct gpio_bank *bank)
{
struct device *dev = bank->chip.parent;
u32 l = 0, gen, gen0, gen1;
int c;
/*
* On the first resume during the probe, the context has not
* been initialised and so initialise it now. Also initialise
* the context loss count.
*/
if (bank->loses_context && !bank->context_valid) {
omap_gpio_init_context(bank);
if (bank->get_context_loss_count)
bank->context_loss_count =
bank->get_context_loss_count(dev);
}
omap_gpio_dbck_enable(bank);
if (bank->loses_context) {
if (!bank->get_context_loss_count) {
omap_gpio_restore_context(bank);
} else {
c = bank->get_context_loss_count(dev);
if (c != bank->context_loss_count) {
omap_gpio_restore_context(bank);
} else {
return;
}
}
} else {
/* Restore changes done for OMAP2420 errata 1.101 */
writel_relaxed(bank->context.fallingdetect,
bank->base + bank->regs->fallingdetect);
writel_relaxed(bank->context.risingdetect,
bank->base + bank->regs->risingdetect);
}
l = readl_relaxed(bank->base + bank->regs->datain);
/*
* Check if any of the non-wakeup interrupt GPIOs have changed
* state. If so, generate an IRQ by software. This is
* horribly racy, but it's the best we can do to work around
* this silicon bug.
*/
l ^= bank->saved_datain;
l &= bank->enabled_non_wakeup_gpios;
/*
* No need to generate IRQs for the rising edge for gpio IRQs
* configured with falling edge only; and vice versa.
*/
gen0 = l & bank->context.fallingdetect;
gen0 &= bank->saved_datain;
gen1 = l & bank->context.risingdetect;
gen1 &= ~(bank->saved_datain);
/* FIXME: Consider GPIO IRQs with level detections properly! */
gen = l & (~(bank->context.fallingdetect) &
~(bank->context.risingdetect));
/* Consider all GPIO IRQs needed to be updated */
gen |= gen0 | gen1;
if (gen) {
u32 old0, old1;
old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
if (!bank->regs->irqstatus_raw0) {
writel_relaxed(old0 | gen, bank->base +
bank->regs->leveldetect0);
writel_relaxed(old1 | gen, bank->base +
bank->regs->leveldetect1);
}
if (bank->regs->irqstatus_raw0) {
writel_relaxed(old0 | l, bank->base +
bank->regs->leveldetect0);
writel_relaxed(old1 | l, bank->base +
bank->regs->leveldetect1);
}
writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
}
}
static int gpio_omap_cpu_notifier(struct notifier_block *nb,
unsigned long cmd, void *v)
{
struct gpio_bank *bank;
unsigned long flags;
int ret = NOTIFY_OK;
u32 isr, mask;
bank = container_of(nb, struct gpio_bank, nb);
raw_spin_lock_irqsave(&bank->lock, flags);
if (bank->is_suspended)
goto out_unlock;
switch (cmd) {
case CPU_CLUSTER_PM_ENTER:
mask = omap_get_gpio_irqbank_mask(bank);
isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
if (isr) {
ret = NOTIFY_BAD;
break;
}
omap_gpio_idle(bank, true);
break;
case CPU_CLUSTER_PM_ENTER_FAILED:
case CPU_CLUSTER_PM_EXIT:
omap_gpio_unidle(bank);
break;
}
out_unlock:
raw_spin_unlock_irqrestore(&bank->lock, flags);
return ret;
}
static const struct omap_gpio_reg_offs omap2_gpio_regs = {
.revision = OMAP24XX_GPIO_REVISION,
.sysconfig = OMAP24XX_GPIO_SYSCONFIG,
.direction = OMAP24XX_GPIO_OE,
.datain = OMAP24XX_GPIO_DATAIN,
.dataout = OMAP24XX_GPIO_DATAOUT,
.set_dataout = OMAP24XX_GPIO_SETDATAOUT,
.clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
.irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
.irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
.irqenable = OMAP24XX_GPIO_IRQENABLE1,
.irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
.set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
.clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
.debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
.debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
.ctrl = OMAP24XX_GPIO_CTRL,
.wkup_en = OMAP24XX_GPIO_WAKE_EN,
.leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
.leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
.risingdetect = OMAP24XX_GPIO_RISINGDETECT,
.fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
};
static const struct omap_gpio_reg_offs omap4_gpio_regs = {
.revision = OMAP4_GPIO_REVISION,
.sysconfig = OMAP4_GPIO_SYSCONFIG,
.direction = OMAP4_GPIO_OE,
.datain = OMAP4_GPIO_DATAIN,
.dataout = OMAP4_GPIO_DATAOUT,
.set_dataout = OMAP4_GPIO_SETDATAOUT,
.clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
.irqstatus = OMAP4_GPIO_IRQSTATUS0,
.irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
.irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
.irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
.irqenable = OMAP4_GPIO_IRQSTATUSSET0,
.irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
.set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
.clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
.debounce = OMAP4_GPIO_DEBOUNCINGTIME,
.debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
.ctrl = OMAP4_GPIO_CTRL,
.wkup_en = OMAP4_GPIO_IRQWAKEN0,
.leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
.leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
.risingdetect = OMAP4_GPIO_RISINGDETECT,
.fallingdetect = OMAP4_GPIO_FALLINGDETECT,
};
static const struct omap_gpio_platform_data omap2_pdata = {
.regs = &omap2_gpio_regs,
.bank_width = 32,
.dbck_flag = false,
};
static const struct omap_gpio_platform_data omap3_pdata = {
.regs = &omap2_gpio_regs,
.bank_width = 32,
.dbck_flag = true,
};
static const struct omap_gpio_platform_data omap4_pdata = {
.regs = &omap4_gpio_regs,
.bank_width = 32,
.dbck_flag = true,
};
static const struct of_device_id omap_gpio_match[] = {
{
.compatible = "ti,omap4-gpio",
.data = &omap4_pdata,
},
{
.compatible = "ti,omap3-gpio",
.data = &omap3_pdata,
},
{
.compatible = "ti,omap2-gpio",
.data = &omap2_pdata,
},
{ },
};
MODULE_DEVICE_TABLE(of, omap_gpio_match);
static int omap_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
const struct omap_gpio_platform_data *pdata;
struct gpio_bank *bank;
int ret;
pdata = device_get_match_data(dev);
pdata = pdata ?: dev_get_platdata(dev);
if (!pdata)
return -EINVAL;
bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
if (!bank)
return -ENOMEM;
bank->dev = dev;
bank->irq = platform_get_irq(pdev, 0);
if (bank->irq < 0)
return bank->irq;
bank->chip.parent = dev;
bank->chip.owner = THIS_MODULE;
bank->dbck_flag = pdata->dbck_flag;
bank->stride = pdata->bank_stride;
bank->width = pdata->bank_width;
bank->is_mpuio = pdata->is_mpuio;
bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
bank->regs = pdata->regs;
if (node) {
if (!of_property_read_bool(node, "ti,gpio-always-on"))
bank->loses_context = true;
} else {
bank->loses_context = pdata->loses_context;
if (bank->loses_context)
bank->get_context_loss_count =
pdata->get_context_loss_count;
}
if (bank->regs->set_dataout && bank->regs->clr_dataout)
bank->set_dataout = omap_set_gpio_dataout_reg;
else
bank->set_dataout = omap_set_gpio_dataout_mask;
raw_spin_lock_init(&bank->lock);
raw_spin_lock_init(&bank->wa_lock);
/* Static mapping, never released */
bank->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(bank->base)) {
return PTR_ERR(bank->base);
}
if (bank->dbck_flag) {
bank->dbck = devm_clk_get(dev, "dbclk");
if (IS_ERR(bank->dbck)) {
dev_err(dev,
"Could not get gpio dbck. Disable debounce\n");
bank->dbck_flag = false;
} else {
clk_prepare(bank->dbck);
}
}
platform_set_drvdata(pdev, bank);
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
if (bank->is_mpuio)
omap_mpuio_init(bank);
omap_gpio_mod_init(bank);
ret = omap_gpio_chip_init(bank, dev);
if (ret) {
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
if (bank->dbck_flag)
clk_unprepare(bank->dbck);
return ret;
}
omap_gpio_show_rev(bank);
bank->nb.notifier_call = gpio_omap_cpu_notifier;
cpu_pm_register_notifier(&bank->nb);
pm_runtime_put(dev);
return 0;
}
static int omap_gpio_remove(struct platform_device *pdev)
{
struct gpio_bank *bank = platform_get_drvdata(pdev);
cpu_pm_unregister_notifier(&bank->nb);
gpiochip_remove(&bank->chip);
pm_runtime_disable(&pdev->dev);
if (bank->dbck_flag)
clk_unprepare(bank->dbck);
return 0;
}
static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
{
struct gpio_bank *bank = dev_get_drvdata(dev);
unsigned long flags;
raw_spin_lock_irqsave(&bank->lock, flags);
omap_gpio_idle(bank, true);
bank->is_suspended = true;
raw_spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
{
struct gpio_bank *bank = dev_get_drvdata(dev);
unsigned long flags;
raw_spin_lock_irqsave(&bank->lock, flags);
omap_gpio_unidle(bank);
bank->is_suspended = false;
raw_spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
static int __maybe_unused omap_gpio_suspend(struct device *dev)
{
struct gpio_bank *bank = dev_get_drvdata(dev);
if (bank->is_suspended)
return 0;
bank->needs_resume = 1;
return omap_gpio_runtime_suspend(dev);
}
static int __maybe_unused omap_gpio_resume(struct device *dev)
{
struct gpio_bank *bank = dev_get_drvdata(dev);
if (!bank->needs_resume)
return 0;
bank->needs_resume = 0;
return omap_gpio_runtime_resume(dev);
}
static const struct dev_pm_ops gpio_pm_ops = {
SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
NULL)
SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
};
static struct platform_driver omap_gpio_driver = {
.probe = omap_gpio_probe,
.remove = omap_gpio_remove,
.driver = {
.name = "omap_gpio",
.pm = &gpio_pm_ops,
.of_match_table = omap_gpio_match,
},
};
/*
* gpio driver register needs to be done before
* machine_init functions access gpio APIs.
* Hence omap_gpio_drv_reg() is a postcore_initcall.
*/
static int __init omap_gpio_drv_reg(void)
{
return platform_driver_register(&omap_gpio_driver);
}
postcore_initcall(omap_gpio_drv_reg);
static void __exit omap_gpio_exit(void)
{
platform_driver_unregister(&omap_gpio_driver);
}
module_exit(omap_gpio_exit);
MODULE_DESCRIPTION("omap gpio driver");
MODULE_ALIAS("platform:gpio-omap");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-omap.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
*
* Copyright (C) 2010 Extreme Engineering Solutions.
*/
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/ioport.h>
#include <linux/mfd/lpc_ich.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#define DRV_NAME "gpio_ich"
/*
* GPIO register offsets in GPIO I/O space.
* Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
* LVLx registers. Logic in the read/write functions takes a register and
* an absolute bit number and determines the proper register offset and bit
* number in that register. For example, to read the value of GPIO bit 50
* the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
* bit 18 (50%32).
*/
enum GPIO_REG {
GPIO_USE_SEL = 0,
GPIO_IO_SEL,
GPIO_LVL,
GPO_BLINK
};
static const u8 ichx_regs[4][3] = {
{0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
{0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
{0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
{0x18, 0x18, 0x18}, /* BLINK offset */
};
static const u8 ichx_reglen[3] = {
0x30, 0x10, 0x10,
};
static const u8 avoton_regs[4][3] = {
{0x00, 0x80, 0x00},
{0x04, 0x84, 0x00},
{0x08, 0x88, 0x00},
};
static const u8 avoton_reglen[3] = {
0x10, 0x10, 0x00,
};
#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
struct ichx_desc {
/* Max GPIO pins the chipset can have */
uint ngpio;
/* chipset registers */
const u8 (*regs)[3];
const u8 *reglen;
/* GPO_BLINK is available on this chipset */
bool have_blink;
/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
bool uses_gpe0;
/* USE_SEL is bogus on some chipsets, eg 3100 */
u32 use_sel_ignore[3];
/* Some chipsets have quirks, let these use their own request/get */
int (*request)(struct gpio_chip *chip, unsigned int offset);
int (*get)(struct gpio_chip *chip, unsigned int offset);
/*
* Some chipsets don't let reading output values on GPIO_LVL register
* this option allows driver caching written output values
*/
bool use_outlvl_cache;
};
static struct {
spinlock_t lock;
struct device *dev;
struct gpio_chip chip;
struct resource *gpio_base; /* GPIO IO base */
struct resource *pm_base; /* Power Management IO base */
struct ichx_desc *desc; /* Pointer to chipset-specific description */
u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
u8 use_gpio; /* Which GPIO groups are usable */
int outlvl_cache[3]; /* cached output values */
} ichx_priv;
static int modparam_gpiobase = -1; /* dynamic */
module_param_named(gpiobase, modparam_gpiobase, int, 0444);
MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default.");
static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)
{
unsigned long flags;
u32 data, tmp;
int reg_nr = nr / 32;
int bit = nr & 0x1f;
spin_lock_irqsave(&ichx_priv.lock, flags);
if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
data = ichx_priv.outlvl_cache[reg_nr];
else
data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
ichx_priv.gpio_base);
if (val)
data |= BIT(bit);
else
data &= ~BIT(bit);
ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
ichx_priv.gpio_base);
if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
ichx_priv.outlvl_cache[reg_nr] = data;
tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
ichx_priv.gpio_base);
spin_unlock_irqrestore(&ichx_priv.lock, flags);
return (verify && data != tmp) ? -EPERM : 0;
}
static int ichx_read_bit(int reg, unsigned int nr)
{
unsigned long flags;
u32 data;
int reg_nr = nr / 32;
int bit = nr & 0x1f;
spin_lock_irqsave(&ichx_priv.lock, flags);
data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
ichx_priv.gpio_base);
if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
data = ichx_priv.outlvl_cache[reg_nr] | data;
spin_unlock_irqrestore(&ichx_priv.lock, flags);
return !!(data & BIT(bit));
}
static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned int nr)
{
return !!(ichx_priv.use_gpio & BIT(nr / 32));
}
static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
{
if (ichx_read_bit(GPIO_IO_SEL, nr))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
{
/*
* Try setting pin as an input and verify it worked since many pins
* are output-only.
*/
return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1);
}
static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
int val)
{
/* Disable blink hardware which is available for GPIOs from 0 to 31. */
if (nr < 32 && ichx_priv.desc->have_blink)
ichx_write_bit(GPO_BLINK, nr, 0, 0);
/* Set GPIO output value. */
ichx_write_bit(GPIO_LVL, nr, val, 0);
/*
* Try setting pin as an output and verify it worked since many pins
* are input-only.
*/
return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1);
}
static int ichx_gpio_get(struct gpio_chip *chip, unsigned int nr)
{
return ichx_read_bit(GPIO_LVL, nr);
}
static int ich6_gpio_get(struct gpio_chip *chip, unsigned int nr)
{
unsigned long flags;
u32 data;
/*
* GPI 0 - 15 need to be read from the power management registers on
* a ICH6/3100 bridge.
*/
if (nr < 16) {
if (!ichx_priv.pm_base)
return -ENXIO;
spin_lock_irqsave(&ichx_priv.lock, flags);
/* GPI 0 - 15 are latched, write 1 to clear*/
ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);
data = ICHX_READ(0, ichx_priv.pm_base);
spin_unlock_irqrestore(&ichx_priv.lock, flags);
return !!((data >> 16) & BIT(nr));
} else {
return ichx_gpio_get(chip, nr);
}
}
static int ichx_gpio_request(struct gpio_chip *chip, unsigned int nr)
{
if (!ichx_gpio_check_available(chip, nr))
return -ENXIO;
/*
* Note we assume the BIOS properly set a bridge's USE value. Some
* chips (eg Intel 3100) have bogus USE values though, so first see if
* the chipset's USE value can be trusted for this specific bit.
* If it can't be trusted, assume that the pin can be used as a GPIO.
*/
if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
return 0;
return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
}
static int ich6_gpio_request(struct gpio_chip *chip, unsigned int nr)
{
/*
* Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
* bridge as they are controlled by USE register bits 0 and 1. See
* "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
* additional info.
*/
if (nr == 16 || nr == 17)
nr -= 16;
return ichx_gpio_request(chip, nr);
}
static void ichx_gpio_set(struct gpio_chip *chip, unsigned int nr, int val)
{
ichx_write_bit(GPIO_LVL, nr, val, 0);
}
static void ichx_gpiolib_setup(struct gpio_chip *chip)
{
chip->owner = THIS_MODULE;
chip->label = DRV_NAME;
chip->parent = ichx_priv.dev;
/* Allow chip-specific overrides of request()/get() */
chip->request = ichx_priv.desc->request ?
ichx_priv.desc->request : ichx_gpio_request;
chip->get = ichx_priv.desc->get ?
ichx_priv.desc->get : ichx_gpio_get;
chip->set = ichx_gpio_set;
chip->get_direction = ichx_gpio_get_direction;
chip->direction_input = ichx_gpio_direction_input;
chip->direction_output = ichx_gpio_direction_output;
chip->base = modparam_gpiobase;
chip->ngpio = ichx_priv.desc->ngpio;
chip->can_sleep = false;
chip->dbg_show = NULL;
}
/* ICH6-based, 631xesb-based */
static struct ichx_desc ich6_desc = {
/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
.request = ich6_gpio_request,
.get = ich6_gpio_get,
/* GPIO 0-15 are read in the GPE0_STS PM register */
.uses_gpe0 = true,
.ngpio = 50,
.have_blink = true,
.regs = ichx_regs,
.reglen = ichx_reglen,
};
/* Intel 3100 */
static struct ichx_desc i3100_desc = {
/*
* Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
* the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
* Datasheet for more info.
*/
.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
/* The 3100 needs fixups for GPIO 0 - 17 */
.request = ich6_gpio_request,
.get = ich6_gpio_get,
/* GPIO 0-15 are read in the GPE0_STS PM register */
.uses_gpe0 = true,
.ngpio = 50,
.regs = ichx_regs,
.reglen = ichx_reglen,
};
/* ICH7 and ICH8-based */
static struct ichx_desc ich7_desc = {
.ngpio = 50,
.have_blink = true,
.regs = ichx_regs,
.reglen = ichx_reglen,
};
/* ICH9-based */
static struct ichx_desc ich9_desc = {
.ngpio = 61,
.have_blink = true,
.regs = ichx_regs,
.reglen = ichx_reglen,
};
/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
static struct ichx_desc ich10_cons_desc = {
.ngpio = 61,
.have_blink = true,
.regs = ichx_regs,
.reglen = ichx_reglen,
};
static struct ichx_desc ich10_corp_desc = {
.ngpio = 72,
.have_blink = true,
.regs = ichx_regs,
.reglen = ichx_reglen,
};
/* Intel 5 series, 6 series, 3400 series, and C200 series */
static struct ichx_desc intel5_desc = {
.ngpio = 76,
.regs = ichx_regs,
.reglen = ichx_reglen,
};
/* Avoton */
static struct ichx_desc avoton_desc = {
/* Avoton has only 59 GPIOs, but we assume the first set of register
* (Core) has 32 instead of 31 to keep gpio-ich compliance
*/
.ngpio = 60,
.regs = avoton_regs,
.reglen = avoton_reglen,
.use_outlvl_cache = true,
};
static int ichx_gpio_request_regions(struct device *dev,
struct resource *res_base, const char *name, u8 use_gpio)
{
int i;
if (!res_base || !res_base->start || !res_base->end)
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
if (!(use_gpio & BIT(i)))
continue;
if (!devm_request_region(dev,
res_base->start + ichx_priv.desc->regs[0][i],
ichx_priv.desc->reglen[i], name))
return -EBUSY;
}
return 0;
}
static int ichx_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct lpc_ich_info *ich_info = dev_get_platdata(dev);
struct resource *res_base, *res_pm;
int err;
if (!ich_info)
return -ENODEV;
switch (ich_info->gpio_version) {
case ICH_I3100_GPIO:
ichx_priv.desc = &i3100_desc;
break;
case ICH_V5_GPIO:
ichx_priv.desc = &intel5_desc;
break;
case ICH_V6_GPIO:
ichx_priv.desc = &ich6_desc;
break;
case ICH_V7_GPIO:
ichx_priv.desc = &ich7_desc;
break;
case ICH_V9_GPIO:
ichx_priv.desc = &ich9_desc;
break;
case ICH_V10CORP_GPIO:
ichx_priv.desc = &ich10_corp_desc;
break;
case ICH_V10CONS_GPIO:
ichx_priv.desc = &ich10_cons_desc;
break;
case AVOTON_GPIO:
ichx_priv.desc = &avoton_desc;
break;
default:
return -ENODEV;
}
ichx_priv.dev = dev;
spin_lock_init(&ichx_priv.lock);
res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
err = ichx_gpio_request_regions(dev, res_base, pdev->name,
ich_info->use_gpio);
if (err)
return err;
ichx_priv.gpio_base = res_base;
ichx_priv.use_gpio = ich_info->use_gpio;
/*
* If necessary, determine the I/O address of ACPI/power management
* registers which are needed to read the GPE0 register for GPI pins
* 0 - 15 on some chipsets.
*/
if (!ichx_priv.desc->uses_gpe0)
goto init;
res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
if (!res_pm) {
dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
goto init;
}
if (!devm_request_region(dev, res_pm->start, resource_size(res_pm),
pdev->name)) {
dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n");
goto init;
}
ichx_priv.pm_base = res_pm;
init:
ichx_gpiolib_setup(&ichx_priv.chip);
err = devm_gpiochip_add_data(dev, &ichx_priv.chip, NULL);
if (err) {
dev_err(dev, "Failed to register GPIOs\n");
return err;
}
dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base,
ichx_priv.chip.base + ichx_priv.chip.ngpio - 1);
return 0;
}
static struct platform_driver ichx_gpio_driver = {
.driver = {
.name = DRV_NAME,
},
.probe = ichx_gpio_probe,
};
module_platform_driver(ichx_gpio_driver);
MODULE_AUTHOR("Peter Tyser <[email protected]>");
MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:"DRV_NAME);
| linux-master | drivers/gpio/gpio-ich.c |
// SPDX-License-Identifier: GPL-2.0
/* Driver for IDT/Renesas 79RC3243x Interrupt Controller */
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#define IDT_PIC_IRQ_PEND 0x00
#define IDT_PIC_IRQ_MASK 0x08
#define IDT_GPIO_DIR 0x00
#define IDT_GPIO_DATA 0x04
#define IDT_GPIO_ILEVEL 0x08
#define IDT_GPIO_ISTAT 0x0C
struct idt_gpio_ctrl {
struct gpio_chip gc;
void __iomem *pic;
void __iomem *gpio;
u32 mask_cache;
};
static void idt_gpio_dispatch(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
struct irq_chip *host_chip = irq_desc_get_chip(desc);
unsigned int bit, virq;
unsigned long pending;
chained_irq_enter(host_chip, desc);
pending = readl(ctrl->pic + IDT_PIC_IRQ_PEND);
pending &= ~ctrl->mask_cache;
for_each_set_bit(bit, &pending, gc->ngpio) {
virq = irq_linear_revmap(gc->irq.domain, bit);
if (virq)
generic_handle_irq(virq);
}
chained_irq_exit(host_chip, desc);
}
static int idt_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
unsigned int sense = flow_type & IRQ_TYPE_SENSE_MASK;
unsigned long flags;
u32 ilevel;
/* hardware only supports level triggered */
if (sense == IRQ_TYPE_NONE || (sense & IRQ_TYPE_EDGE_BOTH))
return -EINVAL;
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
ilevel = readl(ctrl->gpio + IDT_GPIO_ILEVEL);
if (sense & IRQ_TYPE_LEVEL_HIGH)
ilevel |= BIT(d->hwirq);
else if (sense & IRQ_TYPE_LEVEL_LOW)
ilevel &= ~BIT(d->hwirq);
writel(ilevel, ctrl->gpio + IDT_GPIO_ILEVEL);
irq_set_handler_locked(d, handle_level_irq);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
return 0;
}
static void idt_gpio_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
writel(~BIT(d->hwirq), ctrl->gpio + IDT_GPIO_ISTAT);
}
static void idt_gpio_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
unsigned long flags;
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
ctrl->mask_cache |= BIT(d->hwirq);
writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
static void idt_gpio_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
unsigned long flags;
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
ctrl->mask_cache &= ~BIT(d->hwirq);
writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
static int idt_gpio_irq_init_hw(struct gpio_chip *gc)
{
struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
/* Mask interrupts. */
ctrl->mask_cache = 0xffffffff;
writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
return 0;
}
static const struct irq_chip idt_gpio_irqchip = {
.name = "IDTGPIO",
.irq_mask = idt_gpio_mask,
.irq_ack = idt_gpio_ack,
.irq_unmask = idt_gpio_unmask,
.irq_set_type = idt_gpio_irq_set_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int idt_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct gpio_irq_chip *girq;
struct idt_gpio_ctrl *ctrl;
int parent_irq;
int ngpios;
int ret;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return -ENOMEM;
ctrl->gpio = devm_platform_ioremap_resource_byname(pdev, "gpio");
if (IS_ERR(ctrl->gpio))
return PTR_ERR(ctrl->gpio);
ctrl->gc.parent = dev;
ret = bgpio_init(&ctrl->gc, &pdev->dev, 4, ctrl->gpio + IDT_GPIO_DATA,
NULL, NULL, ctrl->gpio + IDT_GPIO_DIR, NULL, 0);
if (ret) {
dev_err(dev, "bgpio_init failed\n");
return ret;
}
ret = device_property_read_u32(dev, "ngpios", &ngpios);
if (!ret)
ctrl->gc.ngpio = ngpios;
if (device_property_read_bool(dev, "interrupt-controller")) {
ctrl->pic = devm_platform_ioremap_resource_byname(pdev, "pic");
if (IS_ERR(ctrl->pic))
return PTR_ERR(ctrl->pic);
parent_irq = platform_get_irq(pdev, 0);
if (parent_irq < 0)
return parent_irq;
girq = &ctrl->gc.irq;
gpio_irq_chip_set_chip(girq, &idt_gpio_irqchip);
girq->init_hw = idt_gpio_irq_init_hw;
girq->parent_handler = idt_gpio_dispatch;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, girq->num_parents,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = parent_irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
}
return devm_gpiochip_add_data(&pdev->dev, &ctrl->gc, ctrl);
}
static const struct of_device_id idt_gpio_of_match[] = {
{ .compatible = "idt,32434-gpio" },
{ }
};
MODULE_DEVICE_TABLE(of, idt_gpio_of_match);
static struct platform_driver idt_gpio_driver = {
.probe = idt_gpio_probe,
.driver = {
.name = "idt3243x-gpio",
.of_match_table = idt_gpio_of_match,
},
};
module_platform_driver(idt_gpio_driver);
MODULE_DESCRIPTION("IDT 79RC3243x GPIO/PIC Driver");
MODULE_AUTHOR("Thomas Bogendoerfer <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-idt3243x.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019, Linaro Limited
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#define WCD_PIN_MASK(p) BIT(p)
#define WCD_REG_DIR_CTL_OFFSET 0x42
#define WCD_REG_VAL_CTL_OFFSET 0x43
#define WCD934X_NPINS 5
struct wcd_gpio_data {
struct regmap *map;
struct gpio_chip chip;
};
static int wcd_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
{
struct wcd_gpio_data *data = gpiochip_get_data(chip);
unsigned int value;
int ret;
ret = regmap_read(data->map, WCD_REG_DIR_CTL_OFFSET, &value);
if (ret < 0)
return ret;
if (value & WCD_PIN_MASK(pin))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int wcd_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
{
struct wcd_gpio_data *data = gpiochip_get_data(chip);
return regmap_update_bits(data->map, WCD_REG_DIR_CTL_OFFSET,
WCD_PIN_MASK(pin), 0);
}
static int wcd_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
int val)
{
struct wcd_gpio_data *data = gpiochip_get_data(chip);
regmap_update_bits(data->map, WCD_REG_DIR_CTL_OFFSET,
WCD_PIN_MASK(pin), WCD_PIN_MASK(pin));
return regmap_update_bits(data->map, WCD_REG_VAL_CTL_OFFSET,
WCD_PIN_MASK(pin),
val ? WCD_PIN_MASK(pin) : 0);
}
static int wcd_gpio_get(struct gpio_chip *chip, unsigned int pin)
{
struct wcd_gpio_data *data = gpiochip_get_data(chip);
unsigned int value;
regmap_read(data->map, WCD_REG_VAL_CTL_OFFSET, &value);
return !!(value & WCD_PIN_MASK(pin));
}
static void wcd_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
{
struct wcd_gpio_data *data = gpiochip_get_data(chip);
regmap_update_bits(data->map, WCD_REG_VAL_CTL_OFFSET,
WCD_PIN_MASK(pin), val ? WCD_PIN_MASK(pin) : 0);
}
static int wcd_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct wcd_gpio_data *data;
struct gpio_chip *chip;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->map = dev_get_regmap(dev->parent, NULL);
if (!data->map) {
dev_err(dev, "%s: failed to get regmap\n", __func__);
return -EINVAL;
}
chip = &data->chip;
chip->direction_input = wcd_gpio_direction_input;
chip->direction_output = wcd_gpio_direction_output;
chip->get_direction = wcd_gpio_get_direction;
chip->get = wcd_gpio_get;
chip->set = wcd_gpio_set;
chip->parent = dev;
chip->base = -1;
chip->ngpio = WCD934X_NPINS;
chip->label = dev_name(dev);
chip->can_sleep = false;
return devm_gpiochip_add_data(dev, chip, data);
}
static const struct of_device_id wcd_gpio_of_match[] = {
{ .compatible = "qcom,wcd9340-gpio" },
{ .compatible = "qcom,wcd9341-gpio" },
{ }
};
MODULE_DEVICE_TABLE(of, wcd_gpio_of_match);
static struct platform_driver wcd_gpio_driver = {
.driver = {
.name = "wcd934x-gpio",
.of_match_table = wcd_gpio_of_match,
},
.probe = wcd_gpio_probe,
};
module_platform_driver(wcd_gpio_driver);
MODULE_DESCRIPTION("Qualcomm Technologies, Inc WCD GPIO control driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-wcd934x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for the Diolan DLN-2 USB-GPIO adapter
*
* Copyright (c) 2014 Intel Corporation
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/mfd/dln2.h>
#define DLN2_GPIO_ID 0x01
#define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID)
#define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID)
#define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID)
#define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID)
#define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID)
#define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID)
#define DLN2_GPIO_EVENT_NONE 0
#define DLN2_GPIO_EVENT_CHANGE 1
#define DLN2_GPIO_EVENT_LVL_HIGH 2
#define DLN2_GPIO_EVENT_LVL_LOW 3
#define DLN2_GPIO_EVENT_CHANGE_RISING 0x11
#define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21
#define DLN2_GPIO_EVENT_MASK 0x0F
#define DLN2_GPIO_MAX_PINS 32
struct dln2_gpio {
struct platform_device *pdev;
struct gpio_chip gpio;
/*
* Cache pin direction to save us one transfer, since the hardware has
* separate commands to read the in and out values.
*/
DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
/* active IRQs - not synced to hardware */
DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS);
/* active IRQS - synced to hardware */
DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS);
int irq_type[DLN2_GPIO_MAX_PINS];
struct mutex irq_lock;
};
struct dln2_gpio_pin {
__le16 pin;
};
struct dln2_gpio_pin_val {
__le16 pin __packed;
u8 value;
};
static int dln2_gpio_get_pin_count(struct platform_device *pdev)
{
int ret;
__le16 count;
int len = sizeof(count);
ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
if (ret < 0)
return ret;
if (len < sizeof(count))
return -EPROTO;
return le16_to_cpu(count);
}
static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
{
struct dln2_gpio_pin req = {
.pin = cpu_to_le16(pin),
};
return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
}
static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
{
int ret;
struct dln2_gpio_pin req = {
.pin = cpu_to_le16(pin),
};
struct dln2_gpio_pin_val rsp;
int len = sizeof(rsp);
ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
if (ret < 0)
return ret;
if (len < sizeof(rsp) || req.pin != rsp.pin)
return -EPROTO;
return rsp.value;
}
static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
{
int ret;
ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
if (ret < 0)
return ret;
return !!ret;
}
static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
{
int ret;
ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
if (ret < 0)
return ret;
return !!ret;
}
static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
unsigned int pin, int value)
{
struct dln2_gpio_pin_val req = {
.pin = cpu_to_le16(pin),
.value = value,
};
return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
sizeof(req));
}
#define DLN2_GPIO_DIRECTION_IN 0
#define DLN2_GPIO_DIRECTION_OUT 1
static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct dln2_gpio *dln2 = gpiochip_get_data(chip);
struct dln2_gpio_pin req = {
.pin = cpu_to_le16(offset),
};
struct dln2_gpio_pin_val rsp;
int len = sizeof(rsp);
int ret;
ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
if (ret < 0)
return ret;
/* cache the pin direction */
ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
&req, sizeof(req), &rsp, &len);
if (ret < 0)
return ret;
if (len < sizeof(rsp) || req.pin != rsp.pin) {
ret = -EPROTO;
goto out_disable;
}
switch (rsp.value) {
case DLN2_GPIO_DIRECTION_IN:
clear_bit(offset, dln2->output_enabled);
return 0;
case DLN2_GPIO_DIRECTION_OUT:
set_bit(offset, dln2->output_enabled);
return 0;
default:
ret = -EPROTO;
goto out_disable;
}
out_disable:
dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
return ret;
}
static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
{
struct dln2_gpio *dln2 = gpiochip_get_data(chip);
dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
}
static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
struct dln2_gpio *dln2 = gpiochip_get_data(chip);
if (test_bit(offset, dln2->output_enabled))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct dln2_gpio *dln2 = gpiochip_get_data(chip);
int dir;
dir = dln2_gpio_get_direction(chip, offset);
if (dir < 0)
return dir;
if (dir == GPIO_LINE_DIRECTION_IN)
return dln2_gpio_pin_get_in_val(dln2, offset);
return dln2_gpio_pin_get_out_val(dln2, offset);
}
static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct dln2_gpio *dln2 = gpiochip_get_data(chip);
dln2_gpio_pin_set_out_val(dln2, offset, value);
}
static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
unsigned dir)
{
struct dln2_gpio *dln2 = gpiochip_get_data(chip);
struct dln2_gpio_pin_val req = {
.pin = cpu_to_le16(offset),
.value = dir,
};
int ret;
ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
&req, sizeof(req));
if (ret < 0)
return ret;
if (dir == DLN2_GPIO_DIRECTION_OUT)
set_bit(offset, dln2->output_enabled);
else
clear_bit(offset, dln2->output_enabled);
return ret;
}
static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
}
static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
struct dln2_gpio *dln2 = gpiochip_get_data(chip);
int ret;
ret = dln2_gpio_pin_set_out_val(dln2, offset, value);
if (ret < 0)
return ret;
return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
}
static int dln2_gpio_set_config(struct gpio_chip *chip, unsigned offset,
unsigned long config)
{
struct dln2_gpio *dln2 = gpiochip_get_data(chip);
__le32 duration;
if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
return -ENOTSUPP;
duration = cpu_to_le32(pinconf_to_config_argument(config));
return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
&duration, sizeof(duration));
}
static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
unsigned type, unsigned period)
{
struct {
__le16 pin;
u8 type;
__le16 period;
} __packed req = {
.pin = cpu_to_le16(pin),
.type = type,
.period = cpu_to_le16(period),
};
return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
&req, sizeof(req));
}
static void dln2_irq_unmask(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct dln2_gpio *dln2 = gpiochip_get_data(gc);
int pin = irqd_to_hwirq(irqd);
gpiochip_enable_irq(gc, pin);
set_bit(pin, dln2->unmasked_irqs);
}
static void dln2_irq_mask(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct dln2_gpio *dln2 = gpiochip_get_data(gc);
int pin = irqd_to_hwirq(irqd);
clear_bit(pin, dln2->unmasked_irqs);
gpiochip_disable_irq(gc, pin);
}
static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct dln2_gpio *dln2 = gpiochip_get_data(gc);
int pin = irqd_to_hwirq(irqd);
switch (type) {
case IRQ_TYPE_LEVEL_HIGH:
dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW;
break;
case IRQ_TYPE_EDGE_BOTH:
dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE;
break;
case IRQ_TYPE_EDGE_RISING:
dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING;
break;
default:
return -EINVAL;
}
return 0;
}
static void dln2_irq_bus_lock(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct dln2_gpio *dln2 = gpiochip_get_data(gc);
mutex_lock(&dln2->irq_lock);
}
static void dln2_irq_bus_unlock(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct dln2_gpio *dln2 = gpiochip_get_data(gc);
int pin = irqd_to_hwirq(irqd);
int enabled, unmasked;
unsigned type;
int ret;
enabled = test_bit(pin, dln2->enabled_irqs);
unmasked = test_bit(pin, dln2->unmasked_irqs);
if (enabled != unmasked) {
if (unmasked) {
type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK;
set_bit(pin, dln2->enabled_irqs);
} else {
type = DLN2_GPIO_EVENT_NONE;
clear_bit(pin, dln2->enabled_irqs);
}
ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0);
if (ret)
dev_err(dln2->gpio.parent, "failed to set event\n");
}
mutex_unlock(&dln2->irq_lock);
}
static const struct irq_chip dln2_irqchip = {
.name = "dln2-irq",
.irq_mask = dln2_irq_mask,
.irq_unmask = dln2_irq_unmask,
.irq_set_type = dln2_irq_set_type,
.irq_bus_lock = dln2_irq_bus_lock,
.irq_bus_sync_unlock = dln2_irq_bus_unlock,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
const void *data, int len)
{
int pin, ret;
const struct {
__le16 count;
__u8 type;
__le16 pin;
__u8 value;
} __packed *event = data;
struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
if (len < sizeof(*event)) {
dev_err(dln2->gpio.parent, "short event message\n");
return;
}
pin = le16_to_cpu(event->pin);
if (pin >= dln2->gpio.ngpio) {
dev_err(dln2->gpio.parent, "out of bounds pin %d\n", pin);
return;
}
switch (dln2->irq_type[pin]) {
case DLN2_GPIO_EVENT_CHANGE_RISING:
if (!event->value)
return;
break;
case DLN2_GPIO_EVENT_CHANGE_FALLING:
if (event->value)
return;
break;
}
ret = generic_handle_domain_irq(dln2->gpio.irq.domain, pin);
if (unlikely(ret))
dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
}
static int dln2_gpio_probe(struct platform_device *pdev)
{
struct dln2_gpio *dln2;
struct device *dev = &pdev->dev;
struct gpio_irq_chip *girq;
int pins;
int ret;
pins = dln2_gpio_get_pin_count(pdev);
if (pins < 0) {
dev_err(dev, "failed to get pin count: %d\n", pins);
return pins;
}
if (pins > DLN2_GPIO_MAX_PINS) {
pins = DLN2_GPIO_MAX_PINS;
dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
}
dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
if (!dln2)
return -ENOMEM;
mutex_init(&dln2->irq_lock);
dln2->pdev = pdev;
dln2->gpio.label = "dln2";
dln2->gpio.parent = dev;
dln2->gpio.owner = THIS_MODULE;
dln2->gpio.base = -1;
dln2->gpio.ngpio = pins;
dln2->gpio.can_sleep = true;
dln2->gpio.set = dln2_gpio_set;
dln2->gpio.get = dln2_gpio_get;
dln2->gpio.request = dln2_gpio_request;
dln2->gpio.free = dln2_gpio_free;
dln2->gpio.get_direction = dln2_gpio_get_direction;
dln2->gpio.direction_input = dln2_gpio_direction_input;
dln2->gpio.direction_output = dln2_gpio_direction_output;
dln2->gpio.set_config = dln2_gpio_set_config;
girq = &dln2->gpio.irq;
gpio_irq_chip_set_chip(girq, &dln2_irqchip);
/* The event comes from the outside so no parent handler */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
platform_set_drvdata(pdev, dln2);
ret = devm_gpiochip_add_data(dev, &dln2->gpio, dln2);
if (ret < 0) {
dev_err(dev, "failed to add gpio chip: %d\n", ret);
return ret;
}
ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
dln2_gpio_event);
if (ret) {
dev_err(dev, "failed to register event cb: %d\n", ret);
return ret;
}
return 0;
}
static int dln2_gpio_remove(struct platform_device *pdev)
{
dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
return 0;
}
static struct platform_driver dln2_gpio_driver = {
.driver.name = "dln2-gpio",
.probe = dln2_gpio_probe,
.remove = dln2_gpio_remove,
};
module_platform_driver(dln2_gpio_driver);
MODULE_AUTHOR("Daniel Baluta <[email protected]");
MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dln2-gpio");
| linux-master | drivers/gpio/gpio-dln2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Spreadtrum Communications Inc.
* Copyright (C) 2018 Linaro Ltd.
*/
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
/* EIC registers definition */
#define SPRD_PMIC_EIC_DATA 0x0
#define SPRD_PMIC_EIC_DMSK 0x4
#define SPRD_PMIC_EIC_IEV 0x14
#define SPRD_PMIC_EIC_IE 0x18
#define SPRD_PMIC_EIC_RIS 0x1c
#define SPRD_PMIC_EIC_MIS 0x20
#define SPRD_PMIC_EIC_IC 0x24
#define SPRD_PMIC_EIC_TRIG 0x28
#define SPRD_PMIC_EIC_CTRL0 0x40
/*
* The PMIC EIC controller only has one bank, and each bank now can contain
* 16 EICs.
*/
#define SPRD_PMIC_EIC_PER_BANK_NR 16
#define SPRD_PMIC_EIC_NR SPRD_PMIC_EIC_PER_BANK_NR
#define SPRD_PMIC_EIC_DATA_MASK GENMASK(15, 0)
#define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
#define SPRD_PMIC_EIC_DBNC_MASK GENMASK(11, 0)
/*
* These registers are modified under the irq bus lock and cached to avoid
* unnecessary writes in bus_sync_unlock.
*/
enum {
REG_IEV,
REG_IE,
REG_TRIG,
CACHE_NR_REGS
};
/**
* struct sprd_pmic_eic - PMIC EIC controller
* @chip: the gpio_chip structure.
* @map: the regmap from the parent device.
* @offset: the EIC controller's offset address of the PMIC.
* @reg: the array to cache the EIC registers.
* @buslock: for bus lock/sync and unlock.
* @irq: the interrupt number of the PMIC EIC conteroller.
*/
struct sprd_pmic_eic {
struct gpio_chip chip;
struct regmap *map;
u32 offset;
u8 reg[CACHE_NR_REGS];
struct mutex buslock;
int irq;
};
static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset,
u16 reg, unsigned int val)
{
struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
u32 shift = SPRD_PMIC_EIC_BIT(offset);
regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg,
BIT(shift), val << shift);
}
static int sprd_pmic_eic_read(struct gpio_chip *chip, unsigned int offset,
u16 reg)
{
struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
u32 value;
int ret;
ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
if (ret)
return ret;
return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset)));
}
static int sprd_pmic_eic_request(struct gpio_chip *chip, unsigned int offset)
{
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 1);
return 0;
}
static void sprd_pmic_eic_free(struct gpio_chip *chip, unsigned int offset)
{
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 0);
}
static int sprd_pmic_eic_get(struct gpio_chip *chip, unsigned int offset)
{
return sprd_pmic_eic_read(chip, offset, SPRD_PMIC_EIC_DATA);
}
static int sprd_pmic_eic_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
/* EICs are always input, nothing need to do here. */
return 0;
}
static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
/* EICs are always input, nothing need to do here. */
}
static int sprd_pmic_eic_set_debounce(struct gpio_chip *chip,
unsigned int offset,
unsigned int debounce)
{
struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
u32 reg, value;
int ret;
reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4;
ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
if (ret)
return ret;
value &= ~SPRD_PMIC_EIC_DBNC_MASK;
value |= (debounce / 1000) & SPRD_PMIC_EIC_DBNC_MASK;
return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value);
}
static int sprd_pmic_eic_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
unsigned long param = pinconf_to_config_param(config);
u32 arg = pinconf_to_config_argument(config);
if (param == PIN_CONFIG_INPUT_DEBOUNCE)
return sprd_pmic_eic_set_debounce(chip, offset, arg);
return -ENOTSUPP;
}
static void sprd_pmic_eic_irq_mask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
u32 offset = irqd_to_hwirq(data);
pmic_eic->reg[REG_IE] = 0;
pmic_eic->reg[REG_TRIG] = 0;
gpiochip_disable_irq(chip, offset);
}
static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
u32 offset = irqd_to_hwirq(data);
gpiochip_enable_irq(chip, offset);
pmic_eic->reg[REG_IE] = 1;
pmic_eic->reg[REG_TRIG] = 1;
}
static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
unsigned int flow_type)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
switch (flow_type) {
case IRQ_TYPE_LEVEL_HIGH:
pmic_eic->reg[REG_IEV] = 1;
break;
case IRQ_TYPE_LEVEL_LOW:
pmic_eic->reg[REG_IEV] = 0;
break;
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_EDGE_BOTH:
/*
* Will set the trigger level according to current EIC level
* in irq_bus_sync_unlock() interface, so here nothing to do.
*/
break;
default:
return -ENOTSUPP;
}
return 0;
}
static void sprd_pmic_eic_bus_lock(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
mutex_lock(&pmic_eic->buslock);
}
static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
u32 trigger = irqd_get_trigger_type(data);
u32 offset = irqd_to_hwirq(data);
int state;
/* Set irq type */
if (trigger & IRQ_TYPE_EDGE_BOTH) {
state = sprd_pmic_eic_get(chip, offset);
if (state)
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
else
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
} else {
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
pmic_eic->reg[REG_IEV]);
}
/* Set irq unmask */
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
pmic_eic->reg[REG_IE]);
/* Generate trigger start pulse for debounce EIC */
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
pmic_eic->reg[REG_TRIG]);
mutex_unlock(&pmic_eic->buslock);
}
static void sprd_pmic_eic_toggle_trigger(struct gpio_chip *chip,
unsigned int irq, unsigned int offset)
{
u32 trigger = irq_get_trigger_type(irq);
int state, post_state;
if (!(trigger & IRQ_TYPE_EDGE_BOTH))
return;
state = sprd_pmic_eic_get(chip, offset);
retry:
if (state)
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
else
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
post_state = sprd_pmic_eic_get(chip, offset);
if (state != post_state) {
dev_warn(chip->parent, "PMIC EIC level was changed.\n");
state = post_state;
goto retry;
}
/* Set irq unmask */
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 1);
/* Generate trigger start pulse for debounce EIC */
sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 1);
}
static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data)
{
struct sprd_pmic_eic *pmic_eic = data;
struct gpio_chip *chip = &pmic_eic->chip;
unsigned long status;
u32 n, girq, val;
int ret;
ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS,
&val);
if (ret)
return IRQ_RETVAL(ret);
status = val & SPRD_PMIC_EIC_DATA_MASK;
for_each_set_bit(n, &status, chip->ngpio) {
/* Clear the interrupt */
sprd_pmic_eic_update(chip, n, SPRD_PMIC_EIC_IC, 1);
girq = irq_find_mapping(chip->irq.domain, n);
handle_nested_irq(girq);
/*
* The PMIC EIC can only support level trigger, so we can
* toggle the level trigger to emulate the edge trigger.
*/
sprd_pmic_eic_toggle_trigger(chip, girq, n);
}
return IRQ_HANDLED;
}
static const struct irq_chip pmic_eic_irq_chip = {
.name = "sprd-pmic-eic",
.irq_mask = sprd_pmic_eic_irq_mask,
.irq_unmask = sprd_pmic_eic_irq_unmask,
.irq_set_type = sprd_pmic_eic_irq_set_type,
.irq_bus_lock = sprd_pmic_eic_bus_lock,
.irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock,
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int sprd_pmic_eic_probe(struct platform_device *pdev)
{
struct gpio_irq_chip *irq;
struct sprd_pmic_eic *pmic_eic;
int ret;
pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL);
if (!pmic_eic)
return -ENOMEM;
mutex_init(&pmic_eic->buslock);
pmic_eic->irq = platform_get_irq(pdev, 0);
if (pmic_eic->irq < 0)
return pmic_eic->irq;
pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL);
if (!pmic_eic->map)
return -ENODEV;
ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset);
if (ret) {
dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n");
return ret;
}
ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL,
sprd_pmic_eic_irq_handler,
IRQF_ONESHOT | IRQF_NO_SUSPEND,
dev_name(&pdev->dev), pmic_eic);
if (ret) {
dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n");
return ret;
}
pmic_eic->chip.label = dev_name(&pdev->dev);
pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR;
pmic_eic->chip.base = -1;
pmic_eic->chip.parent = &pdev->dev;
pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input;
pmic_eic->chip.request = sprd_pmic_eic_request;
pmic_eic->chip.free = sprd_pmic_eic_free;
pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
pmic_eic->chip.set = sprd_pmic_eic_set;
pmic_eic->chip.get = sprd_pmic_eic_get;
irq = &pmic_eic->chip.irq;
gpio_irq_chip_set_chip(irq, &pmic_eic_irq_chip);
irq->threaded = true;
ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic);
if (ret < 0) {
dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
return ret;
}
return 0;
}
static const struct of_device_id sprd_pmic_eic_of_match[] = {
{ .compatible = "sprd,sc2731-eic", },
{ /* end of list */ }
};
MODULE_DEVICE_TABLE(of, sprd_pmic_eic_of_match);
static struct platform_driver sprd_pmic_eic_driver = {
.probe = sprd_pmic_eic_probe,
.driver = {
.name = "sprd-pmic-eic",
.of_match_table = sprd_pmic_eic_of_match,
},
};
module_platform_driver(sprd_pmic_eic_driver);
MODULE_DESCRIPTION("Spreadtrum PMIC EIC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-pmic-eic-sprd.c |
// SPDX-License-Identifier: GPL-2.0
/*
* GPIO latch driver
*
* Copyright (C) 2022 Sascha Hauer <[email protected]>
*
* This driver implements a GPIO (or better GPO as there is no input)
* multiplexer based on latches like this:
*
* CLK0 ----------------------. ,--------.
* CLK1 -------------------. `--------|> #0 |
* | | |
* OUT0 ----------------+--|-----------|D0 Q0|-----|<
* OUT1 --------------+-|--|-----------|D1 Q1|-----|<
* OUT2 ------------+-|-|--|-----------|D2 Q2|-----|<
* OUT3 ----------+-|-|-|--|-----------|D3 Q3|-----|<
* OUT4 --------+-|-|-|-|--|-----------|D4 Q4|-----|<
* OUT5 ------+-|-|-|-|-|--|-----------|D5 Q5|-----|<
* OUT6 ----+-|-|-|-|-|-|--|-----------|D6 Q6|-----|<
* OUT7 --+-|-|-|-|-|-|-|--|-----------|D7 Q7|-----|<
* | | | | | | | | | `--------'
* | | | | | | | | |
* | | | | | | | | | ,--------.
* | | | | | | | | `-----------|> #1 |
* | | | | | | | | | |
* | | | | | | | `--------------|D0 Q0|-----|<
* | | | | | | `----------------|D1 Q1|-----|<
* | | | | | `------------------|D2 Q2|-----|<
* | | | | `--------------------|D3 Q3|-----|<
* | | | `----------------------|D4 Q4|-----|<
* | | `------------------------|D5 Q5|-----|<
* | `--------------------------|D6 Q6|-----|<
* `----------------------------|D7 Q7|-----|<
* `--------'
*
* The above is just an example. The actual number of number of latches and
* the number of inputs per latch is derived from the number of GPIOs given
* in the corresponding device tree properties.
*/
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include "gpiolib.h"
struct gpio_latch_priv {
struct gpio_chip gc;
struct gpio_descs *clk_gpios;
struct gpio_descs *latched_gpios;
int n_latched_gpios;
unsigned int setup_duration_ns;
unsigned int clock_duration_ns;
unsigned long *shadow;
/*
* Depending on whether any of the underlying GPIOs may sleep we either
* use a mutex or a spinlock to protect our shadow map.
*/
union {
struct mutex mutex; /* protects @shadow */
spinlock_t spinlock; /* protects @shadow */
};
};
static int gpio_latch_get_direction(struct gpio_chip *gc, unsigned int offset)
{
return GPIO_LINE_DIRECTION_OUT;
}
static void gpio_latch_set_unlocked(struct gpio_latch_priv *priv,
void (*set)(struct gpio_desc *desc, int value),
unsigned int offset, bool val)
{
int latch = offset / priv->n_latched_gpios;
int i;
assign_bit(offset, priv->shadow, val);
for (i = 0; i < priv->n_latched_gpios; i++)
set(priv->latched_gpios->desc[i],
test_bit(latch * priv->n_latched_gpios + i, priv->shadow));
ndelay(priv->setup_duration_ns);
set(priv->clk_gpios->desc[latch], 1);
ndelay(priv->clock_duration_ns);
set(priv->clk_gpios->desc[latch], 0);
}
static void gpio_latch_set(struct gpio_chip *gc, unsigned int offset, int val)
{
struct gpio_latch_priv *priv = gpiochip_get_data(gc);
unsigned long flags;
spin_lock_irqsave(&priv->spinlock, flags);
gpio_latch_set_unlocked(priv, gpiod_set_value, offset, val);
spin_unlock_irqrestore(&priv->spinlock, flags);
}
static void gpio_latch_set_can_sleep(struct gpio_chip *gc, unsigned int offset, int val)
{
struct gpio_latch_priv *priv = gpiochip_get_data(gc);
mutex_lock(&priv->mutex);
gpio_latch_set_unlocked(priv, gpiod_set_value_cansleep, offset, val);
mutex_unlock(&priv->mutex);
}
static bool gpio_latch_can_sleep(struct gpio_latch_priv *priv, unsigned int n_latches)
{
int i;
for (i = 0; i < n_latches; i++)
if (gpiod_cansleep(priv->clk_gpios->desc[i]))
return true;
for (i = 0; i < priv->n_latched_gpios; i++)
if (gpiod_cansleep(priv->latched_gpios->desc[i]))
return true;
return false;
}
/*
* Some value which is still acceptable to delay in atomic context.
* If we need to go higher we might have to switch to usleep_range(),
* but that cannot ne used in atomic context and the driver would have
* to be adjusted to support that.
*/
#define DURATION_NS_MAX 5000
static int gpio_latch_probe(struct platform_device *pdev)
{
struct gpio_latch_priv *priv;
unsigned int n_latches;
struct device_node *np = pdev->dev.of_node;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->clk_gpios = devm_gpiod_get_array(&pdev->dev, "clk", GPIOD_OUT_LOW);
if (IS_ERR(priv->clk_gpios))
return PTR_ERR(priv->clk_gpios);
priv->latched_gpios = devm_gpiod_get_array(&pdev->dev, "latched", GPIOD_OUT_LOW);
if (IS_ERR(priv->latched_gpios))
return PTR_ERR(priv->latched_gpios);
n_latches = priv->clk_gpios->ndescs;
priv->n_latched_gpios = priv->latched_gpios->ndescs;
priv->shadow = devm_bitmap_zalloc(&pdev->dev, n_latches * priv->n_latched_gpios,
GFP_KERNEL);
if (!priv->shadow)
return -ENOMEM;
if (gpio_latch_can_sleep(priv, n_latches)) {
priv->gc.can_sleep = true;
priv->gc.set = gpio_latch_set_can_sleep;
mutex_init(&priv->mutex);
} else {
priv->gc.can_sleep = false;
priv->gc.set = gpio_latch_set;
spin_lock_init(&priv->spinlock);
}
of_property_read_u32(np, "setup-duration-ns", &priv->setup_duration_ns);
if (priv->setup_duration_ns > DURATION_NS_MAX) {
dev_warn(&pdev->dev, "setup-duration-ns too high, limit to %d\n",
DURATION_NS_MAX);
priv->setup_duration_ns = DURATION_NS_MAX;
}
of_property_read_u32(np, "clock-duration-ns", &priv->clock_duration_ns);
if (priv->clock_duration_ns > DURATION_NS_MAX) {
dev_warn(&pdev->dev, "clock-duration-ns too high, limit to %d\n",
DURATION_NS_MAX);
priv->clock_duration_ns = DURATION_NS_MAX;
}
priv->gc.get_direction = gpio_latch_get_direction;
priv->gc.ngpio = n_latches * priv->n_latched_gpios;
priv->gc.owner = THIS_MODULE;
priv->gc.base = -1;
priv->gc.parent = &pdev->dev;
platform_set_drvdata(pdev, priv);
return devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
}
static const struct of_device_id gpio_latch_ids[] = {
{
.compatible = "gpio-latch",
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, gpio_latch_ids);
static struct platform_driver gpio_latch_driver = {
.driver = {
.name = "gpio-latch",
.of_match_table = gpio_latch_ids,
},
.probe = gpio_latch_probe,
};
module_platform_driver(gpio_latch_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sascha Hauer <[email protected]>");
MODULE_DESCRIPTION("GPIO latch driver");
| linux-master | drivers/gpio/gpio-latch.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Raspberry Pi 3 expander GPIO driver
*
* Uses the firmware mailbox service to communicate with the
* GPIO expander on the VPU.
*
* Copyright (C) 2017 Raspberry Pi Trading Ltd.
*/
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <soc/bcm2835/raspberrypi-firmware.h>
#define MODULE_NAME "raspberrypi-exp-gpio"
#define NUM_GPIO 8
#define RPI_EXP_GPIO_BASE 128
#define RPI_EXP_GPIO_DIR_IN 0
#define RPI_EXP_GPIO_DIR_OUT 1
struct rpi_exp_gpio {
struct gpio_chip gc;
struct rpi_firmware *fw;
};
/* VC4 firmware mailbox interface data structures */
struct gpio_set_config {
u32 gpio;
u32 direction;
u32 polarity;
u32 term_en;
u32 term_pull_up;
u32 state;
};
struct gpio_get_config {
u32 gpio;
u32 direction;
u32 polarity;
u32 term_en;
u32 term_pull_up;
};
struct gpio_get_set_state {
u32 gpio;
u32 state;
};
static int rpi_exp_gpio_get_polarity(struct gpio_chip *gc, unsigned int off)
{
struct rpi_exp_gpio *gpio;
struct gpio_get_config get;
int ret;
gpio = gpiochip_get_data(gc);
get.gpio = off + RPI_EXP_GPIO_BASE; /* GPIO to update */
ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_GET_GPIO_CONFIG,
&get, sizeof(get));
if (ret || get.gpio != 0) {
dev_err(gc->parent, "Failed to get GPIO %u config (%d %x)\n",
off, ret, get.gpio);
return ret ? ret : -EIO;
}
return get.polarity;
}
static int rpi_exp_gpio_dir_in(struct gpio_chip *gc, unsigned int off)
{
struct rpi_exp_gpio *gpio;
struct gpio_set_config set_in;
int ret;
gpio = gpiochip_get_data(gc);
set_in.gpio = off + RPI_EXP_GPIO_BASE; /* GPIO to update */
set_in.direction = RPI_EXP_GPIO_DIR_IN;
set_in.term_en = 0; /* termination disabled */
set_in.term_pull_up = 0; /* n/a as termination disabled */
set_in.state = 0; /* n/a as configured as an input */
ret = rpi_exp_gpio_get_polarity(gc, off);
if (ret < 0)
return ret;
set_in.polarity = ret; /* Retain existing setting */
ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_SET_GPIO_CONFIG,
&set_in, sizeof(set_in));
if (ret || set_in.gpio != 0) {
dev_err(gc->parent, "Failed to set GPIO %u to input (%d %x)\n",
off, ret, set_in.gpio);
return ret ? ret : -EIO;
}
return 0;
}
static int rpi_exp_gpio_dir_out(struct gpio_chip *gc, unsigned int off, int val)
{
struct rpi_exp_gpio *gpio;
struct gpio_set_config set_out;
int ret;
gpio = gpiochip_get_data(gc);
set_out.gpio = off + RPI_EXP_GPIO_BASE; /* GPIO to update */
set_out.direction = RPI_EXP_GPIO_DIR_OUT;
set_out.term_en = 0; /* n/a as an output */
set_out.term_pull_up = 0; /* n/a as termination disabled */
set_out.state = val; /* Output state */
ret = rpi_exp_gpio_get_polarity(gc, off);
if (ret < 0)
return ret;
set_out.polarity = ret; /* Retain existing setting */
ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_SET_GPIO_CONFIG,
&set_out, sizeof(set_out));
if (ret || set_out.gpio != 0) {
dev_err(gc->parent, "Failed to set GPIO %u to output (%d %x)\n",
off, ret, set_out.gpio);
return ret ? ret : -EIO;
}
return 0;
}
static int rpi_exp_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
{
struct rpi_exp_gpio *gpio;
struct gpio_get_config get;
int ret;
gpio = gpiochip_get_data(gc);
get.gpio = off + RPI_EXP_GPIO_BASE; /* GPIO to update */
ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_GET_GPIO_CONFIG,
&get, sizeof(get));
if (ret || get.gpio != 0) {
dev_err(gc->parent,
"Failed to get GPIO %u config (%d %x)\n", off, ret,
get.gpio);
return ret ? ret : -EIO;
}
if (get.direction)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int rpi_exp_gpio_get(struct gpio_chip *gc, unsigned int off)
{
struct rpi_exp_gpio *gpio;
struct gpio_get_set_state get;
int ret;
gpio = gpiochip_get_data(gc);
get.gpio = off + RPI_EXP_GPIO_BASE; /* GPIO to update */
get.state = 0; /* storage for returned value */
ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_GET_GPIO_STATE,
&get, sizeof(get));
if (ret || get.gpio != 0) {
dev_err(gc->parent,
"Failed to get GPIO %u state (%d %x)\n", off, ret,
get.gpio);
return ret ? ret : -EIO;
}
return !!get.state;
}
static void rpi_exp_gpio_set(struct gpio_chip *gc, unsigned int off, int val)
{
struct rpi_exp_gpio *gpio;
struct gpio_get_set_state set;
int ret;
gpio = gpiochip_get_data(gc);
set.gpio = off + RPI_EXP_GPIO_BASE; /* GPIO to update */
set.state = val; /* Output state */
ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_SET_GPIO_STATE,
&set, sizeof(set));
if (ret || set.gpio != 0)
dev_err(gc->parent,
"Failed to set GPIO %u state (%d %x)\n", off, ret,
set.gpio);
}
static int rpi_exp_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *fw_node;
struct rpi_firmware *fw;
struct rpi_exp_gpio *rpi_gpio;
fw_node = of_get_parent(np);
if (!fw_node) {
dev_err(dev, "Missing firmware node\n");
return -ENOENT;
}
fw = devm_rpi_firmware_get(&pdev->dev, fw_node);
of_node_put(fw_node);
if (!fw)
return -EPROBE_DEFER;
rpi_gpio = devm_kzalloc(dev, sizeof(*rpi_gpio), GFP_KERNEL);
if (!rpi_gpio)
return -ENOMEM;
rpi_gpio->fw = fw;
rpi_gpio->gc.parent = dev;
rpi_gpio->gc.label = MODULE_NAME;
rpi_gpio->gc.owner = THIS_MODULE;
rpi_gpio->gc.base = -1;
rpi_gpio->gc.ngpio = NUM_GPIO;
rpi_gpio->gc.direction_input = rpi_exp_gpio_dir_in;
rpi_gpio->gc.direction_output = rpi_exp_gpio_dir_out;
rpi_gpio->gc.get_direction = rpi_exp_gpio_get_direction;
rpi_gpio->gc.get = rpi_exp_gpio_get;
rpi_gpio->gc.set = rpi_exp_gpio_set;
rpi_gpio->gc.can_sleep = true;
return devm_gpiochip_add_data(dev, &rpi_gpio->gc, rpi_gpio);
}
static const struct of_device_id rpi_exp_gpio_ids[] = {
{ .compatible = "raspberrypi,firmware-gpio" },
{ }
};
MODULE_DEVICE_TABLE(of, rpi_exp_gpio_ids);
static struct platform_driver rpi_exp_gpio_driver = {
.driver = {
.name = MODULE_NAME,
.of_match_table = rpi_exp_gpio_ids,
},
.probe = rpi_exp_gpio_probe,
};
module_platform_driver(rpi_exp_gpio_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Dave Stevenson <[email protected]>");
MODULE_DESCRIPTION("Raspberry Pi 3 expander GPIO driver");
MODULE_ALIAS("platform:rpi-exp-gpio");
| linux-master | drivers/gpio/gpio-raspberrypi-exp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MPC52xx gpio driver
*
* Copyright (c) 2008 Sascha Hauer <[email protected]>, Pengutronix
*/
#include <linux/of.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/gpio/legacy-of-mm-gpiochip.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <asm/mpc52xx.h>
#include <sysdev/fsl_soc.h>
static DEFINE_SPINLOCK(gpio_lock);
struct mpc52xx_gpiochip {
struct of_mm_gpio_chip mmchip;
unsigned int shadow_dvo;
unsigned int shadow_gpioe;
unsigned int shadow_ddr;
};
/*
* GPIO LIB API implementation for wakeup GPIOs.
*
* There's a maximum of 8 wakeup GPIOs. Which of these are available
* for use depends on your board setup.
*
* 0 -> GPIO_WKUP_7
* 1 -> GPIO_WKUP_6
* 2 -> PSC6_1
* 3 -> PSC6_0
* 4 -> ETH_17
* 5 -> PSC3_9
* 6 -> PSC2_4
* 7 -> PSC1_4
*
*/
static int mpc52xx_wkup_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
unsigned int ret;
ret = (in_8(®s->wkup_ival) >> (7 - gpio)) & 1;
pr_debug("%s: gpio: %d ret: %d\n", __func__, gpio, ret);
return ret;
}
static inline void
__mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
if (val)
chip->shadow_dvo |= 1 << (7 - gpio);
else
chip->shadow_dvo &= ~(1 << (7 - gpio));
out_8(®s->wkup_dvo, chip->shadow_dvo);
}
static void
mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
__mpc52xx_wkup_gpio_set(gc, gpio, val);
spin_unlock_irqrestore(&gpio_lock, flags);
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
}
static int mpc52xx_wkup_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
/* set the direction */
chip->shadow_ddr &= ~(1 << (7 - gpio));
out_8(®s->wkup_ddr, chip->shadow_ddr);
/* and enable the pin */
chip->shadow_gpioe |= 1 << (7 - gpio);
out_8(®s->wkup_gpioe, chip->shadow_gpioe);
spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
}
static int
mpc52xx_wkup_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
__mpc52xx_wkup_gpio_set(gc, gpio, val);
/* Then set direction */
chip->shadow_ddr |= 1 << (7 - gpio);
out_8(®s->wkup_ddr, chip->shadow_ddr);
/* Finally enable the pin */
chip->shadow_gpioe |= 1 << (7 - gpio);
out_8(®s->wkup_gpioe, chip->shadow_gpioe);
spin_unlock_irqrestore(&gpio_lock, flags);
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
return 0;
}
static int mpc52xx_wkup_gpiochip_probe(struct platform_device *ofdev)
{
struct mpc52xx_gpiochip *chip;
struct mpc52xx_gpio_wkup __iomem *regs;
struct gpio_chip *gc;
int ret;
chip = devm_kzalloc(&ofdev->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
platform_set_drvdata(ofdev, chip);
gc = &chip->mmchip.gc;
gc->ngpio = 8;
gc->direction_input = mpc52xx_wkup_gpio_dir_in;
gc->direction_output = mpc52xx_wkup_gpio_dir_out;
gc->get = mpc52xx_wkup_gpio_get;
gc->set = mpc52xx_wkup_gpio_set;
ret = of_mm_gpiochip_add_data(ofdev->dev.of_node, &chip->mmchip, chip);
if (ret)
return ret;
regs = chip->mmchip.regs;
chip->shadow_gpioe = in_8(®s->wkup_gpioe);
chip->shadow_ddr = in_8(®s->wkup_ddr);
chip->shadow_dvo = in_8(®s->wkup_dvo);
return 0;
}
static int mpc52xx_gpiochip_remove(struct platform_device *ofdev)
{
struct mpc52xx_gpiochip *chip = platform_get_drvdata(ofdev);
of_mm_gpiochip_remove(&chip->mmchip);
return 0;
}
static const struct of_device_id mpc52xx_wkup_gpiochip_match[] = {
{ .compatible = "fsl,mpc5200-gpio-wkup", },
{}
};
static struct platform_driver mpc52xx_wkup_gpiochip_driver = {
.driver = {
.name = "mpc5200-gpio-wkup",
.of_match_table = mpc52xx_wkup_gpiochip_match,
},
.probe = mpc52xx_wkup_gpiochip_probe,
.remove = mpc52xx_gpiochip_remove,
};
/*
* GPIO LIB API implementation for simple GPIOs
*
* There's a maximum of 32 simple GPIOs. Which of these are available
* for use depends on your board setup.
* The numbering reflects the bit numbering in the port registers:
*
* 0..1 > reserved
* 2..3 > IRDA
* 4..7 > ETHR
* 8..11 > reserved
* 12..15 > USB
* 16..17 > reserved
* 18..23 > PSC3
* 24..27 > PSC2
* 28..31 > PSC1
*/
static int mpc52xx_simple_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
unsigned int ret;
ret = (in_be32(®s->simple_ival) >> (31 - gpio)) & 1;
return ret;
}
static inline void
__mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
if (val)
chip->shadow_dvo |= 1 << (31 - gpio);
else
chip->shadow_dvo &= ~(1 << (31 - gpio));
out_be32(®s->simple_dvo, chip->shadow_dvo);
}
static void
mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
__mpc52xx_simple_gpio_set(gc, gpio, val);
spin_unlock_irqrestore(&gpio_lock, flags);
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
}
static int mpc52xx_simple_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
/* set the direction */
chip->shadow_ddr &= ~(1 << (31 - gpio));
out_be32(®s->simple_ddr, chip->shadow_ddr);
/* and enable the pin */
chip->shadow_gpioe |= 1 << (31 - gpio);
out_be32(®s->simple_gpioe, chip->shadow_gpioe);
spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
}
static int
mpc52xx_simple_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpiochip *chip = gpiochip_get_data(gc);
struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
/* First set initial value */
__mpc52xx_simple_gpio_set(gc, gpio, val);
/* Then set direction */
chip->shadow_ddr |= 1 << (31 - gpio);
out_be32(®s->simple_ddr, chip->shadow_ddr);
/* Finally enable the pin */
chip->shadow_gpioe |= 1 << (31 - gpio);
out_be32(®s->simple_gpioe, chip->shadow_gpioe);
spin_unlock_irqrestore(&gpio_lock, flags);
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
return 0;
}
static int mpc52xx_simple_gpiochip_probe(struct platform_device *ofdev)
{
struct mpc52xx_gpiochip *chip;
struct gpio_chip *gc;
struct mpc52xx_gpio __iomem *regs;
int ret;
chip = devm_kzalloc(&ofdev->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
platform_set_drvdata(ofdev, chip);
gc = &chip->mmchip.gc;
gc->ngpio = 32;
gc->direction_input = mpc52xx_simple_gpio_dir_in;
gc->direction_output = mpc52xx_simple_gpio_dir_out;
gc->get = mpc52xx_simple_gpio_get;
gc->set = mpc52xx_simple_gpio_set;
ret = of_mm_gpiochip_add_data(ofdev->dev.of_node, &chip->mmchip, chip);
if (ret)
return ret;
regs = chip->mmchip.regs;
chip->shadow_gpioe = in_be32(®s->simple_gpioe);
chip->shadow_ddr = in_be32(®s->simple_ddr);
chip->shadow_dvo = in_be32(®s->simple_dvo);
return 0;
}
static const struct of_device_id mpc52xx_simple_gpiochip_match[] = {
{ .compatible = "fsl,mpc5200-gpio", },
{}
};
static struct platform_driver mpc52xx_simple_gpiochip_driver = {
.driver = {
.name = "mpc5200-gpio",
.of_match_table = mpc52xx_simple_gpiochip_match,
},
.probe = mpc52xx_simple_gpiochip_probe,
.remove = mpc52xx_gpiochip_remove,
};
static struct platform_driver * const drivers[] = {
&mpc52xx_wkup_gpiochip_driver,
&mpc52xx_simple_gpiochip_driver,
};
static int __init mpc52xx_gpio_init(void)
{
return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
}
/* Make sure we get initialised before anyone else tries to use us */
subsys_initcall(mpc52xx_gpio_init);
static void __exit mpc52xx_gpio_exit(void)
{
platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
}
module_exit(mpc52xx_gpio_exit);
MODULE_DESCRIPTION("Freescale MPC52xx gpio driver");
MODULE_AUTHOR("Sascha Hauer <[email protected]");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-mpc5200.c |
// SPDX-License-Identifier: GPL-2.0
/*
* GPIO interface for Intel Sodaville SoCs.
*
* Copyright (c) 2010, 2011 Intel Corporation
*
* Author: Hans J. Koch <[email protected]>
*/
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of_irq.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#define DRV_NAME "sdv_gpio"
#define SDV_NUM_PUB_GPIOS 12
#define PCI_DEVICE_ID_SDV_GPIO 0x2e67
#define GPIO_BAR 0
#define GPOUTR 0x00
#define GPOER 0x04
#define GPINR 0x08
#define GPSTR 0x0c
#define GPIT1R0 0x10
#define GPIO_INT 0x14
#define GPIT1R1 0x18
#define GPMUXCTL 0x1c
struct sdv_gpio_chip_data {
int irq_base;
void __iomem *gpio_pub_base;
struct irq_domain *id;
struct irq_chip_generic *gc;
struct gpio_chip chip;
};
static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct sdv_gpio_chip_data *sd = gc->private;
void __iomem *type_reg;
u32 reg;
if (d->hwirq < 8)
type_reg = sd->gpio_pub_base + GPIT1R0;
else
type_reg = sd->gpio_pub_base + GPIT1R1;
reg = readl(type_reg);
switch (type) {
case IRQ_TYPE_LEVEL_HIGH:
reg &= ~BIT(4 * (d->hwirq % 8));
break;
case IRQ_TYPE_LEVEL_LOW:
reg |= BIT(4 * (d->hwirq % 8));
break;
default:
return -EINVAL;
}
writel(reg, type_reg);
return 0;
}
static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
{
struct sdv_gpio_chip_data *sd = data;
unsigned long irq_stat = readl(sd->gpio_pub_base + GPSTR);
int irq_bit;
irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
if (!irq_stat)
return IRQ_NONE;
for_each_set_bit(irq_bit, &irq_stat, 32)
generic_handle_domain_irq(sd->id, irq_bit);
return IRQ_HANDLED;
}
static int sdv_xlate(struct irq_domain *h, struct device_node *node,
const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
u32 *out_type)
{
u32 line, type;
if (node != irq_domain_get_of_node(h))
return -EINVAL;
if (intsize < 2)
return -EINVAL;
line = *intspec;
*out_hwirq = line;
intspec++;
type = *intspec;
switch (type) {
case IRQ_TYPE_LEVEL_LOW:
case IRQ_TYPE_LEVEL_HIGH:
*out_type = type;
break;
default:
return -EINVAL;
}
return 0;
}
static const struct irq_domain_ops irq_domain_sdv_ops = {
.xlate = sdv_xlate,
};
static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
struct pci_dev *pdev)
{
struct irq_chip_type *ct;
int ret;
sd->irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
SDV_NUM_PUB_GPIOS, -1);
if (sd->irq_base < 0)
return sd->irq_base;
/* mask + ACK all interrupt sources */
writel(0, sd->gpio_pub_base + GPIO_INT);
writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
ret = devm_request_irq(&pdev->dev, pdev->irq,
sdv_gpio_pub_irq_handler, IRQF_SHARED,
"sdv_gpio", sd);
if (ret)
return ret;
/*
* This gpio irq controller latches level irqs. Testing shows that if
* we unmask & ACK the IRQ before the source of the interrupt is gone
* then the interrupt is active again.
*/
sd->gc = devm_irq_alloc_generic_chip(&pdev->dev, "sdv-gpio", 1,
sd->irq_base,
sd->gpio_pub_base,
handle_fasteoi_irq);
if (!sd->gc)
return -ENOMEM;
sd->gc->private = sd;
ct = sd->gc->chip_types;
ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
ct->regs.eoi = GPSTR;
ct->regs.mask = GPIO_INT;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->chip.irq_eoi = irq_gc_eoi;
ct->chip.irq_set_type = sdv_gpio_pub_set_type;
irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
IRQ_LEVEL | IRQ_NOPROBE);
sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
sd->irq_base, 0, &irq_domain_sdv_ops, sd);
if (!sd->id)
return -ENODEV;
return 0;
}
static int sdv_gpio_probe(struct pci_dev *pdev,
const struct pci_device_id *pci_id)
{
struct sdv_gpio_chip_data *sd;
int ret;
u32 mux_val;
sd = devm_kzalloc(&pdev->dev, sizeof(*sd), GFP_KERNEL);
if (!sd)
return -ENOMEM;
ret = pcim_enable_device(pdev);
if (ret) {
dev_err(&pdev->dev, "can't enable device.\n");
return ret;
}
ret = pcim_iomap_regions(pdev, 1 << GPIO_BAR, DRV_NAME);
if (ret) {
dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
return ret;
}
sd->gpio_pub_base = pcim_iomap_table(pdev)[GPIO_BAR];
ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val);
if (!ret)
writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
ret = bgpio_init(&sd->chip, &pdev->dev, 4,
sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
NULL, sd->gpio_pub_base + GPOER, NULL, 0);
if (ret)
return ret;
sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd);
if (ret < 0) {
dev_err(&pdev->dev, "gpiochip_add() failed.\n");
return ret;
}
ret = sdv_register_irqsupport(sd, pdev);
if (ret)
return ret;
pci_set_drvdata(pdev, sd);
dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
return 0;
}
static const struct pci_device_id sdv_gpio_pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
{ 0, },
};
static struct pci_driver sdv_gpio_driver = {
.driver = {
.suppress_bind_attrs = true,
},
.name = DRV_NAME,
.id_table = sdv_gpio_pci_ids,
.probe = sdv_gpio_probe,
};
builtin_pci_driver(sdv_gpio_driver);
| linux-master | drivers/gpio/gpio-sodaville.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
* Keerthy <[email protected]>
*
* Based on the TPS65218 driver
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/lp873x.h>
#define BITS_PER_GPO 0x4
#define LP873X_GPO_CTRL_OD 0x2
struct lp873x_gpio {
struct gpio_chip chip;
struct lp873x *lp873;
};
static int lp873x_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
/* This device is output only */
return GPIO_LINE_DIRECTION_OUT;
}
static int lp873x_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
/* This device is output only */
return -EINVAL;
}
static int lp873x_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct lp873x_gpio *gpio = gpiochip_get_data(chip);
/* Set the initial value */
return regmap_update_bits(gpio->lp873->regmap, LP873X_REG_GPO_CTRL,
BIT(offset * BITS_PER_GPO),
value ? BIT(offset * BITS_PER_GPO) : 0);
}
static int lp873x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct lp873x_gpio *gpio = gpiochip_get_data(chip);
int ret, val;
ret = regmap_read(gpio->lp873->regmap, LP873X_REG_GPO_CTRL, &val);
if (ret < 0)
return ret;
return val & BIT(offset * BITS_PER_GPO);
}
static void lp873x_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct lp873x_gpio *gpio = gpiochip_get_data(chip);
regmap_update_bits(gpio->lp873->regmap, LP873X_REG_GPO_CTRL,
BIT(offset * BITS_PER_GPO),
value ? BIT(offset * BITS_PER_GPO) : 0);
}
static int lp873x_gpio_request(struct gpio_chip *gc, unsigned int offset)
{
struct lp873x_gpio *gpio = gpiochip_get_data(gc);
int ret;
switch (offset) {
case 0:
/* No MUX Set up Needed for GPO */
break;
case 1:
/* Setup the CLKIN_PIN_SEL MUX to GPO2 */
ret = regmap_update_bits(gpio->lp873->regmap, LP873X_REG_CONFIG,
LP873X_CONFIG_CLKIN_PIN_SEL, 0);
if (ret)
return ret;
break;
default:
return -EINVAL;
}
return 0;
}
static int lp873x_gpio_set_config(struct gpio_chip *gc, unsigned offset,
unsigned long config)
{
struct lp873x_gpio *gpio = gpiochip_get_data(gc);
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
return regmap_update_bits(gpio->lp873->regmap,
LP873X_REG_GPO_CTRL,
BIT(offset * BITS_PER_GPO +
LP873X_GPO_CTRL_OD),
BIT(offset * BITS_PER_GPO +
LP873X_GPO_CTRL_OD));
case PIN_CONFIG_DRIVE_PUSH_PULL:
return regmap_update_bits(gpio->lp873->regmap,
LP873X_REG_GPO_CTRL,
BIT(offset * BITS_PER_GPO +
LP873X_GPO_CTRL_OD), 0);
default:
return -ENOTSUPP;
}
}
static const struct gpio_chip template_chip = {
.label = "lp873x-gpio",
.owner = THIS_MODULE,
.request = lp873x_gpio_request,
.get_direction = lp873x_gpio_get_direction,
.direction_input = lp873x_gpio_direction_input,
.direction_output = lp873x_gpio_direction_output,
.get = lp873x_gpio_get,
.set = lp873x_gpio_set,
.set_config = lp873x_gpio_set_config,
.base = -1,
.ngpio = 2,
.can_sleep = true,
};
static int lp873x_gpio_probe(struct platform_device *pdev)
{
struct lp873x_gpio *gpio;
int ret;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
platform_set_drvdata(pdev, gpio);
gpio->lp873 = dev_get_drvdata(pdev->dev.parent);
gpio->chip = template_chip;
gpio->chip.parent = gpio->lp873->dev;
ret = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
if (ret < 0) {
dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
return ret;
}
return 0;
}
static const struct platform_device_id lp873x_gpio_id_table[] = {
{ "lp873x-gpio", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, lp873x_gpio_id_table);
static struct platform_driver lp873x_gpio_driver = {
.driver = {
.name = "lp873x-gpio",
},
.probe = lp873x_gpio_probe,
.id_table = lp873x_gpio_id_table,
};
module_platform_driver(lp873x_gpio_driver);
MODULE_AUTHOR("Keerthy <[email protected]>");
MODULE_DESCRIPTION("LP873X GPIO driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-lp873x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* GPIO driver for RICOH583 power management chip.
*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
* Author: Laxman dewangan <[email protected]>
*
* Based on code
* Copyright (C) 2011 RICOH COMPANY,LTD
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/mfd/rc5t583.h>
struct rc5t583_gpio {
struct gpio_chip gpio_chip;
struct rc5t583 *rc5t583;
};
static int rc5t583_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct rc5t583_gpio *rc5t583_gpio = gpiochip_get_data(gc);
struct device *parent = rc5t583_gpio->rc5t583->dev;
uint8_t val = 0;
int ret;
ret = rc5t583_read(parent, RC5T583_GPIO_MON_IOIN, &val);
if (ret < 0)
return ret;
return !!(val & BIT(offset));
}
static void rc5t583_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
{
struct rc5t583_gpio *rc5t583_gpio = gpiochip_get_data(gc);
struct device *parent = rc5t583_gpio->rc5t583->dev;
if (val)
rc5t583_set_bits(parent, RC5T583_GPIO_IOOUT, BIT(offset));
else
rc5t583_clear_bits(parent, RC5T583_GPIO_IOOUT, BIT(offset));
}
static int rc5t583_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
{
struct rc5t583_gpio *rc5t583_gpio = gpiochip_get_data(gc);
struct device *parent = rc5t583_gpio->rc5t583->dev;
int ret;
ret = rc5t583_clear_bits(parent, RC5T583_GPIO_IOSEL, BIT(offset));
if (ret < 0)
return ret;
/* Set pin to gpio mode */
return rc5t583_clear_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset));
}
static int rc5t583_gpio_dir_output(struct gpio_chip *gc, unsigned offset,
int value)
{
struct rc5t583_gpio *rc5t583_gpio = gpiochip_get_data(gc);
struct device *parent = rc5t583_gpio->rc5t583->dev;
int ret;
rc5t583_gpio_set(gc, offset, value);
ret = rc5t583_set_bits(parent, RC5T583_GPIO_IOSEL, BIT(offset));
if (ret < 0)
return ret;
/* Set pin to gpio mode */
return rc5t583_clear_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset));
}
static int rc5t583_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct rc5t583_gpio *rc5t583_gpio = gpiochip_get_data(gc);
if (offset < RC5T583_MAX_GPIO)
return rc5t583_gpio->rc5t583->irq_base +
RC5T583_IRQ_GPIO0 + offset;
return -EINVAL;
}
static void rc5t583_gpio_free(struct gpio_chip *gc, unsigned offset)
{
struct rc5t583_gpio *rc5t583_gpio = gpiochip_get_data(gc);
struct device *parent = rc5t583_gpio->rc5t583->dev;
rc5t583_set_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset));
}
static int rc5t583_gpio_probe(struct platform_device *pdev)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(pdev->dev.parent);
struct rc5t583_platform_data *pdata = dev_get_platdata(rc5t583->dev);
struct rc5t583_gpio *rc5t583_gpio;
rc5t583_gpio = devm_kzalloc(&pdev->dev, sizeof(*rc5t583_gpio),
GFP_KERNEL);
if (!rc5t583_gpio)
return -ENOMEM;
rc5t583_gpio->gpio_chip.label = "gpio-rc5t583",
rc5t583_gpio->gpio_chip.owner = THIS_MODULE,
rc5t583_gpio->gpio_chip.free = rc5t583_gpio_free,
rc5t583_gpio->gpio_chip.direction_input = rc5t583_gpio_dir_input,
rc5t583_gpio->gpio_chip.direction_output = rc5t583_gpio_dir_output,
rc5t583_gpio->gpio_chip.set = rc5t583_gpio_set,
rc5t583_gpio->gpio_chip.get = rc5t583_gpio_get,
rc5t583_gpio->gpio_chip.to_irq = rc5t583_gpio_to_irq,
rc5t583_gpio->gpio_chip.ngpio = RC5T583_MAX_GPIO,
rc5t583_gpio->gpio_chip.can_sleep = true,
rc5t583_gpio->gpio_chip.parent = &pdev->dev;
rc5t583_gpio->gpio_chip.base = -1;
rc5t583_gpio->rc5t583 = rc5t583;
if (pdata && pdata->gpio_base)
rc5t583_gpio->gpio_chip.base = pdata->gpio_base;
return devm_gpiochip_add_data(&pdev->dev, &rc5t583_gpio->gpio_chip,
rc5t583_gpio);
}
static struct platform_driver rc5t583_gpio_driver = {
.driver = {
.name = "rc5t583-gpio",
},
.probe = rc5t583_gpio_probe,
};
static int __init rc5t583_gpio_init(void)
{
return platform_driver_register(&rc5t583_gpio_driver);
}
subsys_initcall(rc5t583_gpio_init);
| linux-master | drivers/gpio/gpio-rc5t583.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2015 Verifone Int.
*
* Author: Nicolas Saenz Julienne <[email protected]>
*
* This driver is based on the gpio-tps65912 implementation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/tps65218.h>
struct tps65218_gpio {
struct tps65218 *tps65218;
struct gpio_chip gpio_chip;
};
static int tps65218_gpio_get(struct gpio_chip *gc, unsigned offset)
{
struct tps65218_gpio *tps65218_gpio = gpiochip_get_data(gc);
struct tps65218 *tps65218 = tps65218_gpio->tps65218;
unsigned int val;
int ret;
ret = regmap_read(tps65218->regmap, TPS65218_REG_ENABLE2, &val);
if (ret)
return ret;
return !!(val & (TPS65218_ENABLE2_GPIO1 << offset));
}
static void tps65218_gpio_set(struct gpio_chip *gc, unsigned offset,
int value)
{
struct tps65218_gpio *tps65218_gpio = gpiochip_get_data(gc);
struct tps65218 *tps65218 = tps65218_gpio->tps65218;
if (value)
tps65218_set_bits(tps65218, TPS65218_REG_ENABLE2,
TPS65218_ENABLE2_GPIO1 << offset,
TPS65218_ENABLE2_GPIO1 << offset,
TPS65218_PROTECT_L1);
else
tps65218_clear_bits(tps65218, TPS65218_REG_ENABLE2,
TPS65218_ENABLE2_GPIO1 << offset,
TPS65218_PROTECT_L1);
}
static int tps65218_gpio_output(struct gpio_chip *gc, unsigned offset,
int value)
{
/* Only drives GPOs */
tps65218_gpio_set(gc, offset, value);
return 0;
}
static int tps65218_gpio_input(struct gpio_chip *gc, unsigned offset)
{
return -EPERM;
}
static int tps65218_gpio_request(struct gpio_chip *gc, unsigned offset)
{
struct tps65218_gpio *tps65218_gpio = gpiochip_get_data(gc);
struct tps65218 *tps65218 = tps65218_gpio->tps65218;
int ret;
if (gpiochip_line_is_open_source(gc, offset)) {
dev_err(gc->parent, "can't work as open source\n");
return -EINVAL;
}
switch (offset) {
case 0:
if (!gpiochip_line_is_open_drain(gc, offset)) {
dev_err(gc->parent, "GPO1 works only as open drain\n");
return -EINVAL;
}
/* Disable sequencer for GPO1 */
ret = tps65218_clear_bits(tps65218, TPS65218_REG_SEQ7,
TPS65218_SEQ7_GPO1_SEQ_MASK,
TPS65218_PROTECT_L1);
if (ret)
return ret;
/* Setup GPO1 */
ret = tps65218_clear_bits(tps65218, TPS65218_REG_CONFIG1,
TPS65218_CONFIG1_IO1_SEL,
TPS65218_PROTECT_L1);
if (ret)
return ret;
break;
case 1:
/* Setup GPO2 */
ret = tps65218_clear_bits(tps65218, TPS65218_REG_CONFIG1,
TPS65218_CONFIG1_IO1_SEL,
TPS65218_PROTECT_L1);
if (ret)
return ret;
break;
case 2:
if (!gpiochip_line_is_open_drain(gc, offset)) {
dev_err(gc->parent, "GPO3 works only as open drain\n");
return -EINVAL;
}
/* Disable sequencer for GPO3 */
ret = tps65218_clear_bits(tps65218, TPS65218_REG_SEQ7,
TPS65218_SEQ7_GPO3_SEQ_MASK,
TPS65218_PROTECT_L1);
if (ret)
return ret;
/* Setup GPO3 */
ret = tps65218_clear_bits(tps65218, TPS65218_REG_CONFIG2,
TPS65218_CONFIG2_DC12_RST,
TPS65218_PROTECT_L1);
if (ret)
return ret;
break;
default:
return -EINVAL;
}
return 0;
}
static int tps65218_gpio_set_config(struct gpio_chip *gc, unsigned offset,
unsigned long config)
{
struct tps65218_gpio *tps65218_gpio = gpiochip_get_data(gc);
struct tps65218 *tps65218 = tps65218_gpio->tps65218;
enum pin_config_param param = pinconf_to_config_param(config);
switch (offset) {
case 0:
case 2:
/* GPO1 is hardwired to be open drain */
if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
return 0;
return -ENOTSUPP;
case 1:
/* GPO2 is push-pull by default, can be set as open drain. */
if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
return tps65218_clear_bits(tps65218,
TPS65218_REG_CONFIG1,
TPS65218_CONFIG1_GPO2_BUF,
TPS65218_PROTECT_L1);
if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
return tps65218_set_bits(tps65218,
TPS65218_REG_CONFIG1,
TPS65218_CONFIG1_GPO2_BUF,
TPS65218_CONFIG1_GPO2_BUF,
TPS65218_PROTECT_L1);
return -ENOTSUPP;
default:
break;
}
return -ENOTSUPP;
}
static const struct gpio_chip template_chip = {
.label = "gpio-tps65218",
.owner = THIS_MODULE,
.request = tps65218_gpio_request,
.direction_output = tps65218_gpio_output,
.direction_input = tps65218_gpio_input,
.get = tps65218_gpio_get,
.set = tps65218_gpio_set,
.set_config = tps65218_gpio_set_config,
.can_sleep = true,
.ngpio = 3,
.base = -1,
};
static int tps65218_gpio_probe(struct platform_device *pdev)
{
struct tps65218 *tps65218 = dev_get_drvdata(pdev->dev.parent);
struct tps65218_gpio *tps65218_gpio;
tps65218_gpio = devm_kzalloc(&pdev->dev, sizeof(*tps65218_gpio),
GFP_KERNEL);
if (!tps65218_gpio)
return -ENOMEM;
tps65218_gpio->tps65218 = tps65218;
tps65218_gpio->gpio_chip = template_chip;
tps65218_gpio->gpio_chip.parent = &pdev->dev;
return devm_gpiochip_add_data(&pdev->dev, &tps65218_gpio->gpio_chip,
tps65218_gpio);
}
static const struct of_device_id tps65218_dt_match[] = {
{ .compatible = "ti,tps65218-gpio" },
{ }
};
MODULE_DEVICE_TABLE(of, tps65218_dt_match);
static const struct platform_device_id tps65218_gpio_id_table[] = {
{ "tps65218-gpio", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, tps65218_gpio_id_table);
static struct platform_driver tps65218_gpio_driver = {
.driver = {
.name = "tps65218-gpio",
.of_match_table = tps65218_dt_match,
},
.probe = tps65218_gpio_probe,
.id_table = tps65218_gpio_id_table,
};
module_platform_driver(tps65218_gpio_driver);
MODULE_AUTHOR("Nicolas Saenz Julienne <[email protected]>");
MODULE_DESCRIPTION("GPO interface for TPS65218 PMICs");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-tps65218.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/types.h>
#include <linux/io.h>
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#define AIROHA_GPIO_MAX 32
/**
* airoha_gpio_ctrl - Airoha GPIO driver data
* @gc: Associated gpio_chip instance.
* @data: The data register.
* @dir0: The direction register for the lower 16 pins.
* @dir1: The direction register for the higher 16 pins.
* @output: The output enable register.
*/
struct airoha_gpio_ctrl {
struct gpio_chip gc;
void __iomem *data;
void __iomem *dir[2];
void __iomem *output;
};
static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc)
{
return container_of(gc, struct airoha_gpio_ctrl, gc);
}
static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio,
int val, int out)
{
struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
u32 dir = ioread32(ctrl->dir[gpio / 16]);
u32 output = ioread32(ctrl->output);
u32 mask = BIT((gpio % 16) * 2);
if (out) {
dir |= mask;
output |= BIT(gpio);
} else {
dir &= ~mask;
output &= ~BIT(gpio);
}
iowrite32(dir, ctrl->dir[gpio / 16]);
if (out)
gc->set(gc, gpio, val);
iowrite32(output, ctrl->output);
return 0;
}
static int airoha_dir_out(struct gpio_chip *gc, unsigned int gpio,
int val)
{
return airoha_dir_set(gc, gpio, val, 1);
}
static int airoha_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
return airoha_dir_set(gc, gpio, 0, 0);
}
static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio)
{
struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
u32 dir = ioread32(ctrl->dir[gpio / 16]);
u32 mask = BIT((gpio % 16) * 2);
return (dir & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
}
static int airoha_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct airoha_gpio_ctrl *ctrl;
int err;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return -ENOMEM;
ctrl->data = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ctrl->data))
return PTR_ERR(ctrl->data);
ctrl->dir[0] = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(ctrl->dir[0]))
return PTR_ERR(ctrl->dir[0]);
ctrl->dir[1] = devm_platform_ioremap_resource(pdev, 2);
if (IS_ERR(ctrl->dir[1]))
return PTR_ERR(ctrl->dir[1]);
ctrl->output = devm_platform_ioremap_resource(pdev, 3);
if (IS_ERR(ctrl->output))
return PTR_ERR(ctrl->output);
err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL,
NULL, NULL, NULL, 0);
if (err)
return dev_err_probe(dev, err, "unable to init generic GPIO");
ctrl->gc.ngpio = AIROHA_GPIO_MAX;
ctrl->gc.owner = THIS_MODULE;
ctrl->gc.direction_output = airoha_dir_out;
ctrl->gc.direction_input = airoha_dir_in;
ctrl->gc.get_direction = airoha_get_dir;
return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
}
static const struct of_device_id airoha_gpio_of_match[] = {
{ .compatible = "airoha,en7523-gpio" },
{ }
};
MODULE_DEVICE_TABLE(of, airoha_gpio_of_match);
static struct platform_driver airoha_gpio_driver = {
.driver = {
.name = "airoha-gpio",
.of_match_table = airoha_gpio_of_match,
},
.probe = airoha_gpio_probe,
};
module_platform_driver(airoha_gpio_driver);
MODULE_DESCRIPTION("Airoha GPIO support");
MODULE_AUTHOR("John Crispin <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-en7523.c |
// SPDX-License-Identifier: GPL-2.0+
//
// MXC GPIO support. (c) 2008 Daniel Mack <[email protected]>
// Copyright 2008 Juergen Beisert, [email protected]
//
// Based on code from Freescale Semiconductor,
// Authors: Daniel Mack, Juergen Beisert.
// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/syscore_ops.h>
#include <linux/gpio/driver.h>
#include <linux/of.h>
#include <linux/bug.h>
#define IMX_SCU_WAKEUP_OFF 0
#define IMX_SCU_WAKEUP_LOW_LVL 4
#define IMX_SCU_WAKEUP_FALL_EDGE 5
#define IMX_SCU_WAKEUP_RISE_EDGE 6
#define IMX_SCU_WAKEUP_HIGH_LVL 7
/* device type dependent stuff */
struct mxc_gpio_hwdata {
unsigned dr_reg;
unsigned gdir_reg;
unsigned psr_reg;
unsigned icr1_reg;
unsigned icr2_reg;
unsigned imr_reg;
unsigned isr_reg;
int edge_sel_reg;
unsigned low_level;
unsigned high_level;
unsigned rise_edge;
unsigned fall_edge;
};
struct mxc_gpio_reg_saved {
u32 icr1;
u32 icr2;
u32 imr;
u32 gdir;
u32 edge_sel;
u32 dr;
};
struct mxc_gpio_port {
struct list_head node;
void __iomem *base;
struct clk *clk;
int irq;
int irq_high;
void (*mx_irq_handler)(struct irq_desc *desc);
struct irq_domain *domain;
struct gpio_chip gc;
struct device *dev;
u32 both_edges;
struct mxc_gpio_reg_saved gpio_saved_reg;
bool power_off;
u32 wakeup_pads;
bool is_pad_wakeup;
u32 pad_type[32];
const struct mxc_gpio_hwdata *hwdata;
};
static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
.dr_reg = 0x1c,
.gdir_reg = 0x00,
.psr_reg = 0x24,
.icr1_reg = 0x28,
.icr2_reg = 0x2c,
.imr_reg = 0x30,
.isr_reg = 0x34,
.edge_sel_reg = -EINVAL,
.low_level = 0x03,
.high_level = 0x02,
.rise_edge = 0x00,
.fall_edge = 0x01,
};
static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
.dr_reg = 0x00,
.gdir_reg = 0x04,
.psr_reg = 0x08,
.icr1_reg = 0x0c,
.icr2_reg = 0x10,
.imr_reg = 0x14,
.isr_reg = 0x18,
.edge_sel_reg = -EINVAL,
.low_level = 0x00,
.high_level = 0x01,
.rise_edge = 0x02,
.fall_edge = 0x03,
};
static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
.dr_reg = 0x00,
.gdir_reg = 0x04,
.psr_reg = 0x08,
.icr1_reg = 0x0c,
.icr2_reg = 0x10,
.imr_reg = 0x14,
.isr_reg = 0x18,
.edge_sel_reg = 0x1c,
.low_level = 0x00,
.high_level = 0x01,
.rise_edge = 0x02,
.fall_edge = 0x03,
};
#define GPIO_DR (port->hwdata->dr_reg)
#define GPIO_GDIR (port->hwdata->gdir_reg)
#define GPIO_PSR (port->hwdata->psr_reg)
#define GPIO_ICR1 (port->hwdata->icr1_reg)
#define GPIO_ICR2 (port->hwdata->icr2_reg)
#define GPIO_IMR (port->hwdata->imr_reg)
#define GPIO_ISR (port->hwdata->isr_reg)
#define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg)
#define GPIO_INT_LOW_LEV (port->hwdata->low_level)
#define GPIO_INT_HIGH_LEV (port->hwdata->high_level)
#define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge)
#define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge)
#define GPIO_INT_BOTH_EDGES 0x4
static const struct of_device_id mxc_gpio_dt_ids[] = {
{ .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata },
{ .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata },
{ .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
{ .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
{ .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
{ .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata },
{ .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata },
{ .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
/*
* MX2 has one interrupt *for all* gpio ports. The list is used
* to save the references to all ports, so that mx2_gpio_irq_handler
* can walk through all interrupt status registers.
*/
static LIST_HEAD(mxc_gpio_ports);
/* Note: This driver assumes 32 GPIOs are handled in one register */
static int gpio_set_irq_type(struct irq_data *d, u32 type)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct mxc_gpio_port *port = gc->private;
unsigned long flags;
u32 bit, val;
u32 gpio_idx = d->hwirq;
int edge;
void __iomem *reg = port->base;
port->both_edges &= ~(1 << gpio_idx);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
edge = GPIO_INT_RISE_EDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
edge = GPIO_INT_FALL_EDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
if (GPIO_EDGE_SEL >= 0) {
edge = GPIO_INT_BOTH_EDGES;
} else {
val = port->gc.get(&port->gc, gpio_idx);
if (val) {
edge = GPIO_INT_LOW_LEV;
pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
} else {
edge = GPIO_INT_HIGH_LEV;
pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
}
port->both_edges |= 1 << gpio_idx;
}
break;
case IRQ_TYPE_LEVEL_LOW:
edge = GPIO_INT_LOW_LEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
edge = GPIO_INT_HIGH_LEV;
break;
default:
return -EINVAL;
}
raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
if (GPIO_EDGE_SEL >= 0) {
val = readl(port->base + GPIO_EDGE_SEL);
if (edge == GPIO_INT_BOTH_EDGES)
writel(val | (1 << gpio_idx),
port->base + GPIO_EDGE_SEL);
else
writel(val & ~(1 << gpio_idx),
port->base + GPIO_EDGE_SEL);
}
if (edge != GPIO_INT_BOTH_EDGES) {
reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
bit = gpio_idx & 0xf;
val = readl(reg) & ~(0x3 << (bit << 1));
writel(val | (edge << (bit << 1)), reg);
}
writel(1 << gpio_idx, port->base + GPIO_ISR);
port->pad_type[gpio_idx] = type;
raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
return port->gc.direction_input(&port->gc, gpio_idx);
}
static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
{
void __iomem *reg = port->base;
unsigned long flags;
u32 bit, val;
int edge;
raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
bit = gpio & 0xf;
val = readl(reg);
edge = (val >> (bit << 1)) & 3;
val &= ~(0x3 << (bit << 1));
if (edge == GPIO_INT_HIGH_LEV) {
edge = GPIO_INT_LOW_LEV;
pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
} else if (edge == GPIO_INT_LOW_LEV) {
edge = GPIO_INT_HIGH_LEV;
pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
} else {
pr_err("mxc: invalid configuration for GPIO %d: %x\n",
gpio, edge);
goto unlock;
}
writel(val | (edge << (bit << 1)), reg);
unlock:
raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
}
/* handle 32 interrupts in one status register */
static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
{
while (irq_stat != 0) {
int irqoffset = fls(irq_stat) - 1;
if (port->both_edges & (1 << irqoffset))
mxc_flip_edge(port, irqoffset);
generic_handle_domain_irq(port->domain, irqoffset);
irq_stat &= ~(1 << irqoffset);
}
}
/* MX1 and MX3 has one interrupt *per* gpio port */
static void mx3_gpio_irq_handler(struct irq_desc *desc)
{
u32 irq_stat;
struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
if (port->is_pad_wakeup)
return;
chained_irq_enter(chip, desc);
irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
mxc_gpio_irq_handler(port, irq_stat);
chained_irq_exit(chip, desc);
}
/* MX2 has one interrupt *for all* gpio ports */
static void mx2_gpio_irq_handler(struct irq_desc *desc)
{
u32 irq_msk, irq_stat;
struct mxc_gpio_port *port;
struct irq_chip *chip = irq_desc_get_chip(desc);
chained_irq_enter(chip, desc);
/* walk through all interrupt status registers */
list_for_each_entry(port, &mxc_gpio_ports, node) {
irq_msk = readl(port->base + GPIO_IMR);
if (!irq_msk)
continue;
irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
if (irq_stat)
mxc_gpio_irq_handler(port, irq_stat);
}
chained_irq_exit(chip, desc);
}
/*
* Set interrupt number "irq" in the GPIO as a wake-up source.
* While system is running, all registered GPIO interrupts need to have
* wake-up enabled. When system is suspended, only selected GPIO interrupts
* need to have wake-up enabled.
* @param irq interrupt source number
* @param enable enable as wake-up if equal to non-zero
* @return This function returns 0 on success.
*/
static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct mxc_gpio_port *port = gc->private;
u32 gpio_idx = d->hwirq;
int ret;
if (enable) {
if (port->irq_high && (gpio_idx >= 16))
ret = enable_irq_wake(port->irq_high);
else
ret = enable_irq_wake(port->irq);
port->wakeup_pads |= (1 << gpio_idx);
} else {
if (port->irq_high && (gpio_idx >= 16))
ret = disable_irq_wake(port->irq_high);
else
ret = disable_irq_wake(port->irq);
port->wakeup_pads &= ~(1 << gpio_idx);
}
return ret;
}
static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
int rv;
gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
port->base, handle_level_irq);
if (!gc)
return -ENOMEM;
gc->private = port;
ct = gc->chip_types;
ct->chip.irq_ack = irq_gc_ack_set_bit;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->chip.irq_set_type = gpio_set_irq_type;
ct->chip.irq_set_wake = gpio_set_wake_irq;
ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
ct->regs.ack = GPIO_ISR;
ct->regs.mask = GPIO_IMR;
rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
IRQ_GC_INIT_NESTED_LOCK,
IRQ_NOREQUEST, 0);
return rv;
}
static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct mxc_gpio_port *port = gpiochip_get_data(gc);
return irq_find_mapping(port->domain, offset);
}
static int mxc_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
int ret;
ret = gpiochip_generic_request(chip, offset);
if (ret)
return ret;
return pm_runtime_resume_and_get(chip->parent);
}
static void mxc_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
gpiochip_generic_free(chip, offset);
pm_runtime_put(chip->parent);
}
static void mxc_update_irq_chained_handler(struct mxc_gpio_port *port, bool enable)
{
if (enable)
irq_set_chained_handler_and_data(port->irq, port->mx_irq_handler, port);
else
irq_set_chained_handler_and_data(port->irq, NULL, NULL);
/* setup handler for GPIO 16 to 31 */
if (port->irq_high > 0) {
if (enable)
irq_set_chained_handler_and_data(port->irq_high,
port->mx_irq_handler,
port);
else
irq_set_chained_handler_and_data(port->irq_high, NULL, NULL);
}
}
static int mxc_gpio_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct mxc_gpio_port *port;
int irq_count;
int irq_base;
int err;
port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
if (!port)
return -ENOMEM;
port->dev = &pdev->dev;
port->hwdata = device_get_match_data(&pdev->dev);
port->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(port->base))
return PTR_ERR(port->base);
irq_count = platform_irq_count(pdev);
if (irq_count < 0)
return irq_count;
if (irq_count > 1) {
port->irq_high = platform_get_irq(pdev, 1);
if (port->irq_high < 0)
port->irq_high = 0;
}
port->irq = platform_get_irq(pdev, 0);
if (port->irq < 0)
return port->irq;
/* the controller clock is optional */
port->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
if (IS_ERR(port->clk))
return PTR_ERR(port->clk);
if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
port->power_off = true;
pm_runtime_get_noresume(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
/* disable the interrupt and clear the status */
writel(0, port->base + GPIO_IMR);
writel(~0, port->base + GPIO_ISR);
if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
/*
* Setup one handler for all GPIO interrupts. Actually setting
* the handler is needed only once, but doing it for every port
* is more robust and easier.
*/
port->irq_high = -1;
port->mx_irq_handler = mx2_gpio_irq_handler;
} else
port->mx_irq_handler = mx3_gpio_irq_handler;
mxc_update_irq_chained_handler(port, true);
err = bgpio_init(&port->gc, &pdev->dev, 4,
port->base + GPIO_PSR,
port->base + GPIO_DR, NULL,
port->base + GPIO_GDIR, NULL,
BGPIOF_READ_OUTPUT_REG_SET);
if (err)
goto out_bgio;
port->gc.request = mxc_gpio_request;
port->gc.free = mxc_gpio_free;
port->gc.to_irq = mxc_gpio_to_irq;
port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
pdev->id * 32;
err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
if (err)
goto out_bgio;
irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
if (irq_base < 0) {
err = irq_base;
goto out_bgio;
}
port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
&irq_domain_simple_ops, NULL);
if (!port->domain) {
err = -ENODEV;
goto out_bgio;
}
irq_domain_set_pm_device(port->domain, &pdev->dev);
/* gpio-mxc can be a generic irq chip */
err = mxc_gpio_init_gc(port, irq_base);
if (err < 0)
goto out_irqdomain_remove;
list_add_tail(&port->node, &mxc_gpio_ports);
platform_set_drvdata(pdev, port);
pm_runtime_put_autosuspend(&pdev->dev);
return 0;
out_irqdomain_remove:
irq_domain_remove(port->domain);
out_bgio:
pm_runtime_disable(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
return err;
}
static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
{
if (!port->power_off)
return;
port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
}
static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
{
if (!port->power_off)
return;
writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
}
static bool mxc_gpio_generic_config(struct mxc_gpio_port *port,
unsigned int offset, unsigned long conf)
{
struct device_node *np = port->dev->of_node;
if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") ||
of_device_is_compatible(np, "fsl,imx8qxp-gpio") ||
of_device_is_compatible(np, "fsl,imx8qm-gpio"))
return (gpiochip_generic_config(&port->gc, offset, conf) == 0);
return false;
}
static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable)
{
unsigned long config;
bool ret = false;
int i, type;
static const u32 pad_type_map[] = {
IMX_SCU_WAKEUP_OFF, /* 0 */
IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */
IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */
IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_BOTH */
IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */
IMX_SCU_WAKEUP_OFF, /* 5 */
IMX_SCU_WAKEUP_OFF, /* 6 */
IMX_SCU_WAKEUP_OFF, /* 7 */
IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */
};
for (i = 0; i < 32; i++) {
if ((port->wakeup_pads & (1 << i))) {
type = port->pad_type[i];
if (enable)
config = pad_type_map[type];
else
config = IMX_SCU_WAKEUP_OFF;
ret |= mxc_gpio_generic_config(port, i, config);
}
}
return ret;
}
static int mxc_gpio_runtime_suspend(struct device *dev)
{
struct mxc_gpio_port *port = dev_get_drvdata(dev);
mxc_gpio_save_regs(port);
clk_disable_unprepare(port->clk);
mxc_update_irq_chained_handler(port, false);
return 0;
}
static int mxc_gpio_runtime_resume(struct device *dev)
{
struct mxc_gpio_port *port = dev_get_drvdata(dev);
int ret;
mxc_update_irq_chained_handler(port, true);
ret = clk_prepare_enable(port->clk);
if (ret) {
mxc_update_irq_chained_handler(port, false);
return ret;
}
mxc_gpio_restore_regs(port);
return 0;
}
static int mxc_gpio_noirq_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct mxc_gpio_port *port = platform_get_drvdata(pdev);
if (port->wakeup_pads > 0)
port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true);
return 0;
}
static int mxc_gpio_noirq_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct mxc_gpio_port *port = platform_get_drvdata(pdev);
if (port->wakeup_pads > 0)
mxc_gpio_set_pad_wakeup(port, false);
port->is_pad_wakeup = false;
return 0;
}
static const struct dev_pm_ops mxc_gpio_dev_pm_ops = {
NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume)
RUNTIME_PM_OPS(mxc_gpio_runtime_suspend, mxc_gpio_runtime_resume, NULL)
};
static int mxc_gpio_syscore_suspend(void)
{
struct mxc_gpio_port *port;
int ret;
/* walk through all ports */
list_for_each_entry(port, &mxc_gpio_ports, node) {
ret = clk_prepare_enable(port->clk);
if (ret)
return ret;
mxc_gpio_save_regs(port);
clk_disable_unprepare(port->clk);
}
return 0;
}
static void mxc_gpio_syscore_resume(void)
{
struct mxc_gpio_port *port;
int ret;
/* walk through all ports */
list_for_each_entry(port, &mxc_gpio_ports, node) {
ret = clk_prepare_enable(port->clk);
if (ret) {
pr_err("mxc: failed to enable gpio clock %d\n", ret);
return;
}
mxc_gpio_restore_regs(port);
clk_disable_unprepare(port->clk);
}
}
static struct syscore_ops mxc_gpio_syscore_ops = {
.suspend = mxc_gpio_syscore_suspend,
.resume = mxc_gpio_syscore_resume,
};
static struct platform_driver mxc_gpio_driver = {
.driver = {
.name = "gpio-mxc",
.of_match_table = mxc_gpio_dt_ids,
.suppress_bind_attrs = true,
.pm = pm_ptr(&mxc_gpio_dev_pm_ops),
},
.probe = mxc_gpio_probe,
};
static int __init gpio_mxc_init(void)
{
register_syscore_ops(&mxc_gpio_syscore_ops);
return platform_driver_register(&mxc_gpio_driver);
}
subsys_initcall(gpio_mxc_init);
MODULE_AUTHOR("Shawn Guo <[email protected]>");
MODULE_DESCRIPTION("i.MX GPIO Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-mxc.c |
/*
* Support for the GPIO/IRQ expander chips present on several HTC phones.
* These are implemented in CPLD chips present on the board.
*
* Copyright (c) 2007 Kevin O'Connor <[email protected]>
* Copyright (c) 2007 Philipp Zabel <[email protected]>
*
* This file may be distributed under the terms of the GNU GPL license.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_data/gpio-htc-egpio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/gpio/driver.h>
struct egpio_chip {
int reg_start;
int cached_values;
unsigned long is_out;
struct device *dev;
struct gpio_chip chip;
};
struct egpio_info {
spinlock_t lock;
/* iomem info */
void __iomem *base_addr;
int bus_shift; /* byte shift */
int reg_shift; /* bit shift */
int reg_mask;
/* irq info */
int ack_register;
int ack_write;
u16 irqs_enabled;
uint irq_start;
int nirqs;
uint chained_irq;
/* egpio info */
struct egpio_chip *chip;
int nchips;
};
static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
{
writew(value, ei->base_addr + (reg << ei->bus_shift));
}
static inline u16 egpio_readw(struct egpio_info *ei, int reg)
{
return readw(ei->base_addr + (reg << ei->bus_shift));
}
/*
* IRQs
*/
static inline void ack_irqs(struct egpio_info *ei)
{
egpio_writew(ei->ack_write, ei, ei->ack_register);
pr_debug("EGPIO ack - write %x to base+%x\n",
ei->ack_write, ei->ack_register << ei->bus_shift);
}
static void egpio_ack(struct irq_data *data)
{
}
/* There does not appear to be a way to proactively mask interrupts
* on the egpio chip itself. So, we simply ignore interrupts that
* aren't desired. */
static void egpio_mask(struct irq_data *data)
{
struct egpio_info *ei = irq_data_get_irq_chip_data(data);
ei->irqs_enabled &= ~(1 << (data->irq - ei->irq_start));
pr_debug("EGPIO mask %d %04x\n", data->irq, ei->irqs_enabled);
}
static void egpio_unmask(struct irq_data *data)
{
struct egpio_info *ei = irq_data_get_irq_chip_data(data);
ei->irqs_enabled |= 1 << (data->irq - ei->irq_start);
pr_debug("EGPIO unmask %d %04x\n", data->irq, ei->irqs_enabled);
}
static struct irq_chip egpio_muxed_chip = {
.name = "htc-egpio",
.irq_ack = egpio_ack,
.irq_mask = egpio_mask,
.irq_unmask = egpio_unmask,
};
static void egpio_handler(struct irq_desc *desc)
{
struct egpio_info *ei = irq_desc_get_handler_data(desc);
int irqpin;
/* Read current pins. */
unsigned long readval = egpio_readw(ei, ei->ack_register);
pr_debug("IRQ reg: %x\n", (unsigned int)readval);
/* Ack/unmask interrupts. */
ack_irqs(ei);
/* Process all set pins. */
readval &= ei->irqs_enabled;
for_each_set_bit(irqpin, &readval, ei->nirqs) {
/* Run irq handler */
pr_debug("got IRQ %d\n", irqpin);
generic_handle_irq(ei->irq_start + irqpin);
}
}
static inline int egpio_pos(struct egpio_info *ei, int bit)
{
return bit >> ei->reg_shift;
}
static inline int egpio_bit(struct egpio_info *ei, int bit)
{
return 1 << (bit & ((1 << ei->reg_shift)-1));
}
/*
* Input pins
*/
static int egpio_get(struct gpio_chip *chip, unsigned offset)
{
struct egpio_chip *egpio;
struct egpio_info *ei;
unsigned bit;
int reg;
int value;
pr_debug("egpio_get_value(%d)\n", chip->base + offset);
egpio = gpiochip_get_data(chip);
ei = dev_get_drvdata(egpio->dev);
bit = egpio_bit(ei, offset);
reg = egpio->reg_start + egpio_pos(ei, offset);
if (test_bit(offset, &egpio->is_out)) {
return !!(egpio->cached_values & (1 << offset));
} else {
value = egpio_readw(ei, reg);
pr_debug("readw(%p + %x) = %x\n",
ei->base_addr, reg << ei->bus_shift, value);
return !!(value & bit);
}
}
static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct egpio_chip *egpio;
egpio = gpiochip_get_data(chip);
return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
}
/*
* Output pins
*/
static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
unsigned long flag;
struct egpio_chip *egpio;
struct egpio_info *ei;
int pos;
int reg;
int shift;
pr_debug("egpio_set(%s, %d(%d), %d)\n",
chip->label, offset, offset+chip->base, value);
egpio = gpiochip_get_data(chip);
ei = dev_get_drvdata(egpio->dev);
pos = egpio_pos(ei, offset);
reg = egpio->reg_start + pos;
shift = pos << ei->reg_shift;
pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
reg, (egpio->cached_values >> shift) & ei->reg_mask);
spin_lock_irqsave(&ei->lock, flag);
if (value)
egpio->cached_values |= (1 << offset);
else
egpio->cached_values &= ~(1 << offset);
egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
spin_unlock_irqrestore(&ei->lock, flag);
}
static int egpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct egpio_chip *egpio;
egpio = gpiochip_get_data(chip);
if (test_bit(offset, &egpio->is_out)) {
egpio_set(chip, offset, value);
return 0;
} else {
return -EINVAL;
}
}
static int egpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
struct egpio_chip *egpio;
egpio = gpiochip_get_data(chip);
if (test_bit(offset, &egpio->is_out))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static void egpio_write_cache(struct egpio_info *ei)
{
int i;
struct egpio_chip *egpio;
int shift;
for (i = 0; i < ei->nchips; i++) {
egpio = &(ei->chip[i]);
if (!egpio->is_out)
continue;
for (shift = 0; shift < egpio->chip.ngpio;
shift += (1<<ei->reg_shift)) {
int reg = egpio->reg_start + egpio_pos(ei, shift);
if (!((egpio->is_out >> shift) & ei->reg_mask))
continue;
pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
(egpio->cached_values >> shift) & ei->reg_mask,
egpio_readw(ei, reg));
egpio_writew((egpio->cached_values >> shift)
& ei->reg_mask, ei, reg);
}
}
}
/*
* Setup
*/
static int __init egpio_probe(struct platform_device *pdev)
{
struct htc_egpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
struct resource *res;
struct egpio_info *ei;
struct gpio_chip *chip;
unsigned int irq, irq_end;
int i;
/* Initialize ei data structure. */
ei = devm_kzalloc(&pdev->dev, sizeof(*ei), GFP_KERNEL);
if (!ei)
return -ENOMEM;
spin_lock_init(&ei->lock);
/* Find chained irq */
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (res)
ei->chained_irq = res->start;
/* Map egpio chip into virtual address space. */
ei->base_addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ei->base_addr))
return PTR_ERR(ei->base_addr);
if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
return -EINVAL;
ei->bus_shift = fls(pdata->bus_width - 1) - 3;
pr_debug("bus_shift = %d\n", ei->bus_shift);
if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
return -EINVAL;
ei->reg_shift = fls(pdata->reg_width - 1);
pr_debug("reg_shift = %d\n", ei->reg_shift);
ei->reg_mask = (1 << pdata->reg_width) - 1;
platform_set_drvdata(pdev, ei);
ei->nchips = pdata->num_chips;
ei->chip = devm_kcalloc(&pdev->dev,
ei->nchips, sizeof(struct egpio_chip),
GFP_KERNEL);
if (!ei->chip)
return -ENOMEM;
for (i = 0; i < ei->nchips; i++) {
ei->chip[i].reg_start = pdata->chip[i].reg_start;
ei->chip[i].cached_values = pdata->chip[i].initial_values;
ei->chip[i].is_out = pdata->chip[i].direction;
ei->chip[i].dev = &(pdev->dev);
chip = &(ei->chip[i].chip);
chip->label = devm_kasprintf(&pdev->dev, GFP_KERNEL,
"htc-egpio-%d",
i);
if (!chip->label)
return -ENOMEM;
chip->parent = &pdev->dev;
chip->owner = THIS_MODULE;
chip->get = egpio_get;
chip->set = egpio_set;
chip->direction_input = egpio_direction_input;
chip->direction_output = egpio_direction_output;
chip->get_direction = egpio_get_direction;
chip->base = pdata->chip[i].gpio_base;
chip->ngpio = pdata->chip[i].num_gpios;
gpiochip_add_data(chip, &ei->chip[i]);
}
/* Set initial pin values */
egpio_write_cache(ei);
ei->irq_start = pdata->irq_base;
ei->nirqs = pdata->num_irqs;
ei->ack_register = pdata->ack_register;
if (ei->chained_irq) {
/* Setup irq handlers */
ei->ack_write = 0xFFFF;
if (pdata->invert_acks)
ei->ack_write = 0;
irq_end = ei->irq_start + ei->nirqs;
for (irq = ei->irq_start; irq < irq_end; irq++) {
irq_set_chip_and_handler(irq, &egpio_muxed_chip,
handle_simple_irq);
irq_set_chip_data(irq, ei);
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
irq_set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
irq_set_chained_handler_and_data(ei->chained_irq,
egpio_handler, ei);
ack_irqs(ei);
device_init_wakeup(&pdev->dev, 1);
}
return 0;
}
#ifdef CONFIG_PM
static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
{
struct egpio_info *ei = platform_get_drvdata(pdev);
if (ei->chained_irq && device_may_wakeup(&pdev->dev))
enable_irq_wake(ei->chained_irq);
return 0;
}
static int egpio_resume(struct platform_device *pdev)
{
struct egpio_info *ei = platform_get_drvdata(pdev);
if (ei->chained_irq && device_may_wakeup(&pdev->dev))
disable_irq_wake(ei->chained_irq);
/* Update registers from the cache, in case
the CPLD was powered off during suspend */
egpio_write_cache(ei);
return 0;
}
#else
#define egpio_suspend NULL
#define egpio_resume NULL
#endif
static struct platform_driver egpio_driver = {
.driver = {
.name = "htc-egpio",
.suppress_bind_attrs = true,
},
.suspend = egpio_suspend,
.resume = egpio_resume,
};
static int __init egpio_init(void)
{
return platform_driver_probe(&egpio_driver, egpio_probe);
}
/* start early for dependencies */
subsys_initcall(egpio_init);
| linux-master | drivers/gpio/gpio-htc-egpio.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-tegra/gpio.c
*
* Copyright (c) 2010 Google, Inc
* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Erik Gilling <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>
#define GPIO_BANK(x) ((x) >> 5)
#define GPIO_PORT(x) (((x) >> 3) & 0x3)
#define GPIO_BIT(x) ((x) & 0x7)
#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
GPIO_PORT(x) * 4)
#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
#define GPIO_INT_LVL_MASK 0x010101
#define GPIO_INT_LVL_EDGE_RISING 0x000101
#define GPIO_INT_LVL_EDGE_FALLING 0x000100
#define GPIO_INT_LVL_EDGE_BOTH 0x010100
#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
#define GPIO_INT_LVL_LEVEL_LOW 0x000000
struct tegra_gpio_info;
struct tegra_gpio_bank {
unsigned int bank;
/*
* IRQ-core code uses raw locking, and thus, nested locking also
* should be raw in order not to trip spinlock debug warnings.
*/
raw_spinlock_t lvl_lock[4];
/* Lock for updating debounce count register */
spinlock_t dbc_lock[4];
#ifdef CONFIG_PM_SLEEP
u32 cnf[4];
u32 out[4];
u32 oe[4];
u32 int_enb[4];
u32 int_lvl[4];
u32 wake_enb[4];
u32 dbc_enb[4];
#endif
u32 dbc_cnt[4];
};
struct tegra_gpio_soc_config {
bool debounce_supported;
u32 bank_stride;
u32 upper_offset;
};
struct tegra_gpio_info {
struct device *dev;
void __iomem *regs;
struct tegra_gpio_bank *bank_info;
const struct tegra_gpio_soc_config *soc;
struct gpio_chip gc;
u32 bank_count;
unsigned int *irqs;
};
static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
u32 val, u32 reg)
{
writel_relaxed(val, tgi->regs + reg);
}
static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
{
return readl_relaxed(tgi->regs + reg);
}
static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
unsigned int bit)
{
return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
}
static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
unsigned int gpio, u32 value)
{
u32 val;
val = 0x100 << GPIO_BIT(gpio);
if (value)
val |= 1 << GPIO_BIT(gpio);
tegra_gpio_writel(tgi, val, reg);
}
static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
{
tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
}
static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
{
tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
}
static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
return pinctrl_gpio_request(chip->base + offset);
}
static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
pinctrl_gpio_free(chip->base + offset);
tegra_gpio_disable(tgi, offset);
}
static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
}
static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
unsigned int bval = BIT(GPIO_BIT(offset));
/* If gpio is in output mode then read from the out value */
if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
}
static int tegra_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
int ret;
tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
tegra_gpio_enable(tgi, offset);
ret = pinctrl_gpio_direction_input(chip->base + offset);
if (ret < 0)
dev_err(tgi->dev,
"Failed to set pinctrl input direction of GPIO %d: %d",
chip->base + offset, ret);
return ret;
}
static int tegra_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset,
int value)
{
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
int ret;
tegra_gpio_set(chip, offset, value);
tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
tegra_gpio_enable(tgi, offset);
ret = pinctrl_gpio_direction_output(chip->base + offset);
if (ret < 0)
dev_err(tgi->dev,
"Failed to set pinctrl output direction of GPIO %d: %d",
chip->base + offset, ret);
return ret;
}
static int tegra_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
u32 pin_mask = BIT(GPIO_BIT(offset));
u32 cnf, oe;
cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
if (!(cnf & pin_mask))
return -EINVAL;
oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
if (oe & pin_mask)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
unsigned int debounce)
{
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
unsigned long flags;
unsigned int port;
if (!debounce_ms) {
tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
offset, 0);
return 0;
}
debounce_ms = min(debounce_ms, 255U);
port = GPIO_PORT(offset);
/* There is only one debounce count register per port and hence
* set the maximum of current and requested debounce time.
*/
spin_lock_irqsave(&bank->dbc_lock[port], flags);
if (bank->dbc_cnt[port] < debounce_ms) {
tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
bank->dbc_cnt[port] = debounce_ms;
}
spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
return 0;
}
static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
u32 debounce;
if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
return -ENOTSUPP;
debounce = pinconf_to_config_argument(config);
return tegra_gpio_set_debounce(chip, offset, debounce);
}
static void tegra_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
unsigned int gpio = d->hwirq;
tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
}
static void tegra_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
unsigned int gpio = d->hwirq;
tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
gpiochip_disable_irq(chip, gpio);
}
static void tegra_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
unsigned int gpio = d->hwirq;
gpiochip_enable_irq(chip, gpio);
tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
}
static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
struct tegra_gpio_bank *bank;
unsigned long flags;
int ret;
u32 val;
bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
lvl_type = GPIO_INT_LVL_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
lvl_type = GPIO_INT_LVL_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
lvl_type = GPIO_INT_LVL_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_HIGH:
lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
lvl_type = GPIO_INT_LVL_LEVEL_LOW;
break;
default:
return -EINVAL;
}
raw_spin_lock_irqsave(&bank->lvl_lock[port], flags);
val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
val |= lvl_type << GPIO_BIT(gpio);
tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
tegra_gpio_enable(tgi, gpio);
ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
if (ret) {
dev_err(tgi->dev,
"unable to lock Tegra GPIO %u as IRQ\n", gpio);
tegra_gpio_disable(tgi, gpio);
return ret;
}
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
irq_set_handler_locked(d, handle_level_irq);
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
irq_set_handler_locked(d, handle_edge_irq);
if (d->parent_data)
ret = irq_chip_set_type_parent(d, type);
return ret;
}
static void tegra_gpio_irq_shutdown(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
unsigned int gpio = d->hwirq;
tegra_gpio_irq_mask(d);
gpiochip_unlock_as_irq(&tgi->gc, gpio);
}
static void tegra_gpio_irq_handler(struct irq_desc *desc)
{
struct tegra_gpio_info *tgi = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_domain *domain = tgi->gc.irq.domain;
unsigned int irq = irq_desc_get_irq(desc);
struct tegra_gpio_bank *bank = NULL;
unsigned int port, pin, gpio, i;
bool unmasked = false;
unsigned long sta;
u32 lvl;
for (i = 0; i < tgi->bank_count; i++) {
if (tgi->irqs[i] == irq) {
bank = &tgi->bank_info[i];
break;
}
}
if (WARN_ON(bank == NULL))
return;
chained_irq_enter(chip, desc);
for (port = 0; port < 4; port++) {
gpio = tegra_gpio_compose(bank->bank, port, 0);
sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
for_each_set_bit(pin, &sta, 8) {
int ret;
tegra_gpio_writel(tgi, 1 << pin,
GPIO_INT_CLR(tgi, gpio));
/* if gpio is edge triggered, clear condition
* before executing the handler so that we don't
* miss edges
*/
if (!unmasked && lvl & (0x100 << pin)) {
unmasked = true;
chained_irq_exit(chip, desc);
}
ret = generic_handle_domain_irq(domain, gpio + pin);
WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
}
}
if (!unmasked)
chained_irq_exit(chip, desc);
}
static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
unsigned int hwirq,
unsigned int type,
unsigned int *parent_hwirq,
unsigned int *parent_type)
{
*parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
*parent_type = type;
return 0;
}
static int tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip,
union gpio_irq_fwspec *gfwspec,
unsigned int parent_hwirq,
unsigned int parent_type)
{
struct irq_fwspec *fwspec = &gfwspec->fwspec;
fwspec->fwnode = chip->irq.parent_domain->fwnode;
fwspec->param_count = 3;
fwspec->param[0] = 0;
fwspec->param[1] = parent_hwirq;
fwspec->param[2] = parent_type;
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int tegra_gpio_resume(struct device *dev)
{
struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
unsigned int b, p;
for (b = 0; b < tgi->bank_count; b++) {
struct tegra_gpio_bank *bank = &tgi->bank_info[b];
for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
unsigned int gpio = (b << 5) | (p << 3);
tegra_gpio_writel(tgi, bank->cnf[p],
GPIO_CNF(tgi, gpio));
if (tgi->soc->debounce_supported) {
tegra_gpio_writel(tgi, bank->dbc_cnt[p],
GPIO_DBC_CNT(tgi, gpio));
tegra_gpio_writel(tgi, bank->dbc_enb[p],
GPIO_MSK_DBC_EN(tgi, gpio));
}
tegra_gpio_writel(tgi, bank->out[p],
GPIO_OUT(tgi, gpio));
tegra_gpio_writel(tgi, bank->oe[p],
GPIO_OE(tgi, gpio));
tegra_gpio_writel(tgi, bank->int_lvl[p],
GPIO_INT_LVL(tgi, gpio));
tegra_gpio_writel(tgi, bank->int_enb[p],
GPIO_INT_ENB(tgi, gpio));
}
}
return 0;
}
static int tegra_gpio_suspend(struct device *dev)
{
struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
unsigned int b, p;
for (b = 0; b < tgi->bank_count; b++) {
struct tegra_gpio_bank *bank = &tgi->bank_info[b];
for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
unsigned int gpio = (b << 5) | (p << 3);
bank->cnf[p] = tegra_gpio_readl(tgi,
GPIO_CNF(tgi, gpio));
bank->out[p] = tegra_gpio_readl(tgi,
GPIO_OUT(tgi, gpio));
bank->oe[p] = tegra_gpio_readl(tgi,
GPIO_OE(tgi, gpio));
if (tgi->soc->debounce_supported) {
bank->dbc_enb[p] = tegra_gpio_readl(tgi,
GPIO_MSK_DBC_EN(tgi, gpio));
bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
bank->dbc_enb[p];
}
bank->int_enb[p] = tegra_gpio_readl(tgi,
GPIO_INT_ENB(tgi, gpio));
bank->int_lvl[p] = tegra_gpio_readl(tgi,
GPIO_INT_LVL(tgi, gpio));
/* Enable gpio irq for wake up source */
tegra_gpio_writel(tgi, bank->wake_enb[p],
GPIO_INT_ENB(tgi, gpio));
}
}
return 0;
}
static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
struct tegra_gpio_bank *bank;
unsigned int gpio = d->hwirq;
u32 port, bit, mask;
int err;
bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
port = GPIO_PORT(gpio);
bit = GPIO_BIT(gpio);
mask = BIT(bit);
err = irq_set_irq_wake(tgi->irqs[bank->bank], enable);
if (err)
return err;
if (d->parent_data) {
err = irq_chip_set_wake_parent(d, enable);
if (err) {
irq_set_irq_wake(tgi->irqs[bank->bank], !enable);
return err;
}
}
if (enable)
bank->wake_enb[port] |= mask;
else
bank->wake_enb[port] &= ~mask;
return 0;
}
#endif
static int tegra_gpio_irq_set_affinity(struct irq_data *data,
const struct cpumask *dest,
bool force)
{
if (data->parent_data)
return irq_chip_set_affinity_parent(data, dest, force);
return -EINVAL;
}
static int tegra_gpio_irq_request_resources(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
tegra_gpio_enable(tgi, d->hwirq);
return gpiochip_reqres_irq(chip, d->hwirq);
}
static void tegra_gpio_irq_release_resources(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
gpiochip_relres_irq(chip, d->hwirq);
tegra_gpio_enable(tgi, d->hwirq);
}
static void tegra_gpio_irq_print_chip(struct irq_data *d, struct seq_file *s)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
seq_printf(s, dev_name(chip->parent));
}
static const struct irq_chip tegra_gpio_irq_chip = {
.irq_shutdown = tegra_gpio_irq_shutdown,
.irq_ack = tegra_gpio_irq_ack,
.irq_mask = tegra_gpio_irq_mask,
.irq_unmask = tegra_gpio_irq_unmask,
.irq_set_type = tegra_gpio_irq_set_type,
#ifdef CONFIG_PM_SLEEP
.irq_set_wake = tegra_gpio_irq_set_wake,
#endif
.irq_print_chip = tegra_gpio_irq_print_chip,
.irq_request_resources = tegra_gpio_irq_request_resources,
.irq_release_resources = tegra_gpio_irq_release_resources,
.flags = IRQCHIP_IMMUTABLE,
};
static const struct irq_chip tegra210_gpio_irq_chip = {
.irq_shutdown = tegra_gpio_irq_shutdown,
.irq_ack = tegra_gpio_irq_ack,
.irq_mask = tegra_gpio_irq_mask,
.irq_unmask = tegra_gpio_irq_unmask,
.irq_set_affinity = tegra_gpio_irq_set_affinity,
.irq_set_type = tegra_gpio_irq_set_type,
#ifdef CONFIG_PM_SLEEP
.irq_set_wake = tegra_gpio_irq_set_wake,
#endif
.irq_print_chip = tegra_gpio_irq_print_chip,
.irq_request_resources = tegra_gpio_irq_request_resources,
.irq_release_resources = tegra_gpio_irq_release_resources,
.flags = IRQCHIP_IMMUTABLE,
};
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
{
struct tegra_gpio_info *tgi = dev_get_drvdata(s->private);
unsigned int i, j;
for (i = 0; i < tgi->bank_count; i++) {
for (j = 0; j < 4; j++) {
unsigned int gpio = tegra_gpio_compose(i, j, 0);
seq_printf(s,
"%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
i, j,
tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
}
}
return 0;
}
static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
{
debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL,
tegra_dbg_gpio_show);
}
#else
static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
{
}
#endif
static const struct dev_pm_ops tegra_gpio_pm_ops = {
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
};
static const struct of_device_id tegra_pmc_of_match[] = {
{ .compatible = "nvidia,tegra210-pmc", },
{ /* sentinel */ },
};
static int tegra_gpio_probe(struct platform_device *pdev)
{
struct tegra_gpio_bank *bank;
struct tegra_gpio_info *tgi;
struct gpio_irq_chip *irq;
struct device_node *np;
unsigned int i, j;
int ret;
tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
if (!tgi)
return -ENODEV;
tgi->soc = of_device_get_match_data(&pdev->dev);
tgi->dev = &pdev->dev;
ret = platform_irq_count(pdev);
if (ret < 0)
return ret;
tgi->bank_count = ret;
if (!tgi->bank_count) {
dev_err(&pdev->dev, "Missing IRQ resource\n");
return -ENODEV;
}
tgi->gc.label = "tegra-gpio";
tgi->gc.request = tegra_gpio_request;
tgi->gc.free = tegra_gpio_free;
tgi->gc.direction_input = tegra_gpio_direction_input;
tgi->gc.get = tegra_gpio_get;
tgi->gc.direction_output = tegra_gpio_direction_output;
tgi->gc.set = tegra_gpio_set;
tgi->gc.get_direction = tegra_gpio_get_direction;
tgi->gc.base = 0;
tgi->gc.ngpio = tgi->bank_count * 32;
tgi->gc.parent = &pdev->dev;
platform_set_drvdata(pdev, tgi);
if (tgi->soc->debounce_supported)
tgi->gc.set_config = tegra_gpio_set_config;
tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
sizeof(*tgi->bank_info), GFP_KERNEL);
if (!tgi->bank_info)
return -ENOMEM;
tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count,
sizeof(*tgi->irqs), GFP_KERNEL);
if (!tgi->irqs)
return -ENOMEM;
for (i = 0; i < tgi->bank_count; i++) {
ret = platform_get_irq(pdev, i);
if (ret < 0)
return ret;
bank = &tgi->bank_info[i];
bank->bank = i;
tgi->irqs[i] = ret;
for (j = 0; j < 4; j++) {
raw_spin_lock_init(&bank->lvl_lock[j]);
spin_lock_init(&bank->dbc_lock[j]);
}
}
irq = &tgi->gc.irq;
irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq;
irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec;
irq->handler = handle_simple_irq;
irq->default_type = IRQ_TYPE_NONE;
irq->parent_handler = tegra_gpio_irq_handler;
irq->parent_handler_data = tgi;
irq->num_parents = tgi->bank_count;
irq->parents = tgi->irqs;
np = of_find_matching_node(NULL, tegra_pmc_of_match);
if (np) {
irq->parent_domain = irq_find_host(np);
of_node_put(np);
if (!irq->parent_domain)
return -EPROBE_DEFER;
gpio_irq_chip_set_chip(irq, &tegra210_gpio_irq_chip);
} else {
gpio_irq_chip_set_chip(irq, &tegra_gpio_irq_chip);
}
tgi->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(tgi->regs))
return PTR_ERR(tgi->regs);
for (i = 0; i < tgi->bank_count; i++) {
for (j = 0; j < 4; j++) {
int gpio = tegra_gpio_compose(i, j, 0);
tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
}
}
ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
if (ret < 0)
return ret;
tegra_gpio_debuginit(tgi);
return 0;
}
static const struct tegra_gpio_soc_config tegra20_gpio_config = {
.bank_stride = 0x80,
.upper_offset = 0x800,
};
static const struct tegra_gpio_soc_config tegra30_gpio_config = {
.bank_stride = 0x100,
.upper_offset = 0x80,
};
static const struct tegra_gpio_soc_config tegra210_gpio_config = {
.debounce_supported = true,
.bank_stride = 0x100,
.upper_offset = 0x80,
};
static const struct of_device_id tegra_gpio_of_match[] = {
{ .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
{ },
};
MODULE_DEVICE_TABLE(of, tegra_gpio_of_match);
static struct platform_driver tegra_gpio_driver = {
.driver = {
.name = "tegra-gpio",
.pm = &tegra_gpio_pm_ops,
.of_match_table = tegra_gpio_of_match,
},
.probe = tegra_gpio_probe,
};
module_platform_driver(tegra_gpio_driver);
MODULE_DESCRIPTION("NVIDIA Tegra GPIO controller driver");
MODULE_AUTHOR("Laxman Dewangan <[email protected]>");
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_AUTHOR("Thierry Reding <[email protected]>");
MODULE_AUTHOR("Erik Gilling <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-tegra.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2013 TangoTec Ltd.
* Author: Baruch Siach <[email protected]>
*
* Driver for the Xtensa LX4 GPIO32 Option
*
* Documentation: Xtensa LX4 Microprocessor Data Book, Section 2.22
*
* GPIO32 is a standard optional extension to the Xtensa architecture core that
* provides preconfigured output and input ports for intra SoC signaling. The
* GPIO32 option is implemented as 32bit Tensilica Instruction Extension (TIE)
* output state called EXPSTATE, and 32bit input wire called IMPWIRE. This
* driver treats input and output states as two distinct devices.
*
* Access to GPIO32 specific instructions is controlled by the CPENABLE
* (Coprocessor Enable Bits) register. By default Xtensa Linux startup code
* disables access to all coprocessors. This driver sets the CPENABLE bit
* corresponding to GPIO32 before any GPIO32 specific instruction, and restores
* CPENABLE state after that.
*
* This driver is currently incompatible with SMP. The GPIO32 extension is not
* guaranteed to be available in all cores. Moreover, each core controls a
* different set of IO wires. A theoretical SMP aware version of this driver
* would need to have a per core workqueue to do the actual GPIO manipulation.
*/
#include <linux/err.h>
#include <linux/module.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>
#include <linux/platform_device.h>
#include <asm/coprocessor.h> /* CPENABLE read/write macros */
#ifndef XCHAL_CP_ID_XTIOP
#error GPIO32 option is not enabled for your xtensa core variant
#endif
#if XCHAL_HAVE_CP
static inline unsigned long enable_cp(unsigned long *cpenable)
{
unsigned long flags;
local_irq_save(flags);
*cpenable = xtensa_get_sr(cpenable);
xtensa_set_sr(*cpenable | BIT(XCHAL_CP_ID_XTIOP), cpenable);
return flags;
}
static inline void disable_cp(unsigned long flags, unsigned long cpenable)
{
xtensa_set_sr(cpenable, cpenable);
local_irq_restore(flags);
}
#else
static inline unsigned long enable_cp(unsigned long *cpenable)
{
*cpenable = 0; /* avoid uninitialized value warning */
return 0;
}
static inline void disable_cp(unsigned long flags, unsigned long cpenable)
{
}
#endif /* XCHAL_HAVE_CP */
static int xtensa_impwire_get_direction(struct gpio_chip *gc, unsigned offset)
{
return GPIO_LINE_DIRECTION_IN; /* input only */
}
static int xtensa_impwire_get_value(struct gpio_chip *gc, unsigned offset)
{
unsigned long flags, saved_cpenable;
u32 impwire;
flags = enable_cp(&saved_cpenable);
__asm__ __volatile__("read_impwire %0" : "=a" (impwire));
disable_cp(flags, saved_cpenable);
return !!(impwire & BIT(offset));
}
static void xtensa_impwire_set_value(struct gpio_chip *gc, unsigned offset,
int value)
{
BUG(); /* output only; should never be called */
}
static int xtensa_expstate_get_direction(struct gpio_chip *gc, unsigned offset)
{
return GPIO_LINE_DIRECTION_OUT; /* output only */
}
static int xtensa_expstate_get_value(struct gpio_chip *gc, unsigned offset)
{
unsigned long flags, saved_cpenable;
u32 expstate;
flags = enable_cp(&saved_cpenable);
__asm__ __volatile__("rur.expstate %0" : "=a" (expstate));
disable_cp(flags, saved_cpenable);
return !!(expstate & BIT(offset));
}
static void xtensa_expstate_set_value(struct gpio_chip *gc, unsigned offset,
int value)
{
unsigned long flags, saved_cpenable;
u32 mask = BIT(offset);
u32 val = value ? BIT(offset) : 0;
flags = enable_cp(&saved_cpenable);
__asm__ __volatile__("wrmsk_expstate %0, %1"
:: "a" (val), "a" (mask));
disable_cp(flags, saved_cpenable);
}
static struct gpio_chip impwire_chip = {
.label = "impwire",
.base = -1,
.ngpio = 32,
.get_direction = xtensa_impwire_get_direction,
.get = xtensa_impwire_get_value,
.set = xtensa_impwire_set_value,
};
static struct gpio_chip expstate_chip = {
.label = "expstate",
.base = -1,
.ngpio = 32,
.get_direction = xtensa_expstate_get_direction,
.get = xtensa_expstate_get_value,
.set = xtensa_expstate_set_value,
};
static int xtensa_gpio_probe(struct platform_device *pdev)
{
int ret;
ret = gpiochip_add_data(&impwire_chip, NULL);
if (ret)
return ret;
return gpiochip_add_data(&expstate_chip, NULL);
}
static struct platform_driver xtensa_gpio_driver = {
.driver = {
.name = "xtensa-gpio",
},
.probe = xtensa_gpio_probe,
};
static int __init xtensa_gpio_init(void)
{
struct platform_device *pdev;
pdev = platform_device_register_simple("xtensa-gpio", 0, NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
return platform_driver_register(&xtensa_gpio_driver);
}
device_initcall(xtensa_gpio_init);
MODULE_AUTHOR("Baruch Siach <[email protected]>");
MODULE_DESCRIPTION("Xtensa LX4 GPIO32 driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-xtensa.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2023 Analog Devices, Inc.
* Driver for the DS4520 I/O Expander
*/
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/regmap.h>
#include <linux/i2c.h>
#include <linux/property.h>
#include <linux/regmap.h>
#define DS4520_PULLUP0 0xF0
#define DS4520_IO_CONTROL0 0xF2
#define DS4520_IO_STATUS0 0xF8
static const struct regmap_config ds4520_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static int ds4520_gpio_probe(struct i2c_client *client)
{
struct gpio_regmap_config config = { };
struct device *dev = &client->dev;
struct regmap *regmap;
u32 ngpio;
u32 base;
int ret;
ret = device_property_read_u32(dev, "reg", &base);
if (ret)
return dev_err_probe(dev, ret, "Missing 'reg' property.\n");
ret = device_property_read_u32(dev, "ngpios", &ngpio);
if (ret)
return dev_err_probe(dev, ret, "Missing 'ngpios' property.\n");
regmap = devm_regmap_init_i2c(client, &ds4520_regmap_config);
if (IS_ERR(regmap))
return dev_err_probe(dev, PTR_ERR(regmap),
"Failed to allocate register map\n");
config.regmap = regmap;
config.parent = dev;
config.ngpio = ngpio;
config.reg_dat_base = base + DS4520_IO_STATUS0;
config.reg_set_base = base + DS4520_PULLUP0;
config.reg_dir_out_base = base + DS4520_IO_CONTROL0;
return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &config));
}
static const struct of_device_id ds4520_gpio_of_match_table[] = {
{ .compatible = "adi,ds4520-gpio" },
{ }
};
MODULE_DEVICE_TABLE(of, ds4520_gpio_of_match_table);
static const struct i2c_device_id ds4520_gpio_id_table[] = {
{ "ds4520-gpio" },
{ }
};
MODULE_DEVICE_TABLE(i2c, ds4520_gpio_id_table);
static struct i2c_driver ds4520_gpio_driver = {
.driver = {
.name = "ds4520-gpio",
.of_match_table = ds4520_gpio_of_match_table,
},
.probe = ds4520_gpio_probe,
.id_table = ds4520_gpio_id_table,
};
module_i2c_driver(ds4520_gpio_driver);
MODULE_DESCRIPTION("DS4520 I/O Expander");
MODULE_AUTHOR("Okan Sahin <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-ds4520.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 SiFive
*/
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/regmap.h>
#define SIFIVE_GPIO_INPUT_VAL 0x00
#define SIFIVE_GPIO_INPUT_EN 0x04
#define SIFIVE_GPIO_OUTPUT_EN 0x08
#define SIFIVE_GPIO_OUTPUT_VAL 0x0C
#define SIFIVE_GPIO_RISE_IE 0x18
#define SIFIVE_GPIO_RISE_IP 0x1C
#define SIFIVE_GPIO_FALL_IE 0x20
#define SIFIVE_GPIO_FALL_IP 0x24
#define SIFIVE_GPIO_HIGH_IE 0x28
#define SIFIVE_GPIO_HIGH_IP 0x2C
#define SIFIVE_GPIO_LOW_IE 0x30
#define SIFIVE_GPIO_LOW_IP 0x34
#define SIFIVE_GPIO_OUTPUT_XOR 0x40
#define SIFIVE_GPIO_MAX 32
struct sifive_gpio {
void __iomem *base;
struct gpio_chip gc;
struct regmap *regs;
unsigned long irq_state;
unsigned int trigger[SIFIVE_GPIO_MAX];
unsigned int irq_number[SIFIVE_GPIO_MAX];
};
static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
{
unsigned long flags;
unsigned int trigger;
raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;
regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),
(trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0);
regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset),
(trigger & IRQ_TYPE_EDGE_FALLING) ? BIT(offset) : 0);
regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset),
(trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0);
regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),
(trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0);
raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
}
static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sifive_gpio *chip = gpiochip_get_data(gc);
int offset = irqd_to_hwirq(d);
if (offset < 0 || offset >= gc->ngpio)
return -EINVAL;
chip->trigger[offset] = trigger;
sifive_gpio_set_ie(chip, offset);
return 0;
}
static void sifive_gpio_irq_enable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sifive_gpio *chip = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
int offset = hwirq % SIFIVE_GPIO_MAX;
u32 bit = BIT(offset);
unsigned long flags;
gpiochip_enable_irq(gc, hwirq);
irq_chip_enable_parent(d);
/* Switch to input */
gc->direction_input(gc, offset);
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
/* Clear any sticky pending interrupts */
regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
/* Enable interrupts */
assign_bit(offset, &chip->irq_state, 1);
sifive_gpio_set_ie(chip, offset);
}
static void sifive_gpio_irq_disable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sifive_gpio *chip = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
int offset = hwirq % SIFIVE_GPIO_MAX;
assign_bit(offset, &chip->irq_state, 0);
sifive_gpio_set_ie(chip, offset);
irq_chip_disable_parent(d);
gpiochip_disable_irq(gc, hwirq);
}
static void sifive_gpio_irq_eoi(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sifive_gpio *chip = gpiochip_get_data(gc);
int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
u32 bit = BIT(offset);
unsigned long flags;
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
/* Clear all pending interrupts */
regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
irq_chip_eoi_parent(d);
}
static int sifive_gpio_irq_set_affinity(struct irq_data *data,
const struct cpumask *dest,
bool force)
{
if (data->parent_data)
return irq_chip_set_affinity_parent(data, dest, force);
return -EINVAL;
}
static const struct irq_chip sifive_gpio_irqchip = {
.name = "sifive-gpio",
.irq_set_type = sifive_gpio_irq_set_type,
.irq_mask = irq_chip_mask_parent,
.irq_unmask = irq_chip_unmask_parent,
.irq_enable = sifive_gpio_irq_enable,
.irq_disable = sifive_gpio_irq_disable,
.irq_eoi = sifive_gpio_irq_eoi,
.irq_set_affinity = sifive_gpio_irq_set_affinity,
.irq_set_wake = irq_chip_set_wake_parent,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
unsigned int child,
unsigned int child_type,
unsigned int *parent,
unsigned int *parent_type)
{
struct sifive_gpio *chip = gpiochip_get_data(gc);
struct irq_data *d = irq_get_irq_data(chip->irq_number[child]);
*parent_type = IRQ_TYPE_NONE;
*parent = irqd_to_hwirq(d);
return 0;
}
static const struct regmap_config sifive_gpio_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
.disable_locking = true,
};
static int sifive_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct irq_domain *parent;
struct gpio_irq_chip *girq;
struct sifive_gpio *chip;
int ret, ngpio;
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(chip->base)) {
dev_err(dev, "failed to allocate device memory\n");
return PTR_ERR(chip->base);
}
chip->regs = devm_regmap_init_mmio(dev, chip->base,
&sifive_gpio_regmap_config);
if (IS_ERR(chip->regs))
return PTR_ERR(chip->regs);
for (ngpio = 0; ngpio < SIFIVE_GPIO_MAX; ngpio++) {
ret = platform_get_irq_optional(pdev, ngpio);
if (ret < 0)
break;
chip->irq_number[ngpio] = ret;
}
if (!ngpio) {
dev_err(dev, "no IRQ found\n");
return -ENODEV;
}
/*
* The check above ensures at least one parent IRQ is valid.
* Assume all parent IRQs belong to the same domain.
*/
parent = irq_get_irq_data(chip->irq_number[0])->domain;
ret = bgpio_init(&chip->gc, dev, 4,
chip->base + SIFIVE_GPIO_INPUT_VAL,
chip->base + SIFIVE_GPIO_OUTPUT_VAL,
NULL,
chip->base + SIFIVE_GPIO_OUTPUT_EN,
chip->base + SIFIVE_GPIO_INPUT_EN,
BGPIOF_READ_OUTPUT_REG_SET);
if (ret) {
dev_err(dev, "unable to init generic GPIO\n");
return ret;
}
/* Disable all GPIO interrupts before enabling parent interrupts */
regmap_write(chip->regs, SIFIVE_GPIO_RISE_IE, 0);
regmap_write(chip->regs, SIFIVE_GPIO_FALL_IE, 0);
regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IE, 0);
regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);
chip->irq_state = 0;
chip->gc.base = -1;
chip->gc.ngpio = ngpio;
chip->gc.label = dev_name(dev);
chip->gc.parent = dev;
chip->gc.owner = THIS_MODULE;
girq = &chip->gc.irq;
gpio_irq_chip_set_chip(girq, &sifive_gpio_irqchip);
girq->fwnode = dev_fwnode(dev);
girq->parent_domain = parent;
girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq;
girq->handler = handle_bad_irq;
girq->default_type = IRQ_TYPE_NONE;
platform_set_drvdata(pdev, chip);
return gpiochip_add_data(&chip->gc, chip);
}
static const struct of_device_id sifive_gpio_match[] = {
{ .compatible = "sifive,gpio0" },
{ .compatible = "sifive,fu540-c000-gpio" },
{ },
};
static struct platform_driver sifive_gpio_driver = {
.probe = sifive_gpio_probe,
.driver = {
.name = "sifive_gpio",
.of_match_table = sifive_gpio_match,
},
};
module_platform_driver(sifive_gpio_driver)
MODULE_AUTHOR("Yash Shah <[email protected]>");
MODULE_DESCRIPTION("SiFive GPIO driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-sifive.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Hanumath Prasad <[email protected]> for ST-Ericsson
* Author: Rabin Vincent <[email protected]> for ST-Ericsson
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/of.h>
#include <linux/interrupt.h>
#include <linux/mfd/tc3589x.h>
#include <linux/bitops.h>
/*
* These registers are modified under the irq bus lock and cached to avoid
* unnecessary writes in bus_sync_unlock.
*/
enum { REG_IBE, REG_IEV, REG_IS, REG_IE, REG_DIRECT };
#define CACHE_NR_REGS 5
#define CACHE_NR_BANKS 3
struct tc3589x_gpio {
struct gpio_chip chip;
struct tc3589x *tc3589x;
struct device *dev;
struct mutex irq_lock;
/* Caches of interrupt control registers for bus_lock */
u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};
static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
u8 mask = BIT(offset % 8);
int ret;
ret = tc3589x_reg_read(tc3589x, reg);
if (ret < 0)
return ret;
return !!(ret & mask);
}
static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
{
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
unsigned int pos = offset % 8;
u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
}
static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int val)
{
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
u8 reg = TC3589x_GPIODIR0 + offset / 8;
unsigned int pos = offset % 8;
tc3589x_gpio_set(chip, offset, val);
return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
}
static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
u8 reg = TC3589x_GPIODIR0 + offset / 8;
unsigned int pos = offset % 8;
return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
}
static int tc3589x_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
u8 reg = TC3589x_GPIODIR0 + offset / 8;
unsigned int pos = offset % 8;
int ret;
ret = tc3589x_reg_read(tc3589x, reg);
if (ret < 0)
return ret;
if (ret & BIT(pos))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int tc3589x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
/*
* These registers are alterated at each second address
* ODM bit 0 = drive to GND or Hi-Z (open drain)
* ODM bit 1 = drive to VDD or Hi-Z (open source)
*/
u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
unsigned int pos = offset % 8;
int ret;
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
/* Set open drain mode */
ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
if (ret)
return ret;
/* Enable open drain/source mode */
return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
case PIN_CONFIG_DRIVE_OPEN_SOURCE:
/* Set open source mode */
ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
if (ret)
return ret;
/* Enable open drain/source mode */
return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
case PIN_CONFIG_DRIVE_PUSH_PULL:
/* Disable open drain/source mode */
return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
default:
break;
}
return -ENOTSUPP;
}
static const struct gpio_chip template_chip = {
.label = "tc3589x",
.owner = THIS_MODULE,
.get = tc3589x_gpio_get,
.set = tc3589x_gpio_set,
.direction_output = tc3589x_gpio_direction_output,
.direction_input = tc3589x_gpio_direction_input,
.get_direction = tc3589x_gpio_get_direction,
.set_config = tc3589x_gpio_set_config,
.can_sleep = true,
};
static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
int offset = d->hwirq;
int regoffset = offset / 8;
int mask = BIT(offset % 8);
if (type == IRQ_TYPE_EDGE_BOTH) {
tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
return 0;
}
tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
else
tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
else
tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
return 0;
}
static void tc3589x_gpio_irq_lock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
mutex_lock(&tc3589x_gpio->irq_lock);
}
static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
static const u8 regmap[] = {
[REG_IBE] = TC3589x_GPIOIBE0,
[REG_IEV] = TC3589x_GPIOIEV0,
[REG_IS] = TC3589x_GPIOIS0,
[REG_IE] = TC3589x_GPIOIE0,
[REG_DIRECT] = TC3589x_DIRECT0,
};
int i, j;
for (i = 0; i < CACHE_NR_REGS; i++) {
for (j = 0; j < CACHE_NR_BANKS; j++) {
u8 old = tc3589x_gpio->oldregs[i][j];
u8 new = tc3589x_gpio->regs[i][j];
if (new == old)
continue;
tc3589x_gpio->oldregs[i][j] = new;
tc3589x_reg_write(tc3589x, regmap[i] + j, new);
}
}
mutex_unlock(&tc3589x_gpio->irq_lock);
}
static void tc3589x_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
int offset = d->hwirq;
int regoffset = offset / 8;
int mask = BIT(offset % 8);
tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
tc3589x_gpio->regs[REG_DIRECT][regoffset] |= mask;
gpiochip_disable_irq(gc, offset);
}
static void tc3589x_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
int offset = d->hwirq;
int regoffset = offset / 8;
int mask = BIT(offset % 8);
gpiochip_enable_irq(gc, offset);
tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
tc3589x_gpio->regs[REG_DIRECT][regoffset] &= ~mask;
}
static const struct irq_chip tc3589x_gpio_irq_chip = {
.name = "tc3589x-gpio",
.irq_bus_lock = tc3589x_gpio_irq_lock,
.irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
.irq_mask = tc3589x_gpio_irq_mask,
.irq_unmask = tc3589x_gpio_irq_unmask,
.irq_set_type = tc3589x_gpio_irq_set_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
{
struct tc3589x_gpio *tc3589x_gpio = dev;
struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
u8 status[CACHE_NR_BANKS];
int ret;
int i;
ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
ARRAY_SIZE(status), status);
if (ret < 0)
return IRQ_NONE;
for (i = 0; i < ARRAY_SIZE(status); i++) {
unsigned int stat = status[i];
if (!stat)
continue;
while (stat) {
int bit = __ffs(stat);
int line = i * 8 + bit;
int irq = irq_find_mapping(tc3589x_gpio->chip.irq.domain,
line);
handle_nested_irq(irq);
stat &= ~(1 << bit);
}
tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
}
return IRQ_HANDLED;
}
static int tc3589x_gpio_probe(struct platform_device *pdev)
{
struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
struct device_node *np = pdev->dev.of_node;
struct tc3589x_gpio *tc3589x_gpio;
struct gpio_irq_chip *girq;
int ret;
int irq;
if (!np) {
dev_err(&pdev->dev, "No Device Tree node found\n");
return -EINVAL;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
GFP_KERNEL);
if (!tc3589x_gpio)
return -ENOMEM;
mutex_init(&tc3589x_gpio->irq_lock);
tc3589x_gpio->dev = &pdev->dev;
tc3589x_gpio->tc3589x = tc3589x;
tc3589x_gpio->chip = template_chip;
tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
tc3589x_gpio->chip.parent = &pdev->dev;
tc3589x_gpio->chip.base = -1;
girq = &tc3589x_gpio->chip.irq;
gpio_irq_chip_set_chip(girq, &tc3589x_gpio_irq_chip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
girq->threaded = true;
/* Bring the GPIO module out of reset */
ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
TC3589x_RSTCTRL_GPIRST, 0);
if (ret < 0)
return ret;
/* For tc35894, have to disable Direct KBD interrupts,
* else IRQST will always be 0x20, IRQN low level, can't
* clear the irq status.
* TODO: need more test on other tc3589x chip.
*
*/
ret = tc3589x_reg_write(tc3589x, TC3589x_DKBDMSK,
TC3589x_DKBDMSK_ELINT | TC3589x_DKBDMSK_EINT);
if (ret < 0)
return ret;
ret = devm_request_threaded_irq(&pdev->dev,
irq, NULL, tc3589x_gpio_irq,
IRQF_ONESHOT, "tc3589x-gpio",
tc3589x_gpio);
if (ret) {
dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
return ret;
}
return devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip, tc3589x_gpio);
}
static struct platform_driver tc3589x_gpio_driver = {
.driver.name = "tc3589x-gpio",
.probe = tc3589x_gpio_probe,
};
static int __init tc3589x_gpio_init(void)
{
return platform_driver_register(&tc3589x_gpio_driver);
}
subsys_initcall(tc3589x_gpio_init);
| linux-master | drivers/gpio/gpio-tc3589x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Delta TN48M CPLD GPIO driver
*
* Copyright (C) 2021 Sartura Ltd.
*
* Author: Robert Marko <[email protected]>
*/
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/regmap.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
enum tn48m_gpio_type {
TN48M_GP0 = 1,
TN48M_GPI,
};
struct tn48m_gpio_config {
int ngpio;
int ngpio_per_reg;
enum tn48m_gpio_type type;
};
static const struct tn48m_gpio_config tn48m_gpo_config = {
.ngpio = 4,
.ngpio_per_reg = 4,
.type = TN48M_GP0,
};
static const struct tn48m_gpio_config tn48m_gpi_config = {
.ngpio = 4,
.ngpio_per_reg = 4,
.type = TN48M_GPI,
};
static int tn48m_gpio_probe(struct platform_device *pdev)
{
const struct tn48m_gpio_config *gpio_config;
struct gpio_regmap_config config = {};
struct regmap *regmap;
u32 base;
int ret;
if (!pdev->dev.parent)
return -ENODEV;
gpio_config = device_get_match_data(&pdev->dev);
if (!gpio_config)
return -ENODEV;
ret = device_property_read_u32(&pdev->dev, "reg", &base);
if (ret)
return ret;
regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!regmap)
return -ENODEV;
config.regmap = regmap;
config.parent = &pdev->dev;
config.ngpio = gpio_config->ngpio;
config.ngpio_per_reg = gpio_config->ngpio_per_reg;
switch (gpio_config->type) {
case TN48M_GP0:
config.reg_set_base = base;
break;
case TN48M_GPI:
config.reg_dat_base = base;
break;
default:
return -EINVAL;
}
return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(&pdev->dev, &config));
}
static const struct of_device_id tn48m_gpio_of_match[] = {
{ .compatible = "delta,tn48m-gpo", .data = &tn48m_gpo_config },
{ .compatible = "delta,tn48m-gpi", .data = &tn48m_gpi_config },
{ }
};
MODULE_DEVICE_TABLE(of, tn48m_gpio_of_match);
static struct platform_driver tn48m_gpio_driver = {
.driver = {
.name = "delta-tn48m-gpio",
.of_match_table = tn48m_gpio_of_match,
},
.probe = tn48m_gpio_probe,
};
module_platform_driver(tn48m_gpio_driver);
MODULE_AUTHOR("Robert Marko <[email protected]>");
MODULE_DESCRIPTION("Delta TN48M CPLD GPIO driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-tn48m.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <[email protected]> for ST-Ericsson
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/mfd/stmpe.h>
#include <linux/seq_file.h>
#include <linux/bitops.h>
/*
* These registers are modified under the irq bus lock and cached to avoid
* unnecessary writes in bus_sync_unlock.
*/
enum { REG_RE, REG_FE, REG_IE };
enum { LSB, CSB, MSB };
#define CACHE_NR_REGS 3
/* No variant has more than 24 GPIOs */
#define CACHE_NR_BANKS (24 / 8)
struct stmpe_gpio {
struct gpio_chip chip;
struct stmpe *stmpe;
struct device *dev;
struct mutex irq_lock;
u32 norequest_mask;
/* Caches of interrupt control registers for bus_lock */
u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};
static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
struct stmpe *stmpe = stmpe_gpio->stmpe;
u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
u8 mask = BIT(offset % 8);
int ret;
ret = stmpe_reg_read(stmpe, reg);
if (ret < 0)
return ret;
return !!(ret & mask);
}
static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
struct stmpe *stmpe = stmpe_gpio->stmpe;
int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
u8 reg = stmpe->regs[which + (offset / 8)];
u8 mask = BIT(offset % 8);
/*
* Some variants have single register for gpio set/clear functionality.
* For them we need to write 0 to clear and 1 to set.
*/
if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
else
stmpe_reg_write(stmpe, reg, mask);
}
static int stmpe_gpio_get_direction(struct gpio_chip *chip,
unsigned offset)
{
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
struct stmpe *stmpe = stmpe_gpio->stmpe;
u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
u8 mask = BIT(offset % 8);
int ret;
ret = stmpe_reg_read(stmpe, reg);
if (ret < 0)
return ret;
if (ret & mask)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int stmpe_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int val)
{
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
struct stmpe *stmpe = stmpe_gpio->stmpe;
u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
u8 mask = BIT(offset % 8);
stmpe_gpio_set(chip, offset, val);
return stmpe_set_bits(stmpe, reg, mask, mask);
}
static int stmpe_gpio_direction_input(struct gpio_chip *chip,
unsigned offset)
{
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
struct stmpe *stmpe = stmpe_gpio->stmpe;
u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
u8 mask = BIT(offset % 8);
return stmpe_set_bits(stmpe, reg, mask, 0);
}
static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
struct stmpe *stmpe = stmpe_gpio->stmpe;
if (stmpe_gpio->norequest_mask & BIT(offset))
return -EINVAL;
return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
}
static const struct gpio_chip template_chip = {
.label = "stmpe",
.owner = THIS_MODULE,
.get_direction = stmpe_gpio_get_direction,
.direction_input = stmpe_gpio_direction_input,
.get = stmpe_gpio_get,
.direction_output = stmpe_gpio_direction_output,
.set = stmpe_gpio_set,
.request = stmpe_gpio_request,
.can_sleep = true,
};
static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
int offset = d->hwirq;
int regoffset = offset / 8;
int mask = BIT(offset % 8);
if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
return -EINVAL;
/* STMPE801 and STMPE 1600 don't have RE and FE registers */
if (stmpe_gpio->stmpe->partnum == STMPE801 ||
stmpe_gpio->stmpe->partnum == STMPE1600)
return 0;
if (type & IRQ_TYPE_EDGE_RISING)
stmpe_gpio->regs[REG_RE][regoffset] |= mask;
else
stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
if (type & IRQ_TYPE_EDGE_FALLING)
stmpe_gpio->regs[REG_FE][regoffset] |= mask;
else
stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
return 0;
}
static void stmpe_gpio_irq_lock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
mutex_lock(&stmpe_gpio->irq_lock);
}
static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
struct stmpe *stmpe = stmpe_gpio->stmpe;
int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
};
int i, j;
/*
* STMPE1600: to be able to get IRQ from pins,
* a read must be done on GPMR register, or a write in
* GPSR or GPCR registers
*/
if (stmpe->partnum == STMPE1600) {
stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
}
for (i = 0; i < CACHE_NR_REGS; i++) {
/* STMPE801 and STMPE1600 don't have RE and FE registers */
if ((stmpe->partnum == STMPE801 ||
stmpe->partnum == STMPE1600) &&
(i != REG_IE))
continue;
for (j = 0; j < num_banks; j++) {
u8 old = stmpe_gpio->oldregs[i][j];
u8 new = stmpe_gpio->regs[i][j];
if (new == old)
continue;
stmpe_gpio->oldregs[i][j] = new;
stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
}
}
mutex_unlock(&stmpe_gpio->irq_lock);
}
static void stmpe_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
int offset = d->hwirq;
int regoffset = offset / 8;
int mask = BIT(offset % 8);
stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
gpiochip_disable_irq(gc, offset);
}
static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
int offset = d->hwirq;
int regoffset = offset / 8;
int mask = BIT(offset % 8);
gpiochip_enable_irq(gc, offset);
stmpe_gpio->regs[REG_IE][regoffset] |= mask;
}
static void stmpe_dbg_show_one(struct seq_file *s,
struct gpio_chip *gc,
unsigned offset, unsigned gpio)
{
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
struct stmpe *stmpe = stmpe_gpio->stmpe;
const char *label = gpiochip_is_requested(gc, offset);
bool val = !!stmpe_gpio_get(gc, offset);
u8 bank = offset / 8;
u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
u8 mask = BIT(offset % 8);
int ret;
u8 dir;
ret = stmpe_reg_read(stmpe, dir_reg);
if (ret < 0)
return;
dir = !!(ret & mask);
if (dir) {
seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
gpio, label ?: "(none)",
val ? "hi" : "lo");
} else {
u8 edge_det_reg;
u8 rise_reg;
u8 fall_reg;
u8 irqen_reg;
static const char * const edge_det_values[] = {
"edge-inactive",
"edge-asserted",
"not-supported"
};
static const char * const rise_values[] = {
"no-rising-edge-detection",
"rising-edge-detection",
"not-supported"
};
static const char * const fall_values[] = {
"no-falling-edge-detection",
"falling-edge-detection",
"not-supported"
};
#define NOT_SUPPORTED_IDX 2
u8 edge_det = NOT_SUPPORTED_IDX;
u8 rise = NOT_SUPPORTED_IDX;
u8 fall = NOT_SUPPORTED_IDX;
bool irqen;
switch (stmpe->partnum) {
case STMPE610:
case STMPE811:
case STMPE1601:
case STMPE2401:
case STMPE2403:
edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
ret = stmpe_reg_read(stmpe, edge_det_reg);
if (ret < 0)
return;
edge_det = !!(ret & mask);
fallthrough;
case STMPE1801:
rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
ret = stmpe_reg_read(stmpe, rise_reg);
if (ret < 0)
return;
rise = !!(ret & mask);
ret = stmpe_reg_read(stmpe, fall_reg);
if (ret < 0)
return;
fall = !!(ret & mask);
fallthrough;
case STMPE801:
case STMPE1600:
irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
break;
default:
return;
}
ret = stmpe_reg_read(stmpe, irqen_reg);
if (ret < 0)
return;
irqen = !!(ret & mask);
seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
gpio, label ?: "(none)",
val ? "hi" : "lo",
edge_det_values[edge_det],
irqen ? "IRQ-enabled" : "IRQ-disabled",
rise_values[rise],
fall_values[fall]);
}
}
static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
{
unsigned i;
unsigned gpio = gc->base;
for (i = 0; i < gc->ngpio; i++, gpio++) {
stmpe_dbg_show_one(s, gc, i, gpio);
seq_putc(s, '\n');
}
}
static const struct irq_chip stmpe_gpio_irq_chip = {
.name = "stmpe-gpio",
.irq_bus_lock = stmpe_gpio_irq_lock,
.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
.irq_mask = stmpe_gpio_irq_mask,
.irq_unmask = stmpe_gpio_irq_unmask,
.irq_set_type = stmpe_gpio_irq_set_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
#define MAX_GPIOS 24
static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
{
struct stmpe_gpio *stmpe_gpio = dev;
struct stmpe *stmpe = stmpe_gpio->stmpe;
u8 statmsbreg;
int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
int ret;
int i;
/*
* the stmpe_block_read() call below, imposes to set statmsbreg
* with the register located at the lowest address. As STMPE1600
* variant is the only one which respect registers address's order
* (LSB regs located at lowest address than MSB ones) whereas all
* the others have a registers layout with MSB located before the
* LSB regs.
*/
if (stmpe->partnum == STMPE1600)
statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
else
statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
if (ret < 0)
return IRQ_NONE;
for (i = 0; i < num_banks; i++) {
int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
num_banks - i - 1;
unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
unsigned int stat = status[i];
stat &= enabled;
if (!stat)
continue;
while (stat) {
int bit = __ffs(stat);
int line = bank * 8 + bit;
int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
line);
handle_nested_irq(child_irq);
stat &= ~BIT(bit);
}
/*
* interrupt status register write has no effect on
* 801/1801/1600, bits are cleared when read.
* Edge detect register is not present on 801/1600/1801
*/
if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
stmpe->partnum != STMPE1801) {
stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
stmpe_reg_write(stmpe,
stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
status[i]);
}
}
return IRQ_HANDLED;
}
static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
unsigned long *valid_mask,
unsigned int ngpios)
{
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
int i;
if (!stmpe_gpio->norequest_mask)
return;
/* Forbid unused lines to be mapped as IRQs */
for (i = 0; i < sizeof(u32); i++) {
if (stmpe_gpio->norequest_mask & BIT(i))
clear_bit(i, valid_mask);
}
}
static void stmpe_gpio_disable(void *stmpe)
{
stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
}
static int stmpe_gpio_probe(struct platform_device *pdev)
{
struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
struct device_node *np = pdev->dev.of_node;
struct stmpe_gpio *stmpe_gpio;
int ret, irq;
if (stmpe->num_gpios > MAX_GPIOS) {
dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
return -EINVAL;
}
stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL);
if (!stmpe_gpio)
return -ENOMEM;
mutex_init(&stmpe_gpio->irq_lock);
stmpe_gpio->dev = &pdev->dev;
stmpe_gpio->stmpe = stmpe;
stmpe_gpio->chip = template_chip;
stmpe_gpio->chip.ngpio = stmpe->num_gpios;
stmpe_gpio->chip.parent = &pdev->dev;
stmpe_gpio->chip.base = -1;
if (IS_ENABLED(CONFIG_DEBUG_FS))
stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
of_property_read_u32(np, "st,norequest-mask",
&stmpe_gpio->norequest_mask);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
dev_info(&pdev->dev,
"device configured in no-irq mode: "
"irqs are not available\n");
ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
if (ret)
return ret;
ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe);
if (ret)
return ret;
if (irq > 0) {
struct gpio_irq_chip *girq;
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
stmpe_gpio_irq, IRQF_ONESHOT,
"stmpe-gpio", stmpe_gpio);
if (ret) {
dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
return ret;
}
girq = &stmpe_gpio->chip.irq;
gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
girq->threaded = true;
girq->init_valid_mask = stmpe_init_irq_valid_mask;
}
return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio);
}
static struct platform_driver stmpe_gpio_driver = {
.driver = {
.suppress_bind_attrs = true,
.name = "stmpe-gpio",
},
.probe = stmpe_gpio_probe,
};
static int __init stmpe_gpio_init(void)
{
return platform_driver_register(&stmpe_gpio_driver);
}
subsys_initcall(stmpe_gpio_init);
| linux-master | drivers/gpio/gpio-stmpe.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* GPIO driver for the AMD G series FCH (eg. GX-412TC)
*
* Copyright (C) 2018 metux IT consult
* Author: Enrico Weigelt, metux IT consult <[email protected]>
*
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>
#include <linux/platform_data/gpio/gpio-amd-fch.h>
#include <linux/spinlock.h>
#define AMD_FCH_MMIO_BASE 0xFED80000
#define AMD_FCH_GPIO_BANK0_BASE 0x1500
#define AMD_FCH_GPIO_SIZE 0x0300
#define AMD_FCH_GPIO_FLAG_DIRECTION BIT(23)
#define AMD_FCH_GPIO_FLAG_WRITE BIT(22)
#define AMD_FCH_GPIO_FLAG_READ BIT(16)
static const struct resource amd_fch_gpio_iores =
DEFINE_RES_MEM_NAMED(
AMD_FCH_MMIO_BASE + AMD_FCH_GPIO_BANK0_BASE,
AMD_FCH_GPIO_SIZE,
"amd-fch-gpio-iomem");
struct amd_fch_gpio_priv {
struct gpio_chip gc;
void __iomem *base;
struct amd_fch_gpio_pdata *pdata;
spinlock_t lock;
};
static void __iomem *amd_fch_gpio_addr(struct amd_fch_gpio_priv *priv,
unsigned int gpio)
{
return priv->base + priv->pdata->gpio_reg[gpio]*sizeof(u32);
}
static int amd_fch_gpio_direction_input(struct gpio_chip *gc,
unsigned int offset)
{
unsigned long flags;
struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
spin_lock_irqsave(&priv->lock, flags);
writel_relaxed(readl_relaxed(ptr) & ~AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
static int amd_fch_gpio_direction_output(struct gpio_chip *gc,
unsigned int gpio, int value)
{
unsigned long flags;
struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
u32 val;
spin_lock_irqsave(&priv->lock, flags);
val = readl_relaxed(ptr);
if (value)
val |= AMD_FCH_GPIO_FLAG_WRITE;
else
val &= ~AMD_FCH_GPIO_FLAG_WRITE;
writel_relaxed(val | AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
static int amd_fch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
{
int ret;
unsigned long flags;
struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
spin_lock_irqsave(&priv->lock, flags);
ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_DIRECTION);
spin_unlock_irqrestore(&priv->lock, flags);
return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
}
static void amd_fch_gpio_set(struct gpio_chip *gc,
unsigned int gpio, int value)
{
unsigned long flags;
struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
u32 mask;
spin_lock_irqsave(&priv->lock, flags);
mask = readl_relaxed(ptr);
if (value)
mask |= AMD_FCH_GPIO_FLAG_WRITE;
else
mask &= ~AMD_FCH_GPIO_FLAG_WRITE;
writel_relaxed(mask, ptr);
spin_unlock_irqrestore(&priv->lock, flags);
}
static int amd_fch_gpio_get(struct gpio_chip *gc,
unsigned int offset)
{
unsigned long flags;
int ret;
struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
spin_lock_irqsave(&priv->lock, flags);
ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_READ);
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
}
static int amd_fch_gpio_request(struct gpio_chip *chip,
unsigned int gpio_pin)
{
return 0;
}
static int amd_fch_gpio_probe(struct platform_device *pdev)
{
struct amd_fch_gpio_priv *priv;
struct amd_fch_gpio_pdata *pdata;
pdata = dev_get_platdata(&pdev->dev);
if (!pdata) {
dev_err(&pdev->dev, "no platform_data\n");
return -ENOENT;
}
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->pdata = pdata;
priv->gc.owner = THIS_MODULE;
priv->gc.parent = &pdev->dev;
priv->gc.label = dev_name(&pdev->dev);
priv->gc.ngpio = priv->pdata->gpio_num;
priv->gc.names = priv->pdata->gpio_names;
priv->gc.base = -1;
priv->gc.request = amd_fch_gpio_request;
priv->gc.direction_input = amd_fch_gpio_direction_input;
priv->gc.direction_output = amd_fch_gpio_direction_output;
priv->gc.get_direction = amd_fch_gpio_get_direction;
priv->gc.get = amd_fch_gpio_get;
priv->gc.set = amd_fch_gpio_set;
spin_lock_init(&priv->lock);
priv->base = devm_ioremap_resource(&pdev->dev, &amd_fch_gpio_iores);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
platform_set_drvdata(pdev, priv);
return devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
}
static struct platform_driver amd_fch_gpio_driver = {
.driver = {
.name = AMD_FCH_GPIO_DRIVER_NAME,
},
.probe = amd_fch_gpio_probe,
};
module_platform_driver(amd_fch_gpio_driver);
MODULE_AUTHOR("Enrico Weigelt, metux IT consult <[email protected]>");
MODULE_DESCRIPTION("AMD G-series FCH GPIO driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" AMD_FCH_GPIO_DRIVER_NAME);
| linux-master | drivers/gpio/gpio-amd-fch.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Keerthy <[email protected]>
*
* Based on the LP873X driver
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/lp87565.h>
struct lp87565_gpio {
struct gpio_chip chip;
struct regmap *map;
};
static int lp87565_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct lp87565_gpio *gpio = gpiochip_get_data(chip);
int ret, val;
ret = regmap_read(gpio->map, LP87565_REG_GPIO_IN, &val);
if (ret < 0)
return ret;
return !!(val & BIT(offset));
}
static void lp87565_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct lp87565_gpio *gpio = gpiochip_get_data(chip);
regmap_update_bits(gpio->map, LP87565_REG_GPIO_OUT,
BIT(offset), value ? BIT(offset) : 0);
}
static int lp87565_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
struct lp87565_gpio *gpio = gpiochip_get_data(chip);
int ret, val;
ret = regmap_read(gpio->map, LP87565_REG_GPIO_CONFIG, &val);
if (ret < 0)
return ret;
if (val & BIT(offset))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int lp87565_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct lp87565_gpio *gpio = gpiochip_get_data(chip);
return regmap_update_bits(gpio->map,
LP87565_REG_GPIO_CONFIG,
BIT(offset), 0);
}
static int lp87565_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct lp87565_gpio *gpio = gpiochip_get_data(chip);
lp87565_gpio_set(chip, offset, value);
return regmap_update_bits(gpio->map,
LP87565_REG_GPIO_CONFIG,
BIT(offset), BIT(offset));
}
static int lp87565_gpio_request(struct gpio_chip *gc, unsigned int offset)
{
struct lp87565_gpio *gpio = gpiochip_get_data(gc);
int ret;
switch (offset) {
case 0:
case 1:
case 2:
/*
* MUX can program the pin to be in EN1/2/3 pin mode
* Or GPIO1/2/3 mode.
* Setup the GPIO*_SEL MUX to GPIO mode
*/
ret = regmap_update_bits(gpio->map,
LP87565_REG_PIN_FUNCTION,
BIT(offset), BIT(offset));
if (ret)
return ret;
break;
default:
return -EINVAL;
}
return 0;
}
static int lp87565_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
unsigned long config)
{
struct lp87565_gpio *gpio = gpiochip_get_data(gc);
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
return regmap_update_bits(gpio->map,
LP87565_REG_GPIO_CONFIG,
BIT(offset +
__ffs(LP87565_GPIO1_OD)),
BIT(offset +
__ffs(LP87565_GPIO1_OD)));
case PIN_CONFIG_DRIVE_PUSH_PULL:
return regmap_update_bits(gpio->map,
LP87565_REG_GPIO_CONFIG,
BIT(offset +
__ffs(LP87565_GPIO1_OD)), 0);
default:
return -ENOTSUPP;
}
}
static const struct gpio_chip template_chip = {
.label = "lp87565-gpio",
.owner = THIS_MODULE,
.request = lp87565_gpio_request,
.get_direction = lp87565_gpio_get_direction,
.direction_input = lp87565_gpio_direction_input,
.direction_output = lp87565_gpio_direction_output,
.get = lp87565_gpio_get,
.set = lp87565_gpio_set,
.set_config = lp87565_gpio_set_config,
.base = -1,
.ngpio = 3,
.can_sleep = true,
};
static int lp87565_gpio_probe(struct platform_device *pdev)
{
struct lp87565_gpio *gpio;
struct lp87565 *lp87565;
int ret;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
lp87565 = dev_get_drvdata(pdev->dev.parent);
gpio->chip = template_chip;
gpio->chip.parent = lp87565->dev;
gpio->map = lp87565->regmap;
ret = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
if (ret < 0) {
dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
return ret;
}
return 0;
}
static const struct platform_device_id lp87565_gpio_id_table[] = {
{ "lp87565-q1-gpio", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, lp87565_gpio_id_table);
static struct platform_driver lp87565_gpio_driver = {
.driver = {
.name = "lp87565-gpio",
},
.probe = lp87565_gpio_probe,
.id_table = lp87565_gpio_id_table,
};
module_platform_driver(lp87565_gpio_driver);
MODULE_AUTHOR("Keerthy <[email protected]>");
MODULE_DESCRIPTION("LP87565 GPIO driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-lp87565.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/slab.h>
#define PCH_EDGE_FALLING 0
#define PCH_EDGE_RISING 1
#define PCH_LEVEL_L 2
#define PCH_LEVEL_H 3
#define PCH_EDGE_BOTH 4
#define PCH_IM_MASK GENMASK(2, 0)
#define PCH_IRQ_BASE 24
struct pch_regs {
u32 ien;
u32 istatus;
u32 idisp;
u32 iclr;
u32 imask;
u32 imaskclr;
u32 po;
u32 pi;
u32 pm;
u32 im0;
u32 im1;
u32 reserved[3];
u32 gpio_use_sel;
u32 reset;
};
#define PCI_DEVICE_ID_INTEL_EG20T_PCH 0x8803
#define PCI_DEVICE_ID_ROHM_ML7223m_IOH 0x8014
#define PCI_DEVICE_ID_ROHM_ML7223n_IOH 0x8043
#define PCI_DEVICE_ID_ROHM_EG20T_PCH 0x8803
enum pch_type_t {
INTEL_EG20T_PCH,
OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
};
/* Specifies number of GPIO PINS */
static int gpio_pins[] = {
[INTEL_EG20T_PCH] = 12,
[OKISEMI_ML7223m_IOH] = 8,
[OKISEMI_ML7223n_IOH] = 8,
};
/**
* struct pch_gpio_reg_data - The register store data.
* @ien_reg: To store contents of IEN register.
* @imask_reg: To store contents of IMASK register.
* @po_reg: To store contents of PO register.
* @pm_reg: To store contents of PM register.
* @im0_reg: To store contents of IM0 register.
* @im1_reg: To store contents of IM1 register.
* @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
* (Only ML7223 Bus-n)
*/
struct pch_gpio_reg_data {
u32 ien_reg;
u32 imask_reg;
u32 po_reg;
u32 pm_reg;
u32 im0_reg;
u32 im1_reg;
u32 gpio_use_sel_reg;
};
/**
* struct pch_gpio - GPIO private data structure.
* @base: PCI base address of Memory mapped I/O register.
* @reg: Memory mapped PCH GPIO register list.
* @dev: Pointer to device structure.
* @gpio: Data for GPIO infrastructure.
* @pch_gpio_reg: Memory mapped Register data is saved here
* when suspend.
* @lock: Used for register access protection
* @irq_base: Save base of IRQ number for interrupt
* @ioh: IOH ID
* @spinlock: Used for register access protection
*/
struct pch_gpio {
void __iomem *base;
struct pch_regs __iomem *reg;
struct device *dev;
struct gpio_chip gpio;
struct pch_gpio_reg_data pch_gpio_reg;
int irq_base;
enum pch_type_t ioh;
spinlock_t spinlock;
};
static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
{
u32 reg_val;
struct pch_gpio *chip = gpiochip_get_data(gpio);
unsigned long flags;
spin_lock_irqsave(&chip->spinlock, flags);
reg_val = ioread32(&chip->reg->po);
if (val)
reg_val |= BIT(nr);
else
reg_val &= ~BIT(nr);
iowrite32(reg_val, &chip->reg->po);
spin_unlock_irqrestore(&chip->spinlock, flags);
}
static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
{
struct pch_gpio *chip = gpiochip_get_data(gpio);
return !!(ioread32(&chip->reg->pi) & BIT(nr));
}
static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
int val)
{
struct pch_gpio *chip = gpiochip_get_data(gpio);
u32 pm;
u32 reg_val;
unsigned long flags;
spin_lock_irqsave(&chip->spinlock, flags);
reg_val = ioread32(&chip->reg->po);
if (val)
reg_val |= BIT(nr);
else
reg_val &= ~BIT(nr);
iowrite32(reg_val, &chip->reg->po);
pm = ioread32(&chip->reg->pm);
pm &= BIT(gpio_pins[chip->ioh]) - 1;
pm |= BIT(nr);
iowrite32(pm, &chip->reg->pm);
spin_unlock_irqrestore(&chip->spinlock, flags);
return 0;
}
static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
{
struct pch_gpio *chip = gpiochip_get_data(gpio);
u32 pm;
unsigned long flags;
spin_lock_irqsave(&chip->spinlock, flags);
pm = ioread32(&chip->reg->pm);
pm &= BIT(gpio_pins[chip->ioh]) - 1;
pm &= ~BIT(nr);
iowrite32(pm, &chip->reg->pm);
spin_unlock_irqrestore(&chip->spinlock, flags);
return 0;
}
/*
* Save register configuration and disable interrupts.
*/
static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
{
chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
if (chip->ioh == INTEL_EG20T_PCH)
chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
if (chip->ioh == OKISEMI_ML7223n_IOH)
chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
}
/*
* This function restores the register configuration of the GPIO device.
*/
static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
{
iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
/* to store contents of PO register */
iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
/* to store contents of PM register */
iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
if (chip->ioh == INTEL_EG20T_PCH)
iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
if (chip->ioh == OKISEMI_ML7223n_IOH)
iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
}
static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
{
struct pch_gpio *chip = gpiochip_get_data(gpio);
return chip->irq_base + offset;
}
static void pch_gpio_setup(struct pch_gpio *chip)
{
struct gpio_chip *gpio = &chip->gpio;
gpio->label = dev_name(chip->dev);
gpio->parent = chip->dev;
gpio->owner = THIS_MODULE;
gpio->direction_input = pch_gpio_direction_input;
gpio->get = pch_gpio_get;
gpio->direction_output = pch_gpio_direction_output;
gpio->set = pch_gpio_set;
gpio->base = -1;
gpio->ngpio = gpio_pins[chip->ioh];
gpio->can_sleep = false;
gpio->to_irq = pch_gpio_to_irq;
}
static int pch_irq_type(struct irq_data *d, unsigned int type)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct pch_gpio *chip = gc->private;
u32 im, im_pos, val;
u32 __iomem *im_reg;
unsigned long flags;
int ch, irq = d->irq;
ch = irq - chip->irq_base;
if (irq < chip->irq_base + 8) {
im_reg = &chip->reg->im0;
im_pos = ch - 0;
} else {
im_reg = &chip->reg->im1;
im_pos = ch - 8;
}
dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
val = PCH_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
val = PCH_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
val = PCH_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_HIGH:
val = PCH_LEVEL_H;
break;
case IRQ_TYPE_LEVEL_LOW:
val = PCH_LEVEL_L;
break;
default:
return 0;
}
spin_lock_irqsave(&chip->spinlock, flags);
/* Set interrupt mode */
im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
iowrite32(im | (val << (im_pos * 4)), im_reg);
/* And the handler */
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
else if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(d, handle_edge_irq);
spin_unlock_irqrestore(&chip->spinlock, flags);
return 0;
}
static void pch_irq_unmask(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct pch_gpio *chip = gc->private;
iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
}
static void pch_irq_mask(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct pch_gpio *chip = gc->private;
iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
}
static void pch_irq_ack(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct pch_gpio *chip = gc->private;
iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
}
static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
{
struct pch_gpio *chip = dev_id;
unsigned long reg_val = ioread32(&chip->reg->istatus);
int i;
dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val);
reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
for_each_set_bit(i, ®_val, gpio_pins[chip->ioh])
generic_handle_irq(chip->irq_base + i);
return IRQ_RETVAL(reg_val);
}
static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
unsigned int irq_start,
unsigned int num)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
int rv;
gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
chip->base, handle_simple_irq);
if (!gc)
return -ENOMEM;
gc->private = chip;
ct = gc->chip_types;
ct->chip.irq_ack = pch_irq_ack;
ct->chip.irq_mask = pch_irq_mask;
ct->chip.irq_unmask = pch_irq_unmask;
ct->chip.irq_set_type = pch_irq_type;
rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
return rv;
}
static int pch_gpio_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct device *dev = &pdev->dev;
s32 ret;
struct pch_gpio *chip;
int irq_base;
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (chip == NULL)
return -ENOMEM;
chip->dev = dev;
ret = pcim_enable_device(pdev);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable PCI device\n");
ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
if (ret)
return dev_err_probe(dev, ret, "Failed to request and map PCI regions\n");
chip->base = pcim_iomap_table(pdev)[1];
chip->ioh = id->driver_data;
chip->reg = chip->base;
pci_set_drvdata(pdev, chip);
spin_lock_init(&chip->spinlock);
pch_gpio_setup(chip);
ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
if (ret)
return dev_err_probe(dev, ret, "Failed to register GPIO\n");
irq_base = devm_irq_alloc_descs(dev, -1, 0,
gpio_pins[chip->ioh], NUMA_NO_NODE);
if (irq_base < 0) {
dev_warn(dev, "PCH gpio: Failed to get IRQ base num\n");
chip->irq_base = -1;
return 0;
}
chip->irq_base = irq_base;
/* Mask all interrupts, but enable them */
iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler,
IRQF_SHARED, KBUILD_MODNAME, chip);
if (ret)
return dev_err_probe(dev, ret, "Failed to request IRQ\n");
return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
}
static int __maybe_unused pch_gpio_suspend(struct device *dev)
{
struct pch_gpio *chip = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&chip->spinlock, flags);
pch_gpio_save_reg_conf(chip);
spin_unlock_irqrestore(&chip->spinlock, flags);
return 0;
}
static int __maybe_unused pch_gpio_resume(struct device *dev)
{
struct pch_gpio *chip = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&chip->spinlock, flags);
iowrite32(0x01, &chip->reg->reset);
iowrite32(0x00, &chip->reg->reset);
pch_gpio_restore_reg_conf(chip);
spin_unlock_irqrestore(&chip->spinlock, flags);
return 0;
}
static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
static const struct pci_device_id pch_gpio_pcidev_id[] = {
{ PCI_DEVICE_DATA(INTEL, EG20T_PCH, INTEL_EG20T_PCH) },
{ PCI_DEVICE_DATA(ROHM, ML7223m_IOH, OKISEMI_ML7223m_IOH) },
{ PCI_DEVICE_DATA(ROHM, ML7223n_IOH, OKISEMI_ML7223n_IOH) },
{ PCI_DEVICE_DATA(ROHM, EG20T_PCH, INTEL_EG20T_PCH) },
{ }
};
MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
static struct pci_driver pch_gpio_driver = {
.name = "pch_gpio",
.id_table = pch_gpio_pcidev_id,
.probe = pch_gpio_probe,
.driver = {
.pm = &pch_gpio_pm_ops,
},
};
module_pci_driver(pch_gpio_driver);
MODULE_DESCRIPTION("PCH GPIO PCI Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-pch.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* FXL6408 GPIO driver
*
* Copyright 2023 Toradex
*
* Author: Emanuele Ghidoli <[email protected]>
*/
#include <linux/err.h>
#include <linux/gpio/regmap.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#define FXL6408_REG_DEVICE_ID 0x01
#define FXL6408_MF_FAIRCHILD 0b101
#define FXL6408_MF_SHIFT 5
/* Bits set here indicate that the GPIO is an output. */
#define FXL6408_REG_IO_DIR 0x03
/*
* Bits set here, when the corresponding bit of IO_DIR is set, drive
* the output high instead of low.
*/
#define FXL6408_REG_OUTPUT 0x05
/* Bits here make the output High-Z, instead of the OUTPUT value. */
#define FXL6408_REG_OUTPUT_HIGH_Z 0x07
/* Returns the current status (1 = HIGH) of the input pins. */
#define FXL6408_REG_INPUT_STATUS 0x0f
/*
* Return the current interrupt status
* This bit is HIGH if input GPIO != default state (register 09h).
* The flag is cleared after being read (bit returns to 0).
* The input must go back to default state and change again before this flag is raised again.
*/
#define FXL6408_REG_INT_STS 0x13
#define FXL6408_NGPIO 8
static const struct regmap_range rd_range[] = {
{ FXL6408_REG_DEVICE_ID, FXL6408_REG_DEVICE_ID },
{ FXL6408_REG_IO_DIR, FXL6408_REG_OUTPUT },
{ FXL6408_REG_INPUT_STATUS, FXL6408_REG_INPUT_STATUS },
};
static const struct regmap_range wr_range[] = {
{ FXL6408_REG_DEVICE_ID, FXL6408_REG_DEVICE_ID },
{ FXL6408_REG_IO_DIR, FXL6408_REG_OUTPUT },
{ FXL6408_REG_OUTPUT_HIGH_Z, FXL6408_REG_OUTPUT_HIGH_Z },
};
static const struct regmap_range volatile_range[] = {
{ FXL6408_REG_DEVICE_ID, FXL6408_REG_DEVICE_ID },
{ FXL6408_REG_INPUT_STATUS, FXL6408_REG_INPUT_STATUS },
};
static const struct regmap_access_table rd_table = {
.yes_ranges = rd_range,
.n_yes_ranges = ARRAY_SIZE(rd_range),
};
static const struct regmap_access_table wr_table = {
.yes_ranges = wr_range,
.n_yes_ranges = ARRAY_SIZE(wr_range),
};
static const struct regmap_access_table volatile_table = {
.yes_ranges = volatile_range,
.n_yes_ranges = ARRAY_SIZE(volatile_range),
};
static const struct regmap_config regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = FXL6408_REG_INT_STS,
.wr_table = &wr_table,
.rd_table = &rd_table,
.volatile_table = &volatile_table,
.cache_type = REGCACHE_RBTREE,
.num_reg_defaults_raw = FXL6408_REG_INT_STS + 1,
};
static int fxl6408_identify(struct device *dev, struct regmap *regmap)
{
int val, ret;
ret = regmap_read(regmap, FXL6408_REG_DEVICE_ID, &val);
if (ret)
return dev_err_probe(dev, ret, "error reading DEVICE_ID\n");
if (val >> FXL6408_MF_SHIFT != FXL6408_MF_FAIRCHILD)
return dev_err_probe(dev, -ENODEV, "invalid device id 0x%02x\n", val);
return 0;
}
static int fxl6408_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
int ret;
struct gpio_regmap_config gpio_config = {
.parent = dev,
.ngpio = FXL6408_NGPIO,
.reg_dat_base = GPIO_REGMAP_ADDR(FXL6408_REG_INPUT_STATUS),
.reg_set_base = GPIO_REGMAP_ADDR(FXL6408_REG_OUTPUT),
.reg_dir_out_base = GPIO_REGMAP_ADDR(FXL6408_REG_IO_DIR),
.ngpio_per_reg = FXL6408_NGPIO,
};
gpio_config.regmap = devm_regmap_init_i2c(client, ®map);
if (IS_ERR(gpio_config.regmap))
return dev_err_probe(dev, PTR_ERR(gpio_config.regmap),
"failed to allocate register map\n");
ret = fxl6408_identify(dev, gpio_config.regmap);
if (ret)
return ret;
/* Disable High-Z of outputs, so that our OUTPUT updates actually take effect. */
ret = regmap_write(gpio_config.regmap, FXL6408_REG_OUTPUT_HIGH_Z, 0);
if (ret)
return dev_err_probe(dev, ret, "failed to write 'output high Z' register\n");
return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config));
}
static const __maybe_unused struct of_device_id fxl6408_dt_ids[] = {
{ .compatible = "fcs,fxl6408" },
{ }
};
MODULE_DEVICE_TABLE(of, fxl6408_dt_ids);
static const struct i2c_device_id fxl6408_id[] = {
{ "fxl6408", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, fxl6408_id);
static struct i2c_driver fxl6408_driver = {
.driver = {
.name = "fxl6408",
.of_match_table = fxl6408_dt_ids,
},
.probe = fxl6408_probe,
.id_table = fxl6408_id,
};
module_i2c_driver(fxl6408_driver);
MODULE_AUTHOR("Emanuele Ghidoli <[email protected]>");
MODULE_DESCRIPTION("FXL6408 GPIO driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-fxl6408.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 MundoReader S.L.
* Author: Heiko Stuebner <[email protected]>
*
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl/core.h"
#include "../pinctrl/pinctrl-rockchip.h"
#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
#define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
static const struct rockchip_gpio_regs gpio_regs_v1 = {
.port_dr = 0x00,
.port_ddr = 0x04,
.int_en = 0x30,
.int_mask = 0x34,
.int_type = 0x38,
.int_polarity = 0x3c,
.int_status = 0x40,
.int_rawstatus = 0x44,
.debounce = 0x48,
.port_eoi = 0x4c,
.ext_port = 0x50,
};
static const struct rockchip_gpio_regs gpio_regs_v2 = {
.port_dr = 0x00,
.port_ddr = 0x08,
.int_en = 0x10,
.int_mask = 0x18,
.int_type = 0x20,
.int_polarity = 0x28,
.int_bothedge = 0x30,
.int_status = 0x50,
.int_rawstatus = 0x58,
.debounce = 0x38,
.dbclk_div_en = 0x40,
.dbclk_div_con = 0x48,
.port_eoi = 0x60,
.ext_port = 0x70,
.version_id = 0x78,
};
static inline void gpio_writel_v2(u32 val, void __iomem *reg)
{
writel((val & 0xffff) | 0xffff0000, reg);
writel((val >> 16) | 0xffff0000, reg + 0x4);
}
static inline u32 gpio_readl_v2(void __iomem *reg)
{
return readl(reg + 0x4) << 16 | readl(reg);
}
static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
u32 value, unsigned int offset)
{
void __iomem *reg = bank->reg_base + offset;
if (bank->gpio_type == GPIO_TYPE_V2)
gpio_writel_v2(value, reg);
else
writel(value, reg);
}
static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
unsigned int offset)
{
void __iomem *reg = bank->reg_base + offset;
u32 value;
if (bank->gpio_type == GPIO_TYPE_V2)
value = gpio_readl_v2(reg);
else
value = readl(reg);
return value;
}
static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
u32 bit, u32 value,
unsigned int offset)
{
void __iomem *reg = bank->reg_base + offset;
u32 data;
if (bank->gpio_type == GPIO_TYPE_V2) {
if (value)
data = BIT(bit % 16) | BIT(bit % 16 + 16);
else
data = BIT(bit % 16 + 16);
writel(data, bit >= 16 ? reg + 0x4 : reg);
} else {
data = readl(reg);
data &= ~BIT(bit);
if (value)
data |= BIT(bit);
writel(data, reg);
}
}
static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
u32 bit, unsigned int offset)
{
void __iomem *reg = bank->reg_base + offset;
u32 data;
if (bank->gpio_type == GPIO_TYPE_V2) {
data = readl(bit >= 16 ? reg + 0x4 : reg);
data >>= bit % 16;
} else {
data = readl(reg);
data >>= bit;
}
return data & (0x1);
}
static int rockchip_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
u32 data;
data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
if (data)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int rockchip_gpio_set_direction(struct gpio_chip *chip,
unsigned int offset, bool input)
{
struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
unsigned long flags;
u32 data = input ? 0 : 1;
if (input)
pinctrl_gpio_direction_input(bank->pin_base + offset);
else
pinctrl_gpio_direction_output(bank->pin_base + offset);
raw_spin_lock_irqsave(&bank->slock, flags);
rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
raw_spin_unlock_irqrestore(&bank->slock, flags);
return 0;
}
static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
int value)
{
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
unsigned long flags;
raw_spin_lock_irqsave(&bank->slock, flags);
rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
raw_spin_unlock_irqrestore(&bank->slock, flags);
}
static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
u32 data;
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
data >>= offset;
data &= 1;
return data;
}
static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
unsigned int offset,
unsigned int debounce)
{
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
const struct rockchip_gpio_regs *reg = bank->gpio_regs;
unsigned long flags, div_reg, freq, max_debounce;
bool div_debounce_support;
unsigned int cur_div_reg;
u64 div;
if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
div_debounce_support = true;
freq = clk_get_rate(bank->db_clk);
max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
if (debounce > max_debounce)
return -EINVAL;
div = debounce * freq;
div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
} else {
div_debounce_support = false;
}
raw_spin_lock_irqsave(&bank->slock, flags);
/* Only the v1 needs to configure div_en and div_con for dbclk */
if (debounce) {
if (div_debounce_support) {
/* Configure the max debounce from consumers */
cur_div_reg = readl(bank->reg_base +
reg->dbclk_div_con);
if (cur_div_reg < div_reg)
writel(div_reg, bank->reg_base +
reg->dbclk_div_con);
rockchip_gpio_writel_bit(bank, offset, 1,
reg->dbclk_div_en);
}
rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
} else {
if (div_debounce_support)
rockchip_gpio_writel_bit(bank, offset, 0,
reg->dbclk_div_en);
rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
}
raw_spin_unlock_irqrestore(&bank->slock, flags);
/* Enable or disable dbclk at last */
if (div_debounce_support) {
if (debounce)
clk_prepare_enable(bank->db_clk);
else
clk_disable_unprepare(bank->db_clk);
}
return 0;
}
static int rockchip_gpio_direction_input(struct gpio_chip *gc,
unsigned int offset)
{
return rockchip_gpio_set_direction(gc, offset, true);
}
static int rockchip_gpio_direction_output(struct gpio_chip *gc,
unsigned int offset, int value)
{
rockchip_gpio_set(gc, offset, value);
return rockchip_gpio_set_direction(gc, offset, false);
}
/*
* gpiolib set_config callback function. The setting of the pin
* mux function as 'gpio output' will be handled by the pinctrl subsystem
* interface.
*/
static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
unsigned long config)
{
enum pin_config_param param = pinconf_to_config_param(config);
switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
rockchip_gpio_set_debounce(gc, offset, true);
/*
* Rockchip's gpio could only support up to one period
* of the debounce clock(pclk), which is far away from
* satisftying the requirement, as pclk is usually near
* 100MHz shared by all peripherals. So the fact is it
* has crippled debounce capability could only be useful
* to prevent any spurious glitches from waking up the system
* if the gpio is conguired as wakeup interrupt source. Let's
* still return -ENOTSUPP as before, to make sure the caller
* of gpiod_set_debounce won't change its behaviour.
*/
return -ENOTSUPP;
default:
return -ENOTSUPP;
}
}
/*
* gpiod_to_irq() callback function. Creates a mapping between a GPIO pin
* and a virtual IRQ, if not already present.
*/
static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
{
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
unsigned int virq;
if (!bank->domain)
return -ENXIO;
virq = irq_create_mapping(bank->domain, offset);
return (virq) ? : -ENXIO;
}
static const struct gpio_chip rockchip_gpiolib_chip = {
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.set = rockchip_gpio_set,
.get = rockchip_gpio_get,
.get_direction = rockchip_gpio_get_direction,
.direction_input = rockchip_gpio_direction_input,
.direction_output = rockchip_gpio_direction_output,
.set_config = rockchip_gpio_set_config,
.to_irq = rockchip_gpio_to_irq,
.owner = THIS_MODULE,
};
static void rockchip_irq_demux(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
unsigned long pending;
unsigned int irq;
dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
chained_irq_enter(chip, desc);
pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
for_each_set_bit(irq, &pending, 32) {
dev_dbg(bank->dev, "handling irq %d\n", irq);
/*
* Triggering IRQ on both rising and falling edge
* needs manual intervention.
*/
if (bank->toggle_edge_mode & BIT(irq)) {
u32 data, data_old, polarity;
unsigned long flags;
data = readl_relaxed(bank->reg_base +
bank->gpio_regs->ext_port);
do {
raw_spin_lock_irqsave(&bank->slock, flags);
polarity = readl_relaxed(bank->reg_base +
bank->gpio_regs->int_polarity);
if (data & BIT(irq))
polarity &= ~BIT(irq);
else
polarity |= BIT(irq);
writel(polarity,
bank->reg_base +
bank->gpio_regs->int_polarity);
raw_spin_unlock_irqrestore(&bank->slock, flags);
data_old = data;
data = readl_relaxed(bank->reg_base +
bank->gpio_regs->ext_port);
} while ((data & BIT(irq)) != (data_old & BIT(irq)));
}
generic_handle_domain_irq(bank->domain, irq);
}
chained_irq_exit(chip, desc);
}
static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
u32 mask = BIT(d->hwirq);
u32 polarity;
u32 level;
u32 data;
unsigned long flags;
int ret = 0;
raw_spin_lock_irqsave(&bank->slock, flags);
rockchip_gpio_writel_bit(bank, d->hwirq, 0,
bank->gpio_regs->port_ddr);
raw_spin_unlock_irqrestore(&bank->slock, flags);
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(d, handle_edge_irq);
else
irq_set_handler_locked(d, handle_level_irq);
raw_spin_lock_irqsave(&bank->slock, flags);
level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
if (type == IRQ_TYPE_EDGE_BOTH) {
if (bank->gpio_type == GPIO_TYPE_V2) {
rockchip_gpio_writel_bit(bank, d->hwirq, 1,
bank->gpio_regs->int_bothedge);
goto out;
} else {
bank->toggle_edge_mode |= mask;
level &= ~mask;
/*
* Determine gpio state. If 1 next interrupt should be
* low otherwise high.
*/
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
if (data & mask)
polarity &= ~mask;
else
polarity |= mask;
}
} else {
if (bank->gpio_type == GPIO_TYPE_V2) {
rockchip_gpio_writel_bit(bank, d->hwirq, 0,
bank->gpio_regs->int_bothedge);
} else {
bank->toggle_edge_mode &= ~mask;
}
switch (type) {
case IRQ_TYPE_EDGE_RISING:
level |= mask;
polarity |= mask;
break;
case IRQ_TYPE_EDGE_FALLING:
level |= mask;
polarity &= ~mask;
break;
case IRQ_TYPE_LEVEL_HIGH:
level &= ~mask;
polarity |= mask;
break;
case IRQ_TYPE_LEVEL_LOW:
level &= ~mask;
polarity &= ~mask;
break;
default:
ret = -EINVAL;
goto out;
}
}
rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
out:
raw_spin_unlock_irqrestore(&bank->slock, flags);
return ret;
}
static int rockchip_irq_reqres(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq);
}
static void rockchip_irq_relres(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
gpiochip_relres_irq(&bank->gpio_chip, d->hwirq);
}
static void rockchip_irq_suspend(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
}
static void rockchip_irq_resume(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
}
static void rockchip_irq_enable(struct irq_data *d)
{
irq_gc_mask_clr_bit(d);
}
static void rockchip_irq_disable(struct irq_data *d)
{
irq_gc_mask_set_bit(d);
}
static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
{
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
bank->domain = irq_domain_add_linear(bank->of_node, 32,
&irq_generic_chip_ops, NULL);
if (!bank->domain) {
dev_warn(bank->dev, "could not init irq domain for bank %s\n",
bank->name);
return -EINVAL;
}
ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
"rockchip_gpio_irq",
handle_level_irq,
clr, 0, 0);
if (ret) {
dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
bank->name);
irq_domain_remove(bank->domain);
return -EINVAL;
}
gc = irq_get_domain_generic_chip(bank->domain, 0);
if (bank->gpio_type == GPIO_TYPE_V2) {
gc->reg_writel = gpio_writel_v2;
gc->reg_readl = gpio_readl_v2;
}
gc->reg_base = bank->reg_base;
gc->private = bank;
gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres;
gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres;
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
/*
* Linux assumes that all interrupts start out disabled/masked.
* Our driver only uses the concept of masked and always keeps
* things enabled, so for us that's all masked and all enabled.
*/
rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
gc->mask_cache = 0xffffffff;
irq_set_chained_handler_and_data(bank->irq,
rockchip_irq_demux, bank);
return 0;
}
static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
{
struct gpio_chip *gc;
int ret;
bank->gpio_chip = rockchip_gpiolib_chip;
gc = &bank->gpio_chip;
gc->base = bank->pin_base;
gc->ngpio = bank->nr_pins;
gc->label = bank->name;
gc->parent = bank->dev;
ret = gpiochip_add_data(gc, bank);
if (ret) {
dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
gc->label, ret);
return ret;
}
/*
* For DeviceTree-supported systems, the gpio core checks the
* pinctrl's device node for the "gpio-ranges" property.
* If it is present, it takes care of adding the pin ranges
* for the driver. In this case the driver can skip ahead.
*
* In order to remain compatible with older, existing DeviceTree
* files which don't set the "gpio-ranges" property or systems that
* utilize ACPI the driver has to call gpiochip_add_pin_range().
*/
if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
struct device_node *pctlnp = of_get_parent(bank->of_node);
struct pinctrl_dev *pctldev = NULL;
if (!pctlnp)
return -ENODATA;
pctldev = of_pinctrl_get(pctlnp);
of_node_put(pctlnp);
if (!pctldev)
return -ENODEV;
ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
gc->base, gc->ngpio);
if (ret) {
dev_err(bank->dev, "Failed to add pin range\n");
goto fail;
}
}
ret = rockchip_interrupts_register(bank);
if (ret) {
dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
goto fail;
}
return 0;
fail:
gpiochip_remove(&bank->gpio_chip);
return ret;
}
static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
{
struct resource res;
int id = 0;
if (of_address_to_resource(bank->of_node, 0, &res)) {
dev_err(bank->dev, "cannot find IO resource for bank\n");
return -ENOENT;
}
bank->reg_base = devm_ioremap_resource(bank->dev, &res);
if (IS_ERR(bank->reg_base))
return PTR_ERR(bank->reg_base);
bank->irq = irq_of_parse_and_map(bank->of_node, 0);
if (!bank->irq)
return -EINVAL;
bank->clk = of_clk_get(bank->of_node, 0);
if (IS_ERR(bank->clk))
return PTR_ERR(bank->clk);
clk_prepare_enable(bank->clk);
id = readl(bank->reg_base + gpio_regs_v2.version_id);
/* If not gpio v2, that is default to v1. */
if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) {
bank->gpio_regs = &gpio_regs_v2;
bank->gpio_type = GPIO_TYPE_V2;
bank->db_clk = of_clk_get(bank->of_node, 1);
if (IS_ERR(bank->db_clk)) {
dev_err(bank->dev, "cannot find debounce clk\n");
clk_disable_unprepare(bank->clk);
return -EINVAL;
}
} else {
bank->gpio_regs = &gpio_regs_v1;
bank->gpio_type = GPIO_TYPE_V1;
}
return 0;
}
static struct rockchip_pin_bank *
rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
{
struct rockchip_pinctrl *info;
struct rockchip_pin_bank *bank;
int i, found = 0;
info = pinctrl_dev_get_drvdata(pctldev);
bank = info->ctrl->pin_banks;
for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
if (bank->bank_num == id) {
found = 1;
break;
}
}
return found ? bank : NULL;
}
static int rockchip_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *pctlnp = of_get_parent(np);
struct pinctrl_dev *pctldev = NULL;
struct rockchip_pin_bank *bank = NULL;
struct rockchip_pin_deferred *cfg;
static int gpio;
int id, ret;
if (!np || !pctlnp)
return -ENODEV;
pctldev = of_pinctrl_get(pctlnp);
if (!pctldev)
return -EPROBE_DEFER;
id = of_alias_get_id(np, "gpio");
if (id < 0)
id = gpio++;
bank = rockchip_gpio_find_bank(pctldev, id);
if (!bank)
return -EINVAL;
bank->dev = dev;
bank->of_node = np;
raw_spin_lock_init(&bank->slock);
ret = rockchip_get_bank_data(bank);
if (ret)
return ret;
/*
* Prevent clashes with a deferred output setting
* being added right at this moment.
*/
mutex_lock(&bank->deferred_lock);
ret = rockchip_gpiolib_register(bank);
if (ret) {
clk_disable_unprepare(bank->clk);
mutex_unlock(&bank->deferred_lock);
return ret;
}
while (!list_empty(&bank->deferred_pins)) {
cfg = list_first_entry(&bank->deferred_pins,
struct rockchip_pin_deferred, head);
list_del(&cfg->head);
switch (cfg->param) {
case PIN_CONFIG_OUTPUT:
ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
if (ret)
dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin,
cfg->arg);
break;
case PIN_CONFIG_INPUT_ENABLE:
ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin);
if (ret)
dev_warn(dev, "setting input pin %u failed\n", cfg->pin);
break;
default:
dev_warn(dev, "unknown deferred config param %d\n", cfg->param);
break;
}
kfree(cfg);
}
mutex_unlock(&bank->deferred_lock);
platform_set_drvdata(pdev, bank);
dev_info(dev, "probed %pOF\n", np);
return 0;
}
static int rockchip_gpio_remove(struct platform_device *pdev)
{
struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
clk_disable_unprepare(bank->clk);
gpiochip_remove(&bank->gpio_chip);
return 0;
}
static const struct of_device_id rockchip_gpio_match[] = {
{ .compatible = "rockchip,gpio-bank", },
{ .compatible = "rockchip,rk3188-gpio-bank0" },
{ },
};
static struct platform_driver rockchip_gpio_driver = {
.probe = rockchip_gpio_probe,
.remove = rockchip_gpio_remove,
.driver = {
.name = "rockchip-gpio",
.of_match_table = rockchip_gpio_match,
},
};
static int __init rockchip_gpio_init(void)
{
return platform_driver_register(&rockchip_gpio_driver);
}
postcore_initcall(rockchip_gpio_init);
static void __exit rockchip_gpio_exit(void)
{
platform_driver_unregister(&rockchip_gpio_driver);
}
module_exit(rockchip_gpio_exit);
MODULE_DESCRIPTION("Rockchip gpio driver");
MODULE_ALIAS("platform:rockchip-gpio");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, rockchip_gpio_match);
| linux-master | drivers/gpio/gpio-rockchip.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#define IOH_EDGE_FALLING 0
#define IOH_EDGE_RISING BIT(0)
#define IOH_LEVEL_L BIT(1)
#define IOH_LEVEL_H (BIT(0) | BIT(1))
#define IOH_EDGE_BOTH BIT(2)
#define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
#define IOH_IRQ_BASE 0
struct ioh_reg_comn {
u32 ien;
u32 istatus;
u32 idisp;
u32 iclr;
u32 imask;
u32 imaskclr;
u32 po;
u32 pi;
u32 pm;
u32 im_0;
u32 im_1;
u32 reserved;
};
struct ioh_regs {
struct ioh_reg_comn regs[8];
u32 reserve1[16];
u32 ioh_sel_reg[4];
u32 reserve2[11];
u32 srst;
};
/**
* struct ioh_gpio_reg_data - The register store data.
* @ien_reg: To store contents of interrupt enable register.
* @imask_reg: To store contents of interrupt mask regist
* @po_reg: To store contents of PO register.
* @pm_reg: To store contents of PM register.
* @im0_reg: To store contents of interrupt mode regist0
* @im1_reg: To store contents of interrupt mode regist1
* @use_sel_reg: To store contents of GPIO_USE_SEL0~3
*/
struct ioh_gpio_reg_data {
u32 ien_reg;
u32 imask_reg;
u32 po_reg;
u32 pm_reg;
u32 im0_reg;
u32 im1_reg;
u32 use_sel_reg;
};
/**
* struct ioh_gpio - GPIO private data structure.
* @base: PCI base address of Memory mapped I/O register.
* @reg: Memory mapped IOH GPIO register list.
* @dev: Pointer to device structure.
* @gpio: Data for GPIO infrastructure.
* @ioh_gpio_reg: Memory mapped Register data is saved here
* when suspend.
* @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
* @ch: Indicate GPIO channel
* @irq_base: Save base of IRQ number for interrupt
* @spinlock: Used for register access protection
*/
struct ioh_gpio {
void __iomem *base;
struct ioh_regs __iomem *reg;
struct device *dev;
struct gpio_chip gpio;
struct ioh_gpio_reg_data ioh_gpio_reg;
u32 gpio_use_sel;
int ch;
int irq_base;
spinlock_t spinlock;
};
static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
{
u32 reg_val;
struct ioh_gpio *chip = gpiochip_get_data(gpio);
unsigned long flags;
spin_lock_irqsave(&chip->spinlock, flags);
reg_val = ioread32(&chip->reg->regs[chip->ch].po);
if (val)
reg_val |= BIT(nr);
else
reg_val &= ~BIT(nr);
iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
spin_unlock_irqrestore(&chip->spinlock, flags);
}
static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
struct ioh_gpio *chip = gpiochip_get_data(gpio);
return !!(ioread32(&chip->reg->regs[chip->ch].pi) & BIT(nr));
}
static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
int val)
{
struct ioh_gpio *chip = gpiochip_get_data(gpio);
u32 pm;
u32 reg_val;
unsigned long flags;
spin_lock_irqsave(&chip->spinlock, flags);
pm = ioread32(&chip->reg->regs[chip->ch].pm);
pm &= BIT(num_ports[chip->ch]) - 1;
pm |= BIT(nr);
iowrite32(pm, &chip->reg->regs[chip->ch].pm);
reg_val = ioread32(&chip->reg->regs[chip->ch].po);
if (val)
reg_val |= BIT(nr);
else
reg_val &= ~BIT(nr);
iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
spin_unlock_irqrestore(&chip->spinlock, flags);
return 0;
}
static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
struct ioh_gpio *chip = gpiochip_get_data(gpio);
u32 pm;
unsigned long flags;
spin_lock_irqsave(&chip->spinlock, flags);
pm = ioread32(&chip->reg->regs[chip->ch].pm);
pm &= BIT(num_ports[chip->ch]) - 1;
pm &= ~BIT(nr);
iowrite32(pm, &chip->reg->regs[chip->ch].pm);
spin_unlock_irqrestore(&chip->spinlock, flags);
return 0;
}
/*
* Save register configuration and disable interrupts.
*/
static void __maybe_unused ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
{
int i;
for (i = 0; i < 8; i ++, chip++) {
chip->ioh_gpio_reg.po_reg =
ioread32(&chip->reg->regs[chip->ch].po);
chip->ioh_gpio_reg.pm_reg =
ioread32(&chip->reg->regs[chip->ch].pm);
chip->ioh_gpio_reg.ien_reg =
ioread32(&chip->reg->regs[chip->ch].ien);
chip->ioh_gpio_reg.imask_reg =
ioread32(&chip->reg->regs[chip->ch].imask);
chip->ioh_gpio_reg.im0_reg =
ioread32(&chip->reg->regs[chip->ch].im_0);
chip->ioh_gpio_reg.im1_reg =
ioread32(&chip->reg->regs[chip->ch].im_1);
if (i < 4)
chip->ioh_gpio_reg.use_sel_reg =
ioread32(&chip->reg->ioh_sel_reg[i]);
}
}
/*
* This function restores the register configuration of the GPIO device.
*/
static void __maybe_unused ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
{
int i;
for (i = 0; i < 8; i ++, chip++) {
iowrite32(chip->ioh_gpio_reg.po_reg,
&chip->reg->regs[chip->ch].po);
iowrite32(chip->ioh_gpio_reg.pm_reg,
&chip->reg->regs[chip->ch].pm);
iowrite32(chip->ioh_gpio_reg.ien_reg,
&chip->reg->regs[chip->ch].ien);
iowrite32(chip->ioh_gpio_reg.imask_reg,
&chip->reg->regs[chip->ch].imask);
iowrite32(chip->ioh_gpio_reg.im0_reg,
&chip->reg->regs[chip->ch].im_0);
iowrite32(chip->ioh_gpio_reg.im1_reg,
&chip->reg->regs[chip->ch].im_1);
if (i < 4)
iowrite32(chip->ioh_gpio_reg.use_sel_reg,
&chip->reg->ioh_sel_reg[i]);
}
}
static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
struct ioh_gpio *chip = gpiochip_get_data(gpio);
return chip->irq_base + offset;
}
static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
{
struct gpio_chip *gpio = &chip->gpio;
gpio->label = dev_name(chip->dev);
gpio->owner = THIS_MODULE;
gpio->direction_input = ioh_gpio_direction_input;
gpio->get = ioh_gpio_get;
gpio->direction_output = ioh_gpio_direction_output;
gpio->set = ioh_gpio_set;
gpio->dbg_show = NULL;
gpio->base = -1;
gpio->ngpio = num_port;
gpio->can_sleep = false;
gpio->to_irq = ioh_gpio_to_irq;
}
static int ioh_irq_type(struct irq_data *d, unsigned int type)
{
u32 im;
void __iomem *im_reg;
u32 ien;
u32 im_pos;
int ch;
unsigned long flags;
u32 val;
int irq = d->irq;
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct ioh_gpio *chip = gc->private;
ch = irq - chip->irq_base;
if (irq <= chip->irq_base + 7) {
im_reg = &chip->reg->regs[chip->ch].im_0;
im_pos = ch;
} else {
im_reg = &chip->reg->regs[chip->ch].im_1;
im_pos = ch - 8;
}
dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
__func__, irq, type, ch, im_pos, type);
spin_lock_irqsave(&chip->spinlock, flags);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
val = IOH_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
val = IOH_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
val = IOH_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_HIGH:
val = IOH_LEVEL_H;
break;
case IRQ_TYPE_LEVEL_LOW:
val = IOH_LEVEL_L;
break;
case IRQ_TYPE_PROBE:
goto end;
default:
dev_warn(chip->dev, "%s: unknown type(%dd)",
__func__, type);
goto end;
}
/* Set interrupt mode */
im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
iowrite32(im | (val << (im_pos * 4)), im_reg);
/* iclr */
iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
/* IMASKCLR */
iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
/* Enable interrupt */
ien = ioread32(&chip->reg->regs[chip->ch].ien);
iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
end:
spin_unlock_irqrestore(&chip->spinlock, flags);
return 0;
}
static void ioh_irq_unmask(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct ioh_gpio *chip = gc->private;
iowrite32(BIT(d->irq - chip->irq_base),
&chip->reg->regs[chip->ch].imaskclr);
}
static void ioh_irq_mask(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct ioh_gpio *chip = gc->private;
iowrite32(BIT(d->irq - chip->irq_base),
&chip->reg->regs[chip->ch].imask);
}
static void ioh_irq_disable(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct ioh_gpio *chip = gc->private;
unsigned long flags;
u32 ien;
spin_lock_irqsave(&chip->spinlock, flags);
ien = ioread32(&chip->reg->regs[chip->ch].ien);
ien &= ~BIT(d->irq - chip->irq_base);
iowrite32(ien, &chip->reg->regs[chip->ch].ien);
spin_unlock_irqrestore(&chip->spinlock, flags);
}
static void ioh_irq_enable(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct ioh_gpio *chip = gc->private;
unsigned long flags;
u32 ien;
spin_lock_irqsave(&chip->spinlock, flags);
ien = ioread32(&chip->reg->regs[chip->ch].ien);
ien |= BIT(d->irq - chip->irq_base);
iowrite32(ien, &chip->reg->regs[chip->ch].ien);
spin_unlock_irqrestore(&chip->spinlock, flags);
}
static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
{
struct ioh_gpio *chip = dev_id;
u32 reg_val;
int i, j;
int ret = IRQ_NONE;
for (i = 0; i < 8; i++, chip++) {
reg_val = ioread32(&chip->reg->regs[i].istatus);
for (j = 0; j < num_ports[i]; j++) {
if (reg_val & BIT(j)) {
dev_dbg(chip->dev,
"%s:[%d]:irq=%d status=0x%x\n",
__func__, j, irq, reg_val);
iowrite32(BIT(j),
&chip->reg->regs[chip->ch].iclr);
generic_handle_irq(chip->irq_base + j);
ret = IRQ_HANDLED;
}
}
}
return ret;
}
static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
unsigned int irq_start,
unsigned int num)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
int rv;
gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
chip->base, handle_simple_irq);
if (!gc)
return -ENOMEM;
gc->private = chip;
ct = gc->chip_types;
ct->chip.irq_mask = ioh_irq_mask;
ct->chip.irq_unmask = ioh_irq_unmask;
ct->chip.irq_set_type = ioh_irq_type;
ct->chip.irq_disable = ioh_irq_disable;
ct->chip.irq_enable = ioh_irq_enable;
rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
return rv;
}
static int ioh_gpio_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct device *dev = &pdev->dev;
int ret;
int i, j;
struct ioh_gpio *chip;
void __iomem *base;
void *chip_save;
int irq_base;
ret = pcim_enable_device(pdev);
if (ret) {
dev_err(dev, "%s : pcim_enable_device failed", __func__);
return ret;
}
ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
if (ret) {
dev_err(dev, "pcim_iomap_regions failed-%d", ret);
return ret;
}
base = pcim_iomap_table(pdev)[1];
if (!base) {
dev_err(dev, "%s : pcim_iomap_table failed", __func__);
return -ENOMEM;
}
chip_save = devm_kcalloc(dev, 8, sizeof(*chip), GFP_KERNEL);
if (chip_save == NULL) {
return -ENOMEM;
}
chip = chip_save;
for (i = 0; i < 8; i++, chip++) {
chip->dev = dev;
chip->base = base;
chip->reg = chip->base;
chip->ch = i;
spin_lock_init(&chip->spinlock);
ioh_gpio_setup(chip, num_ports[i]);
ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
if (ret) {
dev_err(dev, "IOH gpio: Failed to register GPIO\n");
return ret;
}
}
chip = chip_save;
for (j = 0; j < 8; j++, chip++) {
irq_base = devm_irq_alloc_descs(dev, -1, IOH_IRQ_BASE,
num_ports[j], NUMA_NO_NODE);
if (irq_base < 0) {
dev_warn(dev,
"ml_ioh_gpio: Failed to get IRQ base num\n");
return irq_base;
}
chip->irq_base = irq_base;
ret = ioh_gpio_alloc_generic_chip(chip,
irq_base, num_ports[j]);
if (ret)
return ret;
}
chip = chip_save;
ret = devm_request_irq(dev, pdev->irq, ioh_gpio_handler,
IRQF_SHARED, KBUILD_MODNAME, chip);
if (ret != 0) {
dev_err(dev, "%s request_irq failed\n", __func__);
return ret;
}
pci_set_drvdata(pdev, chip);
return 0;
}
static int __maybe_unused ioh_gpio_suspend(struct device *dev)
{
struct ioh_gpio *chip = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&chip->spinlock, flags);
ioh_gpio_save_reg_conf(chip);
spin_unlock_irqrestore(&chip->spinlock, flags);
return 0;
}
static int __maybe_unused ioh_gpio_resume(struct device *dev)
{
struct ioh_gpio *chip = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&chip->spinlock, flags);
iowrite32(0x01, &chip->reg->srst);
iowrite32(0x00, &chip->reg->srst);
ioh_gpio_restore_reg_conf(chip);
spin_unlock_irqrestore(&chip->spinlock, flags);
return 0;
}
static SIMPLE_DEV_PM_OPS(ioh_gpio_pm_ops, ioh_gpio_suspend, ioh_gpio_resume);
static const struct pci_device_id ioh_gpio_pcidev_id[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
static struct pci_driver ioh_gpio_driver = {
.name = "ml_ioh_gpio",
.id_table = ioh_gpio_pcidev_id,
.probe = ioh_gpio_probe,
.driver = {
.pm = &ioh_gpio_pm_ops,
},
};
module_pci_driver(ioh_gpio_driver);
MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-ml-ioh.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* gpio-reg: single register individually fixed-direction GPIOs
*
* Copyright (C) 2016 Russell King
*/
#include <linux/bits.h>
#include <linux/container_of.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/gpio-reg.h>
struct gpio_reg {
struct gpio_chip gc;
spinlock_t lock;
u32 direction;
u32 out;
void __iomem *reg;
struct irq_domain *irqdomain;
const int *irqs;
};
#define to_gpio_reg(x) container_of(x, struct gpio_reg, gc)
static int gpio_reg_get_direction(struct gpio_chip *gc, unsigned offset)
{
struct gpio_reg *r = to_gpio_reg(gc);
return r->direction & BIT(offset) ? GPIO_LINE_DIRECTION_IN :
GPIO_LINE_DIRECTION_OUT;
}
static int gpio_reg_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
struct gpio_reg *r = to_gpio_reg(gc);
if (r->direction & BIT(offset))
return -ENOTSUPP;
gc->set(gc, offset, value);
return 0;
}
static int gpio_reg_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct gpio_reg *r = to_gpio_reg(gc);
return r->direction & BIT(offset) ? 0 : -ENOTSUPP;
}
static void gpio_reg_set(struct gpio_chip *gc, unsigned offset, int value)
{
struct gpio_reg *r = to_gpio_reg(gc);
unsigned long flags;
u32 val, mask = BIT(offset);
spin_lock_irqsave(&r->lock, flags);
val = r->out;
if (value)
val |= mask;
else
val &= ~mask;
r->out = val;
writel_relaxed(val, r->reg);
spin_unlock_irqrestore(&r->lock, flags);
}
static int gpio_reg_get(struct gpio_chip *gc, unsigned offset)
{
struct gpio_reg *r = to_gpio_reg(gc);
u32 val, mask = BIT(offset);
if (r->direction & mask) {
/*
* double-read the value, some registers latch after the
* first read.
*/
readl_relaxed(r->reg);
val = readl_relaxed(r->reg);
} else {
val = r->out;
}
return !!(val & mask);
}
static void gpio_reg_set_multiple(struct gpio_chip *gc, unsigned long *mask,
unsigned long *bits)
{
struct gpio_reg *r = to_gpio_reg(gc);
unsigned long flags;
spin_lock_irqsave(&r->lock, flags);
r->out = (r->out & ~*mask) | (*bits & *mask);
writel_relaxed(r->out, r->reg);
spin_unlock_irqrestore(&r->lock, flags);
}
static int gpio_reg_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct gpio_reg *r = to_gpio_reg(gc);
int irq = r->irqs[offset];
if (irq >= 0 && r->irqdomain)
irq = irq_find_mapping(r->irqdomain, irq);
return irq;
}
/**
* gpio_reg_init - add a fixed in/out register as gpio
* @dev: optional struct device associated with this register
* @base: start gpio number, or -1 to allocate
* @num: number of GPIOs, maximum 32
* @label: GPIO chip label
* @direction: bitmask of fixed direction, one per GPIO signal, 1 = in
* @def_out: initial GPIO output value
* @names: array of %num strings describing each GPIO signal or %NULL
* @irqdom: irq domain or %NULL
* @irqs: array of %num ints describing the interrupt mapping for each
* GPIO signal, or %NULL. If @irqdom is %NULL, then this
* describes the Linux interrupt number, otherwise it describes
* the hardware interrupt number in the specified irq domain.
*
* Add a single-register GPIO device containing up to 32 GPIO signals,
* where each GPIO has a fixed input or output configuration. Only
* input GPIOs are assumed to be readable from the register, and only
* then after a double-read. Output values are assumed not to be
* readable.
*/
struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg,
int base, int num, const char *label, u32 direction, u32 def_out,
const char *const *names, struct irq_domain *irqdom, const int *irqs)
{
struct gpio_reg *r;
int ret;
if (dev)
r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
else
r = kzalloc(sizeof(*r), GFP_KERNEL);
if (!r)
return ERR_PTR(-ENOMEM);
spin_lock_init(&r->lock);
r->gc.label = label;
r->gc.get_direction = gpio_reg_get_direction;
r->gc.direction_input = gpio_reg_direction_input;
r->gc.direction_output = gpio_reg_direction_output;
r->gc.set = gpio_reg_set;
r->gc.get = gpio_reg_get;
r->gc.set_multiple = gpio_reg_set_multiple;
if (irqs)
r->gc.to_irq = gpio_reg_to_irq;
r->gc.base = base;
r->gc.ngpio = num;
r->gc.names = names;
r->direction = direction;
r->out = def_out;
r->reg = reg;
r->irqs = irqs;
if (dev)
ret = devm_gpiochip_add_data(dev, &r->gc, r);
else
ret = gpiochip_add_data(&r->gc, r);
return ret ? ERR_PTR(ret) : &r->gc;
}
int gpio_reg_resume(struct gpio_chip *gc)
{
struct gpio_reg *r = to_gpio_reg(gc);
unsigned long flags;
spin_lock_irqsave(&r->lock, flags);
writel_relaxed(r->out, r->reg);
spin_unlock_irqrestore(&r->lock, flags);
return 0;
}
| linux-master | drivers/gpio/gpio-reg.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas R-Car GPIO Support
*
* Copyright (C) 2014 Renesas Electronics Corporation
* Copyright (C) 2013 Magnus Damm
*/
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
struct gpio_rcar_bank_info {
u32 iointsel;
u32 inoutsel;
u32 outdt;
u32 posneg;
u32 edglevel;
u32 bothedge;
u32 intmsk;
};
struct gpio_rcar_info {
bool has_outdtsel;
bool has_both_edge_trigger;
bool has_always_in;
bool has_inen;
};
struct gpio_rcar_priv {
void __iomem *base;
spinlock_t lock;
struct device *dev;
struct gpio_chip gpio_chip;
unsigned int irq_parent;
atomic_t wakeup_path;
struct gpio_rcar_info info;
struct gpio_rcar_bank_info bank_info;
};
#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
#define INOUTSEL 0x04 /* General Input/Output Switching Register */
#define OUTDT 0x08 /* General Output Register */
#define INDT 0x0c /* General Input Register */
#define INTDT 0x10 /* Interrupt Display Register */
#define INTCLR 0x14 /* Interrupt Clear Register */
#define INTMSK 0x18 /* Interrupt Mask Register */
#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
#define EDGLEVEL 0x24 /* Edge/level Select Register */
#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
#define OUTDTSEL 0x40 /* Output Data Select Register */
#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
#define INEN 0x50 /* General Input Enable Register */
#define RCAR_MAX_GPIO_PER_BANK 32
static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
{
return ioread32(p->base + offs);
}
static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
u32 value)
{
iowrite32(value, p->base + offs);
}
static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
int bit, bool value)
{
u32 tmp = gpio_rcar_read(p, offs);
if (value)
tmp |= BIT(bit);
else
tmp &= ~BIT(bit);
gpio_rcar_write(p, offs, tmp);
}
static void gpio_rcar_irq_disable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct gpio_rcar_priv *p = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
gpio_rcar_write(p, INTMSK, ~BIT(hwirq));
gpiochip_disable_irq(gc, hwirq);
}
static void gpio_rcar_irq_enable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct gpio_rcar_priv *p = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
gpiochip_enable_irq(gc, hwirq);
gpio_rcar_write(p, MSKCLR, BIT(hwirq));
}
static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
unsigned int hwirq,
bool active_high_rising_edge,
bool level_trigger,
bool both)
{
unsigned long flags;
/* follow steps in the GPIO documentation for
* "Setting Edge-Sensitive Interrupt Input Mode" and
* "Setting Level-Sensitive Interrupt Input Mode"
*/
spin_lock_irqsave(&p->lock, flags);
/* Configure positive or negative logic in POSNEG */
gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
/* Configure edge or level trigger in EDGLEVEL */
gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
/* Select one edge or both edges in BOTHEDGE */
if (p->info.has_both_edge_trigger)
gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
/* Select "Interrupt Input Mode" in IOINTSEL */
gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
/* Write INTCLR in case of edge trigger */
if (!level_trigger)
gpio_rcar_write(p, INTCLR, BIT(hwirq));
spin_unlock_irqrestore(&p->lock, flags);
}
static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct gpio_rcar_priv *p = gpiochip_get_data(gc);
unsigned int hwirq = irqd_to_hwirq(d);
dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_LEVEL_HIGH:
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
false);
break;
case IRQ_TYPE_LEVEL_LOW:
gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
false);
break;
case IRQ_TYPE_EDGE_RISING:
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
false);
break;
case IRQ_TYPE_EDGE_FALLING:
gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
false);
break;
case IRQ_TYPE_EDGE_BOTH:
if (!p->info.has_both_edge_trigger)
return -EINVAL;
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
true);
break;
default:
return -EINVAL;
}
return 0;
}
static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct gpio_rcar_priv *p = gpiochip_get_data(gc);
int error;
if (p->irq_parent) {
error = irq_set_irq_wake(p->irq_parent, on);
if (error) {
dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
p->irq_parent);
p->irq_parent = 0;
}
}
if (on)
atomic_inc(&p->wakeup_path);
else
atomic_dec(&p->wakeup_path);
return 0;
}
static const struct irq_chip gpio_rcar_irq_chip = {
.name = "gpio-rcar",
.irq_mask = gpio_rcar_irq_disable,
.irq_unmask = gpio_rcar_irq_enable,
.irq_set_type = gpio_rcar_irq_set_type,
.irq_set_wake = gpio_rcar_irq_set_wake,
.flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED |
IRQCHIP_MASK_ON_SUSPEND,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
{
struct gpio_rcar_priv *p = dev_id;
u32 pending;
unsigned int offset, irqs_handled = 0;
while ((pending = gpio_rcar_read(p, INTDT) &
gpio_rcar_read(p, INTMSK))) {
offset = __ffs(pending);
gpio_rcar_write(p, INTCLR, BIT(offset));
generic_handle_domain_irq(p->gpio_chip.irq.domain,
offset);
irqs_handled++;
}
return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}
static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
unsigned int gpio,
bool output)
{
struct gpio_rcar_priv *p = gpiochip_get_data(chip);
unsigned long flags;
/* follow steps in the GPIO documentation for
* "Setting General Output Mode" and
* "Setting General Input Mode"
*/
spin_lock_irqsave(&p->lock, flags);
/* Configure positive logic in POSNEG */
gpio_rcar_modify_bit(p, POSNEG, gpio, false);
/* Select "General Input/Output Mode" in IOINTSEL */
gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
/* Select Input Mode or Output Mode in INOUTSEL */
gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
/* Select General Output Register to output data in OUTDTSEL */
if (p->info.has_outdtsel && output)
gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
spin_unlock_irqrestore(&p->lock, flags);
}
static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
{
struct gpio_rcar_priv *p = gpiochip_get_data(chip);
int error;
error = pm_runtime_get_sync(p->dev);
if (error < 0) {
pm_runtime_put(p->dev);
return error;
}
error = pinctrl_gpio_request(chip->base + offset);
if (error)
pm_runtime_put(p->dev);
return error;
}
static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
{
struct gpio_rcar_priv *p = gpiochip_get_data(chip);
pinctrl_gpio_free(chip->base + offset);
/*
* Set the GPIO as an input to ensure that the next GPIO request won't
* drive the GPIO pin as an output.
*/
gpio_rcar_config_general_input_output_mode(chip, offset, false);
pm_runtime_put(p->dev);
}
static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct gpio_rcar_priv *p = gpiochip_get_data(chip);
if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
{
gpio_rcar_config_general_input_output_mode(chip, offset, false);
return 0;
}
static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
{
struct gpio_rcar_priv *p = gpiochip_get_data(chip);
u32 bit = BIT(offset);
/*
* Before R-Car Gen3, INDT does not show correct pin state when
* configured as output, so use OUTDT in case of output pins
*/
if (!p->info.has_always_in && (gpio_rcar_read(p, INOUTSEL) & bit))
return !!(gpio_rcar_read(p, OUTDT) & bit);
else
return !!(gpio_rcar_read(p, INDT) & bit);
}
static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask,
unsigned long *bits)
{
struct gpio_rcar_priv *p = gpiochip_get_data(chip);
u32 bankmask, outputs, m, val = 0;
unsigned long flags;
bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
if (chip->valid_mask)
bankmask &= chip->valid_mask[0];
if (!bankmask)
return 0;
if (p->info.has_always_in) {
bits[0] = gpio_rcar_read(p, INDT) & bankmask;
return 0;
}
spin_lock_irqsave(&p->lock, flags);
outputs = gpio_rcar_read(p, INOUTSEL);
m = outputs & bankmask;
if (m)
val |= gpio_rcar_read(p, OUTDT) & m;
m = ~outputs & bankmask;
if (m)
val |= gpio_rcar_read(p, INDT) & m;
spin_unlock_irqrestore(&p->lock, flags);
bits[0] = val;
return 0;
}
static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct gpio_rcar_priv *p = gpiochip_get_data(chip);
unsigned long flags;
spin_lock_irqsave(&p->lock, flags);
gpio_rcar_modify_bit(p, OUTDT, offset, value);
spin_unlock_irqrestore(&p->lock, flags);
}
static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
unsigned long *bits)
{
struct gpio_rcar_priv *p = gpiochip_get_data(chip);
unsigned long flags;
u32 val, bankmask;
bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
if (chip->valid_mask)
bankmask &= chip->valid_mask[0];
if (!bankmask)
return;
spin_lock_irqsave(&p->lock, flags);
val = gpio_rcar_read(p, OUTDT);
val &= ~bankmask;
val |= (bankmask & bits[0]);
gpio_rcar_write(p, OUTDT, val);
spin_unlock_irqrestore(&p->lock, flags);
}
static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
/* write GPIO value to output before selecting output mode of pin */
gpio_rcar_set(chip, offset, value);
gpio_rcar_config_general_input_output_mode(chip, offset, true);
return 0;
}
static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
.has_outdtsel = false,
.has_both_edge_trigger = false,
.has_always_in = false,
.has_inen = false,
};
static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
.has_outdtsel = true,
.has_both_edge_trigger = true,
.has_always_in = false,
.has_inen = false,
};
static const struct gpio_rcar_info gpio_rcar_info_gen3 = {
.has_outdtsel = true,
.has_both_edge_trigger = true,
.has_always_in = true,
.has_inen = false,
};
static const struct gpio_rcar_info gpio_rcar_info_gen4 = {
.has_outdtsel = true,
.has_both_edge_trigger = true,
.has_always_in = true,
.has_inen = true,
};
static const struct of_device_id gpio_rcar_of_table[] = {
{
.compatible = "renesas,gpio-r8a779a0",
.data = &gpio_rcar_info_gen4,
}, {
.compatible = "renesas,rcar-gen1-gpio",
.data = &gpio_rcar_info_gen1,
}, {
.compatible = "renesas,rcar-gen2-gpio",
.data = &gpio_rcar_info_gen2,
}, {
.compatible = "renesas,rcar-gen3-gpio",
.data = &gpio_rcar_info_gen3,
}, {
.compatible = "renesas,rcar-gen4-gpio",
.data = &gpio_rcar_info_gen4,
}, {
.compatible = "renesas,gpio-rcar",
.data = &gpio_rcar_info_gen1,
}, {
/* Terminator */
},
};
MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
{
struct device_node *np = p->dev->of_node;
const struct gpio_rcar_info *info;
struct of_phandle_args args;
int ret;
info = of_device_get_match_data(p->dev);
p->info = *info;
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
*npins, RCAR_MAX_GPIO_PER_BANK);
*npins = RCAR_MAX_GPIO_PER_BANK;
}
return 0;
}
static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p)
{
u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0);
/* Select "Input Enable" in INEN */
if (p->gpio_chip.valid_mask)
mask &= p->gpio_chip.valid_mask[0];
if (mask)
gpio_rcar_write(p, INEN, gpio_rcar_read(p, INEN) | mask);
}
static int gpio_rcar_probe(struct platform_device *pdev)
{
struct gpio_rcar_priv *p;
struct gpio_chip *gpio_chip;
struct gpio_irq_chip *girq;
struct device *dev = &pdev->dev;
const char *name = dev_name(dev);
unsigned int npins;
int ret;
p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
if (!p)
return -ENOMEM;
p->dev = dev;
spin_lock_init(&p->lock);
/* Get device configuration from DT node */
ret = gpio_rcar_parse_dt(p, &npins);
if (ret < 0)
return ret;
platform_set_drvdata(pdev, p);
pm_runtime_enable(dev);
ret = platform_get_irq(pdev, 0);
if (ret < 0)
goto err0;
p->irq_parent = ret;
p->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(p->base)) {
ret = PTR_ERR(p->base);
goto err0;
}
gpio_chip = &p->gpio_chip;
gpio_chip->request = gpio_rcar_request;
gpio_chip->free = gpio_rcar_free;
gpio_chip->get_direction = gpio_rcar_get_direction;
gpio_chip->direction_input = gpio_rcar_direction_input;
gpio_chip->get = gpio_rcar_get;
gpio_chip->get_multiple = gpio_rcar_get_multiple;
gpio_chip->direction_output = gpio_rcar_direction_output;
gpio_chip->set = gpio_rcar_set;
gpio_chip->set_multiple = gpio_rcar_set_multiple;
gpio_chip->label = name;
gpio_chip->parent = dev;
gpio_chip->owner = THIS_MODULE;
gpio_chip->base = -1;
gpio_chip->ngpio = npins;
girq = &gpio_chip->irq;
gpio_irq_chip_set_chip(girq, &gpio_rcar_irq_chip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
ret = gpiochip_add_data(gpio_chip, p);
if (ret) {
dev_err(dev, "failed to add GPIO controller\n");
goto err0;
}
irq_domain_set_pm_device(gpio_chip->irq.domain, dev);
ret = devm_request_irq(dev, p->irq_parent, gpio_rcar_irq_handler,
IRQF_SHARED, name, p);
if (ret) {
dev_err(dev, "failed to request IRQ\n");
goto err1;
}
if (p->info.has_inen) {
pm_runtime_get_sync(dev);
gpio_rcar_enable_inputs(p);
pm_runtime_put(dev);
}
dev_info(dev, "driving %d GPIOs\n", npins);
return 0;
err1:
gpiochip_remove(gpio_chip);
err0:
pm_runtime_disable(dev);
return ret;
}
static int gpio_rcar_remove(struct platform_device *pdev)
{
struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
gpiochip_remove(&p->gpio_chip);
pm_runtime_disable(&pdev->dev);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int gpio_rcar_suspend(struct device *dev)
{
struct gpio_rcar_priv *p = dev_get_drvdata(dev);
p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
if (p->info.has_both_edge_trigger)
p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
if (atomic_read(&p->wakeup_path))
device_set_wakeup_path(dev);
return 0;
}
static int gpio_rcar_resume(struct device *dev)
{
struct gpio_rcar_priv *p = dev_get_drvdata(dev);
unsigned int offset;
u32 mask;
for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
continue;
mask = BIT(offset);
/* I/O pin */
if (!(p->bank_info.iointsel & mask)) {
if (p->bank_info.inoutsel & mask)
gpio_rcar_direction_output(
&p->gpio_chip, offset,
!!(p->bank_info.outdt & mask));
else
gpio_rcar_direction_input(&p->gpio_chip,
offset);
} else {
/* Interrupt pin */
gpio_rcar_config_interrupt_input_mode(
p,
offset,
!(p->bank_info.posneg & mask),
!(p->bank_info.edglevel & mask),
!!(p->bank_info.bothedge & mask));
if (p->bank_info.intmsk & mask)
gpio_rcar_write(p, MSKCLR, mask);
}
}
if (p->info.has_inen)
gpio_rcar_enable_inputs(p);
return 0;
}
#endif /* CONFIG_PM_SLEEP*/
static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
static struct platform_driver gpio_rcar_device_driver = {
.probe = gpio_rcar_probe,
.remove = gpio_rcar_remove,
.driver = {
.name = "gpio_rcar",
.pm = &gpio_rcar_pm_ops,
.of_match_table = gpio_rcar_of_table,
}
};
module_platform_driver(gpio_rcar_device_driver);
MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-rcar.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* GPIO driver for the WinSystems WS16C48
* Copyright (C) 2016 William Breathitt Gray
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/regmap.h>
#include <linux/irq.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/spinlock.h>
#include <linux/regmap.h>
#include <linux/types.h>
#define WS16C48_EXTENT 11
#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
static unsigned int base[MAX_NUM_WS16C48];
static unsigned int num_ws16c48;
module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
static unsigned int irq[MAX_NUM_WS16C48];
static unsigned int num_irq;
module_param_hw_array(irq, uint, irq, &num_irq, 0);
MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
#define WS16C48_DAT_BASE 0x0
#define WS16C48_PAGE_LOCK 0x7
#define WS16C48_PAGE_BASE 0x8
#define WS16C48_POL WS16C48_PAGE_BASE
#define WS16C48_ENAB WS16C48_PAGE_BASE
#define WS16C48_INT_ID WS16C48_PAGE_BASE
#define PAGE_LOCK_PAGE_FIELD GENMASK(7, 6)
#define POL_PAGE u8_encode_bits(1, PAGE_LOCK_PAGE_FIELD)
#define ENAB_PAGE u8_encode_bits(2, PAGE_LOCK_PAGE_FIELD)
#define INT_ID_PAGE u8_encode_bits(3, PAGE_LOCK_PAGE_FIELD)
static const struct regmap_range ws16c48_wr_ranges[] = {
regmap_reg_range(0x0, 0x5), regmap_reg_range(0x7, 0xA),
};
static const struct regmap_range ws16c48_rd_ranges[] = {
regmap_reg_range(0x0, 0xA),
};
static const struct regmap_range ws16c48_volatile_ranges[] = {
regmap_reg_range(0x0, 0x6), regmap_reg_range(0x8, 0xA),
};
static const struct regmap_access_table ws16c48_wr_table = {
.yes_ranges = ws16c48_wr_ranges,
.n_yes_ranges = ARRAY_SIZE(ws16c48_wr_ranges),
};
static const struct regmap_access_table ws16c48_rd_table = {
.yes_ranges = ws16c48_rd_ranges,
.n_yes_ranges = ARRAY_SIZE(ws16c48_rd_ranges),
};
static const struct regmap_access_table ws16c48_volatile_table = {
.yes_ranges = ws16c48_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(ws16c48_volatile_ranges),
};
static const struct regmap_config ws16c48_regmap_config = {
.reg_bits = 8,
.reg_stride = 1,
.val_bits = 8,
.io_port = true,
.wr_table = &ws16c48_wr_table,
.rd_table = &ws16c48_rd_table,
.volatile_table = &ws16c48_volatile_table,
.cache_type = REGCACHE_FLAT,
.use_raw_spinlock = true,
};
#define WS16C48_NGPIO_PER_REG 8
#define WS16C48_REGMAP_IRQ(_id) \
[_id] = { \
.reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
.mask = BIT((_id) % WS16C48_NGPIO_PER_REG), \
.type = { \
.type_reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
.types_supported = IRQ_TYPE_EDGE_BOTH, \
}, \
}
/* Only the first 24 lines (Port 0-2) support interrupts */
#define WS16C48_NUM_IRQS 24
static const struct regmap_irq ws16c48_regmap_irqs[WS16C48_NUM_IRQS] = {
WS16C48_REGMAP_IRQ(0), WS16C48_REGMAP_IRQ(1), WS16C48_REGMAP_IRQ(2), /* 0-2 */
WS16C48_REGMAP_IRQ(3), WS16C48_REGMAP_IRQ(4), WS16C48_REGMAP_IRQ(5), /* 3-5 */
WS16C48_REGMAP_IRQ(6), WS16C48_REGMAP_IRQ(7), WS16C48_REGMAP_IRQ(8), /* 6-8 */
WS16C48_REGMAP_IRQ(9), WS16C48_REGMAP_IRQ(10), WS16C48_REGMAP_IRQ(11), /* 9-11 */
WS16C48_REGMAP_IRQ(12), WS16C48_REGMAP_IRQ(13), WS16C48_REGMAP_IRQ(14), /* 12-14 */
WS16C48_REGMAP_IRQ(15), WS16C48_REGMAP_IRQ(16), WS16C48_REGMAP_IRQ(17), /* 15-17 */
WS16C48_REGMAP_IRQ(18), WS16C48_REGMAP_IRQ(19), WS16C48_REGMAP_IRQ(20), /* 18-20 */
WS16C48_REGMAP_IRQ(21), WS16C48_REGMAP_IRQ(22), WS16C48_REGMAP_IRQ(23), /* 21-23 */
};
/**
* struct ws16c48_gpio - GPIO device private data structure
* @map: regmap for the device
* @lock: synchronization lock to prevent I/O race conditions
* @irq_mask: I/O bits affected by interrupts
*/
struct ws16c48_gpio {
struct regmap *map;
raw_spinlock_t lock;
u8 irq_mask[WS16C48_NUM_IRQS / WS16C48_NGPIO_PER_REG];
};
static int ws16c48_handle_pre_irq(void *const irq_drv_data) __acquires(&ws16c48gpio->lock)
{
struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
/* Lock to prevent Page/Lock register change while we handle IRQ */
raw_spin_lock(&ws16c48gpio->lock);
return 0;
}
static int ws16c48_handle_post_irq(void *const irq_drv_data) __releases(&ws16c48gpio->lock)
{
struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
raw_spin_unlock(&ws16c48gpio->lock);
return 0;
}
static int ws16c48_handle_mask_sync(const int index, const unsigned int mask_buf_def,
const unsigned int mask_buf, void *const irq_drv_data)
{
struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
unsigned long flags;
int ret = 0;
raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
/* exit early if no change since the last mask sync */
if (mask_buf == ws16c48gpio->irq_mask[index])
goto exit_unlock;
ws16c48gpio->irq_mask[index] = mask_buf;
ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, ENAB_PAGE);
if (ret)
goto exit_unlock;
/* Update ENAB register (inverted mask) */
ret = regmap_write(ws16c48gpio->map, WS16C48_ENAB + index, ~mask_buf);
if (ret)
goto exit_unlock;
ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
if (ret)
goto exit_unlock;
exit_unlock:
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
return ret;
}
static int ws16c48_set_type_config(unsigned int **const buf, const unsigned int type,
const struct regmap_irq *const irq_data, const int idx,
void *const irq_drv_data)
{
struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
unsigned int polarity;
unsigned long flags;
int ret;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
polarity = irq_data->mask;
break;
case IRQ_TYPE_EDGE_FALLING:
polarity = 0;
break;
default:
return -EINVAL;
}
raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, POL_PAGE);
if (ret)
goto exit_unlock;
/* Set interrupt polarity */
ret = regmap_update_bits(ws16c48gpio->map, WS16C48_POL + idx, irq_data->mask, polarity);
if (ret)
goto exit_unlock;
ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
if (ret)
goto exit_unlock;
exit_unlock:
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
return ret;
}
#define WS16C48_NGPIO 48
static const char *ws16c48_names[WS16C48_NGPIO] = {
"Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
"Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
"Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
"Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
"Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
"Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
"Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
"Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
"Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
"Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
"Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
};
static int ws16c48_irq_init_hw(struct regmap *const map)
{
int err;
err = regmap_write(map, WS16C48_PAGE_LOCK, ENAB_PAGE);
if (err)
return err;
/* Disable interrupts for all lines */
err = regmap_write(map, WS16C48_ENAB + 0, 0x00);
if (err)
return err;
err = regmap_write(map, WS16C48_ENAB + 1, 0x00);
if (err)
return err;
err = regmap_write(map, WS16C48_ENAB + 2, 0x00);
if (err)
return err;
return regmap_write(map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
}
static int ws16c48_probe(struct device *dev, unsigned int id)
{
struct ws16c48_gpio *ws16c48gpio;
const char *const name = dev_name(dev);
int err;
struct gpio_regmap_config gpio_config = {};
void __iomem *regs;
struct regmap_irq_chip *chip;
struct regmap_irq_chip_data *chip_data;
ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
if (!ws16c48gpio)
return -ENOMEM;
if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
base[id], base[id] + WS16C48_EXTENT);
return -EBUSY;
}
regs = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
if (!regs)
return -ENOMEM;
ws16c48gpio->map = devm_regmap_init_mmio(dev, regs, &ws16c48_regmap_config);
if (IS_ERR(ws16c48gpio->map))
return dev_err_probe(dev, PTR_ERR(ws16c48gpio->map),
"Unable to initialize register map\n");
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->name = name;
chip->status_base = WS16C48_INT_ID;
chip->mask_base = WS16C48_ENAB;
chip->ack_base = WS16C48_INT_ID;
chip->num_regs = 3;
chip->irqs = ws16c48_regmap_irqs;
chip->num_irqs = ARRAY_SIZE(ws16c48_regmap_irqs);
chip->handle_pre_irq = ws16c48_handle_pre_irq;
chip->handle_post_irq = ws16c48_handle_post_irq;
chip->handle_mask_sync = ws16c48_handle_mask_sync;
chip->set_type_config = ws16c48_set_type_config;
chip->irq_drv_data = ws16c48gpio;
raw_spin_lock_init(&ws16c48gpio->lock);
/* Initialize to prevent spurious interrupts before we're ready */
err = ws16c48_irq_init_hw(ws16c48gpio->map);
if (err)
return err;
err = devm_regmap_add_irq_chip(dev, ws16c48gpio->map, irq[id], 0, 0, chip, &chip_data);
if (err)
return dev_err_probe(dev, err, "IRQ registration failed\n");
gpio_config.parent = dev;
gpio_config.regmap = ws16c48gpio->map;
gpio_config.ngpio = WS16C48_NGPIO;
gpio_config.names = ws16c48_names;
gpio_config.reg_dat_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
gpio_config.reg_set_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
/* Setting a GPIO to 0 allows it to be used as an input */
gpio_config.reg_dir_out_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
gpio_config.ngpio_per_reg = WS16C48_NGPIO_PER_REG;
gpio_config.irq_domain = regmap_irq_get_domain(chip_data);
return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config));
}
static struct isa_driver ws16c48_driver = {
.probe = ws16c48_probe,
.driver = {
.name = "ws16c48"
},
};
module_isa_driver_with_irq(ws16c48_driver, num_ws16c48, num_irq);
MODULE_AUTHOR("William Breathitt Gray <[email protected]>");
MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-ws16c48.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2006 Juergen Beisert, Pengutronix
* Copyright (C) 2008 Guennadi Liakhovetski, Pengutronix
* Copyright (C) 2009 Wolfram Sang, Pengutronix
*
* Check max730x.c for further details.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/spi/max7301.h>
/* A write to the MAX7301 means one message with one transfer */
static int max7301_spi_write(struct device *dev, unsigned int reg,
unsigned int val)
{
struct spi_device *spi = to_spi_device(dev);
u16 word = ((reg & 0x7F) << 8) | (val & 0xFF);
return spi_write_then_read(spi, &word, sizeof(word), NULL, 0);
}
/* A read from the MAX7301 means two transfers; here, one message each */
static int max7301_spi_read(struct device *dev, unsigned int reg)
{
int ret;
u16 word;
struct spi_device *spi = to_spi_device(dev);
word = 0x8000 | (reg << 8);
ret = spi_write_then_read(spi, &word, sizeof(word), &word,
sizeof(word));
if (ret)
return ret;
return word & 0xff;
}
static int max7301_probe(struct spi_device *spi)
{
struct max7301 *ts;
int ret;
/* bits_per_word cannot be configured in platform data */
spi->bits_per_word = 16;
ret = spi_setup(spi);
if (ret < 0)
return ret;
ts = devm_kzalloc(&spi->dev, sizeof(struct max7301), GFP_KERNEL);
if (!ts)
return -ENOMEM;
ts->read = max7301_spi_read;
ts->write = max7301_spi_write;
ts->dev = &spi->dev;
ret = __max730x_probe(ts);
return ret;
}
static void max7301_remove(struct spi_device *spi)
{
__max730x_remove(&spi->dev);
}
static const struct spi_device_id max7301_id[] = {
{ "max7301", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, max7301_id);
static struct spi_driver max7301_driver = {
.driver = {
.name = "max7301",
},
.probe = max7301_probe,
.remove = max7301_remove,
.id_table = max7301_id,
};
static int __init max7301_init(void)
{
return spi_register_driver(&max7301_driver);
}
/* register after spi postcore initcall and before
* subsys initcalls that may rely on these GPIOs
*/
subsys_initcall(max7301_init);
static void __exit max7301_exit(void)
{
spi_unregister_driver(&max7301_driver);
}
module_exit(max7301_exit);
MODULE_AUTHOR("Juergen Beisert, Wolfram Sang");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MAX7301 GPIO-Expander");
| linux-master | drivers/gpio/gpio-max7301.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MAX732x I2C Port Expander with 8/16 I/O
*
* Copyright (C) 2007 Marvell International Ltd.
* Copyright (C) 2008 Jack Ren <[email protected]>
* Copyright (C) 2008 Eric Miao <[email protected]>
* Copyright (C) 2015 Linus Walleij <[email protected]>
*
* Derived from drivers/gpio/pca953x.c
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/platform_data/max732x.h>
/*
* Each port of MAX732x (including MAX7319) falls into one of the
* following three types:
*
* - Push Pull Output
* - Input
* - Open Drain I/O
*
* designated by 'O', 'I' and 'P' individually according to MAXIM's
* datasheets. 'I' and 'P' ports are interrupt capables, some with
* a dedicated interrupt mask.
*
* There are two groups of I/O ports, each group usually includes
* up to 8 I/O ports, and is accessed by a specific I2C address:
*
* - Group A : by I2C address 0b'110xxxx
* - Group B : by I2C address 0b'101xxxx
*
* where 'xxxx' is decided by the connections of pin AD2/AD0. The
* address used also affects the initial state of output signals.
*
* Within each group of ports, there are five known combinations of
* I/O ports: 4I4O, 4P4O, 8I, 8P, 8O, see the definitions below for
* the detailed organization of these ports. Only Goup A is interrupt
* capable.
*
* GPIO numbers start from 'gpio_base + 0' to 'gpio_base + 8/16',
* and GPIOs from GROUP_A are numbered before those from GROUP_B
* (if there are two groups).
*
* NOTE: MAX7328/MAX7329 are drop-in replacements for PCF8574/a, so
* they are not supported by this driver.
*/
#define PORT_NONE 0x0 /* '/' No Port */
#define PORT_OUTPUT 0x1 /* 'O' Push-Pull, Output Only */
#define PORT_INPUT 0x2 /* 'I' Input Only */
#define PORT_OPENDRAIN 0x3 /* 'P' Open-Drain, I/O */
#define IO_4I4O 0x5AA5 /* O7 O6 I5 I4 I3 I2 O1 O0 */
#define IO_4P4O 0x5FF5 /* O7 O6 P5 P4 P3 P2 O1 O0 */
#define IO_8I 0xAAAA /* I7 I6 I5 I4 I3 I2 I1 I0 */
#define IO_8P 0xFFFF /* P7 P6 P5 P4 P3 P2 P1 P0 */
#define IO_8O 0x5555 /* O7 O6 O5 O4 O3 O2 O1 O0 */
#define GROUP_A(x) ((x) & 0xffff) /* I2C Addr: 0b'110xxxx */
#define GROUP_B(x) ((x) << 16) /* I2C Addr: 0b'101xxxx */
#define INT_NONE 0x0 /* No interrupt capability */
#define INT_NO_MASK 0x1 /* Has interrupts, no mask */
#define INT_INDEP_MASK 0x2 /* Has interrupts, independent mask */
#define INT_MERGED_MASK 0x3 /* Has interrupts, merged mask */
#define INT_CAPS(x) (((uint64_t)(x)) << 32)
enum {
MAX7319,
MAX7320,
MAX7321,
MAX7322,
MAX7323,
MAX7324,
MAX7325,
MAX7326,
MAX7327,
};
static uint64_t max732x_features[] = {
[MAX7319] = GROUP_A(IO_8I) | INT_CAPS(INT_MERGED_MASK),
[MAX7320] = GROUP_B(IO_8O),
[MAX7321] = GROUP_A(IO_8P) | INT_CAPS(INT_NO_MASK),
[MAX7322] = GROUP_A(IO_4I4O) | INT_CAPS(INT_MERGED_MASK),
[MAX7323] = GROUP_A(IO_4P4O) | INT_CAPS(INT_INDEP_MASK),
[MAX7324] = GROUP_A(IO_8I) | GROUP_B(IO_8O) | INT_CAPS(INT_MERGED_MASK),
[MAX7325] = GROUP_A(IO_8P) | GROUP_B(IO_8O) | INT_CAPS(INT_NO_MASK),
[MAX7326] = GROUP_A(IO_4I4O) | GROUP_B(IO_8O) | INT_CAPS(INT_MERGED_MASK),
[MAX7327] = GROUP_A(IO_4P4O) | GROUP_B(IO_8O) | INT_CAPS(INT_NO_MASK),
};
static const struct i2c_device_id max732x_id[] = {
{ "max7319", MAX7319 },
{ "max7320", MAX7320 },
{ "max7321", MAX7321 },
{ "max7322", MAX7322 },
{ "max7323", MAX7323 },
{ "max7324", MAX7324 },
{ "max7325", MAX7325 },
{ "max7326", MAX7326 },
{ "max7327", MAX7327 },
{ },
};
MODULE_DEVICE_TABLE(i2c, max732x_id);
static const struct of_device_id max732x_of_table[] = {
{ .compatible = "maxim,max7319" },
{ .compatible = "maxim,max7320" },
{ .compatible = "maxim,max7321" },
{ .compatible = "maxim,max7322" },
{ .compatible = "maxim,max7323" },
{ .compatible = "maxim,max7324" },
{ .compatible = "maxim,max7325" },
{ .compatible = "maxim,max7326" },
{ .compatible = "maxim,max7327" },
{ }
};
MODULE_DEVICE_TABLE(of, max732x_of_table);
struct max732x_chip {
struct gpio_chip gpio_chip;
struct i2c_client *client; /* "main" client */
struct i2c_client *client_dummy;
struct i2c_client *client_group_a;
struct i2c_client *client_group_b;
unsigned int mask_group_a;
unsigned int dir_input;
unsigned int dir_output;
struct mutex lock;
uint8_t reg_out[2];
#ifdef CONFIG_GPIO_MAX732X_IRQ
struct mutex irq_lock;
uint8_t irq_mask;
uint8_t irq_mask_cur;
uint8_t irq_trig_raise;
uint8_t irq_trig_fall;
uint8_t irq_features;
#endif
};
static int max732x_writeb(struct max732x_chip *chip, int group_a, uint8_t val)
{
struct i2c_client *client;
int ret;
client = group_a ? chip->client_group_a : chip->client_group_b;
ret = i2c_smbus_write_byte(client, val);
if (ret < 0) {
dev_err(&client->dev, "failed writing\n");
return ret;
}
return 0;
}
static int max732x_readb(struct max732x_chip *chip, int group_a, uint8_t *val)
{
struct i2c_client *client;
int ret;
client = group_a ? chip->client_group_a : chip->client_group_b;
ret = i2c_smbus_read_byte(client);
if (ret < 0) {
dev_err(&client->dev, "failed reading\n");
return ret;
}
*val = (uint8_t)ret;
return 0;
}
static inline int is_group_a(struct max732x_chip *chip, unsigned off)
{
return (1u << off) & chip->mask_group_a;
}
static int max732x_gpio_get_value(struct gpio_chip *gc, unsigned off)
{
struct max732x_chip *chip = gpiochip_get_data(gc);
uint8_t reg_val;
int ret;
ret = max732x_readb(chip, is_group_a(chip, off), ®_val);
if (ret < 0)
return ret;
return !!(reg_val & (1u << (off & 0x7)));
}
static void max732x_gpio_set_mask(struct gpio_chip *gc, unsigned off, int mask,
int val)
{
struct max732x_chip *chip = gpiochip_get_data(gc);
uint8_t reg_out;
int ret;
mutex_lock(&chip->lock);
reg_out = (off > 7) ? chip->reg_out[1] : chip->reg_out[0];
reg_out = (reg_out & ~mask) | (val & mask);
ret = max732x_writeb(chip, is_group_a(chip, off), reg_out);
if (ret < 0)
goto out;
/* update the shadow register then */
if (off > 7)
chip->reg_out[1] = reg_out;
else
chip->reg_out[0] = reg_out;
out:
mutex_unlock(&chip->lock);
}
static void max732x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
{
unsigned base = off & ~0x7;
uint8_t mask = 1u << (off & 0x7);
max732x_gpio_set_mask(gc, base, mask, val << (off & 0x7));
}
static void max732x_gpio_set_multiple(struct gpio_chip *gc,
unsigned long *mask, unsigned long *bits)
{
unsigned mask_lo = mask[0] & 0xff;
unsigned mask_hi = (mask[0] >> 8) & 0xff;
if (mask_lo)
max732x_gpio_set_mask(gc, 0, mask_lo, bits[0] & 0xff);
if (mask_hi)
max732x_gpio_set_mask(gc, 8, mask_hi, (bits[0] >> 8) & 0xff);
}
static int max732x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
{
struct max732x_chip *chip = gpiochip_get_data(gc);
unsigned int mask = 1u << off;
if ((mask & chip->dir_input) == 0) {
dev_dbg(&chip->client->dev, "%s port %d is output only\n",
chip->client->name, off);
return -EACCES;
}
/*
* Open-drain pins must be set to high impedance (which is
* equivalent to output-high) to be turned into an input.
*/
if ((mask & chip->dir_output))
max732x_gpio_set_value(gc, off, 1);
return 0;
}
static int max732x_gpio_direction_output(struct gpio_chip *gc,
unsigned off, int val)
{
struct max732x_chip *chip = gpiochip_get_data(gc);
unsigned int mask = 1u << off;
if ((mask & chip->dir_output) == 0) {
dev_dbg(&chip->client->dev, "%s port %d is input only\n",
chip->client->name, off);
return -EACCES;
}
max732x_gpio_set_value(gc, off, val);
return 0;
}
#ifdef CONFIG_GPIO_MAX732X_IRQ
static int max732x_writew(struct max732x_chip *chip, uint16_t val)
{
int ret;
val = cpu_to_le16(val);
ret = i2c_master_send(chip->client_group_a, (char *)&val, 2);
if (ret < 0) {
dev_err(&chip->client_group_a->dev, "failed writing\n");
return ret;
}
return 0;
}
static int max732x_readw(struct max732x_chip *chip, uint16_t *val)
{
int ret;
ret = i2c_master_recv(chip->client_group_a, (char *)val, 2);
if (ret < 0) {
dev_err(&chip->client_group_a->dev, "failed reading\n");
return ret;
}
*val = le16_to_cpu(*val);
return 0;
}
static void max732x_irq_update_mask(struct max732x_chip *chip)
{
uint16_t msg;
if (chip->irq_mask == chip->irq_mask_cur)
return;
chip->irq_mask = chip->irq_mask_cur;
if (chip->irq_features == INT_NO_MASK)
return;
mutex_lock(&chip->lock);
switch (chip->irq_features) {
case INT_INDEP_MASK:
msg = (chip->irq_mask << 8) | chip->reg_out[0];
max732x_writew(chip, msg);
break;
case INT_MERGED_MASK:
msg = chip->irq_mask | chip->reg_out[0];
max732x_writeb(chip, 1, (uint8_t)msg);
break;
}
mutex_unlock(&chip->lock);
}
static void max732x_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct max732x_chip *chip = gpiochip_get_data(gc);
chip->irq_mask_cur &= ~(1 << d->hwirq);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
static void max732x_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct max732x_chip *chip = gpiochip_get_data(gc);
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
chip->irq_mask_cur |= 1 << d->hwirq;
}
static void max732x_irq_bus_lock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct max732x_chip *chip = gpiochip_get_data(gc);
mutex_lock(&chip->irq_lock);
chip->irq_mask_cur = chip->irq_mask;
}
static void max732x_irq_bus_sync_unlock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct max732x_chip *chip = gpiochip_get_data(gc);
uint16_t new_irqs;
uint16_t level;
max732x_irq_update_mask(chip);
new_irqs = chip->irq_trig_fall | chip->irq_trig_raise;
while (new_irqs) {
level = __ffs(new_irqs);
max732x_gpio_direction_input(&chip->gpio_chip, level);
new_irqs &= ~(1 << level);
}
mutex_unlock(&chip->irq_lock);
}
static int max732x_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct max732x_chip *chip = gpiochip_get_data(gc);
uint16_t off = d->hwirq;
uint16_t mask = 1 << off;
if (!(mask & chip->dir_input)) {
dev_dbg(&chip->client->dev, "%s port %d is output only\n",
chip->client->name, off);
return -EACCES;
}
if (!(type & IRQ_TYPE_EDGE_BOTH)) {
dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
d->irq, type);
return -EINVAL;
}
if (type & IRQ_TYPE_EDGE_FALLING)
chip->irq_trig_fall |= mask;
else
chip->irq_trig_fall &= ~mask;
if (type & IRQ_TYPE_EDGE_RISING)
chip->irq_trig_raise |= mask;
else
chip->irq_trig_raise &= ~mask;
return 0;
}
static int max732x_irq_set_wake(struct irq_data *data, unsigned int on)
{
struct max732x_chip *chip = irq_data_get_irq_chip_data(data);
irq_set_irq_wake(chip->client->irq, on);
return 0;
}
static const struct irq_chip max732x_irq_chip = {
.name = "max732x",
.irq_mask = max732x_irq_mask,
.irq_unmask = max732x_irq_unmask,
.irq_bus_lock = max732x_irq_bus_lock,
.irq_bus_sync_unlock = max732x_irq_bus_sync_unlock,
.irq_set_type = max732x_irq_set_type,
.irq_set_wake = max732x_irq_set_wake,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static uint8_t max732x_irq_pending(struct max732x_chip *chip)
{
uint8_t cur_stat;
uint8_t old_stat;
uint8_t trigger;
uint8_t pending;
uint16_t status;
int ret;
ret = max732x_readw(chip, &status);
if (ret)
return 0;
trigger = status >> 8;
trigger &= chip->irq_mask;
if (!trigger)
return 0;
cur_stat = status & 0xFF;
cur_stat &= chip->irq_mask;
old_stat = cur_stat ^ trigger;
pending = (old_stat & chip->irq_trig_fall) |
(cur_stat & chip->irq_trig_raise);
pending &= trigger;
return pending;
}
static irqreturn_t max732x_irq_handler(int irq, void *devid)
{
struct max732x_chip *chip = devid;
uint8_t pending;
uint8_t level;
pending = max732x_irq_pending(chip);
if (!pending)
return IRQ_HANDLED;
do {
level = __ffs(pending);
handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
level));
pending &= ~(1 << level);
} while (pending);
return IRQ_HANDLED;
}
static int max732x_irq_setup(struct max732x_chip *chip,
const struct i2c_device_id *id)
{
struct i2c_client *client = chip->client;
int has_irq = max732x_features[id->driver_data] >> 32;
int irq_base = 0;
int ret;
if (client->irq && has_irq != INT_NONE) {
struct gpio_irq_chip *girq;
chip->irq_features = has_irq;
mutex_init(&chip->irq_lock);
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, max732x_irq_handler, IRQF_ONESHOT |
IRQF_TRIGGER_FALLING | IRQF_SHARED,
dev_name(&client->dev), chip);
if (ret) {
dev_err(&client->dev, "failed to request irq %d\n",
client->irq);
return ret;
}
girq = &chip->gpio_chip.irq;
gpio_irq_chip_set_chip(girq, &max732x_irq_chip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
girq->threaded = true;
girq->first = irq_base; /* FIXME: get rid of this */
}
return 0;
}
#else /* CONFIG_GPIO_MAX732X_IRQ */
static int max732x_irq_setup(struct max732x_chip *chip,
const struct i2c_device_id *id)
{
struct i2c_client *client = chip->client;
int has_irq = max732x_features[id->driver_data] >> 32;
if (client->irq && has_irq != INT_NONE)
dev_warn(&client->dev, "interrupt support not compiled in\n");
return 0;
}
#endif
static int max732x_setup_gpio(struct max732x_chip *chip,
const struct i2c_device_id *id,
unsigned gpio_start)
{
struct gpio_chip *gc = &chip->gpio_chip;
uint32_t id_data = (uint32_t)max732x_features[id->driver_data];
int i, port = 0;
for (i = 0; i < 16; i++, id_data >>= 2) {
unsigned int mask = 1 << port;
switch (id_data & 0x3) {
case PORT_OUTPUT:
chip->dir_output |= mask;
break;
case PORT_INPUT:
chip->dir_input |= mask;
break;
case PORT_OPENDRAIN:
chip->dir_output |= mask;
chip->dir_input |= mask;
break;
default:
continue;
}
if (i < 8)
chip->mask_group_a |= mask;
port++;
}
if (chip->dir_input)
gc->direction_input = max732x_gpio_direction_input;
if (chip->dir_output) {
gc->direction_output = max732x_gpio_direction_output;
gc->set = max732x_gpio_set_value;
gc->set_multiple = max732x_gpio_set_multiple;
}
gc->get = max732x_gpio_get_value;
gc->can_sleep = true;
gc->base = gpio_start;
gc->ngpio = port;
gc->label = chip->client->name;
gc->parent = &chip->client->dev;
gc->owner = THIS_MODULE;
return port;
}
static struct max732x_platform_data *of_gpio_max732x(struct device *dev)
{
struct max732x_platform_data *pdata;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return NULL;
pdata->gpio_base = -1;
return pdata;
}
static int max732x_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct max732x_platform_data *pdata;
struct device_node *node;
struct max732x_chip *chip;
struct i2c_client *c;
uint16_t addr_a, addr_b;
int ret, nr_port;
pdata = dev_get_platdata(&client->dev);
node = client->dev.of_node;
if (!pdata && node)
pdata = of_gpio_max732x(&client->dev);
if (!pdata) {
dev_dbg(&client->dev, "no platform data\n");
return -EINVAL;
}
chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
if (chip == NULL)
return -ENOMEM;
chip->client = client;
nr_port = max732x_setup_gpio(chip, id, pdata->gpio_base);
chip->gpio_chip.parent = &client->dev;
addr_a = (client->addr & 0x0f) | 0x60;
addr_b = (client->addr & 0x0f) | 0x50;
switch (client->addr & 0x70) {
case 0x60:
chip->client_group_a = client;
if (nr_port > 8) {
c = devm_i2c_new_dummy_device(&client->dev,
client->adapter, addr_b);
if (IS_ERR(c)) {
dev_err(&client->dev,
"Failed to allocate I2C device\n");
return PTR_ERR(c);
}
chip->client_group_b = chip->client_dummy = c;
}
break;
case 0x50:
chip->client_group_b = client;
if (nr_port > 8) {
c = devm_i2c_new_dummy_device(&client->dev,
client->adapter, addr_a);
if (IS_ERR(c)) {
dev_err(&client->dev,
"Failed to allocate I2C device\n");
return PTR_ERR(c);
}
chip->client_group_a = chip->client_dummy = c;
}
break;
default:
dev_err(&client->dev, "invalid I2C address specified %02x\n",
client->addr);
return -EINVAL;
}
if (nr_port > 8 && !chip->client_dummy) {
dev_err(&client->dev,
"Failed to allocate second group I2C device\n");
return -ENODEV;
}
mutex_init(&chip->lock);
ret = max732x_readb(chip, is_group_a(chip, 0), &chip->reg_out[0]);
if (ret)
return ret;
if (nr_port > 8) {
ret = max732x_readb(chip, is_group_a(chip, 8), &chip->reg_out[1]);
if (ret)
return ret;
}
ret = max732x_irq_setup(chip, id);
if (ret)
return ret;
ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
if (ret)
return ret;
i2c_set_clientdata(client, chip);
return 0;
}
static struct i2c_driver max732x_driver = {
.driver = {
.name = "max732x",
.of_match_table = max732x_of_table,
},
.probe = max732x_probe,
.id_table = max732x_id,
};
static int __init max732x_init(void)
{
return i2c_add_driver(&max732x_driver);
}
/* register after i2c postcore initcall and before
* subsys initcalls that may rely on these GPIOs
*/
subsys_initcall(max732x_init);
static void __exit max732x_exit(void)
{
i2c_del_driver(&max732x_driver);
}
module_exit(max732x_exit);
MODULE_AUTHOR("Eric Miao <[email protected]>");
MODULE_DESCRIPTION("GPIO expander driver for MAX732X");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-max732x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* GPIO Driver for Dialog DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <[email protected]>
*/
#include <linux/fs.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/syscalls.h>
#include <linux/uaccess.h>
#include <linux/mfd/da9052/da9052.h>
#include <linux/mfd/da9052/pdata.h>
#include <linux/mfd/da9052/reg.h>
#define DA9052_INPUT 1
#define DA9052_OUTPUT_OPENDRAIN 2
#define DA9052_OUTPUT_PUSHPULL 3
#define DA9052_SUPPLY_VDD_IO1 0
#define DA9052_DEBOUNCING_OFF 0
#define DA9052_DEBOUNCING_ON 1
#define DA9052_OUTPUT_LOWLEVEL 0
#define DA9052_ACTIVE_LOW 0
#define DA9052_ACTIVE_HIGH 1
#define DA9052_GPIO_MAX_PORTS_PER_REGISTER 8
#define DA9052_GPIO_SHIFT_COUNT(no) (no%8)
#define DA9052_GPIO_MASK_UPPER_NIBBLE 0xF0
#define DA9052_GPIO_MASK_LOWER_NIBBLE 0x0F
#define DA9052_GPIO_NIBBLE_SHIFT 4
#define DA9052_IRQ_GPI0 16
#define DA9052_GPIO_ODD_SHIFT 7
#define DA9052_GPIO_EVEN_SHIFT 3
struct da9052_gpio {
struct da9052 *da9052;
struct gpio_chip gp;
};
static unsigned char da9052_gpio_port_odd(unsigned offset)
{
return offset % 2;
}
static int da9052_gpio_get(struct gpio_chip *gc, unsigned offset)
{
struct da9052_gpio *gpio = gpiochip_get_data(gc);
int da9052_port_direction = 0;
int ret;
ret = da9052_reg_read(gpio->da9052,
DA9052_GPIO_0_1_REG + (offset >> 1));
if (ret < 0)
return ret;
if (da9052_gpio_port_odd(offset)) {
da9052_port_direction = ret & DA9052_GPIO_ODD_PORT_PIN;
da9052_port_direction >>= 4;
} else {
da9052_port_direction = ret & DA9052_GPIO_EVEN_PORT_PIN;
}
switch (da9052_port_direction) {
case DA9052_INPUT:
if (offset < DA9052_GPIO_MAX_PORTS_PER_REGISTER)
ret = da9052_reg_read(gpio->da9052,
DA9052_STATUS_C_REG);
else
ret = da9052_reg_read(gpio->da9052,
DA9052_STATUS_D_REG);
if (ret < 0)
return ret;
return !!(ret & (1 << DA9052_GPIO_SHIFT_COUNT(offset)));
case DA9052_OUTPUT_PUSHPULL:
if (da9052_gpio_port_odd(offset))
return !!(ret & DA9052_GPIO_ODD_PORT_MODE);
else
return !!(ret & DA9052_GPIO_EVEN_PORT_MODE);
default:
return -EINVAL;
}
}
static void da9052_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
{
struct da9052_gpio *gpio = gpiochip_get_data(gc);
int ret;
if (da9052_gpio_port_odd(offset)) {
ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
DA9052_GPIO_0_1_REG,
DA9052_GPIO_ODD_PORT_MODE,
value << DA9052_GPIO_ODD_SHIFT);
if (ret != 0)
dev_err(gpio->da9052->dev,
"Failed to updated gpio odd reg,%d",
ret);
} else {
ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
DA9052_GPIO_0_1_REG,
DA9052_GPIO_EVEN_PORT_MODE,
value << DA9052_GPIO_EVEN_SHIFT);
if (ret != 0)
dev_err(gpio->da9052->dev,
"Failed to updated gpio even reg,%d",
ret);
}
}
static int da9052_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct da9052_gpio *gpio = gpiochip_get_data(gc);
unsigned char register_value;
int ret;
/* Format: function - 2 bits type - 1 bit mode - 1 bit */
register_value = DA9052_INPUT | DA9052_ACTIVE_LOW << 2 |
DA9052_DEBOUNCING_ON << 3;
if (da9052_gpio_port_odd(offset))
ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
DA9052_GPIO_0_1_REG,
DA9052_GPIO_MASK_UPPER_NIBBLE,
(register_value <<
DA9052_GPIO_NIBBLE_SHIFT));
else
ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
DA9052_GPIO_0_1_REG,
DA9052_GPIO_MASK_LOWER_NIBBLE,
register_value);
return ret;
}
static int da9052_gpio_direction_output(struct gpio_chip *gc,
unsigned offset, int value)
{
struct da9052_gpio *gpio = gpiochip_get_data(gc);
unsigned char register_value;
int ret;
/* Format: Function - 2 bits Type - 1 bit Mode - 1 bit */
register_value = DA9052_OUTPUT_PUSHPULL | DA9052_SUPPLY_VDD_IO1 << 2 |
value << 3;
if (da9052_gpio_port_odd(offset))
ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
DA9052_GPIO_0_1_REG,
DA9052_GPIO_MASK_UPPER_NIBBLE,
(register_value <<
DA9052_GPIO_NIBBLE_SHIFT));
else
ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
DA9052_GPIO_0_1_REG,
DA9052_GPIO_MASK_LOWER_NIBBLE,
register_value);
return ret;
}
static int da9052_gpio_to_irq(struct gpio_chip *gc, u32 offset)
{
struct da9052_gpio *gpio = gpiochip_get_data(gc);
struct da9052 *da9052 = gpio->da9052;
int irq;
irq = regmap_irq_get_virq(da9052->irq_data, DA9052_IRQ_GPI0 + offset);
return irq;
}
static const struct gpio_chip reference_gp = {
.label = "da9052-gpio",
.owner = THIS_MODULE,
.get = da9052_gpio_get,
.set = da9052_gpio_set,
.direction_input = da9052_gpio_direction_input,
.direction_output = da9052_gpio_direction_output,
.to_irq = da9052_gpio_to_irq,
.can_sleep = true,
.ngpio = 16,
.base = -1,
};
static int da9052_gpio_probe(struct platform_device *pdev)
{
struct da9052_gpio *gpio;
struct da9052_pdata *pdata;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
gpio->da9052 = dev_get_drvdata(pdev->dev.parent);
pdata = dev_get_platdata(gpio->da9052->dev);
gpio->gp = reference_gp;
if (pdata && pdata->gpio_base)
gpio->gp.base = pdata->gpio_base;
return devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio);
}
static struct platform_driver da9052_gpio_driver = {
.probe = da9052_gpio_probe,
.driver = {
.name = "da9052-gpio",
},
};
module_platform_driver(da9052_gpio_driver);
MODULE_AUTHOR("David Dajun Chen <[email protected]>");
MODULE_DESCRIPTION("DA9052 GPIO Device Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:da9052-gpio");
| linux-master | drivers/gpio/gpio-da9052.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Broadcom Kona GPIO Driver
*
* Author: Broadcom Corporation <[email protected]>
* Copyright (C) 2012-2014 Broadcom Corporation
*/
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#define BCM_GPIO_PASSWD 0x00a5a501
#define GPIO_PER_BANK 32
#define GPIO_MAX_BANK_NUM 8
#define GPIO_BANK(gpio) ((gpio) >> 5)
#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
/* There is a GPIO control register for each GPIO */
#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
/* The remaining registers are per GPIO bank */
#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
#define GPIO_GPPWR_OFFSET 0x00000520
#define GPIO_GPCTR0_DBR_SHIFT 5
#define GPIO_GPCTR0_DBR_MASK 0x000001e0
#define GPIO_GPCTR0_ITR_SHIFT 3
#define GPIO_GPCTR0_ITR_MASK 0x00000018
#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
#define GPIO_GPCTR0_IOTR_MASK 0x00000001
#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
#define LOCK_CODE 0xffffffff
#define UNLOCK_CODE 0x00000000
struct bcm_kona_gpio {
void __iomem *reg_base;
int num_bank;
raw_spinlock_t lock;
struct gpio_chip gpio_chip;
struct irq_domain *irq_domain;
struct bcm_kona_gpio_bank *banks;
};
struct bcm_kona_gpio_bank {
int id;
int irq;
/* Used in the interrupt handler */
struct bcm_kona_gpio *kona_gpio;
};
static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
int bank_id, u32 lockcode)
{
writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
}
static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
unsigned gpio)
{
u32 val;
unsigned long flags;
int bank_id = GPIO_BANK(gpio);
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
val |= BIT(gpio);
bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
}
static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
unsigned gpio)
{
u32 val;
unsigned long flags;
int bank_id = GPIO_BANK(gpio);
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
val &= ~BIT(gpio);
bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
}
static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
{
struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
void __iomem *reg_base = kona_gpio->reg_base;
u32 val;
val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
}
static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
{
struct bcm_kona_gpio *kona_gpio;
void __iomem *reg_base;
int bank_id = GPIO_BANK(gpio);
int bit = GPIO_BIT(gpio);
u32 val, reg_offset;
unsigned long flags;
kona_gpio = gpiochip_get_data(chip);
reg_base = kona_gpio->reg_base;
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
/* this function only applies to output pin */
if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
goto out;
reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
val = readl(reg_base + reg_offset);
val |= BIT(bit);
writel(val, reg_base + reg_offset);
out:
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
}
static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
struct bcm_kona_gpio *kona_gpio;
void __iomem *reg_base;
int bank_id = GPIO_BANK(gpio);
int bit = GPIO_BIT(gpio);
u32 val, reg_offset;
unsigned long flags;
kona_gpio = gpiochip_get_data(chip);
reg_base = kona_gpio->reg_base;
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
reg_offset = GPIO_IN_STATUS(bank_id);
else
reg_offset = GPIO_OUT_STATUS(bank_id);
/* read the GPIO bank status */
val = readl(reg_base + reg_offset);
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
/* return the specified bit status */
return !!(val & BIT(bit));
}
static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
{
struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
return 0;
}
static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
{
struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
}
static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
struct bcm_kona_gpio *kona_gpio;
void __iomem *reg_base;
u32 val;
unsigned long flags;
kona_gpio = gpiochip_get_data(chip);
reg_base = kona_gpio->reg_base;
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
val = readl(reg_base + GPIO_CONTROL(gpio));
val &= ~GPIO_GPCTR0_IOTR_MASK;
val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
writel(val, reg_base + GPIO_CONTROL(gpio));
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
return 0;
}
static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
struct bcm_kona_gpio *kona_gpio;
void __iomem *reg_base;
int bank_id = GPIO_BANK(gpio);
int bit = GPIO_BIT(gpio);
u32 val, reg_offset;
unsigned long flags;
kona_gpio = gpiochip_get_data(chip);
reg_base = kona_gpio->reg_base;
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
val = readl(reg_base + GPIO_CONTROL(gpio));
val &= ~GPIO_GPCTR0_IOTR_MASK;
val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
writel(val, reg_base + GPIO_CONTROL(gpio));
reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
val = readl(reg_base + reg_offset);
val |= BIT(bit);
writel(val, reg_base + reg_offset);
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
return 0;
}
static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
{
struct bcm_kona_gpio *kona_gpio;
kona_gpio = gpiochip_get_data(chip);
if (gpio >= kona_gpio->gpio_chip.ngpio)
return -ENXIO;
return irq_create_mapping(kona_gpio->irq_domain, gpio);
}
static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
unsigned debounce)
{
struct bcm_kona_gpio *kona_gpio;
void __iomem *reg_base;
u32 val, res;
unsigned long flags;
kona_gpio = gpiochip_get_data(chip);
reg_base = kona_gpio->reg_base;
/* debounce must be 1-128ms (or 0) */
if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
dev_err(chip->parent, "Debounce value %u not in range\n",
debounce);
return -EINVAL;
}
/* calculate debounce bit value */
if (debounce != 0) {
/* Convert to ms */
debounce /= 1000;
/* find the MSB */
res = fls(debounce) - 1;
/* Check if MSB-1 is set (round up or down) */
if (res > 0 && (debounce & BIT(res - 1)))
res++;
}
/* spin lock for read-modify-write of the GPIO register */
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
val = readl(reg_base + GPIO_CONTROL(gpio));
val &= ~GPIO_GPCTR0_DBR_MASK;
if (debounce == 0) {
/* disable debounce */
val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
} else {
val |= GPIO_GPCTR0_DB_ENABLE_MASK |
(res << GPIO_GPCTR0_DBR_SHIFT);
}
writel(val, reg_base + GPIO_CONTROL(gpio));
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
return 0;
}
static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
unsigned long config)
{
u32 debounce;
if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
return -ENOTSUPP;
debounce = pinconf_to_config_argument(config);
return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
}
static const struct gpio_chip template_chip = {
.label = "bcm-kona-gpio",
.owner = THIS_MODULE,
.request = bcm_kona_gpio_request,
.free = bcm_kona_gpio_free,
.get_direction = bcm_kona_gpio_get_dir,
.direction_input = bcm_kona_gpio_direction_input,
.get = bcm_kona_gpio_get,
.direction_output = bcm_kona_gpio_direction_output,
.set = bcm_kona_gpio_set,
.set_config = bcm_kona_gpio_set_config,
.to_irq = bcm_kona_gpio_to_irq,
.base = 0,
};
static void bcm_kona_gpio_irq_ack(struct irq_data *d)
{
struct bcm_kona_gpio *kona_gpio;
void __iomem *reg_base;
unsigned gpio = d->hwirq;
int bank_id = GPIO_BANK(gpio);
int bit = GPIO_BIT(gpio);
u32 val;
unsigned long flags;
kona_gpio = irq_data_get_irq_chip_data(d);
reg_base = kona_gpio->reg_base;
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
val = readl(reg_base + GPIO_INT_STATUS(bank_id));
val |= BIT(bit);
writel(val, reg_base + GPIO_INT_STATUS(bank_id));
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
}
static void bcm_kona_gpio_irq_mask(struct irq_data *d)
{
struct bcm_kona_gpio *kona_gpio;
void __iomem *reg_base;
unsigned gpio = d->hwirq;
int bank_id = GPIO_BANK(gpio);
int bit = GPIO_BIT(gpio);
u32 val;
unsigned long flags;
kona_gpio = irq_data_get_irq_chip_data(d);
reg_base = kona_gpio->reg_base;
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
val = readl(reg_base + GPIO_INT_MASK(bank_id));
val |= BIT(bit);
writel(val, reg_base + GPIO_INT_MASK(bank_id));
gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
}
static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
{
struct bcm_kona_gpio *kona_gpio;
void __iomem *reg_base;
unsigned gpio = d->hwirq;
int bank_id = GPIO_BANK(gpio);
int bit = GPIO_BIT(gpio);
u32 val;
unsigned long flags;
kona_gpio = irq_data_get_irq_chip_data(d);
reg_base = kona_gpio->reg_base;
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
val |= BIT(bit);
writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
}
static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct bcm_kona_gpio *kona_gpio;
void __iomem *reg_base;
unsigned gpio = d->hwirq;
u32 lvl_type;
u32 val;
unsigned long flags;
kona_gpio = irq_data_get_irq_chip_data(d);
reg_base = kona_gpio->reg_base;
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
break;
case IRQ_TYPE_LEVEL_HIGH:
case IRQ_TYPE_LEVEL_LOW:
/* BCM GPIO doesn't support level triggering */
default:
dev_err(kona_gpio->gpio_chip.parent,
"Invalid BCM GPIO irq type 0x%x\n", type);
return -EINVAL;
}
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
val = readl(reg_base + GPIO_CONTROL(gpio));
val &= ~GPIO_GPCTR0_ITR_MASK;
val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
writel(val, reg_base + GPIO_CONTROL(gpio));
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
return 0;
}
static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
{
void __iomem *reg_base;
int bit, bank_id;
unsigned long sta;
struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
chained_irq_enter(chip, desc);
/*
* For bank interrupts, we can't use chip_data to store the kona_gpio
* pointer, since GIC needs it for its own purposes. Therefore, we get
* our pointer from the bank structure.
*/
reg_base = bank->kona_gpio->reg_base;
bank_id = bank->id;
while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
(~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
for_each_set_bit(bit, &sta, 32) {
int hwirq = GPIO_PER_BANK * bank_id + bit;
/*
* Clear interrupt before handler is called so we don't
* miss any interrupt occurred during executing them.
*/
writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
/* Invoke interrupt handler */
generic_handle_domain_irq(bank->kona_gpio->irq_domain,
hwirq);
}
}
chained_irq_exit(chip, desc);
}
static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
{
struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
}
static void bcm_kona_gpio_irq_relres(struct irq_data *d)
{
struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
}
static struct irq_chip bcm_gpio_irq_chip = {
.name = "bcm-kona-gpio",
.irq_ack = bcm_kona_gpio_irq_ack,
.irq_mask = bcm_kona_gpio_irq_mask,
.irq_unmask = bcm_kona_gpio_irq_unmask,
.irq_set_type = bcm_kona_gpio_irq_set_type,
.irq_request_resources = bcm_kona_gpio_irq_reqres,
.irq_release_resources = bcm_kona_gpio_irq_relres,
};
static struct of_device_id const bcm_kona_gpio_of_match[] = {
{ .compatible = "brcm,kona-gpio" },
{}
};
/*
* This lock class tells lockdep that GPIO irqs are in a different
* category than their parents, so it won't report false recursion.
*/
static struct lock_class_key gpio_lock_class;
static struct lock_class_key gpio_request_class;
static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
int ret;
ret = irq_set_chip_data(irq, d->host_data);
if (ret < 0)
return ret;
irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
irq_set_noprobe(irq);
return 0;
}
static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
{
irq_set_chip_and_handler(irq, NULL, NULL);
irq_set_chip_data(irq, NULL);
}
static const struct irq_domain_ops bcm_kona_irq_ops = {
.map = bcm_kona_gpio_irq_map,
.unmap = bcm_kona_gpio_irq_unmap,
.xlate = irq_domain_xlate_twocell,
};
static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
{
void __iomem *reg_base;
int i;
reg_base = kona_gpio->reg_base;
/* disable interrupts and clear status */
for (i = 0; i < kona_gpio->num_bank; i++) {
/* Unlock the entire bank first */
bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
/* Now re-lock the bank */
bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
}
}
static int bcm_kona_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct bcm_kona_gpio_bank *bank;
struct bcm_kona_gpio *kona_gpio;
struct gpio_chip *chip;
int ret;
int i;
kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
if (!kona_gpio)
return -ENOMEM;
kona_gpio->gpio_chip = template_chip;
chip = &kona_gpio->gpio_chip;
ret = platform_irq_count(pdev);
if (!ret) {
dev_err(dev, "Couldn't determine # GPIO banks\n");
return -ENOENT;
} else if (ret < 0) {
return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n");
}
kona_gpio->num_bank = ret;
if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
GPIO_MAX_BANK_NUM);
return -ENXIO;
}
kona_gpio->banks = devm_kcalloc(dev,
kona_gpio->num_bank,
sizeof(*kona_gpio->banks),
GFP_KERNEL);
if (!kona_gpio->banks)
return -ENOMEM;
chip->parent = dev;
chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
kona_gpio->irq_domain = irq_domain_create_linear(dev_fwnode(dev),
chip->ngpio,
&bcm_kona_irq_ops,
kona_gpio);
if (!kona_gpio->irq_domain) {
dev_err(dev, "Couldn't allocate IRQ domain\n");
return -ENXIO;
}
kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(kona_gpio->reg_base)) {
ret = PTR_ERR(kona_gpio->reg_base);
goto err_irq_domain;
}
for (i = 0; i < kona_gpio->num_bank; i++) {
bank = &kona_gpio->banks[i];
bank->id = i;
bank->irq = platform_get_irq(pdev, i);
bank->kona_gpio = kona_gpio;
if (bank->irq < 0) {
dev_err(dev, "Couldn't get IRQ for bank %d", i);
ret = -ENOENT;
goto err_irq_domain;
}
}
dev_info(&pdev->dev, "Setting up Kona GPIO\n");
bcm_kona_gpio_reset(kona_gpio);
ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
if (ret < 0) {
dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
goto err_irq_domain;
}
for (i = 0; i < kona_gpio->num_bank; i++) {
bank = &kona_gpio->banks[i];
irq_set_chained_handler_and_data(bank->irq,
bcm_kona_gpio_irq_handler,
bank);
}
raw_spin_lock_init(&kona_gpio->lock);
return 0;
err_irq_domain:
irq_domain_remove(kona_gpio->irq_domain);
return ret;
}
static struct platform_driver bcm_kona_gpio_driver = {
.driver = {
.name = "bcm-kona-gpio",
.of_match_table = bcm_kona_gpio_of_match,
},
.probe = bcm_kona_gpio_probe,
};
builtin_platform_driver(bcm_kona_gpio_driver);
| linux-master | drivers/gpio/gpio-bcm-kona.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* GPIO driver for virtio-based virtual GPIO controllers
*
* Copyright (C) 2021 metux IT consult
* Enrico Weigelt, metux IT consult <[email protected]>
*
* Copyright (C) 2021 Linaro.
* Viresh Kumar <[email protected]>
*/
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>
#include <linux/virtio_config.h>
#include <uapi/linux/virtio_gpio.h>
#include <uapi/linux/virtio_ids.h>
struct virtio_gpio_line {
struct mutex lock; /* Protects line operation */
struct completion completion;
struct virtio_gpio_request req ____cacheline_aligned;
struct virtio_gpio_response res ____cacheline_aligned;
unsigned int rxlen;
};
struct vgpio_irq_line {
u8 type;
bool disabled;
bool masked;
bool queued;
bool update_pending;
bool queue_pending;
struct virtio_gpio_irq_request ireq ____cacheline_aligned;
struct virtio_gpio_irq_response ires ____cacheline_aligned;
};
struct virtio_gpio {
struct virtio_device *vdev;
struct mutex lock; /* Protects virtqueue operation */
struct gpio_chip gc;
struct virtio_gpio_line *lines;
struct virtqueue *request_vq;
/* irq support */
struct virtqueue *event_vq;
struct mutex irq_lock; /* Protects irq operation */
raw_spinlock_t eventq_lock; /* Protects queuing of the buffer */
struct vgpio_irq_line *irq_lines;
};
static int _virtio_gpio_req(struct virtio_gpio *vgpio, u16 type, u16 gpio,
u8 txvalue, u8 *rxvalue, void *response, u32 rxlen)
{
struct virtio_gpio_line *line = &vgpio->lines[gpio];
struct virtio_gpio_request *req = &line->req;
struct virtio_gpio_response *res = response;
struct scatterlist *sgs[2], req_sg, res_sg;
struct device *dev = &vgpio->vdev->dev;
int ret;
/*
* Prevent concurrent requests for the same line since we have
* pre-allocated request/response buffers for each GPIO line. Moreover
* Linux always accesses a GPIO line sequentially, so this locking shall
* always go through without any delays.
*/
mutex_lock(&line->lock);
req->type = cpu_to_le16(type);
req->gpio = cpu_to_le16(gpio);
req->value = cpu_to_le32(txvalue);
sg_init_one(&req_sg, req, sizeof(*req));
sg_init_one(&res_sg, res, rxlen);
sgs[0] = &req_sg;
sgs[1] = &res_sg;
line->rxlen = 0;
reinit_completion(&line->completion);
/*
* Virtqueue callers need to ensure they don't call its APIs with other
* virtqueue operations at the same time.
*/
mutex_lock(&vgpio->lock);
ret = virtqueue_add_sgs(vgpio->request_vq, sgs, 1, 1, line, GFP_KERNEL);
if (ret) {
dev_err(dev, "failed to add request to vq\n");
mutex_unlock(&vgpio->lock);
goto out;
}
virtqueue_kick(vgpio->request_vq);
mutex_unlock(&vgpio->lock);
wait_for_completion(&line->completion);
if (unlikely(res->status != VIRTIO_GPIO_STATUS_OK)) {
dev_err(dev, "GPIO request failed: %d\n", gpio);
ret = -EINVAL;
goto out;
}
if (unlikely(line->rxlen != rxlen)) {
dev_err(dev, "GPIO operation returned incorrect len (%u : %u)\n",
rxlen, line->rxlen);
ret = -EINVAL;
goto out;
}
if (rxvalue)
*rxvalue = res->value;
out:
mutex_unlock(&line->lock);
return ret;
}
static int virtio_gpio_req(struct virtio_gpio *vgpio, u16 type, u16 gpio,
u8 txvalue, u8 *rxvalue)
{
struct virtio_gpio_line *line = &vgpio->lines[gpio];
struct virtio_gpio_response *res = &line->res;
return _virtio_gpio_req(vgpio, type, gpio, txvalue, rxvalue, res,
sizeof(*res));
}
static void virtio_gpio_free(struct gpio_chip *gc, unsigned int gpio)
{
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_SET_DIRECTION, gpio,
VIRTIO_GPIO_DIRECTION_NONE, NULL);
}
static int virtio_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
{
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
u8 direction;
int ret;
ret = virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_GET_DIRECTION, gpio, 0,
&direction);
if (ret)
return ret;
switch (direction) {
case VIRTIO_GPIO_DIRECTION_IN:
return GPIO_LINE_DIRECTION_IN;
case VIRTIO_GPIO_DIRECTION_OUT:
return GPIO_LINE_DIRECTION_OUT;
default:
return -EINVAL;
}
}
static int virtio_gpio_direction_input(struct gpio_chip *gc, unsigned int gpio)
{
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
return virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_SET_DIRECTION, gpio,
VIRTIO_GPIO_DIRECTION_IN, NULL);
}
static int virtio_gpio_direction_output(struct gpio_chip *gc, unsigned int gpio,
int value)
{
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
int ret;
ret = virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_SET_VALUE, gpio, value, NULL);
if (ret)
return ret;
return virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_SET_DIRECTION, gpio,
VIRTIO_GPIO_DIRECTION_OUT, NULL);
}
static int virtio_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
u8 value;
int ret;
ret = virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_GET_VALUE, gpio, 0, &value);
return ret ? ret : value;
}
static void virtio_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value)
{
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_SET_VALUE, gpio, value, NULL);
}
/* Interrupt handling */
static void virtio_gpio_irq_prepare(struct virtio_gpio *vgpio, u16 gpio)
{
struct vgpio_irq_line *irq_line = &vgpio->irq_lines[gpio];
struct virtio_gpio_irq_request *ireq = &irq_line->ireq;
struct virtio_gpio_irq_response *ires = &irq_line->ires;
struct scatterlist *sgs[2], req_sg, res_sg;
int ret;
if (WARN_ON(irq_line->queued || irq_line->masked || irq_line->disabled))
return;
ireq->gpio = cpu_to_le16(gpio);
sg_init_one(&req_sg, ireq, sizeof(*ireq));
sg_init_one(&res_sg, ires, sizeof(*ires));
sgs[0] = &req_sg;
sgs[1] = &res_sg;
ret = virtqueue_add_sgs(vgpio->event_vq, sgs, 1, 1, irq_line, GFP_ATOMIC);
if (ret) {
dev_err(&vgpio->vdev->dev, "failed to add request to eventq\n");
return;
}
irq_line->queued = true;
virtqueue_kick(vgpio->event_vq);
}
static void virtio_gpio_irq_enable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
raw_spin_lock(&vgpio->eventq_lock);
irq_line->disabled = false;
irq_line->masked = false;
irq_line->queue_pending = true;
raw_spin_unlock(&vgpio->eventq_lock);
irq_line->update_pending = true;
}
static void virtio_gpio_irq_disable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
raw_spin_lock(&vgpio->eventq_lock);
irq_line->disabled = true;
irq_line->masked = true;
irq_line->queue_pending = false;
raw_spin_unlock(&vgpio->eventq_lock);
irq_line->update_pending = true;
}
static void virtio_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
raw_spin_lock(&vgpio->eventq_lock);
irq_line->masked = true;
raw_spin_unlock(&vgpio->eventq_lock);
}
static void virtio_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
raw_spin_lock(&vgpio->eventq_lock);
irq_line->masked = false;
/* Queue the buffer unconditionally on unmask */
virtio_gpio_irq_prepare(vgpio, d->hwirq);
raw_spin_unlock(&vgpio->eventq_lock);
}
static int virtio_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
switch (type) {
case IRQ_TYPE_EDGE_RISING:
type = VIRTIO_GPIO_IRQ_TYPE_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
type = VIRTIO_GPIO_IRQ_TYPE_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
type = VIRTIO_GPIO_IRQ_TYPE_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_LOW:
type = VIRTIO_GPIO_IRQ_TYPE_LEVEL_LOW;
break;
case IRQ_TYPE_LEVEL_HIGH:
type = VIRTIO_GPIO_IRQ_TYPE_LEVEL_HIGH;
break;
default:
dev_err(&vgpio->vdev->dev, "unsupported irq type: %u\n", type);
return -EINVAL;
}
irq_line->type = type;
irq_line->update_pending = true;
return 0;
}
static void virtio_gpio_irq_bus_lock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
mutex_lock(&vgpio->irq_lock);
}
static void virtio_gpio_irq_bus_sync_unlock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
struct vgpio_irq_line *irq_line = &vgpio->irq_lines[d->hwirq];
u8 type = irq_line->disabled ? VIRTIO_GPIO_IRQ_TYPE_NONE : irq_line->type;
unsigned long flags;
if (irq_line->update_pending) {
irq_line->update_pending = false;
virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_IRQ_TYPE, d->hwirq, type,
NULL);
/* Queue the buffer only after interrupt is enabled */
raw_spin_lock_irqsave(&vgpio->eventq_lock, flags);
if (irq_line->queue_pending) {
irq_line->queue_pending = false;
virtio_gpio_irq_prepare(vgpio, d->hwirq);
}
raw_spin_unlock_irqrestore(&vgpio->eventq_lock, flags);
}
mutex_unlock(&vgpio->irq_lock);
}
static struct irq_chip vgpio_irq_chip = {
.name = "virtio-gpio",
.irq_enable = virtio_gpio_irq_enable,
.irq_disable = virtio_gpio_irq_disable,
.irq_mask = virtio_gpio_irq_mask,
.irq_unmask = virtio_gpio_irq_unmask,
.irq_set_type = virtio_gpio_irq_set_type,
/* These are required to implement irqchip for slow busses */
.irq_bus_lock = virtio_gpio_irq_bus_lock,
.irq_bus_sync_unlock = virtio_gpio_irq_bus_sync_unlock,
};
static bool ignore_irq(struct virtio_gpio *vgpio, int gpio,
struct vgpio_irq_line *irq_line)
{
bool ignore = false;
raw_spin_lock(&vgpio->eventq_lock);
irq_line->queued = false;
/* Interrupt is disabled currently */
if (irq_line->masked || irq_line->disabled) {
ignore = true;
goto unlock;
}
/*
* Buffer is returned as the interrupt was disabled earlier, but is
* enabled again now. Requeue the buffers.
*/
if (irq_line->ires.status == VIRTIO_GPIO_IRQ_STATUS_INVALID) {
virtio_gpio_irq_prepare(vgpio, gpio);
ignore = true;
goto unlock;
}
if (WARN_ON(irq_line->ires.status != VIRTIO_GPIO_IRQ_STATUS_VALID))
ignore = true;
unlock:
raw_spin_unlock(&vgpio->eventq_lock);
return ignore;
}
static void virtio_gpio_event_vq(struct virtqueue *vq)
{
struct virtio_gpio *vgpio = vq->vdev->priv;
struct device *dev = &vgpio->vdev->dev;
struct vgpio_irq_line *irq_line;
int gpio, ret;
unsigned int len;
while (true) {
irq_line = virtqueue_get_buf(vgpio->event_vq, &len);
if (!irq_line)
break;
if (len != sizeof(irq_line->ires)) {
dev_err(dev, "irq with incorrect length (%u : %u)\n",
len, (unsigned int)sizeof(irq_line->ires));
continue;
}
/*
* Find GPIO line number from the offset of irq_line within the
* irq_lines block. We can also get GPIO number from
* irq-request, but better not to rely on a buffer returned by
* remote.
*/
gpio = irq_line - vgpio->irq_lines;
WARN_ON(gpio >= vgpio->gc.ngpio);
if (unlikely(ignore_irq(vgpio, gpio, irq_line)))
continue;
ret = generic_handle_domain_irq(vgpio->gc.irq.domain, gpio);
if (ret)
dev_err(dev, "failed to handle interrupt: %d\n", ret);
}
}
static void virtio_gpio_request_vq(struct virtqueue *vq)
{
struct virtio_gpio_line *line;
unsigned int len;
do {
line = virtqueue_get_buf(vq, &len);
if (!line)
return;
line->rxlen = len;
complete(&line->completion);
} while (1);
}
static void virtio_gpio_free_vqs(struct virtio_device *vdev)
{
virtio_reset_device(vdev);
vdev->config->del_vqs(vdev);
}
static int virtio_gpio_alloc_vqs(struct virtio_gpio *vgpio,
struct virtio_device *vdev)
{
const char * const names[] = { "requestq", "eventq" };
vq_callback_t *cbs[] = {
virtio_gpio_request_vq,
virtio_gpio_event_vq,
};
struct virtqueue *vqs[2] = { NULL, NULL };
int ret;
ret = virtio_find_vqs(vdev, vgpio->irq_lines ? 2 : 1, vqs, cbs, names, NULL);
if (ret) {
dev_err(&vdev->dev, "failed to find vqs: %d\n", ret);
return ret;
}
if (!vqs[0]) {
dev_err(&vdev->dev, "failed to find requestq vq\n");
goto out;
}
vgpio->request_vq = vqs[0];
if (vgpio->irq_lines && !vqs[1]) {
dev_err(&vdev->dev, "failed to find eventq vq\n");
goto out;
}
vgpio->event_vq = vqs[1];
return 0;
out:
if (vqs[0] || vqs[1])
virtio_gpio_free_vqs(vdev);
return -ENODEV;
}
static const char **virtio_gpio_get_names(struct virtio_gpio *vgpio,
u32 gpio_names_size, u16 ngpio)
{
struct virtio_gpio_response_get_names *res;
struct device *dev = &vgpio->vdev->dev;
u8 *gpio_names, *str;
const char **names;
int i, ret, len;
if (!gpio_names_size)
return NULL;
len = sizeof(*res) + gpio_names_size;
res = devm_kzalloc(dev, len, GFP_KERNEL);
if (!res)
return NULL;
gpio_names = res->value;
ret = _virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_GET_NAMES, 0, 0, NULL,
res, len);
if (ret) {
dev_err(dev, "Failed to get GPIO names: %d\n", ret);
return NULL;
}
names = devm_kcalloc(dev, ngpio, sizeof(*names), GFP_KERNEL);
if (!names)
return NULL;
/* NULL terminate the string instead of checking it */
gpio_names[gpio_names_size - 1] = '\0';
for (i = 0, str = gpio_names; i < ngpio; i++) {
names[i] = str;
str += strlen(str) + 1; /* zero-length strings are allowed */
if (str > gpio_names + gpio_names_size) {
dev_err(dev, "gpio_names block is too short (%d)\n", i);
return NULL;
}
}
return names;
}
static int virtio_gpio_probe(struct virtio_device *vdev)
{
struct virtio_gpio_config config;
struct device *dev = &vdev->dev;
struct virtio_gpio *vgpio;
u32 gpio_names_size;
u16 ngpio;
int ret, i;
vgpio = devm_kzalloc(dev, sizeof(*vgpio), GFP_KERNEL);
if (!vgpio)
return -ENOMEM;
/* Read configuration */
virtio_cread_bytes(vdev, 0, &config, sizeof(config));
gpio_names_size = le32_to_cpu(config.gpio_names_size);
ngpio = le16_to_cpu(config.ngpio);
if (!ngpio) {
dev_err(dev, "Number of GPIOs can't be zero\n");
return -EINVAL;
}
vgpio->lines = devm_kcalloc(dev, ngpio, sizeof(*vgpio->lines), GFP_KERNEL);
if (!vgpio->lines)
return -ENOMEM;
for (i = 0; i < ngpio; i++) {
mutex_init(&vgpio->lines[i].lock);
init_completion(&vgpio->lines[i].completion);
}
mutex_init(&vgpio->lock);
vdev->priv = vgpio;
vgpio->vdev = vdev;
vgpio->gc.free = virtio_gpio_free;
vgpio->gc.get_direction = virtio_gpio_get_direction;
vgpio->gc.direction_input = virtio_gpio_direction_input;
vgpio->gc.direction_output = virtio_gpio_direction_output;
vgpio->gc.get = virtio_gpio_get;
vgpio->gc.set = virtio_gpio_set;
vgpio->gc.ngpio = ngpio;
vgpio->gc.base = -1; /* Allocate base dynamically */
vgpio->gc.label = dev_name(dev);
vgpio->gc.parent = dev;
vgpio->gc.owner = THIS_MODULE;
vgpio->gc.can_sleep = true;
/* Interrupt support */
if (virtio_has_feature(vdev, VIRTIO_GPIO_F_IRQ)) {
vgpio->irq_lines = devm_kcalloc(dev, ngpio, sizeof(*vgpio->irq_lines), GFP_KERNEL);
if (!vgpio->irq_lines)
return -ENOMEM;
/* The event comes from the outside so no parent handler */
vgpio->gc.irq.parent_handler = NULL;
vgpio->gc.irq.num_parents = 0;
vgpio->gc.irq.parents = NULL;
vgpio->gc.irq.default_type = IRQ_TYPE_NONE;
vgpio->gc.irq.handler = handle_level_irq;
vgpio->gc.irq.chip = &vgpio_irq_chip;
for (i = 0; i < ngpio; i++) {
vgpio->irq_lines[i].type = VIRTIO_GPIO_IRQ_TYPE_NONE;
vgpio->irq_lines[i].disabled = true;
vgpio->irq_lines[i].masked = true;
}
mutex_init(&vgpio->irq_lock);
raw_spin_lock_init(&vgpio->eventq_lock);
}
ret = virtio_gpio_alloc_vqs(vgpio, vdev);
if (ret)
return ret;
/* Mark the device ready to perform operations from within probe() */
virtio_device_ready(vdev);
vgpio->gc.names = virtio_gpio_get_names(vgpio, gpio_names_size, ngpio);
ret = gpiochip_add_data(&vgpio->gc, vgpio);
if (ret) {
virtio_gpio_free_vqs(vdev);
dev_err(dev, "Failed to add virtio-gpio controller\n");
}
return ret;
}
static void virtio_gpio_remove(struct virtio_device *vdev)
{
struct virtio_gpio *vgpio = vdev->priv;
gpiochip_remove(&vgpio->gc);
virtio_gpio_free_vqs(vdev);
}
static const struct virtio_device_id id_table[] = {
{ VIRTIO_ID_GPIO, VIRTIO_DEV_ANY_ID },
{},
};
MODULE_DEVICE_TABLE(virtio, id_table);
static const unsigned int features[] = {
VIRTIO_GPIO_F_IRQ,
};
static struct virtio_driver virtio_gpio_driver = {
.feature_table = features,
.feature_table_size = ARRAY_SIZE(features),
.id_table = id_table,
.probe = virtio_gpio_probe,
.remove = virtio_gpio_remove,
.driver = {
.name = KBUILD_MODNAME,
.owner = THIS_MODULE,
},
};
module_virtio_driver(virtio_gpio_driver);
MODULE_AUTHOR("Enrico Weigelt, metux IT consult <[email protected]>");
MODULE_AUTHOR("Viresh Kumar <[email protected]>");
MODULE_DESCRIPTION("VirtIO GPIO driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-virtio.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Generic EP93xx GPIO handling
*
* Copyright (c) 2008 Ryan Mallon
* Copyright (c) 2011 H Hartley Sweeten <[email protected]>
*
* Based on code originally from:
* linux/arch/arm/mach-ep93xx/core.c
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>
#include <linux/seq_file.h>
#define EP93XX_GPIO_F_INT_STATUS 0x5c
#define EP93XX_GPIO_A_INT_STATUS 0xa0
#define EP93XX_GPIO_B_INT_STATUS 0xbc
/* Maximum value for gpio line identifiers */
#define EP93XX_GPIO_LINE_MAX 63
/* Number of GPIO chips in EP93XX */
#define EP93XX_GPIO_CHIP_NUM 8
/* Maximum value for irq capable line identifiers */
#define EP93XX_GPIO_LINE_MAX_IRQ 23
#define EP93XX_GPIO_A_IRQ_BASE 64
#define EP93XX_GPIO_B_IRQ_BASE 72
/*
* Static mapping of GPIO bank F IRQS:
* F0..F7 (16..24) to irq 80..87.
*/
#define EP93XX_GPIO_F_IRQ_BASE 80
struct ep93xx_gpio_irq_chip {
u8 irq_offset;
u8 int_unmasked;
u8 int_enabled;
u8 int_type1;
u8 int_type2;
u8 int_debounce;
};
struct ep93xx_gpio_chip {
struct gpio_chip gc;
struct ep93xx_gpio_irq_chip *eic;
};
struct ep93xx_gpio {
void __iomem *base;
struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM];
};
#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
{
struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
return egc->eic;
}
/*************************************************************************
* Interrupt handling for EP93xx on-chip GPIOs
*************************************************************************/
#define EP93XX_INT_TYPE1_OFFSET 0x00
#define EP93XX_INT_TYPE2_OFFSET 0x04
#define EP93XX_INT_EOI_OFFSET 0x08
#define EP93XX_INT_EN_OFFSET 0x0c
#define EP93XX_INT_STATUS_OFFSET 0x10
#define EP93XX_INT_RAW_STATUS_OFFSET 0x14
#define EP93XX_INT_DEBOUNCE_OFFSET 0x18
static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
struct ep93xx_gpio_irq_chip *eic)
{
writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
writeb_relaxed(eic->int_type2,
epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
writeb_relaxed(eic->int_type1,
epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
writeb_relaxed(eic->int_unmasked & eic->int_enabled,
epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
}
static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
unsigned int offset, bool enable)
{
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
int port_mask = BIT(offset);
if (enable)
eic->int_debounce |= port_mask;
else
eic->int_debounce &= ~port_mask;
writeb(eic->int_debounce,
epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
}
static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
struct irq_chip *irqchip = irq_desc_get_chip(desc);
unsigned long stat;
int offset;
chained_irq_enter(irqchip, desc);
/*
* Dispatch the IRQs to the irqdomain of each A and B
* gpiochip irqdomains depending on what has fired.
* The tricky part is that the IRQ line is shared
* between bank A and B and each has their own gpiochip.
*/
stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
for_each_set_bit(offset, &stat, 8)
generic_handle_domain_irq(epg->gc[0].gc.irq.domain,
offset);
stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
for_each_set_bit(offset, &stat, 8)
generic_handle_domain_irq(epg->gc[1].gc.irq.domain,
offset);
chained_irq_exit(irqchip, desc);
}
static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
{
/*
* map discontiguous hw irq range to continuous sw irq range:
*
* IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
*/
struct irq_chip *irqchip = irq_desc_get_chip(desc);
unsigned int irq = irq_desc_get_irq(desc);
int port_f_idx = (irq & 7) ^ 4; /* {20..23,48..51} -> {0..7} */
int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
chained_irq_enter(irqchip, desc);
generic_handle_irq(gpio_irq);
chained_irq_exit(irqchip, desc);
}
static void ep93xx_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
int port_mask = BIT(d->irq & 7);
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
eic->int_type2 ^= port_mask; /* switch edge direction */
ep93xx_gpio_update_int_params(epg, eic);
}
writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
}
static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
int port_mask = BIT(d->irq & 7);
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
eic->int_type2 ^= port_mask; /* switch edge direction */
eic->int_unmasked &= ~port_mask;
ep93xx_gpio_update_int_params(epg, eic);
writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
static void ep93xx_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
eic->int_unmasked &= ~BIT(d->irq & 7);
ep93xx_gpio_update_int_params(epg, eic);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
static void ep93xx_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
eic->int_unmasked |= BIT(d->irq & 7);
ep93xx_gpio_update_int_params(epg, eic);
}
/*
* gpio_int_type1 controls whether the interrupt is level (0) or
* edge (1) triggered, while gpio_int_type2 controls whether it
* triggers on low/falling (0) or high/rising (1).
*/
static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
int offset = d->irq & 7;
int port_mask = BIT(offset);
irq_flow_handler_t handler;
gc->direction_input(gc, offset);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
eic->int_type1 |= port_mask;
eic->int_type2 |= port_mask;
handler = handle_edge_irq;
break;
case IRQ_TYPE_EDGE_FALLING:
eic->int_type1 |= port_mask;
eic->int_type2 &= ~port_mask;
handler = handle_edge_irq;
break;
case IRQ_TYPE_LEVEL_HIGH:
eic->int_type1 &= ~port_mask;
eic->int_type2 |= port_mask;
handler = handle_level_irq;
break;
case IRQ_TYPE_LEVEL_LOW:
eic->int_type1 &= ~port_mask;
eic->int_type2 &= ~port_mask;
handler = handle_level_irq;
break;
case IRQ_TYPE_EDGE_BOTH:
eic->int_type1 |= port_mask;
/* set initial polarity based on current input level */
if (gc->get(gc, offset))
eic->int_type2 &= ~port_mask; /* falling */
else
eic->int_type2 |= port_mask; /* rising */
handler = handle_edge_irq;
break;
default:
return -EINVAL;
}
irq_set_handler_locked(d, handler);
eic->int_enabled |= port_mask;
ep93xx_gpio_update_int_params(epg, eic);
return 0;
}
/*************************************************************************
* gpiolib interface for EP93xx on-chip GPIOs
*************************************************************************/
struct ep93xx_gpio_bank {
const char *label;
int data;
int dir;
int irq;
int base;
bool has_irq;
bool has_hierarchical_irq;
unsigned int irq_base;
};
#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
{ \
.label = _label, \
.data = _data, \
.dir = _dir, \
.irq = _irq, \
.base = _base, \
.has_irq = _has_irq, \
.has_hierarchical_irq = _has_hier, \
.irq_base = _irq_base, \
}
static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
/* Bank A has 8 IRQs */
EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ_BASE),
/* Bank B has 8 IRQs */
EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ_BASE),
EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
/* Bank F has 8 IRQs */
EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IRQ_BASE),
EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
};
static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
unsigned long config)
{
u32 debounce;
if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
return -ENOTSUPP;
debounce = pinconf_to_config_argument(config);
ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
return 0;
}
static void ep93xx_irq_print_chip(struct irq_data *data, struct seq_file *p)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
seq_printf(p, dev_name(gc->parent));
}
static const struct irq_chip gpio_eic_irq_chip = {
.name = "ep93xx-gpio-eic",
.irq_ack = ep93xx_gpio_irq_ack,
.irq_mask = ep93xx_gpio_irq_mask,
.irq_unmask = ep93xx_gpio_irq_unmask,
.irq_mask_ack = ep93xx_gpio_irq_mask_ack,
.irq_set_type = ep93xx_gpio_irq_type,
.irq_print_chip = ep93xx_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
struct platform_device *pdev,
struct ep93xx_gpio *epg,
struct ep93xx_gpio_bank *bank)
{
void __iomem *data = epg->base + bank->data;
void __iomem *dir = epg->base + bank->dir;
struct gpio_chip *gc = &egc->gc;
struct device *dev = &pdev->dev;
struct gpio_irq_chip *girq;
int err;
err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
if (err)
return err;
gc->label = bank->label;
gc->base = bank->base;
girq = &gc->irq;
if (bank->has_irq || bank->has_hierarchical_irq) {
gc->set_config = ep93xx_gpio_set_config;
egc->eic = devm_kcalloc(dev, 1,
sizeof(*egc->eic),
GFP_KERNEL);
if (!egc->eic)
return -ENOMEM;
egc->eic->irq_offset = bank->irq;
gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip);
}
if (bank->has_irq) {
int ab_parent_irq = platform_get_irq(pdev, 0);
girq->parent_handler = ep93xx_gpio_ab_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, girq->num_parents,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
girq->parents[0] = ab_parent_irq;
girq->first = bank->irq_base;
}
/* Only bank F has especially funky IRQ handling */
if (bank->has_hierarchical_irq) {
int gpio_irq;
int i;
/*
* FIXME: convert this to use hierarchical IRQ support!
* this requires fixing the root irqchip to be hierarchical.
*/
girq->parent_handler = ep93xx_gpio_f_irq_handler;
girq->num_parents = 8;
girq->parents = devm_kcalloc(dev, girq->num_parents,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
/* Pick resources 1..8 for these IRQs */
for (i = 0; i < girq->num_parents; i++) {
girq->parents[i] = platform_get_irq(pdev, i + 1);
gpio_irq = bank->irq_base + i;
irq_set_chip_data(gpio_irq, &epg->gc[5]);
irq_set_chip_and_handler(gpio_irq,
girq->chip,
handle_level_irq);
irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
}
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
girq->first = bank->irq_base;
}
return devm_gpiochip_add_data(dev, gc, epg);
}
static int ep93xx_gpio_probe(struct platform_device *pdev)
{
struct ep93xx_gpio *epg;
int i;
epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
if (!epg)
return -ENOMEM;
epg->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(epg->base))
return PTR_ERR(epg->base);
for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
struct ep93xx_gpio_chip *gc = &epg->gc[i];
struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
bank->label);
}
return 0;
}
static struct platform_driver ep93xx_gpio_driver = {
.driver = {
.name = "gpio-ep93xx",
},
.probe = ep93xx_gpio_probe,
};
static int __init ep93xx_gpio_init(void)
{
return platform_driver_register(&ep93xx_gpio_driver);
}
postcore_initcall(ep93xx_gpio_init);
MODULE_AUTHOR("Ryan Mallon <[email protected]> "
"H Hartley Sweeten <[email protected]>");
MODULE_DESCRIPTION("EP93XX GPIO driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-ep93xx.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/gpio/driver.h>
#include <linux/cpumask.h>
#include <linux/irq.h>
#include <linux/minmax.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
/*
* Total register block size is 0x1C for one bank of four ports (A, B, C, D).
* An optional second bank, with ports E, F, G, and H, may be present, starting
* at register offset 0x1C.
*/
/*
* Pin select: (0) "normal", (1) "dedicate peripheral"
* Not used on RTL8380/RTL8390, peripheral selection is managed by control bits
* in the peripheral registers.
*/
#define REALTEK_GPIO_REG_CNR 0x00
/* Clear bit (0) for input, set bit (1) for output */
#define REALTEK_GPIO_REG_DIR 0x08
#define REALTEK_GPIO_REG_DATA 0x0C
/* Read bit for IRQ status, write 1 to clear IRQ */
#define REALTEK_GPIO_REG_ISR 0x10
/* Two bits per GPIO in IMR registers */
#define REALTEK_GPIO_REG_IMR 0x14
#define REALTEK_GPIO_REG_IMR_AB 0x14
#define REALTEK_GPIO_REG_IMR_CD 0x18
#define REALTEK_GPIO_IMR_LINE_MASK GENMASK(1, 0)
#define REALTEK_GPIO_IRQ_EDGE_FALLING 1
#define REALTEK_GPIO_IRQ_EDGE_RISING 2
#define REALTEK_GPIO_IRQ_EDGE_BOTH 3
#define REALTEK_GPIO_MAX 32
#define REALTEK_GPIO_PORTS_PER_BANK 4
/**
* realtek_gpio_ctrl - Realtek Otto GPIO driver data
*
* @gc: Associated gpio_chip instance
* @base: Base address of the register block for a GPIO bank
* @lock: Lock for accessing the IRQ registers and values
* @intr_mask: Mask for interrupts lines
* @intr_type: Interrupt type selection
* @bank_read: Read a bank setting as a single 32-bit value
* @bank_write: Write a bank setting as a single 32-bit value
* @imr_line_pos: Bit shift of an IRQ line's IMR value.
*
* The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
* into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
* a value from (to) these registers. The IMR register consists of four 16-bit
* port values, packed into two 32-bit registers. Use @imr_line_pos to get the
* bit shift of the 2-bit field for a line's IMR settings. Shifts larger than
* 32 overflow into the second register.
*
* Because the interrupt mask register (IMR) combines the function of IRQ type
* selection and masking, two extra values are stored. @intr_mask is used to
* mask/unmask the interrupts for a GPIO line, and @intr_type is used to store
* the selected interrupt types. The logical AND of these values is written to
* IMR on changes.
*/
struct realtek_gpio_ctrl {
struct gpio_chip gc;
void __iomem *base;
void __iomem *cpumask_base;
struct cpumask cpu_irq_maskable;
raw_spinlock_t lock;
u8 intr_mask[REALTEK_GPIO_MAX];
u8 intr_type[REALTEK_GPIO_MAX];
u32 (*bank_read)(void __iomem *reg);
void (*bank_write)(void __iomem *reg, u32 value);
unsigned int (*line_imr_pos)(unsigned int line);
};
/* Expand with more flags as devices with other quirks are added */
enum realtek_gpio_flags {
/*
* Allow disabling interrupts, for cases where the port order is
* unknown. This may result in a port mismatch between ISR and IMR.
* An interrupt would appear to come from a different line than the
* line the IRQ handler was assigned to, causing uncaught interrupts.
*/
GPIO_INTERRUPTS_DISABLED = BIT(0),
/*
* Port order is reversed, meaning DCBA register layout for 1-bit
* fields, and [BA, DC] for 2-bit fields.
*/
GPIO_PORTS_REVERSED = BIT(1),
/*
* Interrupts can be enabled per cpu. This requires a secondary IO
* range, where the per-cpu enable masks are located.
*/
GPIO_INTERRUPTS_PER_CPU = BIT(2),
};
static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
return container_of(gc, struct realtek_gpio_ctrl, gc);
}
/*
* Normal port order register access
*
* Port information is stored with the first port at offset 0, followed by the
* second, etc. Most registers store one bit per GPIO and use a u8 value per
* port. The two interrupt mask registers store two bits per GPIO, so use u16
* values.
*/
static u32 realtek_gpio_bank_read_swapped(void __iomem *reg)
{
return ioread32be(reg);
}
static void realtek_gpio_bank_write_swapped(void __iomem *reg, u32 value)
{
iowrite32be(value, reg);
}
static unsigned int realtek_gpio_line_imr_pos_swapped(unsigned int line)
{
unsigned int port_pin = line % 8;
unsigned int port = line / 8;
return 2 * (8 * (port ^ 1) + port_pin);
}
/*
* Reversed port order register access
*
* For registers with one bit per GPIO, all ports are stored as u8-s in one
* register in reversed order. The two interrupt mask registers store two bits
* per GPIO, so use u16 values. The first register contains ports 1 and 0, the
* second ports 3 and 2.
*/
static u32 realtek_gpio_bank_read(void __iomem *reg)
{
return ioread32(reg);
}
static void realtek_gpio_bank_write(void __iomem *reg, u32 value)
{
iowrite32(value, reg);
}
static unsigned int realtek_gpio_line_imr_pos(unsigned int line)
{
return 2 * line;
}
static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, u32 mask)
{
ctrl->bank_write(ctrl->base + REALTEK_GPIO_REG_ISR, mask);
}
static u32 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl)
{
return ctrl->bank_read(ctrl->base + REALTEK_GPIO_REG_ISR);
}
/* Set the rising and falling edge mask bits for a GPIO pin */
static void realtek_gpio_update_line_imr(struct realtek_gpio_ctrl *ctrl, unsigned int line)
{
void __iomem *reg = ctrl->base + REALTEK_GPIO_REG_IMR;
unsigned int line_shift = ctrl->line_imr_pos(line);
unsigned int shift = line_shift % 32;
u32 irq_type = ctrl->intr_type[line];
u32 irq_mask = ctrl->intr_mask[line];
u32 reg_val;
reg += 4 * (line_shift / 32);
reg_val = ioread32(reg);
reg_val &= ~(REALTEK_GPIO_IMR_LINE_MASK << shift);
reg_val |= (irq_type & irq_mask & REALTEK_GPIO_IMR_LINE_MASK) << shift;
iowrite32(reg_val, reg);
}
static void realtek_gpio_irq_ack(struct irq_data *data)
{
struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
irq_hw_number_t line = irqd_to_hwirq(data);
realtek_gpio_clear_isr(ctrl, BIT(line));
}
static void realtek_gpio_irq_unmask(struct irq_data *data)
{
struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
unsigned int line = irqd_to_hwirq(data);
unsigned long flags;
gpiochip_enable_irq(&ctrl->gc, line);
raw_spin_lock_irqsave(&ctrl->lock, flags);
ctrl->intr_mask[line] = REALTEK_GPIO_IMR_LINE_MASK;
realtek_gpio_update_line_imr(ctrl, line);
raw_spin_unlock_irqrestore(&ctrl->lock, flags);
}
static void realtek_gpio_irq_mask(struct irq_data *data)
{
struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
unsigned int line = irqd_to_hwirq(data);
unsigned long flags;
raw_spin_lock_irqsave(&ctrl->lock, flags);
ctrl->intr_mask[line] = 0;
realtek_gpio_update_line_imr(ctrl, line);
raw_spin_unlock_irqrestore(&ctrl->lock, flags);
gpiochip_disable_irq(&ctrl->gc, line);
}
static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
{
struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
unsigned int line = irqd_to_hwirq(data);
unsigned long flags;
u8 type;
switch (flow_type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_FALLING:
type = REALTEK_GPIO_IRQ_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_RISING:
type = REALTEK_GPIO_IRQ_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_BOTH:
type = REALTEK_GPIO_IRQ_EDGE_BOTH;
break;
default:
return -EINVAL;
}
irq_set_handler_locked(data, handle_edge_irq);
raw_spin_lock_irqsave(&ctrl->lock, flags);
ctrl->intr_type[line] = type;
realtek_gpio_update_line_imr(ctrl, line);
raw_spin_unlock_irqrestore(&ctrl->lock, flags);
return 0;
}
static void realtek_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
struct irq_chip *irq_chip = irq_desc_get_chip(desc);
unsigned long status;
int offset;
chained_irq_enter(irq_chip, desc);
status = realtek_gpio_read_isr(ctrl);
for_each_set_bit(offset, &status, gc->ngpio)
generic_handle_domain_irq(gc->irq.domain, offset);
chained_irq_exit(irq_chip, desc);
}
static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, int cpu)
{
return ctrl->cpumask_base + REALTEK_GPIO_PORTS_PER_BANK * cpu;
}
static int realtek_gpio_irq_set_affinity(struct irq_data *data,
const struct cpumask *dest, bool force)
{
struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
unsigned int line = irqd_to_hwirq(data);
void __iomem *irq_cpu_mask;
unsigned long flags;
int cpu;
u32 v;
if (!ctrl->cpumask_base)
return -ENXIO;
raw_spin_lock_irqsave(&ctrl->lock, flags);
for_each_cpu(cpu, &ctrl->cpu_irq_maskable) {
irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, cpu);
v = ctrl->bank_read(irq_cpu_mask);
if (cpumask_test_cpu(cpu, dest))
v |= BIT(line);
else
v &= ~BIT(line);
ctrl->bank_write(irq_cpu_mask, v);
}
raw_spin_unlock_irqrestore(&ctrl->lock, flags);
irq_data_update_effective_affinity(data, dest);
return 0;
}
static int realtek_gpio_irq_init(struct gpio_chip *gc)
{
struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
u32 mask_all = GENMASK(gc->ngpio - 1, 0);
unsigned int line;
int cpu;
for (line = 0; line < gc->ngpio; line++)
realtek_gpio_update_line_imr(ctrl, line);
realtek_gpio_clear_isr(ctrl, mask_all);
for_each_cpu(cpu, &ctrl->cpu_irq_maskable)
ctrl->bank_write(realtek_gpio_irq_cpu_mask(ctrl, cpu), mask_all);
return 0;
}
static const struct irq_chip realtek_gpio_irq_chip = {
.name = "realtek-otto-gpio",
.irq_ack = realtek_gpio_irq_ack,
.irq_mask = realtek_gpio_irq_mask,
.irq_unmask = realtek_gpio_irq_unmask,
.irq_set_type = realtek_gpio_irq_set_type,
.irq_set_affinity = realtek_gpio_irq_set_affinity,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static const struct of_device_id realtek_gpio_of_match[] = {
{
.compatible = "realtek,otto-gpio",
.data = (void *)GPIO_INTERRUPTS_DISABLED,
},
{
.compatible = "realtek,rtl8380-gpio",
},
{
.compatible = "realtek,rtl8390-gpio",
},
{
.compatible = "realtek,rtl9300-gpio",
.data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU)
},
{
.compatible = "realtek,rtl9310-gpio",
},
{}
};
MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);
static int realtek_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
unsigned long bgpio_flags;
unsigned int dev_flags;
struct gpio_irq_chip *girq;
struct realtek_gpio_ctrl *ctrl;
struct resource *res;
u32 ngpios;
unsigned int nr_cpus;
int cpu, err, irq;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return -ENOMEM;
dev_flags = (unsigned int) device_get_match_data(dev);
ngpios = REALTEK_GPIO_MAX;
device_property_read_u32(dev, "ngpios", &ngpios);
if (ngpios > REALTEK_GPIO_MAX) {
dev_err(&pdev->dev, "invalid ngpios (max. %d)\n",
REALTEK_GPIO_MAX);
return -EINVAL;
}
ctrl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ctrl->base))
return PTR_ERR(ctrl->base);
raw_spin_lock_init(&ctrl->lock);
if (dev_flags & GPIO_PORTS_REVERSED) {
bgpio_flags = 0;
ctrl->bank_read = realtek_gpio_bank_read;
ctrl->bank_write = realtek_gpio_bank_write;
ctrl->line_imr_pos = realtek_gpio_line_imr_pos;
} else {
bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
ctrl->bank_read = realtek_gpio_bank_read_swapped;
ctrl->bank_write = realtek_gpio_bank_write_swapped;
ctrl->line_imr_pos = realtek_gpio_line_imr_pos_swapped;
}
err = bgpio_init(&ctrl->gc, dev, 4,
ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL,
ctrl->base + REALTEK_GPIO_REG_DIR, NULL,
bgpio_flags);
if (err) {
dev_err(dev, "unable to init generic GPIO");
return err;
}
ctrl->gc.ngpio = ngpios;
ctrl->gc.owner = THIS_MODULE;
irq = platform_get_irq_optional(pdev, 0);
if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) {
girq = &ctrl->gc.irq;
gpio_irq_chip_set_chip(girq, &realtek_gpio_irq_chip);
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
girq->parent_handler = realtek_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, girq->num_parents,
sizeof(*girq->parents), GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = irq;
girq->init_hw = realtek_gpio_irq_init;
}
cpumask_clear(&ctrl->cpu_irq_maskable);
if ((dev_flags & GPIO_INTERRUPTS_PER_CPU) && irq > 0) {
ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
if (IS_ERR(ctrl->cpumask_base))
return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base),
"missing CPU IRQ mask registers");
nr_cpus = resource_size(res) / REALTEK_GPIO_PORTS_PER_BANK;
nr_cpus = min(nr_cpus, num_present_cpus());
for (cpu = 0; cpu < nr_cpus; cpu++)
cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable);
}
return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
}
static struct platform_driver realtek_gpio_driver = {
.driver = {
.name = "realtek-otto-gpio",
.of_match_table = realtek_gpio_of_match,
},
.probe = realtek_gpio_probe,
};
module_platform_driver(realtek_gpio_driver);
MODULE_DESCRIPTION("Realtek Otto GPIO support");
MODULE_AUTHOR("Sander Vanheule <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-realtek-otto.c |
// SPDX-License-Identifier: GPL-2.0
/*
* GPIO interface for Intel Poulsbo SCH
*
* Copyright (c) 2010 CompuLab Ltd
* Author: Denis Turischev <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci_ids.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#define GEN 0x00
#define GIO 0x04
#define GLV 0x08
#define GTPE 0x0c
#define GTNE 0x10
#define GGPE 0x14
#define GSMI 0x18
#define GTS 0x1c
#define CORE_BANK_OFFSET 0x00
#define RESUME_BANK_OFFSET 0x20
/*
* iLB datasheet describes GPE0BLK registers, in particular GPE0E.GPIO bit.
* Document Number: 328195-001
*/
#define GPE0E_GPIO 14
struct sch_gpio {
struct gpio_chip chip;
spinlock_t lock;
unsigned short iobase;
unsigned short resume_base;
/* GPE handling */
u32 gpe;
acpi_gpe_handler gpe_handler;
};
static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio,
unsigned int reg)
{
unsigned int base = CORE_BANK_OFFSET;
if (gpio >= sch->resume_base) {
gpio -= sch->resume_base;
base = RESUME_BANK_OFFSET;
}
return base + reg + gpio / 8;
}
static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio)
{
if (gpio >= sch->resume_base)
gpio -= sch->resume_base;
return gpio % 8;
}
static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg)
{
unsigned short offset, bit;
u8 reg_val;
offset = sch_gpio_offset(sch, gpio, reg);
bit = sch_gpio_bit(sch, gpio);
reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
return reg_val;
}
static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg,
int val)
{
unsigned short offset, bit;
u8 reg_val;
offset = sch_gpio_offset(sch, gpio, reg);
bit = sch_gpio_bit(sch, gpio);
reg_val = inb(sch->iobase + offset);
if (val)
outb(reg_val | BIT(bit), sch->iobase + offset);
else
outb((reg_val & ~BIT(bit)), sch->iobase + offset);
}
static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned int gpio_num)
{
struct sch_gpio *sch = gpiochip_get_data(gc);
unsigned long flags;
spin_lock_irqsave(&sch->lock, flags);
sch_gpio_reg_set(sch, gpio_num, GIO, 1);
spin_unlock_irqrestore(&sch->lock, flags);
return 0;
}
static int sch_gpio_get(struct gpio_chip *gc, unsigned int gpio_num)
{
struct sch_gpio *sch = gpiochip_get_data(gc);
return sch_gpio_reg_get(sch, gpio_num, GLV);
}
static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)
{
struct sch_gpio *sch = gpiochip_get_data(gc);
unsigned long flags;
spin_lock_irqsave(&sch->lock, flags);
sch_gpio_reg_set(sch, gpio_num, GLV, val);
spin_unlock_irqrestore(&sch->lock, flags);
}
static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num,
int val)
{
struct sch_gpio *sch = gpiochip_get_data(gc);
unsigned long flags;
spin_lock_irqsave(&sch->lock, flags);
sch_gpio_reg_set(sch, gpio_num, GIO, 0);
spin_unlock_irqrestore(&sch->lock, flags);
/*
* according to the datasheet, writing to the level register has no
* effect when GPIO is programmed as input.
* Actually the level register is read-only when configured as input.
* Thus presetting the output level before switching to output is _NOT_ possible.
* Hence we set the level after configuring the GPIO as output.
* But we cannot prevent a short low pulse if direction is set to high
* and an external pull-up is connected.
*/
sch_gpio_set(gc, gpio_num, val);
return 0;
}
static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num)
{
struct sch_gpio *sch = gpiochip_get_data(gc);
if (sch_gpio_reg_get(sch, gpio_num, GIO))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static const struct gpio_chip sch_gpio_chip = {
.label = "sch_gpio",
.owner = THIS_MODULE,
.direction_input = sch_gpio_direction_in,
.get = sch_gpio_get,
.direction_output = sch_gpio_direction_out,
.set = sch_gpio_set,
.get_direction = sch_gpio_get_direction,
};
static int sch_irq_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sch_gpio *sch = gpiochip_get_data(gc);
irq_hw_number_t gpio_num = irqd_to_hwirq(d);
unsigned long flags;
int rising, falling;
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
rising = 1;
falling = 0;
break;
case IRQ_TYPE_EDGE_FALLING:
rising = 0;
falling = 1;
break;
case IRQ_TYPE_EDGE_BOTH:
rising = 1;
falling = 1;
break;
default:
return -EINVAL;
}
spin_lock_irqsave(&sch->lock, flags);
sch_gpio_reg_set(sch, gpio_num, GTPE, rising);
sch_gpio_reg_set(sch, gpio_num, GTNE, falling);
irq_set_handler_locked(d, handle_edge_irq);
spin_unlock_irqrestore(&sch->lock, flags);
return 0;
}
static void sch_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sch_gpio *sch = gpiochip_get_data(gc);
irq_hw_number_t gpio_num = irqd_to_hwirq(d);
unsigned long flags;
spin_lock_irqsave(&sch->lock, flags);
sch_gpio_reg_set(sch, gpio_num, GTS, 1);
spin_unlock_irqrestore(&sch->lock, flags);
}
static void sch_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t gpio_num, int val)
{
struct sch_gpio *sch = gpiochip_get_data(gc);
unsigned long flags;
spin_lock_irqsave(&sch->lock, flags);
sch_gpio_reg_set(sch, gpio_num, GGPE, val);
spin_unlock_irqrestore(&sch->lock, flags);
}
static void sch_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t gpio_num = irqd_to_hwirq(d);
sch_irq_mask_unmask(gc, gpio_num, 0);
gpiochip_disable_irq(gc, gpio_num);
}
static void sch_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t gpio_num = irqd_to_hwirq(d);
gpiochip_enable_irq(gc, gpio_num);
sch_irq_mask_unmask(gc, gpio_num, 1);
}
static const struct irq_chip sch_irqchip = {
.name = "sch_gpio",
.irq_ack = sch_irq_ack,
.irq_mask = sch_irq_mask,
.irq_unmask = sch_irq_unmask,
.irq_set_type = sch_irq_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context)
{
struct sch_gpio *sch = context;
struct gpio_chip *gc = &sch->chip;
unsigned long core_status, resume_status;
unsigned long pending;
unsigned long flags;
int offset;
u32 ret;
spin_lock_irqsave(&sch->lock, flags);
core_status = inl(sch->iobase + CORE_BANK_OFFSET + GTS);
resume_status = inl(sch->iobase + RESUME_BANK_OFFSET + GTS);
spin_unlock_irqrestore(&sch->lock, flags);
pending = (resume_status << sch->resume_base) | core_status;
for_each_set_bit(offset, &pending, sch->chip.ngpio)
generic_handle_domain_irq(gc->irq.domain, offset);
/* Set returning value depending on whether we handled an interrupt */
ret = pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;
/* Acknowledge GPE to ACPICA */
ret |= ACPI_REENABLE_GPE;
return ret;
}
static void sch_gpio_remove_gpe_handler(void *data)
{
struct sch_gpio *sch = data;
acpi_disable_gpe(NULL, sch->gpe);
acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
}
static int sch_gpio_install_gpe_handler(struct sch_gpio *sch)
{
struct device *dev = sch->chip.parent;
acpi_status status;
status = acpi_install_gpe_handler(NULL, sch->gpe, ACPI_GPE_LEVEL_TRIGGERED,
sch->gpe_handler, sch);
if (ACPI_FAILURE(status)) {
dev_err(dev, "Failed to install GPE handler for %u: %s\n",
sch->gpe, acpi_format_exception(status));
return -ENODEV;
}
status = acpi_enable_gpe(NULL, sch->gpe);
if (ACPI_FAILURE(status)) {
dev_err(dev, "Failed to enable GPE handler for %u: %s\n",
sch->gpe, acpi_format_exception(status));
acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
return -ENODEV;
}
return devm_add_action_or_reset(dev, sch_gpio_remove_gpe_handler, sch);
}
static int sch_gpio_probe(struct platform_device *pdev)
{
struct gpio_irq_chip *girq;
struct sch_gpio *sch;
struct resource *res;
int ret;
sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
if (!sch)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!res)
return -EBUSY;
if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
pdev->name))
return -EBUSY;
spin_lock_init(&sch->lock);
sch->iobase = res->start;
sch->chip = sch_gpio_chip;
sch->chip.label = dev_name(&pdev->dev);
sch->chip.parent = &pdev->dev;
switch (pdev->id) {
case PCI_DEVICE_ID_INTEL_SCH_LPC:
sch->resume_base = 10;
sch->chip.ngpio = 14;
/*
* GPIO[6:0] enabled by default
* GPIO7 is configured by the CMC as SLPIOVR
* Enable GPIO[9:8] core powered gpios explicitly
*/
sch_gpio_reg_set(sch, 8, GEN, 1);
sch_gpio_reg_set(sch, 9, GEN, 1);
/*
* SUS_GPIO[2:0] enabled by default
* Enable SUS_GPIO3 resume powered gpio explicitly
*/
sch_gpio_reg_set(sch, 13, GEN, 1);
break;
case PCI_DEVICE_ID_INTEL_ITC_LPC:
sch->resume_base = 5;
sch->chip.ngpio = 14;
break;
case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
sch->resume_base = 21;
sch->chip.ngpio = 30;
break;
case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
sch->resume_base = 2;
sch->chip.ngpio = 8;
break;
default:
return -ENODEV;
}
girq = &sch->chip.irq;
gpio_irq_chip_set_chip(girq, &sch_irqchip);
girq->num_parents = 0;
girq->parents = NULL;
girq->parent_handler = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
/* GPE setup is optional */
sch->gpe = GPE0E_GPIO;
sch->gpe_handler = sch_gpio_gpe_handler;
ret = sch_gpio_install_gpe_handler(sch);
if (ret)
dev_warn(&pdev->dev, "Can't setup GPE, no IRQ support\n");
return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
}
static struct platform_driver sch_gpio_driver = {
.driver = {
.name = "sch_gpio",
},
.probe = sch_gpio_probe,
};
module_platform_driver(sch_gpio_driver);
MODULE_AUTHOR("Denis Turischev <[email protected]>");
MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:sch_gpio");
| linux-master | drivers/gpio/gpio-sch.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Linux GPIOlib driver for the VIA VX855 integrated southbridge GPIO
*
* Copyright (C) 2009 VIA Technologies, Inc.
* Copyright (C) 2010 One Laptop per Child
* Author: Harald Welte <[email protected]>
* All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/io.h>
#define MODULE_NAME "vx855_gpio"
/* The VX855 south bridge has the following GPIO pins:
* GPI 0...13 General Purpose Input
* GPO 0...12 General Purpose Output
* GPIO 0...14 General Purpose I/O (Open-Drain)
*/
#define NR_VX855_GPI 14
#define NR_VX855_GPO 13
#define NR_VX855_GPIO 15
#define NR_VX855_GPInO (NR_VX855_GPI + NR_VX855_GPO)
#define NR_VX855_GP (NR_VX855_GPI + NR_VX855_GPO + NR_VX855_GPIO)
struct vx855_gpio {
struct gpio_chip gpio;
spinlock_t lock;
u32 io_gpi;
u32 io_gpo;
};
/* resolve a GPIx into the corresponding bit position */
static inline u_int32_t gpi_i_bit(int i)
{
if (i < 10)
return 1 << i;
else
return 1 << (i + 14);
}
static inline u_int32_t gpo_o_bit(int i)
{
if (i < 11)
return 1 << i;
else
return 1 << (i + 14);
}
static inline u_int32_t gpio_i_bit(int i)
{
if (i < 14)
return 1 << (i + 10);
else
return 1 << (i + 14);
}
static inline u_int32_t gpio_o_bit(int i)
{
if (i < 14)
return 1 << (i + 11);
else
return 1 << (i + 13);
}
/* Mapping between numeric GPIO ID and the actual GPIO hardware numbering:
* 0..13 GPI 0..13
* 14..26 GPO 0..12
* 27..41 GPIO 0..14
*/
static int vx855gpio_direction_input(struct gpio_chip *gpio,
unsigned int nr)
{
struct vx855_gpio *vg = gpiochip_get_data(gpio);
unsigned long flags;
u_int32_t reg_out;
/* Real GPI bits are always in input direction */
if (nr < NR_VX855_GPI)
return 0;
/* Real GPO bits cannot be put in output direction */
if (nr < NR_VX855_GPInO)
return -EINVAL;
/* Open Drain GPIO have to be set to one */
spin_lock_irqsave(&vg->lock, flags);
reg_out = inl(vg->io_gpo);
reg_out |= gpio_o_bit(nr - NR_VX855_GPInO);
outl(reg_out, vg->io_gpo);
spin_unlock_irqrestore(&vg->lock, flags);
return 0;
}
static int vx855gpio_get(struct gpio_chip *gpio, unsigned int nr)
{
struct vx855_gpio *vg = gpiochip_get_data(gpio);
u_int32_t reg_in;
int ret = 0;
if (nr < NR_VX855_GPI) {
reg_in = inl(vg->io_gpi);
if (reg_in & gpi_i_bit(nr))
ret = 1;
} else if (nr < NR_VX855_GPInO) {
/* GPO don't have an input bit, we need to read it
* back from the output register */
reg_in = inl(vg->io_gpo);
if (reg_in & gpo_o_bit(nr - NR_VX855_GPI))
ret = 1;
} else {
reg_in = inl(vg->io_gpi);
if (reg_in & gpio_i_bit(nr - NR_VX855_GPInO))
ret = 1;
}
return ret;
}
static void vx855gpio_set(struct gpio_chip *gpio, unsigned int nr,
int val)
{
struct vx855_gpio *vg = gpiochip_get_data(gpio);
unsigned long flags;
u_int32_t reg_out;
/* True GPI cannot be switched to output mode */
if (nr < NR_VX855_GPI)
return;
spin_lock_irqsave(&vg->lock, flags);
reg_out = inl(vg->io_gpo);
if (nr < NR_VX855_GPInO) {
if (val)
reg_out |= gpo_o_bit(nr - NR_VX855_GPI);
else
reg_out &= ~gpo_o_bit(nr - NR_VX855_GPI);
} else {
if (val)
reg_out |= gpio_o_bit(nr - NR_VX855_GPInO);
else
reg_out &= ~gpio_o_bit(nr - NR_VX855_GPInO);
}
outl(reg_out, vg->io_gpo);
spin_unlock_irqrestore(&vg->lock, flags);
}
static int vx855gpio_direction_output(struct gpio_chip *gpio,
unsigned int nr, int val)
{
/* True GPI cannot be switched to output mode */
if (nr < NR_VX855_GPI)
return -EINVAL;
/* True GPO don't need to be switched to output mode,
* and GPIO are open-drain, i.e. also need no switching,
* so all we do is set the level */
vx855gpio_set(gpio, nr, val);
return 0;
}
static int vx855gpio_set_config(struct gpio_chip *gpio, unsigned int nr,
unsigned long config)
{
enum pin_config_param param = pinconf_to_config_param(config);
/* The GPI cannot be single-ended */
if (nr < NR_VX855_GPI)
return -EINVAL;
/* The GPO's are push-pull */
if (nr < NR_VX855_GPInO) {
if (param != PIN_CONFIG_DRIVE_PUSH_PULL)
return -ENOTSUPP;
return 0;
}
/* The GPIO's are open drain */
if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN)
return -ENOTSUPP;
return 0;
}
static const char *vx855gpio_names[NR_VX855_GP] = {
"VX855_GPI0", "VX855_GPI1", "VX855_GPI2", "VX855_GPI3", "VX855_GPI4",
"VX855_GPI5", "VX855_GPI6", "VX855_GPI7", "VX855_GPI8", "VX855_GPI9",
"VX855_GPI10", "VX855_GPI11", "VX855_GPI12", "VX855_GPI13",
"VX855_GPO0", "VX855_GPO1", "VX855_GPO2", "VX855_GPO3", "VX855_GPO4",
"VX855_GPO5", "VX855_GPO6", "VX855_GPO7", "VX855_GPO8", "VX855_GPO9",
"VX855_GPO10", "VX855_GPO11", "VX855_GPO12",
"VX855_GPIO0", "VX855_GPIO1", "VX855_GPIO2", "VX855_GPIO3",
"VX855_GPIO4", "VX855_GPIO5", "VX855_GPIO6", "VX855_GPIO7",
"VX855_GPIO8", "VX855_GPIO9", "VX855_GPIO10", "VX855_GPIO11",
"VX855_GPIO12", "VX855_GPIO13", "VX855_GPIO14"
};
static void vx855gpio_gpio_setup(struct vx855_gpio *vg)
{
struct gpio_chip *c = &vg->gpio;
c->label = "VX855 South Bridge";
c->owner = THIS_MODULE;
c->direction_input = vx855gpio_direction_input;
c->direction_output = vx855gpio_direction_output;
c->get = vx855gpio_get;
c->set = vx855gpio_set;
c->set_config = vx855gpio_set_config;
c->dbg_show = NULL;
c->base = 0;
c->ngpio = NR_VX855_GP;
c->can_sleep = false;
c->names = vx855gpio_names;
}
/* This platform device is ordinarily registered by the vx855 mfd driver */
static int vx855gpio_probe(struct platform_device *pdev)
{
struct resource *res_gpi;
struct resource *res_gpo;
struct vx855_gpio *vg;
res_gpi = platform_get_resource(pdev, IORESOURCE_IO, 0);
res_gpo = platform_get_resource(pdev, IORESOURCE_IO, 1);
if (!res_gpi || !res_gpo)
return -EBUSY;
vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
if (!vg)
return -ENOMEM;
dev_info(&pdev->dev, "found VX855 GPIO controller\n");
vg->io_gpi = res_gpi->start;
vg->io_gpo = res_gpo->start;
spin_lock_init(&vg->lock);
/*
* A single byte is used to control various GPIO ports on the VX855,
* and in the case of the OLPC XO-1.5, some of those ports are used
* for switches that are interpreted and exposed through ACPI. ACPI
* will have reserved the region, so our own reservation will not
* succeed. Ignore and continue.
*/
if (!devm_request_region(&pdev->dev, res_gpi->start,
resource_size(res_gpi), MODULE_NAME "_gpi"))
dev_warn(&pdev->dev,
"GPI I/O resource busy, probably claimed by ACPI\n");
if (!devm_request_region(&pdev->dev, res_gpo->start,
resource_size(res_gpo), MODULE_NAME "_gpo"))
dev_warn(&pdev->dev,
"GPO I/O resource busy, probably claimed by ACPI\n");
vx855gpio_gpio_setup(vg);
return devm_gpiochip_add_data(&pdev->dev, &vg->gpio, vg);
}
static struct platform_driver vx855gpio_driver = {
.driver = {
.name = MODULE_NAME,
},
.probe = vx855gpio_probe,
};
module_platform_driver(vx855gpio_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Harald Welte <[email protected]>");
MODULE_DESCRIPTION("GPIO driver for the VIA VX855 chipset");
MODULE_ALIAS("platform:vx855_gpio");
| linux-master | drivers/gpio/gpio-vx855.c |
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2020 HiSilicon Limited. */
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#define HISI_GPIO_SWPORT_DR_SET_WX 0x000
#define HISI_GPIO_SWPORT_DR_CLR_WX 0x004
#define HISI_GPIO_SWPORT_DDR_SET_WX 0x010
#define HISI_GPIO_SWPORT_DDR_CLR_WX 0x014
#define HISI_GPIO_SWPORT_DDR_ST_WX 0x018
#define HISI_GPIO_INTEN_SET_WX 0x020
#define HISI_GPIO_INTEN_CLR_WX 0x024
#define HISI_GPIO_INTMASK_SET_WX 0x030
#define HISI_GPIO_INTMASK_CLR_WX 0x034
#define HISI_GPIO_INTTYPE_EDGE_SET_WX 0x040
#define HISI_GPIO_INTTYPE_EDGE_CLR_WX 0x044
#define HISI_GPIO_INT_POLARITY_SET_WX 0x050
#define HISI_GPIO_INT_POLARITY_CLR_WX 0x054
#define HISI_GPIO_DEBOUNCE_SET_WX 0x060
#define HISI_GPIO_DEBOUNCE_CLR_WX 0x064
#define HISI_GPIO_INTSTATUS_WX 0x070
#define HISI_GPIO_PORTA_EOI_WX 0x078
#define HISI_GPIO_EXT_PORT_WX 0x080
#define HISI_GPIO_INTCOMB_MASK_WX 0x0a0
#define HISI_GPIO_INT_DEDGE_SET 0x0b0
#define HISI_GPIO_INT_DEDGE_CLR 0x0b4
#define HISI_GPIO_INT_DEDGE_ST 0x0b8
#define HISI_GPIO_LINE_NUM_MAX 32
#define HISI_GPIO_DRIVER_NAME "gpio-hisi"
struct hisi_gpio {
struct gpio_chip chip;
struct device *dev;
void __iomem *reg_base;
unsigned int line_num;
int irq;
};
static inline u32 hisi_gpio_read_reg(struct gpio_chip *chip,
unsigned int off)
{
struct hisi_gpio *hisi_gpio =
container_of(chip, struct hisi_gpio, chip);
void __iomem *reg = hisi_gpio->reg_base + off;
return readl(reg);
}
static inline void hisi_gpio_write_reg(struct gpio_chip *chip,
unsigned int off, u32 val)
{
struct hisi_gpio *hisi_gpio =
container_of(chip, struct hisi_gpio, chip);
void __iomem *reg = hisi_gpio->reg_base + off;
writel(val, reg);
}
static void hisi_gpio_set_debounce(struct gpio_chip *chip, unsigned int off,
u32 debounce)
{
if (debounce)
hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_SET_WX, BIT(off));
else
hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_CLR_WX, BIT(off));
}
static int hisi_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
u32 config_para = pinconf_to_config_param(config);
u32 config_arg;
switch (config_para) {
case PIN_CONFIG_INPUT_DEBOUNCE:
config_arg = pinconf_to_config_argument(config);
hisi_gpio_set_debounce(chip, offset, config_arg);
break;
default:
return -ENOTSUPP;
}
return 0;
}
static void hisi_gpio_set_ack(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
hisi_gpio_write_reg(chip, HISI_GPIO_PORTA_EOI_WX, BIT(irqd_to_hwirq(d)));
}
static void hisi_gpio_irq_set_mask(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_SET_WX, BIT(irqd_to_hwirq(d)));
gpiochip_disable_irq(chip, irqd_to_hwirq(d));
}
static void hisi_gpio_irq_clr_mask(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
gpiochip_enable_irq(chip, irqd_to_hwirq(d));
hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_CLR_WX, BIT(irqd_to_hwirq(d)));
}
static int hisi_gpio_irq_set_type(struct irq_data *d, u32 type)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
unsigned int mask = BIT(irqd_to_hwirq(d));
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_SET, mask);
break;
case IRQ_TYPE_EDGE_RISING:
hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask);
hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask);
break;
case IRQ_TYPE_EDGE_FALLING:
hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask);
hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask);
break;
case IRQ_TYPE_LEVEL_HIGH:
hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask);
hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask);
break;
case IRQ_TYPE_LEVEL_LOW:
hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask);
hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask);
break;
default:
return -EINVAL;
}
/*
* The dual-edge interrupt and other interrupt's registers do not
* take effect at the same time. The registers of the two-edge
* interrupts have higher priorities, the configuration of
* the dual-edge interrupts must be disabled before the configuration
* of other kind of interrupts.
*/
if (type != IRQ_TYPE_EDGE_BOTH) {
unsigned int both = hisi_gpio_read_reg(chip, HISI_GPIO_INT_DEDGE_ST);
if (both & mask)
hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_CLR, mask);
}
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
else if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(d, handle_edge_irq);
return 0;
}
static void hisi_gpio_irq_enable(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
hisi_gpio_irq_clr_mask(d);
hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_SET_WX, BIT(irqd_to_hwirq(d)));
}
static void hisi_gpio_irq_disable(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
hisi_gpio_irq_set_mask(d);
hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_CLR_WX, BIT(irqd_to_hwirq(d)));
}
static void hisi_gpio_irq_handler(struct irq_desc *desc)
{
struct hisi_gpio *hisi_gpio = irq_desc_get_handler_data(desc);
unsigned long irq_msk = hisi_gpio_read_reg(&hisi_gpio->chip,
HISI_GPIO_INTSTATUS_WX);
struct irq_chip *irq_c = irq_desc_get_chip(desc);
int hwirq;
chained_irq_enter(irq_c, desc);
for_each_set_bit(hwirq, &irq_msk, HISI_GPIO_LINE_NUM_MAX)
generic_handle_domain_irq(hisi_gpio->chip.irq.domain,
hwirq);
chained_irq_exit(irq_c, desc);
}
static const struct irq_chip hisi_gpio_irq_chip = {
.name = "HISI-GPIO",
.irq_ack = hisi_gpio_set_ack,
.irq_mask = hisi_gpio_irq_set_mask,
.irq_unmask = hisi_gpio_irq_clr_mask,
.irq_set_type = hisi_gpio_irq_set_type,
.irq_enable = hisi_gpio_irq_enable,
.irq_disable = hisi_gpio_irq_disable,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void hisi_gpio_init_irq(struct hisi_gpio *hisi_gpio)
{
struct gpio_chip *chip = &hisi_gpio->chip;
struct gpio_irq_chip *girq_chip = &chip->irq;
gpio_irq_chip_set_chip(girq_chip, &hisi_gpio_irq_chip);
girq_chip->default_type = IRQ_TYPE_NONE;
girq_chip->num_parents = 1;
girq_chip->parents = &hisi_gpio->irq;
girq_chip->parent_handler = hisi_gpio_irq_handler;
girq_chip->parent_handler_data = hisi_gpio;
/* Clear Mask of GPIO controller combine IRQ */
hisi_gpio_write_reg(chip, HISI_GPIO_INTCOMB_MASK_WX, 1);
}
static const struct acpi_device_id hisi_gpio_acpi_match[] = {
{"HISI0184", 0},
{}
};
MODULE_DEVICE_TABLE(acpi, hisi_gpio_acpi_match);
static const struct of_device_id hisi_gpio_dts_match[] = {
{ .compatible = "hisilicon,ascend910-gpio", },
{ }
};
MODULE_DEVICE_TABLE(of, hisi_gpio_dts_match);
static void hisi_gpio_get_pdata(struct device *dev,
struct hisi_gpio *hisi_gpio)
{
struct platform_device *pdev = to_platform_device(dev);
struct fwnode_handle *fwnode;
int idx = 0;
device_for_each_child_node(dev, fwnode) {
/* Cycle for once, no need for an array to save line_num */
if (fwnode_property_read_u32(fwnode, "ngpios",
&hisi_gpio->line_num)) {
dev_err(dev,
"failed to get number of lines for port%d and use default value instead\n",
idx);
hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX;
}
if (WARN_ON(hisi_gpio->line_num > HISI_GPIO_LINE_NUM_MAX))
hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX;
hisi_gpio->irq = platform_get_irq(pdev, idx);
dev_info(dev,
"get hisi_gpio[%d] with %d lines\n", idx,
hisi_gpio->line_num);
idx++;
}
}
static int hisi_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct hisi_gpio *hisi_gpio;
int port_num;
int ret;
/*
* One GPIO controller own one port currently,
* if we get more from ACPI table, return error.
*/
port_num = device_get_child_node_count(dev);
if (WARN_ON(port_num != 1))
return -ENODEV;
hisi_gpio = devm_kzalloc(dev, sizeof(*hisi_gpio), GFP_KERNEL);
if (!hisi_gpio)
return -ENOMEM;
hisi_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(hisi_gpio->reg_base))
return PTR_ERR(hisi_gpio->reg_base);
hisi_gpio_get_pdata(dev, hisi_gpio);
hisi_gpio->dev = dev;
ret = bgpio_init(&hisi_gpio->chip, hisi_gpio->dev, 0x4,
hisi_gpio->reg_base + HISI_GPIO_EXT_PORT_WX,
hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_SET_WX,
hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_CLR_WX,
hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_SET_WX,
hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_CLR_WX,
BGPIOF_NO_SET_ON_INPUT);
if (ret) {
dev_err(dev, "failed to init, ret = %d\n", ret);
return ret;
}
hisi_gpio->chip.set_config = hisi_gpio_set_config;
hisi_gpio->chip.ngpio = hisi_gpio->line_num;
hisi_gpio->chip.bgpio_dir_unreadable = 1;
hisi_gpio->chip.base = -1;
if (hisi_gpio->irq > 0)
hisi_gpio_init_irq(hisi_gpio);
ret = devm_gpiochip_add_data(dev, &hisi_gpio->chip, hisi_gpio);
if (ret) {
dev_err(dev, "failed to register gpiochip, ret = %d\n", ret);
return ret;
}
return 0;
}
static struct platform_driver hisi_gpio_driver = {
.driver = {
.name = HISI_GPIO_DRIVER_NAME,
.acpi_match_table = hisi_gpio_acpi_match,
.of_match_table = hisi_gpio_dts_match,
},
.probe = hisi_gpio_probe,
};
module_platform_driver(hisi_gpio_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Luo Jiaxing <[email protected]>");
MODULE_DESCRIPTION("HiSilicon GPIO controller driver");
MODULE_ALIAS("platform:" HISI_GPIO_DRIVER_NAME);
| linux-master | drivers/gpio/gpio-hisi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* gpio-max3191x.c - GPIO driver for Maxim MAX3191x industrial serializer
*
* Copyright (C) 2017 KUNBUS GmbH
*
* The MAX3191x makes 8 digital 24V inputs available via SPI.
* Multiple chips can be daisy-chained, the spec does not impose
* a limit on the number of chips and neither does this driver.
*
* Either of two modes is selectable: In 8-bit mode, only the state
* of the inputs is clocked out to achieve high readout speeds;
* In 16-bit mode, an additional status byte is clocked out with
* a CRC and indicator bits for undervoltage and overtemperature.
* The driver returns an error instead of potentially bogus data
* if any of these fault conditions occur. However it does allow
* readout of non-faulting chips in the same daisy-chain.
*
* MAX3191x supports four debounce settings and the driver is
* capable of configuring these differently for each chip in the
* daisy-chain.
*
* If the chips are hardwired to 8-bit mode ("modesel" pulled high),
* gpio-pisosr.c can be used alternatively to this driver.
*
* https://datasheets.maximintegrated.com/en/ds/MAX31910.pdf
* https://datasheets.maximintegrated.com/en/ds/MAX31911.pdf
* https://datasheets.maximintegrated.com/en/ds/MAX31912.pdf
* https://datasheets.maximintegrated.com/en/ds/MAX31913.pdf
* https://datasheets.maximintegrated.com/en/ds/MAX31953-MAX31963.pdf
*/
#include <linux/bitmap.h>
#include <linux/bitops.h>
#include <linux/crc8.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
enum max3191x_mode {
STATUS_BYTE_ENABLED,
STATUS_BYTE_DISABLED,
};
/**
* struct max3191x_chip - max3191x daisy-chain
* @gpio: GPIO controller struct
* @lock: protects read sequences
* @nchips: number of chips in the daisy-chain
* @mode: current mode, 0 for 16-bit, 1 for 8-bit;
* for simplicity, all chips in the daisy-chain are assumed
* to use the same mode
* @modesel_pins: GPIO pins to configure modesel of each chip
* @fault_pins: GPIO pins to detect fault of each chip
* @db0_pins: GPIO pins to configure debounce of each chip
* @db1_pins: GPIO pins to configure debounce of each chip
* @mesg: SPI message to perform a readout
* @xfer: SPI transfer used by @mesg
* @crc_error: bitmap signaling CRC error for each chip
* @overtemp: bitmap signaling overtemperature alarm for each chip
* @undervolt1: bitmap signaling undervoltage alarm for each chip
* @undervolt2: bitmap signaling undervoltage warning for each chip
* @fault: bitmap signaling assertion of @fault_pins for each chip
* @ignore_uv: whether to ignore undervoltage alarms;
* set by a device property if the chips are powered through
* 5VOUT instead of VCC24V, in which case they will constantly
* signal undervoltage;
* for simplicity, all chips in the daisy-chain are assumed
* to be powered the same way
*/
struct max3191x_chip {
struct gpio_chip gpio;
struct mutex lock;
u32 nchips;
enum max3191x_mode mode;
struct gpio_descs *modesel_pins;
struct gpio_descs *fault_pins;
struct gpio_descs *db0_pins;
struct gpio_descs *db1_pins;
struct spi_message mesg;
struct spi_transfer xfer;
unsigned long *crc_error;
unsigned long *overtemp;
unsigned long *undervolt1;
unsigned long *undervolt2;
unsigned long *fault;
bool ignore_uv;
};
#define MAX3191X_NGPIO 8
#define MAX3191X_CRC8_POLYNOMIAL 0xa8 /* (x^5) + x^4 + x^2 + x^0 */
DECLARE_CRC8_TABLE(max3191x_crc8);
static int max3191x_get_direction(struct gpio_chip *gpio, unsigned int offset)
{
return GPIO_LINE_DIRECTION_IN; /* always in */
}
static int max3191x_direction_input(struct gpio_chip *gpio, unsigned int offset)
{
return 0;
}
static int max3191x_direction_output(struct gpio_chip *gpio,
unsigned int offset, int value)
{
return -EINVAL;
}
static void max3191x_set(struct gpio_chip *gpio, unsigned int offset, int value)
{ }
static void max3191x_set_multiple(struct gpio_chip *gpio, unsigned long *mask,
unsigned long *bits)
{ }
static unsigned int max3191x_wordlen(struct max3191x_chip *max3191x)
{
return max3191x->mode == STATUS_BYTE_ENABLED ? 2 : 1;
}
static int max3191x_readout_locked(struct max3191x_chip *max3191x)
{
struct device *dev = max3191x->gpio.parent;
struct spi_device *spi = to_spi_device(dev);
int val, i, ot = 0, uv1 = 0;
val = spi_sync(spi, &max3191x->mesg);
if (val) {
dev_err_ratelimited(dev, "SPI receive error %d\n", val);
return val;
}
for (i = 0; i < max3191x->nchips; i++) {
if (max3191x->mode == STATUS_BYTE_ENABLED) {
u8 in = ((u8 *)max3191x->xfer.rx_buf)[i * 2];
u8 status = ((u8 *)max3191x->xfer.rx_buf)[i * 2 + 1];
val = (status & 0xf8) != crc8(max3191x_crc8, &in, 1, 0);
__assign_bit(i, max3191x->crc_error, val);
if (val)
dev_err_ratelimited(dev,
"chip %d: CRC error\n", i);
ot = (status >> 1) & 1;
__assign_bit(i, max3191x->overtemp, ot);
if (ot)
dev_err_ratelimited(dev,
"chip %d: overtemperature\n", i);
if (!max3191x->ignore_uv) {
uv1 = !((status >> 2) & 1);
__assign_bit(i, max3191x->undervolt1, uv1);
if (uv1)
dev_err_ratelimited(dev,
"chip %d: undervoltage\n", i);
val = !(status & 1);
__assign_bit(i, max3191x->undervolt2, val);
if (val && !uv1)
dev_warn_ratelimited(dev,
"chip %d: voltage warn\n", i);
}
}
if (max3191x->fault_pins && !max3191x->ignore_uv) {
/* fault pin shared by all chips or per chip */
struct gpio_desc *fault_pin =
(max3191x->fault_pins->ndescs == 1)
? max3191x->fault_pins->desc[0]
: max3191x->fault_pins->desc[i];
val = gpiod_get_value_cansleep(fault_pin);
if (val < 0) {
dev_err_ratelimited(dev,
"GPIO read error %d\n", val);
return val;
}
__assign_bit(i, max3191x->fault, val);
if (val && !uv1 && !ot)
dev_err_ratelimited(dev,
"chip %d: fault\n", i);
}
}
return 0;
}
static bool max3191x_chip_is_faulting(struct max3191x_chip *max3191x,
unsigned int chipnum)
{
/* without status byte the only diagnostic is the fault pin */
if (!max3191x->ignore_uv && test_bit(chipnum, max3191x->fault))
return true;
if (max3191x->mode == STATUS_BYTE_DISABLED)
return false;
return test_bit(chipnum, max3191x->crc_error) ||
test_bit(chipnum, max3191x->overtemp) ||
(!max3191x->ignore_uv &&
test_bit(chipnum, max3191x->undervolt1));
}
static int max3191x_get(struct gpio_chip *gpio, unsigned int offset)
{
struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
int ret, chipnum, wordlen = max3191x_wordlen(max3191x);
u8 in;
mutex_lock(&max3191x->lock);
ret = max3191x_readout_locked(max3191x);
if (ret)
goto out_unlock;
chipnum = offset / MAX3191X_NGPIO;
if (max3191x_chip_is_faulting(max3191x, chipnum)) {
ret = -EIO;
goto out_unlock;
}
in = ((u8 *)max3191x->xfer.rx_buf)[chipnum * wordlen];
ret = (in >> (offset % MAX3191X_NGPIO)) & 1;
out_unlock:
mutex_unlock(&max3191x->lock);
return ret;
}
static int max3191x_get_multiple(struct gpio_chip *gpio, unsigned long *mask,
unsigned long *bits)
{
struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
const unsigned int wordlen = max3191x_wordlen(max3191x);
int ret;
unsigned long bit;
unsigned long gpio_mask;
unsigned long in;
mutex_lock(&max3191x->lock);
ret = max3191x_readout_locked(max3191x);
if (ret)
goto out_unlock;
bitmap_zero(bits, gpio->ngpio);
for_each_set_clump8(bit, gpio_mask, mask, gpio->ngpio) {
unsigned int chipnum = bit / MAX3191X_NGPIO;
if (max3191x_chip_is_faulting(max3191x, chipnum)) {
ret = -EIO;
goto out_unlock;
}
in = ((u8 *)max3191x->xfer.rx_buf)[chipnum * wordlen];
in &= gpio_mask;
bitmap_set_value8(bits, in, bit);
}
out_unlock:
mutex_unlock(&max3191x->lock);
return ret;
}
static int max3191x_set_config(struct gpio_chip *gpio, unsigned int offset,
unsigned long config)
{
struct max3191x_chip *max3191x = gpiochip_get_data(gpio);
u32 debounce, chipnum, db0_val, db1_val;
if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
return -ENOTSUPP;
if (!max3191x->db0_pins || !max3191x->db1_pins)
return -EINVAL;
debounce = pinconf_to_config_argument(config);
switch (debounce) {
case 0:
db0_val = 0;
db1_val = 0;
break;
case 1 ... 25:
db0_val = 0;
db1_val = 1;
break;
case 26 ... 750:
db0_val = 1;
db1_val = 0;
break;
case 751 ... 3000:
db0_val = 1;
db1_val = 1;
break;
default:
return -EINVAL;
}
if (max3191x->db0_pins->ndescs == 1)
chipnum = 0; /* all chips use the same pair of debounce pins */
else
chipnum = offset / MAX3191X_NGPIO; /* per chip debounce pins */
mutex_lock(&max3191x->lock);
gpiod_set_value_cansleep(max3191x->db0_pins->desc[chipnum], db0_val);
gpiod_set_value_cansleep(max3191x->db1_pins->desc[chipnum], db1_val);
mutex_unlock(&max3191x->lock);
return 0;
}
static void gpiod_set_array_single_value_cansleep(unsigned int ndescs,
struct gpio_desc **desc,
struct gpio_array *info,
int value)
{
unsigned long *values;
values = bitmap_alloc(ndescs, GFP_KERNEL);
if (!values)
return;
if (value)
bitmap_fill(values, ndescs);
else
bitmap_zero(values, ndescs);
gpiod_set_array_value_cansleep(ndescs, desc, info, values);
bitmap_free(values);
}
static struct gpio_descs *devm_gpiod_get_array_optional_count(
struct device *dev, const char *con_id,
enum gpiod_flags flags, unsigned int expected)
{
struct gpio_descs *descs;
int found = gpiod_count(dev, con_id);
if (found == -ENOENT)
return NULL;
if (found != expected && found != 1) {
dev_err(dev, "ignoring %s-gpios: found %d, expected %u or 1\n",
con_id, found, expected);
return NULL;
}
descs = devm_gpiod_get_array_optional(dev, con_id, flags);
if (IS_ERR(descs)) {
dev_err(dev, "failed to get %s-gpios: %ld\n",
con_id, PTR_ERR(descs));
return NULL;
}
return descs;
}
static int max3191x_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct max3191x_chip *max3191x;
int n, ret;
max3191x = devm_kzalloc(dev, sizeof(*max3191x), GFP_KERNEL);
if (!max3191x)
return -ENOMEM;
spi_set_drvdata(spi, max3191x);
max3191x->nchips = 1;
device_property_read_u32(dev, "#daisy-chained-devices",
&max3191x->nchips);
n = BITS_TO_LONGS(max3191x->nchips);
max3191x->crc_error = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
max3191x->undervolt1 = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
max3191x->undervolt2 = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
max3191x->overtemp = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
max3191x->fault = devm_kcalloc(dev, n, sizeof(long), GFP_KERNEL);
max3191x->xfer.rx_buf = devm_kcalloc(dev, max3191x->nchips,
2, GFP_KERNEL);
if (!max3191x->crc_error || !max3191x->undervolt1 ||
!max3191x->overtemp || !max3191x->undervolt2 ||
!max3191x->fault || !max3191x->xfer.rx_buf)
return -ENOMEM;
max3191x->modesel_pins = devm_gpiod_get_array_optional_count(dev,
"maxim,modesel", GPIOD_ASIS, max3191x->nchips);
max3191x->fault_pins = devm_gpiod_get_array_optional_count(dev,
"maxim,fault", GPIOD_IN, max3191x->nchips);
max3191x->db0_pins = devm_gpiod_get_array_optional_count(dev,
"maxim,db0", GPIOD_OUT_LOW, max3191x->nchips);
max3191x->db1_pins = devm_gpiod_get_array_optional_count(dev,
"maxim,db1", GPIOD_OUT_LOW, max3191x->nchips);
max3191x->mode = device_property_read_bool(dev, "maxim,modesel-8bit")
? STATUS_BYTE_DISABLED : STATUS_BYTE_ENABLED;
if (max3191x->modesel_pins)
gpiod_set_array_single_value_cansleep(
max3191x->modesel_pins->ndescs,
max3191x->modesel_pins->desc,
max3191x->modesel_pins->info, max3191x->mode);
max3191x->ignore_uv = device_property_read_bool(dev,
"maxim,ignore-undervoltage");
if (max3191x->db0_pins && max3191x->db1_pins &&
max3191x->db0_pins->ndescs != max3191x->db1_pins->ndescs) {
dev_err(dev, "ignoring maxim,db*-gpios: array len mismatch\n");
devm_gpiod_put_array(dev, max3191x->db0_pins);
devm_gpiod_put_array(dev, max3191x->db1_pins);
max3191x->db0_pins = NULL;
max3191x->db1_pins = NULL;
}
max3191x->xfer.len = max3191x->nchips * max3191x_wordlen(max3191x);
spi_message_init_with_transfers(&max3191x->mesg, &max3191x->xfer, 1);
max3191x->gpio.label = spi->modalias;
max3191x->gpio.owner = THIS_MODULE;
max3191x->gpio.parent = dev;
max3191x->gpio.base = -1;
max3191x->gpio.ngpio = max3191x->nchips * MAX3191X_NGPIO;
max3191x->gpio.can_sleep = true;
max3191x->gpio.get_direction = max3191x_get_direction;
max3191x->gpio.direction_input = max3191x_direction_input;
max3191x->gpio.direction_output = max3191x_direction_output;
max3191x->gpio.set = max3191x_set;
max3191x->gpio.set_multiple = max3191x_set_multiple;
max3191x->gpio.get = max3191x_get;
max3191x->gpio.get_multiple = max3191x_get_multiple;
max3191x->gpio.set_config = max3191x_set_config;
mutex_init(&max3191x->lock);
ret = gpiochip_add_data(&max3191x->gpio, max3191x);
if (ret) {
mutex_destroy(&max3191x->lock);
return ret;
}
return 0;
}
static void max3191x_remove(struct spi_device *spi)
{
struct max3191x_chip *max3191x = spi_get_drvdata(spi);
gpiochip_remove(&max3191x->gpio);
mutex_destroy(&max3191x->lock);
}
static int __init max3191x_register_driver(struct spi_driver *sdrv)
{
crc8_populate_msb(max3191x_crc8, MAX3191X_CRC8_POLYNOMIAL);
return spi_register_driver(sdrv);
}
static const struct of_device_id max3191x_of_id[] = {
{ .compatible = "maxim,max31910" },
{ .compatible = "maxim,max31911" },
{ .compatible = "maxim,max31912" },
{ .compatible = "maxim,max31913" },
{ .compatible = "maxim,max31953" },
{ .compatible = "maxim,max31963" },
{ }
};
MODULE_DEVICE_TABLE(of, max3191x_of_id);
static const struct spi_device_id max3191x_spi_id[] = {
{ "max31910" },
{ "max31911" },
{ "max31912" },
{ "max31913" },
{ "max31953" },
{ "max31963" },
{ }
};
MODULE_DEVICE_TABLE(spi, max3191x_spi_id);
static struct spi_driver max3191x_driver = {
.driver = {
.name = "max3191x",
.of_match_table = max3191x_of_id,
},
.probe = max3191x_probe,
.remove = max3191x_remove,
.id_table = max3191x_spi_id,
};
module_driver(max3191x_driver, max3191x_register_driver, spi_unregister_driver);
MODULE_AUTHOR("Lukas Wunner <[email protected]>");
MODULE_DESCRIPTION("GPIO driver for Maxim MAX3191x industrial serializer");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-max3191x.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Synopsys CREG (Control REGisters) GPIO driver
//
// Copyright (C) 2018 Synopsys
// Author: Eugeniy Paltsev <[email protected]>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#define MAX_GPIO 32
struct creg_layout {
u8 ngpio;
u8 shift[MAX_GPIO];
u8 on[MAX_GPIO];
u8 off[MAX_GPIO];
u8 bit_per_gpio[MAX_GPIO];
};
struct creg_gpio {
struct gpio_chip gc;
void __iomem *regs;
spinlock_t lock;
const struct creg_layout *layout;
};
static void creg_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
{
struct creg_gpio *hcg = gpiochip_get_data(gc);
const struct creg_layout *layout = hcg->layout;
u32 reg, reg_shift, value;
unsigned long flags;
int i;
value = val ? hcg->layout->on[offset] : hcg->layout->off[offset];
reg_shift = layout->shift[offset];
for (i = 0; i < offset; i++)
reg_shift += layout->bit_per_gpio[i] + layout->shift[i];
spin_lock_irqsave(&hcg->lock, flags);
reg = readl(hcg->regs);
reg &= ~(GENMASK(layout->bit_per_gpio[i] - 1, 0) << reg_shift);
reg |= (value << reg_shift);
writel(reg, hcg->regs);
spin_unlock_irqrestore(&hcg->lock, flags);
}
static int creg_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
{
creg_gpio_set(gc, offset, val);
return 0;
}
static int creg_gpio_validate_pg(struct device *dev, struct creg_gpio *hcg,
int i)
{
const struct creg_layout *layout = hcg->layout;
if (layout->bit_per_gpio[i] < 1 || layout->bit_per_gpio[i] > 8)
return -EINVAL;
/* Check that on value fits its placeholder */
if (GENMASK(31, layout->bit_per_gpio[i]) & layout->on[i])
return -EINVAL;
/* Check that off value fits its placeholder */
if (GENMASK(31, layout->bit_per_gpio[i]) & layout->off[i])
return -EINVAL;
if (layout->on[i] == layout->off[i])
return -EINVAL;
return 0;
}
static int creg_gpio_validate(struct device *dev, struct creg_gpio *hcg,
u32 ngpios)
{
u32 reg_len = 0;
int i;
if (hcg->layout->ngpio < 1 || hcg->layout->ngpio > MAX_GPIO)
return -EINVAL;
if (ngpios < 1 || ngpios > hcg->layout->ngpio) {
dev_err(dev, "ngpios must be in [1:%u]\n", hcg->layout->ngpio);
return -EINVAL;
}
for (i = 0; i < hcg->layout->ngpio; i++) {
if (creg_gpio_validate_pg(dev, hcg, i))
return -EINVAL;
reg_len += hcg->layout->shift[i] + hcg->layout->bit_per_gpio[i];
}
/* Check that we fit in 32 bit register */
if (reg_len > 32)
return -EINVAL;
return 0;
}
static const struct creg_layout hsdk_cs_ctl = {
.ngpio = 10,
.shift = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
.off = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 },
.on = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
.bit_per_gpio = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 }
};
static const struct creg_layout axs10x_flsh_cs_ctl = {
.ngpio = 1,
.shift = { 0 },
.off = { 1 },
.on = { 3 },
.bit_per_gpio = { 2 }
};
static const struct of_device_id creg_gpio_ids[] = {
{
.compatible = "snps,creg-gpio-axs10x",
.data = &axs10x_flsh_cs_ctl
}, {
.compatible = "snps,creg-gpio-hsdk",
.data = &hsdk_cs_ctl
}, { /* sentinel */ }
};
static int creg_gpio_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct device *dev = &pdev->dev;
struct creg_gpio *hcg;
u32 ngpios;
int ret;
hcg = devm_kzalloc(dev, sizeof(struct creg_gpio), GFP_KERNEL);
if (!hcg)
return -ENOMEM;
hcg->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(hcg->regs))
return PTR_ERR(hcg->regs);
match = of_match_node(creg_gpio_ids, pdev->dev.of_node);
hcg->layout = match->data;
if (!hcg->layout)
return -EINVAL;
ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
if (ret)
return ret;
ret = creg_gpio_validate(dev, hcg, ngpios);
if (ret)
return ret;
spin_lock_init(&hcg->lock);
hcg->gc.parent = dev;
hcg->gc.label = dev_name(dev);
hcg->gc.base = -1;
hcg->gc.ngpio = ngpios;
hcg->gc.set = creg_gpio_set;
hcg->gc.direction_output = creg_gpio_dir_out;
ret = devm_gpiochip_add_data(dev, &hcg->gc, hcg);
if (ret)
return ret;
dev_info(dev, "GPIO controller with %d gpios probed\n", ngpios);
return 0;
}
static struct platform_driver creg_gpio_snps_driver = {
.driver = {
.name = "snps-creg-gpio",
.of_match_table = creg_gpio_ids,
},
.probe = creg_gpio_probe,
};
builtin_platform_driver(creg_gpio_snps_driver);
| linux-master | drivers/gpio/gpio-creg-snps.c |
// SPDX-License-Identifier: GPL-2.0
/*
* GPIO driver for TI TPS65912x PMICs
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
* Andrew F. Davis <[email protected]>
*
* Based on the Arizona GPIO driver and the previous TPS65912 driver by
* Margarita Olaya Cabrera <[email protected]>
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/tps65912.h>
struct tps65912_gpio {
struct gpio_chip gpio_chip;
struct tps65912 *tps;
};
static int tps65912_gpio_get_direction(struct gpio_chip *gc,
unsigned offset)
{
struct tps65912_gpio *gpio = gpiochip_get_data(gc);
int ret, val;
ret = regmap_read(gpio->tps->regmap, TPS65912_GPIO1 + offset, &val);
if (ret)
return ret;
if (val & GPIO_CFG_MASK)
return GPIO_LINE_DIRECTION_OUT;
else
return GPIO_LINE_DIRECTION_IN;
}
static int tps65912_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct tps65912_gpio *gpio = gpiochip_get_data(gc);
return regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset,
GPIO_CFG_MASK, 0);
}
static int tps65912_gpio_direction_output(struct gpio_chip *gc,
unsigned offset, int value)
{
struct tps65912_gpio *gpio = gpiochip_get_data(gc);
/* Set the initial value */
regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset,
GPIO_SET_MASK, value ? GPIO_SET_MASK : 0);
return regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset,
GPIO_CFG_MASK, GPIO_CFG_MASK);
}
static int tps65912_gpio_get(struct gpio_chip *gc, unsigned offset)
{
struct tps65912_gpio *gpio = gpiochip_get_data(gc);
int ret, val;
ret = regmap_read(gpio->tps->regmap, TPS65912_GPIO1 + offset, &val);
if (ret)
return ret;
if (val & GPIO_STS_MASK)
return 1;
return 0;
}
static void tps65912_gpio_set(struct gpio_chip *gc, unsigned offset,
int value)
{
struct tps65912_gpio *gpio = gpiochip_get_data(gc);
regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset,
GPIO_SET_MASK, value ? GPIO_SET_MASK : 0);
}
static const struct gpio_chip template_chip = {
.label = "tps65912-gpio",
.owner = THIS_MODULE,
.get_direction = tps65912_gpio_get_direction,
.direction_input = tps65912_gpio_direction_input,
.direction_output = tps65912_gpio_direction_output,
.get = tps65912_gpio_get,
.set = tps65912_gpio_set,
.base = -1,
.ngpio = 5,
.can_sleep = true,
};
static int tps65912_gpio_probe(struct platform_device *pdev)
{
struct tps65912 *tps = dev_get_drvdata(pdev->dev.parent);
struct tps65912_gpio *gpio;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
gpio->tps = dev_get_drvdata(pdev->dev.parent);
gpio->gpio_chip = template_chip;
gpio->gpio_chip.parent = tps->dev;
return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio_chip, gpio);
}
static const struct platform_device_id tps65912_gpio_id_table[] = {
{ "tps65912-gpio", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, tps65912_gpio_id_table);
static struct platform_driver tps65912_gpio_driver = {
.driver = {
.name = "tps65912-gpio",
},
.probe = tps65912_gpio_probe,
.id_table = tps65912_gpio_id_table,
};
module_platform_driver(tps65912_gpio_driver);
MODULE_AUTHOR("Andrew F. Davis <[email protected]>");
MODULE_DESCRIPTION("TPS65912 GPIO driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-tps65912.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* 74xx MMIO GPIO driver
*
* Copyright (C) 2014 Alexander Shiyan <[email protected]>
*/
#include <linux/bits.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#define MMIO_74XX_DIR_IN BIT(8)
#define MMIO_74XX_DIR_OUT BIT(9)
#define MMIO_74XX_BIT_CNT(x) ((x) & GENMASK(7, 0))
struct mmio_74xx_gpio_priv {
struct gpio_chip gc;
unsigned flags;
};
static const struct of_device_id mmio_74xx_gpio_ids[] = {
{
.compatible = "ti,741g125",
.data = (const void *)(MMIO_74XX_DIR_IN | 1),
},
{
.compatible = "ti,742g125",
.data = (const void *)(MMIO_74XX_DIR_IN | 2),
},
{
.compatible = "ti,74125",
.data = (const void *)(MMIO_74XX_DIR_IN | 4),
},
{
.compatible = "ti,74365",
.data = (const void *)(MMIO_74XX_DIR_IN | 6),
},
{
.compatible = "ti,74244",
.data = (const void *)(MMIO_74XX_DIR_IN | 8),
},
{
.compatible = "ti,741624",
.data = (const void *)(MMIO_74XX_DIR_IN | 16),
},
{
.compatible = "ti,741g74",
.data = (const void *)(MMIO_74XX_DIR_OUT | 1),
},
{
.compatible = "ti,7474",
.data = (const void *)(MMIO_74XX_DIR_OUT | 2),
},
{
.compatible = "ti,74175",
.data = (const void *)(MMIO_74XX_DIR_OUT | 4),
},
{
.compatible = "ti,74174",
.data = (const void *)(MMIO_74XX_DIR_OUT | 6),
},
{
.compatible = "ti,74273",
.data = (const void *)(MMIO_74XX_DIR_OUT | 8),
},
{
.compatible = "ti,7416374",
.data = (const void *)(MMIO_74XX_DIR_OUT | 16),
},
{ }
};
MODULE_DEVICE_TABLE(of, mmio_74xx_gpio_ids);
static int mmio_74xx_get_direction(struct gpio_chip *gc, unsigned offset)
{
struct mmio_74xx_gpio_priv *priv = gpiochip_get_data(gc);
if (priv->flags & MMIO_74XX_DIR_OUT)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int mmio_74xx_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct mmio_74xx_gpio_priv *priv = gpiochip_get_data(gc);
if (priv->flags & MMIO_74XX_DIR_IN)
return 0;
return -ENOTSUPP;
}
static int mmio_74xx_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct mmio_74xx_gpio_priv *priv = gpiochip_get_data(gc);
if (priv->flags & MMIO_74XX_DIR_OUT) {
gc->set(gc, gpio, val);
return 0;
}
return -ENOTSUPP;
}
static int mmio_74xx_gpio_probe(struct platform_device *pdev)
{
struct mmio_74xx_gpio_priv *priv;
void __iomem *dat;
int err;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->flags = (uintptr_t)device_get_match_data(&pdev->dev);
dat = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dat))
return PTR_ERR(dat);
err = bgpio_init(&priv->gc, &pdev->dev,
DIV_ROUND_UP(MMIO_74XX_BIT_CNT(priv->flags), 8),
dat, NULL, NULL, NULL, NULL, 0);
if (err)
return err;
priv->gc.direction_input = mmio_74xx_dir_in;
priv->gc.direction_output = mmio_74xx_dir_out;
priv->gc.get_direction = mmio_74xx_get_direction;
priv->gc.ngpio = MMIO_74XX_BIT_CNT(priv->flags);
priv->gc.owner = THIS_MODULE;
return devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
}
static struct platform_driver mmio_74xx_gpio_driver = {
.driver = {
.name = "74xx-mmio-gpio",
.of_match_table = mmio_74xx_gpio_ids,
},
.probe = mmio_74xx_gpio_probe,
};
module_platform_driver(mmio_74xx_gpio_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Alexander Shiyan <[email protected]>");
MODULE_DESCRIPTION("74xx MMIO GPIO driver");
| linux-master | drivers/gpio/gpio-74xx-mmio.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Whiskey Cove PMIC GPIO Driver
*
* This driver is written based on gpio-crystalcove.c
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*/
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
/*
* Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
* Bank 0: Pin 0 - 6
* Bank 1: Pin 7 - 10
* Bank 2: Pin 11 - 12
* Each pin has one output control register and one input control register.
*/
#define BANK0_NR_PINS 7
#define BANK1_NR_PINS 4
#define BANK2_NR_PINS 2
#define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
#define WCOVE_VGPIO_NUM 94
/* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
#define GPIO_OUT_CTRL_BASE 0x4e44
/* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
#define GPIO_IN_CTRL_BASE 0x4e51
/*
* GPIO interrupts are organized in two groups:
* Group 0: Bank 0 pins (Pin 0 - 6)
* Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
* Each group has two registers (one bit per pin): status and mask.
*/
#define GROUP0_NR_IRQS 7
#define GROUP1_NR_IRQS 6
#define IRQ_MASK_BASE 0x4e19
#define IRQ_STATUS_BASE 0x4e0b
#define GPIO_IRQ0_MASK GENMASK(6, 0)
#define GPIO_IRQ1_MASK GENMASK(5, 0)
#define UPDATE_IRQ_TYPE BIT(0)
#define UPDATE_IRQ_MASK BIT(1)
#define CTLI_INTCNT_DIS (0 << 1)
#define CTLI_INTCNT_NE (1 << 1)
#define CTLI_INTCNT_PE (2 << 1)
#define CTLI_INTCNT_BE (3 << 1)
#define CTLO_DIR_IN (0 << 5)
#define CTLO_DIR_OUT (1 << 5)
#define CTLO_DRV_MASK (1 << 4)
#define CTLO_DRV_OD (0 << 4)
#define CTLO_DRV_CMOS (1 << 4)
#define CTLO_DRV_REN (1 << 3)
#define CTLO_RVAL_2KDOWN (0 << 1)
#define CTLO_RVAL_2KUP (1 << 1)
#define CTLO_RVAL_50KDOWN (2 << 1)
#define CTLO_RVAL_50KUP (3 << 1)
#define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
#define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
enum ctrl_register {
CTRL_IN,
CTRL_OUT,
IRQ_STATUS,
IRQ_MASK,
};
/*
* struct wcove_gpio - Whiskey Cove GPIO controller
* @buslock: for bus lock/sync and unlock.
* @chip: the abstract gpio_chip structure.
* @dev: the gpio device
* @regmap: the regmap from the parent device.
* @regmap_irq_chip: the regmap of the gpio irq chip.
* @update: pending IRQ setting update, to be written to the chip upon unlock.
* @intcnt: the Interrupt Detect value to be written.
* @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
*/
struct wcove_gpio {
struct mutex buslock;
struct gpio_chip chip;
struct device *dev;
struct regmap *regmap;
struct regmap_irq_chip_data *regmap_irq_chip;
int update;
int intcnt;
bool set_irq_mask;
};
static inline int to_reg(int gpio, enum ctrl_register type)
{
unsigned int reg = type == CTRL_IN ? GPIO_IN_CTRL_BASE : GPIO_OUT_CTRL_BASE;
if (gpio >= WCOVE_GPIO_NUM)
return -EOPNOTSUPP;
return reg + gpio;
}
static inline int to_ireg(int gpio, enum ctrl_register type, unsigned int *mask)
{
unsigned int reg = type == IRQ_STATUS ? IRQ_STATUS_BASE : IRQ_MASK_BASE;
if (gpio < GROUP0_NR_IRQS) {
reg += 0;
*mask = BIT(gpio);
} else {
reg += 1;
*mask = BIT(gpio - GROUP0_NR_IRQS);
}
return reg;
}
static void wcove_update_irq_mask(struct wcove_gpio *wg, irq_hw_number_t gpio)
{
unsigned int mask, reg = to_ireg(gpio, IRQ_MASK, &mask);
if (wg->set_irq_mask)
regmap_set_bits(wg->regmap, reg, mask);
else
regmap_clear_bits(wg->regmap, reg, mask);
}
static void wcove_update_irq_ctrl(struct wcove_gpio *wg, irq_hw_number_t gpio)
{
int reg = to_reg(gpio, CTRL_IN);
regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
}
static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
{
struct wcove_gpio *wg = gpiochip_get_data(chip);
int reg = to_reg(gpio, CTRL_OUT);
if (reg < 0)
return 0;
return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
}
static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
int value)
{
struct wcove_gpio *wg = gpiochip_get_data(chip);
int reg = to_reg(gpio, CTRL_OUT);
if (reg < 0)
return 0;
return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
}
static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
{
struct wcove_gpio *wg = gpiochip_get_data(chip);
unsigned int val;
int ret, reg = to_reg(gpio, CTRL_OUT);
if (reg < 0)
return GPIO_LINE_DIRECTION_OUT;
ret = regmap_read(wg->regmap, reg, &val);
if (ret)
return ret;
if (val & CTLO_DIR_OUT)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
struct wcove_gpio *wg = gpiochip_get_data(chip);
unsigned int val;
int ret, reg = to_reg(gpio, CTRL_IN);
if (reg < 0)
return 0;
ret = regmap_read(wg->regmap, reg, &val);
if (ret)
return ret;
return val & 0x1;
}
static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct wcove_gpio *wg = gpiochip_get_data(chip);
int reg = to_reg(gpio, CTRL_OUT);
if (reg < 0)
return;
if (value)
regmap_set_bits(wg->regmap, reg, 1);
else
regmap_clear_bits(wg->regmap, reg, 1);
}
static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
unsigned long config)
{
struct wcove_gpio *wg = gpiochip_get_data(chip);
int reg = to_reg(gpio, CTRL_OUT);
if (reg < 0)
return 0;
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
CTLO_DRV_OD);
case PIN_CONFIG_DRIVE_PUSH_PULL:
return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
CTLO_DRV_CMOS);
default:
break;
}
return -ENOTSUPP;
}
static int wcove_irq_type(struct irq_data *data, unsigned int type)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct wcove_gpio *wg = gpiochip_get_data(chip);
irq_hw_number_t gpio = irqd_to_hwirq(data);
if (gpio >= WCOVE_GPIO_NUM)
return 0;
switch (type) {
case IRQ_TYPE_NONE:
wg->intcnt = CTLI_INTCNT_DIS;
break;
case IRQ_TYPE_EDGE_BOTH:
wg->intcnt = CTLI_INTCNT_BE;
break;
case IRQ_TYPE_EDGE_RISING:
wg->intcnt = CTLI_INTCNT_PE;
break;
case IRQ_TYPE_EDGE_FALLING:
wg->intcnt = CTLI_INTCNT_NE;
break;
default:
return -EINVAL;
}
wg->update |= UPDATE_IRQ_TYPE;
return 0;
}
static void wcove_bus_lock(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct wcove_gpio *wg = gpiochip_get_data(chip);
mutex_lock(&wg->buslock);
}
static void wcove_bus_sync_unlock(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct wcove_gpio *wg = gpiochip_get_data(chip);
irq_hw_number_t gpio = irqd_to_hwirq(data);
if (wg->update & UPDATE_IRQ_TYPE)
wcove_update_irq_ctrl(wg, gpio);
if (wg->update & UPDATE_IRQ_MASK)
wcove_update_irq_mask(wg, gpio);
wg->update = 0;
mutex_unlock(&wg->buslock);
}
static void wcove_irq_unmask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct wcove_gpio *wg = gpiochip_get_data(chip);
irq_hw_number_t gpio = irqd_to_hwirq(data);
if (gpio >= WCOVE_GPIO_NUM)
return;
gpiochip_enable_irq(chip, gpio);
wg->set_irq_mask = false;
wg->update |= UPDATE_IRQ_MASK;
}
static void wcove_irq_mask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct wcove_gpio *wg = gpiochip_get_data(chip);
irq_hw_number_t gpio = irqd_to_hwirq(data);
if (gpio >= WCOVE_GPIO_NUM)
return;
wg->set_irq_mask = true;
wg->update |= UPDATE_IRQ_MASK;
gpiochip_disable_irq(chip, gpio);
}
static const struct irq_chip wcove_irqchip = {
.name = "Whiskey Cove",
.irq_mask = wcove_irq_mask,
.irq_unmask = wcove_irq_unmask,
.irq_set_type = wcove_irq_type,
.irq_bus_lock = wcove_bus_lock,
.irq_bus_sync_unlock = wcove_bus_sync_unlock,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
{
struct wcove_gpio *wg = (struct wcove_gpio *)data;
unsigned int virq, gpio;
unsigned long pending;
u8 p[2];
if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
dev_err(wg->dev, "Failed to read irq status register\n");
return IRQ_NONE;
}
pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
if (!pending)
return IRQ_NONE;
/* Iterate until no interrupt is pending */
while (pending) {
/* One iteration is for all pending bits */
for_each_set_bit(gpio, &pending, WCOVE_GPIO_NUM) {
unsigned int mask, reg = to_ireg(gpio, IRQ_STATUS, &mask);
virq = irq_find_mapping(wg->chip.irq.domain, gpio);
handle_nested_irq(virq);
regmap_set_bits(wg->regmap, reg, mask);
}
/* Next iteration */
if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
dev_err(wg->dev, "Failed to read irq status\n");
break;
}
pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
}
return IRQ_HANDLED;
}
static void wcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
unsigned int ctlo, ctli, irq_mask, irq_status;
struct wcove_gpio *wg = gpiochip_get_data(chip);
int gpio, mask, ret = 0;
for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
if (ret) {
dev_err(wg->dev, "Failed to read registers: CTRL out/in\n");
break;
}
ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_MASK, &mask), &irq_mask);
ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_STATUS, &mask), &irq_status);
if (ret) {
dev_err(wg->dev, "Failed to read registers: IRQ status/mask\n");
break;
}
seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
ctli & 0x1 ? "hi" : "lo",
ctli & CTLI_INTCNT_NE ? "fall" : " ",
ctli & CTLI_INTCNT_PE ? "rise" : " ",
ctlo,
irq_mask & mask ? "mask " : "unmask",
irq_status & mask ? "pending" : " ");
}
}
static int wcove_gpio_probe(struct platform_device *pdev)
{
struct intel_soc_pmic *pmic;
struct wcove_gpio *wg;
int virq, ret, irq;
struct device *dev;
struct gpio_irq_chip *girq;
/*
* This gpio platform device is created by a mfd device (see
* drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
* shared by all sub-devices created by the mfd device, the regmap
* pointer for instance, is stored as driver data of the mfd device
* driver.
*/
pmic = dev_get_drvdata(pdev->dev.parent);
if (!pmic)
return -ENODEV;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
dev = &pdev->dev;
wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
if (!wg)
return -ENOMEM;
wg->regmap_irq_chip = pmic->irq_chip_data;
platform_set_drvdata(pdev, wg);
mutex_init(&wg->buslock);
wg->chip.label = KBUILD_MODNAME;
wg->chip.direction_input = wcove_gpio_dir_in;
wg->chip.direction_output = wcove_gpio_dir_out;
wg->chip.get_direction = wcove_gpio_get_direction;
wg->chip.get = wcove_gpio_get;
wg->chip.set = wcove_gpio_set;
wg->chip.set_config = wcove_gpio_set_config;
wg->chip.base = -1;
wg->chip.ngpio = WCOVE_VGPIO_NUM;
wg->chip.can_sleep = true;
wg->chip.parent = pdev->dev.parent;
wg->chip.dbg_show = wcove_gpio_dbg_show;
wg->dev = dev;
wg->regmap = pmic->regmap;
virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
if (virq < 0) {
dev_err(dev, "Failed to get virq by irq %d\n", irq);
return virq;
}
girq = &wg->chip.irq;
gpio_irq_chip_set_chip(girq, &wcove_irqchip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
girq->threaded = true;
ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler,
IRQF_ONESHOT, pdev->name, wg);
if (ret) {
dev_err(dev, "Failed to request irq %d\n", virq);
return ret;
}
ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
if (ret) {
dev_err(dev, "Failed to add gpiochip: %d\n", ret);
return ret;
}
/* Enable GPIO0 interrupts */
ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 0, GPIO_IRQ0_MASK);
if (ret)
return ret;
/* Enable GPIO1 interrupts */
ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK);
if (ret)
return ret;
return 0;
}
/*
* Whiskey Cove PMIC itself is a analog device(but with digital control
* interface) providing power management support for other devices in
* the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
*/
static struct platform_driver wcove_gpio_driver = {
.driver = {
.name = "bxt_wcove_gpio",
},
.probe = wcove_gpio_probe,
};
module_platform_driver(wcove_gpio_driver);
MODULE_AUTHOR("Ajay Thomas <[email protected]>");
MODULE_AUTHOR("Bin Gao <[email protected]>");
MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:bxt_wcove_gpio");
| linux-master | drivers/gpio/gpio-wcove.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015-2023 Texas Instruments Incorporated - https://www.ti.com/
* Andrew Davis <[email protected]>
*/
#include <linux/gpio/driver.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/mutex.h>
#define TPIC2810_WS_COMMAND 0x44
/**
* struct tpic2810 - GPIO driver data
* @chip: GPIO controller chip
* @client: I2C device pointer
* @buffer: Buffer for device register
* @lock: Protects write sequences
*/
struct tpic2810 {
struct gpio_chip chip;
struct i2c_client *client;
u8 buffer;
struct mutex lock;
};
static void tpic2810_set(struct gpio_chip *chip, unsigned offset, int value);
static int tpic2810_get_direction(struct gpio_chip *chip,
unsigned offset)
{
/* This device always output */
return GPIO_LINE_DIRECTION_OUT;
}
static int tpic2810_direction_input(struct gpio_chip *chip,
unsigned offset)
{
/* This device is output only */
return -EINVAL;
}
static int tpic2810_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
/* This device always output */
tpic2810_set(chip, offset, value);
return 0;
}
static void tpic2810_set_mask_bits(struct gpio_chip *chip, u8 mask, u8 bits)
{
struct tpic2810 *gpio = gpiochip_get_data(chip);
u8 buffer;
int err;
mutex_lock(&gpio->lock);
buffer = gpio->buffer & ~mask;
buffer |= (mask & bits);
err = i2c_smbus_write_byte_data(gpio->client, TPIC2810_WS_COMMAND,
buffer);
if (!err)
gpio->buffer = buffer;
mutex_unlock(&gpio->lock);
}
static void tpic2810_set(struct gpio_chip *chip, unsigned offset, int value)
{
tpic2810_set_mask_bits(chip, BIT(offset), value ? BIT(offset) : 0);
}
static void tpic2810_set_multiple(struct gpio_chip *chip, unsigned long *mask,
unsigned long *bits)
{
tpic2810_set_mask_bits(chip, *mask, *bits);
}
static const struct gpio_chip template_chip = {
.label = "tpic2810",
.owner = THIS_MODULE,
.get_direction = tpic2810_get_direction,
.direction_input = tpic2810_direction_input,
.direction_output = tpic2810_direction_output,
.set = tpic2810_set,
.set_multiple = tpic2810_set_multiple,
.base = -1,
.ngpio = 8,
.can_sleep = true,
};
static const struct of_device_id tpic2810_of_match_table[] = {
{ .compatible = "ti,tpic2810" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, tpic2810_of_match_table);
static int tpic2810_probe(struct i2c_client *client)
{
struct tpic2810 *gpio;
gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
gpio->chip = template_chip;
gpio->chip.parent = &client->dev;
gpio->client = client;
mutex_init(&gpio->lock);
return devm_gpiochip_add_data(&client->dev, &gpio->chip, gpio);
}
static const struct i2c_device_id tpic2810_id_table[] = {
{ "tpic2810", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(i2c, tpic2810_id_table);
static struct i2c_driver tpic2810_driver = {
.driver = {
.name = "tpic2810",
.of_match_table = tpic2810_of_match_table,
},
.probe = tpic2810_probe,
.id_table = tpic2810_id_table,
};
module_i2c_driver(tpic2810_driver);
MODULE_AUTHOR("Andrew Davis <[email protected]>");
MODULE_DESCRIPTION("TPIC2810 8-Bit LED Driver GPIO Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-tpic2810.c |
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2011, 2012 Cavium Inc.
*/
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-gpio-defs.h>
#define RX_DAT 0x80
#define TX_SET 0x88
#define TX_CLEAR 0x90
/*
* The address offset of the GPIO configuration register for a given
* line.
*/
static unsigned int bit_cfg_reg(unsigned int offset)
{
/*
* The register stride is 8, with a discontinuity after the
* first 16.
*/
if (offset < 16)
return 8 * offset;
else
return 8 * (offset - 16) + 0x100;
}
struct octeon_gpio {
struct gpio_chip chip;
u64 register_base;
};
static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
{
struct octeon_gpio *gpio = gpiochip_get_data(chip);
cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
return 0;
}
static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct octeon_gpio *gpio = gpiochip_get_data(chip);
u64 mask = 1ull << offset;
u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
cvmx_write_csr(reg, mask);
}
static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
int value)
{
struct octeon_gpio *gpio = gpiochip_get_data(chip);
union cvmx_gpio_bit_cfgx cfgx;
octeon_gpio_set(chip, offset, value);
cfgx.u64 = 0;
cfgx.s.tx_oe = 1;
cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
return 0;
}
static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct octeon_gpio *gpio = gpiochip_get_data(chip);
u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
return ((1ull << offset) & read_bits) != 0;
}
static int octeon_gpio_probe(struct platform_device *pdev)
{
struct octeon_gpio *gpio;
struct gpio_chip *chip;
void __iomem *reg_base;
int err = 0;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
chip = &gpio->chip;
reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
gpio->register_base = (u64)reg_base;
pdev->dev.platform_data = chip;
chip->label = "octeon-gpio";
chip->parent = &pdev->dev;
chip->owner = THIS_MODULE;
chip->base = 0;
chip->can_sleep = false;
chip->ngpio = 20;
chip->direction_input = octeon_gpio_dir_in;
chip->get = octeon_gpio_get;
chip->direction_output = octeon_gpio_dir_out;
chip->set = octeon_gpio_set;
err = devm_gpiochip_add_data(&pdev->dev, chip, gpio);
if (err)
return err;
dev_info(&pdev->dev, "OCTEON GPIO driver probed.\n");
return 0;
}
static const struct of_device_id octeon_gpio_match[] = {
{
.compatible = "cavium,octeon-3860-gpio",
},
{},
};
MODULE_DEVICE_TABLE(of, octeon_gpio_match);
static struct platform_driver octeon_gpio_driver = {
.driver = {
.name = "octeon_gpio",
.of_match_table = octeon_gpio_match,
},
.probe = octeon_gpio_probe,
};
module_platform_driver(octeon_gpio_driver);
MODULE_DESCRIPTION("Cavium Inc. OCTEON GPIO Driver");
MODULE_AUTHOR("David Daney");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-octeon.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* TI DaVinci GPIO Support
*
* Copyright (c) 2006-2007 David Brownell
* Copyright (c) 2007, MontaVista Software, Inc. <[email protected]>
*/
#include <linux/gpio/driver.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/spinlock.h>
#include <linux/pm_runtime.h>
#define MAX_REGS_BANKS 5
#define MAX_INT_PER_BANK 32
struct davinci_gpio_regs {
u32 dir;
u32 out_data;
u32 set_data;
u32 clr_data;
u32 in_data;
u32 set_rising;
u32 clr_rising;
u32 set_falling;
u32 clr_falling;
u32 intstat;
};
typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
static void __iomem *gpio_base;
static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
struct davinci_gpio_irq_data {
void __iomem *regs;
struct davinci_gpio_controller *chip;
int bank_num;
};
struct davinci_gpio_controller {
struct gpio_chip chip;
struct irq_domain *irq_domain;
/* Serialize access to GPIO registers */
spinlock_t lock;
void __iomem *regs[MAX_REGS_BANKS];
int gpio_unbanked;
int irqs[MAX_INT_PER_BANK];
struct davinci_gpio_regs context[MAX_REGS_BANKS];
u32 binten_context;
};
static inline u32 __gpio_mask(unsigned gpio)
{
return 1 << (gpio % 32);
}
static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
{
struct davinci_gpio_regs __iomem *g;
g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
return g;
}
static int davinci_gpio_irq_setup(struct platform_device *pdev);
/*--------------------------------------------------------------------------*/
/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
static inline int __davinci_direction(struct gpio_chip *chip,
unsigned offset, bool out, int value)
{
struct davinci_gpio_controller *d = gpiochip_get_data(chip);
struct davinci_gpio_regs __iomem *g;
unsigned long flags;
u32 temp;
int bank = offset / 32;
u32 mask = __gpio_mask(offset);
g = d->regs[bank];
spin_lock_irqsave(&d->lock, flags);
temp = readl_relaxed(&g->dir);
if (out) {
temp &= ~mask;
writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
} else {
temp |= mask;
}
writel_relaxed(temp, &g->dir);
spin_unlock_irqrestore(&d->lock, flags);
return 0;
}
static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
return __davinci_direction(chip, offset, false, 0);
}
static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
return __davinci_direction(chip, offset, true, value);
}
/*
* Read the pin's value (works even if it's set up as output);
* returns zero/nonzero.
*
* Note that changes are synched to the GPIO clock, so reading values back
* right after you've set them may give old values.
*/
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio_controller *d = gpiochip_get_data(chip);
struct davinci_gpio_regs __iomem *g;
int bank = offset / 32;
g = d->regs[bank];
return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
}
/*
* Assuming the pin is muxed as a gpio output, set its output value.
*/
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct davinci_gpio_controller *d = gpiochip_get_data(chip);
struct davinci_gpio_regs __iomem *g;
int bank = offset / 32;
g = d->regs[bank];
writel_relaxed(__gpio_mask(offset),
value ? &g->set_data : &g->clr_data);
}
static struct davinci_gpio_platform_data *
davinci_gpio_get_pdata(struct platform_device *pdev)
{
struct device_node *dn = pdev->dev.of_node;
struct davinci_gpio_platform_data *pdata;
int ret;
u32 val;
if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
return dev_get_platdata(&pdev->dev);
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return NULL;
ret = of_property_read_u32(dn, "ti,ngpio", &val);
if (ret)
goto of_err;
pdata->ngpio = val;
ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
if (ret)
goto of_err;
pdata->gpio_unbanked = val;
return pdata;
of_err:
dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
return NULL;
}
static int davinci_gpio_probe(struct platform_device *pdev)
{
int bank, i, ret = 0;
unsigned int ngpio, nbank, nirq;
struct davinci_gpio_controller *chips;
struct davinci_gpio_platform_data *pdata;
struct device *dev = &pdev->dev;
pdata = davinci_gpio_get_pdata(pdev);
if (!pdata) {
dev_err(dev, "No platform data found\n");
return -EINVAL;
}
dev->platform_data = pdata;
/*
* The gpio banks conceptually expose a segmented bitmap,
* and "ngpio" is one more than the largest zero-based
* bit index that's valid.
*/
ngpio = pdata->ngpio;
if (ngpio == 0) {
dev_err(dev, "How many GPIOs?\n");
return -EINVAL;
}
/*
* If there are unbanked interrupts then the number of
* interrupts is equal to number of gpios else all are banked so
* number of interrupts is equal to number of banks(each with 16 gpios)
*/
if (pdata->gpio_unbanked)
nirq = pdata->gpio_unbanked;
else
nirq = DIV_ROUND_UP(ngpio, 16);
chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
if (!chips)
return -ENOMEM;
gpio_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(gpio_base))
return PTR_ERR(gpio_base);
for (i = 0; i < nirq; i++) {
chips->irqs[i] = platform_get_irq(pdev, i);
if (chips->irqs[i] < 0)
return chips->irqs[i];
}
chips->chip.label = dev_name(dev);
chips->chip.direction_input = davinci_direction_in;
chips->chip.get = davinci_gpio_get;
chips->chip.direction_output = davinci_direction_out;
chips->chip.set = davinci_gpio_set;
chips->chip.ngpio = ngpio;
chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
#ifdef CONFIG_OF_GPIO
chips->chip.parent = dev;
chips->chip.request = gpiochip_generic_request;
chips->chip.free = gpiochip_generic_free;
#endif
spin_lock_init(&chips->lock);
nbank = DIV_ROUND_UP(ngpio, 32);
for (bank = 0; bank < nbank; bank++)
chips->regs[bank] = gpio_base + offset_array[bank];
ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
if (ret)
return ret;
platform_set_drvdata(pdev, chips);
ret = davinci_gpio_irq_setup(pdev);
if (ret)
return ret;
return 0;
}
/*--------------------------------------------------------------------------*/
/*
* We expect irqs will normally be set up as input pins, but they can also be
* used as output pins ... which is convenient for testing.
*
* NOTE: The first few GPIOs also have direct INTC hookups in addition
* to their GPIOBNK0 irq, with a bit less overhead.
*
* All those INTC hookups (direct, plus several IRQ banks) can also
* serve as EDMA event triggers.
*/
static void gpio_irq_disable(struct irq_data *d)
{
struct davinci_gpio_regs __iomem *g = irq2regs(d);
uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
writel_relaxed(mask, &g->clr_falling);
writel_relaxed(mask, &g->clr_rising);
}
static void gpio_irq_enable(struct irq_data *d)
{
struct davinci_gpio_regs __iomem *g = irq2regs(d);
uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
unsigned status = irqd_get_trigger_type(d);
status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
if (!status)
status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
if (status & IRQ_TYPE_EDGE_FALLING)
writel_relaxed(mask, &g->set_falling);
if (status & IRQ_TYPE_EDGE_RISING)
writel_relaxed(mask, &g->set_rising);
}
static int gpio_irq_type(struct irq_data *d, unsigned trigger)
{
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
return -EINVAL;
return 0;
}
static struct irq_chip gpio_irqchip = {
.name = "GPIO",
.irq_enable = gpio_irq_enable,
.irq_disable = gpio_irq_disable,
.irq_set_type = gpio_irq_type,
.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE,
};
static void gpio_irq_handler(struct irq_desc *desc)
{
struct davinci_gpio_regs __iomem *g;
u32 mask = 0xffff;
int bank_num;
struct davinci_gpio_controller *d;
struct davinci_gpio_irq_data *irqdata;
irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
bank_num = irqdata->bank_num;
g = irqdata->regs;
d = irqdata->chip;
/* we only care about one bank */
if ((bank_num % 2) == 1)
mask <<= 16;
/* temporarily mask (level sensitive) parent IRQ */
chained_irq_enter(irq_desc_get_chip(desc), desc);
while (1) {
u32 status;
int bit;
irq_hw_number_t hw_irq;
/* ack any irqs */
status = readl_relaxed(&g->intstat) & mask;
if (!status)
break;
writel_relaxed(status, &g->intstat);
/* now demux them to the right lowlevel handler */
while (status) {
bit = __ffs(status);
status &= ~BIT(bit);
/* Max number of gpios per controller is 144 so
* hw_irq will be in [0..143]
*/
hw_irq = (bank_num / 2) * 32 + bit;
generic_handle_domain_irq(d->irq_domain, hw_irq);
}
}
chained_irq_exit(irq_desc_get_chip(desc), desc);
/* now it may re-trigger */
}
static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio_controller *d = gpiochip_get_data(chip);
if (d->irq_domain)
return irq_create_mapping(d->irq_domain, offset);
else
return -ENXIO;
}
static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio_controller *d = gpiochip_get_data(chip);
/*
* NOTE: we assume for now that only irqs in the first gpio_chip
* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
*/
if (offset < d->gpio_unbanked)
return d->irqs[offset];
else
return -ENODEV;
}
static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
{
struct davinci_gpio_controller *d;
struct davinci_gpio_regs __iomem *g;
u32 mask, i;
d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
g = (struct davinci_gpio_regs __iomem *)d->regs[0];
for (i = 0; i < MAX_INT_PER_BANK; i++)
if (data->irq == d->irqs[i])
break;
if (i == MAX_INT_PER_BANK)
return -EINVAL;
mask = __gpio_mask(i);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
return -EINVAL;
writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
? &g->set_falling : &g->clr_falling);
writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
? &g->set_rising : &g->clr_rising);
return 0;
}
static int
davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
struct davinci_gpio_controller *chips =
(struct davinci_gpio_controller *)d->host_data;
struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
"davinci_gpio");
irq_set_irq_type(irq, IRQ_TYPE_NONE);
irq_set_chip_data(irq, (__force void *)g);
irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
return 0;
}
static const struct irq_domain_ops davinci_gpio_irq_ops = {
.map = davinci_gpio_irq_map,
.xlate = irq_domain_xlate_onetwocell,
};
static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
{
static struct irq_chip_type gpio_unbanked;
gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
return &gpio_unbanked.chip;
};
static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
{
static struct irq_chip gpio_unbanked;
gpio_unbanked = *irq_get_chip(irq);
return &gpio_unbanked;
};
static const struct of_device_id davinci_gpio_ids[];
/*
* NOTE: for suspend/resume, probably best to make a platform_device with
* suspend_late/resume_resume calls hooking into results of the set_wake()
* calls ... so if no gpios are wakeup events the clock can be disabled,
* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
* (dm6446) can be set appropriately for GPIOV33 pins.
*/
static int davinci_gpio_irq_setup(struct platform_device *pdev)
{
unsigned gpio, bank;
int irq;
int ret;
struct clk *clk;
u32 binten = 0;
unsigned ngpio;
struct device *dev = &pdev->dev;
struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
struct davinci_gpio_platform_data *pdata = dev->platform_data;
struct davinci_gpio_regs __iomem *g;
struct irq_domain *irq_domain = NULL;
const struct of_device_id *match;
struct irq_chip *irq_chip;
struct davinci_gpio_irq_data *irqdata;
gpio_get_irq_chip_cb_t gpio_get_irq_chip;
/*
* Use davinci_gpio_get_irq_chip by default to handle non DT cases
*/
gpio_get_irq_chip = davinci_gpio_get_irq_chip;
match = of_match_device(of_match_ptr(davinci_gpio_ids),
dev);
if (match)
gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
ngpio = pdata->ngpio;
clk = devm_clk_get(dev, "gpio");
if (IS_ERR(clk)) {
dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
return PTR_ERR(clk);
}
ret = clk_prepare_enable(clk);
if (ret)
return ret;
if (!pdata->gpio_unbanked) {
irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
if (irq < 0) {
dev_err(dev, "Couldn't allocate IRQ numbers\n");
clk_disable_unprepare(clk);
return irq;
}
irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
&davinci_gpio_irq_ops,
chips);
if (!irq_domain) {
dev_err(dev, "Couldn't register an IRQ domain\n");
clk_disable_unprepare(clk);
return -ENODEV;
}
}
/*
* Arrange gpiod_to_irq() support, handling either direct IRQs or
* banked IRQs. Having GPIOs in the first GPIO bank use direct
* IRQs, while the others use banked IRQs, would need some setup
* tweaks to recognize hardware which can do that.
*/
chips->chip.to_irq = gpio_to_irq_banked;
chips->irq_domain = irq_domain;
/*
* AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
* controller only handling trigger modes. We currently assume no
* IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
*/
if (pdata->gpio_unbanked) {
/* pass "bank 0" GPIO IRQs to AINTC */
chips->chip.to_irq = gpio_to_irq_unbanked;
chips->gpio_unbanked = pdata->gpio_unbanked;
binten = GENMASK(pdata->gpio_unbanked / 16, 0);
/* AINTC handles mask/unmask; GPIO handles triggering */
irq = chips->irqs[0];
irq_chip = gpio_get_irq_chip(irq);
irq_chip->name = "GPIO-AINTC";
irq_chip->irq_set_type = gpio_irq_type_unbanked;
/* default trigger: both edges */
g = chips->regs[0];
writel_relaxed(~0, &g->set_falling);
writel_relaxed(~0, &g->set_rising);
/* set the direct IRQs up to use that irqchip */
for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
irq_set_chip(chips->irqs[gpio], irq_chip);
irq_set_handler_data(chips->irqs[gpio], chips);
irq_set_status_flags(chips->irqs[gpio],
IRQ_TYPE_EDGE_BOTH);
}
goto done;
}
/*
* Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
* then chain through our own handler.
*/
for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
/* disabled by default, enabled only as needed
* There are register sets for 32 GPIOs. 2 banks of 16
* GPIOs are covered by each set of registers hence divide by 2
*/
g = chips->regs[bank / 2];
writel_relaxed(~0, &g->clr_falling);
writel_relaxed(~0, &g->clr_rising);
/*
* Each chip handles 32 gpios, and each irq bank consists of 16
* gpio irqs. Pass the irq bank's corresponding controller to
* the chained irq handler.
*/
irqdata = devm_kzalloc(&pdev->dev,
sizeof(struct
davinci_gpio_irq_data),
GFP_KERNEL);
if (!irqdata) {
clk_disable_unprepare(clk);
return -ENOMEM;
}
irqdata->regs = g;
irqdata->bank_num = bank;
irqdata->chip = chips;
irq_set_chained_handler_and_data(chips->irqs[bank],
gpio_irq_handler, irqdata);
binten |= BIT(bank);
}
done:
/*
* BINTEN -- per-bank interrupt enable. genirq would also let these
* bits be set/cleared dynamically.
*/
writel_relaxed(binten, gpio_base + BINTEN);
return 0;
}
static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
u32 nbank)
{
struct davinci_gpio_regs __iomem *g;
struct davinci_gpio_regs *context;
u32 bank;
void __iomem *base;
base = chips->regs[0] - offset_array[0];
chips->binten_context = readl_relaxed(base + BINTEN);
for (bank = 0; bank < nbank; bank++) {
g = chips->regs[bank];
context = &chips->context[bank];
context->dir = readl_relaxed(&g->dir);
context->set_data = readl_relaxed(&g->set_data);
context->set_rising = readl_relaxed(&g->set_rising);
context->set_falling = readl_relaxed(&g->set_falling);
}
/* Clear all interrupt status registers */
writel_relaxed(GENMASK(31, 0), &g->intstat);
}
static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
u32 nbank)
{
struct davinci_gpio_regs __iomem *g;
struct davinci_gpio_regs *context;
u32 bank;
void __iomem *base;
base = chips->regs[0] - offset_array[0];
if (readl_relaxed(base + BINTEN) != chips->binten_context)
writel_relaxed(chips->binten_context, base + BINTEN);
for (bank = 0; bank < nbank; bank++) {
g = chips->regs[bank];
context = &chips->context[bank];
if (readl_relaxed(&g->dir) != context->dir)
writel_relaxed(context->dir, &g->dir);
if (readl_relaxed(&g->set_data) != context->set_data)
writel_relaxed(context->set_data, &g->set_data);
if (readl_relaxed(&g->set_rising) != context->set_rising)
writel_relaxed(context->set_rising, &g->set_rising);
if (readl_relaxed(&g->set_falling) != context->set_falling)
writel_relaxed(context->set_falling, &g->set_falling);
}
}
static int davinci_gpio_suspend(struct device *dev)
{
struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
davinci_gpio_save_context(chips, nbank);
return 0;
}
static int davinci_gpio_resume(struct device *dev)
{
struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
davinci_gpio_restore_context(chips, nbank);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
davinci_gpio_resume);
static const struct of_device_id davinci_gpio_ids[] = {
{ .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
{ .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
{ .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
static struct platform_driver davinci_gpio_driver = {
.probe = davinci_gpio_probe,
.driver = {
.name = "davinci_gpio",
.pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
.of_match_table = of_match_ptr(davinci_gpio_ids),
},
};
/*
* GPIO driver registration needs to be done before machine_init functions
* access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
*/
static int __init davinci_gpio_drv_reg(void)
{
return platform_driver_register(&davinci_gpio_driver);
}
postcore_initcall(davinci_gpio_drv_reg);
static void __exit davinci_gpio_exit(void)
{
platform_driver_unregister(&davinci_gpio_driver);
}
module_exit(davinci_gpio_exit);
MODULE_AUTHOR("Jan Kotas <[email protected]>");
MODULE_DESCRIPTION("DAVINCI GPIO driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:gpio-davinci");
| linux-master | drivers/gpio/gpio-davinci.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* GPIO driver for EXAR XRA1403 16-bit GPIO expander
*
* Copyright (c) 2017, General Electric Company
*/
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/seq_file.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
/* XRA1403 registers */
#define XRA_GSR 0x00 /* GPIO State */
#define XRA_OCR 0x02 /* Output Control */
#define XRA_PIR 0x04 /* Input Polarity Inversion */
#define XRA_GCR 0x06 /* GPIO Configuration */
#define XRA_PUR 0x08 /* Input Internal Pull-up Resistor Enable/Disable */
#define XRA_IER 0x0A /* Input Interrupt Enable */
#define XRA_TSCR 0x0C /* Output Three-State Control */
#define XRA_ISR 0x0E /* Input Interrupt Status */
#define XRA_REIR 0x10 /* Input Rising Edge Interrupt Enable */
#define XRA_FEIR 0x12 /* Input Falling Edge Interrupt Enable */
#define XRA_IFR 0x14 /* Input Filter Enable/Disable */
#define XRA_LAST 0x15 /* Bounds */
struct xra1403 {
struct gpio_chip chip;
struct regmap *regmap;
};
static const struct regmap_config xra1403_regmap_cfg = {
.reg_bits = 7,
.pad_bits = 1,
.val_bits = 8,
.max_register = XRA_LAST,
};
static unsigned int to_reg(unsigned int reg, unsigned int offset)
{
return reg + (offset > 7);
}
static int xra1403_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct xra1403 *xra = gpiochip_get_data(chip);
return regmap_update_bits(xra->regmap, to_reg(XRA_GCR, offset),
BIT(offset % 8), BIT(offset % 8));
}
static int xra1403_direction_output(struct gpio_chip *chip, unsigned int offset,
int value)
{
int ret;
struct xra1403 *xra = gpiochip_get_data(chip);
ret = regmap_update_bits(xra->regmap, to_reg(XRA_GCR, offset),
BIT(offset % 8), 0);
if (ret)
return ret;
ret = regmap_update_bits(xra->regmap, to_reg(XRA_OCR, offset),
BIT(offset % 8), value ? BIT(offset % 8) : 0);
return ret;
}
static int xra1403_get_direction(struct gpio_chip *chip, unsigned int offset)
{
int ret;
unsigned int val;
struct xra1403 *xra = gpiochip_get_data(chip);
ret = regmap_read(xra->regmap, to_reg(XRA_GCR, offset), &val);
if (ret)
return ret;
if (val & BIT(offset % 8))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static int xra1403_get(struct gpio_chip *chip, unsigned int offset)
{
int ret;
unsigned int val;
struct xra1403 *xra = gpiochip_get_data(chip);
ret = regmap_read(xra->regmap, to_reg(XRA_GSR, offset), &val);
if (ret)
return ret;
return !!(val & BIT(offset % 8));
}
static void xra1403_set(struct gpio_chip *chip, unsigned int offset, int value)
{
int ret;
struct xra1403 *xra = gpiochip_get_data(chip);
ret = regmap_update_bits(xra->regmap, to_reg(XRA_OCR, offset),
BIT(offset % 8), value ? BIT(offset % 8) : 0);
if (ret)
dev_err(chip->parent, "Failed to set pin: %d, ret: %d\n",
offset, ret);
}
#ifdef CONFIG_DEBUG_FS
static void xra1403_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
int reg;
struct xra1403 *xra = gpiochip_get_data(chip);
int value[XRA_LAST];
int i;
const char *label;
unsigned int gcr;
unsigned int gsr;
seq_puts(s, "xra reg:");
for (reg = 0; reg <= XRA_LAST; reg++)
seq_printf(s, " %2.2x", reg);
seq_puts(s, "\n value:");
for (reg = 0; reg < XRA_LAST; reg++) {
regmap_read(xra->regmap, reg, &value[reg]);
seq_printf(s, " %2.2x", value[reg]);
}
seq_puts(s, "\n");
gcr = value[XRA_GCR + 1] << 8 | value[XRA_GCR];
gsr = value[XRA_GSR + 1] << 8 | value[XRA_GSR];
for_each_requested_gpio(chip, i, label) {
seq_printf(s, " gpio-%-3d (%-12s) %s %s\n",
chip->base + i, label,
(gcr & BIT(i)) ? "in" : "out",
(gsr & BIT(i)) ? "hi" : "lo");
}
}
#else
#define xra1403_dbg_show NULL
#endif
static int xra1403_probe(struct spi_device *spi)
{
struct xra1403 *xra;
struct gpio_desc *reset_gpio;
int ret;
xra = devm_kzalloc(&spi->dev, sizeof(*xra), GFP_KERNEL);
if (!xra)
return -ENOMEM;
/* bring the chip out of reset if reset pin is provided*/
reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(reset_gpio))
dev_warn(&spi->dev, "Could not get reset-gpios\n");
xra->chip.direction_input = xra1403_direction_input;
xra->chip.direction_output = xra1403_direction_output;
xra->chip.get_direction = xra1403_get_direction;
xra->chip.get = xra1403_get;
xra->chip.set = xra1403_set;
xra->chip.dbg_show = xra1403_dbg_show;
xra->chip.ngpio = 16;
xra->chip.label = "xra1403";
xra->chip.base = -1;
xra->chip.can_sleep = true;
xra->chip.parent = &spi->dev;
xra->chip.owner = THIS_MODULE;
xra->regmap = devm_regmap_init_spi(spi, &xra1403_regmap_cfg);
if (IS_ERR(xra->regmap)) {
ret = PTR_ERR(xra->regmap);
dev_err(&spi->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
return devm_gpiochip_add_data(&spi->dev, &xra->chip, xra);
}
static const struct spi_device_id xra1403_ids[] = {
{ "xra1403" },
{},
};
MODULE_DEVICE_TABLE(spi, xra1403_ids);
static const struct of_device_id xra1403_spi_of_match[] = {
{ .compatible = "exar,xra1403" },
{},
};
MODULE_DEVICE_TABLE(of, xra1403_spi_of_match);
static struct spi_driver xra1403_driver = {
.probe = xra1403_probe,
.id_table = xra1403_ids,
.driver = {
.name = "xra1403",
.of_match_table = xra1403_spi_of_match,
},
};
module_spi_driver(xra1403_driver);
MODULE_AUTHOR("Nandor Han <[email protected]>");
MODULE_AUTHOR("Semi Malinen <[email protected]>");
MODULE_DESCRIPTION("GPIO expander driver for EXAR XRA1403");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-xra1403.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AMD Promontory GPIO driver
*
* Copyright (C) 2015 ASMedia Technology Inc.
* Author: YD Tseng <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gpio/driver.h>
#include <linux/spinlock.h>
#include <linux/acpi.h>
#include <linux/platform_device.h>
#define PT_TOTAL_GPIO 8
#define PT_TOTAL_GPIO_EX 24
/* PCI-E MMIO register offsets */
#define PT_DIRECTION_REG 0x00
#define PT_INPUTDATA_REG 0x04
#define PT_OUTPUTDATA_REG 0x08
#define PT_CLOCKRATE_REG 0x0C
#define PT_SYNC_REG 0x28
struct pt_gpio_chip {
struct gpio_chip gc;
void __iomem *reg_base;
};
static int pt_gpio_request(struct gpio_chip *gc, unsigned offset)
{
struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
unsigned long flags;
u32 using_pins;
dev_dbg(gc->parent, "pt_gpio_request offset=%x\n", offset);
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
if (using_pins & BIT(offset)) {
dev_warn(gc->parent, "PT GPIO pin %x reconfigured\n",
offset);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
return -EINVAL;
}
writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
return 0;
}
static void pt_gpio_free(struct gpio_chip *gc, unsigned offset)
{
struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
unsigned long flags;
u32 using_pins;
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
using_pins &= ~BIT(offset);
writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
dev_dbg(gc->parent, "pt_gpio_free offset=%x\n", offset);
}
static int pt_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct pt_gpio_chip *pt_gpio;
int ret = 0;
if (!ACPI_COMPANION(dev)) {
dev_err(dev, "PT GPIO device node not found\n");
return -ENODEV;
}
pt_gpio = devm_kzalloc(dev, sizeof(struct pt_gpio_chip), GFP_KERNEL);
if (!pt_gpio)
return -ENOMEM;
pt_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pt_gpio->reg_base)) {
dev_err(dev, "Failed to map MMIO resource for PT GPIO.\n");
return PTR_ERR(pt_gpio->reg_base);
}
ret = bgpio_init(&pt_gpio->gc, dev, 4,
pt_gpio->reg_base + PT_INPUTDATA_REG,
pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL,
pt_gpio->reg_base + PT_DIRECTION_REG, NULL,
BGPIOF_READ_OUTPUT_REG_SET);
if (ret) {
dev_err(dev, "bgpio_init failed\n");
return ret;
}
pt_gpio->gc.owner = THIS_MODULE;
pt_gpio->gc.request = pt_gpio_request;
pt_gpio->gc.free = pt_gpio_free;
pt_gpio->gc.ngpio = (uintptr_t)device_get_match_data(dev);
ret = gpiochip_add_data(&pt_gpio->gc, pt_gpio);
if (ret) {
dev_err(dev, "Failed to register GPIO lib\n");
return ret;
}
platform_set_drvdata(pdev, pt_gpio);
/* initialize register setting */
writel(0, pt_gpio->reg_base + PT_SYNC_REG);
writel(0, pt_gpio->reg_base + PT_CLOCKRATE_REG);
dev_dbg(dev, "PT GPIO driver loaded\n");
return ret;
}
static int pt_gpio_remove(struct platform_device *pdev)
{
struct pt_gpio_chip *pt_gpio = platform_get_drvdata(pdev);
gpiochip_remove(&pt_gpio->gc);
return 0;
}
static const struct acpi_device_id pt_gpio_acpi_match[] = {
{ "AMDF030", PT_TOTAL_GPIO },
{ "AMDIF030", PT_TOTAL_GPIO },
{ "AMDIF031", PT_TOTAL_GPIO_EX },
{ },
};
MODULE_DEVICE_TABLE(acpi, pt_gpio_acpi_match);
static struct platform_driver pt_gpio_driver = {
.driver = {
.name = "pt-gpio",
.acpi_match_table = ACPI_PTR(pt_gpio_acpi_match),
},
.probe = pt_gpio_probe,
.remove = pt_gpio_remove,
};
module_platform_driver(pt_gpio_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("YD Tseng <[email protected]>");
MODULE_DESCRIPTION("AMD Promontory GPIO Driver");
| linux-master | drivers/gpio/gpio-amdpt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Intel Elkhart Lake PSE GPIO driver
*
* Copyright (c) 2023 Intel Corporation.
*
* Authors: Pandith N <[email protected]>
* Raag Jadav <[email protected]>
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include "gpio-tangier.h"
/* Each Intel EHL PSE GPIO Controller has 30 GPIO pins */
#define EHL_PSE_NGPIO 30
static int ehl_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tng_gpio *priv;
int irq, ret;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->reg_base))
return PTR_ERR(priv->reg_base);
priv->dev = dev;
priv->irq = irq;
priv->info.base = -1;
priv->info.ngpio = EHL_PSE_NGPIO;
priv->wake_regs.gwmr = GWMR_EHL;
priv->wake_regs.gwsr = GWSR_EHL;
priv->wake_regs.gsir = GSIR_EHL;
ret = devm_tng_gpio_probe(dev, priv);
if (ret)
return dev_err_probe(dev, ret, "tng_gpio_probe error\n");
platform_set_drvdata(pdev, priv);
return 0;
}
static int ehl_gpio_suspend(struct device *dev)
{
return tng_gpio_suspend(dev);
}
static int ehl_gpio_resume(struct device *dev)
{
return tng_gpio_resume(dev);
}
static DEFINE_SIMPLE_DEV_PM_OPS(ehl_gpio_pm_ops, ehl_gpio_suspend, ehl_gpio_resume);
static const struct platform_device_id ehl_gpio_ids[] = {
{ "gpio-elkhartlake" },
{ }
};
MODULE_DEVICE_TABLE(platform, ehl_gpio_ids);
static struct platform_driver ehl_gpio_driver = {
.driver = {
.name = "gpio-elkhartlake",
.pm = pm_sleep_ptr(&ehl_gpio_pm_ops),
},
.probe = ehl_gpio_probe,
.id_table = ehl_gpio_ids,
};
module_platform_driver(ehl_gpio_driver);
MODULE_AUTHOR("Pandith N <[email protected]>");
MODULE_AUTHOR("Raag Jadav <[email protected]>");
MODULE_DESCRIPTION("Intel Elkhart Lake PSE GPIO driver");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(GPIO_TANGIER);
| linux-master | drivers/gpio/gpio-elkhartlake.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Toshiba Visconti GPIO Support
*
* (C) Copyright 2020 Toshiba Electronic Devices & Storage Corporation
* (C) Copyright 2020 TOSHIBA CORPORATION
*
* Nobuhiro Iwamatsu <[email protected]>
*/
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/bitops.h>
/* register offset */
#define GPIO_DIR 0x00
#define GPIO_IDATA 0x08
#define GPIO_ODATA 0x10
#define GPIO_OSET 0x18
#define GPIO_OCLR 0x20
#define GPIO_INTMODE 0x30
#define BASE_HW_IRQ 24
struct visconti_gpio {
void __iomem *base;
spinlock_t lock; /* protect gpio register */
struct gpio_chip gpio_chip;
struct device *dev;
};
static int visconti_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct visconti_gpio *priv = gpiochip_get_data(gc);
u32 offset = irqd_to_hwirq(d);
u32 bit = BIT(offset);
u32 intc_type = IRQ_TYPE_EDGE_RISING;
u32 intmode, odata;
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
odata = readl(priv->base + GPIO_ODATA);
intmode = readl(priv->base + GPIO_INTMODE);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
odata &= ~bit;
intmode &= ~bit;
break;
case IRQ_TYPE_EDGE_FALLING:
odata |= bit;
intmode &= ~bit;
break;
case IRQ_TYPE_EDGE_BOTH:
intmode |= bit;
break;
case IRQ_TYPE_LEVEL_HIGH:
intc_type = IRQ_TYPE_LEVEL_HIGH;
odata &= ~bit;
intmode &= ~bit;
break;
case IRQ_TYPE_LEVEL_LOW:
intc_type = IRQ_TYPE_LEVEL_HIGH;
odata |= bit;
intmode &= ~bit;
break;
default:
ret = -EINVAL;
goto err;
}
writel(odata, priv->base + GPIO_ODATA);
writel(intmode, priv->base + GPIO_INTMODE);
irq_set_irq_type(offset, intc_type);
ret = irq_chip_set_type_parent(d, type);
err:
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
}
static int visconti_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
unsigned int child,
unsigned int child_type,
unsigned int *parent,
unsigned int *parent_type)
{
/* Interrupts 0..15 mapped to interrupts 24..39 on the GIC */
if (child < 16) {
/* All these interrupts are level high in the CPU */
*parent_type = IRQ_TYPE_LEVEL_HIGH;
*parent = child + BASE_HW_IRQ;
return 0;
}
return -EINVAL;
}
static int visconti_gpio_populate_parent_fwspec(struct gpio_chip *chip,
union gpio_irq_fwspec *gfwspec,
unsigned int parent_hwirq,
unsigned int parent_type)
{
struct irq_fwspec *fwspec = &gfwspec->fwspec;
fwspec->fwnode = chip->irq.parent_domain->fwnode;
fwspec->param_count = 3;
fwspec->param[0] = 0;
fwspec->param[1] = parent_hwirq;
fwspec->param[2] = parent_type;
return 0;
}
static void visconti_gpio_mask_irq(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_chip_mask_parent(d);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
static void visconti_gpio_unmask_irq(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
irq_chip_unmask_parent(d);
}
static void visconti_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct visconti_gpio *priv = gpiochip_get_data(gc);
seq_printf(p, dev_name(priv->dev));
}
static const struct irq_chip visconti_gpio_irq_chip = {
.irq_mask = visconti_gpio_mask_irq,
.irq_unmask = visconti_gpio_unmask_irq,
.irq_eoi = irq_chip_eoi_parent,
.irq_set_type = visconti_gpio_irq_set_type,
.irq_print_chip = visconti_gpio_irq_print_chip,
.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND |
IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int visconti_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct visconti_gpio *priv;
struct gpio_irq_chip *girq;
struct irq_domain *parent;
struct device_node *irq_parent;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
spin_lock_init(&priv->lock);
priv->dev = dev;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
irq_parent = of_irq_find_parent(dev->of_node);
if (!irq_parent) {
dev_err(dev, "No IRQ parent node\n");
return -ENODEV;
}
parent = irq_find_host(irq_parent);
of_node_put(irq_parent);
if (!parent) {
dev_err(dev, "No IRQ parent domain\n");
return -ENODEV;
}
ret = bgpio_init(&priv->gpio_chip, dev, 4,
priv->base + GPIO_IDATA,
priv->base + GPIO_OSET,
priv->base + GPIO_OCLR,
priv->base + GPIO_DIR,
NULL,
0);
if (ret) {
dev_err(dev, "unable to init generic GPIO\n");
return ret;
}
girq = &priv->gpio_chip.irq;
gpio_irq_chip_set_chip(girq, &visconti_gpio_irq_chip);
girq->fwnode = of_node_to_fwnode(dev->of_node);
girq->parent_domain = parent;
girq->child_to_parent_hwirq = visconti_gpio_child_to_parent_hwirq;
girq->populate_parent_alloc_arg = visconti_gpio_populate_parent_fwspec;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
return devm_gpiochip_add_data(dev, &priv->gpio_chip, priv);
}
static const struct of_device_id visconti_gpio_of_match[] = {
{ .compatible = "toshiba,gpio-tmpv7708", },
{ /* end of table */ }
};
MODULE_DEVICE_TABLE(of, visconti_gpio_of_match);
static struct platform_driver visconti_gpio_driver = {
.probe = visconti_gpio_probe,
.driver = {
.name = "visconti_gpio",
.of_match_table = visconti_gpio_of_match,
}
};
module_platform_driver(visconti_gpio_driver);
MODULE_AUTHOR("Nobuhiro Iwamatsu <[email protected]>");
MODULE_DESCRIPTION("Toshiba Visconti GPIO Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-visconti.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Intel 8255 Programmable Peripheral Interface
* Copyright (C) 2022 William Breathitt Gray
*/
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/gpio/regmap.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include "gpio-i8255.h"
#define I8255_NGPIO 24
#define I8255_NGPIO_PER_REG 8
#define I8255_CONTROL_PORTC_LOWER_DIRECTION BIT(0)
#define I8255_CONTROL_PORTB_DIRECTION BIT(1)
#define I8255_CONTROL_PORTC_UPPER_DIRECTION BIT(3)
#define I8255_CONTROL_PORTA_DIRECTION BIT(4)
#define I8255_CONTROL_MODE_SET BIT(7)
#define I8255_PORTA 0x0
#define I8255_PORTB 0x1
#define I8255_PORTC 0x2
#define I8255_CONTROL 0x3
#define I8255_REG_DAT_BASE I8255_PORTA
#define I8255_REG_DIR_IN_BASE I8255_CONTROL
static int i8255_direction_mask(const unsigned int offset)
{
const unsigned int stride = offset / I8255_NGPIO_PER_REG;
const unsigned int line = offset % I8255_NGPIO_PER_REG;
switch (stride) {
case I8255_PORTA:
return I8255_CONTROL_PORTA_DIRECTION;
case I8255_PORTB:
return I8255_CONTROL_PORTB_DIRECTION;
case I8255_PORTC:
/* Port C can be configured by nibble */
if (line >= 4)
return I8255_CONTROL_PORTC_UPPER_DIRECTION;
return I8255_CONTROL_PORTC_LOWER_DIRECTION;
default:
/* Should never reach this path */
return 0;
}
}
static int i8255_ppi_init(struct regmap *const map, const unsigned int base)
{
int err;
/* Configure all ports to MODE 0 output mode */
err = regmap_write(map, base + I8255_CONTROL, I8255_CONTROL_MODE_SET);
if (err)
return err;
/* Initialize all GPIO to output 0 */
err = regmap_write(map, base + I8255_PORTA, 0x00);
if (err)
return err;
err = regmap_write(map, base + I8255_PORTB, 0x00);
if (err)
return err;
return regmap_write(map, base + I8255_PORTC, 0x00);
}
static int i8255_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
unsigned int offset, unsigned int *reg,
unsigned int *mask)
{
const unsigned int ppi = offset / I8255_NGPIO;
const unsigned int ppi_offset = offset % I8255_NGPIO;
const unsigned int stride = ppi_offset / I8255_NGPIO_PER_REG;
const unsigned int line = ppi_offset % I8255_NGPIO_PER_REG;
switch (base) {
case I8255_REG_DAT_BASE:
*reg = base + stride + ppi * 4;
*mask = BIT(line);
return 0;
case I8255_REG_DIR_IN_BASE:
*reg = base + ppi * 4;
*mask = i8255_direction_mask(ppi_offset);
return 0;
default:
/* Should never reach this path */
return -EINVAL;
}
}
/**
* devm_i8255_regmap_register - Register an i8255 GPIO controller
* @dev: device that is registering this i8255 GPIO device
* @config: configuration for i8255_regmap_config
*
* Registers an Intel 8255 Programmable Peripheral Interface GPIO controller.
* Returns 0 on success and negative error number on failure.
*/
int devm_i8255_regmap_register(struct device *const dev,
const struct i8255_regmap_config *const config)
{
struct gpio_regmap_config gpio_config = {0};
unsigned long i;
int err;
if (!config->parent)
return -EINVAL;
if (!config->map)
return -EINVAL;
if (!config->num_ppi)
return -EINVAL;
for (i = 0; i < config->num_ppi; i++) {
err = i8255_ppi_init(config->map, i * 4);
if (err)
return err;
}
gpio_config.parent = config->parent;
gpio_config.regmap = config->map;
gpio_config.ngpio = I8255_NGPIO * config->num_ppi;
gpio_config.names = config->names;
gpio_config.reg_dat_base = GPIO_REGMAP_ADDR(I8255_REG_DAT_BASE);
gpio_config.reg_set_base = GPIO_REGMAP_ADDR(I8255_REG_DAT_BASE);
gpio_config.reg_dir_in_base = GPIO_REGMAP_ADDR(I8255_REG_DIR_IN_BASE);
gpio_config.ngpio_per_reg = I8255_NGPIO_PER_REG;
gpio_config.irq_domain = config->domain;
gpio_config.reg_mask_xlate = i8255_reg_mask_xlate;
return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config));
}
EXPORT_SYMBOL_NS_GPL(devm_i8255_regmap_register, I8255);
MODULE_AUTHOR("William Breathitt Gray");
MODULE_DESCRIPTION("Intel 8255 Programmable Peripheral Interface");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-i8255.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* GPIO driver for Analog Devices ADP5520 MFD PMICs
*
* Copyright 2009 Analog Devices Inc.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mfd/adp5520.h>
#include <linux/gpio/driver.h>
struct adp5520_gpio {
struct device *master;
struct gpio_chip gpio_chip;
unsigned char lut[ADP5520_MAXGPIOS];
unsigned long output;
};
static int adp5520_gpio_get_value(struct gpio_chip *chip, unsigned off)
{
struct adp5520_gpio *dev;
uint8_t reg_val;
dev = gpiochip_get_data(chip);
/*
* There are dedicated registers for GPIO IN/OUT.
* Make sure we return the right value, even when configured as output
*/
if (test_bit(off, &dev->output))
adp5520_read(dev->master, ADP5520_GPIO_OUT, ®_val);
else
adp5520_read(dev->master, ADP5520_GPIO_IN, ®_val);
return !!(reg_val & dev->lut[off]);
}
static void adp5520_gpio_set_value(struct gpio_chip *chip,
unsigned off, int val)
{
struct adp5520_gpio *dev;
dev = gpiochip_get_data(chip);
if (val)
adp5520_set_bits(dev->master, ADP5520_GPIO_OUT, dev->lut[off]);
else
adp5520_clr_bits(dev->master, ADP5520_GPIO_OUT, dev->lut[off]);
}
static int adp5520_gpio_direction_input(struct gpio_chip *chip, unsigned off)
{
struct adp5520_gpio *dev;
dev = gpiochip_get_data(chip);
clear_bit(off, &dev->output);
return adp5520_clr_bits(dev->master, ADP5520_GPIO_CFG_2,
dev->lut[off]);
}
static int adp5520_gpio_direction_output(struct gpio_chip *chip,
unsigned off, int val)
{
struct adp5520_gpio *dev;
int ret = 0;
dev = gpiochip_get_data(chip);
set_bit(off, &dev->output);
if (val)
ret |= adp5520_set_bits(dev->master, ADP5520_GPIO_OUT,
dev->lut[off]);
else
ret |= adp5520_clr_bits(dev->master, ADP5520_GPIO_OUT,
dev->lut[off]);
ret |= adp5520_set_bits(dev->master, ADP5520_GPIO_CFG_2,
dev->lut[off]);
return ret;
}
static int adp5520_gpio_probe(struct platform_device *pdev)
{
struct adp5520_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
struct adp5520_gpio *dev;
struct gpio_chip *gc;
int ret, i, gpios;
unsigned char ctl_mask = 0;
if (pdata == NULL) {
dev_err(&pdev->dev, "missing platform data\n");
return -ENODEV;
}
if (pdev->id != ID_ADP5520) {
dev_err(&pdev->dev, "only ADP5520 supports GPIO\n");
return -ENODEV;
}
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
if (dev == NULL)
return -ENOMEM;
dev->master = pdev->dev.parent;
for (gpios = 0, i = 0; i < ADP5520_MAXGPIOS; i++)
if (pdata->gpio_en_mask & (1 << i))
dev->lut[gpios++] = 1 << i;
if (gpios < 1)
return -EINVAL;
gc = &dev->gpio_chip;
gc->direction_input = adp5520_gpio_direction_input;
gc->direction_output = adp5520_gpio_direction_output;
gc->get = adp5520_gpio_get_value;
gc->set = adp5520_gpio_set_value;
gc->can_sleep = true;
gc->base = pdata->gpio_start;
gc->ngpio = gpios;
gc->label = pdev->name;
gc->owner = THIS_MODULE;
ret = adp5520_clr_bits(dev->master, ADP5520_GPIO_CFG_1,
pdata->gpio_en_mask);
if (pdata->gpio_en_mask & ADP5520_GPIO_C3)
ctl_mask |= ADP5520_C3_MODE;
if (pdata->gpio_en_mask & ADP5520_GPIO_R3)
ctl_mask |= ADP5520_R3_MODE;
if (ctl_mask)
ret = adp5520_set_bits(dev->master, ADP5520_LED_CONTROL,
ctl_mask);
ret |= adp5520_set_bits(dev->master, ADP5520_GPIO_PULLUP,
pdata->gpio_pullup_mask);
if (ret) {
dev_err(&pdev->dev, "failed to write\n");
return ret;
}
return devm_gpiochip_add_data(&pdev->dev, &dev->gpio_chip, dev);
}
static struct platform_driver adp5520_gpio_driver = {
.driver = {
.name = "adp5520-gpio",
},
.probe = adp5520_gpio_probe,
};
module_platform_driver(adp5520_gpio_driver);
MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("GPIO ADP5520 Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:adp5520-gpio");
| linux-master | drivers/gpio/gpio-adp5520.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2008, 2009 Provigent Ltd.
*
* Author: Baruch Siach <[email protected]>
*
* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
*
* Data sheet: ARM DDI 0190B, September 2000
*/
#include <linux/amba/bus.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#define GPIODIR 0x400
#define GPIOIS 0x404
#define GPIOIBE 0x408
#define GPIOIEV 0x40C
#define GPIOIE 0x410
#define GPIORIS 0x414
#define GPIOMIS 0x418
#define GPIOIC 0x41C
#define PL061_GPIO_NR 8
#ifdef CONFIG_PM
struct pl061_context_save_regs {
u8 gpio_data;
u8 gpio_dir;
u8 gpio_is;
u8 gpio_ibe;
u8 gpio_iev;
u8 gpio_ie;
};
#endif
struct pl061 {
raw_spinlock_t lock;
void __iomem *base;
struct gpio_chip gc;
int parent_irq;
#ifdef CONFIG_PM
struct pl061_context_save_regs csave_regs;
#endif
};
static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
{
struct pl061 *pl061 = gpiochip_get_data(gc);
if (readb(pl061->base + GPIODIR) & BIT(offset))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct pl061 *pl061 = gpiochip_get_data(gc);
unsigned long flags;
unsigned char gpiodir;
raw_spin_lock_irqsave(&pl061->lock, flags);
gpiodir = readb(pl061->base + GPIODIR);
gpiodir &= ~(BIT(offset));
writeb(gpiodir, pl061->base + GPIODIR);
raw_spin_unlock_irqrestore(&pl061->lock, flags);
return 0;
}
static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
struct pl061 *pl061 = gpiochip_get_data(gc);
unsigned long flags;
unsigned char gpiodir;
raw_spin_lock_irqsave(&pl061->lock, flags);
writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
gpiodir = readb(pl061->base + GPIODIR);
gpiodir |= BIT(offset);
writeb(gpiodir, pl061->base + GPIODIR);
/*
* gpio value is set again, because pl061 doesn't allow to set value of
* a gpio pin before configuring it in OUT mode.
*/
writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
raw_spin_unlock_irqrestore(&pl061->lock, flags);
return 0;
}
static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
{
struct pl061 *pl061 = gpiochip_get_data(gc);
return !!readb(pl061->base + (BIT(offset + 2)));
}
static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
struct pl061 *pl061 = gpiochip_get_data(gc);
writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
}
static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pl061 *pl061 = gpiochip_get_data(gc);
int offset = irqd_to_hwirq(d);
unsigned long flags;
u8 gpiois, gpioibe, gpioiev;
u8 bit = BIT(offset);
if (offset < 0 || offset >= PL061_GPIO_NR)
return -EINVAL;
if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
(trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
{
dev_err(gc->parent,
"trying to configure line %d for both level and edge "
"detection, choose one!\n",
offset);
return -EINVAL;
}
raw_spin_lock_irqsave(&pl061->lock, flags);
gpioiev = readb(pl061->base + GPIOIEV);
gpiois = readb(pl061->base + GPIOIS);
gpioibe = readb(pl061->base + GPIOIBE);
if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
/* Disable edge detection */
gpioibe &= ~bit;
/* Enable level detection */
gpiois |= bit;
/* Select polarity */
if (polarity)
gpioiev |= bit;
else
gpioiev &= ~bit;
irq_set_handler_locked(d, handle_level_irq);
dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
offset,
polarity ? "HIGH" : "LOW");
} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
/* Disable level detection */
gpiois &= ~bit;
/* Select both edges, setting this makes GPIOEV be ignored */
gpioibe |= bit;
irq_set_handler_locked(d, handle_edge_irq);
dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
} else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
(trigger & IRQ_TYPE_EDGE_FALLING)) {
bool rising = trigger & IRQ_TYPE_EDGE_RISING;
/* Disable level detection */
gpiois &= ~bit;
/* Clear detection on both edges */
gpioibe &= ~bit;
/* Select edge */
if (rising)
gpioiev |= bit;
else
gpioiev &= ~bit;
irq_set_handler_locked(d, handle_edge_irq);
dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
offset,
rising ? "RISING" : "FALLING");
} else {
/* No trigger: disable everything */
gpiois &= ~bit;
gpioibe &= ~bit;
gpioiev &= ~bit;
irq_set_handler_locked(d, handle_bad_irq);
dev_warn(gc->parent, "no trigger selected for line %d\n",
offset);
}
writeb(gpiois, pl061->base + GPIOIS);
writeb(gpioibe, pl061->base + GPIOIBE);
writeb(gpioiev, pl061->base + GPIOIEV);
raw_spin_unlock_irqrestore(&pl061->lock, flags);
return 0;
}
static void pl061_irq_handler(struct irq_desc *desc)
{
unsigned long pending;
int offset;
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct pl061 *pl061 = gpiochip_get_data(gc);
struct irq_chip *irqchip = irq_desc_get_chip(desc);
chained_irq_enter(irqchip, desc);
pending = readb(pl061->base + GPIOMIS);
if (pending) {
for_each_set_bit(offset, &pending, PL061_GPIO_NR)
generic_handle_domain_irq(gc->irq.domain,
offset);
}
chained_irq_exit(irqchip, desc);
}
static void pl061_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pl061 *pl061 = gpiochip_get_data(gc);
u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
u8 gpioie;
raw_spin_lock(&pl061->lock);
gpioie = readb(pl061->base + GPIOIE) & ~mask;
writeb(gpioie, pl061->base + GPIOIE);
raw_spin_unlock(&pl061->lock);
gpiochip_disable_irq(gc, d->hwirq);
}
static void pl061_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pl061 *pl061 = gpiochip_get_data(gc);
u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
u8 gpioie;
gpiochip_enable_irq(gc, d->hwirq);
raw_spin_lock(&pl061->lock);
gpioie = readb(pl061->base + GPIOIE) | mask;
writeb(gpioie, pl061->base + GPIOIE);
raw_spin_unlock(&pl061->lock);
}
/**
* pl061_irq_ack() - ACK an edge IRQ
* @d: IRQ data for this IRQ
*
* This gets called from the edge IRQ handler to ACK the edge IRQ
* in the GPIOIC (interrupt-clear) register. For level IRQs this is
* not needed: these go away when the level signal goes away.
*/
static void pl061_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pl061 *pl061 = gpiochip_get_data(gc);
u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
raw_spin_lock(&pl061->lock);
writeb(mask, pl061->base + GPIOIC);
raw_spin_unlock(&pl061->lock);
}
static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pl061 *pl061 = gpiochip_get_data(gc);
return irq_set_irq_wake(pl061->parent_irq, state);
}
static void pl061_irq_print_chip(struct irq_data *data, struct seq_file *p)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
seq_printf(p, dev_name(gc->parent));
}
static const struct irq_chip pl061_irq_chip = {
.irq_ack = pl061_irq_ack,
.irq_mask = pl061_irq_mask,
.irq_unmask = pl061_irq_unmask,
.irq_set_type = pl061_irq_type,
.irq_set_wake = pl061_irq_set_wake,
.irq_print_chip = pl061_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device *dev = &adev->dev;
struct pl061 *pl061;
struct gpio_irq_chip *girq;
int ret, irq;
pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
if (pl061 == NULL)
return -ENOMEM;
pl061->base = devm_ioremap_resource(dev, &adev->res);
if (IS_ERR(pl061->base))
return PTR_ERR(pl061->base);
raw_spin_lock_init(&pl061->lock);
pl061->gc.request = gpiochip_generic_request;
pl061->gc.free = gpiochip_generic_free;
pl061->gc.base = -1;
pl061->gc.get_direction = pl061_get_direction;
pl061->gc.direction_input = pl061_direction_input;
pl061->gc.direction_output = pl061_direction_output;
pl061->gc.get = pl061_get_value;
pl061->gc.set = pl061_set_value;
pl061->gc.ngpio = PL061_GPIO_NR;
pl061->gc.label = dev_name(dev);
pl061->gc.parent = dev;
pl061->gc.owner = THIS_MODULE;
/*
* irq_chip support
*/
writeb(0, pl061->base + GPIOIE); /* disable irqs */
irq = adev->irq[0];
if (!irq)
dev_warn(&adev->dev, "IRQ support disabled\n");
pl061->parent_irq = irq;
girq = &pl061->gc.irq;
gpio_irq_chip_set_chip(girq, &pl061_irq_chip);
girq->parent_handler = pl061_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
if (ret)
return ret;
amba_set_drvdata(adev, pl061);
dev_info(dev, "PL061 GPIO chip registered\n");
return 0;
}
#ifdef CONFIG_PM
static int pl061_suspend(struct device *dev)
{
struct pl061 *pl061 = dev_get_drvdata(dev);
int offset;
pl061->csave_regs.gpio_data = 0;
pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
for (offset = 0; offset < PL061_GPIO_NR; offset++) {
if (pl061->csave_regs.gpio_dir & (BIT(offset)))
pl061->csave_regs.gpio_data |=
pl061_get_value(&pl061->gc, offset) << offset;
}
return 0;
}
static int pl061_resume(struct device *dev)
{
struct pl061 *pl061 = dev_get_drvdata(dev);
int offset;
for (offset = 0; offset < PL061_GPIO_NR; offset++) {
if (pl061->csave_regs.gpio_dir & (BIT(offset)))
pl061_direction_output(&pl061->gc, offset,
pl061->csave_regs.gpio_data &
(BIT(offset)));
else
pl061_direction_input(&pl061->gc, offset);
}
writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
return 0;
}
static const struct dev_pm_ops pl061_dev_pm_ops = {
.suspend = pl061_suspend,
.resume = pl061_resume,
.freeze = pl061_suspend,
.restore = pl061_resume,
};
#endif
static const struct amba_id pl061_ids[] = {
{
.id = 0x00041061,
.mask = 0x000fffff,
},
{ 0, 0 },
};
MODULE_DEVICE_TABLE(amba, pl061_ids);
static struct amba_driver pl061_gpio_driver = {
.drv = {
.name = "pl061_gpio",
#ifdef CONFIG_PM
.pm = &pl061_dev_pm_ops,
#endif
},
.id_table = pl061_ids,
.probe = pl061_probe,
};
module_amba_driver(pl061_gpio_driver);
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-pl061.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* GPIO interface for Winbond Super I/O chips
* Currently, only W83627UHG (Nuvoton NCT6627UD) is supported.
*
* Author: Maciej S. Szmigiero <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/gpio/driver.h>
#include <linux/ioport.h>
#include <linux/isa.h>
#include <linux/module.h>
#define WB_GPIO_DRIVER_NAME KBUILD_MODNAME
#define WB_SIO_BASE 0x2e
#define WB_SIO_BASE_HIGH 0x4e
#define WB_SIO_EXT_ENTER_KEY 0x87
#define WB_SIO_EXT_EXIT_KEY 0xaa
/* global chip registers */
#define WB_SIO_REG_LOGICAL 0x07
#define WB_SIO_REG_CHIP_MSB 0x20
#define WB_SIO_REG_CHIP_LSB 0x21
#define WB_SIO_CHIP_ID_W83627UHG 0xa230
#define WB_SIO_CHIP_ID_W83627UHG_MASK GENMASK(15, 4)
#define WB_SIO_REG_DPD 0x22
#define WB_SIO_REG_DPD_UARTA 4
#define WB_SIO_REG_DPD_UARTB 5
#define WB_SIO_REG_IDPD 0x23
#define WB_SIO_REG_IDPD_UARTC 4
#define WB_SIO_REG_IDPD_UARTD 5
#define WB_SIO_REG_IDPD_UARTE 6
#define WB_SIO_REG_IDPD_UARTF 7
#define WB_SIO_REG_GLOBAL_OPT 0x24
#define WB_SIO_REG_GO_ENFDC 1
#define WB_SIO_REG_OVTGPIO3456 0x29
#define WB_SIO_REG_OG3456_G3PP 3
#define WB_SIO_REG_OG3456_G4PP 4
#define WB_SIO_REG_OG3456_G5PP 5
#define WB_SIO_REG_OG3456_G6PP 7
#define WB_SIO_REG_I2C_PS 0x2a
#define WB_SIO_REG_I2CPS_I2CFS 1
#define WB_SIO_REG_GPIO1_MF 0x2c
#define WB_SIO_REG_G1MF_G1PP 6
#define WB_SIO_REG_G1MF_G2PP 7
#define WB_SIO_REG_G1MF_FS_MASK GENMASK(1, 0)
#define WB_SIO_REG_G1MF_FS_IR_OFF 0
#define WB_SIO_REG_G1MF_FS_IR 1
#define WB_SIO_REG_G1MF_FS_GPIO1 2
#define WB_SIO_REG_G1MF_FS_UARTB 3
/* not an actual device number, just a value meaning 'no device' */
#define WB_SIO_DEV_NONE 0xff
/* registers with offsets >= 0x30 are specific for a particular device */
/* UART B logical device */
#define WB_SIO_DEV_UARTB 0x03
#define WB_SIO_UARTB_REG_ENABLE 0x30
#define WB_SIO_UARTB_ENABLE_ON 0
/* UART C logical device */
#define WB_SIO_DEV_UARTC 0x06
#define WB_SIO_UARTC_REG_ENABLE 0x30
#define WB_SIO_UARTC_ENABLE_ON 0
/* GPIO3, GPIO4 logical device */
#define WB_SIO_DEV_GPIO34 0x07
#define WB_SIO_GPIO34_REG_ENABLE 0x30
#define WB_SIO_GPIO34_ENABLE_3 0
#define WB_SIO_GPIO34_ENABLE_4 1
#define WB_SIO_GPIO34_REG_IO3 0xe0
#define WB_SIO_GPIO34_REG_DATA3 0xe1
#define WB_SIO_GPIO34_REG_INV3 0xe2
#define WB_SIO_GPIO34_REG_IO4 0xe4
#define WB_SIO_GPIO34_REG_DATA4 0xe5
#define WB_SIO_GPIO34_REG_INV4 0xe6
/* WDTO, PLED, GPIO5, GPIO6 logical device */
#define WB_SIO_DEV_WDGPIO56 0x08
#define WB_SIO_WDGPIO56_REG_ENABLE 0x30
#define WB_SIO_WDGPIO56_ENABLE_5 1
#define WB_SIO_WDGPIO56_ENABLE_6 2
#define WB_SIO_WDGPIO56_REG_IO5 0xe0
#define WB_SIO_WDGPIO56_REG_DATA5 0xe1
#define WB_SIO_WDGPIO56_REG_INV5 0xe2
#define WB_SIO_WDGPIO56_REG_IO6 0xe4
#define WB_SIO_WDGPIO56_REG_DATA6 0xe5
#define WB_SIO_WDGPIO56_REG_INV6 0xe6
/* GPIO1, GPIO2, SUSLED logical device */
#define WB_SIO_DEV_GPIO12 0x09
#define WB_SIO_GPIO12_REG_ENABLE 0x30
#define WB_SIO_GPIO12_ENABLE_1 0
#define WB_SIO_GPIO12_ENABLE_2 1
#define WB_SIO_GPIO12_REG_IO1 0xe0
#define WB_SIO_GPIO12_REG_DATA1 0xe1
#define WB_SIO_GPIO12_REG_INV1 0xe2
#define WB_SIO_GPIO12_REG_IO2 0xe4
#define WB_SIO_GPIO12_REG_DATA2 0xe5
#define WB_SIO_GPIO12_REG_INV2 0xe6
/* UART D logical device */
#define WB_SIO_DEV_UARTD 0x0d
#define WB_SIO_UARTD_REG_ENABLE 0x30
#define WB_SIO_UARTD_ENABLE_ON 0
/* UART E logical device */
#define WB_SIO_DEV_UARTE 0x0e
#define WB_SIO_UARTE_REG_ENABLE 0x30
#define WB_SIO_UARTE_ENABLE_ON 0
/*
* for a description what a particular field of this struct means please see
* a description of the relevant module parameter at the bottom of this file
*/
struct winbond_gpio_params {
unsigned long base;
unsigned long gpios;
unsigned long ppgpios;
unsigned long odgpios;
bool pledgpio;
bool beepgpio;
bool i2cgpio;
};
static struct winbond_gpio_params params;
static int winbond_sio_enter(unsigned long base)
{
if (!request_muxed_region(base, 2, WB_GPIO_DRIVER_NAME))
return -EBUSY;
/*
* datasheet says two successive writes of the "key" value are needed
* in order for chip to enter the "Extended Function Mode"
*/
outb(WB_SIO_EXT_ENTER_KEY, base);
outb(WB_SIO_EXT_ENTER_KEY, base);
return 0;
}
static void winbond_sio_select_logical(unsigned long base, u8 dev)
{
outb(WB_SIO_REG_LOGICAL, base);
outb(dev, base + 1);
}
static void winbond_sio_leave(unsigned long base)
{
outb(WB_SIO_EXT_EXIT_KEY, base);
release_region(base, 2);
}
static void winbond_sio_reg_write(unsigned long base, u8 reg, u8 data)
{
outb(reg, base);
outb(data, base + 1);
}
static u8 winbond_sio_reg_read(unsigned long base, u8 reg)
{
outb(reg, base);
return inb(base + 1);
}
static void winbond_sio_reg_bset(unsigned long base, u8 reg, u8 bit)
{
u8 val;
val = winbond_sio_reg_read(base, reg);
val |= BIT(bit);
winbond_sio_reg_write(base, reg, val);
}
static void winbond_sio_reg_bclear(unsigned long base, u8 reg, u8 bit)
{
u8 val;
val = winbond_sio_reg_read(base, reg);
val &= ~BIT(bit);
winbond_sio_reg_write(base, reg, val);
}
static bool winbond_sio_reg_btest(unsigned long base, u8 reg, u8 bit)
{
return winbond_sio_reg_read(base, reg) & BIT(bit);
}
/**
* struct winbond_gpio_port_conflict - possibly conflicting device information
* @name: device name (NULL means no conflicting device defined)
* @dev: Super I/O logical device number where the testreg register
* is located (or WB_SIO_DEV_NONE - don't select any
* logical device)
* @testreg: register number where the testbit bit is located
* @testbit: index of a bit to check whether an actual conflict exists
* @warnonly: if set then a conflict isn't fatal (just warn about it),
* otherwise disable the particular GPIO port if a conflict
* is detected
*/
struct winbond_gpio_port_conflict {
const char *name;
u8 dev;
u8 testreg;
u8 testbit;
bool warnonly;
};
/**
* struct winbond_gpio_info - information about a particular GPIO port (device)
* @dev: Super I/O logical device number of the registers
* specified below
* @enablereg: port enable bit register number
* @enablebit: index of a port enable bit
* @outputreg: output driver mode bit register number
* @outputppbit: index of a push-pull output driver mode bit
* @ioreg: data direction register number
* @invreg: pin data inversion register number
* @datareg: pin data register number
* @conflict: description of a device that possibly conflicts with
* this port
*/
struct winbond_gpio_info {
u8 dev;
u8 enablereg;
u8 enablebit;
u8 outputreg;
u8 outputppbit;
u8 ioreg;
u8 invreg;
u8 datareg;
struct winbond_gpio_port_conflict conflict;
};
static const struct winbond_gpio_info winbond_gpio_infos[6] = {
{ /* 0 */
.dev = WB_SIO_DEV_GPIO12,
.enablereg = WB_SIO_GPIO12_REG_ENABLE,
.enablebit = WB_SIO_GPIO12_ENABLE_1,
.outputreg = WB_SIO_REG_GPIO1_MF,
.outputppbit = WB_SIO_REG_G1MF_G1PP,
.ioreg = WB_SIO_GPIO12_REG_IO1,
.invreg = WB_SIO_GPIO12_REG_INV1,
.datareg = WB_SIO_GPIO12_REG_DATA1,
.conflict = {
.name = "UARTB",
.dev = WB_SIO_DEV_UARTB,
.testreg = WB_SIO_UARTB_REG_ENABLE,
.testbit = WB_SIO_UARTB_ENABLE_ON,
.warnonly = true
}
},
{ /* 1 */
.dev = WB_SIO_DEV_GPIO12,
.enablereg = WB_SIO_GPIO12_REG_ENABLE,
.enablebit = WB_SIO_GPIO12_ENABLE_2,
.outputreg = WB_SIO_REG_GPIO1_MF,
.outputppbit = WB_SIO_REG_G1MF_G2PP,
.ioreg = WB_SIO_GPIO12_REG_IO2,
.invreg = WB_SIO_GPIO12_REG_INV2,
.datareg = WB_SIO_GPIO12_REG_DATA2
/* special conflict handling so doesn't use conflict data */
},
{ /* 2 */
.dev = WB_SIO_DEV_GPIO34,
.enablereg = WB_SIO_GPIO34_REG_ENABLE,
.enablebit = WB_SIO_GPIO34_ENABLE_3,
.outputreg = WB_SIO_REG_OVTGPIO3456,
.outputppbit = WB_SIO_REG_OG3456_G3PP,
.ioreg = WB_SIO_GPIO34_REG_IO3,
.invreg = WB_SIO_GPIO34_REG_INV3,
.datareg = WB_SIO_GPIO34_REG_DATA3,
.conflict = {
.name = "UARTC",
.dev = WB_SIO_DEV_UARTC,
.testreg = WB_SIO_UARTC_REG_ENABLE,
.testbit = WB_SIO_UARTC_ENABLE_ON,
.warnonly = true
}
},
{ /* 3 */
.dev = WB_SIO_DEV_GPIO34,
.enablereg = WB_SIO_GPIO34_REG_ENABLE,
.enablebit = WB_SIO_GPIO34_ENABLE_4,
.outputreg = WB_SIO_REG_OVTGPIO3456,
.outputppbit = WB_SIO_REG_OG3456_G4PP,
.ioreg = WB_SIO_GPIO34_REG_IO4,
.invreg = WB_SIO_GPIO34_REG_INV4,
.datareg = WB_SIO_GPIO34_REG_DATA4,
.conflict = {
.name = "UARTD",
.dev = WB_SIO_DEV_UARTD,
.testreg = WB_SIO_UARTD_REG_ENABLE,
.testbit = WB_SIO_UARTD_ENABLE_ON,
.warnonly = true
}
},
{ /* 4 */
.dev = WB_SIO_DEV_WDGPIO56,
.enablereg = WB_SIO_WDGPIO56_REG_ENABLE,
.enablebit = WB_SIO_WDGPIO56_ENABLE_5,
.outputreg = WB_SIO_REG_OVTGPIO3456,
.outputppbit = WB_SIO_REG_OG3456_G5PP,
.ioreg = WB_SIO_WDGPIO56_REG_IO5,
.invreg = WB_SIO_WDGPIO56_REG_INV5,
.datareg = WB_SIO_WDGPIO56_REG_DATA5,
.conflict = {
.name = "UARTE",
.dev = WB_SIO_DEV_UARTE,
.testreg = WB_SIO_UARTE_REG_ENABLE,
.testbit = WB_SIO_UARTE_ENABLE_ON,
.warnonly = true
}
},
{ /* 5 */
.dev = WB_SIO_DEV_WDGPIO56,
.enablereg = WB_SIO_WDGPIO56_REG_ENABLE,
.enablebit = WB_SIO_WDGPIO56_ENABLE_6,
.outputreg = WB_SIO_REG_OVTGPIO3456,
.outputppbit = WB_SIO_REG_OG3456_G6PP,
.ioreg = WB_SIO_WDGPIO56_REG_IO6,
.invreg = WB_SIO_WDGPIO56_REG_INV6,
.datareg = WB_SIO_WDGPIO56_REG_DATA6,
.conflict = {
.name = "FDC",
.dev = WB_SIO_DEV_NONE,
.testreg = WB_SIO_REG_GLOBAL_OPT,
.testbit = WB_SIO_REG_GO_ENFDC,
.warnonly = false
}
}
};
/* returns whether changing a pin is allowed */
static bool winbond_gpio_get_info(unsigned int *gpio_num,
const struct winbond_gpio_info **info)
{
bool allow_changing = true;
unsigned long i;
for_each_set_bit(i, ¶ms.gpios, BITS_PER_LONG) {
if (*gpio_num < 8)
break;
*gpio_num -= 8;
}
*info = &winbond_gpio_infos[i];
/*
* GPIO2 (the second port) shares some pins with a basic PC
* functionality, which is very likely controlled by the firmware.
* Don't allow changing these pins by default.
*/
if (i == 1) {
if (*gpio_num == 0 && !params.pledgpio)
allow_changing = false;
else if (*gpio_num == 1 && !params.beepgpio)
allow_changing = false;
else if ((*gpio_num == 5 || *gpio_num == 6) && !params.i2cgpio)
allow_changing = false;
}
return allow_changing;
}
static int winbond_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
unsigned long *base = gpiochip_get_data(gc);
const struct winbond_gpio_info *info;
bool val;
int ret;
winbond_gpio_get_info(&offset, &info);
ret = winbond_sio_enter(*base);
if (ret)
return ret;
winbond_sio_select_logical(*base, info->dev);
val = winbond_sio_reg_btest(*base, info->datareg, offset);
if (winbond_sio_reg_btest(*base, info->invreg, offset))
val = !val;
winbond_sio_leave(*base);
return val;
}
static int winbond_gpio_direction_in(struct gpio_chip *gc, unsigned int offset)
{
unsigned long *base = gpiochip_get_data(gc);
const struct winbond_gpio_info *info;
int ret;
if (!winbond_gpio_get_info(&offset, &info))
return -EACCES;
ret = winbond_sio_enter(*base);
if (ret)
return ret;
winbond_sio_select_logical(*base, info->dev);
winbond_sio_reg_bset(*base, info->ioreg, offset);
winbond_sio_leave(*base);
return 0;
}
static int winbond_gpio_direction_out(struct gpio_chip *gc,
unsigned int offset,
int val)
{
unsigned long *base = gpiochip_get_data(gc);
const struct winbond_gpio_info *info;
int ret;
if (!winbond_gpio_get_info(&offset, &info))
return -EACCES;
ret = winbond_sio_enter(*base);
if (ret)
return ret;
winbond_sio_select_logical(*base, info->dev);
winbond_sio_reg_bclear(*base, info->ioreg, offset);
if (winbond_sio_reg_btest(*base, info->invreg, offset))
val = !val;
if (val)
winbond_sio_reg_bset(*base, info->datareg, offset);
else
winbond_sio_reg_bclear(*base, info->datareg, offset);
winbond_sio_leave(*base);
return 0;
}
static void winbond_gpio_set(struct gpio_chip *gc, unsigned int offset,
int val)
{
unsigned long *base = gpiochip_get_data(gc);
const struct winbond_gpio_info *info;
if (!winbond_gpio_get_info(&offset, &info))
return;
if (winbond_sio_enter(*base) != 0)
return;
winbond_sio_select_logical(*base, info->dev);
if (winbond_sio_reg_btest(*base, info->invreg, offset))
val = !val;
if (val)
winbond_sio_reg_bset(*base, info->datareg, offset);
else
winbond_sio_reg_bclear(*base, info->datareg, offset);
winbond_sio_leave(*base);
}
static struct gpio_chip winbond_gpio_chip = {
.base = -1,
.label = WB_GPIO_DRIVER_NAME,
.owner = THIS_MODULE,
.can_sleep = true,
.get = winbond_gpio_get,
.direction_input = winbond_gpio_direction_in,
.set = winbond_gpio_set,
.direction_output = winbond_gpio_direction_out,
};
static void winbond_gpio_configure_port0_pins(unsigned long base)
{
unsigned int val;
val = winbond_sio_reg_read(base, WB_SIO_REG_GPIO1_MF);
if ((val & WB_SIO_REG_G1MF_FS_MASK) == WB_SIO_REG_G1MF_FS_GPIO1)
return;
pr_warn("GPIO1 pins were connected to something else (%.2x), fixing\n",
val);
val &= ~WB_SIO_REG_G1MF_FS_MASK;
val |= WB_SIO_REG_G1MF_FS_GPIO1;
winbond_sio_reg_write(base, WB_SIO_REG_GPIO1_MF, val);
}
static void winbond_gpio_configure_port1_check_i2c(unsigned long base)
{
params.i2cgpio = !winbond_sio_reg_btest(base, WB_SIO_REG_I2C_PS,
WB_SIO_REG_I2CPS_I2CFS);
if (!params.i2cgpio)
pr_warn("disabling GPIO2.5 and GPIO2.6 as I2C is enabled\n");
}
static bool winbond_gpio_configure_port(unsigned long base, unsigned int idx)
{
const struct winbond_gpio_info *info = &winbond_gpio_infos[idx];
const struct winbond_gpio_port_conflict *conflict = &info->conflict;
/* is there a possible conflicting device defined? */
if (conflict->name != NULL) {
if (conflict->dev != WB_SIO_DEV_NONE)
winbond_sio_select_logical(base, conflict->dev);
if (winbond_sio_reg_btest(base, conflict->testreg,
conflict->testbit)) {
if (conflict->warnonly)
pr_warn("enabled GPIO%u share pins with active %s\n",
idx + 1, conflict->name);
else {
pr_warn("disabling GPIO%u as %s is enabled\n",
idx + 1, conflict->name);
return false;
}
}
}
/* GPIO1 and GPIO2 need some (additional) special handling */
if (idx == 0)
winbond_gpio_configure_port0_pins(base);
else if (idx == 1)
winbond_gpio_configure_port1_check_i2c(base);
winbond_sio_select_logical(base, info->dev);
winbond_sio_reg_bset(base, info->enablereg, info->enablebit);
if (params.ppgpios & BIT(idx))
winbond_sio_reg_bset(base, info->outputreg,
info->outputppbit);
else if (params.odgpios & BIT(idx))
winbond_sio_reg_bclear(base, info->outputreg,
info->outputppbit);
else
pr_notice("GPIO%u pins are %s\n", idx + 1,
winbond_sio_reg_btest(base, info->outputreg,
info->outputppbit) ?
"push-pull" :
"open drain");
return true;
}
static int winbond_gpio_configure(unsigned long base)
{
unsigned long i;
for_each_set_bit(i, ¶ms.gpios, BITS_PER_LONG)
if (!winbond_gpio_configure_port(base, i))
__clear_bit(i, ¶ms.gpios);
if (!params.gpios) {
pr_err("please use 'gpios' module parameter to select some active GPIO ports to enable\n");
return -EINVAL;
}
return 0;
}
static int winbond_gpio_check_chip(unsigned long base)
{
int ret;
unsigned int chip;
ret = winbond_sio_enter(base);
if (ret)
return ret;
chip = winbond_sio_reg_read(base, WB_SIO_REG_CHIP_MSB) << 8;
chip |= winbond_sio_reg_read(base, WB_SIO_REG_CHIP_LSB);
pr_notice("chip ID at %lx is %.4x\n", base, chip);
if ((chip & WB_SIO_CHIP_ID_W83627UHG_MASK) !=
WB_SIO_CHIP_ID_W83627UHG) {
pr_err("not an our chip\n");
ret = -ENODEV;
}
winbond_sio_leave(base);
return ret;
}
static int winbond_gpio_imatch(struct device *dev, unsigned int id)
{
unsigned long gpios_rem;
int ret;
gpios_rem = params.gpios & ~GENMASK(ARRAY_SIZE(winbond_gpio_infos) - 1,
0);
if (gpios_rem) {
pr_warn("unknown ports (%lx) enabled in GPIO ports bitmask\n",
gpios_rem);
params.gpios &= ~gpios_rem;
}
if (params.ppgpios & params.odgpios) {
pr_err("some GPIO ports are set both to push-pull and open drain mode at the same time\n");
return 0;
}
if (params.base != 0)
return winbond_gpio_check_chip(params.base) == 0;
/*
* if the 'base' module parameter is unset probe two chip default
* I/O port bases
*/
params.base = WB_SIO_BASE;
ret = winbond_gpio_check_chip(params.base);
if (ret == 0)
return 1;
if (ret != -ENODEV && ret != -EBUSY)
return 0;
params.base = WB_SIO_BASE_HIGH;
return winbond_gpio_check_chip(params.base) == 0;
}
static int winbond_gpio_iprobe(struct device *dev, unsigned int id)
{
int ret;
if (params.base == 0)
return -EINVAL;
ret = winbond_sio_enter(params.base);
if (ret)
return ret;
ret = winbond_gpio_configure(params.base);
winbond_sio_leave(params.base);
if (ret)
return ret;
/*
* Add 8 gpios for every GPIO port that was enabled in gpios
* module parameter (that wasn't disabled earlier in
* winbond_gpio_configure() & co. due to, for example, a pin conflict).
*/
winbond_gpio_chip.ngpio = hweight_long(params.gpios) * 8;
/*
* GPIO6 port has only 5 pins, so if it is enabled we have to adjust
* the total count appropriately
*/
if (params.gpios & BIT(5))
winbond_gpio_chip.ngpio -= (8 - 5);
winbond_gpio_chip.parent = dev;
return devm_gpiochip_add_data(dev, &winbond_gpio_chip, ¶ms.base);
}
static struct isa_driver winbond_gpio_idriver = {
.driver = {
.name = WB_GPIO_DRIVER_NAME,
},
.match = winbond_gpio_imatch,
.probe = winbond_gpio_iprobe,
};
module_isa_driver(winbond_gpio_idriver, 1);
module_param_named(base, params.base, ulong, 0444);
MODULE_PARM_DESC(base,
"I/O port base (when unset - probe chip default ones)");
/* This parameter sets which GPIO devices (ports) we enable */
module_param_named(gpios, params.gpios, ulong, 0444);
MODULE_PARM_DESC(gpios,
"bitmask of GPIO ports to enable (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
/*
* These two parameters below set how we configure GPIO ports output drivers.
* It can't be a one bitmask since we need three values per port: push-pull,
* open-drain and keep as-is (this is the default).
*/
module_param_named(ppgpios, params.ppgpios, ulong, 0444);
MODULE_PARM_DESC(ppgpios,
"bitmask of GPIO ports to set to push-pull mode (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
module_param_named(odgpios, params.odgpios, ulong, 0444);
MODULE_PARM_DESC(odgpios,
"bitmask of GPIO ports to set to open drain mode (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
/*
* GPIO2.0 and GPIO2.1 control a basic PC functionality that we
* don't allow tinkering with by default (it is very likely that the
* firmware owns these pins).
* These two parameters below allow overriding these prohibitions.
*/
module_param_named(pledgpio, params.pledgpio, bool, 0644);
MODULE_PARM_DESC(pledgpio,
"enable changing value of GPIO2.0 bit (Power LED), default no.");
module_param_named(beepgpio, params.beepgpio, bool, 0644);
MODULE_PARM_DESC(beepgpio,
"enable changing value of GPIO2.1 bit (BEEP), default no.");
MODULE_AUTHOR("Maciej S. Szmigiero <[email protected]>");
MODULE_DESCRIPTION("GPIO interface for Winbond Super I/O chips");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-winbond.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Turris Mox Moxtet GPIO expander
*
* Copyright (C) 2018 Marek Behún <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/moxtet.h>
#include <linux/module.h>
#define MOXTET_GPIO_NGPIOS 12
#define MOXTET_GPIO_INPUTS 4
struct moxtet_gpio_desc {
u16 in_mask;
u16 out_mask;
};
static const struct moxtet_gpio_desc descs[] = {
[TURRIS_MOX_MODULE_SFP] = {
.in_mask = GENMASK(2, 0),
.out_mask = GENMASK(5, 4),
},
};
struct moxtet_gpio_chip {
struct device *dev;
struct gpio_chip gpio_chip;
const struct moxtet_gpio_desc *desc;
};
static int moxtet_gpio_get_value(struct gpio_chip *gc, unsigned int offset)
{
struct moxtet_gpio_chip *chip = gpiochip_get_data(gc);
int ret;
if (chip->desc->in_mask & BIT(offset)) {
ret = moxtet_device_read(chip->dev);
} else if (chip->desc->out_mask & BIT(offset)) {
ret = moxtet_device_written(chip->dev);
if (ret >= 0)
ret <<= MOXTET_GPIO_INPUTS;
} else {
return -EINVAL;
}
if (ret < 0)
return ret;
return !!(ret & BIT(offset));
}
static void moxtet_gpio_set_value(struct gpio_chip *gc, unsigned int offset,
int val)
{
struct moxtet_gpio_chip *chip = gpiochip_get_data(gc);
int state;
state = moxtet_device_written(chip->dev);
if (state < 0)
return;
offset -= MOXTET_GPIO_INPUTS;
if (val)
state |= BIT(offset);
else
state &= ~BIT(offset);
moxtet_device_write(chip->dev, state);
}
static int moxtet_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
struct moxtet_gpio_chip *chip = gpiochip_get_data(gc);
/* All lines are hard wired to be either input or output, not both. */
if (chip->desc->in_mask & BIT(offset))
return GPIO_LINE_DIRECTION_IN;
else if (chip->desc->out_mask & BIT(offset))
return GPIO_LINE_DIRECTION_OUT;
else
return -EINVAL;
}
static int moxtet_gpio_direction_input(struct gpio_chip *gc,
unsigned int offset)
{
struct moxtet_gpio_chip *chip = gpiochip_get_data(gc);
if (chip->desc->in_mask & BIT(offset))
return 0;
else if (chip->desc->out_mask & BIT(offset))
return -ENOTSUPP;
else
return -EINVAL;
}
static int moxtet_gpio_direction_output(struct gpio_chip *gc,
unsigned int offset, int val)
{
struct moxtet_gpio_chip *chip = gpiochip_get_data(gc);
if (chip->desc->out_mask & BIT(offset))
moxtet_gpio_set_value(gc, offset, val);
else if (chip->desc->in_mask & BIT(offset))
return -ENOTSUPP;
else
return -EINVAL;
return 0;
}
static int moxtet_gpio_probe(struct device *dev)
{
struct moxtet_gpio_chip *chip;
struct device_node *nc = dev->of_node;
int id;
id = to_moxtet_device(dev)->id;
if (id >= ARRAY_SIZE(descs)) {
dev_err(dev, "%pOF Moxtet device id 0x%x is not supported by gpio-moxtet driver\n",
nc, id);
return -ENOTSUPP;
}
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->dev = dev;
chip->gpio_chip.parent = dev;
chip->desc = &descs[id];
dev_set_drvdata(dev, chip);
chip->gpio_chip.label = dev_name(dev);
chip->gpio_chip.get_direction = moxtet_gpio_get_direction;
chip->gpio_chip.direction_input = moxtet_gpio_direction_input;
chip->gpio_chip.direction_output = moxtet_gpio_direction_output;
chip->gpio_chip.get = moxtet_gpio_get_value;
chip->gpio_chip.set = moxtet_gpio_set_value;
chip->gpio_chip.base = -1;
chip->gpio_chip.ngpio = MOXTET_GPIO_NGPIOS;
chip->gpio_chip.can_sleep = true;
chip->gpio_chip.owner = THIS_MODULE;
return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip);
}
static const struct of_device_id moxtet_gpio_dt_ids[] = {
{ .compatible = "cznic,moxtet-gpio", },
{},
};
MODULE_DEVICE_TABLE(of, moxtet_gpio_dt_ids);
static const enum turris_mox_module_id moxtet_gpio_module_table[] = {
TURRIS_MOX_MODULE_SFP,
0,
};
static struct moxtet_driver moxtet_gpio_driver = {
.driver = {
.name = "moxtet-gpio",
.of_match_table = moxtet_gpio_dt_ids,
.probe = moxtet_gpio_probe,
},
.id_table = moxtet_gpio_module_table,
};
module_moxtet_driver(moxtet_gpio_driver);
MODULE_AUTHOR("Marek Behun <[email protected]>");
MODULE_DESCRIPTION("Turris Mox Moxtet GPIO expander");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-moxtet.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Spreadtrum Communications Inc.
* Copyright (C) 2018 Linaro Ltd.
*/
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
/* EIC registers definition */
#define SPRD_EIC_DBNC_DATA 0x0
#define SPRD_EIC_DBNC_DMSK 0x4
#define SPRD_EIC_DBNC_IEV 0x14
#define SPRD_EIC_DBNC_IE 0x18
#define SPRD_EIC_DBNC_RIS 0x1c
#define SPRD_EIC_DBNC_MIS 0x20
#define SPRD_EIC_DBNC_IC 0x24
#define SPRD_EIC_DBNC_TRIG 0x28
#define SPRD_EIC_DBNC_CTRL0 0x40
#define SPRD_EIC_LATCH_INTEN 0x0
#define SPRD_EIC_LATCH_INTRAW 0x4
#define SPRD_EIC_LATCH_INTMSK 0x8
#define SPRD_EIC_LATCH_INTCLR 0xc
#define SPRD_EIC_LATCH_INTPOL 0x10
#define SPRD_EIC_LATCH_INTMODE 0x14
#define SPRD_EIC_ASYNC_INTIE 0x0
#define SPRD_EIC_ASYNC_INTRAW 0x4
#define SPRD_EIC_ASYNC_INTMSK 0x8
#define SPRD_EIC_ASYNC_INTCLR 0xc
#define SPRD_EIC_ASYNC_INTMODE 0x10
#define SPRD_EIC_ASYNC_INTBOTH 0x14
#define SPRD_EIC_ASYNC_INTPOL 0x18
#define SPRD_EIC_ASYNC_DATA 0x1c
#define SPRD_EIC_SYNC_INTIE 0x0
#define SPRD_EIC_SYNC_INTRAW 0x4
#define SPRD_EIC_SYNC_INTMSK 0x8
#define SPRD_EIC_SYNC_INTCLR 0xc
#define SPRD_EIC_SYNC_INTMODE 0x10
#define SPRD_EIC_SYNC_INTBOTH 0x14
#define SPRD_EIC_SYNC_INTPOL 0x18
#define SPRD_EIC_SYNC_DATA 0x1c
/*
* The digital-chip EIC controller can support maximum 3 banks, and each bank
* contains 8 EICs.
*/
#define SPRD_EIC_MAX_BANK 3
#define SPRD_EIC_PER_BANK_NR 8
#define SPRD_EIC_DATA_MASK GENMASK(7, 0)
#define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
#define SPRD_EIC_DBNC_MASK GENMASK(11, 0)
/*
* The Spreadtrum EIC (external interrupt controller) can be used only in
* input mode to generate interrupts if detecting input signals.
*
* The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
* debounce EIC, latch EIC, async EIC and sync EIC,
*
* The debounce EIC is used to capture the input signals' stable status
* (millisecond resolution) and a single-trigger mechanism is introduced
* into this sub-module to enhance the input event detection reliability.
* The debounce range is from 1ms to 4s with a step size of 1ms.
*
* The latch EIC is used to latch some special power down signals and
* generate interrupts, since the latch EIC does not depend on the APB clock
* to capture signals.
*
* The async EIC uses a 32k clock to capture the short signals (microsecond
* resolution) to generate interrupts by level or edge trigger.
*
* The EIC-sync is similar with GPIO's input function, which is a synchronized
* signal input register.
*/
enum sprd_eic_type {
SPRD_EIC_DEBOUNCE,
SPRD_EIC_LATCH,
SPRD_EIC_ASYNC,
SPRD_EIC_SYNC,
SPRD_EIC_MAX,
};
struct sprd_eic {
struct gpio_chip chip;
void __iomem *base[SPRD_EIC_MAX_BANK];
enum sprd_eic_type type;
spinlock_t lock;
int irq;
};
struct sprd_eic_variant_data {
enum sprd_eic_type type;
u32 num_eics;
};
static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
"eic-debounce", "eic-latch", "eic-async",
"eic-sync",
};
static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
.type = SPRD_EIC_DEBOUNCE,
.num_eics = 8,
};
static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
.type = SPRD_EIC_LATCH,
.num_eics = 8,
};
static const struct sprd_eic_variant_data sc9860_eic_async_data = {
.type = SPRD_EIC_ASYNC,
.num_eics = 8,
};
static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
.type = SPRD_EIC_SYNC,
.num_eics = 8,
};
static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
unsigned int bank)
{
if (bank >= SPRD_EIC_MAX_BANK)
return NULL;
return sprd_eic->base[bank];
}
static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
u16 reg, unsigned int val)
{
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
void __iomem *base =
sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
unsigned long flags;
u32 tmp;
spin_lock_irqsave(&sprd_eic->lock, flags);
tmp = readl_relaxed(base + reg);
if (val)
tmp |= BIT(SPRD_EIC_BIT(offset));
else
tmp &= ~BIT(SPRD_EIC_BIT(offset));
writel_relaxed(tmp, base + reg);
spin_unlock_irqrestore(&sprd_eic->lock, flags);
}
static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
{
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
void __iomem *base =
sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
}
static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
{
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
return 0;
}
static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
{
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
}
static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
{
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
switch (sprd_eic->type) {
case SPRD_EIC_DEBOUNCE:
return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
case SPRD_EIC_ASYNC:
return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);
case SPRD_EIC_SYNC:
return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);
default:
return -ENOTSUPP;
}
}
static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
{
/* EICs are always input, nothing need to do here. */
return 0;
}
static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
{
/* EICs are always input, nothing need to do here. */
}
static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
unsigned int debounce)
{
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
void __iomem *base =
sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
writel_relaxed(value, base + reg);
return 0;
}
static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
unsigned long param = pinconf_to_config_param(config);
u32 arg = pinconf_to_config_argument(config);
if (param == PIN_CONFIG_INPUT_DEBOUNCE)
return sprd_eic_set_debounce(chip, offset, arg);
return -ENOTSUPP;
}
static void sprd_eic_irq_mask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
u32 offset = irqd_to_hwirq(data);
switch (sprd_eic->type) {
case SPRD_EIC_DEBOUNCE:
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
break;
case SPRD_EIC_LATCH:
sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
break;
case SPRD_EIC_ASYNC:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
break;
case SPRD_EIC_SYNC:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
break;
default:
dev_err(chip->parent, "Unsupported EIC type.\n");
}
gpiochip_disable_irq(chip, offset);
}
static void sprd_eic_irq_unmask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
u32 offset = irqd_to_hwirq(data);
gpiochip_enable_irq(chip, offset);
switch (sprd_eic->type) {
case SPRD_EIC_DEBOUNCE:
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
break;
case SPRD_EIC_LATCH:
sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
break;
case SPRD_EIC_ASYNC:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
break;
case SPRD_EIC_SYNC:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
break;
default:
dev_err(chip->parent, "Unsupported EIC type.\n");
}
}
static void sprd_eic_irq_ack(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
u32 offset = irqd_to_hwirq(data);
switch (sprd_eic->type) {
case SPRD_EIC_DEBOUNCE:
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
break;
case SPRD_EIC_LATCH:
sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
break;
case SPRD_EIC_ASYNC:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
break;
case SPRD_EIC_SYNC:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
break;
default:
dev_err(chip->parent, "Unsupported EIC type.\n");
}
}
static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
u32 offset = irqd_to_hwirq(data);
int state;
switch (sprd_eic->type) {
case SPRD_EIC_DEBOUNCE:
switch (flow_type) {
case IRQ_TYPE_LEVEL_HIGH:
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
break;
case IRQ_TYPE_LEVEL_LOW:
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
break;
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_EDGE_BOTH:
state = sprd_eic_get(chip, offset);
if (state)
sprd_eic_update(chip, offset,
SPRD_EIC_DBNC_IEV, 0);
else
sprd_eic_update(chip, offset,
SPRD_EIC_DBNC_IEV, 1);
break;
default:
return -ENOTSUPP;
}
irq_set_handler_locked(data, handle_level_irq);
break;
case SPRD_EIC_LATCH:
switch (flow_type) {
case IRQ_TYPE_LEVEL_HIGH:
sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
break;
case IRQ_TYPE_LEVEL_LOW:
sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
break;
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_EDGE_BOTH:
state = sprd_eic_get(chip, offset);
if (state)
sprd_eic_update(chip, offset,
SPRD_EIC_LATCH_INTPOL, 0);
else
sprd_eic_update(chip, offset,
SPRD_EIC_LATCH_INTPOL, 1);
break;
default:
return -ENOTSUPP;
}
irq_set_handler_locked(data, handle_level_irq);
break;
case SPRD_EIC_ASYNC:
switch (flow_type) {
case IRQ_TYPE_EDGE_RISING:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_BOTH:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
irq_set_handler_locked(data, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
irq_set_handler_locked(data, handle_level_irq);
break;
default:
return -ENOTSUPP;
}
break;
case SPRD_EIC_SYNC:
switch (flow_type) {
case IRQ_TYPE_EDGE_RISING:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_BOTH:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
irq_set_handler_locked(data, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
irq_set_handler_locked(data, handle_level_irq);
break;
default:
return -ENOTSUPP;
}
break;
default:
dev_err(chip->parent, "Unsupported EIC type.\n");
return -ENOTSUPP;
}
return 0;
}
static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq,
unsigned int offset)
{
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
struct irq_data *data = irq_get_irq_data(irq);
u32 trigger = irqd_get_trigger_type(data);
int state, post_state;
/*
* The debounce EIC and latch EIC can only support level trigger, so we
* can toggle the level trigger to emulate the edge trigger.
*/
if ((sprd_eic->type != SPRD_EIC_DEBOUNCE &&
sprd_eic->type != SPRD_EIC_LATCH) ||
!(trigger & IRQ_TYPE_EDGE_BOTH))
return;
sprd_eic_irq_mask(data);
state = sprd_eic_get(chip, offset);
retry:
switch (sprd_eic->type) {
case SPRD_EIC_DEBOUNCE:
if (state)
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
else
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
break;
case SPRD_EIC_LATCH:
if (state)
sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
else
sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
break;
default:
sprd_eic_irq_unmask(data);
return;
}
post_state = sprd_eic_get(chip, offset);
if (state != post_state) {
dev_warn(chip->parent, "EIC level was changed.\n");
state = post_state;
goto retry;
}
sprd_eic_irq_unmask(data);
}
static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data)
{
enum sprd_eic_type type = *(enum sprd_eic_type *)data;
return !strcmp(chip->label, sprd_eic_label_name[type]);
}
static void sprd_eic_handle_one_type(struct gpio_chip *chip)
{
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
u32 bank, n, girq;
for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
unsigned long reg;
switch (sprd_eic->type) {
case SPRD_EIC_DEBOUNCE:
reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
SPRD_EIC_DATA_MASK;
break;
case SPRD_EIC_LATCH:
reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
SPRD_EIC_DATA_MASK;
break;
case SPRD_EIC_ASYNC:
reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
SPRD_EIC_DATA_MASK;
break;
case SPRD_EIC_SYNC:
reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
SPRD_EIC_DATA_MASK;
break;
default:
dev_err(chip->parent, "Unsupported EIC type.\n");
return;
}
for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) {
u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;
girq = irq_find_mapping(chip->irq.domain, offset);
generic_handle_irq(girq);
sprd_eic_toggle_trigger(chip, girq, offset);
}
}
}
static void sprd_eic_irq_handler(struct irq_desc *desc)
{
struct irq_chip *ic = irq_desc_get_chip(desc);
struct gpio_chip *chip;
enum sprd_eic_type type;
chained_irq_enter(ic, desc);
/*
* Since the digital-chip EIC 4 sub-modules (debounce, latch, async
* and sync) share one same interrupt line, we should iterate each
* EIC module to check if there are EIC interrupts were triggered.
*/
for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) {
chip = gpiochip_find(&type, sprd_eic_match_chip_by_type);
if (!chip)
continue;
sprd_eic_handle_one_type(chip);
}
chained_irq_exit(ic, desc);
}
static const struct irq_chip sprd_eic_irq = {
.name = "sprd-eic",
.irq_ack = sprd_eic_irq_ack,
.irq_mask = sprd_eic_irq_mask,
.irq_unmask = sprd_eic_irq_unmask,
.irq_set_type = sprd_eic_irq_set_type,
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int sprd_eic_probe(struct platform_device *pdev)
{
const struct sprd_eic_variant_data *pdata;
struct gpio_irq_chip *irq;
struct sprd_eic *sprd_eic;
struct resource *res;
int ret, i;
pdata = of_device_get_match_data(&pdev->dev);
if (!pdata) {
dev_err(&pdev->dev, "No matching driver data found.\n");
return -EINVAL;
}
sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL);
if (!sprd_eic)
return -ENOMEM;
spin_lock_init(&sprd_eic->lock);
sprd_eic->type = pdata->type;
sprd_eic->irq = platform_get_irq(pdev, 0);
if (sprd_eic->irq < 0)
return sprd_eic->irq;
for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
/*
* We can have maximum 3 banks EICs, and each EIC has
* its own base address. But some platform maybe only
* have one bank EIC, thus base[1] and base[2] can be
* optional.
*/
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
if (!res)
break;
sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(sprd_eic->base[i]))
return PTR_ERR(sprd_eic->base[i]);
}
sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
sprd_eic->chip.ngpio = pdata->num_eics;
sprd_eic->chip.base = -1;
sprd_eic->chip.parent = &pdev->dev;
sprd_eic->chip.direction_input = sprd_eic_direction_input;
switch (sprd_eic->type) {
case SPRD_EIC_DEBOUNCE:
sprd_eic->chip.request = sprd_eic_request;
sprd_eic->chip.free = sprd_eic_free;
sprd_eic->chip.set_config = sprd_eic_set_config;
sprd_eic->chip.set = sprd_eic_set;
fallthrough;
case SPRD_EIC_ASYNC:
case SPRD_EIC_SYNC:
sprd_eic->chip.get = sprd_eic_get;
break;
case SPRD_EIC_LATCH:
default:
break;
}
irq = &sprd_eic->chip.irq;
gpio_irq_chip_set_chip(irq, &sprd_eic_irq);
irq->handler = handle_bad_irq;
irq->default_type = IRQ_TYPE_NONE;
irq->parent_handler = sprd_eic_irq_handler;
irq->parent_handler_data = sprd_eic;
irq->num_parents = 1;
irq->parents = &sprd_eic->irq;
ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic);
if (ret < 0) {
dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
return ret;
}
return 0;
}
static const struct of_device_id sprd_eic_of_match[] = {
{
.compatible = "sprd,sc9860-eic-debounce",
.data = &sc9860_eic_dbnc_data,
},
{
.compatible = "sprd,sc9860-eic-latch",
.data = &sc9860_eic_latch_data,
},
{
.compatible = "sprd,sc9860-eic-async",
.data = &sc9860_eic_async_data,
},
{
.compatible = "sprd,sc9860-eic-sync",
.data = &sc9860_eic_sync_data,
},
{
/* end of list */
}
};
MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
static struct platform_driver sprd_eic_driver = {
.probe = sprd_eic_probe,
.driver = {
.name = "sprd-eic",
.of_match_table = sprd_eic_of_match,
},
};
module_platform_driver(sprd_eic_driver);
MODULE_DESCRIPTION("Spreadtrum EIC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-eic-sprd.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* GPIO driver for Exar XR17V35X chip
*
* Copyright (C) 2015 Sudip Mukherjee <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/idr.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define EXAR_OFFSET_MPIOLVL_LO 0x90
#define EXAR_OFFSET_MPIOSEL_LO 0x93
#define EXAR_OFFSET_MPIOLVL_HI 0x96
#define EXAR_OFFSET_MPIOSEL_HI 0x99
/*
* The Device Configuration and UART Configuration Registers
* for each UART channel take 1KB of memory address space.
*/
#define EXAR_UART_CHANNEL_SIZE 0x400
#define DRIVER_NAME "gpio_exar"
static DEFINE_IDA(ida_index);
struct exar_gpio_chip {
struct gpio_chip gpio_chip;
struct regmap *regmap;
int index;
char name[20];
unsigned int first_pin;
/*
* The offset to the cascaded device's (if existing)
* Device Configuration Registers.
*/
unsigned int cascaded_offset;
};
static unsigned int
exar_offset_to_sel_addr(struct exar_gpio_chip *exar_gpio, unsigned int offset)
{
unsigned int pin = exar_gpio->first_pin + (offset % 16);
unsigned int cascaded = offset / 16;
unsigned int addr = pin / 8 ? EXAR_OFFSET_MPIOSEL_HI : EXAR_OFFSET_MPIOSEL_LO;
return addr + (cascaded ? exar_gpio->cascaded_offset : 0);
}
static unsigned int
exar_offset_to_lvl_addr(struct exar_gpio_chip *exar_gpio, unsigned int offset)
{
unsigned int pin = exar_gpio->first_pin + (offset % 16);
unsigned int cascaded = offset / 16;
unsigned int addr = pin / 8 ? EXAR_OFFSET_MPIOLVL_HI : EXAR_OFFSET_MPIOLVL_LO;
return addr + (cascaded ? exar_gpio->cascaded_offset : 0);
}
static unsigned int
exar_offset_to_bit(struct exar_gpio_chip *exar_gpio, unsigned int offset)
{
unsigned int pin = exar_gpio->first_pin + (offset % 16);
return pin % 8;
}
static int exar_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
unsigned int addr = exar_offset_to_sel_addr(exar_gpio, offset);
unsigned int bit = exar_offset_to_bit(exar_gpio, offset);
if (regmap_test_bits(exar_gpio->regmap, addr, BIT(bit)))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static int exar_get_value(struct gpio_chip *chip, unsigned int offset)
{
struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
unsigned int addr = exar_offset_to_lvl_addr(exar_gpio, offset);
unsigned int bit = exar_offset_to_bit(exar_gpio, offset);
return !!(regmap_test_bits(exar_gpio->regmap, addr, BIT(bit)));
}
static void exar_set_value(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
unsigned int addr = exar_offset_to_lvl_addr(exar_gpio, offset);
unsigned int bit = exar_offset_to_bit(exar_gpio, offset);
if (value)
regmap_set_bits(exar_gpio->regmap, addr, BIT(bit));
else
regmap_clear_bits(exar_gpio->regmap, addr, BIT(bit));
}
static int exar_direction_output(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
unsigned int addr = exar_offset_to_sel_addr(exar_gpio, offset);
unsigned int bit = exar_offset_to_bit(exar_gpio, offset);
exar_set_value(chip, offset, value);
regmap_clear_bits(exar_gpio->regmap, addr, BIT(bit));
return 0;
}
static int exar_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
unsigned int addr = exar_offset_to_sel_addr(exar_gpio, offset);
unsigned int bit = exar_offset_to_bit(exar_gpio, offset);
regmap_set_bits(exar_gpio->regmap, addr, BIT(bit));
return 0;
}
static void exar_devm_ida_free(void *data)
{
struct exar_gpio_chip *exar_gpio = data;
ida_free(&ida_index, exar_gpio->index);
}
static const struct regmap_config exar_regmap_config = {
.name = "exar-gpio",
.reg_bits = 16,
.val_bits = 8,
.io_port = true,
};
static int gpio_exar_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct pci_dev *pcidev = to_pci_dev(dev->parent);
struct exar_gpio_chip *exar_gpio;
u32 first_pin, ngpios;
void __iomem *p;
int index, ret;
/*
* The UART driver must have mapped region 0 prior to registering this
* device - use it.
*/
p = pcim_iomap_table(pcidev)[0];
if (!p)
return -ENOMEM;
ret = device_property_read_u32(dev, "exar,first-pin", &first_pin);
if (ret)
return ret;
ret = device_property_read_u32(dev, "ngpios", &ngpios);
if (ret)
return ret;
exar_gpio = devm_kzalloc(dev, sizeof(*exar_gpio), GFP_KERNEL);
if (!exar_gpio)
return -ENOMEM;
/*
* If cascaded, secondary xr17v354 or xr17v358 have the same amount
* of MPIOs as their primaries and the last 4 bits of the primary's
* PCI Device ID is the number of its UART channels.
*/
if (pcidev->device & GENMASK(15, 12)) {
ngpios += ngpios;
exar_gpio->cascaded_offset = (pcidev->device & GENMASK(3, 0)) *
EXAR_UART_CHANNEL_SIZE;
}
/*
* We don't need to check the return values of mmio regmap operations (unless
* the regmap has a clock attached which is not the case here).
*/
exar_gpio->regmap = devm_regmap_init_mmio(dev, p, &exar_regmap_config);
if (IS_ERR(exar_gpio->regmap))
return PTR_ERR(exar_gpio->regmap);
index = ida_alloc(&ida_index, GFP_KERNEL);
if (index < 0)
return index;
ret = devm_add_action_or_reset(dev, exar_devm_ida_free, exar_gpio);
if (ret)
return ret;
sprintf(exar_gpio->name, "exar_gpio%d", index);
exar_gpio->gpio_chip.label = exar_gpio->name;
exar_gpio->gpio_chip.parent = dev;
exar_gpio->gpio_chip.direction_output = exar_direction_output;
exar_gpio->gpio_chip.direction_input = exar_direction_input;
exar_gpio->gpio_chip.get_direction = exar_get_direction;
exar_gpio->gpio_chip.get = exar_get_value;
exar_gpio->gpio_chip.set = exar_set_value;
exar_gpio->gpio_chip.base = -1;
exar_gpio->gpio_chip.ngpio = ngpios;
exar_gpio->index = index;
exar_gpio->first_pin = first_pin;
ret = devm_gpiochip_add_data(dev, &exar_gpio->gpio_chip, exar_gpio);
if (ret)
return ret;
return 0;
}
static struct platform_driver gpio_exar_driver = {
.probe = gpio_exar_probe,
.driver = {
.name = DRIVER_NAME,
},
};
module_platform_driver(gpio_exar_driver);
MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_DESCRIPTION("Exar GPIO driver");
MODULE_AUTHOR("Sudip Mukherjee <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-exar.c |
// SPDX-License-Identifier: GPL-2.0
/*
* GPIO driver for TI TPS65219 PMICs
*
* Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/mfd/tps65219.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define TPS65219_GPIO0_DIR_MASK BIT(3)
#define TPS65219_GPIO0_OFFSET 2
#define TPS65219_GPIO0_IDX 0
#define TPS65219_GPIO_DIR_IN 1
#define TPS65219_GPIO_DIR_OUT 0
struct tps65219_gpio {
struct gpio_chip gpio_chip;
struct tps65219 *tps;
};
static int tps65219_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
struct tps65219_gpio *gpio = gpiochip_get_data(gc);
int ret, val;
if (offset != TPS65219_GPIO0_IDX)
return GPIO_LINE_DIRECTION_OUT;
ret = regmap_read(gpio->tps->regmap, TPS65219_REG_MFP_1_CONFIG, &val);
if (ret)
return ret;
return !!(val & TPS65219_GPIO0_DIR_MASK);
}
static int tps65219_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct tps65219_gpio *gpio = gpiochip_get_data(gc);
struct device *dev = gpio->tps->dev;
int ret, val;
if (offset != TPS65219_GPIO0_IDX) {
dev_err(dev, "GPIO%d is output only, cannot get\n", offset);
return -ENOTSUPP;
}
ret = regmap_read(gpio->tps->regmap, TPS65219_REG_MFP_CTRL, &val);
if (ret)
return ret;
ret = !!(val & BIT(TPS65219_MFP_GPIO_STATUS_MASK));
dev_warn(dev, "GPIO%d = %d, MULTI_DEVICE_ENABLE, not a standard GPIO\n", offset, ret);
/*
* Depending on NVM config, return an error if direction is output, otherwise the GPIO0
* status bit.
*/
if (tps65219_gpio_get_direction(gc, offset) == TPS65219_GPIO_DIR_OUT)
return -ENOTSUPP;
return ret;
}
static void tps65219_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
{
struct tps65219_gpio *gpio = gpiochip_get_data(gc);
struct device *dev = gpio->tps->dev;
int v, mask, bit;
bit = (offset == TPS65219_GPIO0_IDX) ? TPS65219_GPIO0_OFFSET : offset - 1;
mask = BIT(bit);
v = value ? mask : 0;
if (regmap_update_bits(gpio->tps->regmap, TPS65219_REG_GENERAL_CONFIG, mask, v))
dev_err(dev, "GPIO%d, set to value %d failed.\n", offset, value);
}
static int tps65219_gpio_change_direction(struct gpio_chip *gc, unsigned int offset,
unsigned int direction)
{
struct tps65219_gpio *gpio = gpiochip_get_data(gc);
struct device *dev = gpio->tps->dev;
/*
* Documentation is stating that GPIO0 direction must not be changed in Linux:
* Table 8-34. MFP_1_CONFIG(3): MULTI_DEVICE_ENABLE, should only be changed in INITIALIZE
* state (prior to ON Request).
* Set statically by NVM, changing direction in application can cause a hang.
* Below can be used for test purpose only.
*/
if (IS_ENABLED(CONFIG_DEBUG_GPIO)) {
int ret = regmap_update_bits(gpio->tps->regmap, TPS65219_REG_MFP_1_CONFIG,
TPS65219_GPIO0_DIR_MASK, direction);
if (ret) {
dev_err(dev,
"GPIO DEBUG enabled: Fail to change direction to %u for GPIO%d.\n",
direction, offset);
return ret;
}
}
dev_err(dev,
"GPIO%d direction set by NVM, change to %u failed, not allowed by specification\n",
offset, direction);
return -ENOTSUPP;
}
static int tps65219_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
{
struct tps65219_gpio *gpio = gpiochip_get_data(gc);
struct device *dev = gpio->tps->dev;
if (offset != TPS65219_GPIO0_IDX) {
dev_err(dev, "GPIO%d is output only, cannot change to input\n", offset);
return -ENOTSUPP;
}
if (tps65219_gpio_get_direction(gc, offset) == TPS65219_GPIO_DIR_IN)
return 0;
return tps65219_gpio_change_direction(gc, offset, TPS65219_GPIO_DIR_IN);
}
static int tps65219_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
{
tps65219_gpio_set(gc, offset, value);
if (offset != TPS65219_GPIO0_IDX)
return 0;
if (tps65219_gpio_get_direction(gc, offset) == TPS65219_GPIO_DIR_OUT)
return 0;
return tps65219_gpio_change_direction(gc, offset, TPS65219_GPIO_DIR_OUT);
}
static const struct gpio_chip tps65219_template_chip = {
.label = "tps65219-gpio",
.owner = THIS_MODULE,
.get_direction = tps65219_gpio_get_direction,
.direction_input = tps65219_gpio_direction_input,
.direction_output = tps65219_gpio_direction_output,
.get = tps65219_gpio_get,
.set = tps65219_gpio_set,
.base = -1,
.ngpio = 3,
.can_sleep = true,
};
static int tps65219_gpio_probe(struct platform_device *pdev)
{
struct tps65219 *tps = dev_get_drvdata(pdev->dev.parent);
struct tps65219_gpio *gpio;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
gpio->tps = tps;
gpio->gpio_chip = tps65219_template_chip;
gpio->gpio_chip.parent = tps->dev;
return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio_chip, gpio);
}
static struct platform_driver tps65219_gpio_driver = {
.driver = {
.name = "tps65219-gpio",
},
.probe = tps65219_gpio_probe,
};
module_platform_driver(tps65219_gpio_driver);
MODULE_ALIAS("platform:tps65219-gpio");
MODULE_AUTHOR("Jonathan Cormier <[email protected]>");
MODULE_DESCRIPTION("TPS65219 GPIO driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-tps65219.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale vf610 GPIO support through PORT and GPIO
*
* Copyright (c) 2014 Toradex AG.
*
* Author: Stefan Agner <[email protected]>.
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>
#define VF610_GPIO_PER_PORT 32
struct fsl_gpio_soc_data {
/* SoCs has a Port Data Direction Register (PDDR) */
bool have_paddr;
};
struct vf610_gpio_port {
struct gpio_chip gc;
void __iomem *base;
void __iomem *gpio_base;
const struct fsl_gpio_soc_data *sdata;
u8 irqc[VF610_GPIO_PER_PORT];
struct clk *clk_port;
struct clk *clk_gpio;
int irq;
};
#define GPIO_PDOR 0x00
#define GPIO_PSOR 0x04
#define GPIO_PCOR 0x08
#define GPIO_PTOR 0x0c
#define GPIO_PDIR 0x10
#define GPIO_PDDR 0x14
#define PORT_PCR(n) ((n) * 0x4)
#define PORT_PCR_IRQC_OFFSET 16
#define PORT_ISFR 0xa0
#define PORT_DFER 0xc0
#define PORT_DFCR 0xc4
#define PORT_DFWR 0xc8
#define PORT_INT_OFF 0x0
#define PORT_INT_LOGIC_ZERO 0x8
#define PORT_INT_RISING_EDGE 0x9
#define PORT_INT_FALLING_EDGE 0xa
#define PORT_INT_EITHER_EDGE 0xb
#define PORT_INT_LOGIC_ONE 0xc
static const struct fsl_gpio_soc_data imx_data = {
.have_paddr = true,
};
static const struct of_device_id vf610_gpio_dt_ids[] = {
{ .compatible = "fsl,vf610-gpio", .data = NULL, },
{ .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
{ /* sentinel */ }
};
static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
{
writel_relaxed(val, reg);
}
static inline u32 vf610_gpio_readl(void __iomem *reg)
{
return readl_relaxed(reg);
}
static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
struct vf610_gpio_port *port = gpiochip_get_data(gc);
unsigned long mask = BIT(gpio);
unsigned long offset = GPIO_PDIR;
if (port->sdata && port->sdata->have_paddr) {
mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
if (mask)
offset = GPIO_PDOR;
}
return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
}
static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct vf610_gpio_port *port = gpiochip_get_data(gc);
unsigned long mask = BIT(gpio);
unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;
vf610_gpio_writel(mask, port->gpio_base + offset);
}
static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
struct vf610_gpio_port *port = gpiochip_get_data(chip);
unsigned long mask = BIT(gpio);
u32 val;
if (port->sdata && port->sdata->have_paddr) {
val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
val &= ~mask;
vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
}
return pinctrl_gpio_direction_input(chip->base + gpio);
}
static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
int value)
{
struct vf610_gpio_port *port = gpiochip_get_data(chip);
unsigned long mask = BIT(gpio);
u32 val;
if (port->sdata && port->sdata->have_paddr) {
val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
val |= mask;
vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
}
vf610_gpio_set(chip, gpio, value);
return pinctrl_gpio_direction_output(chip->base + gpio);
}
static void vf610_gpio_irq_handler(struct irq_desc *desc)
{
struct vf610_gpio_port *port =
gpiochip_get_data(irq_desc_get_handler_data(desc));
struct irq_chip *chip = irq_desc_get_chip(desc);
int pin;
unsigned long irq_isfr;
chained_irq_enter(chip, desc);
irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
generic_handle_domain_irq(port->gc.irq.domain, pin);
}
chained_irq_exit(chip, desc);
}
static void vf610_gpio_irq_ack(struct irq_data *d)
{
struct vf610_gpio_port *port =
gpiochip_get_data(irq_data_get_irq_chip_data(d));
int gpio = d->hwirq;
vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
}
static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
{
struct vf610_gpio_port *port =
gpiochip_get_data(irq_data_get_irq_chip_data(d));
u8 irqc;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
irqc = PORT_INT_RISING_EDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
irqc = PORT_INT_FALLING_EDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
irqc = PORT_INT_EITHER_EDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
irqc = PORT_INT_LOGIC_ZERO;
break;
case IRQ_TYPE_LEVEL_HIGH:
irqc = PORT_INT_LOGIC_ONE;
break;
default:
return -EINVAL;
}
port->irqc[d->hwirq] = irqc;
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
else
irq_set_handler_locked(d, handle_edge_irq);
return 0;
}
static void vf610_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct vf610_gpio_port *port = gpiochip_get_data(gc);
irq_hw_number_t gpio_num = irqd_to_hwirq(d);
void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
vf610_gpio_writel(0, pcr_base);
gpiochip_disable_irq(gc, gpio_num);
}
static void vf610_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct vf610_gpio_port *port = gpiochip_get_data(gc);
irq_hw_number_t gpio_num = irqd_to_hwirq(d);
void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
gpiochip_enable_irq(gc, gpio_num);
vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
pcr_base);
}
static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
{
struct vf610_gpio_port *port =
gpiochip_get_data(irq_data_get_irq_chip_data(d));
if (enable)
enable_irq_wake(port->irq);
else
disable_irq_wake(port->irq);
return 0;
}
static const struct irq_chip vf610_irqchip = {
.name = "gpio-vf610",
.irq_ack = vf610_gpio_irq_ack,
.irq_mask = vf610_gpio_irq_mask,
.irq_unmask = vf610_gpio_irq_unmask,
.irq_set_type = vf610_gpio_irq_set_type,
.irq_set_wake = vf610_gpio_irq_set_wake,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void vf610_gpio_disable_clk(void *data)
{
clk_disable_unprepare(data);
}
static int vf610_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct vf610_gpio_port *port;
struct gpio_chip *gc;
struct gpio_irq_chip *girq;
int i;
int ret;
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
if (!port)
return -ENOMEM;
port->sdata = of_device_get_match_data(dev);
port->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(port->base))
return PTR_ERR(port->base);
port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(port->gpio_base))
return PTR_ERR(port->gpio_base);
port->irq = platform_get_irq(pdev, 0);
if (port->irq < 0)
return port->irq;
port->clk_port = devm_clk_get(dev, "port");
ret = PTR_ERR_OR_ZERO(port->clk_port);
if (!ret) {
ret = clk_prepare_enable(port->clk_port);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
port->clk_port);
if (ret)
return ret;
} else if (ret == -EPROBE_DEFER) {
/*
* Percolate deferrals, for anything else,
* just live without the clocking.
*/
return ret;
}
port->clk_gpio = devm_clk_get(dev, "gpio");
ret = PTR_ERR_OR_ZERO(port->clk_gpio);
if (!ret) {
ret = clk_prepare_enable(port->clk_gpio);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
port->clk_gpio);
if (ret)
return ret;
} else if (ret == -EPROBE_DEFER) {
return ret;
}
gc = &port->gc;
gc->parent = dev;
gc->label = dev_name(dev);
gc->ngpio = VF610_GPIO_PER_PORT;
gc->base = -1;
gc->request = gpiochip_generic_request;
gc->free = gpiochip_generic_free;
gc->direction_input = vf610_gpio_direction_input;
gc->get = vf610_gpio_get;
gc->direction_output = vf610_gpio_direction_output;
gc->set = vf610_gpio_set;
/* Mask all GPIO interrupts */
for (i = 0; i < gc->ngpio; i++)
vf610_gpio_writel(0, port->base + PORT_PCR(i));
/* Clear the interrupt status register for all GPIO's */
vf610_gpio_writel(~0, port->base + PORT_ISFR);
girq = &gc->irq;
gpio_irq_chip_set_chip(girq, &vf610_irqchip);
girq->parent_handler = vf610_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(&pdev->dev, 1,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = port->irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_edge_irq;
return devm_gpiochip_add_data(dev, gc, port);
}
static struct platform_driver vf610_gpio_driver = {
.driver = {
.name = "gpio-vf610",
.of_match_table = vf610_gpio_dt_ids,
},
.probe = vf610_gpio_probe,
};
builtin_platform_driver(vf610_gpio_driver);
| linux-master | drivers/gpio/gpio-vf610.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Crystal Cove GPIO Driver
*
* Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
*
* Author: Yang, Bin <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/types.h>
#define CRYSTALCOVE_GPIO_NUM 16
#define CRYSTALCOVE_VGPIO_NUM 95
#define UPDATE_IRQ_TYPE BIT(0)
#define UPDATE_IRQ_MASK BIT(1)
#define GPIO0IRQ 0x0b
#define GPIO1IRQ 0x0c
#define MGPIO0IRQS0 0x19
#define MGPIO1IRQS0 0x1a
#define MGPIO0IRQSX 0x1b
#define MGPIO1IRQSX 0x1c
#define GPIO0P0CTLO 0x2b
#define GPIO0P0CTLI 0x33
#define GPIO1P0CTLO 0x3b
#define GPIO1P0CTLI 0x43
#define GPIOPANELCTL 0x52
#define CTLI_INTCNT_DIS (0)
#define CTLI_INTCNT_NE (1 << 1)
#define CTLI_INTCNT_PE (2 << 1)
#define CTLI_INTCNT_BE (3 << 1)
#define CTLO_DIR_IN (0)
#define CTLO_DIR_OUT (1 << 5)
#define CTLO_DRV_CMOS (0)
#define CTLO_DRV_OD (1 << 4)
#define CTLO_DRV_REN (1 << 3)
#define CTLO_RVAL_2KDW (0)
#define CTLO_RVAL_2KUP (1 << 1)
#define CTLO_RVAL_50KDW (2 << 1)
#define CTLO_RVAL_50KUP (3 << 1)
#define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
#define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
enum ctrl_register {
CTRL_IN,
CTRL_OUT,
};
/**
* struct crystalcove_gpio - Crystal Cove GPIO controller
* @buslock: for bus lock/sync and unlock.
* @chip: the abstract gpio_chip structure.
* @regmap: the regmap from the parent device.
* @update: pending IRQ setting update, to be written to the chip upon unlock.
* @intcnt_value: the Interrupt Detect value to be written.
* @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
*/
struct crystalcove_gpio {
struct mutex buslock; /* irq_bus_lock */
struct gpio_chip chip;
struct regmap *regmap;
int update;
int intcnt_value;
bool set_irq_mask;
};
static inline int to_reg(int gpio, enum ctrl_register reg_type)
{
int reg;
if (gpio >= CRYSTALCOVE_GPIO_NUM) {
/*
* Virtual GPIO called from ACPI, for now we only support
* the panel ctl.
*/
switch (gpio) {
case 0x5e:
return GPIOPANELCTL;
default:
return -EOPNOTSUPP;
}
}
if (reg_type == CTRL_IN) {
if (gpio < 8)
reg = GPIO0P0CTLI;
else
reg = GPIO1P0CTLI;
} else {
if (gpio < 8)
reg = GPIO0P0CTLO;
else
reg = GPIO1P0CTLO;
}
return reg + gpio % 8;
}
static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio)
{
u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
int mask = BIT(gpio % 8);
if (cg->set_irq_mask)
regmap_update_bits(cg->regmap, mirqs0, mask, mask);
else
regmap_update_bits(cg->regmap, mirqs0, mask, 0);
}
static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
{
int reg = to_reg(gpio, CTRL_IN);
regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
}
static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
{
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
int reg = to_reg(gpio, CTRL_OUT);
if (reg < 0)
return 0;
return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
}
static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
int reg = to_reg(gpio, CTRL_OUT);
if (reg < 0)
return 0;
return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
}
static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
unsigned int val;
int ret, reg = to_reg(gpio, CTRL_IN);
if (reg < 0)
return 0;
ret = regmap_read(cg->regmap, reg, &val);
if (ret)
return ret;
return val & 0x1;
}
static void crystalcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
int reg = to_reg(gpio, CTRL_OUT);
if (reg < 0)
return;
if (value)
regmap_update_bits(cg->regmap, reg, 1, 1);
else
regmap_update_bits(cg->regmap, reg, 1, 0);
}
static int crystalcove_irq_type(struct irq_data *data, unsigned int type)
{
struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
irq_hw_number_t hwirq = irqd_to_hwirq(data);
if (hwirq >= CRYSTALCOVE_GPIO_NUM)
return 0;
switch (type) {
case IRQ_TYPE_NONE:
cg->intcnt_value = CTLI_INTCNT_DIS;
break;
case IRQ_TYPE_EDGE_BOTH:
cg->intcnt_value = CTLI_INTCNT_BE;
break;
case IRQ_TYPE_EDGE_RISING:
cg->intcnt_value = CTLI_INTCNT_PE;
break;
case IRQ_TYPE_EDGE_FALLING:
cg->intcnt_value = CTLI_INTCNT_NE;
break;
default:
return -EINVAL;
}
cg->update |= UPDATE_IRQ_TYPE;
return 0;
}
static void crystalcove_bus_lock(struct irq_data *data)
{
struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
mutex_lock(&cg->buslock);
}
static void crystalcove_bus_sync_unlock(struct irq_data *data)
{
struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
irq_hw_number_t hwirq = irqd_to_hwirq(data);
if (cg->update & UPDATE_IRQ_TYPE)
crystalcove_update_irq_ctrl(cg, hwirq);
if (cg->update & UPDATE_IRQ_MASK)
crystalcove_update_irq_mask(cg, hwirq);
cg->update = 0;
mutex_unlock(&cg->buslock);
}
static void crystalcove_irq_unmask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct crystalcove_gpio *cg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(data);
if (hwirq >= CRYSTALCOVE_GPIO_NUM)
return;
gpiochip_enable_irq(gc, hwirq);
cg->set_irq_mask = false;
cg->update |= UPDATE_IRQ_MASK;
}
static void crystalcove_irq_mask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct crystalcove_gpio *cg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(data);
if (hwirq >= CRYSTALCOVE_GPIO_NUM)
return;
cg->set_irq_mask = true;
cg->update |= UPDATE_IRQ_MASK;
gpiochip_disable_irq(gc, hwirq);
}
static const struct irq_chip crystalcove_irqchip = {
.name = "Crystal Cove",
.irq_mask = crystalcove_irq_mask,
.irq_unmask = crystalcove_irq_unmask,
.irq_set_type = crystalcove_irq_type,
.irq_bus_lock = crystalcove_bus_lock,
.irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
{
struct crystalcove_gpio *cg = data;
unsigned long pending;
unsigned int p0, p1;
int gpio;
unsigned int virq;
if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
regmap_read(cg->regmap, GPIO1IRQ, &p1))
return IRQ_NONE;
regmap_write(cg->regmap, GPIO0IRQ, p0);
regmap_write(cg->regmap, GPIO1IRQ, p1);
pending = p0 | p1 << 8;
for_each_set_bit(gpio, &pending, CRYSTALCOVE_GPIO_NUM) {
virq = irq_find_mapping(cg->chip.irq.domain, gpio);
handle_nested_irq(virq);
}
return IRQ_HANDLED;
}
static void crystalcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
int gpio, offset;
unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
&mirqs0);
regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
&mirqsx);
regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
&irq);
offset = gpio % 8;
seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
ctli & 0x1 ? "hi" : "lo",
ctli & CTLI_INTCNT_NE ? "fall" : " ",
ctli & CTLI_INTCNT_PE ? "rise" : " ",
ctlo,
mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask",
mirqsx & BIT(offset) ? "sx mask " : "sx unmask",
irq & BIT(offset) ? "pending" : " ");
}
}
static int crystalcove_gpio_probe(struct platform_device *pdev)
{
int irq = platform_get_irq(pdev, 0);
struct crystalcove_gpio *cg;
int retval;
struct device *dev = pdev->dev.parent;
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
struct gpio_irq_chip *girq;
if (irq < 0)
return irq;
cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
if (!cg)
return -ENOMEM;
mutex_init(&cg->buslock);
cg->chip.label = KBUILD_MODNAME;
cg->chip.direction_input = crystalcove_gpio_dir_in;
cg->chip.direction_output = crystalcove_gpio_dir_out;
cg->chip.get = crystalcove_gpio_get;
cg->chip.set = crystalcove_gpio_set;
cg->chip.base = -1;
cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
cg->chip.can_sleep = true;
cg->chip.parent = dev;
cg->chip.dbg_show = crystalcove_gpio_dbg_show;
cg->regmap = pmic->regmap;
girq = &cg->chip.irq;
gpio_irq_chip_set_chip(girq, &crystalcove_irqchip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
girq->threaded = true;
retval = devm_request_threaded_irq(&pdev->dev, irq, NULL,
crystalcove_gpio_irq_handler,
IRQF_ONESHOT, KBUILD_MODNAME, cg);
if (retval) {
dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
return retval;
}
retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
if (retval)
return retval;
/* Distuingish IRQ domain from others sharing (MFD) the same fwnode */
irq_domain_update_bus_token(cg->chip.irq.domain, DOMAIN_BUS_WIRED);
return 0;
}
static struct platform_driver crystalcove_gpio_driver = {
.probe = crystalcove_gpio_probe,
.driver = {
.name = "crystal_cove_gpio",
},
};
module_platform_driver(crystalcove_gpio_driver);
MODULE_AUTHOR("Yang, Bin <[email protected]>");
MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-crystalcove.c |
// SPDX-License-Identifier: GPL-2.0
/*
* TI TPS6586x GPIO driver
*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
* Author: Laxman dewangan <[email protected]>
*
* Based on tps6586x.c
* Copyright (c) 2010 CompuLab Ltd.
* Mike Rapoport <[email protected]>
*/
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mfd/tps6586x.h>
#include <linux/of.h>
#include <linux/platform_device.h>
/* GPIO control registers */
#define TPS6586X_GPIOSET1 0x5d
#define TPS6586X_GPIOSET2 0x5e
struct tps6586x_gpio {
struct gpio_chip gpio_chip;
struct device *parent;
};
static int tps6586x_gpio_get(struct gpio_chip *gc, unsigned offset)
{
struct tps6586x_gpio *tps6586x_gpio = gpiochip_get_data(gc);
uint8_t val;
int ret;
ret = tps6586x_read(tps6586x_gpio->parent, TPS6586X_GPIOSET2, &val);
if (ret)
return ret;
return !!(val & (1 << offset));
}
static void tps6586x_gpio_set(struct gpio_chip *gc, unsigned offset,
int value)
{
struct tps6586x_gpio *tps6586x_gpio = gpiochip_get_data(gc);
tps6586x_update(tps6586x_gpio->parent, TPS6586X_GPIOSET2,
value << offset, 1 << offset);
}
static int tps6586x_gpio_output(struct gpio_chip *gc, unsigned offset,
int value)
{
struct tps6586x_gpio *tps6586x_gpio = gpiochip_get_data(gc);
uint8_t val, mask;
tps6586x_gpio_set(gc, offset, value);
val = 0x1 << (offset * 2);
mask = 0x3 << (offset * 2);
return tps6586x_update(tps6586x_gpio->parent, TPS6586X_GPIOSET1,
val, mask);
}
static int tps6586x_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct tps6586x_gpio *tps6586x_gpio = gpiochip_get_data(gc);
return tps6586x_irq_get_virq(tps6586x_gpio->parent,
TPS6586X_INT_PLDO_0 + offset);
}
static int tps6586x_gpio_probe(struct platform_device *pdev)
{
struct tps6586x_platform_data *pdata;
struct tps6586x_gpio *tps6586x_gpio;
device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
pdata = dev_get_platdata(pdev->dev.parent);
tps6586x_gpio = devm_kzalloc(&pdev->dev,
sizeof(*tps6586x_gpio), GFP_KERNEL);
if (!tps6586x_gpio)
return -ENOMEM;
tps6586x_gpio->parent = pdev->dev.parent;
tps6586x_gpio->gpio_chip.owner = THIS_MODULE;
tps6586x_gpio->gpio_chip.label = pdev->name;
tps6586x_gpio->gpio_chip.parent = &pdev->dev;
tps6586x_gpio->gpio_chip.ngpio = 4;
tps6586x_gpio->gpio_chip.can_sleep = true;
/* FIXME: add handling of GPIOs as dedicated inputs */
tps6586x_gpio->gpio_chip.direction_output = tps6586x_gpio_output;
tps6586x_gpio->gpio_chip.set = tps6586x_gpio_set;
tps6586x_gpio->gpio_chip.get = tps6586x_gpio_get;
tps6586x_gpio->gpio_chip.to_irq = tps6586x_gpio_to_irq;
if (pdata && pdata->gpio_base)
tps6586x_gpio->gpio_chip.base = pdata->gpio_base;
else
tps6586x_gpio->gpio_chip.base = -1;
return devm_gpiochip_add_data(&pdev->dev, &tps6586x_gpio->gpio_chip,
tps6586x_gpio);
}
static struct platform_driver tps6586x_gpio_driver = {
.driver.name = "tps6586x-gpio",
.probe = tps6586x_gpio_probe,
};
static int __init tps6586x_gpio_init(void)
{
return platform_driver_register(&tps6586x_gpio_driver);
}
subsys_initcall(tps6586x_gpio_init);
| linux-master | drivers/gpio/gpio-tps6586x.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Spreadtrum Communications Inc.
* Copyright (C) 2018 Linaro Ltd.
*/
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
/* GPIO registers definition */
#define SPRD_GPIO_DATA 0x0
#define SPRD_GPIO_DMSK 0x4
#define SPRD_GPIO_DIR 0x8
#define SPRD_GPIO_IS 0xc
#define SPRD_GPIO_IBE 0x10
#define SPRD_GPIO_IEV 0x14
#define SPRD_GPIO_IE 0x18
#define SPRD_GPIO_RIS 0x1c
#define SPRD_GPIO_MIS 0x20
#define SPRD_GPIO_IC 0x24
#define SPRD_GPIO_INEN 0x28
/* We have 16 banks GPIOs and each bank contain 16 GPIOs */
#define SPRD_GPIO_BANK_NR 16
#define SPRD_GPIO_NR 256
#define SPRD_GPIO_BANK_SIZE 0x80
#define SPRD_GPIO_BANK_MASK GENMASK(15, 0)
#define SPRD_GPIO_BIT(x) ((x) & (SPRD_GPIO_BANK_NR - 1))
struct sprd_gpio {
struct gpio_chip chip;
void __iomem *base;
spinlock_t lock;
int irq;
};
static inline void __iomem *sprd_gpio_bank_base(struct sprd_gpio *sprd_gpio,
unsigned int bank)
{
return sprd_gpio->base + SPRD_GPIO_BANK_SIZE * bank;
}
static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset,
u16 reg, int val)
{
struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
offset / SPRD_GPIO_BANK_NR);
unsigned long flags;
u32 tmp;
spin_lock_irqsave(&sprd_gpio->lock, flags);
tmp = readl_relaxed(base + reg);
if (val)
tmp |= BIT(SPRD_GPIO_BIT(offset));
else
tmp &= ~BIT(SPRD_GPIO_BIT(offset));
writel_relaxed(tmp, base + reg);
spin_unlock_irqrestore(&sprd_gpio->lock, flags);
}
static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
{
struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
offset / SPRD_GPIO_BANK_NR);
return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset)));
}
static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 1);
return 0;
}
static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 0);
}
static int sprd_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 0);
sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 1);
return 0;
}
static int sprd_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 1);
sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 0);
sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
return 0;
}
static int sprd_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
return sprd_gpio_read(chip, offset, SPRD_GPIO_DATA);
}
static void sprd_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
}
static void sprd_gpio_irq_mask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
u32 offset = irqd_to_hwirq(data);
sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 0);
gpiochip_disable_irq(chip, offset);
}
static void sprd_gpio_irq_ack(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
u32 offset = irqd_to_hwirq(data);
sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
}
static void sprd_gpio_irq_unmask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
u32 offset = irqd_to_hwirq(data);
sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 1);
gpiochip_enable_irq(chip, offset);
}
static int sprd_gpio_irq_set_type(struct irq_data *data,
unsigned int flow_type)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
u32 offset = irqd_to_hwirq(data);
switch (flow_type) {
case IRQ_TYPE_EDGE_RISING:
sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_BOTH:
sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 1);
sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
irq_set_handler_locked(data, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
irq_set_handler_locked(data, handle_level_irq);
break;
default:
return -EINVAL;
}
return 0;
}
static void sprd_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
struct irq_chip *ic = irq_desc_get_chip(desc);
struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
u32 bank, n;
chained_irq_enter(ic, desc);
for (bank = 0; bank * SPRD_GPIO_BANK_NR < chip->ngpio; bank++) {
void __iomem *base = sprd_gpio_bank_base(sprd_gpio, bank);
unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) &
SPRD_GPIO_BANK_MASK;
for_each_set_bit(n, ®, SPRD_GPIO_BANK_NR)
generic_handle_domain_irq(chip->irq.domain,
bank * SPRD_GPIO_BANK_NR + n);
}
chained_irq_exit(ic, desc);
}
static const struct irq_chip sprd_gpio_irqchip = {
.name = "sprd-gpio",
.irq_ack = sprd_gpio_irq_ack,
.irq_mask = sprd_gpio_irq_mask,
.irq_unmask = sprd_gpio_irq_unmask,
.irq_set_type = sprd_gpio_irq_set_type,
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int sprd_gpio_probe(struct platform_device *pdev)
{
struct gpio_irq_chip *irq;
struct sprd_gpio *sprd_gpio;
sprd_gpio = devm_kzalloc(&pdev->dev, sizeof(*sprd_gpio), GFP_KERNEL);
if (!sprd_gpio)
return -ENOMEM;
sprd_gpio->irq = platform_get_irq(pdev, 0);
if (sprd_gpio->irq < 0)
return sprd_gpio->irq;
sprd_gpio->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sprd_gpio->base))
return PTR_ERR(sprd_gpio->base);
spin_lock_init(&sprd_gpio->lock);
sprd_gpio->chip.label = dev_name(&pdev->dev);
sprd_gpio->chip.ngpio = SPRD_GPIO_NR;
sprd_gpio->chip.base = -1;
sprd_gpio->chip.parent = &pdev->dev;
sprd_gpio->chip.request = sprd_gpio_request;
sprd_gpio->chip.free = sprd_gpio_free;
sprd_gpio->chip.get = sprd_gpio_get;
sprd_gpio->chip.set = sprd_gpio_set;
sprd_gpio->chip.direction_input = sprd_gpio_direction_input;
sprd_gpio->chip.direction_output = sprd_gpio_direction_output;
irq = &sprd_gpio->chip.irq;
gpio_irq_chip_set_chip(irq, &sprd_gpio_irqchip);
irq->handler = handle_bad_irq;
irq->default_type = IRQ_TYPE_NONE;
irq->parent_handler = sprd_gpio_irq_handler;
irq->parent_handler_data = sprd_gpio;
irq->num_parents = 1;
irq->parents = &sprd_gpio->irq;
return devm_gpiochip_add_data(&pdev->dev, &sprd_gpio->chip, sprd_gpio);
}
static const struct of_device_id sprd_gpio_of_match[] = {
{ .compatible = "sprd,sc9860-gpio", },
{ /* end of list */ }
};
MODULE_DEVICE_TABLE(of, sprd_gpio_of_match);
static struct platform_driver sprd_gpio_driver = {
.probe = sprd_gpio_probe,
.driver = {
.name = "sprd-gpio",
.of_match_table = sprd_gpio_of_match,
},
};
module_platform_driver_probe(sprd_gpio_driver, sprd_gpio_probe);
MODULE_DESCRIPTION("Spreadtrum GPIO driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-sprd.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Loongson-2F/3A/3B GPIO Support
*
* Copyright (c) 2008 Richard Liu, STMicroelectronics <[email protected]>
* Copyright (c) 2008-2010 Arnaud Patard <[email protected]>
* Copyright (c) 2013 Hongbing Hu <[email protected]>
* Copyright (c) 2014 Huacai Chen <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/bitops.h>
#include <asm/types.h>
#include <loongson.h>
#define STLS2F_N_GPIO 4
#define STLS3A_N_GPIO 16
#ifdef CONFIG_CPU_LOONGSON64
#define LOONGSON_N_GPIO STLS3A_N_GPIO
#else
#define LOONGSON_N_GPIO STLS2F_N_GPIO
#endif
/*
* Offset into the register where we read lines, we write them from offset 0.
* This offset is the only thing that stand between us and using
* GPIO_GENERIC.
*/
#define LOONGSON_GPIO_IN_OFFSET 16
static DEFINE_SPINLOCK(gpio_lock);
static int loongson_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
{
u32 val;
spin_lock(&gpio_lock);
val = LOONGSON_GPIODATA;
spin_unlock(&gpio_lock);
return !!(val & BIT(gpio + LOONGSON_GPIO_IN_OFFSET));
}
static void loongson_gpio_set_value(struct gpio_chip *chip,
unsigned gpio, int value)
{
u32 val;
spin_lock(&gpio_lock);
val = LOONGSON_GPIODATA;
if (value)
val |= BIT(gpio);
else
val &= ~BIT(gpio);
LOONGSON_GPIODATA = val;
spin_unlock(&gpio_lock);
}
static int loongson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
u32 temp;
spin_lock(&gpio_lock);
temp = LOONGSON_GPIOIE;
temp |= BIT(gpio);
LOONGSON_GPIOIE = temp;
spin_unlock(&gpio_lock);
return 0;
}
static int loongson_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int level)
{
u32 temp;
loongson_gpio_set_value(chip, gpio, level);
spin_lock(&gpio_lock);
temp = LOONGSON_GPIOIE;
temp &= ~BIT(gpio);
LOONGSON_GPIOIE = temp;
spin_unlock(&gpio_lock);
return 0;
}
static int loongson_gpio_probe(struct platform_device *pdev)
{
struct gpio_chip *gc;
struct device *dev = &pdev->dev;
gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
if (!gc)
return -ENOMEM;
gc->label = "loongson-gpio-chip";
gc->base = 0;
gc->ngpio = LOONGSON_N_GPIO;
gc->get = loongson_gpio_get_value;
gc->set = loongson_gpio_set_value;
gc->direction_input = loongson_gpio_direction_input;
gc->direction_output = loongson_gpio_direction_output;
return gpiochip_add_data(gc, NULL);
}
static struct platform_driver loongson_gpio_driver = {
.driver = {
.name = "loongson-gpio",
},
.probe = loongson_gpio_probe,
};
static int __init loongson_gpio_setup(void)
{
struct platform_device *pdev;
int ret;
ret = platform_driver_register(&loongson_gpio_driver);
if (ret) {
pr_err("error registering loongson GPIO driver\n");
return ret;
}
pdev = platform_device_register_simple("loongson-gpio", -1, NULL, 0);
return PTR_ERR_OR_ZERO(pdev);
}
postcore_initcall(loongson_gpio_setup);
| linux-master | drivers/gpio/gpio-loongson.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Loongson GPIO Support
*
* Copyright (C) 2022-2023 Loongson Technology Corporation Limited
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/bitops.h>
#include <asm/types.h>
enum loongson_gpio_mode {
BIT_CTRL_MODE,
BYTE_CTRL_MODE,
};
struct loongson_gpio_chip_data {
const char *label;
enum loongson_gpio_mode mode;
unsigned int conf_offset;
unsigned int out_offset;
unsigned int in_offset;
};
struct loongson_gpio_chip {
struct gpio_chip chip;
struct fwnode_handle *fwnode;
spinlock_t lock;
void __iomem *reg_base;
const struct loongson_gpio_chip_data *chip_data;
};
static inline struct loongson_gpio_chip *to_loongson_gpio_chip(struct gpio_chip *chip)
{
return container_of(chip, struct loongson_gpio_chip, chip);
}
static inline void loongson_commit_direction(struct loongson_gpio_chip *lgpio, unsigned int pin,
int input)
{
u8 bval = input ? 1 : 0;
writeb(bval, lgpio->reg_base + lgpio->chip_data->conf_offset + pin);
}
static void loongson_commit_level(struct loongson_gpio_chip *lgpio, unsigned int pin, int high)
{
u8 bval = high ? 1 : 0;
writeb(bval, lgpio->reg_base + lgpio->chip_data->out_offset + pin);
}
static int loongson_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
{
unsigned long flags;
struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
spin_lock_irqsave(&lgpio->lock, flags);
loongson_commit_direction(lgpio, pin, 1);
spin_unlock_irqrestore(&lgpio->lock, flags);
return 0;
}
static int loongson_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, int value)
{
unsigned long flags;
struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
spin_lock_irqsave(&lgpio->lock, flags);
loongson_commit_level(lgpio, pin, value);
loongson_commit_direction(lgpio, pin, 0);
spin_unlock_irqrestore(&lgpio->lock, flags);
return 0;
}
static int loongson_gpio_get(struct gpio_chip *chip, unsigned int pin)
{
u8 bval;
int val;
struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
bval = readb(lgpio->reg_base + lgpio->chip_data->in_offset + pin);
val = bval & 1;
return val;
}
static int loongson_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
{
u8 bval;
struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
bval = readb(lgpio->reg_base + lgpio->chip_data->conf_offset + pin);
if (bval & 1)
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static void loongson_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
{
unsigned long flags;
struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
spin_lock_irqsave(&lgpio->lock, flags);
loongson_commit_level(lgpio, pin, value);
spin_unlock_irqrestore(&lgpio->lock, flags);
}
static int loongson_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct platform_device *pdev = to_platform_device(chip->parent);
return platform_get_irq(pdev, offset);
}
static int loongson_gpio_init(struct device *dev, struct loongson_gpio_chip *lgpio,
struct device_node *np, void __iomem *reg_base)
{
int ret;
u32 ngpios;
lgpio->reg_base = reg_base;
if (lgpio->chip_data->mode == BIT_CTRL_MODE) {
ret = bgpio_init(&lgpio->chip, dev, 8,
lgpio->reg_base + lgpio->chip_data->in_offset,
lgpio->reg_base + lgpio->chip_data->out_offset,
NULL, NULL,
lgpio->reg_base + lgpio->chip_data->conf_offset,
0);
if (ret) {
dev_err(dev, "unable to init generic GPIO\n");
return ret;
}
} else {
lgpio->chip.direction_input = loongson_gpio_direction_input;
lgpio->chip.get = loongson_gpio_get;
lgpio->chip.get_direction = loongson_gpio_get_direction;
lgpio->chip.direction_output = loongson_gpio_direction_output;
lgpio->chip.set = loongson_gpio_set;
lgpio->chip.parent = dev;
spin_lock_init(&lgpio->lock);
}
device_property_read_u32(dev, "ngpios", &ngpios);
lgpio->chip.can_sleep = 0;
lgpio->chip.ngpio = ngpios;
lgpio->chip.label = lgpio->chip_data->label;
lgpio->chip.to_irq = loongson_gpio_to_irq;
return devm_gpiochip_add_data(dev, &lgpio->chip, lgpio);
}
static int loongson_gpio_probe(struct platform_device *pdev)
{
void __iomem *reg_base;
struct loongson_gpio_chip *lgpio;
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
lgpio = devm_kzalloc(dev, sizeof(*lgpio), GFP_KERNEL);
if (!lgpio)
return -ENOMEM;
lgpio->chip_data = device_get_match_data(dev);
reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
return loongson_gpio_init(dev, lgpio, np, reg_base);
}
static const struct loongson_gpio_chip_data loongson_gpio_ls2k_data = {
.label = "ls2k_gpio",
.mode = BIT_CTRL_MODE,
.conf_offset = 0x0,
.in_offset = 0x20,
.out_offset = 0x10,
};
static const struct loongson_gpio_chip_data loongson_gpio_ls7a_data = {
.label = "ls7a_gpio",
.mode = BYTE_CTRL_MODE,
.conf_offset = 0x800,
.in_offset = 0xa00,
.out_offset = 0x900,
};
static const struct of_device_id loongson_gpio_of_match[] = {
{
.compatible = "loongson,ls2k-gpio",
.data = &loongson_gpio_ls2k_data,
},
{
.compatible = "loongson,ls7a-gpio",
.data = &loongson_gpio_ls7a_data,
},
{}
};
MODULE_DEVICE_TABLE(of, loongson_gpio_of_match);
static const struct acpi_device_id loongson_gpio_acpi_match[] = {
{
.id = "LOON0002",
.driver_data = (kernel_ulong_t)&loongson_gpio_ls7a_data,
},
{}
};
MODULE_DEVICE_TABLE(acpi, loongson_gpio_acpi_match);
static struct platform_driver loongson_gpio_driver = {
.driver = {
.name = "loongson-gpio",
.of_match_table = loongson_gpio_of_match,
.acpi_match_table = loongson_gpio_acpi_match,
},
.probe = loongson_gpio_probe,
};
static int __init loongson_gpio_setup(void)
{
return platform_driver_register(&loongson_gpio_driver);
}
postcore_initcall(loongson_gpio_setup);
MODULE_DESCRIPTION("Loongson gpio driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-loongson-64bit.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2015 IBM Corp.
*
* Joel Stanley <[email protected]>
*/
#include <linux/clk.h>
#include <linux/gpio/aspeed.h>
#include <linux/gpio/driver.h>
#include <linux/hashtable.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <asm/div64.h>
/*
* These two headers aren't meant to be used by GPIO drivers. We need
* them in order to access gpio_chip_hwgpio() which we need to implement
* the aspeed specific API which allows the coprocessor to request
* access to some GPIOs and to arbitrate between coprocessor and ARM.
*/
#include <linux/gpio/consumer.h>
#include "gpiolib.h"
struct aspeed_bank_props {
unsigned int bank;
u32 input;
u32 output;
};
struct aspeed_gpio_config {
unsigned int nr_gpios;
const struct aspeed_bank_props *props;
};
/*
* @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
* @timer_users: Tracks the number of users for each timer
*
* The @timer_users has four elements but the first element is unused. This is
* to simplify accounting and indexing, as a zero value in @offset_timer
* represents disabled debouncing for the GPIO. Any other value for an element
* of @offset_timer is used as an index into @timer_users. This behaviour of
* the zero value aligns with the behaviour of zero built from the timer
* configuration registers (i.e. debouncing is disabled).
*/
struct aspeed_gpio {
struct gpio_chip chip;
struct device *dev;
raw_spinlock_t lock;
void __iomem *base;
int irq;
const struct aspeed_gpio_config *config;
u8 *offset_timer;
unsigned int timer_users[4];
struct clk *clk;
u32 *dcache;
u8 *cf_copro_bankmap;
};
struct aspeed_gpio_bank {
uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
* +4: Rd/Wr: Direction (0=in, 1=out)
*/
uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */
uint16_t irq_regs;
uint16_t debounce_regs;
uint16_t tolerance_regs;
uint16_t cmdsrc_regs;
const char names[4][3];
};
/*
* Note: The "value" register returns the input value sampled on the
* line even when the GPIO is configured as an output. Since
* that input goes through synchronizers, writing, then reading
* back may not return the written value right away.
*
* The "rdata" register returns the content of the write latch
* and thus can be used to read back what was last written
* reliably.
*/
static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
static const struct aspeed_gpio_copro_ops *copro_ops;
static void *copro_data;
static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
{
.val_regs = 0x0000,
.rdata_reg = 0x00c0,
.irq_regs = 0x0008,
.debounce_regs = 0x0040,
.tolerance_regs = 0x001c,
.cmdsrc_regs = 0x0060,
.names = { "A", "B", "C", "D" },
},
{
.val_regs = 0x0020,
.rdata_reg = 0x00c4,
.irq_regs = 0x0028,
.debounce_regs = 0x0048,
.tolerance_regs = 0x003c,
.cmdsrc_regs = 0x0068,
.names = { "E", "F", "G", "H" },
},
{
.val_regs = 0x0070,
.rdata_reg = 0x00c8,
.irq_regs = 0x0098,
.debounce_regs = 0x00b0,
.tolerance_regs = 0x00ac,
.cmdsrc_regs = 0x0090,
.names = { "I", "J", "K", "L" },
},
{
.val_regs = 0x0078,
.rdata_reg = 0x00cc,
.irq_regs = 0x00e8,
.debounce_regs = 0x0100,
.tolerance_regs = 0x00fc,
.cmdsrc_regs = 0x00e0,
.names = { "M", "N", "O", "P" },
},
{
.val_regs = 0x0080,
.rdata_reg = 0x00d0,
.irq_regs = 0x0118,
.debounce_regs = 0x0130,
.tolerance_regs = 0x012c,
.cmdsrc_regs = 0x0110,
.names = { "Q", "R", "S", "T" },
},
{
.val_regs = 0x0088,
.rdata_reg = 0x00d4,
.irq_regs = 0x0148,
.debounce_regs = 0x0160,
.tolerance_regs = 0x015c,
.cmdsrc_regs = 0x0140,
.names = { "U", "V", "W", "X" },
},
{
.val_regs = 0x01E0,
.rdata_reg = 0x00d8,
.irq_regs = 0x0178,
.debounce_regs = 0x0190,
.tolerance_regs = 0x018c,
.cmdsrc_regs = 0x0170,
.names = { "Y", "Z", "AA", "AB" },
},
{
.val_regs = 0x01e8,
.rdata_reg = 0x00dc,
.irq_regs = 0x01a8,
.debounce_regs = 0x01c0,
.tolerance_regs = 0x01bc,
.cmdsrc_regs = 0x01a0,
.names = { "AC", "", "", "" },
},
};
enum aspeed_gpio_reg {
reg_val,
reg_rdata,
reg_dir,
reg_irq_enable,
reg_irq_type0,
reg_irq_type1,
reg_irq_type2,
reg_irq_status,
reg_debounce_sel1,
reg_debounce_sel2,
reg_tolerance,
reg_cmdsrc0,
reg_cmdsrc1,
};
#define GPIO_VAL_VALUE 0x00
#define GPIO_VAL_DIR 0x04
#define GPIO_IRQ_ENABLE 0x00
#define GPIO_IRQ_TYPE0 0x04
#define GPIO_IRQ_TYPE1 0x08
#define GPIO_IRQ_TYPE2 0x0c
#define GPIO_IRQ_STATUS 0x10
#define GPIO_DEBOUNCE_SEL1 0x00
#define GPIO_DEBOUNCE_SEL2 0x04
#define GPIO_CMDSRC_0 0x00
#define GPIO_CMDSRC_1 0x04
#define GPIO_CMDSRC_ARM 0
#define GPIO_CMDSRC_LPC 1
#define GPIO_CMDSRC_COLDFIRE 2
#define GPIO_CMDSRC_RESERVED 3
/* This will be resolved at compile time */
static inline void __iomem *bank_reg(struct aspeed_gpio *gpio,
const struct aspeed_gpio_bank *bank,
const enum aspeed_gpio_reg reg)
{
switch (reg) {
case reg_val:
return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
case reg_rdata:
return gpio->base + bank->rdata_reg;
case reg_dir:
return gpio->base + bank->val_regs + GPIO_VAL_DIR;
case reg_irq_enable:
return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
case reg_irq_type0:
return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
case reg_irq_type1:
return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
case reg_irq_type2:
return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
case reg_irq_status:
return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
case reg_debounce_sel1:
return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
case reg_debounce_sel2:
return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
case reg_tolerance:
return gpio->base + bank->tolerance_regs;
case reg_cmdsrc0:
return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
case reg_cmdsrc1:
return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
}
BUG();
}
#define GPIO_BANK(x) ((x) >> 5)
#define GPIO_OFFSET(x) ((x) & 0x1f)
#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
#define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
#define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
#define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
{
unsigned int bank = GPIO_BANK(offset);
WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
return &aspeed_gpio_banks[bank];
}
static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props)
{
return !(props->input || props->output);
}
static inline const struct aspeed_bank_props *find_bank_props(
struct aspeed_gpio *gpio, unsigned int offset)
{
const struct aspeed_bank_props *props = gpio->config->props;
while (!is_bank_props_sentinel(props)) {
if (props->bank == GPIO_BANK(offset))
return props;
props++;
}
return NULL;
}
static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
{
const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
const struct aspeed_gpio_bank *bank = to_bank(offset);
unsigned int group = GPIO_OFFSET(offset) / 8;
return bank->names[group][0] != '\0' &&
(!props || ((props->input | props->output) & GPIO_BIT(offset)));
}
static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
{
const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
return !props || (props->input & GPIO_BIT(offset));
}
#define have_irq(g, o) have_input((g), (o))
#define have_debounce(g, o) have_input((g), (o))
static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
{
const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
return !props || (props->output & GPIO_BIT(offset));
}
static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio,
const struct aspeed_gpio_bank *bank,
int bindex, int cmdsrc)
{
void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);
void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);
u32 bit, reg;
/*
* Each register controls 4 banks, so take the bottom 2
* bits of the bank index, and use them to select the
* right control bit (0, 8, 16 or 24).
*/
bit = BIT((bindex & 3) << 3);
/* Source 1 first to avoid illegal 11 combination */
reg = ioread32(c1);
if (cmdsrc & 2)
reg |= bit;
else
reg &= ~bit;
iowrite32(reg, c1);
/* Then Source 0 */
reg = ioread32(c0);
if (cmdsrc & 1)
reg |= bit;
else
reg &= ~bit;
iowrite32(reg, c0);
}
static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
unsigned int offset)
{
const struct aspeed_gpio_bank *bank = to_bank(offset);
if (!copro_ops || !gpio->cf_copro_bankmap)
return false;
if (!gpio->cf_copro_bankmap[offset >> 3])
return false;
if (!copro_ops->request_access)
return false;
/* Pause the coprocessor */
copro_ops->request_access(copro_data);
/* Change command source back to ARM */
aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM);
/* Update cache */
gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));
return true;
}
static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
unsigned int offset)
{
const struct aspeed_gpio_bank *bank = to_bank(offset);
if (!copro_ops || !gpio->cf_copro_bankmap)
return;
if (!gpio->cf_copro_bankmap[offset >> 3])
return;
if (!copro_ops->release_access)
return;
/* Change command source back to ColdFire */
aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3,
GPIO_CMDSRC_COLDFIRE);
/* Restart the coprocessor */
copro_ops->release_access(copro_data);
}
static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
const struct aspeed_gpio_bank *bank = to_bank(offset);
return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));
}
static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
int val)
{
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
const struct aspeed_gpio_bank *bank = to_bank(offset);
void __iomem *addr;
u32 reg;
addr = bank_reg(gpio, bank, reg_val);
reg = gpio->dcache[GPIO_BANK(offset)];
if (val)
reg |= GPIO_BIT(offset);
else
reg &= ~GPIO_BIT(offset);
gpio->dcache[GPIO_BANK(offset)] = reg;
iowrite32(reg, addr);
}
static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
int val)
{
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
unsigned long flags;
bool copro;
raw_spin_lock_irqsave(&gpio->lock, flags);
copro = aspeed_gpio_copro_request(gpio, offset);
__aspeed_gpio_set(gc, offset, val);
if (copro)
aspeed_gpio_copro_release(gpio, offset);
raw_spin_unlock_irqrestore(&gpio->lock, flags);
}
static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
{
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
const struct aspeed_gpio_bank *bank = to_bank(offset);
void __iomem *addr = bank_reg(gpio, bank, reg_dir);
unsigned long flags;
bool copro;
u32 reg;
if (!have_input(gpio, offset))
return -ENOTSUPP;
raw_spin_lock_irqsave(&gpio->lock, flags);
reg = ioread32(addr);
reg &= ~GPIO_BIT(offset);
copro = aspeed_gpio_copro_request(gpio, offset);
iowrite32(reg, addr);
if (copro)
aspeed_gpio_copro_release(gpio, offset);
raw_spin_unlock_irqrestore(&gpio->lock, flags);
return 0;
}
static int aspeed_gpio_dir_out(struct gpio_chip *gc,
unsigned int offset, int val)
{
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
const struct aspeed_gpio_bank *bank = to_bank(offset);
void __iomem *addr = bank_reg(gpio, bank, reg_dir);
unsigned long flags;
bool copro;
u32 reg;
if (!have_output(gpio, offset))
return -ENOTSUPP;
raw_spin_lock_irqsave(&gpio->lock, flags);
reg = ioread32(addr);
reg |= GPIO_BIT(offset);
copro = aspeed_gpio_copro_request(gpio, offset);
__aspeed_gpio_set(gc, offset, val);
iowrite32(reg, addr);
if (copro)
aspeed_gpio_copro_release(gpio, offset);
raw_spin_unlock_irqrestore(&gpio->lock, flags);
return 0;
}
static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
const struct aspeed_gpio_bank *bank = to_bank(offset);
unsigned long flags;
u32 val;
if (!have_input(gpio, offset))
return GPIO_LINE_DIRECTION_OUT;
if (!have_output(gpio, offset))
return GPIO_LINE_DIRECTION_IN;
raw_spin_lock_irqsave(&gpio->lock, flags);
val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
raw_spin_unlock_irqrestore(&gpio->lock, flags);
return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
}
static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
struct aspeed_gpio **gpio,
const struct aspeed_gpio_bank **bank,
u32 *bit, int *offset)
{
struct aspeed_gpio *internal;
*offset = irqd_to_hwirq(d);
internal = irq_data_get_irq_chip_data(d);
/* This might be a bit of a questionable place to check */
if (!have_irq(internal, *offset))
return -ENOTSUPP;
*gpio = internal;
*bank = to_bank(*offset);
*bit = GPIO_BIT(*offset);
return 0;
}
static void aspeed_gpio_irq_ack(struct irq_data *d)
{
const struct aspeed_gpio_bank *bank;
struct aspeed_gpio *gpio;
unsigned long flags;
void __iomem *status_addr;
int rc, offset;
bool copro;
u32 bit;
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
if (rc)
return;
status_addr = bank_reg(gpio, bank, reg_irq_status);
raw_spin_lock_irqsave(&gpio->lock, flags);
copro = aspeed_gpio_copro_request(gpio, offset);
iowrite32(bit, status_addr);
if (copro)
aspeed_gpio_copro_release(gpio, offset);
raw_spin_unlock_irqrestore(&gpio->lock, flags);
}
static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
{
const struct aspeed_gpio_bank *bank;
struct aspeed_gpio *gpio;
unsigned long flags;
u32 reg, bit;
void __iomem *addr;
int rc, offset;
bool copro;
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
if (rc)
return;
addr = bank_reg(gpio, bank, reg_irq_enable);
/* Unmasking the IRQ */
if (set)
gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d));
raw_spin_lock_irqsave(&gpio->lock, flags);
copro = aspeed_gpio_copro_request(gpio, offset);
reg = ioread32(addr);
if (set)
reg |= bit;
else
reg &= ~bit;
iowrite32(reg, addr);
if (copro)
aspeed_gpio_copro_release(gpio, offset);
raw_spin_unlock_irqrestore(&gpio->lock, flags);
/* Masking the IRQ */
if (!set)
gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d));
}
static void aspeed_gpio_irq_mask(struct irq_data *d)
{
aspeed_gpio_irq_set_mask(d, false);
}
static void aspeed_gpio_irq_unmask(struct irq_data *d)
{
aspeed_gpio_irq_set_mask(d, true);
}
static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
{
u32 type0 = 0;
u32 type1 = 0;
u32 type2 = 0;
u32 bit, reg;
const struct aspeed_gpio_bank *bank;
irq_flow_handler_t handler;
struct aspeed_gpio *gpio;
unsigned long flags;
void __iomem *addr;
int rc, offset;
bool copro;
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
if (rc)
return -EINVAL;
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_BOTH:
type2 |= bit;
fallthrough;
case IRQ_TYPE_EDGE_RISING:
type0 |= bit;
fallthrough;
case IRQ_TYPE_EDGE_FALLING:
handler = handle_edge_irq;
break;
case IRQ_TYPE_LEVEL_HIGH:
type0 |= bit;
fallthrough;
case IRQ_TYPE_LEVEL_LOW:
type1 |= bit;
handler = handle_level_irq;
break;
default:
return -EINVAL;
}
raw_spin_lock_irqsave(&gpio->lock, flags);
copro = aspeed_gpio_copro_request(gpio, offset);
addr = bank_reg(gpio, bank, reg_irq_type0);
reg = ioread32(addr);
reg = (reg & ~bit) | type0;
iowrite32(reg, addr);
addr = bank_reg(gpio, bank, reg_irq_type1);
reg = ioread32(addr);
reg = (reg & ~bit) | type1;
iowrite32(reg, addr);
addr = bank_reg(gpio, bank, reg_irq_type2);
reg = ioread32(addr);
reg = (reg & ~bit) | type2;
iowrite32(reg, addr);
if (copro)
aspeed_gpio_copro_release(gpio, offset);
raw_spin_unlock_irqrestore(&gpio->lock, flags);
irq_set_handler_locked(d, handler);
return 0;
}
static void aspeed_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct irq_chip *ic = irq_desc_get_chip(desc);
struct aspeed_gpio *data = gpiochip_get_data(gc);
unsigned int i, p, banks;
unsigned long reg;
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
chained_irq_enter(ic, desc);
banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
for (i = 0; i < banks; i++) {
const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
reg = ioread32(bank_reg(data, bank, reg_irq_status));
for_each_set_bit(p, ®, 32)
generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
}
chained_irq_exit(ic, desc);
}
static void aspeed_init_irq_valid_mask(struct gpio_chip *gc,
unsigned long *valid_mask,
unsigned int ngpios)
{
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
const struct aspeed_bank_props *props = gpio->config->props;
while (!is_bank_props_sentinel(props)) {
unsigned int offset;
const unsigned long int input = props->input;
/* Pretty crummy approach, but similar to GPIO core */
for_each_clear_bit(offset, &input, 32) {
unsigned int i = props->bank * 32 + offset;
if (i >= gpio->chip.ngpio)
break;
clear_bit(i, valid_mask);
}
props++;
}
}
static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip,
unsigned int offset, bool enable)
{
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
unsigned long flags;
void __iomem *treg;
bool copro;
u32 val;
treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
raw_spin_lock_irqsave(&gpio->lock, flags);
copro = aspeed_gpio_copro_request(gpio, offset);
val = readl(treg);
if (enable)
val |= GPIO_BIT(offset);
else
val &= ~GPIO_BIT(offset);
writel(val, treg);
if (copro)
aspeed_gpio_copro_release(gpio, offset);
raw_spin_unlock_irqrestore(&gpio->lock, flags);
return 0;
}
static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
if (!have_gpio(gpiochip_get_data(chip), offset))
return -ENODEV;
return pinctrl_gpio_request(chip->base + offset);
}
static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
pinctrl_gpio_free(chip->base + offset);
}
static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
u32 *cycles)
{
u64 rate;
u64 n;
u32 r;
rate = clk_get_rate(gpio->clk);
if (!rate)
return -ENOTSUPP;
n = rate * usecs;
r = do_div(n, 1000000);
if (n >= U32_MAX)
return -ERANGE;
/* At least as long as the requested time */
*cycles = n + (!!r);
return 0;
}
/* Call under gpio->lock */
static int register_allocated_timer(struct aspeed_gpio *gpio,
unsigned int offset, unsigned int timer)
{
if (WARN(gpio->offset_timer[offset] != 0,
"Offset %d already allocated timer %d\n",
offset, gpio->offset_timer[offset]))
return -EINVAL;
if (WARN(gpio->timer_users[timer] == UINT_MAX,
"Timer user count would overflow\n"))
return -EPERM;
gpio->offset_timer[offset] = timer;
gpio->timer_users[timer]++;
return 0;
}
/* Call under gpio->lock */
static int unregister_allocated_timer(struct aspeed_gpio *gpio,
unsigned int offset)
{
if (WARN(gpio->offset_timer[offset] == 0,
"No timer allocated to offset %d\n", offset))
return -EINVAL;
if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
"No users recorded for timer %d\n",
gpio->offset_timer[offset]))
return -EINVAL;
gpio->timer_users[gpio->offset_timer[offset]]--;
gpio->offset_timer[offset] = 0;
return 0;
}
/* Call under gpio->lock */
static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
unsigned int offset)
{
return gpio->offset_timer[offset] > 0;
}
/* Call under gpio->lock */
static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
unsigned int timer)
{
const struct aspeed_gpio_bank *bank = to_bank(offset);
const u32 mask = GPIO_BIT(offset);
void __iomem *addr;
u32 val;
/* Note: Debounce timer isn't under control of the command
* source registers, so no need to sync with the coprocessor
*/
addr = bank_reg(gpio, bank, reg_debounce_sel1);
val = ioread32(addr);
iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr);
addr = bank_reg(gpio, bank, reg_debounce_sel2);
val = ioread32(addr);
iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr);
}
static int enable_debounce(struct gpio_chip *chip, unsigned int offset,
unsigned long usecs)
{
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
u32 requested_cycles;
unsigned long flags;
int rc;
int i;
if (!gpio->clk)
return -EINVAL;
rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
if (rc < 0) {
dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
usecs, clk_get_rate(gpio->clk), rc);
return rc;
}
raw_spin_lock_irqsave(&gpio->lock, flags);
if (timer_allocation_registered(gpio, offset)) {
rc = unregister_allocated_timer(gpio, offset);
if (rc < 0)
goto out;
}
/* Try to find a timer already configured for the debounce period */
for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) {
u32 cycles;
cycles = ioread32(gpio->base + debounce_timers[i]);
if (requested_cycles == cycles)
break;
}
if (i == ARRAY_SIZE(debounce_timers)) {
int j;
/*
* As there are no timers configured for the requested debounce
* period, find an unused timer instead
*/
for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
if (gpio->timer_users[j] == 0)
break;
}
if (j == ARRAY_SIZE(gpio->timer_users)) {
dev_warn(chip->parent,
"Debounce timers exhausted, cannot debounce for period %luus\n",
usecs);
rc = -EPERM;
/*
* We already adjusted the accounting to remove @offset
* as a user of its previous timer, so also configure
* the hardware so @offset has timers disabled for
* consistency.
*/
configure_timer(gpio, offset, 0);
goto out;
}
i = j;
iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
}
if (WARN(i == 0, "Cannot register index of disabled timer\n")) {
rc = -EINVAL;
goto out;
}
register_allocated_timer(gpio, offset, i);
configure_timer(gpio, offset, i);
out:
raw_spin_unlock_irqrestore(&gpio->lock, flags);
return rc;
}
static int disable_debounce(struct gpio_chip *chip, unsigned int offset)
{
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
unsigned long flags;
int rc;
raw_spin_lock_irqsave(&gpio->lock, flags);
rc = unregister_allocated_timer(gpio, offset);
if (!rc)
configure_timer(gpio, offset, 0);
raw_spin_unlock_irqrestore(&gpio->lock, flags);
return rc;
}
static int set_debounce(struct gpio_chip *chip, unsigned int offset,
unsigned long usecs)
{
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
if (!have_debounce(gpio, offset))
return -ENOTSUPP;
if (usecs)
return enable_debounce(chip, offset, usecs);
return disable_debounce(chip, offset);
}
static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
unsigned long param = pinconf_to_config_param(config);
u32 arg = pinconf_to_config_argument(config);
if (param == PIN_CONFIG_INPUT_DEBOUNCE)
return set_debounce(chip, offset, arg);
else if (param == PIN_CONFIG_BIAS_DISABLE ||
param == PIN_CONFIG_BIAS_PULL_DOWN ||
param == PIN_CONFIG_DRIVE_STRENGTH)
return pinctrl_gpio_set_config(offset, config);
else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
/* Return -ENOTSUPP to trigger emulation, as per datasheet */
return -ENOTSUPP;
else if (param == PIN_CONFIG_PERSIST_STATE)
return aspeed_gpio_reset_tolerance(chip, offset, arg);
return -ENOTSUPP;
}
/**
* aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
* the coprocessor for shared GPIO banks
* @ops: The callbacks
* @data: Pointer passed back to the callbacks
*/
int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data)
{
copro_data = data;
copro_ops = ops;
return 0;
}
EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops);
/**
* aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
* bank gets marked and any access from the ARM will
* result in handshaking via callbacks.
* @desc: The GPIO to be marked
* @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
* @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
* @bit: If non-NULL, returns the bit number of the GPIO in the registers
*/
int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc,
u16 *vreg_offset, u16 *dreg_offset, u8 *bit)
{
struct gpio_chip *chip = gpiod_to_chip(desc);
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
const struct aspeed_gpio_bank *bank = to_bank(offset);
unsigned long flags;
if (!gpio->cf_copro_bankmap)
gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
if (!gpio->cf_copro_bankmap)
return -ENOMEM;
if (offset < 0 || offset > gpio->chip.ngpio)
return -EINVAL;
bindex = offset >> 3;
raw_spin_lock_irqsave(&gpio->lock, flags);
/* Sanity check, this shouldn't happen */
if (gpio->cf_copro_bankmap[bindex] == 0xff) {
rc = -EIO;
goto bail;
}
gpio->cf_copro_bankmap[bindex]++;
/* Switch command source */
if (gpio->cf_copro_bankmap[bindex] == 1)
aspeed_gpio_change_cmd_source(gpio, bank, bindex,
GPIO_CMDSRC_COLDFIRE);
if (vreg_offset)
*vreg_offset = bank->val_regs;
if (dreg_offset)
*dreg_offset = bank->rdata_reg;
if (bit)
*bit = GPIO_OFFSET(offset);
bail:
raw_spin_unlock_irqrestore(&gpio->lock, flags);
return rc;
}
EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio);
/**
* aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
* @desc: The GPIO to be marked
*/
int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc)
{
struct gpio_chip *chip = gpiod_to_chip(desc);
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
const struct aspeed_gpio_bank *bank = to_bank(offset);
unsigned long flags;
if (!gpio->cf_copro_bankmap)
return -ENXIO;
if (offset < 0 || offset > gpio->chip.ngpio)
return -EINVAL;
bindex = offset >> 3;
raw_spin_lock_irqsave(&gpio->lock, flags);
/* Sanity check, this shouldn't happen */
if (gpio->cf_copro_bankmap[bindex] == 0) {
rc = -EIO;
goto bail;
}
gpio->cf_copro_bankmap[bindex]--;
/* Switch command source */
if (gpio->cf_copro_bankmap[bindex] == 0)
aspeed_gpio_change_cmd_source(gpio, bank, bindex,
GPIO_CMDSRC_ARM);
bail:
raw_spin_unlock_irqrestore(&gpio->lock, flags);
return rc;
}
EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio);
static void aspeed_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
{
const struct aspeed_gpio_bank *bank;
struct aspeed_gpio *gpio;
u32 bit;
int rc, offset;
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
if (rc)
return;
seq_printf(p, dev_name(gpio->dev));
}
static const struct irq_chip aspeed_gpio_irq_chip = {
.irq_ack = aspeed_gpio_irq_ack,
.irq_mask = aspeed_gpio_irq_mask,
.irq_unmask = aspeed_gpio_irq_unmask,
.irq_set_type = aspeed_gpio_set_type,
.irq_print_chip = aspeed_gpio_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
/*
* Any banks not specified in a struct aspeed_bank_props array are assumed to
* have the properties:
*
* { .input = 0xffffffff, .output = 0xffffffff }
*/
static const struct aspeed_bank_props ast2400_bank_props[] = {
/* input output */
{ 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
{ 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
{ },
};
static const struct aspeed_gpio_config ast2400_config =
/* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
{ .nr_gpios = 220, .props = ast2400_bank_props, };
static const struct aspeed_bank_props ast2500_bank_props[] = {
/* input output */
{ 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
{ 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
{ 7, 0x000000ff, 0x000000ff }, /* AC */
{ },
};
static const struct aspeed_gpio_config ast2500_config =
/* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
{ .nr_gpios = 232, .props = ast2500_bank_props, };
static const struct aspeed_bank_props ast2600_bank_props[] = {
/* input output */
{4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */
{5, 0xffffffff, 0xffffff00}, /* U/V/W/X */
{6, 0x0000ffff, 0x0000ffff}, /* Y/Z */
{ },
};
static const struct aspeed_gpio_config ast2600_config =
/*
* ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs.
* We expect ngpio being set in the device tree and this is a fallback
* option.
*/
{ .nr_gpios = 208, .props = ast2600_bank_props, };
static const struct of_device_id aspeed_gpio_of_table[] = {
{ .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
{ .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
{ .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
{}
};
MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
static int __init aspeed_gpio_probe(struct platform_device *pdev)
{
const struct of_device_id *gpio_id;
struct gpio_irq_chip *girq;
struct aspeed_gpio *gpio;
int rc, irq, i, banks, err;
u32 ngpio;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
gpio->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(gpio->base))
return PTR_ERR(gpio->base);
gpio->dev = &pdev->dev;
raw_spin_lock_init(&gpio->lock);
gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
if (!gpio_id)
return -EINVAL;
gpio->clk = of_clk_get(pdev->dev.of_node, 0);
if (IS_ERR(gpio->clk)) {
dev_warn(&pdev->dev,
"Failed to get clock from devicetree, debouncing disabled\n");
gpio->clk = NULL;
}
gpio->config = gpio_id->data;
gpio->chip.parent = &pdev->dev;
err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio);
gpio->chip.ngpio = (u16) ngpio;
if (err)
gpio->chip.ngpio = gpio->config->nr_gpios;
gpio->chip.direction_input = aspeed_gpio_dir_in;
gpio->chip.direction_output = aspeed_gpio_dir_out;
gpio->chip.get_direction = aspeed_gpio_get_direction;
gpio->chip.request = aspeed_gpio_request;
gpio->chip.free = aspeed_gpio_free;
gpio->chip.get = aspeed_gpio_get;
gpio->chip.set = aspeed_gpio_set;
gpio->chip.set_config = aspeed_gpio_set_config;
gpio->chip.label = dev_name(&pdev->dev);
gpio->chip.base = -1;
/* Allocate a cache of the output registers */
banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
gpio->dcache = devm_kcalloc(&pdev->dev,
banks, sizeof(u32), GFP_KERNEL);
if (!gpio->dcache)
return -ENOMEM;
/*
* Populate it with initial values read from the HW and switch
* all command sources to the ARM by default
*/
for (i = 0; i < banks; i++) {
const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
void __iomem *addr = bank_reg(gpio, bank, reg_rdata);
gpio->dcache[i] = ioread32(addr);
aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM);
aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM);
aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM);
aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
}
/* Set up an irqchip */
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
gpio->irq = irq;
girq = &gpio->chip.irq;
gpio_irq_chip_set_chip(girq, &aspeed_gpio_irq_chip);
girq->parent_handler = aspeed_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = gpio->irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
girq->init_valid_mask = aspeed_init_irq_valid_mask;
gpio->offset_timer =
devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
if (!gpio->offset_timer)
return -ENOMEM;
rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
if (rc < 0)
return rc;
return 0;
}
static struct platform_driver aspeed_gpio_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = aspeed_gpio_of_table,
},
};
module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe);
MODULE_DESCRIPTION("Aspeed GPIO Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-aspeed.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ROHM BD9571MWV-M and BD9574MWF-M GPIO driver
*
* Copyright (C) 2017 Marek Vasut <[email protected]>
*
* Based on the TPS65086 driver
*
* NOTE: Interrupts are not supported yet.
*/
#include <linux/gpio/driver.h>
#include <linux/mfd/rohm-generic.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/bd9571mwv.h>
struct bd9571mwv_gpio {
struct regmap *regmap;
struct gpio_chip chip;
};
static int bd9571mwv_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
struct bd9571mwv_gpio *gpio = gpiochip_get_data(chip);
int ret, val;
ret = regmap_read(gpio->regmap, BD9571MWV_GPIO_DIR, &val);
if (ret < 0)
return ret;
if (val & BIT(offset))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static int bd9571mwv_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct bd9571mwv_gpio *gpio = gpiochip_get_data(chip);
regmap_update_bits(gpio->regmap, BD9571MWV_GPIO_DIR, BIT(offset), 0);
return 0;
}
static int bd9571mwv_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct bd9571mwv_gpio *gpio = gpiochip_get_data(chip);
/* Set the initial value */
regmap_update_bits(gpio->regmap, BD9571MWV_GPIO_OUT,
BIT(offset), value ? BIT(offset) : 0);
regmap_update_bits(gpio->regmap, BD9571MWV_GPIO_DIR,
BIT(offset), BIT(offset));
return 0;
}
static int bd9571mwv_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct bd9571mwv_gpio *gpio = gpiochip_get_data(chip);
int ret, val;
ret = regmap_read(gpio->regmap, BD9571MWV_GPIO_IN, &val);
if (ret < 0)
return ret;
return val & BIT(offset);
}
static void bd9571mwv_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct bd9571mwv_gpio *gpio = gpiochip_get_data(chip);
regmap_update_bits(gpio->regmap, BD9571MWV_GPIO_OUT,
BIT(offset), value ? BIT(offset) : 0);
}
static const struct gpio_chip template_chip = {
.label = "bd9571mwv-gpio",
.owner = THIS_MODULE,
.get_direction = bd9571mwv_gpio_get_direction,
.direction_input = bd9571mwv_gpio_direction_input,
.direction_output = bd9571mwv_gpio_direction_output,
.get = bd9571mwv_gpio_get,
.set = bd9571mwv_gpio_set,
.base = -1,
.ngpio = 2,
.can_sleep = true,
};
static int bd9571mwv_gpio_probe(struct platform_device *pdev)
{
struct bd9571mwv_gpio *gpio;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
gpio->regmap = dev_get_regmap(pdev->dev.parent, NULL);
gpio->chip = template_chip;
gpio->chip.parent = pdev->dev.parent;
return devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
}
static const struct platform_device_id bd9571mwv_gpio_id_table[] = {
{ "bd9571mwv-gpio", ROHM_CHIP_TYPE_BD9571 },
{ "bd9574mwf-gpio", ROHM_CHIP_TYPE_BD9574 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, bd9571mwv_gpio_id_table);
static struct platform_driver bd9571mwv_gpio_driver = {
.driver = {
.name = "bd9571mwv-gpio",
},
.probe = bd9571mwv_gpio_probe,
.id_table = bd9571mwv_gpio_id_table,
};
module_platform_driver(bd9571mwv_gpio_driver);
MODULE_AUTHOR("Marek Vasut <[email protected]>");
MODULE_DESCRIPTION("BD9571MWV GPIO driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-bd9571mwv.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Merrifield SoC GPIO driver
*
* Copyright (c) 2016, 2023 Intel Corporation.
* Author: Andy Shevchenko <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/types.h>
#include "gpio-tangier.h"
/* Intel Merrifield has 192 GPIO pins */
#define MRFLD_NGPIO 192
static const struct tng_gpio_pinrange mrfld_gpio_ranges[] = {
GPIO_PINRANGE(0, 11, 146),
GPIO_PINRANGE(12, 13, 144),
GPIO_PINRANGE(14, 15, 35),
GPIO_PINRANGE(16, 16, 164),
GPIO_PINRANGE(17, 18, 105),
GPIO_PINRANGE(19, 22, 101),
GPIO_PINRANGE(23, 30, 107),
GPIO_PINRANGE(32, 43, 67),
GPIO_PINRANGE(44, 63, 195),
GPIO_PINRANGE(64, 67, 140),
GPIO_PINRANGE(68, 69, 165),
GPIO_PINRANGE(70, 71, 65),
GPIO_PINRANGE(72, 76, 228),
GPIO_PINRANGE(77, 86, 37),
GPIO_PINRANGE(87, 87, 48),
GPIO_PINRANGE(88, 88, 47),
GPIO_PINRANGE(89, 96, 49),
GPIO_PINRANGE(97, 97, 34),
GPIO_PINRANGE(102, 119, 83),
GPIO_PINRANGE(120, 123, 79),
GPIO_PINRANGE(124, 135, 115),
GPIO_PINRANGE(137, 142, 158),
GPIO_PINRANGE(154, 163, 24),
GPIO_PINRANGE(164, 176, 215),
GPIO_PINRANGE(177, 189, 127),
GPIO_PINRANGE(190, 191, 178),
};
static const char *mrfld_gpio_get_pinctrl_dev_name(struct tng_gpio *priv)
{
struct device *dev = priv->dev;
struct acpi_device *adev;
const char *name;
adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1);
if (adev) {
name = devm_kstrdup(dev, acpi_dev_name(adev), GFP_KERNEL);
acpi_dev_put(adev);
} else {
name = "pinctrl-merrifield";
}
return name;
}
static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct device *dev = &pdev->dev;
struct tng_gpio *priv;
u32 gpio_base, irq_base;
void __iomem *base;
int retval;
retval = pcim_enable_device(pdev);
if (retval)
return retval;
retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
if (retval)
return dev_err_probe(dev, retval, "I/O memory mapping error\n");
base = pcim_iomap_table(pdev)[1];
irq_base = readl(base + 0 * sizeof(u32));
gpio_base = readl(base + 1 * sizeof(u32));
/* Release the IO mapping, since we already get the info from BAR1 */
pcim_iounmap_regions(pdev, BIT(1));
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
priv->reg_base = pcim_iomap_table(pdev)[0];
priv->pin_info.pin_ranges = mrfld_gpio_ranges;
priv->pin_info.nranges = ARRAY_SIZE(mrfld_gpio_ranges);
priv->pin_info.name = mrfld_gpio_get_pinctrl_dev_name(priv);
if (!priv->pin_info.name)
return -ENOMEM;
priv->info.base = gpio_base;
priv->info.ngpio = MRFLD_NGPIO;
priv->info.first = irq_base;
retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
if (retval < 0)
return retval;
priv->irq = pci_irq_vector(pdev, 0);
priv->wake_regs.gwmr = GWMR_MRFLD;
priv->wake_regs.gwsr = GWSR_MRFLD;
priv->wake_regs.gsir = GSIR_MRFLD;
retval = devm_tng_gpio_probe(dev, priv);
if (retval)
return dev_err_probe(dev, retval, "tng_gpio_probe error\n");
pci_set_drvdata(pdev, priv);
return 0;
}
static const struct pci_device_id mrfld_gpio_ids[] = {
{ PCI_VDEVICE(INTEL, 0x1199) },
{ }
};
MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids);
static struct pci_driver mrfld_gpio_driver = {
.name = "gpio-merrifield",
.id_table = mrfld_gpio_ids,
.probe = mrfld_gpio_probe,
};
module_pci_driver(mrfld_gpio_driver);
MODULE_AUTHOR("Andy Shevchenko <[email protected]>");
MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(GPIO_TANGIER);
| linux-master | drivers/gpio/gpio-merrifield.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ACPI helpers for GPIO API
*
* Copyright (C) 2012, Intel Corporation
* Authors: Mathias Nyman <[email protected]>
* Mika Westerberg <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/dmi.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mutex.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/machine.h>
#include "gpiolib.h"
#include "gpiolib-acpi.h"
static int run_edge_events_on_boot = -1;
module_param(run_edge_events_on_boot, int, 0444);
MODULE_PARM_DESC(run_edge_events_on_boot,
"Run edge _AEI event-handlers at boot: 0=no, 1=yes, -1=auto");
static char *ignore_wake;
module_param(ignore_wake, charp, 0444);
MODULE_PARM_DESC(ignore_wake,
"controller@pin combos on which to ignore the ACPI wake flag "
"ignore_wake=controller@pin[,controller@pin[,...]]");
static char *ignore_interrupt;
module_param(ignore_interrupt, charp, 0444);
MODULE_PARM_DESC(ignore_interrupt,
"controller@pin combos on which to ignore interrupt "
"ignore_interrupt=controller@pin[,controller@pin[,...]]");
struct acpi_gpiolib_dmi_quirk {
bool no_edge_events_on_boot;
char *ignore_wake;
char *ignore_interrupt;
};
/**
* struct acpi_gpio_event - ACPI GPIO event handler data
*
* @node: list-entry of the events list of the struct acpi_gpio_chip
* @handle: handle of ACPI method to execute when the IRQ triggers
* @handler: handler function to pass to request_irq() when requesting the IRQ
* @pin: GPIO pin number on the struct gpio_chip
* @irq: Linux IRQ number for the event, for request_irq() / free_irq()
* @irqflags: flags to pass to request_irq() when requesting the IRQ
* @irq_is_wake: If the ACPI flags indicate the IRQ is a wakeup source
* @irq_requested:True if request_irq() has been done
* @desc: struct gpio_desc for the GPIO pin for this event
*/
struct acpi_gpio_event {
struct list_head node;
acpi_handle handle;
irq_handler_t handler;
unsigned int pin;
unsigned int irq;
unsigned long irqflags;
bool irq_is_wake;
bool irq_requested;
struct gpio_desc *desc;
};
struct acpi_gpio_connection {
struct list_head node;
unsigned int pin;
struct gpio_desc *desc;
};
struct acpi_gpio_chip {
/*
* ACPICA requires that the first field of the context parameter
* passed to acpi_install_address_space_handler() is large enough
* to hold struct acpi_connection_info.
*/
struct acpi_connection_info conn_info;
struct list_head conns;
struct mutex conn_lock;
struct gpio_chip *chip;
struct list_head events;
struct list_head deferred_req_irqs_list_entry;
};
/**
* struct acpi_gpio_info - ACPI GPIO specific information
* @adev: reference to ACPI device which consumes GPIO resource
* @flags: GPIO initialization flags
* @gpioint: if %true this GPIO is of type GpioInt otherwise type is GpioIo
* @pin_config: pin bias as provided by ACPI
* @polarity: interrupt polarity as provided by ACPI
* @triggering: triggering type as provided by ACPI
* @wake_capable: wake capability as provided by ACPI
* @debounce: debounce timeout as provided by ACPI
* @quirks: Linux specific quirks as provided by struct acpi_gpio_mapping
*/
struct acpi_gpio_info {
struct acpi_device *adev;
enum gpiod_flags flags;
bool gpioint;
int pin_config;
int polarity;
int triggering;
bool wake_capable;
unsigned int debounce;
unsigned int quirks;
};
/*
* For GPIO chips which call acpi_gpiochip_request_interrupts() before late_init
* (so builtin drivers) we register the ACPI GpioInt IRQ handlers from a
* late_initcall_sync() handler, so that other builtin drivers can register their
* OpRegions before the event handlers can run. This list contains GPIO chips
* for which the acpi_gpiochip_request_irqs() call has been deferred.
*/
static DEFINE_MUTEX(acpi_gpio_deferred_req_irqs_lock);
static LIST_HEAD(acpi_gpio_deferred_req_irqs_list);
static bool acpi_gpio_deferred_req_irqs_done;
static int acpi_gpiochip_find(struct gpio_chip *gc, void *data)
{
return device_match_acpi_handle(&gc->gpiodev->dev, data);
}
/**
* acpi_get_gpiod() - Translate ACPI GPIO pin to GPIO descriptor usable with GPIO API
* @path: ACPI GPIO controller full path name, (e.g. "\\_SB.GPO1")
* @pin: ACPI GPIO pin number (0-based, controller-relative)
*
* Return: GPIO descriptor to use with Linux generic GPIO API, or ERR_PTR
* error value. Specifically returns %-EPROBE_DEFER if the referenced GPIO
* controller does not have GPIO chip registered at the moment. This is to
* support probe deferral.
*/
static struct gpio_desc *acpi_get_gpiod(char *path, unsigned int pin)
{
struct gpio_chip *chip;
acpi_handle handle;
acpi_status status;
status = acpi_get_handle(NULL, path, &handle);
if (ACPI_FAILURE(status))
return ERR_PTR(-ENODEV);
chip = gpiochip_find(handle, acpi_gpiochip_find);
if (!chip)
return ERR_PTR(-EPROBE_DEFER);
return gpiochip_get_desc(chip, pin);
}
/**
* acpi_get_and_request_gpiod - Translate ACPI GPIO pin to GPIO descriptor and
* hold a refcount to the GPIO device.
* @path: ACPI GPIO controller full path name, (e.g. "\\_SB.GPO1")
* @pin: ACPI GPIO pin number (0-based, controller-relative)
* @label: Label to pass to gpiod_request()
*
* This function is a simple pass-through to acpi_get_gpiod(), except that
* as it is intended for use outside of the GPIO layer (in a similar fashion to
* gpiod_get_index() for example) it also holds a reference to the GPIO device.
*/
struct gpio_desc *acpi_get_and_request_gpiod(char *path, unsigned int pin, char *label)
{
struct gpio_desc *gpio;
int ret;
gpio = acpi_get_gpiod(path, pin);
if (IS_ERR(gpio))
return gpio;
ret = gpiod_request(gpio, label);
if (ret)
return ERR_PTR(ret);
return gpio;
}
EXPORT_SYMBOL_GPL(acpi_get_and_request_gpiod);
static irqreturn_t acpi_gpio_irq_handler(int irq, void *data)
{
struct acpi_gpio_event *event = data;
acpi_evaluate_object(event->handle, NULL, NULL, NULL);
return IRQ_HANDLED;
}
static irqreturn_t acpi_gpio_irq_handler_evt(int irq, void *data)
{
struct acpi_gpio_event *event = data;
acpi_execute_simple_method(event->handle, NULL, event->pin);
return IRQ_HANDLED;
}
static void acpi_gpio_chip_dh(acpi_handle handle, void *data)
{
/* The address of this function is used as a key. */
}
bool acpi_gpio_get_irq_resource(struct acpi_resource *ares,
struct acpi_resource_gpio **agpio)
{
struct acpi_resource_gpio *gpio;
if (ares->type != ACPI_RESOURCE_TYPE_GPIO)
return false;
gpio = &ares->data.gpio;
if (gpio->connection_type != ACPI_RESOURCE_GPIO_TYPE_INT)
return false;
*agpio = gpio;
return true;
}
EXPORT_SYMBOL_GPL(acpi_gpio_get_irq_resource);
/**
* acpi_gpio_get_io_resource - Fetch details of an ACPI resource if it is a GPIO
* I/O resource or return False if not.
* @ares: Pointer to the ACPI resource to fetch
* @agpio: Pointer to a &struct acpi_resource_gpio to store the output pointer
*/
bool acpi_gpio_get_io_resource(struct acpi_resource *ares,
struct acpi_resource_gpio **agpio)
{
struct acpi_resource_gpio *gpio;
if (ares->type != ACPI_RESOURCE_TYPE_GPIO)
return false;
gpio = &ares->data.gpio;
if (gpio->connection_type != ACPI_RESOURCE_GPIO_TYPE_IO)
return false;
*agpio = gpio;
return true;
}
EXPORT_SYMBOL_GPL(acpi_gpio_get_io_resource);
static void acpi_gpiochip_request_irq(struct acpi_gpio_chip *acpi_gpio,
struct acpi_gpio_event *event)
{
struct device *parent = acpi_gpio->chip->parent;
int ret, value;
ret = request_threaded_irq(event->irq, NULL, event->handler,
event->irqflags | IRQF_ONESHOT, "ACPI:Event", event);
if (ret) {
dev_err(parent, "Failed to setup interrupt handler for %d\n", event->irq);
return;
}
if (event->irq_is_wake)
enable_irq_wake(event->irq);
event->irq_requested = true;
/* Make sure we trigger the initial state of edge-triggered IRQs */
if (run_edge_events_on_boot &&
(event->irqflags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))) {
value = gpiod_get_raw_value_cansleep(event->desc);
if (((event->irqflags & IRQF_TRIGGER_RISING) && value == 1) ||
((event->irqflags & IRQF_TRIGGER_FALLING) && value == 0))
event->handler(event->irq, event);
}
}
static void acpi_gpiochip_request_irqs(struct acpi_gpio_chip *acpi_gpio)
{
struct acpi_gpio_event *event;
list_for_each_entry(event, &acpi_gpio->events, node)
acpi_gpiochip_request_irq(acpi_gpio, event);
}
static enum gpiod_flags
acpi_gpio_to_gpiod_flags(const struct acpi_resource_gpio *agpio, int polarity)
{
/* GpioInt() implies input configuration */
if (agpio->connection_type == ACPI_RESOURCE_GPIO_TYPE_INT)
return GPIOD_IN;
switch (agpio->io_restriction) {
case ACPI_IO_RESTRICT_INPUT:
return GPIOD_IN;
case ACPI_IO_RESTRICT_OUTPUT:
/*
* ACPI GPIO resources don't contain an initial value for the
* GPIO. Therefore we deduce that value from the pull field
* and the polarity instead. If the pin is pulled up we assume
* default to be high, if it is pulled down we assume default
* to be low, otherwise we leave pin untouched. For active low
* polarity values will be switched. See also
* Documentation/firmware-guide/acpi/gpio-properties.rst.
*/
switch (agpio->pin_config) {
case ACPI_PIN_CONFIG_PULLUP:
return polarity == GPIO_ACTIVE_LOW ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH;
case ACPI_PIN_CONFIG_PULLDOWN:
return polarity == GPIO_ACTIVE_LOW ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
default:
break;
}
break;
default:
break;
}
/*
* Assume that the BIOS has configured the direction and pull
* accordingly.
*/
return GPIOD_ASIS;
}
static struct gpio_desc *acpi_request_own_gpiod(struct gpio_chip *chip,
struct acpi_resource_gpio *agpio,
unsigned int index,
const char *label)
{
int polarity = GPIO_ACTIVE_HIGH;
enum gpiod_flags flags = acpi_gpio_to_gpiod_flags(agpio, polarity);
unsigned int pin = agpio->pin_table[index];
struct gpio_desc *desc;
int ret;
desc = gpiochip_request_own_desc(chip, pin, label, polarity, flags);
if (IS_ERR(desc))
return desc;
/* ACPI uses hundredths of milliseconds units */
ret = gpio_set_debounce_timeout(desc, agpio->debounce_timeout * 10);
if (ret)
dev_warn(chip->parent,
"Failed to set debounce-timeout for pin 0x%04X, err %d\n",
pin, ret);
return desc;
}
static bool acpi_gpio_in_ignore_list(const char *ignore_list, const char *controller_in,
unsigned int pin_in)
{
const char *controller, *pin_str;
unsigned int pin;
char *endp;
int len;
controller = ignore_list;
while (controller) {
pin_str = strchr(controller, '@');
if (!pin_str)
goto err;
len = pin_str - controller;
if (len == strlen(controller_in) &&
strncmp(controller, controller_in, len) == 0) {
pin = simple_strtoul(pin_str + 1, &endp, 10);
if (*endp != 0 && *endp != ',')
goto err;
if (pin == pin_in)
return true;
}
controller = strchr(controller, ',');
if (controller)
controller++;
}
return false;
err:
pr_err_once("Error: Invalid value for gpiolib_acpi.ignore_...: %s\n", ignore_list);
return false;
}
static bool acpi_gpio_irq_is_wake(struct device *parent,
const struct acpi_resource_gpio *agpio)
{
unsigned int pin = agpio->pin_table[0];
if (agpio->wake_capable != ACPI_WAKE_CAPABLE)
return false;
if (acpi_gpio_in_ignore_list(ignore_wake, dev_name(parent), pin)) {
dev_info(parent, "Ignoring wakeup on pin %u\n", pin);
return false;
}
return true;
}
/* Always returns AE_OK so that we keep looping over the resources */
static acpi_status acpi_gpiochip_alloc_event(struct acpi_resource *ares,
void *context)
{
struct acpi_gpio_chip *acpi_gpio = context;
struct gpio_chip *chip = acpi_gpio->chip;
struct acpi_resource_gpio *agpio;
acpi_handle handle, evt_handle;
struct acpi_gpio_event *event;
irq_handler_t handler = NULL;
struct gpio_desc *desc;
unsigned int pin;
int ret, irq;
if (!acpi_gpio_get_irq_resource(ares, &agpio))
return AE_OK;
handle = ACPI_HANDLE(chip->parent);
pin = agpio->pin_table[0];
if (pin <= 255) {
char ev_name[8];
sprintf(ev_name, "_%c%02X",
agpio->triggering == ACPI_EDGE_SENSITIVE ? 'E' : 'L',
pin);
if (ACPI_SUCCESS(acpi_get_handle(handle, ev_name, &evt_handle)))
handler = acpi_gpio_irq_handler;
}
if (!handler) {
if (ACPI_SUCCESS(acpi_get_handle(handle, "_EVT", &evt_handle)))
handler = acpi_gpio_irq_handler_evt;
}
if (!handler)
return AE_OK;
desc = acpi_request_own_gpiod(chip, agpio, 0, "ACPI:Event");
if (IS_ERR(desc)) {
dev_err(chip->parent,
"Failed to request GPIO for pin 0x%04X, err %ld\n",
pin, PTR_ERR(desc));
return AE_OK;
}
ret = gpiochip_lock_as_irq(chip, pin);
if (ret) {
dev_err(chip->parent,
"Failed to lock GPIO pin 0x%04X as interrupt, err %d\n",
pin, ret);
goto fail_free_desc;
}
irq = gpiod_to_irq(desc);
if (irq < 0) {
dev_err(chip->parent,
"Failed to translate GPIO pin 0x%04X to IRQ, err %d\n",
pin, irq);
goto fail_unlock_irq;
}
if (acpi_gpio_in_ignore_list(ignore_interrupt, dev_name(chip->parent), pin)) {
dev_info(chip->parent, "Ignoring interrupt on pin %u\n", pin);
return AE_OK;
}
event = kzalloc(sizeof(*event), GFP_KERNEL);
if (!event)
goto fail_unlock_irq;
event->irqflags = IRQF_ONESHOT;
if (agpio->triggering == ACPI_LEVEL_SENSITIVE) {
if (agpio->polarity == ACPI_ACTIVE_HIGH)
event->irqflags |= IRQF_TRIGGER_HIGH;
else
event->irqflags |= IRQF_TRIGGER_LOW;
} else {
switch (agpio->polarity) {
case ACPI_ACTIVE_HIGH:
event->irqflags |= IRQF_TRIGGER_RISING;
break;
case ACPI_ACTIVE_LOW:
event->irqflags |= IRQF_TRIGGER_FALLING;
break;
default:
event->irqflags |= IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING;
break;
}
}
event->handle = evt_handle;
event->handler = handler;
event->irq = irq;
event->irq_is_wake = acpi_gpio_irq_is_wake(chip->parent, agpio);
event->pin = pin;
event->desc = desc;
list_add_tail(&event->node, &acpi_gpio->events);
return AE_OK;
fail_unlock_irq:
gpiochip_unlock_as_irq(chip, pin);
fail_free_desc:
gpiochip_free_own_desc(desc);
return AE_OK;
}
/**
* acpi_gpiochip_request_interrupts() - Register isr for gpio chip ACPI events
* @chip: GPIO chip
*
* ACPI5 platforms can use GPIO signaled ACPI events. These GPIO interrupts are
* handled by ACPI event methods which need to be called from the GPIO
* chip's interrupt handler. acpi_gpiochip_request_interrupts() finds out which
* GPIO pins have ACPI event methods and assigns interrupt handlers that calls
* the ACPI event methods for those pins.
*/
void acpi_gpiochip_request_interrupts(struct gpio_chip *chip)
{
struct acpi_gpio_chip *acpi_gpio;
acpi_handle handle;
acpi_status status;
bool defer;
if (!chip->parent || !chip->to_irq)
return;
handle = ACPI_HANDLE(chip->parent);
if (!handle)
return;
status = acpi_get_data(handle, acpi_gpio_chip_dh, (void **)&acpi_gpio);
if (ACPI_FAILURE(status))
return;
if (acpi_quirk_skip_gpio_event_handlers())
return;
acpi_walk_resources(handle, METHOD_NAME__AEI,
acpi_gpiochip_alloc_event, acpi_gpio);
mutex_lock(&acpi_gpio_deferred_req_irqs_lock);
defer = !acpi_gpio_deferred_req_irqs_done;
if (defer)
list_add(&acpi_gpio->deferred_req_irqs_list_entry,
&acpi_gpio_deferred_req_irqs_list);
mutex_unlock(&acpi_gpio_deferred_req_irqs_lock);
if (defer)
return;
acpi_gpiochip_request_irqs(acpi_gpio);
}
EXPORT_SYMBOL_GPL(acpi_gpiochip_request_interrupts);
/**
* acpi_gpiochip_free_interrupts() - Free GPIO ACPI event interrupts.
* @chip: GPIO chip
*
* Free interrupts associated with GPIO ACPI event method for the given
* GPIO chip.
*/
void acpi_gpiochip_free_interrupts(struct gpio_chip *chip)
{
struct acpi_gpio_chip *acpi_gpio;
struct acpi_gpio_event *event, *ep;
acpi_handle handle;
acpi_status status;
if (!chip->parent || !chip->to_irq)
return;
handle = ACPI_HANDLE(chip->parent);
if (!handle)
return;
status = acpi_get_data(handle, acpi_gpio_chip_dh, (void **)&acpi_gpio);
if (ACPI_FAILURE(status))
return;
mutex_lock(&acpi_gpio_deferred_req_irqs_lock);
if (!list_empty(&acpi_gpio->deferred_req_irqs_list_entry))
list_del_init(&acpi_gpio->deferred_req_irqs_list_entry);
mutex_unlock(&acpi_gpio_deferred_req_irqs_lock);
list_for_each_entry_safe_reverse(event, ep, &acpi_gpio->events, node) {
if (event->irq_requested) {
if (event->irq_is_wake)
disable_irq_wake(event->irq);
free_irq(event->irq, event);
}
gpiochip_unlock_as_irq(chip, event->pin);
gpiochip_free_own_desc(event->desc);
list_del(&event->node);
kfree(event);
}
}
EXPORT_SYMBOL_GPL(acpi_gpiochip_free_interrupts);
int acpi_dev_add_driver_gpios(struct acpi_device *adev,
const struct acpi_gpio_mapping *gpios)
{
if (adev && gpios) {
adev->driver_gpios = gpios;
return 0;
}
return -EINVAL;
}
EXPORT_SYMBOL_GPL(acpi_dev_add_driver_gpios);
void acpi_dev_remove_driver_gpios(struct acpi_device *adev)
{
if (adev)
adev->driver_gpios = NULL;
}
EXPORT_SYMBOL_GPL(acpi_dev_remove_driver_gpios);
static void acpi_dev_release_driver_gpios(void *adev)
{
acpi_dev_remove_driver_gpios(adev);
}
int devm_acpi_dev_add_driver_gpios(struct device *dev,
const struct acpi_gpio_mapping *gpios)
{
struct acpi_device *adev = ACPI_COMPANION(dev);
int ret;
ret = acpi_dev_add_driver_gpios(adev, gpios);
if (ret)
return ret;
return devm_add_action_or_reset(dev, acpi_dev_release_driver_gpios, adev);
}
EXPORT_SYMBOL_GPL(devm_acpi_dev_add_driver_gpios);
static bool acpi_get_driver_gpio_data(struct acpi_device *adev,
const char *name, int index,
struct fwnode_reference_args *args,
unsigned int *quirks)
{
const struct acpi_gpio_mapping *gm;
if (!adev || !adev->driver_gpios)
return false;
for (gm = adev->driver_gpios; gm->name; gm++)
if (!strcmp(name, gm->name) && gm->data && index < gm->size) {
const struct acpi_gpio_params *par = gm->data + index;
args->fwnode = acpi_fwnode_handle(adev);
args->args[0] = par->crs_entry_index;
args->args[1] = par->line_index;
args->args[2] = par->active_low;
args->nargs = 3;
*quirks = gm->quirks;
return true;
}
return false;
}
static int
__acpi_gpio_update_gpiod_flags(enum gpiod_flags *flags, enum gpiod_flags update)
{
const enum gpiod_flags mask =
GPIOD_FLAGS_BIT_DIR_SET | GPIOD_FLAGS_BIT_DIR_OUT |
GPIOD_FLAGS_BIT_DIR_VAL;
int ret = 0;
/*
* Check if the BIOS has IoRestriction with explicitly set direction
* and update @flags accordingly. Otherwise use whatever caller asked
* for.
*/
if (update & GPIOD_FLAGS_BIT_DIR_SET) {
enum gpiod_flags diff = *flags ^ update;
/*
* Check if caller supplied incompatible GPIO initialization
* flags.
*
* Return %-EINVAL to notify that firmware has different
* settings and we are going to use them.
*/
if (((*flags & GPIOD_FLAGS_BIT_DIR_SET) && (diff & GPIOD_FLAGS_BIT_DIR_OUT)) ||
((*flags & GPIOD_FLAGS_BIT_DIR_OUT) && (diff & GPIOD_FLAGS_BIT_DIR_VAL)))
ret = -EINVAL;
*flags = (*flags & ~mask) | (update & mask);
}
return ret;
}
static int acpi_gpio_update_gpiod_flags(enum gpiod_flags *flags,
struct acpi_gpio_info *info)
{
struct device *dev = &info->adev->dev;
enum gpiod_flags old = *flags;
int ret;
ret = __acpi_gpio_update_gpiod_flags(&old, info->flags);
if (info->quirks & ACPI_GPIO_QUIRK_NO_IO_RESTRICTION) {
if (ret)
dev_warn(dev, FW_BUG "GPIO not in correct mode, fixing\n");
} else {
if (ret)
dev_dbg(dev, "Override GPIO initialization flags\n");
*flags = old;
}
return ret;
}
static int acpi_gpio_update_gpiod_lookup_flags(unsigned long *lookupflags,
struct acpi_gpio_info *info)
{
switch (info->pin_config) {
case ACPI_PIN_CONFIG_PULLUP:
*lookupflags |= GPIO_PULL_UP;
break;
case ACPI_PIN_CONFIG_PULLDOWN:
*lookupflags |= GPIO_PULL_DOWN;
break;
case ACPI_PIN_CONFIG_NOPULL:
*lookupflags |= GPIO_PULL_DISABLE;
break;
default:
break;
}
if (info->polarity == GPIO_ACTIVE_LOW)
*lookupflags |= GPIO_ACTIVE_LOW;
return 0;
}
struct acpi_gpio_lookup {
struct acpi_gpio_info info;
int index;
u16 pin_index;
bool active_low;
struct gpio_desc *desc;
int n;
};
static int acpi_populate_gpio_lookup(struct acpi_resource *ares, void *data)
{
struct acpi_gpio_lookup *lookup = data;
if (ares->type != ACPI_RESOURCE_TYPE_GPIO)
return 1;
if (!lookup->desc) {
const struct acpi_resource_gpio *agpio = &ares->data.gpio;
bool gpioint = agpio->connection_type == ACPI_RESOURCE_GPIO_TYPE_INT;
struct gpio_desc *desc;
u16 pin_index;
if (lookup->info.quirks & ACPI_GPIO_QUIRK_ONLY_GPIOIO && gpioint)
lookup->index++;
if (lookup->n++ != lookup->index)
return 1;
pin_index = lookup->pin_index;
if (pin_index >= agpio->pin_table_length)
return 1;
if (lookup->info.quirks & ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER)
desc = gpio_to_desc(agpio->pin_table[pin_index]);
else
desc = acpi_get_gpiod(agpio->resource_source.string_ptr,
agpio->pin_table[pin_index]);
lookup->desc = desc;
lookup->info.pin_config = agpio->pin_config;
lookup->info.debounce = agpio->debounce_timeout;
lookup->info.gpioint = gpioint;
lookup->info.wake_capable = acpi_gpio_irq_is_wake(&lookup->info.adev->dev, agpio);
/*
* Polarity and triggering are only specified for GpioInt
* resource.
* Note: we expect here:
* - ACPI_ACTIVE_LOW == GPIO_ACTIVE_LOW
* - ACPI_ACTIVE_HIGH == GPIO_ACTIVE_HIGH
*/
if (lookup->info.gpioint) {
lookup->info.polarity = agpio->polarity;
lookup->info.triggering = agpio->triggering;
} else {
lookup->info.polarity = lookup->active_low;
}
lookup->info.flags = acpi_gpio_to_gpiod_flags(agpio, lookup->info.polarity);
}
return 1;
}
static int acpi_gpio_resource_lookup(struct acpi_gpio_lookup *lookup,
struct acpi_gpio_info *info)
{
struct acpi_device *adev = lookup->info.adev;
struct list_head res_list;
int ret;
INIT_LIST_HEAD(&res_list);
ret = acpi_dev_get_resources(adev, &res_list,
acpi_populate_gpio_lookup,
lookup);
if (ret < 0)
return ret;
acpi_dev_free_resource_list(&res_list);
if (!lookup->desc)
return -ENOENT;
if (info)
*info = lookup->info;
return 0;
}
static int acpi_gpio_property_lookup(struct fwnode_handle *fwnode,
const char *propname, int index,
struct acpi_gpio_lookup *lookup)
{
struct fwnode_reference_args args;
unsigned int quirks = 0;
int ret;
memset(&args, 0, sizeof(args));
ret = __acpi_node_get_property_reference(fwnode, propname, index, 3,
&args);
if (ret) {
struct acpi_device *adev;
adev = to_acpi_device_node(fwnode);
if (!acpi_get_driver_gpio_data(adev, propname, index, &args, &quirks))
return ret;
}
/*
* The property was found and resolved, so need to lookup the GPIO based
* on returned args.
*/
if (!to_acpi_device_node(args.fwnode))
return -EINVAL;
if (args.nargs != 3)
return -EPROTO;
lookup->index = args.args[0];
lookup->pin_index = args.args[1];
lookup->active_low = !!args.args[2];
lookup->info.adev = to_acpi_device_node(args.fwnode);
lookup->info.quirks = quirks;
return 0;
}
/**
* acpi_get_gpiod_by_index() - get a GPIO descriptor from device resources
* @adev: pointer to a ACPI device to get GPIO from
* @propname: Property name of the GPIO (optional)
* @index: index of GpioIo/GpioInt resource (starting from %0)
* @info: info pointer to fill in (optional)
*
* Function goes through ACPI resources for @adev and based on @index looks
* up a GpioIo/GpioInt resource, translates it to the Linux GPIO descriptor,
* and returns it. @index matches GpioIo/GpioInt resources only so if there
* are total %3 GPIO resources, the index goes from %0 to %2.
*
* If @propname is specified the GPIO is looked using device property. In
* that case @index is used to select the GPIO entry in the property value
* (in case of multiple).
*
* If the GPIO cannot be translated or there is an error, an ERR_PTR is
* returned.
*
* Note: if the GPIO resource has multiple entries in the pin list, this
* function only returns the first.
*/
static struct gpio_desc *acpi_get_gpiod_by_index(struct acpi_device *adev,
const char *propname,
int index,
struct acpi_gpio_info *info)
{
struct acpi_gpio_lookup lookup;
int ret;
if (!adev)
return ERR_PTR(-ENODEV);
memset(&lookup, 0, sizeof(lookup));
lookup.index = index;
if (propname) {
dev_dbg(&adev->dev, "GPIO: looking up %s\n", propname);
ret = acpi_gpio_property_lookup(acpi_fwnode_handle(adev),
propname, index, &lookup);
if (ret)
return ERR_PTR(ret);
dev_dbg(&adev->dev, "GPIO: _DSD returned %s %d %u %u\n",
dev_name(&lookup.info.adev->dev), lookup.index,
lookup.pin_index, lookup.active_low);
} else {
dev_dbg(&adev->dev, "GPIO: looking up %d in _CRS\n", index);
lookup.info.adev = adev;
}
ret = acpi_gpio_resource_lookup(&lookup, info);
return ret ? ERR_PTR(ret) : lookup.desc;
}
/**
* acpi_get_gpiod_from_data() - get a GPIO descriptor from ACPI data node
* @fwnode: pointer to an ACPI firmware node to get the GPIO information from
* @propname: Property name of the GPIO
* @index: index of GpioIo/GpioInt resource (starting from %0)
* @info: info pointer to fill in (optional)
*
* This function uses the property-based GPIO lookup to get to the GPIO
* resource with the relevant information from a data-only ACPI firmware node
* and uses that to obtain the GPIO descriptor to return.
*
* If the GPIO cannot be translated or there is an error an ERR_PTR is
* returned.
*/
static struct gpio_desc *acpi_get_gpiod_from_data(struct fwnode_handle *fwnode,
const char *propname,
int index,
struct acpi_gpio_info *info)
{
struct acpi_gpio_lookup lookup;
int ret;
if (!is_acpi_data_node(fwnode))
return ERR_PTR(-ENODEV);
if (!propname)
return ERR_PTR(-EINVAL);
lookup.index = index;
ret = acpi_gpio_property_lookup(fwnode, propname, index, &lookup);
if (ret)
return ERR_PTR(ret);
ret = acpi_gpio_resource_lookup(&lookup, info);
return ret ? ERR_PTR(ret) : lookup.desc;
}
static bool acpi_can_fallback_to_crs(struct acpi_device *adev,
const char *con_id)
{
/* Never allow fallback if the device has properties */
if (acpi_dev_has_props(adev) || adev->driver_gpios)
return false;
return con_id == NULL;
}
struct gpio_desc *acpi_find_gpio(struct fwnode_handle *fwnode,
const char *con_id,
unsigned int idx,
enum gpiod_flags *dflags,
unsigned long *lookupflags)
{
struct acpi_device *adev = to_acpi_device_node(fwnode);
struct acpi_gpio_info info;
struct gpio_desc *desc;
char propname[32];
int i;
/* Try first from _DSD */
for (i = 0; i < ARRAY_SIZE(gpio_suffixes); i++) {
if (con_id) {
snprintf(propname, sizeof(propname), "%s-%s",
con_id, gpio_suffixes[i]);
} else {
snprintf(propname, sizeof(propname), "%s",
gpio_suffixes[i]);
}
if (adev)
desc = acpi_get_gpiod_by_index(adev,
propname, idx, &info);
else
desc = acpi_get_gpiod_from_data(fwnode,
propname, idx, &info);
if (!IS_ERR(desc))
break;
if (PTR_ERR(desc) == -EPROBE_DEFER)
return ERR_CAST(desc);
}
/* Then from plain _CRS GPIOs */
if (IS_ERR(desc)) {
if (!adev || !acpi_can_fallback_to_crs(adev, con_id))
return ERR_PTR(-ENOENT);
desc = acpi_get_gpiod_by_index(adev, NULL, idx, &info);
if (IS_ERR(desc))
return desc;
}
if (info.gpioint &&
(*dflags == GPIOD_OUT_LOW || *dflags == GPIOD_OUT_HIGH)) {
dev_dbg(&adev->dev, "refusing GpioInt() entry when doing GPIOD_OUT_* lookup\n");
return ERR_PTR(-ENOENT);
}
acpi_gpio_update_gpiod_flags(dflags, &info);
acpi_gpio_update_gpiod_lookup_flags(lookupflags, &info);
return desc;
}
/**
* acpi_dev_gpio_irq_wake_get_by() - Find GpioInt and translate it to Linux IRQ number
* @adev: pointer to a ACPI device to get IRQ from
* @name: optional name of GpioInt resource
* @index: index of GpioInt resource (starting from %0)
* @wake_capable: Set to true if the IRQ is wake capable
*
* If the device has one or more GpioInt resources, this function can be
* used to translate from the GPIO offset in the resource to the Linux IRQ
* number.
*
* The function is idempotent, though each time it runs it will configure GPIO
* pin direction according to the flags in GpioInt resource.
*
* The function takes optional @name parameter. If the resource has a property
* name, then only those will be taken into account.
*
* The GPIO is considered wake capable if the GpioInt resource specifies
* SharedAndWake or ExclusiveAndWake.
*
* Return: Linux IRQ number (> %0) on success, negative errno on failure.
*/
int acpi_dev_gpio_irq_wake_get_by(struct acpi_device *adev, const char *name, int index,
bool *wake_capable)
{
int idx, i;
unsigned int irq_flags;
int ret;
for (i = 0, idx = 0; idx <= index; i++) {
struct acpi_gpio_info info;
struct gpio_desc *desc;
desc = acpi_get_gpiod_by_index(adev, name, i, &info);
/* Ignore -EPROBE_DEFER, it only matters if idx matches */
if (IS_ERR(desc) && PTR_ERR(desc) != -EPROBE_DEFER)
return PTR_ERR(desc);
if (info.gpioint && idx++ == index) {
unsigned long lflags = GPIO_LOOKUP_FLAGS_DEFAULT;
enum gpiod_flags dflags = GPIOD_ASIS;
char label[32];
int irq;
if (IS_ERR(desc))
return PTR_ERR(desc);
irq = gpiod_to_irq(desc);
if (irq < 0)
return irq;
acpi_gpio_update_gpiod_flags(&dflags, &info);
acpi_gpio_update_gpiod_lookup_flags(&lflags, &info);
snprintf(label, sizeof(label), "GpioInt() %d", index);
ret = gpiod_configure_flags(desc, label, lflags, dflags);
if (ret < 0)
return ret;
/* ACPI uses hundredths of milliseconds units */
ret = gpio_set_debounce_timeout(desc, info.debounce * 10);
if (ret)
return ret;
irq_flags = acpi_dev_get_irq_type(info.triggering,
info.polarity);
/*
* If the IRQ is not already in use then set type
* if specified and different than the current one.
*/
if (can_request_irq(irq, irq_flags)) {
if (irq_flags != IRQ_TYPE_NONE &&
irq_flags != irq_get_trigger_type(irq))
irq_set_irq_type(irq, irq_flags);
} else {
dev_dbg(&adev->dev, "IRQ %d already in use\n", irq);
}
/* avoid suspend issues with GPIOs when systems are using S3 */
if (wake_capable && acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)
*wake_capable = info.wake_capable;
return irq;
}
}
return -ENOENT;
}
EXPORT_SYMBOL_GPL(acpi_dev_gpio_irq_wake_get_by);
static acpi_status
acpi_gpio_adr_space_handler(u32 function, acpi_physical_address address,
u32 bits, u64 *value, void *handler_context,
void *region_context)
{
struct acpi_gpio_chip *achip = region_context;
struct gpio_chip *chip = achip->chip;
struct acpi_resource_gpio *agpio;
struct acpi_resource *ares;
u16 pin_index = address;
acpi_status status;
int length;
int i;
status = acpi_buffer_to_resource(achip->conn_info.connection,
achip->conn_info.length, &ares);
if (ACPI_FAILURE(status))
return status;
if (WARN_ON(ares->type != ACPI_RESOURCE_TYPE_GPIO)) {
ACPI_FREE(ares);
return AE_BAD_PARAMETER;
}
agpio = &ares->data.gpio;
if (WARN_ON(agpio->io_restriction == ACPI_IO_RESTRICT_INPUT &&
function == ACPI_WRITE)) {
ACPI_FREE(ares);
return AE_BAD_PARAMETER;
}
length = min_t(u16, agpio->pin_table_length, pin_index + bits);
for (i = pin_index; i < length; ++i) {
unsigned int pin = agpio->pin_table[i];
struct acpi_gpio_connection *conn;
struct gpio_desc *desc;
bool found;
mutex_lock(&achip->conn_lock);
found = false;
list_for_each_entry(conn, &achip->conns, node) {
if (conn->pin == pin) {
found = true;
desc = conn->desc;
break;
}
}
/*
* The same GPIO can be shared between operation region and
* event but only if the access here is ACPI_READ. In that
* case we "borrow" the event GPIO instead.
*/
if (!found && agpio->shareable == ACPI_SHARED &&
function == ACPI_READ) {
struct acpi_gpio_event *event;
list_for_each_entry(event, &achip->events, node) {
if (event->pin == pin) {
desc = event->desc;
found = true;
break;
}
}
}
if (!found) {
desc = acpi_request_own_gpiod(chip, agpio, i, "ACPI:OpRegion");
if (IS_ERR(desc)) {
mutex_unlock(&achip->conn_lock);
status = AE_ERROR;
goto out;
}
conn = kzalloc(sizeof(*conn), GFP_KERNEL);
if (!conn) {
gpiochip_free_own_desc(desc);
mutex_unlock(&achip->conn_lock);
status = AE_NO_MEMORY;
goto out;
}
conn->pin = pin;
conn->desc = desc;
list_add_tail(&conn->node, &achip->conns);
}
mutex_unlock(&achip->conn_lock);
if (function == ACPI_WRITE)
gpiod_set_raw_value_cansleep(desc, !!(*value & BIT(i)));
else
*value |= (u64)gpiod_get_raw_value_cansleep(desc) << i;
}
out:
ACPI_FREE(ares);
return status;
}
static void acpi_gpiochip_request_regions(struct acpi_gpio_chip *achip)
{
struct gpio_chip *chip = achip->chip;
acpi_handle handle = ACPI_HANDLE(chip->parent);
acpi_status status;
INIT_LIST_HEAD(&achip->conns);
mutex_init(&achip->conn_lock);
status = acpi_install_address_space_handler(handle, ACPI_ADR_SPACE_GPIO,
acpi_gpio_adr_space_handler,
NULL, achip);
if (ACPI_FAILURE(status))
dev_err(chip->parent,
"Failed to install GPIO OpRegion handler\n");
}
static void acpi_gpiochip_free_regions(struct acpi_gpio_chip *achip)
{
struct gpio_chip *chip = achip->chip;
acpi_handle handle = ACPI_HANDLE(chip->parent);
struct acpi_gpio_connection *conn, *tmp;
acpi_status status;
status = acpi_remove_address_space_handler(handle, ACPI_ADR_SPACE_GPIO,
acpi_gpio_adr_space_handler);
if (ACPI_FAILURE(status)) {
dev_err(chip->parent,
"Failed to remove GPIO OpRegion handler\n");
return;
}
list_for_each_entry_safe_reverse(conn, tmp, &achip->conns, node) {
gpiochip_free_own_desc(conn->desc);
list_del(&conn->node);
kfree(conn);
}
}
static struct gpio_desc *
acpi_gpiochip_parse_own_gpio(struct acpi_gpio_chip *achip,
struct fwnode_handle *fwnode,
const char **name,
unsigned long *lflags,
enum gpiod_flags *dflags)
{
struct gpio_chip *chip = achip->chip;
struct gpio_desc *desc;
u32 gpios[2];
int ret;
*lflags = GPIO_LOOKUP_FLAGS_DEFAULT;
*dflags = GPIOD_ASIS;
*name = NULL;
ret = fwnode_property_read_u32_array(fwnode, "gpios", gpios,
ARRAY_SIZE(gpios));
if (ret < 0)
return ERR_PTR(ret);
desc = gpiochip_get_desc(chip, gpios[0]);
if (IS_ERR(desc))
return desc;
if (gpios[1])
*lflags |= GPIO_ACTIVE_LOW;
if (fwnode_property_present(fwnode, "input"))
*dflags |= GPIOD_IN;
else if (fwnode_property_present(fwnode, "output-low"))
*dflags |= GPIOD_OUT_LOW;
else if (fwnode_property_present(fwnode, "output-high"))
*dflags |= GPIOD_OUT_HIGH;
else
return ERR_PTR(-EINVAL);
fwnode_property_read_string(fwnode, "line-name", name);
return desc;
}
static void acpi_gpiochip_scan_gpios(struct acpi_gpio_chip *achip)
{
struct gpio_chip *chip = achip->chip;
struct fwnode_handle *fwnode;
device_for_each_child_node(chip->parent, fwnode) {
unsigned long lflags;
enum gpiod_flags dflags;
struct gpio_desc *desc;
const char *name;
int ret;
if (!fwnode_property_present(fwnode, "gpio-hog"))
continue;
desc = acpi_gpiochip_parse_own_gpio(achip, fwnode, &name,
&lflags, &dflags);
if (IS_ERR(desc))
continue;
ret = gpiod_hog(desc, name, lflags, dflags);
if (ret) {
dev_err(chip->parent, "Failed to hog GPIO\n");
fwnode_handle_put(fwnode);
return;
}
}
}
void acpi_gpiochip_add(struct gpio_chip *chip)
{
struct acpi_gpio_chip *acpi_gpio;
struct acpi_device *adev;
acpi_status status;
if (!chip || !chip->parent)
return;
adev = ACPI_COMPANION(chip->parent);
if (!adev)
return;
acpi_gpio = kzalloc(sizeof(*acpi_gpio), GFP_KERNEL);
if (!acpi_gpio) {
dev_err(chip->parent,
"Failed to allocate memory for ACPI GPIO chip\n");
return;
}
acpi_gpio->chip = chip;
INIT_LIST_HEAD(&acpi_gpio->events);
INIT_LIST_HEAD(&acpi_gpio->deferred_req_irqs_list_entry);
status = acpi_attach_data(adev->handle, acpi_gpio_chip_dh, acpi_gpio);
if (ACPI_FAILURE(status)) {
dev_err(chip->parent, "Failed to attach ACPI GPIO chip\n");
kfree(acpi_gpio);
return;
}
acpi_gpiochip_request_regions(acpi_gpio);
acpi_gpiochip_scan_gpios(acpi_gpio);
acpi_dev_clear_dependencies(adev);
}
void acpi_gpiochip_remove(struct gpio_chip *chip)
{
struct acpi_gpio_chip *acpi_gpio;
acpi_handle handle;
acpi_status status;
if (!chip || !chip->parent)
return;
handle = ACPI_HANDLE(chip->parent);
if (!handle)
return;
status = acpi_get_data(handle, acpi_gpio_chip_dh, (void **)&acpi_gpio);
if (ACPI_FAILURE(status)) {
dev_warn(chip->parent, "Failed to retrieve ACPI GPIO chip\n");
return;
}
acpi_gpiochip_free_regions(acpi_gpio);
acpi_detach_data(handle, acpi_gpio_chip_dh);
kfree(acpi_gpio);
}
static int acpi_gpio_package_count(const union acpi_object *obj)
{
const union acpi_object *element = obj->package.elements;
const union acpi_object *end = element + obj->package.count;
unsigned int count = 0;
while (element < end) {
switch (element->type) {
case ACPI_TYPE_LOCAL_REFERENCE:
element += 3;
fallthrough;
case ACPI_TYPE_INTEGER:
element++;
count++;
break;
default:
return -EPROTO;
}
}
return count;
}
static int acpi_find_gpio_count(struct acpi_resource *ares, void *data)
{
unsigned int *count = data;
if (ares->type == ACPI_RESOURCE_TYPE_GPIO)
*count += ares->data.gpio.pin_table_length;
return 1;
}
/**
* acpi_gpio_count - count the GPIOs associated with a device / function
* @dev: GPIO consumer, can be %NULL for system-global GPIOs
* @con_id: function within the GPIO consumer
*
* Return:
* The number of GPIOs associated with a device / function or %-ENOENT,
* if no GPIO has been assigned to the requested function.
*/
int acpi_gpio_count(struct device *dev, const char *con_id)
{
struct acpi_device *adev = ACPI_COMPANION(dev);
const union acpi_object *obj;
const struct acpi_gpio_mapping *gm;
int count = -ENOENT;
int ret;
char propname[32];
unsigned int i;
/* Try first from _DSD */
for (i = 0; i < ARRAY_SIZE(gpio_suffixes); i++) {
if (con_id)
snprintf(propname, sizeof(propname), "%s-%s",
con_id, gpio_suffixes[i]);
else
snprintf(propname, sizeof(propname), "%s",
gpio_suffixes[i]);
ret = acpi_dev_get_property(adev, propname, ACPI_TYPE_ANY,
&obj);
if (ret == 0) {
if (obj->type == ACPI_TYPE_LOCAL_REFERENCE)
count = 1;
else if (obj->type == ACPI_TYPE_PACKAGE)
count = acpi_gpio_package_count(obj);
} else if (adev->driver_gpios) {
for (gm = adev->driver_gpios; gm->name; gm++)
if (strcmp(propname, gm->name) == 0) {
count = gm->size;
break;
}
}
if (count > 0)
break;
}
/* Then from plain _CRS GPIOs */
if (count < 0) {
struct list_head resource_list;
unsigned int crs_count = 0;
if (!acpi_can_fallback_to_crs(adev, con_id))
return count;
INIT_LIST_HEAD(&resource_list);
acpi_dev_get_resources(adev, &resource_list,
acpi_find_gpio_count, &crs_count);
acpi_dev_free_resource_list(&resource_list);
if (crs_count > 0)
count = crs_count;
}
return count ? count : -ENOENT;
}
/* Run deferred acpi_gpiochip_request_irqs() */
static int __init acpi_gpio_handle_deferred_request_irqs(void)
{
struct acpi_gpio_chip *acpi_gpio, *tmp;
mutex_lock(&acpi_gpio_deferred_req_irqs_lock);
list_for_each_entry_safe(acpi_gpio, tmp,
&acpi_gpio_deferred_req_irqs_list,
deferred_req_irqs_list_entry)
acpi_gpiochip_request_irqs(acpi_gpio);
acpi_gpio_deferred_req_irqs_done = true;
mutex_unlock(&acpi_gpio_deferred_req_irqs_lock);
return 0;
}
/* We must use _sync so that this runs after the first deferred_probe run */
late_initcall_sync(acpi_gpio_handle_deferred_request_irqs);
static const struct dmi_system_id gpiolib_acpi_quirks[] __initconst = {
{
/*
* The Minix Neo Z83-4 has a micro-USB-B id-pin handler for
* a non existing micro-USB-B connector which puts the HDMI
* DDC pins in GPIO mode, breaking HDMI support.
*/
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "MINIX"),
DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"),
},
.driver_data = &(struct acpi_gpiolib_dmi_quirk) {
.no_edge_events_on_boot = true,
},
},
{
/*
* The Terra Pad 1061 has a micro-USB-B id-pin handler, which
* instead of controlling the actual micro-USB-B turns the 5V
* boost for its USB-A connector off. The actual micro-USB-B
* connector is wired for charging only.
*/
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Wortmann_AG"),
DMI_MATCH(DMI_PRODUCT_NAME, "TERRA_PAD_1061"),
},
.driver_data = &(struct acpi_gpiolib_dmi_quirk) {
.no_edge_events_on_boot = true,
},
},
{
/*
* The Dell Venue 10 Pro 5055, with Bay Trail SoC + TI PMIC uses an
* external embedded-controller connected via I2C + an ACPI GPIO
* event handler on INT33FFC:02 pin 12, causing spurious wakeups.
*/
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "Venue 10 Pro 5055"),
},
.driver_data = &(struct acpi_gpiolib_dmi_quirk) {
.ignore_wake = "INT33FC:02@12",
},
},
{
/*
* HP X2 10 models with Cherry Trail SoC + TI PMIC use an
* external embedded-controller connected via I2C + an ACPI GPIO
* event handler on INT33FF:01 pin 0, causing spurious wakeups.
* When suspending by closing the LID, the power to the USB
* keyboard is turned off, causing INT0002 ACPI events to
* trigger once the XHCI controller notices the keyboard is
* gone. So INT0002 events cause spurious wakeups too. Ignoring
* EC wakes breaks wakeup when opening the lid, the user needs
* to press the power-button to wakeup the system. The
* alternative is suspend simply not working, which is worse.
*/
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
DMI_MATCH(DMI_PRODUCT_NAME, "HP x2 Detachable 10-p0XX"),
},
.driver_data = &(struct acpi_gpiolib_dmi_quirk) {
.ignore_wake = "INT33FF:01@0,INT0002:00@2",
},
},
{
/*
* HP X2 10 models with Bay Trail SoC + AXP288 PMIC use an
* external embedded-controller connected via I2C + an ACPI GPIO
* event handler on INT33FC:02 pin 28, causing spurious wakeups.
*/
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion x2 Detachable"),
DMI_MATCH(DMI_BOARD_NAME, "815D"),
},
.driver_data = &(struct acpi_gpiolib_dmi_quirk) {
.ignore_wake = "INT33FC:02@28",
},
},
{
/*
* HP X2 10 models with Cherry Trail SoC + AXP288 PMIC use an
* external embedded-controller connected via I2C + an ACPI GPIO
* event handler on INT33FF:01 pin 0, causing spurious wakeups.
*/
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion x2 Detachable"),
DMI_MATCH(DMI_BOARD_NAME, "813E"),
},
.driver_data = &(struct acpi_gpiolib_dmi_quirk) {
.ignore_wake = "INT33FF:01@0",
},
},
{
/*
* Interrupt storm caused from edge triggered floating pin
* Found in BIOS UX325UAZ.300
* https://bugzilla.kernel.org/show_bug.cgi?id=216208
*/
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_PRODUCT_NAME, "ZenBook UX325UAZ_UM325UAZ"),
},
.driver_data = &(struct acpi_gpiolib_dmi_quirk) {
.ignore_interrupt = "AMDI0030:00@18",
},
},
{
/*
* Spurious wakeups from TP_ATTN# pin
* Found in BIOS 1.7.8
* https://gitlab.freedesktop.org/drm/amd/-/issues/1722#note_1720627
*/
.matches = {
DMI_MATCH(DMI_BOARD_NAME, "NL5xNU"),
},
.driver_data = &(struct acpi_gpiolib_dmi_quirk) {
.ignore_wake = "ELAN0415:00@9",
},
},
{
/*
* Spurious wakeups from TP_ATTN# pin
* Found in BIOS 1.7.8
* https://gitlab.freedesktop.org/drm/amd/-/issues/1722#note_1720627
*/
.matches = {
DMI_MATCH(DMI_BOARD_NAME, "NL5xRU"),
},
.driver_data = &(struct acpi_gpiolib_dmi_quirk) {
.ignore_wake = "ELAN0415:00@9",
},
},
{
/*
* Spurious wakeups from TP_ATTN# pin
* Found in BIOS 1.7.7
*/
.matches = {
DMI_MATCH(DMI_BOARD_NAME, "NH5xAx"),
},
.driver_data = &(struct acpi_gpiolib_dmi_quirk) {
.ignore_wake = "SYNA1202:00@16",
},
},
{} /* Terminating entry */
};
static int __init acpi_gpio_setup_params(void)
{
const struct acpi_gpiolib_dmi_quirk *quirk = NULL;
const struct dmi_system_id *id;
id = dmi_first_match(gpiolib_acpi_quirks);
if (id)
quirk = id->driver_data;
if (run_edge_events_on_boot < 0) {
if (quirk && quirk->no_edge_events_on_boot)
run_edge_events_on_boot = 0;
else
run_edge_events_on_boot = 1;
}
if (ignore_wake == NULL && quirk && quirk->ignore_wake)
ignore_wake = quirk->ignore_wake;
if (ignore_interrupt == NULL && quirk && quirk->ignore_interrupt)
ignore_interrupt = quirk->ignore_interrupt;
return 0;
}
/* Directly after dmi_setup() which runs as core_initcall() */
postcore_initcall(acpi_gpio_setup_params);
| linux-master | drivers/gpio/gpiolib-acpi.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2015-2017 Broadcom
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
enum gio_reg_index {
GIO_REG_ODEN = 0,
GIO_REG_DATA,
GIO_REG_IODIR,
GIO_REG_EC,
GIO_REG_EI,
GIO_REG_MASK,
GIO_REG_LEVEL,
GIO_REG_STAT,
NUMBER_OF_GIO_REGISTERS
};
#define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
#define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
#define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
#define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
#define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
#define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
#define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
#define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
#define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
#define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
struct brcmstb_gpio_bank {
struct list_head node;
int id;
struct gpio_chip gc;
struct brcmstb_gpio_priv *parent_priv;
u32 width;
u32 wake_active;
u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
};
struct brcmstb_gpio_priv {
struct list_head bank_list;
void __iomem *reg_base;
struct platform_device *pdev;
struct irq_domain *irq_domain;
struct irq_chip irq_chip;
int parent_irq;
int gpio_base;
int num_gpios;
int parent_wake_irq;
};
#define MAX_GPIO_PER_BANK 32
#define GPIO_BANK(gpio) ((gpio) >> 5)
/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
static inline struct brcmstb_gpio_priv *
brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
{
struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
return bank->parent_priv;
}
static unsigned long
__brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
{
void __iomem *reg_base = bank->parent_priv->reg_base;
return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
}
static unsigned long
brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
{
unsigned long status;
unsigned long flags;
raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
status = __brcmstb_gpio_get_active_irqs(bank);
raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
return status;
}
static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
struct brcmstb_gpio_bank *bank)
{
return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
}
static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
unsigned int hwirq, bool enable)
{
struct gpio_chip *gc = &bank->gc;
struct brcmstb_gpio_priv *priv = bank->parent_priv;
u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
u32 imask;
unsigned long flags;
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
if (enable)
imask |= mask;
else
imask &= ~mask;
gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
/* gc_offset is relative to this gpio_chip; want real offset */
int hwirq = offset + (gc->base - priv->gpio_base);
if (hwirq >= priv->num_gpios)
return -ENXIO;
return irq_create_mapping(priv->irq_domain, hwirq);
}
/* -------------------- IRQ chip functions -------------------- */
static void brcmstb_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
brcmstb_gpio_set_imask(bank, d->hwirq, false);
}
static void brcmstb_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
brcmstb_gpio_set_imask(bank, d->hwirq, true);
}
static void brcmstb_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
struct brcmstb_gpio_priv *priv = bank->parent_priv;
u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
}
static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
struct brcmstb_gpio_priv *priv = bank->parent_priv;
u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
u32 edge_insensitive, iedge_insensitive;
u32 edge_config, iedge_config;
u32 level, ilevel;
unsigned long flags;
switch (type) {
case IRQ_TYPE_LEVEL_LOW:
level = mask;
edge_config = 0;
edge_insensitive = 0;
break;
case IRQ_TYPE_LEVEL_HIGH:
level = mask;
edge_config = mask;
edge_insensitive = 0;
break;
case IRQ_TYPE_EDGE_FALLING:
level = 0;
edge_config = 0;
edge_insensitive = 0;
break;
case IRQ_TYPE_EDGE_RISING:
level = 0;
edge_config = mask;
edge_insensitive = 0;
break;
case IRQ_TYPE_EDGE_BOTH:
level = 0;
edge_config = 0; /* don't care, but want known value */
edge_insensitive = mask;
break;
default:
return -EINVAL;
}
raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
iedge_config = bank->gc.read_reg(priv->reg_base +
GIO_EC(bank->id)) & ~mask;
iedge_insensitive = bank->gc.read_reg(priv->reg_base +
GIO_EI(bank->id)) & ~mask;
ilevel = bank->gc.read_reg(priv->reg_base +
GIO_LEVEL(bank->id)) & ~mask;
bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
iedge_config | edge_config);
bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
iedge_insensitive | edge_insensitive);
bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
ilevel | level);
raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
return 0;
}
static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
unsigned int enable)
{
int ret = 0;
if (enable)
ret = enable_irq_wake(priv->parent_wake_irq);
else
ret = disable_irq_wake(priv->parent_wake_irq);
if (ret)
dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
enable ? "enable" : "disable");
return ret;
}
static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
struct brcmstb_gpio_priv *priv = bank->parent_priv;
u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
/*
* Do not do anything specific for now, suspend/resume callbacks will
* configure the interrupt mask appropriately
*/
if (enable)
bank->wake_active |= mask;
else
bank->wake_active &= ~mask;
return brcmstb_gpio_priv_set_wake(priv, enable);
}
static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
{
struct brcmstb_gpio_priv *priv = data;
if (!priv || irq != priv->parent_wake_irq)
return IRQ_NONE;
/* Nothing to do */
return IRQ_HANDLED;
}
static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
{
struct brcmstb_gpio_priv *priv = bank->parent_priv;
struct irq_domain *domain = priv->irq_domain;
int hwbase = bank->gc.base - priv->gpio_base;
unsigned long status;
while ((status = brcmstb_gpio_get_active_irqs(bank))) {
unsigned int offset;
for_each_set_bit(offset, &status, 32) {
if (offset >= bank->width)
dev_warn(&priv->pdev->dev,
"IRQ for invalid GPIO (bank=%d, offset=%d)\n",
bank->id, offset);
generic_handle_domain_irq(domain, hwbase + offset);
}
}
}
/* Each UPG GIO block has one IRQ for all banks */
static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
{
struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct brcmstb_gpio_bank *bank;
/* Interrupts weren't properly cleared during probe */
BUG_ON(!priv || !chip);
chained_irq_enter(chip, desc);
list_for_each_entry(bank, &priv->bank_list, node)
brcmstb_gpio_irq_bank_handler(bank);
chained_irq_exit(chip, desc);
}
static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
{
struct brcmstb_gpio_bank *bank;
int i = 0;
/* banks are in descending order */
list_for_each_entry_reverse(bank, &priv->bank_list, node) {
i += bank->gc.ngpio;
if (hwirq < i)
return bank;
}
return NULL;
}
/*
* This lock class tells lockdep that GPIO irqs are in a different
* category than their parents, so it won't report false recursion.
*/
static struct lock_class_key brcmstb_gpio_irq_lock_class;
static struct lock_class_key brcmstb_gpio_irq_request_class;
static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
struct brcmstb_gpio_priv *priv = d->host_data;
struct brcmstb_gpio_bank *bank =
brcmstb_gpio_hwirq_to_bank(priv, hwirq);
struct platform_device *pdev = priv->pdev;
int ret;
if (!bank)
return -EINVAL;
dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
irq, (int)hwirq, bank->id);
ret = irq_set_chip_data(irq, &bank->gc);
if (ret < 0)
return ret;
irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
&brcmstb_gpio_irq_request_class);
irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
irq_set_noprobe(irq);
return 0;
}
static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
{
irq_set_chip_and_handler(irq, NULL, NULL);
irq_set_chip_data(irq, NULL);
}
static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
.map = brcmstb_gpio_irq_map,
.unmap = brcmstb_gpio_irq_unmap,
.xlate = irq_domain_xlate_twocell,
};
/* Make sure that the number of banks matches up between properties */
static int brcmstb_gpio_sanity_check_banks(struct device *dev,
struct device_node *np, struct resource *res)
{
int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
int num_banks =
of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
if (res_num_banks != num_banks) {
dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
res_num_banks, num_banks);
return -EINVAL;
} else {
return 0;
}
}
static int brcmstb_gpio_remove(struct platform_device *pdev)
{
struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
struct brcmstb_gpio_bank *bank;
int offset, virq;
if (priv->parent_irq > 0)
irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
/* Remove all IRQ mappings and delete the domain */
if (priv->irq_domain) {
for (offset = 0; offset < priv->num_gpios; offset++) {
virq = irq_find_mapping(priv->irq_domain, offset);
irq_dispose_mapping(virq);
}
irq_domain_remove(priv->irq_domain);
}
/*
* You can lose return values below, but we report all errors, and it's
* more important to actually perform all of the steps.
*/
list_for_each_entry(bank, &priv->bank_list, node)
gpiochip_remove(&bank->gc);
return 0;
}
static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
const struct of_phandle_args *gpiospec, u32 *flags)
{
struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
int offset;
if (gc->of_gpio_n_cells != 2) {
WARN_ON(1);
return -EINVAL;
}
if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
return -EINVAL;
offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
if (offset >= gc->ngpio || offset < 0)
return -EINVAL;
if (unlikely(offset >= bank->width)) {
dev_warn_ratelimited(&priv->pdev->dev,
"Received request for invalid GPIO offset %d\n",
gpiospec->args[0]);
}
if (flags)
*flags = gpiospec->args[1];
return offset;
}
/* priv->parent_irq and priv->num_gpios must be set before calling */
static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
struct brcmstb_gpio_priv *priv)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
int err;
priv->irq_domain =
irq_domain_add_linear(np, priv->num_gpios,
&brcmstb_gpio_irq_domain_ops,
priv);
if (!priv->irq_domain) {
dev_err(dev, "Couldn't allocate IRQ domain\n");
return -ENXIO;
}
if (of_property_read_bool(np, "wakeup-source")) {
priv->parent_wake_irq = platform_get_irq(pdev, 1);
if (priv->parent_wake_irq < 0) {
priv->parent_wake_irq = 0;
dev_warn(dev,
"Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
} else {
/*
* Set wakeup capability so we can process boot-time
* "wakeups" (e.g., from S5 cold boot)
*/
device_set_wakeup_capable(dev, true);
device_wakeup_enable(dev);
err = devm_request_irq(dev, priv->parent_wake_irq,
brcmstb_gpio_wake_irq_handler,
IRQF_SHARED,
"brcmstb-gpio-wake", priv);
if (err < 0) {
dev_err(dev, "Couldn't request wake IRQ");
goto out_free_domain;
}
}
}
priv->irq_chip.name = dev_name(dev);
priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
if (priv->parent_wake_irq)
priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
irq_set_chained_handler_and_data(priv->parent_irq,
brcmstb_gpio_irq_handler, priv);
irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
return 0;
out_free_domain:
irq_domain_remove(priv->irq_domain);
return err;
}
static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
struct brcmstb_gpio_bank *bank)
{
struct gpio_chip *gc = &bank->gc;
unsigned int i;
for (i = 0; i < GIO_REG_STAT; i++)
bank->saved_regs[i] = gc->read_reg(priv->reg_base +
GIO_BANK_OFF(bank->id, i));
}
static void brcmstb_gpio_quiesce(struct device *dev, bool save)
{
struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
struct brcmstb_gpio_bank *bank;
struct gpio_chip *gc;
u32 imask;
/* disable non-wake interrupt */
if (priv->parent_irq >= 0)
disable_irq(priv->parent_irq);
list_for_each_entry(bank, &priv->bank_list, node) {
gc = &bank->gc;
if (save)
brcmstb_gpio_bank_save(priv, bank);
/* Unmask GPIOs which have been flagged as wake-up sources */
if (priv->parent_wake_irq)
imask = bank->wake_active;
else
imask = 0;
gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
imask);
}
}
static void brcmstb_gpio_shutdown(struct platform_device *pdev)
{
/* Enable GPIO for S5 cold boot */
brcmstb_gpio_quiesce(&pdev->dev, false);
}
#ifdef CONFIG_PM_SLEEP
static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
struct brcmstb_gpio_bank *bank)
{
struct gpio_chip *gc = &bank->gc;
unsigned int i;
for (i = 0; i < GIO_REG_STAT; i++)
gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
bank->saved_regs[i]);
}
static int brcmstb_gpio_suspend(struct device *dev)
{
brcmstb_gpio_quiesce(dev, true);
return 0;
}
static int brcmstb_gpio_resume(struct device *dev)
{
struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
struct brcmstb_gpio_bank *bank;
bool need_wakeup_event = false;
list_for_each_entry(bank, &priv->bank_list, node) {
need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
brcmstb_gpio_bank_restore(priv, bank);
}
if (priv->parent_wake_irq && need_wakeup_event)
pm_wakeup_event(dev, 0);
/* enable non-wake interrupt */
if (priv->parent_irq >= 0)
enable_irq(priv->parent_irq);
return 0;
}
#else
#define brcmstb_gpio_suspend NULL
#define brcmstb_gpio_resume NULL
#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
.suspend_noirq = brcmstb_gpio_suspend,
.resume_noirq = brcmstb_gpio_resume,
};
static int brcmstb_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
void __iomem *reg_base;
struct brcmstb_gpio_priv *priv;
struct resource *res;
struct property *prop;
const __be32 *p;
u32 bank_width;
int num_banks = 0;
int err;
static int gpio_base;
unsigned long flags = 0;
bool need_wakeup_event = false;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
INIT_LIST_HEAD(&priv->bank_list);
reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
priv->gpio_base = gpio_base;
priv->reg_base = reg_base;
priv->pdev = pdev;
if (of_property_read_bool(np, "interrupt-controller")) {
priv->parent_irq = platform_get_irq(pdev, 0);
if (priv->parent_irq <= 0)
return -ENOENT;
} else {
priv->parent_irq = -ENOENT;
}
if (brcmstb_gpio_sanity_check_banks(dev, np, res))
return -EINVAL;
/*
* MIPS endianness is configured by boot strap, which also reverses all
* bus endianness (i.e., big-endian CPU + big endian bus ==> native
* endian I/O).
*
* Other architectures (e.g., ARM) either do not support big endian, or
* else leave I/O in little endian mode.
*/
#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
#endif
of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
bank_width) {
struct brcmstb_gpio_bank *bank;
struct gpio_chip *gc;
/*
* If bank_width is 0, then there is an empty bank in the
* register block. Special handling for this case.
*/
if (bank_width == 0) {
dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
num_banks);
num_banks++;
gpio_base += MAX_GPIO_PER_BANK;
continue;
}
bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
if (!bank) {
err = -ENOMEM;
goto fail;
}
bank->parent_priv = priv;
bank->id = num_banks;
if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
dev_err(dev, "Invalid bank width %d\n", bank_width);
err = -EINVAL;
goto fail;
} else {
bank->width = bank_width;
}
/*
* Regs are 4 bytes wide, have data reg, no set/clear regs,
* and direction bits have 0 = output and 1 = input
*/
gc = &bank->gc;
err = bgpio_init(gc, dev, 4,
reg_base + GIO_DATA(bank->id),
NULL, NULL, NULL,
reg_base + GIO_IODIR(bank->id), flags);
if (err) {
dev_err(dev, "bgpio_init() failed\n");
goto fail;
}
gc->owner = THIS_MODULE;
gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
if (!gc->label) {
err = -ENOMEM;
goto fail;
}
gc->base = gpio_base;
gc->of_gpio_n_cells = 2;
gc->of_xlate = brcmstb_gpio_of_xlate;
/* not all ngpio lines are valid, will use bank width later */
gc->ngpio = MAX_GPIO_PER_BANK;
gc->offset = bank->id * MAX_GPIO_PER_BANK;
if (priv->parent_irq > 0)
gc->to_irq = brcmstb_gpio_to_irq;
/*
* Mask all interrupts by default, since wakeup interrupts may
* be retained from S5 cold boot
*/
need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
err = gpiochip_add_data(gc, bank);
if (err) {
dev_err(dev, "Could not add gpiochip for bank %d\n",
bank->id);
goto fail;
}
gpio_base += gc->ngpio;
dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
gc->base, gc->ngpio, bank->width);
/* Everything looks good, so add bank to list */
list_add(&bank->node, &priv->bank_list);
num_banks++;
}
priv->num_gpios = gpio_base - priv->gpio_base;
if (priv->parent_irq > 0) {
err = brcmstb_gpio_irq_setup(pdev, priv);
if (err)
goto fail;
}
if (priv->parent_wake_irq && need_wakeup_event)
pm_wakeup_event(dev, 0);
return 0;
fail:
(void) brcmstb_gpio_remove(pdev);
return err;
}
static const struct of_device_id brcmstb_gpio_of_match[] = {
{ .compatible = "brcm,brcmstb-gpio" },
{},
};
MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
static struct platform_driver brcmstb_gpio_driver = {
.driver = {
.name = "brcmstb-gpio",
.of_match_table = brcmstb_gpio_of_match,
.pm = &brcmstb_gpio_pm_ops,
},
.probe = brcmstb_gpio_probe,
.remove = brcmstb_gpio_remove,
.shutdown = brcmstb_gpio_shutdown,
};
module_platform_driver(brcmstb_gpio_driver);
MODULE_AUTHOR("Gregory Fong");
MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-brcmstb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* gpiolib support for Wolfson Arizona class devices
*
* Copyright 2012 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/pdata.h>
#include <linux/mfd/arizona/registers.h>
struct arizona_gpio {
struct arizona *arizona;
struct gpio_chip gpio_chip;
};
static int arizona_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
struct arizona_gpio *arizona_gpio = gpiochip_get_data(chip);
struct arizona *arizona = arizona_gpio->arizona;
bool persistent = gpiochip_line_is_persistent(chip, offset);
bool change;
int ret;
ret = regmap_update_bits_check(arizona->regmap,
ARIZONA_GPIO1_CTRL + offset,
ARIZONA_GPN_DIR, ARIZONA_GPN_DIR,
&change);
if (ret < 0)
return ret;
if (change && persistent) {
pm_runtime_mark_last_busy(chip->parent);
pm_runtime_put_autosuspend(chip->parent);
}
return 0;
}
static int arizona_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct arizona_gpio *arizona_gpio = gpiochip_get_data(chip);
struct arizona *arizona = arizona_gpio->arizona;
unsigned int reg, val;
int ret;
reg = ARIZONA_GPIO1_CTRL + offset;
ret = regmap_read(arizona->regmap, reg, &val);
if (ret < 0)
return ret;
/* Resume to read actual registers for input pins */
if (val & ARIZONA_GPN_DIR) {
ret = pm_runtime_get_sync(chip->parent);
if (ret < 0) {
dev_err(chip->parent, "Failed to resume: %d\n", ret);
pm_runtime_put_autosuspend(chip->parent);
return ret;
}
/* Register is cached, drop it to ensure a physical read */
ret = regcache_drop_region(arizona->regmap, reg, reg);
if (ret < 0) {
dev_err(chip->parent, "Failed to drop cache: %d\n",
ret);
pm_runtime_put_autosuspend(chip->parent);
return ret;
}
ret = regmap_read(arizona->regmap, reg, &val);
if (ret < 0) {
pm_runtime_put_autosuspend(chip->parent);
return ret;
}
pm_runtime_mark_last_busy(chip->parent);
pm_runtime_put_autosuspend(chip->parent);
}
if (val & ARIZONA_GPN_LVL)
return 1;
else
return 0;
}
static int arizona_gpio_direction_out(struct gpio_chip *chip,
unsigned offset, int value)
{
struct arizona_gpio *arizona_gpio = gpiochip_get_data(chip);
struct arizona *arizona = arizona_gpio->arizona;
bool persistent = gpiochip_line_is_persistent(chip, offset);
unsigned int val;
int ret;
ret = regmap_read(arizona->regmap, ARIZONA_GPIO1_CTRL + offset, &val);
if (ret < 0)
return ret;
if ((val & ARIZONA_GPN_DIR) && persistent) {
ret = pm_runtime_get_sync(chip->parent);
if (ret < 0) {
dev_err(chip->parent, "Failed to resume: %d\n", ret);
pm_runtime_put(chip->parent);
return ret;
}
}
if (value)
value = ARIZONA_GPN_LVL;
return regmap_update_bits(arizona->regmap, ARIZONA_GPIO1_CTRL + offset,
ARIZONA_GPN_DIR | ARIZONA_GPN_LVL, value);
}
static void arizona_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct arizona_gpio *arizona_gpio = gpiochip_get_data(chip);
struct arizona *arizona = arizona_gpio->arizona;
if (value)
value = ARIZONA_GPN_LVL;
regmap_update_bits(arizona->regmap, ARIZONA_GPIO1_CTRL + offset,
ARIZONA_GPN_LVL, value);
}
static const struct gpio_chip template_chip = {
.label = "arizona",
.owner = THIS_MODULE,
.direction_input = arizona_gpio_direction_in,
.get = arizona_gpio_get,
.direction_output = arizona_gpio_direction_out,
.set = arizona_gpio_set,
.can_sleep = true,
};
static int arizona_gpio_probe(struct platform_device *pdev)
{
struct arizona *arizona = dev_get_drvdata(pdev->dev.parent);
struct arizona_pdata *pdata = &arizona->pdata;
struct arizona_gpio *arizona_gpio;
int ret;
device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
arizona_gpio = devm_kzalloc(&pdev->dev, sizeof(*arizona_gpio),
GFP_KERNEL);
if (!arizona_gpio)
return -ENOMEM;
arizona_gpio->arizona = arizona;
arizona_gpio->gpio_chip = template_chip;
arizona_gpio->gpio_chip.parent = &pdev->dev;
switch (arizona->type) {
case WM5102:
case WM5110:
case WM8280:
case WM8997:
case WM8998:
case WM1814:
arizona_gpio->gpio_chip.ngpio = 5;
break;
case WM1831:
case CS47L24:
arizona_gpio->gpio_chip.ngpio = 2;
break;
default:
dev_err(&pdev->dev, "Unknown chip variant %d\n",
arizona->type);
return -EINVAL;
}
if (pdata->gpio_base)
arizona_gpio->gpio_chip.base = pdata->gpio_base;
else
arizona_gpio->gpio_chip.base = -1;
pm_runtime_enable(&pdev->dev);
ret = devm_gpiochip_add_data(&pdev->dev, &arizona_gpio->gpio_chip,
arizona_gpio);
if (ret < 0) {
pm_runtime_disable(&pdev->dev);
dev_err(&pdev->dev, "Could not register gpiochip, %d\n",
ret);
return ret;
}
return 0;
}
static struct platform_driver arizona_gpio_driver = {
.driver.name = "arizona-gpio",
.probe = arizona_gpio_probe,
};
module_platform_driver(arizona_gpio_driver);
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_DESCRIPTION("GPIO interface for Arizona devices");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:arizona-gpio");
| linux-master | drivers/gpio/gpio-arizona.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/acpi.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/resource.h>
#include <linux/types.h>
/* Number of pins on BlueField */
#define MLXBF_GPIO_NR 54
/* Pad Electrical Controls. */
#define MLXBF_GPIO_PAD_CONTROL_FIRST_WORD 0x0700
#define MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD 0x0708
#define MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD 0x0710
#define MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD 0x0718
#define MLXBF_GPIO_PIN_DIR_I 0x1040
#define MLXBF_GPIO_PIN_DIR_O 0x1048
#define MLXBF_GPIO_PIN_STATE 0x1000
#define MLXBF_GPIO_SCRATCHPAD 0x20
#ifdef CONFIG_PM
struct mlxbf_gpio_context_save_regs {
u64 scratchpad;
u64 pad_control[MLXBF_GPIO_NR];
u64 pin_dir_i;
u64 pin_dir_o;
};
#endif
/* Device state structure. */
struct mlxbf_gpio_state {
struct gpio_chip gc;
/* Memory Address */
void __iomem *base;
#ifdef CONFIG_PM
struct mlxbf_gpio_context_save_regs csave_regs;
#endif
};
static int mlxbf_gpio_probe(struct platform_device *pdev)
{
struct mlxbf_gpio_state *gs;
struct device *dev = &pdev->dev;
struct gpio_chip *gc;
int ret;
gs = devm_kzalloc(&pdev->dev, sizeof(*gs), GFP_KERNEL);
if (!gs)
return -ENOMEM;
gs->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(gs->base))
return PTR_ERR(gs->base);
gc = &gs->gc;
ret = bgpio_init(gc, dev, 8,
gs->base + MLXBF_GPIO_PIN_STATE,
NULL,
NULL,
gs->base + MLXBF_GPIO_PIN_DIR_O,
gs->base + MLXBF_GPIO_PIN_DIR_I,
0);
if (ret)
return -ENODEV;
gc->owner = THIS_MODULE;
gc->ngpio = MLXBF_GPIO_NR;
ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
if (ret) {
dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
return ret;
}
platform_set_drvdata(pdev, gs);
dev_info(&pdev->dev, "registered Mellanox BlueField GPIO");
return 0;
}
#ifdef CONFIG_PM
static int mlxbf_gpio_suspend(struct platform_device *pdev, pm_message_t state)
{
struct mlxbf_gpio_state *gs = platform_get_drvdata(pdev);
gs->csave_regs.scratchpad = readq(gs->base + MLXBF_GPIO_SCRATCHPAD);
gs->csave_regs.pad_control[0] =
readq(gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD);
gs->csave_regs.pad_control[1] =
readq(gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD);
gs->csave_regs.pad_control[2] =
readq(gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD);
gs->csave_regs.pad_control[3] =
readq(gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD);
gs->csave_regs.pin_dir_i = readq(gs->base + MLXBF_GPIO_PIN_DIR_I);
gs->csave_regs.pin_dir_o = readq(gs->base + MLXBF_GPIO_PIN_DIR_O);
return 0;
}
static int mlxbf_gpio_resume(struct platform_device *pdev)
{
struct mlxbf_gpio_state *gs = platform_get_drvdata(pdev);
writeq(gs->csave_regs.scratchpad, gs->base + MLXBF_GPIO_SCRATCHPAD);
writeq(gs->csave_regs.pad_control[0],
gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD);
writeq(gs->csave_regs.pad_control[1],
gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD);
writeq(gs->csave_regs.pad_control[2],
gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD);
writeq(gs->csave_regs.pad_control[3],
gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD);
writeq(gs->csave_regs.pin_dir_i, gs->base + MLXBF_GPIO_PIN_DIR_I);
writeq(gs->csave_regs.pin_dir_o, gs->base + MLXBF_GPIO_PIN_DIR_O);
return 0;
}
#endif
static const struct acpi_device_id __maybe_unused mlxbf_gpio_acpi_match[] = {
{ "MLNXBF02", 0 },
{}
};
MODULE_DEVICE_TABLE(acpi, mlxbf_gpio_acpi_match);
static struct platform_driver mlxbf_gpio_driver = {
.driver = {
.name = "mlxbf_gpio",
.acpi_match_table = ACPI_PTR(mlxbf_gpio_acpi_match),
},
.probe = mlxbf_gpio_probe,
#ifdef CONFIG_PM
.suspend = mlxbf_gpio_suspend,
.resume = mlxbf_gpio_resume,
#endif
};
module_platform_driver(mlxbf_gpio_driver);
MODULE_DESCRIPTION("Mellanox BlueField GPIO Driver");
MODULE_AUTHOR("Mellanox Technologies");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-mlxbf.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SYSCON GPIO driver
*
* Copyright (C) 2014 Alexander Shiyan <[email protected]>
*/
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#define GPIO_SYSCON_FEAT_IN BIT(0)
#define GPIO_SYSCON_FEAT_OUT BIT(1)
#define GPIO_SYSCON_FEAT_DIR BIT(2)
/* SYSCON driver is designed to use 32-bit wide registers */
#define SYSCON_REG_SIZE (4)
#define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8)
/**
* struct syscon_gpio_data - Configuration for the device.
* @compatible: SYSCON driver compatible string.
* @flags: Set of GPIO_SYSCON_FEAT_ flags:
* GPIO_SYSCON_FEAT_IN: GPIOs supports input,
* GPIO_SYSCON_FEAT_OUT: GPIOs supports output,
* GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction.
* @bit_count: Number of bits used as GPIOs.
* @dat_bit_offset: Offset (in bits) to the first GPIO bit.
* @dir_bit_offset: Optional offset (in bits) to the first bit to switch
* GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
* @set: HW specific callback to assigns output value
* for signal "offset"
*/
struct syscon_gpio_data {
unsigned int flags;
unsigned int bit_count;
unsigned int dat_bit_offset;
unsigned int dir_bit_offset;
void (*set)(struct gpio_chip *chip,
unsigned offset, int value);
};
struct syscon_gpio_priv {
struct gpio_chip chip;
struct regmap *syscon;
const struct syscon_gpio_data *data;
u32 dreg_offset;
u32 dir_reg_offset;
};
static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
unsigned int val, offs;
int ret;
offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
ret = regmap_read(priv->syscon,
(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val);
if (ret)
return ret;
return !!(val & BIT(offs % SYSCON_REG_BITS));
}
static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
unsigned int offs;
offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
regmap_update_bits(priv->syscon,
(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
BIT(offs % SYSCON_REG_BITS),
val ? BIT(offs % SYSCON_REG_BITS) : 0);
}
static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
{
struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
unsigned int offs;
offs = priv->dir_reg_offset +
priv->data->dir_bit_offset + offset;
regmap_update_bits(priv->syscon,
(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
BIT(offs % SYSCON_REG_BITS), 0);
}
return 0;
}
static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val)
{
struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
unsigned int offs;
offs = priv->dir_reg_offset +
priv->data->dir_bit_offset + offset;
regmap_update_bits(priv->syscon,
(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
BIT(offs % SYSCON_REG_BITS),
BIT(offs % SYSCON_REG_BITS));
}
chip->set(chip, offset, val);
return 0;
}
static const struct syscon_gpio_data clps711x_mctrl_gpio = {
/* ARM CLPS711X SYSFLG1 Bits 8-10 */
.flags = GPIO_SYSCON_FEAT_IN,
.bit_count = 3,
.dat_bit_offset = 0x40 * 8 + 8,
};
static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
int val)
{
struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
unsigned int offs;
u8 bit;
u32 data;
int ret;
offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
bit = offs % SYSCON_REG_BITS;
data = (val ? BIT(bit) : 0) | BIT(bit + 16);
ret = regmap_write(priv->syscon,
(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
data);
if (ret < 0)
dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
}
static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = {
/* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */
.flags = GPIO_SYSCON_FEAT_OUT,
.bit_count = 1,
.dat_bit_offset = 0x0428 * 8 + 1,
.set = rockchip_gpio_set,
};
#define KEYSTONE_LOCK_BIT BIT(0)
static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
unsigned int offs;
int ret;
offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
if (!val)
return;
ret = regmap_update_bits(
priv->syscon,
(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT,
BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT);
if (ret < 0)
dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
}
static const struct syscon_gpio_data keystone_dsp_gpio = {
/* ARM Keystone 2 */
.flags = GPIO_SYSCON_FEAT_OUT,
.bit_count = 28,
.dat_bit_offset = 4,
.set = keystone_gpio_set,
};
static const struct of_device_id syscon_gpio_ids[] = {
{
.compatible = "cirrus,ep7209-mctrl-gpio",
.data = &clps711x_mctrl_gpio,
},
{
.compatible = "ti,keystone-dsp-gpio",
.data = &keystone_dsp_gpio,
},
{
.compatible = "rockchip,rk3328-grf-gpio",
.data = &rockchip_rk3328_gpio_mute,
},
{ }
};
MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
static int syscon_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct syscon_gpio_priv *priv;
struct device_node *np = dev->of_node;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->data = of_device_get_match_data(dev);
priv->syscon = syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
if (IS_ERR(priv->syscon) && np->parent)
priv->syscon = syscon_node_to_regmap(np->parent);
if (IS_ERR(priv->syscon))
return PTR_ERR(priv->syscon);
ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1,
&priv->dreg_offset);
if (ret)
dev_err(dev, "can't read the data register offset!\n");
priv->dreg_offset <<= 3;
ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2,
&priv->dir_reg_offset);
if (ret)
dev_dbg(dev, "can't read the dir register offset!\n");
priv->dir_reg_offset <<= 3;
priv->chip.parent = dev;
priv->chip.owner = THIS_MODULE;
priv->chip.label = dev_name(dev);
priv->chip.base = -1;
priv->chip.ngpio = priv->data->bit_count;
priv->chip.get = syscon_gpio_get;
if (priv->data->flags & GPIO_SYSCON_FEAT_IN)
priv->chip.direction_input = syscon_gpio_dir_in;
if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {
priv->chip.set = priv->data->set ? : syscon_gpio_set;
priv->chip.direction_output = syscon_gpio_dir_out;
}
return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
}
static struct platform_driver syscon_gpio_driver = {
.driver = {
.name = "gpio-syscon",
.of_match_table = syscon_gpio_ids,
},
.probe = syscon_gpio_probe,
};
module_platform_driver(syscon_gpio_driver);
MODULE_AUTHOR("Alexander Shiyan <[email protected]>");
MODULE_DESCRIPTION("SYSCON GPIO driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-syscon.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* GPIO driver for the ACCES 104-IDI-48 family
* Copyright (C) 2015 William Breathitt Gray
*
* This driver supports the following ACCES devices: 104-IDI-48A,
* 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
*/
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/regmap.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/regmap.h>
#include <linux/types.h>
#define IDI_48_EXTENT 8
#define MAX_NUM_IDI_48 max_num_isa_dev(IDI_48_EXTENT)
static unsigned int base[MAX_NUM_IDI_48];
static unsigned int num_idi_48;
module_param_hw_array(base, uint, ioport, &num_idi_48, 0);
MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
static unsigned int irq[MAX_NUM_IDI_48];
static unsigned int num_irq;
module_param_hw_array(irq, uint, irq, &num_irq, 0);
MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
#define IDI48_IRQ_STATUS 0x7
#define IDI48_IRQ_ENABLE IDI48_IRQ_STATUS
static int idi_48_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
unsigned int offset, unsigned int *reg,
unsigned int *mask)
{
const unsigned int line = offset % 8;
const unsigned int stride = offset / 8;
const unsigned int port = (stride / 3) * 4;
const unsigned int port_stride = stride % 3;
*reg = base + port + port_stride;
*mask = BIT(line);
return 0;
}
static const struct regmap_range idi_48_wr_ranges[] = {
regmap_reg_range(0x0, 0x6),
};
static const struct regmap_range idi_48_rd_ranges[] = {
regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x7),
};
static const struct regmap_range idi_48_precious_ranges[] = {
regmap_reg_range(0x7, 0x7),
};
static const struct regmap_access_table idi_48_wr_table = {
.no_ranges = idi_48_wr_ranges,
.n_no_ranges = ARRAY_SIZE(idi_48_wr_ranges),
};
static const struct regmap_access_table idi_48_rd_table = {
.yes_ranges = idi_48_rd_ranges,
.n_yes_ranges = ARRAY_SIZE(idi_48_rd_ranges),
};
static const struct regmap_access_table idi_48_precious_table = {
.yes_ranges = idi_48_precious_ranges,
.n_yes_ranges = ARRAY_SIZE(idi_48_precious_ranges),
};
static const struct regmap_config idi48_regmap_config = {
.reg_bits = 8,
.reg_stride = 1,
.val_bits = 8,
.io_port = true,
.max_register = 0x6,
.wr_table = &idi_48_wr_table,
.rd_table = &idi_48_rd_table,
.precious_table = &idi_48_precious_table,
.use_raw_spinlock = true,
};
#define IDI48_NGPIO 48
#define IDI48_REGMAP_IRQ(_id) \
[_id] = { \
.mask = BIT((_id) / 8), \
.type = { .types_supported = IRQ_TYPE_EDGE_BOTH }, \
}
static const struct regmap_irq idi48_regmap_irqs[IDI48_NGPIO] = {
IDI48_REGMAP_IRQ(0), IDI48_REGMAP_IRQ(1), IDI48_REGMAP_IRQ(2), /* 0-2 */
IDI48_REGMAP_IRQ(3), IDI48_REGMAP_IRQ(4), IDI48_REGMAP_IRQ(5), /* 3-5 */
IDI48_REGMAP_IRQ(6), IDI48_REGMAP_IRQ(7), IDI48_REGMAP_IRQ(8), /* 6-8 */
IDI48_REGMAP_IRQ(9), IDI48_REGMAP_IRQ(10), IDI48_REGMAP_IRQ(11), /* 9-11 */
IDI48_REGMAP_IRQ(12), IDI48_REGMAP_IRQ(13), IDI48_REGMAP_IRQ(14), /* 12-14 */
IDI48_REGMAP_IRQ(15), IDI48_REGMAP_IRQ(16), IDI48_REGMAP_IRQ(17), /* 15-17 */
IDI48_REGMAP_IRQ(18), IDI48_REGMAP_IRQ(19), IDI48_REGMAP_IRQ(20), /* 18-20 */
IDI48_REGMAP_IRQ(21), IDI48_REGMAP_IRQ(22), IDI48_REGMAP_IRQ(23), /* 21-23 */
IDI48_REGMAP_IRQ(24), IDI48_REGMAP_IRQ(25), IDI48_REGMAP_IRQ(26), /* 24-26 */
IDI48_REGMAP_IRQ(27), IDI48_REGMAP_IRQ(28), IDI48_REGMAP_IRQ(29), /* 27-29 */
IDI48_REGMAP_IRQ(30), IDI48_REGMAP_IRQ(31), IDI48_REGMAP_IRQ(32), /* 30-32 */
IDI48_REGMAP_IRQ(33), IDI48_REGMAP_IRQ(34), IDI48_REGMAP_IRQ(35), /* 33-35 */
IDI48_REGMAP_IRQ(36), IDI48_REGMAP_IRQ(37), IDI48_REGMAP_IRQ(38), /* 36-38 */
IDI48_REGMAP_IRQ(39), IDI48_REGMAP_IRQ(40), IDI48_REGMAP_IRQ(41), /* 39-41 */
IDI48_REGMAP_IRQ(42), IDI48_REGMAP_IRQ(43), IDI48_REGMAP_IRQ(44), /* 42-44 */
IDI48_REGMAP_IRQ(45), IDI48_REGMAP_IRQ(46), IDI48_REGMAP_IRQ(47), /* 45-47 */
};
static const char *idi48_names[IDI48_NGPIO] = {
"Bit 0 A", "Bit 1 A", "Bit 2 A", "Bit 3 A", "Bit 4 A", "Bit 5 A",
"Bit 6 A", "Bit 7 A", "Bit 8 A", "Bit 9 A", "Bit 10 A", "Bit 11 A",
"Bit 12 A", "Bit 13 A", "Bit 14 A", "Bit 15 A", "Bit 16 A", "Bit 17 A",
"Bit 18 A", "Bit 19 A", "Bit 20 A", "Bit 21 A", "Bit 22 A", "Bit 23 A",
"Bit 0 B", "Bit 1 B", "Bit 2 B", "Bit 3 B", "Bit 4 B", "Bit 5 B",
"Bit 6 B", "Bit 7 B", "Bit 8 B", "Bit 9 B", "Bit 10 B", "Bit 11 B",
"Bit 12 B", "Bit 13 B", "Bit 14 B", "Bit 15 B", "Bit 16 B", "Bit 17 B",
"Bit 18 B", "Bit 19 B", "Bit 20 B", "Bit 21 B", "Bit 22 B", "Bit 23 B"
};
static int idi_48_probe(struct device *dev, unsigned int id)
{
const char *const name = dev_name(dev);
struct gpio_regmap_config config = {};
void __iomem *regs;
struct regmap *map;
struct regmap_irq_chip *chip;
struct regmap_irq_chip_data *chip_data;
int err;
if (!devm_request_region(dev, base[id], IDI_48_EXTENT, name)) {
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
base[id], base[id] + IDI_48_EXTENT);
return -EBUSY;
}
regs = devm_ioport_map(dev, base[id], IDI_48_EXTENT);
if (!regs)
return -ENOMEM;
map = devm_regmap_init_mmio(dev, regs, &idi48_regmap_config);
if (IS_ERR(map))
return dev_err_probe(dev, PTR_ERR(map),
"Unable to initialize register map\n");
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->name = name;
chip->status_base = IDI48_IRQ_STATUS;
chip->unmask_base = IDI48_IRQ_ENABLE;
chip->clear_on_unmask = true;
chip->num_regs = 1;
chip->irqs = idi48_regmap_irqs;
chip->num_irqs = ARRAY_SIZE(idi48_regmap_irqs);
err = devm_regmap_add_irq_chip(dev, map, irq[id], IRQF_SHARED, 0, chip,
&chip_data);
if (err)
return dev_err_probe(dev, err, "IRQ registration failed\n");
config.parent = dev;
config.regmap = map;
config.ngpio = IDI48_NGPIO;
config.names = idi48_names;
config.reg_dat_base = GPIO_REGMAP_ADDR(0x0);
config.ngpio_per_reg = 8;
config.reg_mask_xlate = idi_48_reg_mask_xlate;
config.irq_domain = regmap_irq_get_domain(chip_data);
return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &config));
}
static struct isa_driver idi_48_driver = {
.probe = idi_48_probe,
.driver = {
.name = "104-idi-48"
},
};
module_isa_driver_with_irq(idi_48_driver, num_idi_48, num_irq);
MODULE_AUTHOR("William Breathitt Gray <[email protected]>");
MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-104-idi-48.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Xilinx Zynq GPIO device driver
*
* Copyright (C) 2009 - 2014 Xilinx, Inc.
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#define DRIVER_NAME "zynq-gpio"
/* Maximum banks */
#define ZYNQ_GPIO_MAX_BANK 4
#define ZYNQMP_GPIO_MAX_BANK 6
#define VERSAL_GPIO_MAX_BANK 4
#define PMC_GPIO_MAX_BANK 5
#define VERSAL_UNUSED_BANKS 2
#define ZYNQ_GPIO_BANK0_NGPIO 32
#define ZYNQ_GPIO_BANK1_NGPIO 22
#define ZYNQ_GPIO_BANK2_NGPIO 32
#define ZYNQ_GPIO_BANK3_NGPIO 32
#define ZYNQMP_GPIO_BANK0_NGPIO 26
#define ZYNQMP_GPIO_BANK1_NGPIO 26
#define ZYNQMP_GPIO_BANK2_NGPIO 26
#define ZYNQMP_GPIO_BANK3_NGPIO 32
#define ZYNQMP_GPIO_BANK4_NGPIO 32
#define ZYNQMP_GPIO_BANK5_NGPIO 32
#define ZYNQ_GPIO_NR_GPIOS 118
#define ZYNQMP_GPIO_NR_GPIOS 174
#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
/* Register offsets for the GPIO device */
/* LSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
/* MSW Mask & Data -WO */
#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
/* Data Register-RW */
#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
/* Direction mode reg-RW */
#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
/* Output enable reg-RW */
#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
/* Interrupt mask reg-RO */
#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
/* Interrupt enable reg-WO */
#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
/* Interrupt disable reg-WO */
#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
/* Interrupt status reg-RO */
#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
/* Interrupt type reg-RW */
#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
/* Interrupt polarity reg-RW */
#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
/* Interrupt on any, reg-RW */
#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
/* Disable all interrupts mask */
#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
/* Mid pin number of a bank */
#define ZYNQ_GPIO_MID_PIN_NUM 16
/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
#define GPIO_QUIRK_VERSAL BIT(2)
struct gpio_regs {
u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
u32 dirm[ZYNQMP_GPIO_MAX_BANK];
u32 outen[ZYNQMP_GPIO_MAX_BANK];
u32 int_en[ZYNQMP_GPIO_MAX_BANK];
u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
u32 int_type[ZYNQMP_GPIO_MAX_BANK];
u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
u32 int_any[ZYNQMP_GPIO_MAX_BANK];
};
/**
* struct zynq_gpio - gpio device private data structure
* @chip: instance of the gpio_chip
* @base_addr: base address of the GPIO device
* @clk: clock resource for this controller
* @irq: interrupt for the GPIO device
* @p_data: pointer to platform data
* @context: context registers
* @dirlock: lock used for direction in/out synchronization
*/
struct zynq_gpio {
struct gpio_chip chip;
void __iomem *base_addr;
struct clk *clk;
int irq;
const struct zynq_platform_data *p_data;
struct gpio_regs context;
spinlock_t dirlock; /* lock */
};
/**
* struct zynq_platform_data - zynq gpio platform data structure
* @label: string to store in gpio->label
* @quirks: Flags is used to identify the platform
* @ngpio: max number of gpio pins
* @max_bank: maximum number of gpio banks
* @bank_min: this array represents bank's min pin
* @bank_max: this array represents bank's max pin
*/
struct zynq_platform_data {
const char *label;
u32 quirks;
u16 ngpio;
int max_bank;
int bank_min[ZYNQMP_GPIO_MAX_BANK];
int bank_max[ZYNQMP_GPIO_MAX_BANK];
};
static const struct irq_chip zynq_gpio_level_irqchip;
static const struct irq_chip zynq_gpio_edge_irqchip;
/**
* zynq_gpio_is_zynq - test if HW is zynq or zynqmp
* @gpio: Pointer to driver data struct
*
* Return: 0 if zynqmp, 1 if zynq.
*/
static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
{
return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
}
/**
* gpio_data_ro_bug - test if HW bug exists or not
* @gpio: Pointer to driver data struct
*
* Return: 0 if bug doesnot exist, 1 if bug exists.
*/
static int gpio_data_ro_bug(struct zynq_gpio *gpio)
{
return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
}
/**
* zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
* for a given pin in the GPIO device
* @pin_num: gpio pin number within the device
* @bank_num: an output parameter used to return the bank number of the gpio
* pin
* @bank_pin_num: an output parameter used to return pin number within a bank
* for the given gpio pin
* @gpio: gpio device data structure
*
* Returns the bank number and pin offset within the bank.
*/
static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
unsigned int *bank_num,
unsigned int *bank_pin_num,
struct zynq_gpio *gpio)
{
int bank;
for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
if ((pin_num >= gpio->p_data->bank_min[bank]) &&
(pin_num <= gpio->p_data->bank_max[bank])) {
*bank_num = bank;
*bank_pin_num = pin_num -
gpio->p_data->bank_min[bank];
return;
}
if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
bank = bank + VERSAL_UNUSED_BANKS;
}
/* default */
WARN(true, "invalid GPIO pin number: %u", pin_num);
*bank_num = 0;
*bank_pin_num = 0;
}
/**
* zynq_gpio_get_value - Get the state of the specified pin of GPIO device
* @chip: gpio_chip instance to be worked on
* @pin: gpio pin number within the device
*
* This function reads the state of the specified pin of the GPIO device.
*
* Return: 0 if the pin is low, 1 if pin is high.
*/
static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
{
u32 data;
unsigned int bank_num, bank_pin_num;
struct zynq_gpio *gpio = gpiochip_get_data(chip);
zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
if (gpio_data_ro_bug(gpio)) {
if (zynq_gpio_is_zynq(gpio)) {
if (bank_num <= 1) {
data = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
} else {
data = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_DATA_OFFSET(bank_num));
}
} else {
if (bank_num <= 2) {
data = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
} else {
data = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_DATA_OFFSET(bank_num));
}
}
} else {
data = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
}
return (data >> bank_pin_num) & 1;
}
/**
* zynq_gpio_set_value - Modify the state of the pin with specified value
* @chip: gpio_chip instance to be worked on
* @pin: gpio pin number within the device
* @state: value used to modify the state of the specified pin
*
* This function calculates the register offset (i.e to lower 16 bits or
* upper 16 bits) based on the given pin number and sets the state of a
* gpio pin to the specified value. The state is either 0 or non-zero.
*/
static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
int state)
{
unsigned int reg_offset, bank_num, bank_pin_num;
struct zynq_gpio *gpio = gpiochip_get_data(chip);
zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
/* only 16 data bits in bit maskable reg */
bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
} else {
reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
}
/*
* get the 32 bit value to be written to the mask/data register where
* the upper 16 bits is the mask and lower 16 bits is the data
*/
state = !!state;
state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
writel_relaxed(state, gpio->base_addr + reg_offset);
}
/**
* zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
* @chip: gpio_chip instance to be worked on
* @pin: gpio pin number within the device
*
* This function uses the read-modify-write sequence to set the direction of
* the gpio pin as input.
*
* Return: 0 always
*/
static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
{
u32 reg;
unsigned int bank_num, bank_pin_num;
unsigned long flags;
struct zynq_gpio *gpio = gpiochip_get_data(chip);
zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
/*
* On zynq bank 0 pins 7 and 8 are special and cannot be used
* as inputs.
*/
if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
(bank_pin_num == 7 || bank_pin_num == 8))
return -EINVAL;
/* clear the bit in direction mode reg to set the pin as input */
spin_lock_irqsave(&gpio->dirlock, flags);
reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= ~BIT(bank_pin_num);
writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
spin_unlock_irqrestore(&gpio->dirlock, flags);
return 0;
}
/**
* zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
* @chip: gpio_chip instance to be worked on
* @pin: gpio pin number within the device
* @state: value to be written to specified pin
*
* This function sets the direction of specified GPIO pin as output, configures
* the Output Enable register for the pin and uses zynq_gpio_set to set
* the state of the pin to the value specified.
*
* Return: 0 always
*/
static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
int state)
{
u32 reg;
unsigned int bank_num, bank_pin_num;
unsigned long flags;
struct zynq_gpio *gpio = gpiochip_get_data(chip);
zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
/* set the GPIO pin as output */
spin_lock_irqsave(&gpio->dirlock, flags);
reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
/* configure the output enable reg for the pin */
reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
spin_unlock_irqrestore(&gpio->dirlock, flags);
/* set the state of the pin */
zynq_gpio_set_value(chip, pin, state);
return 0;
}
/**
* zynq_gpio_get_direction - Read the direction of the specified GPIO pin
* @chip: gpio_chip instance to be worked on
* @pin: gpio pin number within the device
*
* This function returns the direction of the specified GPIO.
*
* Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN
*/
static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
{
u32 reg;
unsigned int bank_num, bank_pin_num;
struct zynq_gpio *gpio = gpiochip_get_data(chip);
zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
if (reg & BIT(bank_pin_num))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
/**
* zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
* @irq_data: per irq and chip data passed down to chip functions
*
* This function calculates gpio pin number from irq number and sets the
* bit in the Interrupt Disable register of the corresponding bank to disable
* interrupts for that pin.
*/
static void zynq_gpio_irq_mask(struct irq_data *irq_data)
{
unsigned int device_pin_num, bank_num, bank_pin_num;
const unsigned long offset = irqd_to_hwirq(irq_data);
struct gpio_chip *chip = irq_data_get_irq_chip_data(irq_data);
struct zynq_gpio *gpio =
gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
gpiochip_disable_irq(chip, offset);
device_pin_num = irq_data->hwirq;
zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
writel_relaxed(BIT(bank_pin_num),
gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
}
/**
* zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
* @irq_data: irq data containing irq number of gpio pin for the interrupt
* to enable
*
* This function calculates the gpio pin number from irq number and sets the
* bit in the Interrupt Enable register of the corresponding bank to enable
* interrupts for that pin.
*/
static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
{
unsigned int device_pin_num, bank_num, bank_pin_num;
const unsigned long offset = irqd_to_hwirq(irq_data);
struct gpio_chip *chip = irq_data_get_irq_chip_data(irq_data);
struct zynq_gpio *gpio =
gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
gpiochip_enable_irq(chip, offset);
device_pin_num = irq_data->hwirq;
zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
writel_relaxed(BIT(bank_pin_num),
gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
}
/**
* zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
* @irq_data: irq data containing irq number of gpio pin for the interrupt
* to ack
*
* This function calculates gpio pin number from irq number and sets the bit
* in the Interrupt Status Register of the corresponding bank, to ACK the irq.
*/
static void zynq_gpio_irq_ack(struct irq_data *irq_data)
{
unsigned int device_pin_num, bank_num, bank_pin_num;
struct zynq_gpio *gpio =
gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
device_pin_num = irq_data->hwirq;
zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
writel_relaxed(BIT(bank_pin_num),
gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
}
/**
* zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
* @irq_data: irq data containing irq number of gpio pin for the interrupt
* to enable
*
* Clears the INTSTS bit and unmasks the given interrupt.
*/
static void zynq_gpio_irq_enable(struct irq_data *irq_data)
{
/*
* The Zynq GPIO controller does not disable interrupt detection when
* the interrupt is masked and only disables the propagation of the
* interrupt. This means when the controller detects an interrupt
* condition while the interrupt is logically disabled it will propagate
* that interrupt event once the interrupt is enabled. This will cause
* the interrupt consumer to see spurious interrupts to prevent this
* first make sure that the interrupt is not asserted and then enable
* it.
*/
zynq_gpio_irq_ack(irq_data);
zynq_gpio_irq_unmask(irq_data);
}
/**
* zynq_gpio_set_irq_type - Set the irq type for a gpio pin
* @irq_data: irq data containing irq number of gpio pin
* @type: interrupt type that is to be set for the gpio pin
*
* This function gets the gpio pin number and its bank from the gpio pin number
* and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
*
* Return: 0, negative error otherwise.
* TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
* TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
* TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
* TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
* TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
*/
static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
{
u32 int_type, int_pol, int_any;
unsigned int device_pin_num, bank_num, bank_pin_num;
struct zynq_gpio *gpio =
gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
device_pin_num = irq_data->hwirq;
zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
int_type = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
int_pol = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
int_any = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_INTANY_OFFSET(bank_num));
/*
* based on the type requested, configure the INT_TYPE, INT_POLARITY
* and INT_ANY registers
*/
switch (type) {
case IRQ_TYPE_EDGE_RISING:
int_type |= BIT(bank_pin_num);
int_pol |= BIT(bank_pin_num);
int_any &= ~BIT(bank_pin_num);
break;
case IRQ_TYPE_EDGE_FALLING:
int_type |= BIT(bank_pin_num);
int_pol &= ~BIT(bank_pin_num);
int_any &= ~BIT(bank_pin_num);
break;
case IRQ_TYPE_EDGE_BOTH:
int_type |= BIT(bank_pin_num);
int_any |= BIT(bank_pin_num);
break;
case IRQ_TYPE_LEVEL_HIGH:
int_type &= ~BIT(bank_pin_num);
int_pol |= BIT(bank_pin_num);
break;
case IRQ_TYPE_LEVEL_LOW:
int_type &= ~BIT(bank_pin_num);
int_pol &= ~BIT(bank_pin_num);
break;
default:
return -EINVAL;
}
writel_relaxed(int_type,
gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
writel_relaxed(int_pol,
gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
writel_relaxed(int_any,
gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_chip_handler_name_locked(irq_data,
&zynq_gpio_level_irqchip,
handle_fasteoi_irq, NULL);
else
irq_set_chip_handler_name_locked(irq_data,
&zynq_gpio_edge_irqchip,
handle_level_irq, NULL);
return 0;
}
static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
{
struct zynq_gpio *gpio =
gpiochip_get_data(irq_data_get_irq_chip_data(data));
irq_set_irq_wake(gpio->irq, on);
return 0;
}
static int zynq_gpio_irq_reqres(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
int ret;
ret = pm_runtime_resume_and_get(chip->parent);
if (ret < 0)
return ret;
return gpiochip_reqres_irq(chip, d->hwirq);
}
static void zynq_gpio_irq_relres(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
gpiochip_relres_irq(chip, d->hwirq);
pm_runtime_put(chip->parent);
}
/* irq chip descriptor */
static const struct irq_chip zynq_gpio_level_irqchip = {
.name = DRIVER_NAME,
.irq_enable = zynq_gpio_irq_enable,
.irq_eoi = zynq_gpio_irq_ack,
.irq_mask = zynq_gpio_irq_mask,
.irq_unmask = zynq_gpio_irq_unmask,
.irq_set_type = zynq_gpio_set_irq_type,
.irq_set_wake = zynq_gpio_set_wake,
.irq_request_resources = zynq_gpio_irq_reqres,
.irq_release_resources = zynq_gpio_irq_relres,
.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
};
static const struct irq_chip zynq_gpio_edge_irqchip = {
.name = DRIVER_NAME,
.irq_enable = zynq_gpio_irq_enable,
.irq_ack = zynq_gpio_irq_ack,
.irq_mask = zynq_gpio_irq_mask,
.irq_unmask = zynq_gpio_irq_unmask,
.irq_set_type = zynq_gpio_set_irq_type,
.irq_set_wake = zynq_gpio_set_wake,
.irq_request_resources = zynq_gpio_irq_reqres,
.irq_release_resources = zynq_gpio_irq_relres,
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
};
static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
unsigned int bank_num,
unsigned long pending)
{
unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
struct irq_domain *irqdomain = gpio->chip.irq.domain;
int offset;
if (!pending)
return;
for_each_set_bit(offset, &pending, 32)
generic_handle_domain_irq(irqdomain, offset + bank_offset);
}
/**
* zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
* @desc: irq descriptor instance of the 'irq'
*
* This function reads the Interrupt Status Register of each bank to get the
* gpio pin number which has triggered an interrupt. It then acks the triggered
* interrupt and calls the pin specific handler set by the higher layer
* application for that pin.
* Note: A bug is reported if no handler is set for the gpio pin.
*/
static void zynq_gpio_irqhandler(struct irq_desc *desc)
{
u32 int_sts, int_enb;
unsigned int bank_num;
struct zynq_gpio *gpio =
gpiochip_get_data(irq_desc_get_handler_data(desc));
struct irq_chip *irqchip = irq_desc_get_chip(desc);
chained_irq_enter(irqchip, desc);
for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
int_sts = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
int_enb = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
bank_num = bank_num + VERSAL_UNUSED_BANKS;
}
chained_irq_exit(irqchip, desc);
}
static void zynq_gpio_save_context(struct zynq_gpio *gpio)
{
unsigned int bank_num;
for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
gpio->context.datalsw[bank_num] =
readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
gpio->context.datamsw[bank_num] =
readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_DIRM_OFFSET(bank_num));
gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
gpio->context.int_type[bank_num] =
readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
gpio->context.int_polarity[bank_num] =
readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
gpio->context.int_any[bank_num] =
readl_relaxed(gpio->base_addr +
ZYNQ_GPIO_INTANY_OFFSET(bank_num));
if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
bank_num = bank_num + VERSAL_UNUSED_BANKS;
}
}
static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
{
unsigned int bank_num;
for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
writel_relaxed(gpio->context.datalsw[bank_num],
gpio->base_addr +
ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
writel_relaxed(gpio->context.datamsw[bank_num],
gpio->base_addr +
ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
writel_relaxed(gpio->context.dirm[bank_num],
gpio->base_addr +
ZYNQ_GPIO_DIRM_OFFSET(bank_num));
writel_relaxed(gpio->context.int_type[bank_num],
gpio->base_addr +
ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
writel_relaxed(gpio->context.int_polarity[bank_num],
gpio->base_addr +
ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
writel_relaxed(gpio->context.int_any[bank_num],
gpio->base_addr +
ZYNQ_GPIO_INTANY_OFFSET(bank_num));
writel_relaxed(~(gpio->context.int_en[bank_num]),
gpio->base_addr +
ZYNQ_GPIO_INTEN_OFFSET(bank_num));
if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
bank_num = bank_num + VERSAL_UNUSED_BANKS;
}
}
static int __maybe_unused zynq_gpio_suspend(struct device *dev)
{
struct zynq_gpio *gpio = dev_get_drvdata(dev);
struct irq_data *data = irq_get_irq_data(gpio->irq);
if (!data) {
dev_err(dev, "irq_get_irq_data() failed\n");
return -EINVAL;
}
if (!device_may_wakeup(dev))
disable_irq(gpio->irq);
if (!irqd_is_wakeup_set(data)) {
zynq_gpio_save_context(gpio);
return pm_runtime_force_suspend(dev);
}
return 0;
}
static int __maybe_unused zynq_gpio_resume(struct device *dev)
{
struct zynq_gpio *gpio = dev_get_drvdata(dev);
struct irq_data *data = irq_get_irq_data(gpio->irq);
int ret;
if (!data) {
dev_err(dev, "irq_get_irq_data() failed\n");
return -EINVAL;
}
if (!device_may_wakeup(dev))
enable_irq(gpio->irq);
if (!irqd_is_wakeup_set(data)) {
ret = pm_runtime_force_resume(dev);
zynq_gpio_restore_context(gpio);
return ret;
}
return 0;
}
static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
{
struct zynq_gpio *gpio = dev_get_drvdata(dev);
clk_disable_unprepare(gpio->clk);
return 0;
}
static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
{
struct zynq_gpio *gpio = dev_get_drvdata(dev);
return clk_prepare_enable(gpio->clk);
}
static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
int ret;
ret = pm_runtime_get_sync(chip->parent);
/*
* If the device is already active pm_runtime_get() will return 1 on
* success, but gpio_request still needs to return 0.
*/
return ret < 0 ? ret : 0;
}
static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
pm_runtime_put(chip->parent);
}
static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
zynq_gpio_runtime_resume, NULL)
};
static const struct zynq_platform_data versal_gpio_def = {
.label = "versal_gpio",
.quirks = GPIO_QUIRK_VERSAL,
.ngpio = 58,
.max_bank = VERSAL_GPIO_MAX_BANK,
.bank_min[0] = 0,
.bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
.bank_min[3] = 26,
.bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
};
static const struct zynq_platform_data pmc_gpio_def = {
.label = "pmc_gpio",
.ngpio = 116,
.max_bank = PMC_GPIO_MAX_BANK,
.bank_min[0] = 0,
.bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
.bank_min[1] = 26,
.bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
.bank_min[3] = 52,
.bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
.bank_min[4] = 84,
.bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
};
static const struct zynq_platform_data zynqmp_gpio_def = {
.label = "zynqmp_gpio",
.quirks = GPIO_QUIRK_DATA_RO_BUG,
.ngpio = ZYNQMP_GPIO_NR_GPIOS,
.max_bank = ZYNQMP_GPIO_MAX_BANK,
.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
.bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
.bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
.bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
.bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
};
static const struct zynq_platform_data zynq_gpio_def = {
.label = "zynq_gpio",
.quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
.ngpio = ZYNQ_GPIO_NR_GPIOS,
.max_bank = ZYNQ_GPIO_MAX_BANK,
.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
};
static const struct of_device_id zynq_gpio_of_match[] = {
{ .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
{ .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
{ .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
{ .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
{ /* end of table */ }
};
MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
/**
* zynq_gpio_probe - Initialization method for a zynq_gpio device
* @pdev: platform device instance
*
* This function allocates memory resources for the gpio device and registers
* all the banks of the device. It will also set up interrupts for the gpio
* pins.
* Note: Interrupts are disabled for all the banks during initialization.
*
* Return: 0 on success, negative error otherwise.
*/
static int zynq_gpio_probe(struct platform_device *pdev)
{
int ret, bank_num;
struct zynq_gpio *gpio;
struct gpio_chip *chip;
struct gpio_irq_chip *girq;
const struct of_device_id *match;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
if (!match) {
dev_err(&pdev->dev, "of_match_node() failed\n");
return -EINVAL;
}
gpio->p_data = match->data;
platform_set_drvdata(pdev, gpio);
gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(gpio->base_addr))
return PTR_ERR(gpio->base_addr);
gpio->irq = platform_get_irq(pdev, 0);
if (gpio->irq < 0)
return gpio->irq;
/* configure the gpio chip */
chip = &gpio->chip;
chip->label = gpio->p_data->label;
chip->owner = THIS_MODULE;
chip->parent = &pdev->dev;
chip->get = zynq_gpio_get_value;
chip->set = zynq_gpio_set_value;
chip->request = zynq_gpio_request;
chip->free = zynq_gpio_free;
chip->direction_input = zynq_gpio_dir_in;
chip->direction_output = zynq_gpio_dir_out;
chip->get_direction = zynq_gpio_get_direction;
chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
chip->ngpio = gpio->p_data->ngpio;
/* Retrieve GPIO clock */
gpio->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(gpio->clk))
return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n");
ret = clk_prepare_enable(gpio->clk);
if (ret) {
dev_err(&pdev->dev, "Unable to enable clock.\n");
return ret;
}
spin_lock_init(&gpio->dirlock);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0)
goto err_pm_dis;
/* disable interrupts for all banks */
for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
bank_num = bank_num + VERSAL_UNUSED_BANKS;
}
/* Set up the GPIO irqchip */
girq = &chip->irq;
gpio_irq_chip_set_chip(girq, &zynq_gpio_edge_irqchip);
girq->parent_handler = zynq_gpio_irqhandler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(&pdev->dev, 1,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents) {
ret = -ENOMEM;
goto err_pm_put;
}
girq->parents[0] = gpio->irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
/* report a bug if gpio chip registration fails */
ret = gpiochip_add_data(chip, gpio);
if (ret) {
dev_err(&pdev->dev, "Failed to add gpio chip\n");
goto err_pm_put;
}
irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
device_init_wakeup(&pdev->dev, 1);
pm_runtime_put(&pdev->dev);
return 0;
err_pm_put:
pm_runtime_put(&pdev->dev);
err_pm_dis:
pm_runtime_disable(&pdev->dev);
clk_disable_unprepare(gpio->clk);
return ret;
}
/**
* zynq_gpio_remove - Driver removal function
* @pdev: platform device instance
*
* Return: 0 always
*/
static int zynq_gpio_remove(struct platform_device *pdev)
{
struct zynq_gpio *gpio = platform_get_drvdata(pdev);
int ret;
ret = pm_runtime_get_sync(&pdev->dev);
if (ret < 0)
dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n");
gpiochip_remove(&gpio->chip);
clk_disable_unprepare(gpio->clk);
device_set_wakeup_capable(&pdev->dev, 0);
pm_runtime_disable(&pdev->dev);
return 0;
}
static struct platform_driver zynq_gpio_driver = {
.driver = {
.name = DRIVER_NAME,
.pm = &zynq_gpio_dev_pm_ops,
.of_match_table = zynq_gpio_of_match,
},
.probe = zynq_gpio_probe,
.remove = zynq_gpio_remove,
};
module_platform_driver(zynq_gpio_driver);
MODULE_AUTHOR("Xilinx Inc.");
MODULE_DESCRIPTION("Zynq GPIO driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-zynq.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* GPIO Driver for Dialog DA9055 PMICs.
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>
#include <linux/mfd/da9055/core.h>
#include <linux/mfd/da9055/reg.h>
#include <linux/mfd/da9055/pdata.h>
#define DA9055_VDD_IO 0x0
#define DA9055_PUSH_PULL 0x3
#define DA9055_ACT_LOW 0x0
#define DA9055_GPI 0x1
#define DA9055_PORT_MASK 0x3
#define DA9055_PORT_SHIFT(offset) (4 * (offset % 2))
#define DA9055_INPUT DA9055_GPI
#define DA9055_OUTPUT DA9055_PUSH_PULL
#define DA9055_IRQ_GPI0 3
struct da9055_gpio {
struct da9055 *da9055;
struct gpio_chip gp;
};
static int da9055_gpio_get(struct gpio_chip *gc, unsigned offset)
{
struct da9055_gpio *gpio = gpiochip_get_data(gc);
int gpio_direction = 0;
int ret;
/* Get GPIO direction */
ret = da9055_reg_read(gpio->da9055, (offset >> 1) + DA9055_REG_GPIO0_1);
if (ret < 0)
return ret;
gpio_direction = ret & (DA9055_PORT_MASK) << DA9055_PORT_SHIFT(offset);
gpio_direction >>= DA9055_PORT_SHIFT(offset);
switch (gpio_direction) {
case DA9055_INPUT:
ret = da9055_reg_read(gpio->da9055, DA9055_REG_STATUS_B);
if (ret < 0)
return ret;
break;
case DA9055_OUTPUT:
ret = da9055_reg_read(gpio->da9055, DA9055_REG_GPIO_MODE0_2);
if (ret < 0)
return ret;
}
return ret & (1 << offset);
}
static void da9055_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
{
struct da9055_gpio *gpio = gpiochip_get_data(gc);
da9055_reg_update(gpio->da9055,
DA9055_REG_GPIO_MODE0_2,
1 << offset,
value << offset);
}
static int da9055_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct da9055_gpio *gpio = gpiochip_get_data(gc);
unsigned char reg_byte;
reg_byte = (DA9055_ACT_LOW | DA9055_GPI)
<< DA9055_PORT_SHIFT(offset);
return da9055_reg_update(gpio->da9055, (offset >> 1) +
DA9055_REG_GPIO0_1,
DA9055_PORT_MASK <<
DA9055_PORT_SHIFT(offset),
reg_byte);
}
static int da9055_gpio_direction_output(struct gpio_chip *gc,
unsigned offset, int value)
{
struct da9055_gpio *gpio = gpiochip_get_data(gc);
unsigned char reg_byte;
int ret;
reg_byte = (DA9055_VDD_IO | DA9055_PUSH_PULL)
<< DA9055_PORT_SHIFT(offset);
ret = da9055_reg_update(gpio->da9055, (offset >> 1) +
DA9055_REG_GPIO0_1,
DA9055_PORT_MASK <<
DA9055_PORT_SHIFT(offset),
reg_byte);
if (ret < 0)
return ret;
da9055_gpio_set(gc, offset, value);
return 0;
}
static int da9055_gpio_to_irq(struct gpio_chip *gc, u32 offset)
{
struct da9055_gpio *gpio = gpiochip_get_data(gc);
struct da9055 *da9055 = gpio->da9055;
return regmap_irq_get_virq(da9055->irq_data,
DA9055_IRQ_GPI0 + offset);
}
static const struct gpio_chip reference_gp = {
.label = "da9055-gpio",
.owner = THIS_MODULE,
.get = da9055_gpio_get,
.set = da9055_gpio_set,
.direction_input = da9055_gpio_direction_input,
.direction_output = da9055_gpio_direction_output,
.to_irq = da9055_gpio_to_irq,
.can_sleep = true,
.ngpio = 3,
.base = -1,
};
static int da9055_gpio_probe(struct platform_device *pdev)
{
struct da9055_gpio *gpio;
struct da9055_pdata *pdata;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
gpio->da9055 = dev_get_drvdata(pdev->dev.parent);
pdata = dev_get_platdata(gpio->da9055->dev);
gpio->gp = reference_gp;
if (pdata && pdata->gpio_base)
gpio->gp.base = pdata->gpio_base;
return devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio);
}
static struct platform_driver da9055_gpio_driver = {
.probe = da9055_gpio_probe,
.driver = {
.name = "da9055-gpio",
},
};
static int __init da9055_gpio_init(void)
{
return platform_driver_register(&da9055_gpio_driver);
}
subsys_initcall(da9055_gpio_init);
static void __exit da9055_gpio_exit(void)
{
platform_driver_unregister(&da9055_gpio_driver);
}
module_exit(da9055_gpio_exit);
MODULE_AUTHOR("David Dajun Chen <[email protected]>");
MODULE_DESCRIPTION("DA9055 GPIO Device Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:da9055-gpio");
| linux-master | drivers/gpio/gpio-da9055.c |
// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/types.h>
/*
* There are 2 YU GPIO blocks:
* gpio[0]: HOST_GPIO0->HOST_GPIO31
* gpio[1]: HOST_GPIO32->HOST_GPIO55
*/
#define MLXBF3_GPIO_MAX_PINS_PER_BLOCK 32
#define MLXBF3_GPIO_MAX_PINS_BLOCK0 32
#define MLXBF3_GPIO_MAX_PINS_BLOCK1 24
/*
* fw_gpio[x] block registers and their offset
*/
#define MLXBF_GPIO_FW_OUTPUT_ENABLE_SET 0x00
#define MLXBF_GPIO_FW_DATA_OUT_SET 0x04
#define MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR 0x00
#define MLXBF_GPIO_FW_DATA_OUT_CLEAR 0x04
#define MLXBF_GPIO_CAUSE_RISE_EN 0x00
#define MLXBF_GPIO_CAUSE_FALL_EN 0x04
#define MLXBF_GPIO_READ_DATA_IN 0x08
#define MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x00
#define MLXBF_GPIO_CAUSE_OR_EVTEN0 0x14
#define MLXBF_GPIO_CAUSE_OR_CLRCAUSE 0x18
struct mlxbf3_gpio_context {
struct gpio_chip gc;
/* YU GPIO block address */
void __iomem *gpio_set_io;
void __iomem *gpio_clr_io;
void __iomem *gpio_io;
/* YU GPIO cause block address */
void __iomem *gpio_cause_io;
};
static void mlxbf3_gpio_irq_enable(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
irq_hw_number_t offset = irqd_to_hwirq(irqd);
unsigned long flags;
u32 val;
gpiochip_enable_irq(gc, offset);
raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
val |= BIT(offset);
writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
}
static void mlxbf3_gpio_irq_disable(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
irq_hw_number_t offset = irqd_to_hwirq(irqd);
unsigned long flags;
u32 val;
raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
val &= ~BIT(offset);
writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
gpiochip_disable_irq(gc, offset);
}
static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr)
{
struct mlxbf3_gpio_context *gs = ptr;
struct gpio_chip *gc = &gs->gc;
unsigned long pending;
u32 level;
pending = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0);
writel(pending, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
for_each_set_bit(level, &pending, gc->ngpio)
generic_handle_domain_irq(gc->irq.domain, level);
return IRQ_RETVAL(pending);
}
static int
mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
irq_hw_number_t offset = irqd_to_hwirq(irqd);
unsigned long flags;
u32 val;
raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_BOTH:
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
val |= BIT(offset);
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
val |= BIT(offset);
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
break;
case IRQ_TYPE_EDGE_RISING:
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
val |= BIT(offset);
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
break;
case IRQ_TYPE_EDGE_FALLING:
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
val |= BIT(offset);
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
break;
default:
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
return -EINVAL;
}
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
irq_set_handler_locked(irqd, handle_edge_irq);
return 0;
}
/* This function needs to be defined for handle_edge_irq() */
static void mlxbf3_gpio_irq_ack(struct irq_data *data)
{
}
static const struct irq_chip gpio_mlxbf3_irqchip = {
.name = "MLNXBF33",
.irq_ack = mlxbf3_gpio_irq_ack,
.irq_set_type = mlxbf3_gpio_irq_set_type,
.irq_enable = mlxbf3_gpio_irq_enable,
.irq_disable = mlxbf3_gpio_irq_disable,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip *chip)
{
unsigned int id;
switch(chip->ngpio) {
case MLXBF3_GPIO_MAX_PINS_BLOCK0:
id = 0;
break;
case MLXBF3_GPIO_MAX_PINS_BLOCK1:
id = 1;
break;
default:
return -EINVAL;
}
return gpiochip_add_pin_range(chip, "MLNXBF34:00",
chip->base, id * MLXBF3_GPIO_MAX_PINS_PER_BLOCK,
chip->ngpio);
}
static int mlxbf3_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mlxbf3_gpio_context *gs;
struct gpio_irq_chip *girq;
struct gpio_chip *gc;
int ret, irq;
gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
if (!gs)
return -ENOMEM;
gs->gpio_io = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(gs->gpio_io))
return PTR_ERR(gs->gpio_io);
gs->gpio_cause_io = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(gs->gpio_cause_io))
return PTR_ERR(gs->gpio_cause_io);
gs->gpio_set_io = devm_platform_ioremap_resource(pdev, 2);
if (IS_ERR(gs->gpio_set_io))
return PTR_ERR(gs->gpio_set_io);
gs->gpio_clr_io = devm_platform_ioremap_resource(pdev, 3);
if (IS_ERR(gs->gpio_clr_io))
return PTR_ERR(gs->gpio_clr_io);
gc = &gs->gc;
ret = bgpio_init(gc, dev, 4,
gs->gpio_io + MLXBF_GPIO_READ_DATA_IN,
gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET,
gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR,
gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET,
gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0);
gc->request = gpiochip_generic_request;
gc->free = gpiochip_generic_free;
gc->owner = THIS_MODULE;
gc->add_pin_ranges = mlxbf3_gpio_add_pin_ranges;
irq = platform_get_irq(pdev, 0);
if (irq >= 0) {
girq = &gs->gc.irq;
gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip);
girq->default_type = IRQ_TYPE_NONE;
/* This will let us handle the parent IRQ in the driver */
girq->num_parents = 0;
girq->parents = NULL;
girq->parent_handler = NULL;
girq->handler = handle_bad_irq;
/*
* Directly request the irq here instead of passing
* a flow-handler because the irq is shared.
*/
ret = devm_request_irq(dev, irq, mlxbf3_gpio_irq_handler,
IRQF_SHARED, dev_name(dev), gs);
if (ret)
return dev_err_probe(dev, ret, "failed to request IRQ");
}
platform_set_drvdata(pdev, gs);
ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
if (ret)
dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n");
return 0;
}
static const struct acpi_device_id mlxbf3_gpio_acpi_match[] = {
{ "MLNXBF33", 0 },
{}
};
MODULE_DEVICE_TABLE(acpi, mlxbf3_gpio_acpi_match);
static struct platform_driver mlxbf3_gpio_driver = {
.driver = {
.name = "mlxbf3_gpio",
.acpi_match_table = mlxbf3_gpio_acpi_match,
},
.probe = mlxbf3_gpio_probe,
};
module_platform_driver(mlxbf3_gpio_driver);
MODULE_SOFTDEP("pre: pinctrl-mlxbf3");
MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver");
MODULE_AUTHOR("Asmaa Mnebhi <[email protected]>");
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | drivers/gpio/gpio-mlxbf3.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015-2023 Texas Instruments Incorporated - https://www.ti.com/
* Andrew Davis <[email protected]>
*
* Based on the TPS65912 driver
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/tps65086.h>
struct tps65086_gpio {
struct gpio_chip chip;
struct tps65086 *tps;
};
static int tps65086_gpio_get_direction(struct gpio_chip *chip,
unsigned offset)
{
/* This device is output only */
return GPIO_LINE_DIRECTION_OUT;
}
static int tps65086_gpio_direction_input(struct gpio_chip *chip,
unsigned offset)
{
/* This device is output only */
return -EINVAL;
}
static int tps65086_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct tps65086_gpio *gpio = gpiochip_get_data(chip);
/* Set the initial value */
regmap_update_bits(gpio->tps->regmap, TPS65086_GPOCTRL,
BIT(4 + offset), value ? BIT(4 + offset) : 0);
return 0;
}
static int tps65086_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct tps65086_gpio *gpio = gpiochip_get_data(chip);
int ret, val;
ret = regmap_read(gpio->tps->regmap, TPS65086_GPOCTRL, &val);
if (ret < 0)
return ret;
return val & BIT(4 + offset);
}
static void tps65086_gpio_set(struct gpio_chip *chip, unsigned offset,
int value)
{
struct tps65086_gpio *gpio = gpiochip_get_data(chip);
regmap_update_bits(gpio->tps->regmap, TPS65086_GPOCTRL,
BIT(4 + offset), value ? BIT(4 + offset) : 0);
}
static const struct gpio_chip template_chip = {
.label = "tps65086-gpio",
.owner = THIS_MODULE,
.get_direction = tps65086_gpio_get_direction,
.direction_input = tps65086_gpio_direction_input,
.direction_output = tps65086_gpio_direction_output,
.get = tps65086_gpio_get,
.set = tps65086_gpio_set,
.base = -1,
.ngpio = 4,
.can_sleep = true,
};
static int tps65086_gpio_probe(struct platform_device *pdev)
{
struct tps65086_gpio *gpio;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
gpio->tps = dev_get_drvdata(pdev->dev.parent);
gpio->chip = template_chip;
gpio->chip.parent = gpio->tps->dev;
return devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
}
static const struct platform_device_id tps65086_gpio_id_table[] = {
{ "tps65086-gpio", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, tps65086_gpio_id_table);
static struct platform_driver tps65086_gpio_driver = {
.driver = {
.name = "tps65086-gpio",
},
.probe = tps65086_gpio_probe,
.id_table = tps65086_gpio_id_table,
};
module_platform_driver(tps65086_gpio_driver);
MODULE_AUTHOR("Andrew Davis <[email protected]>");
MODULE_DESCRIPTION("TPS65086 GPIO driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/gpio/gpio-tps65086.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2009-2011 Gabor Juhos <[email protected]>
* Copyright (C) 2013 John Crispin <[email protected]>
*/
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#define MTK_BANK_CNT 3
#define MTK_BANK_WIDTH 32
#define GPIO_BANK_STRIDE 0x04
#define GPIO_REG_CTRL 0x00
#define GPIO_REG_POL 0x10
#define GPIO_REG_DATA 0x20
#define GPIO_REG_DSET 0x30
#define GPIO_REG_DCLR 0x40
#define GPIO_REG_REDGE 0x50
#define GPIO_REG_FEDGE 0x60
#define GPIO_REG_HLVL 0x70
#define GPIO_REG_LLVL 0x80
#define GPIO_REG_STAT 0x90
#define GPIO_REG_EDGE 0xA0
struct mtk_gc {
struct irq_chip irq_chip;
struct gpio_chip chip;
spinlock_t lock;
int bank;
u32 rising;
u32 falling;
u32 hlevel;
u32 llevel;
};
/**
* struct mtk - state container for
* data of the platform driver. It is 3
* separate gpio-chip each one with its
* own irq_chip.
* @dev: device instance
* @base: memory base address
* @gpio_irq: irq number from the device tree
* @gc_map: array of the gpio chips
*/
struct mtk {
struct device *dev;
void __iomem *base;
int gpio_irq;
struct mtk_gc gc_map[MTK_BANK_CNT];
};
static inline struct mtk_gc *
to_mediatek_gpio(struct gpio_chip *chip)
{
return container_of(chip, struct mtk_gc, chip);
}
static inline void
mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
{
struct gpio_chip *gc = &rg->chip;
struct mtk *mtk = gpiochip_get_data(gc);
offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
gc->write_reg(mtk->base + offset, val);
}
static inline u32
mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
{
struct gpio_chip *gc = &rg->chip;
struct mtk *mtk = gpiochip_get_data(gc);
offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
return gc->read_reg(mtk->base + offset);
}
static irqreturn_t
mediatek_gpio_irq_handler(int irq, void *data)
{
struct gpio_chip *gc = data;
struct mtk_gc *rg = to_mediatek_gpio(gc);
irqreturn_t ret = IRQ_NONE;
unsigned long pending;
int bit;
pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
generic_handle_domain_irq(gc->irq.domain, bit);
mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
ret |= IRQ_HANDLED;
}
return ret;
}
static void
mediatek_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct mtk_gc *rg = to_mediatek_gpio(gc);
int pin = d->hwirq;
unsigned long flags;
u32 rise, fall, high, low;
gpiochip_enable_irq(gc, d->hwirq);
spin_lock_irqsave(&rg->lock, flags);
rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));
mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
spin_unlock_irqrestore(&rg->lock, flags);
}
static void
mediatek_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct mtk_gc *rg = to_mediatek_gpio(gc);
int pin = d->hwirq;
unsigned long flags;
u32 rise, fall, high, low;
spin_lock_irqsave(&rg->lock, flags);
rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
spin_unlock_irqrestore(&rg->lock, flags);
gpiochip_disable_irq(gc, d->hwirq);
}
static int
mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct mtk_gc *rg = to_mediatek_gpio(gc);
int pin = d->hwirq;
u32 mask = BIT(pin);
if (type == IRQ_TYPE_PROBE) {
if ((rg->rising | rg->falling |
rg->hlevel | rg->llevel) & mask)
return 0;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
rg->rising &= ~mask;
rg->falling &= ~mask;
rg->hlevel &= ~mask;
rg->llevel &= ~mask;
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_BOTH:
rg->rising |= mask;
rg->falling |= mask;
break;
case IRQ_TYPE_EDGE_RISING:
rg->rising |= mask;
break;
case IRQ_TYPE_EDGE_FALLING:
rg->falling |= mask;
break;
case IRQ_TYPE_LEVEL_HIGH:
rg->hlevel |= mask;
break;
case IRQ_TYPE_LEVEL_LOW:
rg->llevel |= mask;
break;
}
return 0;
}
static int
mediatek_gpio_xlate(struct gpio_chip *chip,
const struct of_phandle_args *spec, u32 *flags)
{
int gpio = spec->args[0];
struct mtk_gc *rg = to_mediatek_gpio(chip);
if (rg->bank != gpio / MTK_BANK_WIDTH)
return -EINVAL;
if (flags)
*flags = spec->args[1];
return gpio % MTK_BANK_WIDTH;
}
static const struct irq_chip mt7621_irq_chip = {
.name = "mt7621-gpio",
.irq_mask_ack = mediatek_gpio_irq_mask,
.irq_mask = mediatek_gpio_irq_mask,
.irq_unmask = mediatek_gpio_irq_unmask,
.irq_set_type = mediatek_gpio_irq_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int
mediatek_gpio_bank_probe(struct device *dev, int bank)
{
struct mtk *mtk = dev_get_drvdata(dev);
struct mtk_gc *rg;
void __iomem *dat, *set, *ctrl, *diro;
int ret;
rg = &mtk->gc_map[bank];
memset(rg, 0, sizeof(*rg));
spin_lock_init(&rg->lock);
rg->bank = bank;
dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);
ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL,
BGPIOF_NO_SET_ON_INPUT);
if (ret) {
dev_err(dev, "bgpio_init() failed\n");
return ret;
}
rg->chip.of_gpio_n_cells = 2;
rg->chip.of_xlate = mediatek_gpio_xlate;
rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
dev_name(dev), bank);
if (!rg->chip.label)
return -ENOMEM;
rg->chip.offset = bank * MTK_BANK_WIDTH;
if (mtk->gpio_irq) {
struct gpio_irq_chip *girq;
/*
* Directly request the irq here instead of passing
* a flow-handler because the irq is shared.
*/
ret = devm_request_irq(dev, mtk->gpio_irq,
mediatek_gpio_irq_handler, IRQF_SHARED,
rg->chip.label, &rg->chip);
if (ret) {
dev_err(dev, "Error requesting IRQ %d: %d\n",
mtk->gpio_irq, ret);
return ret;
}
girq = &rg->chip.irq;
gpio_irq_chip_set_chip(girq, &mt7621_irq_chip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
}
ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
if (ret < 0) {
dev_err(dev, "Could not register gpio %d, ret=%d\n",
rg->chip.ngpio, ret);
return ret;
}
/* set polarity to low for all gpios */
mtk_gpio_w32(rg, GPIO_REG_POL, 0);
dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);
return 0;
}
static int
mediatek_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk *mtk;
int i;
int ret;
mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
if (!mtk)
return -ENOMEM;
mtk->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(mtk->base))
return PTR_ERR(mtk->base);
mtk->gpio_irq = platform_get_irq(pdev, 0);
if (mtk->gpio_irq < 0)
return mtk->gpio_irq;
mtk->dev = dev;
platform_set_drvdata(pdev, mtk);
for (i = 0; i < MTK_BANK_CNT; i++) {
ret = mediatek_gpio_bank_probe(dev, i);
if (ret)
return ret;
}
return 0;
}
static const struct of_device_id mediatek_gpio_match[] = {
{ .compatible = "mediatek,mt7621-gpio" },
{},
};
MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
static struct platform_driver mediatek_gpio_driver = {
.probe = mediatek_gpio_probe,
.driver = {
.name = "mt7621_gpio",
.of_match_table = mediatek_gpio_match,
},
};
builtin_platform_driver(mediatek_gpio_driver);
| linux-master | drivers/gpio/gpio-mt7621.c |
// SPDX-License-Identifier: GPL-2.0+
//
// MXS GPIO support. (c) 2008 Daniel Mack <[email protected]>
// Copyright 2008 Juergen Beisert, [email protected]
//
// Based on code from Freescale,
// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#define MXS_SET 0x4
#define MXS_CLR 0x8
#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
#define GPIO_INT_FALL_EDGE 0x0
#define GPIO_INT_LOW_LEV 0x1
#define GPIO_INT_RISE_EDGE 0x2
#define GPIO_INT_HIGH_LEV 0x3
#define GPIO_INT_LEV_MASK (1 << 0)
#define GPIO_INT_POL_MASK (1 << 1)
enum mxs_gpio_id {
IMX23_GPIO,
IMX28_GPIO,
};
struct mxs_gpio_port {
void __iomem *base;
int id;
int irq;
struct irq_domain *domain;
struct gpio_chip gc;
struct device *dev;
enum mxs_gpio_id devid;
u32 both_edges;
};
static inline int is_imx23_gpio(struct mxs_gpio_port *port)
{
return port->devid == IMX23_GPIO;
}
/* Note: This driver assumes 32 GPIOs are handled in one register */
static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
u32 val;
u32 pin_mask = 1 << d->hwirq;
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
struct mxs_gpio_port *port = gc->private;
void __iomem *pin_addr;
int edge;
if (!(ct->type & type))
if (irq_setup_alt_chip(d, type))
return -EINVAL;
port->both_edges &= ~pin_mask;
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
if (val)
edge = GPIO_INT_FALL_EDGE;
else
edge = GPIO_INT_RISE_EDGE;
port->both_edges |= pin_mask;
break;
case IRQ_TYPE_EDGE_RISING:
edge = GPIO_INT_RISE_EDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
edge = GPIO_INT_FALL_EDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
edge = GPIO_INT_LOW_LEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
edge = GPIO_INT_HIGH_LEV;
break;
default:
return -EINVAL;
}
/* set level or edge */
pin_addr = port->base + PINCTRL_IRQLEV(port);
if (edge & GPIO_INT_LEV_MASK) {
writel(pin_mask, pin_addr + MXS_SET);
writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
} else {
writel(pin_mask, pin_addr + MXS_CLR);
writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
}
/* set polarity */
pin_addr = port->base + PINCTRL_IRQPOL(port);
if (edge & GPIO_INT_POL_MASK)
writel(pin_mask, pin_addr + MXS_SET);
else
writel(pin_mask, pin_addr + MXS_CLR);
writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
return 0;
}
static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
{
u32 bit, val, edge;
void __iomem *pin_addr;
bit = 1 << gpio;
pin_addr = port->base + PINCTRL_IRQPOL(port);
val = readl(pin_addr);
edge = val & bit;
if (edge)
writel(bit, pin_addr + MXS_CLR);
else
writel(bit, pin_addr + MXS_SET);
}
/* MXS has one interrupt *per* gpio port */
static void mxs_gpio_irq_handler(struct irq_desc *desc)
{
u32 irq_stat;
struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
desc->irq_data.chip->irq_ack(&desc->irq_data);
irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
readl(port->base + PINCTRL_IRQEN(port));
while (irq_stat != 0) {
int irqoffset = fls(irq_stat) - 1;
if (port->both_edges & (1 << irqoffset))
mxs_flip_edge(port, irqoffset);
generic_handle_domain_irq(port->domain, irqoffset);
irq_stat &= ~(1 << irqoffset);
}
}
/*
* Set interrupt number "irq" in the GPIO as a wake-up source.
* While system is running, all registered GPIO interrupts need to have
* wake-up enabled. When system is suspended, only selected GPIO interrupts
* need to have wake-up enabled.
* @param irq interrupt source number
* @param enable enable as wake-up if equal to non-zero
* @return This function returns 0 on success.
*/
static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct mxs_gpio_port *port = gc->private;
if (enable)
enable_irq_wake(port->irq);
else
disable_irq_wake(port->irq);
return 0;
}
static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
int rv;
gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
port->base, handle_level_irq);
if (!gc)
return -ENOMEM;
gc->private = port;
ct = &gc->chip_types[0];
ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
ct->chip.irq_ack = irq_gc_ack_set_bit;
ct->chip.irq_mask = irq_gc_mask_disable_reg;
ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
ct->chip.irq_set_type = mxs_gpio_set_irq_type;
ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
ct = &gc->chip_types[1];
ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
ct->chip.irq_ack = irq_gc_ack_set_bit;
ct->chip.irq_mask = irq_gc_mask_disable_reg;
ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
ct->chip.irq_set_type = mxs_gpio_set_irq_type;
ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
ct->handler = handle_level_irq;
rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
IRQ_GC_INIT_NESTED_LOCK,
IRQ_NOREQUEST, 0);
return rv;
}
static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
{
struct mxs_gpio_port *port = gpiochip_get_data(gc);
return irq_find_mapping(port->domain, offset);
}
static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
struct mxs_gpio_port *port = gpiochip_get_data(gc);
u32 mask = 1 << offset;
u32 dir;
dir = readl(port->base + PINCTRL_DOE(port));
if (dir & mask)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static const struct of_device_id mxs_gpio_dt_ids[] = {
{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
static int mxs_gpio_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *parent;
static void __iomem *base;
struct mxs_gpio_port *port;
int irq_base;
int err;
port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
if (!port)
return -ENOMEM;
port->id = of_alias_get_id(np, "gpio");
if (port->id < 0)
return port->id;
port->devid = (uintptr_t)of_device_get_match_data(&pdev->dev);
port->dev = &pdev->dev;
port->irq = platform_get_irq(pdev, 0);
if (port->irq < 0)
return port->irq;
/*
* map memory region only once, as all the gpio ports
* share the same one
*/
if (!base) {
parent = of_get_parent(np);
base = of_iomap(parent, 0);
of_node_put(parent);
if (!base)
return -EADDRNOTAVAIL;
}
port->base = base;
/* initially disable the interrupts */
writel(0, port->base + PINCTRL_PIN2IRQ(port));
writel(0, port->base + PINCTRL_IRQEN(port));
/* clear address has to be used to clear IRQSTAT bits */
writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
if (irq_base < 0) {
err = irq_base;
goto out_iounmap;
}
port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
&irq_domain_simple_ops, NULL);
if (!port->domain) {
err = -ENODEV;
goto out_iounmap;
}
/* gpio-mxs can be a generic irq chip */
err = mxs_gpio_init_gc(port, irq_base);
if (err < 0)
goto out_irqdomain_remove;
/* setup one handler for each entry */
irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
port);
err = bgpio_init(&port->gc, &pdev->dev, 4,
port->base + PINCTRL_DIN(port),
port->base + PINCTRL_DOUT(port) + MXS_SET,
port->base + PINCTRL_DOUT(port) + MXS_CLR,
port->base + PINCTRL_DOE(port), NULL, 0);
if (err)
goto out_irqdomain_remove;
port->gc.to_irq = mxs_gpio_to_irq;
port->gc.get_direction = mxs_gpio_get_direction;
port->gc.base = port->id * 32;
err = gpiochip_add_data(&port->gc, port);
if (err)
goto out_irqdomain_remove;
return 0;
out_irqdomain_remove:
irq_domain_remove(port->domain);
out_iounmap:
iounmap(port->base);
return err;
}
static struct platform_driver mxs_gpio_driver = {
.driver = {
.name = "gpio-mxs",
.of_match_table = mxs_gpio_dt_ids,
.suppress_bind_attrs = true,
},
.probe = mxs_gpio_probe,
};
static int __init mxs_gpio_init(void)
{
return platform_driver_register(&mxs_gpio_driver);
}
postcore_initcall(mxs_gpio_init);
MODULE_AUTHOR("Freescale Semiconductor, "
"Daniel Mack <danielncaiaq.de>, "
"Juergen Beisert <[email protected]>");
MODULE_DESCRIPTION("Freescale MXS GPIO");
| linux-master | drivers/gpio/gpio-mxs.c |
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2016, 2017 Cavium Inc.
*/
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#define GPIO_RX_DAT 0x0
#define GPIO_TX_SET 0x8
#define GPIO_TX_CLR 0x10
#define GPIO_CONST 0x90
#define GPIO_CONST_GPIOS_MASK 0xff
#define GPIO_BIT_CFG 0x400
#define GPIO_BIT_CFG_TX_OE BIT(0)
#define GPIO_BIT_CFG_PIN_XOR BIT(1)
#define GPIO_BIT_CFG_INT_EN BIT(2)
#define GPIO_BIT_CFG_INT_TYPE BIT(3)
#define GPIO_BIT_CFG_FIL_MASK GENMASK(11, 4)
#define GPIO_BIT_CFG_FIL_CNT_SHIFT 4
#define GPIO_BIT_CFG_FIL_SEL_SHIFT 8
#define GPIO_BIT_CFG_TX_OD BIT(12)
#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16)
#define GPIO_INTR 0x800
#define GPIO_INTR_INTR BIT(0)
#define GPIO_INTR_INTR_W1S BIT(1)
#define GPIO_INTR_ENA_W1C BIT(2)
#define GPIO_INTR_ENA_W1S BIT(3)
#define GPIO_2ND_BANK 0x1400
#define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \
(9u << GPIO_BIT_CFG_FIL_CNT_SHIFT))
struct thunderx_gpio;
struct thunderx_line {
struct thunderx_gpio *txgpio;
unsigned int line;
unsigned int fil_bits;
};
struct thunderx_gpio {
struct gpio_chip chip;
u8 __iomem *register_base;
struct msix_entry *msix_entries; /* per line MSI-X */
struct thunderx_line *line_entries; /* per line irq info */
raw_spinlock_t lock;
unsigned long invert_mask[2];
unsigned long od_mask[2];
int base_msi;
};
static unsigned int bit_cfg_reg(unsigned int line)
{
return 8 * line + GPIO_BIT_CFG;
}
static unsigned int intr_reg(unsigned int line)
{
return 8 * line + GPIO_INTR;
}
static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio,
unsigned int line)
{
u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
}
/*
* Check (and WARN) that the pin is available for GPIO. We will not
* allow modification of the state of non-GPIO pins from this driver.
*/
static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio,
unsigned int line)
{
bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line);
WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line);
return rv;
}
static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line)
{
struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO;
}
static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line)
{
struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
if (!thunderx_gpio_is_gpio(txgpio, line))
return -EIO;
raw_spin_lock(&txgpio->lock);
clear_bit(line, txgpio->invert_mask);
clear_bit(line, txgpio->od_mask);
writeq(txgpio->line_entries[line].fil_bits,
txgpio->register_base + bit_cfg_reg(line));
raw_spin_unlock(&txgpio->lock);
return 0;
}
static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
int value)
{
struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
int bank = line / 64;
int bank_bit = line % 64;
void __iomem *reg = txgpio->register_base +
(bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);
writeq(BIT_ULL(bank_bit), reg);
}
static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line,
int value)
{
struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;
if (!thunderx_gpio_is_gpio(txgpio, line))
return -EIO;
raw_spin_lock(&txgpio->lock);
thunderx_gpio_set(chip, line, value);
if (test_bit(line, txgpio->invert_mask))
bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
if (test_bit(line, txgpio->od_mask))
bit_cfg |= GPIO_BIT_CFG_TX_OD;
writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
raw_spin_unlock(&txgpio->lock);
return 0;
}
static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line)
{
struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
u64 bit_cfg;
if (!thunderx_gpio_is_gpio_nowarn(txgpio, line))
/*
* Say it is input for now to avoid WARNing on
* gpiochip_add_data(). We will WARN if someone
* requests it or tries to use it.
*/
return 1;
bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
if (bit_cfg & GPIO_BIT_CFG_TX_OE)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int thunderx_gpio_set_config(struct gpio_chip *chip,
unsigned int line,
unsigned long cfg)
{
bool orig_invert, orig_od, orig_dat, new_invert, new_od;
u32 arg, sel;
u64 bit_cfg;
int bank = line / 64;
int bank_bit = line % 64;
int ret = -ENOTSUPP;
struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;
if (!thunderx_gpio_is_gpio(txgpio, line))
return -EIO;
raw_spin_lock(&txgpio->lock);
orig_invert = test_bit(line, txgpio->invert_mask);
new_invert = orig_invert;
orig_od = test_bit(line, txgpio->od_mask);
new_od = orig_od;
orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert;
bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
switch (pinconf_to_config_param(cfg)) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
/*
* Weird, setting open-drain mode causes signal
* inversion. Note this so we can compensate in the
* dir_out function.
*/
set_bit(line, txgpio->invert_mask);
new_invert = true;
set_bit(line, txgpio->od_mask);
new_od = true;
ret = 0;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
clear_bit(line, txgpio->invert_mask);
new_invert = false;
clear_bit(line, txgpio->od_mask);
new_od = false;
ret = 0;
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
arg = pinconf_to_config_argument(cfg);
if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */
ret = -EINVAL;
break;
}
arg *= 400; /* scale to 2.5nS clocks. */
sel = 0;
while (arg > 15) {
sel++;
arg++; /* always round up */
arg >>= 1;
}
txgpio->line_entries[line].fil_bits =
(sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) |
(arg << GPIO_BIT_CFG_FIL_CNT_SHIFT);
bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
bit_cfg |= txgpio->line_entries[line].fil_bits;
writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
ret = 0;
break;
default:
break;
}
raw_spin_unlock(&txgpio->lock);
/*
* If currently output and OPEN_DRAIN changed, install the new
* settings
*/
if ((new_invert != orig_invert || new_od != orig_od) &&
(bit_cfg & GPIO_BIT_CFG_TX_OE))
ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert);
return ret;
}
static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line)
{
struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
int bank = line / 64;
int bank_bit = line % 64;
u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
u64 masked_bits = read_bits & BIT_ULL(bank_bit);
if (test_bit(line, txgpio->invert_mask))
return masked_bits == 0;
else
return masked_bits != 0;
}
static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
unsigned long *mask,
unsigned long *bits)
{
int bank;
u64 set_bits, clear_bits;
struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
for (bank = 0; bank <= chip->ngpio / 64; bank++) {
set_bits = bits[bank] & mask[bank];
clear_bits = ~bits[bank] & mask[bank];
writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
}
}
static void thunderx_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
writeq(GPIO_INTR_INTR,
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
}
static void thunderx_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
writeq(GPIO_INTR_ENA_W1C,
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
}
static void thunderx_gpio_irq_mask_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
}
static void thunderx_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
writeq(GPIO_INTR_ENA_W1S,
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
}
static int thunderx_gpio_irq_set_type(struct irq_data *d,
unsigned int flow_type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
struct thunderx_line *txline =
&txgpio->line_entries[irqd_to_hwirq(d)];
u64 bit_cfg;
irqd_set_trigger_type(d, flow_type);
bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
if (flow_type & IRQ_TYPE_EDGE_BOTH) {
irq_set_handler_locked(d, handle_fasteoi_ack_irq);
bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
} else {
irq_set_handler_locked(d, handle_fasteoi_mask_irq);
}
raw_spin_lock(&txgpio->lock);
if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) {
bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
set_bit(txline->line, txgpio->invert_mask);
} else {
clear_bit(txline->line, txgpio->invert_mask);
}
clear_bit(txline->line, txgpio->od_mask);
writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
raw_spin_unlock(&txgpio->lock);
return IRQ_SET_MASK_OK;
}
static void thunderx_gpio_irq_enable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
irq_chip_enable_parent(d);
thunderx_gpio_irq_unmask(d);
}
static void thunderx_gpio_irq_disable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
thunderx_gpio_irq_mask(d);
irq_chip_disable_parent(d);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
/*
* Interrupts are chained from underlying MSI-X vectors. We have
* these irq_chip functions to be able to handle level triggering
* semantics and other acknowledgment tasks associated with the GPIO
* mechanism.
*/
static const struct irq_chip thunderx_gpio_irq_chip = {
.name = "GPIO",
.irq_enable = thunderx_gpio_irq_enable,
.irq_disable = thunderx_gpio_irq_disable,
.irq_ack = thunderx_gpio_irq_ack,
.irq_mask = thunderx_gpio_irq_mask,
.irq_mask_ack = thunderx_gpio_irq_mask_ack,
.irq_unmask = thunderx_gpio_irq_unmask,
.irq_eoi = irq_chip_eoi_parent,
.irq_set_affinity = irq_chip_set_affinity_parent,
.irq_set_type = thunderx_gpio_irq_set_type,
.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
unsigned int child,
unsigned int child_type,
unsigned int *parent,
unsigned int *parent_type)
{
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
struct irq_data *irqd;
unsigned int irq;
irq = txgpio->msix_entries[child].vector;
irqd = irq_domain_get_irq_data(gc->irq.parent_domain, irq);
if (!irqd)
return -EINVAL;
*parent = irqd_to_hwirq(irqd);
*parent_type = IRQ_TYPE_LEVEL_HIGH;
return 0;
}
static int thunderx_gpio_populate_parent_alloc_info(struct gpio_chip *chip,
union gpio_irq_fwspec *gfwspec,
unsigned int parent_hwirq,
unsigned int parent_type)
{
msi_alloc_info_t *info = &gfwspec->msiinfo;
info->hwirq = parent_hwirq;
return 0;
}
static int thunderx_gpio_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
void __iomem * const *tbl;
struct device *dev = &pdev->dev;
struct thunderx_gpio *txgpio;
struct gpio_chip *chip;
struct gpio_irq_chip *girq;
int ngpio, i;
int err = 0;
txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL);
if (!txgpio)
return -ENOMEM;
raw_spin_lock_init(&txgpio->lock);
chip = &txgpio->chip;
pci_set_drvdata(pdev, txgpio);
err = pcim_enable_device(pdev);
if (err) {
dev_err(dev, "Failed to enable PCI device: err %d\n", err);
goto out;
}
err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME);
if (err) {
dev_err(dev, "Failed to iomap PCI device: err %d\n", err);
goto out;
}
tbl = pcim_iomap_table(pdev);
txgpio->register_base = tbl[0];
if (!txgpio->register_base) {
dev_err(dev, "Cannot map PCI resource\n");
err = -ENOMEM;
goto out;
}
if (pdev->subsystem_device == 0xa10a) {
/* CN88XX has no GPIO_CONST register*/
ngpio = 50;
txgpio->base_msi = 48;
} else {
u64 c = readq(txgpio->register_base + GPIO_CONST);
ngpio = c & GPIO_CONST_GPIOS_MASK;
txgpio->base_msi = (c >> 8) & 0xff;
}
txgpio->msix_entries = devm_kcalloc(dev,
ngpio, sizeof(struct msix_entry),
GFP_KERNEL);
if (!txgpio->msix_entries) {
err = -ENOMEM;
goto out;
}
txgpio->line_entries = devm_kcalloc(dev,
ngpio,
sizeof(struct thunderx_line),
GFP_KERNEL);
if (!txgpio->line_entries) {
err = -ENOMEM;
goto out;
}
for (i = 0; i < ngpio; i++) {
u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i);
txgpio->line_entries[i].line = i;
txgpio->line_entries[i].txgpio = txgpio;
/*
* If something has already programmed the pin, use
* the existing glitch filter settings, otherwise go
* to 400nS.
*/
txgpio->line_entries[i].fil_bits = bit_cfg ?
(bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;
if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
set_bit(i, txgpio->od_mask);
if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)
set_bit(i, txgpio->invert_mask);
}
/* Enable all MSI-X for interrupts on all possible lines. */
err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio);
if (err < 0)
goto out;
chip->label = KBUILD_MODNAME;
chip->parent = dev;
chip->owner = THIS_MODULE;
chip->request = thunderx_gpio_request;
chip->base = -1; /* System allocated */
chip->can_sleep = false;
chip->ngpio = ngpio;
chip->get_direction = thunderx_gpio_get_direction;
chip->direction_input = thunderx_gpio_dir_in;
chip->get = thunderx_gpio_get;
chip->direction_output = thunderx_gpio_dir_out;
chip->set = thunderx_gpio_set;
chip->set_multiple = thunderx_gpio_set_multiple;
chip->set_config = thunderx_gpio_set_config;
girq = &chip->irq;
gpio_irq_chip_set_chip(girq, &thunderx_gpio_irq_chip);
girq->fwnode = of_node_to_fwnode(dev->of_node);
girq->parent_domain =
irq_get_irq_data(txgpio->msix_entries[0].vector)->domain;
girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq;
girq->populate_parent_alloc_arg = thunderx_gpio_populate_parent_alloc_info;
girq->handler = handle_bad_irq;
girq->default_type = IRQ_TYPE_NONE;
err = devm_gpiochip_add_data(dev, chip, txgpio);
if (err)
goto out;
/* Push on irq_data and the domain for each line. */
for (i = 0; i < ngpio; i++) {
struct irq_fwspec fwspec;
fwspec.fwnode = of_node_to_fwnode(dev->of_node);
fwspec.param_count = 2;
fwspec.param[0] = i;
fwspec.param[1] = IRQ_TYPE_NONE;
err = irq_domain_push_irq(girq->domain,
txgpio->msix_entries[i].vector,
&fwspec);
if (err < 0)
dev_err(dev, "irq_domain_push_irq: %d\n", err);
}
dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
ngpio, chip->base);
return 0;
out:
pci_set_drvdata(pdev, NULL);
return err;
}
static void thunderx_gpio_remove(struct pci_dev *pdev)
{
int i;
struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
for (i = 0; i < txgpio->chip.ngpio; i++)
irq_domain_pop_irq(txgpio->chip.irq.domain,
txgpio->msix_entries[i].vector);
irq_domain_remove(txgpio->chip.irq.domain);
pci_set_drvdata(pdev, NULL);
}
static const struct pci_device_id thunderx_gpio_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) },
{ 0, } /* end of table */
};
MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table);
static struct pci_driver thunderx_gpio_driver = {
.name = KBUILD_MODNAME,
.id_table = thunderx_gpio_id_table,
.probe = thunderx_gpio_probe,
.remove = thunderx_gpio_remove,
};
module_pci_driver(thunderx_gpio_driver);
MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-thunderx.c |
// SPDX-License-Identifier: GPL-2.0
/*
* GPIO driver for AMD 8111 south bridges
*
* Copyright (c) 2012 Dmitry Eremin-Solenikov
*
* Based on the AMD RNG driver:
* Copyright 2005 (c) MontaVista Software, Inc.
* with the majority of the code coming from:
*
* Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
* (c) Copyright 2003 Red Hat Inc <[email protected]>
*
* derived from
*
* Hardware driver for the AMD 768 Random Number Generator (RNG)
* (c) Copyright 2001 Red Hat Inc
*
* derived from
*
* Hardware driver for Intel i810 Random Number Generator (RNG)
* Copyright 2000,2001 Jeff Garzik <[email protected]>
* Copyright 2000,2001 Philipp Rumpf <[email protected]>
*/
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/gpio/driver.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#define PMBASE_OFFSET 0xb0
#define PMBASE_SIZE 0x30
#define AMD_REG_GPIO(i) (0x10 + (i))
#define AMD_GPIO_LTCH_STS 0x40 /* Latch status, w1 */
#define AMD_GPIO_RTIN 0x20 /* Real Time in, ro */
#define AMD_GPIO_DEBOUNCE 0x10 /* Debounce, rw */
#define AMD_GPIO_MODE_MASK 0x0c /* Pin Mode Select, rw */
#define AMD_GPIO_MODE_IN 0x00
#define AMD_GPIO_MODE_OUT 0x04
/* Enable alternative (e.g. clkout, IRQ, etc) function of the pin */
#define AMD_GPIO_MODE_ALTFN 0x08 /* Or 0x09 */
#define AMD_GPIO_X_MASK 0x03 /* In/Out specific, rw */
#define AMD_GPIO_X_IN_ACTIVEHI 0x01 /* Active High */
#define AMD_GPIO_X_IN_LATCH 0x02 /* Latched version is selected */
#define AMD_GPIO_X_OUT_LOW 0x00
#define AMD_GPIO_X_OUT_HI 0x01
#define AMD_GPIO_X_OUT_CLK0 0x02
#define AMD_GPIO_X_OUT_CLK1 0x03
/*
* Data for PCI driver interface
*
* This data only exists for exporting the supported
* PCI ids via MODULE_DEVICE_TABLE. We do not actually
* register a pci_driver, because someone else might one day
* want to register another driver on the same PCI id.
*/
static const struct pci_device_id pci_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS), 0 },
{ 0, }, /* terminate list */
};
MODULE_DEVICE_TABLE(pci, pci_tbl);
struct amd_gpio {
struct gpio_chip chip;
u32 pmbase;
void __iomem *pm;
struct pci_dev *pdev;
spinlock_t lock; /* guards hw registers and orig table */
u8 orig[32];
};
static int amd_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) &
(AMD_GPIO_DEBOUNCE | AMD_GPIO_MODE_MASK | AMD_GPIO_X_MASK);
dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]);
return 0;
}
static void amd_gpio_free(struct gpio_chip *chip, unsigned offset)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]);
iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset));
}
static void amd_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
u8 temp;
unsigned long flags;
spin_lock_irqsave(&agp->lock, flags);
temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
spin_unlock_irqrestore(&agp->lock, flags);
dev_dbg(&agp->pdev->dev, "Setting gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
}
static int amd_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
u8 temp;
temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
dev_dbg(&agp->pdev->dev, "Getting gpio %d, reg=%02x\n", offset, temp);
return (temp & AMD_GPIO_RTIN) ? 1 : 0;
}
static int amd_gpio_dirout(struct gpio_chip *chip, unsigned offset, int value)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
u8 temp;
unsigned long flags;
spin_lock_irqsave(&agp->lock, flags);
temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
spin_unlock_irqrestore(&agp->lock, flags);
dev_dbg(&agp->pdev->dev, "Dirout gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
return 0;
}
static int amd_gpio_dirin(struct gpio_chip *chip, unsigned offset)
{
struct amd_gpio *agp = gpiochip_get_data(chip);
u8 temp;
unsigned long flags;
spin_lock_irqsave(&agp->lock, flags);
temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_IN;
iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
spin_unlock_irqrestore(&agp->lock, flags);
dev_dbg(&agp->pdev->dev, "Dirin gpio %d, reg=%02x\n", offset, temp);
return 0;
}
static struct amd_gpio gp = {
.chip = {
.label = "AMD GPIO",
.owner = THIS_MODULE,
.base = -1,
.ngpio = 32,
.request = amd_gpio_request,
.free = amd_gpio_free,
.set = amd_gpio_set,
.get = amd_gpio_get,
.direction_output = amd_gpio_dirout,
.direction_input = amd_gpio_dirin,
},
};
static int __init amd_gpio_init(void)
{
int err = -ENODEV;
struct pci_dev *pdev = NULL;
const struct pci_device_id *ent;
/* We look for our device - AMD South Bridge
* I don't know about a system with two such bridges,
* so we can assume that there is max. one device.
*
* We can't use plain pci_driver mechanism,
* as the device is really a multiple function device,
* main driver that binds to the pci_device is an smbus
* driver and have to find & bind to the device this way.
*/
for_each_pci_dev(pdev) {
ent = pci_match_id(pci_tbl, pdev);
if (ent)
goto found;
}
/* Device not found. */
goto out;
found:
err = pci_read_config_dword(pdev, 0x58, &gp.pmbase);
if (err)
goto out;
err = -EIO;
gp.pmbase &= 0x0000FF00;
if (gp.pmbase == 0)
goto out;
if (!devm_request_region(&pdev->dev, gp.pmbase + PMBASE_OFFSET,
PMBASE_SIZE, "AMD GPIO")) {
dev_err(&pdev->dev, "AMD GPIO region 0x%x already in use!\n",
gp.pmbase + PMBASE_OFFSET);
err = -EBUSY;
goto out;
}
gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
if (!gp.pm) {
dev_err(&pdev->dev, "Couldn't map io port into io memory\n");
err = -ENOMEM;
goto out;
}
gp.pdev = pdev;
gp.chip.parent = &pdev->dev;
spin_lock_init(&gp.lock);
dev_info(&pdev->dev, "AMD-8111 GPIO detected\n");
err = gpiochip_add_data(&gp.chip, &gp);
if (err) {
dev_err(&pdev->dev, "GPIO registering failed (%d)\n", err);
ioport_unmap(gp.pm);
goto out;
}
return 0;
out:
pci_dev_put(pdev);
return err;
}
static void __exit amd_gpio_exit(void)
{
gpiochip_remove(&gp.chip);
ioport_unmap(gp.pm);
pci_dev_put(gp.pdev);
}
module_init(amd_gpio_init);
module_exit(amd_gpio_exit);
MODULE_AUTHOR("The Linux Kernel team");
MODULE_DESCRIPTION("GPIO driver for AMD chipsets");
MODULE_LICENSE("GPL");
| linux-master | drivers/gpio/gpio-amd8111.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Janz MODULbus VMOD-TTL GPIO Driver
*
* Copyright (c) 2010 Ira W. Snyder <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/mfd/janz.h>
#define DRV_NAME "janz-ttl"
#define PORTA_DIRECTION 0x23
#define PORTB_DIRECTION 0x2B
#define PORTC_DIRECTION 0x06
#define PORTA_IOCTL 0x24
#define PORTB_IOCTL 0x2C
#define PORTC_IOCTL 0x07
#define MASTER_INT_CTL 0x00
#define MASTER_CONF_CTL 0x01
#define CONF_PAE BIT(2)
#define CONF_PBE BIT(7)
#define CONF_PCE BIT(4)
struct ttl_control_regs {
__be16 portc;
__be16 portb;
__be16 porta;
__be16 control;
};
struct ttl_module {
struct gpio_chip gpio;
/* base address of registers */
struct ttl_control_regs __iomem *regs;
u8 portc_shadow;
u8 portb_shadow;
u8 porta_shadow;
spinlock_t lock;
};
static int ttl_get_value(struct gpio_chip *gpio, unsigned offset)
{
struct ttl_module *mod = dev_get_drvdata(gpio->parent);
u8 *shadow;
int ret;
if (offset < 8) {
shadow = &mod->porta_shadow;
} else if (offset < 16) {
shadow = &mod->portb_shadow;
offset -= 8;
} else {
shadow = &mod->portc_shadow;
offset -= 16;
}
spin_lock(&mod->lock);
ret = *shadow & BIT(offset);
spin_unlock(&mod->lock);
return !!ret;
}
static void ttl_set_value(struct gpio_chip *gpio, unsigned offset, int value)
{
struct ttl_module *mod = dev_get_drvdata(gpio->parent);
void __iomem *port;
u8 *shadow;
if (offset < 8) {
port = &mod->regs->porta;
shadow = &mod->porta_shadow;
} else if (offset < 16) {
port = &mod->regs->portb;
shadow = &mod->portb_shadow;
offset -= 8;
} else {
port = &mod->regs->portc;
shadow = &mod->portc_shadow;
offset -= 16;
}
spin_lock(&mod->lock);
if (value)
*shadow |= BIT(offset);
else
*shadow &= ~BIT(offset);
iowrite16be(*shadow, port);
spin_unlock(&mod->lock);
}
static void ttl_write_reg(struct ttl_module *mod, u8 reg, u16 val)
{
iowrite16be(reg, &mod->regs->control);
iowrite16be(val, &mod->regs->control);
}
static void ttl_setup_device(struct ttl_module *mod)
{
/* reset the device to a known state */
iowrite16be(0x0000, &mod->regs->control);
iowrite16be(0x0001, &mod->regs->control);
iowrite16be(0x0000, &mod->regs->control);
/* put all ports in open-drain mode */
ttl_write_reg(mod, PORTA_IOCTL, 0x00ff);
ttl_write_reg(mod, PORTB_IOCTL, 0x00ff);
ttl_write_reg(mod, PORTC_IOCTL, 0x000f);
/* set all ports as outputs */
ttl_write_reg(mod, PORTA_DIRECTION, 0x0000);
ttl_write_reg(mod, PORTB_DIRECTION, 0x0000);
ttl_write_reg(mod, PORTC_DIRECTION, 0x0000);
/* set all ports to drive zeroes */
iowrite16be(0x0000, &mod->regs->porta);
iowrite16be(0x0000, &mod->regs->portb);
iowrite16be(0x0000, &mod->regs->portc);
/* enable all ports */
ttl_write_reg(mod, MASTER_CONF_CTL, CONF_PAE | CONF_PBE | CONF_PCE);
}
static int ttl_probe(struct platform_device *pdev)
{
struct janz_platform_data *pdata;
struct ttl_module *mod;
struct gpio_chip *gpio;
int ret;
pdata = dev_get_platdata(&pdev->dev);
if (!pdata) {
dev_err(&pdev->dev, "no platform data\n");
return -ENXIO;
}
mod = devm_kzalloc(&pdev->dev, sizeof(*mod), GFP_KERNEL);
if (!mod)
return -ENOMEM;
platform_set_drvdata(pdev, mod);
spin_lock_init(&mod->lock);
/* get access to the MODULbus registers for this module */
mod->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(mod->regs))
return PTR_ERR(mod->regs);
ttl_setup_device(mod);
/* Initialize the GPIO data structures */
gpio = &mod->gpio;
gpio->parent = &pdev->dev;
gpio->label = pdev->name;
gpio->get = ttl_get_value;
gpio->set = ttl_set_value;
gpio->owner = THIS_MODULE;
/* request dynamic allocation */
gpio->base = -1;
gpio->ngpio = 20;
ret = devm_gpiochip_add_data(&pdev->dev, gpio, NULL);
if (ret) {
dev_err(&pdev->dev, "unable to add GPIO chip\n");
return ret;
}
return 0;
}
static struct platform_driver ttl_driver = {
.driver = {
.name = DRV_NAME,
},
.probe = ttl_probe,
};
module_platform_driver(ttl_driver);
MODULE_AUTHOR("Ira W. Snyder <[email protected]>");
MODULE_DESCRIPTION("Janz MODULbus VMOD-TTL Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:janz-ttl");
| linux-master | drivers/gpio/gpio-janz-ttl.c |
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