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// SPDX-License-Identifier: GPL-2.0-only
/*
* HID Sensors Driver
* Copyright (c) 2012, Intel Corporation.
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/slab.h>
#include <linux/hid-sensor-hub.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include "../common/hid-sensors/hid-sensor-trigger.h"
enum {
CHANNEL_SCAN_INDEX_INTENSITY = 0,
CHANNEL_SCAN_INDEX_ILLUM = 1,
CHANNEL_SCAN_INDEX_MAX
};
#define CHANNEL_SCAN_INDEX_TIMESTAMP CHANNEL_SCAN_INDEX_MAX
struct als_state {
struct hid_sensor_hub_callbacks callbacks;
struct hid_sensor_common common_attributes;
struct hid_sensor_hub_attribute_info als_illum;
struct {
u32 illum[CHANNEL_SCAN_INDEX_MAX];
u64 timestamp __aligned(8);
} scan;
int scale_pre_decml;
int scale_post_decml;
int scale_precision;
int value_offset;
s64 timestamp;
};
static const u32 als_sensitivity_addresses[] = {
HID_USAGE_SENSOR_DATA_LIGHT,
HID_USAGE_SENSOR_LIGHT_ILLUM,
};
/* Channel definitions */
static const struct iio_chan_spec als_channels[] = {
{
.type = IIO_INTENSITY,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_BOTH,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_SAMP_FREQ) |
BIT(IIO_CHAN_INFO_HYSTERESIS) |
BIT(IIO_CHAN_INFO_HYSTERESIS_RELATIVE),
.scan_index = CHANNEL_SCAN_INDEX_INTENSITY,
},
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_SAMP_FREQ) |
BIT(IIO_CHAN_INFO_HYSTERESIS) |
BIT(IIO_CHAN_INFO_HYSTERESIS_RELATIVE),
.scan_index = CHANNEL_SCAN_INDEX_ILLUM,
},
IIO_CHAN_SOFT_TIMESTAMP(CHANNEL_SCAN_INDEX_TIMESTAMP)
};
/* Adjust channel real bits based on report descriptor */
static void als_adjust_channel_bit_mask(struct iio_chan_spec *channels,
int channel, int size)
{
channels[channel].scan_type.sign = 's';
/* Real storage bits will change based on the report desc. */
channels[channel].scan_type.realbits = size * 8;
/* Maximum size of a sample to capture is u32 */
channels[channel].scan_type.storagebits = sizeof(u32) * 8;
}
/* Channel read_raw handler */
static int als_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2,
long mask)
{
struct als_state *als_state = iio_priv(indio_dev);
struct hid_sensor_hub_device *hsdev = als_state->common_attributes.hsdev;
int report_id = -1;
u32 address;
int ret_type;
s32 min;
*val = 0;
*val2 = 0;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->scan_index) {
case CHANNEL_SCAN_INDEX_INTENSITY:
case CHANNEL_SCAN_INDEX_ILLUM:
report_id = als_state->als_illum.report_id;
min = als_state->als_illum.logical_minimum;
address = HID_USAGE_SENSOR_LIGHT_ILLUM;
break;
default:
report_id = -1;
break;
}
if (report_id >= 0) {
hid_sensor_power_state(&als_state->common_attributes,
true);
*val = sensor_hub_input_attr_get_raw_value(
hsdev, hsdev->usage, address, report_id,
SENSOR_HUB_SYNC, min < 0);
hid_sensor_power_state(&als_state->common_attributes,
false);
} else {
*val = 0;
return -EINVAL;
}
ret_type = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SCALE:
*val = als_state->scale_pre_decml;
*val2 = als_state->scale_post_decml;
ret_type = als_state->scale_precision;
break;
case IIO_CHAN_INFO_OFFSET:
*val = als_state->value_offset;
ret_type = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SAMP_FREQ:
ret_type = hid_sensor_read_samp_freq_value(
&als_state->common_attributes, val, val2);
break;
case IIO_CHAN_INFO_HYSTERESIS:
ret_type = hid_sensor_read_raw_hyst_value(
&als_state->common_attributes, val, val2);
break;
case IIO_CHAN_INFO_HYSTERESIS_RELATIVE:
ret_type = hid_sensor_read_raw_hyst_rel_value(
&als_state->common_attributes, val, val2);
break;
default:
ret_type = -EINVAL;
break;
}
return ret_type;
}
/* Channel write_raw handler */
static int als_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct als_state *als_state = iio_priv(indio_dev);
int ret = 0;
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
ret = hid_sensor_write_samp_freq_value(
&als_state->common_attributes, val, val2);
break;
case IIO_CHAN_INFO_HYSTERESIS:
ret = hid_sensor_write_raw_hyst_value(
&als_state->common_attributes, val, val2);
break;
case IIO_CHAN_INFO_HYSTERESIS_RELATIVE:
ret = hid_sensor_write_raw_hyst_rel_value(
&als_state->common_attributes, val, val2);
break;
default:
ret = -EINVAL;
}
return ret;
}
static const struct iio_info als_info = {
.read_raw = &als_read_raw,
.write_raw = &als_write_raw,
};
/* Callback handler to send event after all samples are received and captured */
static int als_proc_event(struct hid_sensor_hub_device *hsdev,
unsigned usage_id,
void *priv)
{
struct iio_dev *indio_dev = platform_get_drvdata(priv);
struct als_state *als_state = iio_priv(indio_dev);
dev_dbg(&indio_dev->dev, "als_proc_event\n");
if (atomic_read(&als_state->common_attributes.data_ready)) {
if (!als_state->timestamp)
als_state->timestamp = iio_get_time_ns(indio_dev);
iio_push_to_buffers_with_timestamp(indio_dev, &als_state->scan,
als_state->timestamp);
als_state->timestamp = 0;
}
return 0;
}
/* Capture samples in local storage */
static int als_capture_sample(struct hid_sensor_hub_device *hsdev,
unsigned usage_id,
size_t raw_len, char *raw_data,
void *priv)
{
struct iio_dev *indio_dev = platform_get_drvdata(priv);
struct als_state *als_state = iio_priv(indio_dev);
int ret = -EINVAL;
u32 sample_data = *(u32 *)raw_data;
switch (usage_id) {
case HID_USAGE_SENSOR_LIGHT_ILLUM:
als_state->scan.illum[CHANNEL_SCAN_INDEX_INTENSITY] = sample_data;
als_state->scan.illum[CHANNEL_SCAN_INDEX_ILLUM] = sample_data;
ret = 0;
break;
case HID_USAGE_SENSOR_TIME_TIMESTAMP:
als_state->timestamp = hid_sensor_convert_timestamp(&als_state->common_attributes,
*(s64 *)raw_data);
break;
default:
break;
}
return ret;
}
/* Parse report which is specific to an usage id*/
static int als_parse_report(struct platform_device *pdev,
struct hid_sensor_hub_device *hsdev,
struct iio_chan_spec *channels,
unsigned usage_id,
struct als_state *st)
{
int ret;
ret = sensor_hub_input_get_attribute_info(hsdev, HID_INPUT_REPORT,
usage_id,
HID_USAGE_SENSOR_LIGHT_ILLUM,
&st->als_illum);
if (ret < 0)
return ret;
als_adjust_channel_bit_mask(channels, CHANNEL_SCAN_INDEX_INTENSITY,
st->als_illum.size);
als_adjust_channel_bit_mask(channels, CHANNEL_SCAN_INDEX_ILLUM,
st->als_illum.size);
dev_dbg(&pdev->dev, "als %x:%x\n", st->als_illum.index,
st->als_illum.report_id);
st->scale_precision = hid_sensor_format_scale(usage_id, &st->als_illum,
&st->scale_pre_decml, &st->scale_post_decml);
return ret;
}
/* Function to initialize the processing for usage id */
static int hid_als_probe(struct platform_device *pdev)
{
int ret = 0;
static const char *name = "als";
struct iio_dev *indio_dev;
struct als_state *als_state;
struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct als_state));
if (!indio_dev)
return -ENOMEM;
platform_set_drvdata(pdev, indio_dev);
als_state = iio_priv(indio_dev);
als_state->common_attributes.hsdev = hsdev;
als_state->common_attributes.pdev = pdev;
ret = hid_sensor_parse_common_attributes(hsdev,
hsdev->usage,
&als_state->common_attributes,
als_sensitivity_addresses,
ARRAY_SIZE(als_sensitivity_addresses));
if (ret) {
dev_err(&pdev->dev, "failed to setup common attributes\n");
return ret;
}
indio_dev->channels = devm_kmemdup(&pdev->dev, als_channels,
sizeof(als_channels), GFP_KERNEL);
if (!indio_dev->channels) {
dev_err(&pdev->dev, "failed to duplicate channels\n");
return -ENOMEM;
}
ret = als_parse_report(pdev, hsdev,
(struct iio_chan_spec *)indio_dev->channels,
hsdev->usage,
als_state);
if (ret) {
dev_err(&pdev->dev, "failed to setup attributes\n");
return ret;
}
indio_dev->num_channels =
ARRAY_SIZE(als_channels);
indio_dev->info = &als_info;
indio_dev->name = name;
indio_dev->modes = INDIO_DIRECT_MODE;
atomic_set(&als_state->common_attributes.data_ready, 0);
ret = hid_sensor_setup_trigger(indio_dev, name,
&als_state->common_attributes);
if (ret < 0) {
dev_err(&pdev->dev, "trigger setup failed\n");
return ret;
}
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&pdev->dev, "device register failed\n");
goto error_remove_trigger;
}
als_state->callbacks.send_event = als_proc_event;
als_state->callbacks.capture_sample = als_capture_sample;
als_state->callbacks.pdev = pdev;
ret = sensor_hub_register_callback(hsdev, hsdev->usage, &als_state->callbacks);
if (ret < 0) {
dev_err(&pdev->dev, "callback reg failed\n");
goto error_iio_unreg;
}
return ret;
error_iio_unreg:
iio_device_unregister(indio_dev);
error_remove_trigger:
hid_sensor_remove_trigger(indio_dev, &als_state->common_attributes);
return ret;
}
/* Function to deinitialize the processing for usage id */
static int hid_als_remove(struct platform_device *pdev)
{
struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data;
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct als_state *als_state = iio_priv(indio_dev);
sensor_hub_remove_callback(hsdev, hsdev->usage);
iio_device_unregister(indio_dev);
hid_sensor_remove_trigger(indio_dev, &als_state->common_attributes);
return 0;
}
static const struct platform_device_id hid_als_ids[] = {
{
/* Format: HID-SENSOR-usage_id_in_hex_lowercase */
.name = "HID-SENSOR-200041",
},
{
/* Format: HID-SENSOR-custom_sensor_tag-usage_id_in_hex_lowercase */
.name = "HID-SENSOR-LISS-0041",
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, hid_als_ids);
static struct platform_driver hid_als_platform_driver = {
.id_table = hid_als_ids,
.driver = {
.name = KBUILD_MODNAME,
.pm = &hid_sensor_pm_ops,
},
.probe = hid_als_probe,
.remove = hid_als_remove,
};
module_platform_driver(hid_als_platform_driver);
MODULE_DESCRIPTION("HID Sensor ALS");
MODULE_AUTHOR("Srinivas Pandruvada <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(IIO_HID);
| linux-master | drivers/iio/light/hid-sensor-als.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* BU27034 ROHM Ambient Light Sensor
*
* Copyright (c) 2023, ROHM Semiconductor.
* https://fscdn.rohm.com/en/products/databook/datasheet/ic/sensor/light/bu27034nuc-e.pdf
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/units.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/iio-gts-helper.h>
#include <linux/iio/kfifo_buf.h>
#define BU27034_REG_SYSTEM_CONTROL 0x40
#define BU27034_MASK_SW_RESET BIT(7)
#define BU27034_MASK_PART_ID GENMASK(5, 0)
#define BU27034_ID 0x19
#define BU27034_REG_MODE_CONTROL1 0x41
#define BU27034_MASK_MEAS_MODE GENMASK(2, 0)
#define BU27034_REG_MODE_CONTROL2 0x42
#define BU27034_MASK_D01_GAIN GENMASK(7, 3)
#define BU27034_MASK_D2_GAIN_HI GENMASK(7, 6)
#define BU27034_MASK_D2_GAIN_LO GENMASK(2, 0)
#define BU27034_REG_MODE_CONTROL3 0x43
#define BU27034_REG_MODE_CONTROL4 0x44
#define BU27034_MASK_MEAS_EN BIT(0)
#define BU27034_MASK_VALID BIT(7)
#define BU27034_REG_DATA0_LO 0x50
#define BU27034_REG_DATA1_LO 0x52
#define BU27034_REG_DATA2_LO 0x54
#define BU27034_REG_DATA2_HI 0x55
#define BU27034_REG_MANUFACTURER_ID 0x92
#define BU27034_REG_MAX BU27034_REG_MANUFACTURER_ID
/*
* The BU27034 does not have interrupt to trigger the data read when a
* measurement has finished. Hence we poll the VALID bit in a thread. We will
* try to wake the thread BU27034_MEAS_WAIT_PREMATURE_MS milliseconds before
* the expected sampling time to prevent the drifting.
*
* If we constantly wake up a bit too late we would eventually skip a sample.
* And because the sleep can't wake up _exactly_ at given time this would be
* inevitable even if the sensor clock would be perfectly phase-locked to CPU
* clock - which we can't say is the case.
*
* This is still fragile. No matter how big advance do we have, we will still
* risk of losing a sample because things can in a rainy-day scenario be
* delayed a lot. Yet, more we reserve the time for polling, more we also lose
* the performance by spending cycles polling the register. So, selecting this
* value is a balancing dance between severity of wasting CPU time and severity
* of losing samples.
*
* In most cases losing the samples is not _that_ crucial because light levels
* tend to change slowly.
*
* Other option that was pointed to me would be always sleeping 1/2 of the
* measurement time, checking the VALID bit and just sleeping again if the bit
* was not set. That should be pretty tolerant against missing samples due to
* the scheduling delays while also not wasting much of cycles for polling.
* Downside is that the time-stamps would be very inaccurate as the wake-up
* would not really be tied to the sensor toggling the valid bit. This would also
* result 'jumps' in the time-stamps when the delay drifted so that wake-up was
* performed during the consecutive wake-ups (Or, when sensor and CPU clocks
* were very different and scheduling the wake-ups was very close to given
* timeout - and when the time-outs were very close to the actual sensor
* sampling, Eg. once in a blue moon, two consecutive time-outs would occur
* without having a sample ready).
*/
#define BU27034_MEAS_WAIT_PREMATURE_MS 5
#define BU27034_DATA_WAIT_TIME_US 1000
#define BU27034_TOTAL_DATA_WAIT_TIME_US (BU27034_MEAS_WAIT_PREMATURE_MS * 1000)
#define BU27034_RETRY_LIMIT 18
enum {
BU27034_CHAN_ALS,
BU27034_CHAN_DATA0,
BU27034_CHAN_DATA1,
BU27034_CHAN_DATA2,
BU27034_NUM_CHANS
};
static const unsigned long bu27034_scan_masks[] = {
GENMASK(BU27034_CHAN_DATA2, BU27034_CHAN_ALS), 0
};
/*
* Available scales with gain 1x - 4096x, timings 55, 100, 200, 400 mS
* Time impacts to gain: 1x, 2x, 4x, 8x.
*
* => Max total gain is HWGAIN * gain by integration time (8 * 4096) = 32768
*
* Using NANO precision for scale we must use scale 64x corresponding gain 1x
* to avoid precision loss. (32x would result scale 976 562.5(nanos).
*/
#define BU27034_SCALE_1X 64
/* See the data sheet for the "Gain Setting" table */
#define BU27034_GSEL_1X 0x00 /* 00000 */
#define BU27034_GSEL_4X 0x08 /* 01000 */
#define BU27034_GSEL_16X 0x0a /* 01010 */
#define BU27034_GSEL_32X 0x0b /* 01011 */
#define BU27034_GSEL_64X 0x0c /* 01100 */
#define BU27034_GSEL_256X 0x18 /* 11000 */
#define BU27034_GSEL_512X 0x19 /* 11001 */
#define BU27034_GSEL_1024X 0x1a /* 11010 */
#define BU27034_GSEL_2048X 0x1b /* 11011 */
#define BU27034_GSEL_4096X 0x1c /* 11100 */
/* Available gain settings */
static const struct iio_gain_sel_pair bu27034_gains[] = {
GAIN_SCALE_GAIN(1, BU27034_GSEL_1X),
GAIN_SCALE_GAIN(4, BU27034_GSEL_4X),
GAIN_SCALE_GAIN(16, BU27034_GSEL_16X),
GAIN_SCALE_GAIN(32, BU27034_GSEL_32X),
GAIN_SCALE_GAIN(64, BU27034_GSEL_64X),
GAIN_SCALE_GAIN(256, BU27034_GSEL_256X),
GAIN_SCALE_GAIN(512, BU27034_GSEL_512X),
GAIN_SCALE_GAIN(1024, BU27034_GSEL_1024X),
GAIN_SCALE_GAIN(2048, BU27034_GSEL_2048X),
GAIN_SCALE_GAIN(4096, BU27034_GSEL_4096X),
};
/*
* The IC has 5 modes for sampling time. 5 mS mode is exceptional as it limits
* the data collection to data0-channel only and cuts the supported range to
* 10 bit. It is not supported by the driver.
*
* "normal" modes are 55, 100, 200 and 400 mS modes - which do have direct
* multiplying impact to the register values (similar to gain).
*
* This means that if meas-mode is changed for example from 400 => 200,
* the scale is doubled. Eg, time impact to total gain is x1, x2, x4, x8.
*/
#define BU27034_MEAS_MODE_100MS 0
#define BU27034_MEAS_MODE_55MS 1
#define BU27034_MEAS_MODE_200MS 2
#define BU27034_MEAS_MODE_400MS 4
static const struct iio_itime_sel_mul bu27034_itimes[] = {
GAIN_SCALE_ITIME_US(400000, BU27034_MEAS_MODE_400MS, 8),
GAIN_SCALE_ITIME_US(200000, BU27034_MEAS_MODE_200MS, 4),
GAIN_SCALE_ITIME_US(100000, BU27034_MEAS_MODE_100MS, 2),
GAIN_SCALE_ITIME_US(55000, BU27034_MEAS_MODE_55MS, 1),
};
#define BU27034_CHAN_DATA(_name, _ch2) \
{ \
.type = IIO_INTENSITY, \
.channel = BU27034_CHAN_##_name, \
.channel2 = (_ch2), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME), \
.info_mask_shared_by_all_available = \
BIT(IIO_CHAN_INFO_INT_TIME), \
.address = BU27034_REG_##_name##_LO, \
.scan_index = BU27034_CHAN_##_name, \
.scan_type = { \
.sign = 'u', \
.realbits = 16, \
.storagebits = 16, \
.endianness = IIO_LE, \
}, \
.indexed = 1, \
}
static const struct iio_chan_spec bu27034_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.channel = BU27034_CHAN_ALS,
.scan_index = BU27034_CHAN_ALS,
.scan_type = {
.sign = 'u',
.realbits = 32,
.storagebits = 32,
.endianness = IIO_CPU,
},
},
/*
* The BU27034 DATA0 and DATA1 channels are both on the visible light
* area (mostly). The data0 sensitivity peaks at 500nm, DATA1 at 600nm.
* These wave lengths are pretty much on the border of colours making
* these a poor candidates for R/G/B standardization. Hence they're both
* marked as clear channels
*/
BU27034_CHAN_DATA(DATA0, IIO_MOD_LIGHT_CLEAR),
BU27034_CHAN_DATA(DATA1, IIO_MOD_LIGHT_CLEAR),
BU27034_CHAN_DATA(DATA2, IIO_MOD_LIGHT_IR),
IIO_CHAN_SOFT_TIMESTAMP(4),
};
struct bu27034_data {
struct regmap *regmap;
struct device *dev;
/*
* Protect gain and time during scale adjustment and data reading.
* Protect measurement enabling/disabling.
*/
struct mutex mutex;
struct iio_gts gts;
struct task_struct *task;
__le16 raw[3];
struct {
u32 mlux;
__le16 channels[3];
s64 ts __aligned(8);
} scan;
};
struct bu27034_result {
u16 ch0;
u16 ch1;
u16 ch2;
};
static const struct regmap_range bu27034_volatile_ranges[] = {
{
.range_min = BU27034_REG_SYSTEM_CONTROL,
.range_max = BU27034_REG_SYSTEM_CONTROL,
}, {
.range_min = BU27034_REG_MODE_CONTROL4,
.range_max = BU27034_REG_MODE_CONTROL4,
}, {
.range_min = BU27034_REG_DATA0_LO,
.range_max = BU27034_REG_DATA2_HI,
},
};
static const struct regmap_access_table bu27034_volatile_regs = {
.yes_ranges = &bu27034_volatile_ranges[0],
.n_yes_ranges = ARRAY_SIZE(bu27034_volatile_ranges),
};
static const struct regmap_range bu27034_read_only_ranges[] = {
{
.range_min = BU27034_REG_DATA0_LO,
.range_max = BU27034_REG_DATA2_HI,
}, {
.range_min = BU27034_REG_MANUFACTURER_ID,
.range_max = BU27034_REG_MANUFACTURER_ID,
}
};
static const struct regmap_access_table bu27034_ro_regs = {
.no_ranges = &bu27034_read_only_ranges[0],
.n_no_ranges = ARRAY_SIZE(bu27034_read_only_ranges),
};
static const struct regmap_config bu27034_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = BU27034_REG_MAX,
.cache_type = REGCACHE_RBTREE,
.volatile_table = &bu27034_volatile_regs,
.wr_table = &bu27034_ro_regs,
};
struct bu27034_gain_check {
int old_gain;
int new_gain;
int chan;
};
static int bu27034_get_gain_sel(struct bu27034_data *data, int chan)
{
int ret, val;
switch (chan) {
case BU27034_CHAN_DATA0:
case BU27034_CHAN_DATA1:
{
int reg[] = {
[BU27034_CHAN_DATA0] = BU27034_REG_MODE_CONTROL2,
[BU27034_CHAN_DATA1] = BU27034_REG_MODE_CONTROL3,
};
ret = regmap_read(data->regmap, reg[chan], &val);
if (ret)
return ret;
return FIELD_GET(BU27034_MASK_D01_GAIN, val);
}
case BU27034_CHAN_DATA2:
{
int d2_lo_bits = fls(BU27034_MASK_D2_GAIN_LO);
ret = regmap_read(data->regmap, BU27034_REG_MODE_CONTROL2, &val);
if (ret)
return ret;
/*
* The data2 channel gain is composed by 5 non continuous bits
* [7:6], [2:0]. Thus when we combine the 5-bit 'selector'
* from register value we must right shift the high bits by 3.
*/
return FIELD_GET(BU27034_MASK_D2_GAIN_HI, val) << d2_lo_bits |
FIELD_GET(BU27034_MASK_D2_GAIN_LO, val);
}
default:
return -EINVAL;
}
}
static int bu27034_get_gain(struct bu27034_data *data, int chan, int *gain)
{
int ret, sel;
ret = bu27034_get_gain_sel(data, chan);
if (ret < 0)
return ret;
sel = ret;
ret = iio_gts_find_gain_by_sel(&data->gts, sel);
if (ret < 0) {
dev_err(data->dev, "chan %u: unknown gain value 0x%x\n", chan,
sel);
return ret;
}
*gain = ret;
return 0;
}
static int bu27034_get_int_time(struct bu27034_data *data)
{
int ret, sel;
ret = regmap_read(data->regmap, BU27034_REG_MODE_CONTROL1, &sel);
if (ret)
return ret;
return iio_gts_find_int_time_by_sel(&data->gts,
sel & BU27034_MASK_MEAS_MODE);
}
static int _bu27034_get_scale(struct bu27034_data *data, int channel, int *val,
int *val2)
{
int gain, ret;
ret = bu27034_get_gain(data, channel, &gain);
if (ret)
return ret;
ret = bu27034_get_int_time(data);
if (ret < 0)
return ret;
return iio_gts_get_scale(&data->gts, gain, ret, val, val2);
}
static int bu27034_get_scale(struct bu27034_data *data, int channel, int *val,
int *val2)
{
int ret;
if (channel == BU27034_CHAN_ALS) {
*val = 0;
*val2 = 1000;
return IIO_VAL_INT_PLUS_MICRO;
}
mutex_lock(&data->mutex);
ret = _bu27034_get_scale(data, channel, val, val2);
mutex_unlock(&data->mutex);
if (ret)
return ret;
return IIO_VAL_INT_PLUS_NANO;
}
/* Caller should hold the lock to protect lux reading */
static int bu27034_write_gain_sel(struct bu27034_data *data, int chan, int sel)
{
static const int reg[] = {
[BU27034_CHAN_DATA0] = BU27034_REG_MODE_CONTROL2,
[BU27034_CHAN_DATA1] = BU27034_REG_MODE_CONTROL3,
};
int mask, val;
if (chan != BU27034_CHAN_DATA0 && chan != BU27034_CHAN_DATA1)
return -EINVAL;
val = FIELD_PREP(BU27034_MASK_D01_GAIN, sel);
mask = BU27034_MASK_D01_GAIN;
if (chan == BU27034_CHAN_DATA0) {
/*
* We keep the same gain for channel 2 as we set for channel 0
* We can't allow them to be individually controlled because
* setting one will impact also the other. Also, if we don't
* always update both gains we may result unsupported bit
* combinations.
*
* This is not nice but this is yet another place where the
* user space must be prepared to surprizes. Namely, see chan 2
* gain changed when chan 0 gain is changed.
*
* This is not fatal for most users though. I don't expect the
* channel 2 to be used in any generic cases - the intensity
* values provided by the sensor for IR area are not openly
* documented. Also, channel 2 is not used for visible light.
*
* So, if there is application which is written to utilize the
* channel 2 - then it is probably specifically targeted to this
* sensor and knows how to utilize those values. It is safe to
* hope such user can also cope with the gain changes.
*/
mask |= BU27034_MASK_D2_GAIN_LO;
/*
* The D2 gain bits are directly the lowest bits of selector.
* Just do add those bits to the value
*/
val |= sel & BU27034_MASK_D2_GAIN_LO;
}
return regmap_update_bits(data->regmap, reg[chan], mask, val);
}
static int bu27034_set_gain(struct bu27034_data *data, int chan, int gain)
{
int ret;
/*
* We don't allow setting channel 2 gain as it messes up the
* gain for channel 0 - which shares the high bits
*/
if (chan != BU27034_CHAN_DATA0 && chan != BU27034_CHAN_DATA1)
return -EINVAL;
ret = iio_gts_find_sel_by_gain(&data->gts, gain);
if (ret < 0)
return ret;
return bu27034_write_gain_sel(data, chan, ret);
}
/* Caller should hold the lock to protect data->int_time */
static int bu27034_set_int_time(struct bu27034_data *data, int time)
{
int ret;
ret = iio_gts_find_sel_by_int_time(&data->gts, time);
if (ret < 0)
return ret;
return regmap_update_bits(data->regmap, BU27034_REG_MODE_CONTROL1,
BU27034_MASK_MEAS_MODE, ret);
}
/*
* We try to change the time in such way that the scale is maintained for
* given channels by adjusting gain so that it compensates the time change.
*/
static int bu27034_try_set_int_time(struct bu27034_data *data, int time_us)
{
struct bu27034_gain_check gains[] = {
{ .chan = BU27034_CHAN_DATA0 },
{ .chan = BU27034_CHAN_DATA1 },
};
int numg = ARRAY_SIZE(gains);
int ret, int_time_old, i;
mutex_lock(&data->mutex);
ret = bu27034_get_int_time(data);
if (ret < 0)
goto unlock_out;
int_time_old = ret;
if (!iio_gts_valid_time(&data->gts, time_us)) {
dev_err(data->dev, "Unsupported integration time %u\n",
time_us);
ret = -EINVAL;
goto unlock_out;
}
if (time_us == int_time_old) {
ret = 0;
goto unlock_out;
}
for (i = 0; i < numg; i++) {
ret = bu27034_get_gain(data, gains[i].chan, &gains[i].old_gain);
if (ret)
goto unlock_out;
ret = iio_gts_find_new_gain_by_old_gain_time(&data->gts,
gains[i].old_gain,
int_time_old, time_us,
&gains[i].new_gain);
if (ret) {
int scale1, scale2;
bool ok;
_bu27034_get_scale(data, gains[i].chan, &scale1, &scale2);
dev_dbg(data->dev,
"chan %u, can't support time %u with scale %u %u\n",
gains[i].chan, time_us, scale1, scale2);
if (gains[i].new_gain < 0)
goto unlock_out;
/*
* If caller requests for integration time change and we
* can't support the scale - then the caller should be
* prepared to 'pick up the pieces and deal with the
* fact that the scale changed'.
*/
ret = iio_find_closest_gain_low(&data->gts,
gains[i].new_gain, &ok);
if (!ok)
dev_dbg(data->dev,
"optimal gain out of range for chan %u\n",
gains[i].chan);
if (ret < 0) {
dev_dbg(data->dev,
"Total gain increase. Risk of saturation");
ret = iio_gts_get_min_gain(&data->gts);
if (ret < 0)
goto unlock_out;
}
dev_dbg(data->dev, "chan %u scale changed\n",
gains[i].chan);
gains[i].new_gain = ret;
dev_dbg(data->dev, "chan %u new gain %u\n",
gains[i].chan, gains[i].new_gain);
}
}
for (i = 0; i < numg; i++) {
ret = bu27034_set_gain(data, gains[i].chan, gains[i].new_gain);
if (ret)
goto unlock_out;
}
ret = bu27034_set_int_time(data, time_us);
unlock_out:
mutex_unlock(&data->mutex);
return ret;
}
static int bu27034_set_scale(struct bu27034_data *data, int chan,
int val, int val2)
{
int ret, time_sel, gain_sel, i;
bool found = false;
if (chan == BU27034_CHAN_DATA2)
return -EINVAL;
if (chan == BU27034_CHAN_ALS) {
if (val == 0 && val2 == 1000000)
return 0;
return -EINVAL;
}
mutex_lock(&data->mutex);
ret = regmap_read(data->regmap, BU27034_REG_MODE_CONTROL1, &time_sel);
if (ret)
goto unlock_out;
ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts, time_sel,
val, val2, &gain_sel);
if (ret) {
/*
* Could not support scale with given time. Need to change time.
* We still want to maintain the scale for all channels
*/
struct bu27034_gain_check gain;
int new_time_sel;
/*
* Populate information for the other channel which should also
* maintain the scale. (Due to the HW limitations the chan2
* gets the same gain as chan0, so we only need to explicitly
* set the chan 0 and 1).
*/
if (chan == BU27034_CHAN_DATA0)
gain.chan = BU27034_CHAN_DATA1;
else if (chan == BU27034_CHAN_DATA1)
gain.chan = BU27034_CHAN_DATA0;
ret = bu27034_get_gain(data, gain.chan, &gain.old_gain);
if (ret)
goto unlock_out;
/*
* Iterate through all the times to see if we find one which
* can support requested scale for requested channel, while
* maintaining the scale for other channels
*/
for (i = 0; i < data->gts.num_itime; i++) {
new_time_sel = data->gts.itime_table[i].sel;
if (new_time_sel == time_sel)
continue;
/* Can we provide requested scale with this time? */
ret = iio_gts_find_gain_sel_for_scale_using_time(
&data->gts, new_time_sel, val, val2,
&gain_sel);
if (ret)
continue;
/* Can the other channel(s) maintain scale? */
ret = iio_gts_find_new_gain_sel_by_old_gain_time(
&data->gts, gain.old_gain, time_sel,
new_time_sel, &gain.new_gain);
if (!ret) {
/* Yes - we found suitable time */
found = true;
break;
}
}
if (!found) {
dev_dbg(data->dev,
"Can't set scale maintaining other channels\n");
ret = -EINVAL;
goto unlock_out;
}
ret = bu27034_set_gain(data, gain.chan, gain.new_gain);
if (ret)
goto unlock_out;
ret = regmap_update_bits(data->regmap, BU27034_REG_MODE_CONTROL1,
BU27034_MASK_MEAS_MODE, new_time_sel);
if (ret)
goto unlock_out;
}
ret = bu27034_write_gain_sel(data, chan, gain_sel);
unlock_out:
mutex_unlock(&data->mutex);
return ret;
}
/*
* for (D1/D0 < 0.87):
* lx = 0.004521097 * D1 - 0.002663996 * D0 +
* 0.00012213 * D1 * D1 / D0
*
* => 115.7400832 * ch1 / gain1 / mt -
* 68.1982976 * ch0 / gain0 / mt +
* 0.00012213 * 25600 * (ch1 / gain1 / mt) * 25600 *
* (ch1 /gain1 / mt) / (25600 * ch0 / gain0 / mt)
*
* A = 0.00012213 * 25600 * (ch1 /gain1 / mt) * 25600 *
* (ch1 /gain1 / mt) / (25600 * ch0 / gain0 / mt)
* => 0.00012213 * 25600 * (ch1 /gain1 / mt) *
* (ch1 /gain1 / mt) / (ch0 / gain0 / mt)
* => 0.00012213 * 25600 * (ch1 / gain1) * (ch1 /gain1 / mt) /
* (ch0 / gain0)
* => 0.00012213 * 25600 * (ch1 / gain1) * (ch1 /gain1 / mt) *
* gain0 / ch0
* => 3.126528 * ch1 * ch1 * gain0 / gain1 / gain1 / mt /ch0
*
* lx = (115.7400832 * ch1 / gain1 - 68.1982976 * ch0 / gain0) /
* mt + A
* => (115.7400832 * ch1 / gain1 - 68.1982976 * ch0 / gain0) /
* mt + 3.126528 * ch1 * ch1 * gain0 / gain1 / gain1 / mt /
* ch0
*
* => (115.7400832 * ch1 / gain1 - 68.1982976 * ch0 / gain0 +
* 3.126528 * ch1 * ch1 * gain0 / gain1 / gain1 / ch0) /
* mt
*
* For (0.87 <= D1/D0 < 1.00)
* lx = (0.001331* D0 + 0.0000354 * D1) * ((D1/D0 – 0.87) * (0.385) + 1)
* => (0.001331 * 256 * 100 * ch0 / gain0 / mt + 0.0000354 * 256 *
* 100 * ch1 / gain1 / mt) * ((D1/D0 - 0.87) * (0.385) + 1)
* => (34.0736 * ch0 / gain0 / mt + 0.90624 * ch1 / gain1 / mt) *
* ((D1/D0 - 0.87) * (0.385) + 1)
* => (34.0736 * ch0 / gain0 / mt + 0.90624 * ch1 / gain1 / mt) *
* (0.385 * D1/D0 - 0.66505)
* => (34.0736 * ch0 / gain0 / mt + 0.90624 * ch1 / gain1 / mt) *
* (0.385 * 256 * 100 * ch1 / gain1 / mt / (256 * 100 * ch0 / gain0 / mt) - 0.66505)
* => (34.0736 * ch0 / gain0 / mt + 0.90624 * ch1 / gain1 / mt) *
* (9856 * ch1 / gain1 / mt / (25600 * ch0 / gain0 / mt) + 0.66505)
* => 13.118336 * ch1 / (gain1 * mt)
* + 22.66064768 * ch0 / (gain0 * mt)
* + 8931.90144 * ch1 * ch1 * gain0 /
* (25600 * ch0 * gain1 * gain1 * mt)
* + 0.602694912 * ch1 / (gain1 * mt)
*
* => [0.3489024 * ch1 * ch1 * gain0 / (ch0 * gain1 * gain1)
* + 22.66064768 * ch0 / gain0
* + 13.721030912 * ch1 / gain1
* ] / mt
*
* For (D1/D0 >= 1.00)
*
* lx = (0.001331* D0 + 0.0000354 * D1) * ((D1/D0 – 2.0) * (-0.05) + 1)
* => (0.001331* D0 + 0.0000354 * D1) * (-0.05D1/D0 + 1.1)
* => (0.001331 * 256 * 100 * ch0 / gain0 / mt + 0.0000354 * 256 *
* 100 * ch1 / gain1 / mt) * (-0.05D1/D0 + 1.1)
* => (34.0736 * ch0 / gain0 / mt + 0.90624 * ch1 / gain1 / mt) *
* (-0.05 * 256 * 100 * ch1 / gain1 / mt / (256 * 100 * ch0 / gain0 / mt) + 1.1)
* => (34.0736 * ch0 / gain0 / mt + 0.90624 * ch1 / gain1 / mt) *
* (-1280 * ch1 / (gain1 * mt * 25600 * ch0 / gain0 / mt) + 1.1)
* => (34.0736 * ch0 * -1280 * ch1 * gain0 * mt /( gain0 * mt * gain1 * mt * 25600 * ch0)
* + 34.0736 * 1.1 * ch0 / (gain0 * mt)
* + 0.90624 * ch1 * -1280 * ch1 *gain0 * mt / (gain1 * mt *gain1 * mt * 25600 * ch0)
* + 1.1 * 0.90624 * ch1 / (gain1 * mt)
* => -43614.208 * ch1 / (gain1 * mt * 25600)
* + 37.48096 ch0 / (gain0 * mt)
* - 1159.9872 * ch1 * ch1 * gain0 / (gain1 * gain1 * mt * 25600 * ch0)
* + 0.996864 ch1 / (gain1 * mt)
* => [
* - 0.045312 * ch1 * ch1 * gain0 / (gain1 * gain1 * ch0)
* - 0.706816 * ch1 / gain1
* + 37.48096 ch0 /gain0
* ] * mt
*
*
* So, the first case (D1/D0 < 0.87) can be computed to a form:
*
* lx = (3.126528 * ch1 * ch1 * gain0 / (ch0 * gain1 * gain1) +
* 115.7400832 * ch1 / gain1 +
* -68.1982976 * ch0 / gain0
* / mt
*
* Second case (0.87 <= D1/D0 < 1.00) goes to form:
*
* => [0.3489024 * ch1 * ch1 * gain0 / (ch0 * gain1 * gain1) +
* 13.721030912 * ch1 / gain1 +
* 22.66064768 * ch0 / gain0
* ] / mt
*
* Third case (D1/D0 >= 1.00) goes to form:
* => [-0.045312 * ch1 * ch1 * gain0 / (ch0 * gain1 * gain1) +
* -0.706816 * ch1 / gain1 +
* 37.48096 ch0 /(gain0
* ] / mt
*
* This can be unified to format:
* lx = [
* A * ch1 * ch1 * gain0 / (ch0 * gain1 * gain1) +
* B * ch1 / gain1 +
* C * ch0 / gain0
* ] / mt
*
* For case 1:
* A = 3.126528,
* B = 115.7400832
* C = -68.1982976
*
* For case 2:
* A = 0.3489024
* B = 13.721030912
* C = 22.66064768
*
* For case 3:
* A = -0.045312
* B = -0.706816
* C = 37.48096
*/
struct bu27034_lx_coeff {
unsigned int A;
unsigned int B;
unsigned int C;
/* Indicate which of the coefficients above are negative */
bool is_neg[3];
};
static inline u64 gain_mul_div_helper(u64 val, unsigned int gain,
unsigned int div)
{
/*
* Max gain for a channel is 4096. The max u64 (0xffffffffffffffffULL)
* divided by 4096 is 0xFFFFFFFFFFFFF (GENMASK_ULL(51, 0)) (floored).
* Thus, the 0xFFFFFFFFFFFFF is the largest value we can safely multiply
* with the gain, no matter what gain is set.
*
* So, multiplication with max gain may overflow if val is greater than
* 0xFFFFFFFFFFFFF (52 bits set)..
*
* If this is the case we divide first.
*/
if (val < GENMASK_ULL(51, 0)) {
val *= gain;
do_div(val, div);
} else {
do_div(val, div);
val *= gain;
}
return val;
}
static u64 bu27034_fixp_calc_t1_64bit(unsigned int coeff, unsigned int ch0,
unsigned int ch1, unsigned int gain0,
unsigned int gain1)
{
unsigned int helper;
u64 helper64;
helper64 = (u64)coeff * (u64)ch1 * (u64)ch1;
helper = gain1 * gain1;
if (helper > ch0) {
do_div(helper64, helper);
return gain_mul_div_helper(helper64, gain0, ch0);
}
do_div(helper64, ch0);
return gain_mul_div_helper(helper64, gain0, helper);
}
static u64 bu27034_fixp_calc_t1(unsigned int coeff, unsigned int ch0,
unsigned int ch1, unsigned int gain0,
unsigned int gain1)
{
unsigned int helper, tmp;
/*
* Here we could overflow even the 64bit value. Hence we
* multiply with gain0 only after the divisions - even though
* it may result loss of accuracy
*/
helper = coeff * ch1 * ch1;
tmp = helper * gain0;
helper = ch1 * ch1;
if (check_mul_overflow(helper, coeff, &helper))
return bu27034_fixp_calc_t1_64bit(coeff, ch0, ch1, gain0, gain1);
if (check_mul_overflow(helper, gain0, &tmp))
return bu27034_fixp_calc_t1_64bit(coeff, ch0, ch1, gain0, gain1);
return tmp / (gain1 * gain1) / ch0;
}
static u64 bu27034_fixp_calc_t23(unsigned int coeff, unsigned int ch,
unsigned int gain)
{
unsigned int helper;
u64 helper64;
if (!check_mul_overflow(coeff, ch, &helper))
return helper / gain;
helper64 = (u64)coeff * (u64)ch;
do_div(helper64, gain);
return helper64;
}
static int bu27034_fixp_calc_lx(unsigned int ch0, unsigned int ch1,
unsigned int gain0, unsigned int gain1,
unsigned int meastime, int coeff_idx)
{
static const struct bu27034_lx_coeff coeff[] = {
{
.A = 31265280, /* 3.126528 */
.B = 1157400832, /*115.7400832 */
.C = 681982976, /* -68.1982976 */
.is_neg = {false, false, true},
}, {
.A = 3489024, /* 0.3489024 */
.B = 137210309, /* 13.721030912 */
.C = 226606476, /* 22.66064768 */
/* All terms positive */
}, {
.A = 453120, /* -0.045312 */
.B = 7068160, /* -0.706816 */
.C = 374809600, /* 37.48096 */
.is_neg = {true, true, false},
}
};
const struct bu27034_lx_coeff *c = &coeff[coeff_idx];
u64 res = 0, terms[3];
int i;
if (coeff_idx >= ARRAY_SIZE(coeff))
return -EINVAL;
terms[0] = bu27034_fixp_calc_t1(c->A, ch0, ch1, gain0, gain1);
terms[1] = bu27034_fixp_calc_t23(c->B, ch1, gain1);
terms[2] = bu27034_fixp_calc_t23(c->C, ch0, gain0);
/* First, add positive terms */
for (i = 0; i < 3; i++)
if (!c->is_neg[i])
res += terms[i];
/* No positive term => zero lux */
if (!res)
return 0;
/* Then, subtract negative terms (if any) */
for (i = 0; i < 3; i++)
if (c->is_neg[i]) {
/*
* If the negative term is greater than positive - then
* the darkness has taken over and we are all doomed! Eh,
* I mean, then we can just return 0 lx and go out
*/
if (terms[i] >= res)
return 0;
res -= terms[i];
}
meastime *= 10;
do_div(res, meastime);
return (int) res;
}
static bool bu27034_has_valid_sample(struct bu27034_data *data)
{
int ret, val;
ret = regmap_read(data->regmap, BU27034_REG_MODE_CONTROL4, &val);
if (ret) {
dev_err(data->dev, "Read failed %d\n", ret);
return false;
}
return val & BU27034_MASK_VALID;
}
/*
* Reading the register where VALID bit is clears this bit. (So does changing
* any gain / integration time configuration registers) The bit gets
* set when we have acquired new data. We use this bit to indicate data
* validity.
*/
static void bu27034_invalidate_read_data(struct bu27034_data *data)
{
bu27034_has_valid_sample(data);
}
static int bu27034_read_result(struct bu27034_data *data, int chan, int *res)
{
int reg[] = {
[BU27034_CHAN_DATA0] = BU27034_REG_DATA0_LO,
[BU27034_CHAN_DATA1] = BU27034_REG_DATA1_LO,
[BU27034_CHAN_DATA2] = BU27034_REG_DATA2_LO,
};
int valid, ret;
__le16 val;
ret = regmap_read_poll_timeout(data->regmap, BU27034_REG_MODE_CONTROL4,
valid, (valid & BU27034_MASK_VALID),
BU27034_DATA_WAIT_TIME_US, 0);
if (ret)
return ret;
ret = regmap_bulk_read(data->regmap, reg[chan], &val, sizeof(val));
if (ret)
return ret;
*res = le16_to_cpu(val);
return 0;
}
static int bu27034_get_result_unlocked(struct bu27034_data *data, __le16 *res,
int size)
{
int ret = 0, retry_cnt = 0;
retry:
/* Get new value from sensor if data is ready */
if (bu27034_has_valid_sample(data)) {
ret = regmap_bulk_read(data->regmap, BU27034_REG_DATA0_LO,
res, size);
if (ret)
return ret;
bu27034_invalidate_read_data(data);
} else {
/* No new data in sensor. Wait and retry */
retry_cnt++;
if (retry_cnt > BU27034_RETRY_LIMIT) {
dev_err(data->dev, "No data from sensor\n");
return -ETIMEDOUT;
}
msleep(25);
goto retry;
}
return ret;
}
static int bu27034_meas_set(struct bu27034_data *data, bool en)
{
if (en)
return regmap_set_bits(data->regmap, BU27034_REG_MODE_CONTROL4,
BU27034_MASK_MEAS_EN);
return regmap_clear_bits(data->regmap, BU27034_REG_MODE_CONTROL4,
BU27034_MASK_MEAS_EN);
}
static int bu27034_get_single_result(struct bu27034_data *data, int chan,
int *val)
{
int ret;
if (chan < BU27034_CHAN_DATA0 || chan > BU27034_CHAN_DATA2)
return -EINVAL;
ret = bu27034_meas_set(data, true);
if (ret)
return ret;
ret = bu27034_get_int_time(data);
if (ret < 0)
return ret;
msleep(ret / 1000);
return bu27034_read_result(data, chan, val);
}
/*
* The formula given by vendor for computing luxes out of data0 and data1
* (in open air) is as follows:
*
* Let's mark:
* D0 = data0/ch0_gain/meas_time_ms * 25600
* D1 = data1/ch1_gain/meas_time_ms * 25600
*
* Then:
* if (D1/D0 < 0.87)
* lx = (0.001331 * D0 + 0.0000354 * D1) * ((D1 / D0 - 0.87) * 3.45 + 1)
* else if (D1/D0 < 1)
* lx = (0.001331 * D0 + 0.0000354 * D1) * ((D1 / D0 - 0.87) * 0.385 + 1)
* else
* lx = (0.001331 * D0 + 0.0000354 * D1) * ((D1 / D0 - 2) * -0.05 + 1)
*
* We use it here. Users who have for example some colored lens
* need to modify the calculation but I hope this gives a starting point for
* those working with such devices.
*/
static int bu27034_calc_mlux(struct bu27034_data *data, __le16 *res, int *val)
{
unsigned int gain0, gain1, meastime;
unsigned int d1_d0_ratio_scaled;
u16 ch0, ch1;
u64 helper64;
int ret;
/*
* We return 0 lux if calculation fails. This should be reasonably
* easy to spot from the buffers especially if raw-data channels show
* valid values
*/
*val = 0;
ch0 = max_t(u16, 1, le16_to_cpu(res[0]));
ch1 = max_t(u16, 1, le16_to_cpu(res[1]));
ret = bu27034_get_gain(data, BU27034_CHAN_DATA0, &gain0);
if (ret)
return ret;
ret = bu27034_get_gain(data, BU27034_CHAN_DATA1, &gain1);
if (ret)
return ret;
ret = bu27034_get_int_time(data);
if (ret < 0)
return ret;
meastime = ret;
d1_d0_ratio_scaled = (unsigned int)ch1 * (unsigned int)gain0 * 100;
helper64 = (u64)ch1 * (u64)gain0 * 100LLU;
if (helper64 != d1_d0_ratio_scaled) {
unsigned int div = (unsigned int)ch0 * gain1;
do_div(helper64, div);
d1_d0_ratio_scaled = helper64;
} else {
d1_d0_ratio_scaled /= ch0 * gain1;
}
if (d1_d0_ratio_scaled < 87)
ret = bu27034_fixp_calc_lx(ch0, ch1, gain0, gain1, meastime, 0);
else if (d1_d0_ratio_scaled < 100)
ret = bu27034_fixp_calc_lx(ch0, ch1, gain0, gain1, meastime, 1);
else
ret = bu27034_fixp_calc_lx(ch0, ch1, gain0, gain1, meastime, 2);
if (ret < 0)
return ret;
*val = ret;
return 0;
}
static int bu27034_get_mlux(struct bu27034_data *data, int chan, int *val)
{
__le16 res[3];
int ret;
ret = bu27034_meas_set(data, true);
if (ret)
return ret;
ret = bu27034_get_result_unlocked(data, &res[0], sizeof(res));
if (ret)
return ret;
ret = bu27034_calc_mlux(data, res, val);
if (ret)
return ret;
ret = bu27034_meas_set(data, false);
if (ret)
dev_err(data->dev, "failed to disable measurement\n");
return 0;
}
static int bu27034_read_raw(struct iio_dev *idev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct bu27034_data *data = iio_priv(idev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
*val = 0;
*val2 = bu27034_get_int_time(data);
if (*val2 < 0)
return *val2;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_SCALE:
return bu27034_get_scale(data, chan->channel, val, val2);
case IIO_CHAN_INFO_RAW:
{
int (*result_get)(struct bu27034_data *data, int chan, int *val);
if (chan->type == IIO_INTENSITY)
result_get = bu27034_get_single_result;
else if (chan->type == IIO_LIGHT)
result_get = bu27034_get_mlux;
else
return -EINVAL;
/* Don't mess with measurement enabling while buffering */
ret = iio_device_claim_direct_mode(idev);
if (ret)
return ret;
mutex_lock(&data->mutex);
/*
* Reading one channel at a time is inefficient but we
* don't care here. Buffered version should be used if
* performance is an issue.
*/
ret = result_get(data, chan->channel, val);
mutex_unlock(&data->mutex);
iio_device_release_direct_mode(idev);
if (ret)
return ret;
return IIO_VAL_INT;
}
default:
return -EINVAL;
}
}
static int bu27034_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_SCALE:
return IIO_VAL_INT_PLUS_NANO;
case IIO_CHAN_INFO_INT_TIME:
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int bu27034_write_raw(struct iio_dev *idev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct bu27034_data *data = iio_priv(idev);
int ret;
ret = iio_device_claim_direct_mode(idev);
if (ret)
return ret;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
ret = bu27034_set_scale(data, chan->channel, val, val2);
break;
case IIO_CHAN_INFO_INT_TIME:
if (!val)
ret = bu27034_try_set_int_time(data, val2);
else
ret = -EINVAL;
break;
default:
ret = -EINVAL;
break;
}
iio_device_release_direct_mode(idev);
return ret;
}
static int bu27034_read_avail(struct iio_dev *idev,
struct iio_chan_spec const *chan, const int **vals,
int *type, int *length, long mask)
{
struct bu27034_data *data = iio_priv(idev);
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
return iio_gts_avail_times(&data->gts, vals, type, length);
case IIO_CHAN_INFO_SCALE:
return iio_gts_all_avail_scales(&data->gts, vals, type, length);
default:
return -EINVAL;
}
}
static const struct iio_info bu27034_info = {
.read_raw = &bu27034_read_raw,
.write_raw = &bu27034_write_raw,
.write_raw_get_fmt = &bu27034_write_raw_get_fmt,
.read_avail = &bu27034_read_avail,
};
static int bu27034_chip_init(struct bu27034_data *data)
{
int ret, sel;
/* Reset */
ret = regmap_write_bits(data->regmap, BU27034_REG_SYSTEM_CONTROL,
BU27034_MASK_SW_RESET, BU27034_MASK_SW_RESET);
if (ret)
return dev_err_probe(data->dev, ret, "Sensor reset failed\n");
msleep(1);
ret = regmap_reinit_cache(data->regmap, &bu27034_regmap);
if (ret) {
dev_err(data->dev, "Failed to reinit reg cache\n");
return ret;
}
/*
* Read integration time here to ensure it is in regmap cache. We do
* this to speed-up the int-time acquisition in the start of the buffer
* handling thread where longer delays could make it more likely we end
* up skipping a sample, and where the longer delays make timestamps
* less accurate.
*/
ret = regmap_read(data->regmap, BU27034_REG_MODE_CONTROL1, &sel);
if (ret)
dev_err(data->dev, "reading integration time failed\n");
return 0;
}
static int bu27034_wait_for_data(struct bu27034_data *data)
{
int ret, val;
ret = regmap_read_poll_timeout(data->regmap, BU27034_REG_MODE_CONTROL4,
val, val & BU27034_MASK_VALID,
BU27034_DATA_WAIT_TIME_US,
BU27034_TOTAL_DATA_WAIT_TIME_US);
if (ret) {
dev_err(data->dev, "data polling %s\n",
!(val & BU27034_MASK_VALID) ? "timeout" : "fail");
return ret;
}
ret = regmap_bulk_read(data->regmap, BU27034_REG_DATA0_LO,
&data->scan.channels[0],
sizeof(data->scan.channels));
if (ret)
return ret;
bu27034_invalidate_read_data(data);
return 0;
}
static int bu27034_buffer_thread(void *arg)
{
struct iio_dev *idev = arg;
struct bu27034_data *data;
int wait_ms;
data = iio_priv(idev);
wait_ms = bu27034_get_int_time(data);
wait_ms /= 1000;
wait_ms -= BU27034_MEAS_WAIT_PREMATURE_MS;
while (!kthread_should_stop()) {
int ret;
int64_t tstamp;
msleep(wait_ms);
ret = bu27034_wait_for_data(data);
if (ret)
continue;
tstamp = iio_get_time_ns(idev);
if (test_bit(BU27034_CHAN_ALS, idev->active_scan_mask)) {
int mlux;
ret = bu27034_calc_mlux(data, &data->scan.channels[0],
&mlux);
if (ret)
dev_err(data->dev, "failed to calculate lux\n");
/*
* The maximum Milli lux value we get with gain 1x time
* 55mS data ch0 = 0xffff ch1 = 0xffff fits in 26 bits
* so there should be no problem returning int from
* computations and casting it to u32
*/
data->scan.mlux = (u32)mlux;
}
iio_push_to_buffers_with_timestamp(idev, &data->scan, tstamp);
}
return 0;
}
static int bu27034_buffer_enable(struct iio_dev *idev)
{
struct bu27034_data *data = iio_priv(idev);
struct task_struct *task;
int ret;
mutex_lock(&data->mutex);
ret = bu27034_meas_set(data, true);
if (ret)
goto unlock_out;
task = kthread_run(bu27034_buffer_thread, idev,
"bu27034-buffering-%u",
iio_device_id(idev));
if (IS_ERR(task)) {
ret = PTR_ERR(task);
goto unlock_out;
}
data->task = task;
unlock_out:
mutex_unlock(&data->mutex);
return ret;
}
static int bu27034_buffer_disable(struct iio_dev *idev)
{
struct bu27034_data *data = iio_priv(idev);
int ret;
mutex_lock(&data->mutex);
if (data->task) {
kthread_stop(data->task);
data->task = NULL;
}
ret = bu27034_meas_set(data, false);
mutex_unlock(&data->mutex);
return ret;
}
static const struct iio_buffer_setup_ops bu27034_buffer_ops = {
.postenable = &bu27034_buffer_enable,
.predisable = &bu27034_buffer_disable,
};
static int bu27034_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct bu27034_data *data;
struct regmap *regmap;
struct iio_dev *idev;
unsigned int part_id, reg;
int ret;
regmap = devm_regmap_init_i2c(i2c, &bu27034_regmap);
if (IS_ERR(regmap))
return dev_err_probe(dev, PTR_ERR(regmap),
"Failed to initialize Regmap\n");
idev = devm_iio_device_alloc(dev, sizeof(*data));
if (!idev)
return -ENOMEM;
ret = devm_regulator_get_enable(dev, "vdd");
if (ret)
return dev_err_probe(dev, ret, "Failed to get regulator\n");
data = iio_priv(idev);
ret = regmap_read(regmap, BU27034_REG_SYSTEM_CONTROL, ®);
if (ret)
return dev_err_probe(dev, ret, "Failed to access sensor\n");
part_id = FIELD_GET(BU27034_MASK_PART_ID, reg);
if (part_id != BU27034_ID)
dev_warn(dev, "unknown device 0x%x\n", part_id);
ret = devm_iio_init_iio_gts(dev, BU27034_SCALE_1X, 0, bu27034_gains,
ARRAY_SIZE(bu27034_gains), bu27034_itimes,
ARRAY_SIZE(bu27034_itimes), &data->gts);
if (ret)
return ret;
mutex_init(&data->mutex);
data->regmap = regmap;
data->dev = dev;
idev->channels = bu27034_channels;
idev->num_channels = ARRAY_SIZE(bu27034_channels);
idev->name = "bu27034";
idev->info = &bu27034_info;
idev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
idev->available_scan_masks = bu27034_scan_masks;
ret = bu27034_chip_init(data);
if (ret)
return ret;
ret = devm_iio_kfifo_buffer_setup(dev, idev, &bu27034_buffer_ops);
if (ret)
return dev_err_probe(dev, ret, "buffer setup failed\n");
ret = devm_iio_device_register(dev, idev);
if (ret < 0)
return dev_err_probe(dev, ret,
"Unable to register iio device\n");
return ret;
}
static const struct of_device_id bu27034_of_match[] = {
{ .compatible = "rohm,bu27034" },
{ }
};
MODULE_DEVICE_TABLE(of, bu27034_of_match);
static struct i2c_driver bu27034_i2c_driver = {
.driver = {
.name = "bu27034-als",
.of_match_table = bu27034_of_match,
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
.probe = bu27034_probe,
};
module_i2c_driver(bu27034_i2c_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Matti Vaittinen <[email protected]>");
MODULE_DESCRIPTION("ROHM BU27034 ambient light sensor driver");
MODULE_IMPORT_NS(IIO_GTS_HELPER);
| linux-master | drivers/iio/light/rohm-bu27034.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2023 Axis Communications AB
*
* Datasheet: https://www.ti.com/lit/gpn/opt4001
*
* Device driver for the Texas Instruments OPT4001.
*/
#include <linux/bitfield.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
/* OPT4001 register set */
#define OPT4001_LIGHT1_MSB 0x00
#define OPT4001_LIGHT1_LSB 0x01
#define OPT4001_CTRL 0x0A
#define OPT4001_DEVICE_ID 0x11
/* OPT4001 register mask */
#define OPT4001_EXPONENT_MASK GENMASK(15, 12)
#define OPT4001_MSB_MASK GENMASK(11, 0)
#define OPT4001_LSB_MASK GENMASK(15, 8)
#define OPT4001_COUNTER_MASK GENMASK(7, 4)
#define OPT4001_CRC_MASK GENMASK(3, 0)
/* OPT4001 device id mask */
#define OPT4001_DEVICE_ID_MASK GENMASK(11, 0)
/* OPT4001 control registers mask */
#define OPT4001_CTRL_QWAKE_MASK GENMASK(15, 15)
#define OPT4001_CTRL_RANGE_MASK GENMASK(13, 10)
#define OPT4001_CTRL_CONV_TIME_MASK GENMASK(9, 6)
#define OPT4001_CTRL_OPER_MODE_MASK GENMASK(5, 4)
#define OPT4001_CTRL_LATCH_MASK GENMASK(3, 3)
#define OPT4001_CTRL_INT_POL_MASK GENMASK(2, 2)
#define OPT4001_CTRL_FAULT_COUNT GENMASK(0, 1)
/* OPT4001 constants */
#define OPT4001_DEVICE_ID_VAL 0x121
/* OPT4001 operating modes */
#define OPT4001_CTRL_OPER_MODE_OFF 0x0
#define OPT4001_CTRL_OPER_MODE_FORCED 0x1
#define OPT4001_CTRL_OPER_MODE_ONE_SHOT 0x2
#define OPT4001_CTRL_OPER_MODE_CONTINUOUS 0x3
/* OPT4001 conversion control register definitions */
#define OPT4001_CTRL_CONVERSION_0_6MS 0x0
#define OPT4001_CTRL_CONVERSION_1MS 0x1
#define OPT4001_CTRL_CONVERSION_1_8MS 0x2
#define OPT4001_CTRL_CONVERSION_3_4MS 0x3
#define OPT4001_CTRL_CONVERSION_6_5MS 0x4
#define OPT4001_CTRL_CONVERSION_12_7MS 0x5
#define OPT4001_CTRL_CONVERSION_25MS 0x6
#define OPT4001_CTRL_CONVERSION_50MS 0x7
#define OPT4001_CTRL_CONVERSION_100MS 0x8
#define OPT4001_CTRL_CONVERSION_200MS 0x9
#define OPT4001_CTRL_CONVERSION_400MS 0xa
#define OPT4001_CTRL_CONVERSION_800MS 0xb
/* OPT4001 scale light level range definitions */
#define OPT4001_CTRL_LIGHT_SCALE_AUTO 12
/* OPT4001 default values */
#define OPT4001_DEFAULT_CONVERSION_TIME OPT4001_CTRL_CONVERSION_800MS
/*
* The different packaging of OPT4001 has different constants used when calculating
* lux values.
*/
struct opt4001_chip_info {
int mul;
int div;
const char *name;
};
struct opt4001_chip {
struct regmap *regmap;
struct i2c_client *client;
u8 int_time;
const struct opt4001_chip_info *chip_info;
};
static const struct opt4001_chip_info opt4001_sot_5x3_info = {
.mul = 4375,
.div = 10000000,
.name = "opt4001-sot-5x3"
};
static const struct opt4001_chip_info opt4001_picostar_info = {
.mul = 3125,
.div = 10000000,
.name = "opt4001-picostar"
};
static const int opt4001_int_time_available[][2] = {
{ 0, 600 },
{ 0, 1000 },
{ 0, 1800 },
{ 0, 3400 },
{ 0, 6500 },
{ 0, 12700 },
{ 0, 25000 },
{ 0, 50000 },
{ 0, 100000 },
{ 0, 200000 },
{ 0, 400000 },
{ 0, 800000 },
};
/*
* Conversion time is integration time + time to set register
* this is used as integration time.
*/
static const int opt4001_int_time_reg[][2] = {
{ 600, OPT4001_CTRL_CONVERSION_0_6MS },
{ 1000, OPT4001_CTRL_CONVERSION_1MS },
{ 1800, OPT4001_CTRL_CONVERSION_1_8MS },
{ 3400, OPT4001_CTRL_CONVERSION_3_4MS },
{ 6500, OPT4001_CTRL_CONVERSION_6_5MS },
{ 12700, OPT4001_CTRL_CONVERSION_12_7MS },
{ 25000, OPT4001_CTRL_CONVERSION_25MS },
{ 50000, OPT4001_CTRL_CONVERSION_50MS },
{ 100000, OPT4001_CTRL_CONVERSION_100MS },
{ 200000, OPT4001_CTRL_CONVERSION_200MS },
{ 400000, OPT4001_CTRL_CONVERSION_400MS },
{ 800000, OPT4001_CTRL_CONVERSION_800MS },
};
static int opt4001_als_time_to_index(const u32 als_integration_time)
{
int i;
for (i = 0; i < ARRAY_SIZE(opt4001_int_time_available); i++) {
if (als_integration_time == opt4001_int_time_available[i][1])
return i;
}
return -EINVAL;
}
static u8 opt4001_calculate_crc(u8 exp, u32 mantissa, u8 count)
{
u8 crc;
crc = (hweight32(mantissa) + hweight32(exp) + hweight32(count)) % 2;
crc |= ((hweight32(mantissa & 0xAAAAA) + hweight32(exp & 0xA)
+ hweight32(count & 0xA)) % 2) << 1;
crc |= ((hweight32(mantissa & 0x88888) + hweight32(exp & 0x8)
+ hweight32(count & 0x8)) % 2) << 2;
crc |= (hweight32(mantissa & 0x80808) % 2) << 3;
return crc;
}
static int opt4001_read_lux_value(struct iio_dev *indio_dev,
int *val, int *val2)
{
struct opt4001_chip *chip = iio_priv(indio_dev);
struct device *dev = &chip->client->dev;
unsigned int light1;
unsigned int light2;
u16 msb;
u16 lsb;
u8 exp;
u8 count;
u8 crc;
u8 calc_crc;
u64 lux_raw;
int ret;
ret = regmap_read(chip->regmap, OPT4001_LIGHT1_MSB, &light1);
if (ret < 0) {
dev_err(dev, "Failed to read data bytes");
return ret;
}
ret = regmap_read(chip->regmap, OPT4001_LIGHT1_LSB, &light2);
if (ret < 0) {
dev_err(dev, "Failed to read data bytes");
return ret;
}
count = FIELD_GET(OPT4001_COUNTER_MASK, light2);
exp = FIELD_GET(OPT4001_EXPONENT_MASK, light1);
crc = FIELD_GET(OPT4001_CRC_MASK, light2);
msb = FIELD_GET(OPT4001_MSB_MASK, light1);
lsb = FIELD_GET(OPT4001_LSB_MASK, light2);
lux_raw = (msb << 8) + lsb;
calc_crc = opt4001_calculate_crc(exp, lux_raw, count);
if (calc_crc != crc)
return -EIO;
lux_raw = lux_raw << exp;
lux_raw = lux_raw * chip->chip_info->mul;
*val = div_u64_rem(lux_raw, chip->chip_info->div, val2);
*val2 = *val2 * 100;
return IIO_VAL_INT_PLUS_NANO;
}
static int opt4001_set_conf(struct opt4001_chip *chip)
{
struct device *dev = &chip->client->dev;
u16 reg;
int ret;
reg = FIELD_PREP(OPT4001_CTRL_RANGE_MASK, OPT4001_CTRL_LIGHT_SCALE_AUTO);
reg |= FIELD_PREP(OPT4001_CTRL_CONV_TIME_MASK, chip->int_time);
reg |= FIELD_PREP(OPT4001_CTRL_OPER_MODE_MASK, OPT4001_CTRL_OPER_MODE_CONTINUOUS);
ret = regmap_write(chip->regmap, OPT4001_CTRL, reg);
if (ret)
dev_err(dev, "Failed to set configuration\n");
return ret;
}
static int opt4001_power_down(struct opt4001_chip *chip)
{
struct device *dev = &chip->client->dev;
int ret;
unsigned int reg;
ret = regmap_read(chip->regmap, OPT4001_DEVICE_ID, ®);
if (ret) {
dev_err(dev, "Failed to read configuration\n");
return ret;
}
/* MODE_OFF is 0x0 so just set bits to 0 */
reg &= ~OPT4001_CTRL_OPER_MODE_MASK;
ret = regmap_write(chip->regmap, OPT4001_CTRL, reg);
if (ret)
dev_err(dev, "Failed to set configuration to power down\n");
return ret;
}
static void opt4001_chip_off_action(void *data)
{
struct opt4001_chip *chip = data;
opt4001_power_down(chip);
}
static const struct iio_chan_spec opt4001_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME)
},
};
static int opt4001_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct opt4001_chip *chip = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
return opt4001_read_lux_value(indio_dev, val, val2);
case IIO_CHAN_INFO_INT_TIME:
*val = 0;
*val2 = opt4001_int_time_reg[chip->int_time][0];
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int opt4001_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct opt4001_chip *chip = iio_priv(indio_dev);
int int_time;
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
int_time = opt4001_als_time_to_index(val2);
if (int_time < 0)
return int_time;
chip->int_time = int_time;
return opt4001_set_conf(chip);
default:
return -EINVAL;
}
}
static int opt4001_read_available(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
*length = ARRAY_SIZE(opt4001_int_time_available) * 2;
*vals = (const int *)opt4001_int_time_available;
*type = IIO_VAL_INT_PLUS_MICRO;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static const struct iio_info opt4001_info_no_irq = {
.read_raw = opt4001_read_raw,
.write_raw = opt4001_write_raw,
.read_avail = opt4001_read_available,
};
static int opt4001_load_defaults(struct opt4001_chip *chip)
{
chip->int_time = OPT4001_DEFAULT_CONVERSION_TIME;
return opt4001_set_conf(chip);
}
static bool opt4001_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case OPT4001_LIGHT1_MSB:
case OPT4001_LIGHT1_LSB:
case OPT4001_CTRL:
case OPT4001_DEVICE_ID:
return true;
default:
return false;
}
}
static bool opt4001_writable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case OPT4001_CTRL:
return true;
default:
return false;
}
}
static bool opt4001_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case OPT4001_LIGHT1_MSB:
case OPT4001_LIGHT1_LSB:
return true;
default:
return false;
}
}
static const struct regmap_config opt4001_regmap_config = {
.name = "opt4001",
.reg_bits = 8,
.val_bits = 16,
.cache_type = REGCACHE_RBTREE,
.max_register = OPT4001_DEVICE_ID,
.readable_reg = opt4001_readable_reg,
.writeable_reg = opt4001_writable_reg,
.volatile_reg = opt4001_volatile_reg,
.val_format_endian = REGMAP_ENDIAN_BIG,
};
static int opt4001_probe(struct i2c_client *client)
{
struct opt4001_chip *chip;
struct iio_dev *indio_dev;
int ret;
uint dev_id;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
if (!indio_dev)
return -ENOMEM;
chip = iio_priv(indio_dev);
ret = devm_regulator_get_enable(&client->dev, "vdd");
if (ret)
return dev_err_probe(&client->dev, ret, "Failed to enable vdd supply\n");
chip->regmap = devm_regmap_init_i2c(client, &opt4001_regmap_config);
if (IS_ERR(chip->regmap))
return dev_err_probe(&client->dev, PTR_ERR(chip->regmap),
"regmap initialization failed\n");
chip->client = client;
indio_dev->info = &opt4001_info_no_irq;
ret = regmap_reinit_cache(chip->regmap, &opt4001_regmap_config);
if (ret)
return dev_err_probe(&client->dev, ret,
"failed to reinit regmap cache\n");
ret = regmap_read(chip->regmap, OPT4001_DEVICE_ID, &dev_id);
if (ret < 0)
return dev_err_probe(&client->dev, ret,
"Failed to read the device ID register\n");
dev_id = FIELD_GET(OPT4001_DEVICE_ID_MASK, dev_id);
if (dev_id != OPT4001_DEVICE_ID_VAL)
dev_warn(&client->dev, "Device ID: %#04x unknown\n", dev_id);
chip->chip_info = device_get_match_data(&client->dev);
indio_dev->channels = opt4001_channels;
indio_dev->num_channels = ARRAY_SIZE(opt4001_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->name = chip->chip_info->name;
ret = opt4001_load_defaults(chip);
if (ret < 0)
return dev_err_probe(&client->dev, ret,
"Failed to set sensor defaults\n");
ret = devm_add_action_or_reset(&client->dev,
opt4001_chip_off_action,
chip);
if (ret < 0)
return dev_err_probe(&client->dev, ret,
"Failed to setup power off action\n");
return devm_iio_device_register(&client->dev, indio_dev);
}
/*
* The compatible string determines which constants to use depending on
* opt4001 packaging
*/
static const struct i2c_device_id opt4001_id[] = {
{ "opt4001-sot-5x3", (kernel_ulong_t)&opt4001_sot_5x3_info },
{ "opt4001-picostar", (kernel_ulong_t)&opt4001_picostar_info },
{ }
};
MODULE_DEVICE_TABLE(i2c, opt4001_id);
static const struct of_device_id opt4001_of_match[] = {
{ .compatible = "ti,opt4001-sot-5x3", .data = &opt4001_sot_5x3_info},
{ .compatible = "ti,opt4001-picostar", .data = &opt4001_picostar_info},
{}
};
MODULE_DEVICE_TABLE(of, opt4001_of_match);
static struct i2c_driver opt4001_driver = {
.driver = {
.name = "opt4001",
.of_match_table = opt4001_of_match,
},
.probe = opt4001_probe,
.id_table = opt4001_id,
};
module_i2c_driver(opt4001_driver);
MODULE_AUTHOR("Stefan Windfeldt-Prytz <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments opt4001 ambient light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/opt4001.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ROHM Colour Sensor driver for
* - BU27008 RGBC sensor
* - BU27010 RGBC + Flickering sensor
*
* Copyright (c) 2023, ROHM Semiconductor.
*/
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/units.h>
#include <linux/iio/iio.h>
#include <linux/iio/iio-gts-helper.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
/*
* A word about register address and mask definitions.
*
* At a quick glance to the data-sheet register tables, the BU27010 has all the
* registers that the BU27008 has. On top of that the BU27010 adds couple of new
* ones.
*
* So, all definitions BU27008_REG_* are there also for BU27010 but none of the
* BU27010_REG_* are present on BU27008. This makes sense as BU27010 just adds
* some features (Flicker FIFO, more power control) on top of the BU27008.
*
* Unfortunately, some of the wheel has been re-invented. Even though the names
* of the registers have stayed the same, pretty much all of the functionality
* provided by the registers has changed place. Contents of all MODE_CONTROL
* registers on BU27008 and BU27010 are different.
*
* Chip-specific mapping from register addresses/bits to functionality is done
* in bu27_chip_data structures.
*/
#define BU27008_REG_SYSTEM_CONTROL 0x40
#define BU27008_MASK_SW_RESET BIT(7)
#define BU27008_MASK_PART_ID GENMASK(5, 0)
#define BU27008_ID 0x1a
#define BU27008_REG_MODE_CONTROL1 0x41
#define BU27008_MASK_MEAS_MODE GENMASK(2, 0)
#define BU27008_MASK_CHAN_SEL GENMASK(3, 2)
#define BU27008_REG_MODE_CONTROL2 0x42
#define BU27008_MASK_RGBC_GAIN GENMASK(7, 3)
#define BU27008_MASK_IR_GAIN_LO GENMASK(2, 0)
#define BU27008_SHIFT_IR_GAIN 3
#define BU27008_REG_MODE_CONTROL3 0x43
#define BU27008_MASK_VALID BIT(7)
#define BU27008_MASK_INT_EN BIT(1)
#define BU27008_INT_EN BU27008_MASK_INT_EN
#define BU27008_INT_DIS 0
#define BU27008_MASK_MEAS_EN BIT(0)
#define BU27008_MEAS_EN BIT(0)
#define BU27008_MEAS_DIS 0
#define BU27008_REG_DATA0_LO 0x50
#define BU27008_REG_DATA1_LO 0x52
#define BU27008_REG_DATA2_LO 0x54
#define BU27008_REG_DATA3_LO 0x56
#define BU27008_REG_DATA3_HI 0x57
#define BU27008_REG_MANUFACTURER_ID 0x92
#define BU27008_REG_MAX BU27008_REG_MANUFACTURER_ID
/* BU27010 specific definitions */
#define BU27010_MASK_SW_RESET BIT(7)
#define BU27010_ID 0x1b
#define BU27010_REG_POWER 0x3e
#define BU27010_MASK_POWER BIT(0)
#define BU27010_REG_RESET 0x3f
#define BU27010_MASK_RESET BIT(0)
#define BU27010_RESET_RELEASE BU27010_MASK_RESET
#define BU27010_MASK_MEAS_EN BIT(1)
#define BU27010_MASK_CHAN_SEL GENMASK(7, 6)
#define BU27010_MASK_MEAS_MODE GENMASK(5, 4)
#define BU27010_MASK_RGBC_GAIN GENMASK(3, 0)
#define BU27010_MASK_DATA3_GAIN GENMASK(7, 6)
#define BU27010_MASK_DATA2_GAIN GENMASK(5, 4)
#define BU27010_MASK_DATA1_GAIN GENMASK(3, 2)
#define BU27010_MASK_DATA0_GAIN GENMASK(1, 0)
#define BU27010_MASK_FLC_MODE BIT(7)
#define BU27010_MASK_FLC_GAIN GENMASK(4, 0)
#define BU27010_REG_MODE_CONTROL4 0x44
/* If flicker is ever to be supported the IRQ must be handled as a field */
#define BU27010_IRQ_DIS_ALL GENMASK(1, 0)
#define BU27010_DRDY_EN BIT(0)
#define BU27010_MASK_INT_SEL GENMASK(1, 0)
#define BU27010_REG_MODE_CONTROL5 0x45
#define BU27010_MASK_RGB_VALID BIT(7)
#define BU27010_MASK_FLC_VALID BIT(6)
#define BU27010_MASK_WAIT_EN BIT(3)
#define BU27010_MASK_FIFO_EN BIT(2)
#define BU27010_MASK_RGB_EN BIT(1)
#define BU27010_MASK_FLC_EN BIT(0)
#define BU27010_REG_DATA_FLICKER_LO 0x56
#define BU27010_MASK_DATA_FLICKER_HI GENMASK(2, 0)
#define BU27010_REG_FLICKER_COUNT 0x5a
#define BU27010_REG_FIFO_LEVEL_LO 0x5b
#define BU27010_MASK_FIFO_LEVEL_HI BIT(0)
#define BU27010_REG_FIFO_DATA_LO 0x5d
#define BU27010_REG_FIFO_DATA_HI 0x5e
#define BU27010_MASK_FIFO_DATA_HI GENMASK(2, 0)
#define BU27010_REG_MANUFACTURER_ID 0x92
#define BU27010_REG_MAX BU27010_REG_MANUFACTURER_ID
/**
* enum bu27008_chan_type - BU27008 channel types
* @BU27008_RED: Red channel. Always via data0.
* @BU27008_GREEN: Green channel. Always via data1.
* @BU27008_BLUE: Blue channel. Via data2 (when used).
* @BU27008_CLEAR: Clear channel. Via data2 or data3 (when used).
* @BU27008_IR: IR channel. Via data3 (when used).
* @BU27008_NUM_CHANS: Number of channel types.
*/
enum bu27008_chan_type {
BU27008_RED,
BU27008_GREEN,
BU27008_BLUE,
BU27008_CLEAR,
BU27008_IR,
BU27008_NUM_CHANS
};
/**
* enum bu27008_chan - BU27008 physical data channel
* @BU27008_DATA0: Always red.
* @BU27008_DATA1: Always green.
* @BU27008_DATA2: Blue or clear.
* @BU27008_DATA3: IR or clear.
* @BU27008_NUM_HW_CHANS: Number of physical channels
*/
enum bu27008_chan {
BU27008_DATA0,
BU27008_DATA1,
BU27008_DATA2,
BU27008_DATA3,
BU27008_NUM_HW_CHANS
};
/* We can always measure red and green at same time */
#define ALWAYS_SCANNABLE (BIT(BU27008_RED) | BIT(BU27008_GREEN))
/* We use these data channel configs. Ensure scan_masks below follow them too */
#define BU27008_BLUE2_CLEAR3 0x0 /* buffer is R, G, B, C */
#define BU27008_CLEAR2_IR3 0x1 /* buffer is R, G, C, IR */
#define BU27008_BLUE2_IR3 0x2 /* buffer is R, G, B, IR */
static const unsigned long bu27008_scan_masks[] = {
/* buffer is R, G, B, C */
ALWAYS_SCANNABLE | BIT(BU27008_BLUE) | BIT(BU27008_CLEAR),
/* buffer is R, G, C, IR */
ALWAYS_SCANNABLE | BIT(BU27008_CLEAR) | BIT(BU27008_IR),
/* buffer is R, G, B, IR */
ALWAYS_SCANNABLE | BIT(BU27008_BLUE) | BIT(BU27008_IR),
0
};
/*
* Available scales with gain 1x - 1024x, timings 55, 100, 200, 400 mS
* Time impacts to gain: 1x, 2x, 4x, 8x.
*
* => Max total gain is HWGAIN * gain by integration time (8 * 1024) = 8192
*
* Max amplification is (HWGAIN * MAX integration-time multiplier) 1024 * 8
* = 8192. With NANO scale we get rid of accuracy loss when we start with the
* scale 16.0 for HWGAIN1, INT-TIME 55 mS. This way the nano scale for MAX
* total gain 8192 will be 1953125
*/
#define BU27008_SCALE_1X 16
/*
* On BU27010 available scales with gain 1x - 4096x,
* timings 55, 100, 200, 400 mS. Time impacts to gain: 1x, 2x, 4x, 8x.
*
* => Max total gain is HWGAIN * gain by integration time (8 * 4096)
*
* Using NANO precision for scale we must use scale 64x corresponding gain 1x
* to avoid precision loss.
*/
#define BU27010_SCALE_1X 64
/* See the data sheet for the "Gain Setting" table */
#define BU27008_GSEL_1X 0x00
#define BU27008_GSEL_4X 0x08
#define BU27008_GSEL_8X 0x09
#define BU27008_GSEL_16X 0x0a
#define BU27008_GSEL_32X 0x0b
#define BU27008_GSEL_64X 0x0c
#define BU27008_GSEL_256X 0x18
#define BU27008_GSEL_512X 0x19
#define BU27008_GSEL_1024X 0x1a
static const struct iio_gain_sel_pair bu27008_gains[] = {
GAIN_SCALE_GAIN(1, BU27008_GSEL_1X),
GAIN_SCALE_GAIN(4, BU27008_GSEL_4X),
GAIN_SCALE_GAIN(8, BU27008_GSEL_8X),
GAIN_SCALE_GAIN(16, BU27008_GSEL_16X),
GAIN_SCALE_GAIN(32, BU27008_GSEL_32X),
GAIN_SCALE_GAIN(64, BU27008_GSEL_64X),
GAIN_SCALE_GAIN(256, BU27008_GSEL_256X),
GAIN_SCALE_GAIN(512, BU27008_GSEL_512X),
GAIN_SCALE_GAIN(1024, BU27008_GSEL_1024X),
};
static const struct iio_gain_sel_pair bu27008_gains_ir[] = {
GAIN_SCALE_GAIN(2, BU27008_GSEL_1X),
GAIN_SCALE_GAIN(4, BU27008_GSEL_4X),
GAIN_SCALE_GAIN(8, BU27008_GSEL_8X),
GAIN_SCALE_GAIN(16, BU27008_GSEL_16X),
GAIN_SCALE_GAIN(32, BU27008_GSEL_32X),
GAIN_SCALE_GAIN(64, BU27008_GSEL_64X),
GAIN_SCALE_GAIN(256, BU27008_GSEL_256X),
GAIN_SCALE_GAIN(512, BU27008_GSEL_512X),
GAIN_SCALE_GAIN(1024, BU27008_GSEL_1024X),
};
#define BU27010_GSEL_1X 0x00 /* 000000 */
#define BU27010_GSEL_4X 0x08 /* 001000 */
#define BU27010_GSEL_16X 0x09 /* 001001 */
#define BU27010_GSEL_64X 0x0e /* 001110 */
#define BU27010_GSEL_256X 0x1e /* 011110 */
#define BU27010_GSEL_1024X 0x2e /* 101110 */
#define BU27010_GSEL_4096X 0x3f /* 111111 */
static const struct iio_gain_sel_pair bu27010_gains[] = {
GAIN_SCALE_GAIN(1, BU27010_GSEL_1X),
GAIN_SCALE_GAIN(4, BU27010_GSEL_4X),
GAIN_SCALE_GAIN(16, BU27010_GSEL_16X),
GAIN_SCALE_GAIN(64, BU27010_GSEL_64X),
GAIN_SCALE_GAIN(256, BU27010_GSEL_256X),
GAIN_SCALE_GAIN(1024, BU27010_GSEL_1024X),
GAIN_SCALE_GAIN(4096, BU27010_GSEL_4096X),
};
static const struct iio_gain_sel_pair bu27010_gains_ir[] = {
GAIN_SCALE_GAIN(2, BU27010_GSEL_1X),
GAIN_SCALE_GAIN(4, BU27010_GSEL_4X),
GAIN_SCALE_GAIN(16, BU27010_GSEL_16X),
GAIN_SCALE_GAIN(64, BU27010_GSEL_64X),
GAIN_SCALE_GAIN(256, BU27010_GSEL_256X),
GAIN_SCALE_GAIN(1024, BU27010_GSEL_1024X),
GAIN_SCALE_GAIN(4096, BU27010_GSEL_4096X),
};
#define BU27008_MEAS_MODE_100MS 0x00
#define BU27008_MEAS_MODE_55MS 0x01
#define BU27008_MEAS_MODE_200MS 0x02
#define BU27008_MEAS_MODE_400MS 0x04
#define BU27010_MEAS_MODE_100MS 0x00
#define BU27010_MEAS_MODE_55MS 0x03
#define BU27010_MEAS_MODE_200MS 0x01
#define BU27010_MEAS_MODE_400MS 0x02
#define BU27008_MEAS_TIME_MAX_MS 400
static const struct iio_itime_sel_mul bu27008_itimes[] = {
GAIN_SCALE_ITIME_US(400000, BU27008_MEAS_MODE_400MS, 8),
GAIN_SCALE_ITIME_US(200000, BU27008_MEAS_MODE_200MS, 4),
GAIN_SCALE_ITIME_US(100000, BU27008_MEAS_MODE_100MS, 2),
GAIN_SCALE_ITIME_US(55000, BU27008_MEAS_MODE_55MS, 1),
};
static const struct iio_itime_sel_mul bu27010_itimes[] = {
GAIN_SCALE_ITIME_US(400000, BU27010_MEAS_MODE_400MS, 8),
GAIN_SCALE_ITIME_US(200000, BU27010_MEAS_MODE_200MS, 4),
GAIN_SCALE_ITIME_US(100000, BU27010_MEAS_MODE_100MS, 2),
GAIN_SCALE_ITIME_US(55000, BU27010_MEAS_MODE_55MS, 1),
};
/*
* All the RGBC channels share the same gain.
* IR gain can be fine-tuned from the gain set for the RGBC by 2 bit, but this
* would yield quite complex gain setting. Especially since not all bit
* compinations are supported. And in any case setting GAIN for RGBC will
* always also change the IR-gain.
*
* On top of this, the selector '0' which corresponds to hw-gain 1X on RGBC,
* corresponds to gain 2X on IR. Rest of the selctors correspond to same gains
* though. This, however, makes it not possible to use shared gain for all
* RGBC and IR settings even though they are all changed at the one go.
*/
#define BU27008_CHAN(color, data, separate_avail) \
{ \
.type = IIO_INTENSITY, \
.modified = 1, \
.channel2 = IIO_MOD_LIGHT_##color, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_separate_available = (separate_avail), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME), \
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME), \
.address = BU27008_REG_##data##_LO, \
.scan_index = BU27008_##color, \
.scan_type = { \
.sign = 'u', \
.realbits = 16, \
.storagebits = 16, \
.endianness = IIO_LE, \
}, \
}
/* For raw reads we always configure DATA3 for CLEAR */
static const struct iio_chan_spec bu27008_channels[] = {
BU27008_CHAN(RED, DATA0, BIT(IIO_CHAN_INFO_SCALE)),
BU27008_CHAN(GREEN, DATA1, BIT(IIO_CHAN_INFO_SCALE)),
BU27008_CHAN(BLUE, DATA2, BIT(IIO_CHAN_INFO_SCALE)),
BU27008_CHAN(CLEAR, DATA2, BIT(IIO_CHAN_INFO_SCALE)),
/*
* We don't allow setting scale for IR (because of shared gain bits).
* Hence we don't advertise available ones either.
*/
BU27008_CHAN(IR, DATA3, 0),
IIO_CHAN_SOFT_TIMESTAMP(BU27008_NUM_CHANS),
};
struct bu27008_data;
struct bu27_chip_data {
const char *name;
int (*chip_init)(struct bu27008_data *data);
int (*get_gain_sel)(struct bu27008_data *data, int *sel);
int (*write_gain_sel)(struct bu27008_data *data, int sel);
const struct regmap_config *regmap_cfg;
const struct iio_gain_sel_pair *gains;
const struct iio_gain_sel_pair *gains_ir;
const struct iio_itime_sel_mul *itimes;
int num_gains;
int num_gains_ir;
int num_itimes;
int scale1x;
int drdy_en_reg;
int drdy_en_mask;
int meas_en_reg;
int meas_en_mask;
int valid_reg;
int chan_sel_reg;
int chan_sel_mask;
int int_time_mask;
u8 part_id;
};
struct bu27008_data {
const struct bu27_chip_data *cd;
struct regmap *regmap;
struct iio_trigger *trig;
struct device *dev;
struct iio_gts gts;
struct iio_gts gts_ir;
int irq;
/*
* Prevent changing gain/time config when scale is read/written.
* Similarly, protect the integration_time read/change sequence.
* Prevent changing gain/time when data is read.
*/
struct mutex mutex;
};
static const struct regmap_range bu27008_volatile_ranges[] = {
{
.range_min = BU27008_REG_SYSTEM_CONTROL, /* SWRESET */
.range_max = BU27008_REG_SYSTEM_CONTROL,
}, {
.range_min = BU27008_REG_MODE_CONTROL3, /* VALID */
.range_max = BU27008_REG_MODE_CONTROL3,
}, {
.range_min = BU27008_REG_DATA0_LO, /* DATA */
.range_max = BU27008_REG_DATA3_HI,
},
};
static const struct regmap_range bu27010_volatile_ranges[] = {
{
.range_min = BU27010_REG_RESET, /* RSTB */
.range_max = BU27008_REG_SYSTEM_CONTROL, /* RESET */
}, {
.range_min = BU27010_REG_MODE_CONTROL5, /* VALID bits */
.range_max = BU27010_REG_MODE_CONTROL5,
}, {
.range_min = BU27008_REG_DATA0_LO,
.range_max = BU27010_REG_FIFO_DATA_HI,
},
};
static const struct regmap_access_table bu27008_volatile_regs = {
.yes_ranges = &bu27008_volatile_ranges[0],
.n_yes_ranges = ARRAY_SIZE(bu27008_volatile_ranges),
};
static const struct regmap_access_table bu27010_volatile_regs = {
.yes_ranges = &bu27010_volatile_ranges[0],
.n_yes_ranges = ARRAY_SIZE(bu27010_volatile_ranges),
};
static const struct regmap_range bu27008_read_only_ranges[] = {
{
.range_min = BU27008_REG_DATA0_LO,
.range_max = BU27008_REG_DATA3_HI,
}, {
.range_min = BU27008_REG_MANUFACTURER_ID,
.range_max = BU27008_REG_MANUFACTURER_ID,
},
};
static const struct regmap_range bu27010_read_only_ranges[] = {
{
.range_min = BU27008_REG_DATA0_LO,
.range_max = BU27010_REG_FIFO_DATA_HI,
}, {
.range_min = BU27010_REG_MANUFACTURER_ID,
.range_max = BU27010_REG_MANUFACTURER_ID,
}
};
static const struct regmap_access_table bu27008_ro_regs = {
.no_ranges = &bu27008_read_only_ranges[0],
.n_no_ranges = ARRAY_SIZE(bu27008_read_only_ranges),
};
static const struct regmap_access_table bu27010_ro_regs = {
.no_ranges = &bu27010_read_only_ranges[0],
.n_no_ranges = ARRAY_SIZE(bu27010_read_only_ranges),
};
static const struct regmap_config bu27008_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = BU27008_REG_MAX,
.cache_type = REGCACHE_RBTREE,
.volatile_table = &bu27008_volatile_regs,
.wr_table = &bu27008_ro_regs,
/*
* All register writes are serialized by the mutex which protects the
* scale setting/getting. This is needed because scale is combined by
* gain and integration time settings and we need to ensure those are
* not read / written when scale is being computed.
*
* As a result of this serializing, we don't need regmap locking. Note,
* this is not true if we add any configurations which are not
* serialized by the mutex and which may need for example a protected
* read-modify-write cycle (eg. regmap_update_bits()). Please, revise
* this when adding features to the driver.
*/
.disable_locking = true,
};
static const struct regmap_config bu27010_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = BU27010_REG_MAX,
.cache_type = REGCACHE_RBTREE,
.volatile_table = &bu27010_volatile_regs,
.wr_table = &bu27010_ro_regs,
.disable_locking = true,
};
static int bu27008_write_gain_sel(struct bu27008_data *data, int sel)
{
int regval;
regval = FIELD_PREP(BU27008_MASK_RGBC_GAIN, sel);
/*
* We do always set also the LOW bits of IR-gain because othervice we
* would risk resulting an invalid GAIN register value.
*
* We could allow setting separate gains for RGBC and IR when the
* values were such that HW could support both gain settings.
* Eg, when the shared bits were same for both gain values.
*
* This, however, has a negligible benefit compared to the increased
* software complexity when we would need to go through the gains
* for both channels separately when the integration time changes.
* This would end up with nasty logic for computing gain values for
* both channels - and rejecting them if shared bits changed.
*
* We should then build the logic by guessing what a user prefers.
* RGBC or IR gains correctly set while other jumps to odd value?
* Maybe look-up a value where both gains are somehow optimized
* <what this somehow is, is ATM unknown to us>. Or maybe user would
* expect us to reject changes when optimal gains can't be set to both
* channels w/given integration time. At best that would result
* solution that works well for a very specific subset of
* configurations but causes unexpected corner-cases.
*
* So, we keep it simple. Always set same selector to IR and RGBC.
* We disallow setting IR (as I expect that most of the users are
* interested in RGBC). This way we can show the user that the scales
* for RGBC and IR channels are different (1X Vs 2X with sel 0) while
* still keeping the operation deterministic.
*/
regval |= FIELD_PREP(BU27008_MASK_IR_GAIN_LO, sel);
return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL2,
BU27008_MASK_RGBC_GAIN, regval);
}
static int bu27010_write_gain_sel(struct bu27008_data *data, int sel)
{
unsigned int regval;
int ret, chan_selector;
/*
* Gain 'selector' is composed of two registers. Selector is 6bit value,
* 4 high bits being the RGBC gain fieild in MODE_CONTROL1 register and
* two low bits being the channel specific gain in MODE_CONTROL2.
*
* Let's take the 4 high bits of whole 6 bit selector, and prepare
* the MODE_CONTROL1 value (RGBC gain part).
*/
regval = FIELD_PREP(BU27010_MASK_RGBC_GAIN, (sel >> 2));
ret = regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL1,
BU27010_MASK_RGBC_GAIN, regval);
if (ret)
return ret;
/*
* Two low two bits of the selector must be written for all 4
* channels in the MODE_CONTROL2 register. Copy these two bits for
* all channels.
*/
chan_selector = sel & GENMASK(1, 0);
regval = FIELD_PREP(BU27010_MASK_DATA0_GAIN, chan_selector);
regval |= FIELD_PREP(BU27010_MASK_DATA1_GAIN, chan_selector);
regval |= FIELD_PREP(BU27010_MASK_DATA2_GAIN, chan_selector);
regval |= FIELD_PREP(BU27010_MASK_DATA3_GAIN, chan_selector);
return regmap_write(data->regmap, BU27008_REG_MODE_CONTROL2, regval);
}
static int bu27008_get_gain_sel(struct bu27008_data *data, int *sel)
{
int ret;
/*
* If we always "lock" the gain selectors for all channels to prevent
* unsupported configs, then it does not matter which channel is used
* we can just return selector from any of them.
*
* This, however is not true if we decide to support only 4X and 16X
* and then individual gains for channels. Currently this is not the
* case.
*
* If we some day decide to support individual gains, then we need to
* have channel information here.
*/
ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL2, sel);
if (ret)
return ret;
*sel = FIELD_GET(BU27008_MASK_RGBC_GAIN, *sel);
return 0;
}
static int bu27010_get_gain_sel(struct bu27008_data *data, int *sel)
{
int ret, tmp;
/*
* We always "lock" the gain selectors for all channels to prevent
* unsupported configs. It does not matter which channel is used
* we can just return selector from any of them.
*
* Read the channel0 gain.
*/
ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL2, sel);
if (ret)
return ret;
*sel = FIELD_GET(BU27010_MASK_DATA0_GAIN, *sel);
/* Read the shared gain */
ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL1, &tmp);
if (ret)
return ret;
/*
* The gain selector is made as a combination of common RGBC gain and
* the channel specific gain. The channel specific gain forms the low
* bits of selector and RGBC gain is appended right after it.
*
* Compose the selector from channel0 gain and shared RGBC gain.
*/
*sel |= FIELD_GET(BU27010_MASK_RGBC_GAIN, tmp) << fls(BU27010_MASK_DATA0_GAIN);
return ret;
}
static int bu27008_chip_init(struct bu27008_data *data)
{
int ret;
ret = regmap_write_bits(data->regmap, BU27008_REG_SYSTEM_CONTROL,
BU27008_MASK_SW_RESET, BU27008_MASK_SW_RESET);
if (ret)
return dev_err_probe(data->dev, ret, "Sensor reset failed\n");
/*
* The data-sheet does not tell how long performing the IC reset takes.
* However, the data-sheet says the minimum time it takes the IC to be
* able to take inputs after power is applied, is 100 uS. I'd assume
* > 1 mS is enough.
*/
msleep(1);
ret = regmap_reinit_cache(data->regmap, data->cd->regmap_cfg);
if (ret)
dev_err(data->dev, "Failed to reinit reg cache\n");
return ret;
}
static int bu27010_chip_init(struct bu27008_data *data)
{
int ret;
ret = regmap_write_bits(data->regmap, BU27008_REG_SYSTEM_CONTROL,
BU27010_MASK_SW_RESET, BU27010_MASK_SW_RESET);
if (ret)
return dev_err_probe(data->dev, ret, "Sensor reset failed\n");
msleep(1);
/* Power ON*/
ret = regmap_write_bits(data->regmap, BU27010_REG_POWER,
BU27010_MASK_POWER, BU27010_MASK_POWER);
if (ret)
return dev_err_probe(data->dev, ret, "Sensor power-on failed\n");
msleep(1);
/* Release blocks from reset */
ret = regmap_write_bits(data->regmap, BU27010_REG_RESET,
BU27010_MASK_RESET, BU27010_RESET_RELEASE);
if (ret)
return dev_err_probe(data->dev, ret, "Sensor powering failed\n");
msleep(1);
/*
* The IRQ enabling on BU27010 is done in a peculiar way. The IRQ
* enabling is not a bit mask where individual IRQs could be enabled but
* a field which values are:
* 00 => IRQs disabled
* 01 => Data-ready (RGBC/IR)
* 10 => Data-ready (flicker)
* 11 => Flicker FIFO
*
* So, only one IRQ can be enabled at a time and enabling for example
* flicker FIFO would automagically disable data-ready IRQ.
*
* Currently the driver does not support the flicker. Hence, we can
* just treat the RGBC data-ready as single bit which can be enabled /
* disabled. This works for as long as the second bit in the field
* stays zero. Here we ensure it gets zeroed.
*/
return regmap_clear_bits(data->regmap, BU27010_REG_MODE_CONTROL4,
BU27010_IRQ_DIS_ALL);
}
static const struct bu27_chip_data bu27010_chip = {
.name = "bu27010",
.chip_init = bu27010_chip_init,
.get_gain_sel = bu27010_get_gain_sel,
.write_gain_sel = bu27010_write_gain_sel,
.regmap_cfg = &bu27010_regmap,
.gains = &bu27010_gains[0],
.gains_ir = &bu27010_gains_ir[0],
.itimes = &bu27010_itimes[0],
.num_gains = ARRAY_SIZE(bu27010_gains),
.num_gains_ir = ARRAY_SIZE(bu27010_gains_ir),
.num_itimes = ARRAY_SIZE(bu27010_itimes),
.scale1x = BU27010_SCALE_1X,
.drdy_en_reg = BU27010_REG_MODE_CONTROL4,
.drdy_en_mask = BU27010_DRDY_EN,
.meas_en_reg = BU27010_REG_MODE_CONTROL5,
.meas_en_mask = BU27010_MASK_MEAS_EN,
.valid_reg = BU27010_REG_MODE_CONTROL5,
.chan_sel_reg = BU27008_REG_MODE_CONTROL1,
.chan_sel_mask = BU27010_MASK_CHAN_SEL,
.int_time_mask = BU27010_MASK_MEAS_MODE,
.part_id = BU27010_ID,
};
static const struct bu27_chip_data bu27008_chip = {
.name = "bu27008",
.chip_init = bu27008_chip_init,
.get_gain_sel = bu27008_get_gain_sel,
.write_gain_sel = bu27008_write_gain_sel,
.regmap_cfg = &bu27008_regmap,
.gains = &bu27008_gains[0],
.gains_ir = &bu27008_gains_ir[0],
.itimes = &bu27008_itimes[0],
.num_gains = ARRAY_SIZE(bu27008_gains),
.num_gains_ir = ARRAY_SIZE(bu27008_gains_ir),
.num_itimes = ARRAY_SIZE(bu27008_itimes),
.scale1x = BU27008_SCALE_1X,
.drdy_en_reg = BU27008_REG_MODE_CONTROL3,
.drdy_en_mask = BU27008_MASK_INT_EN,
.valid_reg = BU27008_REG_MODE_CONTROL3,
.meas_en_reg = BU27008_REG_MODE_CONTROL3,
.meas_en_mask = BU27008_MASK_MEAS_EN,
.chan_sel_reg = BU27008_REG_MODE_CONTROL3,
.chan_sel_mask = BU27008_MASK_CHAN_SEL,
.int_time_mask = BU27008_MASK_MEAS_MODE,
.part_id = BU27008_ID,
};
#define BU27008_MAX_VALID_RESULT_WAIT_US 50000
#define BU27008_VALID_RESULT_WAIT_QUANTA_US 1000
static int bu27008_chan_read_data(struct bu27008_data *data, int reg, int *val)
{
int ret, valid;
__le16 tmp;
ret = regmap_read_poll_timeout(data->regmap, data->cd->valid_reg,
valid, (valid & BU27008_MASK_VALID),
BU27008_VALID_RESULT_WAIT_QUANTA_US,
BU27008_MAX_VALID_RESULT_WAIT_US);
if (ret)
return ret;
ret = regmap_bulk_read(data->regmap, reg, &tmp, sizeof(tmp));
if (ret)
dev_err(data->dev, "Reading channel data failed\n");
*val = le16_to_cpu(tmp);
return ret;
}
static int bu27008_get_gain(struct bu27008_data *data, struct iio_gts *gts, int *gain)
{
int ret, sel;
ret = data->cd->get_gain_sel(data, &sel);
if (ret)
return ret;
ret = iio_gts_find_gain_by_sel(gts, sel);
if (ret < 0) {
dev_err(data->dev, "unknown gain value 0x%x\n", sel);
return ret;
}
*gain = ret;
return 0;
}
static int bu27008_set_gain(struct bu27008_data *data, int gain)
{
int ret;
ret = iio_gts_find_sel_by_gain(&data->gts, gain);
if (ret < 0)
return ret;
return data->cd->write_gain_sel(data, ret);
}
static int bu27008_get_int_time_sel(struct bu27008_data *data, int *sel)
{
int ret, val;
ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL1, &val);
if (ret)
return ret;
val &= data->cd->int_time_mask;
val >>= ffs(data->cd->int_time_mask) - 1;
*sel = val;
return 0;
}
static int bu27008_set_int_time_sel(struct bu27008_data *data, int sel)
{
sel <<= ffs(data->cd->int_time_mask) - 1;
return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL1,
data->cd->int_time_mask, sel);
}
static int bu27008_get_int_time_us(struct bu27008_data *data)
{
int ret, sel;
ret = bu27008_get_int_time_sel(data, &sel);
if (ret)
return ret;
return iio_gts_find_int_time_by_sel(&data->gts, sel);
}
static int _bu27008_get_scale(struct bu27008_data *data, bool ir, int *val,
int *val2)
{
struct iio_gts *gts;
int gain, ret;
if (ir)
gts = &data->gts_ir;
else
gts = &data->gts;
ret = bu27008_get_gain(data, gts, &gain);
if (ret)
return ret;
ret = bu27008_get_int_time_us(data);
if (ret < 0)
return ret;
return iio_gts_get_scale(gts, gain, ret, val, val2);
}
static int bu27008_get_scale(struct bu27008_data *data, bool ir, int *val,
int *val2)
{
int ret;
mutex_lock(&data->mutex);
ret = _bu27008_get_scale(data, ir, val, val2);
mutex_unlock(&data->mutex);
return ret;
}
static int bu27008_set_int_time(struct bu27008_data *data, int time)
{
int ret;
ret = iio_gts_find_sel_by_int_time(&data->gts, time);
if (ret < 0)
return ret;
return bu27008_set_int_time_sel(data, ret);
}
/* Try to change the time so that the scale is maintained */
static int bu27008_try_set_int_time(struct bu27008_data *data, int int_time_new)
{
int ret, old_time_sel, new_time_sel, old_gain, new_gain;
mutex_lock(&data->mutex);
ret = bu27008_get_int_time_sel(data, &old_time_sel);
if (ret < 0)
goto unlock_out;
if (!iio_gts_valid_time(&data->gts, int_time_new)) {
dev_dbg(data->dev, "Unsupported integration time %u\n",
int_time_new);
ret = -EINVAL;
goto unlock_out;
}
/* If we already use requested time, then we're done */
new_time_sel = iio_gts_find_sel_by_int_time(&data->gts, int_time_new);
if (new_time_sel == old_time_sel)
goto unlock_out;
ret = bu27008_get_gain(data, &data->gts, &old_gain);
if (ret)
goto unlock_out;
ret = iio_gts_find_new_gain_sel_by_old_gain_time(&data->gts, old_gain,
old_time_sel, new_time_sel, &new_gain);
if (ret) {
int scale1, scale2;
bool ok;
_bu27008_get_scale(data, false, &scale1, &scale2);
dev_dbg(data->dev,
"Can't support time %u with current scale %u %u\n",
int_time_new, scale1, scale2);
if (new_gain < 0)
goto unlock_out;
/*
* If caller requests for integration time change and we
* can't support the scale - then the caller should be
* prepared to 'pick up the pieces and deal with the
* fact that the scale changed'.
*/
ret = iio_find_closest_gain_low(&data->gts, new_gain, &ok);
if (!ok)
dev_dbg(data->dev, "optimal gain out of range\n");
if (ret < 0) {
dev_dbg(data->dev,
"Total gain increase. Risk of saturation");
ret = iio_gts_get_min_gain(&data->gts);
if (ret < 0)
goto unlock_out;
}
new_gain = ret;
dev_dbg(data->dev, "scale changed, new gain %u\n", new_gain);
}
ret = bu27008_set_gain(data, new_gain);
if (ret)
goto unlock_out;
ret = bu27008_set_int_time(data, int_time_new);
unlock_out:
mutex_unlock(&data->mutex);
return ret;
}
static int bu27008_meas_set(struct bu27008_data *data, bool enable)
{
if (enable)
return regmap_set_bits(data->regmap, data->cd->meas_en_reg,
data->cd->meas_en_mask);
return regmap_clear_bits(data->regmap, data->cd->meas_en_reg,
data->cd->meas_en_mask);
}
static int bu27008_chan_cfg(struct bu27008_data *data,
struct iio_chan_spec const *chan)
{
int chan_sel;
if (chan->scan_index == BU27008_BLUE)
chan_sel = BU27008_BLUE2_CLEAR3;
else
chan_sel = BU27008_CLEAR2_IR3;
/*
* prepare bitfield for channel sel. The FIELD_PREP works only when
* mask is constant. In our case the mask is assigned based on the
* chip type. Hence the open-coded FIELD_PREP here. We don't bother
* zeroing the irrelevant bits though - update_bits takes care of that.
*/
chan_sel <<= ffs(data->cd->chan_sel_mask) - 1;
return regmap_update_bits(data->regmap, data->cd->chan_sel_reg,
BU27008_MASK_CHAN_SEL, chan_sel);
}
static int bu27008_read_one(struct bu27008_data *data, struct iio_dev *idev,
struct iio_chan_spec const *chan, int *val, int *val2)
{
int ret, int_time;
ret = bu27008_chan_cfg(data, chan);
if (ret)
return ret;
ret = bu27008_meas_set(data, true);
if (ret)
return ret;
ret = bu27008_get_int_time_us(data);
if (ret < 0)
int_time = BU27008_MEAS_TIME_MAX_MS;
else
int_time = ret / USEC_PER_MSEC;
msleep(int_time);
ret = bu27008_chan_read_data(data, chan->address, val);
if (!ret)
ret = IIO_VAL_INT;
if (bu27008_meas_set(data, false))
dev_warn(data->dev, "measurement disabling failed\n");
return ret;
}
static int bu27008_read_raw(struct iio_dev *idev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct bu27008_data *data = iio_priv(idev);
int busy, ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
busy = iio_device_claim_direct_mode(idev);
if (busy)
return -EBUSY;
mutex_lock(&data->mutex);
ret = bu27008_read_one(data, idev, chan, val, val2);
mutex_unlock(&data->mutex);
iio_device_release_direct_mode(idev);
return ret;
case IIO_CHAN_INFO_SCALE:
ret = bu27008_get_scale(data, chan->scan_index == BU27008_IR,
val, val2);
if (ret)
return ret;
return IIO_VAL_INT_PLUS_NANO;
case IIO_CHAN_INFO_INT_TIME:
ret = bu27008_get_int_time_us(data);
if (ret < 0)
return ret;
*val = 0;
*val2 = ret;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
/* Called if the new scale could not be supported with existing int-time */
static int bu27008_try_find_new_time_gain(struct bu27008_data *data, int val,
int val2, int *gain_sel)
{
int i, ret, new_time_sel;
for (i = 0; i < data->gts.num_itime; i++) {
new_time_sel = data->gts.itime_table[i].sel;
ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts,
new_time_sel, val, val2, gain_sel);
if (!ret)
break;
}
if (i == data->gts.num_itime) {
dev_err(data->dev, "Can't support scale %u %u\n", val, val2);
return -EINVAL;
}
return bu27008_set_int_time_sel(data, new_time_sel);
}
static int bu27008_set_scale(struct bu27008_data *data,
struct iio_chan_spec const *chan,
int val, int val2)
{
int ret, gain_sel, time_sel;
if (chan->scan_index == BU27008_IR)
return -EINVAL;
mutex_lock(&data->mutex);
ret = bu27008_get_int_time_sel(data, &time_sel);
if (ret < 0)
goto unlock_out;
ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts, time_sel,
val, val2, &gain_sel);
if (ret) {
ret = bu27008_try_find_new_time_gain(data, val, val2, &gain_sel);
if (ret)
goto unlock_out;
}
ret = data->cd->write_gain_sel(data, gain_sel);
unlock_out:
mutex_unlock(&data->mutex);
return ret;
}
static int bu27008_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_SCALE:
return IIO_VAL_INT_PLUS_NANO;
case IIO_CHAN_INFO_INT_TIME:
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int bu27008_write_raw(struct iio_dev *idev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct bu27008_data *data = iio_priv(idev);
int ret;
/*
* Do not allow changing scale when measurement is ongoing as doing so
* could make values in the buffer inconsistent.
*/
ret = iio_device_claim_direct_mode(idev);
if (ret)
return ret;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
ret = bu27008_set_scale(data, chan, val, val2);
break;
case IIO_CHAN_INFO_INT_TIME:
if (val) {
ret = -EINVAL;
break;
}
ret = bu27008_try_set_int_time(data, val2);
break;
default:
ret = -EINVAL;
break;
}
iio_device_release_direct_mode(idev);
return ret;
}
static int bu27008_read_avail(struct iio_dev *idev,
struct iio_chan_spec const *chan, const int **vals,
int *type, int *length, long mask)
{
struct bu27008_data *data = iio_priv(idev);
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
return iio_gts_avail_times(&data->gts, vals, type, length);
case IIO_CHAN_INFO_SCALE:
if (chan->channel2 == IIO_MOD_LIGHT_IR)
return iio_gts_all_avail_scales(&data->gts_ir, vals,
type, length);
return iio_gts_all_avail_scales(&data->gts, vals, type, length);
default:
return -EINVAL;
}
}
static int bu27008_update_scan_mode(struct iio_dev *idev,
const unsigned long *scan_mask)
{
struct bu27008_data *data = iio_priv(idev);
int chan_sel;
/* Configure channel selection */
if (test_bit(BU27008_BLUE, idev->active_scan_mask)) {
if (test_bit(BU27008_CLEAR, idev->active_scan_mask))
chan_sel = BU27008_BLUE2_CLEAR3;
else
chan_sel = BU27008_BLUE2_IR3;
} else {
chan_sel = BU27008_CLEAR2_IR3;
}
chan_sel <<= ffs(data->cd->chan_sel_mask) - 1;
return regmap_update_bits(data->regmap, data->cd->chan_sel_reg,
data->cd->chan_sel_mask, chan_sel);
}
static const struct iio_info bu27008_info = {
.read_raw = &bu27008_read_raw,
.write_raw = &bu27008_write_raw,
.write_raw_get_fmt = &bu27008_write_raw_get_fmt,
.read_avail = &bu27008_read_avail,
.update_scan_mode = bu27008_update_scan_mode,
.validate_trigger = iio_validate_own_trigger,
};
static int bu27008_trigger_set_state(struct iio_trigger *trig, bool state)
{
struct bu27008_data *data = iio_trigger_get_drvdata(trig);
int ret;
if (state)
ret = regmap_set_bits(data->regmap, data->cd->drdy_en_reg,
data->cd->drdy_en_mask);
else
ret = regmap_clear_bits(data->regmap, data->cd->drdy_en_reg,
data->cd->drdy_en_mask);
if (ret)
dev_err(data->dev, "Failed to set trigger state\n");
return ret;
}
static void bu27008_trigger_reenable(struct iio_trigger *trig)
{
struct bu27008_data *data = iio_trigger_get_drvdata(trig);
enable_irq(data->irq);
}
static const struct iio_trigger_ops bu27008_trigger_ops = {
.set_trigger_state = bu27008_trigger_set_state,
.reenable = bu27008_trigger_reenable,
};
static irqreturn_t bu27008_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *idev = pf->indio_dev;
struct bu27008_data *data = iio_priv(idev);
struct {
__le16 chan[BU27008_NUM_HW_CHANS];
s64 ts __aligned(8);
} raw;
int ret, dummy;
memset(&raw, 0, sizeof(raw));
/*
* After some measurements, it seems reading the
* BU27008_REG_MODE_CONTROL3 debounces the IRQ line
*/
ret = regmap_read(data->regmap, data->cd->valid_reg, &dummy);
if (ret < 0)
goto err_read;
ret = regmap_bulk_read(data->regmap, BU27008_REG_DATA0_LO, &raw.chan,
sizeof(raw.chan));
if (ret < 0)
goto err_read;
iio_push_to_buffers_with_timestamp(idev, &raw, pf->timestamp);
err_read:
iio_trigger_notify_done(idev->trig);
return IRQ_HANDLED;
}
static int bu27008_buffer_preenable(struct iio_dev *idev)
{
struct bu27008_data *data = iio_priv(idev);
return bu27008_meas_set(data, true);
}
static int bu27008_buffer_postdisable(struct iio_dev *idev)
{
struct bu27008_data *data = iio_priv(idev);
return bu27008_meas_set(data, false);
}
static const struct iio_buffer_setup_ops bu27008_buffer_ops = {
.preenable = bu27008_buffer_preenable,
.postdisable = bu27008_buffer_postdisable,
};
static irqreturn_t bu27008_data_rdy_poll(int irq, void *private)
{
/*
* The BU27008 keeps IRQ asserted until we read the VALID bit from
* a register. We need to keep the IRQ disabled until then.
*/
disable_irq_nosync(irq);
iio_trigger_poll(private);
return IRQ_HANDLED;
}
static int bu27008_setup_trigger(struct bu27008_data *data, struct iio_dev *idev)
{
struct iio_trigger *itrig;
char *name;
int ret;
ret = devm_iio_triggered_buffer_setup(data->dev, idev,
&iio_pollfunc_store_time,
bu27008_trigger_handler,
&bu27008_buffer_ops);
if (ret)
return dev_err_probe(data->dev, ret,
"iio_triggered_buffer_setup_ext FAIL\n");
itrig = devm_iio_trigger_alloc(data->dev, "%sdata-rdy-dev%d",
idev->name, iio_device_id(idev));
if (!itrig)
return -ENOMEM;
data->trig = itrig;
itrig->ops = &bu27008_trigger_ops;
iio_trigger_set_drvdata(itrig, data);
name = devm_kasprintf(data->dev, GFP_KERNEL, "%s-bu27008",
dev_name(data->dev));
ret = devm_request_irq(data->dev, data->irq,
&bu27008_data_rdy_poll,
0, name, itrig);
if (ret)
return dev_err_probe(data->dev, ret, "Could not request IRQ\n");
ret = devm_iio_trigger_register(data->dev, itrig);
if (ret)
return dev_err_probe(data->dev, ret,
"Trigger registration failed\n");
/* set default trigger */
idev->trig = iio_trigger_get(itrig);
return 0;
}
static int bu27008_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct bu27008_data *data;
struct regmap *regmap;
unsigned int part_id, reg;
struct iio_dev *idev;
int ret;
idev = devm_iio_device_alloc(dev, sizeof(*data));
if (!idev)
return -ENOMEM;
ret = devm_regulator_get_enable(dev, "vdd");
if (ret)
return dev_err_probe(dev, ret, "Failed to get regulator\n");
data = iio_priv(idev);
data->cd = device_get_match_data(&i2c->dev);
if (!data->cd)
return -ENODEV;
regmap = devm_regmap_init_i2c(i2c, data->cd->regmap_cfg);
if (IS_ERR(regmap))
return dev_err_probe(dev, PTR_ERR(regmap),
"Failed to initialize Regmap\n");
ret = regmap_read(regmap, BU27008_REG_SYSTEM_CONTROL, ®);
if (ret)
return dev_err_probe(dev, ret, "Failed to access sensor\n");
part_id = FIELD_GET(BU27008_MASK_PART_ID, reg);
if (part_id != data->cd->part_id)
dev_warn(dev, "unknown device 0x%x\n", part_id);
ret = devm_iio_init_iio_gts(dev, data->cd->scale1x, 0, data->cd->gains,
data->cd->num_gains, data->cd->itimes,
data->cd->num_itimes, &data->gts);
if (ret)
return ret;
ret = devm_iio_init_iio_gts(dev, data->cd->scale1x, 0, data->cd->gains_ir,
data->cd->num_gains_ir, data->cd->itimes,
data->cd->num_itimes, &data->gts_ir);
if (ret)
return ret;
mutex_init(&data->mutex);
data->regmap = regmap;
data->dev = dev;
data->irq = i2c->irq;
idev->channels = bu27008_channels;
idev->num_channels = ARRAY_SIZE(bu27008_channels);
idev->name = data->cd->name;
idev->info = &bu27008_info;
idev->modes = INDIO_DIRECT_MODE;
idev->available_scan_masks = bu27008_scan_masks;
ret = data->cd->chip_init(data);
if (ret)
return ret;
if (i2c->irq) {
ret = bu27008_setup_trigger(data, idev);
if (ret)
return ret;
} else {
dev_info(dev, "No IRQ, buffered mode disabled\n");
}
ret = devm_iio_device_register(dev, idev);
if (ret)
return dev_err_probe(dev, ret,
"Unable to register iio device\n");
return 0;
}
static const struct of_device_id bu27008_of_match[] = {
{ .compatible = "rohm,bu27008", .data = &bu27008_chip },
{ .compatible = "rohm,bu27010", .data = &bu27010_chip },
{ }
};
MODULE_DEVICE_TABLE(of, bu27008_of_match);
static struct i2c_driver bu27008_i2c_driver = {
.driver = {
.name = "bu27008",
.of_match_table = bu27008_of_match,
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
.probe = bu27008_probe,
};
module_i2c_driver(bu27008_i2c_driver);
MODULE_DESCRIPTION("ROHM BU27008 and BU27010 colour sensor driver");
MODULE_AUTHOR("Matti Vaittinen <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(IIO_GTS_HELPER);
| linux-master | drivers/iio/light/rohm-bu27008.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* VEML6030 Ambient Light Sensor
*
* Copyright (c) 2019, Rishi Gupta <[email protected]>
*
* Datasheet: https://www.vishay.com/docs/84366/veml6030.pdf
* Appnote-84367: https://www.vishay.com/docs/84367/designingveml6030.pdf
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/regmap.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
/* Device registers */
#define VEML6030_REG_ALS_CONF 0x00
#define VEML6030_REG_ALS_WH 0x01
#define VEML6030_REG_ALS_WL 0x02
#define VEML6030_REG_ALS_PSM 0x03
#define VEML6030_REG_ALS_DATA 0x04
#define VEML6030_REG_WH_DATA 0x05
#define VEML6030_REG_ALS_INT 0x06
/* Bit masks for specific functionality */
#define VEML6030_ALS_IT GENMASK(9, 6)
#define VEML6030_PSM GENMASK(2, 1)
#define VEML6030_ALS_PERS GENMASK(5, 4)
#define VEML6030_ALS_GAIN GENMASK(12, 11)
#define VEML6030_PSM_EN BIT(0)
#define VEML6030_INT_TH_LOW BIT(15)
#define VEML6030_INT_TH_HIGH BIT(14)
#define VEML6030_ALS_INT_EN BIT(1)
#define VEML6030_ALS_SD BIT(0)
/*
* The resolution depends on both gain and integration time. The
* cur_resolution stores one of the resolution mentioned in the
* table during startup and gets updated whenever integration time
* or gain is changed.
*
* Table 'resolution and maximum detection range' in appnote 84367
* is visualized as a 2D array. The cur_gain stores index of gain
* in this table (0-3) while the cur_integration_time holds index
* of integration time (0-5).
*/
struct veml6030_data {
struct i2c_client *client;
struct regmap *regmap;
int cur_resolution;
int cur_gain;
int cur_integration_time;
};
/* Integration time available in seconds */
static IIO_CONST_ATTR(in_illuminance_integration_time_available,
"0.025 0.05 0.1 0.2 0.4 0.8");
/*
* Scale is 1/gain. Value 0.125 is ALS gain x (1/8), 0.25 is
* ALS gain x (1/4), 1.0 = ALS gain x 1 and 2.0 is ALS gain x 2.
*/
static IIO_CONST_ATTR(in_illuminance_scale_available,
"0.125 0.25 1.0 2.0");
static struct attribute *veml6030_attributes[] = {
&iio_const_attr_in_illuminance_integration_time_available.dev_attr.attr,
&iio_const_attr_in_illuminance_scale_available.dev_attr.attr,
NULL
};
static const struct attribute_group veml6030_attr_group = {
.attrs = veml6030_attributes,
};
/*
* Persistence = 1/2/4/8 x integration time
* Minimum time for which light readings must stay above configured
* threshold to assert the interrupt.
*/
static const char * const period_values[] = {
"0.1 0.2 0.4 0.8",
"0.2 0.4 0.8 1.6",
"0.4 0.8 1.6 3.2",
"0.8 1.6 3.2 6.4",
"0.05 0.1 0.2 0.4",
"0.025 0.050 0.1 0.2"
};
/*
* Return list of valid period values in seconds corresponding to
* the currently active integration time.
*/
static ssize_t in_illuminance_period_available_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int ret, reg, x;
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct veml6030_data *data = iio_priv(indio_dev);
ret = regmap_read(data->regmap, VEML6030_REG_ALS_CONF, ®);
if (ret) {
dev_err(&data->client->dev,
"can't read als conf register %d\n", ret);
return ret;
}
ret = ((reg >> 6) & 0xF);
switch (ret) {
case 0:
case 1:
case 2:
case 3:
x = ret;
break;
case 8:
x = 4;
break;
case 12:
x = 5;
break;
default:
return -EINVAL;
}
return sysfs_emit(buf, "%s\n", period_values[x]);
}
static IIO_DEVICE_ATTR_RO(in_illuminance_period_available, 0);
static struct attribute *veml6030_event_attributes[] = {
&iio_dev_attr_in_illuminance_period_available.dev_attr.attr,
NULL
};
static const struct attribute_group veml6030_event_attr_group = {
.attrs = veml6030_event_attributes,
};
static int veml6030_als_pwr_on(struct veml6030_data *data)
{
return regmap_update_bits(data->regmap, VEML6030_REG_ALS_CONF,
VEML6030_ALS_SD, 0);
}
static int veml6030_als_shut_down(struct veml6030_data *data)
{
return regmap_update_bits(data->regmap, VEML6030_REG_ALS_CONF,
VEML6030_ALS_SD, 1);
}
static void veml6030_als_shut_down_action(void *data)
{
veml6030_als_shut_down(data);
}
static const struct iio_event_spec veml6030_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_PERIOD) |
BIT(IIO_EV_INFO_ENABLE),
},
};
/* Channel number */
enum veml6030_chan {
CH_ALS,
CH_WHITE,
};
static const struct iio_chan_spec veml6030_channels[] = {
{
.type = IIO_LIGHT,
.channel = CH_ALS,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_SCALE),
.event_spec = veml6030_event_spec,
.num_event_specs = ARRAY_SIZE(veml6030_event_spec),
},
{
.type = IIO_INTENSITY,
.channel = CH_WHITE,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_BOTH,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_PROCESSED),
},
};
static const struct regmap_config veml6030_regmap_config = {
.name = "veml6030_regmap",
.reg_bits = 8,
.val_bits = 16,
.max_register = VEML6030_REG_ALS_INT,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
};
static int veml6030_get_intgrn_tm(struct iio_dev *indio_dev,
int *val, int *val2)
{
int ret, reg;
struct veml6030_data *data = iio_priv(indio_dev);
ret = regmap_read(data->regmap, VEML6030_REG_ALS_CONF, ®);
if (ret) {
dev_err(&data->client->dev,
"can't read als conf register %d\n", ret);
return ret;
}
switch ((reg >> 6) & 0xF) {
case 0:
*val2 = 100000;
break;
case 1:
*val2 = 200000;
break;
case 2:
*val2 = 400000;
break;
case 3:
*val2 = 800000;
break;
case 8:
*val2 = 50000;
break;
case 12:
*val2 = 25000;
break;
default:
return -EINVAL;
}
*val = 0;
return IIO_VAL_INT_PLUS_MICRO;
}
static int veml6030_set_intgrn_tm(struct iio_dev *indio_dev,
int val, int val2)
{
int ret, new_int_time, int_idx;
struct veml6030_data *data = iio_priv(indio_dev);
if (val)
return -EINVAL;
switch (val2) {
case 25000:
new_int_time = 0x300;
int_idx = 5;
break;
case 50000:
new_int_time = 0x200;
int_idx = 4;
break;
case 100000:
new_int_time = 0x00;
int_idx = 3;
break;
case 200000:
new_int_time = 0x40;
int_idx = 2;
break;
case 400000:
new_int_time = 0x80;
int_idx = 1;
break;
case 800000:
new_int_time = 0xC0;
int_idx = 0;
break;
default:
return -EINVAL;
}
ret = regmap_update_bits(data->regmap, VEML6030_REG_ALS_CONF,
VEML6030_ALS_IT, new_int_time);
if (ret) {
dev_err(&data->client->dev,
"can't update als integration time %d\n", ret);
return ret;
}
/*
* Cache current integration time and update resolution. For every
* increase in integration time to next level, resolution is halved
* and vice-versa.
*/
if (data->cur_integration_time < int_idx)
data->cur_resolution <<= int_idx - data->cur_integration_time;
else if (data->cur_integration_time > int_idx)
data->cur_resolution >>= data->cur_integration_time - int_idx;
data->cur_integration_time = int_idx;
return ret;
}
static int veml6030_read_persistence(struct iio_dev *indio_dev,
int *val, int *val2)
{
int ret, reg, period, x, y;
struct veml6030_data *data = iio_priv(indio_dev);
ret = veml6030_get_intgrn_tm(indio_dev, &x, &y);
if (ret < 0)
return ret;
ret = regmap_read(data->regmap, VEML6030_REG_ALS_CONF, ®);
if (ret) {
dev_err(&data->client->dev,
"can't read als conf register %d\n", ret);
}
/* integration time multiplied by 1/2/4/8 */
period = y * (1 << ((reg >> 4) & 0x03));
*val = period / 1000000;
*val2 = period % 1000000;
return IIO_VAL_INT_PLUS_MICRO;
}
static int veml6030_write_persistence(struct iio_dev *indio_dev,
int val, int val2)
{
int ret, period, x, y;
struct veml6030_data *data = iio_priv(indio_dev);
ret = veml6030_get_intgrn_tm(indio_dev, &x, &y);
if (ret < 0)
return ret;
if (!val) {
period = val2 / y;
} else {
if ((val == 1) && (val2 == 600000))
period = 1600000 / y;
else if ((val == 3) && (val2 == 200000))
period = 3200000 / y;
else if ((val == 6) && (val2 == 400000))
period = 6400000 / y;
else
period = -1;
}
if (period <= 0 || period > 8 || hweight8(period) != 1)
return -EINVAL;
ret = regmap_update_bits(data->regmap, VEML6030_REG_ALS_CONF,
VEML6030_ALS_PERS, (ffs(period) - 1) << 4);
if (ret)
dev_err(&data->client->dev,
"can't set persistence value %d\n", ret);
return ret;
}
static int veml6030_set_als_gain(struct iio_dev *indio_dev,
int val, int val2)
{
int ret, new_gain, gain_idx;
struct veml6030_data *data = iio_priv(indio_dev);
if (val == 0 && val2 == 125000) {
new_gain = 0x1000; /* 0x02 << 11 */
gain_idx = 3;
} else if (val == 0 && val2 == 250000) {
new_gain = 0x1800;
gain_idx = 2;
} else if (val == 1 && val2 == 0) {
new_gain = 0x00;
gain_idx = 1;
} else if (val == 2 && val2 == 0) {
new_gain = 0x800;
gain_idx = 0;
} else {
return -EINVAL;
}
ret = regmap_update_bits(data->regmap, VEML6030_REG_ALS_CONF,
VEML6030_ALS_GAIN, new_gain);
if (ret) {
dev_err(&data->client->dev,
"can't set als gain %d\n", ret);
return ret;
}
/*
* Cache currently set gain & update resolution. For every
* increase in the gain to next level, resolution is halved
* and vice-versa.
*/
if (data->cur_gain < gain_idx)
data->cur_resolution <<= gain_idx - data->cur_gain;
else if (data->cur_gain > gain_idx)
data->cur_resolution >>= data->cur_gain - gain_idx;
data->cur_gain = gain_idx;
return ret;
}
static int veml6030_get_als_gain(struct iio_dev *indio_dev,
int *val, int *val2)
{
int ret, reg;
struct veml6030_data *data = iio_priv(indio_dev);
ret = regmap_read(data->regmap, VEML6030_REG_ALS_CONF, ®);
if (ret) {
dev_err(&data->client->dev,
"can't read als conf register %d\n", ret);
return ret;
}
switch ((reg >> 11) & 0x03) {
case 0:
*val = 1;
*val2 = 0;
break;
case 1:
*val = 2;
*val2 = 0;
break;
case 2:
*val = 0;
*val2 = 125000;
break;
case 3:
*val = 0;
*val2 = 250000;
break;
default:
return -EINVAL;
}
return IIO_VAL_INT_PLUS_MICRO;
}
static int veml6030_read_thresh(struct iio_dev *indio_dev,
int *val, int *val2, int dir)
{
int ret, reg;
struct veml6030_data *data = iio_priv(indio_dev);
if (dir == IIO_EV_DIR_RISING)
ret = regmap_read(data->regmap, VEML6030_REG_ALS_WH, ®);
else
ret = regmap_read(data->regmap, VEML6030_REG_ALS_WL, ®);
if (ret) {
dev_err(&data->client->dev,
"can't read als threshold value %d\n", ret);
return ret;
}
*val = reg & 0xffff;
return IIO_VAL_INT;
}
static int veml6030_write_thresh(struct iio_dev *indio_dev,
int val, int val2, int dir)
{
int ret;
struct veml6030_data *data = iio_priv(indio_dev);
if (val > 0xFFFF || val < 0 || val2)
return -EINVAL;
if (dir == IIO_EV_DIR_RISING) {
ret = regmap_write(data->regmap, VEML6030_REG_ALS_WH, val);
if (ret)
dev_err(&data->client->dev,
"can't set high threshold %d\n", ret);
} else {
ret = regmap_write(data->regmap, VEML6030_REG_ALS_WL, val);
if (ret)
dev_err(&data->client->dev,
"can't set low threshold %d\n", ret);
}
return ret;
}
/*
* Provide both raw as well as light reading in lux.
* light (in lux) = resolution * raw reading
*/
static int veml6030_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
int ret, reg;
struct veml6030_data *data = iio_priv(indio_dev);
struct regmap *regmap = data->regmap;
struct device *dev = &data->client->dev;
switch (mask) {
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_LIGHT:
ret = regmap_read(regmap, VEML6030_REG_ALS_DATA, ®);
if (ret < 0) {
dev_err(dev, "can't read als data %d\n", ret);
return ret;
}
if (mask == IIO_CHAN_INFO_PROCESSED) {
*val = (reg * data->cur_resolution) / 10000;
*val2 = (reg * data->cur_resolution) % 10000;
return IIO_VAL_INT_PLUS_MICRO;
}
*val = reg;
return IIO_VAL_INT;
case IIO_INTENSITY:
ret = regmap_read(regmap, VEML6030_REG_WH_DATA, ®);
if (ret < 0) {
dev_err(dev, "can't read white data %d\n", ret);
return ret;
}
if (mask == IIO_CHAN_INFO_PROCESSED) {
*val = (reg * data->cur_resolution) / 10000;
*val2 = (reg * data->cur_resolution) % 10000;
return IIO_VAL_INT_PLUS_MICRO;
}
*val = reg;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_INT_TIME:
if (chan->type == IIO_LIGHT)
return veml6030_get_intgrn_tm(indio_dev, val, val2);
return -EINVAL;
case IIO_CHAN_INFO_SCALE:
if (chan->type == IIO_LIGHT)
return veml6030_get_als_gain(indio_dev, val, val2);
return -EINVAL;
default:
return -EINVAL;
}
}
static int veml6030_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
switch (chan->type) {
case IIO_LIGHT:
return veml6030_set_intgrn_tm(indio_dev, val, val2);
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_LIGHT:
return veml6030_set_als_gain(indio_dev, val, val2);
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int veml6030_read_event_val(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info,
int *val, int *val2)
{
switch (info) {
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
case IIO_EV_DIR_FALLING:
return veml6030_read_thresh(indio_dev, val, val2, dir);
default:
return -EINVAL;
}
break;
case IIO_EV_INFO_PERIOD:
return veml6030_read_persistence(indio_dev, val, val2);
default:
return -EINVAL;
}
}
static int veml6030_write_event_val(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info,
int val, int val2)
{
switch (info) {
case IIO_EV_INFO_VALUE:
return veml6030_write_thresh(indio_dev, val, val2, dir);
case IIO_EV_INFO_PERIOD:
return veml6030_write_persistence(indio_dev, val, val2);
default:
return -EINVAL;
}
}
static int veml6030_read_interrupt_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir)
{
int ret, reg;
struct veml6030_data *data = iio_priv(indio_dev);
ret = regmap_read(data->regmap, VEML6030_REG_ALS_CONF, ®);
if (ret) {
dev_err(&data->client->dev,
"can't read als conf register %d\n", ret);
return ret;
}
if (reg & VEML6030_ALS_INT_EN)
return 1;
else
return 0;
}
/*
* Sensor should not be measuring light when interrupt is configured.
* Therefore correct sequence to configure interrupt functionality is:
* shut down -> enable/disable interrupt -> power on
*
* state = 1 enables interrupt, state = 0 disables interrupt
*/
static int veml6030_write_interrupt_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, int state)
{
int ret;
struct veml6030_data *data = iio_priv(indio_dev);
if (state < 0 || state > 1)
return -EINVAL;
ret = veml6030_als_shut_down(data);
if (ret < 0) {
dev_err(&data->client->dev,
"can't disable als to configure interrupt %d\n", ret);
return ret;
}
/* enable interrupt + power on */
ret = regmap_update_bits(data->regmap, VEML6030_REG_ALS_CONF,
VEML6030_ALS_INT_EN | VEML6030_ALS_SD, state << 1);
if (ret)
dev_err(&data->client->dev,
"can't enable interrupt & poweron als %d\n", ret);
return ret;
}
static const struct iio_info veml6030_info = {
.read_raw = veml6030_read_raw,
.write_raw = veml6030_write_raw,
.read_event_value = veml6030_read_event_val,
.write_event_value = veml6030_write_event_val,
.read_event_config = veml6030_read_interrupt_config,
.write_event_config = veml6030_write_interrupt_config,
.attrs = &veml6030_attr_group,
.event_attrs = &veml6030_event_attr_group,
};
static const struct iio_info veml6030_info_no_irq = {
.read_raw = veml6030_read_raw,
.write_raw = veml6030_write_raw,
.attrs = &veml6030_attr_group,
};
static irqreturn_t veml6030_event_handler(int irq, void *private)
{
int ret, reg, evtdir;
struct iio_dev *indio_dev = private;
struct veml6030_data *data = iio_priv(indio_dev);
ret = regmap_read(data->regmap, VEML6030_REG_ALS_INT, ®);
if (ret) {
dev_err(&data->client->dev,
"can't read als interrupt register %d\n", ret);
return IRQ_HANDLED;
}
/* Spurious interrupt handling */
if (!(reg & (VEML6030_INT_TH_HIGH | VEML6030_INT_TH_LOW)))
return IRQ_NONE;
if (reg & VEML6030_INT_TH_HIGH)
evtdir = IIO_EV_DIR_RISING;
else
evtdir = IIO_EV_DIR_FALLING;
iio_push_event(indio_dev, IIO_UNMOD_EVENT_CODE(IIO_INTENSITY,
0, IIO_EV_TYPE_THRESH, evtdir),
iio_get_time_ns(indio_dev));
return IRQ_HANDLED;
}
/*
* Set ALS gain to 1/8, integration time to 100 ms, PSM to mode 2,
* persistence to 1 x integration time and the threshold
* interrupt disabled by default. First shutdown the sensor,
* update registers and then power on the sensor.
*/
static int veml6030_hw_init(struct iio_dev *indio_dev)
{
int ret, val;
struct veml6030_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
ret = veml6030_als_shut_down(data);
if (ret) {
dev_err(&client->dev, "can't shutdown als %d\n", ret);
return ret;
}
ret = regmap_write(data->regmap, VEML6030_REG_ALS_CONF, 0x1001);
if (ret) {
dev_err(&client->dev, "can't setup als configs %d\n", ret);
return ret;
}
ret = regmap_update_bits(data->regmap, VEML6030_REG_ALS_PSM,
VEML6030_PSM | VEML6030_PSM_EN, 0x03);
if (ret) {
dev_err(&client->dev, "can't setup default PSM %d\n", ret);
return ret;
}
ret = regmap_write(data->regmap, VEML6030_REG_ALS_WH, 0xFFFF);
if (ret) {
dev_err(&client->dev, "can't setup high threshold %d\n", ret);
return ret;
}
ret = regmap_write(data->regmap, VEML6030_REG_ALS_WL, 0x0000);
if (ret) {
dev_err(&client->dev, "can't setup low threshold %d\n", ret);
return ret;
}
ret = veml6030_als_pwr_on(data);
if (ret) {
dev_err(&client->dev, "can't poweron als %d\n", ret);
return ret;
}
/* Wait 4 ms to let processor & oscillator start correctly */
usleep_range(4000, 4002);
/* Clear stale interrupt status bits if any during start */
ret = regmap_read(data->regmap, VEML6030_REG_ALS_INT, &val);
if (ret < 0) {
dev_err(&client->dev,
"can't clear als interrupt status %d\n", ret);
return ret;
}
/* Cache currently active measurement parameters */
data->cur_gain = 3;
data->cur_resolution = 4608;
data->cur_integration_time = 3;
return ret;
}
static int veml6030_probe(struct i2c_client *client)
{
int ret;
struct veml6030_data *data;
struct iio_dev *indio_dev;
struct regmap *regmap;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
dev_err(&client->dev, "i2c adapter doesn't support plain i2c\n");
return -EOPNOTSUPP;
}
regmap = devm_regmap_init_i2c(client, &veml6030_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "can't setup regmap\n");
return PTR_ERR(regmap);
}
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->regmap = regmap;
indio_dev->name = "veml6030";
indio_dev->channels = veml6030_channels;
indio_dev->num_channels = ARRAY_SIZE(veml6030_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
if (client->irq) {
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, veml6030_event_handler,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"veml6030", indio_dev);
if (ret < 0) {
dev_err(&client->dev,
"irq %d request failed\n", client->irq);
return ret;
}
indio_dev->info = &veml6030_info;
} else {
indio_dev->info = &veml6030_info_no_irq;
}
ret = veml6030_hw_init(indio_dev);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&client->dev,
veml6030_als_shut_down_action, data);
if (ret < 0)
return ret;
return devm_iio_device_register(&client->dev, indio_dev);
}
static int veml6030_runtime_suspend(struct device *dev)
{
int ret;
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct veml6030_data *data = iio_priv(indio_dev);
ret = veml6030_als_shut_down(data);
if (ret < 0)
dev_err(&data->client->dev, "can't suspend als %d\n", ret);
return ret;
}
static int veml6030_runtime_resume(struct device *dev)
{
int ret;
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct veml6030_data *data = iio_priv(indio_dev);
ret = veml6030_als_pwr_on(data);
if (ret < 0)
dev_err(&data->client->dev, "can't resume als %d\n", ret);
return ret;
}
static DEFINE_RUNTIME_DEV_PM_OPS(veml6030_pm_ops, veml6030_runtime_suspend,
veml6030_runtime_resume, NULL);
static const struct of_device_id veml6030_of_match[] = {
{ .compatible = "vishay,veml6030" },
{ }
};
MODULE_DEVICE_TABLE(of, veml6030_of_match);
static const struct i2c_device_id veml6030_id[] = {
{ "veml6030", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, veml6030_id);
static struct i2c_driver veml6030_driver = {
.driver = {
.name = "veml6030",
.of_match_table = veml6030_of_match,
.pm = pm_ptr(&veml6030_pm_ops),
},
.probe = veml6030_probe,
.id_table = veml6030_id,
};
module_i2c_driver(veml6030_driver);
MODULE_AUTHOR("Rishi Gupta <[email protected]>");
MODULE_DESCRIPTION("VEML6030 Ambient Light Sensor");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/veml6030.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Support for AMS AS73211 JENCOLOR(R) Digital XYZ Sensor
*
* Author: Christian Eggers <[email protected]>
*
* Copyright (c) 2020 ARRI Lighting
*
* Color light sensor with 16-bit channels for x, y, z and temperature);
* 7-bit I2C slave address 0x74 .. 0x77.
*
* Datasheet: https://ams.com/documents/20143/36005/AS73211_DS000556_3-01.pdf
*/
#include <linux/bitfield.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/pm.h>
#include <linux/units.h>
#define AS73211_DRV_NAME "as73211"
/* AS73211 configuration registers */
#define AS73211_REG_OSR 0x0
#define AS73211_REG_AGEN 0x2
#define AS73211_REG_CREG1 0x6
#define AS73211_REG_CREG2 0x7
#define AS73211_REG_CREG3 0x8
/* AS73211 output register bank */
#define AS73211_OUT_OSR_STATUS 0
#define AS73211_OUT_TEMP 1
#define AS73211_OUT_MRES1 2
#define AS73211_OUT_MRES2 3
#define AS73211_OUT_MRES3 4
#define AS73211_OSR_SS BIT(7)
#define AS73211_OSR_PD BIT(6)
#define AS73211_OSR_SW_RES BIT(3)
#define AS73211_OSR_DOS_MASK GENMASK(2, 0)
#define AS73211_OSR_DOS_CONFIG FIELD_PREP(AS73211_OSR_DOS_MASK, 0x2)
#define AS73211_OSR_DOS_MEASURE FIELD_PREP(AS73211_OSR_DOS_MASK, 0x3)
#define AS73211_AGEN_DEVID_MASK GENMASK(7, 4)
#define AS73211_AGEN_DEVID(x) FIELD_PREP(AS73211_AGEN_DEVID_MASK, (x))
#define AS73211_AGEN_MUT_MASK GENMASK(3, 0)
#define AS73211_AGEN_MUT(x) FIELD_PREP(AS73211_AGEN_MUT_MASK, (x))
#define AS73211_CREG1_GAIN_MASK GENMASK(7, 4)
#define AS73211_CREG1_GAIN_1 11
#define AS73211_CREG1_TIME_MASK GENMASK(3, 0)
#define AS73211_CREG3_CCLK_MASK GENMASK(1, 0)
#define AS73211_OSR_STATUS_OUTCONVOF BIT(15)
#define AS73211_OSR_STATUS_MRESOF BIT(14)
#define AS73211_OSR_STATUS_ADCOF BIT(13)
#define AS73211_OSR_STATUS_LDATA BIT(12)
#define AS73211_OSR_STATUS_NDATA BIT(11)
#define AS73211_OSR_STATUS_NOTREADY BIT(10)
#define AS73211_SAMPLE_FREQ_BASE 1024000
#define AS73211_SAMPLE_TIME_NUM 15
#define AS73211_SAMPLE_TIME_MAX_MS BIT(AS73211_SAMPLE_TIME_NUM - 1)
/* Available sample frequencies are 1.024MHz multiplied by powers of two. */
static const int as73211_samp_freq_avail[] = {
AS73211_SAMPLE_FREQ_BASE * 1,
AS73211_SAMPLE_FREQ_BASE * 2,
AS73211_SAMPLE_FREQ_BASE * 4,
AS73211_SAMPLE_FREQ_BASE * 8,
};
static const int as73211_hardwaregain_avail[] = {
1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
};
/**
* struct as73211_data - Instance data for one AS73211
* @client: I2C client.
* @osr: Cached Operational State Register.
* @creg1: Cached Configuration Register 1.
* @creg2: Cached Configuration Register 2.
* @creg3: Cached Configuration Register 3.
* @mutex: Keeps cached registers in sync with the device.
* @completion: Completion to wait for interrupt.
* @int_time_avail: Available integration times (depend on sampling frequency).
*/
struct as73211_data {
struct i2c_client *client;
u8 osr;
u8 creg1;
u8 creg2;
u8 creg3;
struct mutex mutex;
struct completion completion;
int int_time_avail[AS73211_SAMPLE_TIME_NUM * 2];
};
#define AS73211_COLOR_CHANNEL(_color, _si, _addr) { \
.type = IIO_INTENSITY, \
.modified = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_type = \
BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
BIT(IIO_CHAN_INFO_HARDWAREGAIN) | \
BIT(IIO_CHAN_INFO_INT_TIME), \
.info_mask_shared_by_type_available = \
BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
BIT(IIO_CHAN_INFO_HARDWAREGAIN) | \
BIT(IIO_CHAN_INFO_INT_TIME), \
.channel2 = IIO_MOD_##_color, \
.address = _addr, \
.scan_index = _si, \
.scan_type = { \
.sign = 'u', \
.realbits = 16, \
.storagebits = 16, \
.endianness = IIO_LE, \
}, \
}
#define AS73211_OFFSET_TEMP_INT (-66)
#define AS73211_OFFSET_TEMP_MICRO 900000
#define AS73211_SCALE_TEMP_INT 0
#define AS73211_SCALE_TEMP_MICRO 50000
#define AS73211_SCALE_X 277071108 /* nW/m^2 */
#define AS73211_SCALE_Y 298384270 /* nW/m^2 */
#define AS73211_SCALE_Z 160241927 /* nW/m^2 */
/* Channel order MUST match devices result register order */
#define AS73211_SCAN_INDEX_TEMP 0
#define AS73211_SCAN_INDEX_X 1
#define AS73211_SCAN_INDEX_Y 2
#define AS73211_SCAN_INDEX_Z 3
#define AS73211_SCAN_INDEX_TS 4
#define AS73211_SCAN_MASK_COLOR ( \
BIT(AS73211_SCAN_INDEX_X) | \
BIT(AS73211_SCAN_INDEX_Y) | \
BIT(AS73211_SCAN_INDEX_Z))
#define AS73211_SCAN_MASK_ALL ( \
BIT(AS73211_SCAN_INDEX_TEMP) | \
AS73211_SCAN_MASK_COLOR)
static const struct iio_chan_spec as73211_channels[] = {
{
.type = IIO_TEMP,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE),
.address = AS73211_OUT_TEMP,
.scan_index = AS73211_SCAN_INDEX_TEMP,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_LE,
}
},
AS73211_COLOR_CHANNEL(X, AS73211_SCAN_INDEX_X, AS73211_OUT_MRES1),
AS73211_COLOR_CHANNEL(Y, AS73211_SCAN_INDEX_Y, AS73211_OUT_MRES2),
AS73211_COLOR_CHANNEL(Z, AS73211_SCAN_INDEX_Z, AS73211_OUT_MRES3),
IIO_CHAN_SOFT_TIMESTAMP(AS73211_SCAN_INDEX_TS),
};
static unsigned int as73211_integration_time_1024cyc(struct as73211_data *data)
{
/*
* Return integration time in units of 1024 clock cycles. Integration time
* in CREG1 is in powers of 2 (x 1024 cycles).
*/
return BIT(FIELD_GET(AS73211_CREG1_TIME_MASK, data->creg1));
}
static unsigned int as73211_integration_time_us(struct as73211_data *data,
unsigned int integration_time_1024cyc)
{
/*
* f_samp is configured in CREG3 in powers of 2 (x 1.024 MHz)
* t_cycl is configured in CREG1 in powers of 2 (x 1024 cycles)
* t_int_us = 1 / (f_samp) * t_cycl * US_PER_SEC
* = 1 / (2^CREG3_CCLK * 1,024,000) * 2^CREG1_CYCLES * 1,024 * US_PER_SEC
* = 2^(-CREG3_CCLK) * 2^CREG1_CYCLES * 1,000
* In order to get rid of negative exponents, we extend the "fraction"
* by 2^3 (CREG3_CCLK,max = 3)
* t_int_us = 2^(3-CREG3_CCLK) * 2^CREG1_CYCLES * 125
*/
return BIT(3 - FIELD_GET(AS73211_CREG3_CCLK_MASK, data->creg3)) *
integration_time_1024cyc * 125;
}
static void as73211_integration_time_calc_avail(struct as73211_data *data)
{
int i;
for (i = 0; i < ARRAY_SIZE(data->int_time_avail) / 2; i++) {
unsigned int time_us = as73211_integration_time_us(data, BIT(i));
data->int_time_avail[i * 2 + 0] = time_us / USEC_PER_SEC;
data->int_time_avail[i * 2 + 1] = time_us % USEC_PER_SEC;
}
}
static unsigned int as73211_gain(struct as73211_data *data)
{
/* gain can be calculated from CREG1 as 2^(11 - CREG1_GAIN) */
return BIT(AS73211_CREG1_GAIN_1 - FIELD_GET(AS73211_CREG1_GAIN_MASK, data->creg1));
}
/* must be called with as73211_data::mutex held. */
static int as73211_req_data(struct as73211_data *data)
{
unsigned int time_us = as73211_integration_time_us(data,
as73211_integration_time_1024cyc(data));
struct device *dev = &data->client->dev;
union i2c_smbus_data smbus_data;
u16 osr_status;
int ret;
if (data->client->irq)
reinit_completion(&data->completion);
/*
* During measurement, there should be no traffic on the i2c bus as the
* electrical noise would disturb the measurement process.
*/
i2c_lock_bus(data->client->adapter, I2C_LOCK_SEGMENT);
data->osr &= ~AS73211_OSR_DOS_MASK;
data->osr |= AS73211_OSR_DOS_MEASURE | AS73211_OSR_SS;
smbus_data.byte = data->osr;
ret = __i2c_smbus_xfer(data->client->adapter, data->client->addr,
data->client->flags, I2C_SMBUS_WRITE,
AS73211_REG_OSR, I2C_SMBUS_BYTE_DATA, &smbus_data);
if (ret < 0) {
i2c_unlock_bus(data->client->adapter, I2C_LOCK_SEGMENT);
return ret;
}
/*
* Reset AS73211_OSR_SS (is self clearing) in order to avoid unintentional
* triggering of further measurements later.
*/
data->osr &= ~AS73211_OSR_SS;
/*
* Add 33% extra margin for the timeout. fclk,min = fclk,typ - 27%.
*/
time_us += time_us / 3;
if (data->client->irq) {
ret = wait_for_completion_timeout(&data->completion, usecs_to_jiffies(time_us));
if (!ret) {
dev_err(dev, "timeout waiting for READY IRQ\n");
i2c_unlock_bus(data->client->adapter, I2C_LOCK_SEGMENT);
return -ETIMEDOUT;
}
} else {
/* Wait integration time */
usleep_range(time_us, 2 * time_us);
}
i2c_unlock_bus(data->client->adapter, I2C_LOCK_SEGMENT);
ret = i2c_smbus_read_word_data(data->client, AS73211_OUT_OSR_STATUS);
if (ret < 0)
return ret;
osr_status = ret;
if (osr_status != (AS73211_OSR_DOS_MEASURE | AS73211_OSR_STATUS_NDATA)) {
if (osr_status & AS73211_OSR_SS) {
dev_err(dev, "%s() Measurement has not stopped\n", __func__);
return -ETIME;
}
if (osr_status & AS73211_OSR_STATUS_NOTREADY) {
dev_err(dev, "%s() Data is not ready\n", __func__);
return -ENODATA;
}
if (!(osr_status & AS73211_OSR_STATUS_NDATA)) {
dev_err(dev, "%s() No new data available\n", __func__);
return -ENODATA;
}
if (osr_status & AS73211_OSR_STATUS_LDATA) {
dev_err(dev, "%s() Result buffer overrun\n", __func__);
return -ENOBUFS;
}
if (osr_status & AS73211_OSR_STATUS_ADCOF) {
dev_err(dev, "%s() ADC overflow\n", __func__);
return -EOVERFLOW;
}
if (osr_status & AS73211_OSR_STATUS_MRESOF) {
dev_err(dev, "%s() Measurement result overflow\n", __func__);
return -EOVERFLOW;
}
if (osr_status & AS73211_OSR_STATUS_OUTCONVOF) {
dev_err(dev, "%s() Timer overflow\n", __func__);
return -EOVERFLOW;
}
dev_err(dev, "%s() Unexpected status value\n", __func__);
return -EIO;
}
return 0;
}
static int as73211_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct as73211_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW: {
int ret;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret < 0)
return ret;
ret = as73211_req_data(data);
if (ret < 0) {
iio_device_release_direct_mode(indio_dev);
return ret;
}
ret = i2c_smbus_read_word_data(data->client, chan->address);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
}
case IIO_CHAN_INFO_OFFSET:
*val = AS73211_OFFSET_TEMP_INT;
*val2 = AS73211_OFFSET_TEMP_MICRO;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_TEMP:
*val = AS73211_SCALE_TEMP_INT;
*val2 = AS73211_SCALE_TEMP_MICRO;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_INTENSITY: {
unsigned int scale;
switch (chan->channel2) {
case IIO_MOD_X:
scale = AS73211_SCALE_X;
break;
case IIO_MOD_Y:
scale = AS73211_SCALE_Y;
break;
case IIO_MOD_Z:
scale = AS73211_SCALE_Z;
break;
default:
return -EINVAL;
}
scale /= as73211_gain(data);
scale /= as73211_integration_time_1024cyc(data);
*val = scale;
return IIO_VAL_INT;
default:
return -EINVAL;
}}
case IIO_CHAN_INFO_SAMP_FREQ:
/* f_samp is configured in CREG3 in powers of 2 (x 1.024 MHz) */
*val = BIT(FIELD_GET(AS73211_CREG3_CCLK_MASK, data->creg3)) *
AS73211_SAMPLE_FREQ_BASE;
return IIO_VAL_INT;
case IIO_CHAN_INFO_HARDWAREGAIN:
*val = as73211_gain(data);
return IIO_VAL_INT;
case IIO_CHAN_INFO_INT_TIME: {
unsigned int time_us;
mutex_lock(&data->mutex);
time_us = as73211_integration_time_us(data, as73211_integration_time_1024cyc(data));
mutex_unlock(&data->mutex);
*val = time_us / USEC_PER_SEC;
*val2 = time_us % USEC_PER_SEC;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}}
}
static int as73211_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
const int **vals, int *type, int *length, long mask)
{
struct as73211_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
*length = ARRAY_SIZE(as73211_samp_freq_avail);
*vals = as73211_samp_freq_avail;
*type = IIO_VAL_INT;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_HARDWAREGAIN:
*length = ARRAY_SIZE(as73211_hardwaregain_avail);
*vals = as73211_hardwaregain_avail;
*type = IIO_VAL_INT;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_INT_TIME:
*length = ARRAY_SIZE(data->int_time_avail);
*vals = data->int_time_avail;
*type = IIO_VAL_INT_PLUS_MICRO;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static int _as73211_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan __always_unused,
int val, int val2, long mask)
{
struct as73211_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ: {
int reg_bits, freq_kHz = val / HZ_PER_KHZ; /* 1024, 2048, ... */
/* val must be 1024 * 2^x */
if (val < 0 || (freq_kHz * HZ_PER_KHZ) != val ||
!is_power_of_2(freq_kHz) || val2)
return -EINVAL;
/* f_samp is configured in CREG3 in powers of 2 (x 1.024 MHz (=2^10)) */
reg_bits = ilog2(freq_kHz) - 10;
if (!FIELD_FIT(AS73211_CREG3_CCLK_MASK, reg_bits))
return -EINVAL;
data->creg3 &= ~AS73211_CREG3_CCLK_MASK;
data->creg3 |= FIELD_PREP(AS73211_CREG3_CCLK_MASK, reg_bits);
as73211_integration_time_calc_avail(data);
ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_CREG3, data->creg3);
if (ret < 0)
return ret;
return 0;
}
case IIO_CHAN_INFO_HARDWAREGAIN: {
unsigned int reg_bits;
if (val < 0 || !is_power_of_2(val) || val2)
return -EINVAL;
/* gain can be calculated from CREG1 as 2^(11 - CREG1_GAIN) */
reg_bits = AS73211_CREG1_GAIN_1 - ilog2(val);
if (!FIELD_FIT(AS73211_CREG1_GAIN_MASK, reg_bits))
return -EINVAL;
data->creg1 &= ~AS73211_CREG1_GAIN_MASK;
data->creg1 |= FIELD_PREP(AS73211_CREG1_GAIN_MASK, reg_bits);
ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_CREG1, data->creg1);
if (ret < 0)
return ret;
return 0;
}
case IIO_CHAN_INFO_INT_TIME: {
int val_us = val * USEC_PER_SEC + val2;
int time_ms;
int reg_bits;
/* f_samp is configured in CREG3 in powers of 2 (x 1.024 MHz) */
int f_samp_1_024mhz = BIT(FIELD_GET(AS73211_CREG3_CCLK_MASK, data->creg3));
/*
* time_ms = time_us * US_PER_MS * f_samp_1_024mhz / MHZ_PER_HZ
* = time_us * f_samp_1_024mhz / 1000
*/
time_ms = (val_us * f_samp_1_024mhz) / 1000; /* 1 ms, 2 ms, ... (power of two) */
if (time_ms < 0 || !is_power_of_2(time_ms) || time_ms > AS73211_SAMPLE_TIME_MAX_MS)
return -EINVAL;
reg_bits = ilog2(time_ms);
if (!FIELD_FIT(AS73211_CREG1_TIME_MASK, reg_bits))
return -EINVAL; /* not possible due to previous tests */
data->creg1 &= ~AS73211_CREG1_TIME_MASK;
data->creg1 |= FIELD_PREP(AS73211_CREG1_TIME_MASK, reg_bits);
ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_CREG1, data->creg1);
if (ret < 0)
return ret;
return 0;
default:
return -EINVAL;
}}
}
static int as73211_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct as73211_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->mutex);
ret = iio_device_claim_direct_mode(indio_dev);
if (ret < 0)
goto error_unlock;
/* Need to switch to config mode ... */
if ((data->osr & AS73211_OSR_DOS_MASK) != AS73211_OSR_DOS_CONFIG) {
data->osr &= ~AS73211_OSR_DOS_MASK;
data->osr |= AS73211_OSR_DOS_CONFIG;
ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_OSR, data->osr);
if (ret < 0)
goto error_release;
}
ret = _as73211_write_raw(indio_dev, chan, val, val2, mask);
error_release:
iio_device_release_direct_mode(indio_dev);
error_unlock:
mutex_unlock(&data->mutex);
return ret;
}
static irqreturn_t as73211_ready_handler(int irq __always_unused, void *priv)
{
struct as73211_data *data = iio_priv(priv);
complete(&data->completion);
return IRQ_HANDLED;
}
static irqreturn_t as73211_trigger_handler(int irq __always_unused, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct as73211_data *data = iio_priv(indio_dev);
struct {
__le16 chan[4];
s64 ts __aligned(8);
} scan;
int data_result, ret;
mutex_lock(&data->mutex);
data_result = as73211_req_data(data);
if (data_result < 0 && data_result != -EOVERFLOW)
goto done; /* don't push any data for errors other than EOVERFLOW */
if (*indio_dev->active_scan_mask == AS73211_SCAN_MASK_ALL) {
/* Optimization for reading all (color + temperature) channels */
u8 addr = as73211_channels[0].address;
struct i2c_msg msgs[] = {
{
.addr = data->client->addr,
.flags = 0,
.len = 1,
.buf = &addr,
},
{
.addr = data->client->addr,
.flags = I2C_M_RD,
.len = sizeof(scan.chan),
.buf = (u8 *)&scan.chan,
},
};
ret = i2c_transfer(data->client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret < 0)
goto done;
} else {
/* Optimization for reading only color channels */
/* AS73211 starts reading at address 2 */
ret = i2c_master_recv(data->client,
(char *)&scan.chan[1], 3 * sizeof(scan.chan[1]));
if (ret < 0)
goto done;
}
if (data_result) {
/*
* Saturate all channels (in case of overflows). Temperature channel
* is not affected by overflows.
*/
scan.chan[1] = cpu_to_le16(U16_MAX);
scan.chan[2] = cpu_to_le16(U16_MAX);
scan.chan[3] = cpu_to_le16(U16_MAX);
}
iio_push_to_buffers_with_timestamp(indio_dev, &scan, iio_get_time_ns(indio_dev));
done:
mutex_unlock(&data->mutex);
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static const struct iio_info as73211_info = {
.read_raw = as73211_read_raw,
.read_avail = as73211_read_avail,
.write_raw = as73211_write_raw,
};
static int as73211_power(struct iio_dev *indio_dev, bool state)
{
struct as73211_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->mutex);
if (state)
data->osr &= ~AS73211_OSR_PD;
else
data->osr |= AS73211_OSR_PD;
ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_OSR, data->osr);
mutex_unlock(&data->mutex);
if (ret < 0)
return ret;
return 0;
}
static void as73211_power_disable(void *data)
{
struct iio_dev *indio_dev = data;
as73211_power(indio_dev, false);
}
static int as73211_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct as73211_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
mutex_init(&data->mutex);
init_completion(&data->completion);
indio_dev->info = &as73211_info;
indio_dev->name = AS73211_DRV_NAME;
indio_dev->channels = as73211_channels;
indio_dev->num_channels = ARRAY_SIZE(as73211_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_OSR);
if (ret < 0)
return ret;
data->osr = ret;
/* reset device */
data->osr |= AS73211_OSR_SW_RES;
ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_OSR, data->osr);
if (ret < 0)
return ret;
ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_OSR);
if (ret < 0)
return ret;
data->osr = ret;
/*
* Reading AGEN is only possible after reset (AGEN is not available if
* device is in measurement mode).
*/
ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_AGEN);
if (ret < 0)
return ret;
/* At the time of writing this driver, only DEVID 2 and MUT 1 are known. */
if ((ret & AS73211_AGEN_DEVID_MASK) != AS73211_AGEN_DEVID(2) ||
(ret & AS73211_AGEN_MUT_MASK) != AS73211_AGEN_MUT(1))
return -ENODEV;
ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_CREG1);
if (ret < 0)
return ret;
data->creg1 = ret;
ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_CREG2);
if (ret < 0)
return ret;
data->creg2 = ret;
ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_CREG3);
if (ret < 0)
return ret;
data->creg3 = ret;
as73211_integration_time_calc_avail(data);
ret = as73211_power(indio_dev, true);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(dev, as73211_power_disable, indio_dev);
if (ret)
return ret;
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, as73211_trigger_handler, NULL);
if (ret)
return ret;
if (client->irq) {
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL,
as73211_ready_handler,
IRQF_ONESHOT,
client->name, indio_dev);
if (ret)
return ret;
}
return devm_iio_device_register(dev, indio_dev);
}
static int as73211_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
return as73211_power(indio_dev, false);
}
static int as73211_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
return as73211_power(indio_dev, true);
}
static DEFINE_SIMPLE_DEV_PM_OPS(as73211_pm_ops, as73211_suspend,
as73211_resume);
static const struct of_device_id as73211_of_match[] = {
{ .compatible = "ams,as73211" },
{ }
};
MODULE_DEVICE_TABLE(of, as73211_of_match);
static const struct i2c_device_id as73211_id[] = {
{ "as73211", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, as73211_id);
static struct i2c_driver as73211_driver = {
.driver = {
.name = AS73211_DRV_NAME,
.of_match_table = as73211_of_match,
.pm = pm_sleep_ptr(&as73211_pm_ops),
},
.probe = as73211_probe,
.id_table = as73211_id,
};
module_i2c_driver(as73211_driver);
MODULE_AUTHOR("Christian Eggers <[email protected]>");
MODULE_DESCRIPTION("AS73211 XYZ True Color Sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/as73211.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Device driver for monitoring ambient light intensity (lux)
* within the TAOS tsl258x family of devices (tsl2580, tsl2581, tsl2583).
*
* Copyright (c) 2011, TAOS Corporation.
* Copyright (c) 2016-2017 Brian Masney <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/mutex.h>
#include <linux/unistd.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/pm_runtime.h>
/* Device Registers and Masks */
#define TSL2583_CNTRL 0x00
#define TSL2583_ALS_TIME 0X01
#define TSL2583_INTERRUPT 0x02
#define TSL2583_GAIN 0x07
#define TSL2583_REVID 0x11
#define TSL2583_CHIPID 0x12
#define TSL2583_ALS_CHAN0LO 0x14
#define TSL2583_ALS_CHAN0HI 0x15
#define TSL2583_ALS_CHAN1LO 0x16
#define TSL2583_ALS_CHAN1HI 0x17
#define TSL2583_TMR_LO 0x18
#define TSL2583_TMR_HI 0x19
/* tsl2583 cmd reg masks */
#define TSL2583_CMD_REG 0x80
#define TSL2583_CMD_SPL_FN 0x60
#define TSL2583_CMD_ALS_INT_CLR 0x01
/* tsl2583 cntrl reg masks */
#define TSL2583_CNTL_ADC_ENBL 0x02
#define TSL2583_CNTL_PWR_OFF 0x00
#define TSL2583_CNTL_PWR_ON 0x01
/* tsl2583 status reg masks */
#define TSL2583_STA_ADC_VALID 0x01
#define TSL2583_STA_ADC_INTR 0x10
/* Lux calculation constants */
#define TSL2583_LUX_CALC_OVER_FLOW 65535
#define TSL2583_INTERRUPT_DISABLED 0x00
#define TSL2583_CHIP_ID 0x90
#define TSL2583_CHIP_ID_MASK 0xf0
#define TSL2583_POWER_OFF_DELAY_MS 2000
/* Per-device data */
struct tsl2583_als_info {
u16 als_ch0;
u16 als_ch1;
u16 lux;
};
struct tsl2583_lux {
unsigned int ratio;
unsigned int ch0;
unsigned int ch1;
};
static const struct tsl2583_lux tsl2583_default_lux[] = {
{ 9830, 8520, 15729 },
{ 12452, 10807, 23344 },
{ 14746, 6383, 11705 },
{ 17695, 4063, 6554 },
{ 0, 0, 0 } /* Termination segment */
};
#define TSL2583_MAX_LUX_TABLE_ENTRIES 11
struct tsl2583_settings {
int als_time;
int als_gain;
int als_gain_trim;
int als_cal_target;
/*
* This structure is intentionally large to accommodate updates via
* sysfs. Sized to 11 = max 10 segments + 1 termination segment.
* Assumption is that one and only one type of glass used.
*/
struct tsl2583_lux als_device_lux[TSL2583_MAX_LUX_TABLE_ENTRIES];
};
struct tsl2583_chip {
struct mutex als_mutex;
struct i2c_client *client;
struct tsl2583_als_info als_cur_info;
struct tsl2583_settings als_settings;
int als_time_scale;
int als_saturation;
};
struct gainadj {
s16 ch0;
s16 ch1;
s16 mean;
};
/* Index = (0 - 3) Used to validate the gain selection index */
static const struct gainadj gainadj[] = {
{ 1, 1, 1 },
{ 8, 8, 8 },
{ 16, 16, 16 },
{ 107, 115, 111 }
};
/*
* Provides initial operational parameter defaults.
* These defaults may be changed through the device's sysfs files.
*/
static void tsl2583_defaults(struct tsl2583_chip *chip)
{
/*
* The integration time must be a multiple of 50ms and within the
* range [50, 600] ms.
*/
chip->als_settings.als_time = 100;
/*
* This is an index into the gainadj table. Assume clear glass as the
* default.
*/
chip->als_settings.als_gain = 0;
/* Default gain trim to account for aperture effects */
chip->als_settings.als_gain_trim = 1000;
/* Known external ALS reading used for calibration */
chip->als_settings.als_cal_target = 130;
/* Default lux table. */
memcpy(chip->als_settings.als_device_lux, tsl2583_default_lux,
sizeof(tsl2583_default_lux));
}
/*
* Reads and calculates current lux value.
* The raw ch0 and ch1 values of the ambient light sensed in the last
* integration cycle are read from the device.
* Time scale factor array values are adjusted based on the integration time.
* The raw values are multiplied by a scale factor, and device gain is obtained
* using gain index. Limit checks are done next, then the ratio of a multiple
* of ch1 value, to the ch0 value, is calculated. The array als_device_lux[]
* declared above is then scanned to find the first ratio value that is just
* above the ratio we just calculated. The ch0 and ch1 multiplier constants in
* the array are then used along with the time scale factor array values, to
* calculate the lux.
*/
static int tsl2583_get_lux(struct iio_dev *indio_dev)
{
u16 ch0, ch1; /* separated ch0/ch1 data from device */
u32 lux; /* raw lux calculated from device data */
u64 lux64;
u32 ratio;
u8 buf[5];
struct tsl2583_lux *p;
struct tsl2583_chip *chip = iio_priv(indio_dev);
int i, ret;
ret = i2c_smbus_read_byte_data(chip->client, TSL2583_CMD_REG);
if (ret < 0) {
dev_err(&chip->client->dev, "%s: failed to read CMD_REG register\n",
__func__);
goto done;
}
/* is data new & valid */
if (!(ret & TSL2583_STA_ADC_INTR)) {
dev_err(&chip->client->dev, "%s: data not valid; returning last value\n",
__func__);
ret = chip->als_cur_info.lux; /* return LAST VALUE */
goto done;
}
for (i = 0; i < 4; i++) {
int reg = TSL2583_CMD_REG | (TSL2583_ALS_CHAN0LO + i);
ret = i2c_smbus_read_byte_data(chip->client, reg);
if (ret < 0) {
dev_err(&chip->client->dev, "%s: failed to read register %x\n",
__func__, reg);
goto done;
}
buf[i] = ret;
}
/*
* Clear the pending interrupt status bit on the chip to allow the next
* integration cycle to start. This has to be done even though this
* driver currently does not support interrupts.
*/
ret = i2c_smbus_write_byte(chip->client,
(TSL2583_CMD_REG | TSL2583_CMD_SPL_FN |
TSL2583_CMD_ALS_INT_CLR));
if (ret < 0) {
dev_err(&chip->client->dev, "%s: failed to clear the interrupt bit\n",
__func__);
goto done; /* have no data, so return failure */
}
/* extract ALS/lux data */
ch0 = le16_to_cpup((const __le16 *)&buf[0]);
ch1 = le16_to_cpup((const __le16 *)&buf[2]);
chip->als_cur_info.als_ch0 = ch0;
chip->als_cur_info.als_ch1 = ch1;
if ((ch0 >= chip->als_saturation) || (ch1 >= chip->als_saturation))
goto return_max;
if (!ch0) {
/*
* The sensor appears to be in total darkness so set the
* calculated lux to 0 and return early to avoid a division by
* zero below when calculating the ratio.
*/
ret = 0;
chip->als_cur_info.lux = 0;
goto done;
}
/* calculate ratio */
ratio = (ch1 << 15) / ch0;
/* convert to unscaled lux using the pointer to the table */
for (p = (struct tsl2583_lux *)chip->als_settings.als_device_lux;
p->ratio != 0 && p->ratio < ratio; p++)
;
if (p->ratio == 0) {
lux = 0;
} else {
u32 ch0lux, ch1lux;
ch0lux = ((ch0 * p->ch0) +
(gainadj[chip->als_settings.als_gain].ch0 >> 1))
/ gainadj[chip->als_settings.als_gain].ch0;
ch1lux = ((ch1 * p->ch1) +
(gainadj[chip->als_settings.als_gain].ch1 >> 1))
/ gainadj[chip->als_settings.als_gain].ch1;
/* note: lux is 31 bit max at this point */
if (ch1lux > ch0lux) {
dev_dbg(&chip->client->dev, "%s: No Data - Returning 0\n",
__func__);
ret = 0;
chip->als_cur_info.lux = 0;
goto done;
}
lux = ch0lux - ch1lux;
}
/* adjust for active time scale */
if (chip->als_time_scale == 0)
lux = 0;
else
lux = (lux + (chip->als_time_scale >> 1)) /
chip->als_time_scale;
/*
* Adjust for active gain scale.
* The tsl2583_default_lux tables above have a factor of 8192 built in,
* so we need to shift right.
* User-specified gain provides a multiplier.
* Apply user-specified gain before shifting right to retain precision.
* Use 64 bits to avoid overflow on multiplication.
* Then go back to 32 bits before division to avoid using div_u64().
*/
lux64 = lux;
lux64 = lux64 * chip->als_settings.als_gain_trim;
lux64 >>= 13;
lux = lux64;
lux = DIV_ROUND_CLOSEST(lux, 1000);
if (lux > TSL2583_LUX_CALC_OVER_FLOW) { /* check for overflow */
return_max:
lux = TSL2583_LUX_CALC_OVER_FLOW;
}
/* Update the structure with the latest VALID lux. */
chip->als_cur_info.lux = lux;
ret = lux;
done:
return ret;
}
/*
* Obtain single reading and calculate the als_gain_trim (later used
* to derive actual lux).
* Return updated gain_trim value.
*/
static int tsl2583_als_calibrate(struct iio_dev *indio_dev)
{
struct tsl2583_chip *chip = iio_priv(indio_dev);
unsigned int gain_trim_val;
int ret;
int lux_val;
ret = i2c_smbus_read_byte_data(chip->client,
TSL2583_CMD_REG | TSL2583_CNTRL);
if (ret < 0) {
dev_err(&chip->client->dev,
"%s: failed to read from the CNTRL register\n",
__func__);
return ret;
}
if ((ret & (TSL2583_CNTL_ADC_ENBL | TSL2583_CNTL_PWR_ON))
!= (TSL2583_CNTL_ADC_ENBL | TSL2583_CNTL_PWR_ON)) {
dev_err(&chip->client->dev,
"%s: Device is not powered on and/or ADC is not enabled\n",
__func__);
return -EINVAL;
} else if ((ret & TSL2583_STA_ADC_VALID) != TSL2583_STA_ADC_VALID) {
dev_err(&chip->client->dev,
"%s: The two ADC channels have not completed an integration cycle\n",
__func__);
return -ENODATA;
}
lux_val = tsl2583_get_lux(indio_dev);
if (lux_val < 0) {
dev_err(&chip->client->dev, "%s: failed to get lux\n",
__func__);
return lux_val;
}
/* Avoid division by zero of lux_value later on */
if (lux_val == 0) {
dev_err(&chip->client->dev,
"%s: lux_val of 0 will produce out of range trim_value\n",
__func__);
return -ENODATA;
}
gain_trim_val = (unsigned int)(((chip->als_settings.als_cal_target)
* chip->als_settings.als_gain_trim) / lux_val);
if ((gain_trim_val < 250) || (gain_trim_val > 4000)) {
dev_err(&chip->client->dev,
"%s: trim_val of %d is not within the range [250, 4000]\n",
__func__, gain_trim_val);
return -ENODATA;
}
chip->als_settings.als_gain_trim = (int)gain_trim_val;
return 0;
}
static int tsl2583_set_als_time(struct tsl2583_chip *chip)
{
int als_count, als_time, ret;
u8 val;
/* determine als integration register */
als_count = DIV_ROUND_CLOSEST(chip->als_settings.als_time * 100, 270);
if (!als_count)
als_count = 1; /* ensure at least one cycle */
/* convert back to time (encompasses overrides) */
als_time = DIV_ROUND_CLOSEST(als_count * 27, 10);
val = 256 - als_count;
ret = i2c_smbus_write_byte_data(chip->client,
TSL2583_CMD_REG | TSL2583_ALS_TIME,
val);
if (ret < 0) {
dev_err(&chip->client->dev, "%s: failed to set the als time to %d\n",
__func__, val);
return ret;
}
/* set chip struct re scaling and saturation */
chip->als_saturation = als_count * 922; /* 90% of full scale */
chip->als_time_scale = DIV_ROUND_CLOSEST(als_time, 50);
return ret;
}
static int tsl2583_set_als_gain(struct tsl2583_chip *chip)
{
int ret;
/* Set the gain based on als_settings struct */
ret = i2c_smbus_write_byte_data(chip->client,
TSL2583_CMD_REG | TSL2583_GAIN,
chip->als_settings.als_gain);
if (ret < 0)
dev_err(&chip->client->dev,
"%s: failed to set the gain to %d\n", __func__,
chip->als_settings.als_gain);
return ret;
}
static int tsl2583_set_power_state(struct tsl2583_chip *chip, u8 state)
{
int ret;
ret = i2c_smbus_write_byte_data(chip->client,
TSL2583_CMD_REG | TSL2583_CNTRL, state);
if (ret < 0)
dev_err(&chip->client->dev,
"%s: failed to set the power state to %d\n", __func__,
state);
return ret;
}
/*
* Turn the device on.
* Configuration must be set before calling this function.
*/
static int tsl2583_chip_init_and_power_on(struct iio_dev *indio_dev)
{
struct tsl2583_chip *chip = iio_priv(indio_dev);
int ret;
/* Power on the device; ADC off. */
ret = tsl2583_set_power_state(chip, TSL2583_CNTL_PWR_ON);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(chip->client,
TSL2583_CMD_REG | TSL2583_INTERRUPT,
TSL2583_INTERRUPT_DISABLED);
if (ret < 0) {
dev_err(&chip->client->dev,
"%s: failed to disable interrupts\n", __func__);
return ret;
}
ret = tsl2583_set_als_time(chip);
if (ret < 0)
return ret;
ret = tsl2583_set_als_gain(chip);
if (ret < 0)
return ret;
usleep_range(3000, 3500);
ret = tsl2583_set_power_state(chip, TSL2583_CNTL_PWR_ON |
TSL2583_CNTL_ADC_ENBL);
if (ret < 0)
return ret;
return ret;
}
/* Sysfs Interface Functions */
static ssize_t in_illuminance_input_target_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct tsl2583_chip *chip = iio_priv(indio_dev);
int ret;
mutex_lock(&chip->als_mutex);
ret = sprintf(buf, "%d\n", chip->als_settings.als_cal_target);
mutex_unlock(&chip->als_mutex);
return ret;
}
static ssize_t in_illuminance_input_target_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct tsl2583_chip *chip = iio_priv(indio_dev);
int value;
if (kstrtoint(buf, 0, &value) || !value)
return -EINVAL;
mutex_lock(&chip->als_mutex);
chip->als_settings.als_cal_target = value;
mutex_unlock(&chip->als_mutex);
return len;
}
static ssize_t in_illuminance_calibrate_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct tsl2583_chip *chip = iio_priv(indio_dev);
int value, ret;
if (kstrtoint(buf, 0, &value) || value != 1)
return -EINVAL;
mutex_lock(&chip->als_mutex);
ret = tsl2583_als_calibrate(indio_dev);
if (ret < 0)
goto done;
ret = len;
done:
mutex_unlock(&chip->als_mutex);
return ret;
}
static ssize_t in_illuminance_lux_table_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct tsl2583_chip *chip = iio_priv(indio_dev);
unsigned int i;
int offset = 0;
for (i = 0; i < ARRAY_SIZE(chip->als_settings.als_device_lux); i++) {
offset += sprintf(buf + offset, "%u,%u,%u,",
chip->als_settings.als_device_lux[i].ratio,
chip->als_settings.als_device_lux[i].ch0,
chip->als_settings.als_device_lux[i].ch1);
if (chip->als_settings.als_device_lux[i].ratio == 0) {
/*
* We just printed the first "0" entry.
* Now get rid of the extra "," and break.
*/
offset--;
break;
}
}
offset += sprintf(buf + offset, "\n");
return offset;
}
static ssize_t in_illuminance_lux_table_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct tsl2583_chip *chip = iio_priv(indio_dev);
const unsigned int max_ints = TSL2583_MAX_LUX_TABLE_ENTRIES * 3;
int value[TSL2583_MAX_LUX_TABLE_ENTRIES * 3 + 1];
int ret = -EINVAL;
unsigned int n;
mutex_lock(&chip->als_mutex);
get_options(buf, ARRAY_SIZE(value), value);
/*
* We now have an array of ints starting at value[1], and
* enumerated by value[0].
* We expect each group of three ints is one table entry,
* and the last table entry is all 0.
*/
n = value[0];
if ((n % 3) || n < 6 || n > max_ints) {
dev_err(dev,
"%s: The number of entries in the lux table must be a multiple of 3 and within the range [6, %d]\n",
__func__, max_ints);
goto done;
}
if ((value[n - 2] | value[n - 1] | value[n]) != 0) {
dev_err(dev, "%s: The last 3 entries in the lux table must be zeros.\n",
__func__);
goto done;
}
memcpy(chip->als_settings.als_device_lux, &value[1],
value[0] * sizeof(value[1]));
ret = len;
done:
mutex_unlock(&chip->als_mutex);
return ret;
}
static IIO_CONST_ATTR(in_illuminance_calibscale_available, "1 8 16 111");
static IIO_CONST_ATTR(in_illuminance_integration_time_available,
"0.050 0.100 0.150 0.200 0.250 0.300 0.350 0.400 0.450 0.500 0.550 0.600 0.650");
static IIO_DEVICE_ATTR_RW(in_illuminance_input_target, 0);
static IIO_DEVICE_ATTR_WO(in_illuminance_calibrate, 0);
static IIO_DEVICE_ATTR_RW(in_illuminance_lux_table, 0);
static struct attribute *sysfs_attrs_ctrl[] = {
&iio_const_attr_in_illuminance_calibscale_available.dev_attr.attr,
&iio_const_attr_in_illuminance_integration_time_available.dev_attr.attr,
&iio_dev_attr_in_illuminance_input_target.dev_attr.attr,
&iio_dev_attr_in_illuminance_calibrate.dev_attr.attr,
&iio_dev_attr_in_illuminance_lux_table.dev_attr.attr,
NULL
};
static const struct attribute_group tsl2583_attribute_group = {
.attrs = sysfs_attrs_ctrl,
};
static const struct iio_chan_spec tsl2583_channels[] = {
{
.type = IIO_LIGHT,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_IR,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
},
{
.type = IIO_LIGHT,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_BOTH,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
},
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_CALIBBIAS) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_INT_TIME),
},
};
static int tsl2583_set_pm_runtime_busy(struct tsl2583_chip *chip, bool on)
{
int ret;
if (on) {
ret = pm_runtime_resume_and_get(&chip->client->dev);
} else {
pm_runtime_mark_last_busy(&chip->client->dev);
ret = pm_runtime_put_autosuspend(&chip->client->dev);
}
return ret;
}
static int tsl2583_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct tsl2583_chip *chip = iio_priv(indio_dev);
int ret, pm_ret;
ret = tsl2583_set_pm_runtime_busy(chip, true);
if (ret < 0)
return ret;
mutex_lock(&chip->als_mutex);
ret = -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (chan->type == IIO_LIGHT) {
ret = tsl2583_get_lux(indio_dev);
if (ret < 0)
goto read_done;
/*
* From page 20 of the TSL2581, TSL2583 data
* sheet (TAOS134 − MARCH 2011):
*
* One of the photodiodes (channel 0) is
* sensitive to both visible and infrared light,
* while the second photodiode (channel 1) is
* sensitive primarily to infrared light.
*/
if (chan->channel2 == IIO_MOD_LIGHT_BOTH)
*val = chip->als_cur_info.als_ch0;
else
*val = chip->als_cur_info.als_ch1;
ret = IIO_VAL_INT;
}
break;
case IIO_CHAN_INFO_PROCESSED:
if (chan->type == IIO_LIGHT) {
ret = tsl2583_get_lux(indio_dev);
if (ret < 0)
goto read_done;
*val = ret;
ret = IIO_VAL_INT;
}
break;
case IIO_CHAN_INFO_CALIBBIAS:
if (chan->type == IIO_LIGHT) {
*val = chip->als_settings.als_gain_trim;
ret = IIO_VAL_INT;
}
break;
case IIO_CHAN_INFO_CALIBSCALE:
if (chan->type == IIO_LIGHT) {
*val = gainadj[chip->als_settings.als_gain].mean;
ret = IIO_VAL_INT;
}
break;
case IIO_CHAN_INFO_INT_TIME:
if (chan->type == IIO_LIGHT) {
*val = 0;
*val2 = chip->als_settings.als_time;
ret = IIO_VAL_INT_PLUS_MICRO;
}
break;
default:
break;
}
read_done:
mutex_unlock(&chip->als_mutex);
if (ret < 0) {
tsl2583_set_pm_runtime_busy(chip, false);
return ret;
}
/*
* Preserve the ret variable if the call to
* tsl2583_set_pm_runtime_busy() is successful so the reading
* (if applicable) is returned to user space.
*/
pm_ret = tsl2583_set_pm_runtime_busy(chip, false);
if (pm_ret < 0)
return pm_ret;
return ret;
}
static int tsl2583_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct tsl2583_chip *chip = iio_priv(indio_dev);
int ret;
ret = tsl2583_set_pm_runtime_busy(chip, true);
if (ret < 0)
return ret;
mutex_lock(&chip->als_mutex);
ret = -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_CALIBBIAS:
if (chan->type == IIO_LIGHT) {
chip->als_settings.als_gain_trim = val;
ret = 0;
}
break;
case IIO_CHAN_INFO_CALIBSCALE:
if (chan->type == IIO_LIGHT) {
unsigned int i;
for (i = 0; i < ARRAY_SIZE(gainadj); i++) {
if (gainadj[i].mean == val) {
chip->als_settings.als_gain = i;
ret = tsl2583_set_als_gain(chip);
break;
}
}
}
break;
case IIO_CHAN_INFO_INT_TIME:
if (chan->type == IIO_LIGHT && !val && val2 >= 50 &&
val2 <= 650 && !(val2 % 50)) {
chip->als_settings.als_time = val2;
ret = tsl2583_set_als_time(chip);
}
break;
default:
break;
}
mutex_unlock(&chip->als_mutex);
if (ret < 0) {
tsl2583_set_pm_runtime_busy(chip, false);
return ret;
}
ret = tsl2583_set_pm_runtime_busy(chip, false);
if (ret < 0)
return ret;
return ret;
}
static const struct iio_info tsl2583_info = {
.attrs = &tsl2583_attribute_group,
.read_raw = tsl2583_read_raw,
.write_raw = tsl2583_write_raw,
};
static int tsl2583_probe(struct i2c_client *clientp)
{
int ret;
struct tsl2583_chip *chip;
struct iio_dev *indio_dev;
if (!i2c_check_functionality(clientp->adapter,
I2C_FUNC_SMBUS_BYTE_DATA)) {
dev_err(&clientp->dev, "%s: i2c smbus byte data functionality is unsupported\n",
__func__);
return -EOPNOTSUPP;
}
indio_dev = devm_iio_device_alloc(&clientp->dev, sizeof(*chip));
if (!indio_dev)
return -ENOMEM;
chip = iio_priv(indio_dev);
chip->client = clientp;
i2c_set_clientdata(clientp, indio_dev);
mutex_init(&chip->als_mutex);
ret = i2c_smbus_read_byte_data(clientp,
TSL2583_CMD_REG | TSL2583_CHIPID);
if (ret < 0) {
dev_err(&clientp->dev,
"%s: failed to read the chip ID register\n", __func__);
return ret;
}
if ((ret & TSL2583_CHIP_ID_MASK) != TSL2583_CHIP_ID) {
dev_err(&clientp->dev, "%s: received an unknown chip ID %x\n",
__func__, ret);
return -EINVAL;
}
indio_dev->info = &tsl2583_info;
indio_dev->channels = tsl2583_channels;
indio_dev->num_channels = ARRAY_SIZE(tsl2583_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->name = chip->client->name;
pm_runtime_enable(&clientp->dev);
pm_runtime_set_autosuspend_delay(&clientp->dev,
TSL2583_POWER_OFF_DELAY_MS);
pm_runtime_use_autosuspend(&clientp->dev);
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&clientp->dev, "%s: iio registration failed\n",
__func__);
return ret;
}
/* Load up the V2 defaults (these are hard coded defaults for now) */
tsl2583_defaults(chip);
dev_info(&clientp->dev, "Light sensor found.\n");
return 0;
}
static void tsl2583_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct tsl2583_chip *chip = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
tsl2583_set_power_state(chip, TSL2583_CNTL_PWR_OFF);
}
static int tsl2583_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct tsl2583_chip *chip = iio_priv(indio_dev);
int ret;
mutex_lock(&chip->als_mutex);
ret = tsl2583_set_power_state(chip, TSL2583_CNTL_PWR_OFF);
mutex_unlock(&chip->als_mutex);
return ret;
}
static int tsl2583_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct tsl2583_chip *chip = iio_priv(indio_dev);
int ret;
mutex_lock(&chip->als_mutex);
ret = tsl2583_chip_init_and_power_on(indio_dev);
mutex_unlock(&chip->als_mutex);
return ret;
}
static DEFINE_RUNTIME_DEV_PM_OPS(tsl2583_pm_ops, tsl2583_suspend,
tsl2583_resume, NULL);
static const struct i2c_device_id tsl2583_idtable[] = {
{ "tsl2580", 0 },
{ "tsl2581", 1 },
{ "tsl2583", 2 },
{}
};
MODULE_DEVICE_TABLE(i2c, tsl2583_idtable);
static const struct of_device_id tsl2583_of_match[] = {
{ .compatible = "amstaos,tsl2580", },
{ .compatible = "amstaos,tsl2581", },
{ .compatible = "amstaos,tsl2583", },
{ },
};
MODULE_DEVICE_TABLE(of, tsl2583_of_match);
/* Driver definition */
static struct i2c_driver tsl2583_driver = {
.driver = {
.name = "tsl2583",
.pm = pm_ptr(&tsl2583_pm_ops),
.of_match_table = tsl2583_of_match,
},
.id_table = tsl2583_idtable,
.probe = tsl2583_probe,
.remove = tsl2583_remove,
};
module_i2c_driver(tsl2583_driver);
MODULE_AUTHOR("J. August Brenner <[email protected]>");
MODULE_AUTHOR("Brian Masney <[email protected]>");
MODULE_DESCRIPTION("TAOS tsl2583 ambient light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/tsl2583.c |
// SPDX-License-Identifier: GPL-2.0
/*
* cros_ec_light_prox - Driver for light and prox sensors behing CrosEC.
*
* Copyright (C) 2017 Google, Inc
*/
#include <linux/device.h>
#include <linux/iio/buffer.h>
#include <linux/iio/common/cros_ec_sensors_core.h>
#include <linux/iio/iio.h>
#include <linux/iio/kfifo_buf.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_data/cros_ec_commands.h>
#include <linux/platform_data/cros_ec_proto.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
/*
* We only represent one entry for light or proximity. EC is merging different
* light sensors to return the what the eye would see. For proximity, we
* currently support only one light source.
*/
#define CROS_EC_LIGHT_PROX_MAX_CHANNELS (1 + 1)
/* State data for ec_sensors iio driver. */
struct cros_ec_light_prox_state {
/* Shared by all sensors */
struct cros_ec_sensors_core_state core;
struct iio_chan_spec channels[CROS_EC_LIGHT_PROX_MAX_CHANNELS];
};
static int cros_ec_light_prox_read(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct cros_ec_light_prox_state *st = iio_priv(indio_dev);
u16 data = 0;
s64 val64;
int ret;
int idx = chan->scan_index;
mutex_lock(&st->core.cmd_lock);
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (chan->type == IIO_PROXIMITY) {
ret = cros_ec_sensors_read_cmd(indio_dev, 1 << idx,
(s16 *)&data);
if (ret)
break;
*val = data;
ret = IIO_VAL_INT;
} else {
ret = -EINVAL;
}
break;
case IIO_CHAN_INFO_PROCESSED:
if (chan->type == IIO_LIGHT) {
ret = cros_ec_sensors_read_cmd(indio_dev, 1 << idx,
(s16 *)&data);
if (ret)
break;
/*
* The data coming from the light sensor is
* pre-processed and represents the ambient light
* illuminance reading expressed in lux.
*/
*val = data;
ret = IIO_VAL_INT;
} else {
ret = -EINVAL;
}
break;
case IIO_CHAN_INFO_CALIBBIAS:
st->core.param.cmd = MOTIONSENSE_CMD_SENSOR_OFFSET;
st->core.param.sensor_offset.flags = 0;
ret = cros_ec_motion_send_host_cmd(&st->core, 0);
if (ret)
break;
/* Save values */
st->core.calib[0].offset =
st->core.resp->sensor_offset.offset[0];
*val = st->core.calib[idx].offset;
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_CALIBSCALE:
/*
* RANGE is used for calibration
* scale is a number x.y, where x is coded on 16 bits,
* y coded on 16 bits, between 0 and 9999.
*/
st->core.param.cmd = MOTIONSENSE_CMD_SENSOR_RANGE;
st->core.param.sensor_range.data = EC_MOTION_SENSE_NO_VALUE;
ret = cros_ec_motion_send_host_cmd(&st->core, 0);
if (ret)
break;
val64 = st->core.resp->sensor_range.ret;
*val = val64 >> 16;
*val2 = (val64 & 0xffff) * 100;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
ret = cros_ec_sensors_core_read(&st->core, chan, val, val2,
mask);
break;
}
mutex_unlock(&st->core.cmd_lock);
return ret;
}
static int cros_ec_light_prox_write(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct cros_ec_light_prox_state *st = iio_priv(indio_dev);
int ret;
int idx = chan->scan_index;
mutex_lock(&st->core.cmd_lock);
switch (mask) {
case IIO_CHAN_INFO_CALIBBIAS:
st->core.calib[idx].offset = val;
/* Send to EC for each axis, even if not complete */
st->core.param.cmd = MOTIONSENSE_CMD_SENSOR_OFFSET;
st->core.param.sensor_offset.flags = MOTION_SENSE_SET_OFFSET;
st->core.param.sensor_offset.offset[0] =
st->core.calib[0].offset;
st->core.param.sensor_offset.temp =
EC_MOTION_SENSE_INVALID_CALIB_TEMP;
ret = cros_ec_motion_send_host_cmd(&st->core, 0);
break;
case IIO_CHAN_INFO_CALIBSCALE:
st->core.param.cmd = MOTIONSENSE_CMD_SENSOR_RANGE;
st->core.curr_range = (val << 16) | (val2 / 100);
st->core.param.sensor_range.data = st->core.curr_range;
ret = cros_ec_motion_send_host_cmd(&st->core, 0);
if (ret == 0)
st->core.range_updated = true;
break;
default:
ret = cros_ec_sensors_core_write(&st->core, chan, val, val2,
mask);
break;
}
mutex_unlock(&st->core.cmd_lock);
return ret;
}
static const struct iio_info cros_ec_light_prox_info = {
.read_raw = &cros_ec_light_prox_read,
.write_raw = &cros_ec_light_prox_write,
.read_avail = &cros_ec_sensors_core_read_avail,
};
static int cros_ec_light_prox_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct iio_dev *indio_dev;
struct cros_ec_light_prox_state *state;
struct iio_chan_spec *channel;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*state));
if (!indio_dev)
return -ENOMEM;
ret = cros_ec_sensors_core_init(pdev, indio_dev, true,
cros_ec_sensors_capture);
if (ret)
return ret;
indio_dev->info = &cros_ec_light_prox_info;
state = iio_priv(indio_dev);
channel = state->channels;
/* Common part */
channel->info_mask_shared_by_all =
BIT(IIO_CHAN_INFO_SAMP_FREQ);
channel->info_mask_shared_by_all_available =
BIT(IIO_CHAN_INFO_SAMP_FREQ);
channel->scan_type.realbits = CROS_EC_SENSOR_BITS;
channel->scan_type.storagebits = CROS_EC_SENSOR_BITS;
channel->scan_type.shift = 0;
channel->scan_index = 0;
channel->ext_info = cros_ec_sensors_ext_info;
channel->scan_type.sign = 'u';
/* Sensor specific */
switch (state->core.type) {
case MOTIONSENSE_TYPE_LIGHT:
channel->type = IIO_LIGHT;
channel->info_mask_separate =
BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_CALIBBIAS) |
BIT(IIO_CHAN_INFO_CALIBSCALE);
break;
case MOTIONSENSE_TYPE_PROX:
channel->type = IIO_PROXIMITY;
channel->info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBBIAS) |
BIT(IIO_CHAN_INFO_CALIBSCALE);
break;
default:
dev_warn(dev, "Unknown motion sensor\n");
return -EINVAL;
}
/* Timestamp */
channel++;
channel->type = IIO_TIMESTAMP;
channel->channel = -1;
channel->scan_index = 1;
channel->scan_type.sign = 's';
channel->scan_type.realbits = 64;
channel->scan_type.storagebits = 64;
indio_dev->channels = state->channels;
indio_dev->num_channels = CROS_EC_LIGHT_PROX_MAX_CHANNELS;
state->core.read_ec_sensors_data = cros_ec_sensors_read_cmd;
return cros_ec_sensors_core_register(dev, indio_dev,
cros_ec_sensors_push_data);
}
static const struct platform_device_id cros_ec_light_prox_ids[] = {
{
.name = "cros-ec-prox",
},
{
.name = "cros-ec-light",
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, cros_ec_light_prox_ids);
static struct platform_driver cros_ec_light_prox_platform_driver = {
.driver = {
.name = "cros-ec-light-prox",
.pm = &cros_ec_sensors_pm_ops,
},
.probe = cros_ec_light_prox_probe,
.id_table = cros_ec_light_prox_ids,
};
module_platform_driver(cros_ec_light_prox_platform_driver);
MODULE_DESCRIPTION("ChromeOS EC light/proximity sensors driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/cros_ec_light_prox.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* A iio driver for the light sensor ISL 29018/29023/29035.
*
* IIO driver for monitoring ambient light intensity in luxi, proximity
* sensing and infrared sensing.
*
* Copyright (c) 2010, NVIDIA Corporation.
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/acpi.h>
#define ISL29018_CONV_TIME_MS 100
#define ISL29018_REG_ADD_COMMAND1 0x00
#define ISL29018_CMD1_OPMODE_SHIFT 5
#define ISL29018_CMD1_OPMODE_MASK (7 << ISL29018_CMD1_OPMODE_SHIFT)
#define ISL29018_CMD1_OPMODE_POWER_DOWN 0
#define ISL29018_CMD1_OPMODE_ALS_ONCE 1
#define ISL29018_CMD1_OPMODE_IR_ONCE 2
#define ISL29018_CMD1_OPMODE_PROX_ONCE 3
#define ISL29018_REG_ADD_COMMAND2 0x01
#define ISL29018_CMD2_RESOLUTION_SHIFT 2
#define ISL29018_CMD2_RESOLUTION_MASK (0x3 << ISL29018_CMD2_RESOLUTION_SHIFT)
#define ISL29018_CMD2_RANGE_SHIFT 0
#define ISL29018_CMD2_RANGE_MASK (0x3 << ISL29018_CMD2_RANGE_SHIFT)
#define ISL29018_CMD2_SCHEME_SHIFT 7
#define ISL29018_CMD2_SCHEME_MASK (0x1 << ISL29018_CMD2_SCHEME_SHIFT)
#define ISL29018_REG_ADD_DATA_LSB 0x02
#define ISL29018_REG_ADD_DATA_MSB 0x03
#define ISL29018_REG_TEST 0x08
#define ISL29018_TEST_SHIFT 0
#define ISL29018_TEST_MASK (0xFF << ISL29018_TEST_SHIFT)
#define ISL29035_REG_DEVICE_ID 0x0F
#define ISL29035_DEVICE_ID_SHIFT 0x03
#define ISL29035_DEVICE_ID_MASK (0x7 << ISL29035_DEVICE_ID_SHIFT)
#define ISL29035_DEVICE_ID 0x5
#define ISL29035_BOUT_SHIFT 0x07
#define ISL29035_BOUT_MASK (0x01 << ISL29035_BOUT_SHIFT)
enum isl29018_int_time {
ISL29018_INT_TIME_16,
ISL29018_INT_TIME_12,
ISL29018_INT_TIME_8,
ISL29018_INT_TIME_4,
};
static const unsigned int isl29018_int_utimes[3][4] = {
{90000, 5630, 351, 21},
{90000, 5600, 352, 22},
{105000, 6500, 410, 25},
};
static const struct isl29018_scale {
unsigned int scale;
unsigned int uscale;
} isl29018_scales[4][4] = {
{ {0, 15258}, {0, 61035}, {0, 244140}, {0, 976562} },
{ {0, 244140}, {0, 976562}, {3, 906250}, {15, 625000} },
{ {3, 906250}, {15, 625000}, {62, 500000}, {250, 0} },
{ {62, 500000}, {250, 0}, {1000, 0}, {4000, 0} }
};
struct isl29018_chip {
struct regmap *regmap;
struct mutex lock;
int type;
unsigned int calibscale;
unsigned int ucalibscale;
unsigned int int_time;
struct isl29018_scale scale;
int prox_scheme;
bool suspended;
struct regulator *vcc_reg;
};
static int isl29018_set_integration_time(struct isl29018_chip *chip,
unsigned int utime)
{
unsigned int i;
int ret;
unsigned int int_time, new_int_time;
for (i = 0; i < ARRAY_SIZE(isl29018_int_utimes[chip->type]); ++i) {
if (utime == isl29018_int_utimes[chip->type][i]) {
new_int_time = i;
break;
}
}
if (i >= ARRAY_SIZE(isl29018_int_utimes[chip->type]))
return -EINVAL;
ret = regmap_update_bits(chip->regmap, ISL29018_REG_ADD_COMMAND2,
ISL29018_CMD2_RESOLUTION_MASK,
i << ISL29018_CMD2_RESOLUTION_SHIFT);
if (ret < 0)
return ret;
/* Keep the same range when integration time changes */
int_time = chip->int_time;
for (i = 0; i < ARRAY_SIZE(isl29018_scales[int_time]); ++i) {
if (chip->scale.scale == isl29018_scales[int_time][i].scale &&
chip->scale.uscale == isl29018_scales[int_time][i].uscale) {
chip->scale = isl29018_scales[new_int_time][i];
break;
}
}
chip->int_time = new_int_time;
return 0;
}
static int isl29018_set_scale(struct isl29018_chip *chip, int scale, int uscale)
{
unsigned int i;
int ret;
struct isl29018_scale new_scale;
for (i = 0; i < ARRAY_SIZE(isl29018_scales[chip->int_time]); ++i) {
if (scale == isl29018_scales[chip->int_time][i].scale &&
uscale == isl29018_scales[chip->int_time][i].uscale) {
new_scale = isl29018_scales[chip->int_time][i];
break;
}
}
if (i >= ARRAY_SIZE(isl29018_scales[chip->int_time]))
return -EINVAL;
ret = regmap_update_bits(chip->regmap, ISL29018_REG_ADD_COMMAND2,
ISL29018_CMD2_RANGE_MASK,
i << ISL29018_CMD2_RANGE_SHIFT);
if (ret < 0)
return ret;
chip->scale = new_scale;
return 0;
}
static int isl29018_read_sensor_input(struct isl29018_chip *chip, int mode)
{
int status;
unsigned int lsb;
unsigned int msb;
struct device *dev = regmap_get_device(chip->regmap);
/* Set mode */
status = regmap_write(chip->regmap, ISL29018_REG_ADD_COMMAND1,
mode << ISL29018_CMD1_OPMODE_SHIFT);
if (status) {
dev_err(dev,
"Error in setting operating mode err %d\n", status);
return status;
}
msleep(ISL29018_CONV_TIME_MS);
status = regmap_read(chip->regmap, ISL29018_REG_ADD_DATA_LSB, &lsb);
if (status < 0) {
dev_err(dev,
"Error in reading LSB DATA with err %d\n", status);
return status;
}
status = regmap_read(chip->regmap, ISL29018_REG_ADD_DATA_MSB, &msb);
if (status < 0) {
dev_err(dev,
"Error in reading MSB DATA with error %d\n", status);
return status;
}
dev_vdbg(dev, "MSB 0x%x and LSB 0x%x\n", msb, lsb);
return (msb << 8) | lsb;
}
static int isl29018_read_lux(struct isl29018_chip *chip, int *lux)
{
int lux_data;
unsigned int data_x_range;
lux_data = isl29018_read_sensor_input(chip,
ISL29018_CMD1_OPMODE_ALS_ONCE);
if (lux_data < 0)
return lux_data;
data_x_range = lux_data * chip->scale.scale +
lux_data * chip->scale.uscale / 1000000;
*lux = data_x_range * chip->calibscale +
data_x_range * chip->ucalibscale / 1000000;
return 0;
}
static int isl29018_read_ir(struct isl29018_chip *chip, int *ir)
{
int ir_data;
ir_data = isl29018_read_sensor_input(chip,
ISL29018_CMD1_OPMODE_IR_ONCE);
if (ir_data < 0)
return ir_data;
*ir = ir_data;
return 0;
}
static int isl29018_read_proximity_ir(struct isl29018_chip *chip, int scheme,
int *near_ir)
{
int status;
int prox_data = -1;
int ir_data = -1;
struct device *dev = regmap_get_device(chip->regmap);
/* Do proximity sensing with required scheme */
status = regmap_update_bits(chip->regmap, ISL29018_REG_ADD_COMMAND2,
ISL29018_CMD2_SCHEME_MASK,
scheme << ISL29018_CMD2_SCHEME_SHIFT);
if (status) {
dev_err(dev, "Error in setting operating mode\n");
return status;
}
prox_data = isl29018_read_sensor_input(chip,
ISL29018_CMD1_OPMODE_PROX_ONCE);
if (prox_data < 0)
return prox_data;
if (scheme == 1) {
*near_ir = prox_data;
return 0;
}
ir_data = isl29018_read_sensor_input(chip,
ISL29018_CMD1_OPMODE_IR_ONCE);
if (ir_data < 0)
return ir_data;
if (prox_data >= ir_data)
*near_ir = prox_data - ir_data;
else
*near_ir = 0;
return 0;
}
static ssize_t in_illuminance_scale_available_show
(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct isl29018_chip *chip = iio_priv(indio_dev);
unsigned int i;
int len = 0;
mutex_lock(&chip->lock);
for (i = 0; i < ARRAY_SIZE(isl29018_scales[chip->int_time]); ++i)
len += sprintf(buf + len, "%d.%06d ",
isl29018_scales[chip->int_time][i].scale,
isl29018_scales[chip->int_time][i].uscale);
mutex_unlock(&chip->lock);
buf[len - 1] = '\n';
return len;
}
static ssize_t in_illuminance_integration_time_available_show
(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct isl29018_chip *chip = iio_priv(indio_dev);
unsigned int i;
int len = 0;
for (i = 0; i < ARRAY_SIZE(isl29018_int_utimes[chip->type]); ++i)
len += sprintf(buf + len, "0.%06d ",
isl29018_int_utimes[chip->type][i]);
buf[len - 1] = '\n';
return len;
}
/*
* From ISL29018 Data Sheet (FN6619.4, Oct 8, 2012) regarding the
* infrared suppression:
*
* Proximity Sensing Scheme: Bit 7. This bit programs the function
* of the proximity detection. Logic 0 of this bit, Scheme 0, makes
* full n (4, 8, 12, 16) bits (unsigned) proximity detection. The range
* of Scheme 0 proximity count is from 0 to 2^n. Logic 1 of this bit,
* Scheme 1, makes n-1 (3, 7, 11, 15) bits (2's complementary)
* proximity_less_ambient detection. The range of Scheme 1
* proximity count is from -2^(n-1) to 2^(n-1) . The sign bit is extended
* for resolutions less than 16. While Scheme 0 has wider dynamic
* range, Scheme 1 proximity detection is less affected by the
* ambient IR noise variation.
*
* 0 Sensing IR from LED and ambient
* 1 Sensing IR from LED with ambient IR rejection
*/
static ssize_t proximity_on_chip_ambient_infrared_suppression_show
(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct isl29018_chip *chip = iio_priv(indio_dev);
/*
* Return the "proximity scheme" i.e. if the chip does on chip
* infrared suppression (1 means perform on chip suppression)
*/
return sprintf(buf, "%d\n", chip->prox_scheme);
}
static ssize_t proximity_on_chip_ambient_infrared_suppression_store
(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct isl29018_chip *chip = iio_priv(indio_dev);
int val;
if (kstrtoint(buf, 10, &val))
return -EINVAL;
if (!(val == 0 || val == 1))
return -EINVAL;
/*
* Get the "proximity scheme" i.e. if the chip does on chip
* infrared suppression (1 means perform on chip suppression)
*/
mutex_lock(&chip->lock);
chip->prox_scheme = val;
mutex_unlock(&chip->lock);
return count;
}
static int isl29018_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct isl29018_chip *chip = iio_priv(indio_dev);
int ret = -EINVAL;
mutex_lock(&chip->lock);
if (chip->suspended) {
ret = -EBUSY;
goto write_done;
}
switch (mask) {
case IIO_CHAN_INFO_CALIBSCALE:
if (chan->type == IIO_LIGHT) {
chip->calibscale = val;
chip->ucalibscale = val2;
ret = 0;
}
break;
case IIO_CHAN_INFO_INT_TIME:
if (chan->type == IIO_LIGHT && !val)
ret = isl29018_set_integration_time(chip, val2);
break;
case IIO_CHAN_INFO_SCALE:
if (chan->type == IIO_LIGHT)
ret = isl29018_set_scale(chip, val, val2);
break;
default:
break;
}
write_done:
mutex_unlock(&chip->lock);
return ret;
}
static int isl29018_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
int ret = -EINVAL;
struct isl29018_chip *chip = iio_priv(indio_dev);
mutex_lock(&chip->lock);
if (chip->suspended) {
ret = -EBUSY;
goto read_done;
}
switch (mask) {
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_LIGHT:
ret = isl29018_read_lux(chip, val);
break;
case IIO_INTENSITY:
ret = isl29018_read_ir(chip, val);
break;
case IIO_PROXIMITY:
ret = isl29018_read_proximity_ir(chip,
chip->prox_scheme,
val);
break;
default:
break;
}
if (!ret)
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_INT_TIME:
if (chan->type == IIO_LIGHT) {
*val = 0;
*val2 = isl29018_int_utimes[chip->type][chip->int_time];
ret = IIO_VAL_INT_PLUS_MICRO;
}
break;
case IIO_CHAN_INFO_SCALE:
if (chan->type == IIO_LIGHT) {
*val = chip->scale.scale;
*val2 = chip->scale.uscale;
ret = IIO_VAL_INT_PLUS_MICRO;
}
break;
case IIO_CHAN_INFO_CALIBSCALE:
if (chan->type == IIO_LIGHT) {
*val = chip->calibscale;
*val2 = chip->ucalibscale;
ret = IIO_VAL_INT_PLUS_MICRO;
}
break;
default:
break;
}
read_done:
mutex_unlock(&chip->lock);
return ret;
}
#define ISL29018_LIGHT_CHANNEL { \
.type = IIO_LIGHT, \
.indexed = 1, \
.channel = 0, \
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | \
BIT(IIO_CHAN_INFO_CALIBSCALE) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_INT_TIME), \
}
#define ISL29018_IR_CHANNEL { \
.type = IIO_INTENSITY, \
.modified = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.channel2 = IIO_MOD_LIGHT_IR, \
}
#define ISL29018_PROXIMITY_CHANNEL { \
.type = IIO_PROXIMITY, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
}
static const struct iio_chan_spec isl29018_channels[] = {
ISL29018_LIGHT_CHANNEL,
ISL29018_IR_CHANNEL,
ISL29018_PROXIMITY_CHANNEL,
};
static const struct iio_chan_spec isl29023_channels[] = {
ISL29018_LIGHT_CHANNEL,
ISL29018_IR_CHANNEL,
};
static IIO_DEVICE_ATTR_RO(in_illuminance_integration_time_available, 0);
static IIO_DEVICE_ATTR_RO(in_illuminance_scale_available, 0);
static IIO_DEVICE_ATTR_RW(proximity_on_chip_ambient_infrared_suppression, 0);
#define ISL29018_DEV_ATTR(name) (&iio_dev_attr_##name.dev_attr.attr)
static struct attribute *isl29018_attributes[] = {
ISL29018_DEV_ATTR(in_illuminance_scale_available),
ISL29018_DEV_ATTR(in_illuminance_integration_time_available),
ISL29018_DEV_ATTR(proximity_on_chip_ambient_infrared_suppression),
NULL
};
static struct attribute *isl29023_attributes[] = {
ISL29018_DEV_ATTR(in_illuminance_scale_available),
ISL29018_DEV_ATTR(in_illuminance_integration_time_available),
NULL
};
static const struct attribute_group isl29018_group = {
.attrs = isl29018_attributes,
};
static const struct attribute_group isl29023_group = {
.attrs = isl29023_attributes,
};
enum {
isl29018,
isl29023,
isl29035,
};
static int isl29018_chip_init(struct isl29018_chip *chip)
{
int status;
struct device *dev = regmap_get_device(chip->regmap);
if (chip->type == isl29035) {
unsigned int id;
status = regmap_read(chip->regmap, ISL29035_REG_DEVICE_ID, &id);
if (status < 0) {
dev_err(dev,
"Error reading ID register with error %d\n",
status);
return status;
}
id = (id & ISL29035_DEVICE_ID_MASK) >> ISL29035_DEVICE_ID_SHIFT;
if (id != ISL29035_DEVICE_ID)
return -ENODEV;
/* Clear brownout bit */
status = regmap_update_bits(chip->regmap,
ISL29035_REG_DEVICE_ID,
ISL29035_BOUT_MASK, 0);
if (status < 0)
return status;
}
/*
* Code added per Intersil Application Note 1534:
* When VDD sinks to approximately 1.8V or below, some of
* the part's registers may change their state. When VDD
* recovers to 2.25V (or greater), the part may thus be in an
* unknown mode of operation. The user can return the part to
* a known mode of operation either by (a) setting VDD = 0V for
* 1 second or more and then powering back up with a slew rate
* of 0.5V/ms or greater, or (b) via I2C disable all ALS/PROX
* conversions, clear the test registers, and then rewrite all
* registers to the desired values.
* ...
* For ISL29011, ISL29018, ISL29021, ISL29023
* 1. Write 0x00 to register 0x08 (TEST)
* 2. Write 0x00 to register 0x00 (CMD1)
* 3. Rewrite all registers to the desired values
*
* ISL29018 Data Sheet (FN6619.1, Feb 11, 2010) essentially says
* the same thing EXCEPT the data sheet asks for a 1ms delay after
* writing the CMD1 register.
*/
status = regmap_write(chip->regmap, ISL29018_REG_TEST, 0x0);
if (status < 0) {
dev_err(dev, "Failed to clear isl29018 TEST reg.(%d)\n",
status);
return status;
}
/*
* See Intersil AN1534 comments above.
* "Operating Mode" (COMMAND1) register is reprogrammed when
* data is read from the device.
*/
status = regmap_write(chip->regmap, ISL29018_REG_ADD_COMMAND1, 0);
if (status < 0) {
dev_err(dev, "Failed to clear isl29018 CMD1 reg.(%d)\n",
status);
return status;
}
usleep_range(1000, 2000); /* per data sheet, page 10 */
/* Set defaults */
status = isl29018_set_scale(chip, chip->scale.scale,
chip->scale.uscale);
if (status < 0) {
dev_err(dev, "Init of isl29018 fails\n");
return status;
}
status = isl29018_set_integration_time(chip,
isl29018_int_utimes[chip->type][chip->int_time]);
if (status < 0)
dev_err(dev, "Init of isl29018 fails\n");
return status;
}
static const struct iio_info isl29018_info = {
.attrs = &isl29018_group,
.read_raw = isl29018_read_raw,
.write_raw = isl29018_write_raw,
};
static const struct iio_info isl29023_info = {
.attrs = &isl29023_group,
.read_raw = isl29018_read_raw,
.write_raw = isl29018_write_raw,
};
static bool isl29018_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case ISL29018_REG_ADD_DATA_LSB:
case ISL29018_REG_ADD_DATA_MSB:
case ISL29018_REG_ADD_COMMAND1:
case ISL29018_REG_TEST:
case ISL29035_REG_DEVICE_ID:
return true;
default:
return false;
}
}
static const struct regmap_config isl29018_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = isl29018_is_volatile_reg,
.max_register = ISL29018_REG_TEST,
.num_reg_defaults_raw = ISL29018_REG_TEST + 1,
.cache_type = REGCACHE_RBTREE,
};
static const struct regmap_config isl29035_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = isl29018_is_volatile_reg,
.max_register = ISL29035_REG_DEVICE_ID,
.num_reg_defaults_raw = ISL29035_REG_DEVICE_ID + 1,
.cache_type = REGCACHE_RBTREE,
};
struct isl29018_chip_info {
const struct iio_chan_spec *channels;
int num_channels;
const struct iio_info *indio_info;
const struct regmap_config *regmap_cfg;
};
static const struct isl29018_chip_info isl29018_chip_info_tbl[] = {
[isl29018] = {
.channels = isl29018_channels,
.num_channels = ARRAY_SIZE(isl29018_channels),
.indio_info = &isl29018_info,
.regmap_cfg = &isl29018_regmap_config,
},
[isl29023] = {
.channels = isl29023_channels,
.num_channels = ARRAY_SIZE(isl29023_channels),
.indio_info = &isl29023_info,
.regmap_cfg = &isl29018_regmap_config,
},
[isl29035] = {
.channels = isl29023_channels,
.num_channels = ARRAY_SIZE(isl29023_channels),
.indio_info = &isl29023_info,
.regmap_cfg = &isl29035_regmap_config,
},
};
static const char *isl29018_match_acpi_device(struct device *dev, int *data)
{
const struct acpi_device_id *id;
id = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!id)
return NULL;
*data = (int)id->driver_data;
return dev_name(dev);
}
static void isl29018_disable_regulator_action(void *_data)
{
struct isl29018_chip *chip = _data;
int err;
err = regulator_disable(chip->vcc_reg);
if (err)
pr_err("failed to disable isl29018's VCC regulator!\n");
}
static int isl29018_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct isl29018_chip *chip;
struct iio_dev *indio_dev;
int err;
const char *name = NULL;
int dev_id = 0;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
if (!indio_dev)
return -ENOMEM;
chip = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
if (id) {
name = id->name;
dev_id = id->driver_data;
}
if (ACPI_HANDLE(&client->dev))
name = isl29018_match_acpi_device(&client->dev, &dev_id);
mutex_init(&chip->lock);
chip->type = dev_id;
chip->calibscale = 1;
chip->ucalibscale = 0;
chip->int_time = ISL29018_INT_TIME_16;
chip->scale = isl29018_scales[chip->int_time][0];
chip->suspended = false;
chip->vcc_reg = devm_regulator_get(&client->dev, "vcc");
if (IS_ERR(chip->vcc_reg))
return dev_err_probe(&client->dev, PTR_ERR(chip->vcc_reg),
"failed to get VCC regulator!\n");
err = regulator_enable(chip->vcc_reg);
if (err) {
dev_err(&client->dev, "failed to enable VCC regulator!\n");
return err;
}
err = devm_add_action_or_reset(&client->dev, isl29018_disable_regulator_action,
chip);
if (err) {
dev_err(&client->dev, "failed to setup regulator cleanup action!\n");
return err;
}
chip->regmap = devm_regmap_init_i2c(client,
isl29018_chip_info_tbl[dev_id].regmap_cfg);
if (IS_ERR(chip->regmap)) {
err = PTR_ERR(chip->regmap);
dev_err(&client->dev, "regmap initialization fails: %d\n", err);
return err;
}
err = isl29018_chip_init(chip);
if (err)
return err;
indio_dev->info = isl29018_chip_info_tbl[dev_id].indio_info;
indio_dev->channels = isl29018_chip_info_tbl[dev_id].channels;
indio_dev->num_channels = isl29018_chip_info_tbl[dev_id].num_channels;
indio_dev->name = name;
indio_dev->modes = INDIO_DIRECT_MODE;
return devm_iio_device_register(&client->dev, indio_dev);
}
static int isl29018_suspend(struct device *dev)
{
struct isl29018_chip *chip = iio_priv(dev_get_drvdata(dev));
int ret;
mutex_lock(&chip->lock);
/*
* Since this driver uses only polling commands, we are by default in
* auto shutdown (ie, power-down) mode.
* So we do not have much to do here.
*/
chip->suspended = true;
ret = regulator_disable(chip->vcc_reg);
if (ret)
dev_err(dev, "failed to disable VCC regulator\n");
mutex_unlock(&chip->lock);
return ret;
}
static int isl29018_resume(struct device *dev)
{
struct isl29018_chip *chip = iio_priv(dev_get_drvdata(dev));
int err;
mutex_lock(&chip->lock);
err = regulator_enable(chip->vcc_reg);
if (err) {
dev_err(dev, "failed to enable VCC regulator\n");
mutex_unlock(&chip->lock);
return err;
}
err = isl29018_chip_init(chip);
if (!err)
chip->suspended = false;
mutex_unlock(&chip->lock);
return err;
}
static DEFINE_SIMPLE_DEV_PM_OPS(isl29018_pm_ops, isl29018_suspend,
isl29018_resume);
#ifdef CONFIG_ACPI
static const struct acpi_device_id isl29018_acpi_match[] = {
{"ISL29018", isl29018},
{"ISL29023", isl29023},
{"ISL29035", isl29035},
{},
};
MODULE_DEVICE_TABLE(acpi, isl29018_acpi_match);
#endif
static const struct i2c_device_id isl29018_id[] = {
{"isl29018", isl29018},
{"isl29023", isl29023},
{"isl29035", isl29035},
{}
};
MODULE_DEVICE_TABLE(i2c, isl29018_id);
static const struct of_device_id isl29018_of_match[] = {
{ .compatible = "isil,isl29018", },
{ .compatible = "isil,isl29023", },
{ .compatible = "isil,isl29035", },
{ },
};
MODULE_DEVICE_TABLE(of, isl29018_of_match);
static struct i2c_driver isl29018_driver = {
.driver = {
.name = "isl29018",
.acpi_match_table = ACPI_PTR(isl29018_acpi_match),
.pm = pm_sleep_ptr(&isl29018_pm_ops),
.of_match_table = isl29018_of_match,
},
.probe = isl29018_probe,
.id_table = isl29018_id,
};
module_i2c_driver(isl29018_driver);
MODULE_DESCRIPTION("ISL29018 Ambient Light Sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/isl29018.c |
// SPDX-License-Identifier: GPL-2.0
/*
* VCNL4035 Ambient Light and Proximity Sensor - 7-bit I2C slave address 0x60
*
* Copyright (c) 2018, DENX Software Engineering GmbH
* Author: Parthiban Nallathambi <[email protected]>
*
* TODO: Proximity
*/
#include <linux/bitops.h>
#include <linux/bitfield.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/iio/buffer.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#define VCNL4035_DRV_NAME "vcnl4035"
#define VCNL4035_IRQ_NAME "vcnl4035_event"
#define VCNL4035_REGMAP_NAME "vcnl4035_regmap"
/* Device registers */
#define VCNL4035_ALS_CONF 0x00
#define VCNL4035_ALS_THDH 0x01
#define VCNL4035_ALS_THDL 0x02
#define VCNL4035_ALS_DATA 0x0B
#define VCNL4035_WHITE_DATA 0x0C
#define VCNL4035_INT_FLAG 0x0D
#define VCNL4035_DEV_ID 0x0E
/* Register masks */
#define VCNL4035_MODE_ALS_MASK BIT(0)
#define VCNL4035_MODE_ALS_WHITE_CHAN BIT(8)
#define VCNL4035_MODE_ALS_INT_MASK BIT(1)
#define VCNL4035_ALS_IT_MASK GENMASK(7, 5)
#define VCNL4035_ALS_PERS_MASK GENMASK(3, 2)
#define VCNL4035_INT_ALS_IF_H_MASK BIT(12)
#define VCNL4035_INT_ALS_IF_L_MASK BIT(13)
#define VCNL4035_DEV_ID_MASK GENMASK(7, 0)
/* Default values */
#define VCNL4035_MODE_ALS_ENABLE BIT(0)
#define VCNL4035_MODE_ALS_DISABLE 0x00
#define VCNL4035_MODE_ALS_INT_ENABLE BIT(1)
#define VCNL4035_MODE_ALS_INT_DISABLE 0
#define VCNL4035_DEV_ID_VAL 0x80
#define VCNL4035_ALS_IT_DEFAULT 0x01
#define VCNL4035_ALS_PERS_DEFAULT 0x00
#define VCNL4035_ALS_THDH_DEFAULT 5000
#define VCNL4035_ALS_THDL_DEFAULT 100
#define VCNL4035_SLEEP_DELAY_MS 2000
struct vcnl4035_data {
struct i2c_client *client;
struct regmap *regmap;
unsigned int als_it_val;
unsigned int als_persistence;
unsigned int als_thresh_low;
unsigned int als_thresh_high;
struct iio_trigger *drdy_trigger0;
};
static inline bool vcnl4035_is_triggered(struct vcnl4035_data *data)
{
int ret;
int reg;
ret = regmap_read(data->regmap, VCNL4035_INT_FLAG, ®);
if (ret < 0)
return false;
return !!(reg &
(VCNL4035_INT_ALS_IF_H_MASK | VCNL4035_INT_ALS_IF_L_MASK));
}
static irqreturn_t vcnl4035_drdy_irq_thread(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct vcnl4035_data *data = iio_priv(indio_dev);
if (vcnl4035_is_triggered(data)) {
iio_push_event(indio_dev, IIO_UNMOD_EVENT_CODE(IIO_LIGHT,
0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(indio_dev));
iio_trigger_poll_nested(data->drdy_trigger0);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
/* Triggered buffer */
static irqreturn_t vcnl4035_trigger_consumer_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct vcnl4035_data *data = iio_priv(indio_dev);
/* Ensure naturally aligned timestamp */
u8 buffer[ALIGN(sizeof(u16), sizeof(s64)) + sizeof(s64)] __aligned(8);
int ret;
ret = regmap_read(data->regmap, VCNL4035_ALS_DATA, (int *)buffer);
if (ret < 0) {
dev_err(&data->client->dev,
"Trigger consumer can't read from sensor.\n");
goto fail_read;
}
iio_push_to_buffers_with_timestamp(indio_dev, buffer,
iio_get_time_ns(indio_dev));
fail_read:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int vcnl4035_als_drdy_set_state(struct iio_trigger *trigger,
bool enable_drdy)
{
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trigger);
struct vcnl4035_data *data = iio_priv(indio_dev);
int val = enable_drdy ? VCNL4035_MODE_ALS_INT_ENABLE :
VCNL4035_MODE_ALS_INT_DISABLE;
return regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
VCNL4035_MODE_ALS_INT_MASK,
val);
}
static const struct iio_trigger_ops vcnl4035_trigger_ops = {
.validate_device = iio_trigger_validate_own_device,
.set_trigger_state = vcnl4035_als_drdy_set_state,
};
static int vcnl4035_set_pm_runtime_state(struct vcnl4035_data *data, bool on)
{
int ret;
struct device *dev = &data->client->dev;
if (on) {
ret = pm_runtime_resume_and_get(dev);
} else {
pm_runtime_mark_last_busy(dev);
ret = pm_runtime_put_autosuspend(dev);
}
return ret;
}
/*
* Device IT INT Time (ms) Scale (lux/step)
* 000 50 0.064
* 001 100 0.032
* 010 200 0.016
* 100 400 0.008
* 101 - 111 800 0.004
* Values are proportional, so ALS INT is selected for input due to
* simplicity reason. Integration time value and scaling is
* calculated based on device INT value
*
* Raw value needs to be scaled using ALS steps
*/
static int vcnl4035_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct vcnl4035_data *data = iio_priv(indio_dev);
int ret;
int raw_data;
unsigned int reg;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = vcnl4035_set_pm_runtime_state(data, true);
if (ret < 0)
return ret;
ret = iio_device_claim_direct_mode(indio_dev);
if (!ret) {
if (chan->channel)
reg = VCNL4035_ALS_DATA;
else
reg = VCNL4035_WHITE_DATA;
ret = regmap_read(data->regmap, reg, &raw_data);
iio_device_release_direct_mode(indio_dev);
if (!ret) {
*val = raw_data;
ret = IIO_VAL_INT;
}
}
vcnl4035_set_pm_runtime_state(data, false);
return ret;
case IIO_CHAN_INFO_INT_TIME:
*val = 50;
if (data->als_it_val)
*val = data->als_it_val * 100;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 64;
if (!data->als_it_val)
*val2 = 1000;
else
*val2 = data->als_it_val * 2 * 1000;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
}
static int vcnl4035_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
int ret;
struct vcnl4035_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
if (val <= 0 || val > 800)
return -EINVAL;
ret = vcnl4035_set_pm_runtime_state(data, true);
if (ret < 0)
return ret;
ret = regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
VCNL4035_ALS_IT_MASK,
val / 100);
if (!ret)
data->als_it_val = val / 100;
vcnl4035_set_pm_runtime_state(data, false);
return ret;
default:
return -EINVAL;
}
}
/* No direct ABI for persistence and threshold, so eventing */
static int vcnl4035_read_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info,
int *val, int *val2)
{
struct vcnl4035_data *data = iio_priv(indio_dev);
switch (info) {
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
*val = data->als_thresh_high;
return IIO_VAL_INT;
case IIO_EV_DIR_FALLING:
*val = data->als_thresh_low;
return IIO_VAL_INT;
default:
return -EINVAL;
}
break;
case IIO_EV_INFO_PERIOD:
*val = data->als_persistence;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int vcnl4035_write_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info, int val,
int val2)
{
struct vcnl4035_data *data = iio_priv(indio_dev);
int ret;
switch (info) {
case IIO_EV_INFO_VALUE:
/* 16 bit threshold range 0 - 65535 */
if (val < 0 || val > 65535)
return -EINVAL;
if (dir == IIO_EV_DIR_RISING) {
if (val < data->als_thresh_low)
return -EINVAL;
ret = regmap_write(data->regmap, VCNL4035_ALS_THDH,
val);
if (ret)
return ret;
data->als_thresh_high = val;
} else {
if (val > data->als_thresh_high)
return -EINVAL;
ret = regmap_write(data->regmap, VCNL4035_ALS_THDL,
val);
if (ret)
return ret;
data->als_thresh_low = val;
}
return ret;
case IIO_EV_INFO_PERIOD:
/* allow only 1 2 4 8 as persistence value */
if (val < 0 || val > 8 || hweight8(val) != 1)
return -EINVAL;
ret = regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
VCNL4035_ALS_PERS_MASK, val);
if (!ret)
data->als_persistence = val;
return ret;
default:
return -EINVAL;
}
}
static IIO_CONST_ATTR_INT_TIME_AVAIL("50 100 200 400 800");
static struct attribute *vcnl4035_attributes[] = {
&iio_const_attr_integration_time_available.dev_attr.attr,
NULL,
};
static const struct attribute_group vcnl4035_attribute_group = {
.attrs = vcnl4035_attributes,
};
static const struct iio_info vcnl4035_info = {
.read_raw = vcnl4035_read_raw,
.write_raw = vcnl4035_write_raw,
.read_event_value = vcnl4035_read_thresh,
.write_event_value = vcnl4035_write_thresh,
.attrs = &vcnl4035_attribute_group,
};
static const struct iio_event_spec vcnl4035_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_PERIOD),
},
};
enum vcnl4035_scan_index_order {
VCNL4035_CHAN_INDEX_LIGHT,
VCNL4035_CHAN_INDEX_WHITE_LED,
};
static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
.validate_scan_mask = &iio_validate_scan_mask_onehot,
};
static const struct iio_chan_spec vcnl4035_channels[] = {
{
.type = IIO_LIGHT,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_SCALE),
.event_spec = vcnl4035_event_spec,
.num_event_specs = ARRAY_SIZE(vcnl4035_event_spec),
.scan_index = VCNL4035_CHAN_INDEX_LIGHT,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_LE,
},
},
{
.type = IIO_INTENSITY,
.channel = 1,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_BOTH,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.scan_index = VCNL4035_CHAN_INDEX_WHITE_LED,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_LE,
},
},
};
static int vcnl4035_set_als_power_state(struct vcnl4035_data *data, u8 status)
{
return regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
VCNL4035_MODE_ALS_MASK,
status);
}
static int vcnl4035_init(struct vcnl4035_data *data)
{
int ret;
int id;
ret = regmap_read(data->regmap, VCNL4035_DEV_ID, &id);
if (ret < 0) {
dev_err(&data->client->dev, "Failed to read DEV_ID register\n");
return ret;
}
id = FIELD_GET(VCNL4035_DEV_ID_MASK, id);
if (id != VCNL4035_DEV_ID_VAL) {
dev_err(&data->client->dev, "Wrong id, got %x, expected %x\n",
id, VCNL4035_DEV_ID_VAL);
return -ENODEV;
}
ret = vcnl4035_set_als_power_state(data, VCNL4035_MODE_ALS_ENABLE);
if (ret < 0)
return ret;
/* ALS white channel enable */
ret = regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
VCNL4035_MODE_ALS_WHITE_CHAN,
1);
if (ret) {
dev_err(&data->client->dev, "set white channel enable %d\n",
ret);
return ret;
}
/* set default integration time - 100 ms for ALS */
ret = regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
VCNL4035_ALS_IT_MASK,
VCNL4035_ALS_IT_DEFAULT);
if (ret) {
dev_err(&data->client->dev, "set default ALS IT returned %d\n",
ret);
return ret;
}
data->als_it_val = VCNL4035_ALS_IT_DEFAULT;
/* set default persistence time - 1 for ALS */
ret = regmap_update_bits(data->regmap, VCNL4035_ALS_CONF,
VCNL4035_ALS_PERS_MASK,
VCNL4035_ALS_PERS_DEFAULT);
if (ret) {
dev_err(&data->client->dev, "set default PERS returned %d\n",
ret);
return ret;
}
data->als_persistence = VCNL4035_ALS_PERS_DEFAULT;
/* set default HIGH threshold for ALS */
ret = regmap_write(data->regmap, VCNL4035_ALS_THDH,
VCNL4035_ALS_THDH_DEFAULT);
if (ret) {
dev_err(&data->client->dev, "set default THDH returned %d\n",
ret);
return ret;
}
data->als_thresh_high = VCNL4035_ALS_THDH_DEFAULT;
/* set default LOW threshold for ALS */
ret = regmap_write(data->regmap, VCNL4035_ALS_THDL,
VCNL4035_ALS_THDL_DEFAULT);
if (ret) {
dev_err(&data->client->dev, "set default THDL returned %d\n",
ret);
return ret;
}
data->als_thresh_low = VCNL4035_ALS_THDL_DEFAULT;
return 0;
}
static bool vcnl4035_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case VCNL4035_ALS_CONF:
case VCNL4035_DEV_ID:
return false;
default:
return true;
}
}
static const struct regmap_config vcnl4035_regmap_config = {
.name = VCNL4035_REGMAP_NAME,
.reg_bits = 8,
.val_bits = 16,
.max_register = VCNL4035_DEV_ID,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = vcnl4035_is_volatile_reg,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
};
static int vcnl4035_probe_trigger(struct iio_dev *indio_dev)
{
int ret;
struct vcnl4035_data *data = iio_priv(indio_dev);
data->drdy_trigger0 = devm_iio_trigger_alloc(
indio_dev->dev.parent,
"%s-dev%d", indio_dev->name, iio_device_id(indio_dev));
if (!data->drdy_trigger0)
return -ENOMEM;
data->drdy_trigger0->ops = &vcnl4035_trigger_ops;
iio_trigger_set_drvdata(data->drdy_trigger0, indio_dev);
ret = devm_iio_trigger_register(indio_dev->dev.parent,
data->drdy_trigger0);
if (ret) {
dev_err(&data->client->dev, "iio trigger register failed\n");
return ret;
}
/* Trigger setup */
ret = devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev,
NULL, vcnl4035_trigger_consumer_handler,
&iio_triggered_buffer_setup_ops);
if (ret < 0) {
dev_err(&data->client->dev, "iio triggered buffer setup failed\n");
return ret;
}
/* IRQ to trigger mapping */
ret = devm_request_threaded_irq(&data->client->dev, data->client->irq,
NULL, vcnl4035_drdy_irq_thread,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
VCNL4035_IRQ_NAME, indio_dev);
if (ret < 0)
dev_err(&data->client->dev, "request irq %d for trigger0 failed\n",
data->client->irq);
return ret;
}
static int vcnl4035_probe(struct i2c_client *client)
{
struct vcnl4035_data *data;
struct iio_dev *indio_dev;
struct regmap *regmap;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
regmap = devm_regmap_init_i2c(client, &vcnl4035_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "regmap_init failed!\n");
return PTR_ERR(regmap);
}
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->regmap = regmap;
indio_dev->info = &vcnl4035_info;
indio_dev->name = VCNL4035_DRV_NAME;
indio_dev->channels = vcnl4035_channels;
indio_dev->num_channels = ARRAY_SIZE(vcnl4035_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = vcnl4035_init(data);
if (ret < 0) {
dev_err(&client->dev, "vcnl4035 chip init failed\n");
return ret;
}
if (client->irq > 0) {
ret = vcnl4035_probe_trigger(indio_dev);
if (ret < 0) {
dev_err(&client->dev, "vcnl4035 unable init trigger\n");
goto fail_poweroff;
}
}
ret = pm_runtime_set_active(&client->dev);
if (ret < 0)
goto fail_poweroff;
ret = iio_device_register(indio_dev);
if (ret < 0)
goto fail_poweroff;
pm_runtime_enable(&client->dev);
pm_runtime_set_autosuspend_delay(&client->dev, VCNL4035_SLEEP_DELAY_MS);
pm_runtime_use_autosuspend(&client->dev);
return 0;
fail_poweroff:
vcnl4035_set_als_power_state(data, VCNL4035_MODE_ALS_DISABLE);
return ret;
}
static void vcnl4035_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
int ret;
pm_runtime_dont_use_autosuspend(&client->dev);
pm_runtime_disable(&client->dev);
iio_device_unregister(indio_dev);
pm_runtime_set_suspended(&client->dev);
ret = vcnl4035_set_als_power_state(iio_priv(indio_dev),
VCNL4035_MODE_ALS_DISABLE);
if (ret)
dev_warn(&client->dev, "Failed to put device into standby (%pe)\n",
ERR_PTR(ret));
}
static int vcnl4035_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct vcnl4035_data *data = iio_priv(indio_dev);
int ret;
ret = vcnl4035_set_als_power_state(data, VCNL4035_MODE_ALS_DISABLE);
regcache_mark_dirty(data->regmap);
return ret;
}
static int vcnl4035_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct vcnl4035_data *data = iio_priv(indio_dev);
int ret;
regcache_sync(data->regmap);
ret = vcnl4035_set_als_power_state(data, VCNL4035_MODE_ALS_ENABLE);
if (ret < 0)
return ret;
/* wait for 1 ALS integration cycle */
msleep(data->als_it_val * 100);
return 0;
}
static DEFINE_RUNTIME_DEV_PM_OPS(vcnl4035_pm_ops, vcnl4035_runtime_suspend,
vcnl4035_runtime_resume, NULL);
static const struct i2c_device_id vcnl4035_id[] = {
{ "vcnl4035", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, vcnl4035_id);
static const struct of_device_id vcnl4035_of_match[] = {
{ .compatible = "vishay,vcnl4035", },
{ }
};
MODULE_DEVICE_TABLE(of, vcnl4035_of_match);
static struct i2c_driver vcnl4035_driver = {
.driver = {
.name = VCNL4035_DRV_NAME,
.pm = pm_ptr(&vcnl4035_pm_ops),
.of_match_table = vcnl4035_of_match,
},
.probe = vcnl4035_probe,
.remove = vcnl4035_remove,
.id_table = vcnl4035_id,
};
module_i2c_driver(vcnl4035_driver);
MODULE_AUTHOR("Parthiban Nallathambi <[email protected]>");
MODULE_DESCRIPTION("VCNL4035 Ambient Light Sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/vcnl4035.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* STMicroelectronics uvis25 i2c driver
*
* Copyright 2017 STMicroelectronics Inc.
*
* Lorenzo Bianconi <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include "st_uvis25.h"
#define UVIS25_I2C_AUTO_INCREMENT BIT(7)
static const struct regmap_config st_uvis25_i2c_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.write_flag_mask = UVIS25_I2C_AUTO_INCREMENT,
.read_flag_mask = UVIS25_I2C_AUTO_INCREMENT,
};
static int st_uvis25_i2c_probe(struct i2c_client *client)
{
struct regmap *regmap;
regmap = devm_regmap_init_i2c(client, &st_uvis25_i2c_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "Failed to register i2c regmap %ld\n",
PTR_ERR(regmap));
return PTR_ERR(regmap);
}
return st_uvis25_probe(&client->dev, client->irq, regmap);
}
static const struct of_device_id st_uvis25_i2c_of_match[] = {
{ .compatible = "st,uvis25", },
{},
};
MODULE_DEVICE_TABLE(of, st_uvis25_i2c_of_match);
static const struct i2c_device_id st_uvis25_i2c_id_table[] = {
{ ST_UVIS25_DEV_NAME },
{},
};
MODULE_DEVICE_TABLE(i2c, st_uvis25_i2c_id_table);
static struct i2c_driver st_uvis25_driver = {
.driver = {
.name = "st_uvis25_i2c",
.pm = pm_sleep_ptr(&st_uvis25_pm_ops),
.of_match_table = st_uvis25_i2c_of_match,
},
.probe = st_uvis25_i2c_probe,
.id_table = st_uvis25_i2c_id_table,
};
module_i2c_driver(st_uvis25_driver);
MODULE_AUTHOR("Lorenzo Bianconi <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics uvis25 i2c driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_UVIS25);
| linux-master | drivers/iio/light/st_uvis25_i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* veml6070.c - Support for Vishay VEML6070 UV A light sensor
*
* Copyright 2016 Peter Meerwald-Stadler <[email protected]>
*
* IIO driver for VEML6070 (7-bit I2C slave addresses 0x38 and 0x39)
*
* TODO: integration time, ACK signal
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define VEML6070_DRV_NAME "veml6070"
#define VEML6070_ADDR_CONFIG_DATA_MSB 0x38 /* read: MSB data, write: config */
#define VEML6070_ADDR_DATA_LSB 0x39 /* LSB data */
#define VEML6070_COMMAND_ACK BIT(5) /* raise interrupt when over threshold */
#define VEML6070_COMMAND_IT GENMASK(3, 2) /* bit mask integration time */
#define VEML6070_COMMAND_RSRVD BIT(1) /* reserved, set to 1 */
#define VEML6070_COMMAND_SD BIT(0) /* shutdown mode when set */
#define VEML6070_IT_10 0x04 /* integration time 1x */
struct veml6070_data {
struct i2c_client *client1;
struct i2c_client *client2;
u8 config;
struct mutex lock;
};
static int veml6070_read(struct veml6070_data *data)
{
int ret;
u8 msb, lsb;
mutex_lock(&data->lock);
/* disable shutdown */
ret = i2c_smbus_write_byte(data->client1,
data->config & ~VEML6070_COMMAND_SD);
if (ret < 0)
goto out;
msleep(125 + 10); /* measurement takes up to 125 ms for IT 1x */
ret = i2c_smbus_read_byte(data->client2); /* read MSB, address 0x39 */
if (ret < 0)
goto out;
msb = ret;
ret = i2c_smbus_read_byte(data->client1); /* read LSB, address 0x38 */
if (ret < 0)
goto out;
lsb = ret;
/* shutdown again */
ret = i2c_smbus_write_byte(data->client1, data->config);
if (ret < 0)
goto out;
ret = (msb << 8) | lsb;
out:
mutex_unlock(&data->lock);
return ret;
}
static const struct iio_chan_spec veml6070_channels[] = {
{
.type = IIO_INTENSITY,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_UV,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
},
{
.type = IIO_UVINDEX,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
}
};
static int veml6070_to_uv_index(unsigned val)
{
/*
* conversion of raw UV intensity values to UV index depends on
* integration time (IT) and value of the resistor connected to
* the RSET pin (default: 270 KOhm)
*/
unsigned uvi[11] = {
187, 373, 560, /* low */
746, 933, 1120, /* moderate */
1308, 1494, /* high */
1681, 1868, 2054}; /* very high */
int i;
for (i = 0; i < ARRAY_SIZE(uvi); i++)
if (val <= uvi[i])
return i;
return 11; /* extreme */
}
static int veml6070_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct veml6070_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_PROCESSED:
ret = veml6070_read(data);
if (ret < 0)
return ret;
if (mask == IIO_CHAN_INFO_PROCESSED)
*val = veml6070_to_uv_index(ret);
else
*val = ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static const struct iio_info veml6070_info = {
.read_raw = veml6070_read_raw,
};
static int veml6070_probe(struct i2c_client *client)
{
struct veml6070_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client1 = client;
mutex_init(&data->lock);
indio_dev->info = &veml6070_info;
indio_dev->channels = veml6070_channels;
indio_dev->num_channels = ARRAY_SIZE(veml6070_channels);
indio_dev->name = VEML6070_DRV_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
data->client2 = i2c_new_dummy_device(client->adapter, VEML6070_ADDR_DATA_LSB);
if (IS_ERR(data->client2)) {
dev_err(&client->dev, "i2c device for second chip address failed\n");
return PTR_ERR(data->client2);
}
data->config = VEML6070_IT_10 | VEML6070_COMMAND_RSRVD |
VEML6070_COMMAND_SD;
ret = i2c_smbus_write_byte(data->client1, data->config);
if (ret < 0)
goto fail;
ret = iio_device_register(indio_dev);
if (ret < 0)
goto fail;
return ret;
fail:
i2c_unregister_device(data->client2);
return ret;
}
static void veml6070_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct veml6070_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
i2c_unregister_device(data->client2);
}
static const struct i2c_device_id veml6070_id[] = {
{ "veml6070", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, veml6070_id);
static struct i2c_driver veml6070_driver = {
.driver = {
.name = VEML6070_DRV_NAME,
},
.probe = veml6070_probe,
.remove = veml6070_remove,
.id_table = veml6070_id,
};
module_i2c_driver(veml6070_driver);
MODULE_AUTHOR("Peter Meerwald-Stadler <[email protected]>");
MODULE_DESCRIPTION("Vishay VEML6070 UV A light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/veml6070.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ACPI Ambient Light Sensor Driver
*
* Based on ALS driver:
* Copyright (C) 2009 Zhang Rui <[email protected]>
*
* Rework for IIO subsystem:
* Copyright (C) 2012-2013 Martin Liska <[email protected]>
*
* Final cleanup and debugging:
* Copyright (C) 2013-2014 Marek Vasut <[email protected]>
* Copyright (C) 2015 Gabriele Mazzotta <[email protected]>
*/
#include <linux/module.h>
#include <linux/acpi.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/mutex.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#define ACPI_ALS_CLASS "als"
#define ACPI_ALS_DEVICE_NAME "acpi-als"
#define ACPI_ALS_NOTIFY_ILLUMINANCE 0x80
/*
* So far, there's only one channel in here, but the specification for
* ACPI0008 says there can be more to what the block can report. Like
* chromaticity and such. We are ready for incoming additions!
*/
static const struct iio_chan_spec acpi_als_channels[] = {
{
.type = IIO_LIGHT,
.scan_type = {
.sign = 's',
.realbits = 32,
.storagebits = 32,
},
/* _RAW is here for backward ABI compatibility */
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_PROCESSED),
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
/*
* The event buffer contains timestamp and all the data from
* the ACPI0008 block. There are multiple, but so far we only
* support _ALI (illuminance): One channel, padding and timestamp.
*/
#define ACPI_ALS_EVT_BUFFER_SIZE \
(sizeof(s32) + sizeof(s32) + sizeof(s64))
struct acpi_als {
struct acpi_device *device;
struct mutex lock;
struct iio_trigger *trig;
s32 evt_buffer[ACPI_ALS_EVT_BUFFER_SIZE / sizeof(s32)] __aligned(8);
};
/*
* All types of properties the ACPI0008 block can report. The ALI, ALC, ALT
* and ALP can all be handled by acpi_als_read_value() below, while the ALR is
* special.
*
* The _ALR property returns tables that can be used to fine-tune the values
* reported by the other props based on the particular hardware type and it's
* location (it contains tables for "rainy", "bright inhouse lighting" etc.).
*
* So far, we support only ALI (illuminance).
*/
#define ACPI_ALS_ILLUMINANCE "_ALI"
#define ACPI_ALS_CHROMATICITY "_ALC"
#define ACPI_ALS_COLOR_TEMP "_ALT"
#define ACPI_ALS_POLLING "_ALP"
#define ACPI_ALS_TABLES "_ALR"
static int acpi_als_read_value(struct acpi_als *als, char *prop, s32 *val)
{
unsigned long long temp_val;
acpi_status status;
status = acpi_evaluate_integer(als->device->handle, prop, NULL,
&temp_val);
if (ACPI_FAILURE(status)) {
acpi_evaluation_failure_warn(als->device->handle, prop, status);
return -EIO;
}
*val = temp_val;
return 0;
}
static void acpi_als_notify(struct acpi_device *device, u32 event)
{
struct iio_dev *indio_dev = acpi_driver_data(device);
struct acpi_als *als = iio_priv(indio_dev);
if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev)) {
switch (event) {
case ACPI_ALS_NOTIFY_ILLUMINANCE:
iio_trigger_poll_nested(als->trig);
break;
default:
/* Unhandled event */
dev_dbg(&device->dev,
"Unhandled ACPI ALS event (%08x)!\n",
event);
}
}
}
static int acpi_als_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct acpi_als *als = iio_priv(indio_dev);
s32 temp_val;
int ret;
if ((mask != IIO_CHAN_INFO_PROCESSED) && (mask != IIO_CHAN_INFO_RAW))
return -EINVAL;
/* we support only illumination (_ALI) so far. */
if (chan->type != IIO_LIGHT)
return -EINVAL;
ret = acpi_als_read_value(als, ACPI_ALS_ILLUMINANCE, &temp_val);
if (ret < 0)
return ret;
*val = temp_val;
return IIO_VAL_INT;
}
static const struct iio_info acpi_als_info = {
.read_raw = acpi_als_read_raw,
};
static irqreturn_t acpi_als_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct acpi_als *als = iio_priv(indio_dev);
s32 *buffer = als->evt_buffer;
s32 val;
int ret;
mutex_lock(&als->lock);
ret = acpi_als_read_value(als, ACPI_ALS_ILLUMINANCE, &val);
if (ret < 0)
goto out;
*buffer = val;
/*
* When coming from own trigger via polls, set polling function
* timestamp here. Given ACPI notifier is already in a thread and call
* function directly, there is no need to set the timestamp in the
* notify function.
*
* If the timestamp was actually 0, the timestamp is set one more time.
*/
if (!pf->timestamp)
pf->timestamp = iio_get_time_ns(indio_dev);
iio_push_to_buffers_with_timestamp(indio_dev, buffer, pf->timestamp);
out:
mutex_unlock(&als->lock);
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int acpi_als_add(struct acpi_device *device)
{
struct device *dev = &device->dev;
struct iio_dev *indio_dev;
struct acpi_als *als;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*als));
if (!indio_dev)
return -ENOMEM;
als = iio_priv(indio_dev);
device->driver_data = indio_dev;
als->device = device;
mutex_init(&als->lock);
indio_dev->name = ACPI_ALS_DEVICE_NAME;
indio_dev->info = &acpi_als_info;
indio_dev->channels = acpi_als_channels;
indio_dev->num_channels = ARRAY_SIZE(acpi_als_channels);
als->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,
iio_device_id(indio_dev));
if (!als->trig)
return -ENOMEM;
ret = devm_iio_trigger_register(dev, als->trig);
if (ret)
return ret;
/*
* Set hardware trigger by default to let events flow when
* BIOS support notification.
*/
indio_dev->trig = iio_trigger_get(als->trig);
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
iio_pollfunc_store_time,
acpi_als_trigger_handler,
NULL);
if (ret)
return ret;
return devm_iio_device_register(dev, indio_dev);
}
static const struct acpi_device_id acpi_als_device_ids[] = {
{"ACPI0008", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, acpi_als_device_ids);
static struct acpi_driver acpi_als_driver = {
.name = "acpi_als",
.class = ACPI_ALS_CLASS,
.ids = acpi_als_device_ids,
.ops = {
.add = acpi_als_add,
.notify = acpi_als_notify,
},
};
module_acpi_driver(acpi_als_driver);
MODULE_AUTHOR("Zhang Rui <[email protected]>");
MODULE_AUTHOR("Martin Liska <[email protected]>");
MODULE_AUTHOR("Marek Vasut <[email protected]>");
MODULE_DESCRIPTION("ACPI Ambient Light Sensor Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/acpi-als.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* vcnl4000.c - Support for Vishay VCNL4000/4010/4020/4040/4200 combined ambient
* light and proximity sensor
*
* Copyright 2012 Peter Meerwald <[email protected]>
* Copyright 2019 Pursim SPC
* Copyright 2020 Mathieu Othacehe <[email protected]>
*
* IIO driver for:
* VCNL4000/10/20 (7-bit I2C slave address 0x13)
* VCNL4040 (7-bit I2C slave address 0x60)
* VCNL4200 (7-bit I2C slave address 0x51)
*
* TODO:
* allow to adjust IR current
* interrupts (VCNL4040, VCNL4200)
*/
#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/units.h>
#include <linux/iio/buffer.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#define VCNL4000_DRV_NAME "vcnl4000"
#define VCNL4000_PROD_ID 0x01
#define VCNL4010_PROD_ID 0x02 /* for VCNL4020, VCNL4010 */
#define VCNL4040_PROD_ID 0x86
#define VCNL4200_PROD_ID 0x58
#define VCNL4000_COMMAND 0x80 /* Command register */
#define VCNL4000_PROD_REV 0x81 /* Product ID and Revision ID */
#define VCNL4010_PROX_RATE 0x82 /* Proximity rate */
#define VCNL4000_LED_CURRENT 0x83 /* IR LED current for proximity mode */
#define VCNL4000_AL_PARAM 0x84 /* Ambient light parameter register */
#define VCNL4010_ALS_PARAM 0x84 /* ALS rate */
#define VCNL4000_AL_RESULT_HI 0x85 /* Ambient light result register, MSB */
#define VCNL4000_AL_RESULT_LO 0x86 /* Ambient light result register, LSB */
#define VCNL4000_PS_RESULT_HI 0x87 /* Proximity result register, MSB */
#define VCNL4000_PS_RESULT_LO 0x88 /* Proximity result register, LSB */
#define VCNL4000_PS_MEAS_FREQ 0x89 /* Proximity test signal frequency */
#define VCNL4010_INT_CTRL 0x89 /* Interrupt control */
#define VCNL4000_PS_MOD_ADJ 0x8a /* Proximity modulator timing adjustment */
#define VCNL4010_LOW_THR_HI 0x8a /* Low threshold, MSB */
#define VCNL4010_LOW_THR_LO 0x8b /* Low threshold, LSB */
#define VCNL4010_HIGH_THR_HI 0x8c /* High threshold, MSB */
#define VCNL4010_HIGH_THR_LO 0x8d /* High threshold, LSB */
#define VCNL4010_ISR 0x8e /* Interrupt status */
#define VCNL4200_AL_CONF 0x00 /* Ambient light configuration */
#define VCNL4200_PS_CONF1 0x03 /* Proximity configuration */
#define VCNL4200_PS_CONF3 0x04 /* Proximity configuration */
#define VCNL4040_PS_THDL_LM 0x06 /* Proximity threshold low */
#define VCNL4040_PS_THDH_LM 0x07 /* Proximity threshold high */
#define VCNL4040_ALS_THDL_LM 0x02 /* Ambient light threshold low */
#define VCNL4040_ALS_THDH_LM 0x01 /* Ambient light threshold high */
#define VCNL4200_PS_DATA 0x08 /* Proximity data */
#define VCNL4200_AL_DATA 0x09 /* Ambient light data */
#define VCNL4040_INT_FLAGS 0x0b /* Interrupt register */
#define VCNL4200_INT_FLAGS 0x0d /* Interrupt register */
#define VCNL4200_DEV_ID 0x0e /* Device ID, slave address and version */
#define VCNL4040_DEV_ID 0x0c /* Device ID and version */
/* Bit masks for COMMAND register */
#define VCNL4000_AL_RDY BIT(6) /* ALS data ready? */
#define VCNL4000_PS_RDY BIT(5) /* proximity data ready? */
#define VCNL4000_AL_OD BIT(4) /* start on-demand ALS measurement */
#define VCNL4000_PS_OD BIT(3) /* start on-demand proximity measurement */
#define VCNL4000_ALS_EN BIT(2) /* start ALS measurement */
#define VCNL4000_PROX_EN BIT(1) /* start proximity measurement */
#define VCNL4000_SELF_TIMED_EN BIT(0) /* start self-timed measurement */
#define VCNL4040_ALS_CONF_ALS_SHUTDOWN BIT(0)
#define VCNL4040_ALS_CONF_IT GENMASK(7, 6) /* Ambient integration time */
#define VCNL4040_ALS_CONF_INT_EN BIT(1) /* Ambient light Interrupt enable */
#define VCNL4040_ALS_CONF_PERS GENMASK(3, 2) /* Ambient interrupt persistence setting */
#define VCNL4040_PS_CONF1_PS_SHUTDOWN BIT(0)
#define VCNL4040_PS_CONF2_PS_IT GENMASK(3, 1) /* Proximity integration time */
#define VCNL4040_CONF1_PS_PERS GENMASK(5, 4) /* Proximity interrupt persistence setting */
#define VCNL4040_PS_CONF2_PS_INT GENMASK(9, 8) /* Proximity interrupt mode */
#define VCNL4040_PS_CONF3_MPS GENMASK(6, 5) /* Proximity multi pulse number */
#define VCNL4040_PS_MS_LED_I GENMASK(10, 8) /* Proximity current */
#define VCNL4040_PS_IF_AWAY BIT(8) /* Proximity event cross low threshold */
#define VCNL4040_PS_IF_CLOSE BIT(9) /* Proximity event cross high threshold */
#define VCNL4040_ALS_RISING BIT(12) /* Ambient Light cross high threshold */
#define VCNL4040_ALS_FALLING BIT(13) /* Ambient Light cross low threshold */
/* Bit masks for interrupt registers. */
#define VCNL4010_INT_THR_SEL BIT(0) /* Select threshold interrupt source */
#define VCNL4010_INT_THR_EN BIT(1) /* Threshold interrupt type */
#define VCNL4010_INT_ALS_EN BIT(2) /* Enable on ALS data ready */
#define VCNL4010_INT_PROX_EN BIT(3) /* Enable on proximity data ready */
#define VCNL4010_INT_THR_HIGH 0 /* High threshold exceeded */
#define VCNL4010_INT_THR_LOW 1 /* Low threshold exceeded */
#define VCNL4010_INT_ALS 2 /* ALS data ready */
#define VCNL4010_INT_PROXIMITY 3 /* Proximity data ready */
#define VCNL4010_INT_THR \
(BIT(VCNL4010_INT_THR_LOW) | BIT(VCNL4010_INT_THR_HIGH))
#define VCNL4010_INT_DRDY \
(BIT(VCNL4010_INT_PROXIMITY) | BIT(VCNL4010_INT_ALS))
static const int vcnl4010_prox_sampling_frequency[][2] = {
{1, 950000},
{3, 906250},
{7, 812500},
{16, 625000},
{31, 250000},
{62, 500000},
{125, 0},
{250, 0},
};
static const int vcnl4040_ps_it_times[][2] = {
{0, 100},
{0, 150},
{0, 200},
{0, 250},
{0, 300},
{0, 350},
{0, 400},
{0, 800},
};
static const int vcnl4200_ps_it_times[][2] = {
{0, 96},
{0, 144},
{0, 192},
{0, 384},
{0, 768},
{0, 864},
};
static const int vcnl4040_als_it_times[][2] = {
{0, 80000},
{0, 160000},
{0, 320000},
{0, 640000},
};
static const int vcnl4200_als_it_times[][2] = {
{0, 50000},
{0, 100000},
{0, 200000},
{0, 400000},
};
static const int vcnl4040_ps_calibbias_ua[][2] = {
{0, 50000},
{0, 75000},
{0, 100000},
{0, 120000},
{0, 140000},
{0, 160000},
{0, 180000},
{0, 200000},
};
static const int vcnl4040_als_persistence[] = {1, 2, 4, 8};
static const int vcnl4040_ps_persistence[] = {1, 2, 3, 4};
static const int vcnl4040_ps_oversampling_ratio[] = {1, 2, 4, 8};
#define VCNL4000_SLEEP_DELAY_MS 2000 /* before we enter pm_runtime_suspend */
enum vcnl4000_device_ids {
VCNL4000,
VCNL4010,
VCNL4040,
VCNL4200,
};
struct vcnl4200_channel {
u8 reg;
ktime_t last_measurement;
ktime_t sampling_rate;
struct mutex lock;
};
struct vcnl4000_data {
struct i2c_client *client;
enum vcnl4000_device_ids id;
int rev;
int al_scale;
u8 ps_int; /* proximity interrupt mode */
u8 als_int; /* ambient light interrupt mode*/
const struct vcnl4000_chip_spec *chip_spec;
struct mutex vcnl4000_lock;
struct vcnl4200_channel vcnl4200_al;
struct vcnl4200_channel vcnl4200_ps;
uint32_t near_level;
};
struct vcnl4000_chip_spec {
const char *prod;
struct iio_chan_spec const *channels;
const int num_channels;
const struct iio_info *info;
const struct iio_buffer_setup_ops *buffer_setup_ops;
int (*init)(struct vcnl4000_data *data);
int (*measure_light)(struct vcnl4000_data *data, int *val);
int (*measure_proximity)(struct vcnl4000_data *data, int *val);
int (*set_power_state)(struct vcnl4000_data *data, bool on);
irqreturn_t (*irq_thread)(int irq, void *priv);
irqreturn_t (*trig_buffer_func)(int irq, void *priv);
u8 int_reg;
const int(*ps_it_times)[][2];
const int num_ps_it_times;
const int(*als_it_times)[][2];
const int num_als_it_times;
const unsigned int ulux_step;
};
static const struct i2c_device_id vcnl4000_id[] = {
{ "vcnl4000", VCNL4000 },
{ "vcnl4010", VCNL4010 },
{ "vcnl4020", VCNL4010 },
{ "vcnl4040", VCNL4040 },
{ "vcnl4200", VCNL4200 },
{ }
};
MODULE_DEVICE_TABLE(i2c, vcnl4000_id);
static int vcnl4000_set_power_state(struct vcnl4000_data *data, bool on)
{
/* no suspend op */
return 0;
}
static int vcnl4000_init(struct vcnl4000_data *data)
{
int ret, prod_id;
ret = i2c_smbus_read_byte_data(data->client, VCNL4000_PROD_REV);
if (ret < 0)
return ret;
prod_id = ret >> 4;
switch (prod_id) {
case VCNL4000_PROD_ID:
if (data->id != VCNL4000)
dev_warn(&data->client->dev,
"wrong device id, use vcnl4000");
break;
case VCNL4010_PROD_ID:
if (data->id != VCNL4010)
dev_warn(&data->client->dev,
"wrong device id, use vcnl4010/4020");
break;
default:
return -ENODEV;
}
data->rev = ret & 0xf;
data->al_scale = 250000;
return data->chip_spec->set_power_state(data, true);
};
static ssize_t vcnl4000_write_als_enable(struct vcnl4000_data *data, bool en)
{
int ret;
mutex_lock(&data->vcnl4000_lock);
ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF);
if (ret < 0)
goto out;
if (en)
ret &= ~VCNL4040_ALS_CONF_ALS_SHUTDOWN;
else
ret |= VCNL4040_ALS_CONF_ALS_SHUTDOWN;
ret = i2c_smbus_write_word_data(data->client, VCNL4200_AL_CONF, ret);
out:
mutex_unlock(&data->vcnl4000_lock);
return ret;
}
static ssize_t vcnl4000_write_ps_enable(struct vcnl4000_data *data, bool en)
{
int ret;
mutex_lock(&data->vcnl4000_lock);
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1);
if (ret < 0)
goto out;
if (en)
ret &= ~VCNL4040_PS_CONF1_PS_SHUTDOWN;
else
ret |= VCNL4040_PS_CONF1_PS_SHUTDOWN;
ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1, ret);
out:
mutex_unlock(&data->vcnl4000_lock);
return ret;
}
static int vcnl4200_set_power_state(struct vcnl4000_data *data, bool on)
{
int ret;
/* Do not power down if interrupts are enabled */
if (!on && (data->ps_int || data->als_int))
return 0;
ret = vcnl4000_write_als_enable(data, on);
if (ret < 0)
return ret;
ret = vcnl4000_write_ps_enable(data, on);
if (ret < 0)
return ret;
if (on) {
/* Wait at least one integration cycle before fetching data */
data->vcnl4200_al.last_measurement = ktime_get();
data->vcnl4200_ps.last_measurement = ktime_get();
}
return 0;
}
static int vcnl4200_init(struct vcnl4000_data *data)
{
int ret, id;
ret = i2c_smbus_read_word_data(data->client, VCNL4200_DEV_ID);
if (ret < 0)
return ret;
id = ret & 0xff;
if (id != VCNL4200_PROD_ID) {
ret = i2c_smbus_read_word_data(data->client, VCNL4040_DEV_ID);
if (ret < 0)
return ret;
id = ret & 0xff;
if (id != VCNL4040_PROD_ID)
return -ENODEV;
}
dev_dbg(&data->client->dev, "device id 0x%x", id);
data->rev = (ret >> 8) & 0xf;
data->ps_int = 0;
data->als_int = 0;
data->vcnl4200_al.reg = VCNL4200_AL_DATA;
data->vcnl4200_ps.reg = VCNL4200_PS_DATA;
switch (id) {
case VCNL4200_PROD_ID:
/* Default wait time is 50ms, add 20% tolerance. */
data->vcnl4200_al.sampling_rate = ktime_set(0, 60000 * 1000);
/* Default wait time is 4.8ms, add 20% tolerance. */
data->vcnl4200_ps.sampling_rate = ktime_set(0, 5760 * 1000);
break;
case VCNL4040_PROD_ID:
/* Default wait time is 80ms, add 20% tolerance. */
data->vcnl4200_al.sampling_rate = ktime_set(0, 96000 * 1000);
/* Default wait time is 5ms, add 20% tolerance. */
data->vcnl4200_ps.sampling_rate = ktime_set(0, 6000 * 1000);
break;
}
data->al_scale = data->chip_spec->ulux_step;
mutex_init(&data->vcnl4200_al.lock);
mutex_init(&data->vcnl4200_ps.lock);
ret = data->chip_spec->set_power_state(data, true);
if (ret < 0)
return ret;
return 0;
};
static int vcnl4000_read_data(struct vcnl4000_data *data, u8 data_reg, int *val)
{
s32 ret;
ret = i2c_smbus_read_word_swapped(data->client, data_reg);
if (ret < 0)
return ret;
*val = ret;
return 0;
}
static int vcnl4000_write_data(struct vcnl4000_data *data, u8 data_reg, int val)
{
if (val > U16_MAX)
return -ERANGE;
return i2c_smbus_write_word_swapped(data->client, data_reg, val);
}
static int vcnl4000_measure(struct vcnl4000_data *data, u8 req_mask,
u8 rdy_mask, u8 data_reg, int *val)
{
int tries = 20;
int ret;
mutex_lock(&data->vcnl4000_lock);
ret = i2c_smbus_write_byte_data(data->client, VCNL4000_COMMAND,
req_mask);
if (ret < 0)
goto fail;
/* wait for data to become ready */
while (tries--) {
ret = i2c_smbus_read_byte_data(data->client, VCNL4000_COMMAND);
if (ret < 0)
goto fail;
if (ret & rdy_mask)
break;
msleep(20); /* measurement takes up to 100 ms */
}
if (tries < 0) {
dev_err(&data->client->dev,
"vcnl4000_measure() failed, data not ready\n");
ret = -EIO;
goto fail;
}
ret = vcnl4000_read_data(data, data_reg, val);
if (ret < 0)
goto fail;
mutex_unlock(&data->vcnl4000_lock);
return 0;
fail:
mutex_unlock(&data->vcnl4000_lock);
return ret;
}
static int vcnl4200_measure(struct vcnl4000_data *data,
struct vcnl4200_channel *chan, int *val)
{
int ret;
s64 delta;
ktime_t next_measurement;
mutex_lock(&chan->lock);
next_measurement = ktime_add(chan->last_measurement,
chan->sampling_rate);
delta = ktime_us_delta(next_measurement, ktime_get());
if (delta > 0)
usleep_range(delta, delta + 500);
chan->last_measurement = ktime_get();
mutex_unlock(&chan->lock);
ret = i2c_smbus_read_word_data(data->client, chan->reg);
if (ret < 0)
return ret;
*val = ret;
return 0;
}
static int vcnl4000_measure_light(struct vcnl4000_data *data, int *val)
{
return vcnl4000_measure(data,
VCNL4000_AL_OD, VCNL4000_AL_RDY,
VCNL4000_AL_RESULT_HI, val);
}
static int vcnl4200_measure_light(struct vcnl4000_data *data, int *val)
{
return vcnl4200_measure(data, &data->vcnl4200_al, val);
}
static int vcnl4000_measure_proximity(struct vcnl4000_data *data, int *val)
{
return vcnl4000_measure(data,
VCNL4000_PS_OD, VCNL4000_PS_RDY,
VCNL4000_PS_RESULT_HI, val);
}
static int vcnl4200_measure_proximity(struct vcnl4000_data *data, int *val)
{
return vcnl4200_measure(data, &data->vcnl4200_ps, val);
}
static int vcnl4010_read_proxy_samp_freq(struct vcnl4000_data *data, int *val,
int *val2)
{
int ret;
ret = i2c_smbus_read_byte_data(data->client, VCNL4010_PROX_RATE);
if (ret < 0)
return ret;
if (ret >= ARRAY_SIZE(vcnl4010_prox_sampling_frequency))
return -EINVAL;
*val = vcnl4010_prox_sampling_frequency[ret][0];
*val2 = vcnl4010_prox_sampling_frequency[ret][1];
return 0;
}
static bool vcnl4010_is_in_periodic_mode(struct vcnl4000_data *data)
{
int ret;
ret = i2c_smbus_read_byte_data(data->client, VCNL4000_COMMAND);
if (ret < 0)
return false;
return !!(ret & VCNL4000_SELF_TIMED_EN);
}
static int vcnl4000_set_pm_runtime_state(struct vcnl4000_data *data, bool on)
{
struct device *dev = &data->client->dev;
int ret;
if (on) {
ret = pm_runtime_resume_and_get(dev);
} else {
pm_runtime_mark_last_busy(dev);
ret = pm_runtime_put_autosuspend(dev);
}
return ret;
}
static int vcnl4040_read_als_it(struct vcnl4000_data *data, int *val, int *val2)
{
int ret;
ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF);
if (ret < 0)
return ret;
ret = FIELD_GET(VCNL4040_ALS_CONF_IT, ret);
if (ret >= data->chip_spec->num_als_it_times)
return -EINVAL;
*val = (*data->chip_spec->als_it_times)[ret][0];
*val2 = (*data->chip_spec->als_it_times)[ret][1];
return 0;
}
static ssize_t vcnl4040_write_als_it(struct vcnl4000_data *data, int val)
{
unsigned int i;
int ret;
u16 regval;
for (i = 0; i < data->chip_spec->num_als_it_times; i++) {
if (val == (*data->chip_spec->als_it_times)[i][1])
break;
}
if (i == data->chip_spec->num_als_it_times)
return -EINVAL;
data->vcnl4200_al.sampling_rate = ktime_set(0, val * 1200);
data->al_scale = div_u64(mul_u32_u32(data->chip_spec->ulux_step,
(*data->chip_spec->als_it_times)[0][1]),
val);
mutex_lock(&data->vcnl4000_lock);
ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF);
if (ret < 0)
goto out_unlock;
regval = FIELD_PREP(VCNL4040_ALS_CONF_IT, i);
regval |= (ret & ~VCNL4040_ALS_CONF_IT);
ret = i2c_smbus_write_word_data(data->client,
VCNL4200_AL_CONF,
regval);
out_unlock:
mutex_unlock(&data->vcnl4000_lock);
return ret;
}
static int vcnl4040_read_ps_it(struct vcnl4000_data *data, int *val, int *val2)
{
int ret;
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1);
if (ret < 0)
return ret;
ret = FIELD_GET(VCNL4040_PS_CONF2_PS_IT, ret);
if (ret >= data->chip_spec->num_ps_it_times)
return -EINVAL;
*val = (*data->chip_spec->ps_it_times)[ret][0];
*val2 = (*data->chip_spec->ps_it_times)[ret][1];
return 0;
}
static ssize_t vcnl4040_write_ps_it(struct vcnl4000_data *data, int val)
{
unsigned int i;
int ret, index = -1;
u16 regval;
for (i = 0; i < data->chip_spec->num_ps_it_times; i++) {
if (val == (*data->chip_spec->ps_it_times)[i][1]) {
index = i;
break;
}
}
if (index < 0)
return -EINVAL;
data->vcnl4200_ps.sampling_rate = ktime_set(0, val * 60 * NSEC_PER_USEC);
mutex_lock(&data->vcnl4000_lock);
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1);
if (ret < 0)
goto out;
regval = (ret & ~VCNL4040_PS_CONF2_PS_IT) |
FIELD_PREP(VCNL4040_PS_CONF2_PS_IT, index);
ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1,
regval);
out:
mutex_unlock(&data->vcnl4000_lock);
return ret;
}
static ssize_t vcnl4040_read_als_period(struct vcnl4000_data *data, int *val, int *val2)
{
int ret, ret_pers, it;
int64_t val_c;
ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF);
if (ret < 0)
return ret;
ret_pers = FIELD_GET(VCNL4040_ALS_CONF_PERS, ret);
if (ret_pers >= ARRAY_SIZE(vcnl4040_als_persistence))
return -EINVAL;
it = FIELD_GET(VCNL4040_ALS_CONF_IT, ret);
if (it >= data->chip_spec->num_als_it_times)
return -EINVAL;
val_c = mul_u32_u32((*data->chip_spec->als_it_times)[it][1],
vcnl4040_als_persistence[ret_pers]);
*val = div_u64_rem(val_c, MICRO, val2);
return IIO_VAL_INT_PLUS_MICRO;
}
static ssize_t vcnl4040_write_als_period(struct vcnl4000_data *data, int val, int val2)
{
unsigned int i;
int ret, it;
u16 regval;
u64 val_n = mul_u32_u32(val, MICRO) + val2;
ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF);
if (ret < 0)
return ret;
it = FIELD_GET(VCNL4040_ALS_CONF_IT, ret);
if (it >= data->chip_spec->num_als_it_times)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(vcnl4040_als_persistence) - 1; i++) {
if (val_n < mul_u32_u32(vcnl4040_als_persistence[i],
(*data->chip_spec->als_it_times)[it][1]))
break;
}
mutex_lock(&data->vcnl4000_lock);
ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF);
if (ret < 0)
goto out_unlock;
regval = FIELD_PREP(VCNL4040_ALS_CONF_PERS, i);
regval |= (ret & ~VCNL4040_ALS_CONF_PERS);
ret = i2c_smbus_write_word_data(data->client, VCNL4200_AL_CONF,
regval);
out_unlock:
mutex_unlock(&data->vcnl4000_lock);
return ret;
}
static ssize_t vcnl4040_read_ps_period(struct vcnl4000_data *data, int *val, int *val2)
{
int ret, ret_pers, it;
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1);
if (ret < 0)
return ret;
ret_pers = FIELD_GET(VCNL4040_CONF1_PS_PERS, ret);
if (ret_pers >= ARRAY_SIZE(vcnl4040_ps_persistence))
return -EINVAL;
it = FIELD_GET(VCNL4040_PS_CONF2_PS_IT, ret);
if (it >= data->chip_spec->num_ps_it_times)
return -EINVAL;
*val = (*data->chip_spec->ps_it_times)[it][0];
*val2 = (*data->chip_spec->ps_it_times)[it][1] *
vcnl4040_ps_persistence[ret_pers];
return IIO_VAL_INT_PLUS_MICRO;
}
static ssize_t vcnl4040_write_ps_period(struct vcnl4000_data *data, int val, int val2)
{
int ret, it, i;
u16 regval;
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1);
if (ret < 0)
return ret;
it = FIELD_GET(VCNL4040_PS_CONF2_PS_IT, ret);
if (it >= data->chip_spec->num_ps_it_times)
return -EINVAL;
if (val > 0)
i = ARRAY_SIZE(vcnl4040_ps_persistence) - 1;
else {
for (i = 0; i < ARRAY_SIZE(vcnl4040_ps_persistence) - 1; i++) {
if (val2 <= vcnl4040_ps_persistence[i] *
(*data->chip_spec->ps_it_times)[it][1])
break;
}
}
mutex_lock(&data->vcnl4000_lock);
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1);
if (ret < 0)
goto out_unlock;
regval = FIELD_PREP(VCNL4040_CONF1_PS_PERS, i);
regval |= (ret & ~VCNL4040_CONF1_PS_PERS);
ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1,
regval);
out_unlock:
mutex_unlock(&data->vcnl4000_lock);
return ret;
}
static ssize_t vcnl4040_read_ps_oversampling_ratio(struct vcnl4000_data *data, int *val)
{
int ret;
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF3);
if (ret < 0)
return ret;
ret = FIELD_GET(VCNL4040_PS_CONF3_MPS, ret);
if (ret >= ARRAY_SIZE(vcnl4040_ps_oversampling_ratio))
return -EINVAL;
*val = vcnl4040_ps_oversampling_ratio[ret];
return ret;
}
static ssize_t vcnl4040_write_ps_oversampling_ratio(struct vcnl4000_data *data, int val)
{
unsigned int i;
int ret;
u16 regval;
for (i = 0; i < ARRAY_SIZE(vcnl4040_ps_oversampling_ratio); i++) {
if (val == vcnl4040_ps_oversampling_ratio[i])
break;
}
if (i >= ARRAY_SIZE(vcnl4040_ps_oversampling_ratio))
return -EINVAL;
mutex_lock(&data->vcnl4000_lock);
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF3);
if (ret < 0)
goto out_unlock;
regval = FIELD_PREP(VCNL4040_PS_CONF3_MPS, i);
regval |= (ret & ~VCNL4040_PS_CONF3_MPS);
ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF3,
regval);
out_unlock:
mutex_unlock(&data->vcnl4000_lock);
return ret;
}
static ssize_t vcnl4040_read_ps_calibbias(struct vcnl4000_data *data, int *val, int *val2)
{
int ret;
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF3);
if (ret < 0)
return ret;
ret = FIELD_GET(VCNL4040_PS_MS_LED_I, ret);
if (ret >= ARRAY_SIZE(vcnl4040_ps_calibbias_ua))
return -EINVAL;
*val = vcnl4040_ps_calibbias_ua[ret][0];
*val2 = vcnl4040_ps_calibbias_ua[ret][1];
return ret;
}
static ssize_t vcnl4040_write_ps_calibbias(struct vcnl4000_data *data, int val)
{
unsigned int i;
int ret;
u16 regval;
for (i = 0; i < ARRAY_SIZE(vcnl4040_ps_calibbias_ua); i++) {
if (val == vcnl4040_ps_calibbias_ua[i][1])
break;
}
if (i >= ARRAY_SIZE(vcnl4040_ps_calibbias_ua))
return -EINVAL;
mutex_lock(&data->vcnl4000_lock);
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF3);
if (ret < 0)
goto out_unlock;
regval = (ret & ~VCNL4040_PS_MS_LED_I);
regval |= FIELD_PREP(VCNL4040_PS_MS_LED_I, i);
ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF3,
regval);
out_unlock:
mutex_unlock(&data->vcnl4000_lock);
return ret;
}
static int vcnl4000_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
int ret;
struct vcnl4000_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = vcnl4000_set_pm_runtime_state(data, true);
if (ret < 0)
return ret;
switch (chan->type) {
case IIO_LIGHT:
ret = data->chip_spec->measure_light(data, val);
if (!ret)
ret = IIO_VAL_INT;
break;
case IIO_PROXIMITY:
ret = data->chip_spec->measure_proximity(data, val);
if (!ret)
ret = IIO_VAL_INT;
break;
default:
ret = -EINVAL;
}
vcnl4000_set_pm_runtime_state(data, false);
return ret;
case IIO_CHAN_INFO_SCALE:
if (chan->type != IIO_LIGHT)
return -EINVAL;
*val = 0;
*val2 = data->al_scale;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_INT_TIME:
switch (chan->type) {
case IIO_LIGHT:
ret = vcnl4040_read_als_it(data, val, val2);
break;
case IIO_PROXIMITY:
ret = vcnl4040_read_ps_it(data, val, val2);
break;
default:
return -EINVAL;
}
if (ret < 0)
return ret;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
switch (chan->type) {
case IIO_PROXIMITY:
ret = vcnl4040_read_ps_oversampling_ratio(data, val);
if (ret < 0)
return ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_CALIBBIAS:
switch (chan->type) {
case IIO_PROXIMITY:
ret = vcnl4040_read_ps_calibbias(data, val, val2);
if (ret < 0)
return ret;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int vcnl4040_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct vcnl4000_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
if (val != 0)
return -EINVAL;
switch (chan->type) {
case IIO_LIGHT:
return vcnl4040_write_als_it(data, val2);
case IIO_PROXIMITY:
return vcnl4040_write_ps_it(data, val2);
default:
return -EINVAL;
}
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
switch (chan->type) {
case IIO_PROXIMITY:
return vcnl4040_write_ps_oversampling_ratio(data, val);
default:
return -EINVAL;
}
case IIO_CHAN_INFO_CALIBBIAS:
switch (chan->type) {
case IIO_PROXIMITY:
return vcnl4040_write_ps_calibbias(data, val2);
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int vcnl4040_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
struct vcnl4000_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
switch (chan->type) {
case IIO_LIGHT:
*vals = (int *)(*data->chip_spec->als_it_times);
*length = 2 * data->chip_spec->num_als_it_times;
break;
case IIO_PROXIMITY:
*vals = (int *)(*data->chip_spec->ps_it_times);
*length = 2 * data->chip_spec->num_ps_it_times;
break;
default:
return -EINVAL;
}
*type = IIO_VAL_INT_PLUS_MICRO;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
switch (chan->type) {
case IIO_PROXIMITY:
*vals = (int *)vcnl4040_ps_oversampling_ratio;
*length = ARRAY_SIZE(vcnl4040_ps_oversampling_ratio);
*type = IIO_VAL_INT;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_CALIBBIAS:
switch (chan->type) {
case IIO_PROXIMITY:
*vals = (int *)vcnl4040_ps_calibbias_ua;
*length = 2 * ARRAY_SIZE(vcnl4040_ps_calibbias_ua);
*type = IIO_VAL_INT_PLUS_MICRO;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int vcnl4010_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
int ret;
struct vcnl4000_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_SCALE:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
/* Protect against event capture. */
if (vcnl4010_is_in_periodic_mode(data)) {
ret = -EBUSY;
} else {
ret = vcnl4000_read_raw(indio_dev, chan, val, val2,
mask);
}
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_SAMP_FREQ:
switch (chan->type) {
case IIO_PROXIMITY:
ret = vcnl4010_read_proxy_samp_freq(data, val, val2);
if (ret < 0)
return ret;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int vcnl4010_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
*vals = (int *)vcnl4010_prox_sampling_frequency;
*type = IIO_VAL_INT_PLUS_MICRO;
*length = 2 * ARRAY_SIZE(vcnl4010_prox_sampling_frequency);
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static int vcnl4010_write_proxy_samp_freq(struct vcnl4000_data *data, int val,
int val2)
{
unsigned int i;
int index = -1;
for (i = 0; i < ARRAY_SIZE(vcnl4010_prox_sampling_frequency); i++) {
if (val == vcnl4010_prox_sampling_frequency[i][0] &&
val2 == vcnl4010_prox_sampling_frequency[i][1]) {
index = i;
break;
}
}
if (index < 0)
return -EINVAL;
return i2c_smbus_write_byte_data(data->client, VCNL4010_PROX_RATE,
index);
}
static int vcnl4010_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
int ret;
struct vcnl4000_data *data = iio_priv(indio_dev);
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
/* Protect against event capture. */
if (vcnl4010_is_in_periodic_mode(data)) {
ret = -EBUSY;
goto end;
}
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
switch (chan->type) {
case IIO_PROXIMITY:
ret = vcnl4010_write_proxy_samp_freq(data, val, val2);
goto end;
default:
ret = -EINVAL;
goto end;
}
default:
ret = -EINVAL;
goto end;
}
end:
iio_device_release_direct_mode(indio_dev);
return ret;
}
static int vcnl4010_read_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
int ret;
struct vcnl4000_data *data = iio_priv(indio_dev);
switch (info) {
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
ret = vcnl4000_read_data(data, VCNL4010_HIGH_THR_HI,
val);
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_EV_DIR_FALLING:
ret = vcnl4000_read_data(data, VCNL4010_LOW_THR_HI,
val);
if (ret < 0)
return ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int vcnl4010_write_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
int ret;
struct vcnl4000_data *data = iio_priv(indio_dev);
switch (info) {
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
ret = vcnl4000_write_data(data, VCNL4010_HIGH_THR_HI,
val);
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_EV_DIR_FALLING:
ret = vcnl4000_write_data(data, VCNL4010_LOW_THR_HI,
val);
if (ret < 0)
return ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int vcnl4040_read_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
int ret;
struct vcnl4000_data *data = iio_priv(indio_dev);
switch (chan->type) {
case IIO_LIGHT:
switch (info) {
case IIO_EV_INFO_PERIOD:
return vcnl4040_read_als_period(data, val, val2);
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
ret = i2c_smbus_read_word_data(data->client,
VCNL4040_ALS_THDH_LM);
break;
case IIO_EV_DIR_FALLING:
ret = i2c_smbus_read_word_data(data->client,
VCNL4040_ALS_THDL_LM);
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
break;
case IIO_PROXIMITY:
switch (info) {
case IIO_EV_INFO_PERIOD:
return vcnl4040_read_ps_period(data, val, val2);
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
ret = i2c_smbus_read_word_data(data->client,
VCNL4040_PS_THDH_LM);
break;
case IIO_EV_DIR_FALLING:
ret = i2c_smbus_read_word_data(data->client,
VCNL4040_PS_THDL_LM);
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
}
static int vcnl4040_write_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
int ret;
struct vcnl4000_data *data = iio_priv(indio_dev);
switch (chan->type) {
case IIO_LIGHT:
switch (info) {
case IIO_EV_INFO_PERIOD:
return vcnl4040_write_als_period(data, val, val2);
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
ret = i2c_smbus_write_word_data(data->client,
VCNL4040_ALS_THDH_LM,
val);
break;
case IIO_EV_DIR_FALLING:
ret = i2c_smbus_write_word_data(data->client,
VCNL4040_ALS_THDL_LM,
val);
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
break;
case IIO_PROXIMITY:
switch (info) {
case IIO_EV_INFO_PERIOD:
return vcnl4040_write_ps_period(data, val, val2);
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
ret = i2c_smbus_write_word_data(data->client,
VCNL4040_PS_THDH_LM,
val);
break;
case IIO_EV_DIR_FALLING:
ret = i2c_smbus_write_word_data(data->client,
VCNL4040_PS_THDL_LM,
val);
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
if (ret < 0)
return ret;
return IIO_VAL_INT;
}
static bool vcnl4010_is_thr_enabled(struct vcnl4000_data *data)
{
int ret;
ret = i2c_smbus_read_byte_data(data->client, VCNL4010_INT_CTRL);
if (ret < 0)
return false;
return !!(ret & VCNL4010_INT_THR_EN);
}
static int vcnl4010_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct vcnl4000_data *data = iio_priv(indio_dev);
switch (chan->type) {
case IIO_PROXIMITY:
return vcnl4010_is_thr_enabled(data);
default:
return -EINVAL;
}
}
static int vcnl4010_config_threshold(struct iio_dev *indio_dev, bool state)
{
struct vcnl4000_data *data = iio_priv(indio_dev);
int ret;
int icr;
int command;
if (state) {
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
/* Enable periodic measurement of proximity data. */
command = VCNL4000_SELF_TIMED_EN | VCNL4000_PROX_EN;
/*
* Enable interrupts on threshold, for proximity data by
* default.
*/
icr = VCNL4010_INT_THR_EN;
} else {
if (!vcnl4010_is_thr_enabled(data))
return 0;
command = 0;
icr = 0;
}
ret = i2c_smbus_write_byte_data(data->client, VCNL4000_COMMAND,
command);
if (ret < 0)
goto end;
ret = i2c_smbus_write_byte_data(data->client, VCNL4010_INT_CTRL, icr);
end:
if (state)
iio_device_release_direct_mode(indio_dev);
return ret;
}
static int vcnl4010_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
switch (chan->type) {
case IIO_PROXIMITY:
return vcnl4010_config_threshold(indio_dev, state);
default:
return -EINVAL;
}
}
static int vcnl4040_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
int ret;
struct vcnl4000_data *data = iio_priv(indio_dev);
switch (chan->type) {
case IIO_LIGHT:
ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF);
if (ret < 0)
return ret;
data->als_int = FIELD_GET(VCNL4040_ALS_CONF_INT_EN, ret);
return data->als_int;
case IIO_PROXIMITY:
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1);
if (ret < 0)
return ret;
data->ps_int = FIELD_GET(VCNL4040_PS_CONF2_PS_INT, ret);
return (dir == IIO_EV_DIR_RISING) ?
FIELD_GET(VCNL4040_PS_IF_AWAY, ret) :
FIELD_GET(VCNL4040_PS_IF_CLOSE, ret);
default:
return -EINVAL;
}
}
static int vcnl4040_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir, int state)
{
int ret = -EINVAL;
u16 val, mask;
struct vcnl4000_data *data = iio_priv(indio_dev);
mutex_lock(&data->vcnl4000_lock);
switch (chan->type) {
case IIO_LIGHT:
ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF);
if (ret < 0)
goto out;
mask = VCNL4040_ALS_CONF_INT_EN;
if (state)
val = (ret | mask);
else
val = (ret & ~mask);
data->als_int = FIELD_GET(VCNL4040_ALS_CONF_INT_EN, val);
ret = i2c_smbus_write_word_data(data->client, VCNL4200_AL_CONF,
val);
break;
case IIO_PROXIMITY:
ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1);
if (ret < 0)
goto out;
if (dir == IIO_EV_DIR_RISING)
mask = VCNL4040_PS_IF_AWAY;
else
mask = VCNL4040_PS_IF_CLOSE;
val = state ? (ret | mask) : (ret & ~mask);
data->ps_int = FIELD_GET(VCNL4040_PS_CONF2_PS_INT, val);
ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1,
val);
break;
default:
break;
}
out:
mutex_unlock(&data->vcnl4000_lock);
data->chip_spec->set_power_state(data, data->ps_int || data->als_int);
return ret;
}
static irqreturn_t vcnl4040_irq_thread(int irq, void *p)
{
struct iio_dev *indio_dev = p;
struct vcnl4000_data *data = iio_priv(indio_dev);
int ret;
ret = i2c_smbus_read_word_data(data->client, data->chip_spec->int_reg);
if (ret < 0)
return IRQ_HANDLED;
if (ret & VCNL4040_PS_IF_CLOSE) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
}
if (ret & VCNL4040_PS_IF_AWAY) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
iio_get_time_ns(indio_dev));
}
if (ret & VCNL4040_ALS_FALLING) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
iio_get_time_ns(indio_dev));
}
if (ret & VCNL4040_ALS_RISING) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
}
return IRQ_HANDLED;
}
static ssize_t vcnl4000_read_near_level(struct iio_dev *indio_dev,
uintptr_t priv,
const struct iio_chan_spec *chan,
char *buf)
{
struct vcnl4000_data *data = iio_priv(indio_dev);
return sprintf(buf, "%u\n", data->near_level);
}
static irqreturn_t vcnl4010_irq_thread(int irq, void *p)
{
struct iio_dev *indio_dev = p;
struct vcnl4000_data *data = iio_priv(indio_dev);
unsigned long isr;
int ret;
ret = i2c_smbus_read_byte_data(data->client, VCNL4010_ISR);
if (ret < 0)
goto end;
isr = ret;
if (isr & VCNL4010_INT_THR) {
if (test_bit(VCNL4010_INT_THR_LOW, &isr)) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(
IIO_PROXIMITY,
1,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
iio_get_time_ns(indio_dev));
}
if (test_bit(VCNL4010_INT_THR_HIGH, &isr)) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(
IIO_PROXIMITY,
1,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
}
i2c_smbus_write_byte_data(data->client, VCNL4010_ISR,
isr & VCNL4010_INT_THR);
}
if (isr & VCNL4010_INT_DRDY && iio_buffer_enabled(indio_dev))
iio_trigger_poll_nested(indio_dev->trig);
end:
return IRQ_HANDLED;
}
static irqreturn_t vcnl4010_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct vcnl4000_data *data = iio_priv(indio_dev);
const unsigned long *active_scan_mask = indio_dev->active_scan_mask;
u16 buffer[8] __aligned(8) = {0}; /* 1x16-bit + naturally aligned ts */
bool data_read = false;
unsigned long isr;
int val = 0;
int ret;
ret = i2c_smbus_read_byte_data(data->client, VCNL4010_ISR);
if (ret < 0)
goto end;
isr = ret;
if (test_bit(0, active_scan_mask)) {
if (test_bit(VCNL4010_INT_PROXIMITY, &isr)) {
ret = vcnl4000_read_data(data,
VCNL4000_PS_RESULT_HI,
&val);
if (ret < 0)
goto end;
buffer[0] = val;
data_read = true;
}
}
ret = i2c_smbus_write_byte_data(data->client, VCNL4010_ISR,
isr & VCNL4010_INT_DRDY);
if (ret < 0)
goto end;
if (!data_read)
goto end;
iio_push_to_buffers_with_timestamp(indio_dev, buffer,
iio_get_time_ns(indio_dev));
end:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int vcnl4010_buffer_postenable(struct iio_dev *indio_dev)
{
struct vcnl4000_data *data = iio_priv(indio_dev);
int ret;
int cmd;
/* Do not enable the buffer if we are already capturing events. */
if (vcnl4010_is_in_periodic_mode(data))
return -EBUSY;
ret = i2c_smbus_write_byte_data(data->client, VCNL4010_INT_CTRL,
VCNL4010_INT_PROX_EN);
if (ret < 0)
return ret;
cmd = VCNL4000_SELF_TIMED_EN | VCNL4000_PROX_EN;
return i2c_smbus_write_byte_data(data->client, VCNL4000_COMMAND, cmd);
}
static int vcnl4010_buffer_predisable(struct iio_dev *indio_dev)
{
struct vcnl4000_data *data = iio_priv(indio_dev);
int ret;
ret = i2c_smbus_write_byte_data(data->client, VCNL4010_INT_CTRL, 0);
if (ret < 0)
return ret;
return i2c_smbus_write_byte_data(data->client, VCNL4000_COMMAND, 0);
}
static const struct iio_buffer_setup_ops vcnl4010_buffer_ops = {
.postenable = &vcnl4010_buffer_postenable,
.predisable = &vcnl4010_buffer_predisable,
};
static const struct iio_chan_spec_ext_info vcnl4000_ext_info[] = {
{
.name = "nearlevel",
.shared = IIO_SEPARATE,
.read = vcnl4000_read_near_level,
},
{ /* sentinel */ }
};
static const struct iio_event_spec vcnl4000_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
}
};
static const struct iio_event_spec vcnl4040_als_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_PERIOD),
},
};
static const struct iio_event_spec vcnl4040_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_PERIOD),
},
};
static const struct iio_chan_spec vcnl4000_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
}, {
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.ext_info = vcnl4000_ext_info,
}
};
static const struct iio_chan_spec vcnl4010_channels[] = {
{
.type = IIO_LIGHT,
.scan_index = -1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
}, {
.type = IIO_PROXIMITY,
.scan_index = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.event_spec = vcnl4000_event_spec,
.num_event_specs = ARRAY_SIZE(vcnl4000_event_spec),
.ext_info = vcnl4000_ext_info,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_CPU,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static const struct iio_chan_spec vcnl4040_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_INT_TIME),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_INT_TIME),
.event_spec = vcnl4040_als_event_spec,
.num_event_specs = ARRAY_SIZE(vcnl4040_als_event_spec),
}, {
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.ext_info = vcnl4000_ext_info,
.event_spec = vcnl4040_event_spec,
.num_event_specs = ARRAY_SIZE(vcnl4040_event_spec),
}
};
static const struct iio_info vcnl4000_info = {
.read_raw = vcnl4000_read_raw,
};
static const struct iio_info vcnl4010_info = {
.read_raw = vcnl4010_read_raw,
.read_avail = vcnl4010_read_avail,
.write_raw = vcnl4010_write_raw,
.read_event_value = vcnl4010_read_event,
.write_event_value = vcnl4010_write_event,
.read_event_config = vcnl4010_read_event_config,
.write_event_config = vcnl4010_write_event_config,
};
static const struct iio_info vcnl4040_info = {
.read_raw = vcnl4000_read_raw,
.write_raw = vcnl4040_write_raw,
.read_event_value = vcnl4040_read_event,
.write_event_value = vcnl4040_write_event,
.read_event_config = vcnl4040_read_event_config,
.write_event_config = vcnl4040_write_event_config,
.read_avail = vcnl4040_read_avail,
};
static const struct vcnl4000_chip_spec vcnl4000_chip_spec_cfg[] = {
[VCNL4000] = {
.prod = "VCNL4000",
.init = vcnl4000_init,
.measure_light = vcnl4000_measure_light,
.measure_proximity = vcnl4000_measure_proximity,
.set_power_state = vcnl4000_set_power_state,
.channels = vcnl4000_channels,
.num_channels = ARRAY_SIZE(vcnl4000_channels),
.info = &vcnl4000_info,
},
[VCNL4010] = {
.prod = "VCNL4010/4020",
.init = vcnl4000_init,
.measure_light = vcnl4000_measure_light,
.measure_proximity = vcnl4000_measure_proximity,
.set_power_state = vcnl4000_set_power_state,
.channels = vcnl4010_channels,
.num_channels = ARRAY_SIZE(vcnl4010_channels),
.info = &vcnl4010_info,
.irq_thread = vcnl4010_irq_thread,
.trig_buffer_func = vcnl4010_trigger_handler,
.buffer_setup_ops = &vcnl4010_buffer_ops,
},
[VCNL4040] = {
.prod = "VCNL4040",
.init = vcnl4200_init,
.measure_light = vcnl4200_measure_light,
.measure_proximity = vcnl4200_measure_proximity,
.set_power_state = vcnl4200_set_power_state,
.channels = vcnl4040_channels,
.num_channels = ARRAY_SIZE(vcnl4040_channels),
.info = &vcnl4040_info,
.irq_thread = vcnl4040_irq_thread,
.int_reg = VCNL4040_INT_FLAGS,
.ps_it_times = &vcnl4040_ps_it_times,
.num_ps_it_times = ARRAY_SIZE(vcnl4040_ps_it_times),
.als_it_times = &vcnl4040_als_it_times,
.num_als_it_times = ARRAY_SIZE(vcnl4040_als_it_times),
.ulux_step = 100000,
},
[VCNL4200] = {
.prod = "VCNL4200",
.init = vcnl4200_init,
.measure_light = vcnl4200_measure_light,
.measure_proximity = vcnl4200_measure_proximity,
.set_power_state = vcnl4200_set_power_state,
.channels = vcnl4040_channels,
.num_channels = ARRAY_SIZE(vcnl4000_channels),
.info = &vcnl4040_info,
.irq_thread = vcnl4040_irq_thread,
.int_reg = VCNL4200_INT_FLAGS,
.ps_it_times = &vcnl4200_ps_it_times,
.num_ps_it_times = ARRAY_SIZE(vcnl4200_ps_it_times),
.als_it_times = &vcnl4200_als_it_times,
.num_als_it_times = ARRAY_SIZE(vcnl4200_als_it_times),
.ulux_step = 24000,
},
};
static const struct iio_trigger_ops vcnl4010_trigger_ops = {
.validate_device = iio_trigger_validate_own_device,
};
static int vcnl4010_probe_trigger(struct iio_dev *indio_dev)
{
struct vcnl4000_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
struct iio_trigger *trigger;
trigger = devm_iio_trigger_alloc(&client->dev, "%s-dev%d",
indio_dev->name,
iio_device_id(indio_dev));
if (!trigger)
return -ENOMEM;
trigger->ops = &vcnl4010_trigger_ops;
iio_trigger_set_drvdata(trigger, indio_dev);
return devm_iio_trigger_register(&client->dev, trigger);
}
static int vcnl4000_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct vcnl4000_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->id = id->driver_data;
data->chip_spec = &vcnl4000_chip_spec_cfg[data->id];
mutex_init(&data->vcnl4000_lock);
ret = data->chip_spec->init(data);
if (ret < 0)
return ret;
dev_dbg(&client->dev, "%s Ambient light/proximity sensor, Rev: %02x\n",
data->chip_spec->prod, data->rev);
if (device_property_read_u32(&client->dev, "proximity-near-level",
&data->near_level))
data->near_level = 0;
indio_dev->info = data->chip_spec->info;
indio_dev->channels = data->chip_spec->channels;
indio_dev->num_channels = data->chip_spec->num_channels;
indio_dev->name = VCNL4000_DRV_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
if (data->chip_spec->trig_buffer_func &&
data->chip_spec->buffer_setup_ops) {
ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev,
NULL,
data->chip_spec->trig_buffer_func,
data->chip_spec->buffer_setup_ops);
if (ret < 0) {
dev_err(&client->dev,
"unable to setup iio triggered buffer\n");
return ret;
}
}
if (client->irq && data->chip_spec->irq_thread) {
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, data->chip_spec->irq_thread,
IRQF_TRIGGER_FALLING |
IRQF_ONESHOT,
"vcnl4000_irq",
indio_dev);
if (ret < 0) {
dev_err(&client->dev, "irq request failed\n");
return ret;
}
ret = vcnl4010_probe_trigger(indio_dev);
if (ret < 0)
return ret;
}
ret = pm_runtime_set_active(&client->dev);
if (ret < 0)
goto fail_poweroff;
ret = iio_device_register(indio_dev);
if (ret < 0)
goto fail_poweroff;
pm_runtime_enable(&client->dev);
pm_runtime_set_autosuspend_delay(&client->dev, VCNL4000_SLEEP_DELAY_MS);
pm_runtime_use_autosuspend(&client->dev);
return 0;
fail_poweroff:
data->chip_spec->set_power_state(data, false);
return ret;
}
static const struct of_device_id vcnl_4000_of_match[] = {
{
.compatible = "vishay,vcnl4000",
.data = (void *)VCNL4000,
},
{
.compatible = "vishay,vcnl4010",
.data = (void *)VCNL4010,
},
{
.compatible = "vishay,vcnl4020",
.data = (void *)VCNL4010,
},
{
.compatible = "vishay,vcnl4040",
.data = (void *)VCNL4040,
},
{
.compatible = "vishay,vcnl4200",
.data = (void *)VCNL4200,
},
{},
};
MODULE_DEVICE_TABLE(of, vcnl_4000_of_match);
static void vcnl4000_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct vcnl4000_data *data = iio_priv(indio_dev);
int ret;
pm_runtime_dont_use_autosuspend(&client->dev);
pm_runtime_disable(&client->dev);
iio_device_unregister(indio_dev);
pm_runtime_set_suspended(&client->dev);
ret = data->chip_spec->set_power_state(data, false);
if (ret)
dev_warn(&client->dev, "Failed to power down (%pe)\n",
ERR_PTR(ret));
}
static int vcnl4000_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct vcnl4000_data *data = iio_priv(indio_dev);
return data->chip_spec->set_power_state(data, false);
}
static int vcnl4000_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct vcnl4000_data *data = iio_priv(indio_dev);
return data->chip_spec->set_power_state(data, true);
}
static DEFINE_RUNTIME_DEV_PM_OPS(vcnl4000_pm_ops, vcnl4000_runtime_suspend,
vcnl4000_runtime_resume, NULL);
static struct i2c_driver vcnl4000_driver = {
.driver = {
.name = VCNL4000_DRV_NAME,
.pm = pm_ptr(&vcnl4000_pm_ops),
.of_match_table = vcnl_4000_of_match,
},
.probe = vcnl4000_probe,
.id_table = vcnl4000_id,
.remove = vcnl4000_remove,
};
module_i2c_driver(vcnl4000_driver);
MODULE_AUTHOR("Peter Meerwald <[email protected]>");
MODULE_AUTHOR("Mathieu Othacehe <[email protected]>");
MODULE_DESCRIPTION("Vishay VCNL4000 proximity/ambient light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/vcnl4000.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* si1133.c - Support for Silabs SI1133 combined ambient
* light and UV index sensors
*
* Copyright 2018 Maxime Roussin-Belanger <[email protected]>
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/util_macros.h>
#include <asm/unaligned.h>
#define SI1133_REG_PART_ID 0x00
#define SI1133_REG_REV_ID 0x01
#define SI1133_REG_MFR_ID 0x02
#define SI1133_REG_INFO0 0x03
#define SI1133_REG_INFO1 0x04
#define SI1133_PART_ID 0x33
#define SI1133_REG_HOSTIN0 0x0A
#define SI1133_REG_COMMAND 0x0B
#define SI1133_REG_IRQ_ENABLE 0x0F
#define SI1133_REG_RESPONSE1 0x10
#define SI1133_REG_RESPONSE0 0x11
#define SI1133_REG_IRQ_STATUS 0x12
#define SI1133_REG_MEAS_RATE 0x1A
#define SI1133_IRQ_CHANNEL_ENABLE 0xF
#define SI1133_CMD_RESET_CTR 0x00
#define SI1133_CMD_RESET_SW 0x01
#define SI1133_CMD_FORCE 0x11
#define SI1133_CMD_START_AUTONOMOUS 0x13
#define SI1133_CMD_PARAM_SET 0x80
#define SI1133_CMD_PARAM_QUERY 0x40
#define SI1133_CMD_PARAM_MASK 0x3F
#define SI1133_CMD_ERR_MASK BIT(4)
#define SI1133_CMD_SEQ_MASK 0xF
#define SI1133_MAX_CMD_CTR 0xF
#define SI1133_PARAM_REG_CHAN_LIST 0x01
#define SI1133_PARAM_REG_ADCCONFIG(x) ((x) * 4) + 2
#define SI1133_PARAM_REG_ADCSENS(x) ((x) * 4) + 3
#define SI1133_PARAM_REG_ADCPOST(x) ((x) * 4) + 4
#define SI1133_ADCMUX_MASK 0x1F
#define SI1133_ADCCONFIG_DECIM_RATE(x) (x) << 5
#define SI1133_ADCSENS_SCALE_MASK 0x70
#define SI1133_ADCSENS_SCALE_SHIFT 4
#define SI1133_ADCSENS_HSIG_MASK BIT(7)
#define SI1133_ADCSENS_HSIG_SHIFT 7
#define SI1133_ADCSENS_HW_GAIN_MASK 0xF
#define SI1133_ADCSENS_NB_MEAS(x) fls(x) << SI1133_ADCSENS_SCALE_SHIFT
#define SI1133_ADCPOST_24BIT_EN BIT(6)
#define SI1133_ADCPOST_POSTSHIFT_BITQTY(x) (x & GENMASK(2, 0)) << 3
#define SI1133_PARAM_ADCMUX_SMALL_IR 0x0
#define SI1133_PARAM_ADCMUX_MED_IR 0x1
#define SI1133_PARAM_ADCMUX_LARGE_IR 0x2
#define SI1133_PARAM_ADCMUX_WHITE 0xB
#define SI1133_PARAM_ADCMUX_LARGE_WHITE 0xD
#define SI1133_PARAM_ADCMUX_UV 0x18
#define SI1133_PARAM_ADCMUX_UV_DEEP 0x19
#define SI1133_ERR_INVALID_CMD 0x0
#define SI1133_ERR_INVALID_LOCATION_CMD 0x1
#define SI1133_ERR_SATURATION_ADC_OR_OVERFLOW_ACCUMULATION 0x2
#define SI1133_ERR_OUTPUT_BUFFER_OVERFLOW 0x3
#define SI1133_COMPLETION_TIMEOUT_MS 500
#define SI1133_CMD_MINSLEEP_US_LOW 5000
#define SI1133_CMD_MINSLEEP_US_HIGH 7500
#define SI1133_CMD_TIMEOUT_MS 25
#define SI1133_CMD_LUX_TIMEOUT_MS 5000
#define SI1133_CMD_TIMEOUT_US SI1133_CMD_TIMEOUT_MS * 1000
#define SI1133_REG_HOSTOUT(x) (x) + 0x13
#define SI1133_MEASUREMENT_FREQUENCY 1250
#define SI1133_X_ORDER_MASK 0x0070
#define SI1133_Y_ORDER_MASK 0x0007
#define si1133_get_x_order(m) ((m) & SI1133_X_ORDER_MASK) >> 4
#define si1133_get_y_order(m) ((m) & SI1133_Y_ORDER_MASK)
#define SI1133_LUX_ADC_MASK 0xE
#define SI1133_ADC_THRESHOLD 16000
#define SI1133_INPUT_FRACTION_HIGH 7
#define SI1133_INPUT_FRACTION_LOW 15
#define SI1133_LUX_OUTPUT_FRACTION 12
#define SI1133_LUX_BUFFER_SIZE 9
#define SI1133_MEASURE_BUFFER_SIZE 3
static const int si1133_scale_available[] = {
1, 2, 4, 8, 16, 32, 64, 128};
static IIO_CONST_ATTR(scale_available, "1 2 4 8 16 32 64 128");
static IIO_CONST_ATTR_INT_TIME_AVAIL("0.0244 0.0488 0.0975 0.195 0.390 0.780 "
"1.560 3.120 6.24 12.48 25.0 50.0");
/* A.K.A. HW_GAIN in datasheet */
enum si1133_int_time {
_24_4_us = 0,
_48_8_us = 1,
_97_5_us = 2,
_195_0_us = 3,
_390_0_us = 4,
_780_0_us = 5,
_1_560_0_us = 6,
_3_120_0_us = 7,
_6_240_0_us = 8,
_12_480_0_us = 9,
_25_ms = 10,
_50_ms = 11,
};
/* Integration time in milliseconds, nanoseconds */
static const int si1133_int_time_table[][2] = {
[_24_4_us] = {0, 24400},
[_48_8_us] = {0, 48800},
[_97_5_us] = {0, 97500},
[_195_0_us] = {0, 195000},
[_390_0_us] = {0, 390000},
[_780_0_us] = {0, 780000},
[_1_560_0_us] = {1, 560000},
[_3_120_0_us] = {3, 120000},
[_6_240_0_us] = {6, 240000},
[_12_480_0_us] = {12, 480000},
[_25_ms] = {25, 000000},
[_50_ms] = {50, 000000},
};
static const struct regmap_range si1133_reg_ranges[] = {
regmap_reg_range(0x00, 0x02),
regmap_reg_range(0x0A, 0x0B),
regmap_reg_range(0x0F, 0x0F),
regmap_reg_range(0x10, 0x12),
regmap_reg_range(0x13, 0x2C),
};
static const struct regmap_range si1133_reg_ro_ranges[] = {
regmap_reg_range(0x00, 0x02),
regmap_reg_range(0x10, 0x2C),
};
static const struct regmap_range si1133_precious_ranges[] = {
regmap_reg_range(0x12, 0x12),
};
static const struct regmap_access_table si1133_write_ranges_table = {
.yes_ranges = si1133_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(si1133_reg_ranges),
.no_ranges = si1133_reg_ro_ranges,
.n_no_ranges = ARRAY_SIZE(si1133_reg_ro_ranges),
};
static const struct regmap_access_table si1133_read_ranges_table = {
.yes_ranges = si1133_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(si1133_reg_ranges),
};
static const struct regmap_access_table si1133_precious_table = {
.yes_ranges = si1133_precious_ranges,
.n_yes_ranges = ARRAY_SIZE(si1133_precious_ranges),
};
static const struct regmap_config si1133_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x2C,
.wr_table = &si1133_write_ranges_table,
.rd_table = &si1133_read_ranges_table,
.precious_table = &si1133_precious_table,
};
struct si1133_data {
struct regmap *regmap;
struct i2c_client *client;
/* Lock protecting one command at a time can be processed */
struct mutex mutex;
int rsp_seq;
u8 scan_mask;
u8 adc_sens[6];
u8 adc_config[6];
struct completion completion;
};
struct si1133_coeff {
s16 info;
u16 mag;
};
struct si1133_lux_coeff {
struct si1133_coeff coeff_high[4];
struct si1133_coeff coeff_low[9];
};
static const struct si1133_lux_coeff lux_coeff = {
{
{ 0, 209},
{ 1665, 93},
{ 2064, 65},
{-2671, 234}
},
{
{ 0, 0},
{ 1921, 29053},
{-1022, 36363},
{ 2320, 20789},
{ -367, 57909},
{-1774, 38240},
{ -608, 46775},
{-1503, 51831},
{-1886, 58928}
}
};
static int si1133_calculate_polynomial_inner(s32 input, u8 fraction, u16 mag,
s8 shift)
{
return ((input << fraction) / mag) << shift;
}
static int si1133_calculate_output(s32 x, s32 y, u8 x_order, u8 y_order,
u8 input_fraction, s8 sign,
const struct si1133_coeff *coeffs)
{
s8 shift;
int x1 = 1;
int x2 = 1;
int y1 = 1;
int y2 = 1;
shift = ((u16)coeffs->info & 0xFF00) >> 8;
shift ^= 0xFF;
shift += 1;
shift = -shift;
if (x_order > 0) {
x1 = si1133_calculate_polynomial_inner(x, input_fraction,
coeffs->mag, shift);
if (x_order > 1)
x2 = x1;
}
if (y_order > 0) {
y1 = si1133_calculate_polynomial_inner(y, input_fraction,
coeffs->mag, shift);
if (y_order > 1)
y2 = y1;
}
return sign * x1 * x2 * y1 * y2;
}
/*
* The algorithm is from:
* https://siliconlabs.github.io/Gecko_SDK_Doc/efm32zg/html/si1133_8c_source.html#l00716
*/
static int si1133_calc_polynomial(s32 x, s32 y, u8 input_fraction, u8 num_coeff,
const struct si1133_coeff *coeffs)
{
u8 x_order, y_order;
u8 counter;
s8 sign;
int output = 0;
for (counter = 0; counter < num_coeff; counter++) {
if (coeffs->info < 0)
sign = -1;
else
sign = 1;
x_order = si1133_get_x_order(coeffs->info);
y_order = si1133_get_y_order(coeffs->info);
if ((x_order == 0) && (y_order == 0))
output +=
sign * coeffs->mag << SI1133_LUX_OUTPUT_FRACTION;
else
output += si1133_calculate_output(x, y, x_order,
y_order,
input_fraction, sign,
coeffs);
coeffs++;
}
return abs(output);
}
static int si1133_cmd_reset_sw(struct si1133_data *data)
{
struct device *dev = &data->client->dev;
unsigned int resp;
unsigned long timeout;
int err;
err = regmap_write(data->regmap, SI1133_REG_COMMAND,
SI1133_CMD_RESET_SW);
if (err)
return err;
timeout = jiffies + msecs_to_jiffies(SI1133_CMD_TIMEOUT_MS);
while (true) {
err = regmap_read(data->regmap, SI1133_REG_RESPONSE0, &resp);
if (err == -ENXIO) {
usleep_range(SI1133_CMD_MINSLEEP_US_LOW,
SI1133_CMD_MINSLEEP_US_HIGH);
continue;
}
if ((resp & SI1133_MAX_CMD_CTR) == SI1133_MAX_CMD_CTR)
break;
if (time_after(jiffies, timeout)) {
dev_warn(dev, "Timeout on reset ctr resp: %d\n", resp);
return -ETIMEDOUT;
}
}
if (!err)
data->rsp_seq = SI1133_MAX_CMD_CTR;
return err;
}
static int si1133_parse_response_err(struct device *dev, u32 resp, u8 cmd)
{
resp &= 0xF;
switch (resp) {
case SI1133_ERR_OUTPUT_BUFFER_OVERFLOW:
dev_warn(dev, "Output buffer overflow: 0x%02x\n", cmd);
return -EOVERFLOW;
case SI1133_ERR_SATURATION_ADC_OR_OVERFLOW_ACCUMULATION:
dev_warn(dev, "Saturation of the ADC or overflow of accumulation: 0x%02x\n",
cmd);
return -EOVERFLOW;
case SI1133_ERR_INVALID_LOCATION_CMD:
dev_warn(dev,
"Parameter access to an invalid location: 0x%02x\n",
cmd);
return -EINVAL;
case SI1133_ERR_INVALID_CMD:
dev_warn(dev, "Invalid command 0x%02x\n", cmd);
return -EINVAL;
default:
dev_warn(dev, "Unknown error 0x%02x\n", cmd);
return -EINVAL;
}
}
static int si1133_cmd_reset_counter(struct si1133_data *data)
{
int err = regmap_write(data->regmap, SI1133_REG_COMMAND,
SI1133_CMD_RESET_CTR);
if (err)
return err;
data->rsp_seq = 0;
return 0;
}
static int si1133_command(struct si1133_data *data, u8 cmd)
{
struct device *dev = &data->client->dev;
u32 resp;
int err;
int expected_seq;
mutex_lock(&data->mutex);
expected_seq = (data->rsp_seq + 1) & SI1133_MAX_CMD_CTR;
if (cmd == SI1133_CMD_FORCE)
reinit_completion(&data->completion);
err = regmap_write(data->regmap, SI1133_REG_COMMAND, cmd);
if (err) {
dev_warn(dev, "Failed to write command 0x%02x, ret=%d\n", cmd,
err);
goto out;
}
if (cmd == SI1133_CMD_FORCE) {
/* wait for irq */
if (!wait_for_completion_timeout(&data->completion,
msecs_to_jiffies(SI1133_COMPLETION_TIMEOUT_MS))) {
err = -ETIMEDOUT;
goto out;
}
err = regmap_read(data->regmap, SI1133_REG_RESPONSE0, &resp);
if (err)
goto out;
} else {
err = regmap_read_poll_timeout(data->regmap,
SI1133_REG_RESPONSE0, resp,
(resp & SI1133_CMD_SEQ_MASK) ==
expected_seq ||
(resp & SI1133_CMD_ERR_MASK),
SI1133_CMD_MINSLEEP_US_LOW,
SI1133_CMD_TIMEOUT_MS * 1000);
if (err) {
dev_warn(dev,
"Failed to read command 0x%02x, ret=%d\n",
cmd, err);
goto out;
}
}
if (resp & SI1133_CMD_ERR_MASK) {
err = si1133_parse_response_err(dev, resp, cmd);
si1133_cmd_reset_counter(data);
} else {
data->rsp_seq = expected_seq;
}
out:
mutex_unlock(&data->mutex);
return err;
}
static int si1133_param_set(struct si1133_data *data, u8 param, u32 value)
{
int err = regmap_write(data->regmap, SI1133_REG_HOSTIN0, value);
if (err)
return err;
return si1133_command(data, SI1133_CMD_PARAM_SET |
(param & SI1133_CMD_PARAM_MASK));
}
static int si1133_param_query(struct si1133_data *data, u8 param, u32 *result)
{
int err = si1133_command(data, SI1133_CMD_PARAM_QUERY |
(param & SI1133_CMD_PARAM_MASK));
if (err)
return err;
return regmap_read(data->regmap, SI1133_REG_RESPONSE1, result);
}
#define SI1133_CHANNEL(_ch, _type) \
.type = _type, \
.channel = _ch, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
static const struct iio_chan_spec si1133_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.channel = 0,
},
{
SI1133_CHANNEL(SI1133_PARAM_ADCMUX_WHITE, IIO_INTENSITY)
.channel2 = IIO_MOD_LIGHT_BOTH,
},
{
SI1133_CHANNEL(SI1133_PARAM_ADCMUX_LARGE_WHITE, IIO_INTENSITY)
.channel2 = IIO_MOD_LIGHT_BOTH,
.extend_name = "large",
},
{
SI1133_CHANNEL(SI1133_PARAM_ADCMUX_SMALL_IR, IIO_INTENSITY)
.extend_name = "small",
.modified = 1,
.channel2 = IIO_MOD_LIGHT_IR,
},
{
SI1133_CHANNEL(SI1133_PARAM_ADCMUX_MED_IR, IIO_INTENSITY)
.modified = 1,
.channel2 = IIO_MOD_LIGHT_IR,
},
{
SI1133_CHANNEL(SI1133_PARAM_ADCMUX_LARGE_IR, IIO_INTENSITY)
.extend_name = "large",
.modified = 1,
.channel2 = IIO_MOD_LIGHT_IR,
},
{
SI1133_CHANNEL(SI1133_PARAM_ADCMUX_UV, IIO_UVINDEX)
},
{
SI1133_CHANNEL(SI1133_PARAM_ADCMUX_UV_DEEP, IIO_UVINDEX)
.modified = 1,
.channel2 = IIO_MOD_LIGHT_DUV,
}
};
static int si1133_get_int_time_index(int milliseconds, int nanoseconds)
{
int i;
for (i = 0; i < ARRAY_SIZE(si1133_int_time_table); i++) {
if (milliseconds == si1133_int_time_table[i][0] &&
nanoseconds == si1133_int_time_table[i][1])
return i;
}
return -EINVAL;
}
static int si1133_set_integration_time(struct si1133_data *data, u8 adc,
int milliseconds, int nanoseconds)
{
int index;
index = si1133_get_int_time_index(milliseconds, nanoseconds);
if (index < 0)
return index;
data->adc_sens[adc] &= 0xF0;
data->adc_sens[adc] |= index;
return si1133_param_set(data, SI1133_PARAM_REG_ADCSENS(0),
data->adc_sens[adc]);
}
static int si1133_set_chlist(struct si1133_data *data, u8 scan_mask)
{
/* channel list already set, no need to reprogram */
if (data->scan_mask == scan_mask)
return 0;
data->scan_mask = scan_mask;
return si1133_param_set(data, SI1133_PARAM_REG_CHAN_LIST, scan_mask);
}
static int si1133_chan_set_adcconfig(struct si1133_data *data, u8 adc,
u8 adc_config)
{
int err;
err = si1133_param_set(data, SI1133_PARAM_REG_ADCCONFIG(adc),
adc_config);
if (err)
return err;
data->adc_config[adc] = adc_config;
return 0;
}
static int si1133_update_adcconfig(struct si1133_data *data, uint8_t adc,
u8 mask, u8 shift, u8 value)
{
u32 adc_config;
int err;
err = si1133_param_query(data, SI1133_PARAM_REG_ADCCONFIG(adc),
&adc_config);
if (err)
return err;
adc_config &= ~mask;
adc_config |= (value << shift);
return si1133_chan_set_adcconfig(data, adc, adc_config);
}
static int si1133_set_adcmux(struct si1133_data *data, u8 adc, u8 mux)
{
if ((mux & data->adc_config[adc]) == mux)
return 0; /* mux already set to correct value */
return si1133_update_adcconfig(data, adc, SI1133_ADCMUX_MASK, 0, mux);
}
static int si1133_force_measurement(struct si1133_data *data)
{
return si1133_command(data, SI1133_CMD_FORCE);
}
static int si1133_bulk_read(struct si1133_data *data, u8 start_reg, u8 length,
u8 *buffer)
{
int err;
err = si1133_force_measurement(data);
if (err)
return err;
return regmap_bulk_read(data->regmap, start_reg, buffer, length);
}
static int si1133_measure(struct si1133_data *data,
struct iio_chan_spec const *chan,
int *val)
{
int err;
u8 buffer[SI1133_MEASURE_BUFFER_SIZE];
err = si1133_set_adcmux(data, 0, chan->channel);
if (err)
return err;
/* Deactivate lux measurements if they were active */
err = si1133_set_chlist(data, BIT(0));
if (err)
return err;
err = si1133_bulk_read(data, SI1133_REG_HOSTOUT(0), sizeof(buffer),
buffer);
if (err)
return err;
*val = sign_extend32(get_unaligned_be24(&buffer[0]), 23);
return err;
}
static irqreturn_t si1133_threaded_irq_handler(int irq, void *private)
{
struct iio_dev *iio_dev = private;
struct si1133_data *data = iio_priv(iio_dev);
u32 irq_status;
int err;
err = regmap_read(data->regmap, SI1133_REG_IRQ_STATUS, &irq_status);
if (err) {
dev_err_ratelimited(&iio_dev->dev, "Error reading IRQ\n");
goto out;
}
if (irq_status != data->scan_mask)
return IRQ_NONE;
out:
complete(&data->completion);
return IRQ_HANDLED;
}
static int si1133_scale_to_swgain(int scale_integer, int scale_fractional)
{
scale_integer = find_closest(scale_integer, si1133_scale_available,
ARRAY_SIZE(si1133_scale_available));
if (scale_integer < 0 ||
scale_integer > ARRAY_SIZE(si1133_scale_available) ||
scale_fractional != 0)
return -EINVAL;
return scale_integer;
}
static int si1133_chan_set_adcsens(struct si1133_data *data, u8 adc,
u8 adc_sens)
{
int err;
err = si1133_param_set(data, SI1133_PARAM_REG_ADCSENS(adc), adc_sens);
if (err)
return err;
data->adc_sens[adc] = adc_sens;
return 0;
}
static int si1133_update_adcsens(struct si1133_data *data, u8 mask,
u8 shift, u8 value)
{
int err;
u32 adc_sens;
err = si1133_param_query(data, SI1133_PARAM_REG_ADCSENS(0),
&adc_sens);
if (err)
return err;
adc_sens &= ~mask;
adc_sens |= (value << shift);
return si1133_chan_set_adcsens(data, 0, adc_sens);
}
static int si1133_get_lux(struct si1133_data *data, int *val)
{
int err;
int lux;
s32 high_vis;
s32 low_vis;
s32 ir;
u8 buffer[SI1133_LUX_BUFFER_SIZE];
/* Activate lux channels */
err = si1133_set_chlist(data, SI1133_LUX_ADC_MASK);
if (err)
return err;
err = si1133_bulk_read(data, SI1133_REG_HOSTOUT(0),
SI1133_LUX_BUFFER_SIZE, buffer);
if (err)
return err;
high_vis = sign_extend32(get_unaligned_be24(&buffer[0]), 23);
low_vis = sign_extend32(get_unaligned_be24(&buffer[3]), 23);
ir = sign_extend32(get_unaligned_be24(&buffer[6]), 23);
if (high_vis > SI1133_ADC_THRESHOLD || ir > SI1133_ADC_THRESHOLD)
lux = si1133_calc_polynomial(high_vis, ir,
SI1133_INPUT_FRACTION_HIGH,
ARRAY_SIZE(lux_coeff.coeff_high),
&lux_coeff.coeff_high[0]);
else
lux = si1133_calc_polynomial(low_vis, ir,
SI1133_INPUT_FRACTION_LOW,
ARRAY_SIZE(lux_coeff.coeff_low),
&lux_coeff.coeff_low[0]);
*val = lux >> SI1133_LUX_OUTPUT_FRACTION;
return err;
}
static int si1133_read_raw(struct iio_dev *iio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct si1133_data *data = iio_priv(iio_dev);
u8 adc_sens = data->adc_sens[0];
int err;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_LIGHT:
err = si1133_get_lux(data, val);
if (err)
return err;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_INTENSITY:
case IIO_UVINDEX:
err = si1133_measure(data, chan, val);
if (err)
return err;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_INT_TIME:
switch (chan->type) {
case IIO_INTENSITY:
case IIO_UVINDEX:
adc_sens &= SI1133_ADCSENS_HW_GAIN_MASK;
*val = si1133_int_time_table[adc_sens][0];
*val2 = si1133_int_time_table[adc_sens][1];
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_INTENSITY:
case IIO_UVINDEX:
adc_sens &= SI1133_ADCSENS_SCALE_MASK;
adc_sens >>= SI1133_ADCSENS_SCALE_SHIFT;
*val = BIT(adc_sens);
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_HARDWAREGAIN:
switch (chan->type) {
case IIO_INTENSITY:
case IIO_UVINDEX:
adc_sens >>= SI1133_ADCSENS_HSIG_SHIFT;
*val = adc_sens;
return IIO_VAL_INT;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int si1133_write_raw(struct iio_dev *iio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct si1133_data *data = iio_priv(iio_dev);
switch (mask) {
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_INTENSITY:
case IIO_UVINDEX:
val = si1133_scale_to_swgain(val, val2);
if (val < 0)
return val;
return si1133_update_adcsens(data,
SI1133_ADCSENS_SCALE_MASK,
SI1133_ADCSENS_SCALE_SHIFT,
val);
default:
return -EINVAL;
}
case IIO_CHAN_INFO_INT_TIME:
return si1133_set_integration_time(data, 0, val, val2);
case IIO_CHAN_INFO_HARDWAREGAIN:
switch (chan->type) {
case IIO_INTENSITY:
case IIO_UVINDEX:
if (val != 0 && val != 1)
return -EINVAL;
return si1133_update_adcsens(data,
SI1133_ADCSENS_HSIG_MASK,
SI1133_ADCSENS_HSIG_SHIFT,
val);
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static struct attribute *si1133_attributes[] = {
&iio_const_attr_integration_time_available.dev_attr.attr,
&iio_const_attr_scale_available.dev_attr.attr,
NULL,
};
static const struct attribute_group si1133_attribute_group = {
.attrs = si1133_attributes,
};
static const struct iio_info si1133_info = {
.read_raw = si1133_read_raw,
.write_raw = si1133_write_raw,
.attrs = &si1133_attribute_group,
};
/*
* si1133_init_lux_channels - Configure 3 different channels(adc) (1,2 and 3)
* The channel configuration for the lux measurement was taken from :
* https://siliconlabs.github.io/Gecko_SDK_Doc/efm32zg/html/si1133_8c_source.html#l00578
*
* Reserved the channel 0 for the other raw measurements
*/
static int si1133_init_lux_channels(struct si1133_data *data)
{
int err;
err = si1133_chan_set_adcconfig(data, 1,
SI1133_ADCCONFIG_DECIM_RATE(1) |
SI1133_PARAM_ADCMUX_LARGE_WHITE);
if (err)
return err;
err = si1133_param_set(data, SI1133_PARAM_REG_ADCPOST(1),
SI1133_ADCPOST_24BIT_EN |
SI1133_ADCPOST_POSTSHIFT_BITQTY(0));
if (err)
return err;
err = si1133_chan_set_adcsens(data, 1, SI1133_ADCSENS_HSIG_MASK |
SI1133_ADCSENS_NB_MEAS(64) | _48_8_us);
if (err)
return err;
err = si1133_chan_set_adcconfig(data, 2,
SI1133_ADCCONFIG_DECIM_RATE(1) |
SI1133_PARAM_ADCMUX_LARGE_WHITE);
if (err)
return err;
err = si1133_param_set(data, SI1133_PARAM_REG_ADCPOST(2),
SI1133_ADCPOST_24BIT_EN |
SI1133_ADCPOST_POSTSHIFT_BITQTY(2));
if (err)
return err;
err = si1133_chan_set_adcsens(data, 2, SI1133_ADCSENS_HSIG_MASK |
SI1133_ADCSENS_NB_MEAS(1) | _3_120_0_us);
if (err)
return err;
err = si1133_chan_set_adcconfig(data, 3,
SI1133_ADCCONFIG_DECIM_RATE(1) |
SI1133_PARAM_ADCMUX_MED_IR);
if (err)
return err;
err = si1133_param_set(data, SI1133_PARAM_REG_ADCPOST(3),
SI1133_ADCPOST_24BIT_EN |
SI1133_ADCPOST_POSTSHIFT_BITQTY(2));
if (err)
return err;
return si1133_chan_set_adcsens(data, 3, SI1133_ADCSENS_HSIG_MASK |
SI1133_ADCSENS_NB_MEAS(64) | _48_8_us);
}
static int si1133_initialize(struct si1133_data *data)
{
int err;
err = si1133_cmd_reset_sw(data);
if (err)
return err;
/* Turn off autonomous mode */
err = si1133_param_set(data, SI1133_REG_MEAS_RATE, 0);
if (err)
return err;
err = si1133_init_lux_channels(data);
if (err)
return err;
return regmap_write(data->regmap, SI1133_REG_IRQ_ENABLE,
SI1133_IRQ_CHANNEL_ENABLE);
}
static int si1133_validate_ids(struct iio_dev *iio_dev)
{
struct si1133_data *data = iio_priv(iio_dev);
unsigned int part_id, rev_id, mfr_id;
int err;
err = regmap_read(data->regmap, SI1133_REG_PART_ID, &part_id);
if (err)
return err;
err = regmap_read(data->regmap, SI1133_REG_REV_ID, &rev_id);
if (err)
return err;
err = regmap_read(data->regmap, SI1133_REG_MFR_ID, &mfr_id);
if (err)
return err;
dev_info(&iio_dev->dev,
"Device ID part 0x%02x rev 0x%02x mfr 0x%02x\n",
part_id, rev_id, mfr_id);
if (part_id != SI1133_PART_ID) {
dev_err(&iio_dev->dev,
"Part ID mismatch got 0x%02x, expected 0x%02x\n",
part_id, SI1133_PART_ID);
return -ENODEV;
}
return 0;
}
static int si1133_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct si1133_data *data;
struct iio_dev *iio_dev;
int err;
iio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!iio_dev)
return -ENOMEM;
data = iio_priv(iio_dev);
init_completion(&data->completion);
data->regmap = devm_regmap_init_i2c(client, &si1133_regmap_config);
if (IS_ERR(data->regmap)) {
err = PTR_ERR(data->regmap);
dev_err(&client->dev, "Failed to initialise regmap: %d\n", err);
return err;
}
i2c_set_clientdata(client, iio_dev);
data->client = client;
iio_dev->name = id->name;
iio_dev->channels = si1133_channels;
iio_dev->num_channels = ARRAY_SIZE(si1133_channels);
iio_dev->info = &si1133_info;
iio_dev->modes = INDIO_DIRECT_MODE;
mutex_init(&data->mutex);
err = si1133_validate_ids(iio_dev);
if (err)
return err;
err = si1133_initialize(data);
if (err) {
dev_err(&client->dev,
"Error when initializing chip: %d\n", err);
return err;
}
if (!client->irq) {
dev_err(&client->dev,
"Required interrupt not provided, cannot proceed\n");
return -EINVAL;
}
err = devm_request_threaded_irq(&client->dev, client->irq,
NULL,
si1133_threaded_irq_handler,
IRQF_ONESHOT | IRQF_SHARED,
client->name, iio_dev);
if (err) {
dev_warn(&client->dev, "Request irq %d failed: %i\n",
client->irq, err);
return err;
}
return devm_iio_device_register(&client->dev, iio_dev);
}
static const struct i2c_device_id si1133_ids[] = {
{ "si1133", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, si1133_ids);
static struct i2c_driver si1133_driver = {
.driver = {
.name = "si1133",
},
.probe = si1133_probe,
.id_table = si1133_ids,
};
module_i2c_driver(si1133_driver);
MODULE_AUTHOR("Maxime Roussin-Belanger <[email protected]>");
MODULE_DESCRIPTION("Silabs SI1133, UV index sensor and ambient light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/si1133.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ROHM BH1710/BH1715/BH1721/BH1750/BH1751 ambient light sensor driver
*
* Copyright (c) Tomasz Duszynski <[email protected]>
*
* Data sheets:
* http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/light/bh1710fvc-e.pdf
* http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/light/bh1715fvc-e.pdf
* http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/light/bh1721fvc-e.pdf
* http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/light/bh1750fvi-e.pdf
* http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/light/bh1751fvi-e.pdf
*
* 7-bit I2C slave addresses:
* 0x23 (ADDR pin low)
* 0x5C (ADDR pin high)
*
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/module.h>
#define BH1750_POWER_DOWN 0x00
#define BH1750_ONE_TIME_H_RES_MODE 0x20 /* auto-mode for BH1721 */
#define BH1750_CHANGE_INT_TIME_H_BIT 0x40
#define BH1750_CHANGE_INT_TIME_L_BIT 0x60
enum {
BH1710,
BH1721,
BH1750,
};
struct bh1750_chip_info;
struct bh1750_data {
struct i2c_client *client;
struct mutex lock;
const struct bh1750_chip_info *chip_info;
u16 mtreg;
};
struct bh1750_chip_info {
u16 mtreg_min;
u16 mtreg_max;
u16 mtreg_default;
int mtreg_to_usec;
int mtreg_to_scale;
/*
* For BH1710/BH1721 all possible integration time values won't fit
* into one page so displaying is limited to every second one.
* Note, that user can still write proper values which were not
* listed.
*/
int inc;
u16 int_time_low_mask;
u16 int_time_high_mask;
};
static const struct bh1750_chip_info bh1750_chip_info_tbl[] = {
[BH1710] = { 140, 1022, 300, 400, 250000000, 2, 0x001F, 0x03E0 },
[BH1721] = { 140, 1020, 300, 400, 250000000, 2, 0x0010, 0x03E0 },
[BH1750] = { 31, 254, 69, 1740, 57500000, 1, 0x001F, 0x00E0 },
};
static int bh1750_change_int_time(struct bh1750_data *data, int usec)
{
int ret;
u16 val;
u8 regval;
const struct bh1750_chip_info *chip_info = data->chip_info;
if ((usec % chip_info->mtreg_to_usec) != 0)
return -EINVAL;
val = usec / chip_info->mtreg_to_usec;
if (val < chip_info->mtreg_min || val > chip_info->mtreg_max)
return -EINVAL;
ret = i2c_smbus_write_byte(data->client, BH1750_POWER_DOWN);
if (ret < 0)
return ret;
regval = (val & chip_info->int_time_high_mask) >> 5;
ret = i2c_smbus_write_byte(data->client,
BH1750_CHANGE_INT_TIME_H_BIT | regval);
if (ret < 0)
return ret;
regval = val & chip_info->int_time_low_mask;
ret = i2c_smbus_write_byte(data->client,
BH1750_CHANGE_INT_TIME_L_BIT | regval);
if (ret < 0)
return ret;
data->mtreg = val;
return 0;
}
static int bh1750_read(struct bh1750_data *data, int *val)
{
int ret;
__be16 result;
const struct bh1750_chip_info *chip_info = data->chip_info;
unsigned long delay = chip_info->mtreg_to_usec * data->mtreg;
/*
* BH1721 will enter continuous mode on receiving this command.
* Note, that this eliminates need for bh1750_resume().
*/
ret = i2c_smbus_write_byte(data->client, BH1750_ONE_TIME_H_RES_MODE);
if (ret < 0)
return ret;
usleep_range(delay + 15000, delay + 40000);
ret = i2c_master_recv(data->client, (char *)&result, 2);
if (ret < 0)
return ret;
*val = be16_to_cpu(result);
return 0;
}
static int bh1750_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
int ret, tmp;
struct bh1750_data *data = iio_priv(indio_dev);
const struct bh1750_chip_info *chip_info = data->chip_info;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_LIGHT:
mutex_lock(&data->lock);
ret = bh1750_read(data, val);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SCALE:
tmp = chip_info->mtreg_to_scale / data->mtreg;
*val = tmp / 1000000;
*val2 = tmp % 1000000;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_INT_TIME:
*val = 0;
*val2 = chip_info->mtreg_to_usec * data->mtreg;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int bh1750_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
int ret;
struct bh1750_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
if (val != 0)
return -EINVAL;
mutex_lock(&data->lock);
ret = bh1750_change_int_time(data, val2);
mutex_unlock(&data->lock);
return ret;
default:
return -EINVAL;
}
}
static ssize_t bh1750_show_int_time_available(struct device *dev,
struct device_attribute *attr, char *buf)
{
int i;
size_t len = 0;
struct bh1750_data *data = iio_priv(dev_to_iio_dev(dev));
const struct bh1750_chip_info *chip_info = data->chip_info;
for (i = chip_info->mtreg_min; i <= chip_info->mtreg_max; i += chip_info->inc)
len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06d ",
chip_info->mtreg_to_usec * i);
buf[len - 1] = '\n';
return len;
}
static IIO_DEV_ATTR_INT_TIME_AVAIL(bh1750_show_int_time_available);
static struct attribute *bh1750_attributes[] = {
&iio_dev_attr_integration_time_available.dev_attr.attr,
NULL,
};
static const struct attribute_group bh1750_attribute_group = {
.attrs = bh1750_attributes,
};
static const struct iio_info bh1750_info = {
.attrs = &bh1750_attribute_group,
.read_raw = bh1750_read_raw,
.write_raw = bh1750_write_raw,
};
static const struct iio_chan_spec bh1750_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_INT_TIME)
}
};
static int bh1750_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
int ret, usec;
struct bh1750_data *data;
struct iio_dev *indio_dev;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
I2C_FUNC_SMBUS_WRITE_BYTE))
return -EOPNOTSUPP;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->chip_info = &bh1750_chip_info_tbl[id->driver_data];
usec = data->chip_info->mtreg_to_usec * data->chip_info->mtreg_default;
ret = bh1750_change_int_time(data, usec);
if (ret < 0)
return ret;
mutex_init(&data->lock);
indio_dev->info = &bh1750_info;
indio_dev->name = id->name;
indio_dev->channels = bh1750_channels;
indio_dev->num_channels = ARRAY_SIZE(bh1750_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
return iio_device_register(indio_dev);
}
static void bh1750_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct bh1750_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
mutex_lock(&data->lock);
i2c_smbus_write_byte(client, BH1750_POWER_DOWN);
mutex_unlock(&data->lock);
}
static int bh1750_suspend(struct device *dev)
{
int ret;
struct bh1750_data *data =
iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
/*
* This is mainly for BH1721 which doesn't enter power down
* mode automatically.
*/
mutex_lock(&data->lock);
ret = i2c_smbus_write_byte(data->client, BH1750_POWER_DOWN);
mutex_unlock(&data->lock);
return ret;
}
static DEFINE_SIMPLE_DEV_PM_OPS(bh1750_pm_ops, bh1750_suspend, NULL);
static const struct i2c_device_id bh1750_id[] = {
{ "bh1710", BH1710 },
{ "bh1715", BH1750 },
{ "bh1721", BH1721 },
{ "bh1750", BH1750 },
{ "bh1751", BH1750 },
{ }
};
MODULE_DEVICE_TABLE(i2c, bh1750_id);
static const struct of_device_id bh1750_of_match[] = {
{ .compatible = "rohm,bh1710", },
{ .compatible = "rohm,bh1715", },
{ .compatible = "rohm,bh1721", },
{ .compatible = "rohm,bh1750", },
{ .compatible = "rohm,bh1751", },
{ }
};
MODULE_DEVICE_TABLE(of, bh1750_of_match);
static struct i2c_driver bh1750_driver = {
.driver = {
.name = "bh1750",
.of_match_table = bh1750_of_match,
.pm = pm_sleep_ptr(&bh1750_pm_ops),
},
.probe = bh1750_probe,
.remove = bh1750_remove,
.id_table = bh1750_id,
};
module_i2c_driver(bh1750_driver);
MODULE_AUTHOR("Tomasz Duszynski <[email protected]>");
MODULE_DESCRIPTION("ROHM BH1710/BH1715/BH1721/BH1750/BH1751 als driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/bh1750.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015 Intel Corporation
*
* Driver for UPISEMI us5182d Proximity and Ambient Light Sensor.
*
* To do: Interrupt support.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/iio/sysfs.h>
#include <linux/mutex.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#define US5182D_REG_CFG0 0x00
#define US5182D_CFG0_ONESHOT_EN BIT(6)
#define US5182D_CFG0_SHUTDOWN_EN BIT(7)
#define US5182D_CFG0_WORD_ENABLE BIT(0)
#define US5182D_CFG0_PROX BIT(3)
#define US5182D_CFG0_PX_IRQ BIT(2)
#define US5182D_REG_CFG1 0x01
#define US5182D_CFG1_ALS_RES16 BIT(4)
#define US5182D_CFG1_AGAIN_DEFAULT 0x00
#define US5182D_REG_CFG2 0x02
#define US5182D_CFG2_PX_RES16 BIT(4)
#define US5182D_CFG2_PXGAIN_DEFAULT BIT(2)
#define US5182D_REG_CFG3 0x03
#define US5182D_CFG3_LED_CURRENT100 (BIT(4) | BIT(5))
#define US5182D_CFG3_INT_SOURCE_PX BIT(3)
#define US5182D_REG_CFG4 0x10
/*
* Registers for tuning the auto dark current cancelling feature.
* DARK_TH(reg 0x27,0x28) - threshold (counts) for auto dark cancelling.
* when ALS > DARK_TH --> ALS_Code = ALS - Upper(0x2A) * Dark
* when ALS < DARK_TH --> ALS_Code = ALS - Lower(0x29) * Dark
*/
#define US5182D_REG_UDARK_TH 0x27
#define US5182D_REG_DARK_AUTO_EN 0x2b
#define US5182D_REG_AUTO_LDARK_GAIN 0x29
#define US5182D_REG_AUTO_HDARK_GAIN 0x2a
/* Thresholds for events: px low (0x08-l, 0x09-h), px high (0x0a-l 0x0b-h) */
#define US5182D_REG_PXL_TH 0x08
#define US5182D_REG_PXH_TH 0x0a
#define US5182D_REG_PXL_TH_DEFAULT 1000
#define US5182D_REG_PXH_TH_DEFAULT 30000
#define US5182D_OPMODE_ALS 0x01
#define US5182D_OPMODE_PX 0x02
#define US5182D_OPMODE_SHIFT 4
#define US5182D_REG_DARK_AUTO_EN_DEFAULT 0x80
#define US5182D_REG_AUTO_LDARK_GAIN_DEFAULT 0x16
#define US5182D_REG_AUTO_HDARK_GAIN_DEFAULT 0x00
#define US5182D_REG_ADL 0x0c
#define US5182D_REG_PDL 0x0e
#define US5182D_REG_MODE_STORE 0x21
#define US5182D_STORE_MODE 0x01
#define US5182D_REG_CHIPID 0xb2
#define US5182D_OPMODE_MASK GENMASK(5, 4)
#define US5182D_AGAIN_MASK 0x07
#define US5182D_RESET_CHIP 0x01
#define US5182D_CHIPID 0x26
#define US5182D_DRV_NAME "us5182d"
#define US5182D_GA_RESOLUTION 1000
#define US5182D_READ_BYTE 1
#define US5182D_READ_WORD 2
#define US5182D_OPSTORE_SLEEP_TIME 20 /* ms */
#define US5182D_SLEEP_MS 3000 /* ms */
#define US5182D_PXH_TH_DISABLE 0xffff
#define US5182D_PXL_TH_DISABLE 0x0000
/* Available ranges: [12354, 7065, 3998, 2202, 1285, 498, 256, 138] lux */
static const int us5182d_scales[] = {188500, 107800, 61000, 33600, 19600, 7600,
3900, 2100};
/*
* Experimental thresholds that work with US5182D sensor on evaluation board
* roughly between 12-32 lux
*/
static u16 us5182d_dark_ths_vals[] = {170, 200, 512, 512, 800, 2000, 4000,
8000};
enum mode {
US5182D_ALS_PX,
US5182D_ALS_ONLY,
US5182D_PX_ONLY
};
enum pmode {
US5182D_CONTINUOUS,
US5182D_ONESHOT
};
struct us5182d_data {
struct i2c_client *client;
struct mutex lock;
/* Glass attenuation factor */
u32 ga;
/* Dark gain tuning */
u8 lower_dark_gain;
u8 upper_dark_gain;
u16 *us5182d_dark_ths;
u16 px_low_th;
u16 px_high_th;
int rising_en;
int falling_en;
u8 opmode;
u8 power_mode;
bool als_enabled;
bool px_enabled;
bool default_continuous;
};
static IIO_CONST_ATTR(in_illuminance_scale_available,
"0.0021 0.0039 0.0076 0.0196 0.0336 0.061 0.1078 0.1885");
static struct attribute *us5182d_attrs[] = {
&iio_const_attr_in_illuminance_scale_available.dev_attr.attr,
NULL
};
static const struct attribute_group us5182d_attr_group = {
.attrs = us5182d_attrs,
};
static const struct {
u8 reg;
u8 val;
} us5182d_regvals[] = {
{US5182D_REG_CFG0, US5182D_CFG0_WORD_ENABLE},
{US5182D_REG_CFG1, US5182D_CFG1_ALS_RES16},
{US5182D_REG_CFG2, (US5182D_CFG2_PX_RES16 |
US5182D_CFG2_PXGAIN_DEFAULT)},
{US5182D_REG_CFG3, US5182D_CFG3_LED_CURRENT100 |
US5182D_CFG3_INT_SOURCE_PX},
{US5182D_REG_CFG4, 0x00},
};
static const struct iio_event_spec us5182d_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec us5182d_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
{
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.event_spec = us5182d_events,
.num_event_specs = ARRAY_SIZE(us5182d_events),
}
};
static int us5182d_oneshot_en(struct us5182d_data *data)
{
int ret;
ret = i2c_smbus_read_byte_data(data->client, US5182D_REG_CFG0);
if (ret < 0)
return ret;
/*
* In oneshot mode the chip will power itself down after taking the
* required measurement.
*/
ret = ret | US5182D_CFG0_ONESHOT_EN;
return i2c_smbus_write_byte_data(data->client, US5182D_REG_CFG0, ret);
}
static int us5182d_set_opmode(struct us5182d_data *data, u8 mode)
{
int ret;
if (mode == data->opmode)
return 0;
ret = i2c_smbus_read_byte_data(data->client, US5182D_REG_CFG0);
if (ret < 0)
return ret;
/* update mode */
ret = ret & ~US5182D_OPMODE_MASK;
ret = ret | (mode << US5182D_OPMODE_SHIFT);
/*
* After updating the operating mode, the chip requires that
* the operation is stored, by writing 1 in the STORE_MODE
* register (auto-clearing).
*/
ret = i2c_smbus_write_byte_data(data->client, US5182D_REG_CFG0, ret);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client, US5182D_REG_MODE_STORE,
US5182D_STORE_MODE);
if (ret < 0)
return ret;
data->opmode = mode;
msleep(US5182D_OPSTORE_SLEEP_TIME);
return 0;
}
static int us5182d_als_enable(struct us5182d_data *data)
{
int ret;
u8 mode;
if (data->power_mode == US5182D_ONESHOT) {
ret = us5182d_set_opmode(data, US5182D_ALS_ONLY);
if (ret < 0)
return ret;
data->px_enabled = false;
}
if (data->als_enabled)
return 0;
mode = data->px_enabled ? US5182D_ALS_PX : US5182D_ALS_ONLY;
ret = us5182d_set_opmode(data, mode);
if (ret < 0)
return ret;
data->als_enabled = true;
return 0;
}
static int us5182d_px_enable(struct us5182d_data *data)
{
int ret;
u8 mode;
if (data->power_mode == US5182D_ONESHOT) {
ret = us5182d_set_opmode(data, US5182D_PX_ONLY);
if (ret < 0)
return ret;
data->als_enabled = false;
}
if (data->px_enabled)
return 0;
mode = data->als_enabled ? US5182D_ALS_PX : US5182D_PX_ONLY;
ret = us5182d_set_opmode(data, mode);
if (ret < 0)
return ret;
data->px_enabled = true;
return 0;
}
static int us5182d_get_als(struct us5182d_data *data)
{
int ret;
unsigned long result;
ret = us5182d_als_enable(data);
if (ret < 0)
return ret;
ret = i2c_smbus_read_word_data(data->client,
US5182D_REG_ADL);
if (ret < 0)
return ret;
result = ret * data->ga / US5182D_GA_RESOLUTION;
if (result > 0xffff)
result = 0xffff;
return result;
}
static int us5182d_get_px(struct us5182d_data *data)
{
int ret;
ret = us5182d_px_enable(data);
if (ret < 0)
return ret;
return i2c_smbus_read_word_data(data->client,
US5182D_REG_PDL);
}
static int us5182d_shutdown_en(struct us5182d_data *data, u8 state)
{
int ret;
if (data->power_mode == US5182D_ONESHOT)
return 0;
ret = i2c_smbus_read_byte_data(data->client, US5182D_REG_CFG0);
if (ret < 0)
return ret;
ret = ret & ~US5182D_CFG0_SHUTDOWN_EN;
ret = ret | state;
ret = i2c_smbus_write_byte_data(data->client, US5182D_REG_CFG0, ret);
if (ret < 0)
return ret;
if (state & US5182D_CFG0_SHUTDOWN_EN) {
data->als_enabled = false;
data->px_enabled = false;
}
return ret;
}
static int us5182d_set_power_state(struct us5182d_data *data, bool on)
{
int ret;
if (data->power_mode == US5182D_ONESHOT)
return 0;
if (on) {
ret = pm_runtime_resume_and_get(&data->client->dev);
} else {
pm_runtime_mark_last_busy(&data->client->dev);
ret = pm_runtime_put_autosuspend(&data->client->dev);
}
return ret;
}
static int us5182d_read_value(struct us5182d_data *data,
struct iio_chan_spec const *chan)
{
int ret, value;
mutex_lock(&data->lock);
if (data->power_mode == US5182D_ONESHOT) {
ret = us5182d_oneshot_en(data);
if (ret < 0)
goto out_err;
}
ret = us5182d_set_power_state(data, true);
if (ret < 0)
goto out_err;
if (chan->type == IIO_LIGHT)
ret = us5182d_get_als(data);
else
ret = us5182d_get_px(data);
if (ret < 0)
goto out_poweroff;
value = ret;
ret = us5182d_set_power_state(data, false);
if (ret < 0)
goto out_err;
mutex_unlock(&data->lock);
return value;
out_poweroff:
us5182d_set_power_state(data, false);
out_err:
mutex_unlock(&data->lock);
return ret;
}
static int us5182d_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct us5182d_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = us5182d_read_value(data, chan);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = i2c_smbus_read_byte_data(data->client, US5182D_REG_CFG1);
if (ret < 0)
return ret;
*val = 0;
*val2 = us5182d_scales[ret & US5182D_AGAIN_MASK];
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
/**
* us5182d_update_dark_th - update Darh_Th registers
* @data: us5182d_data structure
* @index: index in us5182d_dark_ths array to use for the updated value
*
* Function needs to be called with a lock held because it needs two i2c write
* byte operations as these registers (0x27 0x28) don't work in word mode
* accessing.
*/
static int us5182d_update_dark_th(struct us5182d_data *data, int index)
{
__be16 dark_th = cpu_to_be16(data->us5182d_dark_ths[index]);
int ret;
ret = i2c_smbus_write_byte_data(data->client, US5182D_REG_UDARK_TH,
((u8 *)&dark_th)[0]);
if (ret < 0)
return ret;
return i2c_smbus_write_byte_data(data->client, US5182D_REG_UDARK_TH + 1,
((u8 *)&dark_th)[1]);
}
/**
* us5182d_apply_scale - update the ALS scale
* @data: us5182d_data structure
* @index: index in us5182d_scales array to use for the updated value
*
* Function needs to be called with a lock held as we're having more than one
* i2c operation.
*/
static int us5182d_apply_scale(struct us5182d_data *data, int index)
{
int ret;
ret = i2c_smbus_read_byte_data(data->client, US5182D_REG_CFG1);
if (ret < 0)
return ret;
ret = ret & (~US5182D_AGAIN_MASK);
ret |= index;
ret = i2c_smbus_write_byte_data(data->client, US5182D_REG_CFG1, ret);
if (ret < 0)
return ret;
return us5182d_update_dark_th(data, index);
}
static int us5182d_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct us5182d_data *data = iio_priv(indio_dev);
int ret, i;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
if (val != 0)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(us5182d_scales); i++)
if (val2 == us5182d_scales[i]) {
mutex_lock(&data->lock);
ret = us5182d_apply_scale(data, i);
mutex_unlock(&data->lock);
return ret;
}
break;
default:
return -EINVAL;
}
return -EINVAL;
}
static int us5182d_setup_prox(struct iio_dev *indio_dev,
enum iio_event_direction dir, u16 val)
{
struct us5182d_data *data = iio_priv(indio_dev);
if (dir == IIO_EV_DIR_FALLING)
return i2c_smbus_write_word_data(data->client,
US5182D_REG_PXL_TH, val);
else if (dir == IIO_EV_DIR_RISING)
return i2c_smbus_write_word_data(data->client,
US5182D_REG_PXH_TH, val);
return 0;
}
static int us5182d_read_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info, int *val,
int *val2)
{
struct us5182d_data *data = iio_priv(indio_dev);
switch (dir) {
case IIO_EV_DIR_RISING:
mutex_lock(&data->lock);
*val = data->px_high_th;
mutex_unlock(&data->lock);
break;
case IIO_EV_DIR_FALLING:
mutex_lock(&data->lock);
*val = data->px_low_th;
mutex_unlock(&data->lock);
break;
default:
return -EINVAL;
}
return IIO_VAL_INT;
}
static int us5182d_write_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info, int val,
int val2)
{
struct us5182d_data *data = iio_priv(indio_dev);
int ret;
if (val < 0 || val > USHRT_MAX || val2 != 0)
return -EINVAL;
switch (dir) {
case IIO_EV_DIR_RISING:
mutex_lock(&data->lock);
if (data->rising_en) {
ret = us5182d_setup_prox(indio_dev, dir, val);
if (ret < 0)
goto err;
}
data->px_high_th = val;
mutex_unlock(&data->lock);
break;
case IIO_EV_DIR_FALLING:
mutex_lock(&data->lock);
if (data->falling_en) {
ret = us5182d_setup_prox(indio_dev, dir, val);
if (ret < 0)
goto err;
}
data->px_low_th = val;
mutex_unlock(&data->lock);
break;
default:
return -EINVAL;
}
return 0;
err:
mutex_unlock(&data->lock);
return ret;
}
static int us5182d_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir)
{
struct us5182d_data *data = iio_priv(indio_dev);
int ret;
switch (dir) {
case IIO_EV_DIR_RISING:
mutex_lock(&data->lock);
ret = data->rising_en;
mutex_unlock(&data->lock);
break;
case IIO_EV_DIR_FALLING:
mutex_lock(&data->lock);
ret = data->falling_en;
mutex_unlock(&data->lock);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int us5182d_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct us5182d_data *data = iio_priv(indio_dev);
int ret;
u16 new_th;
mutex_lock(&data->lock);
switch (dir) {
case IIO_EV_DIR_RISING:
if (data->rising_en == state) {
mutex_unlock(&data->lock);
return 0;
}
new_th = US5182D_PXH_TH_DISABLE;
if (state) {
data->power_mode = US5182D_CONTINUOUS;
ret = us5182d_set_power_state(data, true);
if (ret < 0)
goto err;
ret = us5182d_px_enable(data);
if (ret < 0)
goto err_poweroff;
new_th = data->px_high_th;
}
ret = us5182d_setup_prox(indio_dev, dir, new_th);
if (ret < 0)
goto err_poweroff;
data->rising_en = state;
break;
case IIO_EV_DIR_FALLING:
if (data->falling_en == state) {
mutex_unlock(&data->lock);
return 0;
}
new_th = US5182D_PXL_TH_DISABLE;
if (state) {
data->power_mode = US5182D_CONTINUOUS;
ret = us5182d_set_power_state(data, true);
if (ret < 0)
goto err;
ret = us5182d_px_enable(data);
if (ret < 0)
goto err_poweroff;
new_th = data->px_low_th;
}
ret = us5182d_setup_prox(indio_dev, dir, new_th);
if (ret < 0)
goto err_poweroff;
data->falling_en = state;
break;
default:
ret = -EINVAL;
goto err;
}
if (!state) {
ret = us5182d_set_power_state(data, false);
if (ret < 0)
goto err;
}
if (!data->falling_en && !data->rising_en && !data->default_continuous)
data->power_mode = US5182D_ONESHOT;
mutex_unlock(&data->lock);
return 0;
err_poweroff:
if (state)
us5182d_set_power_state(data, false);
err:
mutex_unlock(&data->lock);
return ret;
}
static const struct iio_info us5182d_info = {
.read_raw = us5182d_read_raw,
.write_raw = us5182d_write_raw,
.attrs = &us5182d_attr_group,
.read_event_value = &us5182d_read_thresh,
.write_event_value = &us5182d_write_thresh,
.read_event_config = &us5182d_read_event_config,
.write_event_config = &us5182d_write_event_config,
};
static int us5182d_reset(struct iio_dev *indio_dev)
{
struct us5182d_data *data = iio_priv(indio_dev);
return i2c_smbus_write_byte_data(data->client, US5182D_REG_CFG3,
US5182D_RESET_CHIP);
}
static int us5182d_init(struct iio_dev *indio_dev)
{
struct us5182d_data *data = iio_priv(indio_dev);
int i, ret;
ret = us5182d_reset(indio_dev);
if (ret < 0)
return ret;
data->opmode = 0;
data->power_mode = US5182D_CONTINUOUS;
data->px_low_th = US5182D_REG_PXL_TH_DEFAULT;
data->px_high_th = US5182D_REG_PXH_TH_DEFAULT;
for (i = 0; i < ARRAY_SIZE(us5182d_regvals); i++) {
ret = i2c_smbus_write_byte_data(data->client,
us5182d_regvals[i].reg,
us5182d_regvals[i].val);
if (ret < 0)
return ret;
}
data->als_enabled = true;
data->px_enabled = true;
if (!data->default_continuous) {
ret = us5182d_shutdown_en(data, US5182D_CFG0_SHUTDOWN_EN);
if (ret < 0)
return ret;
data->power_mode = US5182D_ONESHOT;
}
return ret;
}
static void us5182d_get_platform_data(struct iio_dev *indio_dev)
{
struct us5182d_data *data = iio_priv(indio_dev);
if (device_property_read_u32(&data->client->dev, "upisemi,glass-coef",
&data->ga))
data->ga = US5182D_GA_RESOLUTION;
if (device_property_read_u16_array(&data->client->dev,
"upisemi,dark-ths",
data->us5182d_dark_ths,
ARRAY_SIZE(us5182d_dark_ths_vals)))
data->us5182d_dark_ths = us5182d_dark_ths_vals;
if (device_property_read_u8(&data->client->dev,
"upisemi,upper-dark-gain",
&data->upper_dark_gain))
data->upper_dark_gain = US5182D_REG_AUTO_HDARK_GAIN_DEFAULT;
if (device_property_read_u8(&data->client->dev,
"upisemi,lower-dark-gain",
&data->lower_dark_gain))
data->lower_dark_gain = US5182D_REG_AUTO_LDARK_GAIN_DEFAULT;
data->default_continuous = device_property_read_bool(&data->client->dev,
"upisemi,continuous");
}
static int us5182d_dark_gain_config(struct iio_dev *indio_dev)
{
struct us5182d_data *data = iio_priv(indio_dev);
int ret;
ret = us5182d_update_dark_th(data, US5182D_CFG1_AGAIN_DEFAULT);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client,
US5182D_REG_AUTO_LDARK_GAIN,
data->lower_dark_gain);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client,
US5182D_REG_AUTO_HDARK_GAIN,
data->upper_dark_gain);
if (ret < 0)
return ret;
return i2c_smbus_write_byte_data(data->client, US5182D_REG_DARK_AUTO_EN,
US5182D_REG_DARK_AUTO_EN_DEFAULT);
}
static irqreturn_t us5182d_irq_thread_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct us5182d_data *data = iio_priv(indio_dev);
enum iio_event_direction dir;
int ret;
u64 ev;
ret = i2c_smbus_read_byte_data(data->client, US5182D_REG_CFG0);
if (ret < 0) {
dev_err(&data->client->dev, "i2c transfer error in irq\n");
return IRQ_HANDLED;
}
dir = ret & US5182D_CFG0_PROX ? IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;
ev = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 1, IIO_EV_TYPE_THRESH, dir);
iio_push_event(indio_dev, ev, iio_get_time_ns(indio_dev));
ret = i2c_smbus_write_byte_data(data->client, US5182D_REG_CFG0,
ret & ~US5182D_CFG0_PX_IRQ);
if (ret < 0)
dev_err(&data->client->dev, "i2c transfer error in irq\n");
return IRQ_HANDLED;
}
static int us5182d_probe(struct i2c_client *client)
{
struct us5182d_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
mutex_init(&data->lock);
indio_dev->info = &us5182d_info;
indio_dev->name = US5182D_DRV_NAME;
indio_dev->channels = us5182d_channels;
indio_dev->num_channels = ARRAY_SIZE(us5182d_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = i2c_smbus_read_byte_data(data->client, US5182D_REG_CHIPID);
if (ret != US5182D_CHIPID) {
dev_err(&data->client->dev,
"Failed to detect US5182 light chip\n");
return (ret < 0) ? ret : -ENODEV;
}
if (client->irq > 0) {
ret = devm_request_threaded_irq(&client->dev, client->irq, NULL,
us5182d_irq_thread_handler,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"us5182d-irq", indio_dev);
if (ret < 0)
return ret;
} else
dev_warn(&client->dev, "no valid irq found\n");
us5182d_get_platform_data(indio_dev);
ret = us5182d_init(indio_dev);
if (ret < 0)
return ret;
ret = us5182d_dark_gain_config(indio_dev);
if (ret < 0)
goto out_err;
if (data->default_continuous) {
ret = pm_runtime_set_active(&client->dev);
if (ret < 0)
goto out_err;
}
pm_runtime_enable(&client->dev);
pm_runtime_set_autosuspend_delay(&client->dev,
US5182D_SLEEP_MS);
pm_runtime_use_autosuspend(&client->dev);
ret = iio_device_register(indio_dev);
if (ret < 0)
goto out_err;
return 0;
out_err:
us5182d_shutdown_en(data, US5182D_CFG0_SHUTDOWN_EN);
return ret;
}
static void us5182d_remove(struct i2c_client *client)
{
struct us5182d_data *data = iio_priv(i2c_get_clientdata(client));
int ret;
iio_device_unregister(i2c_get_clientdata(client));
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
ret = us5182d_shutdown_en(data, US5182D_CFG0_SHUTDOWN_EN);
if (ret)
dev_warn(&client->dev, "Failed to shut down (%pe)\n",
ERR_PTR(ret));
}
static int us5182d_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct us5182d_data *data = iio_priv(indio_dev);
if (data->power_mode == US5182D_CONTINUOUS)
return us5182d_shutdown_en(data, US5182D_CFG0_SHUTDOWN_EN);
return 0;
}
static int us5182d_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct us5182d_data *data = iio_priv(indio_dev);
if (data->power_mode == US5182D_CONTINUOUS)
return us5182d_shutdown_en(data,
~US5182D_CFG0_SHUTDOWN_EN & 0xff);
return 0;
}
static const struct dev_pm_ops us5182d_pm_ops = {
SYSTEM_SLEEP_PM_OPS(us5182d_suspend, us5182d_resume)
RUNTIME_PM_OPS(us5182d_suspend, us5182d_resume, NULL)
};
static const struct acpi_device_id us5182d_acpi_match[] = {
{ "USD5182", 0 },
{}
};
MODULE_DEVICE_TABLE(acpi, us5182d_acpi_match);
static const struct i2c_device_id us5182d_id[] = {
{ "usd5182", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, us5182d_id);
static const struct of_device_id us5182d_of_match[] = {
{ .compatible = "upisemi,usd5182" },
{}
};
MODULE_DEVICE_TABLE(of, us5182d_of_match);
static struct i2c_driver us5182d_driver = {
.driver = {
.name = US5182D_DRV_NAME,
.pm = pm_ptr(&us5182d_pm_ops),
.of_match_table = us5182d_of_match,
.acpi_match_table = ACPI_PTR(us5182d_acpi_match),
},
.probe = us5182d_probe,
.remove = us5182d_remove,
.id_table = us5182d_id,
};
module_i2c_driver(us5182d_driver);
MODULE_AUTHOR("Adriana Reus <[email protected]>");
MODULE_DESCRIPTION("Driver for us5182d Proximity and Light Sensor");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/us5182d.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* zopt2201.c - Support for IDT ZOPT2201 ambient light and UV B sensor
*
* Copyright 2017 Peter Meerwald-Stadler <[email protected]>
*
* Datasheet: https://www.idt.com/document/dst/zopt2201-datasheet
* 7-bit I2C slave addresses 0x53 (default) or 0x52 (programmed)
*
* TODO: interrupt support, ALS/UVB raw mode
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <asm/unaligned.h>
#define ZOPT2201_DRV_NAME "zopt2201"
/* Registers */
#define ZOPT2201_MAIN_CTRL 0x00
#define ZOPT2201_LS_MEAS_RATE 0x04
#define ZOPT2201_LS_GAIN 0x05
#define ZOPT2201_PART_ID 0x06
#define ZOPT2201_MAIN_STATUS 0x07
#define ZOPT2201_ALS_DATA 0x0d /* LSB first, 13 to 20 bits */
#define ZOPT2201_UVB_DATA 0x10 /* LSB first, 13 to 20 bits */
#define ZOPT2201_UV_COMP_DATA 0x13 /* LSB first, 13 to 20 bits */
#define ZOPT2201_COMP_DATA 0x16 /* LSB first, 13 to 20 bits */
#define ZOPT2201_INT_CFG 0x19
#define ZOPT2201_INT_PST 0x1a
#define ZOPT2201_MAIN_CTRL_LS_MODE BIT(3) /* 0 .. ALS, 1 .. UV B */
#define ZOPT2201_MAIN_CTRL_LS_EN BIT(1)
/* Values for ZOPT2201_LS_MEAS_RATE resolution / bit width */
#define ZOPT2201_MEAS_RES_20BIT 0 /* takes 400 ms */
#define ZOPT2201_MEAS_RES_19BIT 1 /* takes 200 ms */
#define ZOPT2201_MEAS_RES_18BIT 2 /* takes 100 ms, default */
#define ZOPT2201_MEAS_RES_17BIT 3 /* takes 50 ms */
#define ZOPT2201_MEAS_RES_16BIT 4 /* takes 25 ms */
#define ZOPT2201_MEAS_RES_13BIT 5 /* takes 3.125 ms */
#define ZOPT2201_MEAS_RES_SHIFT 4
/* Values for ZOPT2201_LS_MEAS_RATE measurement rate */
#define ZOPT2201_MEAS_FREQ_25MS 0
#define ZOPT2201_MEAS_FREQ_50MS 1
#define ZOPT2201_MEAS_FREQ_100MS 2 /* default */
#define ZOPT2201_MEAS_FREQ_200MS 3
#define ZOPT2201_MEAS_FREQ_500MS 4
#define ZOPT2201_MEAS_FREQ_1000MS 5
#define ZOPT2201_MEAS_FREQ_2000MS 6
/* Values for ZOPT2201_LS_GAIN */
#define ZOPT2201_LS_GAIN_1 0
#define ZOPT2201_LS_GAIN_3 1
#define ZOPT2201_LS_GAIN_6 2
#define ZOPT2201_LS_GAIN_9 3
#define ZOPT2201_LS_GAIN_18 4
/* Values for ZOPT2201_MAIN_STATUS */
#define ZOPT2201_MAIN_STATUS_POWERON BIT(5)
#define ZOPT2201_MAIN_STATUS_INT BIT(4)
#define ZOPT2201_MAIN_STATUS_DRDY BIT(3)
#define ZOPT2201_PART_NUMBER 0xb2
struct zopt2201_data {
struct i2c_client *client;
struct mutex lock;
u8 gain;
u8 res;
u8 rate;
};
static const struct {
unsigned int gain; /* gain factor */
unsigned int scale; /* micro lux per count */
} zopt2201_gain_als[] = {
{ 1, 19200000 },
{ 3, 6400000 },
{ 6, 3200000 },
{ 9, 2133333 },
{ 18, 1066666 },
};
static const struct {
unsigned int gain; /* gain factor */
unsigned int scale; /* micro W/m2 per count */
} zopt2201_gain_uvb[] = {
{ 1, 460800 },
{ 3, 153600 },
{ 6, 76800 },
{ 9, 51200 },
{ 18, 25600 },
};
static const struct {
unsigned int bits; /* sensor resolution in bits */
unsigned long us; /* measurement time in micro seconds */
} zopt2201_resolution[] = {
{ 20, 400000 },
{ 19, 200000 },
{ 18, 100000 },
{ 17, 50000 },
{ 16, 25000 },
{ 13, 3125 },
};
static const struct {
unsigned int scale, uscale; /* scale factor as integer + micro */
u8 gain; /* gain register value */
u8 res; /* resolution register value */
} zopt2201_scale_als[] = {
{ 19, 200000, 0, 5 },
{ 6, 400000, 1, 5 },
{ 3, 200000, 2, 5 },
{ 2, 400000, 0, 4 },
{ 2, 133333, 3, 5 },
{ 1, 200000, 0, 3 },
{ 1, 66666, 4, 5 },
{ 0, 800000, 1, 4 },
{ 0, 600000, 0, 2 },
{ 0, 400000, 2, 4 },
{ 0, 300000, 0, 1 },
{ 0, 266666, 3, 4 },
{ 0, 200000, 2, 3 },
{ 0, 150000, 0, 0 },
{ 0, 133333, 4, 4 },
{ 0, 100000, 2, 2 },
{ 0, 66666, 4, 3 },
{ 0, 50000, 2, 1 },
{ 0, 33333, 4, 2 },
{ 0, 25000, 2, 0 },
{ 0, 16666, 4, 1 },
{ 0, 8333, 4, 0 },
};
static const struct {
unsigned int scale, uscale; /* scale factor as integer + micro */
u8 gain; /* gain register value */
u8 res; /* resolution register value */
} zopt2201_scale_uvb[] = {
{ 0, 460800, 0, 5 },
{ 0, 153600, 1, 5 },
{ 0, 76800, 2, 5 },
{ 0, 57600, 0, 4 },
{ 0, 51200, 3, 5 },
{ 0, 28800, 0, 3 },
{ 0, 25600, 4, 5 },
{ 0, 19200, 1, 4 },
{ 0, 14400, 0, 2 },
{ 0, 9600, 2, 4 },
{ 0, 7200, 0, 1 },
{ 0, 6400, 3, 4 },
{ 0, 4800, 2, 3 },
{ 0, 3600, 0, 0 },
{ 0, 3200, 4, 4 },
{ 0, 2400, 2, 2 },
{ 0, 1600, 4, 3 },
{ 0, 1200, 2, 1 },
{ 0, 800, 4, 2 },
{ 0, 600, 2, 0 },
{ 0, 400, 4, 1 },
{ 0, 200, 4, 0 },
};
static int zopt2201_enable_mode(struct zopt2201_data *data, bool uvb_mode)
{
u8 out = ZOPT2201_MAIN_CTRL_LS_EN;
if (uvb_mode)
out |= ZOPT2201_MAIN_CTRL_LS_MODE;
return i2c_smbus_write_byte_data(data->client, ZOPT2201_MAIN_CTRL, out);
}
static int zopt2201_read(struct zopt2201_data *data, u8 reg)
{
struct i2c_client *client = data->client;
int tries = 10;
u8 buf[3];
int ret;
mutex_lock(&data->lock);
ret = zopt2201_enable_mode(data, reg == ZOPT2201_UVB_DATA);
if (ret < 0)
goto fail;
while (tries--) {
unsigned long t = zopt2201_resolution[data->res].us;
if (t <= 20000)
usleep_range(t, t + 1000);
else
msleep(t / 1000);
ret = i2c_smbus_read_byte_data(client, ZOPT2201_MAIN_STATUS);
if (ret < 0)
goto fail;
if (ret & ZOPT2201_MAIN_STATUS_DRDY)
break;
}
if (tries < 0) {
ret = -ETIMEDOUT;
goto fail;
}
ret = i2c_smbus_read_i2c_block_data(client, reg, sizeof(buf), buf);
if (ret < 0)
goto fail;
ret = i2c_smbus_write_byte_data(client, ZOPT2201_MAIN_CTRL, 0x00);
if (ret < 0)
goto fail;
mutex_unlock(&data->lock);
return get_unaligned_le24(&buf[0]);
fail:
mutex_unlock(&data->lock);
return ret;
}
static const struct iio_chan_spec zopt2201_channels[] = {
{
.type = IIO_LIGHT,
.address = ZOPT2201_ALS_DATA,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME),
},
{
.type = IIO_INTENSITY,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_UV,
.address = ZOPT2201_UVB_DATA,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME),
},
{
.type = IIO_UVINDEX,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
},
};
static int zopt2201_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct zopt2201_data *data = iio_priv(indio_dev);
u64 tmp;
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = zopt2201_read(data, chan->address);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_PROCESSED:
ret = zopt2201_read(data, ZOPT2201_UVB_DATA);
if (ret < 0)
return ret;
*val = ret * 18 *
(1 << (20 - zopt2201_resolution[data->res].bits)) /
zopt2201_gain_uvb[data->gain].gain;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
switch (chan->address) {
case ZOPT2201_ALS_DATA:
*val = zopt2201_gain_als[data->gain].scale;
break;
case ZOPT2201_UVB_DATA:
*val = zopt2201_gain_uvb[data->gain].scale;
break;
default:
return -EINVAL;
}
*val2 = 1000000;
*val2 *= (1 << (zopt2201_resolution[data->res].bits - 13));
tmp = div_s64(*val * 1000000ULL, *val2);
*val = div_s64_rem(tmp, 1000000, val2);
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_INT_TIME:
*val = 0;
*val2 = zopt2201_resolution[data->res].us;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int zopt2201_set_resolution(struct zopt2201_data *data, u8 res)
{
int ret;
ret = i2c_smbus_write_byte_data(data->client, ZOPT2201_LS_MEAS_RATE,
(res << ZOPT2201_MEAS_RES_SHIFT) |
data->rate);
if (ret < 0)
return ret;
data->res = res;
return 0;
}
static int zopt2201_write_resolution(struct zopt2201_data *data,
int val, int val2)
{
int i, ret;
if (val != 0)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(zopt2201_resolution); i++)
if (val2 == zopt2201_resolution[i].us) {
mutex_lock(&data->lock);
ret = zopt2201_set_resolution(data, i);
mutex_unlock(&data->lock);
return ret;
}
return -EINVAL;
}
static int zopt2201_set_gain(struct zopt2201_data *data, u8 gain)
{
int ret;
ret = i2c_smbus_write_byte_data(data->client, ZOPT2201_LS_GAIN, gain);
if (ret < 0)
return ret;
data->gain = gain;
return 0;
}
static int zopt2201_write_scale_als_by_idx(struct zopt2201_data *data, int idx)
{
int ret;
mutex_lock(&data->lock);
ret = zopt2201_set_resolution(data, zopt2201_scale_als[idx].res);
if (ret < 0)
goto unlock;
ret = zopt2201_set_gain(data, zopt2201_scale_als[idx].gain);
unlock:
mutex_unlock(&data->lock);
return ret;
}
static int zopt2201_write_scale_als(struct zopt2201_data *data,
int val, int val2)
{
int i;
for (i = 0; i < ARRAY_SIZE(zopt2201_scale_als); i++)
if (val == zopt2201_scale_als[i].scale &&
val2 == zopt2201_scale_als[i].uscale) {
return zopt2201_write_scale_als_by_idx(data, i);
}
return -EINVAL;
}
static int zopt2201_write_scale_uvb_by_idx(struct zopt2201_data *data, int idx)
{
int ret;
mutex_lock(&data->lock);
ret = zopt2201_set_resolution(data, zopt2201_scale_als[idx].res);
if (ret < 0)
goto unlock;
ret = zopt2201_set_gain(data, zopt2201_scale_als[idx].gain);
unlock:
mutex_unlock(&data->lock);
return ret;
}
static int zopt2201_write_scale_uvb(struct zopt2201_data *data,
int val, int val2)
{
int i;
for (i = 0; i < ARRAY_SIZE(zopt2201_scale_uvb); i++)
if (val == zopt2201_scale_uvb[i].scale &&
val2 == zopt2201_scale_uvb[i].uscale)
return zopt2201_write_scale_uvb_by_idx(data, i);
return -EINVAL;
}
static int zopt2201_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct zopt2201_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
return zopt2201_write_resolution(data, val, val2);
case IIO_CHAN_INFO_SCALE:
switch (chan->address) {
case ZOPT2201_ALS_DATA:
return zopt2201_write_scale_als(data, val, val2);
case ZOPT2201_UVB_DATA:
return zopt2201_write_scale_uvb(data, val, val2);
default:
return -EINVAL;
}
}
return -EINVAL;
}
static ssize_t zopt2201_show_int_time_available(struct device *dev,
struct device_attribute *attr,
char *buf)
{
size_t len = 0;
int i;
for (i = 0; i < ARRAY_SIZE(zopt2201_resolution); i++)
len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06lu ",
zopt2201_resolution[i].us);
buf[len - 1] = '\n';
return len;
}
static IIO_DEV_ATTR_INT_TIME_AVAIL(zopt2201_show_int_time_available);
static ssize_t zopt2201_show_als_scale_avail(struct device *dev,
struct device_attribute *attr,
char *buf)
{
ssize_t len = 0;
int i;
for (i = 0; i < ARRAY_SIZE(zopt2201_scale_als); i++)
len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06u ",
zopt2201_scale_als[i].scale,
zopt2201_scale_als[i].uscale);
buf[len - 1] = '\n';
return len;
}
static ssize_t zopt2201_show_uvb_scale_avail(struct device *dev,
struct device_attribute *attr,
char *buf)
{
ssize_t len = 0;
int i;
for (i = 0; i < ARRAY_SIZE(zopt2201_scale_uvb); i++)
len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06u ",
zopt2201_scale_uvb[i].scale,
zopt2201_scale_uvb[i].uscale);
buf[len - 1] = '\n';
return len;
}
static IIO_DEVICE_ATTR(in_illuminance_scale_available, 0444,
zopt2201_show_als_scale_avail, NULL, 0);
static IIO_DEVICE_ATTR(in_intensity_uv_scale_available, 0444,
zopt2201_show_uvb_scale_avail, NULL, 0);
static struct attribute *zopt2201_attributes[] = {
&iio_dev_attr_integration_time_available.dev_attr.attr,
&iio_dev_attr_in_illuminance_scale_available.dev_attr.attr,
&iio_dev_attr_in_intensity_uv_scale_available.dev_attr.attr,
NULL
};
static const struct attribute_group zopt2201_attribute_group = {
.attrs = zopt2201_attributes,
};
static const struct iio_info zopt2201_info = {
.read_raw = zopt2201_read_raw,
.write_raw = zopt2201_write_raw,
.attrs = &zopt2201_attribute_group,
};
static int zopt2201_probe(struct i2c_client *client)
{
struct zopt2201_data *data;
struct iio_dev *indio_dev;
int ret;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_READ_I2C_BLOCK))
return -EOPNOTSUPP;
ret = i2c_smbus_read_byte_data(client, ZOPT2201_PART_ID);
if (ret < 0)
return ret;
if (ret != ZOPT2201_PART_NUMBER)
return -ENODEV;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
mutex_init(&data->lock);
indio_dev->info = &zopt2201_info;
indio_dev->channels = zopt2201_channels;
indio_dev->num_channels = ARRAY_SIZE(zopt2201_channels);
indio_dev->name = ZOPT2201_DRV_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
data->rate = ZOPT2201_MEAS_FREQ_100MS;
ret = zopt2201_set_resolution(data, ZOPT2201_MEAS_RES_18BIT);
if (ret < 0)
return ret;
ret = zopt2201_set_gain(data, ZOPT2201_LS_GAIN_3);
if (ret < 0)
return ret;
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id zopt2201_id[] = {
{ "zopt2201", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, zopt2201_id);
static struct i2c_driver zopt2201_driver = {
.driver = {
.name = ZOPT2201_DRV_NAME,
},
.probe = zopt2201_probe,
.id_table = zopt2201_id,
};
module_i2c_driver(zopt2201_driver);
MODULE_AUTHOR("Peter Meerwald-Stadler <[email protected]>");
MODULE_DESCRIPTION("IDT ZOPT2201 ambient light and UV B sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/zopt2201.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* These are the two Sharp GP2AP002 variants supported by this driver:
* GP2AP002A00F Ambient Light and Proximity Sensor
* GP2AP002S00F Proximity Sensor
*
* Copyright (C) 2020 Linaro Ltd.
* Author: Linus Walleij <[email protected]>
*
* Based partly on the code in Sony Ericssons GP2AP00200F driver by
* Courtney Cavin and Oskar Andero in drivers/input/misc/gp2ap002a00f.c
* Based partly on a Samsung misc driver submitted by
* Donggeun Kim & Minkyu Kang in 2011:
* https://lore.kernel.org/lkml/[email protected]/
* Based partly on a submission by
* Jonathan Bakker and Paweł Chmiel in january 2019:
* https://lore.kernel.org/linux-input/[email protected]/
* Based partly on code from the Samsung GT-S7710 by <[email protected]>
* Based partly on the code in LG Electronics GP2AP00200F driver by
* Kenobi Lee <[email protected]> and EunYoung Cho <[email protected]>
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
#include <linux/iio/consumer.h> /* To get our ADC channel */
#include <linux/iio/types.h> /* To deal with our ADC channel */
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/bits.h>
#include <linux/math64.h>
#include <linux/pm.h>
#define GP2AP002_PROX_CHANNEL 0
#define GP2AP002_ALS_CHANNEL 1
/* ------------------------------------------------------------------------ */
/* ADDRESS SYMBOL DATA Init R/W */
/* D7 D6 D5 D4 D3 D2 D1 D0 */
/* ------------------------------------------------------------------------ */
/* 0 PROX X X X X X X X VO H'00 R */
/* 1 GAIN X X X X LED0 X X X H'00 W */
/* 2 HYS HYSD HYSC1 HYSC0 X HYSF3 HYSF2 HYSF1 HYSF0 H'00 W */
/* 3 CYCLE X X CYCL2 CYCL1 CYCL0 OSC2 X X H'00 W */
/* 4 OPMOD X X X ASD X X VCON SSD H'00 W */
/* 6 CON X X X OCON1 OCON0 X X X H'00 W */
/* ------------------------------------------------------------------------ */
/* VO :Proximity sensing result(0: no detection, 1: detection) */
/* LED0 :Select switch for LED driver's On-registence(0:2x higher, 1:normal)*/
/* HYSD/HYSF :Adjusts the receiver sensitivity */
/* OSC :Select switch internal clocl frequency hoppling(0:effective) */
/* CYCL :Determine the detection cycle(typically 8ms, up to 128x) */
/* SSD :Software Shutdown function(0:shutdown, 1:operating) */
/* VCON :VOUT output method control(0:normal, 1:interrupt) */
/* ASD :Select switch for analog sleep function(0:ineffective, 1:effective)*/
/* OCON :Select switch for enabling/disabling VOUT (00:enable, 11:disable) */
#define GP2AP002_PROX 0x00
#define GP2AP002_GAIN 0x01
#define GP2AP002_HYS 0x02
#define GP2AP002_CYCLE 0x03
#define GP2AP002_OPMOD 0x04
#define GP2AP002_CON 0x06
#define GP2AP002_PROX_VO_DETECT BIT(0)
/* Setting this bit to 0 means 2x higher LED resistance */
#define GP2AP002_GAIN_LED_NORMAL BIT(3)
/*
* These bits adjusts the proximity sensitivity, determining characteristics
* of the detection distance and its hysteresis.
*/
#define GP2AP002_HYS_HYSD_SHIFT 7
#define GP2AP002_HYS_HYSD_MASK BIT(7)
#define GP2AP002_HYS_HYSC_SHIFT 5
#define GP2AP002_HYS_HYSC_MASK GENMASK(6, 5)
#define GP2AP002_HYS_HYSF_SHIFT 0
#define GP2AP002_HYS_HYSF_MASK GENMASK(3, 0)
#define GP2AP002_HYS_MASK (GP2AP002_HYS_HYSD_MASK | \
GP2AP002_HYS_HYSC_MASK | \
GP2AP002_HYS_HYSF_MASK)
/*
* These values determine the detection cycle response time
* 0: 8ms, 1: 16ms, 2: 32ms, 3: 64ms, 4: 128ms,
* 5: 256ms, 6: 512ms, 7: 1024ms
*/
#define GP2AP002_CYCLE_CYCL_SHIFT 3
#define GP2AP002_CYCLE_CYCL_MASK GENMASK(5, 3)
/*
* Select switch for internal clock frequency hopping
* 0: effective,
* 1: ineffective
*/
#define GP2AP002_CYCLE_OSC_EFFECTIVE 0
#define GP2AP002_CYCLE_OSC_INEFFECTIVE BIT(2)
#define GP2AP002_CYCLE_OSC_MASK BIT(2)
/* Analog sleep effective */
#define GP2AP002_OPMOD_ASD BIT(4)
/* Enable chip */
#define GP2AP002_OPMOD_SSD_OPERATING BIT(0)
/* IRQ mode */
#define GP2AP002_OPMOD_VCON_IRQ BIT(1)
#define GP2AP002_OPMOD_MASK (BIT(0) | BIT(1) | BIT(4))
/*
* Select switch for enabling/disabling Vout pin
* 0: enable
* 2: force to go Low
* 3: force to go High
*/
#define GP2AP002_CON_OCON_SHIFT 3
#define GP2AP002_CON_OCON_ENABLE (0x0 << GP2AP002_CON_OCON_SHIFT)
#define GP2AP002_CON_OCON_LOW (0x2 << GP2AP002_CON_OCON_SHIFT)
#define GP2AP002_CON_OCON_HIGH (0x3 << GP2AP002_CON_OCON_SHIFT)
#define GP2AP002_CON_OCON_MASK (0x3 << GP2AP002_CON_OCON_SHIFT)
/**
* struct gp2ap002 - GP2AP002 state
* @map: regmap pointer for the i2c regmap
* @dev: pointer to parent device
* @vdd: regulator controlling VDD
* @vio: regulator controlling VIO
* @alsout: IIO ADC channel to convert the ALSOUT signal
* @hys_far: hysteresis control from device tree
* @hys_close: hysteresis control from device tree
* @is_gp2ap002s00f: this is the GP2AP002F variant of the chip
* @irq: the IRQ line used by this device
* @enabled: we cannot read the status of the hardware so we need to
* keep track of whether the event is enabled using this state variable
*/
struct gp2ap002 {
struct regmap *map;
struct device *dev;
struct regulator *vdd;
struct regulator *vio;
struct iio_channel *alsout;
u8 hys_far;
u8 hys_close;
bool is_gp2ap002s00f;
int irq;
bool enabled;
};
static irqreturn_t gp2ap002_prox_irq(int irq, void *d)
{
struct iio_dev *indio_dev = d;
struct gp2ap002 *gp2ap002 = iio_priv(indio_dev);
u64 ev;
int val;
int ret;
if (!gp2ap002->enabled)
goto err_retrig;
ret = regmap_read(gp2ap002->map, GP2AP002_PROX, &val);
if (ret) {
dev_err(gp2ap002->dev, "error reading proximity\n");
goto err_retrig;
}
if (val & GP2AP002_PROX_VO_DETECT) {
/* Close */
dev_dbg(gp2ap002->dev, "close\n");
ret = regmap_write(gp2ap002->map, GP2AP002_HYS,
gp2ap002->hys_far);
if (ret)
dev_err(gp2ap002->dev,
"error setting up proximity hysteresis\n");
ev = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, GP2AP002_PROX_CHANNEL,
IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING);
} else {
/* Far */
dev_dbg(gp2ap002->dev, "far\n");
ret = regmap_write(gp2ap002->map, GP2AP002_HYS,
gp2ap002->hys_close);
if (ret)
dev_err(gp2ap002->dev,
"error setting up proximity hysteresis\n");
ev = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, GP2AP002_PROX_CHANNEL,
IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING);
}
iio_push_event(indio_dev, ev, iio_get_time_ns(indio_dev));
/*
* After changing hysteresis, we need to wait for one detection
* cycle to see if anything changed, or we will just trigger the
* previous interrupt again. A detection cycle depends on the CYCLE
* register, we are hard-coding ~8 ms in probe() so wait some more
* than this, 20-30 ms.
*/
usleep_range(20000, 30000);
err_retrig:
ret = regmap_write(gp2ap002->map, GP2AP002_CON,
GP2AP002_CON_OCON_ENABLE);
if (ret)
dev_err(gp2ap002->dev, "error setting up VOUT control\n");
return IRQ_HANDLED;
}
/*
* This array maps current and lux.
*
* Ambient light sensing range is 3 to 55000 lux.
*
* This mapping is based on the following formula.
* illuminance = 10 ^ (current[mA] / 10)
*
* When the ADC measures 0, return 0 lux.
*/
static const u16 gp2ap002_illuminance_table[] = {
0, 1, 1, 2, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 25, 32, 40, 50, 63, 79,
100, 126, 158, 200, 251, 316, 398, 501, 631, 794, 1000, 1259, 1585,
1995, 2512, 3162, 3981, 5012, 6310, 7943, 10000, 12589, 15849, 19953,
25119, 31623, 39811, 50119,
};
static int gp2ap002_get_lux(struct gp2ap002 *gp2ap002)
{
int ret, res;
u16 lux;
ret = iio_read_channel_processed(gp2ap002->alsout, &res);
if (ret < 0)
return ret;
dev_dbg(gp2ap002->dev, "read %d mA from ADC\n", res);
/* ensure we don't under/overflow */
res = clamp(res, 0, (int)ARRAY_SIZE(gp2ap002_illuminance_table) - 1);
lux = gp2ap002_illuminance_table[res];
return (int)lux;
}
static int gp2ap002_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct gp2ap002 *gp2ap002 = iio_priv(indio_dev);
int ret;
pm_runtime_get_sync(gp2ap002->dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_LIGHT:
ret = gp2ap002_get_lux(gp2ap002);
if (ret < 0)
return ret;
*val = ret;
ret = IIO_VAL_INT;
goto out;
default:
ret = -EINVAL;
goto out;
}
default:
ret = -EINVAL;
}
out:
pm_runtime_mark_last_busy(gp2ap002->dev);
pm_runtime_put_autosuspend(gp2ap002->dev);
return ret;
}
static int gp2ap002_init(struct gp2ap002 *gp2ap002)
{
int ret;
/* Set up the IR LED resistance */
ret = regmap_write(gp2ap002->map, GP2AP002_GAIN,
GP2AP002_GAIN_LED_NORMAL);
if (ret) {
dev_err(gp2ap002->dev, "error setting up LED gain\n");
return ret;
}
ret = regmap_write(gp2ap002->map, GP2AP002_HYS, gp2ap002->hys_far);
if (ret) {
dev_err(gp2ap002->dev,
"error setting up proximity hysteresis\n");
return ret;
}
/* Disable internal frequency hopping */
ret = regmap_write(gp2ap002->map, GP2AP002_CYCLE,
GP2AP002_CYCLE_OSC_INEFFECTIVE);
if (ret) {
dev_err(gp2ap002->dev,
"error setting up internal frequency hopping\n");
return ret;
}
/* Enable chip and IRQ, disable analog sleep */
ret = regmap_write(gp2ap002->map, GP2AP002_OPMOD,
GP2AP002_OPMOD_SSD_OPERATING |
GP2AP002_OPMOD_VCON_IRQ);
if (ret) {
dev_err(gp2ap002->dev, "error setting up operation mode\n");
return ret;
}
/* Interrupt on VOUT enabled */
ret = regmap_write(gp2ap002->map, GP2AP002_CON,
GP2AP002_CON_OCON_ENABLE);
if (ret)
dev_err(gp2ap002->dev, "error setting up VOUT control\n");
return ret;
}
static int gp2ap002_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct gp2ap002 *gp2ap002 = iio_priv(indio_dev);
/*
* We just keep track of this internally, as it is not possible to
* query the hardware.
*/
return gp2ap002->enabled;
}
static int gp2ap002_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
struct gp2ap002 *gp2ap002 = iio_priv(indio_dev);
if (state) {
/*
* This will bring the regulators up (unless they are on
* already) and reintialize the sensor by using runtime_pm
* callbacks.
*/
pm_runtime_get_sync(gp2ap002->dev);
gp2ap002->enabled = true;
} else {
pm_runtime_mark_last_busy(gp2ap002->dev);
pm_runtime_put_autosuspend(gp2ap002->dev);
gp2ap002->enabled = false;
}
return 0;
}
static const struct iio_info gp2ap002_info = {
.read_raw = gp2ap002_read_raw,
.read_event_config = gp2ap002_read_event_config,
.write_event_config = gp2ap002_write_event_config,
};
static const struct iio_event_spec gp2ap002_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec gp2ap002_channels[] = {
{
.type = IIO_PROXIMITY,
.event_spec = gp2ap002_events,
.num_event_specs = ARRAY_SIZE(gp2ap002_events),
},
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.channel = GP2AP002_ALS_CHANNEL,
},
};
/*
* We need a special regmap because this hardware expects to
* write single bytes to registers but read a 16bit word on some
* variants and discard the lower 8 bits so combine
* i2c_smbus_read_word_data() with i2c_smbus_write_byte_data()
* selectively like this.
*/
static int gp2ap002_regmap_i2c_read(void *context, unsigned int reg,
unsigned int *val)
{
struct device *dev = context;
struct i2c_client *i2c = to_i2c_client(dev);
int ret;
ret = i2c_smbus_read_word_data(i2c, reg);
if (ret < 0)
return ret;
*val = (ret >> 8) & 0xFF;
return 0;
}
static int gp2ap002_regmap_i2c_write(void *context, unsigned int reg,
unsigned int val)
{
struct device *dev = context;
struct i2c_client *i2c = to_i2c_client(dev);
return i2c_smbus_write_byte_data(i2c, reg, val);
}
static struct regmap_bus gp2ap002_regmap_bus = {
.reg_read = gp2ap002_regmap_i2c_read,
.reg_write = gp2ap002_regmap_i2c_write,
};
static int gp2ap002_probe(struct i2c_client *client)
{
struct gp2ap002 *gp2ap002;
struct iio_dev *indio_dev;
struct device *dev = &client->dev;
enum iio_chan_type ch_type;
static const struct regmap_config config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = GP2AP002_CON,
};
struct regmap *regmap;
int num_chan;
const char *compat;
u8 val;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*gp2ap002));
if (!indio_dev)
return -ENOMEM;
i2c_set_clientdata(client, indio_dev);
gp2ap002 = iio_priv(indio_dev);
gp2ap002->dev = dev;
/*
* Check the device compatible like this makes it possible to use
* ACPI PRP0001 for registering the sensor using device tree
* properties.
*/
ret = device_property_read_string(dev, "compatible", &compat);
if (ret) {
dev_err(dev, "cannot check compatible\n");
return ret;
}
gp2ap002->is_gp2ap002s00f = !strcmp(compat, "sharp,gp2ap002s00f");
regmap = devm_regmap_init(dev, &gp2ap002_regmap_bus, dev, &config);
if (IS_ERR(regmap)) {
dev_err(dev, "Failed to register i2c regmap %ld\n", PTR_ERR(regmap));
return PTR_ERR(regmap);
}
gp2ap002->map = regmap;
/*
* The hysteresis settings are coded into the device tree as values
* to be written into the hysteresis register. The datasheet defines
* modes "A", "B1" and "B2" with fixed values to be use but vendor
* code trees for actual devices are tweaking these values and refer to
* modes named things like "B1.5". To be able to support any devices,
* we allow passing an arbitrary hysteresis setting for "near" and
* "far".
*/
/* Check the device tree for the IR LED hysteresis */
ret = device_property_read_u8(dev, "sharp,proximity-far-hysteresis",
&val);
if (ret) {
dev_err(dev, "failed to obtain proximity far setting\n");
return ret;
}
dev_dbg(dev, "proximity far setting %02x\n", val);
gp2ap002->hys_far = val;
ret = device_property_read_u8(dev, "sharp,proximity-close-hysteresis",
&val);
if (ret) {
dev_err(dev, "failed to obtain proximity close setting\n");
return ret;
}
dev_dbg(dev, "proximity close setting %02x\n", val);
gp2ap002->hys_close = val;
/* The GP2AP002A00F has a light sensor too */
if (!gp2ap002->is_gp2ap002s00f) {
gp2ap002->alsout = devm_iio_channel_get(dev, "alsout");
if (IS_ERR(gp2ap002->alsout)) {
ret = PTR_ERR(gp2ap002->alsout);
ret = (ret == -ENODEV) ? -EPROBE_DEFER : ret;
return dev_err_probe(dev, ret, "failed to get ALSOUT ADC channel\n");
}
ret = iio_get_channel_type(gp2ap002->alsout, &ch_type);
if (ret < 0)
return ret;
if (ch_type != IIO_CURRENT) {
dev_err(dev,
"wrong type of IIO channel specified for ALSOUT\n");
return -EINVAL;
}
}
gp2ap002->vdd = devm_regulator_get(dev, "vdd");
if (IS_ERR(gp2ap002->vdd))
return dev_err_probe(dev, PTR_ERR(gp2ap002->vdd),
"failed to get VDD regulator\n");
gp2ap002->vio = devm_regulator_get(dev, "vio");
if (IS_ERR(gp2ap002->vio))
return dev_err_probe(dev, PTR_ERR(gp2ap002->vio),
"failed to get VIO regulator\n");
/* Operating voltage 2.4V .. 3.6V according to datasheet */
ret = regulator_set_voltage(gp2ap002->vdd, 2400000, 3600000);
if (ret) {
dev_err(dev, "failed to sett VDD voltage\n");
return ret;
}
/* VIO should be between 1.65V and VDD */
ret = regulator_get_voltage(gp2ap002->vdd);
if (ret < 0) {
dev_err(dev, "failed to get VDD voltage\n");
return ret;
}
ret = regulator_set_voltage(gp2ap002->vio, 1650000, ret);
if (ret) {
dev_err(dev, "failed to set VIO voltage\n");
return ret;
}
ret = regulator_enable(gp2ap002->vdd);
if (ret) {
dev_err(dev, "failed to enable VDD regulator\n");
return ret;
}
ret = regulator_enable(gp2ap002->vio);
if (ret) {
dev_err(dev, "failed to enable VIO regulator\n");
goto out_disable_vdd;
}
msleep(20);
/*
* Initialize the device and signal to runtime PM that now we are
* definitely up and using power.
*/
ret = gp2ap002_init(gp2ap002);
if (ret) {
dev_err(dev, "initialization failed\n");
goto out_disable_vio;
}
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
gp2ap002->enabled = false;
ret = devm_request_threaded_irq(dev, client->irq, NULL,
gp2ap002_prox_irq, IRQF_ONESHOT,
"gp2ap002", indio_dev);
if (ret) {
dev_err(dev, "unable to request IRQ\n");
goto out_put_pm;
}
gp2ap002->irq = client->irq;
/*
* As the device takes 20 ms + regulator delay to come up with a fresh
* measurement after power-on, do not shut it down unnecessarily.
* Set autosuspend to a one second.
*/
pm_runtime_set_autosuspend_delay(dev, 1000);
pm_runtime_use_autosuspend(dev);
pm_runtime_put(dev);
indio_dev->info = &gp2ap002_info;
indio_dev->name = "gp2ap002";
indio_dev->channels = gp2ap002_channels;
/* Skip light channel for the proximity-only sensor */
num_chan = ARRAY_SIZE(gp2ap002_channels);
if (gp2ap002->is_gp2ap002s00f)
num_chan--;
indio_dev->num_channels = num_chan;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(indio_dev);
if (ret)
goto out_disable_pm;
dev_dbg(dev, "Sharp GP2AP002 probed successfully\n");
return 0;
out_put_pm:
pm_runtime_put_noidle(dev);
out_disable_pm:
pm_runtime_disable(dev);
out_disable_vio:
regulator_disable(gp2ap002->vio);
out_disable_vdd:
regulator_disable(gp2ap002->vdd);
return ret;
}
static void gp2ap002_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct gp2ap002 *gp2ap002 = iio_priv(indio_dev);
struct device *dev = &client->dev;
pm_runtime_get_sync(dev);
pm_runtime_put_noidle(dev);
pm_runtime_disable(dev);
iio_device_unregister(indio_dev);
regulator_disable(gp2ap002->vio);
regulator_disable(gp2ap002->vdd);
}
static int gp2ap002_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct gp2ap002 *gp2ap002 = iio_priv(indio_dev);
int ret;
/* Deactivate the IRQ */
disable_irq(gp2ap002->irq);
/* Disable chip and IRQ, everything off */
ret = regmap_write(gp2ap002->map, GP2AP002_OPMOD, 0x00);
if (ret) {
dev_err(gp2ap002->dev, "error setting up operation mode\n");
return ret;
}
/*
* As these regulators may be shared, at least we are now in
* sleep even if the regulators aren't really turned off.
*/
regulator_disable(gp2ap002->vio);
regulator_disable(gp2ap002->vdd);
return 0;
}
static int gp2ap002_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct gp2ap002 *gp2ap002 = iio_priv(indio_dev);
int ret;
ret = regulator_enable(gp2ap002->vdd);
if (ret) {
dev_err(dev, "failed to enable VDD regulator in resume path\n");
return ret;
}
ret = regulator_enable(gp2ap002->vio);
if (ret) {
dev_err(dev, "failed to enable VIO regulator in resume path\n");
return ret;
}
msleep(20);
ret = gp2ap002_init(gp2ap002);
if (ret) {
dev_err(dev, "re-initialization failed\n");
return ret;
}
/* Re-activate the IRQ */
enable_irq(gp2ap002->irq);
return 0;
}
static DEFINE_RUNTIME_DEV_PM_OPS(gp2ap002_dev_pm_ops, gp2ap002_runtime_suspend,
gp2ap002_runtime_resume, NULL);
static const struct i2c_device_id gp2ap002_id_table[] = {
{ "gp2ap002", 0 },
{ },
};
MODULE_DEVICE_TABLE(i2c, gp2ap002_id_table);
static const struct of_device_id gp2ap002_of_match[] = {
{ .compatible = "sharp,gp2ap002a00f" },
{ .compatible = "sharp,gp2ap002s00f" },
{ },
};
MODULE_DEVICE_TABLE(of, gp2ap002_of_match);
static struct i2c_driver gp2ap002_driver = {
.driver = {
.name = "gp2ap002",
.of_match_table = gp2ap002_of_match,
.pm = pm_ptr(&gp2ap002_dev_pm_ops),
},
.probe = gp2ap002_probe,
.remove = gp2ap002_remove,
.id_table = gp2ap002_id_table,
};
module_i2c_driver(gp2ap002_driver);
MODULE_AUTHOR("Linus Walleij <[email protected]>");
MODULE_DESCRIPTION("GP2AP002 ambient light and proximity sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/gp2ap002.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* IIO DAC driver for Analog Devices AD8801 DAC
*
* Copyright (C) 2016 Gwenhael Goavec-Merou
*/
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/sysfs.h>
#define AD8801_CFG_ADDR_OFFSET 8
enum ad8801_device_ids {
ID_AD8801,
ID_AD8803,
};
struct ad8801_state {
struct spi_device *spi;
unsigned char dac_cache[8]; /* Value write on each channel */
unsigned int vrefh_mv;
unsigned int vrefl_mv;
struct regulator *vrefh_reg;
struct regulator *vrefl_reg;
__be16 data __aligned(IIO_DMA_MINALIGN);
};
static int ad8801_spi_write(struct ad8801_state *state,
u8 channel, unsigned char value)
{
state->data = cpu_to_be16((channel << AD8801_CFG_ADDR_OFFSET) | value);
return spi_write(state->spi, &state->data, sizeof(state->data));
}
static int ad8801_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long mask)
{
struct ad8801_state *state = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val >= 256 || val < 0)
return -EINVAL;
ret = ad8801_spi_write(state, chan->channel, val);
if (ret == 0)
state->dac_cache[chan->channel] = val;
break;
default:
ret = -EINVAL;
}
return ret;
}
static int ad8801_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long info)
{
struct ad8801_state *state = iio_priv(indio_dev);
switch (info) {
case IIO_CHAN_INFO_RAW:
*val = state->dac_cache[chan->channel];
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = state->vrefh_mv - state->vrefl_mv;
*val2 = 8;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_OFFSET:
*val = state->vrefl_mv;
return IIO_VAL_INT;
default:
return -EINVAL;
}
return -EINVAL;
}
static const struct iio_info ad8801_info = {
.read_raw = ad8801_read_raw,
.write_raw = ad8801_write_raw,
};
#define AD8801_CHANNEL(chan) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET), \
}
static const struct iio_chan_spec ad8801_channels[] = {
AD8801_CHANNEL(0),
AD8801_CHANNEL(1),
AD8801_CHANNEL(2),
AD8801_CHANNEL(3),
AD8801_CHANNEL(4),
AD8801_CHANNEL(5),
AD8801_CHANNEL(6),
AD8801_CHANNEL(7),
};
static int ad8801_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct ad8801_state *state;
const struct spi_device_id *id;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state));
if (indio_dev == NULL)
return -ENOMEM;
state = iio_priv(indio_dev);
state->spi = spi;
id = spi_get_device_id(spi);
state->vrefh_reg = devm_regulator_get(&spi->dev, "vrefh");
if (IS_ERR(state->vrefh_reg))
return dev_err_probe(&spi->dev, PTR_ERR(state->vrefh_reg),
"Vrefh regulator not specified\n");
ret = regulator_enable(state->vrefh_reg);
if (ret) {
dev_err(&spi->dev, "Failed to enable vrefh regulator: %d\n",
ret);
return ret;
}
ret = regulator_get_voltage(state->vrefh_reg);
if (ret < 0) {
dev_err(&spi->dev, "Failed to read vrefh regulator: %d\n",
ret);
goto error_disable_vrefh_reg;
}
state->vrefh_mv = ret / 1000;
if (id->driver_data == ID_AD8803) {
state->vrefl_reg = devm_regulator_get(&spi->dev, "vrefl");
if (IS_ERR(state->vrefl_reg)) {
ret = dev_err_probe(&spi->dev, PTR_ERR(state->vrefl_reg),
"Vrefl regulator not specified\n");
goto error_disable_vrefh_reg;
}
ret = regulator_enable(state->vrefl_reg);
if (ret) {
dev_err(&spi->dev, "Failed to enable vrefl regulator: %d\n",
ret);
goto error_disable_vrefh_reg;
}
ret = regulator_get_voltage(state->vrefl_reg);
if (ret < 0) {
dev_err(&spi->dev, "Failed to read vrefl regulator: %d\n",
ret);
goto error_disable_vrefl_reg;
}
state->vrefl_mv = ret / 1000;
} else {
state->vrefl_mv = 0;
state->vrefl_reg = NULL;
}
spi_set_drvdata(spi, indio_dev);
indio_dev->info = &ad8801_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ad8801_channels;
indio_dev->num_channels = ARRAY_SIZE(ad8801_channels);
indio_dev->name = id->name;
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&spi->dev, "Failed to register iio device: %d\n",
ret);
goto error_disable_vrefl_reg;
}
return 0;
error_disable_vrefl_reg:
if (state->vrefl_reg)
regulator_disable(state->vrefl_reg);
error_disable_vrefh_reg:
regulator_disable(state->vrefh_reg);
return ret;
}
static void ad8801_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ad8801_state *state = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (state->vrefl_reg)
regulator_disable(state->vrefl_reg);
regulator_disable(state->vrefh_reg);
}
static const struct spi_device_id ad8801_ids[] = {
{"ad8801", ID_AD8801},
{"ad8803", ID_AD8803},
{}
};
MODULE_DEVICE_TABLE(spi, ad8801_ids);
static struct spi_driver ad8801_driver = {
.driver = {
.name = "ad8801",
},
.probe = ad8801_probe,
.remove = ad8801_remove,
.id_table = ad8801_ids,
};
module_spi_driver(ad8801_driver);
MODULE_AUTHOR("Gwenhael Goavec-Merou <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD8801/AD8803 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad8801.c |
// SPDX-License-Identifier: GPL-2.0
/*
* AD5686R, AD5685R, AD5684R Digital to analog converters driver
*
* Copyright 2011 Analog Devices Inc.
*/
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include "ad5686.h"
static const char * const ad5686_powerdown_modes[] = {
"1kohm_to_gnd",
"100kohm_to_gnd",
"three_state"
};
static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct ad5686_state *st = iio_priv(indio_dev);
return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1;
}
static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int mode)
{
struct ad5686_state *st = iio_priv(indio_dev);
st->pwr_down_mode &= ~(0x3 << (chan->channel * 2));
st->pwr_down_mode |= ((mode + 1) << (chan->channel * 2));
return 0;
}
static const struct iio_enum ad5686_powerdown_mode_enum = {
.items = ad5686_powerdown_modes,
.num_items = ARRAY_SIZE(ad5686_powerdown_modes),
.get = ad5686_get_powerdown_mode,
.set = ad5686_set_powerdown_mode,
};
static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
struct ad5686_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", !!(st->pwr_down_mask &
(0x3 << (chan->channel * 2))));
}
static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf,
size_t len)
{
bool readin;
int ret;
struct ad5686_state *st = iio_priv(indio_dev);
unsigned int val, ref_bit_msk;
u8 shift, address = 0;
ret = kstrtobool(buf, &readin);
if (ret)
return ret;
if (readin)
st->pwr_down_mask |= (0x3 << (chan->channel * 2));
else
st->pwr_down_mask &= ~(0x3 << (chan->channel * 2));
switch (st->chip_info->regmap_type) {
case AD5310_REGMAP:
shift = 9;
ref_bit_msk = AD5310_REF_BIT_MSK;
break;
case AD5683_REGMAP:
shift = 13;
ref_bit_msk = AD5683_REF_BIT_MSK;
break;
case AD5686_REGMAP:
shift = 0;
ref_bit_msk = 0;
/* AD5674R/AD5679R have 16 channels and 2 powerdown registers */
if (chan->channel > 0x7)
address = 0x8;
break;
case AD5693_REGMAP:
shift = 13;
ref_bit_msk = AD5693_REF_BIT_MSK;
break;
default:
return -EINVAL;
}
val = ((st->pwr_down_mask & st->pwr_down_mode) << shift);
if (!st->use_internal_vref)
val |= ref_bit_msk;
ret = st->write(st, AD5686_CMD_POWERDOWN_DAC,
address, val >> (address * 2));
return ret ? ret : len;
}
static int ad5686_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct ad5686_state *st = iio_priv(indio_dev);
int ret;
switch (m) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&st->lock);
ret = st->read(st, chan->address);
mutex_unlock(&st->lock);
if (ret < 0)
return ret;
*val = (ret >> chan->scan_type.shift) &
GENMASK(chan->scan_type.realbits - 1, 0);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = st->vref_mv;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
static int ad5686_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct ad5686_state *st = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val > (1 << chan->scan_type.realbits) || val < 0)
return -EINVAL;
mutex_lock(&st->lock);
ret = st->write(st,
AD5686_CMD_WRITE_INPUT_N_UPDATE_N,
chan->address,
val << chan->scan_type.shift);
mutex_unlock(&st->lock);
break;
default:
ret = -EINVAL;
}
return ret;
}
static const struct iio_info ad5686_info = {
.read_raw = ad5686_read_raw,
.write_raw = ad5686_write_raw,
};
static const struct iio_chan_spec_ext_info ad5686_ext_info[] = {
{
.name = "powerdown",
.read = ad5686_read_dac_powerdown,
.write = ad5686_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5686_powerdown_mode_enum),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5686_powerdown_mode_enum),
{ },
};
#define AD5868_CHANNEL(chan, addr, bits, _shift) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\
.address = addr, \
.scan_type = { \
.sign = 'u', \
.realbits = (bits), \
.storagebits = 16, \
.shift = (_shift), \
}, \
.ext_info = ad5686_ext_info, \
}
#define DECLARE_AD5693_CHANNELS(name, bits, _shift) \
static const struct iio_chan_spec name[] = { \
AD5868_CHANNEL(0, 0, bits, _shift), \
}
#define DECLARE_AD5338_CHANNELS(name, bits, _shift) \
static const struct iio_chan_spec name[] = { \
AD5868_CHANNEL(0, 1, bits, _shift), \
AD5868_CHANNEL(1, 8, bits, _shift), \
}
#define DECLARE_AD5686_CHANNELS(name, bits, _shift) \
static const struct iio_chan_spec name[] = { \
AD5868_CHANNEL(0, 1, bits, _shift), \
AD5868_CHANNEL(1, 2, bits, _shift), \
AD5868_CHANNEL(2, 4, bits, _shift), \
AD5868_CHANNEL(3, 8, bits, _shift), \
}
#define DECLARE_AD5676_CHANNELS(name, bits, _shift) \
static const struct iio_chan_spec name[] = { \
AD5868_CHANNEL(0, 0, bits, _shift), \
AD5868_CHANNEL(1, 1, bits, _shift), \
AD5868_CHANNEL(2, 2, bits, _shift), \
AD5868_CHANNEL(3, 3, bits, _shift), \
AD5868_CHANNEL(4, 4, bits, _shift), \
AD5868_CHANNEL(5, 5, bits, _shift), \
AD5868_CHANNEL(6, 6, bits, _shift), \
AD5868_CHANNEL(7, 7, bits, _shift), \
}
#define DECLARE_AD5679_CHANNELS(name, bits, _shift) \
static const struct iio_chan_spec name[] = { \
AD5868_CHANNEL(0, 0, bits, _shift), \
AD5868_CHANNEL(1, 1, bits, _shift), \
AD5868_CHANNEL(2, 2, bits, _shift), \
AD5868_CHANNEL(3, 3, bits, _shift), \
AD5868_CHANNEL(4, 4, bits, _shift), \
AD5868_CHANNEL(5, 5, bits, _shift), \
AD5868_CHANNEL(6, 6, bits, _shift), \
AD5868_CHANNEL(7, 7, bits, _shift), \
AD5868_CHANNEL(8, 8, bits, _shift), \
AD5868_CHANNEL(9, 9, bits, _shift), \
AD5868_CHANNEL(10, 10, bits, _shift), \
AD5868_CHANNEL(11, 11, bits, _shift), \
AD5868_CHANNEL(12, 12, bits, _shift), \
AD5868_CHANNEL(13, 13, bits, _shift), \
AD5868_CHANNEL(14, 14, bits, _shift), \
AD5868_CHANNEL(15, 15, bits, _shift), \
}
DECLARE_AD5693_CHANNELS(ad5310r_channels, 10, 2);
DECLARE_AD5693_CHANNELS(ad5311r_channels, 10, 6);
DECLARE_AD5338_CHANNELS(ad5337r_channels, 8, 8);
DECLARE_AD5338_CHANNELS(ad5338r_channels, 10, 6);
DECLARE_AD5676_CHANNELS(ad5672_channels, 12, 4);
DECLARE_AD5679_CHANNELS(ad5674r_channels, 12, 4);
DECLARE_AD5676_CHANNELS(ad5676_channels, 16, 0);
DECLARE_AD5679_CHANNELS(ad5679r_channels, 16, 0);
DECLARE_AD5686_CHANNELS(ad5684_channels, 12, 4);
DECLARE_AD5686_CHANNELS(ad5685r_channels, 14, 2);
DECLARE_AD5686_CHANNELS(ad5686_channels, 16, 0);
DECLARE_AD5693_CHANNELS(ad5693_channels, 16, 0);
DECLARE_AD5693_CHANNELS(ad5692r_channels, 14, 2);
DECLARE_AD5693_CHANNELS(ad5691r_channels, 12, 4);
static const struct ad5686_chip_info ad5686_chip_info_tbl[] = {
[ID_AD5310R] = {
.channels = ad5310r_channels,
.int_vref_mv = 2500,
.num_channels = 1,
.regmap_type = AD5310_REGMAP,
},
[ID_AD5311R] = {
.channels = ad5311r_channels,
.int_vref_mv = 2500,
.num_channels = 1,
.regmap_type = AD5693_REGMAP,
},
[ID_AD5337R] = {
.channels = ad5337r_channels,
.int_vref_mv = 2500,
.num_channels = 2,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5338R] = {
.channels = ad5338r_channels,
.int_vref_mv = 2500,
.num_channels = 2,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5671R] = {
.channels = ad5672_channels,
.int_vref_mv = 2500,
.num_channels = 8,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5672R] = {
.channels = ad5672_channels,
.int_vref_mv = 2500,
.num_channels = 8,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5673R] = {
.channels = ad5674r_channels,
.int_vref_mv = 2500,
.num_channels = 16,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5674R] = {
.channels = ad5674r_channels,
.int_vref_mv = 2500,
.num_channels = 16,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5675R] = {
.channels = ad5676_channels,
.int_vref_mv = 2500,
.num_channels = 8,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5676] = {
.channels = ad5676_channels,
.num_channels = 8,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5676R] = {
.channels = ad5676_channels,
.int_vref_mv = 2500,
.num_channels = 8,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5677R] = {
.channels = ad5679r_channels,
.int_vref_mv = 2500,
.num_channels = 16,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5679R] = {
.channels = ad5679r_channels,
.int_vref_mv = 2500,
.num_channels = 16,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5681R] = {
.channels = ad5691r_channels,
.int_vref_mv = 2500,
.num_channels = 1,
.regmap_type = AD5683_REGMAP,
},
[ID_AD5682R] = {
.channels = ad5692r_channels,
.int_vref_mv = 2500,
.num_channels = 1,
.regmap_type = AD5683_REGMAP,
},
[ID_AD5683] = {
.channels = ad5693_channels,
.num_channels = 1,
.regmap_type = AD5683_REGMAP,
},
[ID_AD5683R] = {
.channels = ad5693_channels,
.int_vref_mv = 2500,
.num_channels = 1,
.regmap_type = AD5683_REGMAP,
},
[ID_AD5684] = {
.channels = ad5684_channels,
.num_channels = 4,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5684R] = {
.channels = ad5684_channels,
.int_vref_mv = 2500,
.num_channels = 4,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5685R] = {
.channels = ad5685r_channels,
.int_vref_mv = 2500,
.num_channels = 4,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5686] = {
.channels = ad5686_channels,
.num_channels = 4,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5686R] = {
.channels = ad5686_channels,
.int_vref_mv = 2500,
.num_channels = 4,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5691R] = {
.channels = ad5691r_channels,
.int_vref_mv = 2500,
.num_channels = 1,
.regmap_type = AD5693_REGMAP,
},
[ID_AD5692R] = {
.channels = ad5692r_channels,
.int_vref_mv = 2500,
.num_channels = 1,
.regmap_type = AD5693_REGMAP,
},
[ID_AD5693] = {
.channels = ad5693_channels,
.num_channels = 1,
.regmap_type = AD5693_REGMAP,
},
[ID_AD5693R] = {
.channels = ad5693_channels,
.int_vref_mv = 2500,
.num_channels = 1,
.regmap_type = AD5693_REGMAP,
},
[ID_AD5694] = {
.channels = ad5684_channels,
.num_channels = 4,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5694R] = {
.channels = ad5684_channels,
.int_vref_mv = 2500,
.num_channels = 4,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5696] = {
.channels = ad5686_channels,
.num_channels = 4,
.regmap_type = AD5686_REGMAP,
},
[ID_AD5696R] = {
.channels = ad5686_channels,
.int_vref_mv = 2500,
.num_channels = 4,
.regmap_type = AD5686_REGMAP,
},
};
int ad5686_probe(struct device *dev,
enum ad5686_supported_device_ids chip_type,
const char *name, ad5686_write_func write,
ad5686_read_func read)
{
struct ad5686_state *st;
struct iio_dev *indio_dev;
unsigned int val, ref_bit_msk;
u8 cmd;
int ret, i, voltage_uv = 0;
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
if (indio_dev == NULL)
return -ENOMEM;
st = iio_priv(indio_dev);
dev_set_drvdata(dev, indio_dev);
st->dev = dev;
st->write = write;
st->read = read;
st->reg = devm_regulator_get_optional(dev, "vcc");
if (!IS_ERR(st->reg)) {
ret = regulator_enable(st->reg);
if (ret)
return ret;
ret = regulator_get_voltage(st->reg);
if (ret < 0)
goto error_disable_reg;
voltage_uv = ret;
}
st->chip_info = &ad5686_chip_info_tbl[chip_type];
if (voltage_uv)
st->vref_mv = voltage_uv / 1000;
else
st->vref_mv = st->chip_info->int_vref_mv;
/* Set all the power down mode for all channels to 1K pulldown */
for (i = 0; i < st->chip_info->num_channels; i++)
st->pwr_down_mode |= (0x01 << (i * 2));
indio_dev->name = name;
indio_dev->info = &ad5686_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = st->chip_info->channels;
indio_dev->num_channels = st->chip_info->num_channels;
mutex_init(&st->lock);
switch (st->chip_info->regmap_type) {
case AD5310_REGMAP:
cmd = AD5686_CMD_CONTROL_REG;
ref_bit_msk = AD5310_REF_BIT_MSK;
st->use_internal_vref = !voltage_uv;
break;
case AD5683_REGMAP:
cmd = AD5686_CMD_CONTROL_REG;
ref_bit_msk = AD5683_REF_BIT_MSK;
st->use_internal_vref = !voltage_uv;
break;
case AD5686_REGMAP:
cmd = AD5686_CMD_INTERNAL_REFER_SETUP;
ref_bit_msk = 0;
break;
case AD5693_REGMAP:
cmd = AD5686_CMD_CONTROL_REG;
ref_bit_msk = AD5693_REF_BIT_MSK;
st->use_internal_vref = !voltage_uv;
break;
default:
ret = -EINVAL;
goto error_disable_reg;
}
val = (voltage_uv | ref_bit_msk);
ret = st->write(st, cmd, 0, !!val);
if (ret)
goto error_disable_reg;
ret = iio_device_register(indio_dev);
if (ret)
goto error_disable_reg;
return 0;
error_disable_reg:
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
return ret;
}
EXPORT_SYMBOL_NS_GPL(ad5686_probe, IIO_AD5686);
void ad5686_remove(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct ad5686_state *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
}
EXPORT_SYMBOL_NS_GPL(ad5686_remove, IIO_AD5686);
MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5686.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Analog Devices AD3552R
* Digital to Analog converter driver
*
* Copyright 2021 Analog Devices Inc.
*/
#include <asm/unaligned.h>
#include <linux/device.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
/* Register addresses */
/* Primary address space */
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_A 0x00
#define AD3552R_MASK_SOFTWARE_RESET (BIT(7) | BIT(0))
#define AD3552R_MASK_ADDR_ASCENSION BIT(5)
#define AD3552R_MASK_SDO_ACTIVE BIT(4)
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_B 0x01
#define AD3552R_MASK_SINGLE_INST BIT(7)
#define AD3552R_MASK_SHORT_INSTRUCTION BIT(3)
#define AD3552R_REG_ADDR_DEVICE_CONFIG 0x02
#define AD3552R_MASK_DEVICE_STATUS(n) BIT(4 + (n))
#define AD3552R_MASK_CUSTOM_MODES GENMASK(3, 2)
#define AD3552R_MASK_OPERATING_MODES GENMASK(1, 0)
#define AD3552R_REG_ADDR_CHIP_TYPE 0x03
#define AD3552R_MASK_CLASS GENMASK(7, 0)
#define AD3552R_REG_ADDR_PRODUCT_ID_L 0x04
#define AD3552R_REG_ADDR_PRODUCT_ID_H 0x05
#define AD3552R_REG_ADDR_CHIP_GRADE 0x06
#define AD3552R_MASK_GRADE GENMASK(7, 4)
#define AD3552R_MASK_DEVICE_REVISION GENMASK(3, 0)
#define AD3552R_REG_ADDR_SCRATCH_PAD 0x0A
#define AD3552R_REG_ADDR_SPI_REVISION 0x0B
#define AD3552R_REG_ADDR_VENDOR_L 0x0C
#define AD3552R_REG_ADDR_VENDOR_H 0x0D
#define AD3552R_REG_ADDR_STREAM_MODE 0x0E
#define AD3552R_MASK_LENGTH GENMASK(7, 0)
#define AD3552R_REG_ADDR_TRANSFER_REGISTER 0x0F
#define AD3552R_MASK_MULTI_IO_MODE GENMASK(7, 6)
#define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE BIT(2)
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_C 0x10
#define AD3552R_MASK_CRC_ENABLE (GENMASK(7, 6) |\
GENMASK(1, 0))
#define AD3552R_MASK_STRICT_REGISTER_ACCESS BIT(5)
#define AD3552R_REG_ADDR_INTERFACE_STATUS_A 0x11
#define AD3552R_MASK_INTERFACE_NOT_READY BIT(7)
#define AD3552R_MASK_CLOCK_COUNTING_ERROR BIT(5)
#define AD3552R_MASK_INVALID_OR_NO_CRC BIT(3)
#define AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER BIT(2)
#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS BIT(1)
#define AD3552R_MASK_REGISTER_ADDRESS_INVALID BIT(0)
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_D 0x14
#define AD3552R_MASK_ALERT_ENABLE_PULLUP BIT(6)
#define AD3552R_MASK_MEM_CRC_EN BIT(4)
#define AD3552R_MASK_SDO_DRIVE_STRENGTH GENMASK(3, 2)
#define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN BIT(1)
#define AD3552R_MASK_SPI_CONFIG_DDR BIT(0)
#define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG 0x15
#define AD3552R_MASK_IDUMP_FAST_MODE BIT(6)
#define AD3552R_MASK_SAMPLE_HOLD_DIFFERENTIAL_USER_EN BIT(5)
#define AD3552R_MASK_SAMPLE_HOLD_USER_TRIM GENMASK(4, 3)
#define AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE BIT(2)
#define AD3552R_MASK_REFERENCE_VOLTAGE_SEL GENMASK(1, 0)
#define AD3552R_REG_ADDR_ERR_ALARM_MASK 0x16
#define AD3552R_MASK_REF_RANGE_ALARM BIT(6)
#define AD3552R_MASK_CLOCK_COUNT_ERR_ALARM BIT(5)
#define AD3552R_MASK_MEM_CRC_ERR_ALARM BIT(4)
#define AD3552R_MASK_SPI_CRC_ERR_ALARM BIT(3)
#define AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM BIT(2)
#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM BIT(1)
#define AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM BIT(0)
#define AD3552R_REG_ADDR_ERR_STATUS 0x17
#define AD3552R_MASK_REF_RANGE_ERR_STATUS BIT(6)
#define AD3552R_MASK_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS BIT(5)
#define AD3552R_MASK_MEM_CRC_ERR_STATUS BIT(4)
#define AD3552R_MASK_RESET_STATUS BIT(0)
#define AD3552R_REG_ADDR_POWERDOWN_CONFIG 0x18
#define AD3552R_MASK_CH_DAC_POWERDOWN(ch) BIT(4 + (ch))
#define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch) BIT(ch)
#define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE 0x19
#define AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch) ((ch) ? GENMASK(7, 4) :\
GENMASK(3, 0))
#define AD3552R_REG_ADDR_CH_OFFSET(ch) (0x1B + (ch) * 2)
#define AD3552R_MASK_CH_OFFSET_BITS_0_7 GENMASK(7, 0)
#define AD3552R_REG_ADDR_CH_GAIN(ch) (0x1C + (ch) * 2)
#define AD3552R_MASK_CH_RANGE_OVERRIDE BIT(7)
#define AD3552R_MASK_CH_GAIN_SCALING_N GENMASK(6, 5)
#define AD3552R_MASK_CH_GAIN_SCALING_P GENMASK(4, 3)
#define AD3552R_MASK_CH_OFFSET_POLARITY BIT(2)
#define AD3552R_MASK_CH_OFFSET_BIT_8 BIT(0)
/*
* Secondary region
* For multibyte registers specify the highest address because the access is
* done in descending order
*/
#define AD3552R_SECONDARY_REGION_START 0x28
#define AD3552R_REG_ADDR_HW_LDAC_16B 0x28
#define AD3552R_REG_ADDR_CH_DAC_16B(ch) (0x2C - (1 - ch) * 2)
#define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B 0x2E
#define AD3552R_REG_ADDR_CH_SELECT_16B 0x2F
#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B 0x31
#define AD3552R_REG_ADDR_SW_LDAC_16B 0x32
#define AD3552R_REG_ADDR_CH_INPUT_16B(ch) (0x36 - (1 - ch) * 2)
/* 3 bytes registers */
#define AD3552R_REG_START_24B 0x37
#define AD3552R_REG_ADDR_HW_LDAC_24B 0x37
#define AD3552R_REG_ADDR_CH_DAC_24B(ch) (0x3D - (1 - ch) * 3)
#define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B 0x40
#define AD3552R_REG_ADDR_CH_SELECT_24B 0x41
#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B 0x44
#define AD3552R_REG_ADDR_SW_LDAC_24B 0x45
#define AD3552R_REG_ADDR_CH_INPUT_24B(ch) (0x4B - (1 - ch) * 3)
/* Useful defines */
#define AD3552R_NUM_CH 2
#define AD3552R_MASK_CH(ch) BIT(ch)
#define AD3552R_MASK_ALL_CH GENMASK(1, 0)
#define AD3552R_MAX_REG_SIZE 3
#define AD3552R_READ_BIT BIT(7)
#define AD3552R_ADDR_MASK GENMASK(6, 0)
#define AD3552R_MASK_DAC_12B 0xFFF0
#define AD3552R_DEFAULT_CONFIG_B_VALUE 0x8
#define AD3552R_SCRATCH_PAD_TEST_VAL1 0x34
#define AD3552R_SCRATCH_PAD_TEST_VAL2 0xB2
#define AD3552R_GAIN_SCALE 1000
#define AD3552R_LDAC_PULSE_US 100
enum ad3552r_ch_vref_select {
/* Internal source with Vref I/O floating */
AD3552R_INTERNAL_VREF_PIN_FLOATING,
/* Internal source with Vref I/O at 2.5V */
AD3552R_INTERNAL_VREF_PIN_2P5V,
/* External source with Vref I/O as input */
AD3552R_EXTERNAL_VREF_PIN_INPUT
};
enum ad3542r_id {
AD3542R_ID = 0x4008,
AD3552R_ID = 0x4009,
};
enum ad3552r_ch_output_range {
/* Range from 0 V to 2.5 V. Requires Rfb1x connection */
AD3552R_CH_OUTPUT_RANGE_0__2P5V,
/* Range from 0 V to 5 V. Requires Rfb1x connection */
AD3552R_CH_OUTPUT_RANGE_0__5V,
/* Range from 0 V to 10 V. Requires Rfb2x connection */
AD3552R_CH_OUTPUT_RANGE_0__10V,
/* Range from -5 V to 5 V. Requires Rfb2x connection */
AD3552R_CH_OUTPUT_RANGE_NEG_5__5V,
/* Range from -10 V to 10 V. Requires Rfb4x connection */
AD3552R_CH_OUTPUT_RANGE_NEG_10__10V,
};
static const s32 ad3552r_ch_ranges[][2] = {
[AD3552R_CH_OUTPUT_RANGE_0__2P5V] = {0, 2500},
[AD3552R_CH_OUTPUT_RANGE_0__5V] = {0, 5000},
[AD3552R_CH_OUTPUT_RANGE_0__10V] = {0, 10000},
[AD3552R_CH_OUTPUT_RANGE_NEG_5__5V] = {-5000, 5000},
[AD3552R_CH_OUTPUT_RANGE_NEG_10__10V] = {-10000, 10000}
};
enum ad3542r_ch_output_range {
/* Range from 0 V to 2.5 V. Requires Rfb1x connection */
AD3542R_CH_OUTPUT_RANGE_0__2P5V,
/* Range from 0 V to 3 V. Requires Rfb1x connection */
AD3542R_CH_OUTPUT_RANGE_0__3V,
/* Range from 0 V to 5 V. Requires Rfb1x connection */
AD3542R_CH_OUTPUT_RANGE_0__5V,
/* Range from 0 V to 10 V. Requires Rfb2x connection */
AD3542R_CH_OUTPUT_RANGE_0__10V,
/* Range from -2.5 V to 7.5 V. Requires Rfb2x connection */
AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V,
/* Range from -5 V to 5 V. Requires Rfb2x connection */
AD3542R_CH_OUTPUT_RANGE_NEG_5__5V,
};
static const s32 ad3542r_ch_ranges[][2] = {
[AD3542R_CH_OUTPUT_RANGE_0__2P5V] = {0, 2500},
[AD3542R_CH_OUTPUT_RANGE_0__3V] = {0, 3000},
[AD3542R_CH_OUTPUT_RANGE_0__5V] = {0, 5000},
[AD3542R_CH_OUTPUT_RANGE_0__10V] = {0, 10000},
[AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V] = {-2500, 7500},
[AD3542R_CH_OUTPUT_RANGE_NEG_5__5V] = {-5000, 5000}
};
enum ad3552r_ch_gain_scaling {
/* Gain scaling of 1 */
AD3552R_CH_GAIN_SCALING_1,
/* Gain scaling of 0.5 */
AD3552R_CH_GAIN_SCALING_0_5,
/* Gain scaling of 0.25 */
AD3552R_CH_GAIN_SCALING_0_25,
/* Gain scaling of 0.125 */
AD3552R_CH_GAIN_SCALING_0_125,
};
/* Gain * AD3552R_GAIN_SCALE */
static const s32 gains_scaling_table[] = {
[AD3552R_CH_GAIN_SCALING_1] = 1000,
[AD3552R_CH_GAIN_SCALING_0_5] = 500,
[AD3552R_CH_GAIN_SCALING_0_25] = 250,
[AD3552R_CH_GAIN_SCALING_0_125] = 125
};
enum ad3552r_dev_attributes {
/* - Direct register values */
/* From 0-3 */
AD3552R_SDO_DRIVE_STRENGTH,
/*
* 0 -> Internal Vref, vref_io pin floating (default)
* 1 -> Internal Vref, vref_io driven by internal vref
* 2 or 3 -> External Vref
*/
AD3552R_VREF_SELECT,
/* Read registers in ascending order if set. Else descending */
AD3552R_ADDR_ASCENSION,
};
enum ad3552r_ch_attributes {
/* DAC powerdown */
AD3552R_CH_DAC_POWERDOWN,
/* DAC amplifier powerdown */
AD3552R_CH_AMPLIFIER_POWERDOWN,
/* Select the output range. Select from enum ad3552r_ch_output_range */
AD3552R_CH_OUTPUT_RANGE_SEL,
/*
* Over-rider the range selector in order to manually set the output
* voltage range
*/
AD3552R_CH_RANGE_OVERRIDE,
/* Manually set the offset voltage */
AD3552R_CH_GAIN_OFFSET,
/* Sets the polarity of the offset. */
AD3552R_CH_GAIN_OFFSET_POLARITY,
/* PDAC gain scaling */
AD3552R_CH_GAIN_SCALING_P,
/* NDAC gain scaling */
AD3552R_CH_GAIN_SCALING_N,
/* Rfb value */
AD3552R_CH_RFB,
/* Channel select. When set allow Input -> DAC and Mask -> DAC */
AD3552R_CH_SELECT,
};
struct ad3552r_ch_data {
s32 scale_int;
s32 scale_dec;
s32 offset_int;
s32 offset_dec;
s16 gain_offset;
u16 rfb;
u8 n;
u8 p;
u8 range;
bool range_override;
};
struct ad3552r_desc {
/* Used to look the spi bus for atomic operations where needed */
struct mutex lock;
struct gpio_desc *gpio_reset;
struct gpio_desc *gpio_ldac;
struct spi_device *spi;
struct ad3552r_ch_data ch_data[AD3552R_NUM_CH];
struct iio_chan_spec channels[AD3552R_NUM_CH + 1];
unsigned long enabled_ch;
unsigned int num_ch;
enum ad3542r_id chip_id;
};
static const u16 addr_mask_map[][2] = {
[AD3552R_ADDR_ASCENSION] = {
AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
AD3552R_MASK_ADDR_ASCENSION
},
[AD3552R_SDO_DRIVE_STRENGTH] = {
AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
AD3552R_MASK_SDO_DRIVE_STRENGTH
},
[AD3552R_VREF_SELECT] = {
AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
AD3552R_MASK_REFERENCE_VOLTAGE_SEL
},
};
/* 0 -> reg addr, 1->ch0 mask, 2->ch1 mask */
static const u16 addr_mask_map_ch[][3] = {
[AD3552R_CH_DAC_POWERDOWN] = {
AD3552R_REG_ADDR_POWERDOWN_CONFIG,
AD3552R_MASK_CH_DAC_POWERDOWN(0),
AD3552R_MASK_CH_DAC_POWERDOWN(1)
},
[AD3552R_CH_AMPLIFIER_POWERDOWN] = {
AD3552R_REG_ADDR_POWERDOWN_CONFIG,
AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(0),
AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(1)
},
[AD3552R_CH_OUTPUT_RANGE_SEL] = {
AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,
AD3552R_MASK_CH_OUTPUT_RANGE_SEL(0),
AD3552R_MASK_CH_OUTPUT_RANGE_SEL(1)
},
[AD3552R_CH_SELECT] = {
AD3552R_REG_ADDR_CH_SELECT_16B,
AD3552R_MASK_CH(0),
AD3552R_MASK_CH(1)
}
};
static u8 _ad3552r_reg_len(u8 addr)
{
switch (addr) {
case AD3552R_REG_ADDR_HW_LDAC_16B:
case AD3552R_REG_ADDR_CH_SELECT_16B:
case AD3552R_REG_ADDR_SW_LDAC_16B:
case AD3552R_REG_ADDR_HW_LDAC_24B:
case AD3552R_REG_ADDR_CH_SELECT_24B:
case AD3552R_REG_ADDR_SW_LDAC_24B:
return 1;
default:
break;
}
if (addr > AD3552R_REG_ADDR_HW_LDAC_24B)
return 3;
if (addr > AD3552R_REG_ADDR_HW_LDAC_16B)
return 2;
return 1;
}
/* SPI transfer to device */
static int ad3552r_transfer(struct ad3552r_desc *dac, u8 addr, u32 len,
u8 *data, bool is_read)
{
/* Maximum transfer: Addr (1B) + 2 * (Data Reg (3B)) + SW LDAC(1B) */
u8 buf[8];
buf[0] = addr & AD3552R_ADDR_MASK;
buf[0] |= is_read ? AD3552R_READ_BIT : 0;
if (is_read)
return spi_write_then_read(dac->spi, buf, 1, data, len);
memcpy(buf + 1, data, len);
return spi_write_then_read(dac->spi, buf, len + 1, NULL, 0);
}
static int ad3552r_write_reg(struct ad3552r_desc *dac, u8 addr, u16 val)
{
u8 reg_len;
u8 buf[AD3552R_MAX_REG_SIZE] = { 0 };
reg_len = _ad3552r_reg_len(addr);
if (reg_len == 2)
/* Only DAC register are 2 bytes wide */
val &= AD3552R_MASK_DAC_12B;
if (reg_len == 1)
buf[0] = val & 0xFF;
else
/* reg_len can be 2 or 3, but 3rd bytes needs to be set to 0 */
put_unaligned_be16(val, buf);
return ad3552r_transfer(dac, addr, reg_len, buf, false);
}
static int ad3552r_read_reg(struct ad3552r_desc *dac, u8 addr, u16 *val)
{
int err;
u8 reg_len, buf[AD3552R_MAX_REG_SIZE] = { 0 };
reg_len = _ad3552r_reg_len(addr);
err = ad3552r_transfer(dac, addr, reg_len, buf, true);
if (err)
return err;
if (reg_len == 1)
*val = buf[0];
else
/* reg_len can be 2 or 3, but only first 2 bytes are relevant */
*val = get_unaligned_be16(buf);
return 0;
}
static u16 ad3552r_field_prep(u16 val, u16 mask)
{
return (val << __ffs(mask)) & mask;
}
/* Update field of a register, shift val if needed */
static int ad3552r_update_reg_field(struct ad3552r_desc *dac, u8 addr, u16 mask,
u16 val)
{
int ret;
u16 reg;
ret = ad3552r_read_reg(dac, addr, ®);
if (ret < 0)
return ret;
reg &= ~mask;
reg |= ad3552r_field_prep(val, mask);
return ad3552r_write_reg(dac, addr, reg);
}
static int ad3552r_set_ch_value(struct ad3552r_desc *dac,
enum ad3552r_ch_attributes attr,
u8 ch,
u16 val)
{
/* Update register related to attributes in chip */
return ad3552r_update_reg_field(dac, addr_mask_map_ch[attr][0],
addr_mask_map_ch[attr][ch + 1], val);
}
#define AD3552R_CH_DAC(_idx) ((struct iio_chan_spec) { \
.type = IIO_VOLTAGE, \
.output = true, \
.indexed = true, \
.channel = _idx, \
.scan_index = _idx, \
.scan_type = { \
.sign = 'u', \
.realbits = 16, \
.storagebits = 16, \
.endianness = IIO_BE, \
}, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_ENABLE) | \
BIT(IIO_CHAN_INFO_OFFSET), \
})
static int ad3552r_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
struct ad3552r_desc *dac = iio_priv(indio_dev);
u16 tmp_val;
int err;
u8 ch = chan->channel;
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&dac->lock);
err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_CH_DAC_24B(ch),
&tmp_val);
mutex_unlock(&dac->lock);
if (err < 0)
return err;
*val = tmp_val;
return IIO_VAL_INT;
case IIO_CHAN_INFO_ENABLE:
mutex_lock(&dac->lock);
err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG,
&tmp_val);
mutex_unlock(&dac->lock);
if (err < 0)
return err;
*val = !((tmp_val & AD3552R_MASK_CH_DAC_POWERDOWN(ch)) >>
__ffs(AD3552R_MASK_CH_DAC_POWERDOWN(ch)));
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = dac->ch_data[ch].scale_int;
*val2 = dac->ch_data[ch].scale_dec;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_OFFSET:
*val = dac->ch_data[ch].offset_int;
*val2 = dac->ch_data[ch].offset_dec;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int ad3552r_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct ad3552r_desc *dac = iio_priv(indio_dev);
int err;
mutex_lock(&dac->lock);
switch (mask) {
case IIO_CHAN_INFO_RAW:
err = ad3552r_write_reg(dac,
AD3552R_REG_ADDR_CH_DAC_24B(chan->channel),
val);
break;
case IIO_CHAN_INFO_ENABLE:
err = ad3552r_set_ch_value(dac, AD3552R_CH_DAC_POWERDOWN,
chan->channel, !val);
break;
default:
err = -EINVAL;
break;
}
mutex_unlock(&dac->lock);
return err;
}
static const struct iio_info ad3552r_iio_info = {
.read_raw = ad3552r_read_raw,
.write_raw = ad3552r_write_raw
};
static int32_t ad3552r_trigger_hw_ldac(struct gpio_desc *ldac)
{
gpiod_set_value_cansleep(ldac, 0);
usleep_range(AD3552R_LDAC_PULSE_US, AD3552R_LDAC_PULSE_US + 10);
gpiod_set_value_cansleep(ldac, 1);
return 0;
}
static int ad3552r_write_all_channels(struct ad3552r_desc *dac, u8 *data)
{
int err, len;
u8 addr, buff[AD3552R_NUM_CH * AD3552R_MAX_REG_SIZE + 1];
addr = AD3552R_REG_ADDR_CH_INPUT_24B(1);
/* CH1 */
memcpy(buff, data + 2, 2);
buff[2] = 0;
/* CH0 */
memcpy(buff + 3, data, 2);
buff[5] = 0;
len = 6;
if (!dac->gpio_ldac) {
/* Software LDAC */
buff[6] = AD3552R_MASK_ALL_CH;
++len;
}
err = ad3552r_transfer(dac, addr, len, buff, false);
if (err)
return err;
if (dac->gpio_ldac)
return ad3552r_trigger_hw_ldac(dac->gpio_ldac);
return 0;
}
static int ad3552r_write_codes(struct ad3552r_desc *dac, u32 mask, u8 *data)
{
int err;
u8 addr, buff[AD3552R_MAX_REG_SIZE];
if (mask == AD3552R_MASK_ALL_CH) {
if (memcmp(data, data + 2, 2) != 0)
return ad3552r_write_all_channels(dac, data);
addr = AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B;
} else {
addr = AD3552R_REG_ADDR_CH_INPUT_24B(__ffs(mask));
}
memcpy(buff, data, 2);
buff[2] = 0;
err = ad3552r_transfer(dac, addr, 3, data, false);
if (err)
return err;
if (dac->gpio_ldac)
return ad3552r_trigger_hw_ldac(dac->gpio_ldac);
return ad3552r_write_reg(dac, AD3552R_REG_ADDR_SW_LDAC_24B, mask);
}
static irqreturn_t ad3552r_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct iio_buffer *buf = indio_dev->buffer;
struct ad3552r_desc *dac = iio_priv(indio_dev);
/* Maximum size of a scan */
u8 buff[AD3552R_NUM_CH * AD3552R_MAX_REG_SIZE];
int err;
memset(buff, 0, sizeof(buff));
err = iio_pop_from_buffer(buf, buff);
if (err)
goto end;
mutex_lock(&dac->lock);
ad3552r_write_codes(dac, *indio_dev->active_scan_mask, buff);
mutex_unlock(&dac->lock);
end:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int ad3552r_check_scratch_pad(struct ad3552r_desc *dac)
{
const u16 val1 = AD3552R_SCRATCH_PAD_TEST_VAL1;
const u16 val2 = AD3552R_SCRATCH_PAD_TEST_VAL2;
u16 val;
int err;
err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val1);
if (err < 0)
return err;
err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);
if (err < 0)
return err;
if (val1 != val)
return -ENODEV;
err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val2);
if (err < 0)
return err;
err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);
if (err < 0)
return err;
if (val2 != val)
return -ENODEV;
return 0;
}
struct reg_addr_pool {
struct ad3552r_desc *dac;
u8 addr;
};
static int ad3552r_read_reg_wrapper(struct reg_addr_pool *addr)
{
int err;
u16 val;
err = ad3552r_read_reg(addr->dac, addr->addr, &val);
if (err)
return err;
return val;
}
static int ad3552r_reset(struct ad3552r_desc *dac)
{
struct reg_addr_pool addr;
int ret;
int val;
dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(dac->gpio_reset))
return dev_err_probe(&dac->spi->dev, PTR_ERR(dac->gpio_reset),
"Error while getting gpio reset");
if (dac->gpio_reset) {
/* Perform hardware reset */
usleep_range(10, 20);
gpiod_set_value_cansleep(dac->gpio_reset, 1);
} else {
/* Perform software reset if no GPIO provided */
ret = ad3552r_update_reg_field(dac,
AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
AD3552R_MASK_SOFTWARE_RESET,
AD3552R_MASK_SOFTWARE_RESET);
if (ret < 0)
return ret;
}
addr.dac = dac;
addr.addr = AD3552R_REG_ADDR_INTERFACE_CONFIG_B;
ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
val == AD3552R_DEFAULT_CONFIG_B_VALUE ||
val < 0,
5000, 50000);
if (val < 0)
ret = val;
if (ret) {
dev_err(&dac->spi->dev, "Error while resetting");
return ret;
}
ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
!(val & AD3552R_MASK_INTERFACE_NOT_READY) ||
val < 0,
5000, 50000);
if (val < 0)
ret = val;
if (ret) {
dev_err(&dac->spi->dev, "Error while resetting");
return ret;
}
return ad3552r_update_reg_field(dac,
addr_mask_map[AD3552R_ADDR_ASCENSION][0],
addr_mask_map[AD3552R_ADDR_ASCENSION][1],
val);
}
static void ad3552r_get_custom_range(struct ad3552r_desc *dac, s32 i, s32 *v_min,
s32 *v_max)
{
s64 vref, tmp, common, offset, gn, gp;
/*
* From datasheet formula (In Volts):
* Vmin = 2.5 + [(GainN + Offset / 1024) * 2.5 * Rfb * 1.03]
* Vmax = 2.5 - [(GainP + Offset / 1024) * 2.5 * Rfb * 1.03]
* Calculus are converted to milivolts
*/
vref = 2500;
/* 2.5 * 1.03 * 1000 (To mV) */
common = 2575 * dac->ch_data[i].rfb;
offset = dac->ch_data[i].gain_offset;
gn = gains_scaling_table[dac->ch_data[i].n];
tmp = (1024 * gn + AD3552R_GAIN_SCALE * offset) * common;
tmp = div_s64(tmp, 1024 * AD3552R_GAIN_SCALE);
*v_max = vref + tmp;
gp = gains_scaling_table[dac->ch_data[i].p];
tmp = (1024 * gp - AD3552R_GAIN_SCALE * offset) * common;
tmp = div_s64(tmp, 1024 * AD3552R_GAIN_SCALE);
*v_min = vref - tmp;
}
static void ad3552r_calc_gain_and_offset(struct ad3552r_desc *dac, s32 ch)
{
s32 idx, v_max, v_min, span, rem;
s64 tmp;
if (dac->ch_data[ch].range_override) {
ad3552r_get_custom_range(dac, ch, &v_min, &v_max);
} else {
/* Normal range */
idx = dac->ch_data[ch].range;
if (dac->chip_id == AD3542R_ID) {
v_min = ad3542r_ch_ranges[idx][0];
v_max = ad3542r_ch_ranges[idx][1];
} else {
v_min = ad3552r_ch_ranges[idx][0];
v_max = ad3552r_ch_ranges[idx][1];
}
}
/*
* From datasheet formula:
* Vout = Span * (D / 65536) + Vmin
* Converted to scale and offset:
* Scale = Span / 65536
* Offset = 65536 * Vmin / Span
*
* Reminders are in micros in order to be printed as
* IIO_VAL_INT_PLUS_MICRO
*/
span = v_max - v_min;
dac->ch_data[ch].scale_int = div_s64_rem(span, 65536, &rem);
/* Do operations in microvolts */
dac->ch_data[ch].scale_dec = DIV_ROUND_CLOSEST((s64)rem * 1000000,
65536);
dac->ch_data[ch].offset_int = div_s64_rem(v_min * 65536, span, &rem);
tmp = (s64)rem * 1000000;
dac->ch_data[ch].offset_dec = div_s64(tmp, span);
}
static int ad3552r_find_range(u16 id, s32 *vals)
{
int i, len;
const s32 (*ranges)[2];
if (id == AD3542R_ID) {
len = ARRAY_SIZE(ad3542r_ch_ranges);
ranges = ad3542r_ch_ranges;
} else {
len = ARRAY_SIZE(ad3552r_ch_ranges);
ranges = ad3552r_ch_ranges;
}
for (i = 0; i < len; i++)
if (vals[0] == ranges[i][0] * 1000 &&
vals[1] == ranges[i][1] * 1000)
return i;
return -EINVAL;
}
static int ad3552r_configure_custom_gain(struct ad3552r_desc *dac,
struct fwnode_handle *child,
u32 ch)
{
struct device *dev = &dac->spi->dev;
struct fwnode_handle *gain_child;
u32 val;
int err;
u8 addr;
u16 reg = 0, offset;
gain_child = fwnode_get_named_child_node(child,
"custom-output-range-config");
if (!gain_child) {
dev_err(dev,
"mandatory custom-output-range-config property missing\n");
return -EINVAL;
}
dac->ch_data[ch].range_override = 1;
reg |= ad3552r_field_prep(1, AD3552R_MASK_CH_RANGE_OVERRIDE);
err = fwnode_property_read_u32(gain_child, "adi,gain-scaling-p", &val);
if (err) {
dev_err(dev, "mandatory adi,gain-scaling-p property missing\n");
goto put_child;
}
reg |= ad3552r_field_prep(val, AD3552R_MASK_CH_GAIN_SCALING_P);
dac->ch_data[ch].p = val;
err = fwnode_property_read_u32(gain_child, "adi,gain-scaling-n", &val);
if (err) {
dev_err(dev, "mandatory adi,gain-scaling-n property missing\n");
goto put_child;
}
reg |= ad3552r_field_prep(val, AD3552R_MASK_CH_GAIN_SCALING_N);
dac->ch_data[ch].n = val;
err = fwnode_property_read_u32(gain_child, "adi,rfb-ohms", &val);
if (err) {
dev_err(dev, "mandatory adi,rfb-ohms property missing\n");
goto put_child;
}
dac->ch_data[ch].rfb = val;
err = fwnode_property_read_u32(gain_child, "adi,gain-offset", &val);
if (err) {
dev_err(dev, "mandatory adi,gain-offset property missing\n");
goto put_child;
}
dac->ch_data[ch].gain_offset = val;
offset = abs((s32)val);
reg |= ad3552r_field_prep((offset >> 8), AD3552R_MASK_CH_OFFSET_BIT_8);
reg |= ad3552r_field_prep((s32)val < 0, AD3552R_MASK_CH_OFFSET_POLARITY);
addr = AD3552R_REG_ADDR_CH_GAIN(ch);
err = ad3552r_write_reg(dac, addr,
offset & AD3552R_MASK_CH_OFFSET_BITS_0_7);
if (err) {
dev_err(dev, "Error writing register\n");
goto put_child;
}
err = ad3552r_write_reg(dac, addr, reg);
if (err) {
dev_err(dev, "Error writing register\n");
goto put_child;
}
put_child:
fwnode_handle_put(gain_child);
return err;
}
static void ad3552r_reg_disable(void *reg)
{
regulator_disable(reg);
}
static int ad3552r_configure_device(struct ad3552r_desc *dac)
{
struct device *dev = &dac->spi->dev;
struct fwnode_handle *child;
struct regulator *vref;
int err, cnt = 0, voltage, delta = 100000;
u32 vals[2], val, ch;
dac->gpio_ldac = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH);
if (IS_ERR(dac->gpio_ldac))
return dev_err_probe(dev, PTR_ERR(dac->gpio_ldac),
"Error getting gpio ldac");
vref = devm_regulator_get_optional(dev, "vref");
if (IS_ERR(vref)) {
if (PTR_ERR(vref) != -ENODEV)
return dev_err_probe(dev, PTR_ERR(vref),
"Error getting vref");
if (device_property_read_bool(dev, "adi,vref-out-en"))
val = AD3552R_INTERNAL_VREF_PIN_2P5V;
else
val = AD3552R_INTERNAL_VREF_PIN_FLOATING;
} else {
err = regulator_enable(vref);
if (err) {
dev_err(dev, "Failed to enable external vref supply\n");
return err;
}
err = devm_add_action_or_reset(dev, ad3552r_reg_disable, vref);
if (err) {
regulator_disable(vref);
return err;
}
voltage = regulator_get_voltage(vref);
if (voltage > 2500000 + delta || voltage < 2500000 - delta) {
dev_warn(dev, "vref-supply must be 2.5V");
return -EINVAL;
}
val = AD3552R_EXTERNAL_VREF_PIN_INPUT;
}
err = ad3552r_update_reg_field(dac,
addr_mask_map[AD3552R_VREF_SELECT][0],
addr_mask_map[AD3552R_VREF_SELECT][1],
val);
if (err)
return err;
err = device_property_read_u32(dev, "adi,sdo-drive-strength", &val);
if (!err) {
if (val > 3) {
dev_err(dev, "adi,sdo-drive-strength must be less than 4\n");
return -EINVAL;
}
err = ad3552r_update_reg_field(dac,
addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][0],
addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][1],
val);
if (err)
return err;
}
dac->num_ch = device_get_child_node_count(dev);
if (!dac->num_ch) {
dev_err(dev, "No channels defined\n");
return -ENODEV;
}
device_for_each_child_node(dev, child) {
err = fwnode_property_read_u32(child, "reg", &ch);
if (err) {
dev_err(dev, "mandatory reg property missing\n");
goto put_child;
}
if (ch >= AD3552R_NUM_CH) {
dev_err(dev, "reg must be less than %d\n",
AD3552R_NUM_CH);
err = -EINVAL;
goto put_child;
}
if (fwnode_property_present(child, "adi,output-range-microvolt")) {
err = fwnode_property_read_u32_array(child,
"adi,output-range-microvolt",
vals,
2);
if (err) {
dev_err(dev,
"adi,output-range-microvolt property could not be parsed\n");
goto put_child;
}
err = ad3552r_find_range(dac->chip_id, vals);
if (err < 0) {
dev_err(dev,
"Invalid adi,output-range-microvolt value\n");
goto put_child;
}
val = err;
err = ad3552r_set_ch_value(dac,
AD3552R_CH_OUTPUT_RANGE_SEL,
ch, val);
if (err)
goto put_child;
dac->ch_data[ch].range = val;
} else if (dac->chip_id == AD3542R_ID) {
dev_err(dev,
"adi,output-range-microvolt is required for ad3542r\n");
err = -EINVAL;
goto put_child;
} else {
err = ad3552r_configure_custom_gain(dac, child, ch);
if (err)
goto put_child;
}
ad3552r_calc_gain_and_offset(dac, ch);
dac->enabled_ch |= BIT(ch);
err = ad3552r_set_ch_value(dac, AD3552R_CH_SELECT, ch, 1);
if (err < 0)
goto put_child;
dac->channels[cnt] = AD3552R_CH_DAC(ch);
++cnt;
}
/* Disable unused channels */
for_each_clear_bit(ch, &dac->enabled_ch, AD3552R_NUM_CH) {
err = ad3552r_set_ch_value(dac, AD3552R_CH_AMPLIFIER_POWERDOWN,
ch, 1);
if (err)
return err;
}
dac->num_ch = cnt;
return 0;
put_child:
fwnode_handle_put(child);
return err;
}
static int ad3552r_init(struct ad3552r_desc *dac)
{
int err;
u16 val, id;
err = ad3552r_reset(dac);
if (err) {
dev_err(&dac->spi->dev, "Reset failed\n");
return err;
}
err = ad3552r_check_scratch_pad(dac);
if (err) {
dev_err(&dac->spi->dev, "Scratch pad test failed\n");
return err;
}
err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_L, &val);
if (err) {
dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_L\n");
return err;
}
id = val;
err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_H, &val);
if (err) {
dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_H\n");
return err;
}
id |= val << 8;
if (id != dac->chip_id) {
dev_err(&dac->spi->dev, "Product id not matching\n");
return -ENODEV;
}
return ad3552r_configure_device(dac);
}
static int ad3552r_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct ad3552r_desc *dac;
struct iio_dev *indio_dev;
int err;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*dac));
if (!indio_dev)
return -ENOMEM;
dac = iio_priv(indio_dev);
dac->spi = spi;
dac->chip_id = id->driver_data;
mutex_init(&dac->lock);
err = ad3552r_init(dac);
if (err)
return err;
/* Config triggered buffer device */
if (dac->chip_id == AD3552R_ID)
indio_dev->name = "ad3552r";
else
indio_dev->name = "ad3542r";
indio_dev->dev.parent = &spi->dev;
indio_dev->info = &ad3552r_iio_info;
indio_dev->num_channels = dac->num_ch;
indio_dev->channels = dac->channels;
indio_dev->modes = INDIO_DIRECT_MODE;
err = devm_iio_triggered_buffer_setup_ext(&indio_dev->dev, indio_dev, NULL,
&ad3552r_trigger_handler,
IIO_BUFFER_DIRECTION_OUT,
NULL,
NULL);
if (err)
return err;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id ad3552r_id[] = {
{ "ad3542r", AD3542R_ID },
{ "ad3552r", AD3552R_ID },
{ }
};
MODULE_DEVICE_TABLE(spi, ad3552r_id);
static const struct of_device_id ad3552r_of_match[] = {
{ .compatible = "adi,ad3542r"},
{ .compatible = "adi,ad3552r"},
{ }
};
MODULE_DEVICE_TABLE(of, ad3552r_of_match);
static struct spi_driver ad3552r_driver = {
.driver = {
.name = "ad3552r",
.of_match_table = ad3552r_of_match,
},
.probe = ad3552r_probe,
.id_table = ad3552r_id
};
module_spi_driver(ad3552r_driver);
MODULE_AUTHOR("Mihail Chindris <[email protected]>");
MODULE_DESCRIPTION("Analog Device AD3552R DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad3552r.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD5504, AD5501 High Voltage Digital to Analog Converter
*
* Copyright 2011 Analog Devices Inc.
*/
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
#include <linux/iio/dac/ad5504.h>
#define AD5504_RES_MASK GENMASK(11, 0)
#define AD5504_CMD_READ BIT(15)
#define AD5504_CMD_WRITE 0
#define AD5504_ADDR(addr) ((addr) << 12)
/* Registers */
#define AD5504_ADDR_NOOP 0
#define AD5504_ADDR_DAC(x) ((x) + 1)
#define AD5504_ADDR_ALL_DAC 5
#define AD5504_ADDR_CTRL 7
/* Control Register */
#define AD5504_DAC_PWR(ch) ((ch) << 2)
#define AD5504_DAC_PWRDWN_MODE(mode) ((mode) << 6)
#define AD5504_DAC_PWRDN_20K 0
#define AD5504_DAC_PWRDN_3STATE 1
/**
* struct ad5504_state - driver instance specific data
* @spi: spi_device
* @reg: supply regulator
* @vref_mv: actual reference voltage used
* @pwr_down_mask: power down mask
* @pwr_down_mode: current power down mode
* @data: transfer buffer
*/
struct ad5504_state {
struct spi_device *spi;
struct regulator *reg;
unsigned short vref_mv;
unsigned pwr_down_mask;
unsigned pwr_down_mode;
__be16 data[2] __aligned(IIO_DMA_MINALIGN);
};
/*
* ad5504_supported_device_ids:
*/
enum ad5504_supported_device_ids {
ID_AD5504,
ID_AD5501,
};
static int ad5504_spi_write(struct ad5504_state *st, u8 addr, u16 val)
{
st->data[0] = cpu_to_be16(AD5504_CMD_WRITE | AD5504_ADDR(addr) |
(val & AD5504_RES_MASK));
return spi_write(st->spi, &st->data[0], 2);
}
static int ad5504_spi_read(struct ad5504_state *st, u8 addr)
{
int ret;
struct spi_transfer t = {
.tx_buf = &st->data[0],
.rx_buf = &st->data[1],
.len = 2,
};
st->data[0] = cpu_to_be16(AD5504_CMD_READ | AD5504_ADDR(addr));
ret = spi_sync_transfer(st->spi, &t, 1);
if (ret < 0)
return ret;
return be16_to_cpu(st->data[1]) & AD5504_RES_MASK;
}
static int ad5504_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct ad5504_state *st = iio_priv(indio_dev);
int ret;
switch (m) {
case IIO_CHAN_INFO_RAW:
ret = ad5504_spi_read(st, chan->address);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = st->vref_mv;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
static int ad5504_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct ad5504_state *st = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val >= (1 << chan->scan_type.realbits) || val < 0)
return -EINVAL;
return ad5504_spi_write(st, chan->address, val);
default:
return -EINVAL;
}
}
static const char * const ad5504_powerdown_modes[] = {
"20kohm_to_gnd",
"three_state",
};
static int ad5504_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct ad5504_state *st = iio_priv(indio_dev);
return st->pwr_down_mode;
}
static int ad5504_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, unsigned int mode)
{
struct ad5504_state *st = iio_priv(indio_dev);
st->pwr_down_mode = mode;
return 0;
}
static const struct iio_enum ad5504_powerdown_mode_enum = {
.items = ad5504_powerdown_modes,
.num_items = ARRAY_SIZE(ad5504_powerdown_modes),
.get = ad5504_get_powerdown_mode,
.set = ad5504_set_powerdown_mode,
};
static ssize_t ad5504_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
struct ad5504_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n",
!(st->pwr_down_mask & (1 << chan->channel)));
}
static ssize_t ad5504_write_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
size_t len)
{
bool pwr_down;
int ret;
struct ad5504_state *st = iio_priv(indio_dev);
ret = kstrtobool(buf, &pwr_down);
if (ret)
return ret;
if (pwr_down)
st->pwr_down_mask &= ~(1 << chan->channel);
else
st->pwr_down_mask |= (1 << chan->channel);
ret = ad5504_spi_write(st, AD5504_ADDR_CTRL,
AD5504_DAC_PWRDWN_MODE(st->pwr_down_mode) |
AD5504_DAC_PWR(st->pwr_down_mask));
/* writes to the CTRL register must be followed by a NOOP */
ad5504_spi_write(st, AD5504_ADDR_NOOP, 0);
return ret ? ret : len;
}
static IIO_CONST_ATTR(temp0_thresh_rising_value, "110000");
static IIO_CONST_ATTR(temp0_thresh_rising_en, "1");
static struct attribute *ad5504_ev_attributes[] = {
&iio_const_attr_temp0_thresh_rising_value.dev_attr.attr,
&iio_const_attr_temp0_thresh_rising_en.dev_attr.attr,
NULL,
};
static const struct attribute_group ad5504_ev_attribute_group = {
.attrs = ad5504_ev_attributes,
};
static irqreturn_t ad5504_event_handler(int irq, void *private)
{
iio_push_event(private,
IIO_UNMOD_EVENT_CODE(IIO_TEMP,
0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
iio_get_time_ns(private));
return IRQ_HANDLED;
}
static const struct iio_info ad5504_info = {
.write_raw = ad5504_write_raw,
.read_raw = ad5504_read_raw,
.event_attrs = &ad5504_ev_attribute_group,
};
static const struct iio_chan_spec_ext_info ad5504_ext_info[] = {
{
.name = "powerdown",
.read = ad5504_read_dac_powerdown,
.write = ad5504_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE,
&ad5504_powerdown_mode_enum),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5504_powerdown_mode_enum),
{ },
};
#define AD5504_CHANNEL(_chan) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (_chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.address = AD5504_ADDR_DAC(_chan), \
.scan_type = { \
.sign = 'u', \
.realbits = 12, \
.storagebits = 16, \
}, \
.ext_info = ad5504_ext_info, \
}
static const struct iio_chan_spec ad5504_channels[] = {
AD5504_CHANNEL(0),
AD5504_CHANNEL(1),
AD5504_CHANNEL(2),
AD5504_CHANNEL(3),
};
static int ad5504_probe(struct spi_device *spi)
{
struct ad5504_platform_data *pdata = spi->dev.platform_data;
struct iio_dev *indio_dev;
struct ad5504_state *st;
struct regulator *reg;
int ret, voltage_uv = 0;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
reg = devm_regulator_get(&spi->dev, "vcc");
if (!IS_ERR(reg)) {
ret = regulator_enable(reg);
if (ret)
return ret;
ret = regulator_get_voltage(reg);
if (ret < 0)
goto error_disable_reg;
voltage_uv = ret;
}
spi_set_drvdata(spi, indio_dev);
st = iio_priv(indio_dev);
if (voltage_uv)
st->vref_mv = voltage_uv / 1000;
else if (pdata)
st->vref_mv = pdata->vref_mv;
else
dev_warn(&spi->dev, "reference voltage unspecified\n");
st->reg = reg;
st->spi = spi;
indio_dev->name = spi_get_device_id(st->spi)->name;
indio_dev->info = &ad5504_info;
if (spi_get_device_id(st->spi)->driver_data == ID_AD5501)
indio_dev->num_channels = 1;
else
indio_dev->num_channels = 4;
indio_dev->channels = ad5504_channels;
indio_dev->modes = INDIO_DIRECT_MODE;
if (spi->irq) {
ret = devm_request_threaded_irq(&spi->dev, spi->irq,
NULL,
&ad5504_event_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
spi_get_device_id(st->spi)->name,
indio_dev);
if (ret)
goto error_disable_reg;
}
ret = iio_device_register(indio_dev);
if (ret)
goto error_disable_reg;
return 0;
error_disable_reg:
if (!IS_ERR(reg))
regulator_disable(reg);
return ret;
}
static void ad5504_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ad5504_state *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
}
static const struct spi_device_id ad5504_id[] = {
{"ad5504", ID_AD5504},
{"ad5501", ID_AD5501},
{}
};
MODULE_DEVICE_TABLE(spi, ad5504_id);
static struct spi_driver ad5504_driver = {
.driver = {
.name = "ad5504",
},
.probe = ad5504_probe,
.remove = ad5504_remove,
.id_table = ad5504_id,
};
module_spi_driver(ad5504_driver);
MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5501/AD5501 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5504.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* mcp4922.c
*
* Driver for Microchip Digital to Analog Converters.
* Supports MCP4902, MCP4912, and MCP4922.
*
* Copyright (c) 2014 EMAC Inc.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/bitops.h>
#define MCP4922_NUM_CHANNELS 2
#define MCP4921_NUM_CHANNELS 1
enum mcp4922_supported_device_ids {
ID_MCP4902,
ID_MCP4912,
ID_MCP4921,
ID_MCP4922,
};
struct mcp4922_state {
struct spi_device *spi;
unsigned int value[MCP4922_NUM_CHANNELS];
unsigned int vref_mv;
struct regulator *vref_reg;
u8 mosi[2] __aligned(IIO_DMA_MINALIGN);
};
#define MCP4922_CHAN(chan, bits) { \
.type = IIO_VOLTAGE, \
.output = 1, \
.indexed = 1, \
.channel = chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.scan_type = { \
.sign = 'u', \
.realbits = (bits), \
.storagebits = 16, \
.shift = 12 - (bits), \
}, \
}
static int mcp4922_spi_write(struct mcp4922_state *state, u8 addr, u32 val)
{
state->mosi[1] = val & 0xff;
state->mosi[0] = (addr == 0) ? 0x00 : 0x80;
state->mosi[0] |= 0x30 | ((val >> 8) & 0x0f);
return spi_write(state->spi, state->mosi, 2);
}
static int mcp4922_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
struct mcp4922_state *state = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
*val = state->value[chan->channel];
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = state->vref_mv;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
}
static int mcp4922_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct mcp4922_state *state = iio_priv(indio_dev);
int ret;
if (val2 != 0)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))
return -EINVAL;
val <<= chan->scan_type.shift;
ret = mcp4922_spi_write(state, chan->channel, val);
if (!ret)
state->value[chan->channel] = val;
return ret;
default:
return -EINVAL;
}
}
static const struct iio_chan_spec mcp4922_channels[4][MCP4922_NUM_CHANNELS] = {
[ID_MCP4902] = { MCP4922_CHAN(0, 8), MCP4922_CHAN(1, 8) },
[ID_MCP4912] = { MCP4922_CHAN(0, 10), MCP4922_CHAN(1, 10) },
[ID_MCP4921] = { MCP4922_CHAN(0, 12), {} },
[ID_MCP4922] = { MCP4922_CHAN(0, 12), MCP4922_CHAN(1, 12) },
};
static const struct iio_info mcp4922_info = {
.read_raw = &mcp4922_read_raw,
.write_raw = &mcp4922_write_raw,
};
static int mcp4922_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct mcp4922_state *state;
const struct spi_device_id *id;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state));
if (indio_dev == NULL)
return -ENOMEM;
state = iio_priv(indio_dev);
state->spi = spi;
state->vref_reg = devm_regulator_get(&spi->dev, "vref");
if (IS_ERR(state->vref_reg))
return dev_err_probe(&spi->dev, PTR_ERR(state->vref_reg),
"Vref regulator not specified\n");
ret = regulator_enable(state->vref_reg);
if (ret) {
dev_err(&spi->dev, "Failed to enable vref regulator: %d\n",
ret);
return ret;
}
ret = regulator_get_voltage(state->vref_reg);
if (ret < 0) {
dev_err(&spi->dev, "Failed to read vref regulator: %d\n",
ret);
goto error_disable_reg;
}
state->vref_mv = ret / 1000;
spi_set_drvdata(spi, indio_dev);
id = spi_get_device_id(spi);
indio_dev->info = &mcp4922_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = mcp4922_channels[id->driver_data];
if (id->driver_data == ID_MCP4921)
indio_dev->num_channels = MCP4921_NUM_CHANNELS;
else
indio_dev->num_channels = MCP4922_NUM_CHANNELS;
indio_dev->name = id->name;
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&spi->dev, "Failed to register iio device: %d\n",
ret);
goto error_disable_reg;
}
return 0;
error_disable_reg:
regulator_disable(state->vref_reg);
return ret;
}
static void mcp4922_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct mcp4922_state *state;
iio_device_unregister(indio_dev);
state = iio_priv(indio_dev);
regulator_disable(state->vref_reg);
}
static const struct spi_device_id mcp4922_id[] = {
{"mcp4902", ID_MCP4902},
{"mcp4912", ID_MCP4912},
{"mcp4921", ID_MCP4921},
{"mcp4922", ID_MCP4922},
{}
};
MODULE_DEVICE_TABLE(spi, mcp4922_id);
static struct spi_driver mcp4922_driver = {
.driver = {
.name = "mcp4922",
},
.probe = mcp4922_probe,
.remove = mcp4922_remove,
.id_table = mcp4922_id,
};
module_spi_driver(mcp4922_driver);
MODULE_AUTHOR("Michael Welling <[email protected]>");
MODULE_DESCRIPTION("Microchip MCP4902, MCP4912, MCP4922 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/mcp4922.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD5721, AD5721R, AD5761, AD5761R, Voltage Output Digital to Analog Converter
*
* Copyright 2016 Qtechnology A/S
* 2016 Ricardo Ribalda <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <linux/bitops.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/platform_data/ad5761.h>
#define AD5761_ADDR(addr) ((addr & 0xf) << 16)
#define AD5761_ADDR_NOOP 0x0
#define AD5761_ADDR_DAC_WRITE 0x3
#define AD5761_ADDR_CTRL_WRITE_REG 0x4
#define AD5761_ADDR_SW_DATA_RESET 0x7
#define AD5761_ADDR_DAC_READ 0xb
#define AD5761_ADDR_CTRL_READ_REG 0xc
#define AD5761_ADDR_SW_FULL_RESET 0xf
#define AD5761_CTRL_USE_INTVREF BIT(5)
#define AD5761_CTRL_ETS BIT(6)
/**
* struct ad5761_chip_info - chip specific information
* @int_vref: Value of the internal reference voltage in mV - 0 if external
* reference voltage is used
* @channel: channel specification
*/
struct ad5761_chip_info {
unsigned long int_vref;
const struct iio_chan_spec channel;
};
struct ad5761_range_params {
int m;
int c;
};
enum ad5761_supported_device_ids {
ID_AD5721,
ID_AD5721R,
ID_AD5761,
ID_AD5761R,
};
/**
* struct ad5761_state - driver instance specific data
* @spi: spi_device
* @vref_reg: reference voltage regulator
* @use_intref: true when the internal voltage reference is used
* @vref: actual voltage reference in mVolts
* @range: output range mode used
* @lock: lock to protect the data buffer during SPI ops
* @data: cache aligned spi buffer
*/
struct ad5761_state {
struct spi_device *spi;
struct regulator *vref_reg;
struct mutex lock;
bool use_intref;
int vref;
enum ad5761_voltage_range range;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
union {
__be32 d32;
u8 d8[4];
} data[3] __aligned(IIO_DMA_MINALIGN);
};
static const struct ad5761_range_params ad5761_range_params[] = {
[AD5761_VOLTAGE_RANGE_M10V_10V] = {
.m = 80,
.c = 40,
},
[AD5761_VOLTAGE_RANGE_0V_10V] = {
.m = 40,
.c = 0,
},
[AD5761_VOLTAGE_RANGE_M5V_5V] = {
.m = 40,
.c = 20,
},
[AD5761_VOLTAGE_RANGE_0V_5V] = {
.m = 20,
.c = 0,
},
[AD5761_VOLTAGE_RANGE_M2V5_7V5] = {
.m = 40,
.c = 10,
},
[AD5761_VOLTAGE_RANGE_M3V_3V] = {
.m = 24,
.c = 12,
},
[AD5761_VOLTAGE_RANGE_0V_16V] = {
.m = 64,
.c = 0,
},
[AD5761_VOLTAGE_RANGE_0V_20V] = {
.m = 80,
.c = 0,
},
};
static int _ad5761_spi_write(struct ad5761_state *st, u8 addr, u16 val)
{
st->data[0].d32 = cpu_to_be32(AD5761_ADDR(addr) | val);
return spi_write(st->spi, &st->data[0].d8[1], 3);
}
static int ad5761_spi_write(struct iio_dev *indio_dev, u8 addr, u16 val)
{
struct ad5761_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
ret = _ad5761_spi_write(st, addr, val);
mutex_unlock(&st->lock);
return ret;
}
static int _ad5761_spi_read(struct ad5761_state *st, u8 addr, u16 *val)
{
int ret;
struct spi_transfer xfers[] = {
{
.tx_buf = &st->data[0].d8[1],
.bits_per_word = 8,
.len = 3,
.cs_change = true,
}, {
.tx_buf = &st->data[1].d8[1],
.rx_buf = &st->data[2].d8[1],
.bits_per_word = 8,
.len = 3,
},
};
st->data[0].d32 = cpu_to_be32(AD5761_ADDR(addr));
st->data[1].d32 = cpu_to_be32(AD5761_ADDR(AD5761_ADDR_NOOP));
ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
*val = be32_to_cpu(st->data[2].d32);
return ret;
}
static int ad5761_spi_read(struct iio_dev *indio_dev, u8 addr, u16 *val)
{
struct ad5761_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
ret = _ad5761_spi_read(st, addr, val);
mutex_unlock(&st->lock);
return ret;
}
static int ad5761_spi_set_range(struct ad5761_state *st,
enum ad5761_voltage_range range)
{
u16 aux;
int ret;
aux = (range & 0x7) | AD5761_CTRL_ETS;
if (st->use_intref)
aux |= AD5761_CTRL_USE_INTVREF;
ret = _ad5761_spi_write(st, AD5761_ADDR_SW_FULL_RESET, 0);
if (ret)
return ret;
ret = _ad5761_spi_write(st, AD5761_ADDR_CTRL_WRITE_REG, aux);
if (ret)
return ret;
st->range = range;
return 0;
}
static int ad5761_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
struct ad5761_state *st;
int ret;
u16 aux;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = ad5761_spi_read(indio_dev, AD5761_ADDR_DAC_READ, &aux);
if (ret)
return ret;
*val = aux >> chan->scan_type.shift;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
st = iio_priv(indio_dev);
*val = st->vref * ad5761_range_params[st->range].m;
*val /= 10;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_OFFSET:
st = iio_priv(indio_dev);
*val = -(1 << chan->scan_type.realbits);
*val *= ad5761_range_params[st->range].c;
*val /= ad5761_range_params[st->range].m;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int ad5761_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
u16 aux;
if (mask != IIO_CHAN_INFO_RAW)
return -EINVAL;
if (val2 || (val << chan->scan_type.shift) > 0xffff || val < 0)
return -EINVAL;
aux = val << chan->scan_type.shift;
return ad5761_spi_write(indio_dev, AD5761_ADDR_DAC_WRITE, aux);
}
static const struct iio_info ad5761_info = {
.read_raw = &ad5761_read_raw,
.write_raw = &ad5761_write_raw,
};
#define AD5761_CHAN(_bits) { \
.type = IIO_VOLTAGE, \
.output = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET), \
.scan_type = { \
.sign = 'u', \
.realbits = (_bits), \
.storagebits = 16, \
.shift = 16 - (_bits), \
}, \
}
static const struct ad5761_chip_info ad5761_chip_infos[] = {
[ID_AD5721] = {
.int_vref = 0,
.channel = AD5761_CHAN(12),
},
[ID_AD5721R] = {
.int_vref = 2500,
.channel = AD5761_CHAN(12),
},
[ID_AD5761] = {
.int_vref = 0,
.channel = AD5761_CHAN(16),
},
[ID_AD5761R] = {
.int_vref = 2500,
.channel = AD5761_CHAN(16),
},
};
static int ad5761_get_vref(struct ad5761_state *st,
const struct ad5761_chip_info *chip_info)
{
int ret;
st->vref_reg = devm_regulator_get_optional(&st->spi->dev, "vref");
if (PTR_ERR(st->vref_reg) == -ENODEV) {
/* Use Internal regulator */
if (!chip_info->int_vref) {
dev_err(&st->spi->dev,
"Voltage reference not found\n");
return -EIO;
}
st->use_intref = true;
st->vref = chip_info->int_vref;
return 0;
}
if (IS_ERR(st->vref_reg)) {
dev_err(&st->spi->dev,
"Error getting voltage reference regulator\n");
return PTR_ERR(st->vref_reg);
}
ret = regulator_enable(st->vref_reg);
if (ret) {
dev_err(&st->spi->dev,
"Failed to enable voltage reference\n");
return ret;
}
ret = regulator_get_voltage(st->vref_reg);
if (ret < 0) {
dev_err(&st->spi->dev,
"Failed to get voltage reference value\n");
goto disable_regulator_vref;
}
if (ret < 2000000 || ret > 3000000) {
dev_warn(&st->spi->dev,
"Invalid external voltage ref. value %d uV\n", ret);
ret = -EIO;
goto disable_regulator_vref;
}
st->vref = ret / 1000;
st->use_intref = false;
return 0;
disable_regulator_vref:
regulator_disable(st->vref_reg);
st->vref_reg = NULL;
return ret;
}
static int ad5761_probe(struct spi_device *spi)
{
struct iio_dev *iio_dev;
struct ad5761_state *st;
int ret;
const struct ad5761_chip_info *chip_info =
&ad5761_chip_infos[spi_get_device_id(spi)->driver_data];
enum ad5761_voltage_range voltage_range = AD5761_VOLTAGE_RANGE_0V_5V;
struct ad5761_platform_data *pdata = dev_get_platdata(&spi->dev);
iio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!iio_dev)
return -ENOMEM;
st = iio_priv(iio_dev);
st->spi = spi;
spi_set_drvdata(spi, iio_dev);
ret = ad5761_get_vref(st, chip_info);
if (ret)
return ret;
if (pdata)
voltage_range = pdata->voltage_range;
mutex_init(&st->lock);
ret = ad5761_spi_set_range(st, voltage_range);
if (ret)
goto disable_regulator_err;
iio_dev->info = &ad5761_info;
iio_dev->modes = INDIO_DIRECT_MODE;
iio_dev->channels = &chip_info->channel;
iio_dev->num_channels = 1;
iio_dev->name = spi_get_device_id(st->spi)->name;
ret = iio_device_register(iio_dev);
if (ret)
goto disable_regulator_err;
return 0;
disable_regulator_err:
if (!IS_ERR_OR_NULL(st->vref_reg))
regulator_disable(st->vref_reg);
return ret;
}
static void ad5761_remove(struct spi_device *spi)
{
struct iio_dev *iio_dev = spi_get_drvdata(spi);
struct ad5761_state *st = iio_priv(iio_dev);
iio_device_unregister(iio_dev);
if (!IS_ERR_OR_NULL(st->vref_reg))
regulator_disable(st->vref_reg);
}
static const struct spi_device_id ad5761_id[] = {
{"ad5721", ID_AD5721},
{"ad5721r", ID_AD5721R},
{"ad5761", ID_AD5761},
{"ad5761r", ID_AD5761R},
{}
};
MODULE_DEVICE_TABLE(spi, ad5761_id);
static struct spi_driver ad5761_driver = {
.driver = {
.name = "ad5761",
},
.probe = ad5761_probe,
.remove = ad5761_remove,
.id_table = ad5761_id,
};
module_spi_driver(ad5761_driver);
MODULE_AUTHOR("Ricardo Ribalda <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5721, AD5721R, AD5761, AD5761R driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5761.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD5421 Digital to analog converters driver
*
* Copyright 2011 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
#include <linux/iio/dac/ad5421.h>
#define AD5421_REG_DAC_DATA 0x1
#define AD5421_REG_CTRL 0x2
#define AD5421_REG_OFFSET 0x3
#define AD5421_REG_GAIN 0x4
/* load dac and fault shared the same register number. Writing to it will cause
* a dac load command, reading from it will return the fault status register */
#define AD5421_REG_LOAD_DAC 0x5
#define AD5421_REG_FAULT 0x5
#define AD5421_REG_FORCE_ALARM_CURRENT 0x6
#define AD5421_REG_RESET 0x7
#define AD5421_REG_START_CONVERSION 0x8
#define AD5421_REG_NOOP 0x9
#define AD5421_CTRL_WATCHDOG_DISABLE BIT(12)
#define AD5421_CTRL_AUTO_FAULT_READBACK BIT(11)
#define AD5421_CTRL_MIN_CURRENT BIT(9)
#define AD5421_CTRL_ADC_SOURCE_TEMP BIT(8)
#define AD5421_CTRL_ADC_ENABLE BIT(7)
#define AD5421_CTRL_PWR_DOWN_INT_VREF BIT(6)
#define AD5421_FAULT_SPI BIT(15)
#define AD5421_FAULT_PEC BIT(14)
#define AD5421_FAULT_OVER_CURRENT BIT(13)
#define AD5421_FAULT_UNDER_CURRENT BIT(12)
#define AD5421_FAULT_TEMP_OVER_140 BIT(11)
#define AD5421_FAULT_TEMP_OVER_100 BIT(10)
#define AD5421_FAULT_UNDER_VOLTAGE_6V BIT(9)
#define AD5421_FAULT_UNDER_VOLTAGE_12V BIT(8)
/* These bits will cause the fault pin to go high */
#define AD5421_FAULT_TRIGGER_IRQ \
(AD5421_FAULT_SPI | AD5421_FAULT_PEC | AD5421_FAULT_OVER_CURRENT | \
AD5421_FAULT_UNDER_CURRENT | AD5421_FAULT_TEMP_OVER_140)
/**
* struct ad5421_state - driver instance specific data
* @spi: spi_device
* @ctrl: control register cache
* @current_range: current range which the device is configured for
* @data: spi transfer buffers
* @fault_mask: software masking of events
* @lock: lock to protect the data buffer during SPI ops
*/
struct ad5421_state {
struct spi_device *spi;
unsigned int ctrl;
enum ad5421_current_range current_range;
unsigned int fault_mask;
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
union {
__be32 d32;
u8 d8[4];
} data[2] __aligned(IIO_DMA_MINALIGN);
};
static const struct iio_event_spec ad5421_current_event[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_event_spec ad5421_temp_event[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec ad5421_channels[] = {
{
.type = IIO_CURRENT,
.indexed = 1,
.output = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET),
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
},
.event_spec = ad5421_current_event,
.num_event_specs = ARRAY_SIZE(ad5421_current_event),
},
{
.type = IIO_TEMP,
.channel = -1,
.event_spec = ad5421_temp_event,
.num_event_specs = ARRAY_SIZE(ad5421_temp_event),
},
};
static int ad5421_write_unlocked(struct iio_dev *indio_dev,
unsigned int reg, unsigned int val)
{
struct ad5421_state *st = iio_priv(indio_dev);
st->data[0].d32 = cpu_to_be32((reg << 16) | val);
return spi_write(st->spi, &st->data[0].d8[1], 3);
}
static int ad5421_write(struct iio_dev *indio_dev, unsigned int reg,
unsigned int val)
{
struct ad5421_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
ret = ad5421_write_unlocked(indio_dev, reg, val);
mutex_unlock(&st->lock);
return ret;
}
static int ad5421_read(struct iio_dev *indio_dev, unsigned int reg)
{
struct ad5421_state *st = iio_priv(indio_dev);
int ret;
struct spi_transfer t[] = {
{
.tx_buf = &st->data[0].d8[1],
.len = 3,
.cs_change = 1,
}, {
.rx_buf = &st->data[1].d8[1],
.len = 3,
},
};
mutex_lock(&st->lock);
st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));
ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
if (ret >= 0)
ret = be32_to_cpu(st->data[1].d32) & 0xffff;
mutex_unlock(&st->lock);
return ret;
}
static int ad5421_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
unsigned int clr)
{
struct ad5421_state *st = iio_priv(indio_dev);
unsigned int ret;
mutex_lock(&st->lock);
st->ctrl &= ~clr;
st->ctrl |= set;
ret = ad5421_write_unlocked(indio_dev, AD5421_REG_CTRL, st->ctrl);
mutex_unlock(&st->lock);
return ret;
}
static irqreturn_t ad5421_fault_handler(int irq, void *data)
{
struct iio_dev *indio_dev = data;
struct ad5421_state *st = iio_priv(indio_dev);
unsigned int fault;
unsigned int old_fault = 0;
unsigned int events;
fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
if (!fault)
return IRQ_NONE;
/* If we had a fault, this might mean that the DAC has lost its state
* and has been reset. Make sure that the control register actually
* contains what we expect it to contain. Otherwise the watchdog might
* be enabled and we get watchdog timeout faults, which will render the
* DAC unusable. */
ad5421_update_ctrl(indio_dev, 0, 0);
/* The fault pin stays high as long as a fault condition is present and
* it is not possible to mask fault conditions. For certain fault
* conditions for example like over-temperature it takes some time
* until the fault condition disappears. If we would exit the interrupt
* handler immediately after handling the event it would be entered
* again instantly. Thus we fall back to polling in case we detect that
* a interrupt condition is still present.
*/
do {
/* 0xffff is a invalid value for the register and will only be
* read if there has been a communication error */
if (fault == 0xffff)
fault = 0;
/* we are only interested in new events */
events = (old_fault ^ fault) & fault;
events &= st->fault_mask;
if (events & AD5421_FAULT_OVER_CURRENT) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
}
if (events & AD5421_FAULT_UNDER_CURRENT) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
iio_get_time_ns(indio_dev));
}
if (events & AD5421_FAULT_TEMP_OVER_140) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_TEMP,
0,
IIO_EV_TYPE_MAG,
IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
}
old_fault = fault;
fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
/* still active? go to sleep for some time */
if (fault & AD5421_FAULT_TRIGGER_IRQ)
msleep(1000);
} while (fault & AD5421_FAULT_TRIGGER_IRQ);
return IRQ_HANDLED;
}
static void ad5421_get_current_min_max(struct ad5421_state *st,
unsigned int *min, unsigned int *max)
{
/* The current range is configured using external pins, which are
* usually hard-wired and not run-time switchable. */
switch (st->current_range) {
case AD5421_CURRENT_RANGE_4mA_20mA:
*min = 4000;
*max = 20000;
break;
case AD5421_CURRENT_RANGE_3mA8_21mA:
*min = 3800;
*max = 21000;
break;
case AD5421_CURRENT_RANGE_3mA2_24mA:
*min = 3200;
*max = 24000;
break;
default:
*min = 0;
*max = 1;
break;
}
}
static inline unsigned int ad5421_get_offset(struct ad5421_state *st)
{
unsigned int min, max;
ad5421_get_current_min_max(st, &min, &max);
return (min * (1 << 16)) / (max - min);
}
static int ad5421_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long m)
{
struct ad5421_state *st = iio_priv(indio_dev);
unsigned int min, max;
int ret;
if (chan->type != IIO_CURRENT)
return -EINVAL;
switch (m) {
case IIO_CHAN_INFO_RAW:
ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ad5421_get_current_min_max(st, &min, &max);
*val = max - min;
*val2 = (1 << 16) * 1000;
return IIO_VAL_FRACTIONAL;
case IIO_CHAN_INFO_OFFSET:
*val = ad5421_get_offset(st);
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBBIAS:
ret = ad5421_read(indio_dev, AD5421_REG_OFFSET);
if (ret < 0)
return ret;
*val = ret - 32768;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBSCALE:
ret = ad5421_read(indio_dev, AD5421_REG_GAIN);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
}
return -EINVAL;
}
static int ad5421_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long mask)
{
const unsigned int max_val = 1 << 16;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val >= max_val || val < 0)
return -EINVAL;
return ad5421_write(indio_dev, AD5421_REG_DAC_DATA, val);
case IIO_CHAN_INFO_CALIBBIAS:
val += 32768;
if (val >= max_val || val < 0)
return -EINVAL;
return ad5421_write(indio_dev, AD5421_REG_OFFSET, val);
case IIO_CHAN_INFO_CALIBSCALE:
if (val >= max_val || val < 0)
return -EINVAL;
return ad5421_write(indio_dev, AD5421_REG_GAIN, val);
default:
break;
}
return -EINVAL;
}
static int ad5421_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct ad5421_state *st = iio_priv(indio_dev);
unsigned int mask;
switch (chan->type) {
case IIO_CURRENT:
if (dir == IIO_EV_DIR_RISING)
mask = AD5421_FAULT_OVER_CURRENT;
else
mask = AD5421_FAULT_UNDER_CURRENT;
break;
case IIO_TEMP:
mask = AD5421_FAULT_TEMP_OVER_140;
break;
default:
return -EINVAL;
}
mutex_lock(&st->lock);
if (state)
st->fault_mask |= mask;
else
st->fault_mask &= ~mask;
mutex_unlock(&st->lock);
return 0;
}
static int ad5421_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir)
{
struct ad5421_state *st = iio_priv(indio_dev);
unsigned int mask;
switch (chan->type) {
case IIO_CURRENT:
if (dir == IIO_EV_DIR_RISING)
mask = AD5421_FAULT_OVER_CURRENT;
else
mask = AD5421_FAULT_UNDER_CURRENT;
break;
case IIO_TEMP:
mask = AD5421_FAULT_TEMP_OVER_140;
break;
default:
return -EINVAL;
}
return (bool)(st->fault_mask & mask);
}
static int ad5421_read_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info, int *val,
int *val2)
{
int ret;
switch (chan->type) {
case IIO_CURRENT:
ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
if (ret < 0)
return ret;
*val = ret;
break;
case IIO_TEMP:
*val = 140000;
break;
default:
return -EINVAL;
}
return IIO_VAL_INT;
}
static const struct iio_info ad5421_info = {
.read_raw = ad5421_read_raw,
.write_raw = ad5421_write_raw,
.read_event_config = ad5421_read_event_config,
.write_event_config = ad5421_write_event_config,
.read_event_value = ad5421_read_event_value,
};
static int ad5421_probe(struct spi_device *spi)
{
struct ad5421_platform_data *pdata = dev_get_platdata(&spi->dev);
struct iio_dev *indio_dev;
struct ad5421_state *st;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (indio_dev == NULL) {
dev_err(&spi->dev, "Failed to allocate iio device\n");
return -ENOMEM;
}
st = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
st->spi = spi;
indio_dev->name = "ad5421";
indio_dev->info = &ad5421_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ad5421_channels;
indio_dev->num_channels = ARRAY_SIZE(ad5421_channels);
mutex_init(&st->lock);
st->ctrl = AD5421_CTRL_WATCHDOG_DISABLE |
AD5421_CTRL_AUTO_FAULT_READBACK;
if (pdata) {
st->current_range = pdata->current_range;
if (pdata->external_vref)
st->ctrl |= AD5421_CTRL_PWR_DOWN_INT_VREF;
} else {
st->current_range = AD5421_CURRENT_RANGE_4mA_20mA;
}
/* write initial ctrl register value */
ad5421_update_ctrl(indio_dev, 0, 0);
if (spi->irq) {
ret = devm_request_threaded_irq(&spi->dev, spi->irq,
NULL,
ad5421_fault_handler,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
"ad5421 fault",
indio_dev);
if (ret)
return ret;
}
return devm_iio_device_register(&spi->dev, indio_dev);
}
static struct spi_driver ad5421_driver = {
.driver = {
.name = "ad5421",
},
.probe = ad5421_probe,
};
module_spi_driver(ad5421_driver);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5421 DAC");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("spi:ad5421");
| linux-master | drivers/iio/dac/ad5421.c |
// SPDX-License-Identifier: GPL-2.0
/* ti-dac7311.c - Texas Instruments 8/10/12-bit 1-channel DAC driver
*
* Copyright (C) 2018 CMC NV
*
* https://www.ti.com/lit/ds/symlink/dac7311.pdf
*/
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
enum {
ID_DAC5311 = 0,
ID_DAC6311,
ID_DAC7311,
};
enum {
POWER_1KOHM_TO_GND = 0,
POWER_100KOHM_TO_GND,
POWER_TRI_STATE,
};
struct ti_dac_spec {
u8 resolution;
};
static const struct ti_dac_spec ti_dac_spec[] = {
[ID_DAC5311] = { .resolution = 8 },
[ID_DAC6311] = { .resolution = 10 },
[ID_DAC7311] = { .resolution = 12 },
};
/**
* struct ti_dac_chip - TI DAC chip
* @lock: protects write sequences
* @vref: regulator generating Vref
* @spi: SPI device to send data to the device
* @val: cached value
* @powerdown: whether the chip is powered down
* @powerdown_mode: selected by the user
* @resolution: resolution of the chip
* @buf: buffer for transfer data
*/
struct ti_dac_chip {
struct mutex lock;
struct regulator *vref;
struct spi_device *spi;
u16 val;
bool powerdown;
u8 powerdown_mode;
u8 resolution;
u8 buf[2] __aligned(IIO_DMA_MINALIGN);
};
static u8 ti_dac_get_power(struct ti_dac_chip *ti_dac, bool powerdown)
{
if (powerdown)
return ti_dac->powerdown_mode + 1;
return 0;
}
static int ti_dac_cmd(struct ti_dac_chip *ti_dac, u8 power, u16 val)
{
u8 shift = 14 - ti_dac->resolution;
ti_dac->buf[0] = (val << shift) & 0xFF;
ti_dac->buf[1] = (power << 6) | (val >> (8 - shift));
return spi_write(ti_dac->spi, ti_dac->buf, 2);
}
static const char * const ti_dac_powerdown_modes[] = {
"1kohm_to_gnd",
"100kohm_to_gnd",
"three_state",
};
static int ti_dac_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
return ti_dac->powerdown_mode;
}
static int ti_dac_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int mode)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
ti_dac->powerdown_mode = mode;
return 0;
}
static const struct iio_enum ti_dac_powerdown_mode = {
.items = ti_dac_powerdown_modes,
.num_items = ARRAY_SIZE(ti_dac_powerdown_modes),
.get = ti_dac_get_powerdown_mode,
.set = ti_dac_set_powerdown_mode,
};
static ssize_t ti_dac_read_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", ti_dac->powerdown);
}
static ssize_t ti_dac_write_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
bool powerdown;
u8 power;
int ret;
ret = kstrtobool(buf, &powerdown);
if (ret)
return ret;
power = ti_dac_get_power(ti_dac, powerdown);
mutex_lock(&ti_dac->lock);
ret = ti_dac_cmd(ti_dac, power, 0);
if (!ret)
ti_dac->powerdown = powerdown;
mutex_unlock(&ti_dac->lock);
return ret ? ret : len;
}
static const struct iio_chan_spec_ext_info ti_dac_ext_info[] = {
{
.name = "powerdown",
.read = ti_dac_read_powerdown,
.write = ti_dac_write_powerdown,
.shared = IIO_SHARED_BY_TYPE,
},
IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE, &ti_dac_powerdown_mode),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ti_dac_powerdown_mode),
{ },
};
#define TI_DAC_CHANNEL(chan) { \
.type = IIO_VOLTAGE, \
.channel = (chan), \
.output = true, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.ext_info = ti_dac_ext_info, \
}
static const struct iio_chan_spec ti_dac_channels[] = {
TI_DAC_CHANNEL(0),
};
static int ti_dac_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
*val = ti_dac->val;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = regulator_get_voltage(ti_dac->vref);
if (ret < 0)
return ret;
*val = ret / 1000;
*val2 = ti_dac->resolution;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
static int ti_dac_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
u8 power = ti_dac_get_power(ti_dac, ti_dac->powerdown);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (ti_dac->val == val)
return 0;
if (val >= (1 << ti_dac->resolution) || val < 0)
return -EINVAL;
if (ti_dac->powerdown)
return -EBUSY;
mutex_lock(&ti_dac->lock);
ret = ti_dac_cmd(ti_dac, power, val);
if (!ret)
ti_dac->val = val;
mutex_unlock(&ti_dac->lock);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int ti_dac_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, long mask)
{
return IIO_VAL_INT;
}
static const struct iio_info ti_dac_info = {
.read_raw = ti_dac_read_raw,
.write_raw = ti_dac_write_raw,
.write_raw_get_fmt = ti_dac_write_raw_get_fmt,
};
static int ti_dac_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
const struct ti_dac_spec *spec;
struct ti_dac_chip *ti_dac;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*ti_dac));
if (!indio_dev) {
dev_err(dev, "can not allocate iio device\n");
return -ENOMEM;
}
spi->mode = SPI_MODE_1;
spi->bits_per_word = 16;
spi_setup(spi);
indio_dev->info = &ti_dac_info;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ti_dac_channels;
spi_set_drvdata(spi, indio_dev);
ti_dac = iio_priv(indio_dev);
ti_dac->powerdown = false;
ti_dac->spi = spi;
spec = &ti_dac_spec[spi_get_device_id(spi)->driver_data];
indio_dev->num_channels = 1;
ti_dac->resolution = spec->resolution;
ti_dac->vref = devm_regulator_get(dev, "vref");
if (IS_ERR(ti_dac->vref))
return dev_err_probe(dev, PTR_ERR(ti_dac->vref),
"error to get regulator\n");
ret = regulator_enable(ti_dac->vref);
if (ret < 0) {
dev_err(dev, "can not enable regulator\n");
return ret;
}
mutex_init(&ti_dac->lock);
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(dev, "fail to register iio device: %d\n", ret);
goto err;
}
return 0;
err:
mutex_destroy(&ti_dac->lock);
regulator_disable(ti_dac->vref);
return ret;
}
static void ti_dac_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
mutex_destroy(&ti_dac->lock);
regulator_disable(ti_dac->vref);
}
static const struct of_device_id ti_dac_of_id[] = {
{ .compatible = "ti,dac5311" },
{ .compatible = "ti,dac6311" },
{ .compatible = "ti,dac7311" },
{ }
};
MODULE_DEVICE_TABLE(of, ti_dac_of_id);
static const struct spi_device_id ti_dac_spi_id[] = {
{ "dac5311", ID_DAC5311 },
{ "dac6311", ID_DAC6311 },
{ "dac7311", ID_DAC7311 },
{ }
};
MODULE_DEVICE_TABLE(spi, ti_dac_spi_id);
static struct spi_driver ti_dac_driver = {
.driver = {
.name = "ti-dac7311",
.of_match_table = ti_dac_of_id,
},
.probe = ti_dac_probe,
.remove = ti_dac_remove,
.id_table = ti_dac_spi_id,
};
module_spi_driver(ti_dac_driver);
MODULE_AUTHOR("Charles-Antoine Couret <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments 8/10/12-bit 1-channel DAC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ti-dac7311.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD7293 driver
*
* Copyright 2021 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/iio/iio.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <asm/unaligned.h>
#define AD7293_R1B BIT(16)
#define AD7293_R2B BIT(17)
#define AD7293_PAGE_ADDR_MSK GENMASK(15, 8)
#define AD7293_PAGE(x) FIELD_PREP(AD7293_PAGE_ADDR_MSK, x)
/* AD7293 Register Map Common */
#define AD7293_REG_NO_OP (AD7293_R1B | AD7293_PAGE(0x0) | 0x0)
#define AD7293_REG_PAGE_SELECT (AD7293_R1B | AD7293_PAGE(0x0) | 0x1)
#define AD7293_REG_CONV_CMD (AD7293_R2B | AD7293_PAGE(0x0) | 0x2)
#define AD7293_REG_RESULT (AD7293_R1B | AD7293_PAGE(0x0) | 0x3)
#define AD7293_REG_DAC_EN (AD7293_R1B | AD7293_PAGE(0x0) | 0x4)
#define AD7293_REG_DEVICE_ID (AD7293_R2B | AD7293_PAGE(0x0) | 0xC)
#define AD7293_REG_SOFT_RESET (AD7293_R2B | AD7293_PAGE(0x0) | 0xF)
/* AD7293 Register Map Page 0x0 */
#define AD7293_REG_VIN0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x10)
#define AD7293_REG_VIN1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x11)
#define AD7293_REG_VIN2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x12)
#define AD7293_REG_VIN3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x13)
#define AD7293_REG_TSENSE_INT (AD7293_R2B | AD7293_PAGE(0x0) | 0x20)
#define AD7293_REG_TSENSE_D0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x21)
#define AD7293_REG_TSENSE_D1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x22)
#define AD7293_REG_ISENSE_0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x28)
#define AD7293_REG_ISENSE_1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x29)
#define AD7293_REG_ISENSE_2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x2A)
#define AD7293_REG_ISENSE_3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x2B)
#define AD7293_REG_UNI_VOUT0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x30)
#define AD7293_REG_UNI_VOUT1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x31)
#define AD7293_REG_UNI_VOUT2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x32)
#define AD7293_REG_UNI_VOUT3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x33)
#define AD7293_REG_BI_VOUT0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x34)
#define AD7293_REG_BI_VOUT1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x35)
#define AD7293_REG_BI_VOUT2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x36)
#define AD7293_REG_BI_VOUT3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x37)
/* AD7293 Register Map Page 0x2 */
#define AD7293_REG_DIGITAL_OUT_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x11)
#define AD7293_REG_DIGITAL_INOUT_FUNC (AD7293_R2B | AD7293_PAGE(0x2) | 0x12)
#define AD7293_REG_DIGITAL_FUNC_POL (AD7293_R2B | AD7293_PAGE(0x2) | 0x13)
#define AD7293_REG_GENERAL (AD7293_R2B | AD7293_PAGE(0x2) | 0x14)
#define AD7293_REG_VINX_RANGE0 (AD7293_R2B | AD7293_PAGE(0x2) | 0x15)
#define AD7293_REG_VINX_RANGE1 (AD7293_R2B | AD7293_PAGE(0x2) | 0x16)
#define AD7293_REG_VINX_DIFF_SE (AD7293_R2B | AD7293_PAGE(0x2) | 0x17)
#define AD7293_REG_VINX_FILTER (AD7293_R2B | AD7293_PAGE(0x2) | 0x18)
#define AD7293_REG_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x19)
#define AD7293_REG_CONV_DELAY (AD7293_R2B | AD7293_PAGE(0x2) | 0x1A)
#define AD7293_REG_TSENSE_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x1B)
#define AD7293_REG_ISENSE_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x1C)
#define AD7293_REG_ISENSE_GAIN (AD7293_R2B | AD7293_PAGE(0x2) | 0x1D)
#define AD7293_REG_DAC_SNOOZE_O (AD7293_R2B | AD7293_PAGE(0x2) | 0x1F)
#define AD7293_REG_DAC_SNOOZE_1 (AD7293_R2B | AD7293_PAGE(0x2) | 0x20)
#define AD7293_REG_RSX_MON_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x23)
#define AD7293_REG_INTEGR_CL (AD7293_R2B | AD7293_PAGE(0x2) | 0x28)
#define AD7293_REG_PA_ON_CTRL (AD7293_R2B | AD7293_PAGE(0x2) | 0x29)
#define AD7293_REG_RAMP_TIME_0 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2A)
#define AD7293_REG_RAMP_TIME_1 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2B)
#define AD7293_REG_RAMP_TIME_2 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2C)
#define AD7293_REG_RAMP_TIME_3 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2D)
#define AD7293_REG_CL_FR_IT (AD7293_R2B | AD7293_PAGE(0x2) | 0x2E)
#define AD7293_REG_INTX_AVSS_AVDD (AD7293_R2B | AD7293_PAGE(0x2) | 0x2F)
/* AD7293 Register Map Page 0x3 */
#define AD7293_REG_VINX_SEQ (AD7293_R2B | AD7293_PAGE(0x3) | 0x10)
#define AD7293_REG_ISENSEX_TSENSEX_SEQ (AD7293_R2B | AD7293_PAGE(0x3) | 0x11)
#define AD7293_REG_RSX_MON_BI_VOUTX_SEQ (AD7293_R2B | AD7293_PAGE(0x3) | 0x12)
/* AD7293 Register Map Page 0xE */
#define AD7293_REG_VIN0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x10)
#define AD7293_REG_VIN1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x11)
#define AD7293_REG_VIN2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x12)
#define AD7293_REG_VIN3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x13)
#define AD7293_REG_TSENSE_INT_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x20)
#define AD7293_REG_TSENSE_D0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x21)
#define AD7293_REG_TSENSE_D1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x22)
#define AD7293_REG_ISENSE0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x28)
#define AD7293_REG_ISENSE1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x29)
#define AD7293_REG_ISENSE2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x2A)
#define AD7293_REG_ISENSE3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x2B)
#define AD7293_REG_UNI_VOUT0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x30)
#define AD7293_REG_UNI_VOUT1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x31)
#define AD7293_REG_UNI_VOUT2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x32)
#define AD7293_REG_UNI_VOUT3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x33)
#define AD7293_REG_BI_VOUT0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x34)
#define AD7293_REG_BI_VOUT1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x35)
#define AD7293_REG_BI_VOUT2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x36)
#define AD7293_REG_BI_VOUT3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x37)
/* AD7293 Miscellaneous Definitions */
#define AD7293_READ BIT(7)
#define AD7293_TRANSF_LEN_MSK GENMASK(17, 16)
#define AD7293_REG_ADDR_MSK GENMASK(7, 0)
#define AD7293_REG_VOUT_OFFSET_MSK GENMASK(5, 4)
#define AD7293_REG_DATA_RAW_MSK GENMASK(15, 4)
#define AD7293_REG_VINX_RANGE_GET_CH_MSK(x, ch) (((x) >> (ch)) & 0x1)
#define AD7293_REG_VINX_RANGE_SET_CH_MSK(x, ch) (((x) & 0x1) << (ch))
#define AD7293_CHIP_ID 0x18
enum ad7293_ch_type {
AD7293_ADC_VINX,
AD7293_ADC_TSENSE,
AD7293_ADC_ISENSE,
AD7293_DAC,
};
enum ad7293_max_offset {
AD7293_TSENSE_MIN_OFFSET_CH = 4,
AD7293_ISENSE_MIN_OFFSET_CH = 7,
AD7293_VOUT_MIN_OFFSET_CH = 11,
AD7293_VOUT_MAX_OFFSET_CH = 18,
};
static const int dac_offset_table[] = {0, 1, 2};
static const int isense_gain_table[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10};
static const int adc_range_table[] = {0, 1, 2, 3};
struct ad7293_state {
struct spi_device *spi;
/* Protect against concurrent accesses to the device, page selection and data content */
struct mutex lock;
struct gpio_desc *gpio_reset;
struct regulator *reg_avdd;
struct regulator *reg_vdrive;
u8 page_select;
u8 data[3] __aligned(IIO_DMA_MINALIGN);
};
static int ad7293_page_select(struct ad7293_state *st, unsigned int reg)
{
int ret;
if (st->page_select != FIELD_GET(AD7293_PAGE_ADDR_MSK, reg)) {
st->data[0] = FIELD_GET(AD7293_REG_ADDR_MSK, AD7293_REG_PAGE_SELECT);
st->data[1] = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg);
ret = spi_write(st->spi, &st->data[0], 2);
if (ret)
return ret;
st->page_select = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg);
}
return 0;
}
static int __ad7293_spi_read(struct ad7293_state *st, unsigned int reg,
u16 *val)
{
int ret;
unsigned int length;
struct spi_transfer t = {0};
length = FIELD_GET(AD7293_TRANSF_LEN_MSK, reg);
ret = ad7293_page_select(st, reg);
if (ret)
return ret;
st->data[0] = AD7293_READ | FIELD_GET(AD7293_REG_ADDR_MSK, reg);
st->data[1] = 0x0;
st->data[2] = 0x0;
t.tx_buf = &st->data[0];
t.rx_buf = &st->data[0];
t.len = length + 1;
ret = spi_sync_transfer(st->spi, &t, 1);
if (ret)
return ret;
if (length == 1)
*val = st->data[1];
else
*val = get_unaligned_be16(&st->data[1]);
return 0;
}
static int ad7293_spi_read(struct ad7293_state *st, unsigned int reg,
u16 *val)
{
int ret;
mutex_lock(&st->lock);
ret = __ad7293_spi_read(st, reg, val);
mutex_unlock(&st->lock);
return ret;
}
static int __ad7293_spi_write(struct ad7293_state *st, unsigned int reg,
u16 val)
{
int ret;
unsigned int length;
length = FIELD_GET(AD7293_TRANSF_LEN_MSK, reg);
ret = ad7293_page_select(st, reg);
if (ret)
return ret;
st->data[0] = FIELD_GET(AD7293_REG_ADDR_MSK, reg);
if (length == 1)
st->data[1] = val;
else
put_unaligned_be16(val, &st->data[1]);
return spi_write(st->spi, &st->data[0], length + 1);
}
static int ad7293_spi_write(struct ad7293_state *st, unsigned int reg,
u16 val)
{
int ret;
mutex_lock(&st->lock);
ret = __ad7293_spi_write(st, reg, val);
mutex_unlock(&st->lock);
return ret;
}
static int __ad7293_spi_update_bits(struct ad7293_state *st, unsigned int reg,
u16 mask, u16 val)
{
int ret;
u16 data, temp;
ret = __ad7293_spi_read(st, reg, &data);
if (ret)
return ret;
temp = (data & ~mask) | (val & mask);
return __ad7293_spi_write(st, reg, temp);
}
static int ad7293_spi_update_bits(struct ad7293_state *st, unsigned int reg,
u16 mask, u16 val)
{
int ret;
mutex_lock(&st->lock);
ret = __ad7293_spi_update_bits(st, reg, mask, val);
mutex_unlock(&st->lock);
return ret;
}
static int ad7293_adc_get_scale(struct ad7293_state *st, unsigned int ch,
u16 *range)
{
int ret;
u16 data;
mutex_lock(&st->lock);
ret = __ad7293_spi_read(st, AD7293_REG_VINX_RANGE1, &data);
if (ret)
goto exit;
*range = AD7293_REG_VINX_RANGE_GET_CH_MSK(data, ch);
ret = __ad7293_spi_read(st, AD7293_REG_VINX_RANGE0, &data);
if (ret)
goto exit;
*range |= AD7293_REG_VINX_RANGE_GET_CH_MSK(data, ch) << 1;
exit:
mutex_unlock(&st->lock);
return ret;
}
static int ad7293_adc_set_scale(struct ad7293_state *st, unsigned int ch,
u16 range)
{
int ret;
unsigned int ch_msk = BIT(ch);
mutex_lock(&st->lock);
ret = __ad7293_spi_update_bits(st, AD7293_REG_VINX_RANGE1, ch_msk,
AD7293_REG_VINX_RANGE_SET_CH_MSK(range, ch));
if (ret)
goto exit;
ret = __ad7293_spi_update_bits(st, AD7293_REG_VINX_RANGE0, ch_msk,
AD7293_REG_VINX_RANGE_SET_CH_MSK((range >> 1), ch));
exit:
mutex_unlock(&st->lock);
return ret;
}
static int ad7293_get_offset(struct ad7293_state *st, unsigned int ch,
u16 *offset)
{
if (ch < AD7293_TSENSE_MIN_OFFSET_CH)
return ad7293_spi_read(st, AD7293_REG_VIN0_OFFSET + ch, offset);
else if (ch < AD7293_ISENSE_MIN_OFFSET_CH)
return ad7293_spi_read(st, AD7293_REG_TSENSE_INT_OFFSET + (ch - 4), offset);
else if (ch < AD7293_VOUT_MIN_OFFSET_CH)
return ad7293_spi_read(st, AD7293_REG_ISENSE0_OFFSET + (ch - 7), offset);
else if (ch <= AD7293_VOUT_MAX_OFFSET_CH)
return ad7293_spi_read(st, AD7293_REG_UNI_VOUT0_OFFSET + (ch - 11), offset);
return -EINVAL;
}
static int ad7293_set_offset(struct ad7293_state *st, unsigned int ch,
u16 offset)
{
if (ch < AD7293_TSENSE_MIN_OFFSET_CH)
return ad7293_spi_write(st, AD7293_REG_VIN0_OFFSET + ch,
offset);
else if (ch < AD7293_ISENSE_MIN_OFFSET_CH)
return ad7293_spi_write(st,
AD7293_REG_TSENSE_INT_OFFSET +
(ch - AD7293_TSENSE_MIN_OFFSET_CH),
offset);
else if (ch < AD7293_VOUT_MIN_OFFSET_CH)
return ad7293_spi_write(st,
AD7293_REG_ISENSE0_OFFSET +
(ch - AD7293_ISENSE_MIN_OFFSET_CH),
offset);
else if (ch <= AD7293_VOUT_MAX_OFFSET_CH)
return ad7293_spi_update_bits(st,
AD7293_REG_UNI_VOUT0_OFFSET +
(ch - AD7293_VOUT_MIN_OFFSET_CH),
AD7293_REG_VOUT_OFFSET_MSK,
FIELD_PREP(AD7293_REG_VOUT_OFFSET_MSK, offset));
return -EINVAL;
}
static int ad7293_isense_set_scale(struct ad7293_state *st, unsigned int ch,
u16 gain)
{
unsigned int ch_msk = (0xf << (4 * ch));
return ad7293_spi_update_bits(st, AD7293_REG_ISENSE_GAIN, ch_msk,
gain << (4 * ch));
}
static int ad7293_isense_get_scale(struct ad7293_state *st, unsigned int ch,
u16 *gain)
{
int ret;
ret = ad7293_spi_read(st, AD7293_REG_ISENSE_GAIN, gain);
if (ret)
return ret;
*gain = (*gain >> (4 * ch)) & 0xf;
return ret;
}
static int ad7293_dac_write_raw(struct ad7293_state *st, unsigned int ch,
u16 raw)
{
int ret;
mutex_lock(&st->lock);
ret = __ad7293_spi_update_bits(st, AD7293_REG_DAC_EN, BIT(ch), BIT(ch));
if (ret)
goto exit;
ret = __ad7293_spi_write(st, AD7293_REG_UNI_VOUT0 + ch,
FIELD_PREP(AD7293_REG_DATA_RAW_MSK, raw));
exit:
mutex_unlock(&st->lock);
return ret;
}
static int ad7293_ch_read_raw(struct ad7293_state *st, enum ad7293_ch_type type,
unsigned int ch, u16 *raw)
{
int ret;
unsigned int reg_wr, reg_rd, data_wr;
switch (type) {
case AD7293_ADC_VINX:
reg_wr = AD7293_REG_VINX_SEQ;
reg_rd = AD7293_REG_VIN0 + ch;
data_wr = BIT(ch);
break;
case AD7293_ADC_TSENSE:
reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ;
reg_rd = AD7293_REG_TSENSE_INT + ch;
data_wr = BIT(ch);
break;
case AD7293_ADC_ISENSE:
reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ;
reg_rd = AD7293_REG_ISENSE_0 + ch;
data_wr = BIT(ch) << 8;
break;
case AD7293_DAC:
reg_rd = AD7293_REG_UNI_VOUT0 + ch;
break;
default:
return -EINVAL;
}
mutex_lock(&st->lock);
if (type != AD7293_DAC) {
if (type == AD7293_ADC_TSENSE) {
ret = __ad7293_spi_write(st, AD7293_REG_TSENSE_BG_EN,
BIT(ch));
if (ret)
goto exit;
usleep_range(9000, 9900);
} else if (type == AD7293_ADC_ISENSE) {
ret = __ad7293_spi_write(st, AD7293_REG_ISENSE_BG_EN,
BIT(ch));
if (ret)
goto exit;
usleep_range(2000, 7000);
}
ret = __ad7293_spi_write(st, reg_wr, data_wr);
if (ret)
goto exit;
ret = __ad7293_spi_write(st, AD7293_REG_CONV_CMD, 0x82);
if (ret)
goto exit;
}
ret = __ad7293_spi_read(st, reg_rd, raw);
*raw = FIELD_GET(AD7293_REG_DATA_RAW_MSK, *raw);
exit:
mutex_unlock(&st->lock);
return ret;
}
static int ad7293_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
{
struct ad7293_state *st = iio_priv(indio_dev);
int ret;
u16 data;
switch (info) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_VOLTAGE:
if (chan->output)
ret = ad7293_ch_read_raw(st, AD7293_DAC,
chan->channel, &data);
else
ret = ad7293_ch_read_raw(st, AD7293_ADC_VINX,
chan->channel, &data);
break;
case IIO_CURRENT:
ret = ad7293_ch_read_raw(st, AD7293_ADC_ISENSE,
chan->channel, &data);
break;
case IIO_TEMP:
ret = ad7293_ch_read_raw(st, AD7293_ADC_TSENSE,
chan->channel, &data);
break;
default:
return -EINVAL;
}
if (ret)
return ret;
*val = data;
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
switch (chan->type) {
case IIO_VOLTAGE:
if (chan->output) {
ret = ad7293_get_offset(st,
chan->channel + AD7293_VOUT_MIN_OFFSET_CH,
&data);
data = FIELD_GET(AD7293_REG_VOUT_OFFSET_MSK, data);
} else {
ret = ad7293_get_offset(st, chan->channel, &data);
}
break;
case IIO_CURRENT:
ret = ad7293_get_offset(st,
chan->channel + AD7293_ISENSE_MIN_OFFSET_CH,
&data);
break;
case IIO_TEMP:
ret = ad7293_get_offset(st,
chan->channel + AD7293_TSENSE_MIN_OFFSET_CH,
&data);
break;
default:
return -EINVAL;
}
if (ret)
return ret;
*val = data;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_VOLTAGE:
ret = ad7293_adc_get_scale(st, chan->channel, &data);
if (ret)
return ret;
*val = data;
return IIO_VAL_INT;
case IIO_CURRENT:
ret = ad7293_isense_get_scale(st, chan->channel, &data);
if (ret)
return ret;
*val = data;
return IIO_VAL_INT;
case IIO_TEMP:
*val = 1;
*val2 = 8;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int ad7293_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long info)
{
struct ad7293_state *st = iio_priv(indio_dev);
switch (info) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_VOLTAGE:
if (!chan->output)
return -EINVAL;
return ad7293_dac_write_raw(st, chan->channel, val);
default:
return -EINVAL;
}
case IIO_CHAN_INFO_OFFSET:
switch (chan->type) {
case IIO_VOLTAGE:
if (chan->output)
return ad7293_set_offset(st,
chan->channel +
AD7293_VOUT_MIN_OFFSET_CH,
val);
else
return ad7293_set_offset(st, chan->channel, val);
case IIO_CURRENT:
return ad7293_set_offset(st,
chan->channel +
AD7293_ISENSE_MIN_OFFSET_CH,
val);
case IIO_TEMP:
return ad7293_set_offset(st,
chan->channel +
AD7293_TSENSE_MIN_OFFSET_CH,
val);
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_VOLTAGE:
return ad7293_adc_set_scale(st, chan->channel, val);
case IIO_CURRENT:
return ad7293_isense_set_scale(st, chan->channel, val);
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int ad7293_reg_access(struct iio_dev *indio_dev,
unsigned int reg,
unsigned int write_val,
unsigned int *read_val)
{
struct ad7293_state *st = iio_priv(indio_dev);
int ret;
if (read_val) {
u16 temp;
ret = ad7293_spi_read(st, reg, &temp);
*read_val = temp;
} else {
ret = ad7293_spi_write(st, reg, (u16)write_val);
}
return ret;
}
static int ad7293_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long info)
{
switch (info) {
case IIO_CHAN_INFO_OFFSET:
*vals = dac_offset_table;
*type = IIO_VAL_INT;
*length = ARRAY_SIZE(dac_offset_table);
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_SCALE:
*type = IIO_VAL_INT;
switch (chan->type) {
case IIO_VOLTAGE:
*vals = adc_range_table;
*length = ARRAY_SIZE(adc_range_table);
return IIO_AVAIL_LIST;
case IIO_CURRENT:
*vals = isense_gain_table;
*length = ARRAY_SIZE(isense_gain_table);
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
#define AD7293_CHAN_ADC(_channel) { \
.type = IIO_VOLTAGE, \
.output = 0, \
.indexed = 1, \
.channel = _channel, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET), \
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) \
}
#define AD7293_CHAN_DAC(_channel) { \
.type = IIO_VOLTAGE, \
.output = 1, \
.indexed = 1, \
.channel = _channel, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_OFFSET), \
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OFFSET) \
}
#define AD7293_CHAN_ISENSE(_channel) { \
.type = IIO_CURRENT, \
.output = 0, \
.indexed = 1, \
.channel = _channel, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) \
}
#define AD7293_CHAN_TEMP(_channel) { \
.type = IIO_TEMP, \
.output = 0, \
.indexed = 1, \
.channel = _channel, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_OFFSET), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
}
static const struct iio_chan_spec ad7293_channels[] = {
AD7293_CHAN_ADC(0),
AD7293_CHAN_ADC(1),
AD7293_CHAN_ADC(2),
AD7293_CHAN_ADC(3),
AD7293_CHAN_ISENSE(0),
AD7293_CHAN_ISENSE(1),
AD7293_CHAN_ISENSE(2),
AD7293_CHAN_ISENSE(3),
AD7293_CHAN_TEMP(0),
AD7293_CHAN_TEMP(1),
AD7293_CHAN_TEMP(2),
AD7293_CHAN_DAC(0),
AD7293_CHAN_DAC(1),
AD7293_CHAN_DAC(2),
AD7293_CHAN_DAC(3),
AD7293_CHAN_DAC(4),
AD7293_CHAN_DAC(5),
AD7293_CHAN_DAC(6),
AD7293_CHAN_DAC(7)
};
static int ad7293_soft_reset(struct ad7293_state *st)
{
int ret;
ret = __ad7293_spi_write(st, AD7293_REG_SOFT_RESET, 0x7293);
if (ret)
return ret;
return __ad7293_spi_write(st, AD7293_REG_SOFT_RESET, 0x0000);
}
static int ad7293_reset(struct ad7293_state *st)
{
if (st->gpio_reset) {
gpiod_set_value(st->gpio_reset, 0);
usleep_range(100, 1000);
gpiod_set_value(st->gpio_reset, 1);
usleep_range(100, 1000);
return 0;
}
/* Perform a software reset */
return ad7293_soft_reset(st);
}
static int ad7293_properties_parse(struct ad7293_state *st)
{
struct spi_device *spi = st->spi;
st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(st->gpio_reset))
return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_reset),
"failed to get the reset GPIO\n");
st->reg_avdd = devm_regulator_get(&spi->dev, "avdd");
if (IS_ERR(st->reg_avdd))
return dev_err_probe(&spi->dev, PTR_ERR(st->reg_avdd),
"failed to get the AVDD voltage\n");
st->reg_vdrive = devm_regulator_get(&spi->dev, "vdrive");
if (IS_ERR(st->reg_vdrive))
return dev_err_probe(&spi->dev, PTR_ERR(st->reg_vdrive),
"failed to get the VDRIVE voltage\n");
return 0;
}
static void ad7293_reg_disable(void *data)
{
regulator_disable(data);
}
static int ad7293_init(struct ad7293_state *st)
{
int ret;
u16 chip_id;
struct spi_device *spi = st->spi;
ret = ad7293_properties_parse(st);
if (ret)
return ret;
ret = ad7293_reset(st);
if (ret)
return ret;
ret = regulator_enable(st->reg_avdd);
if (ret) {
dev_err(&spi->dev,
"Failed to enable specified AVDD Voltage!\n");
return ret;
}
ret = devm_add_action_or_reset(&spi->dev, ad7293_reg_disable,
st->reg_avdd);
if (ret)
return ret;
ret = regulator_enable(st->reg_vdrive);
if (ret) {
dev_err(&spi->dev,
"Failed to enable specified VDRIVE Voltage!\n");
return ret;
}
ret = devm_add_action_or_reset(&spi->dev, ad7293_reg_disable,
st->reg_vdrive);
if (ret)
return ret;
ret = regulator_get_voltage(st->reg_avdd);
if (ret < 0) {
dev_err(&spi->dev, "Failed to read avdd regulator: %d\n", ret);
return ret;
}
if (ret > 5500000 || ret < 4500000)
return -EINVAL;
ret = regulator_get_voltage(st->reg_vdrive);
if (ret < 0) {
dev_err(&spi->dev,
"Failed to read vdrive regulator: %d\n", ret);
return ret;
}
if (ret > 5500000 || ret < 1700000)
return -EINVAL;
/* Check Chip ID */
ret = __ad7293_spi_read(st, AD7293_REG_DEVICE_ID, &chip_id);
if (ret)
return ret;
if (chip_id != AD7293_CHIP_ID) {
dev_err(&spi->dev, "Invalid Chip ID.\n");
return -EINVAL;
}
return 0;
}
static const struct iio_info ad7293_info = {
.read_raw = ad7293_read_raw,
.write_raw = ad7293_write_raw,
.read_avail = &ad7293_read_avail,
.debugfs_reg_access = &ad7293_reg_access,
};
static int ad7293_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct ad7293_state *st;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
indio_dev->info = &ad7293_info;
indio_dev->name = "ad7293";
indio_dev->channels = ad7293_channels;
indio_dev->num_channels = ARRAY_SIZE(ad7293_channels);
st->spi = spi;
st->page_select = 0;
mutex_init(&st->lock);
ret = ad7293_init(st);
if (ret)
return ret;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id ad7293_id[] = {
{ "ad7293", 0 },
{}
};
MODULE_DEVICE_TABLE(spi, ad7293_id);
static const struct of_device_id ad7293_of_match[] = {
{ .compatible = "adi,ad7293" },
{}
};
MODULE_DEVICE_TABLE(of, ad7293_of_match);
static struct spi_driver ad7293_driver = {
.driver = {
.name = "ad7293",
.of_match_table = ad7293_of_match,
},
.probe = ad7293_probe,
.id_table = ad7293_id,
};
module_spi_driver(ad7293_driver);
MODULE_AUTHOR("Antoniu Miclaus <[email protected]");
MODULE_DESCRIPTION("Analog Devices AD7293");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad7293.c |
// SPDX-License-Identifier: GPL-2.0
/*
* This file is part of STM32 DAC driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Authors: Amelie Delaunay <[email protected]>
* Fabrice Gasnier <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/string_helpers.h>
#include "stm32-dac-core.h"
#define STM32_DAC_CHANNEL_1 1
#define STM32_DAC_CHANNEL_2 2
#define STM32_DAC_IS_CHAN_1(ch) ((ch) & STM32_DAC_CHANNEL_1)
#define STM32_DAC_AUTO_SUSPEND_DELAY_MS 2000
/**
* struct stm32_dac - private data of DAC driver
* @common: reference to DAC common data
* @lock: lock to protect against potential races when reading
* and update CR, to keep it in sync with pm_runtime
*/
struct stm32_dac {
struct stm32_dac_common *common;
struct mutex lock;
};
static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
{
struct stm32_dac *dac = iio_priv(indio_dev);
u32 en, val;
int ret;
ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
if (ret < 0)
return ret;
if (STM32_DAC_IS_CHAN_1(channel))
en = FIELD_GET(STM32_DAC_CR_EN1, val);
else
en = FIELD_GET(STM32_DAC_CR_EN2, val);
return !!en;
}
static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch,
bool enable)
{
struct stm32_dac *dac = iio_priv(indio_dev);
struct device *dev = indio_dev->dev.parent;
u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2;
u32 en = enable ? msk : 0;
int ret;
/* already enabled / disabled ? */
mutex_lock(&dac->lock);
ret = stm32_dac_is_enabled(indio_dev, ch);
if (ret < 0 || enable == !!ret) {
mutex_unlock(&dac->lock);
return ret < 0 ? ret : 0;
}
if (enable) {
ret = pm_runtime_resume_and_get(dev);
if (ret < 0) {
mutex_unlock(&dac->lock);
return ret;
}
}
ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en);
mutex_unlock(&dac->lock);
if (ret < 0) {
dev_err(&indio_dev->dev, "%s failed\n", str_enable_disable(en));
goto err_put_pm;
}
/*
* When HFSEL is set, it is not allowed to write the DHRx register
* during 8 clock cycles after the ENx bit is set. It is not allowed
* to make software/hardware trigger during this period either.
*/
if (en && dac->common->hfsel)
udelay(1);
if (!enable) {
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
}
return 0;
err_put_pm:
if (enable) {
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
}
return ret;
}
static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val)
{
int ret;
if (STM32_DAC_IS_CHAN_1(channel))
ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val);
else
ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val);
return ret ? ret : IIO_VAL_INT;
}
static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
{
int ret;
if (STM32_DAC_IS_CHAN_1(channel))
ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val);
else
ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val);
return ret;
}
static int stm32_dac_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct stm32_dac *dac = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
return stm32_dac_get_value(dac, chan->channel, val);
case IIO_CHAN_INFO_SCALE:
*val = dac->common->vref_mv;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
}
static int stm32_dac_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct stm32_dac *dac = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
return stm32_dac_set_value(dac, chan->channel, val);
default:
return -EINVAL;
}
}
static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev,
unsigned reg, unsigned writeval,
unsigned *readval)
{
struct stm32_dac *dac = iio_priv(indio_dev);
if (!readval)
return regmap_write(dac->common->regmap, reg, writeval);
else
return regmap_read(dac->common->regmap, reg, readval);
}
static const struct iio_info stm32_dac_iio_info = {
.read_raw = stm32_dac_read_raw,
.write_raw = stm32_dac_write_raw,
.debugfs_reg_access = stm32_dac_debugfs_reg_access,
};
static const char * const stm32_dac_powerdown_modes[] = {
"three_state",
};
static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
return 0;
}
static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int type)
{
return 0;
}
static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
int ret = stm32_dac_is_enabled(indio_dev, chan->channel);
if (ret < 0)
return ret;
return sysfs_emit(buf, "%d\n", ret ? 0 : 1);
}
static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
bool powerdown;
int ret;
ret = kstrtobool(buf, &powerdown);
if (ret)
return ret;
ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown);
if (ret)
return ret;
return len;
}
static const struct iio_enum stm32_dac_powerdown_mode_en = {
.items = stm32_dac_powerdown_modes,
.num_items = ARRAY_SIZE(stm32_dac_powerdown_modes),
.get = stm32_dac_get_powerdown_mode,
.set = stm32_dac_set_powerdown_mode,
};
static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
{
.name = "powerdown",
.read = stm32_dac_read_powerdown,
.write = stm32_dac_write_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &stm32_dac_powerdown_mode_en),
{},
};
#define STM32_DAC_CHANNEL(chan, name) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = chan, \
.info_mask_separate = \
BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
/* scan_index is always 0 as num_channels is 1 */ \
.scan_type = { \
.sign = 'u', \
.realbits = 12, \
.storagebits = 16, \
}, \
.datasheet_name = name, \
.ext_info = stm32_dac_ext_info \
}
static const struct iio_chan_spec stm32_dac_channels[] = {
STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"),
STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"),
};
static int stm32_dac_chan_of_init(struct iio_dev *indio_dev)
{
struct device_node *np = indio_dev->dev.of_node;
unsigned int i;
u32 channel;
int ret;
ret = of_property_read_u32(np, "reg", &channel);
if (ret) {
dev_err(&indio_dev->dev, "Failed to read reg property\n");
return ret;
}
for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) {
if (stm32_dac_channels[i].channel == channel)
break;
}
if (i >= ARRAY_SIZE(stm32_dac_channels)) {
dev_err(&indio_dev->dev, "Invalid reg property\n");
return -EINVAL;
}
indio_dev->channels = &stm32_dac_channels[i];
/*
* Expose only one channel here, as they can be used independently,
* with separate trigger. Then separate IIO devices are instantiated
* to manage this.
*/
indio_dev->num_channels = 1;
return 0;
};
static int stm32_dac_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct iio_dev *indio_dev;
struct stm32_dac *dac;
int ret;
if (!np)
return -ENODEV;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
if (!indio_dev)
return -ENOMEM;
platform_set_drvdata(pdev, indio_dev);
dac = iio_priv(indio_dev);
dac->common = dev_get_drvdata(pdev->dev.parent);
indio_dev->name = dev_name(&pdev->dev);
indio_dev->dev.of_node = pdev->dev.of_node;
indio_dev->info = &stm32_dac_iio_info;
indio_dev->modes = INDIO_DIRECT_MODE;
mutex_init(&dac->lock);
ret = stm32_dac_chan_of_init(indio_dev);
if (ret < 0)
return ret;
/* Get stm32-dac-core PM online */
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_set_autosuspend_delay(dev, STM32_DAC_AUTO_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(dev);
pm_runtime_enable(dev);
ret = iio_device_register(indio_dev);
if (ret)
goto err_pm_put;
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
return 0;
err_pm_put:
pm_runtime_disable(dev);
pm_runtime_set_suspended(dev);
pm_runtime_put_noidle(dev);
return ret;
}
static int stm32_dac_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
pm_runtime_get_sync(&pdev->dev);
iio_device_unregister(indio_dev);
pm_runtime_disable(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
return 0;
}
static int stm32_dac_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
int channel = indio_dev->channels[0].channel;
int ret;
/* Ensure DAC is disabled before suspend */
ret = stm32_dac_is_enabled(indio_dev, channel);
if (ret)
return ret < 0 ? ret : -EBUSY;
return pm_runtime_force_suspend(dev);
}
static DEFINE_SIMPLE_DEV_PM_OPS(stm32_dac_pm_ops, stm32_dac_suspend,
pm_runtime_force_resume);
static const struct of_device_id stm32_dac_of_match[] = {
{ .compatible = "st,stm32-dac", },
{},
};
MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
static struct platform_driver stm32_dac_driver = {
.probe = stm32_dac_probe,
.remove = stm32_dac_remove,
.driver = {
.name = "stm32-dac",
.of_match_table = stm32_dac_of_match,
.pm = pm_sleep_ptr(&stm32_dac_pm_ops),
},
};
module_platform_driver(stm32_dac_driver);
MODULE_ALIAS("platform:stm32-dac");
MODULE_AUTHOR("Amelie Delaunay <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/stm32-dac.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* AD5770R Digital to analog converters driver
*
* Copyright 2018 Analog Devices Inc.
*/
#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#define ADI_SPI_IF_CONFIG_A 0x00
#define ADI_SPI_IF_CONFIG_B 0x01
#define ADI_SPI_IF_DEVICE_CONFIG 0x02
#define ADI_SPI_IF_CHIP_TYPE 0x03
#define ADI_SPI_IF_PRODUCT_ID_L 0x04
#define ADI_SPI_IF_PRODUCT_ID_H 0x05
#define ADI_SPI_IF_CHIP_GRADE 0x06
#define ADI_SPI_IF_SCRACTH_PAD 0x0A
#define ADI_SPI_IF_SPI_REVISION 0x0B
#define ADI_SPI_IF_SPI_VENDOR_L 0x0C
#define ADI_SPI_IF_SPI_VENDOR_H 0x0D
#define ADI_SPI_IF_SPI_STREAM_MODE 0x0E
#define ADI_SPI_IF_CONFIG_C 0x10
#define ADI_SPI_IF_STATUS_A 0x11
/* ADI_SPI_IF_CONFIG_A */
#define ADI_SPI_IF_SW_RESET_MSK (BIT(0) | BIT(7))
#define ADI_SPI_IF_SW_RESET_SEL(x) ((x) & ADI_SPI_IF_SW_RESET_MSK)
#define ADI_SPI_IF_ADDR_ASC_MSK (BIT(2) | BIT(5))
#define ADI_SPI_IF_ADDR_ASC_SEL(x) (((x) << 2) & ADI_SPI_IF_ADDR_ASC_MSK)
/* ADI_SPI_IF_CONFIG_B */
#define ADI_SPI_IF_SINGLE_INS_MSK BIT(7)
#define ADI_SPI_IF_SINGLE_INS_SEL(x) FIELD_PREP(ADI_SPI_IF_SINGLE_INS_MSK, x)
#define ADI_SPI_IF_SHORT_INS_MSK BIT(7)
#define ADI_SPI_IF_SHORT_INS_SEL(x) FIELD_PREP(ADI_SPI_IF_SINGLE_INS_MSK, x)
/* ADI_SPI_IF_CONFIG_C */
#define ADI_SPI_IF_STRICT_REG_MSK BIT(5)
#define ADI_SPI_IF_STRICT_REG_GET(x) FIELD_GET(ADI_SPI_IF_STRICT_REG_MSK, x)
/* AD5770R configuration registers */
#define AD5770R_CHANNEL_CONFIG 0x14
#define AD5770R_OUTPUT_RANGE(ch) (0x15 + (ch))
#define AD5770R_FILTER_RESISTOR(ch) (0x1D + (ch))
#define AD5770R_REFERENCE 0x1B
#define AD5770R_DAC_LSB(ch) (0x26 + 2 * (ch))
#define AD5770R_DAC_MSB(ch) (0x27 + 2 * (ch))
#define AD5770R_CH_SELECT 0x34
#define AD5770R_CH_ENABLE 0x44
/* AD5770R_CHANNEL_CONFIG */
#define AD5770R_CFG_CH0_SINK_EN(x) (((x) & 0x1) << 7)
#define AD5770R_CFG_SHUTDOWN_B(x, ch) (((x) & 0x1) << (ch))
/* AD5770R_OUTPUT_RANGE */
#define AD5770R_RANGE_OUTPUT_SCALING(x) (((x) & GENMASK(5, 0)) << 2)
#define AD5770R_RANGE_MODE(x) ((x) & GENMASK(1, 0))
/* AD5770R_REFERENCE */
#define AD5770R_REF_RESISTOR_SEL(x) (((x) & 0x1) << 2)
#define AD5770R_REF_SEL(x) ((x) & GENMASK(1, 0))
/* AD5770R_CH_ENABLE */
#define AD5770R_CH_SET(x, ch) (((x) & 0x1) << (ch))
#define AD5770R_MAX_CHANNELS 6
#define AD5770R_MAX_CH_MODES 14
#define AD5770R_LOW_VREF_mV 1250
#define AD5770R_HIGH_VREF_mV 2500
enum ad5770r_ch0_modes {
AD5770R_CH0_0_300 = 0,
AD5770R_CH0_NEG_60_0,
AD5770R_CH0_NEG_60_300
};
enum ad5770r_ch1_modes {
AD5770R_CH1_0_140_LOW_HEAD = 1,
AD5770R_CH1_0_140_LOW_NOISE,
AD5770R_CH1_0_250
};
enum ad5770r_ch2_5_modes {
AD5770R_CH_LOW_RANGE = 0,
AD5770R_CH_HIGH_RANGE
};
enum ad5770r_ref_v {
AD5770R_EXT_2_5_V = 0,
AD5770R_INT_1_25_V_OUT_ON,
AD5770R_EXT_1_25_V,
AD5770R_INT_1_25_V_OUT_OFF
};
enum ad5770r_output_filter_resistor {
AD5770R_FILTER_60_OHM = 0x0,
AD5770R_FILTER_5_6_KOHM = 0x5,
AD5770R_FILTER_11_2_KOHM,
AD5770R_FILTER_22_2_KOHM,
AD5770R_FILTER_44_4_KOHM,
AD5770R_FILTER_104_KOHM,
};
struct ad5770r_out_range {
u8 out_scale;
u8 out_range_mode;
};
/**
* struct ad5770r_state - driver instance specific data
* @spi: spi_device
* @regmap: regmap
* @vref_reg: fixed regulator for reference configuration
* @gpio_reset: gpio descriptor
* @output_mode: array contains channels output ranges
* @vref: reference value
* @ch_pwr_down: powerdown flags
* @internal_ref: internal reference flag
* @external_res: external 2.5k resistor flag
* @transf_buf: cache aligned buffer for spi read/write
*/
struct ad5770r_state {
struct spi_device *spi;
struct regmap *regmap;
struct regulator *vref_reg;
struct gpio_desc *gpio_reset;
struct ad5770r_out_range output_mode[AD5770R_MAX_CHANNELS];
int vref;
bool ch_pwr_down[AD5770R_MAX_CHANNELS];
bool internal_ref;
bool external_res;
u8 transf_buf[2] __aligned(IIO_DMA_MINALIGN);
};
static const struct regmap_config ad5770r_spi_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.read_flag_mask = BIT(7),
};
struct ad5770r_output_modes {
unsigned int ch;
u8 mode;
int min;
int max;
};
static struct ad5770r_output_modes ad5770r_rng_tbl[] = {
{ 0, AD5770R_CH0_0_300, 0, 300 },
{ 0, AD5770R_CH0_NEG_60_0, -60, 0 },
{ 0, AD5770R_CH0_NEG_60_300, -60, 300 },
{ 1, AD5770R_CH1_0_140_LOW_HEAD, 0, 140 },
{ 1, AD5770R_CH1_0_140_LOW_NOISE, 0, 140 },
{ 1, AD5770R_CH1_0_250, 0, 250 },
{ 2, AD5770R_CH_LOW_RANGE, 0, 55 },
{ 2, AD5770R_CH_HIGH_RANGE, 0, 150 },
{ 3, AD5770R_CH_LOW_RANGE, 0, 45 },
{ 3, AD5770R_CH_HIGH_RANGE, 0, 100 },
{ 4, AD5770R_CH_LOW_RANGE, 0, 45 },
{ 4, AD5770R_CH_HIGH_RANGE, 0, 100 },
{ 5, AD5770R_CH_LOW_RANGE, 0, 45 },
{ 5, AD5770R_CH_HIGH_RANGE, 0, 100 },
};
static const unsigned int ad5770r_filter_freqs[] = {
153, 357, 715, 1400, 2800, 262000,
};
static const unsigned int ad5770r_filter_reg_vals[] = {
AD5770R_FILTER_104_KOHM,
AD5770R_FILTER_44_4_KOHM,
AD5770R_FILTER_22_2_KOHM,
AD5770R_FILTER_11_2_KOHM,
AD5770R_FILTER_5_6_KOHM,
AD5770R_FILTER_60_OHM
};
static int ad5770r_set_output_mode(struct ad5770r_state *st,
const struct ad5770r_out_range *out_mode,
int channel)
{
unsigned int regval;
regval = AD5770R_RANGE_OUTPUT_SCALING(out_mode->out_scale) |
AD5770R_RANGE_MODE(out_mode->out_range_mode);
return regmap_write(st->regmap,
AD5770R_OUTPUT_RANGE(channel), regval);
}
static int ad5770r_set_reference(struct ad5770r_state *st)
{
unsigned int regval;
regval = AD5770R_REF_RESISTOR_SEL(st->external_res);
if (st->internal_ref) {
regval |= AD5770R_REF_SEL(AD5770R_INT_1_25_V_OUT_OFF);
} else {
switch (st->vref) {
case AD5770R_LOW_VREF_mV:
regval |= AD5770R_REF_SEL(AD5770R_EXT_1_25_V);
break;
case AD5770R_HIGH_VREF_mV:
regval |= AD5770R_REF_SEL(AD5770R_EXT_2_5_V);
break;
default:
regval = AD5770R_REF_SEL(AD5770R_INT_1_25_V_OUT_OFF);
break;
}
}
return regmap_write(st->regmap, AD5770R_REFERENCE, regval);
}
static int ad5770r_soft_reset(struct ad5770r_state *st)
{
return regmap_write(st->regmap, ADI_SPI_IF_CONFIG_A,
ADI_SPI_IF_SW_RESET_SEL(1));
}
static int ad5770r_reset(struct ad5770r_state *st)
{
/* Perform software reset if no GPIO provided */
if (!st->gpio_reset)
return ad5770r_soft_reset(st);
gpiod_set_value_cansleep(st->gpio_reset, 0);
usleep_range(10, 20);
gpiod_set_value_cansleep(st->gpio_reset, 1);
/* data must not be written during reset timeframe */
usleep_range(100, 200);
return 0;
}
static int ad5770r_get_range(struct ad5770r_state *st,
int ch, int *min, int *max)
{
int i;
u8 tbl_ch, tbl_mode, out_range;
out_range = st->output_mode[ch].out_range_mode;
for (i = 0; i < AD5770R_MAX_CH_MODES; i++) {
tbl_ch = ad5770r_rng_tbl[i].ch;
tbl_mode = ad5770r_rng_tbl[i].mode;
if (tbl_ch == ch && tbl_mode == out_range) {
*min = ad5770r_rng_tbl[i].min;
*max = ad5770r_rng_tbl[i].max;
return 0;
}
}
return -EINVAL;
}
static int ad5770r_get_filter_freq(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, int *freq)
{
struct ad5770r_state *st = iio_priv(indio_dev);
int ret;
unsigned int regval, i;
ret = regmap_read(st->regmap,
AD5770R_FILTER_RESISTOR(chan->channel), ®val);
if (ret < 0)
return ret;
for (i = 0; i < ARRAY_SIZE(ad5770r_filter_reg_vals); i++)
if (regval == ad5770r_filter_reg_vals[i])
break;
if (i == ARRAY_SIZE(ad5770r_filter_reg_vals))
return -EINVAL;
*freq = ad5770r_filter_freqs[i];
return IIO_VAL_INT;
}
static int ad5770r_set_filter_freq(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int freq)
{
struct ad5770r_state *st = iio_priv(indio_dev);
unsigned int regval, i;
for (i = 0; i < ARRAY_SIZE(ad5770r_filter_freqs); i++)
if (ad5770r_filter_freqs[i] >= freq)
break;
if (i == ARRAY_SIZE(ad5770r_filter_freqs))
return -EINVAL;
regval = ad5770r_filter_reg_vals[i];
return regmap_write(st->regmap, AD5770R_FILTER_RESISTOR(chan->channel),
regval);
}
static int ad5770r_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
{
struct ad5770r_state *st = iio_priv(indio_dev);
int max, min, ret;
u16 buf16;
switch (info) {
case IIO_CHAN_INFO_RAW:
ret = regmap_bulk_read(st->regmap,
chan->address,
st->transf_buf, 2);
if (ret)
return 0;
buf16 = st->transf_buf[0] + (st->transf_buf[1] << 8);
*val = buf16 >> 2;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = ad5770r_get_range(st, chan->channel, &min, &max);
if (ret < 0)
return ret;
*val = max - min;
/* There is no sign bit. (negative current is mapped from 0)
* (sourced/sinked) current = raw * scale + offset
* where offset in case of CH0 can be negative.
*/
*val2 = 14;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
return ad5770r_get_filter_freq(indio_dev, chan, val);
case IIO_CHAN_INFO_OFFSET:
ret = ad5770r_get_range(st, chan->channel, &min, &max);
if (ret < 0)
return ret;
*val = min;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int ad5770r_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long info)
{
struct ad5770r_state *st = iio_priv(indio_dev);
switch (info) {
case IIO_CHAN_INFO_RAW:
st->transf_buf[0] = ((u16)val >> 6);
st->transf_buf[1] = (val & GENMASK(5, 0)) << 2;
return regmap_bulk_write(st->regmap, chan->address,
st->transf_buf, 2);
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
return ad5770r_set_filter_freq(indio_dev, chan, val);
default:
return -EINVAL;
}
}
static int ad5770r_read_freq_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
*type = IIO_VAL_INT;
*vals = ad5770r_filter_freqs;
*length = ARRAY_SIZE(ad5770r_filter_freqs);
return IIO_AVAIL_LIST;
}
return -EINVAL;
}
static int ad5770r_reg_access(struct iio_dev *indio_dev,
unsigned int reg,
unsigned int writeval,
unsigned int *readval)
{
struct ad5770r_state *st = iio_priv(indio_dev);
if (readval)
return regmap_read(st->regmap, reg, readval);
else
return regmap_write(st->regmap, reg, writeval);
}
static const struct iio_info ad5770r_info = {
.read_raw = ad5770r_read_raw,
.write_raw = ad5770r_write_raw,
.read_avail = ad5770r_read_freq_avail,
.debugfs_reg_access = &ad5770r_reg_access,
};
static int ad5770r_store_output_range(struct ad5770r_state *st,
int min, int max, int index)
{
int i;
for (i = 0; i < AD5770R_MAX_CH_MODES; i++) {
if (ad5770r_rng_tbl[i].ch != index)
continue;
if (ad5770r_rng_tbl[i].min != min ||
ad5770r_rng_tbl[i].max != max)
continue;
st->output_mode[index].out_range_mode = ad5770r_rng_tbl[i].mode;
return 0;
}
return -EINVAL;
}
static ssize_t ad5770r_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct ad5770r_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", st->ch_pwr_down[chan->channel]);
}
static ssize_t ad5770r_write_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct ad5770r_state *st = iio_priv(indio_dev);
unsigned int regval;
unsigned int mask;
bool readin;
int ret;
ret = kstrtobool(buf, &readin);
if (ret)
return ret;
readin = !readin;
regval = AD5770R_CFG_SHUTDOWN_B(readin, chan->channel);
if (chan->channel == 0 &&
st->output_mode[0].out_range_mode > AD5770R_CH0_0_300) {
regval |= AD5770R_CFG_CH0_SINK_EN(readin);
mask = BIT(chan->channel) + BIT(7);
} else {
mask = BIT(chan->channel);
}
ret = regmap_update_bits(st->regmap, AD5770R_CHANNEL_CONFIG, mask,
regval);
if (ret)
return ret;
regval = AD5770R_CH_SET(readin, chan->channel);
ret = regmap_update_bits(st->regmap, AD5770R_CH_ENABLE,
BIT(chan->channel), regval);
if (ret)
return ret;
st->ch_pwr_down[chan->channel] = !readin;
return len;
}
static const struct iio_chan_spec_ext_info ad5770r_ext_info[] = {
{
.name = "powerdown",
.read = ad5770r_read_dac_powerdown,
.write = ad5770r_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
{ }
};
#define AD5770R_IDAC_CHANNEL(index, reg) { \
.type = IIO_CURRENT, \
.address = reg, \
.indexed = 1, \
.channel = index, \
.output = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
.info_mask_shared_by_type_available = \
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
.ext_info = ad5770r_ext_info, \
}
static const struct iio_chan_spec ad5770r_channels[] = {
AD5770R_IDAC_CHANNEL(0, AD5770R_DAC_MSB(0)),
AD5770R_IDAC_CHANNEL(1, AD5770R_DAC_MSB(1)),
AD5770R_IDAC_CHANNEL(2, AD5770R_DAC_MSB(2)),
AD5770R_IDAC_CHANNEL(3, AD5770R_DAC_MSB(3)),
AD5770R_IDAC_CHANNEL(4, AD5770R_DAC_MSB(4)),
AD5770R_IDAC_CHANNEL(5, AD5770R_DAC_MSB(5)),
};
static int ad5770r_channel_config(struct ad5770r_state *st)
{
int ret, tmp[2], min, max;
unsigned int num;
struct fwnode_handle *child;
num = device_get_child_node_count(&st->spi->dev);
if (num != AD5770R_MAX_CHANNELS)
return -EINVAL;
device_for_each_child_node(&st->spi->dev, child) {
ret = fwnode_property_read_u32(child, "reg", &num);
if (ret)
goto err_child_out;
if (num >= AD5770R_MAX_CHANNELS) {
ret = -EINVAL;
goto err_child_out;
}
ret = fwnode_property_read_u32_array(child,
"adi,range-microamp",
tmp, 2);
if (ret)
goto err_child_out;
min = tmp[0] / 1000;
max = tmp[1] / 1000;
ret = ad5770r_store_output_range(st, min, max, num);
if (ret)
goto err_child_out;
}
return 0;
err_child_out:
fwnode_handle_put(child);
return ret;
}
static int ad5770r_init(struct ad5770r_state *st)
{
int ret, i;
st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(st->gpio_reset))
return PTR_ERR(st->gpio_reset);
/* Perform a reset */
ret = ad5770r_reset(st);
if (ret)
return ret;
/* Set output range */
ret = ad5770r_channel_config(st);
if (ret)
return ret;
for (i = 0; i < AD5770R_MAX_CHANNELS; i++) {
ret = ad5770r_set_output_mode(st, &st->output_mode[i], i);
if (ret)
return ret;
}
st->external_res = fwnode_property_read_bool(st->spi->dev.fwnode,
"adi,external-resistor");
ret = ad5770r_set_reference(st);
if (ret)
return ret;
/* Set outputs off */
ret = regmap_write(st->regmap, AD5770R_CHANNEL_CONFIG, 0x00);
if (ret)
return ret;
ret = regmap_write(st->regmap, AD5770R_CH_ENABLE, 0x00);
if (ret)
return ret;
for (i = 0; i < AD5770R_MAX_CHANNELS; i++)
st->ch_pwr_down[i] = true;
return ret;
}
static void ad5770r_disable_regulator(void *data)
{
struct ad5770r_state *st = data;
regulator_disable(st->vref_reg);
}
static int ad5770r_probe(struct spi_device *spi)
{
struct ad5770r_state *st;
struct iio_dev *indio_dev;
struct regmap *regmap;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
st->spi = spi;
regmap = devm_regmap_init_spi(spi, &ad5770r_spi_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&spi->dev, "Error initializing spi regmap: %ld\n",
PTR_ERR(regmap));
return PTR_ERR(regmap);
}
st->regmap = regmap;
st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref");
if (!IS_ERR(st->vref_reg)) {
ret = regulator_enable(st->vref_reg);
if (ret) {
dev_err(&spi->dev,
"Failed to enable vref regulators: %d\n", ret);
return ret;
}
ret = devm_add_action_or_reset(&spi->dev,
ad5770r_disable_regulator,
st);
if (ret < 0)
return ret;
ret = regulator_get_voltage(st->vref_reg);
if (ret < 0)
return ret;
st->vref = ret / 1000;
} else {
if (PTR_ERR(st->vref_reg) == -ENODEV) {
st->vref = AD5770R_LOW_VREF_mV;
st->internal_ref = true;
} else {
return PTR_ERR(st->vref_reg);
}
}
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->info = &ad5770r_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ad5770r_channels;
indio_dev->num_channels = ARRAY_SIZE(ad5770r_channels);
ret = ad5770r_init(st);
if (ret < 0) {
dev_err(&spi->dev, "AD5770R init failed\n");
return ret;
}
return devm_iio_device_register(&st->spi->dev, indio_dev);
}
static const struct of_device_id ad5770r_of_id[] = {
{ .compatible = "adi,ad5770r", },
{},
};
MODULE_DEVICE_TABLE(of, ad5770r_of_id);
static const struct spi_device_id ad5770r_id[] = {
{ "ad5770r", 0 },
{},
};
MODULE_DEVICE_TABLE(spi, ad5770r_id);
static struct spi_driver ad5770r_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = ad5770r_of_id,
},
.probe = ad5770r_probe,
.id_table = ad5770r_id,
};
module_spi_driver(ad5770r_driver);
MODULE_AUTHOR("Mircea Caprioru <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5770R IDAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5770r.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* IIO DAC driver for NXP LPC18xx DAC
*
* Copyright (C) 2016 Joachim Eastwood <[email protected]>
*
* UNSUPPORTED hardware features:
* - Interrupts
* - DMA
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/iio/iio.h>
#include <linux/iio/driver.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
/* LPC18XX DAC registers and bits */
#define LPC18XX_DAC_CR 0x000
#define LPC18XX_DAC_CR_VALUE_SHIFT 6
#define LPC18XX_DAC_CR_VALUE_MASK 0x3ff
#define LPC18XX_DAC_CR_BIAS BIT(16)
#define LPC18XX_DAC_CTRL 0x004
#define LPC18XX_DAC_CTRL_DMA_ENA BIT(3)
struct lpc18xx_dac {
struct regulator *vref;
void __iomem *base;
struct mutex lock;
struct clk *clk;
};
static const struct iio_chan_spec lpc18xx_dac_iio_channels[] = {
{
.type = IIO_VOLTAGE,
.output = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
};
static int lpc18xx_dac_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct lpc18xx_dac *dac = iio_priv(indio_dev);
u32 reg;
switch (mask) {
case IIO_CHAN_INFO_RAW:
reg = readl(dac->base + LPC18XX_DAC_CR);
*val = reg >> LPC18XX_DAC_CR_VALUE_SHIFT;
*val &= LPC18XX_DAC_CR_VALUE_MASK;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = regulator_get_voltage(dac->vref) / 1000;
*val2 = 10;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
static int lpc18xx_dac_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct lpc18xx_dac *dac = iio_priv(indio_dev);
u32 reg;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val < 0 || val > LPC18XX_DAC_CR_VALUE_MASK)
return -EINVAL;
reg = LPC18XX_DAC_CR_BIAS;
reg |= val << LPC18XX_DAC_CR_VALUE_SHIFT;
mutex_lock(&dac->lock);
writel(reg, dac->base + LPC18XX_DAC_CR);
writel(LPC18XX_DAC_CTRL_DMA_ENA, dac->base + LPC18XX_DAC_CTRL);
mutex_unlock(&dac->lock);
return 0;
}
return -EINVAL;
}
static const struct iio_info lpc18xx_dac_info = {
.read_raw = lpc18xx_dac_read_raw,
.write_raw = lpc18xx_dac_write_raw,
};
static int lpc18xx_dac_probe(struct platform_device *pdev)
{
struct iio_dev *indio_dev;
struct lpc18xx_dac *dac;
int ret;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
if (!indio_dev)
return -ENOMEM;
platform_set_drvdata(pdev, indio_dev);
dac = iio_priv(indio_dev);
mutex_init(&dac->lock);
dac->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dac->base))
return PTR_ERR(dac->base);
dac->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(dac->clk))
return dev_err_probe(&pdev->dev, PTR_ERR(dac->clk),
"error getting clock\n");
dac->vref = devm_regulator_get(&pdev->dev, "vref");
if (IS_ERR(dac->vref))
return dev_err_probe(&pdev->dev, PTR_ERR(dac->vref),
"error getting regulator\n");
indio_dev->name = dev_name(&pdev->dev);
indio_dev->info = &lpc18xx_dac_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = lpc18xx_dac_iio_channels;
indio_dev->num_channels = ARRAY_SIZE(lpc18xx_dac_iio_channels);
ret = regulator_enable(dac->vref);
if (ret) {
dev_err(&pdev->dev, "unable to enable regulator\n");
return ret;
}
ret = clk_prepare_enable(dac->clk);
if (ret) {
dev_err(&pdev->dev, "unable to enable clock\n");
goto dis_reg;
}
writel(0, dac->base + LPC18XX_DAC_CTRL);
writel(0, dac->base + LPC18XX_DAC_CR);
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&pdev->dev, "unable to register device\n");
goto dis_clk;
}
return 0;
dis_clk:
clk_disable_unprepare(dac->clk);
dis_reg:
regulator_disable(dac->vref);
return ret;
}
static int lpc18xx_dac_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct lpc18xx_dac *dac = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
writel(0, dac->base + LPC18XX_DAC_CTRL);
clk_disable_unprepare(dac->clk);
regulator_disable(dac->vref);
return 0;
}
static const struct of_device_id lpc18xx_dac_match[] = {
{ .compatible = "nxp,lpc1850-dac" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, lpc18xx_dac_match);
static struct platform_driver lpc18xx_dac_driver = {
.probe = lpc18xx_dac_probe,
.remove = lpc18xx_dac_remove,
.driver = {
.name = "lpc18xx-dac",
.of_match_table = lpc18xx_dac_match,
},
};
module_platform_driver(lpc18xx_dac_driver);
MODULE_DESCRIPTION("LPC18xx DAC driver");
MODULE_AUTHOR("Joachim Eastwood <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/lpc18xx_dac.c |
// SPDX-License-Identifier: GPL-2.0
/*
* AD5338R, AD5671R, AD5673R, AD5675R, AD5677R, AD5691R, AD5692R, AD5693,
* AD5693R, AD5694, AD5694R, AD5695R, AD5696, AD5696R
* Digital to analog converters driver
*
* Copyright 2018 Analog Devices Inc.
*/
#include "ad5686.h"
#include <linux/module.h>
#include <linux/i2c.h>
static int ad5686_i2c_read(struct ad5686_state *st, u8 addr)
{
struct i2c_client *i2c = to_i2c_client(st->dev);
struct i2c_msg msg[2] = {
{
.addr = i2c->addr,
.flags = i2c->flags,
.len = 3,
.buf = &st->data[0].d8[1],
},
{
.addr = i2c->addr,
.flags = i2c->flags | I2C_M_RD,
.len = 2,
.buf = (char *)&st->data[0].d16,
},
};
int ret;
st->data[0].d32 = cpu_to_be32(AD5686_CMD(AD5686_CMD_NOOP) |
AD5686_ADDR(addr) |
0x00);
ret = i2c_transfer(i2c->adapter, msg, 2);
if (ret < 0)
return ret;
return be16_to_cpu(st->data[0].d16);
}
static int ad5686_i2c_write(struct ad5686_state *st,
u8 cmd, u8 addr, u16 val)
{
struct i2c_client *i2c = to_i2c_client(st->dev);
int ret;
st->data[0].d32 = cpu_to_be32(AD5686_CMD(cmd) | AD5686_ADDR(addr)
| val);
ret = i2c_master_send(i2c, &st->data[0].d8[1], 3);
if (ret < 0)
return ret;
return (ret != 3) ? -EIO : 0;
}
static int ad5686_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
return ad5686_probe(&i2c->dev, id->driver_data, id->name,
ad5686_i2c_write, ad5686_i2c_read);
}
static void ad5686_i2c_remove(struct i2c_client *i2c)
{
ad5686_remove(&i2c->dev);
}
static const struct i2c_device_id ad5686_i2c_id[] = {
{"ad5311r", ID_AD5311R},
{"ad5337r", ID_AD5337R},
{"ad5338r", ID_AD5338R},
{"ad5671r", ID_AD5671R},
{"ad5673r", ID_AD5673R},
{"ad5675r", ID_AD5675R},
{"ad5677r", ID_AD5677R},
{"ad5691r", ID_AD5691R},
{"ad5692r", ID_AD5692R},
{"ad5693", ID_AD5693},
{"ad5693r", ID_AD5693R},
{"ad5694", ID_AD5694},
{"ad5694r", ID_AD5694R},
{"ad5695r", ID_AD5695R},
{"ad5696", ID_AD5696},
{"ad5696r", ID_AD5696R},
{}
};
MODULE_DEVICE_TABLE(i2c, ad5686_i2c_id);
static const struct of_device_id ad5686_of_match[] = {
{ .compatible = "adi,ad5311r" },
{ .compatible = "adi,ad5337r" },
{ .compatible = "adi,ad5338r" },
{ .compatible = "adi,ad5671r" },
{ .compatible = "adi,ad5675r" },
{ .compatible = "adi,ad5691r" },
{ .compatible = "adi,ad5692r" },
{ .compatible = "adi,ad5693" },
{ .compatible = "adi,ad5693r" },
{ .compatible = "adi,ad5694" },
{ .compatible = "adi,ad5694r" },
{ .compatible = "adi,ad5695r" },
{ .compatible = "adi,ad5696" },
{ .compatible = "adi,ad5696r" },
{}
};
MODULE_DEVICE_TABLE(of, ad5686_of_match);
static struct i2c_driver ad5686_i2c_driver = {
.driver = {
.name = "ad5696",
.of_match_table = ad5686_of_match,
},
.probe = ad5686_i2c_probe,
.remove = ad5686_i2c_remove,
.id_table = ad5686_i2c_id,
};
module_i2c_driver(ad5686_i2c_driver);
MODULE_AUTHOR("Stefan Popa <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5686 and similar multi-channel DACs");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_AD5686);
| linux-master | drivers/iio/dac/ad5696-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Maxim MAX5522
* Dual, Ultra-Low-Power 10-Bit, Voltage-Output DACs
*
* Copyright 2022 Timesys Corp.
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#define MAX5522_MAX_ADDR 15
#define MAX5522_CTRL_NONE 0
#define MAX5522_CTRL_LOAD_IN_A 9
#define MAX5522_CTRL_LOAD_IN_B 10
#define MAX5522_REG_DATA(x) ((x) + MAX5522_CTRL_LOAD_IN_A)
struct max5522_chip_info {
const char *name;
const struct iio_chan_spec *channels;
unsigned int num_channels;
};
struct max5522_state {
struct regmap *regmap;
const struct max5522_chip_info *chip_info;
unsigned short dac_cache[2];
struct regulator *vrefin_reg;
};
#define MAX5522_CHANNEL(chan) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.scan_type = { \
.sign = 'u', \
.realbits = 10, \
.storagebits = 16, \
.shift = 2, \
} \
}
static const struct iio_chan_spec max5522_channels[] = {
MAX5522_CHANNEL(0),
MAX5522_CHANNEL(1),
};
enum max5522_type {
ID_MAX5522,
};
static const struct max5522_chip_info max5522_chip_info_tbl[] = {
[ID_MAX5522] = {
.name = "max5522",
.channels = max5522_channels,
.num_channels = 2,
},
};
static inline int max5522_info_to_reg(struct iio_chan_spec const *chan)
{
return MAX5522_REG_DATA(chan->channel);
}
static int max5522_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
{
struct max5522_state *state = iio_priv(indio_dev);
int ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
*val = state->dac_cache[chan->channel];
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = regulator_get_voltage(state->vrefin_reg);
if (ret < 0)
return -EINVAL;
*val = ret / 1000;
*val2 = 10;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
return -EINVAL;
}
static int max5522_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long info)
{
struct max5522_state *state = iio_priv(indio_dev);
int rval;
if (val > 1023 || val < 0)
return -EINVAL;
rval = regmap_write(state->regmap, max5522_info_to_reg(chan),
val << chan->scan_type.shift);
if (rval < 0)
return rval;
state->dac_cache[chan->channel] = val;
return 0;
}
static const struct iio_info max5522_info = {
.read_raw = max5522_read_raw,
.write_raw = max5522_write_raw,
};
static const struct regmap_config max5522_regmap_config = {
.reg_bits = 4,
.val_bits = 12,
.max_register = MAX5522_MAX_ADDR,
};
static int max5522_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct iio_dev *indio_dev;
struct max5522_state *state;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state));
if (indio_dev == NULL) {
dev_err(&spi->dev, "failed to allocate iio device\n");
return -ENOMEM;
}
state = iio_priv(indio_dev);
state->chip_info = device_get_match_data(&spi->dev);
if (!state->chip_info) {
state->chip_info =
(struct max5522_chip_info *)(id->driver_data);
if (!state->chip_info)
return -EINVAL;
}
state->vrefin_reg = devm_regulator_get(&spi->dev, "vrefin");
if (IS_ERR(state->vrefin_reg))
return dev_err_probe(&spi->dev, PTR_ERR(state->vrefin_reg),
"Vrefin regulator not specified\n");
ret = regulator_enable(state->vrefin_reg);
if (ret) {
return dev_err_probe(&spi->dev, ret,
"Failed to enable vref regulators\n");
}
state->regmap = devm_regmap_init_spi(spi, &max5522_regmap_config);
if (IS_ERR(state->regmap))
return PTR_ERR(state->regmap);
indio_dev->info = &max5522_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = max5522_channels;
indio_dev->num_channels = ARRAY_SIZE(max5522_channels);
indio_dev->name = max5522_chip_info_tbl[ID_MAX5522].name;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id max5522_ids[] = {
{ "max5522", (kernel_ulong_t)&max5522_chip_info_tbl[ID_MAX5522] },
{}
};
MODULE_DEVICE_TABLE(spi, max5522_ids);
static const struct of_device_id max5522_of_match[] = {
{
.compatible = "maxim,max5522",
.data = &max5522_chip_info_tbl[ID_MAX5522],
},
{}
};
MODULE_DEVICE_TABLE(of, max5522_of_match);
static struct spi_driver max5522_spi_driver = {
.driver = {
.name = "max5522",
.of_match_table = max5522_of_match,
},
.probe = max5522_spi_probe,
.id_table = max5522_ids,
};
module_spi_driver(max5522_spi_driver);
MODULE_AUTHOR("Angelo Dureghello <[email protected]");
MODULE_DESCRIPTION("MAX5522 DAC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/dac/max5522.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ti-dac5571.c - Texas Instruments 8/10/12-bit 1/4-channel DAC driver
*
* Copyright (C) 2018 Prevas A/S
*
* https://www.ti.com/lit/ds/symlink/dac5571.pdf
* https://www.ti.com/lit/ds/symlink/dac6571.pdf
* https://www.ti.com/lit/ds/symlink/dac7571.pdf
* https://www.ti.com/lit/ds/symlink/dac5574.pdf
* https://www.ti.com/lit/ds/symlink/dac6574.pdf
* https://www.ti.com/lit/ds/symlink/dac7574.pdf
* https://www.ti.com/lit/ds/symlink/dac5573.pdf
* https://www.ti.com/lit/ds/symlink/dac6573.pdf
* https://www.ti.com/lit/ds/symlink/dac7573.pdf
* https://www.ti.com/lit/ds/symlink/dac121c081.pdf
*/
#include <linux/iio/iio.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
enum chip_id {
single_8bit, single_10bit, single_12bit,
quad_8bit, quad_10bit, quad_12bit
};
struct dac5571_spec {
u8 num_channels;
u8 resolution;
};
static const struct dac5571_spec dac5571_spec[] = {
[single_8bit] = {.num_channels = 1, .resolution = 8},
[single_10bit] = {.num_channels = 1, .resolution = 10},
[single_12bit] = {.num_channels = 1, .resolution = 12},
[quad_8bit] = {.num_channels = 4, .resolution = 8},
[quad_10bit] = {.num_channels = 4, .resolution = 10},
[quad_12bit] = {.num_channels = 4, .resolution = 12},
};
struct dac5571_data {
struct i2c_client *client;
int id;
struct mutex lock;
struct regulator *vref;
u16 val[4];
bool powerdown[4];
u8 powerdown_mode[4];
struct dac5571_spec const *spec;
int (*dac5571_cmd)(struct dac5571_data *data, int channel, u16 val);
int (*dac5571_pwrdwn)(struct dac5571_data *data, int channel, u8 pwrdwn);
u8 buf[3] __aligned(IIO_DMA_MINALIGN);
};
#define DAC5571_POWERDOWN(mode) ((mode) + 1)
#define DAC5571_POWERDOWN_FLAG BIT(0)
#define DAC5571_CHANNEL_SELECT 1
#define DAC5571_LOADMODE_DIRECT BIT(4)
#define DAC5571_SINGLE_PWRDWN_BITS 4
#define DAC5571_QUAD_PWRDWN_BITS 6
static int dac5571_cmd_single(struct dac5571_data *data, int channel, u16 val)
{
unsigned int shift;
shift = 12 - data->spec->resolution;
data->buf[1] = val << shift;
data->buf[0] = val >> (8 - shift);
if (i2c_master_send(data->client, data->buf, 2) != 2)
return -EIO;
return 0;
}
static int dac5571_cmd_quad(struct dac5571_data *data, int channel, u16 val)
{
unsigned int shift;
shift = 16 - data->spec->resolution;
data->buf[2] = val << shift;
data->buf[1] = (val >> (8 - shift));
data->buf[0] = (channel << DAC5571_CHANNEL_SELECT) |
DAC5571_LOADMODE_DIRECT;
if (i2c_master_send(data->client, data->buf, 3) != 3)
return -EIO;
return 0;
}
static int dac5571_pwrdwn_single(struct dac5571_data *data, int channel, u8 pwrdwn)
{
data->buf[1] = 0;
data->buf[0] = pwrdwn << DAC5571_SINGLE_PWRDWN_BITS;
if (i2c_master_send(data->client, data->buf, 2) != 2)
return -EIO;
return 0;
}
static int dac5571_pwrdwn_quad(struct dac5571_data *data, int channel, u8 pwrdwn)
{
data->buf[2] = 0;
data->buf[1] = pwrdwn << DAC5571_QUAD_PWRDWN_BITS;
data->buf[0] = (channel << DAC5571_CHANNEL_SELECT) |
DAC5571_LOADMODE_DIRECT | DAC5571_POWERDOWN_FLAG;
if (i2c_master_send(data->client, data->buf, 3) != 3)
return -EIO;
return 0;
}
static const char *const dac5571_powerdown_modes[] = {
"1kohm_to_gnd", "100kohm_to_gnd", "three_state",
};
static int dac5571_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct dac5571_data *data = iio_priv(indio_dev);
return data->powerdown_mode[chan->channel];
}
static int dac5571_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int mode)
{
struct dac5571_data *data = iio_priv(indio_dev);
int ret = 0;
if (data->powerdown_mode[chan->channel] == mode)
return 0;
mutex_lock(&data->lock);
if (data->powerdown[chan->channel]) {
ret = data->dac5571_pwrdwn(data, chan->channel,
DAC5571_POWERDOWN(mode));
if (ret)
goto out;
}
data->powerdown_mode[chan->channel] = mode;
out:
mutex_unlock(&data->lock);
return ret;
}
static const struct iio_enum dac5571_powerdown_mode = {
.items = dac5571_powerdown_modes,
.num_items = ARRAY_SIZE(dac5571_powerdown_modes),
.get = dac5571_get_powerdown_mode,
.set = dac5571_set_powerdown_mode,
};
static ssize_t dac5571_read_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct dac5571_data *data = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", data->powerdown[chan->channel]);
}
static ssize_t dac5571_write_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct dac5571_data *data = iio_priv(indio_dev);
bool powerdown;
int ret;
ret = kstrtobool(buf, &powerdown);
if (ret)
return ret;
if (data->powerdown[chan->channel] == powerdown)
return len;
mutex_lock(&data->lock);
if (powerdown)
ret = data->dac5571_pwrdwn(data, chan->channel,
DAC5571_POWERDOWN(data->powerdown_mode[chan->channel]));
else
ret = data->dac5571_cmd(data, chan->channel,
data->val[chan->channel]);
if (ret)
goto out;
data->powerdown[chan->channel] = powerdown;
out:
mutex_unlock(&data->lock);
return ret ? ret : len;
}
static const struct iio_chan_spec_ext_info dac5571_ext_info[] = {
{
.name = "powerdown",
.read = dac5571_read_powerdown,
.write = dac5571_write_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SEPARATE, &dac5571_powerdown_mode),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &dac5571_powerdown_mode),
{},
};
#define dac5571_CHANNEL(chan, name) { \
.type = IIO_VOLTAGE, \
.channel = (chan), \
.address = (chan), \
.indexed = true, \
.output = true, \
.datasheet_name = name, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.ext_info = dac5571_ext_info, \
}
static const struct iio_chan_spec dac5571_channels[] = {
dac5571_CHANNEL(0, "A"),
dac5571_CHANNEL(1, "B"),
dac5571_CHANNEL(2, "C"),
dac5571_CHANNEL(3, "D"),
};
static int dac5571_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct dac5571_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
*val = data->val[chan->channel];
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = regulator_get_voltage(data->vref);
if (ret < 0)
return ret;
*val = ret / 1000;
*val2 = data->spec->resolution;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
}
static int dac5571_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct dac5571_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (data->val[chan->channel] == val)
return 0;
if (val >= (1 << data->spec->resolution) || val < 0)
return -EINVAL;
if (data->powerdown[chan->channel])
return -EBUSY;
mutex_lock(&data->lock);
ret = data->dac5571_cmd(data, chan->channel, val);
if (ret == 0)
data->val[chan->channel] = val;
mutex_unlock(&data->lock);
return ret;
default:
return -EINVAL;
}
}
static int dac5571_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
long mask)
{
return IIO_VAL_INT;
}
static const struct iio_info dac5571_info = {
.read_raw = dac5571_read_raw,
.write_raw = dac5571_write_raw,
.write_raw_get_fmt = dac5571_write_raw_get_fmt,
};
static int dac5571_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct device *dev = &client->dev;
const struct dac5571_spec *spec;
struct dac5571_data *data;
struct iio_dev *indio_dev;
enum chip_id chip_id;
int ret, i;
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
indio_dev->info = &dac5571_info;
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = dac5571_channels;
if (dev_fwnode(dev))
chip_id = (uintptr_t)device_get_match_data(dev);
else
chip_id = id->driver_data;
spec = &dac5571_spec[chip_id];
indio_dev->num_channels = spec->num_channels;
data->spec = spec;
data->vref = devm_regulator_get(dev, "vref");
if (IS_ERR(data->vref))
return PTR_ERR(data->vref);
ret = regulator_enable(data->vref);
if (ret < 0)
return ret;
mutex_init(&data->lock);
switch (spec->num_channels) {
case 1:
data->dac5571_cmd = dac5571_cmd_single;
data->dac5571_pwrdwn = dac5571_pwrdwn_single;
break;
case 4:
data->dac5571_cmd = dac5571_cmd_quad;
data->dac5571_pwrdwn = dac5571_pwrdwn_quad;
break;
default:
ret = -EINVAL;
goto err;
}
for (i = 0; i < spec->num_channels; i++) {
ret = data->dac5571_cmd(data, i, 0);
if (ret) {
dev_err(dev, "failed to initialize channel %d to 0\n", i);
goto err;
}
}
ret = iio_device_register(indio_dev);
if (ret)
goto err;
return 0;
err:
regulator_disable(data->vref);
return ret;
}
static void dac5571_remove(struct i2c_client *i2c)
{
struct iio_dev *indio_dev = i2c_get_clientdata(i2c);
struct dac5571_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
regulator_disable(data->vref);
}
static const struct of_device_id dac5571_of_id[] = {
{.compatible = "ti,dac5571", .data = (void *)single_8bit},
{.compatible = "ti,dac6571", .data = (void *)single_10bit},
{.compatible = "ti,dac7571", .data = (void *)single_12bit},
{.compatible = "ti,dac5574", .data = (void *)quad_8bit},
{.compatible = "ti,dac6574", .data = (void *)quad_10bit},
{.compatible = "ti,dac7574", .data = (void *)quad_12bit},
{.compatible = "ti,dac5573", .data = (void *)quad_8bit},
{.compatible = "ti,dac6573", .data = (void *)quad_10bit},
{.compatible = "ti,dac7573", .data = (void *)quad_12bit},
{.compatible = "ti,dac121c081", .data = (void *)single_12bit},
{}
};
MODULE_DEVICE_TABLE(of, dac5571_of_id);
static const struct i2c_device_id dac5571_id[] = {
{"dac5571", single_8bit},
{"dac6571", single_10bit},
{"dac7571", single_12bit},
{"dac5574", quad_8bit},
{"dac6574", quad_10bit},
{"dac7574", quad_12bit},
{"dac5573", quad_8bit},
{"dac6573", quad_10bit},
{"dac7573", quad_12bit},
{"dac121c081", single_12bit},
{}
};
MODULE_DEVICE_TABLE(i2c, dac5571_id);
static struct i2c_driver dac5571_driver = {
.driver = {
.name = "ti-dac5571",
.of_match_table = dac5571_of_id,
},
.probe = dac5571_probe,
.remove = dac5571_remove,
.id_table = dac5571_id,
};
module_i2c_driver(dac5571_driver);
MODULE_AUTHOR("Sean Nyekjaer <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments 8/10/12-bit 1/4-channel DAC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ti-dac5571.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD5415, AD5426, AD5429, AD5432, AD5439, AD5443, AD5449 Digital to Analog
* Converter driver.
*
* Copyright 2012 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <asm/unaligned.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/platform_data/ad5449.h>
#define AD5449_MAX_CHANNELS 2
#define AD5449_MAX_VREFS 2
#define AD5449_CMD_NOOP 0x0
#define AD5449_CMD_LOAD_AND_UPDATE(x) (0x1 + (x) * 3)
#define AD5449_CMD_READ(x) (0x2 + (x) * 3)
#define AD5449_CMD_LOAD(x) (0x3 + (x) * 3)
#define AD5449_CMD_CTRL 13
#define AD5449_CTRL_SDO_OFFSET 10
#define AD5449_CTRL_DAISY_CHAIN BIT(9)
#define AD5449_CTRL_HCLR_TO_MIDSCALE BIT(8)
#define AD5449_CTRL_SAMPLE_RISING BIT(7)
/**
* struct ad5449_chip_info - chip specific information
* @channels: Channel specification
* @num_channels: Number of channels
* @has_ctrl: Chip has a control register
*/
struct ad5449_chip_info {
const struct iio_chan_spec *channels;
unsigned int num_channels;
bool has_ctrl;
};
/**
* struct ad5449 - driver instance specific data
* @spi: the SPI device for this driver instance
* @chip_info: chip model specific constants, available modes etc
* @vref_reg: vref supply regulators
* @has_sdo: whether the SDO line is connected
* @dac_cache: Cache for the DAC values
* @data: spi transfer buffers
* @lock: lock to protect the data buffer during SPI ops
*/
struct ad5449 {
struct spi_device *spi;
const struct ad5449_chip_info *chip_info;
struct regulator_bulk_data vref_reg[AD5449_MAX_VREFS];
struct mutex lock;
bool has_sdo;
uint16_t dac_cache[AD5449_MAX_CHANNELS];
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
__be16 data[2] __aligned(IIO_DMA_MINALIGN);
};
enum ad5449_type {
ID_AD5426,
ID_AD5429,
ID_AD5432,
ID_AD5439,
ID_AD5443,
ID_AD5449,
};
static int ad5449_write(struct iio_dev *indio_dev, unsigned int addr,
unsigned int val)
{
struct ad5449 *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
st->data[0] = cpu_to_be16((addr << 12) | val);
ret = spi_write(st->spi, st->data, 2);
mutex_unlock(&st->lock);
return ret;
}
static int ad5449_read(struct iio_dev *indio_dev, unsigned int addr,
unsigned int *val)
{
struct ad5449 *st = iio_priv(indio_dev);
int ret;
struct spi_transfer t[] = {
{
.tx_buf = &st->data[0],
.len = 2,
.cs_change = 1,
}, {
.tx_buf = &st->data[1],
.rx_buf = &st->data[1],
.len = 2,
},
};
mutex_lock(&st->lock);
st->data[0] = cpu_to_be16(addr << 12);
st->data[1] = cpu_to_be16(AD5449_CMD_NOOP);
ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
if (ret < 0)
goto out_unlock;
*val = be16_to_cpu(st->data[1]);
out_unlock:
mutex_unlock(&st->lock);
return ret;
}
static int ad5449_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long info)
{
struct ad5449 *st = iio_priv(indio_dev);
struct regulator_bulk_data *reg;
int scale_uv;
int ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
if (st->has_sdo) {
ret = ad5449_read(indio_dev,
AD5449_CMD_READ(chan->address), val);
if (ret)
return ret;
*val &= 0xfff;
} else {
*val = st->dac_cache[chan->address];
}
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
reg = &st->vref_reg[chan->channel];
scale_uv = regulator_get_voltage(reg->consumer);
if (scale_uv < 0)
return scale_uv;
*val = scale_uv / 1000;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
default:
break;
}
return -EINVAL;
}
static int ad5449_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long info)
{
struct ad5449 *st = iio_priv(indio_dev);
int ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
if (val < 0 || val >= (1 << chan->scan_type.realbits))
return -EINVAL;
ret = ad5449_write(indio_dev,
AD5449_CMD_LOAD_AND_UPDATE(chan->address),
val << chan->scan_type.shift);
if (ret == 0)
st->dac_cache[chan->address] = val;
break;
default:
ret = -EINVAL;
}
return ret;
}
static const struct iio_info ad5449_info = {
.read_raw = ad5449_read_raw,
.write_raw = ad5449_write_raw,
};
#define AD5449_CHANNEL(chan, bits) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.address = (chan), \
.scan_type = { \
.sign = 'u', \
.realbits = (bits), \
.storagebits = 16, \
.shift = 12 - (bits), \
}, \
}
#define DECLARE_AD5449_CHANNELS(name, bits) \
const struct iio_chan_spec name[] = { \
AD5449_CHANNEL(0, bits), \
AD5449_CHANNEL(1, bits), \
}
static DECLARE_AD5449_CHANNELS(ad5429_channels, 8);
static DECLARE_AD5449_CHANNELS(ad5439_channels, 10);
static DECLARE_AD5449_CHANNELS(ad5449_channels, 12);
static const struct ad5449_chip_info ad5449_chip_info[] = {
[ID_AD5426] = {
.channels = ad5429_channels,
.num_channels = 1,
.has_ctrl = false,
},
[ID_AD5429] = {
.channels = ad5429_channels,
.num_channels = 2,
.has_ctrl = true,
},
[ID_AD5432] = {
.channels = ad5439_channels,
.num_channels = 1,
.has_ctrl = false,
},
[ID_AD5439] = {
.channels = ad5439_channels,
.num_channels = 2,
.has_ctrl = true,
},
[ID_AD5443] = {
.channels = ad5449_channels,
.num_channels = 1,
.has_ctrl = false,
},
[ID_AD5449] = {
.channels = ad5449_channels,
.num_channels = 2,
.has_ctrl = true,
},
};
static const char *ad5449_vref_name(struct ad5449 *st, int n)
{
if (st->chip_info->num_channels == 1)
return "VREF";
if (n == 0)
return "VREFA";
else
return "VREFB";
}
static int ad5449_spi_probe(struct spi_device *spi)
{
struct ad5449_platform_data *pdata = spi->dev.platform_data;
const struct spi_device_id *id = spi_get_device_id(spi);
struct iio_dev *indio_dev;
struct ad5449 *st;
unsigned int i;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (indio_dev == NULL)
return -ENOMEM;
st = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
st->chip_info = &ad5449_chip_info[id->driver_data];
st->spi = spi;
for (i = 0; i < st->chip_info->num_channels; ++i)
st->vref_reg[i].supply = ad5449_vref_name(st, i);
ret = devm_regulator_bulk_get(&spi->dev, st->chip_info->num_channels,
st->vref_reg);
if (ret)
return ret;
ret = regulator_bulk_enable(st->chip_info->num_channels, st->vref_reg);
if (ret)
return ret;
indio_dev->name = id->name;
indio_dev->info = &ad5449_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = st->chip_info->channels;
indio_dev->num_channels = st->chip_info->num_channels;
mutex_init(&st->lock);
if (st->chip_info->has_ctrl) {
unsigned int ctrl = 0x00;
if (pdata) {
if (pdata->hardware_clear_to_midscale)
ctrl |= AD5449_CTRL_HCLR_TO_MIDSCALE;
ctrl |= pdata->sdo_mode << AD5449_CTRL_SDO_OFFSET;
st->has_sdo = pdata->sdo_mode != AD5449_SDO_DISABLED;
} else {
st->has_sdo = true;
}
ad5449_write(indio_dev, AD5449_CMD_CTRL, ctrl);
}
ret = iio_device_register(indio_dev);
if (ret)
goto error_disable_reg;
return 0;
error_disable_reg:
regulator_bulk_disable(st->chip_info->num_channels, st->vref_reg);
return ret;
}
static void ad5449_spi_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ad5449 *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
regulator_bulk_disable(st->chip_info->num_channels, st->vref_reg);
}
static const struct spi_device_id ad5449_spi_ids[] = {
{ "ad5415", ID_AD5449 },
{ "ad5426", ID_AD5426 },
{ "ad5429", ID_AD5429 },
{ "ad5432", ID_AD5432 },
{ "ad5439", ID_AD5439 },
{ "ad5443", ID_AD5443 },
{ "ad5449", ID_AD5449 },
{}
};
MODULE_DEVICE_TABLE(spi, ad5449_spi_ids);
static struct spi_driver ad5449_spi_driver = {
.driver = {
.name = "ad5449",
},
.probe = ad5449_spi_probe,
.remove = ad5449_spi_remove,
.id_table = ad5449_spi_ids,
};
module_spi_driver(ad5449_spi_driver);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5449 and similar DACs");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5449.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Analog Devices AD5766, AD5767
* Digital to Analog Converters driver
* Copyright 2019-2020 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <asm/unaligned.h>
#define AD5766_UPPER_WORD_SPI_MASK GENMASK(31, 16)
#define AD5766_LOWER_WORD_SPI_MASK GENMASK(15, 0)
#define AD5766_DITHER_SOURCE_MASK(ch) GENMASK(((2 * ch) + 1), (2 * ch))
#define AD5766_DITHER_SOURCE(ch, source) BIT((ch * 2) + source)
#define AD5766_DITHER_SCALE_MASK(x) AD5766_DITHER_SOURCE_MASK(x)
#define AD5766_DITHER_SCALE(ch, scale) (scale << (ch * 2))
#define AD5766_DITHER_ENABLE_MASK(ch) BIT(ch)
#define AD5766_DITHER_ENABLE(ch, state) ((!state) << ch)
#define AD5766_DITHER_INVERT_MASK(ch) BIT(ch)
#define AD5766_DITHER_INVERT(ch, state) (state << ch)
#define AD5766_CMD_NOP_MUX_OUT 0x00
#define AD5766_CMD_SDO_CNTRL 0x01
#define AD5766_CMD_WR_IN_REG(x) (0x10 | ((x) & GENMASK(3, 0)))
#define AD5766_CMD_WR_DAC_REG(x) (0x20 | ((x) & GENMASK(3, 0)))
#define AD5766_CMD_SW_LDAC 0x30
#define AD5766_CMD_SPAN_REG 0x40
#define AD5766_CMD_WR_PWR_DITHER 0x51
#define AD5766_CMD_WR_DAC_REG_ALL 0x60
#define AD5766_CMD_SW_FULL_RESET 0x70
#define AD5766_CMD_READBACK_REG(x) (0x80 | ((x) & GENMASK(3, 0)))
#define AD5766_CMD_DITHER_SIG_1 0x90
#define AD5766_CMD_DITHER_SIG_2 0xA0
#define AD5766_CMD_INV_DITHER 0xB0
#define AD5766_CMD_DITHER_SCALE_1 0xC0
#define AD5766_CMD_DITHER_SCALE_2 0xD0
#define AD5766_FULL_RESET_CODE 0x1234
enum ad5766_type {
ID_AD5766,
ID_AD5767,
};
enum ad5766_voltage_range {
AD5766_VOLTAGE_RANGE_M20V_0V,
AD5766_VOLTAGE_RANGE_M16V_to_0V,
AD5766_VOLTAGE_RANGE_M10V_to_0V,
AD5766_VOLTAGE_RANGE_M12V_to_14V,
AD5766_VOLTAGE_RANGE_M16V_to_10V,
AD5766_VOLTAGE_RANGE_M10V_to_6V,
AD5766_VOLTAGE_RANGE_M5V_to_5V,
AD5766_VOLTAGE_RANGE_M10V_to_10V,
};
/**
* struct ad5766_chip_info - chip specific information
* @num_channels: number of channels
* @channels: channel specification
*/
struct ad5766_chip_info {
unsigned int num_channels;
const struct iio_chan_spec *channels;
};
enum {
AD5766_DITHER_ENABLE,
AD5766_DITHER_INVERT,
AD5766_DITHER_SOURCE,
};
/*
* Dither signal can also be scaled.
* Available dither scale strings corresponding to "dither_scale" field in
* "struct ad5766_state".
*/
static const char * const ad5766_dither_scales[] = {
"1",
"0.75",
"0.5",
"0.25",
};
/**
* struct ad5766_state - driver instance specific data
* @spi: SPI device
* @lock: Lock used to restrict concurrent access to SPI device
* @chip_info: Chip model specific constants
* @gpio_reset: Reset GPIO, used to reset the device
* @crt_range: Current selected output range
* @dither_enable: Power enable bit for each channel dither block (for
* example, D15 = DAC 15,D8 = DAC 8, and D0 = DAC 0)
* 0 - Normal operation, 1 - Power down
* @dither_invert: Inverts the dither signal applied to the selected DAC
* outputs
* @dither_source: Selects between 2 possible sources:
* 1: N0, 2: N1
* Two bits are used for each channel
* @dither_scale: Two bits are used for each of the 16 channels:
* 0: 1 SCALING, 1: 0.75 SCALING, 2: 0.5 SCALING,
* 3: 0.25 SCALING.
* @data: SPI transfer buffers
*/
struct ad5766_state {
struct spi_device *spi;
struct mutex lock;
const struct ad5766_chip_info *chip_info;
struct gpio_desc *gpio_reset;
enum ad5766_voltage_range crt_range;
u16 dither_enable;
u16 dither_invert;
u32 dither_source;
u32 dither_scale;
union {
u32 d32;
u16 w16[2];
u8 b8[4];
} data[3] __aligned(IIO_DMA_MINALIGN);
};
struct ad5766_span_tbl {
int min;
int max;
};
static const struct ad5766_span_tbl ad5766_span_tbl[] = {
[AD5766_VOLTAGE_RANGE_M20V_0V] = {-20, 0},
[AD5766_VOLTAGE_RANGE_M16V_to_0V] = {-16, 0},
[AD5766_VOLTAGE_RANGE_M10V_to_0V] = {-10, 0},
[AD5766_VOLTAGE_RANGE_M12V_to_14V] = {-12, 14},
[AD5766_VOLTAGE_RANGE_M16V_to_10V] = {-16, 10},
[AD5766_VOLTAGE_RANGE_M10V_to_6V] = {-10, 6},
[AD5766_VOLTAGE_RANGE_M5V_to_5V] = {-5, 5},
[AD5766_VOLTAGE_RANGE_M10V_to_10V] = {-10, 10},
};
static int __ad5766_spi_read(struct ad5766_state *st, u8 dac, int *val)
{
int ret;
struct spi_transfer xfers[] = {
{
.tx_buf = &st->data[0].d32,
.bits_per_word = 8,
.len = 3,
.cs_change = 1,
}, {
.tx_buf = &st->data[1].d32,
.rx_buf = &st->data[2].d32,
.bits_per_word = 8,
.len = 3,
},
};
st->data[0].d32 = AD5766_CMD_READBACK_REG(dac);
st->data[1].d32 = AD5766_CMD_NOP_MUX_OUT;
ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
if (ret)
return ret;
*val = st->data[2].w16[1];
return ret;
}
static int __ad5766_spi_write(struct ad5766_state *st, u8 command, u16 data)
{
st->data[0].b8[0] = command;
put_unaligned_be16(data, &st->data[0].b8[1]);
return spi_write(st->spi, &st->data[0].b8[0], 3);
}
static int ad5766_read(struct iio_dev *indio_dev, u8 dac, int *val)
{
struct ad5766_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
ret = __ad5766_spi_read(st, dac, val);
mutex_unlock(&st->lock);
return ret;
}
static int ad5766_write(struct iio_dev *indio_dev, u8 dac, u16 data)
{
struct ad5766_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
ret = __ad5766_spi_write(st, AD5766_CMD_WR_DAC_REG(dac), data);
mutex_unlock(&st->lock);
return ret;
}
static int ad5766_reset(struct ad5766_state *st)
{
int ret;
if (st->gpio_reset) {
gpiod_set_value_cansleep(st->gpio_reset, 1);
ndelay(100); /* t_reset >= 100ns */
gpiod_set_value_cansleep(st->gpio_reset, 0);
} else {
ret = __ad5766_spi_write(st, AD5766_CMD_SW_FULL_RESET,
AD5766_FULL_RESET_CODE);
if (ret < 0)
return ret;
}
/*
* Minimum time between a reset and the subsequent successful write is
* typically 25 ns
*/
ndelay(25);
return 0;
}
static int ad5766_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct ad5766_state *st = iio_priv(indio_dev);
int ret;
switch (m) {
case IIO_CHAN_INFO_RAW:
ret = ad5766_read(indio_dev, chan->address, val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
*val = ad5766_span_tbl[st->crt_range].min;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = ad5766_span_tbl[st->crt_range].max -
ad5766_span_tbl[st->crt_range].min;
*val2 = st->chip_info->channels[0].scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
}
static int ad5766_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long info)
{
switch (info) {
case IIO_CHAN_INFO_RAW:
{
const int max_val = GENMASK(chan->scan_type.realbits - 1, 0);
if (val > max_val || val < 0)
return -EINVAL;
val <<= chan->scan_type.shift;
return ad5766_write(indio_dev, chan->address, val);
}
default:
return -EINVAL;
}
}
static const struct iio_info ad5766_info = {
.read_raw = ad5766_read_raw,
.write_raw = ad5766_write_raw,
};
static int ad5766_get_dither_source(struct iio_dev *dev,
const struct iio_chan_spec *chan)
{
struct ad5766_state *st = iio_priv(dev);
u32 source;
source = st->dither_source & AD5766_DITHER_SOURCE_MASK(chan->channel);
source = source >> (chan->channel * 2);
source -= 1;
return source;
}
static int ad5766_set_dither_source(struct iio_dev *dev,
const struct iio_chan_spec *chan,
unsigned int source)
{
struct ad5766_state *st = iio_priv(dev);
uint16_t val;
int ret;
st->dither_source &= ~AD5766_DITHER_SOURCE_MASK(chan->channel);
st->dither_source |= AD5766_DITHER_SOURCE(chan->channel, source);
val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source);
ret = ad5766_write(dev, AD5766_CMD_DITHER_SIG_1, val);
if (ret)
return ret;
val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source);
return ad5766_write(dev, AD5766_CMD_DITHER_SIG_2, val);
}
static int ad5766_get_dither_scale(struct iio_dev *dev,
const struct iio_chan_spec *chan)
{
struct ad5766_state *st = iio_priv(dev);
u32 scale;
scale = st->dither_scale & AD5766_DITHER_SCALE_MASK(chan->channel);
return (scale >> (chan->channel * 2));
}
static int ad5766_set_dither_scale(struct iio_dev *dev,
const struct iio_chan_spec *chan,
unsigned int scale)
{
int ret;
struct ad5766_state *st = iio_priv(dev);
uint16_t val;
st->dither_scale &= ~AD5766_DITHER_SCALE_MASK(chan->channel);
st->dither_scale |= AD5766_DITHER_SCALE(chan->channel, scale);
val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale);
ret = ad5766_write(dev, AD5766_CMD_DITHER_SCALE_1, val);
if (ret)
return ret;
val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale);
return ad5766_write(dev, AD5766_CMD_DITHER_SCALE_2, val);
}
static const struct iio_enum ad5766_dither_scale_enum = {
.items = ad5766_dither_scales,
.num_items = ARRAY_SIZE(ad5766_dither_scales),
.set = ad5766_set_dither_scale,
.get = ad5766_get_dither_scale,
};
static ssize_t ad5766_read_ext(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct ad5766_state *st = iio_priv(indio_dev);
switch (private) {
case AD5766_DITHER_ENABLE:
return sprintf(buf, "%u\n",
!(st->dither_enable & BIT(chan->channel)));
break;
case AD5766_DITHER_INVERT:
return sprintf(buf, "%u\n",
!!(st->dither_invert & BIT(chan->channel)));
break;
case AD5766_DITHER_SOURCE:
return sprintf(buf, "%d\n",
ad5766_get_dither_source(indio_dev, chan));
default:
return -EINVAL;
}
}
static ssize_t ad5766_write_ext(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct ad5766_state *st = iio_priv(indio_dev);
bool readin;
int ret;
ret = kstrtobool(buf, &readin);
if (ret)
return ret;
switch (private) {
case AD5766_DITHER_ENABLE:
st->dither_enable &= ~AD5766_DITHER_ENABLE_MASK(chan->channel);
st->dither_enable |= AD5766_DITHER_ENABLE(chan->channel,
readin);
ret = ad5766_write(indio_dev, AD5766_CMD_WR_PWR_DITHER,
st->dither_enable);
break;
case AD5766_DITHER_INVERT:
st->dither_invert &= ~AD5766_DITHER_INVERT_MASK(chan->channel);
st->dither_invert |= AD5766_DITHER_INVERT(chan->channel,
readin);
ret = ad5766_write(indio_dev, AD5766_CMD_INV_DITHER,
st->dither_invert);
break;
case AD5766_DITHER_SOURCE:
ret = ad5766_set_dither_source(indio_dev, chan, readin);
break;
default:
return -EINVAL;
}
return ret ? ret : len;
}
#define _AD5766_CHAN_EXT_INFO(_name, _what, _shared) { \
.name = _name, \
.read = ad5766_read_ext, \
.write = ad5766_write_ext, \
.private = _what, \
.shared = _shared, \
}
static const struct iio_chan_spec_ext_info ad5766_ext_info[] = {
_AD5766_CHAN_EXT_INFO("dither_enable", AD5766_DITHER_ENABLE,
IIO_SEPARATE),
_AD5766_CHAN_EXT_INFO("dither_invert", AD5766_DITHER_INVERT,
IIO_SEPARATE),
_AD5766_CHAN_EXT_INFO("dither_source", AD5766_DITHER_SOURCE,
IIO_SEPARATE),
IIO_ENUM("dither_scale", IIO_SEPARATE, &ad5766_dither_scale_enum),
IIO_ENUM_AVAILABLE("dither_scale", IIO_SEPARATE,
&ad5766_dither_scale_enum),
{}
};
#define AD576x_CHANNEL(_chan, _bits) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (_chan), \
.address = (_chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_SCALE), \
.scan_index = (_chan), \
.scan_type = { \
.sign = 'u', \
.realbits = (_bits), \
.storagebits = 16, \
.shift = 16 - (_bits), \
}, \
.ext_info = ad5766_ext_info, \
}
#define DECLARE_AD576x_CHANNELS(_name, _bits) \
const struct iio_chan_spec _name[] = { \
AD576x_CHANNEL(0, (_bits)), \
AD576x_CHANNEL(1, (_bits)), \
AD576x_CHANNEL(2, (_bits)), \
AD576x_CHANNEL(3, (_bits)), \
AD576x_CHANNEL(4, (_bits)), \
AD576x_CHANNEL(5, (_bits)), \
AD576x_CHANNEL(6, (_bits)), \
AD576x_CHANNEL(7, (_bits)), \
AD576x_CHANNEL(8, (_bits)), \
AD576x_CHANNEL(9, (_bits)), \
AD576x_CHANNEL(10, (_bits)), \
AD576x_CHANNEL(11, (_bits)), \
AD576x_CHANNEL(12, (_bits)), \
AD576x_CHANNEL(13, (_bits)), \
AD576x_CHANNEL(14, (_bits)), \
AD576x_CHANNEL(15, (_bits)), \
}
static DECLARE_AD576x_CHANNELS(ad5766_channels, 16);
static DECLARE_AD576x_CHANNELS(ad5767_channels, 12);
static const struct ad5766_chip_info ad5766_chip_infos[] = {
[ID_AD5766] = {
.num_channels = ARRAY_SIZE(ad5766_channels),
.channels = ad5766_channels,
},
[ID_AD5767] = {
.num_channels = ARRAY_SIZE(ad5767_channels),
.channels = ad5767_channels,
},
};
static int ad5766_get_output_range(struct ad5766_state *st)
{
int i, ret, min, max, tmp[2];
ret = device_property_read_u32_array(&st->spi->dev,
"output-range-microvolts",
tmp, 2);
if (ret)
return ret;
min = tmp[0] / 1000000;
max = tmp[1] / 1000000;
for (i = 0; i < ARRAY_SIZE(ad5766_span_tbl); i++) {
if (ad5766_span_tbl[i].min != min ||
ad5766_span_tbl[i].max != max)
continue;
st->crt_range = i;
return 0;
}
return -EINVAL;
}
static int ad5766_default_setup(struct ad5766_state *st)
{
uint16_t val;
int ret, i;
/* Always issue a reset before writing to the span register. */
ret = ad5766_reset(st);
if (ret)
return ret;
ret = ad5766_get_output_range(st);
if (ret)
return ret;
/* Dither power down */
st->dither_enable = GENMASK(15, 0);
ret = __ad5766_spi_write(st, AD5766_CMD_WR_PWR_DITHER,
st->dither_enable);
if (ret)
return ret;
st->dither_source = 0;
for (i = 0; i < ARRAY_SIZE(ad5766_channels); i++)
st->dither_source |= AD5766_DITHER_SOURCE(i, 0);
val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source);
ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_1, val);
if (ret)
return ret;
val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source);
ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_2, val);
if (ret)
return ret;
st->dither_scale = 0;
val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale);
ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_1, val);
if (ret)
return ret;
val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale);
ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_2, val);
if (ret)
return ret;
st->dither_invert = 0;
ret = __ad5766_spi_write(st, AD5766_CMD_INV_DITHER, st->dither_invert);
if (ret)
return ret;
return __ad5766_spi_write(st, AD5766_CMD_SPAN_REG, st->crt_range);
}
static irqreturn_t ad5766_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct iio_buffer *buffer = indio_dev->buffer;
struct ad5766_state *st = iio_priv(indio_dev);
int ret, ch, i;
u16 data[ARRAY_SIZE(ad5766_channels)];
ret = iio_pop_from_buffer(buffer, data);
if (ret)
goto done;
i = 0;
mutex_lock(&st->lock);
for_each_set_bit(ch, indio_dev->active_scan_mask,
st->chip_info->num_channels - 1)
__ad5766_spi_write(st, AD5766_CMD_WR_IN_REG(ch), data[i++]);
__ad5766_spi_write(st, AD5766_CMD_SW_LDAC,
*indio_dev->active_scan_mask);
mutex_unlock(&st->lock);
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int ad5766_probe(struct spi_device *spi)
{
enum ad5766_type type;
struct iio_dev *indio_dev;
struct ad5766_state *st;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
mutex_init(&st->lock);
st->spi = spi;
type = spi_get_device_id(spi)->driver_data;
st->chip_info = &ad5766_chip_infos[type];
indio_dev->channels = st->chip_info->channels;
indio_dev->num_channels = st->chip_info->num_channels;
indio_dev->info = &ad5766_info;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(st->gpio_reset))
return PTR_ERR(st->gpio_reset);
ret = ad5766_default_setup(st);
if (ret)
return ret;
/* Configure trigger buffer */
ret = devm_iio_triggered_buffer_setup_ext(&spi->dev, indio_dev, NULL,
ad5766_trigger_handler,
IIO_BUFFER_DIRECTION_OUT,
NULL,
NULL);
if (ret)
return ret;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct of_device_id ad5766_dt_match[] = {
{ .compatible = "adi,ad5766" },
{ .compatible = "adi,ad5767" },
{}
};
MODULE_DEVICE_TABLE(of, ad5766_dt_match);
static const struct spi_device_id ad5766_spi_ids[] = {
{ "ad5766", ID_AD5766 },
{ "ad5767", ID_AD5767 },
{}
};
MODULE_DEVICE_TABLE(spi, ad5766_spi_ids);
static struct spi_driver ad5766_driver = {
.driver = {
.name = "ad5766",
.of_match_table = ad5766_dt_match,
},
.probe = ad5766_probe,
.id_table = ad5766_spi_ids,
};
module_spi_driver(ad5766_driver);
MODULE_AUTHOR("Denis-Gabriel Gheorghescu <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5766/AD5767 DACs");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5766.c |
// SPDX-License-Identifier: GPL-2.0
/*
* DAC7612 Dual, 12-Bit Serial input Digital-to-Analog Converter
*
* Copyright 2019 Qtechnology A/S
* 2019 Ricardo Ribalda <[email protected]>
*
* Licensed under the GPL-2.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <linux/gpio/consumer.h>
#include <linux/iio/iio.h>
#define DAC7612_RESOLUTION 12
#define DAC7612_ADDRESS 4
#define DAC7612_START 5
struct dac7612 {
struct spi_device *spi;
struct gpio_desc *loaddacs;
uint16_t cache[2];
/*
* Lock to protect the state of the device from potential concurrent
* write accesses from userspace. The write operation requires an
* SPI write, then toggling of a GPIO, so the lock aims to protect
* the sanity of the entire sequence of operation.
*/
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
uint8_t data[2] __aligned(IIO_DMA_MINALIGN);
};
static int dac7612_cmd_single(struct dac7612 *priv, int channel, u16 val)
{
int ret;
priv->data[0] = BIT(DAC7612_START) | (channel << DAC7612_ADDRESS);
priv->data[0] |= val >> 8;
priv->data[1] = val & 0xff;
priv->cache[channel] = val;
ret = spi_write(priv->spi, priv->data, sizeof(priv->data));
if (ret)
return ret;
gpiod_set_value(priv->loaddacs, 1);
gpiod_set_value(priv->loaddacs, 0);
return 0;
}
#define dac7612_CHANNEL(chan, name) { \
.type = IIO_VOLTAGE, \
.channel = (chan), \
.indexed = 1, \
.output = 1, \
.datasheet_name = name, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
}
static const struct iio_chan_spec dac7612_channels[] = {
dac7612_CHANNEL(0, "OUTA"),
dac7612_CHANNEL(1, "OUTB"),
};
static int dac7612_read_raw(struct iio_dev *iio_dev,
const struct iio_chan_spec *chan,
int *val, int *val2, long mask)
{
struct dac7612 *priv;
switch (mask) {
case IIO_CHAN_INFO_RAW:
priv = iio_priv(iio_dev);
*val = priv->cache[chan->channel];
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 1;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int dac7612_write_raw(struct iio_dev *iio_dev,
const struct iio_chan_spec *chan,
int val, int val2, long mask)
{
struct dac7612 *priv = iio_priv(iio_dev);
int ret;
if (mask != IIO_CHAN_INFO_RAW)
return -EINVAL;
if ((val >= BIT(DAC7612_RESOLUTION)) || val < 0 || val2)
return -EINVAL;
if (val == priv->cache[chan->channel])
return 0;
mutex_lock(&priv->lock);
ret = dac7612_cmd_single(priv, chan->channel, val);
mutex_unlock(&priv->lock);
return ret;
}
static const struct iio_info dac7612_info = {
.read_raw = dac7612_read_raw,
.write_raw = dac7612_write_raw,
};
static int dac7612_probe(struct spi_device *spi)
{
struct iio_dev *iio_dev;
struct dac7612 *priv;
int i;
int ret;
iio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*priv));
if (!iio_dev)
return -ENOMEM;
priv = iio_priv(iio_dev);
/*
* LOADDACS pin can be controlled by the driver or externally.
* When controlled by the driver, the DAC value is updated after
* every write.
* When the driver does not control the PIN, the user or an external
* event can change the value of all DACs by pulsing down the LOADDACs
* pin.
*/
priv->loaddacs = devm_gpiod_get_optional(&spi->dev, "ti,loaddacs",
GPIOD_OUT_LOW);
if (IS_ERR(priv->loaddacs))
return PTR_ERR(priv->loaddacs);
priv->spi = spi;
spi_set_drvdata(spi, iio_dev);
iio_dev->info = &dac7612_info;
iio_dev->modes = INDIO_DIRECT_MODE;
iio_dev->channels = dac7612_channels;
iio_dev->num_channels = ARRAY_SIZE(priv->cache);
iio_dev->name = spi_get_device_id(spi)->name;
mutex_init(&priv->lock);
for (i = 0; i < ARRAY_SIZE(priv->cache); i++) {
ret = dac7612_cmd_single(priv, i, 0);
if (ret)
return ret;
}
return devm_iio_device_register(&spi->dev, iio_dev);
}
static const struct spi_device_id dac7612_id[] = {
{"ti-dac7612"},
{}
};
MODULE_DEVICE_TABLE(spi, dac7612_id);
static const struct of_device_id dac7612_of_match[] = {
{ .compatible = "ti,dac7612" },
{ .compatible = "ti,dac7612u" },
{ .compatible = "ti,dac7612ub" },
{ },
};
MODULE_DEVICE_TABLE(of, dac7612_of_match);
static struct spi_driver dac7612_driver = {
.driver = {
.name = "ti-dac7612",
.of_match_table = dac7612_of_match,
},
.probe = dac7612_probe,
.id_table = dac7612_id,
};
module_spi_driver(dac7612_driver);
MODULE_AUTHOR("Ricardo Ribalda <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments DAC7612 DAC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ti-dac7612.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ti-dac082s085.c - Texas Instruments 8/10/12-bit 2/4-channel DAC driver
*
* Copyright (C) 2017 KUNBUS GmbH
*
* https://www.ti.com/lit/ds/symlink/dac082s085.pdf
* https://www.ti.com/lit/ds/symlink/dac102s085.pdf
* https://www.ti.com/lit/ds/symlink/dac122s085.pdf
* https://www.ti.com/lit/ds/symlink/dac084s085.pdf
* https://www.ti.com/lit/ds/symlink/dac104s085.pdf
* https://www.ti.com/lit/ds/symlink/dac124s085.pdf
*/
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
enum { dual_8bit, dual_10bit, dual_12bit, quad_8bit, quad_10bit, quad_12bit };
struct ti_dac_spec {
u8 num_channels;
u8 resolution;
};
static const struct ti_dac_spec ti_dac_spec[] = {
[dual_8bit] = { .num_channels = 2, .resolution = 8 },
[dual_10bit] = { .num_channels = 2, .resolution = 10 },
[dual_12bit] = { .num_channels = 2, .resolution = 12 },
[quad_8bit] = { .num_channels = 4, .resolution = 8 },
[quad_10bit] = { .num_channels = 4, .resolution = 10 },
[quad_12bit] = { .num_channels = 4, .resolution = 12 },
};
/**
* struct ti_dac_chip - TI DAC chip
* @lock: protects write sequences
* @vref: regulator generating Vref
* @mesg: SPI message to perform a write
* @xfer: SPI transfer used by @mesg
* @val: cached value of each output
* @powerdown: whether the chip is powered down
* @powerdown_mode: selected by the user
* @resolution: resolution of the chip
* @buf: buffer for @xfer
*/
struct ti_dac_chip {
struct mutex lock;
struct regulator *vref;
struct spi_message mesg;
struct spi_transfer xfer;
u16 val[4];
bool powerdown;
u8 powerdown_mode;
u8 resolution;
u8 buf[2] __aligned(IIO_DMA_MINALIGN);
};
#define WRITE_NOT_UPDATE(chan) (0x00 | (chan) << 6)
#define WRITE_AND_UPDATE(chan) (0x10 | (chan) << 6)
#define WRITE_ALL_UPDATE 0x20
#define POWERDOWN(mode) (0x30 | ((mode) + 1) << 6)
static int ti_dac_cmd(struct ti_dac_chip *ti_dac, u8 cmd, u16 val)
{
u8 shift = 12 - ti_dac->resolution;
ti_dac->buf[0] = cmd | (val >> (8 - shift));
ti_dac->buf[1] = (val << shift) & 0xff;
return spi_sync(ti_dac->mesg.spi, &ti_dac->mesg);
}
static const char * const ti_dac_powerdown_modes[] = {
"2.5kohm_to_gnd", "100kohm_to_gnd", "three_state",
};
static int ti_dac_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
return ti_dac->powerdown_mode;
}
static int ti_dac_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int mode)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
int ret = 0;
if (ti_dac->powerdown_mode == mode)
return 0;
mutex_lock(&ti_dac->lock);
if (ti_dac->powerdown) {
ret = ti_dac_cmd(ti_dac, POWERDOWN(mode), 0);
if (ret)
goto out;
}
ti_dac->powerdown_mode = mode;
out:
mutex_unlock(&ti_dac->lock);
return ret;
}
static const struct iio_enum ti_dac_powerdown_mode = {
.items = ti_dac_powerdown_modes,
.num_items = ARRAY_SIZE(ti_dac_powerdown_modes),
.get = ti_dac_get_powerdown_mode,
.set = ti_dac_set_powerdown_mode,
};
static ssize_t ti_dac_read_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", ti_dac->powerdown);
}
static ssize_t ti_dac_write_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
bool powerdown;
int ret;
ret = kstrtobool(buf, &powerdown);
if (ret)
return ret;
if (ti_dac->powerdown == powerdown)
return len;
mutex_lock(&ti_dac->lock);
if (powerdown)
ret = ti_dac_cmd(ti_dac, POWERDOWN(ti_dac->powerdown_mode), 0);
else
ret = ti_dac_cmd(ti_dac, WRITE_AND_UPDATE(0), ti_dac->val[0]);
if (!ret)
ti_dac->powerdown = powerdown;
mutex_unlock(&ti_dac->lock);
return ret ? ret : len;
}
static const struct iio_chan_spec_ext_info ti_dac_ext_info[] = {
{
.name = "powerdown",
.read = ti_dac_read_powerdown,
.write = ti_dac_write_powerdown,
.shared = IIO_SHARED_BY_TYPE,
},
IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE, &ti_dac_powerdown_mode),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ti_dac_powerdown_mode),
{ },
};
#define TI_DAC_CHANNEL(chan) { \
.type = IIO_VOLTAGE, \
.channel = (chan), \
.address = (chan), \
.indexed = true, \
.output = true, \
.datasheet_name = (const char[]){ 'A' + (chan), 0 }, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.ext_info = ti_dac_ext_info, \
}
static const struct iio_chan_spec ti_dac_channels[] = {
TI_DAC_CHANNEL(0),
TI_DAC_CHANNEL(1),
TI_DAC_CHANNEL(2),
TI_DAC_CHANNEL(3),
};
static int ti_dac_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
*val = ti_dac->val[chan->channel];
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SCALE:
ret = regulator_get_voltage(ti_dac->vref);
if (ret < 0)
return ret;
*val = ret / 1000;
*val2 = ti_dac->resolution;
ret = IIO_VAL_FRACTIONAL_LOG2;
break;
default:
ret = -EINVAL;
}
return ret;
}
static int ti_dac_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (ti_dac->val[chan->channel] == val)
return 0;
if (val >= (1 << ti_dac->resolution) || val < 0)
return -EINVAL;
if (ti_dac->powerdown)
return -EBUSY;
mutex_lock(&ti_dac->lock);
ret = ti_dac_cmd(ti_dac, WRITE_AND_UPDATE(chan->channel), val);
if (!ret)
ti_dac->val[chan->channel] = val;
mutex_unlock(&ti_dac->lock);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int ti_dac_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, long mask)
{
return IIO_VAL_INT;
}
static const struct iio_info ti_dac_info = {
.read_raw = ti_dac_read_raw,
.write_raw = ti_dac_write_raw,
.write_raw_get_fmt = ti_dac_write_raw_get_fmt,
};
static int ti_dac_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
const struct ti_dac_spec *spec;
struct ti_dac_chip *ti_dac;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*ti_dac));
if (!indio_dev)
return -ENOMEM;
indio_dev->info = &ti_dac_info;
indio_dev->name = spi->modalias;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ti_dac_channels;
spi_set_drvdata(spi, indio_dev);
ti_dac = iio_priv(indio_dev);
ti_dac->xfer.tx_buf = &ti_dac->buf;
ti_dac->xfer.len = sizeof(ti_dac->buf);
spi_message_init_with_transfers(&ti_dac->mesg, &ti_dac->xfer, 1);
ti_dac->mesg.spi = spi;
spec = &ti_dac_spec[spi_get_device_id(spi)->driver_data];
indio_dev->num_channels = spec->num_channels;
ti_dac->resolution = spec->resolution;
ti_dac->vref = devm_regulator_get(dev, "vref");
if (IS_ERR(ti_dac->vref))
return PTR_ERR(ti_dac->vref);
ret = regulator_enable(ti_dac->vref);
if (ret < 0)
return ret;
mutex_init(&ti_dac->lock);
ret = ti_dac_cmd(ti_dac, WRITE_ALL_UPDATE, 0);
if (ret) {
dev_err(dev, "failed to initialize outputs to 0\n");
goto err;
}
ret = iio_device_register(indio_dev);
if (ret)
goto err;
return 0;
err:
mutex_destroy(&ti_dac->lock);
regulator_disable(ti_dac->vref);
return ret;
}
static void ti_dac_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ti_dac_chip *ti_dac = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
mutex_destroy(&ti_dac->lock);
regulator_disable(ti_dac->vref);
}
static const struct of_device_id ti_dac_of_id[] = {
{ .compatible = "ti,dac082s085" },
{ .compatible = "ti,dac102s085" },
{ .compatible = "ti,dac122s085" },
{ .compatible = "ti,dac084s085" },
{ .compatible = "ti,dac104s085" },
{ .compatible = "ti,dac124s085" },
{ }
};
MODULE_DEVICE_TABLE(of, ti_dac_of_id);
static const struct spi_device_id ti_dac_spi_id[] = {
{ "dac082s085", dual_8bit },
{ "dac102s085", dual_10bit },
{ "dac122s085", dual_12bit },
{ "dac084s085", quad_8bit },
{ "dac104s085", quad_10bit },
{ "dac124s085", quad_12bit },
{ }
};
MODULE_DEVICE_TABLE(spi, ti_dac_spi_id);
static struct spi_driver ti_dac_driver = {
.driver = {
.name = "ti-dac082s085",
.of_match_table = ti_dac_of_id,
},
.probe = ti_dac_probe,
.remove = ti_dac_remove,
.id_table = ti_dac_spi_id,
};
module_spi_driver(ti_dac_driver);
MODULE_AUTHOR("Lukas Wunner <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments 8/10/12-bit 2/4-channel DAC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ti-dac082s085.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD5760, AD5780, AD5781, AD5790, AD5791 Voltage Output Digital to Analog
* Converter
*
* Copyright 2011 Analog Devices Inc.
*/
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/dac/ad5791.h>
#define AD5791_DAC_MASK GENMASK(19, 0)
#define AD5791_CMD_READ BIT(23)
#define AD5791_CMD_WRITE 0
#define AD5791_ADDR(addr) ((addr) << 20)
/* Registers */
#define AD5791_ADDR_NOOP 0
#define AD5791_ADDR_DAC0 1
#define AD5791_ADDR_CTRL 2
#define AD5791_ADDR_CLRCODE 3
#define AD5791_ADDR_SW_CTRL 4
/* Control Register */
#define AD5791_CTRL_RBUF BIT(1)
#define AD5791_CTRL_OPGND BIT(2)
#define AD5791_CTRL_DACTRI BIT(3)
#define AD5791_CTRL_BIN2SC BIT(4)
#define AD5791_CTRL_SDODIS BIT(5)
#define AD5761_CTRL_LINCOMP(x) ((x) << 6)
#define AD5791_LINCOMP_0_10 0
#define AD5791_LINCOMP_10_12 1
#define AD5791_LINCOMP_12_16 2
#define AD5791_LINCOMP_16_19 3
#define AD5791_LINCOMP_19_20 12
#define AD5780_LINCOMP_0_10 0
#define AD5780_LINCOMP_10_20 12
/* Software Control Register */
#define AD5791_SWCTRL_LDAC BIT(0)
#define AD5791_SWCTRL_CLR BIT(1)
#define AD5791_SWCTRL_RESET BIT(2)
#define AD5791_DAC_PWRDN_6K 0
#define AD5791_DAC_PWRDN_3STATE 1
/**
* struct ad5791_chip_info - chip specific information
* @get_lin_comp: function pointer to the device specific function
*/
struct ad5791_chip_info {
int (*get_lin_comp) (unsigned int span);
};
/**
* struct ad5791_state - driver instance specific data
* @spi: spi_device
* @reg_vdd: positive supply regulator
* @reg_vss: negative supply regulator
* @chip_info: chip model specific constants
* @vref_mv: actual reference voltage used
* @vref_neg_mv: voltage of the negative supply
* @ctrl: control register cache
* @pwr_down_mode: current power down mode
* @pwr_down: true if device is powered down
* @data: spi transfer buffers
*/
struct ad5791_state {
struct spi_device *spi;
struct regulator *reg_vdd;
struct regulator *reg_vss;
const struct ad5791_chip_info *chip_info;
unsigned short vref_mv;
unsigned int vref_neg_mv;
unsigned ctrl;
unsigned pwr_down_mode;
bool pwr_down;
union {
__be32 d32;
u8 d8[4];
} data[3] __aligned(IIO_DMA_MINALIGN);
};
enum ad5791_supported_device_ids {
ID_AD5760,
ID_AD5780,
ID_AD5781,
ID_AD5791,
};
static int ad5791_spi_write(struct ad5791_state *st, u8 addr, u32 val)
{
st->data[0].d32 = cpu_to_be32(AD5791_CMD_WRITE |
AD5791_ADDR(addr) |
(val & AD5791_DAC_MASK));
return spi_write(st->spi, &st->data[0].d8[1], 3);
}
static int ad5791_spi_read(struct ad5791_state *st, u8 addr, u32 *val)
{
int ret;
struct spi_transfer xfers[] = {
{
.tx_buf = &st->data[0].d8[1],
.bits_per_word = 8,
.len = 3,
.cs_change = 1,
}, {
.tx_buf = &st->data[1].d8[1],
.rx_buf = &st->data[2].d8[1],
.bits_per_word = 8,
.len = 3,
},
};
st->data[0].d32 = cpu_to_be32(AD5791_CMD_READ |
AD5791_ADDR(addr));
st->data[1].d32 = cpu_to_be32(AD5791_ADDR(AD5791_ADDR_NOOP));
ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
*val = be32_to_cpu(st->data[2].d32);
return ret;
}
static const char * const ad5791_powerdown_modes[] = {
"6kohm_to_gnd",
"three_state",
};
static int ad5791_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct ad5791_state *st = iio_priv(indio_dev);
return st->pwr_down_mode;
}
static int ad5791_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, unsigned int mode)
{
struct ad5791_state *st = iio_priv(indio_dev);
st->pwr_down_mode = mode;
return 0;
}
static const struct iio_enum ad5791_powerdown_mode_enum = {
.items = ad5791_powerdown_modes,
.num_items = ARRAY_SIZE(ad5791_powerdown_modes),
.get = ad5791_get_powerdown_mode,
.set = ad5791_set_powerdown_mode,
};
static ssize_t ad5791_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
struct ad5791_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", st->pwr_down);
}
static ssize_t ad5791_write_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
size_t len)
{
bool pwr_down;
int ret;
struct ad5791_state *st = iio_priv(indio_dev);
ret = kstrtobool(buf, &pwr_down);
if (ret)
return ret;
if (!pwr_down) {
st->ctrl &= ~(AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI);
} else {
if (st->pwr_down_mode == AD5791_DAC_PWRDN_6K)
st->ctrl |= AD5791_CTRL_OPGND;
else if (st->pwr_down_mode == AD5791_DAC_PWRDN_3STATE)
st->ctrl |= AD5791_CTRL_DACTRI;
}
st->pwr_down = pwr_down;
ret = ad5791_spi_write(st, AD5791_ADDR_CTRL, st->ctrl);
return ret ? ret : len;
}
static int ad5791_get_lin_comp(unsigned int span)
{
if (span <= 10000)
return AD5791_LINCOMP_0_10;
else if (span <= 12000)
return AD5791_LINCOMP_10_12;
else if (span <= 16000)
return AD5791_LINCOMP_12_16;
else if (span <= 19000)
return AD5791_LINCOMP_16_19;
else
return AD5791_LINCOMP_19_20;
}
static int ad5780_get_lin_comp(unsigned int span)
{
if (span <= 10000)
return AD5780_LINCOMP_0_10;
else
return AD5780_LINCOMP_10_20;
}
static const struct ad5791_chip_info ad5791_chip_info_tbl[] = {
[ID_AD5760] = {
.get_lin_comp = ad5780_get_lin_comp,
},
[ID_AD5780] = {
.get_lin_comp = ad5780_get_lin_comp,
},
[ID_AD5781] = {
.get_lin_comp = ad5791_get_lin_comp,
},
[ID_AD5791] = {
.get_lin_comp = ad5791_get_lin_comp,
},
};
static int ad5791_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct ad5791_state *st = iio_priv(indio_dev);
u64 val64;
int ret;
switch (m) {
case IIO_CHAN_INFO_RAW:
ret = ad5791_spi_read(st, chan->address, val);
if (ret)
return ret;
*val &= AD5791_DAC_MASK;
*val >>= chan->scan_type.shift;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = st->vref_mv;
*val2 = (1 << chan->scan_type.realbits) - 1;
return IIO_VAL_FRACTIONAL;
case IIO_CHAN_INFO_OFFSET:
val64 = (((u64)st->vref_neg_mv) << chan->scan_type.realbits);
do_div(val64, st->vref_mv);
*val = -val64;
return IIO_VAL_INT;
default:
return -EINVAL;
}
};
static const struct iio_chan_spec_ext_info ad5791_ext_info[] = {
{
.name = "powerdown",
.shared = IIO_SHARED_BY_TYPE,
.read = ad5791_read_dac_powerdown,
.write = ad5791_write_dac_powerdown,
},
IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE,
&ad5791_powerdown_mode_enum),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5791_powerdown_mode_enum),
{ },
};
#define AD5791_CHAN(bits, _shift) { \
.type = IIO_VOLTAGE, \
.output = 1, \
.indexed = 1, \
.address = AD5791_ADDR_DAC0, \
.channel = 0, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET), \
.scan_type = { \
.sign = 'u', \
.realbits = (bits), \
.storagebits = 24, \
.shift = (_shift), \
}, \
.ext_info = ad5791_ext_info, \
}
static const struct iio_chan_spec ad5791_channels[] = {
[ID_AD5760] = AD5791_CHAN(16, 4),
[ID_AD5780] = AD5791_CHAN(18, 2),
[ID_AD5781] = AD5791_CHAN(18, 2),
[ID_AD5791] = AD5791_CHAN(20, 0)
};
static int ad5791_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct ad5791_state *st = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
val &= GENMASK(chan->scan_type.realbits - 1, 0);
val <<= chan->scan_type.shift;
return ad5791_spi_write(st, chan->address, val);
default:
return -EINVAL;
}
}
static const struct iio_info ad5791_info = {
.read_raw = &ad5791_read_raw,
.write_raw = &ad5791_write_raw,
};
static int ad5791_probe(struct spi_device *spi)
{
struct ad5791_platform_data *pdata = spi->dev.platform_data;
struct iio_dev *indio_dev;
struct ad5791_state *st;
int ret, pos_voltage_uv = 0, neg_voltage_uv = 0;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->reg_vdd = devm_regulator_get(&spi->dev, "vdd");
if (!IS_ERR(st->reg_vdd)) {
ret = regulator_enable(st->reg_vdd);
if (ret)
return ret;
ret = regulator_get_voltage(st->reg_vdd);
if (ret < 0)
goto error_disable_reg_pos;
pos_voltage_uv = ret;
}
st->reg_vss = devm_regulator_get(&spi->dev, "vss");
if (!IS_ERR(st->reg_vss)) {
ret = regulator_enable(st->reg_vss);
if (ret)
goto error_disable_reg_pos;
ret = regulator_get_voltage(st->reg_vss);
if (ret < 0)
goto error_disable_reg_neg;
neg_voltage_uv = ret;
}
st->pwr_down = true;
st->spi = spi;
if (!IS_ERR(st->reg_vss) && !IS_ERR(st->reg_vdd)) {
st->vref_mv = (pos_voltage_uv + neg_voltage_uv) / 1000;
st->vref_neg_mv = neg_voltage_uv / 1000;
} else if (pdata) {
st->vref_mv = pdata->vref_pos_mv + pdata->vref_neg_mv;
st->vref_neg_mv = pdata->vref_neg_mv;
} else {
dev_warn(&spi->dev, "reference voltage unspecified\n");
}
ret = ad5791_spi_write(st, AD5791_ADDR_SW_CTRL, AD5791_SWCTRL_RESET);
if (ret)
goto error_disable_reg_neg;
st->chip_info = &ad5791_chip_info_tbl[spi_get_device_id(spi)
->driver_data];
st->ctrl = AD5761_CTRL_LINCOMP(st->chip_info->get_lin_comp(st->vref_mv))
| ((pdata && pdata->use_rbuf_gain2) ? 0 : AD5791_CTRL_RBUF) |
AD5791_CTRL_BIN2SC;
ret = ad5791_spi_write(st, AD5791_ADDR_CTRL, st->ctrl |
AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI);
if (ret)
goto error_disable_reg_neg;
spi_set_drvdata(spi, indio_dev);
indio_dev->info = &ad5791_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels
= &ad5791_channels[spi_get_device_id(spi)->driver_data];
indio_dev->num_channels = 1;
indio_dev->name = spi_get_device_id(st->spi)->name;
ret = iio_device_register(indio_dev);
if (ret)
goto error_disable_reg_neg;
return 0;
error_disable_reg_neg:
if (!IS_ERR(st->reg_vss))
regulator_disable(st->reg_vss);
error_disable_reg_pos:
if (!IS_ERR(st->reg_vdd))
regulator_disable(st->reg_vdd);
return ret;
}
static void ad5791_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ad5791_state *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (!IS_ERR(st->reg_vdd))
regulator_disable(st->reg_vdd);
if (!IS_ERR(st->reg_vss))
regulator_disable(st->reg_vss);
}
static const struct spi_device_id ad5791_id[] = {
{"ad5760", ID_AD5760},
{"ad5780", ID_AD5780},
{"ad5781", ID_AD5781},
{"ad5790", ID_AD5791},
{"ad5791", ID_AD5791},
{}
};
MODULE_DEVICE_TABLE(spi, ad5791_id);
static struct spi_driver ad5791_driver = {
.driver = {
.name = "ad5791",
},
.probe = ad5791_probe,
.remove = ad5791_remove,
.id_table = ad5791_id,
};
module_spi_driver(ad5791_driver);
MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5760/AD5780/AD5781/AD5790/AD5791 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5791.c |
// SPDX-License-Identifier: GPL-2.0
/*
* IIO DAC emulation driver using a digital potentiometer
*
* Copyright (C) 2016 Axentia Technologies AB
*
* Author: Peter Rosin <[email protected]>
*/
/*
* It is assumed that the dpot is used as a voltage divider between the
* current dpot wiper setting and the maximum resistance of the dpot. The
* divided voltage is provided by a vref regulator.
*
* .------.
* .-----------. | |
* | vref |--' .---.
* | regulator |--. | |
* '-----------' | | d |
* | | p |
* | | o | wiper
* | | t |<---------+
* | | |
* | '---' dac output voltage
* | |
* '------+------------+
*/
#include <linux/err.h>
#include <linux/iio/consumer.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
struct dpot_dac {
struct regulator *vref;
struct iio_channel *dpot;
u32 max_ohms;
};
static const struct iio_chan_spec dpot_dac_iio_channel = {
.type = IIO_VOLTAGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW)
| BIT(IIO_CHAN_INFO_SCALE),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW),
.output = 1,
.indexed = 1,
};
static int dpot_dac_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct dpot_dac *dac = iio_priv(indio_dev);
int ret;
unsigned long long tmp;
switch (mask) {
case IIO_CHAN_INFO_RAW:
return iio_read_channel_raw(dac->dpot, val);
case IIO_CHAN_INFO_SCALE:
ret = iio_read_channel_scale(dac->dpot, val, val2);
switch (ret) {
case IIO_VAL_FRACTIONAL_LOG2:
tmp = *val * 1000000000LL;
do_div(tmp, dac->max_ohms);
tmp *= regulator_get_voltage(dac->vref) / 1000;
do_div(tmp, 1000000000LL);
*val = tmp;
return ret;
case IIO_VAL_INT:
/*
* Convert integer scale to fractional scale by
* setting the denominator (val2) to one...
*/
*val2 = 1;
ret = IIO_VAL_FRACTIONAL;
/* ...and fall through. Say it again for GCC. */
fallthrough;
case IIO_VAL_FRACTIONAL:
*val *= regulator_get_voltage(dac->vref) / 1000;
*val2 *= dac->max_ohms;
break;
}
return ret;
}
return -EINVAL;
}
static int dpot_dac_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
struct dpot_dac *dac = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
*type = IIO_VAL_INT;
return iio_read_avail_channel_raw(dac->dpot, vals, length);
}
return -EINVAL;
}
static int dpot_dac_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct dpot_dac *dac = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
return iio_write_channel_raw(dac->dpot, val);
}
return -EINVAL;
}
static const struct iio_info dpot_dac_info = {
.read_raw = dpot_dac_read_raw,
.read_avail = dpot_dac_read_avail,
.write_raw = dpot_dac_write_raw,
};
static int dpot_dac_channel_max_ohms(struct iio_dev *indio_dev)
{
struct device *dev = &indio_dev->dev;
struct dpot_dac *dac = iio_priv(indio_dev);
unsigned long long tmp;
int ret;
int val;
int val2;
int max;
ret = iio_read_max_channel_raw(dac->dpot, &max);
if (ret < 0) {
dev_err(dev, "dpot does not indicate its raw maximum value\n");
return ret;
}
switch (iio_read_channel_scale(dac->dpot, &val, &val2)) {
case IIO_VAL_INT:
return max * val;
case IIO_VAL_FRACTIONAL:
tmp = (unsigned long long)max * val;
do_div(tmp, val2);
return tmp;
case IIO_VAL_FRACTIONAL_LOG2:
tmp = val * 1000000000LL * max >> val2;
do_div(tmp, 1000000000LL);
return tmp;
default:
dev_err(dev, "dpot has a scale that is too weird\n");
}
return -EINVAL;
}
static int dpot_dac_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct iio_dev *indio_dev;
struct dpot_dac *dac;
enum iio_chan_type type;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*dac));
if (!indio_dev)
return -ENOMEM;
platform_set_drvdata(pdev, indio_dev);
dac = iio_priv(indio_dev);
indio_dev->name = dev_name(dev);
indio_dev->info = &dpot_dac_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = &dpot_dac_iio_channel;
indio_dev->num_channels = 1;
dac->vref = devm_regulator_get(dev, "vref");
if (IS_ERR(dac->vref))
return dev_err_probe(&pdev->dev, PTR_ERR(dac->vref),
"failed to get vref regulator\n");
dac->dpot = devm_iio_channel_get(dev, "dpot");
if (IS_ERR(dac->dpot))
return dev_err_probe(&pdev->dev, PTR_ERR(dac->dpot),
"failed to get dpot input channel\n");
ret = iio_get_channel_type(dac->dpot, &type);
if (ret < 0)
return ret;
if (type != IIO_RESISTANCE) {
dev_err(dev, "dpot is of the wrong type\n");
return -EINVAL;
}
ret = dpot_dac_channel_max_ohms(indio_dev);
if (ret < 0)
return ret;
dac->max_ohms = ret;
ret = regulator_enable(dac->vref);
if (ret) {
dev_err(dev, "failed to enable the vref regulator\n");
return ret;
}
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(dev, "failed to register iio device\n");
goto disable_reg;
}
return 0;
disable_reg:
regulator_disable(dac->vref);
return ret;
}
static int dpot_dac_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct dpot_dac *dac = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
regulator_disable(dac->vref);
return 0;
}
static const struct of_device_id dpot_dac_match[] = {
{ .compatible = "dpot-dac" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, dpot_dac_match);
static struct platform_driver dpot_dac_driver = {
.probe = dpot_dac_probe,
.remove = dpot_dac_remove,
.driver = {
.name = "iio-dpot-dac",
.of_match_table = dpot_dac_match,
},
};
module_platform_driver(dpot_dac_driver);
MODULE_DESCRIPTION("DAC emulation driver using a digital potentiometer");
MODULE_AUTHOR("Peter Rosin <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/dpot-dac.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for Linear Technology LTC1665/LTC1660, 8 channels DAC
*
* Copyright (C) 2018 Marcus Folkesson <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#define LTC1660_REG_WAKE 0x0
#define LTC1660_REG_DAC_A 0x1
#define LTC1660_REG_DAC_B 0x2
#define LTC1660_REG_DAC_C 0x3
#define LTC1660_REG_DAC_D 0x4
#define LTC1660_REG_DAC_E 0x5
#define LTC1660_REG_DAC_F 0x6
#define LTC1660_REG_DAC_G 0x7
#define LTC1660_REG_DAC_H 0x8
#define LTC1660_REG_SLEEP 0xe
#define LTC1660_NUM_CHANNELS 8
static const struct regmap_config ltc1660_regmap_config = {
.reg_bits = 4,
.val_bits = 12,
};
enum ltc1660_supported_device_ids {
ID_LTC1660,
ID_LTC1665,
};
struct ltc1660_priv {
struct spi_device *spi;
struct regmap *regmap;
struct regulator *vref_reg;
unsigned int value[LTC1660_NUM_CHANNELS];
unsigned int vref_mv;
};
static int ltc1660_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
struct ltc1660_priv *priv = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
*val = priv->value[chan->channel];
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = regulator_get_voltage(priv->vref_reg);
if (*val < 0) {
dev_err(&priv->spi->dev, "failed to read vref regulator: %d\n",
*val);
return *val;
}
/* Convert to mV */
*val /= 1000;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
}
static int ltc1660_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct ltc1660_priv *priv = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val2 != 0)
return -EINVAL;
if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))
return -EINVAL;
ret = regmap_write(priv->regmap, chan->channel,
(val << chan->scan_type.shift));
if (!ret)
priv->value[chan->channel] = val;
return ret;
default:
return -EINVAL;
}
}
#define LTC1660_CHAN(chan, bits) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.scan_type = { \
.sign = 'u', \
.realbits = (bits), \
.storagebits = 16, \
.shift = 12 - (bits), \
}, \
}
#define LTC1660_OCTAL_CHANNELS(bits) { \
LTC1660_CHAN(LTC1660_REG_DAC_A, bits), \
LTC1660_CHAN(LTC1660_REG_DAC_B, bits), \
LTC1660_CHAN(LTC1660_REG_DAC_C, bits), \
LTC1660_CHAN(LTC1660_REG_DAC_D, bits), \
LTC1660_CHAN(LTC1660_REG_DAC_E, bits), \
LTC1660_CHAN(LTC1660_REG_DAC_F, bits), \
LTC1660_CHAN(LTC1660_REG_DAC_G, bits), \
LTC1660_CHAN(LTC1660_REG_DAC_H, bits), \
}
static const struct iio_chan_spec ltc1660_channels[][LTC1660_NUM_CHANNELS] = {
[ID_LTC1660] = LTC1660_OCTAL_CHANNELS(10),
[ID_LTC1665] = LTC1660_OCTAL_CHANNELS(8),
};
static const struct iio_info ltc1660_info = {
.read_raw = <c1660_read_raw,
.write_raw = <c1660_write_raw,
};
static int ltc1660_suspend(struct device *dev)
{
struct ltc1660_priv *priv = iio_priv(spi_get_drvdata(
to_spi_device(dev)));
return regmap_write(priv->regmap, LTC1660_REG_SLEEP, 0x00);
}
static int ltc1660_resume(struct device *dev)
{
struct ltc1660_priv *priv = iio_priv(spi_get_drvdata(
to_spi_device(dev)));
return regmap_write(priv->regmap, LTC1660_REG_WAKE, 0x00);
}
static DEFINE_SIMPLE_DEV_PM_OPS(ltc1660_pm_ops, ltc1660_suspend,
ltc1660_resume);
static int ltc1660_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct ltc1660_priv *priv;
const struct spi_device_id *id = spi_get_device_id(spi);
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*priv));
if (indio_dev == NULL)
return -ENOMEM;
priv = iio_priv(indio_dev);
priv->regmap = devm_regmap_init_spi(spi, <c1660_regmap_config);
if (IS_ERR(priv->regmap)) {
dev_err(&spi->dev, "failed to register spi regmap %ld\n",
PTR_ERR(priv->regmap));
return PTR_ERR(priv->regmap);
}
priv->vref_reg = devm_regulator_get(&spi->dev, "vref");
if (IS_ERR(priv->vref_reg))
return dev_err_probe(&spi->dev, PTR_ERR(priv->vref_reg),
"vref regulator not specified\n");
ret = regulator_enable(priv->vref_reg);
if (ret) {
dev_err(&spi->dev, "failed to enable vref regulator: %d\n",
ret);
return ret;
}
priv->spi = spi;
spi_set_drvdata(spi, indio_dev);
indio_dev->info = <c1660_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ltc1660_channels[id->driver_data];
indio_dev->num_channels = LTC1660_NUM_CHANNELS;
indio_dev->name = id->name;
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&spi->dev, "failed to register iio device: %d\n",
ret);
goto error_disable_reg;
}
return 0;
error_disable_reg:
regulator_disable(priv->vref_reg);
return ret;
}
static void ltc1660_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ltc1660_priv *priv = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
regulator_disable(priv->vref_reg);
}
static const struct of_device_id ltc1660_dt_ids[] = {
{ .compatible = "lltc,ltc1660", .data = (void *)ID_LTC1660 },
{ .compatible = "lltc,ltc1665", .data = (void *)ID_LTC1665 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, ltc1660_dt_ids);
static const struct spi_device_id ltc1660_id[] = {
{"ltc1660", ID_LTC1660},
{"ltc1665", ID_LTC1665},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(spi, ltc1660_id);
static struct spi_driver ltc1660_driver = {
.driver = {
.name = "ltc1660",
.of_match_table = ltc1660_dt_ids,
.pm = pm_sleep_ptr(<c1660_pm_ops),
},
.probe = ltc1660_probe,
.remove = ltc1660_remove,
.id_table = ltc1660_id,
};
module_spi_driver(ltc1660_driver);
MODULE_AUTHOR("Marcus Folkesson <[email protected]>");
MODULE_DESCRIPTION("Linear Technology LTC1660/LTC1665 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ltc1660.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* iio/dac/max5821.c
* Copyright (C) 2014 Philippe Reynes
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/regulator/consumer.h>
#define MAX5821_MAX_DAC_CHANNELS 2
/* command bytes */
#define MAX5821_LOAD_DAC_A_IN_REG_B 0x00
#define MAX5821_LOAD_DAC_B_IN_REG_A 0x10
#define MAX5821_EXTENDED_COMMAND_MODE 0xf0
#define MAX5821_READ_DAC_A_COMMAND 0xf1
#define MAX5821_READ_DAC_B_COMMAND 0xf2
#define MAX5821_EXTENDED_POWER_UP 0x00
#define MAX5821_EXTENDED_POWER_DOWN_MODE0 0x01
#define MAX5821_EXTENDED_POWER_DOWN_MODE1 0x02
#define MAX5821_EXTENDED_POWER_DOWN_MODE2 0x03
#define MAX5821_EXTENDED_DAC_A 0x04
#define MAX5821_EXTENDED_DAC_B 0x08
enum max5821_device_ids {
ID_MAX5821,
};
struct max5821_data {
struct i2c_client *client;
struct regulator *vref_reg;
unsigned short vref_mv;
bool powerdown[MAX5821_MAX_DAC_CHANNELS];
u8 powerdown_mode[MAX5821_MAX_DAC_CHANNELS];
struct mutex lock;
};
static const char * const max5821_powerdown_modes[] = {
"three_state",
"1kohm_to_gnd",
"100kohm_to_gnd",
};
enum {
MAX5821_THREE_STATE,
MAX5821_1KOHM_TO_GND,
MAX5821_100KOHM_TO_GND
};
static int max5821_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct max5821_data *st = iio_priv(indio_dev);
return st->powerdown_mode[chan->channel];
}
static int max5821_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int mode)
{
struct max5821_data *st = iio_priv(indio_dev);
st->powerdown_mode[chan->channel] = mode;
return 0;
}
static const struct iio_enum max5821_powerdown_mode_enum = {
.items = max5821_powerdown_modes,
.num_items = ARRAY_SIZE(max5821_powerdown_modes),
.get = max5821_get_powerdown_mode,
.set = max5821_set_powerdown_mode,
};
static ssize_t max5821_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct max5821_data *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", st->powerdown[chan->channel]);
}
static int max5821_sync_powerdown_mode(struct max5821_data *data,
const struct iio_chan_spec *chan)
{
u8 outbuf[2];
outbuf[0] = MAX5821_EXTENDED_COMMAND_MODE;
if (chan->channel == 0)
outbuf[1] = MAX5821_EXTENDED_DAC_A;
else
outbuf[1] = MAX5821_EXTENDED_DAC_B;
if (data->powerdown[chan->channel])
outbuf[1] |= data->powerdown_mode[chan->channel] + 1;
else
outbuf[1] |= MAX5821_EXTENDED_POWER_UP;
return i2c_master_send(data->client, outbuf, 2);
}
static ssize_t max5821_write_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct max5821_data *data = iio_priv(indio_dev);
bool powerdown;
int ret;
ret = kstrtobool(buf, &powerdown);
if (ret)
return ret;
data->powerdown[chan->channel] = powerdown;
ret = max5821_sync_powerdown_mode(data, chan);
if (ret < 0)
return ret;
return len;
}
static const struct iio_chan_spec_ext_info max5821_ext_info[] = {
{
.name = "powerdown",
.read = max5821_read_dac_powerdown,
.write = max5821_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SEPARATE, &max5821_powerdown_mode_enum),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &max5821_powerdown_mode_enum),
{ },
};
#define MAX5821_CHANNEL(chan) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \
.ext_info = max5821_ext_info, \
}
static const struct iio_chan_spec max5821_channels[] = {
MAX5821_CHANNEL(0),
MAX5821_CHANNEL(1)
};
static const u8 max5821_read_dac_command[] = {
MAX5821_READ_DAC_A_COMMAND,
MAX5821_READ_DAC_B_COMMAND
};
static const u8 max5821_load_dac_command[] = {
MAX5821_LOAD_DAC_A_IN_REG_B,
MAX5821_LOAD_DAC_B_IN_REG_A
};
static int max5821_get_value(struct iio_dev *indio_dev,
int *val, int channel)
{
struct max5821_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
u8 outbuf[1];
u8 inbuf[2];
int ret;
if ((channel != 0) && (channel != 1))
return -EINVAL;
outbuf[0] = max5821_read_dac_command[channel];
mutex_lock(&data->lock);
ret = i2c_master_send(client, outbuf, 1);
if (ret < 0) {
mutex_unlock(&data->lock);
return ret;
} else if (ret != 1) {
mutex_unlock(&data->lock);
return -EIO;
}
ret = i2c_master_recv(client, inbuf, 2);
if (ret < 0) {
mutex_unlock(&data->lock);
return ret;
} else if (ret != 2) {
mutex_unlock(&data->lock);
return -EIO;
}
mutex_unlock(&data->lock);
*val = ((inbuf[0] & 0x0f) << 6) | (inbuf[1] >> 2);
return IIO_VAL_INT;
}
static int max5821_set_value(struct iio_dev *indio_dev,
int val, int channel)
{
struct max5821_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
u8 outbuf[2];
int ret;
if ((val < 0) || (val > 1023))
return -EINVAL;
if ((channel != 0) && (channel != 1))
return -EINVAL;
outbuf[0] = max5821_load_dac_command[channel];
outbuf[0] |= val >> 6;
outbuf[1] = (val & 0x3f) << 2;
ret = i2c_master_send(client, outbuf, 2);
if (ret < 0)
return ret;
else if (ret != 2)
return -EIO;
else
return 0;
}
static int max5821_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct max5821_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
return max5821_get_value(indio_dev, val, chan->channel);
case IIO_CHAN_INFO_SCALE:
*val = data->vref_mv;
*val2 = 10;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
}
static int max5821_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
if (val2 != 0)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
return max5821_set_value(indio_dev, val, chan->channel);
default:
return -EINVAL;
}
}
static int max5821_suspend(struct device *dev)
{
u8 outbuf[2] = { MAX5821_EXTENDED_COMMAND_MODE,
MAX5821_EXTENDED_DAC_A |
MAX5821_EXTENDED_DAC_B |
MAX5821_EXTENDED_POWER_DOWN_MODE2 };
return i2c_master_send(to_i2c_client(dev), outbuf, 2);
}
static int max5821_resume(struct device *dev)
{
u8 outbuf[2] = { MAX5821_EXTENDED_COMMAND_MODE,
MAX5821_EXTENDED_DAC_A |
MAX5821_EXTENDED_DAC_B |
MAX5821_EXTENDED_POWER_UP };
return i2c_master_send(to_i2c_client(dev), outbuf, 2);
}
static DEFINE_SIMPLE_DEV_PM_OPS(max5821_pm_ops, max5821_suspend,
max5821_resume);
static const struct iio_info max5821_info = {
.read_raw = max5821_read_raw,
.write_raw = max5821_write_raw,
};
static void max5821_regulator_disable(void *reg)
{
regulator_disable(reg);
}
static int max5821_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct max5821_data *data;
struct iio_dev *indio_dev;
u32 tmp;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->client = client;
mutex_init(&data->lock);
/* max5821 start in powerdown mode 100Kohm to ground */
for (tmp = 0; tmp < MAX5821_MAX_DAC_CHANNELS; tmp++) {
data->powerdown[tmp] = true;
data->powerdown_mode[tmp] = MAX5821_100KOHM_TO_GND;
}
data->vref_reg = devm_regulator_get(&client->dev, "vref");
if (IS_ERR(data->vref_reg))
return dev_err_probe(&client->dev, PTR_ERR(data->vref_reg),
"Failed to get vref regulator\n");
ret = regulator_enable(data->vref_reg);
if (ret) {
dev_err(&client->dev,
"Failed to enable vref regulator: %d\n", ret);
return ret;
}
ret = devm_add_action_or_reset(&client->dev, max5821_regulator_disable,
data->vref_reg);
if (ret) {
dev_err(&client->dev,
"Failed to add action to managed regulator: %d\n", ret);
return ret;
}
ret = regulator_get_voltage(data->vref_reg);
if (ret < 0) {
dev_err(&client->dev,
"Failed to get voltage on regulator: %d\n", ret);
return ret;
}
data->vref_mv = ret / 1000;
indio_dev->name = id->name;
indio_dev->num_channels = ARRAY_SIZE(max5821_channels);
indio_dev->channels = max5821_channels;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &max5821_info;
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id max5821_id[] = {
{ "max5821", ID_MAX5821 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max5821_id);
static const struct of_device_id max5821_of_match[] = {
{ .compatible = "maxim,max5821" },
{ }
};
MODULE_DEVICE_TABLE(of, max5821_of_match);
static struct i2c_driver max5821_driver = {
.driver = {
.name = "max5821",
.of_match_table = max5821_of_match,
.pm = pm_sleep_ptr(&max5821_pm_ops),
},
.probe = max5821_probe,
.id_table = max5821_id,
};
module_i2c_driver(max5821_driver);
MODULE_AUTHOR("Philippe Reynes <[email protected]>");
MODULE_DESCRIPTION("MAX5821 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/max5821.c |
// SPDX-License-Identifier: GPL-2.0
/*
* This file is part of STM32 DAC driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author: Fabrice Gasnier <[email protected]>.
*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include "stm32-dac-core.h"
/**
* struct stm32_dac_priv - stm32 DAC core private data
* @pclk: peripheral clock common for all DACs
* @vref: regulator reference
* @common: Common data for all DAC instances
*/
struct stm32_dac_priv {
struct clk *pclk;
struct regulator *vref;
struct stm32_dac_common common;
};
/**
* struct stm32_dac_cfg - DAC configuration
* @has_hfsel: DAC has high frequency control
*/
struct stm32_dac_cfg {
bool has_hfsel;
};
static struct stm32_dac_priv *to_stm32_dac_priv(struct stm32_dac_common *com)
{
return container_of(com, struct stm32_dac_priv, common);
}
static const struct regmap_config stm32_dac_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = sizeof(u32),
.max_register = 0x3fc,
};
static int stm32_dac_core_hw_start(struct device *dev)
{
struct stm32_dac_common *common = dev_get_drvdata(dev);
struct stm32_dac_priv *priv = to_stm32_dac_priv(common);
int ret;
ret = regulator_enable(priv->vref);
if (ret < 0) {
dev_err(dev, "vref enable failed: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(priv->pclk);
if (ret < 0) {
dev_err(dev, "pclk enable failed: %d\n", ret);
goto err_regulator_disable;
}
return 0;
err_regulator_disable:
regulator_disable(priv->vref);
return ret;
}
static void stm32_dac_core_hw_stop(struct device *dev)
{
struct stm32_dac_common *common = dev_get_drvdata(dev);
struct stm32_dac_priv *priv = to_stm32_dac_priv(common);
clk_disable_unprepare(priv->pclk);
regulator_disable(priv->vref);
}
static int stm32_dac_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct stm32_dac_cfg *cfg;
struct stm32_dac_priv *priv;
struct regmap *regmap;
void __iomem *mmio;
struct reset_control *rst;
int ret;
if (!dev->of_node)
return -ENODEV;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, &priv->common);
cfg = (const struct stm32_dac_cfg *)
of_match_device(dev->driver->of_match_table, dev)->data;
mmio = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(mmio))
return PTR_ERR(mmio);
regmap = devm_regmap_init_mmio_clk(dev, "pclk", mmio,
&stm32_dac_regmap_cfg);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
priv->common.regmap = regmap;
priv->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(priv->pclk))
return dev_err_probe(dev, PTR_ERR(priv->pclk), "pclk get failed\n");
priv->vref = devm_regulator_get(dev, "vref");
if (IS_ERR(priv->vref))
return dev_err_probe(dev, PTR_ERR(priv->vref), "vref get failed\n");
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
ret = stm32_dac_core_hw_start(dev);
if (ret)
goto err_pm_stop;
ret = regulator_get_voltage(priv->vref);
if (ret < 0) {
dev_err(dev, "vref get voltage failed, %d\n", ret);
goto err_hw_stop;
}
priv->common.vref_mv = ret / 1000;
dev_dbg(dev, "vref+=%dmV\n", priv->common.vref_mv);
rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (rst) {
if (IS_ERR(rst)) {
ret = dev_err_probe(dev, PTR_ERR(rst), "reset get failed\n");
goto err_hw_stop;
}
reset_control_assert(rst);
udelay(2);
reset_control_deassert(rst);
}
if (cfg && cfg->has_hfsel) {
/* When clock speed is higher than 80MHz, set HFSEL */
priv->common.hfsel = (clk_get_rate(priv->pclk) > 80000000UL);
ret = regmap_update_bits(regmap, STM32_DAC_CR,
STM32H7_DAC_CR_HFSEL,
priv->common.hfsel ?
STM32H7_DAC_CR_HFSEL : 0);
if (ret)
goto err_hw_stop;
}
ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, dev);
if (ret < 0) {
dev_err(dev, "failed to populate DT children\n");
goto err_hw_stop;
}
pm_runtime_put(dev);
return 0;
err_hw_stop:
stm32_dac_core_hw_stop(dev);
err_pm_stop:
pm_runtime_disable(dev);
pm_runtime_set_suspended(dev);
pm_runtime_put_noidle(dev);
return ret;
}
static int stm32_dac_remove(struct platform_device *pdev)
{
pm_runtime_get_sync(&pdev->dev);
of_platform_depopulate(&pdev->dev);
stm32_dac_core_hw_stop(&pdev->dev);
pm_runtime_disable(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
return 0;
}
static int stm32_dac_core_resume(struct device *dev)
{
struct stm32_dac_common *common = dev_get_drvdata(dev);
struct stm32_dac_priv *priv = to_stm32_dac_priv(common);
int ret;
if (priv->common.hfsel) {
/* restore hfsel (maybe lost under low power state) */
ret = regmap_update_bits(priv->common.regmap, STM32_DAC_CR,
STM32H7_DAC_CR_HFSEL,
STM32H7_DAC_CR_HFSEL);
if (ret)
return ret;
}
return pm_runtime_force_resume(dev);
}
static int stm32_dac_core_runtime_suspend(struct device *dev)
{
stm32_dac_core_hw_stop(dev);
return 0;
}
static int stm32_dac_core_runtime_resume(struct device *dev)
{
return stm32_dac_core_hw_start(dev);
}
static const struct dev_pm_ops stm32_dac_core_pm_ops = {
SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, stm32_dac_core_resume)
RUNTIME_PM_OPS(stm32_dac_core_runtime_suspend,
stm32_dac_core_runtime_resume,
NULL)
};
static const struct stm32_dac_cfg stm32h7_dac_cfg = {
.has_hfsel = true,
};
static const struct of_device_id stm32_dac_of_match[] = {
{
.compatible = "st,stm32f4-dac-core",
}, {
.compatible = "st,stm32h7-dac-core",
.data = (void *)&stm32h7_dac_cfg,
},
{},
};
MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
static struct platform_driver stm32_dac_driver = {
.probe = stm32_dac_probe,
.remove = stm32_dac_remove,
.driver = {
.name = "stm32-dac-core",
.of_match_table = stm32_dac_of_match,
.pm = pm_ptr(&stm32_dac_core_pm_ops),
},
};
module_platform_driver(stm32_dac_driver);
MODULE_AUTHOR("Fabrice Gasnier <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics STM32 DAC core driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:stm32-dac-core");
| linux-master | drivers/iio/dac/stm32-dac-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* AD5446 SPI DAC driver
*
* Copyright 2010 Analog Devices Inc.
*/
#include <linux/interrupt.h>
#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/list.h>
#include <linux/spi/spi.h>
#include <linux/i2c.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <asm/unaligned.h>
#define MODE_PWRDWN_1k 0x1
#define MODE_PWRDWN_100k 0x2
#define MODE_PWRDWN_TRISTATE 0x3
/**
* struct ad5446_state - driver instance specific data
* @dev: this device
* @chip_info: chip model specific constants, available modes etc
* @reg: supply regulator
* @vref_mv: actual reference voltage used
* @cached_val: store/retrieve values during power down
* @pwr_down_mode: power down mode (1k, 100k or tristate)
* @pwr_down: true if the device is in power down
* @lock: lock to protect the data buffer during write ops
*/
struct ad5446_state {
struct device *dev;
const struct ad5446_chip_info *chip_info;
struct regulator *reg;
unsigned short vref_mv;
unsigned cached_val;
unsigned pwr_down_mode;
unsigned pwr_down;
struct mutex lock;
};
/**
* struct ad5446_chip_info - chip specific information
* @channel: channel spec for the DAC
* @int_vref_mv: AD5620/40/60: the internal reference voltage
* @write: chip specific helper function to write to the register
*/
struct ad5446_chip_info {
struct iio_chan_spec channel;
u16 int_vref_mv;
int (*write)(struct ad5446_state *st, unsigned val);
};
static const char * const ad5446_powerdown_modes[] = {
"1kohm_to_gnd", "100kohm_to_gnd", "three_state"
};
static int ad5446_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, unsigned int mode)
{
struct ad5446_state *st = iio_priv(indio_dev);
st->pwr_down_mode = mode + 1;
return 0;
}
static int ad5446_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct ad5446_state *st = iio_priv(indio_dev);
return st->pwr_down_mode - 1;
}
static const struct iio_enum ad5446_powerdown_mode_enum = {
.items = ad5446_powerdown_modes,
.num_items = ARRAY_SIZE(ad5446_powerdown_modes),
.get = ad5446_get_powerdown_mode,
.set = ad5446_set_powerdown_mode,
};
static ssize_t ad5446_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct ad5446_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", st->pwr_down);
}
static ssize_t ad5446_write_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct ad5446_state *st = iio_priv(indio_dev);
unsigned int shift;
unsigned int val;
bool powerdown;
int ret;
ret = kstrtobool(buf, &powerdown);
if (ret)
return ret;
mutex_lock(&st->lock);
st->pwr_down = powerdown;
if (st->pwr_down) {
shift = chan->scan_type.realbits + chan->scan_type.shift;
val = st->pwr_down_mode << shift;
} else {
val = st->cached_val;
}
ret = st->chip_info->write(st, val);
mutex_unlock(&st->lock);
return ret ? ret : len;
}
static const struct iio_chan_spec_ext_info ad5446_ext_info_powerdown[] = {
{
.name = "powerdown",
.read = ad5446_read_dac_powerdown,
.write = ad5446_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5446_powerdown_mode_enum),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5446_powerdown_mode_enum),
{ },
};
#define _AD5446_CHANNEL(bits, storage, _shift, ext) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = 0, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.scan_type = { \
.sign = 'u', \
.realbits = (bits), \
.storagebits = (storage), \
.shift = (_shift), \
}, \
.ext_info = (ext), \
}
#define AD5446_CHANNEL(bits, storage, shift) \
_AD5446_CHANNEL(bits, storage, shift, NULL)
#define AD5446_CHANNEL_POWERDOWN(bits, storage, shift) \
_AD5446_CHANNEL(bits, storage, shift, ad5446_ext_info_powerdown)
static int ad5446_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct ad5446_state *st = iio_priv(indio_dev);
switch (m) {
case IIO_CHAN_INFO_RAW:
*val = st->cached_val >> chan->scan_type.shift;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = st->vref_mv;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
static int ad5446_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct ad5446_state *st = iio_priv(indio_dev);
int ret = 0;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val >= (1 << chan->scan_type.realbits) || val < 0)
return -EINVAL;
val <<= chan->scan_type.shift;
mutex_lock(&st->lock);
st->cached_val = val;
if (!st->pwr_down)
ret = st->chip_info->write(st, val);
mutex_unlock(&st->lock);
break;
default:
ret = -EINVAL;
}
return ret;
}
static const struct iio_info ad5446_info = {
.read_raw = ad5446_read_raw,
.write_raw = ad5446_write_raw,
};
static int ad5446_probe(struct device *dev, const char *name,
const struct ad5446_chip_info *chip_info)
{
struct ad5446_state *st;
struct iio_dev *indio_dev;
struct regulator *reg;
int ret, voltage_uv = 0;
reg = devm_regulator_get(dev, "vcc");
if (!IS_ERR(reg)) {
ret = regulator_enable(reg);
if (ret)
return ret;
ret = regulator_get_voltage(reg);
if (ret < 0)
goto error_disable_reg;
voltage_uv = ret;
}
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
if (indio_dev == NULL) {
ret = -ENOMEM;
goto error_disable_reg;
}
st = iio_priv(indio_dev);
st->chip_info = chip_info;
dev_set_drvdata(dev, indio_dev);
st->reg = reg;
st->dev = dev;
indio_dev->name = name;
indio_dev->info = &ad5446_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = &st->chip_info->channel;
indio_dev->num_channels = 1;
mutex_init(&st->lock);
st->pwr_down_mode = MODE_PWRDWN_1k;
if (st->chip_info->int_vref_mv)
st->vref_mv = st->chip_info->int_vref_mv;
else if (voltage_uv)
st->vref_mv = voltage_uv / 1000;
else
dev_warn(dev, "reference voltage unspecified\n");
ret = iio_device_register(indio_dev);
if (ret)
goto error_disable_reg;
return 0;
error_disable_reg:
if (!IS_ERR(reg))
regulator_disable(reg);
return ret;
}
static void ad5446_remove(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct ad5446_state *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
}
#if IS_ENABLED(CONFIG_SPI_MASTER)
static int ad5446_write(struct ad5446_state *st, unsigned val)
{
struct spi_device *spi = to_spi_device(st->dev);
__be16 data = cpu_to_be16(val);
return spi_write(spi, &data, sizeof(data));
}
static int ad5660_write(struct ad5446_state *st, unsigned val)
{
struct spi_device *spi = to_spi_device(st->dev);
uint8_t data[3];
put_unaligned_be24(val, &data[0]);
return spi_write(spi, data, sizeof(data));
}
/*
* ad5446_supported_spi_device_ids:
* The AD5620/40/60 parts are available in different fixed internal reference
* voltage options. The actual part numbers may look differently
* (and a bit cryptic), however this style is used to make clear which
* parts are supported here.
*/
enum ad5446_supported_spi_device_ids {
ID_AD5300,
ID_AD5310,
ID_AD5320,
ID_AD5444,
ID_AD5446,
ID_AD5450,
ID_AD5451,
ID_AD5541A,
ID_AD5512A,
ID_AD5553,
ID_AD5600,
ID_AD5601,
ID_AD5611,
ID_AD5621,
ID_AD5641,
ID_AD5620_2500,
ID_AD5620_1250,
ID_AD5640_2500,
ID_AD5640_1250,
ID_AD5660_2500,
ID_AD5660_1250,
ID_AD5662,
};
static const struct ad5446_chip_info ad5446_spi_chip_info[] = {
[ID_AD5300] = {
.channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4),
.write = ad5446_write,
},
[ID_AD5310] = {
.channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2),
.write = ad5446_write,
},
[ID_AD5320] = {
.channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0),
.write = ad5446_write,
},
[ID_AD5444] = {
.channel = AD5446_CHANNEL(12, 16, 2),
.write = ad5446_write,
},
[ID_AD5446] = {
.channel = AD5446_CHANNEL(14, 16, 0),
.write = ad5446_write,
},
[ID_AD5450] = {
.channel = AD5446_CHANNEL(8, 16, 6),
.write = ad5446_write,
},
[ID_AD5451] = {
.channel = AD5446_CHANNEL(10, 16, 4),
.write = ad5446_write,
},
[ID_AD5541A] = {
.channel = AD5446_CHANNEL(16, 16, 0),
.write = ad5446_write,
},
[ID_AD5512A] = {
.channel = AD5446_CHANNEL(12, 16, 4),
.write = ad5446_write,
},
[ID_AD5553] = {
.channel = AD5446_CHANNEL(14, 16, 0),
.write = ad5446_write,
},
[ID_AD5600] = {
.channel = AD5446_CHANNEL(16, 16, 0),
.write = ad5446_write,
},
[ID_AD5601] = {
.channel = AD5446_CHANNEL_POWERDOWN(8, 16, 6),
.write = ad5446_write,
},
[ID_AD5611] = {
.channel = AD5446_CHANNEL_POWERDOWN(10, 16, 4),
.write = ad5446_write,
},
[ID_AD5621] = {
.channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2),
.write = ad5446_write,
},
[ID_AD5641] = {
.channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0),
.write = ad5446_write,
},
[ID_AD5620_2500] = {
.channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2),
.int_vref_mv = 2500,
.write = ad5446_write,
},
[ID_AD5620_1250] = {
.channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2),
.int_vref_mv = 1250,
.write = ad5446_write,
},
[ID_AD5640_2500] = {
.channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0),
.int_vref_mv = 2500,
.write = ad5446_write,
},
[ID_AD5640_1250] = {
.channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0),
.int_vref_mv = 1250,
.write = ad5446_write,
},
[ID_AD5660_2500] = {
.channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0),
.int_vref_mv = 2500,
.write = ad5660_write,
},
[ID_AD5660_1250] = {
.channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0),
.int_vref_mv = 1250,
.write = ad5660_write,
},
[ID_AD5662] = {
.channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0),
.write = ad5660_write,
},
};
static const struct spi_device_id ad5446_spi_ids[] = {
{"ad5300", ID_AD5300},
{"ad5310", ID_AD5310},
{"ad5320", ID_AD5320},
{"ad5444", ID_AD5444},
{"ad5446", ID_AD5446},
{"ad5450", ID_AD5450},
{"ad5451", ID_AD5451},
{"ad5452", ID_AD5444}, /* ad5452 is compatible to the ad5444 */
{"ad5453", ID_AD5446}, /* ad5453 is compatible to the ad5446 */
{"ad5512a", ID_AD5512A},
{"ad5541a", ID_AD5541A},
{"ad5542a", ID_AD5541A}, /* ad5541a and ad5542a are compatible */
{"ad5543", ID_AD5541A}, /* ad5541a and ad5543 are compatible */
{"ad5553", ID_AD5553},
{"ad5600", ID_AD5600},
{"ad5601", ID_AD5601},
{"ad5611", ID_AD5611},
{"ad5621", ID_AD5621},
{"ad5641", ID_AD5641},
{"ad5620-2500", ID_AD5620_2500}, /* AD5620/40/60: */
{"ad5620-1250", ID_AD5620_1250}, /* part numbers may look differently */
{"ad5640-2500", ID_AD5640_2500},
{"ad5640-1250", ID_AD5640_1250},
{"ad5660-2500", ID_AD5660_2500},
{"ad5660-1250", ID_AD5660_1250},
{"ad5662", ID_AD5662},
{"dac081s101", ID_AD5300}, /* compatible Texas Instruments chips */
{"dac101s101", ID_AD5310},
{"dac121s101", ID_AD5320},
{"dac7512", ID_AD5320},
{}
};
MODULE_DEVICE_TABLE(spi, ad5446_spi_ids);
static const struct of_device_id ad5446_of_ids[] = {
{ .compatible = "ti,dac7512" },
{ }
};
MODULE_DEVICE_TABLE(of, ad5446_of_ids);
static int ad5446_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
return ad5446_probe(&spi->dev, id->name,
&ad5446_spi_chip_info[id->driver_data]);
}
static void ad5446_spi_remove(struct spi_device *spi)
{
ad5446_remove(&spi->dev);
}
static struct spi_driver ad5446_spi_driver = {
.driver = {
.name = "ad5446",
.of_match_table = ad5446_of_ids,
},
.probe = ad5446_spi_probe,
.remove = ad5446_spi_remove,
.id_table = ad5446_spi_ids,
};
static int __init ad5446_spi_register_driver(void)
{
return spi_register_driver(&ad5446_spi_driver);
}
static void ad5446_spi_unregister_driver(void)
{
spi_unregister_driver(&ad5446_spi_driver);
}
#else
static inline int ad5446_spi_register_driver(void) { return 0; }
static inline void ad5446_spi_unregister_driver(void) { }
#endif
#if IS_ENABLED(CONFIG_I2C)
static int ad5622_write(struct ad5446_state *st, unsigned val)
{
struct i2c_client *client = to_i2c_client(st->dev);
__be16 data = cpu_to_be16(val);
int ret;
ret = i2c_master_send(client, (char *)&data, sizeof(data));
if (ret < 0)
return ret;
if (ret != sizeof(data))
return -EIO;
return 0;
}
/*
* ad5446_supported_i2c_device_ids:
* The AD5620/40/60 parts are available in different fixed internal reference
* voltage options. The actual part numbers may look differently
* (and a bit cryptic), however this style is used to make clear which
* parts are supported here.
*/
enum ad5446_supported_i2c_device_ids {
ID_AD5602,
ID_AD5612,
ID_AD5622,
};
static const struct ad5446_chip_info ad5446_i2c_chip_info[] = {
[ID_AD5602] = {
.channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4),
.write = ad5622_write,
},
[ID_AD5612] = {
.channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2),
.write = ad5622_write,
},
[ID_AD5622] = {
.channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0),
.write = ad5622_write,
},
};
static int ad5446_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
return ad5446_probe(&i2c->dev, id->name,
&ad5446_i2c_chip_info[id->driver_data]);
}
static void ad5446_i2c_remove(struct i2c_client *i2c)
{
ad5446_remove(&i2c->dev);
}
static const struct i2c_device_id ad5446_i2c_ids[] = {
{"ad5301", ID_AD5602},
{"ad5311", ID_AD5612},
{"ad5321", ID_AD5622},
{"ad5602", ID_AD5602},
{"ad5612", ID_AD5612},
{"ad5622", ID_AD5622},
{}
};
MODULE_DEVICE_TABLE(i2c, ad5446_i2c_ids);
static struct i2c_driver ad5446_i2c_driver = {
.driver = {
.name = "ad5446",
},
.probe = ad5446_i2c_probe,
.remove = ad5446_i2c_remove,
.id_table = ad5446_i2c_ids,
};
static int __init ad5446_i2c_register_driver(void)
{
return i2c_add_driver(&ad5446_i2c_driver);
}
static void __exit ad5446_i2c_unregister_driver(void)
{
i2c_del_driver(&ad5446_i2c_driver);
}
#else
static inline int ad5446_i2c_register_driver(void) { return 0; }
static inline void ad5446_i2c_unregister_driver(void) { }
#endif
static int __init ad5446_init(void)
{
int ret;
ret = ad5446_spi_register_driver();
if (ret)
return ret;
ret = ad5446_i2c_register_driver();
if (ret) {
ad5446_spi_unregister_driver();
return ret;
}
return 0;
}
module_init(ad5446_init);
static void __exit ad5446_exit(void)
{
ad5446_i2c_unregister_driver();
ad5446_spi_unregister_driver();
}
module_exit(ad5446_exit);
MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5444/AD5446 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5446.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* m62332.c - Support for Mitsubishi m62332 DAC
*
* Copyright (c) 2014 Dmitry Eremin-Solenikov
*
* Based on max517 driver:
* Copyright (C) 2010, 2011 Roland Stigge <[email protected]>
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/iio/iio.h>
#include <linux/iio/driver.h>
#include <linux/regulator/consumer.h>
#define M62332_CHANNELS 2
struct m62332_data {
struct i2c_client *client;
struct regulator *vcc;
struct mutex mutex;
u8 raw[M62332_CHANNELS];
u8 save[M62332_CHANNELS];
};
static int m62332_set_value(struct iio_dev *indio_dev, u8 val, int channel)
{
struct m62332_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
u8 outbuf[2];
int res;
if (val == data->raw[channel])
return 0;
outbuf[0] = channel;
outbuf[1] = val;
mutex_lock(&data->mutex);
if (val) {
res = regulator_enable(data->vcc);
if (res)
goto out;
}
res = i2c_master_send(client, outbuf, ARRAY_SIZE(outbuf));
if (res >= 0 && res != ARRAY_SIZE(outbuf))
res = -EIO;
if (res < 0)
goto out;
data->raw[channel] = val;
if (!val)
regulator_disable(data->vcc);
mutex_unlock(&data->mutex);
return 0;
out:
mutex_unlock(&data->mutex);
return res;
}
static int m62332_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
struct m62332_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
/* Corresponds to Vref / 2^(bits) */
ret = regulator_get_voltage(data->vcc);
if (ret < 0)
return ret;
*val = ret / 1000; /* mV */
*val2 = 8;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_RAW:
*val = data->raw[chan->channel];
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
*val = 1;
return IIO_VAL_INT;
default:
break;
}
return -EINVAL;
}
static int m62332_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val < 0 || val > 255)
return -EINVAL;
return m62332_set_value(indio_dev, val, chan->channel);
default:
break;
}
return -EINVAL;
}
static int m62332_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct m62332_data *data = iio_priv(indio_dev);
int ret;
data->save[0] = data->raw[0];
data->save[1] = data->raw[1];
ret = m62332_set_value(indio_dev, 0, 0);
if (ret < 0)
return ret;
return m62332_set_value(indio_dev, 0, 1);
}
static int m62332_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct m62332_data *data = iio_priv(indio_dev);
int ret;
ret = m62332_set_value(indio_dev, data->save[0], 0);
if (ret < 0)
return ret;
return m62332_set_value(indio_dev, data->save[1], 1);
}
static DEFINE_SIMPLE_DEV_PM_OPS(m62332_pm_ops, m62332_suspend, m62332_resume);
static const struct iio_info m62332_info = {
.read_raw = m62332_read_raw,
.write_raw = m62332_write_raw,
};
#define M62332_CHANNEL(chan) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (chan), \
.datasheet_name = "CH" #chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET), \
}
static const struct iio_chan_spec m62332_channels[M62332_CHANNELS] = {
M62332_CHANNEL(0),
M62332_CHANNEL(1)
};
static int m62332_probe(struct i2c_client *client)
{
struct m62332_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
mutex_init(&data->mutex);
data->vcc = devm_regulator_get(&client->dev, "VCC");
if (IS_ERR(data->vcc))
return PTR_ERR(data->vcc);
indio_dev->num_channels = ARRAY_SIZE(m62332_channels);
indio_dev->channels = m62332_channels;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &m62332_info;
ret = iio_map_array_register(indio_dev, client->dev.platform_data);
if (ret < 0)
return ret;
ret = iio_device_register(indio_dev);
if (ret < 0)
goto err;
return 0;
err:
iio_map_array_unregister(indio_dev);
return ret;
}
static void m62332_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
iio_device_unregister(indio_dev);
iio_map_array_unregister(indio_dev);
m62332_set_value(indio_dev, 0, 0);
m62332_set_value(indio_dev, 0, 1);
}
static const struct i2c_device_id m62332_id[] = {
{ "m62332", },
{ }
};
MODULE_DEVICE_TABLE(i2c, m62332_id);
static struct i2c_driver m62332_driver = {
.driver = {
.name = "m62332",
.pm = pm_sleep_ptr(&m62332_pm_ops),
},
.probe = m62332_probe,
.remove = m62332_remove,
.id_table = m62332_id,
};
module_i2c_driver(m62332_driver);
MODULE_AUTHOR("Dmitry Eremin-Solenikov");
MODULE_DESCRIPTION("M62332 8-bit DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/m62332.c |
// SPDX-License-Identifier: GPL-2.0
/*
* AD5758 Digital to analog converters driver
*
* Copyright 2018 Analog Devices Inc.
*
* TODO: Currently CRC is not supported in this driver
*/
#include <linux/bsearch.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/property.h>
#include <linux/spi/spi.h>
#include <linux/gpio/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
/* AD5758 registers definition */
#define AD5758_NOP 0x00
#define AD5758_DAC_INPUT 0x01
#define AD5758_DAC_OUTPUT 0x02
#define AD5758_CLEAR_CODE 0x03
#define AD5758_USER_GAIN 0x04
#define AD5758_USER_OFFSET 0x05
#define AD5758_DAC_CONFIG 0x06
#define AD5758_SW_LDAC 0x07
#define AD5758_KEY 0x08
#define AD5758_GP_CONFIG1 0x09
#define AD5758_GP_CONFIG2 0x0A
#define AD5758_DCDC_CONFIG1 0x0B
#define AD5758_DCDC_CONFIG2 0x0C
#define AD5758_WDT_CONFIG 0x0F
#define AD5758_DIGITAL_DIAG_CONFIG 0x10
#define AD5758_ADC_CONFIG 0x11
#define AD5758_FAULT_PIN_CONFIG 0x12
#define AD5758_TWO_STAGE_READBACK_SELECT 0x13
#define AD5758_DIGITAL_DIAG_RESULTS 0x14
#define AD5758_ANALOG_DIAG_RESULTS 0x15
#define AD5758_STATUS 0x16
#define AD5758_CHIP_ID 0x17
#define AD5758_FREQ_MONITOR 0x18
#define AD5758_DEVICE_ID_0 0x19
#define AD5758_DEVICE_ID_1 0x1A
#define AD5758_DEVICE_ID_2 0x1B
#define AD5758_DEVICE_ID_3 0x1C
/* AD5758_DAC_CONFIG */
#define AD5758_DAC_CONFIG_RANGE_MSK GENMASK(3, 0)
#define AD5758_DAC_CONFIG_RANGE_MODE(x) (((x) & 0xF) << 0)
#define AD5758_DAC_CONFIG_INT_EN_MSK BIT(5)
#define AD5758_DAC_CONFIG_INT_EN_MODE(x) (((x) & 0x1) << 5)
#define AD5758_DAC_CONFIG_OUT_EN_MSK BIT(6)
#define AD5758_DAC_CONFIG_OUT_EN_MODE(x) (((x) & 0x1) << 6)
#define AD5758_DAC_CONFIG_SR_EN_MSK BIT(8)
#define AD5758_DAC_CONFIG_SR_EN_MODE(x) (((x) & 0x1) << 8)
#define AD5758_DAC_CONFIG_SR_CLOCK_MSK GENMASK(12, 9)
#define AD5758_DAC_CONFIG_SR_CLOCK_MODE(x) (((x) & 0xF) << 9)
#define AD5758_DAC_CONFIG_SR_STEP_MSK GENMASK(15, 13)
#define AD5758_DAC_CONFIG_SR_STEP_MODE(x) (((x) & 0x7) << 13)
/* AD5758_KEY */
#define AD5758_KEY_CODE_RESET_1 0x15FA
#define AD5758_KEY_CODE_RESET_2 0xAF51
#define AD5758_KEY_CODE_SINGLE_ADC_CONV 0x1ADC
#define AD5758_KEY_CODE_RESET_WDT 0x0D06
#define AD5758_KEY_CODE_CALIB_MEM_REFRESH 0xFCBA
/* AD5758_DCDC_CONFIG1 */
#define AD5758_DCDC_CONFIG1_DCDC_VPROG_MSK GENMASK(4, 0)
#define AD5758_DCDC_CONFIG1_DCDC_VPROG_MODE(x) (((x) & 0x1F) << 0)
#define AD5758_DCDC_CONFIG1_DCDC_MODE_MSK GENMASK(6, 5)
#define AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(x) (((x) & 0x3) << 5)
/* AD5758_DCDC_CONFIG2 */
#define AD5758_DCDC_CONFIG2_ILIMIT_MSK GENMASK(3, 1)
#define AD5758_DCDC_CONFIG2_ILIMIT_MODE(x) (((x) & 0x7) << 1)
#define AD5758_DCDC_CONFIG2_INTR_SAT_3WI_MSK BIT(11)
#define AD5758_DCDC_CONFIG2_BUSY_3WI_MSK BIT(12)
/* AD5758_DIGITAL_DIAG_RESULTS */
#define AD5758_CAL_MEM_UNREFRESHED_MSK BIT(15)
/* AD5758_ADC_CONFIG */
#define AD5758_ADC_CONFIG_PPC_BUF_EN(x) (((x) & 0x1) << 11)
#define AD5758_ADC_CONFIG_PPC_BUF_MSK BIT(11)
#define AD5758_WR_FLAG_MSK(x) (0x80 | ((x) & 0x1F))
#define AD5758_FULL_SCALE_MICRO 65535000000ULL
struct ad5758_range {
int reg;
int min;
int max;
};
/**
* struct ad5758_state - driver instance specific data
* @spi: spi_device
* @lock: mutex lock
* @gpio_reset: gpio descriptor for the reset line
* @out_range: struct which stores the output range
* @dc_dc_mode: variable which stores the mode of operation
* @dc_dc_ilim: variable which stores the dc-to-dc converter current limit
* @slew_time: variable which stores the target slew time
* @pwr_down: variable which contains whether a channel is powered down or not
* @d32: spi transfer buffers
*/
struct ad5758_state {
struct spi_device *spi;
struct mutex lock;
struct gpio_desc *gpio_reset;
struct ad5758_range out_range;
unsigned int dc_dc_mode;
unsigned int dc_dc_ilim;
unsigned int slew_time;
bool pwr_down;
__be32 d32[3];
};
/*
* Output ranges corresponding to bits [3:0] from DAC_CONFIG register
* 0000: 0 V to 5 V voltage range
* 0001: 0 V to 10 V voltage range
* 0010: ±5 V voltage range
* 0011: ±10 V voltage range
* 1000: 0 mA to 20 mA current range
* 1001: 0 mA to 24 mA current range
* 1010: 4 mA to 20 mA current range
* 1011: ±20 mA current range
* 1100: ±24 mA current range
* 1101: -1 mA to +22 mA current range
*/
enum ad5758_output_range {
AD5758_RANGE_0V_5V,
AD5758_RANGE_0V_10V,
AD5758_RANGE_PLUSMINUS_5V,
AD5758_RANGE_PLUSMINUS_10V,
AD5758_RANGE_0mA_20mA = 8,
AD5758_RANGE_0mA_24mA,
AD5758_RANGE_4mA_24mA,
AD5758_RANGE_PLUSMINUS_20mA,
AD5758_RANGE_PLUSMINUS_24mA,
AD5758_RANGE_MINUS_1mA_PLUS_22mA,
};
enum ad5758_dc_dc_mode {
AD5758_DCDC_MODE_POWER_OFF,
AD5758_DCDC_MODE_DPC_CURRENT,
AD5758_DCDC_MODE_DPC_VOLTAGE,
AD5758_DCDC_MODE_PPC_CURRENT,
};
static const struct ad5758_range ad5758_voltage_range[] = {
{ AD5758_RANGE_0V_5V, 0, 5000000 },
{ AD5758_RANGE_0V_10V, 0, 10000000 },
{ AD5758_RANGE_PLUSMINUS_5V, -5000000, 5000000 },
{ AD5758_RANGE_PLUSMINUS_10V, -10000000, 10000000 }
};
static const struct ad5758_range ad5758_current_range[] = {
{ AD5758_RANGE_0mA_20mA, 0, 20000},
{ AD5758_RANGE_0mA_24mA, 0, 24000 },
{ AD5758_RANGE_4mA_24mA, 4, 24000 },
{ AD5758_RANGE_PLUSMINUS_20mA, -20000, 20000 },
{ AD5758_RANGE_PLUSMINUS_24mA, -24000, 24000 },
{ AD5758_RANGE_MINUS_1mA_PLUS_22mA, -1000, 22000 },
};
static const int ad5758_sr_clk[16] = {
240000, 200000, 150000, 128000, 64000, 32000, 16000, 8000, 4000, 2000,
1000, 512, 256, 128, 64, 16
};
static const int ad5758_sr_step[8] = {
4, 12, 64, 120, 256, 500, 1820, 2048
};
static const int ad5758_dc_dc_ilim[6] = {
150000, 200000, 250000, 300000, 350000, 400000
};
static int ad5758_spi_reg_read(struct ad5758_state *st, unsigned int addr)
{
struct spi_transfer t[] = {
{
.tx_buf = &st->d32[0],
.len = 4,
.cs_change = 1,
}, {
.tx_buf = &st->d32[1],
.rx_buf = &st->d32[2],
.len = 4,
},
};
int ret;
st->d32[0] = cpu_to_be32(
(AD5758_WR_FLAG_MSK(AD5758_TWO_STAGE_READBACK_SELECT) << 24) |
(addr << 8));
st->d32[1] = cpu_to_be32(AD5758_WR_FLAG_MSK(AD5758_NOP) << 24);
ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
if (ret < 0)
return ret;
return (be32_to_cpu(st->d32[2]) >> 8) & 0xFFFF;
}
static int ad5758_spi_reg_write(struct ad5758_state *st,
unsigned int addr,
unsigned int val)
{
st->d32[0] = cpu_to_be32((AD5758_WR_FLAG_MSK(addr) << 24) |
((val & 0xFFFF) << 8));
return spi_write(st->spi, &st->d32[0], sizeof(st->d32[0]));
}
static int ad5758_spi_write_mask(struct ad5758_state *st,
unsigned int addr,
unsigned long int mask,
unsigned int val)
{
int regval;
regval = ad5758_spi_reg_read(st, addr);
if (regval < 0)
return regval;
regval &= ~mask;
regval |= val;
return ad5758_spi_reg_write(st, addr, regval);
}
static int cmpfunc(const void *a, const void *b)
{
return *(int *)a - *(int *)b;
}
static int ad5758_find_closest_match(const int *array,
unsigned int size, int val)
{
int i;
for (i = 0; i < size; i++) {
if (val <= array[i])
return i;
}
return size - 1;
}
static int ad5758_wait_for_task_complete(struct ad5758_state *st,
unsigned int reg,
unsigned int mask)
{
unsigned int timeout;
int ret;
timeout = 10;
do {
ret = ad5758_spi_reg_read(st, reg);
if (ret < 0)
return ret;
if (!(ret & mask))
return 0;
usleep_range(100, 1000);
} while (--timeout);
dev_err(&st->spi->dev,
"Error reading bit 0x%x in 0x%x register\n", mask, reg);
return -EIO;
}
static int ad5758_calib_mem_refresh(struct ad5758_state *st)
{
int ret;
ret = ad5758_spi_reg_write(st, AD5758_KEY,
AD5758_KEY_CODE_CALIB_MEM_REFRESH);
if (ret < 0) {
dev_err(&st->spi->dev,
"Failed to initiate a calibration memory refresh\n");
return ret;
}
/* Wait to allow time for the internal calibrations to complete */
return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
AD5758_CAL_MEM_UNREFRESHED_MSK);
}
static int ad5758_soft_reset(struct ad5758_state *st)
{
int ret;
ret = ad5758_spi_reg_write(st, AD5758_KEY, AD5758_KEY_CODE_RESET_1);
if (ret < 0)
return ret;
ret = ad5758_spi_reg_write(st, AD5758_KEY, AD5758_KEY_CODE_RESET_2);
/* Perform a software reset and wait at least 100us */
usleep_range(100, 1000);
return ret;
}
static int ad5758_set_dc_dc_conv_mode(struct ad5758_state *st,
enum ad5758_dc_dc_mode mode)
{
int ret;
/*
* The ENABLE_PPC_BUFFERS bit must be set prior to enabling PPC current
* mode.
*/
if (mode == AD5758_DCDC_MODE_PPC_CURRENT) {
ret = ad5758_spi_write_mask(st, AD5758_ADC_CONFIG,
AD5758_ADC_CONFIG_PPC_BUF_MSK,
AD5758_ADC_CONFIG_PPC_BUF_EN(1));
if (ret < 0)
return ret;
}
ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG1,
AD5758_DCDC_CONFIG1_DCDC_MODE_MSK,
AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(mode));
if (ret < 0)
return ret;
/*
* Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0.
* This allows the 3-wire interface communication to complete.
*/
ret = ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2,
AD5758_DCDC_CONFIG2_BUSY_3WI_MSK);
if (ret < 0)
return ret;
st->dc_dc_mode = mode;
return ret;
}
static int ad5758_set_dc_dc_ilim(struct ad5758_state *st, unsigned int ilim)
{
int ret;
ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG2,
AD5758_DCDC_CONFIG2_ILIMIT_MSK,
AD5758_DCDC_CONFIG2_ILIMIT_MODE(ilim));
if (ret < 0)
return ret;
/*
* Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0.
* This allows the 3-wire interface communication to complete.
*/
return ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2,
AD5758_DCDC_CONFIG2_BUSY_3WI_MSK);
}
static int ad5758_slew_rate_set(struct ad5758_state *st,
unsigned int sr_clk_idx,
unsigned int sr_step_idx)
{
unsigned int mode;
unsigned long int mask;
int ret;
mask = AD5758_DAC_CONFIG_SR_EN_MSK |
AD5758_DAC_CONFIG_SR_CLOCK_MSK |
AD5758_DAC_CONFIG_SR_STEP_MSK;
mode = AD5758_DAC_CONFIG_SR_EN_MODE(1) |
AD5758_DAC_CONFIG_SR_STEP_MODE(sr_step_idx) |
AD5758_DAC_CONFIG_SR_CLOCK_MODE(sr_clk_idx);
ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, mask, mode);
if (ret < 0)
return ret;
/* Wait to allow time for the internal calibrations to complete */
return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
AD5758_CAL_MEM_UNREFRESHED_MSK);
}
static int ad5758_slew_rate_config(struct ad5758_state *st)
{
unsigned int sr_clk_idx, sr_step_idx;
int i, res;
s64 diff_new, diff_old;
u64 sr_step, calc_slew_time;
sr_clk_idx = 0;
sr_step_idx = 0;
diff_old = S64_MAX;
/*
* The slew time can be determined by using the formula:
* Slew Time = (Full Scale Out / (Step Size x Update Clk Freq))
* where Slew time is expressed in microseconds
* Given the desired slew time, the following algorithm determines the
* best match for the step size and the update clock frequency.
*/
for (i = 0; i < ARRAY_SIZE(ad5758_sr_clk); i++) {
/*
* Go through each valid update clock freq and determine a raw
* value for the step size by using the formula:
* Step Size = Full Scale Out / (Update Clk Freq * Slew Time)
*/
sr_step = AD5758_FULL_SCALE_MICRO;
do_div(sr_step, ad5758_sr_clk[i]);
do_div(sr_step, st->slew_time);
/*
* After a raw value for step size was determined, find the
* closest valid match
*/
res = ad5758_find_closest_match(ad5758_sr_step,
ARRAY_SIZE(ad5758_sr_step),
sr_step);
/* Calculate the slew time */
calc_slew_time = AD5758_FULL_SCALE_MICRO;
do_div(calc_slew_time, ad5758_sr_step[res]);
do_div(calc_slew_time, ad5758_sr_clk[i]);
/*
* Determine with how many microseconds the calculated slew time
* is different from the desired slew time and store the diff
* for the next iteration
*/
diff_new = abs(st->slew_time - calc_slew_time);
if (diff_new < diff_old) {
diff_old = diff_new;
sr_clk_idx = i;
sr_step_idx = res;
}
}
return ad5758_slew_rate_set(st, sr_clk_idx, sr_step_idx);
}
static int ad5758_set_out_range(struct ad5758_state *st, int range)
{
int ret;
ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
AD5758_DAC_CONFIG_RANGE_MSK,
AD5758_DAC_CONFIG_RANGE_MODE(range));
if (ret < 0)
return ret;
/* Wait to allow time for the internal calibrations to complete */
return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
AD5758_CAL_MEM_UNREFRESHED_MSK);
}
static int ad5758_internal_buffers_en(struct ad5758_state *st, bool enable)
{
int ret;
ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
AD5758_DAC_CONFIG_INT_EN_MSK,
AD5758_DAC_CONFIG_INT_EN_MODE(enable));
if (ret < 0)
return ret;
/* Wait to allow time for the internal calibrations to complete */
return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
AD5758_CAL_MEM_UNREFRESHED_MSK);
}
static int ad5758_reset(struct ad5758_state *st)
{
if (st->gpio_reset) {
gpiod_set_value(st->gpio_reset, 0);
usleep_range(100, 1000);
gpiod_set_value(st->gpio_reset, 1);
usleep_range(100, 1000);
return 0;
} else {
/* Perform a software reset */
return ad5758_soft_reset(st);
}
}
static int ad5758_reg_access(struct iio_dev *indio_dev,
unsigned int reg,
unsigned int writeval,
unsigned int *readval)
{
struct ad5758_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
if (readval) {
ret = ad5758_spi_reg_read(st, reg);
if (ret < 0) {
mutex_unlock(&st->lock);
return ret;
}
*readval = ret;
ret = 0;
} else {
ret = ad5758_spi_reg_write(st, reg, writeval);
}
mutex_unlock(&st->lock);
return ret;
}
static int ad5758_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
{
struct ad5758_state *st = iio_priv(indio_dev);
int max, min, ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&st->lock);
ret = ad5758_spi_reg_read(st, AD5758_DAC_INPUT);
mutex_unlock(&st->lock);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
min = st->out_range.min;
max = st->out_range.max;
*val = (max - min) / 1000;
*val2 = 16;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_OFFSET:
min = st->out_range.min;
max = st->out_range.max;
*val = ((min * (1 << 16)) / (max - min)) / 1000;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int ad5758_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long info)
{
struct ad5758_state *st = iio_priv(indio_dev);
int ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&st->lock);
ret = ad5758_spi_reg_write(st, AD5758_DAC_INPUT, val);
mutex_unlock(&st->lock);
return ret;
default:
return -EINVAL;
}
}
static ssize_t ad5758_read_powerdown(struct iio_dev *indio_dev,
uintptr_t priv,
const struct iio_chan_spec *chan,
char *buf)
{
struct ad5758_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", st->pwr_down);
}
static ssize_t ad5758_write_powerdown(struct iio_dev *indio_dev,
uintptr_t priv,
struct iio_chan_spec const *chan,
const char *buf, size_t len)
{
struct ad5758_state *st = iio_priv(indio_dev);
bool pwr_down;
unsigned int dac_config_mode, val;
unsigned long int dac_config_msk;
int ret;
ret = kstrtobool(buf, &pwr_down);
if (ret)
return ret;
mutex_lock(&st->lock);
if (pwr_down)
val = 0;
else
val = 1;
dac_config_mode = AD5758_DAC_CONFIG_OUT_EN_MODE(val) |
AD5758_DAC_CONFIG_INT_EN_MODE(val);
dac_config_msk = AD5758_DAC_CONFIG_OUT_EN_MSK |
AD5758_DAC_CONFIG_INT_EN_MSK;
ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
dac_config_msk,
dac_config_mode);
if (ret < 0)
goto err_unlock;
st->pwr_down = pwr_down;
err_unlock:
mutex_unlock(&st->lock);
return ret ? ret : len;
}
static const struct iio_info ad5758_info = {
.read_raw = ad5758_read_raw,
.write_raw = ad5758_write_raw,
.debugfs_reg_access = &ad5758_reg_access,
};
static const struct iio_chan_spec_ext_info ad5758_ext_info[] = {
{
.name = "powerdown",
.read = ad5758_read_powerdown,
.write = ad5758_write_powerdown,
.shared = IIO_SHARED_BY_TYPE,
},
{ }
};
#define AD5758_DAC_CHAN(_chan_type) { \
.type = (_chan_type), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET), \
.indexed = 1, \
.output = 1, \
.ext_info = ad5758_ext_info, \
}
static const struct iio_chan_spec ad5758_voltage_ch[] = {
AD5758_DAC_CHAN(IIO_VOLTAGE)
};
static const struct iio_chan_spec ad5758_current_ch[] = {
AD5758_DAC_CHAN(IIO_CURRENT)
};
static bool ad5758_is_valid_mode(enum ad5758_dc_dc_mode mode)
{
switch (mode) {
case AD5758_DCDC_MODE_DPC_CURRENT:
case AD5758_DCDC_MODE_DPC_VOLTAGE:
case AD5758_DCDC_MODE_PPC_CURRENT:
return true;
default:
return false;
}
}
static int ad5758_crc_disable(struct ad5758_state *st)
{
unsigned int mask;
mask = (AD5758_WR_FLAG_MSK(AD5758_DIGITAL_DIAG_CONFIG) << 24) | 0x5C3A;
st->d32[0] = cpu_to_be32(mask);
return spi_write(st->spi, &st->d32[0], 4);
}
static int ad5758_find_out_range(struct ad5758_state *st,
const struct ad5758_range *range,
unsigned int size,
int min, int max)
{
int i;
for (i = 0; i < size; i++) {
if ((min == range[i].min) && (max == range[i].max)) {
st->out_range.reg = range[i].reg;
st->out_range.min = range[i].min;
st->out_range.max = range[i].max;
return 0;
}
}
return -EINVAL;
}
static int ad5758_parse_dt(struct ad5758_state *st)
{
unsigned int tmp, tmparray[2], size;
const struct ad5758_range *range;
int *index, ret;
st->dc_dc_ilim = 0;
ret = device_property_read_u32(&st->spi->dev,
"adi,dc-dc-ilim-microamp", &tmp);
if (ret) {
dev_dbg(&st->spi->dev,
"Missing \"dc-dc-ilim-microamp\" property\n");
} else {
index = bsearch(&tmp, ad5758_dc_dc_ilim,
ARRAY_SIZE(ad5758_dc_dc_ilim),
sizeof(int), cmpfunc);
if (!index)
dev_dbg(&st->spi->dev, "dc-dc-ilim out of range\n");
else
st->dc_dc_ilim = index - ad5758_dc_dc_ilim;
}
ret = device_property_read_u32(&st->spi->dev, "adi,dc-dc-mode",
&st->dc_dc_mode);
if (ret) {
dev_err(&st->spi->dev, "Missing \"dc-dc-mode\" property\n");
return ret;
}
if (!ad5758_is_valid_mode(st->dc_dc_mode))
return -EINVAL;
if (st->dc_dc_mode == AD5758_DCDC_MODE_DPC_VOLTAGE) {
ret = device_property_read_u32_array(&st->spi->dev,
"adi,range-microvolt",
tmparray, 2);
if (ret) {
dev_err(&st->spi->dev,
"Missing \"range-microvolt\" property\n");
return ret;
}
range = ad5758_voltage_range;
size = ARRAY_SIZE(ad5758_voltage_range);
} else {
ret = device_property_read_u32_array(&st->spi->dev,
"adi,range-microamp",
tmparray, 2);
if (ret) {
dev_err(&st->spi->dev,
"Missing \"range-microamp\" property\n");
return ret;
}
range = ad5758_current_range;
size = ARRAY_SIZE(ad5758_current_range);
}
ret = ad5758_find_out_range(st, range, size, tmparray[0], tmparray[1]);
if (ret) {
dev_err(&st->spi->dev, "range invalid\n");
return ret;
}
ret = device_property_read_u32(&st->spi->dev, "adi,slew-time-us", &tmp);
if (ret) {
dev_dbg(&st->spi->dev, "Missing \"slew-time-us\" property\n");
st->slew_time = 0;
} else {
st->slew_time = tmp;
}
return 0;
}
static int ad5758_init(struct ad5758_state *st)
{
int regval, ret;
st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(st->gpio_reset))
return PTR_ERR(st->gpio_reset);
/* Disable CRC checks */
ret = ad5758_crc_disable(st);
if (ret < 0)
return ret;
/* Perform a reset */
ret = ad5758_reset(st);
if (ret < 0)
return ret;
/* Disable CRC checks */
ret = ad5758_crc_disable(st);
if (ret < 0)
return ret;
/* Perform a calibration memory refresh */
ret = ad5758_calib_mem_refresh(st);
if (ret < 0)
return ret;
regval = ad5758_spi_reg_read(st, AD5758_DIGITAL_DIAG_RESULTS);
if (regval < 0)
return regval;
/* Clear all the error flags */
ret = ad5758_spi_reg_write(st, AD5758_DIGITAL_DIAG_RESULTS, regval);
if (ret < 0)
return ret;
/* Set the dc-to-dc current limit */
ret = ad5758_set_dc_dc_ilim(st, st->dc_dc_ilim);
if (ret < 0)
return ret;
/* Configure the dc-to-dc controller mode */
ret = ad5758_set_dc_dc_conv_mode(st, st->dc_dc_mode);
if (ret < 0)
return ret;
/* Configure the output range */
ret = ad5758_set_out_range(st, st->out_range.reg);
if (ret < 0)
return ret;
/* Enable Slew Rate Control, set the slew rate clock and step */
if (st->slew_time) {
ret = ad5758_slew_rate_config(st);
if (ret < 0)
return ret;
}
/* Power up the DAC and internal (INT) amplifiers */
ret = ad5758_internal_buffers_en(st, 1);
if (ret < 0)
return ret;
/* Enable VIOUT */
return ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
AD5758_DAC_CONFIG_OUT_EN_MSK,
AD5758_DAC_CONFIG_OUT_EN_MODE(1));
}
static int ad5758_probe(struct spi_device *spi)
{
struct ad5758_state *st;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
st->spi = spi;
mutex_init(&st->lock);
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->info = &ad5758_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->num_channels = 1;
ret = ad5758_parse_dt(st);
if (ret < 0)
return ret;
if (st->dc_dc_mode == AD5758_DCDC_MODE_DPC_VOLTAGE)
indio_dev->channels = ad5758_voltage_ch;
else
indio_dev->channels = ad5758_current_ch;
ret = ad5758_init(st);
if (ret < 0) {
dev_err(&spi->dev, "AD5758 init failed\n");
return ret;
}
return devm_iio_device_register(&st->spi->dev, indio_dev);
}
static const struct spi_device_id ad5758_id[] = {
{ "ad5758", 0 },
{}
};
MODULE_DEVICE_TABLE(spi, ad5758_id);
static const struct of_device_id ad5758_of_match[] = {
{ .compatible = "adi,ad5758" },
{ },
};
MODULE_DEVICE_TABLE(of, ad5758_of_match);
static struct spi_driver ad5758_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = ad5758_of_match,
},
.probe = ad5758_probe,
.id_table = ad5758_id,
};
module_spi_driver(ad5758_driver);
MODULE_AUTHOR("Stefan Popa <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5758 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5758.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Analog devices AD5380, AD5381, AD5382, AD5383, AD5390, AD5391, AD5392
* multi-channel Digital to Analog Converters driver
*
* Copyright 2011 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define AD5380_REG_DATA(x) (((x) << 2) | 3)
#define AD5380_REG_OFFSET(x) (((x) << 2) | 2)
#define AD5380_REG_GAIN(x) (((x) << 2) | 1)
#define AD5380_REG_SF_PWR_DOWN (8 << 2)
#define AD5380_REG_SF_PWR_UP (9 << 2)
#define AD5380_REG_SF_CTRL (12 << 2)
#define AD5380_CTRL_PWR_DOWN_MODE_OFFSET 13
#define AD5380_CTRL_INT_VREF_2V5 BIT(12)
#define AD5380_CTRL_INT_VREF_EN BIT(10)
/**
* struct ad5380_chip_info - chip specific information
* @channel_template: channel specification template
* @num_channels: number of channels
* @int_vref: internal vref in uV
*/
struct ad5380_chip_info {
struct iio_chan_spec channel_template;
unsigned int num_channels;
unsigned int int_vref;
};
/**
* struct ad5380_state - driver instance specific data
* @regmap: regmap instance used by the device
* @chip_info: chip model specific constants, available modes etc
* @vref_reg: vref supply regulator
* @vref: actual reference voltage used in uA
* @pwr_down: whether the chip is currently in power down mode
* @lock: lock to protect the data buffer during regmap ops
*/
struct ad5380_state {
struct regmap *regmap;
const struct ad5380_chip_info *chip_info;
struct regulator *vref_reg;
int vref;
bool pwr_down;
struct mutex lock;
};
enum ad5380_type {
ID_AD5380_3,
ID_AD5380_5,
ID_AD5381_3,
ID_AD5381_5,
ID_AD5382_3,
ID_AD5382_5,
ID_AD5383_3,
ID_AD5383_5,
ID_AD5390_3,
ID_AD5390_5,
ID_AD5391_3,
ID_AD5391_5,
ID_AD5392_3,
ID_AD5392_5,
};
static ssize_t ad5380_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
struct ad5380_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", st->pwr_down);
}
static ssize_t ad5380_write_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
size_t len)
{
struct ad5380_state *st = iio_priv(indio_dev);
bool pwr_down;
int ret;
ret = kstrtobool(buf, &pwr_down);
if (ret)
return ret;
mutex_lock(&st->lock);
if (pwr_down)
ret = regmap_write(st->regmap, AD5380_REG_SF_PWR_DOWN, 0);
else
ret = regmap_write(st->regmap, AD5380_REG_SF_PWR_UP, 0);
st->pwr_down = pwr_down;
mutex_unlock(&st->lock);
return ret ? ret : len;
}
static const char * const ad5380_powerdown_modes[] = {
"100kohm_to_gnd",
"three_state",
};
static int ad5380_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct ad5380_state *st = iio_priv(indio_dev);
unsigned int mode;
int ret;
ret = regmap_read(st->regmap, AD5380_REG_SF_CTRL, &mode);
if (ret)
return ret;
mode = (mode >> AD5380_CTRL_PWR_DOWN_MODE_OFFSET) & 1;
return mode;
}
static int ad5380_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, unsigned int mode)
{
struct ad5380_state *st = iio_priv(indio_dev);
int ret;
ret = regmap_update_bits(st->regmap, AD5380_REG_SF_CTRL,
1 << AD5380_CTRL_PWR_DOWN_MODE_OFFSET,
mode << AD5380_CTRL_PWR_DOWN_MODE_OFFSET);
return ret;
}
static const struct iio_enum ad5380_powerdown_mode_enum = {
.items = ad5380_powerdown_modes,
.num_items = ARRAY_SIZE(ad5380_powerdown_modes),
.get = ad5380_get_powerdown_mode,
.set = ad5380_set_powerdown_mode,
};
static unsigned int ad5380_info_to_reg(struct iio_chan_spec const *chan,
long info)
{
switch (info) {
case IIO_CHAN_INFO_RAW:
return AD5380_REG_DATA(chan->address);
case IIO_CHAN_INFO_CALIBBIAS:
return AD5380_REG_OFFSET(chan->address);
case IIO_CHAN_INFO_CALIBSCALE:
return AD5380_REG_GAIN(chan->address);
default:
break;
}
return 0;
}
static int ad5380_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long info)
{
const unsigned int max_val = (1 << chan->scan_type.realbits);
struct ad5380_state *st = iio_priv(indio_dev);
switch (info) {
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_CALIBSCALE:
if (val >= max_val || val < 0)
return -EINVAL;
return regmap_write(st->regmap,
ad5380_info_to_reg(chan, info),
val << chan->scan_type.shift);
case IIO_CHAN_INFO_CALIBBIAS:
val += (1 << chan->scan_type.realbits) / 2;
if (val >= max_val || val < 0)
return -EINVAL;
return regmap_write(st->regmap,
AD5380_REG_OFFSET(chan->address),
val << chan->scan_type.shift);
default:
break;
}
return -EINVAL;
}
static int ad5380_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long info)
{
struct ad5380_state *st = iio_priv(indio_dev);
int ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_CALIBSCALE:
ret = regmap_read(st->regmap, ad5380_info_to_reg(chan, info),
val);
if (ret)
return ret;
*val >>= chan->scan_type.shift;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBBIAS:
ret = regmap_read(st->regmap, AD5380_REG_OFFSET(chan->address),
val);
if (ret)
return ret;
*val >>= chan->scan_type.shift;
*val -= (1 << chan->scan_type.realbits) / 2;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 2 * st->vref;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
default:
break;
}
return -EINVAL;
}
static const struct iio_info ad5380_info = {
.read_raw = ad5380_read_raw,
.write_raw = ad5380_write_raw,
};
static const struct iio_chan_spec_ext_info ad5380_ext_info[] = {
{
.name = "powerdown",
.read = ad5380_read_dac_powerdown,
.write = ad5380_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE,
&ad5380_powerdown_mode_enum),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5380_powerdown_mode_enum),
{ },
};
#define AD5380_CHANNEL(_bits) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_CALIBSCALE) | \
BIT(IIO_CHAN_INFO_CALIBBIAS), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.scan_type = { \
.sign = 'u', \
.realbits = (_bits), \
.storagebits = 16, \
.shift = 14 - (_bits), \
}, \
.ext_info = ad5380_ext_info, \
}
static const struct ad5380_chip_info ad5380_chip_info_tbl[] = {
[ID_AD5380_3] = {
.channel_template = AD5380_CHANNEL(14),
.num_channels = 40,
.int_vref = 1250,
},
[ID_AD5380_5] = {
.channel_template = AD5380_CHANNEL(14),
.num_channels = 40,
.int_vref = 2500,
},
[ID_AD5381_3] = {
.channel_template = AD5380_CHANNEL(12),
.num_channels = 16,
.int_vref = 1250,
},
[ID_AD5381_5] = {
.channel_template = AD5380_CHANNEL(12),
.num_channels = 16,
.int_vref = 2500,
},
[ID_AD5382_3] = {
.channel_template = AD5380_CHANNEL(14),
.num_channels = 32,
.int_vref = 1250,
},
[ID_AD5382_5] = {
.channel_template = AD5380_CHANNEL(14),
.num_channels = 32,
.int_vref = 2500,
},
[ID_AD5383_3] = {
.channel_template = AD5380_CHANNEL(12),
.num_channels = 32,
.int_vref = 1250,
},
[ID_AD5383_5] = {
.channel_template = AD5380_CHANNEL(12),
.num_channels = 32,
.int_vref = 2500,
},
[ID_AD5390_3] = {
.channel_template = AD5380_CHANNEL(14),
.num_channels = 16,
.int_vref = 1250,
},
[ID_AD5390_5] = {
.channel_template = AD5380_CHANNEL(14),
.num_channels = 16,
.int_vref = 2500,
},
[ID_AD5391_3] = {
.channel_template = AD5380_CHANNEL(12),
.num_channels = 16,
.int_vref = 1250,
},
[ID_AD5391_5] = {
.channel_template = AD5380_CHANNEL(12),
.num_channels = 16,
.int_vref = 2500,
},
[ID_AD5392_3] = {
.channel_template = AD5380_CHANNEL(14),
.num_channels = 8,
.int_vref = 1250,
},
[ID_AD5392_5] = {
.channel_template = AD5380_CHANNEL(14),
.num_channels = 8,
.int_vref = 2500,
},
};
static int ad5380_alloc_channels(struct iio_dev *indio_dev)
{
struct ad5380_state *st = iio_priv(indio_dev);
struct iio_chan_spec *channels;
unsigned int i;
channels = kcalloc(st->chip_info->num_channels,
sizeof(struct iio_chan_spec), GFP_KERNEL);
if (!channels)
return -ENOMEM;
for (i = 0; i < st->chip_info->num_channels; ++i) {
channels[i] = st->chip_info->channel_template;
channels[i].channel = i;
channels[i].address = i;
}
indio_dev->channels = channels;
return 0;
}
static int ad5380_probe(struct device *dev, struct regmap *regmap,
enum ad5380_type type, const char *name)
{
struct iio_dev *indio_dev;
struct ad5380_state *st;
unsigned int ctrl = 0;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
if (indio_dev == NULL) {
dev_err(dev, "Failed to allocate iio device\n");
return -ENOMEM;
}
st = iio_priv(indio_dev);
dev_set_drvdata(dev, indio_dev);
st->chip_info = &ad5380_chip_info_tbl[type];
st->regmap = regmap;
indio_dev->name = name;
indio_dev->info = &ad5380_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->num_channels = st->chip_info->num_channels;
mutex_init(&st->lock);
ret = ad5380_alloc_channels(indio_dev);
if (ret) {
dev_err(dev, "Failed to allocate channel spec: %d\n", ret);
return ret;
}
if (st->chip_info->int_vref == 2500)
ctrl |= AD5380_CTRL_INT_VREF_2V5;
st->vref_reg = devm_regulator_get(dev, "vref");
if (!IS_ERR(st->vref_reg)) {
ret = regulator_enable(st->vref_reg);
if (ret) {
dev_err(dev, "Failed to enable vref regulators: %d\n",
ret);
goto error_free_reg;
}
ret = regulator_get_voltage(st->vref_reg);
if (ret < 0)
goto error_disable_reg;
st->vref = ret / 1000;
} else {
st->vref = st->chip_info->int_vref;
ctrl |= AD5380_CTRL_INT_VREF_EN;
}
ret = regmap_write(st->regmap, AD5380_REG_SF_CTRL, ctrl);
if (ret) {
dev_err(dev, "Failed to write to device: %d\n", ret);
goto error_disable_reg;
}
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(dev, "Failed to register iio device: %d\n", ret);
goto error_disable_reg;
}
return 0;
error_disable_reg:
if (!IS_ERR(st->vref_reg))
regulator_disable(st->vref_reg);
error_free_reg:
kfree(indio_dev->channels);
return ret;
}
static void ad5380_remove(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct ad5380_state *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
kfree(indio_dev->channels);
if (!IS_ERR(st->vref_reg))
regulator_disable(st->vref_reg);
}
static bool ad5380_reg_false(struct device *dev, unsigned int reg)
{
return false;
}
static const struct regmap_config ad5380_regmap_config = {
.reg_bits = 10,
.val_bits = 14,
.max_register = AD5380_REG_DATA(40),
.cache_type = REGCACHE_RBTREE,
.volatile_reg = ad5380_reg_false,
.readable_reg = ad5380_reg_false,
};
#if IS_ENABLED(CONFIG_SPI_MASTER)
static int ad5380_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct regmap *regmap;
regmap = devm_regmap_init_spi(spi, &ad5380_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return ad5380_probe(&spi->dev, regmap, id->driver_data, id->name);
}
static void ad5380_spi_remove(struct spi_device *spi)
{
ad5380_remove(&spi->dev);
}
static const struct spi_device_id ad5380_spi_ids[] = {
{ "ad5380-3", ID_AD5380_3 },
{ "ad5380-5", ID_AD5380_5 },
{ "ad5381-3", ID_AD5381_3 },
{ "ad5381-5", ID_AD5381_5 },
{ "ad5382-3", ID_AD5382_3 },
{ "ad5382-5", ID_AD5382_5 },
{ "ad5383-3", ID_AD5383_3 },
{ "ad5383-5", ID_AD5383_5 },
{ "ad5384-3", ID_AD5380_3 },
{ "ad5384-5", ID_AD5380_5 },
{ "ad5390-3", ID_AD5390_3 },
{ "ad5390-5", ID_AD5390_5 },
{ "ad5391-3", ID_AD5391_3 },
{ "ad5391-5", ID_AD5391_5 },
{ "ad5392-3", ID_AD5392_3 },
{ "ad5392-5", ID_AD5392_5 },
{ }
};
MODULE_DEVICE_TABLE(spi, ad5380_spi_ids);
static struct spi_driver ad5380_spi_driver = {
.driver = {
.name = "ad5380",
},
.probe = ad5380_spi_probe,
.remove = ad5380_spi_remove,
.id_table = ad5380_spi_ids,
};
static inline int ad5380_spi_register_driver(void)
{
return spi_register_driver(&ad5380_spi_driver);
}
static inline void ad5380_spi_unregister_driver(void)
{
spi_unregister_driver(&ad5380_spi_driver);
}
#else
static inline int ad5380_spi_register_driver(void)
{
return 0;
}
static inline void ad5380_spi_unregister_driver(void)
{
}
#endif
#if IS_ENABLED(CONFIG_I2C)
static int ad5380_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct regmap *regmap;
regmap = devm_regmap_init_i2c(i2c, &ad5380_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return ad5380_probe(&i2c->dev, regmap, id->driver_data, id->name);
}
static void ad5380_i2c_remove(struct i2c_client *i2c)
{
ad5380_remove(&i2c->dev);
}
static const struct i2c_device_id ad5380_i2c_ids[] = {
{ "ad5380-3", ID_AD5380_3 },
{ "ad5380-5", ID_AD5380_5 },
{ "ad5381-3", ID_AD5381_3 },
{ "ad5381-5", ID_AD5381_5 },
{ "ad5382-3", ID_AD5382_3 },
{ "ad5382-5", ID_AD5382_5 },
{ "ad5383-3", ID_AD5383_3 },
{ "ad5383-5", ID_AD5383_5 },
{ "ad5384-3", ID_AD5380_3 },
{ "ad5384-5", ID_AD5380_5 },
{ "ad5390-3", ID_AD5390_3 },
{ "ad5390-5", ID_AD5390_5 },
{ "ad5391-3", ID_AD5391_3 },
{ "ad5391-5", ID_AD5391_5 },
{ "ad5392-3", ID_AD5392_3 },
{ "ad5392-5", ID_AD5392_5 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ad5380_i2c_ids);
static struct i2c_driver ad5380_i2c_driver = {
.driver = {
.name = "ad5380",
},
.probe = ad5380_i2c_probe,
.remove = ad5380_i2c_remove,
.id_table = ad5380_i2c_ids,
};
static inline int ad5380_i2c_register_driver(void)
{
return i2c_add_driver(&ad5380_i2c_driver);
}
static inline void ad5380_i2c_unregister_driver(void)
{
i2c_del_driver(&ad5380_i2c_driver);
}
#else
static inline int ad5380_i2c_register_driver(void)
{
return 0;
}
static inline void ad5380_i2c_unregister_driver(void)
{
}
#endif
static int __init ad5380_spi_init(void)
{
int ret;
ret = ad5380_spi_register_driver();
if (ret)
return ret;
ret = ad5380_i2c_register_driver();
if (ret) {
ad5380_spi_unregister_driver();
return ret;
}
return 0;
}
module_init(ad5380_spi_init);
static void __exit ad5380_spi_exit(void)
{
ad5380_i2c_unregister_driver();
ad5380_spi_unregister_driver();
}
module_exit(ad5380_spi_exit);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5380/81/82/83/84/90/91/92 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5380.c |
// SPDX-License-Identifier: GPL-2.0
/*
* LTC2688 16 channel, 16 bit Voltage Output SoftSpan DAC driver
*
* Copyright 2022 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/iio/iio.h>
#include <linux/limits.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#define LTC2688_DAC_CHANNELS 16
#define LTC2688_CMD_CH_CODE(x) (0x00 + (x))
#define LTC2688_CMD_CH_SETTING(x) (0x10 + (x))
#define LTC2688_CMD_CH_OFFSET(x) (0X20 + (x))
#define LTC2688_CMD_CH_GAIN(x) (0x30 + (x))
#define LTC2688_CMD_CH_CODE_UPDATE(x) (0x40 + (x))
#define LTC2688_CMD_CONFIG 0x70
#define LTC2688_CMD_POWERDOWN 0x71
#define LTC2688_CMD_A_B_SELECT 0x72
#define LTC2688_CMD_SW_TOGGLE 0x73
#define LTC2688_CMD_TOGGLE_DITHER_EN 0x74
#define LTC2688_CMD_THERMAL_STAT 0x77
#define LTC2688_CMD_UPDATE_ALL 0x7C
#define LTC2688_CMD_NOOP 0xFF
#define LTC2688_READ_OPERATION 0x80
/* Channel Settings */
#define LTC2688_CH_SPAN_MSK GENMASK(2, 0)
#define LTC2688_CH_OVERRANGE_MSK BIT(3)
#define LTC2688_CH_TD_SEL_MSK GENMASK(5, 4)
#define LTC2688_CH_TGP_MAX 3
#define LTC2688_CH_DIT_PER_MSK GENMASK(8, 6)
#define LTC2688_CH_DIT_PH_MSK GENMASK(10, 9)
#define LTC2688_CH_MODE_MSK BIT(11)
#define LTC2688_DITHER_RAW_MASK GENMASK(15, 2)
#define LTC2688_CH_CALIBBIAS_MASK GENMASK(15, 2)
#define LTC2688_DITHER_RAW_MAX_VAL (BIT(14) - 1)
#define LTC2688_CH_CALIBBIAS_MAX_VAL (BIT(14) - 1)
/* Configuration register */
#define LTC2688_CONFIG_RST BIT(15)
#define LTC2688_CONFIG_EXT_REF BIT(1)
#define LTC2688_DITHER_FREQ_AVAIL_N 5
enum {
LTC2688_SPAN_RANGE_0V_5V,
LTC2688_SPAN_RANGE_0V_10V,
LTC2688_SPAN_RANGE_M5V_5V,
LTC2688_SPAN_RANGE_M10V_10V,
LTC2688_SPAN_RANGE_M15V_15V,
LTC2688_SPAN_RANGE_MAX
};
enum {
LTC2688_MODE_DEFAULT,
LTC2688_MODE_DITHER_TOGGLE,
};
struct ltc2688_chan {
long dither_frequency[LTC2688_DITHER_FREQ_AVAIL_N];
bool overrange;
bool toggle_chan;
u8 mode;
};
struct ltc2688_state {
struct spi_device *spi;
struct regmap *regmap;
struct ltc2688_chan channels[LTC2688_DAC_CHANNELS];
struct iio_chan_spec *iio_chan;
/* lock to protect against multiple access to the device and shared data */
struct mutex lock;
int vref;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
u8 tx_data[6] __aligned(IIO_DMA_MINALIGN);
u8 rx_data[3];
};
static int ltc2688_spi_read(void *context, const void *reg, size_t reg_size,
void *val, size_t val_size)
{
struct ltc2688_state *st = context;
struct spi_transfer xfers[] = {
{
.tx_buf = st->tx_data,
.bits_per_word = 8,
.len = reg_size + val_size,
.cs_change = 1,
}, {
.tx_buf = st->tx_data + 3,
.rx_buf = st->rx_data,
.bits_per_word = 8,
.len = reg_size + val_size,
},
};
int ret;
memcpy(st->tx_data, reg, reg_size);
ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
if (ret)
return ret;
memcpy(val, &st->rx_data[1], val_size);
return 0;
}
static int ltc2688_spi_write(void *context, const void *data, size_t count)
{
struct ltc2688_state *st = context;
return spi_write(st->spi, data, count);
}
static int ltc2688_span_get(const struct ltc2688_state *st, int c)
{
int ret, reg, span;
ret = regmap_read(st->regmap, LTC2688_CMD_CH_SETTING(c), ®);
if (ret)
return ret;
span = FIELD_GET(LTC2688_CH_SPAN_MSK, reg);
/* sanity check to make sure we don't get any weird value from the HW */
if (span >= LTC2688_SPAN_RANGE_MAX)
return -EIO;
return span;
}
static const int ltc2688_span_helper[LTC2688_SPAN_RANGE_MAX][2] = {
{0, 5000}, {0, 10000}, {-5000, 5000}, {-10000, 10000}, {-15000, 15000},
};
static int ltc2688_scale_get(const struct ltc2688_state *st, int c, int *val)
{
const struct ltc2688_chan *chan = &st->channels[c];
int span, fs;
span = ltc2688_span_get(st, c);
if (span < 0)
return span;
fs = ltc2688_span_helper[span][1] - ltc2688_span_helper[span][0];
if (chan->overrange)
fs = mult_frac(fs, 105, 100);
*val = DIV_ROUND_CLOSEST(fs * st->vref, 4096);
return 0;
}
static int ltc2688_offset_get(const struct ltc2688_state *st, int c, int *val)
{
int span;
span = ltc2688_span_get(st, c);
if (span < 0)
return span;
if (ltc2688_span_helper[span][0] < 0)
*val = -32768;
else
*val = 0;
return 0;
}
enum {
LTC2688_INPUT_A,
LTC2688_INPUT_B,
LTC2688_INPUT_B_AVAIL,
LTC2688_DITHER_OFF,
LTC2688_DITHER_FREQ_AVAIL,
};
static int ltc2688_dac_code_write(struct ltc2688_state *st, u32 chan, u32 input,
u16 code)
{
struct ltc2688_chan *c = &st->channels[chan];
int ret, reg;
/* 2 LSBs set to 0 if writing dither amplitude */
if (!c->toggle_chan && input == LTC2688_INPUT_B) {
if (code > LTC2688_DITHER_RAW_MAX_VAL)
return -EINVAL;
code = FIELD_PREP(LTC2688_DITHER_RAW_MASK, code);
}
mutex_lock(&st->lock);
/* select the correct input register to read from */
ret = regmap_update_bits(st->regmap, LTC2688_CMD_A_B_SELECT, BIT(chan),
input << chan);
if (ret)
goto out_unlock;
/*
* If in dither/toggle mode the dac should be updated by an
* external signal (or sw toggle) and not here.
*/
if (c->mode == LTC2688_MODE_DEFAULT)
reg = LTC2688_CMD_CH_CODE_UPDATE(chan);
else
reg = LTC2688_CMD_CH_CODE(chan);
ret = regmap_write(st->regmap, reg, code);
out_unlock:
mutex_unlock(&st->lock);
return ret;
}
static int ltc2688_dac_code_read(struct ltc2688_state *st, u32 chan, u32 input,
u32 *code)
{
struct ltc2688_chan *c = &st->channels[chan];
int ret;
mutex_lock(&st->lock);
ret = regmap_update_bits(st->regmap, LTC2688_CMD_A_B_SELECT, BIT(chan),
input << chan);
if (ret)
goto out_unlock;
ret = regmap_read(st->regmap, LTC2688_CMD_CH_CODE(chan), code);
out_unlock:
mutex_unlock(&st->lock);
if (!c->toggle_chan && input == LTC2688_INPUT_B)
*code = FIELD_GET(LTC2688_DITHER_RAW_MASK, *code);
return ret;
}
static const int ltc2688_raw_range[] = {0, 1, U16_MAX};
static int ltc2688_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long info)
{
switch (info) {
case IIO_CHAN_INFO_RAW:
*vals = ltc2688_raw_range;
*type = IIO_VAL_INT;
return IIO_AVAIL_RANGE;
default:
return -EINVAL;
}
}
static int ltc2688_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long info)
{
struct ltc2688_state *st = iio_priv(indio_dev);
int ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
ret = ltc2688_dac_code_read(st, chan->channel, LTC2688_INPUT_A,
val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
ret = ltc2688_offset_get(st, chan->channel, val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = ltc2688_scale_get(st, chan->channel, val);
if (ret)
return ret;
*val2 = 16;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_CALIBBIAS:
ret = regmap_read(st->regmap,
LTC2688_CMD_CH_OFFSET(chan->channel), val);
if (ret)
return ret;
*val = FIELD_GET(LTC2688_CH_CALIBBIAS_MASK, *val);
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBSCALE:
ret = regmap_read(st->regmap,
LTC2688_CMD_CH_GAIN(chan->channel), val);
if (ret)
return ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int ltc2688_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long info)
{
struct ltc2688_state *st = iio_priv(indio_dev);
switch (info) {
case IIO_CHAN_INFO_RAW:
if (val > U16_MAX || val < 0)
return -EINVAL;
return ltc2688_dac_code_write(st, chan->channel,
LTC2688_INPUT_A, val);
case IIO_CHAN_INFO_CALIBBIAS:
if (val > LTC2688_CH_CALIBBIAS_MAX_VAL)
return -EINVAL;
return regmap_write(st->regmap,
LTC2688_CMD_CH_OFFSET(chan->channel),
FIELD_PREP(LTC2688_CH_CALIBBIAS_MASK, val));
case IIO_CHAN_INFO_CALIBSCALE:
return regmap_write(st->regmap,
LTC2688_CMD_CH_GAIN(chan->channel), val);
default:
return -EINVAL;
}
}
static ssize_t ltc2688_dither_toggle_set(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct ltc2688_state *st = iio_priv(indio_dev);
struct ltc2688_chan *c = &st->channels[chan->channel];
int ret;
bool en;
ret = kstrtobool(buf, &en);
if (ret)
return ret;
mutex_lock(&st->lock);
ret = regmap_update_bits(st->regmap, LTC2688_CMD_TOGGLE_DITHER_EN,
BIT(chan->channel), en << chan->channel);
if (ret)
goto out_unlock;
c->mode = en ? LTC2688_MODE_DITHER_TOGGLE : LTC2688_MODE_DEFAULT;
out_unlock:
mutex_unlock(&st->lock);
return ret ?: len;
}
static ssize_t ltc2688_reg_bool_get(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
const struct ltc2688_state *st = iio_priv(indio_dev);
int ret;
u32 val;
ret = regmap_read(st->regmap, private, &val);
if (ret)
return ret;
return sysfs_emit(buf, "%u\n", !!(val & BIT(chan->channel)));
}
static ssize_t ltc2688_reg_bool_set(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
const struct ltc2688_state *st = iio_priv(indio_dev);
int ret;
bool en;
ret = kstrtobool(buf, &en);
if (ret)
return ret;
ret = regmap_update_bits(st->regmap, private, BIT(chan->channel),
en << chan->channel);
if (ret)
return ret;
return len;
}
static ssize_t ltc2688_dither_freq_avail(const struct ltc2688_state *st,
const struct ltc2688_chan *chan,
char *buf)
{
int sz = 0;
u32 f;
for (f = 0; f < ARRAY_SIZE(chan->dither_frequency); f++)
sz += sysfs_emit_at(buf, sz, "%ld ", chan->dither_frequency[f]);
buf[sz - 1] = '\n';
return sz;
}
static ssize_t ltc2688_dither_freq_get(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
const struct ltc2688_state *st = iio_priv(indio_dev);
const struct ltc2688_chan *c = &st->channels[chan->channel];
u32 reg, freq;
int ret;
if (private == LTC2688_DITHER_FREQ_AVAIL)
return ltc2688_dither_freq_avail(st, c, buf);
ret = regmap_read(st->regmap, LTC2688_CMD_CH_SETTING(chan->channel),
®);
if (ret)
return ret;
freq = FIELD_GET(LTC2688_CH_DIT_PER_MSK, reg);
if (freq >= ARRAY_SIZE(c->dither_frequency))
return -EIO;
return sysfs_emit(buf, "%ld\n", c->dither_frequency[freq]);
}
static ssize_t ltc2688_dither_freq_set(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
const struct ltc2688_state *st = iio_priv(indio_dev);
const struct ltc2688_chan *c = &st->channels[chan->channel];
long val;
u32 freq;
int ret;
if (private == LTC2688_DITHER_FREQ_AVAIL)
return -EINVAL;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
for (freq = 0; freq < ARRAY_SIZE(c->dither_frequency); freq++) {
if (val == c->dither_frequency[freq])
break;
}
if (freq == ARRAY_SIZE(c->dither_frequency))
return -EINVAL;
ret = regmap_update_bits(st->regmap,
LTC2688_CMD_CH_SETTING(chan->channel),
LTC2688_CH_DIT_PER_MSK,
FIELD_PREP(LTC2688_CH_DIT_PER_MSK, freq));
if (ret)
return ret;
return len;
}
static ssize_t ltc2688_dac_input_read(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct ltc2688_state *st = iio_priv(indio_dev);
int ret;
u32 val;
if (private == LTC2688_INPUT_B_AVAIL)
return sysfs_emit(buf, "[%u %u %u]\n", ltc2688_raw_range[0],
ltc2688_raw_range[1],
ltc2688_raw_range[2] / 4);
if (private == LTC2688_DITHER_OFF)
return sysfs_emit(buf, "0\n");
ret = ltc2688_dac_code_read(st, chan->channel, private, &val);
if (ret)
return ret;
return sysfs_emit(buf, "%u\n", val);
}
static ssize_t ltc2688_dac_input_write(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct ltc2688_state *st = iio_priv(indio_dev);
int ret;
u16 val;
if (private == LTC2688_INPUT_B_AVAIL || private == LTC2688_DITHER_OFF)
return -EINVAL;
ret = kstrtou16(buf, 10, &val);
if (ret)
return ret;
ret = ltc2688_dac_code_write(st, chan->channel, private, val);
if (ret)
return ret;
return len;
}
static int ltc2688_get_dither_phase(struct iio_dev *dev,
const struct iio_chan_spec *chan)
{
struct ltc2688_state *st = iio_priv(dev);
int ret, regval;
ret = regmap_read(st->regmap, LTC2688_CMD_CH_SETTING(chan->channel),
®val);
if (ret)
return ret;
return FIELD_GET(LTC2688_CH_DIT_PH_MSK, regval);
}
static int ltc2688_set_dither_phase(struct iio_dev *dev,
const struct iio_chan_spec *chan,
unsigned int phase)
{
struct ltc2688_state *st = iio_priv(dev);
return regmap_update_bits(st->regmap,
LTC2688_CMD_CH_SETTING(chan->channel),
LTC2688_CH_DIT_PH_MSK,
FIELD_PREP(LTC2688_CH_DIT_PH_MSK, phase));
}
static int ltc2688_reg_access(struct iio_dev *indio_dev,
unsigned int reg,
unsigned int writeval,
unsigned int *readval)
{
struct ltc2688_state *st = iio_priv(indio_dev);
if (readval)
return regmap_read(st->regmap, reg, readval);
return regmap_write(st->regmap, reg, writeval);
}
static const char * const ltc2688_dither_phase[] = {
"0", "1.5708", "3.14159", "4.71239",
};
static const struct iio_enum ltc2688_dither_phase_enum = {
.items = ltc2688_dither_phase,
.num_items = ARRAY_SIZE(ltc2688_dither_phase),
.set = ltc2688_set_dither_phase,
.get = ltc2688_get_dither_phase,
};
#define LTC2688_CHAN_EXT_INFO(_name, _what, _shared, _read, _write) { \
.name = _name, \
.read = (_read), \
.write = (_write), \
.private = (_what), \
.shared = (_shared), \
}
/*
* For toggle mode we only expose the symbol attr (sw_toggle) in case a TGPx is
* not provided in dts.
*/
static const struct iio_chan_spec_ext_info ltc2688_toggle_sym_ext_info[] = {
LTC2688_CHAN_EXT_INFO("raw0", LTC2688_INPUT_A, IIO_SEPARATE,
ltc2688_dac_input_read, ltc2688_dac_input_write),
LTC2688_CHAN_EXT_INFO("raw1", LTC2688_INPUT_B, IIO_SEPARATE,
ltc2688_dac_input_read, ltc2688_dac_input_write),
LTC2688_CHAN_EXT_INFO("toggle_en", LTC2688_CMD_TOGGLE_DITHER_EN,
IIO_SEPARATE, ltc2688_reg_bool_get,
ltc2688_dither_toggle_set),
LTC2688_CHAN_EXT_INFO("powerdown", LTC2688_CMD_POWERDOWN, IIO_SEPARATE,
ltc2688_reg_bool_get, ltc2688_reg_bool_set),
LTC2688_CHAN_EXT_INFO("symbol", LTC2688_CMD_SW_TOGGLE, IIO_SEPARATE,
ltc2688_reg_bool_get, ltc2688_reg_bool_set),
{}
};
static const struct iio_chan_spec_ext_info ltc2688_toggle_ext_info[] = {
LTC2688_CHAN_EXT_INFO("raw0", LTC2688_INPUT_A, IIO_SEPARATE,
ltc2688_dac_input_read, ltc2688_dac_input_write),
LTC2688_CHAN_EXT_INFO("raw1", LTC2688_INPUT_B, IIO_SEPARATE,
ltc2688_dac_input_read, ltc2688_dac_input_write),
LTC2688_CHAN_EXT_INFO("toggle_en", LTC2688_CMD_TOGGLE_DITHER_EN,
IIO_SEPARATE, ltc2688_reg_bool_get,
ltc2688_dither_toggle_set),
LTC2688_CHAN_EXT_INFO("powerdown", LTC2688_CMD_POWERDOWN, IIO_SEPARATE,
ltc2688_reg_bool_get, ltc2688_reg_bool_set),
{}
};
static struct iio_chan_spec_ext_info ltc2688_dither_ext_info[] = {
LTC2688_CHAN_EXT_INFO("dither_raw", LTC2688_INPUT_B, IIO_SEPARATE,
ltc2688_dac_input_read, ltc2688_dac_input_write),
LTC2688_CHAN_EXT_INFO("dither_raw_available", LTC2688_INPUT_B_AVAIL,
IIO_SEPARATE, ltc2688_dac_input_read,
ltc2688_dac_input_write),
LTC2688_CHAN_EXT_INFO("dither_offset", LTC2688_DITHER_OFF, IIO_SEPARATE,
ltc2688_dac_input_read, ltc2688_dac_input_write),
/*
* Not IIO_ENUM because the available freq needs to be computed at
* probe. We could still use it, but it didn't felt much right.
*/
LTC2688_CHAN_EXT_INFO("dither_frequency", 0, IIO_SEPARATE,
ltc2688_dither_freq_get, ltc2688_dither_freq_set),
LTC2688_CHAN_EXT_INFO("dither_frequency_available",
LTC2688_DITHER_FREQ_AVAIL, IIO_SEPARATE,
ltc2688_dither_freq_get, ltc2688_dither_freq_set),
IIO_ENUM("dither_phase", IIO_SEPARATE, <c2688_dither_phase_enum),
IIO_ENUM_AVAILABLE("dither_phase", IIO_SEPARATE,
<c2688_dither_phase_enum),
LTC2688_CHAN_EXT_INFO("dither_en", LTC2688_CMD_TOGGLE_DITHER_EN,
IIO_SEPARATE, ltc2688_reg_bool_get,
ltc2688_dither_toggle_set),
LTC2688_CHAN_EXT_INFO("powerdown", LTC2688_CMD_POWERDOWN, IIO_SEPARATE,
ltc2688_reg_bool_get, ltc2688_reg_bool_set),
{}
};
static const struct iio_chan_spec_ext_info ltc2688_ext_info[] = {
LTC2688_CHAN_EXT_INFO("powerdown", LTC2688_CMD_POWERDOWN, IIO_SEPARATE,
ltc2688_reg_bool_get, ltc2688_reg_bool_set),
{}
};
#define LTC2688_CHANNEL(_chan) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (_chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_RAW), \
.info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW), \
.ext_info = ltc2688_ext_info, \
}
static const struct iio_chan_spec ltc2688_channels[] = {
LTC2688_CHANNEL(0),
LTC2688_CHANNEL(1),
LTC2688_CHANNEL(2),
LTC2688_CHANNEL(3),
LTC2688_CHANNEL(4),
LTC2688_CHANNEL(5),
LTC2688_CHANNEL(6),
LTC2688_CHANNEL(7),
LTC2688_CHANNEL(8),
LTC2688_CHANNEL(9),
LTC2688_CHANNEL(10),
LTC2688_CHANNEL(11),
LTC2688_CHANNEL(12),
LTC2688_CHANNEL(13),
LTC2688_CHANNEL(14),
LTC2688_CHANNEL(15),
};
static void ltc2688_clk_disable(void *clk)
{
clk_disable_unprepare(clk);
}
static const int ltc2688_period[LTC2688_DITHER_FREQ_AVAIL_N] = {
4, 8, 16, 32, 64,
};
static int ltc2688_tgp_clk_setup(struct ltc2688_state *st,
struct ltc2688_chan *chan,
struct fwnode_handle *node, int tgp)
{
struct device *dev = &st->spi->dev;
unsigned long rate;
struct clk *clk;
int ret, f;
clk = devm_get_clk_from_child(dev, to_of_node(node), NULL);
if (IS_ERR(clk))
return dev_err_probe(dev, PTR_ERR(clk), "failed to get tgp clk.\n");
ret = clk_prepare_enable(clk);
if (ret)
return dev_err_probe(dev, ret, "failed to enable tgp clk.\n");
ret = devm_add_action_or_reset(dev, ltc2688_clk_disable, clk);
if (ret)
return ret;
if (chan->toggle_chan)
return 0;
/* calculate available dither frequencies */
rate = clk_get_rate(clk);
for (f = 0; f < ARRAY_SIZE(chan->dither_frequency); f++)
chan->dither_frequency[f] = DIV_ROUND_CLOSEST(rate, ltc2688_period[f]);
return 0;
}
static int ltc2688_span_lookup(const struct ltc2688_state *st, int min, int max)
{
u32 span;
for (span = 0; span < ARRAY_SIZE(ltc2688_span_helper); span++) {
if (min == ltc2688_span_helper[span][0] &&
max == ltc2688_span_helper[span][1])
return span;
}
return -EINVAL;
}
static int ltc2688_channel_config(struct ltc2688_state *st)
{
struct device *dev = &st->spi->dev;
struct fwnode_handle *child;
u32 reg, clk_input, val, tmp[2];
int ret, span;
device_for_each_child_node(dev, child) {
struct ltc2688_chan *chan;
ret = fwnode_property_read_u32(child, "reg", ®);
if (ret) {
fwnode_handle_put(child);
return dev_err_probe(dev, ret,
"Failed to get reg property\n");
}
if (reg >= LTC2688_DAC_CHANNELS) {
fwnode_handle_put(child);
return dev_err_probe(dev, -EINVAL,
"reg bigger than: %d\n",
LTC2688_DAC_CHANNELS);
}
val = 0;
chan = &st->channels[reg];
if (fwnode_property_read_bool(child, "adi,toggle-mode")) {
chan->toggle_chan = true;
/* assume sw toggle ABI */
st->iio_chan[reg].ext_info = ltc2688_toggle_sym_ext_info;
/*
* Clear IIO_CHAN_INFO_RAW bit as toggle channels expose
* out_voltage_raw{0|1} files.
*/
__clear_bit(IIO_CHAN_INFO_RAW,
&st->iio_chan[reg].info_mask_separate);
}
ret = fwnode_property_read_u32_array(child, "adi,output-range-microvolt",
tmp, ARRAY_SIZE(tmp));
if (!ret) {
span = ltc2688_span_lookup(st, (int)tmp[0] / 1000,
tmp[1] / 1000);
if (span < 0) {
fwnode_handle_put(child);
return dev_err_probe(dev, -EINVAL,
"output range not valid:[%d %d]\n",
tmp[0], tmp[1]);
}
val |= FIELD_PREP(LTC2688_CH_SPAN_MSK, span);
}
ret = fwnode_property_read_u32(child, "adi,toggle-dither-input",
&clk_input);
if (!ret) {
if (clk_input >= LTC2688_CH_TGP_MAX) {
fwnode_handle_put(child);
return dev_err_probe(dev, -EINVAL,
"toggle-dither-input inv value(%d)\n",
clk_input);
}
ret = ltc2688_tgp_clk_setup(st, chan, child, clk_input);
if (ret) {
fwnode_handle_put(child);
return ret;
}
/*
* 0 means software toggle which is the default mode.
* Hence the +1.
*/
val |= FIELD_PREP(LTC2688_CH_TD_SEL_MSK, clk_input + 1);
/*
* If a TGPx is given, we automatically assume a dither
* capable channel (unless toggle is already enabled).
* On top of this we just set here the dither bit in the
* channel settings. It won't have any effect until the
* global toggle/dither bit is enabled.
*/
if (!chan->toggle_chan) {
val |= FIELD_PREP(LTC2688_CH_MODE_MSK, 1);
st->iio_chan[reg].ext_info = ltc2688_dither_ext_info;
} else {
/* wait, no sw toggle after all */
st->iio_chan[reg].ext_info = ltc2688_toggle_ext_info;
}
}
if (fwnode_property_read_bool(child, "adi,overrange")) {
chan->overrange = true;
val |= LTC2688_CH_OVERRANGE_MSK;
}
if (!val)
continue;
ret = regmap_write(st->regmap, LTC2688_CMD_CH_SETTING(reg),
val);
if (ret) {
fwnode_handle_put(child);
return dev_err_probe(dev, -EINVAL,
"failed to set chan settings\n");
}
}
return 0;
}
static int ltc2688_setup(struct ltc2688_state *st, struct regulator *vref)
{
struct device *dev = &st->spi->dev;
struct gpio_desc *gpio;
int ret;
/*
* If we have a reset pin, use that to reset the board, If not, use
* the reset bit.
*/
gpio = devm_gpiod_get_optional(dev, "clr", GPIOD_OUT_HIGH);
if (IS_ERR(gpio))
return dev_err_probe(dev, PTR_ERR(gpio), "Failed to get reset gpio");
if (gpio) {
usleep_range(1000, 1200);
/* bring device out of reset */
gpiod_set_value_cansleep(gpio, 0);
} else {
ret = regmap_update_bits(st->regmap, LTC2688_CMD_CONFIG,
LTC2688_CONFIG_RST,
LTC2688_CONFIG_RST);
if (ret)
return ret;
}
usleep_range(10000, 12000);
/*
* Duplicate the default channel configuration as it can change during
* @ltc2688_channel_config()
*/
st->iio_chan = devm_kmemdup(dev, ltc2688_channels,
sizeof(ltc2688_channels), GFP_KERNEL);
if (!st->iio_chan)
return -ENOMEM;
ret = ltc2688_channel_config(st);
if (ret)
return ret;
if (!vref)
return 0;
return regmap_set_bits(st->regmap, LTC2688_CMD_CONFIG,
LTC2688_CONFIG_EXT_REF);
}
static void ltc2688_disable_regulator(void *regulator)
{
regulator_disable(regulator);
}
static bool ltc2688_reg_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case LTC2688_CMD_CH_CODE(0) ... LTC2688_CMD_CH_GAIN(15):
return true;
case LTC2688_CMD_CONFIG ... LTC2688_CMD_THERMAL_STAT:
return true;
default:
return false;
}
}
static bool ltc2688_reg_writable(struct device *dev, unsigned int reg)
{
/*
* There's a jump from 0x76 to 0x78 in the write codes and the thermal
* status code is 0x77 (which is read only) so that we need to check
* that special condition.
*/
if (reg <= LTC2688_CMD_UPDATE_ALL && reg != LTC2688_CMD_THERMAL_STAT)
return true;
return false;
}
static struct regmap_bus ltc2688_regmap_bus = {
.read = ltc2688_spi_read,
.write = ltc2688_spi_write,
.read_flag_mask = LTC2688_READ_OPERATION,
.reg_format_endian_default = REGMAP_ENDIAN_BIG,
.val_format_endian_default = REGMAP_ENDIAN_BIG,
};
static const struct regmap_config ltc2688_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.readable_reg = ltc2688_reg_readable,
.writeable_reg = ltc2688_reg_writable,
/* ignoring the no op command */
.max_register = LTC2688_CMD_UPDATE_ALL,
};
static const struct iio_info ltc2688_info = {
.write_raw = ltc2688_write_raw,
.read_raw = ltc2688_read_raw,
.read_avail = ltc2688_read_avail,
.debugfs_reg_access = ltc2688_reg_access,
};
static int ltc2688_probe(struct spi_device *spi)
{
static const char * const regulators[] = { "vcc", "iovcc" };
struct ltc2688_state *st;
struct iio_dev *indio_dev;
struct regulator *vref_reg;
struct device *dev = &spi->dev;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->spi = spi;
/* Just write this once. No need to do it in every regmap read. */
st->tx_data[3] = LTC2688_CMD_NOOP;
mutex_init(&st->lock);
st->regmap = devm_regmap_init(dev, <c2688_regmap_bus, st,
<c2688_regmap_config);
if (IS_ERR(st->regmap))
return dev_err_probe(dev, PTR_ERR(st->regmap),
"Failed to init regmap");
ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators),
regulators);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable regulators\n");
vref_reg = devm_regulator_get_optional(dev, "vref");
if (IS_ERR(vref_reg)) {
if (PTR_ERR(vref_reg) != -ENODEV)
return dev_err_probe(dev, PTR_ERR(vref_reg),
"Failed to get vref regulator");
vref_reg = NULL;
/* internal reference */
st->vref = 4096;
} else {
ret = regulator_enable(vref_reg);
if (ret)
return dev_err_probe(dev, ret,
"Failed to enable vref regulators\n");
ret = devm_add_action_or_reset(dev, ltc2688_disable_regulator,
vref_reg);
if (ret)
return ret;
ret = regulator_get_voltage(vref_reg);
if (ret < 0)
return dev_err_probe(dev, ret, "Failed to get vref\n");
st->vref = ret / 1000;
}
ret = ltc2688_setup(st, vref_reg);
if (ret)
return ret;
indio_dev->name = "ltc2688";
indio_dev->info = <c2688_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = st->iio_chan;
indio_dev->num_channels = ARRAY_SIZE(ltc2688_channels);
return devm_iio_device_register(dev, indio_dev);
}
static const struct of_device_id ltc2688_of_id[] = {
{ .compatible = "adi,ltc2688" },
{}
};
MODULE_DEVICE_TABLE(of, ltc2688_of_id);
static const struct spi_device_id ltc2688_id[] = {
{ "ltc2688" },
{}
};
MODULE_DEVICE_TABLE(spi, ltc2688_id);
static struct spi_driver ltc2688_driver = {
.driver = {
.name = "ltc2688",
.of_match_table = ltc2688_of_id,
},
.probe = ltc2688_probe,
.id_table = ltc2688_id,
};
module_spi_driver(ltc2688_driver);
MODULE_AUTHOR("Nuno Sá <[email protected]>");
MODULE_DESCRIPTION("Analog Devices LTC2688 DAC");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/dac/ltc2688.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD7303 Digital to analog converters driver
*
* Copyright 2013 Analog Devices Inc.
*/
#include <linux/err.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define AD7303_CFG_EXTERNAL_VREF BIT(15)
#define AD7303_CFG_POWER_DOWN(ch) BIT(11 + (ch))
#define AD7303_CFG_ADDR_OFFSET 10
#define AD7303_CMD_UPDATE_DAC (0x3 << 8)
/**
* struct ad7303_state - driver instance specific data
* @spi: the device for this driver instance
* @config: cached config register value
* @dac_cache: current DAC raw value (chip does not support readback)
* @vdd_reg: reference to VDD regulator
* @vref_reg: reference to VREF regulator
* @lock: protect writes and cache updates
* @data: spi transfer buffer
*/
struct ad7303_state {
struct spi_device *spi;
uint16_t config;
uint8_t dac_cache[2];
struct regulator *vdd_reg;
struct regulator *vref_reg;
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
__be16 data __aligned(IIO_DMA_MINALIGN);
};
static int ad7303_write(struct ad7303_state *st, unsigned int chan,
uint8_t val)
{
st->data = cpu_to_be16(AD7303_CMD_UPDATE_DAC |
(chan << AD7303_CFG_ADDR_OFFSET) |
st->config | val);
return spi_write(st->spi, &st->data, sizeof(st->data));
}
static ssize_t ad7303_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
struct ad7303_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", (bool)(st->config &
AD7303_CFG_POWER_DOWN(chan->channel)));
}
static ssize_t ad7303_write_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
size_t len)
{
struct ad7303_state *st = iio_priv(indio_dev);
bool pwr_down;
int ret;
ret = kstrtobool(buf, &pwr_down);
if (ret)
return ret;
mutex_lock(&st->lock);
if (pwr_down)
st->config |= AD7303_CFG_POWER_DOWN(chan->channel);
else
st->config &= ~AD7303_CFG_POWER_DOWN(chan->channel);
/* There is no noop cmd which allows us to only update the powerdown
* mode, so just write one of the DAC channels again */
ad7303_write(st, chan->channel, st->dac_cache[chan->channel]);
mutex_unlock(&st->lock);
return len;
}
static int ad7303_get_vref(struct ad7303_state *st,
struct iio_chan_spec const *chan)
{
int ret;
if (st->config & AD7303_CFG_EXTERNAL_VREF)
return regulator_get_voltage(st->vref_reg);
ret = regulator_get_voltage(st->vdd_reg);
if (ret < 0)
return ret;
return ret / 2;
}
static int ad7303_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long info)
{
struct ad7303_state *st = iio_priv(indio_dev);
int vref_uv;
switch (info) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&st->lock);
*val = st->dac_cache[chan->channel];
mutex_unlock(&st->lock);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
vref_uv = ad7303_get_vref(st, chan);
if (vref_uv < 0)
return vref_uv;
*val = 2 * vref_uv / 1000;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
default:
break;
}
return -EINVAL;
}
static int ad7303_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long mask)
{
struct ad7303_state *st = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val >= (1 << chan->scan_type.realbits) || val < 0)
return -EINVAL;
mutex_lock(&st->lock);
ret = ad7303_write(st, chan->address, val);
if (ret == 0)
st->dac_cache[chan->channel] = val;
mutex_unlock(&st->lock);
break;
default:
ret = -EINVAL;
}
return ret;
}
static const struct iio_info ad7303_info = {
.read_raw = ad7303_read_raw,
.write_raw = ad7303_write_raw,
};
static const struct iio_chan_spec_ext_info ad7303_ext_info[] = {
{
.name = "powerdown",
.read = ad7303_read_dac_powerdown,
.write = ad7303_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
{ },
};
#define AD7303_CHANNEL(chan) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.address = (chan), \
.scan_type = { \
.sign = 'u', \
.realbits = 8, \
.storagebits = 8, \
.shift = 0, \
}, \
.ext_info = ad7303_ext_info, \
}
static const struct iio_chan_spec ad7303_channels[] = {
AD7303_CHANNEL(0),
AD7303_CHANNEL(1),
};
static void ad7303_reg_disable(void *reg)
{
regulator_disable(reg);
}
static int ad7303_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct iio_dev *indio_dev;
struct ad7303_state *st;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (indio_dev == NULL)
return -ENOMEM;
st = iio_priv(indio_dev);
st->spi = spi;
mutex_init(&st->lock);
st->vdd_reg = devm_regulator_get(&spi->dev, "Vdd");
if (IS_ERR(st->vdd_reg))
return PTR_ERR(st->vdd_reg);
ret = regulator_enable(st->vdd_reg);
if (ret)
return ret;
ret = devm_add_action_or_reset(&spi->dev, ad7303_reg_disable, st->vdd_reg);
if (ret)
return ret;
st->vref_reg = devm_regulator_get_optional(&spi->dev, "REF");
if (IS_ERR(st->vref_reg)) {
ret = PTR_ERR(st->vref_reg);
if (ret != -ENODEV)
return ret;
st->vref_reg = NULL;
}
if (st->vref_reg) {
ret = regulator_enable(st->vref_reg);
if (ret)
return ret;
ret = devm_add_action_or_reset(&spi->dev, ad7303_reg_disable,
st->vref_reg);
if (ret)
return ret;
st->config |= AD7303_CFG_EXTERNAL_VREF;
}
indio_dev->name = id->name;
indio_dev->info = &ad7303_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ad7303_channels;
indio_dev->num_channels = ARRAY_SIZE(ad7303_channels);
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct of_device_id ad7303_spi_of_match[] = {
{ .compatible = "adi,ad7303", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, ad7303_spi_of_match);
static const struct spi_device_id ad7303_spi_ids[] = {
{ "ad7303", 0 },
{}
};
MODULE_DEVICE_TABLE(spi, ad7303_spi_ids);
static struct spi_driver ad7303_driver = {
.driver = {
.name = "ad7303",
.of_match_table = ad7303_spi_of_match,
},
.probe = ad7303_probe,
.id_table = ad7303_spi_ids,
};
module_spi_driver(ad7303_driver);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD7303 DAC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad7303.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD5624R, AD5644R, AD5664R Digital to analog convertors spi driver
*
* Copyright 2010-2011 Analog Devices Inc.
*/
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <asm/unaligned.h>
#include "ad5624r.h"
static int ad5624r_spi_write(struct spi_device *spi,
u8 cmd, u8 addr, u16 val, u8 shift)
{
u32 data;
u8 msg[3];
/*
* The input shift register is 24 bits wide. The first two bits are
* don't care bits. The next three are the command bits, C2 to C0,
* followed by the 3-bit DAC address, A2 to A0, and then the
* 16-, 14-, 12-bit data-word. The data-word comprises the 16-,
* 14-, 12-bit input code followed by 0, 2, or 4 don't care bits,
* for the AD5664R, AD5644R, and AD5624R, respectively.
*/
data = (0 << 22) | (cmd << 19) | (addr << 16) | (val << shift);
put_unaligned_be24(data, &msg[0]);
return spi_write(spi, msg, sizeof(msg));
}
static int ad5624r_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct ad5624r_state *st = iio_priv(indio_dev);
switch (m) {
case IIO_CHAN_INFO_SCALE:
*val = st->vref_mv;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
static int ad5624r_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct ad5624r_state *st = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val >= (1 << chan->scan_type.realbits) || val < 0)
return -EINVAL;
return ad5624r_spi_write(st->us,
AD5624R_CMD_WRITE_INPUT_N_UPDATE_N,
chan->address, val,
chan->scan_type.shift);
default:
return -EINVAL;
}
}
static const char * const ad5624r_powerdown_modes[] = {
"1kohm_to_gnd",
"100kohm_to_gnd",
"three_state"
};
static int ad5624r_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct ad5624r_state *st = iio_priv(indio_dev);
return st->pwr_down_mode;
}
static int ad5624r_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, unsigned int mode)
{
struct ad5624r_state *st = iio_priv(indio_dev);
st->pwr_down_mode = mode;
return 0;
}
static const struct iio_enum ad5624r_powerdown_mode_enum = {
.items = ad5624r_powerdown_modes,
.num_items = ARRAY_SIZE(ad5624r_powerdown_modes),
.get = ad5624r_get_powerdown_mode,
.set = ad5624r_set_powerdown_mode,
};
static ssize_t ad5624r_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
struct ad5624r_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n",
!!(st->pwr_down_mask & (1 << chan->channel)));
}
static ssize_t ad5624r_write_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
size_t len)
{
bool pwr_down;
int ret;
struct ad5624r_state *st = iio_priv(indio_dev);
ret = kstrtobool(buf, &pwr_down);
if (ret)
return ret;
if (pwr_down)
st->pwr_down_mask |= (1 << chan->channel);
else
st->pwr_down_mask &= ~(1 << chan->channel);
ret = ad5624r_spi_write(st->us, AD5624R_CMD_POWERDOWN_DAC, 0,
(st->pwr_down_mode << 4) |
st->pwr_down_mask, 16);
return ret ? ret : len;
}
static const struct iio_info ad5624r_info = {
.write_raw = ad5624r_write_raw,
.read_raw = ad5624r_read_raw,
};
static const struct iio_chan_spec_ext_info ad5624r_ext_info[] = {
{
.name = "powerdown",
.read = ad5624r_read_dac_powerdown,
.write = ad5624r_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE,
&ad5624r_powerdown_mode_enum),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5624r_powerdown_mode_enum),
{ },
};
#define AD5624R_CHANNEL(_chan, _bits) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (_chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.address = (_chan), \
.scan_type = { \
.sign = 'u', \
.realbits = (_bits), \
.storagebits = 16, \
.shift = 16 - (_bits), \
}, \
.ext_info = ad5624r_ext_info, \
}
#define DECLARE_AD5624R_CHANNELS(_name, _bits) \
const struct iio_chan_spec _name##_channels[] = { \
AD5624R_CHANNEL(0, _bits), \
AD5624R_CHANNEL(1, _bits), \
AD5624R_CHANNEL(2, _bits), \
AD5624R_CHANNEL(3, _bits), \
}
static DECLARE_AD5624R_CHANNELS(ad5624r, 12);
static DECLARE_AD5624R_CHANNELS(ad5644r, 14);
static DECLARE_AD5624R_CHANNELS(ad5664r, 16);
static const struct ad5624r_chip_info ad5624r_chip_info_tbl[] = {
[ID_AD5624R3] = {
.channels = ad5624r_channels,
.int_vref_mv = 1250,
},
[ID_AD5624R5] = {
.channels = ad5624r_channels,
.int_vref_mv = 2500,
},
[ID_AD5644R3] = {
.channels = ad5644r_channels,
.int_vref_mv = 1250,
},
[ID_AD5644R5] = {
.channels = ad5644r_channels,
.int_vref_mv = 2500,
},
[ID_AD5664R3] = {
.channels = ad5664r_channels,
.int_vref_mv = 1250,
},
[ID_AD5664R5] = {
.channels = ad5664r_channels,
.int_vref_mv = 2500,
},
};
static int ad5624r_probe(struct spi_device *spi)
{
struct ad5624r_state *st;
struct iio_dev *indio_dev;
int ret, voltage_uv = 0;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->reg = devm_regulator_get_optional(&spi->dev, "vref");
if (!IS_ERR(st->reg)) {
ret = regulator_enable(st->reg);
if (ret)
return ret;
ret = regulator_get_voltage(st->reg);
if (ret < 0)
goto error_disable_reg;
voltage_uv = ret;
} else {
if (PTR_ERR(st->reg) != -ENODEV)
return PTR_ERR(st->reg);
/* Backwards compatibility. This naming is not correct */
st->reg = devm_regulator_get_optional(&spi->dev, "vcc");
if (!IS_ERR(st->reg)) {
ret = regulator_enable(st->reg);
if (ret)
return ret;
ret = regulator_get_voltage(st->reg);
if (ret < 0)
goto error_disable_reg;
voltage_uv = ret;
}
}
spi_set_drvdata(spi, indio_dev);
st->chip_info =
&ad5624r_chip_info_tbl[spi_get_device_id(spi)->driver_data];
if (voltage_uv)
st->vref_mv = voltage_uv / 1000;
else
st->vref_mv = st->chip_info->int_vref_mv;
st->us = spi;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->info = &ad5624r_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = st->chip_info->channels;
indio_dev->num_channels = AD5624R_DAC_CHANNELS;
ret = ad5624r_spi_write(spi, AD5624R_CMD_INTERNAL_REFER_SETUP, 0,
!!voltage_uv, 16);
if (ret)
goto error_disable_reg;
ret = iio_device_register(indio_dev);
if (ret)
goto error_disable_reg;
return 0;
error_disable_reg:
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
return ret;
}
static void ad5624r_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ad5624r_state *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
}
static const struct spi_device_id ad5624r_id[] = {
{"ad5624r3", ID_AD5624R3},
{"ad5644r3", ID_AD5644R3},
{"ad5664r3", ID_AD5664R3},
{"ad5624r5", ID_AD5624R5},
{"ad5644r5", ID_AD5644R5},
{"ad5664r5", ID_AD5664R5},
{}
};
MODULE_DEVICE_TABLE(spi, ad5624r_id);
static struct spi_driver ad5624r_driver = {
.driver = {
.name = "ad5624r",
},
.probe = ad5624r_probe,
.remove = ad5624r_remove,
.id_table = ad5624r_id,
};
module_spi_driver(ad5624r_driver);
MODULE_AUTHOR("Barry Song <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5624/44/64R DAC spi driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5624r_spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* mcp4725.c - Support for Microchip MCP4725/6
*
* Copyright (C) 2012 Peter Meerwald <[email protected]>
*
* Based on max517 by Roland Stigge <[email protected]>
*
* driver for the Microchip I2C 12-bit digital-to-analog converter (DAC)
* (7-bit I2C slave address 0x60, the three LSBs can be configured in
* hardware)
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/regulator/consumer.h>
#include <linux/mod_devicetable.h>
#include <linux/property.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/dac/mcp4725.h>
#define MCP4725_DRV_NAME "mcp4725"
#define MCP472X_REF_VDD 0x00
#define MCP472X_REF_VREF_UNBUFFERED 0x02
#define MCP472X_REF_VREF_BUFFERED 0x03
struct mcp4725_data {
struct i2c_client *client;
int id;
unsigned ref_mode;
bool vref_buffered;
u16 dac_value;
bool powerdown;
unsigned powerdown_mode;
struct regulator *vdd_reg;
struct regulator *vref_reg;
};
static int mcp4725_suspend(struct device *dev)
{
struct mcp4725_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
u8 outbuf[2];
int ret;
outbuf[0] = (data->powerdown_mode + 1) << 4;
outbuf[1] = 0;
data->powerdown = true;
ret = i2c_master_send(data->client, outbuf, 2);
if (ret < 0)
return ret;
else if (ret != 2)
return -EIO;
return 0;
}
static int mcp4725_resume(struct device *dev)
{
struct mcp4725_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
u8 outbuf[2];
int ret;
/* restore previous DAC value */
outbuf[0] = (data->dac_value >> 8) & 0xf;
outbuf[1] = data->dac_value & 0xff;
data->powerdown = false;
ret = i2c_master_send(data->client, outbuf, 2);
if (ret < 0)
return ret;
else if (ret != 2)
return -EIO;
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(mcp4725_pm_ops, mcp4725_suspend,
mcp4725_resume);
static ssize_t mcp4725_store_eeprom(struct device *dev,
struct device_attribute *attr, const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct mcp4725_data *data = iio_priv(indio_dev);
int tries = 20;
u8 inoutbuf[3];
bool state;
int ret;
ret = kstrtobool(buf, &state);
if (ret < 0)
return ret;
if (!state)
return 0;
inoutbuf[0] = 0x60; /* write EEPROM */
inoutbuf[0] |= data->ref_mode << 3;
inoutbuf[0] |= data->powerdown ? ((data->powerdown_mode + 1) << 1) : 0;
inoutbuf[1] = data->dac_value >> 4;
inoutbuf[2] = (data->dac_value & 0xf) << 4;
ret = i2c_master_send(data->client, inoutbuf, 3);
if (ret < 0)
return ret;
else if (ret != 3)
return -EIO;
/* wait for write complete, takes up to 50ms */
while (tries--) {
msleep(20);
ret = i2c_master_recv(data->client, inoutbuf, 3);
if (ret < 0)
return ret;
else if (ret != 3)
return -EIO;
if (inoutbuf[0] & 0x80)
break;
}
if (tries < 0) {
dev_err(&data->client->dev,
"mcp4725_store_eeprom() failed, incomplete\n");
return -EIO;
}
return len;
}
static IIO_DEVICE_ATTR(store_eeprom, S_IWUSR, NULL, mcp4725_store_eeprom, 0);
static struct attribute *mcp4725_attributes[] = {
&iio_dev_attr_store_eeprom.dev_attr.attr,
NULL,
};
static const struct attribute_group mcp4725_attribute_group = {
.attrs = mcp4725_attributes,
};
static const char * const mcp4725_powerdown_modes[] = {
"1kohm_to_gnd",
"100kohm_to_gnd",
"500kohm_to_gnd"
};
static const char * const mcp4726_powerdown_modes[] = {
"1kohm_to_gnd",
"125kohm_to_gnd",
"640kohm_to_gnd"
};
static int mcp4725_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct mcp4725_data *data = iio_priv(indio_dev);
return data->powerdown_mode;
}
static int mcp4725_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, unsigned mode)
{
struct mcp4725_data *data = iio_priv(indio_dev);
data->powerdown_mode = mode;
return 0;
}
static ssize_t mcp4725_read_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
struct mcp4725_data *data = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", data->powerdown);
}
static ssize_t mcp4725_write_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct mcp4725_data *data = iio_priv(indio_dev);
bool state;
int ret;
ret = kstrtobool(buf, &state);
if (ret)
return ret;
if (state)
ret = mcp4725_suspend(&data->client->dev);
else
ret = mcp4725_resume(&data->client->dev);
if (ret < 0)
return ret;
return len;
}
enum chip_id {
MCP4725,
MCP4726,
};
static const struct iio_enum mcp472x_powerdown_mode_enum[] = {
[MCP4725] = {
.items = mcp4725_powerdown_modes,
.num_items = ARRAY_SIZE(mcp4725_powerdown_modes),
.get = mcp4725_get_powerdown_mode,
.set = mcp4725_set_powerdown_mode,
},
[MCP4726] = {
.items = mcp4726_powerdown_modes,
.num_items = ARRAY_SIZE(mcp4726_powerdown_modes),
.get = mcp4725_get_powerdown_mode,
.set = mcp4725_set_powerdown_mode,
},
};
static const struct iio_chan_spec_ext_info mcp4725_ext_info[] = {
{
.name = "powerdown",
.read = mcp4725_read_powerdown,
.write = mcp4725_write_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SEPARATE,
&mcp472x_powerdown_mode_enum[MCP4725]),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE,
&mcp472x_powerdown_mode_enum[MCP4725]),
{ },
};
static const struct iio_chan_spec_ext_info mcp4726_ext_info[] = {
{
.name = "powerdown",
.read = mcp4725_read_powerdown,
.write = mcp4725_write_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SEPARATE,
&mcp472x_powerdown_mode_enum[MCP4726]),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE,
&mcp472x_powerdown_mode_enum[MCP4726]),
{ },
};
static const struct iio_chan_spec mcp472x_channel[] = {
[MCP4725] = {
.type = IIO_VOLTAGE,
.indexed = 1,
.output = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
.ext_info = mcp4725_ext_info,
},
[MCP4726] = {
.type = IIO_VOLTAGE,
.indexed = 1,
.output = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
.ext_info = mcp4726_ext_info,
},
};
static int mcp4725_set_value(struct iio_dev *indio_dev, int val)
{
struct mcp4725_data *data = iio_priv(indio_dev);
u8 outbuf[2];
int ret;
if (val >= (1 << 12) || val < 0)
return -EINVAL;
outbuf[0] = (val >> 8) & 0xf;
outbuf[1] = val & 0xff;
ret = i2c_master_send(data->client, outbuf, 2);
if (ret < 0)
return ret;
else if (ret != 2)
return -EIO;
else
return 0;
}
static int mcp4726_set_cfg(struct iio_dev *indio_dev)
{
struct mcp4725_data *data = iio_priv(indio_dev);
u8 outbuf[3];
int ret;
outbuf[0] = 0x40;
outbuf[0] |= data->ref_mode << 3;
if (data->powerdown)
outbuf[0] |= data->powerdown << 1;
outbuf[1] = data->dac_value >> 4;
outbuf[2] = (data->dac_value & 0xf) << 4;
ret = i2c_master_send(data->client, outbuf, 3);
if (ret < 0)
return ret;
else if (ret != 3)
return -EIO;
else
return 0;
}
static int mcp4725_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct mcp4725_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
*val = data->dac_value;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
if (data->ref_mode == MCP472X_REF_VDD)
ret = regulator_get_voltage(data->vdd_reg);
else
ret = regulator_get_voltage(data->vref_reg);
if (ret < 0)
return ret;
*val = ret / 1000;
*val2 = 12;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
static int mcp4725_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct mcp4725_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = mcp4725_set_value(indio_dev, val);
data->dac_value = val;
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static const struct iio_info mcp4725_info = {
.read_raw = mcp4725_read_raw,
.write_raw = mcp4725_write_raw,
.attrs = &mcp4725_attribute_group,
};
static int mcp4725_probe_dt(struct device *dev,
struct mcp4725_platform_data *pdata)
{
/* check if is the vref-supply defined */
pdata->use_vref = device_property_read_bool(dev, "vref-supply");
pdata->vref_buffered =
device_property_read_bool(dev, "microchip,vref-buffered");
return 0;
}
static int mcp4725_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct mcp4725_data *data;
struct iio_dev *indio_dev;
struct mcp4725_platform_data *pdata, pdata_dt;
u8 inbuf[4];
u8 pd;
u8 ref;
int err;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (indio_dev == NULL)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
if (dev_fwnode(&client->dev))
data->id = (uintptr_t)device_get_match_data(&client->dev);
else
data->id = id->driver_data;
pdata = dev_get_platdata(&client->dev);
if (!pdata) {
err = mcp4725_probe_dt(&client->dev, &pdata_dt);
if (err) {
dev_err(&client->dev,
"invalid platform or devicetree data");
return err;
}
pdata = &pdata_dt;
}
if (data->id == MCP4725 && pdata->use_vref) {
dev_err(&client->dev,
"external reference is unavailable on MCP4725");
return -EINVAL;
}
if (!pdata->use_vref && pdata->vref_buffered) {
dev_err(&client->dev,
"buffering is unavailable on the internal reference");
return -EINVAL;
}
if (!pdata->use_vref)
data->ref_mode = MCP472X_REF_VDD;
else
data->ref_mode = pdata->vref_buffered ?
MCP472X_REF_VREF_BUFFERED :
MCP472X_REF_VREF_UNBUFFERED;
data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
if (IS_ERR(data->vdd_reg))
return PTR_ERR(data->vdd_reg);
err = regulator_enable(data->vdd_reg);
if (err)
return err;
if (pdata->use_vref) {
data->vref_reg = devm_regulator_get(&client->dev, "vref");
if (IS_ERR(data->vref_reg)) {
err = PTR_ERR(data->vref_reg);
goto err_disable_vdd_reg;
}
err = regulator_enable(data->vref_reg);
if (err)
goto err_disable_vdd_reg;
}
indio_dev->name = id->name;
indio_dev->info = &mcp4725_info;
indio_dev->channels = &mcp472x_channel[id->driver_data];
indio_dev->num_channels = 1;
indio_dev->modes = INDIO_DIRECT_MODE;
/* read current DAC value and settings */
err = i2c_master_recv(client, inbuf, data->id == MCP4725 ? 3 : 4);
if (err < 0) {
dev_err(&client->dev, "failed to read DAC value");
goto err_disable_vref_reg;
}
pd = (inbuf[0] >> 1) & 0x3;
data->powerdown = pd > 0;
data->powerdown_mode = pd ? pd - 1 : 2; /* largest resistor to gnd */
data->dac_value = (inbuf[1] << 4) | (inbuf[2] >> 4);
if (data->id == MCP4726)
ref = (inbuf[3] >> 3) & 0x3;
if (data->id == MCP4726 && ref != data->ref_mode) {
dev_info(&client->dev,
"voltage reference mode differs (conf: %u, eeprom: %u), setting %u",
data->ref_mode, ref, data->ref_mode);
err = mcp4726_set_cfg(indio_dev);
if (err < 0)
goto err_disable_vref_reg;
}
err = iio_device_register(indio_dev);
if (err)
goto err_disable_vref_reg;
return 0;
err_disable_vref_reg:
if (data->vref_reg)
regulator_disable(data->vref_reg);
err_disable_vdd_reg:
regulator_disable(data->vdd_reg);
return err;
}
static void mcp4725_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct mcp4725_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (data->vref_reg)
regulator_disable(data->vref_reg);
regulator_disable(data->vdd_reg);
}
static const struct i2c_device_id mcp4725_id[] = {
{ "mcp4725", MCP4725 },
{ "mcp4726", MCP4726 },
{ }
};
MODULE_DEVICE_TABLE(i2c, mcp4725_id);
static const struct of_device_id mcp4725_of_match[] = {
{
.compatible = "microchip,mcp4725",
.data = (void *)MCP4725
},
{
.compatible = "microchip,mcp4726",
.data = (void *)MCP4726
},
{ }
};
MODULE_DEVICE_TABLE(of, mcp4725_of_match);
static struct i2c_driver mcp4725_driver = {
.driver = {
.name = MCP4725_DRV_NAME,
.of_match_table = mcp4725_of_match,
.pm = pm_sleep_ptr(&mcp4725_pm_ops),
},
.probe = mcp4725_probe,
.remove = mcp4725_remove,
.id_table = mcp4725_id,
};
module_i2c_driver(mcp4725_driver);
MODULE_AUTHOR("Peter Meerwald <[email protected]>");
MODULE_DESCRIPTION("MCP4725/6 12-bit DAC");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/dac/mcp4725.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Freescale Vybrid vf610 DAC driver
*
* Copyright 2016 Toradex AG
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define VF610_DACx_STATCTRL 0x20
#define VF610_DAC_DACEN BIT(15)
#define VF610_DAC_DACRFS BIT(14)
#define VF610_DAC_LPEN BIT(11)
#define VF610_DAC_DAT0(x) ((x) & 0xFFF)
enum vf610_conversion_mode_sel {
VF610_DAC_CONV_HIGH_POWER,
VF610_DAC_CONV_LOW_POWER,
};
struct vf610_dac {
struct clk *clk;
struct device *dev;
enum vf610_conversion_mode_sel conv_mode;
void __iomem *regs;
struct mutex lock;
};
static void vf610_dac_init(struct vf610_dac *info)
{
int val;
info->conv_mode = VF610_DAC_CONV_LOW_POWER;
val = VF610_DAC_DACEN | VF610_DAC_DACRFS |
VF610_DAC_LPEN;
writel(val, info->regs + VF610_DACx_STATCTRL);
}
static void vf610_dac_exit(struct vf610_dac *info)
{
int val;
val = readl(info->regs + VF610_DACx_STATCTRL);
val &= ~VF610_DAC_DACEN;
writel(val, info->regs + VF610_DACx_STATCTRL);
}
static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int mode)
{
struct vf610_dac *info = iio_priv(indio_dev);
int val;
mutex_lock(&info->lock);
info->conv_mode = mode;
val = readl(info->regs + VF610_DACx_STATCTRL);
if (mode)
val |= VF610_DAC_LPEN;
else
val &= ~VF610_DAC_LPEN;
writel(val, info->regs + VF610_DACx_STATCTRL);
mutex_unlock(&info->lock);
return 0;
}
static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct vf610_dac *info = iio_priv(indio_dev);
return info->conv_mode;
}
static const char * const vf610_conv_modes[] = { "high-power", "low-power" };
static const struct iio_enum vf610_conversion_mode = {
.items = vf610_conv_modes,
.num_items = ARRAY_SIZE(vf610_conv_modes),
.get = vf610_get_conversion_mode,
.set = vf610_set_conversion_mode,
};
static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR,
&vf610_conversion_mode),
{},
};
#define VF610_DAC_CHAN(_chan_type) { \
.type = (_chan_type), \
.output = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.ext_info = vf610_ext_info, \
}
static const struct iio_chan_spec vf610_dac_iio_channels[] = {
VF610_DAC_CHAN(IIO_VOLTAGE),
};
static int vf610_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2,
long mask)
{
struct vf610_dac *info = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
*val = VF610_DAC_DAT0(readl(info->regs));
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/*
* DACRFS is always 1 for valid reference and typical
* reference voltage as per Vybrid datasheet is 3.3V
* from section 9.1.2.1 of Vybrid datasheet
*/
*val = 3300 /* mV */;
*val2 = 12;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
}
static int vf610_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2,
long mask)
{
struct vf610_dac *info = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&info->lock);
writel(VF610_DAC_DAT0(val), info->regs);
mutex_unlock(&info->lock);
return 0;
default:
return -EINVAL;
}
}
static const struct iio_info vf610_dac_iio_info = {
.read_raw = &vf610_read_raw,
.write_raw = &vf610_write_raw,
};
static const struct of_device_id vf610_dac_match[] = {
{ .compatible = "fsl,vf610-dac", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, vf610_dac_match);
static int vf610_dac_probe(struct platform_device *pdev)
{
struct iio_dev *indio_dev;
struct vf610_dac *info;
int ret;
indio_dev = devm_iio_device_alloc(&pdev->dev,
sizeof(struct vf610_dac));
if (!indio_dev) {
dev_err(&pdev->dev, "Failed allocating iio device\n");
return -ENOMEM;
}
info = iio_priv(indio_dev);
info->dev = &pdev->dev;
info->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(info->regs))
return PTR_ERR(info->regs);
info->clk = devm_clk_get(&pdev->dev, "dac");
if (IS_ERR(info->clk)) {
dev_err(&pdev->dev, "Failed getting clock, err = %ld\n",
PTR_ERR(info->clk));
return PTR_ERR(info->clk);
}
platform_set_drvdata(pdev, indio_dev);
indio_dev->name = dev_name(&pdev->dev);
indio_dev->info = &vf610_dac_iio_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = vf610_dac_iio_channels;
indio_dev->num_channels = ARRAY_SIZE(vf610_dac_iio_channels);
mutex_init(&info->lock);
ret = clk_prepare_enable(info->clk);
if (ret) {
dev_err(&pdev->dev,
"Could not prepare or enable the clock\n");
return ret;
}
vf610_dac_init(info);
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&pdev->dev, "Couldn't register the device\n");
goto error_iio_device_register;
}
return 0;
error_iio_device_register:
vf610_dac_exit(info);
clk_disable_unprepare(info->clk);
return ret;
}
static int vf610_dac_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct vf610_dac *info = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
vf610_dac_exit(info);
clk_disable_unprepare(info->clk);
return 0;
}
static int vf610_dac_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct vf610_dac *info = iio_priv(indio_dev);
vf610_dac_exit(info);
clk_disable_unprepare(info->clk);
return 0;
}
static int vf610_dac_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct vf610_dac *info = iio_priv(indio_dev);
int ret;
ret = clk_prepare_enable(info->clk);
if (ret)
return ret;
vf610_dac_init(info);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(vf610_dac_pm_ops, vf610_dac_suspend,
vf610_dac_resume);
static struct platform_driver vf610_dac_driver = {
.probe = vf610_dac_probe,
.remove = vf610_dac_remove,
.driver = {
.name = "vf610-dac",
.of_match_table = vf610_dac_match,
.pm = pm_sleep_ptr(&vf610_dac_pm_ops),
},
};
module_platform_driver(vf610_dac_driver);
MODULE_AUTHOR("Sanchayan Maity <[email protected]>");
MODULE_DESCRIPTION("Freescale VF610 DAC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/vf610_dac.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* IIO driver for the Measurement Computing CIO-DAC
* Copyright (C) 2016 William Breathitt Gray
*
* This driver supports the following Measurement Computing devices: CIO-DAC16,
* CIO-DAC08, and PC104-DAC06.
*/
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/iio/iio.h>
#include <linux/iio/types.h>
#include <linux/isa.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/regmap.h>
#include <linux/types.h>
#define CIO_DAC_NUM_CHAN 16
#define CIO_DAC_CHAN(chan) { \
.type = IIO_VOLTAGE, \
.channel = chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.indexed = 1, \
.output = 1 \
}
#define CIO_DAC_EXTENT 32
static unsigned int base[max_num_isa_dev(CIO_DAC_EXTENT)];
static unsigned int num_cio_dac;
module_param_hw_array(base, uint, ioport, &num_cio_dac, 0);
MODULE_PARM_DESC(base, "Measurement Computing CIO-DAC base addresses");
#define CIO_DAC_BASE 0x00
#define CIO_DAC_CHANNEL_STRIDE 2
static bool cio_dac_precious_reg(struct device *dev, unsigned int reg)
{
/*
* All registers are considered precious; if the XFER jumper is set on
* the device, then no update occurs until a DAC register is read.
*/
return true;
}
static const struct regmap_config cio_dac_regmap_config = {
.reg_bits = 16,
.reg_stride = 2,
.val_bits = 16,
.io_port = true,
.max_register = 0x1F,
.precious_reg = cio_dac_precious_reg,
};
/**
* struct cio_dac_iio - IIO device private data structure
* @map: Regmap for the device
*/
struct cio_dac_iio {
struct regmap *map;
};
static int cio_dac_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long mask)
{
struct cio_dac_iio *const priv = iio_priv(indio_dev);
const unsigned int offset = chan->channel * CIO_DAC_CHANNEL_STRIDE;
int err;
unsigned int dac_val;
if (mask != IIO_CHAN_INFO_RAW)
return -EINVAL;
err = regmap_read(priv->map, CIO_DAC_BASE + offset, &dac_val);
if (err)
return err;
*val = dac_val;
return IIO_VAL_INT;
}
static int cio_dac_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long mask)
{
struct cio_dac_iio *const priv = iio_priv(indio_dev);
const unsigned int offset = chan->channel * CIO_DAC_CHANNEL_STRIDE;
if (mask != IIO_CHAN_INFO_RAW)
return -EINVAL;
/* DAC can only accept up to a 12-bit value */
if ((unsigned int)val > 4095)
return -EINVAL;
return regmap_write(priv->map, CIO_DAC_BASE + offset, val);
}
static const struct iio_info cio_dac_info = {
.read_raw = cio_dac_read_raw,
.write_raw = cio_dac_write_raw
};
static const struct iio_chan_spec cio_dac_channels[CIO_DAC_NUM_CHAN] = {
CIO_DAC_CHAN(0), CIO_DAC_CHAN(1), CIO_DAC_CHAN(2), CIO_DAC_CHAN(3),
CIO_DAC_CHAN(4), CIO_DAC_CHAN(5), CIO_DAC_CHAN(6), CIO_DAC_CHAN(7),
CIO_DAC_CHAN(8), CIO_DAC_CHAN(9), CIO_DAC_CHAN(10), CIO_DAC_CHAN(11),
CIO_DAC_CHAN(12), CIO_DAC_CHAN(13), CIO_DAC_CHAN(14), CIO_DAC_CHAN(15)
};
static int cio_dac_probe(struct device *dev, unsigned int id)
{
struct iio_dev *indio_dev;
struct cio_dac_iio *priv;
void __iomem *regs;
indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
if (!indio_dev)
return -ENOMEM;
if (!devm_request_region(dev, base[id], CIO_DAC_EXTENT,
dev_name(dev))) {
dev_err(dev, "Unable to request port addresses (0x%X-0x%X)\n",
base[id], base[id] + CIO_DAC_EXTENT);
return -EBUSY;
}
regs = devm_ioport_map(dev, base[id], CIO_DAC_EXTENT);
if (!regs)
return -ENOMEM;
priv = iio_priv(indio_dev);
priv->map = devm_regmap_init_mmio(dev, regs, &cio_dac_regmap_config);
if (IS_ERR(priv->map))
return dev_err_probe(dev, PTR_ERR(priv->map),
"Unable to initialize register map\n");
indio_dev->info = &cio_dac_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = cio_dac_channels;
indio_dev->num_channels = CIO_DAC_NUM_CHAN;
indio_dev->name = dev_name(dev);
return devm_iio_device_register(dev, indio_dev);
}
static struct isa_driver cio_dac_driver = {
.probe = cio_dac_probe,
.driver = {
.name = "cio-dac"
}
};
module_isa_driver(cio_dac_driver, num_cio_dac);
MODULE_AUTHOR("William Breathitt Gray <[email protected]>");
MODULE_DESCRIPTION("Measurement Computing CIO-DAC IIO driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/cio-dac.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD5592R Digital <-> Analog converters driver
*
* Copyright 2015-2016 Analog Devices Inc.
* Author: Paul Cercueil <[email protected]>
*/
#include "ad5592r-base.h"
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/spi/spi.h>
#define AD5592R_GPIO_READBACK_EN BIT(10)
#define AD5592R_LDAC_READBACK_EN BIT(6)
static int ad5592r_spi_wnop_r16(struct ad5592r_state *st, __be16 *buf)
{
struct spi_device *spi = container_of(st->dev, struct spi_device, dev);
struct spi_transfer t = {
.tx_buf = &st->spi_msg_nop,
.rx_buf = buf,
.len = 2
};
st->spi_msg_nop = 0; /* NOP */
return spi_sync_transfer(spi, &t, 1);
}
static int ad5592r_write_dac(struct ad5592r_state *st, unsigned chan, u16 value)
{
struct spi_device *spi = container_of(st->dev, struct spi_device, dev);
st->spi_msg = cpu_to_be16(BIT(15) | (chan << 12) | value);
return spi_write(spi, &st->spi_msg, sizeof(st->spi_msg));
}
static int ad5592r_read_adc(struct ad5592r_state *st, unsigned chan, u16 *value)
{
struct spi_device *spi = container_of(st->dev, struct spi_device, dev);
int ret;
st->spi_msg = cpu_to_be16((AD5592R_REG_ADC_SEQ << 11) | BIT(chan));
ret = spi_write(spi, &st->spi_msg, sizeof(st->spi_msg));
if (ret)
return ret;
/*
* Invalid data:
* See Figure 40. Single-Channel ADC Conversion Sequence
*/
ret = ad5592r_spi_wnop_r16(st, &st->spi_msg);
if (ret)
return ret;
ret = ad5592r_spi_wnop_r16(st, &st->spi_msg);
if (ret)
return ret;
*value = be16_to_cpu(st->spi_msg);
return 0;
}
static int ad5592r_reg_write(struct ad5592r_state *st, u8 reg, u16 value)
{
struct spi_device *spi = container_of(st->dev, struct spi_device, dev);
st->spi_msg = cpu_to_be16((reg << 11) | value);
return spi_write(spi, &st->spi_msg, sizeof(st->spi_msg));
}
static int ad5592r_reg_read(struct ad5592r_state *st, u8 reg, u16 *value)
{
struct spi_device *spi = container_of(st->dev, struct spi_device, dev);
int ret;
st->spi_msg = cpu_to_be16((AD5592R_REG_LDAC << 11) |
AD5592R_LDAC_READBACK_EN | (reg << 2));
ret = spi_write(spi, &st->spi_msg, sizeof(st->spi_msg));
if (ret)
return ret;
ret = ad5592r_spi_wnop_r16(st, &st->spi_msg);
if (ret)
return ret;
*value = be16_to_cpu(st->spi_msg);
return 0;
}
static int ad5592r_gpio_read(struct ad5592r_state *st, u8 *value)
{
int ret;
ret = ad5592r_reg_write(st, AD5592R_REG_GPIO_IN_EN,
AD5592R_GPIO_READBACK_EN | st->gpio_in);
if (ret)
return ret;
ret = ad5592r_spi_wnop_r16(st, &st->spi_msg);
if (ret)
return ret;
*value = (u8) be16_to_cpu(st->spi_msg);
return 0;
}
static const struct ad5592r_rw_ops ad5592r_rw_ops = {
.write_dac = ad5592r_write_dac,
.read_adc = ad5592r_read_adc,
.reg_write = ad5592r_reg_write,
.reg_read = ad5592r_reg_read,
.gpio_read = ad5592r_gpio_read,
};
static int ad5592r_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
return ad5592r_probe(&spi->dev, id->name, &ad5592r_rw_ops);
}
static void ad5592r_spi_remove(struct spi_device *spi)
{
ad5592r_remove(&spi->dev);
}
static const struct spi_device_id ad5592r_spi_ids[] = {
{ .name = "ad5592r", },
{}
};
MODULE_DEVICE_TABLE(spi, ad5592r_spi_ids);
static const struct of_device_id ad5592r_of_match[] = {
{ .compatible = "adi,ad5592r", },
{},
};
MODULE_DEVICE_TABLE(of, ad5592r_of_match);
static const struct acpi_device_id ad5592r_acpi_match[] = {
{"ADS5592", },
{ },
};
MODULE_DEVICE_TABLE(acpi, ad5592r_acpi_match);
static struct spi_driver ad5592r_spi_driver = {
.driver = {
.name = "ad5592r",
.of_match_table = ad5592r_of_match,
.acpi_match_table = ad5592r_acpi_match,
},
.probe = ad5592r_spi_probe,
.remove = ad5592r_spi_remove,
.id_table = ad5592r_spi_ids,
};
module_spi_driver(ad5592r_spi_driver);
MODULE_AUTHOR("Paul Cercueil <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_AD5592R);
| linux-master | drivers/iio/dac/ad5592r.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Analog devices AD5764, AD5764R, AD5744, AD5744R quad-channel
* Digital to Analog Converters driver
*
* Copyright 2011 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define AD5764_REG_SF_NOP 0x0
#define AD5764_REG_SF_CONFIG 0x1
#define AD5764_REG_SF_CLEAR 0x4
#define AD5764_REG_SF_LOAD 0x5
#define AD5764_REG_DATA(x) ((2 << 3) | (x))
#define AD5764_REG_COARSE_GAIN(x) ((3 << 3) | (x))
#define AD5764_REG_FINE_GAIN(x) ((4 << 3) | (x))
#define AD5764_REG_OFFSET(x) ((5 << 3) | (x))
#define AD5764_NUM_CHANNELS 4
/**
* struct ad5764_chip_info - chip specific information
* @int_vref: Value of the internal reference voltage in uV - 0 if external
* reference voltage is used
* @channels: channel specification
*/
struct ad5764_chip_info {
unsigned long int_vref;
const struct iio_chan_spec *channels;
};
/**
* struct ad5764_state - driver instance specific data
* @spi: spi_device
* @chip_info: chip info
* @vref_reg: vref supply regulators
* @lock: lock to protect the data buffer during SPI ops
* @data: spi transfer buffers
*/
struct ad5764_state {
struct spi_device *spi;
const struct ad5764_chip_info *chip_info;
struct regulator_bulk_data vref_reg[2];
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
union {
__be32 d32;
u8 d8[4];
} data[2] __aligned(IIO_DMA_MINALIGN);
};
enum ad5764_type {
ID_AD5744,
ID_AD5744R,
ID_AD5764,
ID_AD5764R,
};
#define AD5764_CHANNEL(_chan, _bits) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (_chan), \
.address = (_chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_CALIBSCALE) | \
BIT(IIO_CHAN_INFO_CALIBBIAS), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET), \
.scan_type = { \
.sign = 'u', \
.realbits = (_bits), \
.storagebits = 16, \
.shift = 16 - (_bits), \
}, \
}
#define DECLARE_AD5764_CHANNELS(_name, _bits) \
const struct iio_chan_spec _name##_channels[] = { \
AD5764_CHANNEL(0, (_bits)), \
AD5764_CHANNEL(1, (_bits)), \
AD5764_CHANNEL(2, (_bits)), \
AD5764_CHANNEL(3, (_bits)), \
};
static DECLARE_AD5764_CHANNELS(ad5764, 16);
static DECLARE_AD5764_CHANNELS(ad5744, 14);
static const struct ad5764_chip_info ad5764_chip_infos[] = {
[ID_AD5744] = {
.int_vref = 0,
.channels = ad5744_channels,
},
[ID_AD5744R] = {
.int_vref = 5000000,
.channels = ad5744_channels,
},
[ID_AD5764] = {
.int_vref = 0,
.channels = ad5764_channels,
},
[ID_AD5764R] = {
.int_vref = 5000000,
.channels = ad5764_channels,
},
};
static int ad5764_write(struct iio_dev *indio_dev, unsigned int reg,
unsigned int val)
{
struct ad5764_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
st->data[0].d32 = cpu_to_be32((reg << 16) | val);
ret = spi_write(st->spi, &st->data[0].d8[1], 3);
mutex_unlock(&st->lock);
return ret;
}
static int ad5764_read(struct iio_dev *indio_dev, unsigned int reg,
unsigned int *val)
{
struct ad5764_state *st = iio_priv(indio_dev);
int ret;
struct spi_transfer t[] = {
{
.tx_buf = &st->data[0].d8[1],
.len = 3,
.cs_change = 1,
}, {
.rx_buf = &st->data[1].d8[1],
.len = 3,
},
};
mutex_lock(&st->lock);
st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));
ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
if (ret >= 0)
*val = be32_to_cpu(st->data[1].d32) & 0xffff;
mutex_unlock(&st->lock);
return ret;
}
static int ad5764_chan_info_to_reg(struct iio_chan_spec const *chan, long info)
{
switch (info) {
case IIO_CHAN_INFO_RAW:
return AD5764_REG_DATA(chan->address);
case IIO_CHAN_INFO_CALIBBIAS:
return AD5764_REG_OFFSET(chan->address);
case IIO_CHAN_INFO_CALIBSCALE:
return AD5764_REG_FINE_GAIN(chan->address);
default:
break;
}
return 0;
}
static int ad5764_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long info)
{
const int max_val = (1 << chan->scan_type.realbits);
unsigned int reg;
switch (info) {
case IIO_CHAN_INFO_RAW:
if (val >= max_val || val < 0)
return -EINVAL;
val <<= chan->scan_type.shift;
break;
case IIO_CHAN_INFO_CALIBBIAS:
if (val >= 128 || val < -128)
return -EINVAL;
break;
case IIO_CHAN_INFO_CALIBSCALE:
if (val >= 32 || val < -32)
return -EINVAL;
break;
default:
return -EINVAL;
}
reg = ad5764_chan_info_to_reg(chan, info);
return ad5764_write(indio_dev, reg, (u16)val);
}
static int ad5764_get_channel_vref(struct ad5764_state *st,
unsigned int channel)
{
if (st->chip_info->int_vref)
return st->chip_info->int_vref;
else
return regulator_get_voltage(st->vref_reg[channel / 2].consumer);
}
static int ad5764_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long info)
{
struct ad5764_state *st = iio_priv(indio_dev);
unsigned int reg;
int vref;
int ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
reg = AD5764_REG_DATA(chan->address);
ret = ad5764_read(indio_dev, reg, val);
if (ret < 0)
return ret;
*val >>= chan->scan_type.shift;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBBIAS:
reg = AD5764_REG_OFFSET(chan->address);
ret = ad5764_read(indio_dev, reg, val);
if (ret < 0)
return ret;
*val = sign_extend32(*val, 7);
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBSCALE:
reg = AD5764_REG_FINE_GAIN(chan->address);
ret = ad5764_read(indio_dev, reg, val);
if (ret < 0)
return ret;
*val = sign_extend32(*val, 5);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/* vout = 4 * vref + ((dac_code / 65536) - 0.5) */
vref = ad5764_get_channel_vref(st, chan->channel);
if (vref < 0)
return vref;
*val = vref * 4 / 1000;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_OFFSET:
*val = -(1 << chan->scan_type.realbits) / 2;
return IIO_VAL_INT;
}
return -EINVAL;
}
static const struct iio_info ad5764_info = {
.read_raw = ad5764_read_raw,
.write_raw = ad5764_write_raw,
};
static int ad5764_probe(struct spi_device *spi)
{
enum ad5764_type type = spi_get_device_id(spi)->driver_data;
struct iio_dev *indio_dev;
struct ad5764_state *st;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (indio_dev == NULL) {
dev_err(&spi->dev, "Failed to allocate iio device\n");
return -ENOMEM;
}
st = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
st->spi = spi;
st->chip_info = &ad5764_chip_infos[type];
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->info = &ad5764_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->num_channels = AD5764_NUM_CHANNELS;
indio_dev->channels = st->chip_info->channels;
mutex_init(&st->lock);
if (st->chip_info->int_vref == 0) {
st->vref_reg[0].supply = "vrefAB";
st->vref_reg[1].supply = "vrefCD";
ret = devm_regulator_bulk_get(&st->spi->dev,
ARRAY_SIZE(st->vref_reg), st->vref_reg);
if (ret) {
dev_err(&spi->dev, "Failed to request vref regulators: %d\n",
ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(st->vref_reg),
st->vref_reg);
if (ret) {
dev_err(&spi->dev, "Failed to enable vref regulators: %d\n",
ret);
return ret;
}
}
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
goto error_disable_reg;
}
return 0;
error_disable_reg:
if (st->chip_info->int_vref == 0)
regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);
return ret;
}
static void ad5764_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ad5764_state *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (st->chip_info->int_vref == 0)
regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);
}
static const struct spi_device_id ad5764_ids[] = {
{ "ad5744", ID_AD5744 },
{ "ad5744r", ID_AD5744R },
{ "ad5764", ID_AD5764 },
{ "ad5764r", ID_AD5764R },
{ }
};
MODULE_DEVICE_TABLE(spi, ad5764_ids);
static struct spi_driver ad5764_driver = {
.driver = {
.name = "ad5764",
},
.probe = ad5764_probe,
.remove = ad5764_remove,
.id_table = ad5764_ids,
};
module_spi_driver(ad5764_driver);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5744/AD5744R/AD5764/AD5764R DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5764.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* LTC2632 Digital to analog convertors spi driver
*
* Copyright 2017 Maxime Roussin-Bélanger
* expanded by Silvan Murer <[email protected]>
*/
#include <linux/device.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
#include <asm/unaligned.h>
#define LTC2632_CMD_WRITE_INPUT_N 0x0
#define LTC2632_CMD_UPDATE_DAC_N 0x1
#define LTC2632_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
#define LTC2632_CMD_WRITE_INPUT_N_UPDATE_N 0x3
#define LTC2632_CMD_POWERDOWN_DAC_N 0x4
#define LTC2632_CMD_POWERDOWN_CHIP 0x5
#define LTC2632_CMD_INTERNAL_REFER 0x6
#define LTC2632_CMD_EXTERNAL_REFER 0x7
/**
* struct ltc2632_chip_info - chip specific information
* @channels: channel spec for the DAC
* @num_channels: DAC channel count of the chip
* @vref_mv: internal reference voltage
*/
struct ltc2632_chip_info {
const struct iio_chan_spec *channels;
const size_t num_channels;
const int vref_mv;
};
/**
* struct ltc2632_state - driver instance specific data
* @spi_dev: pointer to the spi_device struct
* @powerdown_cache_mask: used to show current channel powerdown state
* @vref_mv: used reference voltage (internal or external)
* @vref_reg: regulator for the reference voltage
*/
struct ltc2632_state {
struct spi_device *spi_dev;
unsigned int powerdown_cache_mask;
int vref_mv;
struct regulator *vref_reg;
};
enum ltc2632_supported_device_ids {
ID_LTC2632L12,
ID_LTC2632L10,
ID_LTC2632L8,
ID_LTC2632H12,
ID_LTC2632H10,
ID_LTC2632H8,
ID_LTC2634L12,
ID_LTC2634L10,
ID_LTC2634L8,
ID_LTC2634H12,
ID_LTC2634H10,
ID_LTC2634H8,
ID_LTC2636L12,
ID_LTC2636L10,
ID_LTC2636L8,
ID_LTC2636H12,
ID_LTC2636H10,
ID_LTC2636H8,
};
static int ltc2632_spi_write(struct spi_device *spi,
u8 cmd, u8 addr, u16 val, u8 shift)
{
u32 data;
u8 msg[3];
/*
* The input shift register is 24 bits wide.
* The next four are the command bits, C3 to C0,
* followed by the 4-bit DAC address, A3 to A0, and then the
* 12-, 10-, 8-bit data-word. The data-word comprises the 12-,
* 10-, 8-bit input code followed by 4, 6, or 8 don't care bits.
*/
data = (cmd << 20) | (addr << 16) | (val << shift);
put_unaligned_be24(data, &msg[0]);
return spi_write(spi, msg, sizeof(msg));
}
static int ltc2632_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
const struct ltc2632_state *st = iio_priv(indio_dev);
switch (m) {
case IIO_CHAN_INFO_SCALE:
*val = st->vref_mv;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
static int ltc2632_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct ltc2632_state *st = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val >= (1 << chan->scan_type.realbits) || val < 0)
return -EINVAL;
return ltc2632_spi_write(st->spi_dev,
LTC2632_CMD_WRITE_INPUT_N_UPDATE_N,
chan->address, val,
chan->scan_type.shift);
default:
return -EINVAL;
}
}
static ssize_t ltc2632_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct ltc2632_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n",
!!(st->powerdown_cache_mask & (1 << chan->channel)));
}
static ssize_t ltc2632_write_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf,
size_t len)
{
bool pwr_down;
int ret;
struct ltc2632_state *st = iio_priv(indio_dev);
ret = kstrtobool(buf, &pwr_down);
if (ret)
return ret;
if (pwr_down)
st->powerdown_cache_mask |= (1 << chan->channel);
else
st->powerdown_cache_mask &= ~(1 << chan->channel);
ret = ltc2632_spi_write(st->spi_dev,
LTC2632_CMD_POWERDOWN_DAC_N,
chan->channel, 0, 0);
return ret ? ret : len;
}
static const struct iio_info ltc2632_info = {
.write_raw = ltc2632_write_raw,
.read_raw = ltc2632_read_raw,
};
static const struct iio_chan_spec_ext_info ltc2632_ext_info[] = {
{
.name = "powerdown",
.read = ltc2632_read_dac_powerdown,
.write = ltc2632_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
{ },
};
#define LTC2632_CHANNEL(_chan, _bits) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (_chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.address = (_chan), \
.scan_type = { \
.realbits = (_bits), \
.shift = 16 - (_bits), \
}, \
.ext_info = ltc2632_ext_info, \
}
#define DECLARE_LTC2632_CHANNELS(_name, _bits) \
const struct iio_chan_spec _name ## _channels[] = { \
LTC2632_CHANNEL(0, _bits), \
LTC2632_CHANNEL(1, _bits), \
LTC2632_CHANNEL(2, _bits), \
LTC2632_CHANNEL(3, _bits), \
LTC2632_CHANNEL(4, _bits), \
LTC2632_CHANNEL(5, _bits), \
LTC2632_CHANNEL(6, _bits), \
LTC2632_CHANNEL(7, _bits), \
}
static DECLARE_LTC2632_CHANNELS(ltc2632x12, 12);
static DECLARE_LTC2632_CHANNELS(ltc2632x10, 10);
static DECLARE_LTC2632_CHANNELS(ltc2632x8, 8);
static const struct ltc2632_chip_info ltc2632_chip_info_tbl[] = {
[ID_LTC2632L12] = {
.channels = ltc2632x12_channels,
.num_channels = 2,
.vref_mv = 2500,
},
[ID_LTC2632L10] = {
.channels = ltc2632x10_channels,
.num_channels = 2,
.vref_mv = 2500,
},
[ID_LTC2632L8] = {
.channels = ltc2632x8_channels,
.num_channels = 2,
.vref_mv = 2500,
},
[ID_LTC2632H12] = {
.channels = ltc2632x12_channels,
.num_channels = 2,
.vref_mv = 4096,
},
[ID_LTC2632H10] = {
.channels = ltc2632x10_channels,
.num_channels = 2,
.vref_mv = 4096,
},
[ID_LTC2632H8] = {
.channels = ltc2632x8_channels,
.num_channels = 2,
.vref_mv = 4096,
},
[ID_LTC2634L12] = {
.channels = ltc2632x12_channels,
.num_channels = 4,
.vref_mv = 2500,
},
[ID_LTC2634L10] = {
.channels = ltc2632x10_channels,
.num_channels = 4,
.vref_mv = 2500,
},
[ID_LTC2634L8] = {
.channels = ltc2632x8_channels,
.num_channels = 4,
.vref_mv = 2500,
},
[ID_LTC2634H12] = {
.channels = ltc2632x12_channels,
.num_channels = 4,
.vref_mv = 4096,
},
[ID_LTC2634H10] = {
.channels = ltc2632x10_channels,
.num_channels = 4,
.vref_mv = 4096,
},
[ID_LTC2634H8] = {
.channels = ltc2632x8_channels,
.num_channels = 4,
.vref_mv = 4096,
},
[ID_LTC2636L12] = {
.channels = ltc2632x12_channels,
.num_channels = 8,
.vref_mv = 2500,
},
[ID_LTC2636L10] = {
.channels = ltc2632x10_channels,
.num_channels = 8,
.vref_mv = 2500,
},
[ID_LTC2636L8] = {
.channels = ltc2632x8_channels,
.num_channels = 8,
.vref_mv = 2500,
},
[ID_LTC2636H12] = {
.channels = ltc2632x12_channels,
.num_channels = 8,
.vref_mv = 4096,
},
[ID_LTC2636H10] = {
.channels = ltc2632x10_channels,
.num_channels = 8,
.vref_mv = 4096,
},
[ID_LTC2636H8] = {
.channels = ltc2632x8_channels,
.num_channels = 8,
.vref_mv = 4096,
},
};
static int ltc2632_probe(struct spi_device *spi)
{
struct ltc2632_state *st;
struct iio_dev *indio_dev;
struct ltc2632_chip_info *chip_info;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
st->spi_dev = spi;
chip_info = (struct ltc2632_chip_info *)
spi_get_device_id(spi)->driver_data;
st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref");
if (PTR_ERR(st->vref_reg) == -ENODEV) {
/* use internal reference voltage */
st->vref_reg = NULL;
st->vref_mv = chip_info->vref_mv;
ret = ltc2632_spi_write(spi, LTC2632_CMD_INTERNAL_REFER,
0, 0, 0);
if (ret) {
dev_err(&spi->dev,
"Set internal reference command failed, %d\n",
ret);
return ret;
}
} else if (IS_ERR(st->vref_reg)) {
dev_err(&spi->dev,
"Error getting voltage reference regulator\n");
return PTR_ERR(st->vref_reg);
} else {
/* use external reference voltage */
ret = regulator_enable(st->vref_reg);
if (ret) {
dev_err(&spi->dev,
"enable reference regulator failed, %d\n",
ret);
return ret;
}
st->vref_mv = regulator_get_voltage(st->vref_reg) / 1000;
ret = ltc2632_spi_write(spi, LTC2632_CMD_EXTERNAL_REFER,
0, 0, 0);
if (ret) {
dev_err(&spi->dev,
"Set external reference command failed, %d\n",
ret);
return ret;
}
}
indio_dev->name = fwnode_get_name(dev_fwnode(&spi->dev)) ?: spi_get_device_id(spi)->name;
indio_dev->info = <c2632_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = chip_info->channels;
indio_dev->num_channels = chip_info->num_channels;
return iio_device_register(indio_dev);
}
static void ltc2632_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ltc2632_state *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (st->vref_reg)
regulator_disable(st->vref_reg);
}
static const struct spi_device_id ltc2632_id[] = {
{ "ltc2632-l12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L12] },
{ "ltc2632-l10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L10] },
{ "ltc2632-l8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632L8] },
{ "ltc2632-h12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H12] },
{ "ltc2632-h10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H10] },
{ "ltc2632-h8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2632H8] },
{ "ltc2634-l12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634L12] },
{ "ltc2634-l10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634L10] },
{ "ltc2634-l8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634L8] },
{ "ltc2634-h12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634H12] },
{ "ltc2634-h10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634H10] },
{ "ltc2634-h8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2634H8] },
{ "ltc2636-l12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636L12] },
{ "ltc2636-l10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636L10] },
{ "ltc2636-l8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636L8] },
{ "ltc2636-h12", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636H12] },
{ "ltc2636-h10", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636H10] },
{ "ltc2636-h8", (kernel_ulong_t)<c2632_chip_info_tbl[ID_LTC2636H8] },
{}
};
MODULE_DEVICE_TABLE(spi, ltc2632_id);
static const struct of_device_id ltc2632_of_match[] = {
{
.compatible = "lltc,ltc2632-l12",
.data = <c2632_chip_info_tbl[ID_LTC2632L12]
}, {
.compatible = "lltc,ltc2632-l10",
.data = <c2632_chip_info_tbl[ID_LTC2632L10]
}, {
.compatible = "lltc,ltc2632-l8",
.data = <c2632_chip_info_tbl[ID_LTC2632L8]
}, {
.compatible = "lltc,ltc2632-h12",
.data = <c2632_chip_info_tbl[ID_LTC2632H12]
}, {
.compatible = "lltc,ltc2632-h10",
.data = <c2632_chip_info_tbl[ID_LTC2632H10]
}, {
.compatible = "lltc,ltc2632-h8",
.data = <c2632_chip_info_tbl[ID_LTC2632H8]
}, {
.compatible = "lltc,ltc2634-l12",
.data = <c2632_chip_info_tbl[ID_LTC2634L12]
}, {
.compatible = "lltc,ltc2634-l10",
.data = <c2632_chip_info_tbl[ID_LTC2634L10]
}, {
.compatible = "lltc,ltc2634-l8",
.data = <c2632_chip_info_tbl[ID_LTC2634L8]
}, {
.compatible = "lltc,ltc2634-h12",
.data = <c2632_chip_info_tbl[ID_LTC2634H12]
}, {
.compatible = "lltc,ltc2634-h10",
.data = <c2632_chip_info_tbl[ID_LTC2634H10]
}, {
.compatible = "lltc,ltc2634-h8",
.data = <c2632_chip_info_tbl[ID_LTC2634H8]
}, {
.compatible = "lltc,ltc2636-l12",
.data = <c2632_chip_info_tbl[ID_LTC2636L12]
}, {
.compatible = "lltc,ltc2636-l10",
.data = <c2632_chip_info_tbl[ID_LTC2636L10]
}, {
.compatible = "lltc,ltc2636-l8",
.data = <c2632_chip_info_tbl[ID_LTC2636L8]
}, {
.compatible = "lltc,ltc2636-h12",
.data = <c2632_chip_info_tbl[ID_LTC2636H12]
}, {
.compatible = "lltc,ltc2636-h10",
.data = <c2632_chip_info_tbl[ID_LTC2636H10]
}, {
.compatible = "lltc,ltc2636-h8",
.data = <c2632_chip_info_tbl[ID_LTC2636H8]
},
{}
};
MODULE_DEVICE_TABLE(of, ltc2632_of_match);
static struct spi_driver ltc2632_driver = {
.driver = {
.name = "ltc2632",
.of_match_table = ltc2632_of_match,
},
.probe = ltc2632_probe,
.remove = ltc2632_remove,
.id_table = ltc2632_id,
};
module_spi_driver(ltc2632_driver);
MODULE_AUTHOR("Maxime Roussin-Belanger <[email protected]>");
MODULE_DESCRIPTION("LTC2632 DAC SPI driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ltc2632.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD5592R Digital <-> Analog converters driver
*
* Copyright 2014-2016 Analog Devices Inc.
* Author: Paul Cercueil <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/property.h>
#include <dt-bindings/iio/adi,ad5592r.h>
#include "ad5592r-base.h"
static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct ad5592r_state *st = gpiochip_get_data(chip);
int ret = 0;
u8 val;
mutex_lock(&st->gpio_lock);
if (st->gpio_out & BIT(offset))
val = st->gpio_val;
else
ret = st->ops->gpio_read(st, &val);
mutex_unlock(&st->gpio_lock);
if (ret < 0)
return ret;
return !!(val & BIT(offset));
}
static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct ad5592r_state *st = gpiochip_get_data(chip);
mutex_lock(&st->gpio_lock);
if (value)
st->gpio_val |= BIT(offset);
else
st->gpio_val &= ~BIT(offset);
st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
mutex_unlock(&st->gpio_lock);
}
static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct ad5592r_state *st = gpiochip_get_data(chip);
int ret;
mutex_lock(&st->gpio_lock);
st->gpio_out &= ~BIT(offset);
st->gpio_in |= BIT(offset);
ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
if (ret < 0)
goto err_unlock;
ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
err_unlock:
mutex_unlock(&st->gpio_lock);
return ret;
}
static int ad5592r_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct ad5592r_state *st = gpiochip_get_data(chip);
int ret;
mutex_lock(&st->gpio_lock);
if (value)
st->gpio_val |= BIT(offset);
else
st->gpio_val &= ~BIT(offset);
st->gpio_in &= ~BIT(offset);
st->gpio_out |= BIT(offset);
ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
if (ret < 0)
goto err_unlock;
ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
if (ret < 0)
goto err_unlock;
ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
err_unlock:
mutex_unlock(&st->gpio_lock);
return ret;
}
static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct ad5592r_state *st = gpiochip_get_data(chip);
if (!(st->gpio_map & BIT(offset))) {
dev_err(st->dev, "GPIO %d is reserved by alternate function\n",
offset);
return -ENODEV;
}
return 0;
}
static const char * const ad5592r_gpio_names[] = {
"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5", "GPIO6", "GPIO7",
};
static int ad5592r_gpio_init(struct ad5592r_state *st)
{
if (!st->gpio_map)
return 0;
st->gpiochip.label = dev_name(st->dev);
st->gpiochip.base = -1;
st->gpiochip.ngpio = 8;
st->gpiochip.parent = st->dev;
st->gpiochip.can_sleep = true;
st->gpiochip.direction_input = ad5592r_gpio_direction_input;
st->gpiochip.direction_output = ad5592r_gpio_direction_output;
st->gpiochip.get = ad5592r_gpio_get;
st->gpiochip.set = ad5592r_gpio_set;
st->gpiochip.request = ad5592r_gpio_request;
st->gpiochip.owner = THIS_MODULE;
st->gpiochip.names = ad5592r_gpio_names;
mutex_init(&st->gpio_lock);
return gpiochip_add_data(&st->gpiochip, st);
}
static void ad5592r_gpio_cleanup(struct ad5592r_state *st)
{
if (st->gpio_map)
gpiochip_remove(&st->gpiochip);
}
static int ad5592r_reset(struct ad5592r_state *st)
{
struct gpio_desc *gpio;
gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(gpio))
return PTR_ERR(gpio);
if (gpio) {
udelay(1);
gpiod_set_value(gpio, 1);
} else {
mutex_lock(&st->lock);
/* Writing this magic value resets the device */
st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac);
mutex_unlock(&st->lock);
}
udelay(250);
return 0;
}
static int ad5592r_get_vref(struct ad5592r_state *st)
{
int ret;
if (st->reg) {
ret = regulator_get_voltage(st->reg);
if (ret < 0)
return ret;
return ret / 1000;
} else {
return 2500;
}
}
static int ad5592r_set_channel_modes(struct ad5592r_state *st)
{
const struct ad5592r_rw_ops *ops = st->ops;
int ret;
unsigned i;
u8 pulldown = 0, tristate = 0, dac = 0, adc = 0;
u16 read_back;
for (i = 0; i < st->num_channels; i++) {
switch (st->channel_modes[i]) {
case CH_MODE_DAC:
dac |= BIT(i);
break;
case CH_MODE_ADC:
adc |= BIT(i);
break;
case CH_MODE_DAC_AND_ADC:
dac |= BIT(i);
adc |= BIT(i);
break;
case CH_MODE_GPIO:
st->gpio_map |= BIT(i);
st->gpio_in |= BIT(i); /* Default to input */
break;
case CH_MODE_UNUSED:
default:
switch (st->channel_offstate[i]) {
case CH_OFFSTATE_OUT_TRISTATE:
tristate |= BIT(i);
break;
case CH_OFFSTATE_OUT_LOW:
st->gpio_out |= BIT(i);
break;
case CH_OFFSTATE_OUT_HIGH:
st->gpio_out |= BIT(i);
st->gpio_val |= BIT(i);
break;
case CH_OFFSTATE_PULLDOWN:
default:
pulldown |= BIT(i);
break;
}
}
}
mutex_lock(&st->lock);
/* Pull down unused pins to GND */
ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown);
if (ret)
goto err_unlock;
ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate);
if (ret)
goto err_unlock;
/* Configure pins that we use */
ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac);
if (ret)
goto err_unlock;
ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc);
if (ret)
goto err_unlock;
ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
if (ret)
goto err_unlock;
ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
if (ret)
goto err_unlock;
ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
if (ret)
goto err_unlock;
/* Verify that we can read back at least one register */
ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back);
if (!ret && (read_back & 0xff) != adc)
ret = -EIO;
err_unlock:
mutex_unlock(&st->lock);
return ret;
}
static int ad5592r_reset_channel_modes(struct ad5592r_state *st)
{
int i;
for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++)
st->channel_modes[i] = CH_MODE_UNUSED;
return ad5592r_set_channel_modes(st);
}
static int ad5592r_write_raw(struct iio_dev *iio_dev,
struct iio_chan_spec const *chan, int val, int val2, long mask)
{
struct ad5592r_state *st = iio_priv(iio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val >= (1 << chan->scan_type.realbits) || val < 0)
return -EINVAL;
if (!chan->output)
return -EINVAL;
mutex_lock(&st->lock);
ret = st->ops->write_dac(st, chan->channel, val);
if (!ret)
st->cached_dac[chan->channel] = val;
mutex_unlock(&st->lock);
return ret;
case IIO_CHAN_INFO_SCALE:
if (chan->type == IIO_VOLTAGE) {
bool gain;
if (val == st->scale_avail[0][0] &&
val2 == st->scale_avail[0][1])
gain = false;
else if (val == st->scale_avail[1][0] &&
val2 == st->scale_avail[1][1])
gain = true;
else
return -EINVAL;
mutex_lock(&st->lock);
ret = st->ops->reg_read(st, AD5592R_REG_CTRL,
&st->cached_gp_ctrl);
if (ret < 0) {
mutex_unlock(&st->lock);
return ret;
}
if (chan->output) {
if (gain)
st->cached_gp_ctrl |=
AD5592R_REG_CTRL_DAC_RANGE;
else
st->cached_gp_ctrl &=
~AD5592R_REG_CTRL_DAC_RANGE;
} else {
if (gain)
st->cached_gp_ctrl |=
AD5592R_REG_CTRL_ADC_RANGE;
else
st->cached_gp_ctrl &=
~AD5592R_REG_CTRL_ADC_RANGE;
}
ret = st->ops->reg_write(st, AD5592R_REG_CTRL,
st->cached_gp_ctrl);
mutex_unlock(&st->lock);
return ret;
}
break;
default:
return -EINVAL;
}
return 0;
}
static int ad5592r_read_raw(struct iio_dev *iio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long m)
{
struct ad5592r_state *st = iio_priv(iio_dev);
u16 read_val;
int ret, mult;
switch (m) {
case IIO_CHAN_INFO_RAW:
if (!chan->output) {
mutex_lock(&st->lock);
ret = st->ops->read_adc(st, chan->channel, &read_val);
mutex_unlock(&st->lock);
if (ret)
return ret;
if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) {
dev_err(st->dev, "Error while reading channel %u\n",
chan->channel);
return -EIO;
}
read_val &= GENMASK(11, 0);
} else {
mutex_lock(&st->lock);
read_val = st->cached_dac[chan->channel];
mutex_unlock(&st->lock);
}
dev_dbg(st->dev, "Channel %u read: 0x%04hX\n",
chan->channel, read_val);
*val = (int) read_val;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = ad5592r_get_vref(st);
if (chan->type == IIO_TEMP) {
s64 tmp = *val * (3767897513LL / 25LL);
*val = div_s64_rem(tmp, 1000000000LL, val2);
return IIO_VAL_INT_PLUS_MICRO;
}
mutex_lock(&st->lock);
if (chan->output)
mult = !!(st->cached_gp_ctrl &
AD5592R_REG_CTRL_DAC_RANGE);
else
mult = !!(st->cached_gp_ctrl &
AD5592R_REG_CTRL_ADC_RANGE);
mutex_unlock(&st->lock);
*val *= ++mult;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_OFFSET:
ret = ad5592r_get_vref(st);
mutex_lock(&st->lock);
if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE)
*val = (-34365 * 25) / ret;
else
*val = (-75365 * 25) / ret;
mutex_unlock(&st->lock);
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, long mask)
{
switch (mask) {
case IIO_CHAN_INFO_SCALE:
return IIO_VAL_INT_PLUS_NANO;
default:
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
}
static const struct iio_info ad5592r_info = {
.read_raw = ad5592r_read_raw,
.write_raw = ad5592r_write_raw,
.write_raw_get_fmt = ad5592r_write_raw_get_fmt,
};
static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct ad5592r_state *st = iio_priv(iio_dev);
return sprintf(buf, "%d.%09u %d.%09u\n",
st->scale_avail[0][0], st->scale_avail[0][1],
st->scale_avail[1][0], st->scale_avail[1][1]);
}
static const struct iio_chan_spec_ext_info ad5592r_ext_info[] = {
{
.name = "scale_available",
.read = ad5592r_show_scale_available,
.shared = IIO_SHARED_BY_TYPE,
},
{},
};
static void ad5592r_setup_channel(struct iio_dev *iio_dev,
struct iio_chan_spec *chan, bool output, unsigned id)
{
chan->type = IIO_VOLTAGE;
chan->indexed = 1;
chan->output = output;
chan->channel = id;
chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
chan->scan_type.sign = 'u';
chan->scan_type.realbits = 12;
chan->scan_type.storagebits = 16;
chan->ext_info = ad5592r_ext_info;
}
static int ad5592r_alloc_channels(struct iio_dev *iio_dev)
{
struct ad5592r_state *st = iio_priv(iio_dev);
unsigned i, curr_channel = 0,
num_channels = st->num_channels;
struct iio_chan_spec *channels;
struct fwnode_handle *child;
u32 reg, tmp;
int ret;
device_for_each_child_node(st->dev, child) {
ret = fwnode_property_read_u32(child, "reg", ®);
if (ret || reg >= ARRAY_SIZE(st->channel_modes))
continue;
ret = fwnode_property_read_u32(child, "adi,mode", &tmp);
if (!ret)
st->channel_modes[reg] = tmp;
ret = fwnode_property_read_u32(child, "adi,off-state", &tmp);
if (!ret)
st->channel_offstate[reg] = tmp;
}
channels = devm_kcalloc(st->dev,
1 + 2 * num_channels, sizeof(*channels),
GFP_KERNEL);
if (!channels)
return -ENOMEM;
for (i = 0; i < num_channels; i++) {
switch (st->channel_modes[i]) {
case CH_MODE_DAC:
ad5592r_setup_channel(iio_dev, &channels[curr_channel],
true, i);
curr_channel++;
break;
case CH_MODE_ADC:
ad5592r_setup_channel(iio_dev, &channels[curr_channel],
false, i);
curr_channel++;
break;
case CH_MODE_DAC_AND_ADC:
ad5592r_setup_channel(iio_dev, &channels[curr_channel],
true, i);
curr_channel++;
ad5592r_setup_channel(iio_dev, &channels[curr_channel],
false, i);
curr_channel++;
break;
default:
continue;
}
}
channels[curr_channel].type = IIO_TEMP;
channels[curr_channel].channel = 8;
channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET);
curr_channel++;
iio_dev->num_channels = curr_channel;
iio_dev->channels = channels;
return 0;
}
static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV)
{
s64 tmp = (s64)vref_mV * 1000000000LL >> 12;
st->scale_avail[0][0] =
div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]);
st->scale_avail[1][0] =
div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]);
}
int ad5592r_probe(struct device *dev, const char *name,
const struct ad5592r_rw_ops *ops)
{
struct iio_dev *iio_dev;
struct ad5592r_state *st;
int ret;
iio_dev = devm_iio_device_alloc(dev, sizeof(*st));
if (!iio_dev)
return -ENOMEM;
st = iio_priv(iio_dev);
st->dev = dev;
st->ops = ops;
st->num_channels = 8;
dev_set_drvdata(dev, iio_dev);
st->reg = devm_regulator_get_optional(dev, "vref");
if (IS_ERR(st->reg)) {
if ((PTR_ERR(st->reg) != -ENODEV) && dev_fwnode(dev))
return PTR_ERR(st->reg);
st->reg = NULL;
} else {
ret = regulator_enable(st->reg);
if (ret)
return ret;
}
iio_dev->name = name;
iio_dev->info = &ad5592r_info;
iio_dev->modes = INDIO_DIRECT_MODE;
mutex_init(&st->lock);
ad5592r_init_scales(st, ad5592r_get_vref(st));
ret = ad5592r_reset(st);
if (ret)
goto error_disable_reg;
ret = ops->reg_write(st, AD5592R_REG_PD,
(st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0);
if (ret)
goto error_disable_reg;
ret = ad5592r_alloc_channels(iio_dev);
if (ret)
goto error_disable_reg;
ret = ad5592r_set_channel_modes(st);
if (ret)
goto error_reset_ch_modes;
ret = iio_device_register(iio_dev);
if (ret)
goto error_reset_ch_modes;
ret = ad5592r_gpio_init(st);
if (ret)
goto error_dev_unregister;
return 0;
error_dev_unregister:
iio_device_unregister(iio_dev);
error_reset_ch_modes:
ad5592r_reset_channel_modes(st);
error_disable_reg:
if (st->reg)
regulator_disable(st->reg);
return ret;
}
EXPORT_SYMBOL_NS_GPL(ad5592r_probe, IIO_AD5592R);
void ad5592r_remove(struct device *dev)
{
struct iio_dev *iio_dev = dev_get_drvdata(dev);
struct ad5592r_state *st = iio_priv(iio_dev);
iio_device_unregister(iio_dev);
ad5592r_reset_channel_modes(st);
ad5592r_gpio_cleanup(st);
if (st->reg)
regulator_disable(st->reg);
}
EXPORT_SYMBOL_NS_GPL(ad5592r_remove, IIO_AD5592R);
MODULE_AUTHOR("Paul Cercueil <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5592r-base.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD5593R Digital <-> Analog converters driver
*
* Copyright 2015-2016 Analog Devices Inc.
* Author: Paul Cercueil <[email protected]>
*/
#include "ad5592r-base.h"
#include <linux/bitops.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <asm/unaligned.h>
#define AD5593R_MODE_CONF (0 << 4)
#define AD5593R_MODE_DAC_WRITE (1 << 4)
#define AD5593R_MODE_ADC_READBACK (4 << 4)
#define AD5593R_MODE_DAC_READBACK (5 << 4)
#define AD5593R_MODE_GPIO_READBACK (6 << 4)
#define AD5593R_MODE_REG_READBACK (7 << 4)
static int ad5593r_read_word(struct i2c_client *i2c, u8 reg, u16 *value)
{
int ret;
u8 buf[2];
ret = i2c_smbus_write_byte(i2c, reg);
if (ret < 0)
return ret;
ret = i2c_master_recv(i2c, buf, sizeof(buf));
if (ret < 0)
return ret;
*value = get_unaligned_be16(buf);
return 0;
}
static int ad5593r_write_dac(struct ad5592r_state *st, unsigned chan, u16 value)
{
struct i2c_client *i2c = to_i2c_client(st->dev);
return i2c_smbus_write_word_swapped(i2c,
AD5593R_MODE_DAC_WRITE | chan, value);
}
static int ad5593r_read_adc(struct ad5592r_state *st, unsigned chan, u16 *value)
{
struct i2c_client *i2c = to_i2c_client(st->dev);
s32 val;
val = i2c_smbus_write_word_swapped(i2c,
AD5593R_MODE_CONF | AD5592R_REG_ADC_SEQ, BIT(chan));
if (val < 0)
return (int) val;
return ad5593r_read_word(i2c, AD5593R_MODE_ADC_READBACK, value);
}
static int ad5593r_reg_write(struct ad5592r_state *st, u8 reg, u16 value)
{
struct i2c_client *i2c = to_i2c_client(st->dev);
return i2c_smbus_write_word_swapped(i2c,
AD5593R_MODE_CONF | reg, value);
}
static int ad5593r_reg_read(struct ad5592r_state *st, u8 reg, u16 *value)
{
struct i2c_client *i2c = to_i2c_client(st->dev);
return ad5593r_read_word(i2c, AD5593R_MODE_REG_READBACK | reg, value);
}
static int ad5593r_gpio_read(struct ad5592r_state *st, u8 *value)
{
struct i2c_client *i2c = to_i2c_client(st->dev);
u16 val;
int ret;
ret = ad5593r_read_word(i2c, AD5593R_MODE_GPIO_READBACK, &val);
if (ret)
return ret;
*value = (u8) val;
return 0;
}
static const struct ad5592r_rw_ops ad5593r_rw_ops = {
.write_dac = ad5593r_write_dac,
.read_adc = ad5593r_read_adc,
.reg_write = ad5593r_reg_write,
.reg_read = ad5593r_reg_read,
.gpio_read = ad5593r_gpio_read,
};
static int ad5593r_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
if (!i2c_check_functionality(i2c->adapter,
I2C_FUNC_SMBUS_BYTE | I2C_FUNC_I2C))
return -EOPNOTSUPP;
return ad5592r_probe(&i2c->dev, id->name, &ad5593r_rw_ops);
}
static void ad5593r_i2c_remove(struct i2c_client *i2c)
{
ad5592r_remove(&i2c->dev);
}
static const struct i2c_device_id ad5593r_i2c_ids[] = {
{ .name = "ad5593r", },
{},
};
MODULE_DEVICE_TABLE(i2c, ad5593r_i2c_ids);
static const struct of_device_id ad5593r_of_match[] = {
{ .compatible = "adi,ad5593r", },
{},
};
MODULE_DEVICE_TABLE(of, ad5593r_of_match);
static const struct acpi_device_id ad5593r_acpi_match[] = {
{"ADS5593", },
{ },
};
MODULE_DEVICE_TABLE(acpi, ad5593r_acpi_match);
static struct i2c_driver ad5593r_driver = {
.driver = {
.name = "ad5593r",
.of_match_table = ad5593r_of_match,
.acpi_match_table = ad5593r_acpi_match,
},
.probe = ad5593r_i2c_probe,
.remove = ad5593r_i2c_remove,
.id_table = ad5593r_i2c_ids,
};
module_i2c_driver(ad5593r_driver);
MODULE_AUTHOR("Paul Cercueil <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5593R multi-channel converters");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_AD5592R);
| linux-master | drivers/iio/dac/ad5593r.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Maxim Integrated
* 7-bit, Multi-Channel Sink/Source Current DAC Driver
* Copyright (C) 2017 Maxim Integrated
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/driver.h>
#include <linux/iio/machine.h>
#include <linux/iio/consumer.h>
#define DS4422_MAX_DAC_CHANNELS 2
#define DS4424_MAX_DAC_CHANNELS 4
#define DS4424_DAC_ADDR(chan) ((chan) + 0xf8)
#define DS4424_SOURCE_I 1
#define DS4424_SINK_I 0
#define DS4424_CHANNEL(chan) { \
.type = IIO_CURRENT, \
.indexed = 1, \
.output = 1, \
.channel = chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
}
/*
* DS4424 DAC control register 8 bits
* [7] 0: to sink; 1: to source
* [6:0] steps to sink/source
* bit[7] looks like a sign bit, but the value of the register is
* not a two's complement code considering the bit[6:0] is a absolute
* distance from the zero point.
*/
union ds4424_raw_data {
struct {
u8 dx:7;
u8 source_bit:1;
};
u8 bits;
};
enum ds4424_device_ids {
ID_DS4422,
ID_DS4424,
};
struct ds4424_data {
struct i2c_client *client;
struct mutex lock;
uint8_t save[DS4424_MAX_DAC_CHANNELS];
struct regulator *vcc_reg;
uint8_t raw[DS4424_MAX_DAC_CHANNELS];
};
static const struct iio_chan_spec ds4424_channels[] = {
DS4424_CHANNEL(0),
DS4424_CHANNEL(1),
DS4424_CHANNEL(2),
DS4424_CHANNEL(3),
};
static int ds4424_get_value(struct iio_dev *indio_dev,
int *val, int channel)
{
struct ds4424_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->lock);
ret = i2c_smbus_read_byte_data(data->client, DS4424_DAC_ADDR(channel));
if (ret < 0)
goto fail;
*val = ret;
fail:
mutex_unlock(&data->lock);
return ret;
}
static int ds4424_set_value(struct iio_dev *indio_dev,
int val, struct iio_chan_spec const *chan)
{
struct ds4424_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->lock);
ret = i2c_smbus_write_byte_data(data->client,
DS4424_DAC_ADDR(chan->channel), val);
if (ret < 0)
goto fail;
data->raw[chan->channel] = val;
fail:
mutex_unlock(&data->lock);
return ret;
}
static int ds4424_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
union ds4424_raw_data raw;
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = ds4424_get_value(indio_dev, val, chan->channel);
if (ret < 0) {
pr_err("%s : ds4424_get_value returned %d\n",
__func__, ret);
return ret;
}
raw.bits = *val;
*val = raw.dx;
if (raw.source_bit == DS4424_SINK_I)
*val = -*val;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int ds4424_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
union ds4424_raw_data raw;
if (val2 != 0)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val < S8_MIN || val > S8_MAX)
return -EINVAL;
if (val > 0) {
raw.source_bit = DS4424_SOURCE_I;
raw.dx = val;
} else {
raw.source_bit = DS4424_SINK_I;
raw.dx = -val;
}
return ds4424_set_value(indio_dev, raw.bits, chan);
default:
return -EINVAL;
}
}
static int ds4424_verify_chip(struct iio_dev *indio_dev)
{
int ret, val;
ret = ds4424_get_value(indio_dev, &val, 0);
if (ret < 0)
dev_err(&indio_dev->dev,
"%s failed. ret: %d\n", __func__, ret);
return ret;
}
static int ds4424_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct ds4424_data *data = iio_priv(indio_dev);
int ret = 0;
int i;
for (i = 0; i < indio_dev->num_channels; i++) {
data->save[i] = data->raw[i];
ret = ds4424_set_value(indio_dev, 0,
&indio_dev->channels[i]);
if (ret < 0)
return ret;
}
return ret;
}
static int ds4424_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct ds4424_data *data = iio_priv(indio_dev);
int ret = 0;
int i;
for (i = 0; i < indio_dev->num_channels; i++) {
ret = ds4424_set_value(indio_dev, data->save[i],
&indio_dev->channels[i]);
if (ret < 0)
return ret;
}
return ret;
}
static DEFINE_SIMPLE_DEV_PM_OPS(ds4424_pm_ops, ds4424_suspend, ds4424_resume);
static const struct iio_info ds4424_info = {
.read_raw = ds4424_read_raw,
.write_raw = ds4424_write_raw,
};
static int ds4424_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct ds4424_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev) {
dev_err(&client->dev, "iio dev alloc failed.\n");
return -ENOMEM;
}
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
indio_dev->name = id->name;
data->vcc_reg = devm_regulator_get(&client->dev, "vcc");
if (IS_ERR(data->vcc_reg))
return dev_err_probe(&client->dev, PTR_ERR(data->vcc_reg),
"Failed to get vcc-supply regulator.\n");
mutex_init(&data->lock);
ret = regulator_enable(data->vcc_reg);
if (ret < 0) {
dev_err(&client->dev,
"Unable to enable the regulator.\n");
return ret;
}
usleep_range(1000, 1200);
ret = ds4424_verify_chip(indio_dev);
if (ret < 0)
goto fail;
switch (id->driver_data) {
case ID_DS4422:
indio_dev->num_channels = DS4422_MAX_DAC_CHANNELS;
break;
case ID_DS4424:
indio_dev->num_channels = DS4424_MAX_DAC_CHANNELS;
break;
default:
dev_err(&client->dev,
"ds4424: Invalid chip id.\n");
ret = -ENXIO;
goto fail;
}
indio_dev->channels = ds4424_channels;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &ds4424_info;
ret = iio_device_register(indio_dev);
if (ret < 0) {
dev_err(&client->dev,
"iio_device_register failed. ret: %d\n", ret);
goto fail;
}
return ret;
fail:
regulator_disable(data->vcc_reg);
return ret;
}
static void ds4424_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct ds4424_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
regulator_disable(data->vcc_reg);
}
static const struct i2c_device_id ds4424_id[] = {
{ "ds4422", ID_DS4422 },
{ "ds4424", ID_DS4424 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ds4424_id);
static const struct of_device_id ds4424_of_match[] = {
{ .compatible = "maxim,ds4422" },
{ .compatible = "maxim,ds4424" },
{ },
};
MODULE_DEVICE_TABLE(of, ds4424_of_match);
static struct i2c_driver ds4424_driver = {
.driver = {
.name = "ds4424",
.of_match_table = ds4424_of_match,
.pm = pm_sleep_ptr(&ds4424_pm_ops),
},
.probe = ds4424_probe,
.remove = ds4424_remove,
.id_table = ds4424_id,
};
module_i2c_driver(ds4424_driver);
MODULE_DESCRIPTION("Maxim DS4424 DAC Driver");
MODULE_AUTHOR("Ismail H. Kose <[email protected]>");
MODULE_AUTHOR("Vishal Sood <[email protected]>");
MODULE_AUTHOR("David Jung <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ds4424.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* max517.c - Support for Maxim MAX517, MAX518 and MAX519
*
* Copyright (C) 2010, 2011 Roland Stigge <[email protected]>
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/dac/max517.h>
#define MAX517_DRV_NAME "max517"
/* Commands */
#define COMMAND_CHANNEL0 0x00
#define COMMAND_CHANNEL1 0x01 /* for MAX518 and MAX519 */
#define COMMAND_PD 0x08 /* Power Down */
enum max517_device_ids {
ID_MAX517,
ID_MAX518,
ID_MAX519,
ID_MAX520,
ID_MAX521,
};
struct max517_data {
struct i2c_client *client;
unsigned short vref_mv[8];
};
/*
* channel: bit 0: channel 1
* bit 1: channel 2
* (this way, it's possible to set both channels at once)
*/
static int max517_set_value(struct iio_dev *indio_dev,
long val, int channel)
{
struct max517_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
u8 outbuf[2];
int res;
if (val < 0 || val > 255)
return -EINVAL;
outbuf[0] = channel;
outbuf[1] = val;
res = i2c_master_send(client, outbuf, 2);
if (res < 0)
return res;
else if (res != 2)
return -EIO;
else
return 0;
}
static int max517_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct max517_data *data = iio_priv(indio_dev);
switch (m) {
case IIO_CHAN_INFO_SCALE:
/* Corresponds to Vref / 2^(bits) */
*val = data->vref_mv[chan->channel];
*val2 = 8;
return IIO_VAL_FRACTIONAL_LOG2;
default:
break;
}
return -EINVAL;
}
static int max517_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long mask)
{
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = max517_set_value(indio_dev, val, chan->channel);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int max517_suspend(struct device *dev)
{
u8 outbuf = COMMAND_PD;
return i2c_master_send(to_i2c_client(dev), &outbuf, 1);
}
static int max517_resume(struct device *dev)
{
u8 outbuf = 0;
return i2c_master_send(to_i2c_client(dev), &outbuf, 1);
}
static DEFINE_SIMPLE_DEV_PM_OPS(max517_pm_ops, max517_suspend, max517_resume);
static const struct iio_info max517_info = {
.read_raw = max517_read_raw,
.write_raw = max517_write_raw,
};
#define MAX517_CHANNEL(chan) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
}
static const struct iio_chan_spec max517_channels[] = {
MAX517_CHANNEL(0),
MAX517_CHANNEL(1),
MAX517_CHANNEL(2),
MAX517_CHANNEL(3),
MAX517_CHANNEL(4),
MAX517_CHANNEL(5),
MAX517_CHANNEL(6),
MAX517_CHANNEL(7),
};
static int max517_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct max517_data *data;
struct iio_dev *indio_dev;
struct max517_platform_data *platform_data = client->dev.platform_data;
int chan;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->client = client;
switch (id->driver_data) {
case ID_MAX521:
indio_dev->num_channels = 8;
break;
case ID_MAX520:
indio_dev->num_channels = 4;
break;
case ID_MAX519:
case ID_MAX518:
indio_dev->num_channels = 2;
break;
default: /* single channel for MAX517 */
indio_dev->num_channels = 1;
break;
}
indio_dev->channels = max517_channels;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &max517_info;
/*
* Reference voltage on MAX518 and default is 5V, else take vref_mv
* from platform_data
*/
for (chan = 0; chan < indio_dev->num_channels; chan++) {
if (id->driver_data == ID_MAX518 || !platform_data)
data->vref_mv[chan] = 5000; /* mV */
else
data->vref_mv[chan] = platform_data->vref_mv[chan];
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id max517_id[] = {
{ "max517", ID_MAX517 },
{ "max518", ID_MAX518 },
{ "max519", ID_MAX519 },
{ "max520", ID_MAX520 },
{ "max521", ID_MAX521 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max517_id);
static struct i2c_driver max517_driver = {
.driver = {
.name = MAX517_DRV_NAME,
.pm = pm_sleep_ptr(&max517_pm_ops),
},
.probe = max517_probe,
.id_table = max517_id,
};
module_i2c_driver(max517_driver);
MODULE_AUTHOR("Roland Stigge <[email protected]>");
MODULE_DESCRIPTION("MAX517/518/519/520/521 8-bit DAC");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/dac/max517.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Support for Microchip MCP4728
*
* Copyright (C) 2023 Andrea Collamati <[email protected]>
*
* Based on mcp4725 by Peter Meerwald <[email protected]>
*
* Driver for the Microchip I2C 12-bit digital-to-analog quad channels
* converter (DAC).
*
* (7-bit I2C slave address 0x60, the three LSBs can be configured in
* hardware)
*/
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
#define MCP4728_RESOLUTION 12
#define MCP4728_N_CHANNELS 4
#define MCP4728_CMD_MASK GENMASK(7, 3)
#define MCP4728_CHSEL_MASK GENMASK(2, 1)
#define MCP4728_UDAC_MASK BIT(0)
#define MCP4728_VREF_MASK BIT(7)
#define MCP4728_PDMODE_MASK GENMASK(6, 5)
#define MCP4728_GAIN_MASK BIT(4)
#define MCP4728_DAC_H_MASK GENMASK(3, 0)
#define MCP4728_DAC_L_MASK GENMASK(7, 0)
#define MCP4728_RDY_MASK BIT(7)
#define MCP4728_MW_CMD 0x08 /* Multiwrite Command */
#define MCP4728_SW_CMD 0x0A /* Sequential Write Command with EEPROM */
#define MCP4728_READ_RESPONSE_LEN (MCP4728_N_CHANNELS * 3 * 2)
#define MCP4728_WRITE_EEPROM_LEN (1 + MCP4728_N_CHANNELS * 2)
enum vref_mode {
MCP4728_VREF_EXTERNAL_VDD = 0,
MCP4728_VREF_INTERNAL_2048mV = 1,
};
enum gain_mode {
MCP4728_GAIN_X1 = 0,
MCP4728_GAIN_X2 = 1,
};
enum iio_powerdown_mode {
MCP4728_IIO_1K,
MCP4728_IIO_100K,
MCP4728_IIO_500K,
};
struct mcp4728_channel_data {
enum vref_mode ref_mode;
enum iio_powerdown_mode pd_mode;
enum gain_mode g_mode;
u16 dac_value;
};
/* MCP4728 Full Scale Ranges
* the device available ranges are
* - VREF = VDD FSR = from 0.0V to VDD
* - VREF = Internal Gain = 1 FSR = from 0.0V to VREF
* - VREF = Internal Gain = 2 FSR = from 0.0V to 2*VREF
*/
enum mcp4728_scale {
MCP4728_SCALE_VDD,
MCP4728_SCALE_VINT_NO_GAIN,
MCP4728_SCALE_VINT_GAIN_X2,
MCP4728_N_SCALES
};
struct mcp4728_data {
struct i2c_client *client;
struct regulator *vdd_reg;
bool powerdown;
int scales_avail[MCP4728_N_SCALES * 2];
struct mcp4728_channel_data chdata[MCP4728_N_CHANNELS];
};
#define MCP4728_CHAN(chan) { \
.type = IIO_VOLTAGE, \
.output = 1, \
.indexed = 1, \
.channel = chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
.ext_info = mcp4728_ext_info, \
}
static int mcp4728_suspend(struct device *dev);
static int mcp4728_resume(struct device *dev);
static ssize_t mcp4728_store_eeprom(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct mcp4728_data *data = iio_priv(indio_dev);
u8 outbuf[MCP4728_WRITE_EEPROM_LEN];
int tries = 20;
u8 inbuf[3];
bool state;
int ret;
unsigned int i;
ret = kstrtobool(buf, &state);
if (ret < 0)
return ret;
if (!state)
return 0;
outbuf[0] = FIELD_PREP(MCP4728_CMD_MASK, MCP4728_SW_CMD);
for (i = 0; i < MCP4728_N_CHANNELS; i++) {
struct mcp4728_channel_data *ch = &data->chdata[i];
int offset = 1 + i * 2;
outbuf[offset] = FIELD_PREP(MCP4728_VREF_MASK, ch->ref_mode);
if (data->powerdown) {
u8 mcp4728_pd_mode = ch->pd_mode + 1;
outbuf[offset] |= FIELD_PREP(MCP4728_PDMODE_MASK,
mcp4728_pd_mode);
}
outbuf[offset] |= FIELD_PREP(MCP4728_GAIN_MASK, ch->g_mode);
outbuf[offset] |=
FIELD_PREP(MCP4728_DAC_H_MASK, ch->dac_value >> 8);
outbuf[offset + 1] =
FIELD_PREP(MCP4728_DAC_L_MASK, ch->dac_value);
}
ret = i2c_master_send(data->client, outbuf, MCP4728_WRITE_EEPROM_LEN);
if (ret < 0)
return ret;
else if (ret != MCP4728_WRITE_EEPROM_LEN)
return -EIO;
/* wait RDY signal for write complete, takes up to 50ms */
while (tries--) {
msleep(20);
ret = i2c_master_recv(data->client, inbuf, 3);
if (ret < 0)
return ret;
else if (ret != 3)
return -EIO;
if (FIELD_GET(MCP4728_RDY_MASK, inbuf[0]))
break;
}
if (tries < 0) {
dev_err(&data->client->dev, "%s failed, incomplete\n",
__func__);
return -EIO;
}
return len;
}
static IIO_DEVICE_ATTR(store_eeprom, 0200, NULL, mcp4728_store_eeprom, 0);
static struct attribute *mcp4728_attributes[] = {
&iio_dev_attr_store_eeprom.dev_attr.attr,
NULL,
};
static const struct attribute_group mcp4728_attribute_group = {
.attrs = mcp4728_attributes,
};
static int mcp4728_program_channel_cfg(int channel, struct iio_dev *indio_dev)
{
struct mcp4728_data *data = iio_priv(indio_dev);
struct mcp4728_channel_data *ch = &data->chdata[channel];
u8 outbuf[3];
int ret;
outbuf[0] = FIELD_PREP(MCP4728_CMD_MASK, MCP4728_MW_CMD);
outbuf[0] |= FIELD_PREP(MCP4728_CHSEL_MASK, channel);
outbuf[0] |= FIELD_PREP(MCP4728_UDAC_MASK, 0);
outbuf[1] = FIELD_PREP(MCP4728_VREF_MASK, ch->ref_mode);
if (data->powerdown)
outbuf[1] |= FIELD_PREP(MCP4728_PDMODE_MASK, ch->pd_mode + 1);
outbuf[1] |= FIELD_PREP(MCP4728_GAIN_MASK, ch->g_mode);
outbuf[1] |= FIELD_PREP(MCP4728_DAC_H_MASK, ch->dac_value >> 8);
outbuf[2] = FIELD_PREP(MCP4728_DAC_L_MASK, ch->dac_value);
ret = i2c_master_send(data->client, outbuf, 3);
if (ret < 0)
return ret;
else if (ret != 3)
return -EIO;
return 0;
}
static const char *const mcp4728_powerdown_modes[] = { "1kohm_to_gnd",
"100kohm_to_gnd",
"500kohm_to_gnd" };
static int mcp4728_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct mcp4728_data *data = iio_priv(indio_dev);
return data->chdata[chan->channel].pd_mode;
}
static int mcp4728_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int mode)
{
struct mcp4728_data *data = iio_priv(indio_dev);
data->chdata[chan->channel].pd_mode = mode;
return 0;
}
static ssize_t mcp4728_read_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct mcp4728_data *data = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", data->powerdown);
}
static ssize_t mcp4728_write_powerdown(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct mcp4728_data *data = iio_priv(indio_dev);
bool state;
int ret;
ret = kstrtobool(buf, &state);
if (ret)
return ret;
if (state)
ret = mcp4728_suspend(&data->client->dev);
else
ret = mcp4728_resume(&data->client->dev);
if (ret < 0)
return ret;
return len;
}
static const struct iio_enum mcp4728_powerdown_mode_enum = {
.items = mcp4728_powerdown_modes,
.num_items = ARRAY_SIZE(mcp4728_powerdown_modes),
.get = mcp4728_get_powerdown_mode,
.set = mcp4728_set_powerdown_mode,
};
static const struct iio_chan_spec_ext_info mcp4728_ext_info[] = {
{
.name = "powerdown",
.read = mcp4728_read_powerdown,
.write = mcp4728_write_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SEPARATE, &mcp4728_powerdown_mode_enum),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE,
&mcp4728_powerdown_mode_enum),
{},
};
static const struct iio_chan_spec mcp4728_channels[MCP4728_N_CHANNELS] = {
MCP4728_CHAN(0),
MCP4728_CHAN(1),
MCP4728_CHAN(2),
MCP4728_CHAN(3),
};
static void mcp4728_get_scale_avail(enum mcp4728_scale scale,
struct mcp4728_data *data, int *val,
int *val2)
{
*val = data->scales_avail[scale * 2];
*val2 = data->scales_avail[scale * 2 + 1];
}
static void mcp4728_get_scale(int channel, struct mcp4728_data *data, int *val,
int *val2)
{
int ref_mode = data->chdata[channel].ref_mode;
int g_mode = data->chdata[channel].g_mode;
if (ref_mode == MCP4728_VREF_EXTERNAL_VDD) {
mcp4728_get_scale_avail(MCP4728_SCALE_VDD, data, val, val2);
} else {
if (g_mode == MCP4728_GAIN_X1) {
mcp4728_get_scale_avail(MCP4728_SCALE_VINT_NO_GAIN,
data, val, val2);
} else {
mcp4728_get_scale_avail(MCP4728_SCALE_VINT_GAIN_X2,
data, val, val2);
}
}
}
static int mcp4728_find_matching_scale(struct mcp4728_data *data, int val,
int val2)
{
for (int i = 0; i < MCP4728_N_SCALES; i++) {
if (data->scales_avail[i * 2] == val &&
data->scales_avail[i * 2 + 1] == val2)
return i;
}
return -EINVAL;
}
static int mcp4728_set_scale(int channel, struct mcp4728_data *data, int val,
int val2)
{
int scale = mcp4728_find_matching_scale(data, val, val2);
if (scale < 0)
return scale;
switch (scale) {
case MCP4728_SCALE_VDD:
data->chdata[channel].ref_mode = MCP4728_VREF_EXTERNAL_VDD;
return 0;
case MCP4728_SCALE_VINT_NO_GAIN:
data->chdata[channel].ref_mode = MCP4728_VREF_INTERNAL_2048mV;
data->chdata[channel].g_mode = MCP4728_GAIN_X1;
return 0;
case MCP4728_SCALE_VINT_GAIN_X2:
data->chdata[channel].ref_mode = MCP4728_VREF_INTERNAL_2048mV;
data->chdata[channel].g_mode = MCP4728_GAIN_X2;
return 0;
default:
return -EINVAL;
}
}
static int mcp4728_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct mcp4728_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
*val = data->chdata[chan->channel].dac_value;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
mcp4728_get_scale(chan->channel, data, val, val2);
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
}
static int mcp4728_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct mcp4728_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val < 0 || val > GENMASK(MCP4728_RESOLUTION - 1, 0))
return -EINVAL;
data->chdata[chan->channel].dac_value = val;
return mcp4728_program_channel_cfg(chan->channel, indio_dev);
case IIO_CHAN_INFO_SCALE:
ret = mcp4728_set_scale(chan->channel, data, val, val2);
if (ret)
return ret;
return mcp4728_program_channel_cfg(chan->channel, indio_dev);
default:
return -EINVAL;
}
}
static void mcp4728_init_scale_avail(enum mcp4728_scale scale, int vref_mv,
struct mcp4728_data *data)
{
s64 tmp;
int value_micro;
int value_int;
tmp = (s64)vref_mv * 1000000LL >> MCP4728_RESOLUTION;
value_int = div_s64_rem(tmp, 1000000LL, &value_micro);
data->scales_avail[scale * 2] = value_int;
data->scales_avail[scale * 2 + 1] = value_micro;
}
static int mcp4728_init_scales_avail(struct mcp4728_data *data)
{
int ret;
ret = regulator_get_voltage(data->vdd_reg);
if (ret < 0)
return ret;
mcp4728_init_scale_avail(MCP4728_SCALE_VDD, ret / 1000, data);
mcp4728_init_scale_avail(MCP4728_SCALE_VINT_NO_GAIN, 2048, data);
mcp4728_init_scale_avail(MCP4728_SCALE_VINT_GAIN_X2, 4096, data);
return 0;
}
static int mcp4728_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long info)
{
struct mcp4728_data *data = iio_priv(indio_dev);
switch (info) {
case IIO_CHAN_INFO_SCALE:
*type = IIO_VAL_INT_PLUS_MICRO;
switch (chan->type) {
case IIO_VOLTAGE:
*vals = data->scales_avail;
*length = MCP4728_N_SCALES * 2;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static const struct iio_info mcp4728_info = {
.read_raw = mcp4728_read_raw,
.write_raw = mcp4728_write_raw,
.read_avail = &mcp4728_read_avail,
.attrs = &mcp4728_attribute_group,
};
static int mcp4728_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct mcp4728_data *data = iio_priv(indio_dev);
unsigned int i;
data->powerdown = true;
for (i = 0; i < MCP4728_N_CHANNELS; i++) {
int err = mcp4728_program_channel_cfg(i, indio_dev);
if (err)
return err;
}
return 0;
}
static int mcp4728_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct mcp4728_data *data = iio_priv(indio_dev);
int err = 0;
unsigned int i;
data->powerdown = false;
for (i = 0; i < MCP4728_N_CHANNELS; i++) {
int ret = mcp4728_program_channel_cfg(i, indio_dev);
if (ret)
err = ret;
}
return err;
}
static DEFINE_SIMPLE_DEV_PM_OPS(mcp4728_pm_ops, mcp4728_suspend,
mcp4728_resume);
static int mcp4728_init_channels_data(struct mcp4728_data *data)
{
u8 inbuf[MCP4728_READ_RESPONSE_LEN];
int ret;
unsigned int i;
ret = i2c_master_recv(data->client, inbuf, MCP4728_READ_RESPONSE_LEN);
if (ret < 0) {
return dev_err_probe(&data->client->dev, ret,
"failed to read mcp4728 conf.\n");
} else if (ret != MCP4728_READ_RESPONSE_LEN) {
return dev_err_probe(&data->client->dev, -EIO,
"failed to read mcp4728 conf. Wrong Response Len ret=%d\n",
ret);
}
for (i = 0; i < MCP4728_N_CHANNELS; i++) {
struct mcp4728_channel_data *ch = &data->chdata[i];
u8 r2 = inbuf[i * 6 + 1];
u8 r3 = inbuf[i * 6 + 2];
ch->dac_value = FIELD_GET(MCP4728_DAC_H_MASK, r2) << 8 |
FIELD_GET(MCP4728_DAC_L_MASK, r3);
ch->ref_mode = FIELD_GET(MCP4728_VREF_MASK, r2);
ch->pd_mode = FIELD_GET(MCP4728_PDMODE_MASK, r2);
ch->g_mode = FIELD_GET(MCP4728_GAIN_MASK, r2);
}
return 0;
}
static void mcp4728_reg_disable(void *reg)
{
regulator_disable(reg);
}
static int mcp4728_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct mcp4728_data *data;
struct iio_dev *indio_dev;
int err;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
if (IS_ERR(data->vdd_reg))
return PTR_ERR(data->vdd_reg);
err = regulator_enable(data->vdd_reg);
if (err)
return err;
err = devm_add_action_or_reset(&client->dev, mcp4728_reg_disable,
data->vdd_reg);
if (err)
return err;
/*
* MCP4728 has internal EEPROM that save each channel boot
* configuration. It means that device configuration is unknown to the
* driver at kernel boot. mcp4728_init_channels_data() reads back DAC
* settings and stores them in data structure.
*/
err = mcp4728_init_channels_data(data);
if (err) {
return dev_err_probe(&client->dev, err,
"failed to read mcp4728 current configuration\n");
}
err = mcp4728_init_scales_avail(data);
if (err) {
return dev_err_probe(&client->dev, err,
"failed to init scales\n");
}
indio_dev->name = id->name;
indio_dev->info = &mcp4728_info;
indio_dev->channels = mcp4728_channels;
indio_dev->num_channels = MCP4728_N_CHANNELS;
indio_dev->modes = INDIO_DIRECT_MODE;
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id mcp4728_id[] = {
{ "mcp4728", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, mcp4728_id);
static const struct of_device_id mcp4728_of_match[] = {
{ .compatible = "microchip,mcp4728" },
{}
};
MODULE_DEVICE_TABLE(of, mcp4728_of_match);
static struct i2c_driver mcp4728_driver = {
.driver = {
.name = "mcp4728",
.of_match_table = mcp4728_of_match,
.pm = pm_sleep_ptr(&mcp4728_pm_ops),
},
.probe = mcp4728_probe,
.id_table = mcp4728_id,
};
module_i2c_driver(mcp4728_driver);
MODULE_AUTHOR("Andrea Collamati <[email protected]>");
MODULE_DESCRIPTION("MCP4728 12-bit DAC");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/dac/mcp4728.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
*
* Copyright 2012 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/delay.h>
#include <linux/property.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define AD5755_NUM_CHANNELS 4
#define AD5755_ADDR(x) ((x) << 16)
#define AD5755_WRITE_REG_DATA(chan) (chan)
#define AD5755_WRITE_REG_GAIN(chan) (0x08 | (chan))
#define AD5755_WRITE_REG_OFFSET(chan) (0x10 | (chan))
#define AD5755_WRITE_REG_CTRL(chan) (0x1c | (chan))
#define AD5755_READ_REG_DATA(chan) (chan)
#define AD5755_READ_REG_CTRL(chan) (0x4 | (chan))
#define AD5755_READ_REG_GAIN(chan) (0x8 | (chan))
#define AD5755_READ_REG_OFFSET(chan) (0xc | (chan))
#define AD5755_READ_REG_CLEAR(chan) (0x10 | (chan))
#define AD5755_READ_REG_SLEW(chan) (0x14 | (chan))
#define AD5755_READ_REG_STATUS 0x18
#define AD5755_READ_REG_MAIN 0x19
#define AD5755_READ_REG_DC_DC 0x1a
#define AD5755_CTRL_REG_SLEW 0x0
#define AD5755_CTRL_REG_MAIN 0x1
#define AD5755_CTRL_REG_DAC 0x2
#define AD5755_CTRL_REG_DC_DC 0x3
#define AD5755_CTRL_REG_SW 0x4
#define AD5755_READ_FLAG 0x800000
#define AD5755_NOOP 0x1CE000
#define AD5755_DAC_INT_EN BIT(8)
#define AD5755_DAC_CLR_EN BIT(7)
#define AD5755_DAC_OUT_EN BIT(6)
#define AD5755_DAC_INT_CURRENT_SENSE_RESISTOR BIT(5)
#define AD5755_DAC_DC_DC_EN BIT(4)
#define AD5755_DAC_VOLTAGE_OVERRANGE_EN BIT(3)
#define AD5755_DC_DC_MAXV 0
#define AD5755_DC_DC_FREQ_SHIFT 2
#define AD5755_DC_DC_PHASE_SHIFT 4
#define AD5755_EXT_DC_DC_COMP_RES BIT(6)
#define AD5755_SLEW_STEP_SIZE_SHIFT 0
#define AD5755_SLEW_RATE_SHIFT 3
#define AD5755_SLEW_ENABLE BIT(12)
enum ad5755_mode {
AD5755_MODE_VOLTAGE_0V_5V = 0,
AD5755_MODE_VOLTAGE_0V_10V = 1,
AD5755_MODE_VOLTAGE_PLUSMINUS_5V = 2,
AD5755_MODE_VOLTAGE_PLUSMINUS_10V = 3,
AD5755_MODE_CURRENT_4mA_20mA = 4,
AD5755_MODE_CURRENT_0mA_20mA = 5,
AD5755_MODE_CURRENT_0mA_24mA = 6,
};
enum ad5755_dc_dc_phase {
AD5755_DC_DC_PHASE_ALL_SAME_EDGE = 0,
AD5755_DC_DC_PHASE_A_B_SAME_EDGE_C_D_OPP_EDGE = 1,
AD5755_DC_DC_PHASE_A_C_SAME_EDGE_B_D_OPP_EDGE = 2,
AD5755_DC_DC_PHASE_90_DEGREE = 3,
};
enum ad5755_dc_dc_freq {
AD5755_DC_DC_FREQ_250kHZ = 0,
AD5755_DC_DC_FREQ_410kHZ = 1,
AD5755_DC_DC_FREQ_650kHZ = 2,
};
enum ad5755_dc_dc_maxv {
AD5755_DC_DC_MAXV_23V = 0,
AD5755_DC_DC_MAXV_24V5 = 1,
AD5755_DC_DC_MAXV_27V = 2,
AD5755_DC_DC_MAXV_29V5 = 3,
};
enum ad5755_slew_rate {
AD5755_SLEW_RATE_64k = 0,
AD5755_SLEW_RATE_32k = 1,
AD5755_SLEW_RATE_16k = 2,
AD5755_SLEW_RATE_8k = 3,
AD5755_SLEW_RATE_4k = 4,
AD5755_SLEW_RATE_2k = 5,
AD5755_SLEW_RATE_1k = 6,
AD5755_SLEW_RATE_500 = 7,
AD5755_SLEW_RATE_250 = 8,
AD5755_SLEW_RATE_125 = 9,
AD5755_SLEW_RATE_64 = 10,
AD5755_SLEW_RATE_32 = 11,
AD5755_SLEW_RATE_16 = 12,
AD5755_SLEW_RATE_8 = 13,
AD5755_SLEW_RATE_4 = 14,
AD5755_SLEW_RATE_0_5 = 15,
};
enum ad5755_slew_step_size {
AD5755_SLEW_STEP_SIZE_1 = 0,
AD5755_SLEW_STEP_SIZE_2 = 1,
AD5755_SLEW_STEP_SIZE_4 = 2,
AD5755_SLEW_STEP_SIZE_8 = 3,
AD5755_SLEW_STEP_SIZE_16 = 4,
AD5755_SLEW_STEP_SIZE_32 = 5,
AD5755_SLEW_STEP_SIZE_64 = 6,
AD5755_SLEW_STEP_SIZE_128 = 7,
AD5755_SLEW_STEP_SIZE_256 = 8,
};
/**
* struct ad5755_platform_data - AD5755 DAC driver platform data
* @ext_dc_dc_compenstation_resistor: Whether an external DC-DC converter
* compensation register is used.
* @dc_dc_phase: DC-DC converter phase.
* @dc_dc_freq: DC-DC converter frequency.
* @dc_dc_maxv: DC-DC maximum allowed boost voltage.
* @dac: Per DAC instance parameters.
* @dac.mode: The mode to be used for the DAC output.
* @dac.ext_current_sense_resistor: Whether an external current sense resistor
* is used.
* @dac.enable_voltage_overrange: Whether to enable 20% voltage output overrange.
* @dac.slew.enable: Whether to enable digital slew.
* @dac.slew.rate: Slew rate of the digital slew.
* @dac.slew.step_size: Slew step size of the digital slew.
**/
struct ad5755_platform_data {
bool ext_dc_dc_compenstation_resistor;
enum ad5755_dc_dc_phase dc_dc_phase;
enum ad5755_dc_dc_freq dc_dc_freq;
enum ad5755_dc_dc_maxv dc_dc_maxv;
struct {
enum ad5755_mode mode;
bool ext_current_sense_resistor;
bool enable_voltage_overrange;
struct {
bool enable;
enum ad5755_slew_rate rate;
enum ad5755_slew_step_size step_size;
} slew;
} dac[4];
};
/**
* struct ad5755_chip_info - chip specific information
* @channel_template: channel specification
* @calib_shift: shift for the calibration data registers
* @has_voltage_out: whether the chip has voltage outputs
*/
struct ad5755_chip_info {
const struct iio_chan_spec channel_template;
unsigned int calib_shift;
bool has_voltage_out;
};
/**
* struct ad5755_state - driver instance specific data
* @spi: spi device the driver is attached to
* @chip_info: chip model specific constants, available modes etc
* @pwr_down: bitmask which contains hether a channel is powered down or not
* @ctrl: software shadow of the channel ctrl registers
* @channels: iio channel spec for the device
* @lock: lock to protect the data buffer during SPI ops
* @data: spi transfer buffers
*/
struct ad5755_state {
struct spi_device *spi;
const struct ad5755_chip_info *chip_info;
unsigned int pwr_down;
unsigned int ctrl[AD5755_NUM_CHANNELS];
struct iio_chan_spec channels[AD5755_NUM_CHANNELS];
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
union {
__be32 d32;
u8 d8[4];
} data[2] __aligned(IIO_DMA_MINALIGN);
};
enum ad5755_type {
ID_AD5755,
ID_AD5757,
ID_AD5735,
ID_AD5737,
};
static const int ad5755_dcdc_freq_table[][2] = {
{ 250000, AD5755_DC_DC_FREQ_250kHZ },
{ 410000, AD5755_DC_DC_FREQ_410kHZ },
{ 650000, AD5755_DC_DC_FREQ_650kHZ }
};
static const int ad5755_dcdc_maxv_table[][2] = {
{ 23000000, AD5755_DC_DC_MAXV_23V },
{ 24500000, AD5755_DC_DC_MAXV_24V5 },
{ 27000000, AD5755_DC_DC_MAXV_27V },
{ 29500000, AD5755_DC_DC_MAXV_29V5 },
};
static const int ad5755_slew_rate_table[][2] = {
{ 64000, AD5755_SLEW_RATE_64k },
{ 32000, AD5755_SLEW_RATE_32k },
{ 16000, AD5755_SLEW_RATE_16k },
{ 8000, AD5755_SLEW_RATE_8k },
{ 4000, AD5755_SLEW_RATE_4k },
{ 2000, AD5755_SLEW_RATE_2k },
{ 1000, AD5755_SLEW_RATE_1k },
{ 500, AD5755_SLEW_RATE_500 },
{ 250, AD5755_SLEW_RATE_250 },
{ 125, AD5755_SLEW_RATE_125 },
{ 64, AD5755_SLEW_RATE_64 },
{ 32, AD5755_SLEW_RATE_32 },
{ 16, AD5755_SLEW_RATE_16 },
{ 8, AD5755_SLEW_RATE_8 },
{ 4, AD5755_SLEW_RATE_4 },
{ 0, AD5755_SLEW_RATE_0_5 },
};
static const int ad5755_slew_step_table[][2] = {
{ 256, AD5755_SLEW_STEP_SIZE_256 },
{ 128, AD5755_SLEW_STEP_SIZE_128 },
{ 64, AD5755_SLEW_STEP_SIZE_64 },
{ 32, AD5755_SLEW_STEP_SIZE_32 },
{ 16, AD5755_SLEW_STEP_SIZE_16 },
{ 4, AD5755_SLEW_STEP_SIZE_4 },
{ 2, AD5755_SLEW_STEP_SIZE_2 },
{ 1, AD5755_SLEW_STEP_SIZE_1 },
};
static int ad5755_write_unlocked(struct iio_dev *indio_dev,
unsigned int reg, unsigned int val)
{
struct ad5755_state *st = iio_priv(indio_dev);
st->data[0].d32 = cpu_to_be32((reg << 16) | val);
return spi_write(st->spi, &st->data[0].d8[1], 3);
}
static int ad5755_write_ctrl_unlocked(struct iio_dev *indio_dev,
unsigned int channel, unsigned int reg, unsigned int val)
{
return ad5755_write_unlocked(indio_dev,
AD5755_WRITE_REG_CTRL(channel), (reg << 13) | val);
}
static int ad5755_write(struct iio_dev *indio_dev, unsigned int reg,
unsigned int val)
{
struct ad5755_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
ret = ad5755_write_unlocked(indio_dev, reg, val);
mutex_unlock(&st->lock);
return ret;
}
static int ad5755_write_ctrl(struct iio_dev *indio_dev, unsigned int channel,
unsigned int reg, unsigned int val)
{
struct ad5755_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
ret = ad5755_write_ctrl_unlocked(indio_dev, channel, reg, val);
mutex_unlock(&st->lock);
return ret;
}
static int ad5755_read(struct iio_dev *indio_dev, unsigned int addr)
{
struct ad5755_state *st = iio_priv(indio_dev);
int ret;
struct spi_transfer t[] = {
{
.tx_buf = &st->data[0].d8[1],
.len = 3,
.cs_change = 1,
}, {
.tx_buf = &st->data[1].d8[1],
.rx_buf = &st->data[1].d8[1],
.len = 3,
},
};
mutex_lock(&st->lock);
st->data[0].d32 = cpu_to_be32(AD5755_READ_FLAG | (addr << 16));
st->data[1].d32 = cpu_to_be32(AD5755_NOOP);
ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
if (ret >= 0)
ret = be32_to_cpu(st->data[1].d32) & 0xffff;
mutex_unlock(&st->lock);
return ret;
}
static int ad5755_update_dac_ctrl(struct iio_dev *indio_dev,
unsigned int channel, unsigned int set, unsigned int clr)
{
struct ad5755_state *st = iio_priv(indio_dev);
int ret;
st->ctrl[channel] |= set;
st->ctrl[channel] &= ~clr;
ret = ad5755_write_ctrl_unlocked(indio_dev, channel,
AD5755_CTRL_REG_DAC, st->ctrl[channel]);
return ret;
}
static int ad5755_set_channel_pwr_down(struct iio_dev *indio_dev,
unsigned int channel, bool pwr_down)
{
struct ad5755_state *st = iio_priv(indio_dev);
unsigned int mask = BIT(channel);
mutex_lock(&st->lock);
if ((bool)(st->pwr_down & mask) == pwr_down)
goto out_unlock;
if (!pwr_down) {
st->pwr_down &= ~mask;
ad5755_update_dac_ctrl(indio_dev, channel,
AD5755_DAC_INT_EN | AD5755_DAC_DC_DC_EN, 0);
udelay(200);
ad5755_update_dac_ctrl(indio_dev, channel,
AD5755_DAC_OUT_EN, 0);
} else {
st->pwr_down |= mask;
ad5755_update_dac_ctrl(indio_dev, channel,
0, AD5755_DAC_INT_EN | AD5755_DAC_OUT_EN |
AD5755_DAC_DC_DC_EN);
}
out_unlock:
mutex_unlock(&st->lock);
return 0;
}
static const int ad5755_min_max_table[][2] = {
[AD5755_MODE_VOLTAGE_0V_5V] = { 0, 5000 },
[AD5755_MODE_VOLTAGE_0V_10V] = { 0, 10000 },
[AD5755_MODE_VOLTAGE_PLUSMINUS_5V] = { -5000, 5000 },
[AD5755_MODE_VOLTAGE_PLUSMINUS_10V] = { -10000, 10000 },
[AD5755_MODE_CURRENT_4mA_20mA] = { 4, 20 },
[AD5755_MODE_CURRENT_0mA_20mA] = { 0, 20 },
[AD5755_MODE_CURRENT_0mA_24mA] = { 0, 24 },
};
static void ad5755_get_min_max(struct ad5755_state *st,
struct iio_chan_spec const *chan, int *min, int *max)
{
enum ad5755_mode mode = st->ctrl[chan->channel] & 7;
*min = ad5755_min_max_table[mode][0];
*max = ad5755_min_max_table[mode][1];
}
static inline int ad5755_get_offset(struct ad5755_state *st,
struct iio_chan_spec const *chan)
{
int min, max;
ad5755_get_min_max(st, chan, &min, &max);
return (min * (1 << chan->scan_type.realbits)) / (max - min);
}
static int ad5755_chan_reg_info(struct ad5755_state *st,
struct iio_chan_spec const *chan, long info, bool write,
unsigned int *reg, unsigned int *shift, unsigned int *offset)
{
switch (info) {
case IIO_CHAN_INFO_RAW:
if (write)
*reg = AD5755_WRITE_REG_DATA(chan->address);
else
*reg = AD5755_READ_REG_DATA(chan->address);
*shift = chan->scan_type.shift;
*offset = 0;
break;
case IIO_CHAN_INFO_CALIBBIAS:
if (write)
*reg = AD5755_WRITE_REG_OFFSET(chan->address);
else
*reg = AD5755_READ_REG_OFFSET(chan->address);
*shift = st->chip_info->calib_shift;
*offset = 32768;
break;
case IIO_CHAN_INFO_CALIBSCALE:
if (write)
*reg = AD5755_WRITE_REG_GAIN(chan->address);
else
*reg = AD5755_READ_REG_GAIN(chan->address);
*shift = st->chip_info->calib_shift;
*offset = 0;
break;
default:
return -EINVAL;
}
return 0;
}
static int ad5755_read_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, int *val, int *val2, long info)
{
struct ad5755_state *st = iio_priv(indio_dev);
unsigned int reg, shift, offset;
int min, max;
int ret;
switch (info) {
case IIO_CHAN_INFO_SCALE:
ad5755_get_min_max(st, chan, &min, &max);
*val = max - min;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_OFFSET:
*val = ad5755_get_offset(st, chan);
return IIO_VAL_INT;
default:
ret = ad5755_chan_reg_info(st, chan, info, false,
®, &shift, &offset);
if (ret)
return ret;
ret = ad5755_read(indio_dev, reg);
if (ret < 0)
return ret;
*val = (ret - offset) >> shift;
return IIO_VAL_INT;
}
return -EINVAL;
}
static int ad5755_write_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, int val, int val2, long info)
{
struct ad5755_state *st = iio_priv(indio_dev);
unsigned int shift, reg, offset;
int ret;
ret = ad5755_chan_reg_info(st, chan, info, true,
®, &shift, &offset);
if (ret)
return ret;
val <<= shift;
val += offset;
if (val < 0 || val > 0xffff)
return -EINVAL;
return ad5755_write(indio_dev, reg, val);
}
static ssize_t ad5755_read_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
const struct iio_chan_spec *chan, char *buf)
{
struct ad5755_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n",
(bool)(st->pwr_down & (1 << chan->channel)));
}
static ssize_t ad5755_write_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
struct iio_chan_spec const *chan, const char *buf, size_t len)
{
bool pwr_down;
int ret;
ret = kstrtobool(buf, &pwr_down);
if (ret)
return ret;
ret = ad5755_set_channel_pwr_down(indio_dev, chan->channel, pwr_down);
return ret ? ret : len;
}
static const struct iio_info ad5755_info = {
.read_raw = ad5755_read_raw,
.write_raw = ad5755_write_raw,
};
static const struct iio_chan_spec_ext_info ad5755_ext_info[] = {
{
.name = "powerdown",
.read = ad5755_read_powerdown,
.write = ad5755_write_powerdown,
.shared = IIO_SEPARATE,
},
{ },
};
#define AD5755_CHANNEL(_bits) { \
.indexed = 1, \
.output = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_CALIBSCALE) | \
BIT(IIO_CHAN_INFO_CALIBBIAS), \
.scan_type = { \
.sign = 'u', \
.realbits = (_bits), \
.storagebits = 16, \
.shift = 16 - (_bits), \
}, \
.ext_info = ad5755_ext_info, \
}
static const struct ad5755_chip_info ad5755_chip_info_tbl[] = {
[ID_AD5735] = {
.channel_template = AD5755_CHANNEL(14),
.has_voltage_out = true,
.calib_shift = 4,
},
[ID_AD5737] = {
.channel_template = AD5755_CHANNEL(14),
.has_voltage_out = false,
.calib_shift = 4,
},
[ID_AD5755] = {
.channel_template = AD5755_CHANNEL(16),
.has_voltage_out = true,
.calib_shift = 0,
},
[ID_AD5757] = {
.channel_template = AD5755_CHANNEL(16),
.has_voltage_out = false,
.calib_shift = 0,
},
};
static bool ad5755_is_valid_mode(struct ad5755_state *st, enum ad5755_mode mode)
{
switch (mode) {
case AD5755_MODE_VOLTAGE_0V_5V:
case AD5755_MODE_VOLTAGE_0V_10V:
case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
return st->chip_info->has_voltage_out;
case AD5755_MODE_CURRENT_4mA_20mA:
case AD5755_MODE_CURRENT_0mA_20mA:
case AD5755_MODE_CURRENT_0mA_24mA:
return true;
default:
return false;
}
}
static int ad5755_setup_pdata(struct iio_dev *indio_dev,
const struct ad5755_platform_data *pdata)
{
struct ad5755_state *st = iio_priv(indio_dev);
unsigned int val;
unsigned int i;
int ret;
if (pdata->dc_dc_phase > AD5755_DC_DC_PHASE_90_DEGREE ||
pdata->dc_dc_freq > AD5755_DC_DC_FREQ_650kHZ ||
pdata->dc_dc_maxv > AD5755_DC_DC_MAXV_29V5)
return -EINVAL;
val = pdata->dc_dc_maxv << AD5755_DC_DC_MAXV;
val |= pdata->dc_dc_freq << AD5755_DC_DC_FREQ_SHIFT;
val |= pdata->dc_dc_phase << AD5755_DC_DC_PHASE_SHIFT;
if (pdata->ext_dc_dc_compenstation_resistor)
val |= AD5755_EXT_DC_DC_COMP_RES;
ret = ad5755_write_ctrl(indio_dev, 0, AD5755_CTRL_REG_DC_DC, val);
if (ret < 0)
return ret;
for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
val = pdata->dac[i].slew.step_size <<
AD5755_SLEW_STEP_SIZE_SHIFT;
val |= pdata->dac[i].slew.rate <<
AD5755_SLEW_RATE_SHIFT;
if (pdata->dac[i].slew.enable)
val |= AD5755_SLEW_ENABLE;
ret = ad5755_write_ctrl(indio_dev, i,
AD5755_CTRL_REG_SLEW, val);
if (ret < 0)
return ret;
}
for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
if (!ad5755_is_valid_mode(st, pdata->dac[i].mode))
return -EINVAL;
val = 0;
if (!pdata->dac[i].ext_current_sense_resistor)
val |= AD5755_DAC_INT_CURRENT_SENSE_RESISTOR;
if (pdata->dac[i].enable_voltage_overrange)
val |= AD5755_DAC_VOLTAGE_OVERRANGE_EN;
val |= pdata->dac[i].mode;
ret = ad5755_update_dac_ctrl(indio_dev, i, val, 0);
if (ret < 0)
return ret;
}
return 0;
}
static bool ad5755_is_voltage_mode(enum ad5755_mode mode)
{
switch (mode) {
case AD5755_MODE_VOLTAGE_0V_5V:
case AD5755_MODE_VOLTAGE_0V_10V:
case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
return true;
default:
return false;
}
}
static int ad5755_init_channels(struct iio_dev *indio_dev,
const struct ad5755_platform_data *pdata)
{
struct ad5755_state *st = iio_priv(indio_dev);
struct iio_chan_spec *channels = st->channels;
unsigned int i;
for (i = 0; i < AD5755_NUM_CHANNELS; ++i) {
channels[i] = st->chip_info->channel_template;
channels[i].channel = i;
channels[i].address = i;
if (pdata && ad5755_is_voltage_mode(pdata->dac[i].mode))
channels[i].type = IIO_VOLTAGE;
else
channels[i].type = IIO_CURRENT;
}
indio_dev->channels = channels;
return 0;
}
#define AD5755_DEFAULT_DAC_PDATA { \
.mode = AD5755_MODE_CURRENT_4mA_20mA, \
.ext_current_sense_resistor = true, \
.enable_voltage_overrange = false, \
.slew = { \
.enable = false, \
.rate = AD5755_SLEW_RATE_64k, \
.step_size = AD5755_SLEW_STEP_SIZE_1, \
}, \
}
static const struct ad5755_platform_data ad5755_default_pdata = {
.ext_dc_dc_compenstation_resistor = false,
.dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE,
.dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ,
.dc_dc_maxv = AD5755_DC_DC_MAXV_23V,
.dac = {
[0] = AD5755_DEFAULT_DAC_PDATA,
[1] = AD5755_DEFAULT_DAC_PDATA,
[2] = AD5755_DEFAULT_DAC_PDATA,
[3] = AD5755_DEFAULT_DAC_PDATA,
},
};
static struct ad5755_platform_data *ad5755_parse_fw(struct device *dev)
{
struct fwnode_handle *pp;
struct ad5755_platform_data *pdata;
unsigned int tmp;
unsigned int tmparray[3];
int devnr, i;
if (!dev_fwnode(dev))
return NULL;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return NULL;
pdata->ext_dc_dc_compenstation_resistor =
device_property_read_bool(dev, "adi,ext-dc-dc-compenstation-resistor");
pdata->dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE;
device_property_read_u32(dev, "adi,dc-dc-phase", &pdata->dc_dc_phase);
pdata->dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ;
if (!device_property_read_u32(dev, "adi,dc-dc-freq-hz", &tmp)) {
for (i = 0; i < ARRAY_SIZE(ad5755_dcdc_freq_table); i++) {
if (tmp == ad5755_dcdc_freq_table[i][0]) {
pdata->dc_dc_freq = ad5755_dcdc_freq_table[i][1];
break;
}
}
if (i == ARRAY_SIZE(ad5755_dcdc_freq_table))
dev_err(dev,
"adi,dc-dc-freq out of range selecting 410kHz\n");
}
pdata->dc_dc_maxv = AD5755_DC_DC_MAXV_23V;
if (!device_property_read_u32(dev, "adi,dc-dc-max-microvolt", &tmp)) {
for (i = 0; i < ARRAY_SIZE(ad5755_dcdc_maxv_table); i++) {
if (tmp == ad5755_dcdc_maxv_table[i][0]) {
pdata->dc_dc_maxv = ad5755_dcdc_maxv_table[i][1];
break;
}
}
if (i == ARRAY_SIZE(ad5755_dcdc_maxv_table))
dev_err(dev,
"adi,dc-dc-maxv out of range selecting 23V\n");
}
devnr = 0;
device_for_each_child_node(dev, pp) {
if (devnr >= AD5755_NUM_CHANNELS) {
dev_err(dev,
"There are too many channels defined in DT\n");
goto error_out;
}
pdata->dac[devnr].mode = AD5755_MODE_CURRENT_4mA_20mA;
fwnode_property_read_u32(pp, "adi,mode", &pdata->dac[devnr].mode);
pdata->dac[devnr].ext_current_sense_resistor =
fwnode_property_read_bool(pp, "adi,ext-current-sense-resistor");
pdata->dac[devnr].enable_voltage_overrange =
fwnode_property_read_bool(pp, "adi,enable-voltage-overrange");
if (!fwnode_property_read_u32_array(pp, "adi,slew", tmparray, 3)) {
pdata->dac[devnr].slew.enable = tmparray[0];
pdata->dac[devnr].slew.rate = AD5755_SLEW_RATE_64k;
for (i = 0; i < ARRAY_SIZE(ad5755_slew_rate_table); i++) {
if (tmparray[1] == ad5755_slew_rate_table[i][0]) {
pdata->dac[devnr].slew.rate =
ad5755_slew_rate_table[i][1];
break;
}
}
if (i == ARRAY_SIZE(ad5755_slew_rate_table))
dev_err(dev,
"channel %d slew rate out of range selecting 64kHz\n",
devnr);
pdata->dac[devnr].slew.step_size = AD5755_SLEW_STEP_SIZE_1;
for (i = 0; i < ARRAY_SIZE(ad5755_slew_step_table); i++) {
if (tmparray[2] == ad5755_slew_step_table[i][0]) {
pdata->dac[devnr].slew.step_size =
ad5755_slew_step_table[i][1];
break;
}
}
if (i == ARRAY_SIZE(ad5755_slew_step_table))
dev_err(dev,
"channel %d slew step size out of range selecting 1 LSB\n",
devnr);
} else {
pdata->dac[devnr].slew.enable = false;
pdata->dac[devnr].slew.rate = AD5755_SLEW_RATE_64k;
pdata->dac[devnr].slew.step_size =
AD5755_SLEW_STEP_SIZE_1;
}
devnr++;
}
return pdata;
error_out:
fwnode_handle_put(pp);
devm_kfree(dev, pdata);
return NULL;
}
static int ad5755_probe(struct spi_device *spi)
{
enum ad5755_type type = spi_get_device_id(spi)->driver_data;
const struct ad5755_platform_data *pdata;
struct iio_dev *indio_dev;
struct ad5755_state *st;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (indio_dev == NULL) {
dev_err(&spi->dev, "Failed to allocate iio device\n");
return -ENOMEM;
}
st = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
st->chip_info = &ad5755_chip_info_tbl[type];
st->spi = spi;
st->pwr_down = 0xf;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->info = &ad5755_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->num_channels = AD5755_NUM_CHANNELS;
mutex_init(&st->lock);
pdata = ad5755_parse_fw(&spi->dev);
if (!pdata) {
dev_warn(&spi->dev, "no firmware provided parameters? using default\n");
pdata = &ad5755_default_pdata;
}
ret = ad5755_init_channels(indio_dev, pdata);
if (ret)
return ret;
ret = ad5755_setup_pdata(indio_dev, pdata);
if (ret)
return ret;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id ad5755_id[] = {
{ "ad5755", ID_AD5755 },
{ "ad5755-1", ID_AD5755 },
{ "ad5757", ID_AD5757 },
{ "ad5735", ID_AD5735 },
{ "ad5737", ID_AD5737 },
{}
};
MODULE_DEVICE_TABLE(spi, ad5755_id);
static const struct of_device_id ad5755_of_match[] = {
{ .compatible = "adi,ad5755" },
{ .compatible = "adi,ad5755-1" },
{ .compatible = "adi,ad5757" },
{ .compatible = "adi,ad5735" },
{ .compatible = "adi,ad5737" },
{ }
};
MODULE_DEVICE_TABLE(of, ad5755_of_match);
static struct spi_driver ad5755_driver = {
.driver = {
.name = "ad5755",
},
.probe = ad5755_probe,
.id_table = ad5755_id,
};
module_spi_driver(ad5755_driver);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5755/55-1/57/35/37 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5755.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Analog devices AD5360, AD5361, AD5362, AD5363, AD5370, AD5371, AD5373
* multi-channel Digital to Analog Converters driver
*
* Copyright 2011 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define AD5360_CMD(x) ((x) << 22)
#define AD5360_ADDR(x) ((x) << 16)
#define AD5360_READBACK_TYPE(x) ((x) << 13)
#define AD5360_READBACK_ADDR(x) ((x) << 7)
#define AD5360_CHAN_ADDR(chan) ((chan) + 0x8)
#define AD5360_CMD_WRITE_DATA 0x3
#define AD5360_CMD_WRITE_OFFSET 0x2
#define AD5360_CMD_WRITE_GAIN 0x1
#define AD5360_CMD_SPECIAL_FUNCTION 0x0
/* Special function register addresses */
#define AD5360_REG_SF_NOP 0x0
#define AD5360_REG_SF_CTRL 0x1
#define AD5360_REG_SF_OFS(x) (0x2 + (x))
#define AD5360_REG_SF_READBACK 0x5
#define AD5360_SF_CTRL_PWR_DOWN BIT(0)
#define AD5360_READBACK_X1A 0x0
#define AD5360_READBACK_X1B 0x1
#define AD5360_READBACK_OFFSET 0x2
#define AD5360_READBACK_GAIN 0x3
#define AD5360_READBACK_SF 0x4
/**
* struct ad5360_chip_info - chip specific information
* @channel_template: channel specification template
* @num_channels: number of channels
* @channels_per_group: number of channels per group
* @num_vrefs: number of vref supplies for the chip
*/
struct ad5360_chip_info {
struct iio_chan_spec channel_template;
unsigned int num_channels;
unsigned int channels_per_group;
unsigned int num_vrefs;
};
/**
* struct ad5360_state - driver instance specific data
* @spi: spi_device
* @chip_info: chip model specific constants, available modes etc
* @vref_reg: vref supply regulators
* @ctrl: control register cache
* @lock: lock to protect the data buffer during SPI ops
* @data: spi transfer buffers
*/
struct ad5360_state {
struct spi_device *spi;
const struct ad5360_chip_info *chip_info;
struct regulator_bulk_data vref_reg[3];
unsigned int ctrl;
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
union {
__be32 d32;
u8 d8[4];
} data[2] __aligned(IIO_DMA_MINALIGN);
};
enum ad5360_type {
ID_AD5360,
ID_AD5361,
ID_AD5362,
ID_AD5363,
ID_AD5370,
ID_AD5371,
ID_AD5372,
ID_AD5373,
};
#define AD5360_CHANNEL(bits) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_CALIBSCALE) | \
BIT(IIO_CHAN_INFO_CALIBBIAS), \
.scan_type = { \
.sign = 'u', \
.realbits = (bits), \
.storagebits = 16, \
.shift = 16 - (bits), \
}, \
}
static const struct ad5360_chip_info ad5360_chip_info_tbl[] = {
[ID_AD5360] = {
.channel_template = AD5360_CHANNEL(16),
.num_channels = 16,
.channels_per_group = 8,
.num_vrefs = 2,
},
[ID_AD5361] = {
.channel_template = AD5360_CHANNEL(14),
.num_channels = 16,
.channels_per_group = 8,
.num_vrefs = 2,
},
[ID_AD5362] = {
.channel_template = AD5360_CHANNEL(16),
.num_channels = 8,
.channels_per_group = 4,
.num_vrefs = 2,
},
[ID_AD5363] = {
.channel_template = AD5360_CHANNEL(14),
.num_channels = 8,
.channels_per_group = 4,
.num_vrefs = 2,
},
[ID_AD5370] = {
.channel_template = AD5360_CHANNEL(16),
.num_channels = 40,
.channels_per_group = 8,
.num_vrefs = 2,
},
[ID_AD5371] = {
.channel_template = AD5360_CHANNEL(14),
.num_channels = 40,
.channels_per_group = 8,
.num_vrefs = 3,
},
[ID_AD5372] = {
.channel_template = AD5360_CHANNEL(16),
.num_channels = 32,
.channels_per_group = 8,
.num_vrefs = 2,
},
[ID_AD5373] = {
.channel_template = AD5360_CHANNEL(14),
.num_channels = 32,
.channels_per_group = 8,
.num_vrefs = 2,
},
};
static unsigned int ad5360_get_channel_vref_index(struct ad5360_state *st,
unsigned int channel)
{
unsigned int i;
/* The first groups have their own vref, while the remaining groups
* share the last vref */
i = channel / st->chip_info->channels_per_group;
if (i >= st->chip_info->num_vrefs)
i = st->chip_info->num_vrefs - 1;
return i;
}
static int ad5360_get_channel_vref(struct ad5360_state *st,
unsigned int channel)
{
unsigned int i = ad5360_get_channel_vref_index(st, channel);
return regulator_get_voltage(st->vref_reg[i].consumer);
}
static int ad5360_write_unlocked(struct iio_dev *indio_dev,
unsigned int cmd, unsigned int addr, unsigned int val,
unsigned int shift)
{
struct ad5360_state *st = iio_priv(indio_dev);
val <<= shift;
val |= AD5360_CMD(cmd) | AD5360_ADDR(addr);
st->data[0].d32 = cpu_to_be32(val);
return spi_write(st->spi, &st->data[0].d8[1], 3);
}
static int ad5360_write(struct iio_dev *indio_dev, unsigned int cmd,
unsigned int addr, unsigned int val, unsigned int shift)
{
int ret;
struct ad5360_state *st = iio_priv(indio_dev);
mutex_lock(&st->lock);
ret = ad5360_write_unlocked(indio_dev, cmd, addr, val, shift);
mutex_unlock(&st->lock);
return ret;
}
static int ad5360_read(struct iio_dev *indio_dev, unsigned int type,
unsigned int addr)
{
struct ad5360_state *st = iio_priv(indio_dev);
int ret;
struct spi_transfer t[] = {
{
.tx_buf = &st->data[0].d8[1],
.len = 3,
.cs_change = 1,
}, {
.rx_buf = &st->data[1].d8[1],
.len = 3,
},
};
mutex_lock(&st->lock);
st->data[0].d32 = cpu_to_be32(AD5360_CMD(AD5360_CMD_SPECIAL_FUNCTION) |
AD5360_ADDR(AD5360_REG_SF_READBACK) |
AD5360_READBACK_TYPE(type) |
AD5360_READBACK_ADDR(addr));
ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
if (ret >= 0)
ret = be32_to_cpu(st->data[1].d32) & 0xffff;
mutex_unlock(&st->lock);
return ret;
}
static ssize_t ad5360_read_dac_powerdown(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct ad5360_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", (bool)(st->ctrl & AD5360_SF_CTRL_PWR_DOWN));
}
static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
unsigned int clr)
{
struct ad5360_state *st = iio_priv(indio_dev);
unsigned int ret;
mutex_lock(&st->lock);
st->ctrl |= set;
st->ctrl &= ~clr;
ret = ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
AD5360_REG_SF_CTRL, st->ctrl, 0);
mutex_unlock(&st->lock);
return ret;
}
static ssize_t ad5360_write_dac_powerdown(struct device *dev,
struct device_attribute *attr, const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
bool pwr_down;
int ret;
ret = kstrtobool(buf, &pwr_down);
if (ret)
return ret;
if (pwr_down)
ret = ad5360_update_ctrl(indio_dev, AD5360_SF_CTRL_PWR_DOWN, 0);
else
ret = ad5360_update_ctrl(indio_dev, 0, AD5360_SF_CTRL_PWR_DOWN);
return ret ? ret : len;
}
static IIO_DEVICE_ATTR(out_voltage_powerdown,
S_IRUGO | S_IWUSR,
ad5360_read_dac_powerdown,
ad5360_write_dac_powerdown, 0);
static struct attribute *ad5360_attributes[] = {
&iio_dev_attr_out_voltage_powerdown.dev_attr.attr,
NULL,
};
static const struct attribute_group ad5360_attribute_group = {
.attrs = ad5360_attributes,
};
static int ad5360_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct ad5360_state *st = iio_priv(indio_dev);
int max_val = (1 << chan->scan_type.realbits);
unsigned int ofs_index;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val >= max_val || val < 0)
return -EINVAL;
return ad5360_write(indio_dev, AD5360_CMD_WRITE_DATA,
chan->address, val, chan->scan_type.shift);
case IIO_CHAN_INFO_CALIBBIAS:
if (val >= max_val || val < 0)
return -EINVAL;
return ad5360_write(indio_dev, AD5360_CMD_WRITE_OFFSET,
chan->address, val, chan->scan_type.shift);
case IIO_CHAN_INFO_CALIBSCALE:
if (val >= max_val || val < 0)
return -EINVAL;
return ad5360_write(indio_dev, AD5360_CMD_WRITE_GAIN,
chan->address, val, chan->scan_type.shift);
case IIO_CHAN_INFO_OFFSET:
if (val <= -max_val || val > 0)
return -EINVAL;
val = -val;
/* offset is supposed to have the same scale as raw, but it
* is always 14bits wide, so on a chip where the raw value has
* more bits, we need to shift offset. */
val >>= (chan->scan_type.realbits - 14);
/* There is one DAC offset register per vref. Changing one
* channels offset will also change the offset for all other
* channels which share the same vref supply. */
ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
return ad5360_write(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
AD5360_REG_SF_OFS(ofs_index), val, 0);
default:
break;
}
return -EINVAL;
}
static int ad5360_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct ad5360_state *st = iio_priv(indio_dev);
unsigned int ofs_index;
int scale_uv;
int ret;
switch (m) {
case IIO_CHAN_INFO_RAW:
ret = ad5360_read(indio_dev, AD5360_READBACK_X1A,
chan->address);
if (ret < 0)
return ret;
*val = ret >> chan->scan_type.shift;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
scale_uv = ad5360_get_channel_vref(st, chan->channel);
if (scale_uv < 0)
return scale_uv;
/* vout = 4 * vref * dac_code */
*val = scale_uv * 4 / 1000;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_CALIBBIAS:
ret = ad5360_read(indio_dev, AD5360_READBACK_OFFSET,
chan->address);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBSCALE:
ret = ad5360_read(indio_dev, AD5360_READBACK_GAIN,
chan->address);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
ret = ad5360_read(indio_dev, AD5360_READBACK_SF,
AD5360_REG_SF_OFS(ofs_index));
if (ret < 0)
return ret;
ret <<= (chan->scan_type.realbits - 14);
*val = -ret;
return IIO_VAL_INT;
}
return -EINVAL;
}
static const struct iio_info ad5360_info = {
.read_raw = ad5360_read_raw,
.write_raw = ad5360_write_raw,
.attrs = &ad5360_attribute_group,
};
static const char * const ad5360_vref_name[] = {
"vref0", "vref1", "vref2"
};
static int ad5360_alloc_channels(struct iio_dev *indio_dev)
{
struct ad5360_state *st = iio_priv(indio_dev);
struct iio_chan_spec *channels;
unsigned int i;
channels = kcalloc(st->chip_info->num_channels,
sizeof(struct iio_chan_spec), GFP_KERNEL);
if (!channels)
return -ENOMEM;
for (i = 0; i < st->chip_info->num_channels; ++i) {
channels[i] = st->chip_info->channel_template;
channels[i].channel = i;
channels[i].address = AD5360_CHAN_ADDR(i);
}
indio_dev->channels = channels;
return 0;
}
static int ad5360_probe(struct spi_device *spi)
{
enum ad5360_type type = spi_get_device_id(spi)->driver_data;
struct iio_dev *indio_dev;
struct ad5360_state *st;
unsigned int i;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (indio_dev == NULL) {
dev_err(&spi->dev, "Failed to allocate iio device\n");
return -ENOMEM;
}
st = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
st->chip_info = &ad5360_chip_info_tbl[type];
st->spi = spi;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->info = &ad5360_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->num_channels = st->chip_info->num_channels;
mutex_init(&st->lock);
ret = ad5360_alloc_channels(indio_dev);
if (ret) {
dev_err(&spi->dev, "Failed to allocate channel spec: %d\n", ret);
return ret;
}
for (i = 0; i < st->chip_info->num_vrefs; ++i)
st->vref_reg[i].supply = ad5360_vref_name[i];
ret = devm_regulator_bulk_get(&st->spi->dev, st->chip_info->num_vrefs,
st->vref_reg);
if (ret) {
dev_err(&spi->dev, "Failed to request vref regulators: %d\n", ret);
goto error_free_channels;
}
ret = regulator_bulk_enable(st->chip_info->num_vrefs, st->vref_reg);
if (ret) {
dev_err(&spi->dev, "Failed to enable vref regulators: %d\n", ret);
goto error_free_channels;
}
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
goto error_disable_reg;
}
return 0;
error_disable_reg:
regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
error_free_channels:
kfree(indio_dev->channels);
return ret;
}
static void ad5360_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ad5360_state *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
kfree(indio_dev->channels);
regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
}
static const struct spi_device_id ad5360_ids[] = {
{ "ad5360", ID_AD5360 },
{ "ad5361", ID_AD5361 },
{ "ad5362", ID_AD5362 },
{ "ad5363", ID_AD5363 },
{ "ad5370", ID_AD5370 },
{ "ad5371", ID_AD5371 },
{ "ad5372", ID_AD5372 },
{ "ad5373", ID_AD5373 },
{}
};
MODULE_DEVICE_TABLE(spi, ad5360_ids);
static struct spi_driver ad5360_driver = {
.driver = {
.name = "ad5360",
},
.probe = ad5360_probe,
.remove = ad5360_remove,
.id_table = ad5360_ids,
};
module_spi_driver(ad5360_driver);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5360/61/62/63/70/71/72/73 DAC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5360.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R,
* AD5627, AD5627R, AD5628, AD5629R, AD5645R, AD5647R, AD5648, AD5665, AD5665R,
* AD5666, AD5667, AD5667R, AD5668, AD5669R, LTC2606, LTC2607, LTC2609, LTC2616,
* LTC2617, LTC2619, LTC2626, LTC2627, LTC2629, LTC2631, LTC2633, LTC2635
* Digital to analog converters driver
*
* Copyright 2011 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <asm/unaligned.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define AD5064_MAX_DAC_CHANNELS 8
#define AD5064_MAX_VREFS 4
#define AD5064_ADDR(x) ((x) << 20)
#define AD5064_CMD(x) ((x) << 24)
#define AD5064_ADDR_ALL_DAC 0xF
#define AD5064_CMD_WRITE_INPUT_N 0x0
#define AD5064_CMD_UPDATE_DAC_N 0x1
#define AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
#define AD5064_CMD_WRITE_INPUT_N_UPDATE_N 0x3
#define AD5064_CMD_POWERDOWN_DAC 0x4
#define AD5064_CMD_CLEAR 0x5
#define AD5064_CMD_LDAC_MASK 0x6
#define AD5064_CMD_RESET 0x7
#define AD5064_CMD_CONFIG 0x8
#define AD5064_CMD_RESET_V2 0x5
#define AD5064_CMD_CONFIG_V2 0x7
#define AD5064_CONFIG_DAISY_CHAIN_ENABLE BIT(1)
#define AD5064_CONFIG_INT_VREF_ENABLE BIT(0)
#define AD5064_LDAC_PWRDN_NONE 0x0
#define AD5064_LDAC_PWRDN_1K 0x1
#define AD5064_LDAC_PWRDN_100K 0x2
#define AD5064_LDAC_PWRDN_3STATE 0x3
/**
* enum ad5064_regmap_type - Register layout variant
* @AD5064_REGMAP_ADI: Old Analog Devices register map layout
* @AD5064_REGMAP_ADI2: New Analog Devices register map layout
* @AD5064_REGMAP_LTC: LTC register map layout
*/
enum ad5064_regmap_type {
AD5064_REGMAP_ADI,
AD5064_REGMAP_ADI2,
AD5064_REGMAP_LTC,
};
/**
* struct ad5064_chip_info - chip specific information
* @shared_vref: whether the vref supply is shared between channels
* @internal_vref: internal reference voltage. 0 if the chip has no
* internal vref.
* @channels: channel specification
* @num_channels: number of channels
* @regmap_type: register map layout variant
*/
struct ad5064_chip_info {
bool shared_vref;
unsigned long internal_vref;
const struct iio_chan_spec *channels;
unsigned int num_channels;
enum ad5064_regmap_type regmap_type;
};
struct ad5064_state;
typedef int (*ad5064_write_func)(struct ad5064_state *st, unsigned int cmd,
unsigned int addr, unsigned int val);
/**
* struct ad5064_state - driver instance specific data
* @dev: the device for this driver instance
* @chip_info: chip model specific constants, available modes etc
* @vref_reg: vref supply regulators
* @pwr_down: whether channel is powered down
* @pwr_down_mode: channel's current power down mode
* @dac_cache: current DAC raw value (chip does not support readback)
* @use_internal_vref: set to true if the internal reference voltage should be
* used.
* @write: register write callback
* @lock: maintain consistency between cached and dev state
* @data: i2c/spi transfer buffers
*/
struct ad5064_state {
struct device *dev;
const struct ad5064_chip_info *chip_info;
struct regulator_bulk_data vref_reg[AD5064_MAX_VREFS];
bool pwr_down[AD5064_MAX_DAC_CHANNELS];
u8 pwr_down_mode[AD5064_MAX_DAC_CHANNELS];
unsigned int dac_cache[AD5064_MAX_DAC_CHANNELS];
bool use_internal_vref;
ad5064_write_func write;
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
union {
u8 i2c[3];
__be32 spi;
} data __aligned(IIO_DMA_MINALIGN);
};
enum ad5064_type {
ID_AD5024,
ID_AD5025,
ID_AD5044,
ID_AD5045,
ID_AD5064,
ID_AD5064_1,
ID_AD5065,
ID_AD5625,
ID_AD5625R_1V25,
ID_AD5625R_2V5,
ID_AD5627,
ID_AD5627R_1V25,
ID_AD5627R_2V5,
ID_AD5628_1,
ID_AD5628_2,
ID_AD5629_1,
ID_AD5629_2,
ID_AD5645R_1V25,
ID_AD5645R_2V5,
ID_AD5647R_1V25,
ID_AD5647R_2V5,
ID_AD5648_1,
ID_AD5648_2,
ID_AD5665,
ID_AD5665R_1V25,
ID_AD5665R_2V5,
ID_AD5666_1,
ID_AD5666_2,
ID_AD5667,
ID_AD5667R_1V25,
ID_AD5667R_2V5,
ID_AD5668_1,
ID_AD5668_2,
ID_AD5669_1,
ID_AD5669_2,
ID_LTC2606,
ID_LTC2607,
ID_LTC2609,
ID_LTC2616,
ID_LTC2617,
ID_LTC2619,
ID_LTC2626,
ID_LTC2627,
ID_LTC2629,
ID_LTC2631_L12,
ID_LTC2631_H12,
ID_LTC2631_L10,
ID_LTC2631_H10,
ID_LTC2631_L8,
ID_LTC2631_H8,
ID_LTC2633_L12,
ID_LTC2633_H12,
ID_LTC2633_L10,
ID_LTC2633_H10,
ID_LTC2633_L8,
ID_LTC2633_H8,
ID_LTC2635_L12,
ID_LTC2635_H12,
ID_LTC2635_L10,
ID_LTC2635_H10,
ID_LTC2635_L8,
ID_LTC2635_H8,
};
static int ad5064_write(struct ad5064_state *st, unsigned int cmd,
unsigned int addr, unsigned int val, unsigned int shift)
{
val <<= shift;
return st->write(st, cmd, addr, val);
}
static int ad5064_sync_powerdown_mode(struct ad5064_state *st,
const struct iio_chan_spec *chan)
{
unsigned int val, address;
unsigned int shift;
int ret;
if (st->chip_info->regmap_type == AD5064_REGMAP_LTC) {
val = 0;
address = chan->address;
} else {
if (st->chip_info->regmap_type == AD5064_REGMAP_ADI2)
shift = 4;
else
shift = 8;
val = (0x1 << chan->address);
address = 0;
if (st->pwr_down[chan->channel])
val |= st->pwr_down_mode[chan->channel] << shift;
}
ret = ad5064_write(st, AD5064_CMD_POWERDOWN_DAC, address, val, 0);
return ret;
}
static const char * const ad5064_powerdown_modes[] = {
"1kohm_to_gnd",
"100kohm_to_gnd",
"three_state",
};
static const char * const ltc2617_powerdown_modes[] = {
"90kohm_to_gnd",
};
static int ad5064_get_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct ad5064_state *st = iio_priv(indio_dev);
return st->pwr_down_mode[chan->channel] - 1;
}
static int ad5064_set_powerdown_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, unsigned int mode)
{
struct ad5064_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
st->pwr_down_mode[chan->channel] = mode + 1;
ret = ad5064_sync_powerdown_mode(st, chan);
mutex_unlock(&st->lock);
return ret;
}
static const struct iio_enum ad5064_powerdown_mode_enum = {
.items = ad5064_powerdown_modes,
.num_items = ARRAY_SIZE(ad5064_powerdown_modes),
.get = ad5064_get_powerdown_mode,
.set = ad5064_set_powerdown_mode,
};
static const struct iio_enum ltc2617_powerdown_mode_enum = {
.items = ltc2617_powerdown_modes,
.num_items = ARRAY_SIZE(ltc2617_powerdown_modes),
.get = ad5064_get_powerdown_mode,
.set = ad5064_set_powerdown_mode,
};
static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
struct ad5064_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", st->pwr_down[chan->channel]);
}
static ssize_t ad5064_write_dac_powerdown(struct iio_dev *indio_dev,
uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
size_t len)
{
struct ad5064_state *st = iio_priv(indio_dev);
bool pwr_down;
int ret;
ret = kstrtobool(buf, &pwr_down);
if (ret)
return ret;
mutex_lock(&st->lock);
st->pwr_down[chan->channel] = pwr_down;
ret = ad5064_sync_powerdown_mode(st, chan);
mutex_unlock(&st->lock);
return ret ? ret : len;
}
static int ad5064_get_vref(struct ad5064_state *st,
struct iio_chan_spec const *chan)
{
unsigned int i;
if (st->use_internal_vref)
return st->chip_info->internal_vref;
i = st->chip_info->shared_vref ? 0 : chan->channel;
return regulator_get_voltage(st->vref_reg[i].consumer);
}
static int ad5064_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct ad5064_state *st = iio_priv(indio_dev);
int scale_uv;
switch (m) {
case IIO_CHAN_INFO_RAW:
*val = st->dac_cache[chan->channel];
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
scale_uv = ad5064_get_vref(st, chan);
if (scale_uv < 0)
return scale_uv;
*val = scale_uv / 1000;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
default:
break;
}
return -EINVAL;
}
static int ad5064_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long mask)
{
struct ad5064_state *st = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (val >= (1 << chan->scan_type.realbits) || val < 0)
return -EINVAL;
mutex_lock(&st->lock);
ret = ad5064_write(st, AD5064_CMD_WRITE_INPUT_N_UPDATE_N,
chan->address, val, chan->scan_type.shift);
if (ret == 0)
st->dac_cache[chan->channel] = val;
mutex_unlock(&st->lock);
break;
default:
ret = -EINVAL;
}
return ret;
}
static const struct iio_info ad5064_info = {
.read_raw = ad5064_read_raw,
.write_raw = ad5064_write_raw,
};
static const struct iio_chan_spec_ext_info ad5064_ext_info[] = {
{
.name = "powerdown",
.read = ad5064_read_dac_powerdown,
.write = ad5064_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5064_powerdown_mode_enum),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5064_powerdown_mode_enum),
{ },
};
static const struct iio_chan_spec_ext_info ltc2617_ext_info[] = {
{
.name = "powerdown",
.read = ad5064_read_dac_powerdown,
.write = ad5064_write_dac_powerdown,
.shared = IIO_SEPARATE,
},
IIO_ENUM("powerdown_mode", IIO_SEPARATE, <c2617_powerdown_mode_enum),
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, <c2617_powerdown_mode_enum),
{ },
};
#define AD5064_CHANNEL(chan, addr, bits, _shift, _ext_info) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.address = addr, \
.scan_type = { \
.sign = 'u', \
.realbits = (bits), \
.storagebits = 16, \
.shift = (_shift), \
}, \
.ext_info = (_ext_info), \
}
#define DECLARE_AD5064_CHANNELS(name, bits, shift, ext_info) \
const struct iio_chan_spec name[] = { \
AD5064_CHANNEL(0, 0, bits, shift, ext_info), \
AD5064_CHANNEL(1, 1, bits, shift, ext_info), \
AD5064_CHANNEL(2, 2, bits, shift, ext_info), \
AD5064_CHANNEL(3, 3, bits, shift, ext_info), \
AD5064_CHANNEL(4, 4, bits, shift, ext_info), \
AD5064_CHANNEL(5, 5, bits, shift, ext_info), \
AD5064_CHANNEL(6, 6, bits, shift, ext_info), \
AD5064_CHANNEL(7, 7, bits, shift, ext_info), \
}
#define DECLARE_AD5065_CHANNELS(name, bits, shift, ext_info) \
const struct iio_chan_spec name[] = { \
AD5064_CHANNEL(0, 0, bits, shift, ext_info), \
AD5064_CHANNEL(1, 3, bits, shift, ext_info), \
}
static DECLARE_AD5064_CHANNELS(ad5024_channels, 12, 8, ad5064_ext_info);
static DECLARE_AD5064_CHANNELS(ad5044_channels, 14, 6, ad5064_ext_info);
static DECLARE_AD5064_CHANNELS(ad5064_channels, 16, 4, ad5064_ext_info);
static DECLARE_AD5065_CHANNELS(ad5025_channels, 12, 8, ad5064_ext_info);
static DECLARE_AD5065_CHANNELS(ad5045_channels, 14, 6, ad5064_ext_info);
static DECLARE_AD5065_CHANNELS(ad5065_channels, 16, 4, ad5064_ext_info);
static DECLARE_AD5064_CHANNELS(ad5629_channels, 12, 4, ad5064_ext_info);
static DECLARE_AD5064_CHANNELS(ad5645_channels, 14, 2, ad5064_ext_info);
static DECLARE_AD5064_CHANNELS(ad5669_channels, 16, 0, ad5064_ext_info);
static DECLARE_AD5064_CHANNELS(ltc2607_channels, 16, 0, ltc2617_ext_info);
static DECLARE_AD5064_CHANNELS(ltc2617_channels, 14, 2, ltc2617_ext_info);
static DECLARE_AD5064_CHANNELS(ltc2627_channels, 12, 4, ltc2617_ext_info);
#define ltc2631_12_channels ltc2627_channels
static DECLARE_AD5064_CHANNELS(ltc2631_10_channels, 10, 6, ltc2617_ext_info);
static DECLARE_AD5064_CHANNELS(ltc2631_8_channels, 8, 8, ltc2617_ext_info);
#define LTC2631_INFO(vref, pchannels, nchannels) \
{ \
.shared_vref = true, \
.internal_vref = vref, \
.channels = pchannels, \
.num_channels = nchannels, \
.regmap_type = AD5064_REGMAP_LTC, \
}
static const struct ad5064_chip_info ad5064_chip_info_tbl[] = {
[ID_AD5024] = {
.shared_vref = false,
.channels = ad5024_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5025] = {
.shared_vref = false,
.channels = ad5025_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5044] = {
.shared_vref = false,
.channels = ad5044_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5045] = {
.shared_vref = false,
.channels = ad5045_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5064] = {
.shared_vref = false,
.channels = ad5064_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5064_1] = {
.shared_vref = true,
.channels = ad5064_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5065] = {
.shared_vref = false,
.channels = ad5065_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5625] = {
.shared_vref = true,
.channels = ad5629_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5625R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5629_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5625R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5629_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5627] = {
.shared_vref = true,
.channels = ad5629_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5627R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5629_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5627R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5629_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5628_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5024_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5628_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5024_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5629_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5629_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5629_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5629_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5645R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5645_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5645R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5645_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5647R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5645_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5647R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5645_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5648_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5044_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5648_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5044_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5665] = {
.shared_vref = true,
.channels = ad5669_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5665R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5669_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5665R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5669_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5666_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5064_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5666_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5064_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5667] = {
.shared_vref = true,
.channels = ad5669_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5667R_1V25] = {
.shared_vref = true,
.internal_vref = 1250000,
.channels = ad5669_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5667R_2V5] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5669_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_ADI2
},
[ID_AD5668_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5064_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5668_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5064_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5669_1] = {
.shared_vref = true,
.internal_vref = 2500000,
.channels = ad5669_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_AD5669_2] = {
.shared_vref = true,
.internal_vref = 5000000,
.channels = ad5669_channels,
.num_channels = 8,
.regmap_type = AD5064_REGMAP_ADI,
},
[ID_LTC2606] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2607_channels,
.num_channels = 1,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2607] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2607_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2609] = {
.shared_vref = false,
.internal_vref = 0,
.channels = ltc2607_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2616] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2617_channels,
.num_channels = 1,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2617] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2617_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2619] = {
.shared_vref = false,
.internal_vref = 0,
.channels = ltc2617_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2626] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2627_channels,
.num_channels = 1,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2627] = {
.shared_vref = true,
.internal_vref = 0,
.channels = ltc2627_channels,
.num_channels = 2,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2629] = {
.shared_vref = false,
.internal_vref = 0,
.channels = ltc2627_channels,
.num_channels = 4,
.regmap_type = AD5064_REGMAP_LTC,
},
[ID_LTC2631_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 1),
[ID_LTC2631_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 1),
[ID_LTC2631_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 1),
[ID_LTC2631_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 1),
[ID_LTC2631_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 1),
[ID_LTC2631_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 1),
[ID_LTC2633_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 2),
[ID_LTC2633_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 2),
[ID_LTC2633_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 2),
[ID_LTC2633_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 2),
[ID_LTC2633_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 2),
[ID_LTC2633_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 2),
[ID_LTC2635_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 4),
[ID_LTC2635_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 4),
[ID_LTC2635_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 4),
[ID_LTC2635_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 4),
[ID_LTC2635_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 4),
[ID_LTC2635_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 4),
};
static inline unsigned int ad5064_num_vref(struct ad5064_state *st)
{
return st->chip_info->shared_vref ? 1 : st->chip_info->num_channels;
}
static const char * const ad5064_vref_names[] = {
"vrefA",
"vrefB",
"vrefC",
"vrefD",
};
static const char *ad5064_vref_name(struct ad5064_state *st,
unsigned int vref)
{
return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref];
}
static int ad5064_set_config(struct ad5064_state *st, unsigned int val)
{
unsigned int cmd;
switch (st->chip_info->regmap_type) {
case AD5064_REGMAP_ADI2:
cmd = AD5064_CMD_CONFIG_V2;
break;
default:
cmd = AD5064_CMD_CONFIG;
break;
}
return ad5064_write(st, cmd, 0, val, 0);
}
static int ad5064_request_vref(struct ad5064_state *st, struct device *dev)
{
unsigned int i;
int ret;
for (i = 0; i < ad5064_num_vref(st); ++i)
st->vref_reg[i].supply = ad5064_vref_name(st, i);
if (!st->chip_info->internal_vref)
return devm_regulator_bulk_get(dev, ad5064_num_vref(st),
st->vref_reg);
/*
* This assumes that when the regulator has an internal VREF
* there is only one external VREF connection, which is
* currently the case for all supported devices.
*/
st->vref_reg[0].consumer = devm_regulator_get_optional(dev, "vref");
if (!IS_ERR(st->vref_reg[0].consumer))
return 0;
ret = PTR_ERR(st->vref_reg[0].consumer);
if (ret != -ENODEV)
return ret;
/* If no external regulator was supplied use the internal VREF */
st->use_internal_vref = true;
ret = ad5064_set_config(st, AD5064_CONFIG_INT_VREF_ENABLE);
if (ret)
dev_err(dev, "Failed to enable internal vref: %d\n", ret);
return ret;
}
static void ad5064_bulk_reg_disable(void *data)
{
struct ad5064_state *st = data;
regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
}
static int ad5064_probe(struct device *dev, enum ad5064_type type,
const char *name, ad5064_write_func write)
{
struct iio_dev *indio_dev;
struct ad5064_state *st;
unsigned int midscale;
unsigned int i;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
if (indio_dev == NULL)
return -ENOMEM;
st = iio_priv(indio_dev);
mutex_init(&st->lock);
st->chip_info = &ad5064_chip_info_tbl[type];
st->dev = dev;
st->write = write;
ret = ad5064_request_vref(st, dev);
if (ret)
return ret;
if (!st->use_internal_vref) {
ret = regulator_bulk_enable(ad5064_num_vref(st), st->vref_reg);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, ad5064_bulk_reg_disable, st);
if (ret)
return ret;
}
indio_dev->name = name;
indio_dev->info = &ad5064_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = st->chip_info->channels;
indio_dev->num_channels = st->chip_info->num_channels;
midscale = (1 << indio_dev->channels[0].scan_type.realbits) / 2;
for (i = 0; i < st->chip_info->num_channels; ++i) {
st->pwr_down_mode[i] = AD5064_LDAC_PWRDN_1K;
st->dac_cache[i] = midscale;
}
return devm_iio_device_register(dev, indio_dev);
}
#if IS_ENABLED(CONFIG_SPI_MASTER)
static int ad5064_spi_write(struct ad5064_state *st, unsigned int cmd,
unsigned int addr, unsigned int val)
{
struct spi_device *spi = to_spi_device(st->dev);
st->data.spi = cpu_to_be32(AD5064_CMD(cmd) | AD5064_ADDR(addr) | val);
return spi_write(spi, &st->data.spi, sizeof(st->data.spi));
}
static int ad5064_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
return ad5064_probe(&spi->dev, id->driver_data, id->name,
ad5064_spi_write);
}
static const struct spi_device_id ad5064_spi_ids[] = {
{"ad5024", ID_AD5024},
{"ad5025", ID_AD5025},
{"ad5044", ID_AD5044},
{"ad5045", ID_AD5045},
{"ad5064", ID_AD5064},
{"ad5064-1", ID_AD5064_1},
{"ad5065", ID_AD5065},
{"ad5628-1", ID_AD5628_1},
{"ad5628-2", ID_AD5628_2},
{"ad5648-1", ID_AD5648_1},
{"ad5648-2", ID_AD5648_2},
{"ad5666-1", ID_AD5666_1},
{"ad5666-2", ID_AD5666_2},
{"ad5668-1", ID_AD5668_1},
{"ad5668-2", ID_AD5668_2},
{"ad5668-3", ID_AD5668_2}, /* similar enough to ad5668-2 */
{}
};
MODULE_DEVICE_TABLE(spi, ad5064_spi_ids);
static struct spi_driver ad5064_spi_driver = {
.driver = {
.name = "ad5064",
},
.probe = ad5064_spi_probe,
.id_table = ad5064_spi_ids,
};
static int __init ad5064_spi_register_driver(void)
{
return spi_register_driver(&ad5064_spi_driver);
}
static void ad5064_spi_unregister_driver(void)
{
spi_unregister_driver(&ad5064_spi_driver);
}
#else
static inline int ad5064_spi_register_driver(void) { return 0; }
static inline void ad5064_spi_unregister_driver(void) { }
#endif
#if IS_ENABLED(CONFIG_I2C)
static int ad5064_i2c_write(struct ad5064_state *st, unsigned int cmd,
unsigned int addr, unsigned int val)
{
struct i2c_client *i2c = to_i2c_client(st->dev);
unsigned int cmd_shift;
int ret;
switch (st->chip_info->regmap_type) {
case AD5064_REGMAP_ADI2:
cmd_shift = 3;
break;
default:
cmd_shift = 4;
break;
}
st->data.i2c[0] = (cmd << cmd_shift) | addr;
put_unaligned_be16(val, &st->data.i2c[1]);
ret = i2c_master_send(i2c, st->data.i2c, 3);
if (ret < 0)
return ret;
return 0;
}
static int ad5064_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
return ad5064_probe(&i2c->dev, id->driver_data, id->name,
ad5064_i2c_write);
}
static const struct i2c_device_id ad5064_i2c_ids[] = {
{"ad5625", ID_AD5625 },
{"ad5625r-1v25", ID_AD5625R_1V25 },
{"ad5625r-2v5", ID_AD5625R_2V5 },
{"ad5627", ID_AD5627 },
{"ad5627r-1v25", ID_AD5627R_1V25 },
{"ad5627r-2v5", ID_AD5627R_2V5 },
{"ad5629-1", ID_AD5629_1},
{"ad5629-2", ID_AD5629_2},
{"ad5629-3", ID_AD5629_2}, /* similar enough to ad5629-2 */
{"ad5645r-1v25", ID_AD5645R_1V25 },
{"ad5645r-2v5", ID_AD5645R_2V5 },
{"ad5665", ID_AD5665 },
{"ad5665r-1v25", ID_AD5665R_1V25 },
{"ad5665r-2v5", ID_AD5665R_2V5 },
{"ad5667", ID_AD5667 },
{"ad5667r-1v25", ID_AD5667R_1V25 },
{"ad5667r-2v5", ID_AD5667R_2V5 },
{"ad5669-1", ID_AD5669_1},
{"ad5669-2", ID_AD5669_2},
{"ad5669-3", ID_AD5669_2}, /* similar enough to ad5669-2 */
{"ltc2606", ID_LTC2606},
{"ltc2607", ID_LTC2607},
{"ltc2609", ID_LTC2609},
{"ltc2616", ID_LTC2616},
{"ltc2617", ID_LTC2617},
{"ltc2619", ID_LTC2619},
{"ltc2626", ID_LTC2626},
{"ltc2627", ID_LTC2627},
{"ltc2629", ID_LTC2629},
{"ltc2631-l12", ID_LTC2631_L12},
{"ltc2631-h12", ID_LTC2631_H12},
{"ltc2631-l10", ID_LTC2631_L10},
{"ltc2631-h10", ID_LTC2631_H10},
{"ltc2631-l8", ID_LTC2631_L8},
{"ltc2631-h8", ID_LTC2631_H8},
{"ltc2633-l12", ID_LTC2633_L12},
{"ltc2633-h12", ID_LTC2633_H12},
{"ltc2633-l10", ID_LTC2633_L10},
{"ltc2633-h10", ID_LTC2633_H10},
{"ltc2633-l8", ID_LTC2633_L8},
{"ltc2633-h8", ID_LTC2633_H8},
{"ltc2635-l12", ID_LTC2635_L12},
{"ltc2635-h12", ID_LTC2635_H12},
{"ltc2635-l10", ID_LTC2635_L10},
{"ltc2635-h10", ID_LTC2635_H10},
{"ltc2635-l8", ID_LTC2635_L8},
{"ltc2635-h8", ID_LTC2635_H8},
{}
};
MODULE_DEVICE_TABLE(i2c, ad5064_i2c_ids);
static struct i2c_driver ad5064_i2c_driver = {
.driver = {
.name = "ad5064",
},
.probe = ad5064_i2c_probe,
.id_table = ad5064_i2c_ids,
};
static int __init ad5064_i2c_register_driver(void)
{
return i2c_add_driver(&ad5064_i2c_driver);
}
static void __exit ad5064_i2c_unregister_driver(void)
{
i2c_del_driver(&ad5064_i2c_driver);
}
#else
static inline int ad5064_i2c_register_driver(void) { return 0; }
static inline void ad5064_i2c_unregister_driver(void) { }
#endif
static int __init ad5064_init(void)
{
int ret;
ret = ad5064_spi_register_driver();
if (ret)
return ret;
ret = ad5064_i2c_register_driver();
if (ret) {
ad5064_spi_unregister_driver();
return ret;
}
return 0;
}
module_init(ad5064_init);
static void __exit ad5064_exit(void)
{
ad5064_i2c_unregister_driver();
ad5064_spi_unregister_driver();
}
module_exit(ad5064_exit);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5024 and similar multi-channel DACs");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/dac/ad5064.c |
// SPDX-License-Identifier: GPL-2.0
/*
* AD5672R, AD5674R, AD5676, AD5676R, AD5679R,
* AD5681R, AD5682R, AD5683, AD5683R, AD5684,
* AD5684R, AD5685R, AD5686, AD5686R
* Digital to analog converters driver
*
* Copyright 2018 Analog Devices Inc.
*/
#include "ad5686.h"
#include <linux/module.h>
#include <linux/spi/spi.h>
static int ad5686_spi_write(struct ad5686_state *st,
u8 cmd, u8 addr, u16 val)
{
struct spi_device *spi = to_spi_device(st->dev);
u8 tx_len, *buf;
switch (st->chip_info->regmap_type) {
case AD5310_REGMAP:
st->data[0].d16 = cpu_to_be16(AD5310_CMD(cmd) |
val);
buf = &st->data[0].d8[0];
tx_len = 2;
break;
case AD5683_REGMAP:
st->data[0].d32 = cpu_to_be32(AD5686_CMD(cmd) |
AD5683_DATA(val));
buf = &st->data[0].d8[1];
tx_len = 3;
break;
case AD5686_REGMAP:
st->data[0].d32 = cpu_to_be32(AD5686_CMD(cmd) |
AD5686_ADDR(addr) |
val);
buf = &st->data[0].d8[1];
tx_len = 3;
break;
default:
return -EINVAL;
}
return spi_write(spi, buf, tx_len);
}
static int ad5686_spi_read(struct ad5686_state *st, u8 addr)
{
struct spi_transfer t[] = {
{
.tx_buf = &st->data[0].d8[1],
.len = 3,
.cs_change = 1,
}, {
.tx_buf = &st->data[1].d8[1],
.rx_buf = &st->data[2].d8[1],
.len = 3,
},
};
struct spi_device *spi = to_spi_device(st->dev);
u8 cmd = 0;
int ret;
switch (st->chip_info->regmap_type) {
case AD5310_REGMAP:
return -ENOTSUPP;
case AD5683_REGMAP:
cmd = AD5686_CMD_READBACK_ENABLE_V2;
break;
case AD5686_REGMAP:
cmd = AD5686_CMD_READBACK_ENABLE;
break;
default:
return -EINVAL;
}
st->data[0].d32 = cpu_to_be32(AD5686_CMD(cmd) |
AD5686_ADDR(addr));
st->data[1].d32 = cpu_to_be32(AD5686_CMD(AD5686_CMD_NOOP));
ret = spi_sync_transfer(spi, t, ARRAY_SIZE(t));
if (ret < 0)
return ret;
return be32_to_cpu(st->data[2].d32);
}
static int ad5686_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
return ad5686_probe(&spi->dev, id->driver_data, id->name,
ad5686_spi_write, ad5686_spi_read);
}
static void ad5686_spi_remove(struct spi_device *spi)
{
ad5686_remove(&spi->dev);
}
static const struct spi_device_id ad5686_spi_id[] = {
{"ad5310r", ID_AD5310R},
{"ad5672r", ID_AD5672R},
{"ad5674r", ID_AD5674R},
{"ad5676", ID_AD5676},
{"ad5676r", ID_AD5676R},
{"ad5679r", ID_AD5679R},
{"ad5681r", ID_AD5681R},
{"ad5682r", ID_AD5682R},
{"ad5683", ID_AD5683},
{"ad5683r", ID_AD5683R},
{"ad5684", ID_AD5684},
{"ad5684r", ID_AD5684R},
{"ad5685", ID_AD5685R}, /* Does not exist */
{"ad5685r", ID_AD5685R},
{"ad5686", ID_AD5686},
{"ad5686r", ID_AD5686R},
{}
};
MODULE_DEVICE_TABLE(spi, ad5686_spi_id);
static struct spi_driver ad5686_spi_driver = {
.driver = {
.name = "ad5686",
},
.probe = ad5686_spi_probe,
.remove = ad5686_spi_remove,
.id_table = ad5686_spi_id,
};
module_spi_driver(ad5686_spi_driver);
MODULE_AUTHOR("Stefan Popa <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD5686 and similar multi-channel DACs");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_AD5686);
| linux-master | drivers/iio/dac/ad5686-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ADMV8818 driver
*
* Copyright 2021 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
#include <linux/notifier.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/units.h>
/* ADMV8818 Register Map */
#define ADMV8818_REG_SPI_CONFIG_A 0x0
#define ADMV8818_REG_SPI_CONFIG_B 0x1
#define ADMV8818_REG_CHIPTYPE 0x3
#define ADMV8818_REG_PRODUCT_ID_L 0x4
#define ADMV8818_REG_PRODUCT_ID_H 0x5
#define ADMV8818_REG_FAST_LATCH_POINTER 0x10
#define ADMV8818_REG_FAST_LATCH_STOP 0x11
#define ADMV8818_REG_FAST_LATCH_START 0x12
#define ADMV8818_REG_FAST_LATCH_DIRECTION 0x13
#define ADMV8818_REG_FAST_LATCH_STATE 0x14
#define ADMV8818_REG_WR0_SW 0x20
#define ADMV8818_REG_WR0_FILTER 0x21
#define ADMV8818_REG_WR1_SW 0x22
#define ADMV8818_REG_WR1_FILTER 0x23
#define ADMV8818_REG_WR2_SW 0x24
#define ADMV8818_REG_WR2_FILTER 0x25
#define ADMV8818_REG_WR3_SW 0x26
#define ADMV8818_REG_WR3_FILTER 0x27
#define ADMV8818_REG_WR4_SW 0x28
#define ADMV8818_REG_WR4_FILTER 0x29
#define ADMV8818_REG_LUT0_SW 0x100
#define ADMV8818_REG_LUT0_FILTER 0x101
#define ADMV8818_REG_LUT127_SW 0x1FE
#define ADMV8818_REG_LUT127_FILTER 0x1FF
/* ADMV8818_REG_SPI_CONFIG_A Map */
#define ADMV8818_SOFTRESET_N_MSK BIT(7)
#define ADMV8818_LSB_FIRST_N_MSK BIT(6)
#define ADMV8818_ENDIAN_N_MSK BIT(5)
#define ADMV8818_SDOACTIVE_N_MSK BIT(4)
#define ADMV8818_SDOACTIVE_MSK BIT(3)
#define ADMV8818_ENDIAN_MSK BIT(2)
#define ADMV8818_LSBFIRST_MSK BIT(1)
#define ADMV8818_SOFTRESET_MSK BIT(0)
/* ADMV8818_REG_SPI_CONFIG_B Map */
#define ADMV8818_SINGLE_INSTRUCTION_MSK BIT(7)
#define ADMV8818_CSB_STALL_MSK BIT(6)
#define ADMV8818_MASTER_SLAVE_RB_MSK BIT(5)
#define ADMV8818_MASTER_SLAVE_TRANSFER_MSK BIT(0)
/* ADMV8818_REG_WR0_SW Map */
#define ADMV8818_SW_IN_SET_WR0_MSK BIT(7)
#define ADMV8818_SW_OUT_SET_WR0_MSK BIT(6)
#define ADMV8818_SW_IN_WR0_MSK GENMASK(5, 3)
#define ADMV8818_SW_OUT_WR0_MSK GENMASK(2, 0)
/* ADMV8818_REG_WR0_FILTER Map */
#define ADMV8818_HPF_WR0_MSK GENMASK(7, 4)
#define ADMV8818_LPF_WR0_MSK GENMASK(3, 0)
enum {
ADMV8818_BW_FREQ,
ADMV8818_CENTER_FREQ
};
enum {
ADMV8818_AUTO_MODE,
ADMV8818_MANUAL_MODE,
ADMV8818_BYPASS_MODE,
};
struct admv8818_state {
struct spi_device *spi;
struct regmap *regmap;
struct clk *clkin;
struct notifier_block nb;
/* Protect against concurrent accesses to the device and data content*/
struct mutex lock;
unsigned int filter_mode;
u64 cf_hz;
};
static const unsigned long long freq_range_hpf[4][2] = {
{1750000000ULL, 3550000000ULL},
{3400000000ULL, 7250000000ULL},
{6600000000, 12000000000},
{12500000000, 19900000000}
};
static const unsigned long long freq_range_lpf[4][2] = {
{2050000000ULL, 3850000000ULL},
{3350000000ULL, 7250000000ULL},
{7000000000, 13000000000},
{12550000000, 18500000000}
};
static const struct regmap_config admv8818_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.read_flag_mask = 0x80,
.max_register = 0x1FF,
};
static const char * const admv8818_modes[] = {
[0] = "auto",
[1] = "manual",
[2] = "bypass"
};
static int __admv8818_hpf_select(struct admv8818_state *st, u64 freq)
{
unsigned int hpf_step = 0, hpf_band = 0, i, j;
u64 freq_step;
int ret;
if (freq < freq_range_hpf[0][0])
goto hpf_write;
if (freq > freq_range_hpf[3][1]) {
hpf_step = 15;
hpf_band = 4;
goto hpf_write;
}
for (i = 0; i < 4; i++) {
freq_step = div_u64((freq_range_hpf[i][1] -
freq_range_hpf[i][0]), 15);
if (freq > freq_range_hpf[i][0] &&
(freq < freq_range_hpf[i][1] + freq_step)) {
hpf_band = i + 1;
for (j = 1; j <= 16; j++) {
if (freq < (freq_range_hpf[i][0] + (freq_step * j))) {
hpf_step = j - 1;
break;
}
}
break;
}
}
/* Close HPF frequency gap between 12 and 12.5 GHz */
if (freq >= 12000 * HZ_PER_MHZ && freq <= 12500 * HZ_PER_MHZ) {
hpf_band = 3;
hpf_step = 15;
}
hpf_write:
ret = regmap_update_bits(st->regmap, ADMV8818_REG_WR0_SW,
ADMV8818_SW_IN_SET_WR0_MSK |
ADMV8818_SW_IN_WR0_MSK,
FIELD_PREP(ADMV8818_SW_IN_SET_WR0_MSK, 1) |
FIELD_PREP(ADMV8818_SW_IN_WR0_MSK, hpf_band));
if (ret)
return ret;
return regmap_update_bits(st->regmap, ADMV8818_REG_WR0_FILTER,
ADMV8818_HPF_WR0_MSK,
FIELD_PREP(ADMV8818_HPF_WR0_MSK, hpf_step));
}
static int admv8818_hpf_select(struct admv8818_state *st, u64 freq)
{
int ret;
mutex_lock(&st->lock);
ret = __admv8818_hpf_select(st, freq);
mutex_unlock(&st->lock);
return ret;
}
static int __admv8818_lpf_select(struct admv8818_state *st, u64 freq)
{
unsigned int lpf_step = 0, lpf_band = 0, i, j;
u64 freq_step;
int ret;
if (freq > freq_range_lpf[3][1])
goto lpf_write;
if (freq < freq_range_lpf[0][0]) {
lpf_band = 1;
goto lpf_write;
}
for (i = 0; i < 4; i++) {
if (freq > freq_range_lpf[i][0] && freq < freq_range_lpf[i][1]) {
lpf_band = i + 1;
freq_step = div_u64((freq_range_lpf[i][1] - freq_range_lpf[i][0]), 15);
for (j = 0; j <= 15; j++) {
if (freq < (freq_range_lpf[i][0] + (freq_step * j))) {
lpf_step = j;
break;
}
}
break;
}
}
lpf_write:
ret = regmap_update_bits(st->regmap, ADMV8818_REG_WR0_SW,
ADMV8818_SW_OUT_SET_WR0_MSK |
ADMV8818_SW_OUT_WR0_MSK,
FIELD_PREP(ADMV8818_SW_OUT_SET_WR0_MSK, 1) |
FIELD_PREP(ADMV8818_SW_OUT_WR0_MSK, lpf_band));
if (ret)
return ret;
return regmap_update_bits(st->regmap, ADMV8818_REG_WR0_FILTER,
ADMV8818_LPF_WR0_MSK,
FIELD_PREP(ADMV8818_LPF_WR0_MSK, lpf_step));
}
static int admv8818_lpf_select(struct admv8818_state *st, u64 freq)
{
int ret;
mutex_lock(&st->lock);
ret = __admv8818_lpf_select(st, freq);
mutex_unlock(&st->lock);
return ret;
}
static int admv8818_rfin_band_select(struct admv8818_state *st)
{
int ret;
st->cf_hz = clk_get_rate(st->clkin);
mutex_lock(&st->lock);
ret = __admv8818_hpf_select(st, st->cf_hz);
if (ret)
goto exit;
ret = __admv8818_lpf_select(st, st->cf_hz);
exit:
mutex_unlock(&st->lock);
return ret;
}
static int __admv8818_read_hpf_freq(struct admv8818_state *st, u64 *hpf_freq)
{
unsigned int data, hpf_band, hpf_state;
int ret;
ret = regmap_read(st->regmap, ADMV8818_REG_WR0_SW, &data);
if (ret)
return ret;
hpf_band = FIELD_GET(ADMV8818_SW_IN_WR0_MSK, data);
if (!hpf_band || hpf_band > 4) {
*hpf_freq = 0;
return ret;
}
ret = regmap_read(st->regmap, ADMV8818_REG_WR0_FILTER, &data);
if (ret)
return ret;
hpf_state = FIELD_GET(ADMV8818_HPF_WR0_MSK, data);
*hpf_freq = div_u64(freq_range_hpf[hpf_band - 1][1] - freq_range_hpf[hpf_band - 1][0], 15);
*hpf_freq = freq_range_hpf[hpf_band - 1][0] + (*hpf_freq * hpf_state);
return ret;
}
static int admv8818_read_hpf_freq(struct admv8818_state *st, u64 *hpf_freq)
{
int ret;
mutex_lock(&st->lock);
ret = __admv8818_read_hpf_freq(st, hpf_freq);
mutex_unlock(&st->lock);
return ret;
}
static int __admv8818_read_lpf_freq(struct admv8818_state *st, u64 *lpf_freq)
{
unsigned int data, lpf_band, lpf_state;
int ret;
ret = regmap_read(st->regmap, ADMV8818_REG_WR0_SW, &data);
if (ret)
return ret;
lpf_band = FIELD_GET(ADMV8818_SW_OUT_WR0_MSK, data);
if (!lpf_band || lpf_band > 4) {
*lpf_freq = 0;
return ret;
}
ret = regmap_read(st->regmap, ADMV8818_REG_WR0_FILTER, &data);
if (ret)
return ret;
lpf_state = FIELD_GET(ADMV8818_LPF_WR0_MSK, data);
*lpf_freq = div_u64(freq_range_lpf[lpf_band - 1][1] - freq_range_lpf[lpf_band - 1][0], 15);
*lpf_freq = freq_range_lpf[lpf_band - 1][0] + (*lpf_freq * lpf_state);
return ret;
}
static int admv8818_read_lpf_freq(struct admv8818_state *st, u64 *lpf_freq)
{
int ret;
mutex_lock(&st->lock);
ret = __admv8818_read_lpf_freq(st, lpf_freq);
mutex_unlock(&st->lock);
return ret;
}
static int admv8818_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long info)
{
struct admv8818_state *st = iio_priv(indio_dev);
u64 freq = ((u64)val2 << 32 | (u32)val);
switch (info) {
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
return admv8818_lpf_select(st, freq);
case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
return admv8818_hpf_select(st, freq);
default:
return -EINVAL;
}
}
static int admv8818_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
{
struct admv8818_state *st = iio_priv(indio_dev);
int ret;
u64 freq;
switch (info) {
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
ret = admv8818_read_lpf_freq(st, &freq);
if (ret)
return ret;
*val = (u32)freq;
*val2 = (u32)(freq >> 32);
return IIO_VAL_INT_64;
case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
ret = admv8818_read_hpf_freq(st, &freq);
if (ret)
return ret;
*val = (u32)freq;
*val2 = (u32)(freq >> 32);
return IIO_VAL_INT_64;
default:
return -EINVAL;
}
}
static int admv8818_reg_access(struct iio_dev *indio_dev,
unsigned int reg,
unsigned int write_val,
unsigned int *read_val)
{
struct admv8818_state *st = iio_priv(indio_dev);
if (read_val)
return regmap_read(st->regmap, reg, read_val);
else
return regmap_write(st->regmap, reg, write_val);
}
static int admv8818_filter_bypass(struct admv8818_state *st)
{
int ret;
mutex_lock(&st->lock);
ret = regmap_update_bits(st->regmap, ADMV8818_REG_WR0_SW,
ADMV8818_SW_IN_SET_WR0_MSK |
ADMV8818_SW_IN_WR0_MSK |
ADMV8818_SW_OUT_SET_WR0_MSK |
ADMV8818_SW_OUT_WR0_MSK,
FIELD_PREP(ADMV8818_SW_IN_SET_WR0_MSK, 1) |
FIELD_PREP(ADMV8818_SW_IN_WR0_MSK, 0) |
FIELD_PREP(ADMV8818_SW_OUT_SET_WR0_MSK, 1) |
FIELD_PREP(ADMV8818_SW_OUT_WR0_MSK, 0));
if (ret)
goto exit;
ret = regmap_update_bits(st->regmap, ADMV8818_REG_WR0_FILTER,
ADMV8818_HPF_WR0_MSK |
ADMV8818_LPF_WR0_MSK,
FIELD_PREP(ADMV8818_HPF_WR0_MSK, 0) |
FIELD_PREP(ADMV8818_LPF_WR0_MSK, 0));
exit:
mutex_unlock(&st->lock);
return ret;
}
static int admv8818_get_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct admv8818_state *st = iio_priv(indio_dev);
return st->filter_mode;
}
static int admv8818_set_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int mode)
{
struct admv8818_state *st = iio_priv(indio_dev);
int ret = 0;
if (!st->clkin) {
if (mode == ADMV8818_MANUAL_MODE)
goto set_mode;
if (mode == ADMV8818_BYPASS_MODE) {
ret = admv8818_filter_bypass(st);
if (ret)
return ret;
goto set_mode;
}
return -EINVAL;
}
switch (mode) {
case ADMV8818_AUTO_MODE:
if (st->filter_mode == ADMV8818_AUTO_MODE)
return 0;
ret = clk_prepare_enable(st->clkin);
if (ret)
return ret;
ret = clk_notifier_register(st->clkin, &st->nb);
if (ret) {
clk_disable_unprepare(st->clkin);
return ret;
}
break;
case ADMV8818_MANUAL_MODE:
case ADMV8818_BYPASS_MODE:
if (st->filter_mode == ADMV8818_AUTO_MODE) {
clk_disable_unprepare(st->clkin);
ret = clk_notifier_unregister(st->clkin, &st->nb);
if (ret)
return ret;
}
if (mode == ADMV8818_BYPASS_MODE) {
ret = admv8818_filter_bypass(st);
if (ret)
return ret;
}
break;
default:
return -EINVAL;
}
set_mode:
st->filter_mode = mode;
return ret;
}
static const struct iio_info admv8818_info = {
.write_raw = admv8818_write_raw,
.read_raw = admv8818_read_raw,
.debugfs_reg_access = &admv8818_reg_access,
};
static const struct iio_enum admv8818_mode_enum = {
.items = admv8818_modes,
.num_items = ARRAY_SIZE(admv8818_modes),
.get = admv8818_get_mode,
.set = admv8818_set_mode,
};
static const struct iio_chan_spec_ext_info admv8818_ext_info[] = {
IIO_ENUM("filter_mode", IIO_SHARED_BY_ALL, &admv8818_mode_enum),
IIO_ENUM_AVAILABLE("filter_mode", IIO_SHARED_BY_ALL, &admv8818_mode_enum),
{ },
};
#define ADMV8818_CHAN(_channel) { \
.type = IIO_ALTVOLTAGE, \
.output = 1, \
.indexed = 1, \
.channel = _channel, \
.info_mask_separate = \
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) \
}
#define ADMV8818_CHAN_BW_CF(_channel, _admv8818_ext_info) { \
.type = IIO_ALTVOLTAGE, \
.output = 1, \
.indexed = 1, \
.channel = _channel, \
.ext_info = _admv8818_ext_info, \
}
static const struct iio_chan_spec admv8818_channels[] = {
ADMV8818_CHAN(0),
ADMV8818_CHAN_BW_CF(0, admv8818_ext_info),
};
static int admv8818_freq_change(struct notifier_block *nb, unsigned long action, void *data)
{
struct admv8818_state *st = container_of(nb, struct admv8818_state, nb);
if (action == POST_RATE_CHANGE)
return notifier_from_errno(admv8818_rfin_band_select(st));
return NOTIFY_OK;
}
static void admv8818_clk_notifier_unreg(void *data)
{
struct admv8818_state *st = data;
if (st->filter_mode == 0)
clk_notifier_unregister(st->clkin, &st->nb);
}
static void admv8818_clk_disable(void *data)
{
struct admv8818_state *st = data;
if (st->filter_mode == 0)
clk_disable_unprepare(st->clkin);
}
static int admv8818_init(struct admv8818_state *st)
{
int ret;
struct spi_device *spi = st->spi;
unsigned int chip_id;
ret = regmap_update_bits(st->regmap, ADMV8818_REG_SPI_CONFIG_A,
ADMV8818_SOFTRESET_N_MSK |
ADMV8818_SOFTRESET_MSK,
FIELD_PREP(ADMV8818_SOFTRESET_N_MSK, 1) |
FIELD_PREP(ADMV8818_SOFTRESET_MSK, 1));
if (ret) {
dev_err(&spi->dev, "ADMV8818 Soft Reset failed.\n");
return ret;
}
ret = regmap_update_bits(st->regmap, ADMV8818_REG_SPI_CONFIG_A,
ADMV8818_SDOACTIVE_N_MSK |
ADMV8818_SDOACTIVE_MSK,
FIELD_PREP(ADMV8818_SDOACTIVE_N_MSK, 1) |
FIELD_PREP(ADMV8818_SDOACTIVE_MSK, 1));
if (ret) {
dev_err(&spi->dev, "ADMV8818 SDO Enable failed.\n");
return ret;
}
ret = regmap_read(st->regmap, ADMV8818_REG_CHIPTYPE, &chip_id);
if (ret) {
dev_err(&spi->dev, "ADMV8818 Chip ID read failed.\n");
return ret;
}
if (chip_id != 0x1) {
dev_err(&spi->dev, "ADMV8818 Invalid Chip ID.\n");
return -EINVAL;
}
ret = regmap_update_bits(st->regmap, ADMV8818_REG_SPI_CONFIG_B,
ADMV8818_SINGLE_INSTRUCTION_MSK,
FIELD_PREP(ADMV8818_SINGLE_INSTRUCTION_MSK, 1));
if (ret) {
dev_err(&spi->dev, "ADMV8818 Single Instruction failed.\n");
return ret;
}
if (st->clkin)
return admv8818_rfin_band_select(st);
else
return 0;
}
static int admv8818_clk_setup(struct admv8818_state *st)
{
struct spi_device *spi = st->spi;
int ret;
st->clkin = devm_clk_get_optional(&spi->dev, "rf_in");
if (IS_ERR(st->clkin))
return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),
"failed to get the input clock\n");
else if (!st->clkin)
return 0;
ret = clk_prepare_enable(st->clkin);
if (ret)
return ret;
ret = devm_add_action_or_reset(&spi->dev, admv8818_clk_disable, st);
if (ret)
return ret;
st->nb.notifier_call = admv8818_freq_change;
ret = clk_notifier_register(st->clkin, &st->nb);
if (ret < 0)
return ret;
return devm_add_action_or_reset(&spi->dev, admv8818_clk_notifier_unreg, st);
}
static int admv8818_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct regmap *regmap;
struct admv8818_state *st;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
regmap = devm_regmap_init_spi(spi, &admv8818_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
st = iio_priv(indio_dev);
st->regmap = regmap;
indio_dev->info = &admv8818_info;
indio_dev->name = "admv8818";
indio_dev->channels = admv8818_channels;
indio_dev->num_channels = ARRAY_SIZE(admv8818_channels);
st->spi = spi;
ret = admv8818_clk_setup(st);
if (ret)
return ret;
mutex_init(&st->lock);
ret = admv8818_init(st);
if (ret)
return ret;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id admv8818_id[] = {
{ "admv8818", 0 },
{}
};
MODULE_DEVICE_TABLE(spi, admv8818_id);
static const struct of_device_id admv8818_of_match[] = {
{ .compatible = "adi,admv8818" },
{}
};
MODULE_DEVICE_TABLE(of, admv8818_of_match);
static struct spi_driver admv8818_driver = {
.driver = {
.name = "admv8818",
.of_match_table = admv8818_of_match,
},
.probe = admv8818_probe,
.id_table = admv8818_id,
};
module_spi_driver(admv8818_driver);
MODULE_AUTHOR("Antoniu Miclaus <[email protected]");
MODULE_DESCRIPTION("Analog Devices ADMV8818");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/filter/admv8818.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tmp007.c - Support for TI TMP007 IR thermopile sensor with integrated math engine
*
* Copyright (c) 2017 Manivannan Sadhasivam <[email protected]>
*
* Driver for the Texas Instruments I2C 16-bit IR thermopile sensor
*
* (7-bit I2C slave address (0x40 - 0x47), changeable via ADR pins)
*
* Note:
* 1. This driver assumes that the sensor has been calibrated beforehand
* 2. Limit threshold events are enabled at the start
* 3. Operating mode: INT
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/bitops.h>
#include <linux/mod_devicetable.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
#define TMP007_TDIE 0x01
#define TMP007_CONFIG 0x02
#define TMP007_TOBJECT 0x03
#define TMP007_STATUS 0x04
#define TMP007_STATUS_MASK 0x05
#define TMP007_TOBJ_HIGH_LIMIT 0x06
#define TMP007_TOBJ_LOW_LIMIT 0x07
#define TMP007_TDIE_HIGH_LIMIT 0x08
#define TMP007_TDIE_LOW_LIMIT 0x09
#define TMP007_MANUFACTURER_ID 0x1e
#define TMP007_DEVICE_ID 0x1f
#define TMP007_CONFIG_CONV_EN BIT(12)
#define TMP007_CONFIG_TC_EN BIT(6)
#define TMP007_CONFIG_CR_MASK GENMASK(11, 9)
#define TMP007_CONFIG_ALERT_EN BIT(8)
#define TMP007_CONFIG_CR_SHIFT 9
/* Status register flags */
#define TMP007_STATUS_ALERT BIT(15)
#define TMP007_STATUS_CONV_READY BIT(14)
#define TMP007_STATUS_OHF BIT(13)
#define TMP007_STATUS_OLF BIT(12)
#define TMP007_STATUS_LHF BIT(11)
#define TMP007_STATUS_LLF BIT(10)
#define TMP007_STATUS_DATA_VALID BIT(9)
#define TMP007_MANUFACTURER_MAGIC 0x5449
#define TMP007_DEVICE_MAGIC 0x0078
#define TMP007_TEMP_SHIFT 2
struct tmp007_data {
struct i2c_client *client;
struct mutex lock;
u16 config;
u16 status_mask;
};
static const int tmp007_avgs[5][2] = { {4, 0}, {2, 0}, {1, 0},
{0, 500000}, {0, 250000} };
static int tmp007_read_temperature(struct tmp007_data *data, u8 reg)
{
s32 ret;
int tries = 50;
while (tries-- > 0) {
ret = i2c_smbus_read_word_swapped(data->client,
TMP007_STATUS);
if (ret < 0)
return ret;
if ((ret & TMP007_STATUS_CONV_READY) &&
!(ret & TMP007_STATUS_DATA_VALID))
break;
msleep(100);
}
if (tries < 0)
return -EIO;
return i2c_smbus_read_word_swapped(data->client, reg);
}
static int tmp007_powerdown(struct tmp007_data *data)
{
return i2c_smbus_write_word_swapped(data->client, TMP007_CONFIG,
data->config & ~TMP007_CONFIG_CONV_EN);
}
static int tmp007_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
struct tmp007_data *data = iio_priv(indio_dev);
s32 ret;
int conv_rate;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (channel->channel2) {
case IIO_MOD_TEMP_AMBIENT: /* LSB: 0.03125 degree Celsius */
ret = i2c_smbus_read_word_swapped(data->client, TMP007_TDIE);
if (ret < 0)
return ret;
break;
case IIO_MOD_TEMP_OBJECT:
ret = tmp007_read_temperature(data, TMP007_TOBJECT);
if (ret < 0)
return ret;
break;
default:
return -EINVAL;
}
*val = sign_extend32(ret, 15) >> TMP007_TEMP_SHIFT;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 31;
*val2 = 250000;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_SAMP_FREQ:
conv_rate = (data->config & TMP007_CONFIG_CR_MASK)
>> TMP007_CONFIG_CR_SHIFT;
*val = tmp007_avgs[conv_rate][0];
*val2 = tmp007_avgs[conv_rate][1];
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int tmp007_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int val,
int val2, long mask)
{
struct tmp007_data *data = iio_priv(indio_dev);
int i;
u16 tmp;
if (mask == IIO_CHAN_INFO_SAMP_FREQ) {
for (i = 0; i < ARRAY_SIZE(tmp007_avgs); i++) {
if ((val == tmp007_avgs[i][0]) &&
(val2 == tmp007_avgs[i][1])) {
tmp = data->config & ~TMP007_CONFIG_CR_MASK;
tmp |= (i << TMP007_CONFIG_CR_SHIFT);
return i2c_smbus_write_word_swapped(data->client,
TMP007_CONFIG,
data->config = tmp);
}
}
}
return -EINVAL;
}
static irqreturn_t tmp007_interrupt_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct tmp007_data *data = iio_priv(indio_dev);
int ret;
ret = i2c_smbus_read_word_swapped(data->client, TMP007_STATUS);
if ((ret < 0) || !(ret & (TMP007_STATUS_OHF | TMP007_STATUS_OLF |
TMP007_STATUS_LHF | TMP007_STATUS_LLF)))
return IRQ_NONE;
if (ret & TMP007_STATUS_OHF)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_TEMP, 0,
IIO_MOD_TEMP_OBJECT,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
if (ret & TMP007_STATUS_OLF)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_TEMP, 0,
IIO_MOD_TEMP_OBJECT,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
iio_get_time_ns(indio_dev));
if (ret & TMP007_STATUS_LHF)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_TEMP, 0,
IIO_MOD_TEMP_AMBIENT,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
if (ret & TMP007_STATUS_LLF)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_TEMP, 0,
IIO_MOD_TEMP_AMBIENT,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
iio_get_time_ns(indio_dev));
return IRQ_HANDLED;
}
static int tmp007_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct tmp007_data *data = iio_priv(indio_dev);
unsigned int status_mask;
int ret;
switch (chan->channel2) {
case IIO_MOD_TEMP_AMBIENT:
if (dir == IIO_EV_DIR_RISING)
status_mask = TMP007_STATUS_LHF;
else
status_mask = TMP007_STATUS_LLF;
break;
case IIO_MOD_TEMP_OBJECT:
if (dir == IIO_EV_DIR_RISING)
status_mask = TMP007_STATUS_OHF;
else
status_mask = TMP007_STATUS_OLF;
break;
default:
return -EINVAL;
}
mutex_lock(&data->lock);
ret = i2c_smbus_read_word_swapped(data->client, TMP007_STATUS_MASK);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
if (state)
ret |= status_mask;
else
ret &= ~status_mask;
return i2c_smbus_write_word_swapped(data->client, TMP007_STATUS_MASK,
data->status_mask = ret);
}
static int tmp007_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir)
{
struct tmp007_data *data = iio_priv(indio_dev);
unsigned int mask;
switch (chan->channel2) {
case IIO_MOD_TEMP_AMBIENT:
if (dir == IIO_EV_DIR_RISING)
mask = TMP007_STATUS_LHF;
else
mask = TMP007_STATUS_LLF;
break;
case IIO_MOD_TEMP_OBJECT:
if (dir == IIO_EV_DIR_RISING)
mask = TMP007_STATUS_OHF;
else
mask = TMP007_STATUS_OLF;
break;
default:
return -EINVAL;
}
return !!(data->status_mask & mask);
}
static int tmp007_read_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info,
int *val, int *val2)
{
struct tmp007_data *data = iio_priv(indio_dev);
int ret;
u8 reg;
switch (chan->channel2) {
case IIO_MOD_TEMP_AMBIENT: /* LSB: 0.5 degree Celsius */
if (dir == IIO_EV_DIR_RISING)
reg = TMP007_TDIE_HIGH_LIMIT;
else
reg = TMP007_TDIE_LOW_LIMIT;
break;
case IIO_MOD_TEMP_OBJECT:
if (dir == IIO_EV_DIR_RISING)
reg = TMP007_TOBJ_HIGH_LIMIT;
else
reg = TMP007_TOBJ_LOW_LIMIT;
break;
default:
return -EINVAL;
}
ret = i2c_smbus_read_word_swapped(data->client, reg);
if (ret < 0)
return ret;
/* Shift length 7 bits = 6(15:6) + 1(0.5 LSB) */
*val = sign_extend32(ret, 15) >> 7;
return IIO_VAL_INT;
}
static int tmp007_write_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info,
int val, int val2)
{
struct tmp007_data *data = iio_priv(indio_dev);
u8 reg;
switch (chan->channel2) {
case IIO_MOD_TEMP_AMBIENT:
if (dir == IIO_EV_DIR_RISING)
reg = TMP007_TDIE_HIGH_LIMIT;
else
reg = TMP007_TDIE_LOW_LIMIT;
break;
case IIO_MOD_TEMP_OBJECT:
if (dir == IIO_EV_DIR_RISING)
reg = TMP007_TOBJ_HIGH_LIMIT;
else
reg = TMP007_TOBJ_LOW_LIMIT;
break;
default:
return -EINVAL;
}
/* Full scale threshold value is +/- 256 degree Celsius */
if (val < -256 || val > 255)
return -EINVAL;
/* Shift length 7 bits = 6(15:6) + 1(0.5 LSB) */
return i2c_smbus_write_word_swapped(data->client, reg, (val << 7));
}
static IIO_CONST_ATTR(sampling_frequency_available, "4 2 1 0.5 0.25");
static struct attribute *tmp007_attributes[] = {
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL
};
static const struct attribute_group tmp007_attribute_group = {
.attrs = tmp007_attributes,
};
static const struct iio_event_spec tmp007_obj_event[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_event_spec tmp007_die_event[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec tmp007_channels[] = {
{
.type = IIO_TEMP,
.modified = 1,
.channel2 = IIO_MOD_TEMP_AMBIENT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.event_spec = tmp007_die_event,
.num_event_specs = ARRAY_SIZE(tmp007_die_event),
},
{
.type = IIO_TEMP,
.modified = 1,
.channel2 = IIO_MOD_TEMP_OBJECT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.event_spec = tmp007_obj_event,
.num_event_specs = ARRAY_SIZE(tmp007_obj_event),
}
};
static const struct iio_info tmp007_info = {
.read_raw = tmp007_read_raw,
.write_raw = tmp007_write_raw,
.read_event_config = tmp007_read_event_config,
.write_event_config = tmp007_write_event_config,
.read_event_value = tmp007_read_thresh,
.write_event_value = tmp007_write_thresh,
.attrs = &tmp007_attribute_group,
};
static bool tmp007_identify(struct i2c_client *client)
{
int manf_id, dev_id;
manf_id = i2c_smbus_read_word_swapped(client, TMP007_MANUFACTURER_ID);
if (manf_id < 0)
return false;
dev_id = i2c_smbus_read_word_swapped(client, TMP007_DEVICE_ID);
if (dev_id < 0)
return false;
return (manf_id == TMP007_MANUFACTURER_MAGIC && dev_id == TMP007_DEVICE_MAGIC);
}
static void tmp007_powerdown_action_cb(void *priv)
{
struct tmp007_data *data = priv;
tmp007_powerdown(data);
}
static int tmp007_probe(struct i2c_client *client)
{
const struct i2c_device_id *tmp007_id = i2c_client_get_device_id(client);
struct tmp007_data *data;
struct iio_dev *indio_dev;
int ret;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA))
return -EOPNOTSUPP;
if (!tmp007_identify(client)) {
dev_err(&client->dev, "TMP007 not found\n");
return -ENODEV;
}
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
mutex_init(&data->lock);
indio_dev->name = "tmp007";
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &tmp007_info;
indio_dev->channels = tmp007_channels;
indio_dev->num_channels = ARRAY_SIZE(tmp007_channels);
/*
* Set Configuration register:
* 1. Conversion ON
* 2. ALERT enable
* 3. Transient correction enable
*/
ret = i2c_smbus_read_word_swapped(data->client, TMP007_CONFIG);
if (ret < 0)
return ret;
data->config = ret;
data->config |= (TMP007_CONFIG_CONV_EN | TMP007_CONFIG_ALERT_EN | TMP007_CONFIG_TC_EN);
ret = i2c_smbus_write_word_swapped(data->client, TMP007_CONFIG,
data->config);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&client->dev, tmp007_powerdown_action_cb, data);
if (ret)
return ret;
/*
* Only the following flags can activate ALERT pin. Data conversion/validity flags
* flags can still be polled for getting temperature data
*
* Set Status Mask register:
* 1. Object temperature high limit enable
* 2. Object temperature low limit enable
* 3. TDIE temperature high limit enable
* 4. TDIE temperature low limit enable
*/
ret = i2c_smbus_read_word_swapped(data->client, TMP007_STATUS_MASK);
if (ret < 0)
return ret;
data->status_mask = ret;
data->status_mask |= (TMP007_STATUS_OHF | TMP007_STATUS_OLF
| TMP007_STATUS_LHF | TMP007_STATUS_LLF);
ret = i2c_smbus_write_word_swapped(data->client, TMP007_STATUS_MASK, data->status_mask);
if (ret < 0)
return ret;
if (client->irq) {
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, tmp007_interrupt_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
tmp007_id->name, indio_dev);
if (ret) {
dev_err(&client->dev, "irq request error %d\n", -ret);
return ret;
}
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static int tmp007_suspend(struct device *dev)
{
struct tmp007_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
return tmp007_powerdown(data);
}
static int tmp007_resume(struct device *dev)
{
struct tmp007_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
return i2c_smbus_write_word_swapped(data->client, TMP007_CONFIG,
data->config | TMP007_CONFIG_CONV_EN);
}
static DEFINE_SIMPLE_DEV_PM_OPS(tmp007_pm_ops, tmp007_suspend, tmp007_resume);
static const struct of_device_id tmp007_of_match[] = {
{ .compatible = "ti,tmp007", },
{ },
};
MODULE_DEVICE_TABLE(of, tmp007_of_match);
static const struct i2c_device_id tmp007_id[] = {
{ "tmp007", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tmp007_id);
static struct i2c_driver tmp007_driver = {
.driver = {
.name = "tmp007",
.of_match_table = tmp007_of_match,
.pm = pm_sleep_ptr(&tmp007_pm_ops),
},
.probe = tmp007_probe,
.id_table = tmp007_id,
};
module_i2c_driver(tmp007_driver);
MODULE_AUTHOR("Manivannan Sadhasivam <[email protected]>");
MODULE_DESCRIPTION("TI TMP007 IR thermopile sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/temperature/tmp007.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Linumiz 2021
*
* max31865.c - Maxim MAX31865 RTD-to-Digital Converter sensor driver
*
* Author: Navin Sankar Velliangiri <[email protected]>
*/
#include <linux/ctype.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/property.h>
#include <linux/spi/spi.h>
#include <asm/unaligned.h>
/*
* The MSB of the register value determines whether the following byte will
* be written or read. If it is 0, read will follow and if it is 1, write
* will follow.
*/
#define MAX31865_RD_WR_BIT BIT(7)
#define MAX31865_CFG_VBIAS BIT(7)
#define MAX31865_CFG_1SHOT BIT(5)
#define MAX31865_3WIRE_RTD BIT(4)
#define MAX31865_FAULT_STATUS_CLEAR BIT(1)
#define MAX31865_FILTER_50HZ BIT(0)
/* The MAX31865 registers */
#define MAX31865_CFG_REG 0x00
#define MAX31865_RTD_MSB 0x01
#define MAX31865_FAULT_STATUS 0x07
#define MAX31865_FAULT_OVUV BIT(2)
static const char max31865_show_samp_freq[] = "50 60";
static const struct iio_chan_spec max31865_channels[] = {
{ /* RTD Temperature */
.type = IIO_TEMP,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE)
},
};
struct max31865_data {
struct spi_device *spi;
struct mutex lock;
bool filter_50hz;
bool three_wire;
u8 buf[2] __aligned(IIO_DMA_MINALIGN);
};
static int max31865_read(struct max31865_data *data, u8 reg,
unsigned int read_size)
{
return spi_write_then_read(data->spi, ®, 1, data->buf, read_size);
}
static int max31865_write(struct max31865_data *data, size_t len)
{
return spi_write(data->spi, data->buf, len);
}
static int enable_bias(struct max31865_data *data)
{
u8 cfg;
int ret;
ret = max31865_read(data, MAX31865_CFG_REG, 1);
if (ret)
return ret;
cfg = data->buf[0];
data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
data->buf[1] = cfg | MAX31865_CFG_VBIAS;
return max31865_write(data, 2);
}
static int disable_bias(struct max31865_data *data)
{
u8 cfg;
int ret;
ret = max31865_read(data, MAX31865_CFG_REG, 1);
if (ret)
return ret;
cfg = data->buf[0];
cfg &= ~MAX31865_CFG_VBIAS;
data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
data->buf[1] = cfg;
return max31865_write(data, 2);
}
static int max31865_rtd_read(struct max31865_data *data, int *val)
{
u8 reg;
int ret;
/* Enable BIAS to start the conversion */
ret = enable_bias(data);
if (ret)
return ret;
/* wait 10.5ms before initiating the conversion */
msleep(11);
ret = max31865_read(data, MAX31865_CFG_REG, 1);
if (ret)
return ret;
reg = data->buf[0];
reg |= MAX31865_CFG_1SHOT | MAX31865_FAULT_STATUS_CLEAR;
data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
data->buf[1] = reg;
ret = max31865_write(data, 2);
if (ret)
return ret;
if (data->filter_50hz) {
/* 50Hz filter mode requires 62.5ms to complete */
msleep(63);
} else {
/* 60Hz filter mode requires 52ms to complete */
msleep(52);
}
ret = max31865_read(data, MAX31865_RTD_MSB, 2);
if (ret)
return ret;
*val = get_unaligned_be16(&data->buf) >> 1;
return disable_bias(data);
}
static int max31865_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct max31865_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&data->lock);
ret = max31865_rtd_read(data, val);
mutex_unlock(&data->lock);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/* Temp. Data resolution is 0.03125 degree centigrade */
*val = 31;
*val2 = 250000; /* 1000 * 0.03125 */
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int max31865_init(struct max31865_data *data)
{
u8 cfg;
int ret;
ret = max31865_read(data, MAX31865_CFG_REG, 1);
if (ret)
return ret;
cfg = data->buf[0];
if (data->three_wire)
/* 3-wire RTD connection */
cfg |= MAX31865_3WIRE_RTD;
if (data->filter_50hz)
/* 50Hz noise rejection filter */
cfg |= MAX31865_FILTER_50HZ;
data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
data->buf[1] = cfg;
return max31865_write(data, 2);
}
static ssize_t show_fault(struct device *dev, u8 faultbit, char *buf)
{
int ret;
bool fault;
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct max31865_data *data = iio_priv(indio_dev);
ret = max31865_read(data, MAX31865_FAULT_STATUS, 1);
if (ret)
return ret;
fault = data->buf[0] & faultbit;
return sysfs_emit(buf, "%d\n", fault);
}
static ssize_t show_fault_ovuv(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return show_fault(dev, MAX31865_FAULT_OVUV, buf);
}
static ssize_t show_filter(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct max31865_data *data = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", data->filter_50hz ? 50 : 60);
}
static ssize_t set_filter(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct max31865_data *data = iio_priv(indio_dev);
unsigned int freq;
int ret;
ret = kstrtouint(buf, 10, &freq);
if (ret)
return ret;
switch (freq) {
case 50:
data->filter_50hz = true;
break;
case 60:
data->filter_50hz = false;
break;
default:
return -EINVAL;
}
mutex_lock(&data->lock);
ret = max31865_init(data);
mutex_unlock(&data->lock);
if (ret)
return ret;
return len;
}
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(max31865_show_samp_freq);
static IIO_DEVICE_ATTR(fault_ovuv, 0444, show_fault_ovuv, NULL, 0);
static IIO_DEVICE_ATTR(in_filter_notch_center_frequency, 0644,
show_filter, set_filter, 0);
static struct attribute *max31865_attributes[] = {
&iio_dev_attr_fault_ovuv.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
&iio_dev_attr_in_filter_notch_center_frequency.dev_attr.attr,
NULL,
};
static const struct attribute_group max31865_group = {
.attrs = max31865_attributes,
};
static const struct iio_info max31865_info = {
.read_raw = max31865_read_raw,
.attrs = &max31865_group,
};
static int max31865_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct iio_dev *indio_dev;
struct max31865_data *data;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->spi = spi;
data->filter_50hz = false;
mutex_init(&data->lock);
indio_dev->info = &max31865_info;
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = max31865_channels;
indio_dev->num_channels = ARRAY_SIZE(max31865_channels);
if (device_property_read_bool(&spi->dev, "maxim,3-wire")) {
/* select 3 wire */
data->three_wire = 1;
} else {
/* select 2 or 4 wire */
data->three_wire = 0;
}
ret = max31865_init(data);
if (ret) {
dev_err(&spi->dev, "error: Failed to configure max31865\n");
return ret;
}
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id max31865_id[] = {
{ "max31865", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, max31865_id);
static const struct of_device_id max31865_of_match[] = {
{ .compatible = "maxim,max31865" },
{ }
};
MODULE_DEVICE_TABLE(of, max31865_of_match);
static struct spi_driver max31865_driver = {
.driver = {
.name = "max31865",
.of_match_table = max31865_of_match,
},
.probe = max31865_probe,
.id_table = max31865_id,
};
module_spi_driver(max31865_driver);
MODULE_AUTHOR("Navin Sankar Velliangiri <[email protected]>");
MODULE_DESCRIPTION("Maxim MAX31865 RTD-to-Digital Converter sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/temperature/max31865.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Digital temperature sensor with integrated Non-volatile memory
* Copyright (c) 2021 Puranjay Mohan <[email protected]>
*
* Driver for the Texas Instruments TMP117 Temperature Sensor
* (7-bit I2C slave address (0x48 - 0x4B), changeable via ADD pins)
*
* Note: This driver assumes that the sensor has been calibrated beforehand.
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/limits.h>
#include <linux/property.h>
#include <linux/iio/iio.h>
#define TMP117_REG_TEMP 0x0
#define TMP117_REG_CFGR 0x1
#define TMP117_REG_HIGH_LIM 0x2
#define TMP117_REG_LOW_LIM 0x3
#define TMP117_REG_EEPROM_UL 0x4
#define TMP117_REG_EEPROM1 0x5
#define TMP117_REG_EEPROM2 0x6
#define TMP117_REG_TEMP_OFFSET 0x7
#define TMP117_REG_EEPROM3 0x8
#define TMP117_REG_DEVICE_ID 0xF
#define TMP117_RESOLUTION_10UC 78125
#define MICRODEGREE_PER_10MILLIDEGREE 10000
#define TMP116_DEVICE_ID 0x1116
#define TMP117_DEVICE_ID 0x0117
struct tmp117_data {
struct i2c_client *client;
s16 calibbias;
};
static int tmp117_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
struct tmp117_data *data = iio_priv(indio_dev);
s32 ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = i2c_smbus_read_word_swapped(data->client,
TMP117_REG_TEMP);
if (ret < 0)
return ret;
*val = sign_extend32(ret, 15);
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBBIAS:
ret = i2c_smbus_read_word_swapped(data->client,
TMP117_REG_TEMP_OFFSET);
if (ret < 0)
return ret;
*val = sign_extend32(ret, 15);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/*
* Conversion from 10s of uC to mC
* as IIO reports temperature in mC
*/
*val = TMP117_RESOLUTION_10UC / MICRODEGREE_PER_10MILLIDEGREE;
*val2 = (TMP117_RESOLUTION_10UC %
MICRODEGREE_PER_10MILLIDEGREE) * 100;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int tmp117_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec
const *channel, int val, int val2, long mask)
{
struct tmp117_data *data = iio_priv(indio_dev);
s16 off;
switch (mask) {
case IIO_CHAN_INFO_CALIBBIAS:
off = clamp_t(int, val, S16_MIN, S16_MAX);
if (off == data->calibbias)
return 0;
data->calibbias = off;
return i2c_smbus_write_word_swapped(data->client,
TMP117_REG_TEMP_OFFSET, off);
default:
return -EINVAL;
}
}
static const struct iio_chan_spec tmp117_channels[] = {
{
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBBIAS) |
BIT(IIO_CHAN_INFO_SCALE),
},
};
static const struct iio_chan_spec tmp116_channels[] = {
{
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
};
static const struct iio_info tmp117_info = {
.read_raw = tmp117_read_raw,
.write_raw = tmp117_write_raw,
};
static int tmp117_identify(struct i2c_client *client)
{
const struct i2c_device_id *id;
unsigned long match_data;
int dev_id;
dev_id = i2c_smbus_read_word_swapped(client, TMP117_REG_DEVICE_ID);
if (dev_id < 0)
return dev_id;
switch (dev_id) {
case TMP116_DEVICE_ID:
case TMP117_DEVICE_ID:
return dev_id;
}
dev_info(&client->dev, "Unknown device id (0x%x), use fallback compatible\n",
dev_id);
match_data = (uintptr_t)device_get_match_data(&client->dev);
if (match_data)
return match_data;
id = i2c_client_get_device_id(client);
if (id)
return id->driver_data;
dev_err(&client->dev, "Failed to identify unsupported device\n");
return -ENODEV;
}
static int tmp117_probe(struct i2c_client *client)
{
struct tmp117_data *data;
struct iio_dev *indio_dev;
int ret, dev_id;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA))
return -EOPNOTSUPP;
ret = tmp117_identify(client);
if (ret < 0)
return ret;
dev_id = ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->client = client;
data->calibbias = 0;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &tmp117_info;
switch (dev_id) {
case TMP116_DEVICE_ID:
indio_dev->channels = tmp116_channels;
indio_dev->num_channels = ARRAY_SIZE(tmp116_channels);
indio_dev->name = "tmp116";
break;
case TMP117_DEVICE_ID:
indio_dev->channels = tmp117_channels;
indio_dev->num_channels = ARRAY_SIZE(tmp117_channels);
indio_dev->name = "tmp117";
break;
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct of_device_id tmp117_of_match[] = {
{ .compatible = "ti,tmp116", .data = (void *)TMP116_DEVICE_ID },
{ .compatible = "ti,tmp117", .data = (void *)TMP117_DEVICE_ID },
{ }
};
MODULE_DEVICE_TABLE(of, tmp117_of_match);
static const struct i2c_device_id tmp117_id[] = {
{ "tmp116", TMP116_DEVICE_ID },
{ "tmp117", TMP117_DEVICE_ID },
{ }
};
MODULE_DEVICE_TABLE(i2c, tmp117_id);
static struct i2c_driver tmp117_driver = {
.driver = {
.name = "tmp117",
.of_match_table = tmp117_of_match,
},
.probe = tmp117_probe,
.id_table = tmp117_id,
};
module_i2c_driver(tmp117_driver);
MODULE_AUTHOR("Puranjay Mohan <[email protected]>");
MODULE_DESCRIPTION("TI TMP117 Temperature sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/temperature/tmp117.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tsys01.c - Support for Measurement-Specialties tsys01 temperature sensor
*
* Copyright (c) 2015 Measurement-Specialties
*
* Datasheet:
* http://www.meas-spec.com/downloads/TSYS01_Digital_Temperature_Sensor.pdf
*/
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/stat.h>
#include "../common/ms_sensors/ms_sensors_i2c.h"
/* TSYS01 Commands */
#define TSYS01_RESET 0x1E
#define TSYS01_CONVERSION_START 0x48
#define TSYS01_ADC_READ 0x00
#define TSYS01_PROM_READ 0xA0
#define TSYS01_PROM_WORDS_NB 8
struct tsys01_dev {
void *client;
struct mutex lock; /* lock during conversion */
int (*reset)(void *cli, u8 cmd, unsigned int delay);
int (*convert_and_read)(void *cli, u8 conv, u8 rd,
unsigned int delay, u32 *adc);
int (*read_prom_word)(void *cli, int cmd, u16 *word);
u16 prom[TSYS01_PROM_WORDS_NB];
};
/* Multiplication coefficients for temperature computation */
static const int coeff_mul[] = { -1500000, 1000000, -2000000,
4000000, -2000000 };
static int tsys01_read_temperature(struct iio_dev *indio_dev,
s32 *temperature)
{
int ret, i;
u32 adc;
s64 temp = 0;
struct tsys01_dev *dev_data = iio_priv(indio_dev);
mutex_lock(&dev_data->lock);
ret = dev_data->convert_and_read(dev_data->client,
TSYS01_CONVERSION_START,
TSYS01_ADC_READ, 9000, &adc);
mutex_unlock(&dev_data->lock);
if (ret)
return ret;
adc >>= 8;
/* Temperature algorithm */
for (i = 4; i > 0; i--) {
temp += coeff_mul[i] *
(s64)dev_data->prom[5 - i];
temp *= (s64)adc;
temp = div64_s64(temp, 100000);
}
temp *= 10;
temp += coeff_mul[0] * (s64)dev_data->prom[5];
temp = div64_s64(temp, 100000);
*temperature = temp;
return 0;
}
static int tsys01_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
int ret;
s32 temperature;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
switch (channel->type) {
case IIO_TEMP: /* in milli °C */
ret = tsys01_read_temperature(indio_dev, &temperature);
if (ret)
return ret;
*val = temperature;
return IIO_VAL_INT;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static const struct iio_chan_spec tsys01_channels[] = {
{
.type = IIO_TEMP,
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_PROCESSED),
}
};
static const struct iio_info tsys01_info = {
.read_raw = tsys01_read_raw,
};
static bool tsys01_crc_valid(u16 *n_prom)
{
u8 cnt;
u8 sum = 0;
for (cnt = 0; cnt < TSYS01_PROM_WORDS_NB; cnt++)
sum += ((n_prom[0] >> 8) + (n_prom[0] & 0xFF));
return (sum == 0);
}
static int tsys01_read_prom(struct iio_dev *indio_dev)
{
int i, ret;
struct tsys01_dev *dev_data = iio_priv(indio_dev);
char buf[7 * TSYS01_PROM_WORDS_NB + 1];
char *ptr = buf;
for (i = 0; i < TSYS01_PROM_WORDS_NB; i++) {
ret = dev_data->read_prom_word(dev_data->client,
TSYS01_PROM_READ + (i << 1),
&dev_data->prom[i]);
if (ret)
return ret;
ret = sprintf(ptr, "0x%04x ", dev_data->prom[i]);
ptr += ret;
}
if (!tsys01_crc_valid(dev_data->prom)) {
dev_err(&indio_dev->dev, "prom crc check error\n");
return -ENODEV;
}
*ptr = 0;
dev_info(&indio_dev->dev, "PROM coefficients : %s\n", buf);
return 0;
}
static int tsys01_probe(struct iio_dev *indio_dev, struct device *dev)
{
int ret;
struct tsys01_dev *dev_data = iio_priv(indio_dev);
mutex_init(&dev_data->lock);
indio_dev->info = &tsys01_info;
indio_dev->name = dev->driver->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = tsys01_channels;
indio_dev->num_channels = ARRAY_SIZE(tsys01_channels);
ret = dev_data->reset(dev_data->client, TSYS01_RESET, 3000);
if (ret)
return ret;
ret = tsys01_read_prom(indio_dev);
if (ret)
return ret;
return devm_iio_device_register(dev, indio_dev);
}
static int tsys01_i2c_probe(struct i2c_client *client)
{
struct tsys01_dev *dev_data;
struct iio_dev *indio_dev;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_WORD_DATA |
I2C_FUNC_SMBUS_WRITE_BYTE |
I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
dev_err(&client->dev,
"Adapter does not support some i2c transaction\n");
return -EOPNOTSUPP;
}
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*dev_data));
if (!indio_dev)
return -ENOMEM;
dev_data = iio_priv(indio_dev);
dev_data->client = client;
dev_data->reset = ms_sensors_reset;
dev_data->read_prom_word = ms_sensors_read_prom_word;
dev_data->convert_and_read = ms_sensors_convert_and_read;
i2c_set_clientdata(client, indio_dev);
return tsys01_probe(indio_dev, &client->dev);
}
static const struct i2c_device_id tsys01_id[] = {
{"tsys01", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, tsys01_id);
static const struct of_device_id tsys01_of_match[] = {
{ .compatible = "meas,tsys01", },
{ },
};
MODULE_DEVICE_TABLE(of, tsys01_of_match);
static struct i2c_driver tsys01_driver = {
.probe = tsys01_i2c_probe,
.id_table = tsys01_id,
.driver = {
.name = "tsys01",
.of_match_table = tsys01_of_match,
},
};
module_i2c_driver(tsys01_driver);
MODULE_DESCRIPTION("Measurement-Specialties tsys01 temperature driver");
MODULE_AUTHOR("William Markezana <[email protected]>");
MODULE_AUTHOR("Ludovic Tancerel <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_MEAS_SPEC_SENSORS);
| linux-master | drivers/iio/temperature/tsys01.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Rajat Khandelwal <[email protected]>
*
* Maxim MAX30208 digital temperature sensor with 0.1°C accuracy
* (7-bit I2C slave address (0x50 - 0x53))
*/
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/types.h>
#define MAX30208_STATUS 0x00
#define MAX30208_STATUS_TEMP_RDY BIT(0)
#define MAX30208_INT_ENABLE 0x01
#define MAX30208_INT_ENABLE_TEMP_RDY BIT(0)
#define MAX30208_FIFO_OVF_CNTR 0x06
#define MAX30208_FIFO_DATA_CNTR 0x07
#define MAX30208_FIFO_DATA 0x08
#define MAX30208_FIFO_CONFIG 0x0a
#define MAX30208_FIFO_CONFIG_RO BIT(1)
#define MAX30208_SYSTEM_CTRL 0x0c
#define MAX30208_SYSTEM_CTRL_RESET 0x01
#define MAX30208_TEMP_SENSOR_SETUP 0x14
#define MAX30208_TEMP_SENSOR_SETUP_CONV BIT(0)
struct max30208_data {
struct i2c_client *client;
struct iio_dev *indio_dev;
struct mutex lock; /* Lock to prevent concurrent reads of temperature readings */
};
static const struct iio_chan_spec max30208_channels[] = {
{
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
},
};
/**
* max30208_request() - Request a reading
* @data: Struct comprising member elements of the device
*
* Requests a reading from the device and waits until the conversion is ready.
*/
static int max30208_request(struct max30208_data *data)
{
/*
* Sensor can take up to 500 ms to respond so execute a total of
* 10 retries to give the device sufficient time.
*/
int retries = 10;
u8 regval;
int ret;
ret = i2c_smbus_read_byte_data(data->client, MAX30208_TEMP_SENSOR_SETUP);
if (ret < 0)
return ret;
regval = ret | MAX30208_TEMP_SENSOR_SETUP_CONV;
ret = i2c_smbus_write_byte_data(data->client, MAX30208_TEMP_SENSOR_SETUP, regval);
if (ret)
return ret;
while (retries--) {
ret = i2c_smbus_read_byte_data(data->client, MAX30208_STATUS);
if (ret < 0)
return ret;
if (ret & MAX30208_STATUS_TEMP_RDY)
return 0;
msleep(50);
}
dev_err(&data->client->dev, "Temperature conversion failed\n");
return -ETIMEDOUT;
}
static int max30208_update_temp(struct max30208_data *data)
{
u8 data_count;
int ret;
mutex_lock(&data->lock);
ret = max30208_request(data);
if (ret)
goto unlock;
ret = i2c_smbus_read_byte_data(data->client, MAX30208_FIFO_OVF_CNTR);
if (ret < 0)
goto unlock;
else if (!ret) {
ret = i2c_smbus_read_byte_data(data->client, MAX30208_FIFO_DATA_CNTR);
if (ret < 0)
goto unlock;
data_count = ret;
} else
data_count = 1;
while (data_count) {
ret = i2c_smbus_read_word_swapped(data->client, MAX30208_FIFO_DATA);
if (ret < 0)
goto unlock;
data_count--;
}
unlock:
mutex_unlock(&data->lock);
return ret;
}
/**
* max30208_config_setup() - Set up FIFO configuration register
* @data: Struct comprising member elements of the device
*
* Sets the rollover bit to '1' to enable overwriting FIFO during overflow.
*/
static int max30208_config_setup(struct max30208_data *data)
{
u8 regval;
int ret;
ret = i2c_smbus_read_byte_data(data->client, MAX30208_FIFO_CONFIG);
if (ret < 0)
return ret;
regval = ret | MAX30208_FIFO_CONFIG_RO;
ret = i2c_smbus_write_byte_data(data->client, MAX30208_FIFO_CONFIG, regval);
if (ret)
return ret;
return 0;
}
static int max30208_read(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct max30208_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = max30208_update_temp(data);
if (ret < 0)
return ret;
*val = sign_extend32(ret, 15);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 5;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static const struct iio_info max30208_info = {
.read_raw = max30208_read,
};
static int max30208_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct max30208_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->client = i2c;
mutex_init(&data->lock);
indio_dev->name = "max30208";
indio_dev->channels = max30208_channels;
indio_dev->num_channels = ARRAY_SIZE(max30208_channels);
indio_dev->info = &max30208_info;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = i2c_smbus_write_byte_data(data->client, MAX30208_SYSTEM_CTRL,
MAX30208_SYSTEM_CTRL_RESET);
if (ret) {
dev_err(dev, "Failure in performing reset\n");
return ret;
}
msleep(50);
ret = max30208_config_setup(data);
if (ret)
return ret;
ret = devm_iio_device_register(dev, indio_dev);
if (ret) {
dev_err(dev, "Failed to register IIO device\n");
return ret;
}
return 0;
}
static const struct i2c_device_id max30208_id_table[] = {
{ "max30208" },
{ }
};
MODULE_DEVICE_TABLE(i2c, max30208_id_table);
static const struct acpi_device_id max30208_acpi_match[] = {
{ "MAX30208" },
{ }
};
MODULE_DEVICE_TABLE(acpi, max30208_acpi_match);
static const struct of_device_id max30208_of_match[] = {
{ .compatible = "maxim,max30208" },
{ }
};
MODULE_DEVICE_TABLE(of, max30208_of_match);
static struct i2c_driver max30208_driver = {
.driver = {
.name = "max30208",
.of_match_table = max30208_of_match,
.acpi_match_table = max30208_acpi_match,
},
.probe = max30208_probe,
.id_table = max30208_id_table,
};
module_i2c_driver(max30208_driver);
MODULE_AUTHOR("Rajat Khandelwal <[email protected]>");
MODULE_DESCRIPTION("Maxim MAX30208 digital temperature sensor");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/temperature/max30208.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Azoteq IQS620AT Temperature Sensor
*
* Copyright (C) 2019 Jeff LaBundy <[email protected]>
*/
#include <linux/device.h>
#include <linux/iio/iio.h>
#include <linux/kernel.h>
#include <linux/mfd/iqs62x.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define IQS620_TEMP_UI_OUT 0x1A
#define IQS620_TEMP_SCALE 1000
#define IQS620_TEMP_OFFSET (-100)
#define IQS620_TEMP_OFFSET_V3 (-40)
static int iqs620_temp_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct iqs62x_core *iqs62x = iio_device_get_drvdata(indio_dev);
int ret;
__le16 val_buf;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = regmap_raw_read(iqs62x->regmap, IQS620_TEMP_UI_OUT,
&val_buf, sizeof(val_buf));
if (ret)
return ret;
*val = le16_to_cpu(val_buf);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = IQS620_TEMP_SCALE;
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
*val = iqs62x->hw_num < IQS620_HW_NUM_V3 ? IQS620_TEMP_OFFSET
: IQS620_TEMP_OFFSET_V3;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static const struct iio_info iqs620_temp_info = {
.read_raw = &iqs620_temp_read_raw,
};
static const struct iio_chan_spec iqs620_temp_channels[] = {
{
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET),
},
};
static int iqs620_temp_probe(struct platform_device *pdev)
{
struct iqs62x_core *iqs62x = dev_get_drvdata(pdev->dev.parent);
struct iio_dev *indio_dev;
indio_dev = devm_iio_device_alloc(&pdev->dev, 0);
if (!indio_dev)
return -ENOMEM;
iio_device_set_drvdata(indio_dev, iqs62x);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = iqs620_temp_channels;
indio_dev->num_channels = ARRAY_SIZE(iqs620_temp_channels);
indio_dev->name = iqs62x->dev_desc->dev_name;
indio_dev->info = &iqs620_temp_info;
return devm_iio_device_register(&pdev->dev, indio_dev);
}
static struct platform_driver iqs620_temp_platform_driver = {
.driver = {
.name = "iqs620at-temp",
},
.probe = iqs620_temp_probe,
};
module_platform_driver(iqs620_temp_platform_driver);
MODULE_AUTHOR("Jeff LaBundy <[email protected]>");
MODULE_DESCRIPTION("Azoteq IQS620AT Temperature Sensor");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:iqs620at-temp");
| linux-master | drivers/iio/temperature/iqs620at-temp.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mlx90632.c - Melexis MLX90632 contactless IR temperature sensor
*
* Copyright (c) 2017 Melexis <[email protected]>
*
* Driver for the Melexis MLX90632 I2C 16-bit IR thermopile sensor
*/
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/iopoll.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/limits.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/math64.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
/* Memory sections addresses */
#define MLX90632_ADDR_RAM 0x4000 /* Start address of ram */
#define MLX90632_ADDR_EEPROM 0x2480 /* Start address of user eeprom */
/* EEPROM addresses - used at startup */
#define MLX90632_EE_CTRL 0x24d4 /* Control register initial value */
#define MLX90632_EE_I2C_ADDR 0x24d5 /* I2C address register initial value */
#define MLX90632_EE_VERSION 0x240b /* EEPROM version reg address */
#define MLX90632_EE_P_R 0x240c /* P_R calibration register 32bit */
#define MLX90632_EE_P_G 0x240e /* P_G calibration register 32bit */
#define MLX90632_EE_P_T 0x2410 /* P_T calibration register 32bit */
#define MLX90632_EE_P_O 0x2412 /* P_O calibration register 32bit */
#define MLX90632_EE_Aa 0x2414 /* Aa calibration register 32bit */
#define MLX90632_EE_Ab 0x2416 /* Ab calibration register 32bit */
#define MLX90632_EE_Ba 0x2418 /* Ba calibration register 32bit */
#define MLX90632_EE_Bb 0x241a /* Bb calibration register 32bit */
#define MLX90632_EE_Ca 0x241c /* Ca calibration register 32bit */
#define MLX90632_EE_Cb 0x241e /* Cb calibration register 32bit */
#define MLX90632_EE_Da 0x2420 /* Da calibration register 32bit */
#define MLX90632_EE_Db 0x2422 /* Db calibration register 32bit */
#define MLX90632_EE_Ea 0x2424 /* Ea calibration register 32bit */
#define MLX90632_EE_Eb 0x2426 /* Eb calibration register 32bit */
#define MLX90632_EE_Fa 0x2428 /* Fa calibration register 32bit */
#define MLX90632_EE_Fb 0x242a /* Fb calibration register 32bit */
#define MLX90632_EE_Ga 0x242c /* Ga calibration register 32bit */
#define MLX90632_EE_Gb 0x242e /* Gb calibration register 16bit */
#define MLX90632_EE_Ka 0x242f /* Ka calibration register 16bit */
#define MLX90632_EE_Ha 0x2481 /* Ha customer calib value reg 16bit */
#define MLX90632_EE_Hb 0x2482 /* Hb customer calib value reg 16bit */
#define MLX90632_EE_MEDICAL_MEAS1 0x24E1 /* Medical measurement 1 16bit */
#define MLX90632_EE_MEDICAL_MEAS2 0x24E2 /* Medical measurement 2 16bit */
#define MLX90632_EE_EXTENDED_MEAS1 0x24F1 /* Extended measurement 1 16bit */
#define MLX90632_EE_EXTENDED_MEAS2 0x24F2 /* Extended measurement 2 16bit */
#define MLX90632_EE_EXTENDED_MEAS3 0x24F3 /* Extended measurement 3 16bit */
/* Register addresses - volatile */
#define MLX90632_REG_I2C_ADDR 0x3000 /* Chip I2C address register */
/* Control register address - volatile */
#define MLX90632_REG_CONTROL 0x3001 /* Control Register address */
#define MLX90632_CFG_PWR_MASK GENMASK(2, 1) /* PowerMode Mask */
#define MLX90632_CFG_MTYP_MASK GENMASK(8, 4) /* Meas select Mask */
#define MLX90632_CFG_SOB_MASK BIT(11)
/* PowerModes statuses */
#define MLX90632_PWR_STATUS(ctrl_val) (ctrl_val << 1)
#define MLX90632_PWR_STATUS_HALT MLX90632_PWR_STATUS(0) /* hold */
#define MLX90632_PWR_STATUS_SLEEP_STEP MLX90632_PWR_STATUS(1) /* sleep step */
#define MLX90632_PWR_STATUS_STEP MLX90632_PWR_STATUS(2) /* step */
#define MLX90632_PWR_STATUS_CONTINUOUS MLX90632_PWR_STATUS(3) /* continuous */
#define MLX90632_EE_RR GENMASK(10, 8) /* Only Refresh Rate bits */
#define MLX90632_REFRESH_RATE(ee_val) FIELD_GET(MLX90632_EE_RR, ee_val)
/* Extract Refresh Rate from ee register */
#define MLX90632_REFRESH_RATE_STATUS(refresh_rate) (refresh_rate << 8)
/* Measurement types */
#define MLX90632_MTYP_MEDICAL 0
#define MLX90632_MTYP_EXTENDED 17
/* Measurement type select*/
#define MLX90632_MTYP_STATUS(ctrl_val) (ctrl_val << 4)
#define MLX90632_MTYP_STATUS_MEDICAL MLX90632_MTYP_STATUS(MLX90632_MTYP_MEDICAL)
#define MLX90632_MTYP_STATUS_EXTENDED MLX90632_MTYP_STATUS(MLX90632_MTYP_EXTENDED)
/* I2C command register - volatile */
#define MLX90632_REG_I2C_CMD 0x3005 /* I2C command Register address */
/* Device status register - volatile */
#define MLX90632_REG_STATUS 0x3fff /* Device status register */
#define MLX90632_STAT_BUSY BIT(10) /* Device busy indicator */
#define MLX90632_STAT_EE_BUSY BIT(9) /* EEPROM busy indicator */
#define MLX90632_STAT_BRST BIT(8) /* Brown out reset indicator */
#define MLX90632_STAT_CYCLE_POS GENMASK(6, 2) /* Data position */
#define MLX90632_STAT_DATA_RDY BIT(0) /* Data ready indicator */
/* RAM_MEAS address-es for each channel */
#define MLX90632_RAM_1(meas_num) (MLX90632_ADDR_RAM + 3 * meas_num)
#define MLX90632_RAM_2(meas_num) (MLX90632_ADDR_RAM + 3 * meas_num + 1)
#define MLX90632_RAM_3(meas_num) (MLX90632_ADDR_RAM + 3 * meas_num + 2)
/* Name important RAM_MEAS channels */
#define MLX90632_RAM_DSP5_EXTENDED_AMBIENT_1 MLX90632_RAM_3(17)
#define MLX90632_RAM_DSP5_EXTENDED_AMBIENT_2 MLX90632_RAM_3(18)
#define MLX90632_RAM_DSP5_EXTENDED_OBJECT_1 MLX90632_RAM_1(17)
#define MLX90632_RAM_DSP5_EXTENDED_OBJECT_2 MLX90632_RAM_2(17)
#define MLX90632_RAM_DSP5_EXTENDED_OBJECT_3 MLX90632_RAM_1(18)
#define MLX90632_RAM_DSP5_EXTENDED_OBJECT_4 MLX90632_RAM_2(18)
#define MLX90632_RAM_DSP5_EXTENDED_OBJECT_5 MLX90632_RAM_1(19)
#define MLX90632_RAM_DSP5_EXTENDED_OBJECT_6 MLX90632_RAM_2(19)
/* Magic constants */
#define MLX90632_ID_MEDICAL 0x0105 /* EEPROM DSPv5 Medical device id */
#define MLX90632_ID_CONSUMER 0x0205 /* EEPROM DSPv5 Consumer device id */
#define MLX90632_ID_EXTENDED 0x0505 /* EEPROM DSPv5 Extended range device id */
#define MLX90632_ID_MASK GENMASK(14, 0) /* DSP version and device ID in EE_VERSION */
#define MLX90632_DSP_VERSION 5 /* DSP version */
#define MLX90632_DSP_MASK GENMASK(7, 0) /* DSP version in EE_VERSION */
#define MLX90632_RESET_CMD 0x0006 /* Reset sensor (address or global) */
#define MLX90632_REF_12 12LL /* ResCtrlRef value of Ch 1 or Ch 2 */
#define MLX90632_REF_3 12LL /* ResCtrlRef value of Channel 3 */
#define MLX90632_MAX_MEAS_NUM 31 /* Maximum measurements in list */
#define MLX90632_SLEEP_DELAY_MS 6000 /* Autosleep delay */
#define MLX90632_EXTENDED_LIMIT 27000 /* Extended mode raw value limit */
#define MLX90632_MEAS_MAX_TIME 2000 /* Max measurement time in ms for the lowest refresh rate */
/**
* struct mlx90632_data - private data for the MLX90632 device
* @client: I2C client of the device
* @lock: Internal mutex for multiple reads for single measurement
* @regmap: Regmap of the device
* @emissivity: Object emissivity from 0 to 1000 where 1000 = 1.
* @mtyp: Measurement type physical sensor configuration for extended range
* calculations
* @object_ambient_temperature: Ambient temperature at object (might differ of
* the ambient temperature of sensor.
* @regulator: Regulator of the device
* @powerstatus: Current POWER status of the device
* @interaction_ts: Timestamp of the last temperature read that is used
* for power management in jiffies
*/
struct mlx90632_data {
struct i2c_client *client;
struct mutex lock;
struct regmap *regmap;
u16 emissivity;
u8 mtyp;
u32 object_ambient_temperature;
struct regulator *regulator;
int powerstatus;
unsigned long interaction_ts;
};
static const struct regmap_range mlx90632_volatile_reg_range[] = {
regmap_reg_range(MLX90632_REG_I2C_ADDR, MLX90632_REG_CONTROL),
regmap_reg_range(MLX90632_REG_I2C_CMD, MLX90632_REG_I2C_CMD),
regmap_reg_range(MLX90632_REG_STATUS, MLX90632_REG_STATUS),
regmap_reg_range(MLX90632_RAM_1(0),
MLX90632_RAM_3(MLX90632_MAX_MEAS_NUM)),
};
static const struct regmap_access_table mlx90632_volatile_regs_tbl = {
.yes_ranges = mlx90632_volatile_reg_range,
.n_yes_ranges = ARRAY_SIZE(mlx90632_volatile_reg_range),
};
static const struct regmap_range mlx90632_read_reg_range[] = {
regmap_reg_range(MLX90632_EE_VERSION, MLX90632_EE_Ka),
regmap_reg_range(MLX90632_EE_CTRL, MLX90632_EE_I2C_ADDR),
regmap_reg_range(MLX90632_EE_Ha, MLX90632_EE_Hb),
regmap_reg_range(MLX90632_EE_MEDICAL_MEAS1, MLX90632_EE_MEDICAL_MEAS2),
regmap_reg_range(MLX90632_EE_EXTENDED_MEAS1, MLX90632_EE_EXTENDED_MEAS3),
regmap_reg_range(MLX90632_REG_I2C_ADDR, MLX90632_REG_CONTROL),
regmap_reg_range(MLX90632_REG_I2C_CMD, MLX90632_REG_I2C_CMD),
regmap_reg_range(MLX90632_REG_STATUS, MLX90632_REG_STATUS),
regmap_reg_range(MLX90632_RAM_1(0),
MLX90632_RAM_3(MLX90632_MAX_MEAS_NUM)),
};
static const struct regmap_access_table mlx90632_readable_regs_tbl = {
.yes_ranges = mlx90632_read_reg_range,
.n_yes_ranges = ARRAY_SIZE(mlx90632_read_reg_range),
};
static const struct regmap_range mlx90632_no_write_reg_range[] = {
regmap_reg_range(MLX90632_EE_VERSION, MLX90632_EE_Ka),
regmap_reg_range(MLX90632_RAM_1(0),
MLX90632_RAM_3(MLX90632_MAX_MEAS_NUM)),
};
static const struct regmap_access_table mlx90632_writeable_regs_tbl = {
.no_ranges = mlx90632_no_write_reg_range,
.n_no_ranges = ARRAY_SIZE(mlx90632_no_write_reg_range),
};
static const struct regmap_config mlx90632_regmap = {
.reg_bits = 16,
.val_bits = 16,
.volatile_table = &mlx90632_volatile_regs_tbl,
.rd_table = &mlx90632_readable_regs_tbl,
.wr_table = &mlx90632_writeable_regs_tbl,
.use_single_read = true,
.use_single_write = true,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.cache_type = REGCACHE_RBTREE,
};
static int mlx90632_pwr_set_sleep_step(struct regmap *regmap)
{
struct mlx90632_data *data =
iio_priv(dev_get_drvdata(regmap_get_device(regmap)));
int ret;
if (data->powerstatus == MLX90632_PWR_STATUS_SLEEP_STEP)
return 0;
ret = regmap_write_bits(regmap, MLX90632_REG_CONTROL, MLX90632_CFG_PWR_MASK,
MLX90632_PWR_STATUS_SLEEP_STEP);
if (ret < 0)
return ret;
data->powerstatus = MLX90632_PWR_STATUS_SLEEP_STEP;
return 0;
}
static int mlx90632_pwr_continuous(struct regmap *regmap)
{
struct mlx90632_data *data =
iio_priv(dev_get_drvdata(regmap_get_device(regmap)));
int ret;
if (data->powerstatus == MLX90632_PWR_STATUS_CONTINUOUS)
return 0;
ret = regmap_write_bits(regmap, MLX90632_REG_CONTROL, MLX90632_CFG_PWR_MASK,
MLX90632_PWR_STATUS_CONTINUOUS);
if (ret < 0)
return ret;
data->powerstatus = MLX90632_PWR_STATUS_CONTINUOUS;
return 0;
}
/**
* mlx90632_reset_delay() - Give the mlx90632 some time to reset properly
* If this is not done, the following I2C command(s) will not be accepted.
*/
static void mlx90632_reset_delay(void)
{
usleep_range(150, 200);
}
static int mlx90632_get_measurement_time(struct regmap *regmap, u16 meas)
{
unsigned int reg;
int ret;
ret = regmap_read(regmap, meas, ®);
if (ret < 0)
return ret;
return MLX90632_MEAS_MAX_TIME >> FIELD_GET(MLX90632_EE_RR, reg);
}
static int mlx90632_calculate_dataset_ready_time(struct mlx90632_data *data)
{
unsigned int refresh_time;
int ret;
if (data->mtyp == MLX90632_MTYP_MEDICAL) {
ret = mlx90632_get_measurement_time(data->regmap,
MLX90632_EE_MEDICAL_MEAS1);
if (ret < 0)
return ret;
refresh_time = ret;
ret = mlx90632_get_measurement_time(data->regmap,
MLX90632_EE_MEDICAL_MEAS2);
if (ret < 0)
return ret;
refresh_time += ret;
} else {
ret = mlx90632_get_measurement_time(data->regmap,
MLX90632_EE_EXTENDED_MEAS1);
if (ret < 0)
return ret;
refresh_time = ret;
ret = mlx90632_get_measurement_time(data->regmap,
MLX90632_EE_EXTENDED_MEAS2);
if (ret < 0)
return ret;
refresh_time += ret;
ret = mlx90632_get_measurement_time(data->regmap,
MLX90632_EE_EXTENDED_MEAS3);
if (ret < 0)
return ret;
refresh_time += ret;
}
return refresh_time;
}
/**
* mlx90632_perform_measurement() - Trigger and retrieve current measurement cycle
* @data: pointer to mlx90632_data object containing regmap information
*
* Perform a measurement and return latest measurement cycle position reported
* by sensor. This is a blocking function for 500ms, as that is default sensor
* refresh rate.
*/
static int mlx90632_perform_measurement(struct mlx90632_data *data)
{
unsigned int reg_status;
int ret;
ret = regmap_update_bits(data->regmap, MLX90632_REG_STATUS,
MLX90632_STAT_DATA_RDY, 0);
if (ret < 0)
return ret;
ret = regmap_read_poll_timeout(data->regmap, MLX90632_REG_STATUS, reg_status,
!(reg_status & MLX90632_STAT_DATA_RDY), 10000,
100 * 10000);
if (ret < 0) {
dev_err(&data->client->dev, "data not ready");
return -ETIMEDOUT;
}
return (reg_status & MLX90632_STAT_CYCLE_POS) >> 2;
}
/**
* mlx90632_perform_measurement_burst() - Trigger and retrieve current measurement
* cycle in step sleep mode
* @data: pointer to mlx90632_data object containing regmap information
*
* Perform a measurement and return 2 as measurement cycle position reported
* by sensor. This is a blocking function for amount dependent on the sensor
* refresh rate.
*/
static int mlx90632_perform_measurement_burst(struct mlx90632_data *data)
{
unsigned int reg_status;
int ret;
ret = regmap_write_bits(data->regmap, MLX90632_REG_CONTROL,
MLX90632_CFG_SOB_MASK, MLX90632_CFG_SOB_MASK);
if (ret < 0)
return ret;
ret = mlx90632_calculate_dataset_ready_time(data);
if (ret < 0)
return ret;
msleep(ret); /* Wait minimum time for dataset to be ready */
ret = regmap_read_poll_timeout(data->regmap, MLX90632_REG_STATUS,
reg_status,
(reg_status & MLX90632_STAT_BUSY) == 0,
10000, 100 * 10000);
if (ret < 0) {
dev_err(&data->client->dev, "data not ready");
return -ETIMEDOUT;
}
return 2;
}
static int mlx90632_set_meas_type(struct mlx90632_data *data, u8 type)
{
int current_powerstatus;
int ret;
if (data->mtyp == type)
return 0;
current_powerstatus = data->powerstatus;
ret = mlx90632_pwr_continuous(data->regmap);
if (ret < 0)
return ret;
ret = regmap_write(data->regmap, MLX90632_REG_I2C_CMD, MLX90632_RESET_CMD);
if (ret < 0)
return ret;
mlx90632_reset_delay();
ret = regmap_update_bits(data->regmap, MLX90632_REG_CONTROL,
(MLX90632_CFG_MTYP_MASK | MLX90632_CFG_PWR_MASK),
(MLX90632_MTYP_STATUS(type) | MLX90632_PWR_STATUS_HALT));
if (ret < 0)
return ret;
data->mtyp = type;
data->powerstatus = MLX90632_PWR_STATUS_HALT;
if (current_powerstatus == MLX90632_PWR_STATUS_SLEEP_STEP)
return mlx90632_pwr_set_sleep_step(data->regmap);
return mlx90632_pwr_continuous(data->regmap);
}
static int mlx90632_channel_new_select(int perform_ret, uint8_t *channel_new,
uint8_t *channel_old)
{
switch (perform_ret) {
case 1:
*channel_new = 1;
*channel_old = 2;
break;
case 2:
*channel_new = 2;
*channel_old = 1;
break;
default:
return -ECHRNG;
}
return 0;
}
static int mlx90632_read_ambient_raw(struct regmap *regmap,
s16 *ambient_new_raw, s16 *ambient_old_raw)
{
unsigned int read_tmp;
int ret;
ret = regmap_read(regmap, MLX90632_RAM_3(1), &read_tmp);
if (ret < 0)
return ret;
*ambient_new_raw = (s16)read_tmp;
ret = regmap_read(regmap, MLX90632_RAM_3(2), &read_tmp);
if (ret < 0)
return ret;
*ambient_old_raw = (s16)read_tmp;
return ret;
}
static int mlx90632_read_object_raw(struct regmap *regmap,
int perform_measurement_ret,
s16 *object_new_raw, s16 *object_old_raw)
{
unsigned int read_tmp;
u8 channel_old = 0;
u8 channel = 0;
s16 read;
int ret;
ret = mlx90632_channel_new_select(perform_measurement_ret, &channel,
&channel_old);
if (ret != 0)
return ret;
ret = regmap_read(regmap, MLX90632_RAM_2(channel), &read_tmp);
if (ret < 0)
return ret;
read = (s16)read_tmp;
ret = regmap_read(regmap, MLX90632_RAM_1(channel), &read_tmp);
if (ret < 0)
return ret;
*object_new_raw = (read + (s16)read_tmp) / 2;
ret = regmap_read(regmap, MLX90632_RAM_2(channel_old), &read_tmp);
if (ret < 0)
return ret;
read = (s16)read_tmp;
ret = regmap_read(regmap, MLX90632_RAM_1(channel_old), &read_tmp);
if (ret < 0)
return ret;
*object_old_raw = (read + (s16)read_tmp) / 2;
return ret;
}
static int mlx90632_read_all_channel(struct mlx90632_data *data,
s16 *ambient_new_raw, s16 *ambient_old_raw,
s16 *object_new_raw, s16 *object_old_raw)
{
s32 measurement;
int ret;
mutex_lock(&data->lock);
ret = mlx90632_set_meas_type(data, MLX90632_MTYP_MEDICAL);
if (ret < 0)
goto read_unlock;
switch (data->powerstatus) {
case MLX90632_PWR_STATUS_CONTINUOUS:
ret = mlx90632_perform_measurement(data);
if (ret < 0)
goto read_unlock;
break;
case MLX90632_PWR_STATUS_SLEEP_STEP:
ret = mlx90632_perform_measurement_burst(data);
if (ret < 0)
goto read_unlock;
break;
default:
ret = -EOPNOTSUPP;
goto read_unlock;
}
measurement = ret; /* If we came here ret holds the measurement position */
ret = mlx90632_read_ambient_raw(data->regmap, ambient_new_raw,
ambient_old_raw);
if (ret < 0)
goto read_unlock;
ret = mlx90632_read_object_raw(data->regmap, measurement,
object_new_raw, object_old_raw);
read_unlock:
mutex_unlock(&data->lock);
return ret;
}
static int mlx90632_read_ambient_raw_extended(struct regmap *regmap,
s16 *ambient_new_raw, s16 *ambient_old_raw)
{
unsigned int read_tmp;
int ret;
ret = regmap_read(regmap, MLX90632_RAM_DSP5_EXTENDED_AMBIENT_1, &read_tmp);
if (ret < 0)
return ret;
*ambient_new_raw = (s16)read_tmp;
ret = regmap_read(regmap, MLX90632_RAM_DSP5_EXTENDED_AMBIENT_2, &read_tmp);
if (ret < 0)
return ret;
*ambient_old_raw = (s16)read_tmp;
return 0;
}
static int mlx90632_read_object_raw_extended(struct regmap *regmap, s16 *object_new_raw)
{
unsigned int read_tmp;
s32 read;
int ret;
ret = regmap_read(regmap, MLX90632_RAM_DSP5_EXTENDED_OBJECT_1, &read_tmp);
if (ret < 0)
return ret;
read = (s16)read_tmp;
ret = regmap_read(regmap, MLX90632_RAM_DSP5_EXTENDED_OBJECT_2, &read_tmp);
if (ret < 0)
return ret;
read = read - (s16)read_tmp;
ret = regmap_read(regmap, MLX90632_RAM_DSP5_EXTENDED_OBJECT_3, &read_tmp);
if (ret < 0)
return ret;
read = read - (s16)read_tmp;
ret = regmap_read(regmap, MLX90632_RAM_DSP5_EXTENDED_OBJECT_4, &read_tmp);
if (ret < 0)
return ret;
read = (read + (s16)read_tmp) / 2;
ret = regmap_read(regmap, MLX90632_RAM_DSP5_EXTENDED_OBJECT_5, &read_tmp);
if (ret < 0)
return ret;
read = read + (s16)read_tmp;
ret = regmap_read(regmap, MLX90632_RAM_DSP5_EXTENDED_OBJECT_6, &read_tmp);
if (ret < 0)
return ret;
read = read + (s16)read_tmp;
if (read > S16_MAX || read < S16_MIN)
return -ERANGE;
*object_new_raw = read;
return 0;
}
static int mlx90632_read_all_channel_extended(struct mlx90632_data *data, s16 *object_new_raw,
s16 *ambient_new_raw, s16 *ambient_old_raw)
{
s32 ret, meas;
mutex_lock(&data->lock);
ret = mlx90632_set_meas_type(data, MLX90632_MTYP_EXTENDED);
if (ret < 0)
goto read_unlock;
switch (data->powerstatus) {
case MLX90632_PWR_STATUS_CONTINUOUS:
ret = read_poll_timeout(mlx90632_perform_measurement, meas, meas == 19,
50000, 800000, false, data);
if (ret)
goto read_unlock;
break;
case MLX90632_PWR_STATUS_SLEEP_STEP:
ret = mlx90632_perform_measurement_burst(data);
if (ret < 0)
goto read_unlock;
break;
default:
ret = -EOPNOTSUPP;
goto read_unlock;
}
ret = mlx90632_read_object_raw_extended(data->regmap, object_new_raw);
if (ret < 0)
goto read_unlock;
ret = mlx90632_read_ambient_raw_extended(data->regmap, ambient_new_raw, ambient_old_raw);
read_unlock:
mutex_unlock(&data->lock);
return ret;
}
static int mlx90632_read_ee_register(struct regmap *regmap, u16 reg_lsb,
s32 *reg_value)
{
unsigned int read;
u32 value;
int ret;
ret = regmap_read(regmap, reg_lsb, &read);
if (ret < 0)
return ret;
value = read;
ret = regmap_read(regmap, reg_lsb + 1, &read);
if (ret < 0)
return ret;
*reg_value = (read << 16) | (value & 0xffff);
return 0;
}
static s64 mlx90632_preprocess_temp_amb(s16 ambient_new_raw,
s16 ambient_old_raw, s16 Gb)
{
s64 VR_Ta, kGb, tmp;
kGb = ((s64)Gb * 1000LL) >> 10ULL;
VR_Ta = (s64)ambient_old_raw * 1000000LL +
kGb * div64_s64(((s64)ambient_new_raw * 1000LL),
(MLX90632_REF_3));
tmp = div64_s64(
div64_s64(((s64)ambient_new_raw * 1000000000000LL),
(MLX90632_REF_3)), VR_Ta);
return div64_s64(tmp << 19ULL, 1000LL);
}
static s64 mlx90632_preprocess_temp_obj(s16 object_new_raw, s16 object_old_raw,
s16 ambient_new_raw,
s16 ambient_old_raw, s16 Ka)
{
s64 VR_IR, kKa, tmp;
kKa = ((s64)Ka * 1000LL) >> 10ULL;
VR_IR = (s64)ambient_old_raw * 1000000LL +
kKa * div64_s64(((s64)ambient_new_raw * 1000LL),
(MLX90632_REF_3));
tmp = div64_s64(
div64_s64(((s64)((object_new_raw + object_old_raw) / 2)
* 1000000000000LL), (MLX90632_REF_12)),
VR_IR);
return div64_s64((tmp << 19ULL), 1000LL);
}
static s64 mlx90632_preprocess_temp_obj_extended(s16 object_new_raw, s16 ambient_new_raw,
s16 ambient_old_raw, s16 Ka)
{
s64 VR_IR, kKa, tmp;
kKa = ((s64)Ka * 1000LL) >> 10ULL;
VR_IR = (s64)ambient_old_raw * 1000000LL +
kKa * div64_s64((s64)ambient_new_raw * 1000LL,
MLX90632_REF_3);
tmp = div64_s64(
div64_s64((s64) object_new_raw * 1000000000000LL, MLX90632_REF_12),
VR_IR);
return div64_s64(tmp << 19ULL, 1000LL);
}
static s32 mlx90632_calc_temp_ambient(s16 ambient_new_raw, s16 ambient_old_raw,
s32 P_T, s32 P_R, s32 P_G, s32 P_O, s16 Gb)
{
s64 Asub, Bsub, Ablock, Bblock, Cblock, AMB, sum;
AMB = mlx90632_preprocess_temp_amb(ambient_new_raw, ambient_old_raw,
Gb);
Asub = ((s64)P_T * 10000000000LL) >> 44ULL;
Bsub = AMB - (((s64)P_R * 1000LL) >> 8ULL);
Ablock = Asub * (Bsub * Bsub);
Bblock = (div64_s64(Bsub * 10000000LL, P_G)) << 20ULL;
Cblock = ((s64)P_O * 10000000000LL) >> 8ULL;
sum = div64_s64(Ablock, 1000000LL) + Bblock + Cblock;
return div64_s64(sum, 10000000LL);
}
static s32 mlx90632_calc_temp_object_iteration(s32 prev_object_temp, s64 object,
s64 TAdut, s64 TAdut4, s32 Fa, s32 Fb,
s32 Ga, s16 Ha, s16 Hb,
u16 emissivity)
{
s64 calcedKsTO, calcedKsTA, ir_Alpha, Alpha_corr;
s64 Ha_customer, Hb_customer;
Ha_customer = ((s64)Ha * 1000000LL) >> 14ULL;
Hb_customer = ((s64)Hb * 100) >> 10ULL;
calcedKsTO = ((s64)((s64)Ga * (prev_object_temp - 25 * 1000LL)
* 1000LL)) >> 36LL;
calcedKsTA = ((s64)(Fb * (TAdut - 25 * 1000000LL))) >> 36LL;
Alpha_corr = div64_s64((((s64)(Fa * 10000000000LL) >> 46LL)
* Ha_customer), 1000LL);
Alpha_corr *= ((s64)(1 * 1000000LL + calcedKsTO + calcedKsTA));
Alpha_corr = emissivity * div64_s64(Alpha_corr, 100000LL);
Alpha_corr = div64_s64(Alpha_corr, 1000LL);
ir_Alpha = div64_s64((s64)object * 10000000LL, Alpha_corr);
return (int_sqrt64(int_sqrt64(ir_Alpha * 1000000000000LL + TAdut4))
- 27315 - Hb_customer) * 10;
}
static s64 mlx90632_calc_ta4(s64 TAdut, s64 scale)
{
return (div64_s64(TAdut, scale) + 27315) *
(div64_s64(TAdut, scale) + 27315) *
(div64_s64(TAdut, scale) + 27315) *
(div64_s64(TAdut, scale) + 27315);
}
static s32 mlx90632_calc_temp_object(s64 object, s64 ambient, s32 Ea, s32 Eb,
s32 Fa, s32 Fb, s32 Ga, s16 Ha, s16 Hb,
u16 tmp_emi)
{
s64 kTA, kTA0, TAdut, TAdut4;
s64 temp = 25000;
s8 i;
kTA = (Ea * 1000LL) >> 16LL;
kTA0 = (Eb * 1000LL) >> 8LL;
TAdut = div64_s64(((ambient - kTA0) * 1000000LL), kTA) + 25 * 1000000LL;
TAdut4 = mlx90632_calc_ta4(TAdut, 10000LL);
/* Iterations of calculation as described in datasheet */
for (i = 0; i < 5; ++i) {
temp = mlx90632_calc_temp_object_iteration(temp, object, TAdut, TAdut4,
Fa, Fb, Ga, Ha, Hb,
tmp_emi);
}
return temp;
}
static s32 mlx90632_calc_temp_object_extended(s64 object, s64 ambient, s64 reflected,
s32 Ea, s32 Eb, s32 Fa, s32 Fb, s32 Ga,
s16 Ha, s16 Hb, u16 tmp_emi)
{
s64 kTA, kTA0, TAdut, TAdut4, Tr4, TaTr4;
s64 temp = 25000;
s8 i;
kTA = (Ea * 1000LL) >> 16LL;
kTA0 = (Eb * 1000LL) >> 8LL;
TAdut = div64_s64((ambient - kTA0) * 1000000LL, kTA) + 25 * 1000000LL;
Tr4 = mlx90632_calc_ta4(reflected, 10);
TAdut4 = mlx90632_calc_ta4(TAdut, 10000LL);
TaTr4 = Tr4 - div64_s64(Tr4 - TAdut4, tmp_emi) * 1000;
/* Iterations of calculation as described in datasheet */
for (i = 0; i < 5; ++i) {
temp = mlx90632_calc_temp_object_iteration(temp, object, TAdut, TaTr4,
Fa / 2, Fb, Ga, Ha, Hb,
tmp_emi);
}
return temp;
}
static int mlx90632_calc_object_dsp105(struct mlx90632_data *data, int *val)
{
s16 ambient_new_raw, ambient_old_raw, object_new_raw, object_old_raw;
s32 Ea, Eb, Fa, Fb, Ga;
unsigned int read_tmp;
s64 object, ambient;
s16 Ha, Hb, Gb, Ka;
int ret;
ret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_Ea, &Ea);
if (ret < 0)
return ret;
ret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_Eb, &Eb);
if (ret < 0)
return ret;
ret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_Fa, &Fa);
if (ret < 0)
return ret;
ret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_Fb, &Fb);
if (ret < 0)
return ret;
ret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_Ga, &Ga);
if (ret < 0)
return ret;
ret = regmap_read(data->regmap, MLX90632_EE_Ha, &read_tmp);
if (ret < 0)
return ret;
Ha = (s16)read_tmp;
ret = regmap_read(data->regmap, MLX90632_EE_Hb, &read_tmp);
if (ret < 0)
return ret;
Hb = (s16)read_tmp;
ret = regmap_read(data->regmap, MLX90632_EE_Gb, &read_tmp);
if (ret < 0)
return ret;
Gb = (s16)read_tmp;
ret = regmap_read(data->regmap, MLX90632_EE_Ka, &read_tmp);
if (ret < 0)
return ret;
Ka = (s16)read_tmp;
ret = mlx90632_read_all_channel(data,
&ambient_new_raw, &ambient_old_raw,
&object_new_raw, &object_old_raw);
if (ret < 0)
return ret;
if (object_new_raw > MLX90632_EXTENDED_LIMIT &&
data->mtyp == MLX90632_MTYP_EXTENDED) {
ret = mlx90632_read_all_channel_extended(data, &object_new_raw,
&ambient_new_raw, &ambient_old_raw);
if (ret < 0)
return ret;
/* Use extended mode calculations */
ambient = mlx90632_preprocess_temp_amb(ambient_new_raw,
ambient_old_raw, Gb);
object = mlx90632_preprocess_temp_obj_extended(object_new_raw,
ambient_new_raw,
ambient_old_raw, Ka);
*val = mlx90632_calc_temp_object_extended(object, ambient,
data->object_ambient_temperature,
Ea, Eb, Fa, Fb, Ga,
Ha, Hb, data->emissivity);
return 0;
}
ambient = mlx90632_preprocess_temp_amb(ambient_new_raw,
ambient_old_raw, Gb);
object = mlx90632_preprocess_temp_obj(object_new_raw,
object_old_raw,
ambient_new_raw,
ambient_old_raw, Ka);
*val = mlx90632_calc_temp_object(object, ambient, Ea, Eb, Fa, Fb, Ga,
Ha, Hb, data->emissivity);
return 0;
}
static int mlx90632_calc_ambient_dsp105(struct mlx90632_data *data, int *val)
{
s16 ambient_new_raw, ambient_old_raw;
unsigned int read_tmp;
s32 PT, PR, PG, PO;
int ret;
s16 Gb;
ret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_P_R, &PR);
if (ret < 0)
return ret;
ret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_P_G, &PG);
if (ret < 0)
return ret;
ret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_P_T, &PT);
if (ret < 0)
return ret;
ret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_P_O, &PO);
if (ret < 0)
return ret;
ret = regmap_read(data->regmap, MLX90632_EE_Gb, &read_tmp);
if (ret < 0)
return ret;
Gb = (s16)read_tmp;
ret = mlx90632_read_ambient_raw(data->regmap, &ambient_new_raw,
&ambient_old_raw);
if (ret < 0)
return ret;
*val = mlx90632_calc_temp_ambient(ambient_new_raw, ambient_old_raw,
PT, PR, PG, PO, Gb);
return ret;
}
static int mlx90632_get_refresh_rate(struct mlx90632_data *data,
int *refresh_rate)
{
unsigned int meas1;
int ret;
ret = regmap_read(data->regmap, MLX90632_EE_MEDICAL_MEAS1, &meas1);
if (ret < 0)
return ret;
*refresh_rate = MLX90632_REFRESH_RATE(meas1);
return ret;
}
static const int mlx90632_freqs[][2] = {
{0, 500000},
{1, 0},
{2, 0},
{4, 0},
{8, 0},
{16, 0},
{32, 0},
{64, 0}
};
/**
* mlx90632_pm_interraction_wakeup() - Measure time between user interactions to change powermode
* @data: pointer to mlx90632_data object containing interaction_ts information
*
* Switch to continuous mode when interaction is faster than MLX90632_MEAS_MAX_TIME. Update the
* interaction_ts for each function call with the jiffies to enable measurement between function
* calls. Initial value of the interaction_ts needs to be set before this function call.
*/
static int mlx90632_pm_interraction_wakeup(struct mlx90632_data *data)
{
unsigned long now;
int ret;
now = jiffies;
if (time_in_range(now, data->interaction_ts,
data->interaction_ts +
msecs_to_jiffies(MLX90632_MEAS_MAX_TIME + 100))) {
if (data->powerstatus == MLX90632_PWR_STATUS_SLEEP_STEP) {
ret = mlx90632_pwr_continuous(data->regmap);
if (ret < 0)
return ret;
}
}
data->interaction_ts = now;
return 0;
}
static int mlx90632_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
struct mlx90632_data *data = iio_priv(indio_dev);
int ret;
int cr;
pm_runtime_get_sync(&data->client->dev);
ret = mlx90632_pm_interraction_wakeup(data);
if (ret < 0)
goto mlx90632_read_raw_pm;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
switch (channel->channel2) {
case IIO_MOD_TEMP_AMBIENT:
ret = mlx90632_calc_ambient_dsp105(data, val);
if (ret < 0)
goto mlx90632_read_raw_pm;
ret = IIO_VAL_INT;
break;
case IIO_MOD_TEMP_OBJECT:
ret = mlx90632_calc_object_dsp105(data, val);
if (ret < 0)
goto mlx90632_read_raw_pm;
ret = IIO_VAL_INT;
break;
default:
ret = -EINVAL;
break;
}
break;
case IIO_CHAN_INFO_CALIBEMISSIVITY:
if (data->emissivity == 1000) {
*val = 1;
*val2 = 0;
} else {
*val = 0;
*val2 = data->emissivity * 1000;
}
ret = IIO_VAL_INT_PLUS_MICRO;
break;
case IIO_CHAN_INFO_CALIBAMBIENT:
*val = data->object_ambient_temperature;
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SAMP_FREQ:
ret = mlx90632_get_refresh_rate(data, &cr);
if (ret < 0)
goto mlx90632_read_raw_pm;
*val = mlx90632_freqs[cr][0];
*val2 = mlx90632_freqs[cr][1];
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
ret = -EINVAL;
break;
}
mlx90632_read_raw_pm:
pm_runtime_mark_last_busy(&data->client->dev);
pm_runtime_put_autosuspend(&data->client->dev);
return ret;
}
static int mlx90632_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int val,
int val2, long mask)
{
struct mlx90632_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_CALIBEMISSIVITY:
/* Confirm we are within 0 and 1.0 */
if (val < 0 || val2 < 0 || val > 1 ||
(val == 1 && val2 != 0))
return -EINVAL;
data->emissivity = val * 1000 + val2 / 1000;
return 0;
case IIO_CHAN_INFO_CALIBAMBIENT:
data->object_ambient_temperature = val;
return 0;
default:
return -EINVAL;
}
}
static int mlx90632_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
*vals = (int *)mlx90632_freqs;
*type = IIO_VAL_INT_PLUS_MICRO;
*length = 2 * ARRAY_SIZE(mlx90632_freqs);
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static const struct iio_chan_spec mlx90632_channels[] = {
{
.type = IIO_TEMP,
.modified = 1,
.channel2 = IIO_MOD_TEMP_AMBIENT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
},
{
.type = IIO_TEMP,
.modified = 1,
.channel2 = IIO_MOD_TEMP_OBJECT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_CALIBEMISSIVITY) | BIT(IIO_CHAN_INFO_CALIBAMBIENT),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
},
};
static const struct iio_info mlx90632_info = {
.read_raw = mlx90632_read_raw,
.write_raw = mlx90632_write_raw,
.read_avail = mlx90632_read_avail,
};
static void mlx90632_sleep(void *_data)
{
struct mlx90632_data *data = _data;
mlx90632_pwr_set_sleep_step(data->regmap);
}
static int mlx90632_suspend(struct mlx90632_data *data)
{
regcache_mark_dirty(data->regmap);
dev_dbg(&data->client->dev, "Requesting suspend");
return mlx90632_pwr_set_sleep_step(data->regmap);
}
static int mlx90632_wakeup(struct mlx90632_data *data)
{
int ret;
ret = regcache_sync(data->regmap);
if (ret < 0) {
dev_err(&data->client->dev,
"Failed to sync regmap registers: %d\n", ret);
return ret;
}
dev_dbg(&data->client->dev, "Requesting wake-up\n");
return mlx90632_pwr_continuous(data->regmap);
}
static void mlx90632_disable_regulator(void *_data)
{
struct mlx90632_data *data = _data;
int ret;
ret = regulator_disable(data->regulator);
if (ret < 0)
dev_err(regmap_get_device(data->regmap),
"Failed to disable power regulator: %d\n", ret);
}
static int mlx90632_enable_regulator(struct mlx90632_data *data)
{
int ret;
ret = regulator_enable(data->regulator);
if (ret < 0) {
dev_err(regmap_get_device(data->regmap), "Failed to enable power regulator!\n");
return ret;
}
mlx90632_reset_delay();
return ret;
}
static int mlx90632_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct mlx90632_data *mlx90632;
struct iio_dev *indio_dev;
struct regmap *regmap;
unsigned int read;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*mlx90632));
if (!indio_dev) {
dev_err(&client->dev, "Failed to allocate device\n");
return -ENOMEM;
}
regmap = devm_regmap_init_i2c(client, &mlx90632_regmap);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
mlx90632 = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
mlx90632->client = client;
mlx90632->regmap = regmap;
mlx90632->mtyp = MLX90632_MTYP_MEDICAL;
mlx90632->powerstatus = MLX90632_PWR_STATUS_HALT;
mutex_init(&mlx90632->lock);
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &mlx90632_info;
indio_dev->channels = mlx90632_channels;
indio_dev->num_channels = ARRAY_SIZE(mlx90632_channels);
mlx90632->regulator = devm_regulator_get(&client->dev, "vdd");
if (IS_ERR(mlx90632->regulator))
return dev_err_probe(&client->dev, PTR_ERR(mlx90632->regulator),
"failed to get vdd regulator");
ret = mlx90632_enable_regulator(mlx90632);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&client->dev, mlx90632_disable_regulator,
mlx90632);
if (ret < 0) {
dev_err(&client->dev, "Failed to setup regulator cleanup action %d\n",
ret);
return ret;
}
ret = mlx90632_wakeup(mlx90632);
if (ret < 0) {
dev_err(&client->dev, "Wakeup failed: %d\n", ret);
return ret;
}
ret = devm_add_action_or_reset(&client->dev, mlx90632_sleep, mlx90632);
if (ret < 0) {
dev_err(&client->dev, "Failed to setup low power cleanup action %d\n",
ret);
return ret;
}
ret = regmap_read(mlx90632->regmap, MLX90632_EE_VERSION, &read);
if (ret < 0) {
dev_err(&client->dev, "read of version failed: %d\n", ret);
return ret;
}
read = read & MLX90632_ID_MASK;
if (read == MLX90632_ID_MEDICAL) {
dev_dbg(&client->dev,
"Detected Medical EEPROM calibration %x\n", read);
} else if (read == MLX90632_ID_CONSUMER) {
dev_dbg(&client->dev,
"Detected Consumer EEPROM calibration %x\n", read);
} else if (read == MLX90632_ID_EXTENDED) {
dev_dbg(&client->dev,
"Detected Extended range EEPROM calibration %x\n", read);
mlx90632->mtyp = MLX90632_MTYP_EXTENDED;
} else if ((read & MLX90632_DSP_MASK) == MLX90632_DSP_VERSION) {
dev_dbg(&client->dev,
"Detected Unknown EEPROM calibration %x\n", read);
} else {
dev_err(&client->dev,
"Wrong DSP version %x (expected %x)\n",
read, MLX90632_DSP_VERSION);
return -EPROTONOSUPPORT;
}
mlx90632->emissivity = 1000;
mlx90632->object_ambient_temperature = 25000; /* 25 degrees milliCelsius */
mlx90632->interaction_ts = jiffies; /* Set initial value */
pm_runtime_get_noresume(&client->dev);
pm_runtime_set_active(&client->dev);
ret = devm_pm_runtime_enable(&client->dev);
if (ret)
return ret;
pm_runtime_set_autosuspend_delay(&client->dev, MLX90632_SLEEP_DELAY_MS);
pm_runtime_use_autosuspend(&client->dev);
pm_runtime_put_autosuspend(&client->dev);
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id mlx90632_id[] = {
{ "mlx90632", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, mlx90632_id);
static const struct of_device_id mlx90632_of_match[] = {
{ .compatible = "melexis,mlx90632" },
{ }
};
MODULE_DEVICE_TABLE(of, mlx90632_of_match);
static int mlx90632_pm_suspend(struct device *dev)
{
struct mlx90632_data *data = iio_priv(dev_get_drvdata(dev));
int ret;
ret = mlx90632_suspend(data);
if (ret < 0)
return ret;
ret = regulator_disable(data->regulator);
if (ret < 0)
dev_err(regmap_get_device(data->regmap),
"Failed to disable power regulator: %d\n", ret);
return ret;
}
static int mlx90632_pm_resume(struct device *dev)
{
struct mlx90632_data *data = iio_priv(dev_get_drvdata(dev));
int ret;
ret = mlx90632_enable_regulator(data);
if (ret < 0)
return ret;
return mlx90632_wakeup(data);
}
static int mlx90632_pm_runtime_suspend(struct device *dev)
{
struct mlx90632_data *data = iio_priv(dev_get_drvdata(dev));
return mlx90632_pwr_set_sleep_step(data->regmap);
}
static const struct dev_pm_ops mlx90632_pm_ops = {
SYSTEM_SLEEP_PM_OPS(mlx90632_pm_suspend, mlx90632_pm_resume)
RUNTIME_PM_OPS(mlx90632_pm_runtime_suspend, NULL, NULL)
};
static struct i2c_driver mlx90632_driver = {
.driver = {
.name = "mlx90632",
.of_match_table = mlx90632_of_match,
.pm = pm_ptr(&mlx90632_pm_ops),
},
.probe = mlx90632_probe,
.id_table = mlx90632_id,
};
module_i2c_driver(mlx90632_driver);
MODULE_AUTHOR("Crt Mori <[email protected]>");
MODULE_DESCRIPTION("Melexis MLX90632 contactless Infra Red temperature sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/temperature/mlx90632.c |
// SPDX-License-Identifier: GPL-2.0
/* max31856.c
*
* Maxim MAX31856 thermocouple sensor driver
*
* Copyright (C) 2018-2019 Rockwell Collins
*/
#include <linux/ctype.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/property.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/util_macros.h>
#include <asm/unaligned.h>
#include <dt-bindings/iio/temperature/thermocouple.h>
/*
* The MSB of the register value determines whether the following byte will
* be written or read. If it is 0, one or more byte reads will follow.
*/
#define MAX31856_RD_WR_BIT BIT(7)
#define MAX31856_CR0_AUTOCONVERT BIT(7)
#define MAX31856_CR0_1SHOT BIT(6)
#define MAX31856_CR0_OCFAULT BIT(4)
#define MAX31856_CR0_OCFAULT_MASK GENMASK(5, 4)
#define MAX31856_CR0_FILTER_50HZ BIT(0)
#define MAX31856_AVERAGING_MASK GENMASK(6, 4)
#define MAX31856_AVERAGING_SHIFT 4
#define MAX31856_TC_TYPE_MASK GENMASK(3, 0)
#define MAX31856_FAULT_OVUV BIT(1)
#define MAX31856_FAULT_OPEN BIT(0)
/* The MAX31856 registers */
#define MAX31856_CR0_REG 0x00
#define MAX31856_CR1_REG 0x01
#define MAX31856_MASK_REG 0x02
#define MAX31856_CJHF_REG 0x03
#define MAX31856_CJLF_REG 0x04
#define MAX31856_LTHFTH_REG 0x05
#define MAX31856_LTHFTL_REG 0x06
#define MAX31856_LTLFTH_REG 0x07
#define MAX31856_LTLFTL_REG 0x08
#define MAX31856_CJTO_REG 0x09
#define MAX31856_CJTH_REG 0x0A
#define MAX31856_CJTL_REG 0x0B
#define MAX31856_LTCBH_REG 0x0C
#define MAX31856_LTCBM_REG 0x0D
#define MAX31856_LTCBL_REG 0x0E
#define MAX31856_SR_REG 0x0F
static const struct iio_chan_spec max31856_channels[] = {
{ /* Thermocouple Temperature */
.type = IIO_TEMP,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_THERMOCOUPLE_TYPE),
.info_mask_shared_by_type =
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)
},
{ /* Cold Junction Temperature */
.type = IIO_TEMP,
.channel2 = IIO_MOD_TEMP_AMBIENT,
.modified = 1,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_type =
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)
},
};
struct max31856_data {
struct spi_device *spi;
u32 thermocouple_type;
bool filter_50hz;
int averaging;
};
static const char max31856_tc_types[] = {
'B', 'E', 'J', 'K', 'N', 'R', 'S', 'T'
};
static int max31856_read(struct max31856_data *data, u8 reg,
u8 val[], unsigned int read_size)
{
return spi_write_then_read(data->spi, ®, 1, val, read_size);
}
static int max31856_write(struct max31856_data *data, u8 reg,
unsigned int val)
{
u8 buf[2];
buf[0] = reg | (MAX31856_RD_WR_BIT);
buf[1] = val;
return spi_write(data->spi, buf, 2);
}
static int max31856_init(struct max31856_data *data)
{
int ret;
u8 reg_cr0_val, reg_cr1_val;
/* Start by changing to Off mode before making changes as
* some settings are recommended to be set only when the device
* is off
*/
ret = max31856_read(data, MAX31856_CR0_REG, ®_cr0_val, 1);
if (ret)
return ret;
reg_cr0_val &= ~MAX31856_CR0_AUTOCONVERT;
ret = max31856_write(data, MAX31856_CR0_REG, reg_cr0_val);
if (ret)
return ret;
/* Set thermocouple type based on dts property */
ret = max31856_read(data, MAX31856_CR1_REG, ®_cr1_val, 1);
if (ret)
return ret;
reg_cr1_val &= ~MAX31856_TC_TYPE_MASK;
reg_cr1_val |= data->thermocouple_type;
reg_cr1_val &= ~MAX31856_AVERAGING_MASK;
reg_cr1_val |= data->averaging << MAX31856_AVERAGING_SHIFT;
ret = max31856_write(data, MAX31856_CR1_REG, reg_cr1_val);
if (ret)
return ret;
/*
* Enable Open circuit fault detection
* Read datasheet for more information: Table 4.
* Value 01 means : Enabled (Once every 16 conversions)
*/
reg_cr0_val &= ~MAX31856_CR0_OCFAULT_MASK;
reg_cr0_val |= MAX31856_CR0_OCFAULT;
/* Set Auto Conversion Mode */
reg_cr0_val &= ~MAX31856_CR0_1SHOT;
reg_cr0_val |= MAX31856_CR0_AUTOCONVERT;
if (data->filter_50hz)
reg_cr0_val |= MAX31856_CR0_FILTER_50HZ;
else
reg_cr0_val &= ~MAX31856_CR0_FILTER_50HZ;
return max31856_write(data, MAX31856_CR0_REG, reg_cr0_val);
}
static int max31856_thermocouple_read(struct max31856_data *data,
struct iio_chan_spec const *chan,
int *val)
{
int ret, offset_cjto;
u8 reg_val[3];
switch (chan->channel2) {
case IIO_NO_MOD:
/*
* Multibyte Read
* MAX31856_LTCBH_REG, MAX31856_LTCBM_REG, MAX31856_LTCBL_REG
*/
ret = max31856_read(data, MAX31856_LTCBH_REG, reg_val, 3);
if (ret)
return ret;
/* Skip last 5 dead bits of LTCBL */
*val = get_unaligned_be24(®_val[0]) >> 5;
/* Check 7th bit of LTCBH reg. value for sign*/
if (reg_val[0] & 0x80)
*val -= 0x80000;
break;
case IIO_MOD_TEMP_AMBIENT:
/*
* Multibyte Read
* MAX31856_CJTO_REG, MAX31856_CJTH_REG, MAX31856_CJTL_REG
*/
ret = max31856_read(data, MAX31856_CJTO_REG, reg_val, 3);
if (ret)
return ret;
/* Get Cold Junction Temp. offset register value */
offset_cjto = reg_val[0];
/* Get CJTH and CJTL value and skip last 2 dead bits of CJTL */
*val = get_unaligned_be16(®_val[1]) >> 2;
/* As per datasheet add offset into CJTH and CJTL */
*val += offset_cjto;
/* Check 7th bit of CJTH reg. value for sign */
if (reg_val[1] & 0x80)
*val -= 0x4000;
break;
default:
return -EINVAL;
}
ret = max31856_read(data, MAX31856_SR_REG, reg_val, 1);
if (ret)
return ret;
/* Check for over/under voltage or open circuit fault */
if (reg_val[0] & (MAX31856_FAULT_OVUV | MAX31856_FAULT_OPEN))
return -EIO;
return ret;
}
static int max31856_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct max31856_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = max31856_thermocouple_read(data, chan, val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
switch (chan->channel2) {
case IIO_MOD_TEMP_AMBIENT:
/* Cold junction Temp. Data resolution is 0.015625 */
*val = 15;
*val2 = 625000; /* 1000 * 0.015625 */
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
/* Thermocouple Temp. Data resolution is 0.0078125 */
*val = 7;
*val2 = 812500; /* 1000 * 0.0078125) */
return IIO_VAL_INT_PLUS_MICRO;
}
break;
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
*val = 1 << data->averaging;
return IIO_VAL_INT;
case IIO_CHAN_INFO_THERMOCOUPLE_TYPE:
*val = max31856_tc_types[data->thermocouple_type];
return IIO_VAL_CHAR;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int max31856_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_THERMOCOUPLE_TYPE:
return IIO_VAL_CHAR;
default:
return IIO_VAL_INT;
}
}
static int max31856_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct max31856_data *data = iio_priv(indio_dev);
int msb;
switch (mask) {
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
if (val > 16 || val < 1)
return -EINVAL;
msb = fls(val) - 1;
/* Round up to next 2pow if needed */
if (BIT(msb) < val)
msb++;
data->averaging = msb;
max31856_init(data);
break;
case IIO_CHAN_INFO_THERMOCOUPLE_TYPE:
{
int tc_type = -1;
int i;
for (i = 0; i < ARRAY_SIZE(max31856_tc_types); i++) {
if (max31856_tc_types[i] == toupper(val)) {
tc_type = i;
break;
}
}
if (tc_type < 0)
return -EINVAL;
data->thermocouple_type = tc_type;
max31856_init(data);
break;
}
default:
return -EINVAL;
}
return 0;
}
static ssize_t show_fault(struct device *dev, u8 faultbit, char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct max31856_data *data = iio_priv(indio_dev);
u8 reg_val;
int ret;
bool fault;
ret = max31856_read(data, MAX31856_SR_REG, ®_val, 1);
if (ret)
return ret;
fault = reg_val & faultbit;
return sysfs_emit(buf, "%d\n", fault);
}
static ssize_t show_fault_ovuv(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return show_fault(dev, MAX31856_FAULT_OVUV, buf);
}
static ssize_t show_fault_oc(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return show_fault(dev, MAX31856_FAULT_OPEN, buf);
}
static ssize_t show_filter(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct max31856_data *data = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", data->filter_50hz ? 50 : 60);
}
static ssize_t set_filter(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct max31856_data *data = iio_priv(indio_dev);
unsigned int freq;
int ret;
ret = kstrtouint(buf, 10, &freq);
if (ret)
return ret;
switch (freq) {
case 50:
data->filter_50hz = true;
break;
case 60:
data->filter_50hz = false;
break;
default:
return -EINVAL;
}
max31856_init(data);
return len;
}
static IIO_DEVICE_ATTR(fault_ovuv, 0444, show_fault_ovuv, NULL, 0);
static IIO_DEVICE_ATTR(fault_oc, 0444, show_fault_oc, NULL, 0);
static IIO_DEVICE_ATTR(in_temp_filter_notch_center_frequency, 0644,
show_filter, set_filter, 0);
static struct attribute *max31856_attributes[] = {
&iio_dev_attr_fault_ovuv.dev_attr.attr,
&iio_dev_attr_fault_oc.dev_attr.attr,
&iio_dev_attr_in_temp_filter_notch_center_frequency.dev_attr.attr,
NULL,
};
static const struct attribute_group max31856_group = {
.attrs = max31856_attributes,
};
static const struct iio_info max31856_info = {
.read_raw = max31856_read_raw,
.write_raw = max31856_write_raw,
.write_raw_get_fmt = max31856_write_raw_get_fmt,
.attrs = &max31856_group,
};
static int max31856_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct iio_dev *indio_dev;
struct max31856_data *data;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->spi = spi;
data->filter_50hz = false;
spi_set_drvdata(spi, indio_dev);
indio_dev->info = &max31856_info;
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = max31856_channels;
indio_dev->num_channels = ARRAY_SIZE(max31856_channels);
ret = device_property_read_u32(&spi->dev, "thermocouple-type", &data->thermocouple_type);
if (ret) {
dev_info(&spi->dev,
"Could not read thermocouple type DT property, configuring as a K-Type\n");
data->thermocouple_type = THERMOCOUPLE_TYPE_K;
}
/*
* no need to translate values as the supported types
* have the same value as the #defines
*/
switch (data->thermocouple_type) {
case THERMOCOUPLE_TYPE_B:
case THERMOCOUPLE_TYPE_E:
case THERMOCOUPLE_TYPE_J:
case THERMOCOUPLE_TYPE_K:
case THERMOCOUPLE_TYPE_N:
case THERMOCOUPLE_TYPE_R:
case THERMOCOUPLE_TYPE_S:
case THERMOCOUPLE_TYPE_T:
break;
default:
dev_err(&spi->dev,
"error: thermocouple-type %u not supported by max31856\n"
, data->thermocouple_type);
return -EINVAL;
}
ret = max31856_init(data);
if (ret) {
dev_err(&spi->dev, "error: Failed to configure max31856\n");
return ret;
}
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id max31856_id[] = {
{ "max31856", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, max31856_id);
static const struct of_device_id max31856_of_match[] = {
{ .compatible = "maxim,max31856" },
{ }
};
MODULE_DEVICE_TABLE(of, max31856_of_match);
static struct spi_driver max31856_driver = {
.driver = {
.name = "max31856",
.of_match_table = max31856_of_match,
},
.probe = max31856_probe,
.id_table = max31856_id,
};
module_spi_driver(max31856_driver);
MODULE_AUTHOR("Paresh Chaudhary <[email protected]>");
MODULE_AUTHOR("Patrick Havelange <[email protected]>");
MODULE_DESCRIPTION("Maxim MAX31856 thermocouple sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/temperature/max31856.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices LTC2983 Multi-Sensor Digital Temperature Measurement System
* driver
*
* Copyright 2019 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/completion.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/iio/iio.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
/* register map */
#define LTC2983_STATUS_REG 0x0000
#define LTC2983_TEMP_RES_START_REG 0x0010
#define LTC2983_TEMP_RES_END_REG 0x005F
#define LTC2983_EEPROM_KEY_REG 0x00B0
#define LTC2983_EEPROM_READ_STATUS_REG 0x00D0
#define LTC2983_GLOBAL_CONFIG_REG 0x00F0
#define LTC2983_MULT_CHANNEL_START_REG 0x00F4
#define LTC2983_MULT_CHANNEL_END_REG 0x00F7
#define LTC2986_EEPROM_STATUS_REG 0x00F9
#define LTC2983_MUX_CONFIG_REG 0x00FF
#define LTC2983_CHAN_ASSIGN_START_REG 0x0200
#define LTC2983_CHAN_ASSIGN_END_REG 0x024F
#define LTC2983_CUST_SENS_TBL_START_REG 0x0250
#define LTC2983_CUST_SENS_TBL_END_REG 0x03CF
#define LTC2983_DIFFERENTIAL_CHAN_MIN 2
#define LTC2983_MIN_CHANNELS_NR 1
#define LTC2983_SLEEP 0x97
#define LTC2983_CUSTOM_STEINHART_SIZE 24
#define LTC2983_CUSTOM_SENSOR_ENTRY_SZ 6
#define LTC2983_CUSTOM_STEINHART_ENTRY_SZ 4
#define LTC2983_EEPROM_KEY 0xA53C0F5A
#define LTC2983_EEPROM_WRITE_CMD 0x15
#define LTC2983_EEPROM_READ_CMD 0x16
#define LTC2983_EEPROM_STATUS_FAILURE_MASK GENMASK(3, 1)
#define LTC2983_EEPROM_READ_FAILURE_MASK GENMASK(7, 0)
#define LTC2983_EEPROM_WRITE_TIME_MS 2600
#define LTC2983_EEPROM_READ_TIME_MS 20
#define LTC2983_CHAN_START_ADDR(chan) \
(((chan - 1) * 4) + LTC2983_CHAN_ASSIGN_START_REG)
#define LTC2983_CHAN_RES_ADDR(chan) \
(((chan - 1) * 4) + LTC2983_TEMP_RES_START_REG)
#define LTC2983_THERMOCOUPLE_DIFF_MASK BIT(3)
#define LTC2983_THERMOCOUPLE_SGL(x) \
FIELD_PREP(LTC2983_THERMOCOUPLE_DIFF_MASK, x)
#define LTC2983_THERMOCOUPLE_OC_CURR_MASK GENMASK(1, 0)
#define LTC2983_THERMOCOUPLE_OC_CURR(x) \
FIELD_PREP(LTC2983_THERMOCOUPLE_OC_CURR_MASK, x)
#define LTC2983_THERMOCOUPLE_OC_CHECK_MASK BIT(2)
#define LTC2983_THERMOCOUPLE_OC_CHECK(x) \
FIELD_PREP(LTC2983_THERMOCOUPLE_OC_CHECK_MASK, x)
#define LTC2983_THERMISTOR_DIFF_MASK BIT(2)
#define LTC2983_THERMISTOR_SGL(x) \
FIELD_PREP(LTC2983_THERMISTOR_DIFF_MASK, x)
#define LTC2983_THERMISTOR_R_SHARE_MASK BIT(1)
#define LTC2983_THERMISTOR_R_SHARE(x) \
FIELD_PREP(LTC2983_THERMISTOR_R_SHARE_MASK, x)
#define LTC2983_THERMISTOR_C_ROTATE_MASK BIT(0)
#define LTC2983_THERMISTOR_C_ROTATE(x) \
FIELD_PREP(LTC2983_THERMISTOR_C_ROTATE_MASK, x)
#define LTC2983_DIODE_DIFF_MASK BIT(2)
#define LTC2983_DIODE_SGL(x) \
FIELD_PREP(LTC2983_DIODE_DIFF_MASK, x)
#define LTC2983_DIODE_3_CONV_CYCLE_MASK BIT(1)
#define LTC2983_DIODE_3_CONV_CYCLE(x) \
FIELD_PREP(LTC2983_DIODE_3_CONV_CYCLE_MASK, x)
#define LTC2983_DIODE_AVERAGE_ON_MASK BIT(0)
#define LTC2983_DIODE_AVERAGE_ON(x) \
FIELD_PREP(LTC2983_DIODE_AVERAGE_ON_MASK, x)
#define LTC2983_RTD_4_WIRE_MASK BIT(3)
#define LTC2983_RTD_ROTATION_MASK BIT(1)
#define LTC2983_RTD_C_ROTATE(x) \
FIELD_PREP(LTC2983_RTD_ROTATION_MASK, x)
#define LTC2983_RTD_KELVIN_R_SENSE_MASK GENMASK(3, 2)
#define LTC2983_RTD_N_WIRES_MASK GENMASK(3, 2)
#define LTC2983_RTD_N_WIRES(x) \
FIELD_PREP(LTC2983_RTD_N_WIRES_MASK, x)
#define LTC2983_RTD_R_SHARE_MASK BIT(0)
#define LTC2983_RTD_R_SHARE(x) \
FIELD_PREP(LTC2983_RTD_R_SHARE_MASK, 1)
#define LTC2983_COMMON_HARD_FAULT_MASK GENMASK(31, 30)
#define LTC2983_COMMON_SOFT_FAULT_MASK GENMASK(27, 25)
#define LTC2983_STATUS_START_MASK BIT(7)
#define LTC2983_STATUS_START(x) FIELD_PREP(LTC2983_STATUS_START_MASK, x)
#define LTC2983_STATUS_UP_MASK GENMASK(7, 6)
#define LTC2983_STATUS_UP(reg) FIELD_GET(LTC2983_STATUS_UP_MASK, reg)
#define LTC2983_STATUS_CHAN_SEL_MASK GENMASK(4, 0)
#define LTC2983_STATUS_CHAN_SEL(x) \
FIELD_PREP(LTC2983_STATUS_CHAN_SEL_MASK, x)
#define LTC2983_TEMP_UNITS_MASK BIT(2)
#define LTC2983_TEMP_UNITS(x) FIELD_PREP(LTC2983_TEMP_UNITS_MASK, x)
#define LTC2983_NOTCH_FREQ_MASK GENMASK(1, 0)
#define LTC2983_NOTCH_FREQ(x) FIELD_PREP(LTC2983_NOTCH_FREQ_MASK, x)
#define LTC2983_RES_VALID_MASK BIT(24)
#define LTC2983_DATA_MASK GENMASK(23, 0)
#define LTC2983_DATA_SIGN_BIT 23
#define LTC2983_CHAN_TYPE_MASK GENMASK(31, 27)
#define LTC2983_CHAN_TYPE(x) FIELD_PREP(LTC2983_CHAN_TYPE_MASK, x)
/* cold junction for thermocouples and rsense for rtd's and thermistor's */
#define LTC2983_CHAN_ASSIGN_MASK GENMASK(26, 22)
#define LTC2983_CHAN_ASSIGN(x) FIELD_PREP(LTC2983_CHAN_ASSIGN_MASK, x)
#define LTC2983_CUSTOM_LEN_MASK GENMASK(5, 0)
#define LTC2983_CUSTOM_LEN(x) FIELD_PREP(LTC2983_CUSTOM_LEN_MASK, x)
#define LTC2983_CUSTOM_ADDR_MASK GENMASK(11, 6)
#define LTC2983_CUSTOM_ADDR(x) FIELD_PREP(LTC2983_CUSTOM_ADDR_MASK, x)
#define LTC2983_THERMOCOUPLE_CFG_MASK GENMASK(21, 18)
#define LTC2983_THERMOCOUPLE_CFG(x) \
FIELD_PREP(LTC2983_THERMOCOUPLE_CFG_MASK, x)
#define LTC2983_THERMOCOUPLE_HARD_FAULT_MASK GENMASK(31, 29)
#define LTC2983_THERMOCOUPLE_SOFT_FAULT_MASK GENMASK(28, 25)
#define LTC2983_RTD_CFG_MASK GENMASK(21, 18)
#define LTC2983_RTD_CFG(x) FIELD_PREP(LTC2983_RTD_CFG_MASK, x)
#define LTC2983_RTD_EXC_CURRENT_MASK GENMASK(17, 14)
#define LTC2983_RTD_EXC_CURRENT(x) \
FIELD_PREP(LTC2983_RTD_EXC_CURRENT_MASK, x)
#define LTC2983_RTD_CURVE_MASK GENMASK(13, 12)
#define LTC2983_RTD_CURVE(x) FIELD_PREP(LTC2983_RTD_CURVE_MASK, x)
#define LTC2983_THERMISTOR_CFG_MASK GENMASK(21, 19)
#define LTC2983_THERMISTOR_CFG(x) \
FIELD_PREP(LTC2983_THERMISTOR_CFG_MASK, x)
#define LTC2983_THERMISTOR_EXC_CURRENT_MASK GENMASK(18, 15)
#define LTC2983_THERMISTOR_EXC_CURRENT(x) \
FIELD_PREP(LTC2983_THERMISTOR_EXC_CURRENT_MASK, x)
#define LTC2983_DIODE_CFG_MASK GENMASK(26, 24)
#define LTC2983_DIODE_CFG(x) FIELD_PREP(LTC2983_DIODE_CFG_MASK, x)
#define LTC2983_DIODE_EXC_CURRENT_MASK GENMASK(23, 22)
#define LTC2983_DIODE_EXC_CURRENT(x) \
FIELD_PREP(LTC2983_DIODE_EXC_CURRENT_MASK, x)
#define LTC2983_DIODE_IDEAL_FACTOR_MASK GENMASK(21, 0)
#define LTC2983_DIODE_IDEAL_FACTOR(x) \
FIELD_PREP(LTC2983_DIODE_IDEAL_FACTOR_MASK, x)
#define LTC2983_R_SENSE_VAL_MASK GENMASK(26, 0)
#define LTC2983_R_SENSE_VAL(x) FIELD_PREP(LTC2983_R_SENSE_VAL_MASK, x)
#define LTC2983_ADC_SINGLE_ENDED_MASK BIT(26)
#define LTC2983_ADC_SINGLE_ENDED(x) \
FIELD_PREP(LTC2983_ADC_SINGLE_ENDED_MASK, x)
enum {
LTC2983_SENSOR_THERMOCOUPLE = 1,
LTC2983_SENSOR_THERMOCOUPLE_CUSTOM = 9,
LTC2983_SENSOR_RTD = 10,
LTC2983_SENSOR_RTD_CUSTOM = 18,
LTC2983_SENSOR_THERMISTOR = 19,
LTC2983_SENSOR_THERMISTOR_STEINHART = 26,
LTC2983_SENSOR_THERMISTOR_CUSTOM = 27,
LTC2983_SENSOR_DIODE = 28,
LTC2983_SENSOR_SENSE_RESISTOR = 29,
LTC2983_SENSOR_DIRECT_ADC = 30,
LTC2983_SENSOR_ACTIVE_TEMP = 31,
};
#define to_thermocouple(_sensor) \
container_of(_sensor, struct ltc2983_thermocouple, sensor)
#define to_rtd(_sensor) \
container_of(_sensor, struct ltc2983_rtd, sensor)
#define to_thermistor(_sensor) \
container_of(_sensor, struct ltc2983_thermistor, sensor)
#define to_diode(_sensor) \
container_of(_sensor, struct ltc2983_diode, sensor)
#define to_rsense(_sensor) \
container_of(_sensor, struct ltc2983_rsense, sensor)
#define to_adc(_sensor) \
container_of(_sensor, struct ltc2983_adc, sensor)
#define to_temp(_sensor) \
container_of(_sensor, struct ltc2983_temp, sensor)
struct ltc2983_chip_info {
unsigned int max_channels_nr;
bool has_temp;
bool has_eeprom;
};
struct ltc2983_data {
const struct ltc2983_chip_info *info;
struct regmap *regmap;
struct spi_device *spi;
struct mutex lock;
struct completion completion;
struct iio_chan_spec *iio_chan;
struct ltc2983_sensor **sensors;
u32 mux_delay_config;
u32 filter_notch_freq;
u16 custom_table_size;
u8 num_channels;
u8 iio_channels;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
* Holds the converted temperature
*/
__be32 temp __aligned(IIO_DMA_MINALIGN);
__be32 chan_val;
__be32 eeprom_key;
};
struct ltc2983_sensor {
int (*fault_handler)(const struct ltc2983_data *st, const u32 result);
int (*assign_chan)(struct ltc2983_data *st,
const struct ltc2983_sensor *sensor);
/* specifies the sensor channel */
u32 chan;
/* sensor type */
u32 type;
};
struct ltc2983_custom_sensor {
/* raw table sensor data */
void *table;
size_t size;
/* address offset */
s8 offset;
bool is_steinhart;
};
struct ltc2983_thermocouple {
struct ltc2983_sensor sensor;
struct ltc2983_custom_sensor *custom;
u32 sensor_config;
u32 cold_junction_chan;
};
struct ltc2983_rtd {
struct ltc2983_sensor sensor;
struct ltc2983_custom_sensor *custom;
u32 sensor_config;
u32 r_sense_chan;
u32 excitation_current;
u32 rtd_curve;
};
struct ltc2983_thermistor {
struct ltc2983_sensor sensor;
struct ltc2983_custom_sensor *custom;
u32 sensor_config;
u32 r_sense_chan;
u32 excitation_current;
};
struct ltc2983_diode {
struct ltc2983_sensor sensor;
u32 sensor_config;
u32 excitation_current;
u32 ideal_factor_value;
};
struct ltc2983_rsense {
struct ltc2983_sensor sensor;
u32 r_sense_val;
};
struct ltc2983_adc {
struct ltc2983_sensor sensor;
bool single_ended;
};
struct ltc2983_temp {
struct ltc2983_sensor sensor;
struct ltc2983_custom_sensor *custom;
bool single_ended;
};
/*
* Convert to Q format numbers. These number's are integers where
* the number of integer and fractional bits are specified. The resolution
* is given by 1/@resolution and tell us the number of fractional bits. For
* instance a resolution of 2^-10 means we have 10 fractional bits.
*/
static u32 __convert_to_raw(const u64 val, const u32 resolution)
{
u64 __res = val * resolution;
/* all values are multiplied by 1000000 to remove the fraction */
do_div(__res, 1000000);
return __res;
}
static u32 __convert_to_raw_sign(const u64 val, const u32 resolution)
{
s64 __res = -(s32)val;
__res = __convert_to_raw(__res, resolution);
return (u32)-__res;
}
static int __ltc2983_fault_handler(const struct ltc2983_data *st,
const u32 result, const u32 hard_mask,
const u32 soft_mask)
{
const struct device *dev = &st->spi->dev;
if (result & hard_mask) {
dev_err(dev, "Invalid conversion: Sensor HARD fault\n");
return -EIO;
} else if (result & soft_mask) {
/* just print a warning */
dev_warn(dev, "Suspicious conversion: Sensor SOFT fault\n");
}
return 0;
}
static int __ltc2983_chan_assign_common(struct ltc2983_data *st,
const struct ltc2983_sensor *sensor,
u32 chan_val)
{
u32 reg = LTC2983_CHAN_START_ADDR(sensor->chan);
chan_val |= LTC2983_CHAN_TYPE(sensor->type);
dev_dbg(&st->spi->dev, "Assign reg:0x%04X, val:0x%08X\n", reg,
chan_val);
st->chan_val = cpu_to_be32(chan_val);
return regmap_bulk_write(st->regmap, reg, &st->chan_val,
sizeof(st->chan_val));
}
static int __ltc2983_chan_custom_sensor_assign(struct ltc2983_data *st,
struct ltc2983_custom_sensor *custom,
u32 *chan_val)
{
u32 reg;
u8 mult = custom->is_steinhart ? LTC2983_CUSTOM_STEINHART_ENTRY_SZ :
LTC2983_CUSTOM_SENSOR_ENTRY_SZ;
const struct device *dev = &st->spi->dev;
/*
* custom->size holds the raw size of the table. However, when
* configuring the sensor channel, we must write the number of
* entries of the table minus 1. For steinhart sensors 0 is written
* since the size is constant!
*/
const u8 len = custom->is_steinhart ? 0 :
(custom->size / LTC2983_CUSTOM_SENSOR_ENTRY_SZ) - 1;
/*
* Check if the offset was assigned already. It should be for steinhart
* sensors. When coming from sleep, it should be assigned for all.
*/
if (custom->offset < 0) {
/*
* This needs to be done again here because, from the moment
* when this test was done (successfully) for this custom
* sensor, a steinhart sensor might have been added changing
* custom_table_size...
*/
if (st->custom_table_size + custom->size >
(LTC2983_CUST_SENS_TBL_END_REG -
LTC2983_CUST_SENS_TBL_START_REG) + 1) {
dev_err(dev,
"Not space left(%d) for new custom sensor(%zu)",
st->custom_table_size,
custom->size);
return -EINVAL;
}
custom->offset = st->custom_table_size /
LTC2983_CUSTOM_SENSOR_ENTRY_SZ;
st->custom_table_size += custom->size;
}
reg = (custom->offset * mult) + LTC2983_CUST_SENS_TBL_START_REG;
*chan_val |= LTC2983_CUSTOM_LEN(len);
*chan_val |= LTC2983_CUSTOM_ADDR(custom->offset);
dev_dbg(dev, "Assign custom sensor, reg:0x%04X, off:%d, sz:%zu",
reg, custom->offset,
custom->size);
/* write custom sensor table */
return regmap_bulk_write(st->regmap, reg, custom->table, custom->size);
}
static struct ltc2983_custom_sensor *
__ltc2983_custom_sensor_new(struct ltc2983_data *st, const struct fwnode_handle *fn,
const char *propname, const bool is_steinhart,
const u32 resolution, const bool has_signed)
{
struct ltc2983_custom_sensor *new_custom;
struct device *dev = &st->spi->dev;
/*
* For custom steinhart, the full u32 is taken. For all the others
* the MSB is discarded.
*/
const u8 n_size = is_steinhart ? 4 : 3;
u8 index, n_entries;
int ret;
if (is_steinhart)
n_entries = fwnode_property_count_u32(fn, propname);
else
n_entries = fwnode_property_count_u64(fn, propname);
/* n_entries must be an even number */
if (!n_entries || (n_entries % 2) != 0) {
dev_err(dev, "Number of entries either 0 or not even\n");
return ERR_PTR(-EINVAL);
}
new_custom = devm_kzalloc(dev, sizeof(*new_custom), GFP_KERNEL);
if (!new_custom)
return ERR_PTR(-ENOMEM);
new_custom->size = n_entries * n_size;
/* check Steinhart size */
if (is_steinhart && new_custom->size != LTC2983_CUSTOM_STEINHART_SIZE) {
dev_err(dev, "Steinhart sensors size(%zu) must be %u\n", new_custom->size,
LTC2983_CUSTOM_STEINHART_SIZE);
return ERR_PTR(-EINVAL);
}
/* Check space on the table. */
if (st->custom_table_size + new_custom->size >
(LTC2983_CUST_SENS_TBL_END_REG -
LTC2983_CUST_SENS_TBL_START_REG) + 1) {
dev_err(dev, "No space left(%d) for new custom sensor(%zu)",
st->custom_table_size, new_custom->size);
return ERR_PTR(-EINVAL);
}
/* allocate the table */
if (is_steinhart)
new_custom->table = devm_kcalloc(dev, n_entries, sizeof(u32), GFP_KERNEL);
else
new_custom->table = devm_kcalloc(dev, n_entries, sizeof(u64), GFP_KERNEL);
if (!new_custom->table)
return ERR_PTR(-ENOMEM);
/*
* Steinhart sensors are configured with raw values in the firmware
* node. For the other sensors we must convert the value to raw.
* The odd index's correspond to temperatures and always have 1/1024
* of resolution. Temperatures also come in Kelvin, so signed values
* are not possible.
*/
if (is_steinhart) {
ret = fwnode_property_read_u32_array(fn, propname, new_custom->table, n_entries);
if (ret < 0)
return ERR_PTR(ret);
cpu_to_be32_array(new_custom->table, new_custom->table, n_entries);
} else {
ret = fwnode_property_read_u64_array(fn, propname, new_custom->table, n_entries);
if (ret < 0)
return ERR_PTR(ret);
for (index = 0; index < n_entries; index++) {
u64 temp = ((u64 *)new_custom->table)[index];
if ((index % 2) != 0)
temp = __convert_to_raw(temp, 1024);
else if (has_signed && (s64)temp < 0)
temp = __convert_to_raw_sign(temp, resolution);
else
temp = __convert_to_raw(temp, resolution);
put_unaligned_be24(temp, new_custom->table + index * 3);
}
}
new_custom->is_steinhart = is_steinhart;
/*
* This is done to first add all the steinhart sensors to the table,
* in order to maximize the table usage. If we mix adding steinhart
* with the other sensors, we might have to do some roundup to make
* sure that sensor_addr - 0x250(start address) is a multiple of 4
* (for steinhart), and a multiple of 6 for all the other sensors.
* Since we have const 24 bytes for steinhart sensors and 24 is
* also a multiple of 6, we guarantee that the first non-steinhart
* sensor will sit in a correct address without the need of filling
* addresses.
*/
if (is_steinhart) {
new_custom->offset = st->custom_table_size /
LTC2983_CUSTOM_STEINHART_ENTRY_SZ;
st->custom_table_size += new_custom->size;
} else {
/* mark as unset. This is checked later on the assign phase */
new_custom->offset = -1;
}
return new_custom;
}
static int ltc2983_thermocouple_fault_handler(const struct ltc2983_data *st,
const u32 result)
{
return __ltc2983_fault_handler(st, result,
LTC2983_THERMOCOUPLE_HARD_FAULT_MASK,
LTC2983_THERMOCOUPLE_SOFT_FAULT_MASK);
}
static int ltc2983_common_fault_handler(const struct ltc2983_data *st,
const u32 result)
{
return __ltc2983_fault_handler(st, result,
LTC2983_COMMON_HARD_FAULT_MASK,
LTC2983_COMMON_SOFT_FAULT_MASK);
}
static int ltc2983_thermocouple_assign_chan(struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_thermocouple *thermo = to_thermocouple(sensor);
u32 chan_val;
chan_val = LTC2983_CHAN_ASSIGN(thermo->cold_junction_chan);
chan_val |= LTC2983_THERMOCOUPLE_CFG(thermo->sensor_config);
if (thermo->custom) {
int ret;
ret = __ltc2983_chan_custom_sensor_assign(st, thermo->custom,
&chan_val);
if (ret)
return ret;
}
return __ltc2983_chan_assign_common(st, sensor, chan_val);
}
static int ltc2983_rtd_assign_chan(struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_rtd *rtd = to_rtd(sensor);
u32 chan_val;
chan_val = LTC2983_CHAN_ASSIGN(rtd->r_sense_chan);
chan_val |= LTC2983_RTD_CFG(rtd->sensor_config);
chan_val |= LTC2983_RTD_EXC_CURRENT(rtd->excitation_current);
chan_val |= LTC2983_RTD_CURVE(rtd->rtd_curve);
if (rtd->custom) {
int ret;
ret = __ltc2983_chan_custom_sensor_assign(st, rtd->custom,
&chan_val);
if (ret)
return ret;
}
return __ltc2983_chan_assign_common(st, sensor, chan_val);
}
static int ltc2983_thermistor_assign_chan(struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_thermistor *thermistor = to_thermistor(sensor);
u32 chan_val;
chan_val = LTC2983_CHAN_ASSIGN(thermistor->r_sense_chan);
chan_val |= LTC2983_THERMISTOR_CFG(thermistor->sensor_config);
chan_val |=
LTC2983_THERMISTOR_EXC_CURRENT(thermistor->excitation_current);
if (thermistor->custom) {
int ret;
ret = __ltc2983_chan_custom_sensor_assign(st,
thermistor->custom,
&chan_val);
if (ret)
return ret;
}
return __ltc2983_chan_assign_common(st, sensor, chan_val);
}
static int ltc2983_diode_assign_chan(struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_diode *diode = to_diode(sensor);
u32 chan_val;
chan_val = LTC2983_DIODE_CFG(diode->sensor_config);
chan_val |= LTC2983_DIODE_EXC_CURRENT(diode->excitation_current);
chan_val |= LTC2983_DIODE_IDEAL_FACTOR(diode->ideal_factor_value);
return __ltc2983_chan_assign_common(st, sensor, chan_val);
}
static int ltc2983_r_sense_assign_chan(struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_rsense *rsense = to_rsense(sensor);
u32 chan_val;
chan_val = LTC2983_R_SENSE_VAL(rsense->r_sense_val);
return __ltc2983_chan_assign_common(st, sensor, chan_val);
}
static int ltc2983_adc_assign_chan(struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_adc *adc = to_adc(sensor);
u32 chan_val;
chan_val = LTC2983_ADC_SINGLE_ENDED(adc->single_ended);
return __ltc2983_chan_assign_common(st, sensor, chan_val);
}
static int ltc2983_temp_assign_chan(struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_temp *temp = to_temp(sensor);
u32 chan_val;
int ret;
chan_val = LTC2983_ADC_SINGLE_ENDED(temp->single_ended);
ret = __ltc2983_chan_custom_sensor_assign(st, temp->custom, &chan_val);
if (ret)
return ret;
return __ltc2983_chan_assign_common(st, sensor, chan_val);
}
static struct ltc2983_sensor *
ltc2983_thermocouple_new(const struct fwnode_handle *child, struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_thermocouple *thermo;
struct fwnode_handle *ref;
u32 oc_current;
int ret;
thermo = devm_kzalloc(&st->spi->dev, sizeof(*thermo), GFP_KERNEL);
if (!thermo)
return ERR_PTR(-ENOMEM);
if (fwnode_property_read_bool(child, "adi,single-ended"))
thermo->sensor_config = LTC2983_THERMOCOUPLE_SGL(1);
ret = fwnode_property_read_u32(child, "adi,sensor-oc-current-microamp", &oc_current);
if (!ret) {
switch (oc_current) {
case 10:
thermo->sensor_config |=
LTC2983_THERMOCOUPLE_OC_CURR(0);
break;
case 100:
thermo->sensor_config |=
LTC2983_THERMOCOUPLE_OC_CURR(1);
break;
case 500:
thermo->sensor_config |=
LTC2983_THERMOCOUPLE_OC_CURR(2);
break;
case 1000:
thermo->sensor_config |=
LTC2983_THERMOCOUPLE_OC_CURR(3);
break;
default:
dev_err(&st->spi->dev,
"Invalid open circuit current:%u", oc_current);
return ERR_PTR(-EINVAL);
}
thermo->sensor_config |= LTC2983_THERMOCOUPLE_OC_CHECK(1);
}
/* validate channel index */
if (!(thermo->sensor_config & LTC2983_THERMOCOUPLE_DIFF_MASK) &&
sensor->chan < LTC2983_DIFFERENTIAL_CHAN_MIN) {
dev_err(&st->spi->dev,
"Invalid chann:%d for differential thermocouple",
sensor->chan);
return ERR_PTR(-EINVAL);
}
ref = fwnode_find_reference(child, "adi,cold-junction-handle", 0);
if (IS_ERR(ref)) {
ref = NULL;
} else {
ret = fwnode_property_read_u32(ref, "reg", &thermo->cold_junction_chan);
if (ret) {
/*
* This would be catched later but we can just return
* the error right away.
*/
dev_err(&st->spi->dev, "Property reg must be given\n");
goto fail;
}
}
/* check custom sensor */
if (sensor->type == LTC2983_SENSOR_THERMOCOUPLE_CUSTOM) {
const char *propname = "adi,custom-thermocouple";
thermo->custom = __ltc2983_custom_sensor_new(st, child,
propname, false,
16384, true);
if (IS_ERR(thermo->custom)) {
ret = PTR_ERR(thermo->custom);
goto fail;
}
}
/* set common parameters */
thermo->sensor.fault_handler = ltc2983_thermocouple_fault_handler;
thermo->sensor.assign_chan = ltc2983_thermocouple_assign_chan;
fwnode_handle_put(ref);
return &thermo->sensor;
fail:
fwnode_handle_put(ref);
return ERR_PTR(ret);
}
static struct ltc2983_sensor *
ltc2983_rtd_new(const struct fwnode_handle *child, struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_rtd *rtd;
int ret = 0;
struct device *dev = &st->spi->dev;
struct fwnode_handle *ref;
u32 excitation_current = 0, n_wires = 0;
rtd = devm_kzalloc(dev, sizeof(*rtd), GFP_KERNEL);
if (!rtd)
return ERR_PTR(-ENOMEM);
ref = fwnode_find_reference(child, "adi,rsense-handle", 0);
if (IS_ERR(ref)) {
dev_err(dev, "Property adi,rsense-handle missing or invalid");
return ERR_CAST(ref);
}
ret = fwnode_property_read_u32(ref, "reg", &rtd->r_sense_chan);
if (ret) {
dev_err(dev, "Property reg must be given\n");
goto fail;
}
ret = fwnode_property_read_u32(child, "adi,number-of-wires", &n_wires);
if (!ret) {
switch (n_wires) {
case 2:
rtd->sensor_config = LTC2983_RTD_N_WIRES(0);
break;
case 3:
rtd->sensor_config = LTC2983_RTD_N_WIRES(1);
break;
case 4:
rtd->sensor_config = LTC2983_RTD_N_WIRES(2);
break;
case 5:
/* 4 wires, Kelvin Rsense */
rtd->sensor_config = LTC2983_RTD_N_WIRES(3);
break;
default:
dev_err(dev, "Invalid number of wires:%u\n", n_wires);
ret = -EINVAL;
goto fail;
}
}
if (fwnode_property_read_bool(child, "adi,rsense-share")) {
/* Current rotation is only available with rsense sharing */
if (fwnode_property_read_bool(child, "adi,current-rotate")) {
if (n_wires == 2 || n_wires == 3) {
dev_err(dev,
"Rotation not allowed for 2/3 Wire RTDs");
ret = -EINVAL;
goto fail;
}
rtd->sensor_config |= LTC2983_RTD_C_ROTATE(1);
} else {
rtd->sensor_config |= LTC2983_RTD_R_SHARE(1);
}
}
/*
* rtd channel indexes are a bit more complicated to validate.
* For 4wire RTD with rotation, the channel selection cannot be
* >=19 since the chann + 1 is used in this configuration.
* For 4wire RTDs with kelvin rsense, the rsense channel cannot be
* <=1 since chanel - 1 and channel - 2 are used.
*/
if (rtd->sensor_config & LTC2983_RTD_4_WIRE_MASK) {
/* 4-wire */
u8 min = LTC2983_DIFFERENTIAL_CHAN_MIN,
max = st->info->max_channels_nr;
if (rtd->sensor_config & LTC2983_RTD_ROTATION_MASK)
max = st->info->max_channels_nr - 1;
if (((rtd->sensor_config & LTC2983_RTD_KELVIN_R_SENSE_MASK)
== LTC2983_RTD_KELVIN_R_SENSE_MASK) &&
(rtd->r_sense_chan <= min)) {
/* kelvin rsense*/
dev_err(dev,
"Invalid rsense chann:%d to use in kelvin rsense",
rtd->r_sense_chan);
ret = -EINVAL;
goto fail;
}
if (sensor->chan < min || sensor->chan > max) {
dev_err(dev, "Invalid chann:%d for the rtd config",
sensor->chan);
ret = -EINVAL;
goto fail;
}
} else {
/* same as differential case */
if (sensor->chan < LTC2983_DIFFERENTIAL_CHAN_MIN) {
dev_err(&st->spi->dev,
"Invalid chann:%d for RTD", sensor->chan);
ret = -EINVAL;
goto fail;
}
}
/* check custom sensor */
if (sensor->type == LTC2983_SENSOR_RTD_CUSTOM) {
rtd->custom = __ltc2983_custom_sensor_new(st, child,
"adi,custom-rtd",
false, 2048, false);
if (IS_ERR(rtd->custom)) {
ret = PTR_ERR(rtd->custom);
goto fail;
}
}
/* set common parameters */
rtd->sensor.fault_handler = ltc2983_common_fault_handler;
rtd->sensor.assign_chan = ltc2983_rtd_assign_chan;
ret = fwnode_property_read_u32(child, "adi,excitation-current-microamp",
&excitation_current);
if (ret) {
/* default to 5uA */
rtd->excitation_current = 1;
} else {
switch (excitation_current) {
case 5:
rtd->excitation_current = 0x01;
break;
case 10:
rtd->excitation_current = 0x02;
break;
case 25:
rtd->excitation_current = 0x03;
break;
case 50:
rtd->excitation_current = 0x04;
break;
case 100:
rtd->excitation_current = 0x05;
break;
case 250:
rtd->excitation_current = 0x06;
break;
case 500:
rtd->excitation_current = 0x07;
break;
case 1000:
rtd->excitation_current = 0x08;
break;
default:
dev_err(&st->spi->dev,
"Invalid value for excitation current(%u)",
excitation_current);
ret = -EINVAL;
goto fail;
}
}
fwnode_property_read_u32(child, "adi,rtd-curve", &rtd->rtd_curve);
fwnode_handle_put(ref);
return &rtd->sensor;
fail:
fwnode_handle_put(ref);
return ERR_PTR(ret);
}
static struct ltc2983_sensor *
ltc2983_thermistor_new(const struct fwnode_handle *child, struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_thermistor *thermistor;
struct device *dev = &st->spi->dev;
struct fwnode_handle *ref;
u32 excitation_current = 0;
int ret = 0;
thermistor = devm_kzalloc(dev, sizeof(*thermistor), GFP_KERNEL);
if (!thermistor)
return ERR_PTR(-ENOMEM);
ref = fwnode_find_reference(child, "adi,rsense-handle", 0);
if (IS_ERR(ref)) {
dev_err(dev, "Property adi,rsense-handle missing or invalid");
return ERR_CAST(ref);
}
ret = fwnode_property_read_u32(ref, "reg", &thermistor->r_sense_chan);
if (ret) {
dev_err(dev, "rsense channel must be configured...\n");
goto fail;
}
if (fwnode_property_read_bool(child, "adi,single-ended")) {
thermistor->sensor_config = LTC2983_THERMISTOR_SGL(1);
} else if (fwnode_property_read_bool(child, "adi,rsense-share")) {
/* rotation is only possible if sharing rsense */
if (fwnode_property_read_bool(child, "adi,current-rotate"))
thermistor->sensor_config =
LTC2983_THERMISTOR_C_ROTATE(1);
else
thermistor->sensor_config =
LTC2983_THERMISTOR_R_SHARE(1);
}
/* validate channel index */
if (!(thermistor->sensor_config & LTC2983_THERMISTOR_DIFF_MASK) &&
sensor->chan < LTC2983_DIFFERENTIAL_CHAN_MIN) {
dev_err(&st->spi->dev,
"Invalid chann:%d for differential thermistor",
sensor->chan);
ret = -EINVAL;
goto fail;
}
/* check custom sensor */
if (sensor->type >= LTC2983_SENSOR_THERMISTOR_STEINHART) {
bool steinhart = false;
const char *propname;
if (sensor->type == LTC2983_SENSOR_THERMISTOR_STEINHART) {
steinhart = true;
propname = "adi,custom-steinhart";
} else {
propname = "adi,custom-thermistor";
}
thermistor->custom = __ltc2983_custom_sensor_new(st, child,
propname,
steinhart,
64, false);
if (IS_ERR(thermistor->custom)) {
ret = PTR_ERR(thermistor->custom);
goto fail;
}
}
/* set common parameters */
thermistor->sensor.fault_handler = ltc2983_common_fault_handler;
thermistor->sensor.assign_chan = ltc2983_thermistor_assign_chan;
ret = fwnode_property_read_u32(child, "adi,excitation-current-nanoamp",
&excitation_current);
if (ret) {
/* Auto range is not allowed for custom sensors */
if (sensor->type >= LTC2983_SENSOR_THERMISTOR_STEINHART)
/* default to 1uA */
thermistor->excitation_current = 0x03;
else
/* default to auto-range */
thermistor->excitation_current = 0x0c;
} else {
switch (excitation_current) {
case 0:
/* auto range */
if (sensor->type >=
LTC2983_SENSOR_THERMISTOR_STEINHART) {
dev_err(&st->spi->dev,
"Auto Range not allowed for custom sensors\n");
ret = -EINVAL;
goto fail;
}
thermistor->excitation_current = 0x0c;
break;
case 250:
thermistor->excitation_current = 0x01;
break;
case 500:
thermistor->excitation_current = 0x02;
break;
case 1000:
thermistor->excitation_current = 0x03;
break;
case 5000:
thermistor->excitation_current = 0x04;
break;
case 10000:
thermistor->excitation_current = 0x05;
break;
case 25000:
thermistor->excitation_current = 0x06;
break;
case 50000:
thermistor->excitation_current = 0x07;
break;
case 100000:
thermistor->excitation_current = 0x08;
break;
case 250000:
thermistor->excitation_current = 0x09;
break;
case 500000:
thermistor->excitation_current = 0x0a;
break;
case 1000000:
thermistor->excitation_current = 0x0b;
break;
default:
dev_err(&st->spi->dev,
"Invalid value for excitation current(%u)",
excitation_current);
ret = -EINVAL;
goto fail;
}
}
fwnode_handle_put(ref);
return &thermistor->sensor;
fail:
fwnode_handle_put(ref);
return ERR_PTR(ret);
}
static struct ltc2983_sensor *
ltc2983_diode_new(const struct fwnode_handle *child, const struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_diode *diode;
u32 temp = 0, excitation_current = 0;
int ret;
diode = devm_kzalloc(&st->spi->dev, sizeof(*diode), GFP_KERNEL);
if (!diode)
return ERR_PTR(-ENOMEM);
if (fwnode_property_read_bool(child, "adi,single-ended"))
diode->sensor_config = LTC2983_DIODE_SGL(1);
if (fwnode_property_read_bool(child, "adi,three-conversion-cycles"))
diode->sensor_config |= LTC2983_DIODE_3_CONV_CYCLE(1);
if (fwnode_property_read_bool(child, "adi,average-on"))
diode->sensor_config |= LTC2983_DIODE_AVERAGE_ON(1);
/* validate channel index */
if (!(diode->sensor_config & LTC2983_DIODE_DIFF_MASK) &&
sensor->chan < LTC2983_DIFFERENTIAL_CHAN_MIN) {
dev_err(&st->spi->dev,
"Invalid chann:%d for differential thermistor",
sensor->chan);
return ERR_PTR(-EINVAL);
}
/* set common parameters */
diode->sensor.fault_handler = ltc2983_common_fault_handler;
diode->sensor.assign_chan = ltc2983_diode_assign_chan;
ret = fwnode_property_read_u32(child, "adi,excitation-current-microamp",
&excitation_current);
if (!ret) {
switch (excitation_current) {
case 10:
diode->excitation_current = 0x00;
break;
case 20:
diode->excitation_current = 0x01;
break;
case 40:
diode->excitation_current = 0x02;
break;
case 80:
diode->excitation_current = 0x03;
break;
default:
dev_err(&st->spi->dev,
"Invalid value for excitation current(%u)",
excitation_current);
return ERR_PTR(-EINVAL);
}
}
fwnode_property_read_u32(child, "adi,ideal-factor-value", &temp);
/* 2^20 resolution */
diode->ideal_factor_value = __convert_to_raw(temp, 1048576);
return &diode->sensor;
}
static struct ltc2983_sensor *ltc2983_r_sense_new(struct fwnode_handle *child,
struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_rsense *rsense;
int ret;
u32 temp;
rsense = devm_kzalloc(&st->spi->dev, sizeof(*rsense), GFP_KERNEL);
if (!rsense)
return ERR_PTR(-ENOMEM);
/* validate channel index */
if (sensor->chan < LTC2983_DIFFERENTIAL_CHAN_MIN) {
dev_err(&st->spi->dev, "Invalid chann:%d for r_sense",
sensor->chan);
return ERR_PTR(-EINVAL);
}
ret = fwnode_property_read_u32(child, "adi,rsense-val-milli-ohms", &temp);
if (ret) {
dev_err(&st->spi->dev, "Property adi,rsense-val-milli-ohms missing\n");
return ERR_PTR(-EINVAL);
}
/*
* Times 1000 because we have milli-ohms and __convert_to_raw
* expects scales of 1000000 which are used for all other
* properties.
* 2^10 resolution
*/
rsense->r_sense_val = __convert_to_raw((u64)temp * 1000, 1024);
/* set common parameters */
rsense->sensor.assign_chan = ltc2983_r_sense_assign_chan;
return &rsense->sensor;
}
static struct ltc2983_sensor *ltc2983_adc_new(struct fwnode_handle *child,
struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_adc *adc;
adc = devm_kzalloc(&st->spi->dev, sizeof(*adc), GFP_KERNEL);
if (!adc)
return ERR_PTR(-ENOMEM);
if (fwnode_property_read_bool(child, "adi,single-ended"))
adc->single_ended = true;
if (!adc->single_ended &&
sensor->chan < LTC2983_DIFFERENTIAL_CHAN_MIN) {
dev_err(&st->spi->dev, "Invalid chan:%d for differential adc\n",
sensor->chan);
return ERR_PTR(-EINVAL);
}
/* set common parameters */
adc->sensor.assign_chan = ltc2983_adc_assign_chan;
adc->sensor.fault_handler = ltc2983_common_fault_handler;
return &adc->sensor;
}
static struct ltc2983_sensor *ltc2983_temp_new(struct fwnode_handle *child,
struct ltc2983_data *st,
const struct ltc2983_sensor *sensor)
{
struct ltc2983_temp *temp;
temp = devm_kzalloc(&st->spi->dev, sizeof(*temp), GFP_KERNEL);
if (!temp)
return ERR_PTR(-ENOMEM);
if (fwnode_property_read_bool(child, "adi,single-ended"))
temp->single_ended = true;
if (!temp->single_ended &&
sensor->chan < LTC2983_DIFFERENTIAL_CHAN_MIN) {
dev_err(&st->spi->dev, "Invalid chan:%d for differential temp\n",
sensor->chan);
return ERR_PTR(-EINVAL);
}
temp->custom = __ltc2983_custom_sensor_new(st, child, "adi,custom-temp",
false, 4096, true);
if (IS_ERR(temp->custom))
return ERR_CAST(temp->custom);
/* set common parameters */
temp->sensor.assign_chan = ltc2983_temp_assign_chan;
temp->sensor.fault_handler = ltc2983_common_fault_handler;
return &temp->sensor;
}
static int ltc2983_chan_read(struct ltc2983_data *st,
const struct ltc2983_sensor *sensor, int *val)
{
u32 start_conversion = 0;
int ret;
unsigned long time;
start_conversion = LTC2983_STATUS_START(true);
start_conversion |= LTC2983_STATUS_CHAN_SEL(sensor->chan);
dev_dbg(&st->spi->dev, "Start conversion on chan:%d, status:%02X\n",
sensor->chan, start_conversion);
/* start conversion */
ret = regmap_write(st->regmap, LTC2983_STATUS_REG, start_conversion);
if (ret)
return ret;
reinit_completion(&st->completion);
/*
* wait for conversion to complete.
* 300 ms should be more than enough to complete the conversion.
* Depending on the sensor configuration, there are 2/3 conversions
* cycles of 82ms.
*/
time = wait_for_completion_timeout(&st->completion,
msecs_to_jiffies(300));
if (!time) {
dev_warn(&st->spi->dev, "Conversion timed out\n");
return -ETIMEDOUT;
}
/* read the converted data */
ret = regmap_bulk_read(st->regmap, LTC2983_CHAN_RES_ADDR(sensor->chan),
&st->temp, sizeof(st->temp));
if (ret)
return ret;
*val = __be32_to_cpu(st->temp);
if (!(LTC2983_RES_VALID_MASK & *val)) {
dev_err(&st->spi->dev, "Invalid conversion detected\n");
return -EIO;
}
ret = sensor->fault_handler(st, *val);
if (ret)
return ret;
*val = sign_extend32((*val) & LTC2983_DATA_MASK, LTC2983_DATA_SIGN_BIT);
return 0;
}
static int ltc2983_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct ltc2983_data *st = iio_priv(indio_dev);
int ret;
/* sanity check */
if (chan->address >= st->num_channels) {
dev_err(&st->spi->dev, "Invalid chan address:%ld",
chan->address);
return -EINVAL;
}
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&st->lock);
ret = ltc2983_chan_read(st, st->sensors[chan->address], val);
mutex_unlock(&st->lock);
return ret ?: IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_TEMP:
/* value in milli degrees */
*val = 1000;
/* 2^10 */
*val2 = 1024;
return IIO_VAL_FRACTIONAL;
case IIO_VOLTAGE:
/* value in millivolt */
*val = 1000;
/* 2^21 */
*val2 = 2097152;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
}
return -EINVAL;
}
static int ltc2983_reg_access(struct iio_dev *indio_dev,
unsigned int reg,
unsigned int writeval,
unsigned int *readval)
{
struct ltc2983_data *st = iio_priv(indio_dev);
if (readval)
return regmap_read(st->regmap, reg, readval);
else
return regmap_write(st->regmap, reg, writeval);
}
static irqreturn_t ltc2983_irq_handler(int irq, void *data)
{
struct ltc2983_data *st = data;
complete(&st->completion);
return IRQ_HANDLED;
}
#define LTC2983_CHAN(__type, index, __address) ({ \
struct iio_chan_spec __chan = { \
.type = __type, \
.indexed = 1, \
.channel = index, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.address = __address, \
}; \
__chan; \
})
static int ltc2983_parse_dt(struct ltc2983_data *st)
{
struct device *dev = &st->spi->dev;
struct fwnode_handle *child;
int ret = 0, chan = 0, channel_avail_mask = 0;
device_property_read_u32(dev, "adi,mux-delay-config-us", &st->mux_delay_config);
device_property_read_u32(dev, "adi,filter-notch-freq", &st->filter_notch_freq);
st->num_channels = device_get_child_node_count(dev);
if (!st->num_channels) {
dev_err(&st->spi->dev, "At least one channel must be given!");
return -EINVAL;
}
st->sensors = devm_kcalloc(dev, st->num_channels, sizeof(*st->sensors),
GFP_KERNEL);
if (!st->sensors)
return -ENOMEM;
st->iio_channels = st->num_channels;
device_for_each_child_node(dev, child) {
struct ltc2983_sensor sensor;
ret = fwnode_property_read_u32(child, "reg", &sensor.chan);
if (ret) {
dev_err(dev, "reg property must given for child nodes\n");
goto put_child;
}
/* check if we have a valid channel */
if (sensor.chan < LTC2983_MIN_CHANNELS_NR ||
sensor.chan > st->info->max_channels_nr) {
ret = -EINVAL;
dev_err(dev, "chan:%d must be from %u to %u\n", sensor.chan,
LTC2983_MIN_CHANNELS_NR, st->info->max_channels_nr);
goto put_child;
} else if (channel_avail_mask & BIT(sensor.chan)) {
ret = -EINVAL;
dev_err(dev, "chan:%d already in use\n", sensor.chan);
goto put_child;
}
ret = fwnode_property_read_u32(child, "adi,sensor-type", &sensor.type);
if (ret) {
dev_err(dev,
"adi,sensor-type property must given for child nodes\n");
goto put_child;
}
dev_dbg(dev, "Create new sensor, type %u, chann %u",
sensor.type,
sensor.chan);
if (sensor.type >= LTC2983_SENSOR_THERMOCOUPLE &&
sensor.type <= LTC2983_SENSOR_THERMOCOUPLE_CUSTOM) {
st->sensors[chan] = ltc2983_thermocouple_new(child, st,
&sensor);
} else if (sensor.type >= LTC2983_SENSOR_RTD &&
sensor.type <= LTC2983_SENSOR_RTD_CUSTOM) {
st->sensors[chan] = ltc2983_rtd_new(child, st, &sensor);
} else if (sensor.type >= LTC2983_SENSOR_THERMISTOR &&
sensor.type <= LTC2983_SENSOR_THERMISTOR_CUSTOM) {
st->sensors[chan] = ltc2983_thermistor_new(child, st,
&sensor);
} else if (sensor.type == LTC2983_SENSOR_DIODE) {
st->sensors[chan] = ltc2983_diode_new(child, st,
&sensor);
} else if (sensor.type == LTC2983_SENSOR_SENSE_RESISTOR) {
st->sensors[chan] = ltc2983_r_sense_new(child, st,
&sensor);
/* don't add rsense to iio */
st->iio_channels--;
} else if (sensor.type == LTC2983_SENSOR_DIRECT_ADC) {
st->sensors[chan] = ltc2983_adc_new(child, st, &sensor);
} else if (st->info->has_temp &&
sensor.type == LTC2983_SENSOR_ACTIVE_TEMP) {
st->sensors[chan] = ltc2983_temp_new(child, st, &sensor);
} else {
dev_err(dev, "Unknown sensor type %d\n", sensor.type);
ret = -EINVAL;
goto put_child;
}
if (IS_ERR(st->sensors[chan])) {
dev_err(dev, "Failed to create sensor %ld",
PTR_ERR(st->sensors[chan]));
ret = PTR_ERR(st->sensors[chan]);
goto put_child;
}
/* set generic sensor parameters */
st->sensors[chan]->chan = sensor.chan;
st->sensors[chan]->type = sensor.type;
channel_avail_mask |= BIT(sensor.chan);
chan++;
}
return 0;
put_child:
fwnode_handle_put(child);
return ret;
}
static int ltc2983_eeprom_cmd(struct ltc2983_data *st, unsigned int cmd,
unsigned int wait_time, unsigned int status_reg,
unsigned long status_fail_mask)
{
unsigned long time;
unsigned int val;
int ret;
ret = regmap_bulk_write(st->regmap, LTC2983_EEPROM_KEY_REG,
&st->eeprom_key, sizeof(st->eeprom_key));
if (ret)
return ret;
reinit_completion(&st->completion);
ret = regmap_write(st->regmap, LTC2983_STATUS_REG,
LTC2983_STATUS_START(true) | cmd);
if (ret)
return ret;
time = wait_for_completion_timeout(&st->completion,
msecs_to_jiffies(wait_time));
if (!time) {
dev_err(&st->spi->dev, "EEPROM command timed out\n");
return -ETIMEDOUT;
}
ret = regmap_read(st->regmap, status_reg, &val);
if (ret)
return ret;
if (val & status_fail_mask) {
dev_err(&st->spi->dev, "EEPROM command failed: 0x%02X\n", val);
return -EINVAL;
}
return 0;
}
static int ltc2983_setup(struct ltc2983_data *st, bool assign_iio)
{
u32 iio_chan_t = 0, iio_chan_v = 0, chan, iio_idx = 0, status;
int ret;
/* make sure the device is up: start bit (7) is 0 and done bit (6) is 1 */
ret = regmap_read_poll_timeout(st->regmap, LTC2983_STATUS_REG, status,
LTC2983_STATUS_UP(status) == 1, 25000,
25000 * 10);
if (ret) {
dev_err(&st->spi->dev, "Device startup timed out\n");
return ret;
}
ret = regmap_update_bits(st->regmap, LTC2983_GLOBAL_CONFIG_REG,
LTC2983_NOTCH_FREQ_MASK,
LTC2983_NOTCH_FREQ(st->filter_notch_freq));
if (ret)
return ret;
ret = regmap_write(st->regmap, LTC2983_MUX_CONFIG_REG,
st->mux_delay_config);
if (ret)
return ret;
if (st->info->has_eeprom && !assign_iio) {
ret = ltc2983_eeprom_cmd(st, LTC2983_EEPROM_READ_CMD,
LTC2983_EEPROM_READ_TIME_MS,
LTC2983_EEPROM_READ_STATUS_REG,
LTC2983_EEPROM_READ_FAILURE_MASK);
if (!ret)
return 0;
}
for (chan = 0; chan < st->num_channels; chan++) {
u32 chan_type = 0, *iio_chan;
ret = st->sensors[chan]->assign_chan(st, st->sensors[chan]);
if (ret)
return ret;
/*
* The assign_iio flag is necessary for when the device is
* coming out of sleep. In that case, we just need to
* re-configure the device channels.
* We also don't assign iio channels for rsense.
*/
if (st->sensors[chan]->type == LTC2983_SENSOR_SENSE_RESISTOR ||
!assign_iio)
continue;
/* assign iio channel */
if (st->sensors[chan]->type != LTC2983_SENSOR_DIRECT_ADC) {
chan_type = IIO_TEMP;
iio_chan = &iio_chan_t;
} else {
chan_type = IIO_VOLTAGE;
iio_chan = &iio_chan_v;
}
/*
* add chan as the iio .address so that, we can directly
* reference the sensor given the iio_chan_spec
*/
st->iio_chan[iio_idx++] = LTC2983_CHAN(chan_type, (*iio_chan)++,
chan);
}
return 0;
}
static const struct regmap_range ltc2983_reg_ranges[] = {
regmap_reg_range(LTC2983_STATUS_REG, LTC2983_STATUS_REG),
regmap_reg_range(LTC2983_TEMP_RES_START_REG, LTC2983_TEMP_RES_END_REG),
regmap_reg_range(LTC2983_EEPROM_KEY_REG, LTC2983_EEPROM_KEY_REG),
regmap_reg_range(LTC2983_EEPROM_READ_STATUS_REG,
LTC2983_EEPROM_READ_STATUS_REG),
regmap_reg_range(LTC2983_GLOBAL_CONFIG_REG, LTC2983_GLOBAL_CONFIG_REG),
regmap_reg_range(LTC2983_MULT_CHANNEL_START_REG,
LTC2983_MULT_CHANNEL_END_REG),
regmap_reg_range(LTC2986_EEPROM_STATUS_REG, LTC2986_EEPROM_STATUS_REG),
regmap_reg_range(LTC2983_MUX_CONFIG_REG, LTC2983_MUX_CONFIG_REG),
regmap_reg_range(LTC2983_CHAN_ASSIGN_START_REG,
LTC2983_CHAN_ASSIGN_END_REG),
regmap_reg_range(LTC2983_CUST_SENS_TBL_START_REG,
LTC2983_CUST_SENS_TBL_END_REG),
};
static const struct regmap_access_table ltc2983_reg_table = {
.yes_ranges = ltc2983_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(ltc2983_reg_ranges),
};
/*
* The reg_bits are actually 12 but the device needs the first *complete*
* byte for the command (R/W).
*/
static const struct regmap_config ltc2983_regmap_config = {
.reg_bits = 24,
.val_bits = 8,
.wr_table = <c2983_reg_table,
.rd_table = <c2983_reg_table,
.read_flag_mask = GENMASK(1, 0),
.write_flag_mask = BIT(1),
};
static const struct iio_info ltc2983_iio_info = {
.read_raw = ltc2983_read_raw,
.debugfs_reg_access = ltc2983_reg_access,
};
static int ltc2983_probe(struct spi_device *spi)
{
struct ltc2983_data *st;
struct iio_dev *indio_dev;
struct gpio_desc *gpio;
const char *name = spi_get_device_id(spi)->name;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->info = device_get_match_data(&spi->dev);
if (!st->info)
st->info = (void *)spi_get_device_id(spi)->driver_data;
if (!st->info)
return -ENODEV;
st->regmap = devm_regmap_init_spi(spi, <c2983_regmap_config);
if (IS_ERR(st->regmap)) {
dev_err(&spi->dev, "Failed to initialize regmap\n");
return PTR_ERR(st->regmap);
}
mutex_init(&st->lock);
init_completion(&st->completion);
st->spi = spi;
st->eeprom_key = cpu_to_be32(LTC2983_EEPROM_KEY);
spi_set_drvdata(spi, st);
ret = ltc2983_parse_dt(st);
if (ret)
return ret;
gpio = devm_gpiod_get_optional(&st->spi->dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(gpio))
return PTR_ERR(gpio);
if (gpio) {
/* bring the device out of reset */
usleep_range(1000, 1200);
gpiod_set_value_cansleep(gpio, 0);
}
st->iio_chan = devm_kzalloc(&spi->dev,
st->iio_channels * sizeof(*st->iio_chan),
GFP_KERNEL);
if (!st->iio_chan)
return -ENOMEM;
ret = ltc2983_setup(st, true);
if (ret)
return ret;
ret = devm_request_irq(&spi->dev, spi->irq, ltc2983_irq_handler,
IRQF_TRIGGER_RISING, name, st);
if (ret) {
dev_err(&spi->dev, "failed to request an irq, %d", ret);
return ret;
}
if (st->info->has_eeprom) {
ret = ltc2983_eeprom_cmd(st, LTC2983_EEPROM_WRITE_CMD,
LTC2983_EEPROM_WRITE_TIME_MS,
LTC2986_EEPROM_STATUS_REG,
LTC2983_EEPROM_STATUS_FAILURE_MASK);
if (ret)
return ret;
}
indio_dev->name = name;
indio_dev->num_channels = st->iio_channels;
indio_dev->channels = st->iio_chan;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = <c2983_iio_info;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static int ltc2983_resume(struct device *dev)
{
struct ltc2983_data *st = spi_get_drvdata(to_spi_device(dev));
int dummy;
/* dummy read to bring the device out of sleep */
regmap_read(st->regmap, LTC2983_STATUS_REG, &dummy);
/* we need to re-assign the channels */
return ltc2983_setup(st, false);
}
static int ltc2983_suspend(struct device *dev)
{
struct ltc2983_data *st = spi_get_drvdata(to_spi_device(dev));
return regmap_write(st->regmap, LTC2983_STATUS_REG, LTC2983_SLEEP);
}
static DEFINE_SIMPLE_DEV_PM_OPS(ltc2983_pm_ops, ltc2983_suspend,
ltc2983_resume);
static const struct ltc2983_chip_info ltc2983_chip_info_data = {
.max_channels_nr = 20,
};
static const struct ltc2983_chip_info ltc2984_chip_info_data = {
.max_channels_nr = 20,
.has_eeprom = true,
};
static const struct ltc2983_chip_info ltc2986_chip_info_data = {
.max_channels_nr = 10,
.has_temp = true,
.has_eeprom = true,
};
static const struct spi_device_id ltc2983_id_table[] = {
{ "ltc2983", (kernel_ulong_t)<c2983_chip_info_data },
{ "ltc2984", (kernel_ulong_t)<c2984_chip_info_data },
{ "ltc2986", (kernel_ulong_t)<c2986_chip_info_data },
{ "ltm2985", (kernel_ulong_t)<c2986_chip_info_data },
{},
};
MODULE_DEVICE_TABLE(spi, ltc2983_id_table);
static const struct of_device_id ltc2983_of_match[] = {
{ .compatible = "adi,ltc2983", .data = <c2983_chip_info_data },
{ .compatible = "adi,ltc2984", .data = <c2984_chip_info_data },
{ .compatible = "adi,ltc2986", .data = <c2986_chip_info_data },
{ .compatible = "adi,ltm2985", .data = <c2986_chip_info_data },
{},
};
MODULE_DEVICE_TABLE(of, ltc2983_of_match);
static struct spi_driver ltc2983_driver = {
.driver = {
.name = "ltc2983",
.of_match_table = ltc2983_of_match,
.pm = pm_sleep_ptr(<c2983_pm_ops),
},
.probe = ltc2983_probe,
.id_table = ltc2983_id_table,
};
module_spi_driver(ltc2983_driver);
MODULE_AUTHOR("Nuno Sa <[email protected]>");
MODULE_DESCRIPTION("Analog Devices LTC2983 SPI Temperature sensors");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/temperature/ltc2983.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* HID Sensors Driver
* Copyright (c) 2017, Intel Corporation.
*/
#include <linux/device.h>
#include <linux/hid-sensor-hub.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "../common/hid-sensors/hid-sensor-trigger.h"
struct temperature_state {
struct hid_sensor_common common_attributes;
struct hid_sensor_hub_attribute_info temperature_attr;
struct {
s32 temperature_data;
u64 timestamp __aligned(8);
} scan;
int scale_pre_decml;
int scale_post_decml;
int scale_precision;
int value_offset;
};
static const u32 temperature_sensitivity_addresses[] = {
HID_USAGE_SENSOR_DATA_ENVIRONMENTAL_TEMPERATURE,
};
/* Channel definitions */
static const struct iio_chan_spec temperature_channels[] = {
{
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_SAMP_FREQ) |
BIT(IIO_CHAN_INFO_HYSTERESIS),
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
/* Adjust channel real bits based on report descriptor */
static void temperature_adjust_channel_bit_mask(struct iio_chan_spec *channels,
int channel, int size)
{
channels[channel].scan_type.sign = 's';
/* Real storage bits will change based on the report desc. */
channels[channel].scan_type.realbits = size * 8;
/* Maximum size of a sample to capture is s32 */
channels[channel].scan_type.storagebits = sizeof(s32) * 8;
}
static int temperature_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct temperature_state *temp_st = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (chan->type != IIO_TEMP)
return -EINVAL;
hid_sensor_power_state(
&temp_st->common_attributes, true);
*val = sensor_hub_input_attr_get_raw_value(
temp_st->common_attributes.hsdev,
HID_USAGE_SENSOR_TEMPERATURE,
HID_USAGE_SENSOR_DATA_ENVIRONMENTAL_TEMPERATURE,
temp_st->temperature_attr.report_id,
SENSOR_HUB_SYNC,
temp_st->temperature_attr.logical_minimum < 0);
hid_sensor_power_state(
&temp_st->common_attributes,
false);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = temp_st->scale_pre_decml;
*val2 = temp_st->scale_post_decml;
return temp_st->scale_precision;
case IIO_CHAN_INFO_OFFSET:
*val = temp_st->value_offset;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SAMP_FREQ:
return hid_sensor_read_samp_freq_value(
&temp_st->common_attributes, val, val2);
case IIO_CHAN_INFO_HYSTERESIS:
return hid_sensor_read_raw_hyst_value(
&temp_st->common_attributes, val, val2);
default:
return -EINVAL;
}
}
static int temperature_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct temperature_state *temp_st = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
return hid_sensor_write_samp_freq_value(
&temp_st->common_attributes, val, val2);
case IIO_CHAN_INFO_HYSTERESIS:
return hid_sensor_write_raw_hyst_value(
&temp_st->common_attributes, val, val2);
default:
return -EINVAL;
}
}
static const struct iio_info temperature_info = {
.read_raw = &temperature_read_raw,
.write_raw = &temperature_write_raw,
};
/* Callback handler to send event after all samples are received and captured */
static int temperature_proc_event(struct hid_sensor_hub_device *hsdev,
unsigned int usage_id, void *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct temperature_state *temp_st = iio_priv(indio_dev);
if (atomic_read(&temp_st->common_attributes.data_ready))
iio_push_to_buffers_with_timestamp(indio_dev, &temp_st->scan,
iio_get_time_ns(indio_dev));
return 0;
}
/* Capture samples in local storage */
static int temperature_capture_sample(struct hid_sensor_hub_device *hsdev,
unsigned int usage_id, size_t raw_len,
char *raw_data, void *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct temperature_state *temp_st = iio_priv(indio_dev);
switch (usage_id) {
case HID_USAGE_SENSOR_DATA_ENVIRONMENTAL_TEMPERATURE:
temp_st->scan.temperature_data = *(s32 *)raw_data;
return 0;
default:
return -EINVAL;
}
}
/* Parse report which is specific to an usage id*/
static int temperature_parse_report(struct platform_device *pdev,
struct hid_sensor_hub_device *hsdev,
struct iio_chan_spec *channels,
unsigned int usage_id,
struct temperature_state *st)
{
int ret;
ret = sensor_hub_input_get_attribute_info(hsdev, HID_INPUT_REPORT,
usage_id,
HID_USAGE_SENSOR_DATA_ENVIRONMENTAL_TEMPERATURE,
&st->temperature_attr);
if (ret < 0)
return ret;
temperature_adjust_channel_bit_mask(channels, 0,
st->temperature_attr.size);
st->scale_precision = hid_sensor_format_scale(
HID_USAGE_SENSOR_TEMPERATURE,
&st->temperature_attr,
&st->scale_pre_decml, &st->scale_post_decml);
return ret;
}
static struct hid_sensor_hub_callbacks temperature_callbacks = {
.send_event = &temperature_proc_event,
.capture_sample = &temperature_capture_sample,
};
/* Function to initialize the processing for usage id */
static int hid_temperature_probe(struct platform_device *pdev)
{
static const char *name = "temperature";
struct iio_dev *indio_dev;
struct temperature_state *temp_st;
struct iio_chan_spec *temp_chans;
struct hid_sensor_hub_device *hsdev = dev_get_platdata(&pdev->dev);
int ret;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*temp_st));
if (!indio_dev)
return -ENOMEM;
temp_st = iio_priv(indio_dev);
temp_st->common_attributes.hsdev = hsdev;
temp_st->common_attributes.pdev = pdev;
ret = hid_sensor_parse_common_attributes(hsdev,
HID_USAGE_SENSOR_TEMPERATURE,
&temp_st->common_attributes,
temperature_sensitivity_addresses,
ARRAY_SIZE(temperature_sensitivity_addresses));
if (ret)
return ret;
temp_chans = devm_kmemdup(&indio_dev->dev, temperature_channels,
sizeof(temperature_channels), GFP_KERNEL);
if (!temp_chans)
return -ENOMEM;
ret = temperature_parse_report(pdev, hsdev, temp_chans,
HID_USAGE_SENSOR_TEMPERATURE, temp_st);
if (ret)
return ret;
indio_dev->channels = temp_chans;
indio_dev->num_channels = ARRAY_SIZE(temperature_channels);
indio_dev->info = &temperature_info;
indio_dev->name = name;
indio_dev->modes = INDIO_DIRECT_MODE;
atomic_set(&temp_st->common_attributes.data_ready, 0);
ret = hid_sensor_setup_trigger(indio_dev, name,
&temp_st->common_attributes);
if (ret)
return ret;
platform_set_drvdata(pdev, indio_dev);
temperature_callbacks.pdev = pdev;
ret = sensor_hub_register_callback(hsdev, HID_USAGE_SENSOR_TEMPERATURE,
&temperature_callbacks);
if (ret)
goto error_remove_trigger;
ret = devm_iio_device_register(indio_dev->dev.parent, indio_dev);
if (ret)
goto error_remove_callback;
return ret;
error_remove_callback:
sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_TEMPERATURE);
error_remove_trigger:
hid_sensor_remove_trigger(indio_dev, &temp_st->common_attributes);
return ret;
}
/* Function to deinitialize the processing for usage id */
static int hid_temperature_remove(struct platform_device *pdev)
{
struct hid_sensor_hub_device *hsdev = dev_get_platdata(&pdev->dev);
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct temperature_state *temp_st = iio_priv(indio_dev);
sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_TEMPERATURE);
hid_sensor_remove_trigger(indio_dev, &temp_st->common_attributes);
return 0;
}
static const struct platform_device_id hid_temperature_ids[] = {
{
/* Format: HID-SENSOR-usage_id_in_hex_lowercase */
.name = "HID-SENSOR-200033",
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, hid_temperature_ids);
static struct platform_driver hid_temperature_platform_driver = {
.id_table = hid_temperature_ids,
.driver = {
.name = "temperature-sensor",
.pm = &hid_sensor_pm_ops,
},
.probe = hid_temperature_probe,
.remove = hid_temperature_remove,
};
module_platform_driver(hid_temperature_platform_driver);
MODULE_DESCRIPTION("HID Environmental temperature sensor");
MODULE_AUTHOR("Song Hongyan <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_HID);
| linux-master | drivers/iio/temperature/hid-sensor-temperature.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* mlx90614.c - Support for Melexis MLX90614/MLX90615 contactless IR temperature sensor
*
* Copyright (c) 2014 Peter Meerwald <[email protected]>
* Copyright (c) 2015 Essensium NV
* Copyright (c) 2015 Melexis
*
* Driver for the Melexis MLX90614/MLX90615 I2C 16-bit IR thermopile sensor
*
* MLX90614 - 17-bit ADC + MLX90302 DSP
* MLX90615 - 16-bit ADC + MLX90325 DSP
*
* (7-bit I2C slave address 0x5a, 100KHz bus speed only!)
*
* To wake up from sleep mode, the SDA line must be held low while SCL is high
* for at least 33ms. This is achieved with an extra GPIO that can be connected
* directly to the SDA line. In normal operation, the GPIO is set as input and
* will not interfere in I2C communication. While the GPIO is driven low, the
* i2c adapter is locked since it cannot be used by other clients. The SCL line
* always has a pull-up so we do not need an extra GPIO to drive it high. If
* the "wakeup" GPIO is not given, power management will be disabled.
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/jiffies.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define MLX90614_OP_RAM 0x00
#define MLX90614_OP_EEPROM 0x20
#define MLX90614_OP_SLEEP 0xff
#define MLX90615_OP_EEPROM 0x10
#define MLX90615_OP_RAM 0x20
#define MLX90615_OP_SLEEP 0xc6
/* Control bits in configuration register */
#define MLX90614_CONFIG_IIR_SHIFT 0 /* IIR coefficient */
#define MLX90614_CONFIG_IIR_MASK (0x7 << MLX90614_CONFIG_IIR_SHIFT)
#define MLX90614_CONFIG_DUAL_SHIFT 6 /* single (0) or dual (1) IR sensor */
#define MLX90614_CONFIG_DUAL_MASK (1 << MLX90614_CONFIG_DUAL_SHIFT)
#define MLX90614_CONFIG_FIR_SHIFT 8 /* FIR coefficient */
#define MLX90614_CONFIG_FIR_MASK (0x7 << MLX90614_CONFIG_FIR_SHIFT)
#define MLX90615_CONFIG_IIR_SHIFT 12 /* IIR coefficient */
#define MLX90615_CONFIG_IIR_MASK (0x7 << MLX90615_CONFIG_IIR_SHIFT)
/* Timings (in ms) */
#define MLX90614_TIMING_EEPROM 20 /* time for EEPROM write/erase to complete */
#define MLX90614_TIMING_WAKEUP 34 /* time to hold SDA low for wake-up */
#define MLX90614_TIMING_STARTUP 250 /* time before first data after wake-up */
#define MLX90615_TIMING_WAKEUP 22 /* time to hold SCL low for wake-up */
#define MLX90614_AUTOSLEEP_DELAY 5000 /* default autosleep delay */
/* Magic constants */
#define MLX90614_CONST_OFFSET_DEC -13657 /* decimal part of the Kelvin offset */
#define MLX90614_CONST_OFFSET_REM 500000 /* remainder of offset (273.15*50) */
#define MLX90614_CONST_SCALE 20 /* Scale in milliKelvin (0.02 * 1000) */
#define MLX90614_CONST_FIR 0x7 /* Fixed value for FIR part of low pass filter */
/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
struct mlx_chip_info {
/* EEPROM offsets with 16-bit data, MSB first */
/* emissivity correction coefficient */
u8 op_eeprom_emissivity;
u8 op_eeprom_config1;
/* RAM offsets with 16-bit data, MSB first */
/* ambient temperature */
u8 op_ram_ta;
/* object 1 temperature */
u8 op_ram_tobj1;
/* object 2 temperature */
u8 op_ram_tobj2;
u8 op_sleep;
/* support for two input channels (MLX90614 only) */
u8 dual_channel;
u8 wakeup_delay_ms;
u16 emissivity_max;
u16 fir_config_mask;
u16 iir_config_mask;
int iir_valid_offset;
u16 iir_values[8];
int iir_freqs[8][2];
};
struct mlx90614_data {
struct i2c_client *client;
struct mutex lock; /* for EEPROM access only */
struct gpio_desc *wakeup_gpio; /* NULL to disable sleep/wake-up */
const struct mlx_chip_info *chip_info; /* Chip hardware details */
unsigned long ready_timestamp; /* in jiffies */
};
/*
* Erase an address and write word.
* The mutex must be locked before calling.
*/
static s32 mlx90614_write_word(const struct i2c_client *client, u8 command,
u16 value)
{
/*
* Note: The mlx90614 requires a PEC on writing but does not send us a
* valid PEC on reading. Hence, we cannot set I2C_CLIENT_PEC in
* i2c_client.flags. As a workaround, we use i2c_smbus_xfer here.
*/
union i2c_smbus_data data;
s32 ret;
dev_dbg(&client->dev, "Writing 0x%x to address 0x%x", value, command);
data.word = 0x0000; /* erase command */
ret = i2c_smbus_xfer(client->adapter, client->addr,
client->flags | I2C_CLIENT_PEC,
I2C_SMBUS_WRITE, command,
I2C_SMBUS_WORD_DATA, &data);
if (ret < 0)
return ret;
msleep(MLX90614_TIMING_EEPROM);
data.word = value; /* actual write */
ret = i2c_smbus_xfer(client->adapter, client->addr,
client->flags | I2C_CLIENT_PEC,
I2C_SMBUS_WRITE, command,
I2C_SMBUS_WORD_DATA, &data);
msleep(MLX90614_TIMING_EEPROM);
return ret;
}
/*
* Find the IIR value inside iir_values array and return its position
* which is equivalent to the bit value in sensor register
*/
static inline s32 mlx90614_iir_search(const struct i2c_client *client,
int value)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct mlx90614_data *data = iio_priv(indio_dev);
const struct mlx_chip_info *chip_info = data->chip_info;
int i;
s32 ret;
for (i = chip_info->iir_valid_offset;
i < ARRAY_SIZE(chip_info->iir_values);
i++) {
if (value == chip_info->iir_values[i])
break;
}
if (i == ARRAY_SIZE(chip_info->iir_values))
return -EINVAL;
/*
* CONFIG register values must not be changed so
* we must read them before we actually write
* changes
*/
ret = i2c_smbus_read_word_data(client, chip_info->op_eeprom_config1);
if (ret < 0)
return ret;
/* Modify FIR on parts which have configurable FIR filter */
if (chip_info->fir_config_mask) {
ret &= ~chip_info->fir_config_mask;
ret |= field_prep(chip_info->fir_config_mask, MLX90614_CONST_FIR);
}
ret &= ~chip_info->iir_config_mask;
ret |= field_prep(chip_info->iir_config_mask, i);
/* Write changed values */
ret = mlx90614_write_word(client, chip_info->op_eeprom_config1, ret);
return ret;
}
#ifdef CONFIG_PM
/*
* If @startup is true, make sure MLX90614_TIMING_STARTUP ms have elapsed since
* the last wake-up. This is normally only needed to get a valid temperature
* reading. EEPROM access does not need such delay.
* Return 0 on success, <0 on error.
*/
static int mlx90614_power_get(struct mlx90614_data *data, bool startup)
{
unsigned long now;
int ret;
if (!data->wakeup_gpio)
return 0;
ret = pm_runtime_resume_and_get(&data->client->dev);
if (ret < 0)
return ret;
if (startup) {
now = jiffies;
if (time_before(now, data->ready_timestamp) &&
msleep_interruptible(jiffies_to_msecs(
data->ready_timestamp - now)) != 0) {
pm_runtime_put_autosuspend(&data->client->dev);
return -EINTR;
}
}
return 0;
}
static void mlx90614_power_put(struct mlx90614_data *data)
{
if (!data->wakeup_gpio)
return;
pm_runtime_mark_last_busy(&data->client->dev);
pm_runtime_put_autosuspend(&data->client->dev);
}
#else
static inline int mlx90614_power_get(struct mlx90614_data *data, bool startup)
{
return 0;
}
static inline void mlx90614_power_put(struct mlx90614_data *data)
{
}
#endif
static int mlx90614_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
struct mlx90614_data *data = iio_priv(indio_dev);
const struct mlx_chip_info *chip_info = data->chip_info;
u8 cmd, idx;
s32 ret;
switch (mask) {
case IIO_CHAN_INFO_RAW: /* 0.02K / LSB */
switch (channel->channel2) {
case IIO_MOD_TEMP_AMBIENT:
cmd = chip_info->op_ram_ta;
break;
case IIO_MOD_TEMP_OBJECT:
if (chip_info->dual_channel && channel->channel)
return -EINVAL;
switch (channel->channel) {
case 0:
cmd = chip_info->op_ram_tobj1;
break;
case 1:
cmd = chip_info->op_ram_tobj2;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
ret = mlx90614_power_get(data, true);
if (ret < 0)
return ret;
ret = i2c_smbus_read_word_data(data->client, cmd);
mlx90614_power_put(data);
if (ret < 0)
return ret;
/* MSB is an error flag */
if (ret & 0x8000)
return -EIO;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
*val = MLX90614_CONST_OFFSET_DEC;
*val2 = MLX90614_CONST_OFFSET_REM;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_SCALE:
*val = MLX90614_CONST_SCALE;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBEMISSIVITY: /* 1/emissivity_max / LSB */
ret = mlx90614_power_get(data, false);
if (ret < 0)
return ret;
mutex_lock(&data->lock);
ret = i2c_smbus_read_word_data(data->client,
chip_info->op_eeprom_emissivity);
mutex_unlock(&data->lock);
mlx90614_power_put(data);
if (ret < 0)
return ret;
if (ret == chip_info->emissivity_max) {
*val = 1;
*val2 = 0;
} else {
*val = 0;
*val2 = ret * NSEC_PER_SEC / chip_info->emissivity_max;
}
return IIO_VAL_INT_PLUS_NANO;
/* IIR setting with FIR=1024 (MLX90614) or FIR=65536 (MLX90615) */
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
ret = mlx90614_power_get(data, false);
if (ret < 0)
return ret;
mutex_lock(&data->lock);
ret = i2c_smbus_read_word_data(data->client,
chip_info->op_eeprom_config1);
mutex_unlock(&data->lock);
mlx90614_power_put(data);
if (ret < 0)
return ret;
idx = field_get(chip_info->iir_config_mask, ret) -
chip_info->iir_valid_offset;
*val = chip_info->iir_values[idx] / 100;
*val2 = (chip_info->iir_values[idx] % 100) * 10000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int mlx90614_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int val,
int val2, long mask)
{
struct mlx90614_data *data = iio_priv(indio_dev);
const struct mlx_chip_info *chip_info = data->chip_info;
s32 ret;
switch (mask) {
case IIO_CHAN_INFO_CALIBEMISSIVITY: /* 1/emissivity_max / LSB */
if (val < 0 || val2 < 0 || val > 1 || (val == 1 && val2 != 0))
return -EINVAL;
val = val * chip_info->emissivity_max +
val2 * chip_info->emissivity_max / NSEC_PER_SEC;
ret = mlx90614_power_get(data, false);
if (ret < 0)
return ret;
mutex_lock(&data->lock);
ret = mlx90614_write_word(data->client,
chip_info->op_eeprom_emissivity, val);
mutex_unlock(&data->lock);
mlx90614_power_put(data);
return ret;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: /* IIR Filter setting */
if (val < 0 || val2 < 0)
return -EINVAL;
ret = mlx90614_power_get(data, false);
if (ret < 0)
return ret;
mutex_lock(&data->lock);
ret = mlx90614_iir_search(data->client,
val * 100 + val2 / 10000);
mutex_unlock(&data->lock);
mlx90614_power_put(data);
return ret;
default:
return -EINVAL;
}
}
static int mlx90614_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_CALIBEMISSIVITY:
return IIO_VAL_INT_PLUS_NANO;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int mlx90614_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
struct mlx90614_data *data = iio_priv(indio_dev);
const struct mlx_chip_info *chip_info = data->chip_info;
switch (mask) {
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
*vals = (int *)chip_info->iir_freqs;
*type = IIO_VAL_INT_PLUS_MICRO;
*length = 2 * (ARRAY_SIZE(chip_info->iir_freqs) -
chip_info->iir_valid_offset);
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static const struct iio_chan_spec mlx90614_channels[] = {
{
.type = IIO_TEMP,
.modified = 1,
.channel2 = IIO_MOD_TEMP_AMBIENT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE),
},
{
.type = IIO_TEMP,
.modified = 1,
.channel2 = IIO_MOD_TEMP_OBJECT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBEMISSIVITY) |
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE),
},
{
.type = IIO_TEMP,
.indexed = 1,
.modified = 1,
.channel = 1,
.channel2 = IIO_MOD_TEMP_OBJECT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBEMISSIVITY) |
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE),
},
};
static const struct iio_info mlx90614_info = {
.read_raw = mlx90614_read_raw,
.write_raw = mlx90614_write_raw,
.write_raw_get_fmt = mlx90614_write_raw_get_fmt,
.read_avail = mlx90614_read_avail,
};
#ifdef CONFIG_PM
static int mlx90614_sleep(struct mlx90614_data *data)
{
const struct mlx_chip_info *chip_info = data->chip_info;
s32 ret;
if (!data->wakeup_gpio) {
dev_dbg(&data->client->dev, "Sleep disabled");
return -ENOSYS;
}
dev_dbg(&data->client->dev, "Requesting sleep");
mutex_lock(&data->lock);
ret = i2c_smbus_xfer(data->client->adapter, data->client->addr,
data->client->flags | I2C_CLIENT_PEC,
I2C_SMBUS_WRITE, chip_info->op_sleep,
I2C_SMBUS_BYTE, NULL);
mutex_unlock(&data->lock);
return ret;
}
static int mlx90614_wakeup(struct mlx90614_data *data)
{
const struct mlx_chip_info *chip_info = data->chip_info;
if (!data->wakeup_gpio) {
dev_dbg(&data->client->dev, "Wake-up disabled");
return -ENOSYS;
}
dev_dbg(&data->client->dev, "Requesting wake-up");
i2c_lock_bus(data->client->adapter, I2C_LOCK_ROOT_ADAPTER);
gpiod_direction_output(data->wakeup_gpio, 0);
msleep(chip_info->wakeup_delay_ms);
gpiod_direction_input(data->wakeup_gpio);
i2c_unlock_bus(data->client->adapter, I2C_LOCK_ROOT_ADAPTER);
data->ready_timestamp = jiffies +
msecs_to_jiffies(MLX90614_TIMING_STARTUP);
/*
* Quirk: the i2c controller may get confused right after the
* wake-up signal has been sent. As a workaround, do a dummy read.
* If the read fails, the controller will probably be reset so that
* further reads will work.
*/
i2c_smbus_read_word_data(data->client, chip_info->op_eeprom_config1);
return 0;
}
/* Return wake-up GPIO or NULL if sleep functionality should be disabled. */
static struct gpio_desc *mlx90614_probe_wakeup(struct i2c_client *client)
{
struct gpio_desc *gpio;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_WRITE_BYTE)) {
dev_info(&client->dev,
"i2c adapter does not support SMBUS_WRITE_BYTE, sleep disabled");
return NULL;
}
gpio = devm_gpiod_get_optional(&client->dev, "wakeup", GPIOD_IN);
if (IS_ERR(gpio)) {
dev_warn(&client->dev,
"gpio acquisition failed with error %ld, sleep disabled",
PTR_ERR(gpio));
return NULL;
} else if (!gpio) {
dev_info(&client->dev,
"wakeup-gpio not found, sleep disabled");
}
return gpio;
}
#else
static inline int mlx90614_sleep(struct mlx90614_data *data)
{
return -ENOSYS;
}
static inline int mlx90614_wakeup(struct mlx90614_data *data)
{
return -ENOSYS;
}
static inline struct gpio_desc *mlx90614_probe_wakeup(struct i2c_client *client)
{
return NULL;
}
#endif
/* Return 0 for single sensor, 1 for dual sensor, <0 on error. */
static int mlx90614_probe_num_ir_sensors(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct mlx90614_data *data = iio_priv(indio_dev);
const struct mlx_chip_info *chip_info = data->chip_info;
s32 ret;
if (chip_info->dual_channel)
return 0;
ret = i2c_smbus_read_word_data(client, chip_info->op_eeprom_config1);
if (ret < 0)
return ret;
return (ret & MLX90614_CONFIG_DUAL_MASK) ? 1 : 0;
}
static int mlx90614_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct iio_dev *indio_dev;
struct mlx90614_data *data;
int ret;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA))
return -EOPNOTSUPP;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
mutex_init(&data->lock);
data->wakeup_gpio = mlx90614_probe_wakeup(client);
data->chip_info = device_get_match_data(&client->dev);
mlx90614_wakeup(data);
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &mlx90614_info;
ret = mlx90614_probe_num_ir_sensors(client);
switch (ret) {
case 0:
dev_dbg(&client->dev, "Found single sensor");
indio_dev->channels = mlx90614_channels;
indio_dev->num_channels = 2;
break;
case 1:
dev_dbg(&client->dev, "Found dual sensor");
indio_dev->channels = mlx90614_channels;
indio_dev->num_channels = 3;
break;
default:
return ret;
}
if (data->wakeup_gpio) {
pm_runtime_set_autosuspend_delay(&client->dev,
MLX90614_AUTOSLEEP_DELAY);
pm_runtime_use_autosuspend(&client->dev);
pm_runtime_set_active(&client->dev);
pm_runtime_enable(&client->dev);
}
return iio_device_register(indio_dev);
}
static void mlx90614_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct mlx90614_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (data->wakeup_gpio) {
pm_runtime_disable(&client->dev);
if (!pm_runtime_status_suspended(&client->dev))
mlx90614_sleep(data);
pm_runtime_set_suspended(&client->dev);
}
}
static const struct mlx_chip_info mlx90614_chip_info = {
.op_eeprom_emissivity = MLX90614_OP_EEPROM | 0x04,
.op_eeprom_config1 = MLX90614_OP_EEPROM | 0x05,
.op_ram_ta = MLX90614_OP_RAM | 0x06,
.op_ram_tobj1 = MLX90614_OP_RAM | 0x07,
.op_ram_tobj2 = MLX90614_OP_RAM | 0x08,
.op_sleep = MLX90614_OP_SLEEP,
.dual_channel = true,
.wakeup_delay_ms = MLX90614_TIMING_WAKEUP,
.emissivity_max = 65535,
.fir_config_mask = MLX90614_CONFIG_FIR_MASK,
.iir_config_mask = MLX90614_CONFIG_IIR_MASK,
.iir_valid_offset = 0,
.iir_values = { 77, 31, 20, 15, 723, 153, 110, 86 },
.iir_freqs = {
{ 0, 150000 }, /* 13% ~= 0.15 Hz */
{ 0, 200000 }, /* 17% ~= 0.20 Hz */
{ 0, 310000 }, /* 25% ~= 0.31 Hz */
{ 0, 770000 }, /* 50% ~= 0.77 Hz */
{ 0, 860000 }, /* 57% ~= 0.86 Hz */
{ 1, 100000 }, /* 67% ~= 1.10 Hz */
{ 1, 530000 }, /* 80% ~= 1.53 Hz */
{ 7, 230000 } /* 100% ~= 7.23 Hz */
},
};
static const struct mlx_chip_info mlx90615_chip_info = {
.op_eeprom_emissivity = MLX90615_OP_EEPROM | 0x03,
.op_eeprom_config1 = MLX90615_OP_EEPROM | 0x02,
.op_ram_ta = MLX90615_OP_RAM | 0x06,
.op_ram_tobj1 = MLX90615_OP_RAM | 0x07,
.op_ram_tobj2 = MLX90615_OP_RAM | 0x08,
.op_sleep = MLX90615_OP_SLEEP,
.dual_channel = false,
.wakeup_delay_ms = MLX90615_TIMING_WAKEUP,
.emissivity_max = 16383,
.fir_config_mask = 0, /* MLX90615 FIR is fixed */
.iir_config_mask = MLX90615_CONFIG_IIR_MASK,
/* IIR value 0 is FORBIDDEN COMBINATION on MLX90615 */
.iir_valid_offset = 1,
.iir_values = { 500, 50, 30, 20, 15, 13, 10 },
.iir_freqs = {
{ 0, 100000 }, /* 14% ~= 0.10 Hz */
{ 0, 130000 }, /* 17% ~= 0.13 Hz */
{ 0, 150000 }, /* 20% ~= 0.15 Hz */
{ 0, 200000 }, /* 25% ~= 0.20 Hz */
{ 0, 300000 }, /* 33% ~= 0.30 Hz */
{ 0, 500000 }, /* 50% ~= 0.50 Hz */
{ 5, 000000 }, /* 100% ~= 5.00 Hz */
},
};
static const struct i2c_device_id mlx90614_id[] = {
{ "mlx90614", .driver_data = (kernel_ulong_t)&mlx90614_chip_info },
{ "mlx90615", .driver_data = (kernel_ulong_t)&mlx90615_chip_info },
{ }
};
MODULE_DEVICE_TABLE(i2c, mlx90614_id);
static const struct of_device_id mlx90614_of_match[] = {
{ .compatible = "melexis,mlx90614", .data = &mlx90614_chip_info },
{ .compatible = "melexis,mlx90615", .data = &mlx90615_chip_info },
{ }
};
MODULE_DEVICE_TABLE(of, mlx90614_of_match);
static int mlx90614_pm_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct mlx90614_data *data = iio_priv(indio_dev);
if (data->wakeup_gpio && pm_runtime_active(dev))
return mlx90614_sleep(data);
return 0;
}
static int mlx90614_pm_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct mlx90614_data *data = iio_priv(indio_dev);
int err;
if (data->wakeup_gpio) {
err = mlx90614_wakeup(data);
if (err < 0)
return err;
pm_runtime_disable(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
}
return 0;
}
static int mlx90614_pm_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct mlx90614_data *data = iio_priv(indio_dev);
return mlx90614_sleep(data);
}
static int mlx90614_pm_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct mlx90614_data *data = iio_priv(indio_dev);
return mlx90614_wakeup(data);
}
static const struct dev_pm_ops mlx90614_pm_ops = {
SYSTEM_SLEEP_PM_OPS(mlx90614_pm_suspend, mlx90614_pm_resume)
RUNTIME_PM_OPS(mlx90614_pm_runtime_suspend,
mlx90614_pm_runtime_resume, NULL)
};
static struct i2c_driver mlx90614_driver = {
.driver = {
.name = "mlx90614",
.of_match_table = mlx90614_of_match,
.pm = pm_ptr(&mlx90614_pm_ops),
},
.probe = mlx90614_probe,
.remove = mlx90614_remove,
.id_table = mlx90614_id,
};
module_i2c_driver(mlx90614_driver);
MODULE_AUTHOR("Peter Meerwald <[email protected]>");
MODULE_AUTHOR("Vianney le Clément de Saint-Marcq <[email protected]>");
MODULE_AUTHOR("Crt Mori <[email protected]>");
MODULE_DESCRIPTION("Melexis MLX90614 contactless IR temperature sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/temperature/mlx90614.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tsys02d.c - Support for Measurement-Specialties tsys02d temperature sensor
*
* Copyright (c) 2015 Measurement-Specialties
*
* (7-bit I2C slave address 0x40)
*
* Datasheet:
* http://www.meas-spec.com/downloads/Digital_Sensor_TSYS02D.pdf
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/stat.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include "../common/ms_sensors/ms_sensors_i2c.h"
#define TSYS02D_RESET 0xFE
static const int tsys02d_samp_freq[4] = { 20, 40, 70, 140 };
/* String copy of the above const for readability purpose */
static const char tsys02d_show_samp_freq[] = "20 40 70 140";
static int tsys02d_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
int ret;
s32 temperature;
struct ms_ht_dev *dev_data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
switch (channel->type) {
case IIO_TEMP: /* in milli °C */
ret = ms_sensors_ht_read_temperature(dev_data,
&temperature);
if (ret)
return ret;
*val = temperature;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SAMP_FREQ:
*val = tsys02d_samp_freq[dev_data->res_index];
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int tsys02d_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct ms_ht_dev *dev_data = iio_priv(indio_dev);
int i, ret;
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
i = ARRAY_SIZE(tsys02d_samp_freq);
while (i-- > 0)
if (val == tsys02d_samp_freq[i])
break;
if (i < 0)
return -EINVAL;
mutex_lock(&dev_data->lock);
dev_data->res_index = i;
ret = ms_sensors_write_resolution(dev_data, i);
mutex_unlock(&dev_data->lock);
return ret;
default:
return -EINVAL;
}
}
static const struct iio_chan_spec tsys02d_channels[] = {
{
.type = IIO_TEMP,
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_PROCESSED),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
}
};
static ssize_t tsys02_read_battery_low(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct ms_ht_dev *dev_data = iio_priv(indio_dev);
return ms_sensors_show_battery_low(dev_data, buf);
}
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(tsys02d_show_samp_freq);
static IIO_DEVICE_ATTR(battery_low, S_IRUGO,
tsys02_read_battery_low, NULL, 0);
static struct attribute *tsys02d_attributes[] = {
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
&iio_dev_attr_battery_low.dev_attr.attr,
NULL,
};
static const struct attribute_group tsys02d_attribute_group = {
.attrs = tsys02d_attributes,
};
static const struct iio_info tsys02d_info = {
.read_raw = tsys02d_read_raw,
.write_raw = tsys02d_write_raw,
.attrs = &tsys02d_attribute_group,
};
static int tsys02d_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct ms_ht_dev *dev_data;
struct iio_dev *indio_dev;
int ret;
u64 serial_number;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_WRITE_BYTE_DATA |
I2C_FUNC_SMBUS_WRITE_BYTE |
I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
dev_err(&client->dev,
"Adapter does not support some i2c transaction\n");
return -EOPNOTSUPP;
}
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*dev_data));
if (!indio_dev)
return -ENOMEM;
dev_data = iio_priv(indio_dev);
dev_data->client = client;
dev_data->res_index = 0;
mutex_init(&dev_data->lock);
indio_dev->info = &tsys02d_info;
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = tsys02d_channels;
indio_dev->num_channels = ARRAY_SIZE(tsys02d_channels);
i2c_set_clientdata(client, indio_dev);
ret = ms_sensors_reset(client, TSYS02D_RESET, 15000);
if (ret)
return ret;
ret = ms_sensors_read_serial(client, &serial_number);
if (ret)
return ret;
dev_info(&client->dev, "Serial number : %llx", serial_number);
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id tsys02d_id[] = {
{"tsys02d", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, tsys02d_id);
static struct i2c_driver tsys02d_driver = {
.probe = tsys02d_probe,
.id_table = tsys02d_id,
.driver = {
.name = "tsys02d",
},
};
module_i2c_driver(tsys02d_driver);
MODULE_DESCRIPTION("Measurement-Specialties tsys02d temperature driver");
MODULE_AUTHOR("William Markezana <[email protected]>");
MODULE_AUTHOR("Ludovic Tancerel <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_MEAS_SPEC_SENSORS);
| linux-master | drivers/iio/temperature/tsys02d.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tmp006.c - Support for TI TMP006 IR thermopile sensor
*
* Copyright (c) 2013 Peter Meerwald <[email protected]>
*
* Driver for the Texas Instruments I2C 16-bit IR thermopile sensor
*
* (7-bit I2C slave address 0x40, changeable via ADR pins)
*
* TODO: data ready irq
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/pm.h>
#include <linux/bitops.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define TMP006_VOBJECT 0x00
#define TMP006_TAMBIENT 0x01
#define TMP006_CONFIG 0x02
#define TMP006_MANUFACTURER_ID 0xfe
#define TMP006_DEVICE_ID 0xff
#define TMP006_TAMBIENT_SHIFT 2
#define TMP006_CONFIG_RESET BIT(15)
#define TMP006_CONFIG_DRDY_EN BIT(8)
#define TMP006_CONFIG_DRDY BIT(7)
#define TMP006_CONFIG_MOD_MASK GENMASK(14, 12)
#define TMP006_CONFIG_CR_MASK GENMASK(11, 9)
#define TMP006_CONFIG_CR_SHIFT 9
#define TMP006_MANUFACTURER_MAGIC 0x5449
#define TMP006_DEVICE_MAGIC 0x0067
struct tmp006_data {
struct i2c_client *client;
u16 config;
};
static int tmp006_read_measurement(struct tmp006_data *data, u8 reg)
{
s32 ret;
int tries = 50;
while (tries-- > 0) {
ret = i2c_smbus_read_word_swapped(data->client,
TMP006_CONFIG);
if (ret < 0)
return ret;
if (ret & TMP006_CONFIG_DRDY)
break;
msleep(100);
}
if (tries < 0)
return -EIO;
return i2c_smbus_read_word_swapped(data->client, reg);
}
static const int tmp006_freqs[5][2] = { {4, 0}, {2, 0}, {1, 0},
{0, 500000}, {0, 250000} };
static int tmp006_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
struct tmp006_data *data = iio_priv(indio_dev);
s32 ret;
int cr;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (channel->type == IIO_VOLTAGE) {
/* LSB is 156.25 nV */
ret = tmp006_read_measurement(data, TMP006_VOBJECT);
if (ret < 0)
return ret;
*val = sign_extend32(ret, 15);
} else if (channel->type == IIO_TEMP) {
/* LSB is 0.03125 degrees Celsius */
ret = tmp006_read_measurement(data, TMP006_TAMBIENT);
if (ret < 0)
return ret;
*val = sign_extend32(ret, 15) >> TMP006_TAMBIENT_SHIFT;
} else {
break;
}
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
if (channel->type == IIO_VOLTAGE) {
*val = 0;
*val2 = 156250;
} else if (channel->type == IIO_TEMP) {
*val = 31;
*val2 = 250000;
} else {
break;
}
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_SAMP_FREQ:
cr = (data->config & TMP006_CONFIG_CR_MASK)
>> TMP006_CONFIG_CR_SHIFT;
*val = tmp006_freqs[cr][0];
*val2 = tmp006_freqs[cr][1];
return IIO_VAL_INT_PLUS_MICRO;
default:
break;
}
return -EINVAL;
}
static int tmp006_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct tmp006_data *data = iio_priv(indio_dev);
int i;
if (mask != IIO_CHAN_INFO_SAMP_FREQ)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(tmp006_freqs); i++)
if ((val == tmp006_freqs[i][0]) &&
(val2 == tmp006_freqs[i][1])) {
data->config &= ~TMP006_CONFIG_CR_MASK;
data->config |= i << TMP006_CONFIG_CR_SHIFT;
return i2c_smbus_write_word_swapped(data->client,
TMP006_CONFIG,
data->config);
}
return -EINVAL;
}
static IIO_CONST_ATTR(sampling_frequency_available, "4 2 1 0.5 0.25");
static struct attribute *tmp006_attributes[] = {
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL
};
static const struct attribute_group tmp006_attribute_group = {
.attrs = tmp006_attributes,
};
static const struct iio_chan_spec tmp006_channels[] = {
{
.type = IIO_VOLTAGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
},
{
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
}
};
static const struct iio_info tmp006_info = {
.read_raw = tmp006_read_raw,
.write_raw = tmp006_write_raw,
.attrs = &tmp006_attribute_group,
};
static bool tmp006_check_identification(struct i2c_client *client)
{
int mid, did;
mid = i2c_smbus_read_word_swapped(client, TMP006_MANUFACTURER_ID);
if (mid < 0)
return false;
did = i2c_smbus_read_word_swapped(client, TMP006_DEVICE_ID);
if (did < 0)
return false;
return mid == TMP006_MANUFACTURER_MAGIC && did == TMP006_DEVICE_MAGIC;
}
static int tmp006_power(struct device *dev, bool up)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct tmp006_data *data = iio_priv(indio_dev);
if (up)
data->config |= TMP006_CONFIG_MOD_MASK;
else
data->config &= ~TMP006_CONFIG_MOD_MASK;
return i2c_smbus_write_word_swapped(data->client, TMP006_CONFIG,
data->config);
}
static void tmp006_powerdown_cleanup(void *dev)
{
tmp006_power(dev, false);
}
static int tmp006_probe(struct i2c_client *client)
{
struct iio_dev *indio_dev;
struct tmp006_data *data;
int ret;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA))
return -EOPNOTSUPP;
if (!tmp006_check_identification(client)) {
dev_err(&client->dev, "no TMP006 sensor\n");
return -ENODEV;
}
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
indio_dev->name = dev_name(&client->dev);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &tmp006_info;
indio_dev->channels = tmp006_channels;
indio_dev->num_channels = ARRAY_SIZE(tmp006_channels);
ret = i2c_smbus_read_word_swapped(data->client, TMP006_CONFIG);
if (ret < 0)
return ret;
data->config = ret;
if ((ret & TMP006_CONFIG_MOD_MASK) != TMP006_CONFIG_MOD_MASK) {
ret = tmp006_power(&client->dev, true);
if (ret < 0)
return ret;
}
ret = devm_add_action_or_reset(&client->dev, tmp006_powerdown_cleanup,
&client->dev);
if (ret < 0)
return ret;
return devm_iio_device_register(&client->dev, indio_dev);
}
static int tmp006_suspend(struct device *dev)
{
return tmp006_power(dev, false);
}
static int tmp006_resume(struct device *dev)
{
return tmp006_power(dev, true);
}
static DEFINE_SIMPLE_DEV_PM_OPS(tmp006_pm_ops, tmp006_suspend, tmp006_resume);
static const struct of_device_id tmp006_of_match[] = {
{ .compatible = "ti,tmp006" },
{ }
};
MODULE_DEVICE_TABLE(of, tmp006_of_match);
static const struct i2c_device_id tmp006_id[] = {
{ "tmp006", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tmp006_id);
static struct i2c_driver tmp006_driver = {
.driver = {
.name = "tmp006",
.of_match_table = tmp006_of_match,
.pm = pm_sleep_ptr(&tmp006_pm_ops),
},
.probe = tmp006_probe,
.id_table = tmp006_id,
};
module_i2c_driver(tmp006_driver);
MODULE_AUTHOR("Peter Meerwald <[email protected]>");
MODULE_DESCRIPTION("TI TMP006 IR thermopile sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/temperature/tmp006.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* maxim_thermocouple.c - Support for Maxim thermocouple chips
*
* Copyright (C) 2016-2018 Matt Ranostay
* Author: <[email protected]>
*/
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#define MAXIM_THERMOCOUPLE_DRV_NAME "maxim_thermocouple"
enum {
MAX6675,
MAX31855,
MAX31855K,
MAX31855J,
MAX31855N,
MAX31855S,
MAX31855T,
MAX31855E,
MAX31855R,
};
static const char maxim_tc_types[] = {
'K', '?', 'K', 'J', 'N', 'S', 'T', 'E', 'R'
};
static const struct iio_chan_spec max6675_channels[] = {
{ /* thermocouple temperature */
.type = IIO_TEMP,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_THERMOCOUPLE_TYPE),
.scan_index = 0,
.scan_type = {
.sign = 's',
.realbits = 13,
.storagebits = 16,
.shift = 3,
.endianness = IIO_BE,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static const struct iio_chan_spec max31855_channels[] = {
{ /* thermocouple temperature */
.type = IIO_TEMP,
.address = 2,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_THERMOCOUPLE_TYPE),
.scan_index = 0,
.scan_type = {
.sign = 's',
.realbits = 14,
.storagebits = 16,
.shift = 2,
.endianness = IIO_BE,
},
},
{ /* cold junction temperature */
.type = IIO_TEMP,
.address = 0,
.channel2 = IIO_MOD_TEMP_AMBIENT,
.modified = 1,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 1,
.scan_type = {
.sign = 's',
.realbits = 12,
.storagebits = 16,
.shift = 4,
.endianness = IIO_BE,
},
},
IIO_CHAN_SOFT_TIMESTAMP(2),
};
static const unsigned long max31855_scan_masks[] = {0x3, 0};
struct maxim_thermocouple_chip {
const struct iio_chan_spec *channels;
const unsigned long *scan_masks;
u8 num_channels;
u8 read_size;
/* bit-check for valid input */
u32 status_bit;
};
static const struct maxim_thermocouple_chip maxim_thermocouple_chips[] = {
[MAX6675] = {
.channels = max6675_channels,
.num_channels = ARRAY_SIZE(max6675_channels),
.read_size = 2,
.status_bit = BIT(2),
},
[MAX31855] = {
.channels = max31855_channels,
.num_channels = ARRAY_SIZE(max31855_channels),
.read_size = 4,
.scan_masks = max31855_scan_masks,
.status_bit = BIT(16),
},
};
struct maxim_thermocouple_data {
struct spi_device *spi;
const struct maxim_thermocouple_chip *chip;
u8 buffer[16] __aligned(IIO_DMA_MINALIGN);
char tc_type;
};
static int maxim_thermocouple_read(struct maxim_thermocouple_data *data,
struct iio_chan_spec const *chan, int *val)
{
unsigned int storage_bytes = data->chip->read_size;
unsigned int shift = chan->scan_type.shift + (chan->address * 8);
__be16 buf16;
__be32 buf32;
int ret;
switch (storage_bytes) {
case 2:
ret = spi_read(data->spi, (void *)&buf16, storage_bytes);
*val = be16_to_cpu(buf16);
break;
case 4:
ret = spi_read(data->spi, (void *)&buf32, storage_bytes);
*val = be32_to_cpu(buf32);
break;
default:
ret = -EINVAL;
}
if (ret)
return ret;
/* check to be sure this is a valid reading */
if (*val & data->chip->status_bit)
return -EINVAL;
*val = sign_extend32(*val >> shift, chan->scan_type.realbits - 1);
return 0;
}
static irqreturn_t maxim_thermocouple_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct maxim_thermocouple_data *data = iio_priv(indio_dev);
int ret;
ret = spi_read(data->spi, data->buffer, data->chip->read_size);
if (!ret) {
iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
iio_get_time_ns(indio_dev));
}
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int maxim_thermocouple_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct maxim_thermocouple_data *data = iio_priv(indio_dev);
int ret = -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = maxim_thermocouple_read(data, chan, val);
iio_device_release_direct_mode(indio_dev);
if (!ret)
return IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SCALE:
switch (chan->channel2) {
case IIO_MOD_TEMP_AMBIENT:
*val = 62;
*val2 = 500000; /* 1000 * 0.0625 */
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
*val = 250; /* 1000 * 0.25 */
ret = IIO_VAL_INT;
}
break;
case IIO_CHAN_INFO_THERMOCOUPLE_TYPE:
*val = data->tc_type;
ret = IIO_VAL_CHAR;
break;
}
return ret;
}
static const struct iio_info maxim_thermocouple_info = {
.read_raw = maxim_thermocouple_read_raw,
};
static int maxim_thermocouple_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct iio_dev *indio_dev;
struct maxim_thermocouple_data *data;
const int chip_type = (id->driver_data == MAX6675) ? MAX6675 : MAX31855;
const struct maxim_thermocouple_chip *chip =
&maxim_thermocouple_chips[chip_type];
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
indio_dev->info = &maxim_thermocouple_info;
indio_dev->name = MAXIM_THERMOCOUPLE_DRV_NAME;
indio_dev->channels = chip->channels;
indio_dev->available_scan_masks = chip->scan_masks;
indio_dev->num_channels = chip->num_channels;
indio_dev->modes = INDIO_DIRECT_MODE;
data = iio_priv(indio_dev);
data->spi = spi;
data->chip = chip;
data->tc_type = maxim_tc_types[id->driver_data];
ret = devm_iio_triggered_buffer_setup(&spi->dev,
indio_dev, NULL,
maxim_thermocouple_trigger_handler, NULL);
if (ret)
return ret;
if (id->driver_data == MAX31855)
dev_warn(&spi->dev, "generic max31855 ID is deprecated\nplease use more specific part type");
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id maxim_thermocouple_id[] = {
{"max6675", MAX6675},
{"max31855", MAX31855},
{"max31855k", MAX31855K},
{"max31855j", MAX31855J},
{"max31855n", MAX31855N},
{"max31855s", MAX31855S},
{"max31855t", MAX31855T},
{"max31855e", MAX31855E},
{"max31855r", MAX31855R},
{},
};
MODULE_DEVICE_TABLE(spi, maxim_thermocouple_id);
static const struct of_device_id maxim_thermocouple_of_match[] = {
{ .compatible = "maxim,max6675" },
{ .compatible = "maxim,max31855" },
{ .compatible = "maxim,max31855k" },
{ .compatible = "maxim,max31855j" },
{ .compatible = "maxim,max31855n" },
{ .compatible = "maxim,max31855s" },
{ .compatible = "maxim,max31855t" },
{ .compatible = "maxim,max31855e" },
{ .compatible = "maxim,max31855r" },
{ },
};
MODULE_DEVICE_TABLE(of, maxim_thermocouple_of_match);
static struct spi_driver maxim_thermocouple_driver = {
.driver = {
.name = MAXIM_THERMOCOUPLE_DRV_NAME,
.of_match_table = maxim_thermocouple_of_match,
},
.probe = maxim_thermocouple_probe,
.id_table = maxim_thermocouple_id,
};
module_spi_driver(maxim_thermocouple_driver);
MODULE_AUTHOR("Matt Ranostay <[email protected]>");
MODULE_DESCRIPTION("Maxim thermocouple sensors");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/temperature/maxim_thermocouple.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ad2s1200.c simple support for the ADI Resolver to Digital Converters:
* AD2S1200/1205
*
* Copyright (c) 2018-2018 David Veenstra <[email protected]>
* Copyright (c) 2010-2010 Analog Devices Inc.
*/
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
#include <linux/spi/spi.h>
#include <linux/sysfs.h>
#include <linux/types.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define DRV_NAME "ad2s1200"
/* input clock on serial interface */
#define AD2S1200_HZ 8192000
/* clock period in nano second */
#define AD2S1200_TSCLK (1000000000 / AD2S1200_HZ)
/**
* struct ad2s1200_state - driver instance specific data.
* @lock: protects both the GPIO pins and the rx buffer.
* @sdev: spi device.
* @sample: GPIO pin SAMPLE.
* @rdvel: GPIO pin RDVEL.
* @rx: buffer for spi transfers.
*/
struct ad2s1200_state {
struct mutex lock;
struct spi_device *sdev;
struct gpio_desc *sample;
struct gpio_desc *rdvel;
__be16 rx __aligned(IIO_DMA_MINALIGN);
};
static int ad2s1200_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct ad2s1200_state *st = iio_priv(indio_dev);
int ret;
switch (m) {
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_ANGL:
/* 2 * Pi / (2^12 - 1) ~= 0.001534355 */
*val = 0;
*val2 = 1534355;
return IIO_VAL_INT_PLUS_NANO;
case IIO_ANGL_VEL:
/* 2 * Pi ~= 6.283185 */
*val = 6;
*val2 = 283185;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
break;
case IIO_CHAN_INFO_RAW:
mutex_lock(&st->lock);
gpiod_set_value(st->sample, 0);
/* delay (6 * AD2S1200_TSCLK + 20) nano seconds */
udelay(1);
gpiod_set_value(st->sample, 1);
gpiod_set_value(st->rdvel, !!(chan->type == IIO_ANGL));
ret = spi_read(st->sdev, &st->rx, 2);
if (ret < 0) {
mutex_unlock(&st->lock);
return ret;
}
switch (chan->type) {
case IIO_ANGL:
*val = be16_to_cpup(&st->rx) >> 4;
break;
case IIO_ANGL_VEL:
*val = sign_extend32(be16_to_cpup(&st->rx) >> 4, 11);
break;
default:
mutex_unlock(&st->lock);
return -EINVAL;
}
/* delay (2 * AD2S1200_TSCLK + 20) ns for sample pulse */
udelay(1);
mutex_unlock(&st->lock);
return IIO_VAL_INT;
default:
break;
}
return -EINVAL;
}
static const struct iio_chan_spec ad2s1200_channels[] = {
{
.type = IIO_ANGL,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
}, {
.type = IIO_ANGL_VEL,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
}
};
static const struct iio_info ad2s1200_info = {
.read_raw = ad2s1200_read_raw,
};
static int ad2s1200_probe(struct spi_device *spi)
{
struct ad2s1200_state *st;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
spi_set_drvdata(spi, indio_dev);
st = iio_priv(indio_dev);
mutex_init(&st->lock);
st->sdev = spi;
st->sample = devm_gpiod_get(&spi->dev, "adi,sample", GPIOD_OUT_LOW);
if (IS_ERR(st->sample)) {
dev_err(&spi->dev, "Failed to claim SAMPLE gpio: err=%ld\n",
PTR_ERR(st->sample));
return PTR_ERR(st->sample);
}
st->rdvel = devm_gpiod_get(&spi->dev, "adi,rdvel", GPIOD_OUT_LOW);
if (IS_ERR(st->rdvel)) {
dev_err(&spi->dev, "Failed to claim RDVEL gpio: err=%ld\n",
PTR_ERR(st->rdvel));
return PTR_ERR(st->rdvel);
}
indio_dev->info = &ad2s1200_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ad2s1200_channels;
indio_dev->num_channels = ARRAY_SIZE(ad2s1200_channels);
indio_dev->name = spi_get_device_id(spi)->name;
spi->max_speed_hz = AD2S1200_HZ;
spi->mode = SPI_MODE_3;
ret = spi_setup(spi);
if (ret < 0) {
dev_err(&spi->dev, "spi_setup failed!\n");
return ret;
}
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct of_device_id ad2s1200_of_match[] = {
{ .compatible = "adi,ad2s1200", },
{ .compatible = "adi,ad2s1205", },
{ }
};
MODULE_DEVICE_TABLE(of, ad2s1200_of_match);
static const struct spi_device_id ad2s1200_id[] = {
{ "ad2s1200" },
{ "ad2s1205" },
{}
};
MODULE_DEVICE_TABLE(spi, ad2s1200_id);
static struct spi_driver ad2s1200_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = ad2s1200_of_match,
},
.probe = ad2s1200_probe,
.id_table = ad2s1200_id,
};
module_spi_driver(ad2s1200_driver);
MODULE_AUTHOR("David Veenstra <[email protected]>");
MODULE_AUTHOR("Graff Yang <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD2S1200/1205 Resolver to Digital SPI driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/resolver/ad2s1200.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ad2s90.c simple support for the ADI Resolver to Digital Converters: AD2S90
*
* Copyright (c) 2010-2010 Analog Devices Inc.
*/
#include <linux/types.h>
#include <linux/mutex.h>
#include <linux/device.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
/*
* Although chip's max frequency is 2Mhz, it needs 600ns between CS and the
* first falling edge of SCLK, so frequency should be at most 1 / (2 * 6e-7)
*/
#define AD2S90_MAX_SPI_FREQ_HZ 830000
struct ad2s90_state {
struct mutex lock; /* lock to protect rx buffer */
struct spi_device *sdev;
u8 rx[2] __aligned(IIO_DMA_MINALIGN);
};
static int ad2s90_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
int ret;
struct ad2s90_state *st = iio_priv(indio_dev);
if (chan->type != IIO_ANGL)
return -EINVAL;
switch (m) {
case IIO_CHAN_INFO_SCALE:
/* 2 * Pi / 2^12 */
*val = 6283; /* mV */
*val2 = 12;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_RAW:
mutex_lock(&st->lock);
ret = spi_read(st->sdev, st->rx, 2);
if (ret < 0) {
mutex_unlock(&st->lock);
return ret;
}
*val = (((u16)(st->rx[0])) << 4) | ((st->rx[1] & 0xF0) >> 4);
mutex_unlock(&st->lock);
return IIO_VAL_INT;
default:
break;
}
return -EINVAL;
}
static const struct iio_info ad2s90_info = {
.read_raw = ad2s90_read_raw,
};
static const struct iio_chan_spec ad2s90_chan = {
.type = IIO_ANGL,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
};
static int ad2s90_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct ad2s90_state *st;
if (spi->max_speed_hz > AD2S90_MAX_SPI_FREQ_HZ) {
dev_err(&spi->dev, "SPI CLK, %d Hz exceeds %d Hz\n",
spi->max_speed_hz, AD2S90_MAX_SPI_FREQ_HZ);
return -EINVAL;
}
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
mutex_init(&st->lock);
st->sdev = spi;
indio_dev->info = &ad2s90_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = &ad2s90_chan;
indio_dev->num_channels = 1;
indio_dev->name = spi_get_device_id(spi)->name;
return devm_iio_device_register(indio_dev->dev.parent, indio_dev);
}
static const struct of_device_id ad2s90_of_match[] = {
{ .compatible = "adi,ad2s90", },
{}
};
MODULE_DEVICE_TABLE(of, ad2s90_of_match);
static const struct spi_device_id ad2s90_id[] = {
{ "ad2s90" },
{}
};
MODULE_DEVICE_TABLE(spi, ad2s90_id);
static struct spi_driver ad2s90_driver = {
.driver = {
.name = "ad2s90",
.of_match_table = ad2s90_of_match,
},
.probe = ad2s90_probe,
.id_table = ad2s90_id,
};
module_spi_driver(ad2s90_driver);
MODULE_AUTHOR("Graff Yang <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD2S90 Resolver to Digital SPI driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/resolver/ad2s90.c |
// SPDX-License-Identifier: GPL-2.0
/*
* BME680 - SPI Driver
*
* Copyright (C) 2018 Himanshu Jha <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include "bme680.h"
struct bme680_spi_bus_context {
struct spi_device *spi;
u8 current_page;
};
/*
* In SPI mode there are only 7 address bits, a "page" register determines
* which part of the 8-bit range is active. This function looks at the address
* and writes the page selection bit if needed
*/
static int bme680_regmap_spi_select_page(
struct bme680_spi_bus_context *ctx, u8 reg)
{
struct spi_device *spi = ctx->spi;
int ret;
u8 buf[2];
u8 page = (reg & 0x80) ? 0 : 1; /* Page "1" is low range */
if (page == ctx->current_page)
return 0;
/*
* Data sheet claims we're only allowed to change bit 4, so we must do
* a read-modify-write on each and every page select
*/
buf[0] = BME680_REG_STATUS;
ret = spi_write_then_read(spi, buf, 1, buf + 1, 1);
if (ret < 0) {
dev_err(&spi->dev, "failed to set page %u\n", page);
return ret;
}
buf[0] = BME680_REG_STATUS;
if (page)
buf[1] |= BME680_SPI_MEM_PAGE_BIT;
else
buf[1] &= ~BME680_SPI_MEM_PAGE_BIT;
ret = spi_write(spi, buf, 2);
if (ret < 0) {
dev_err(&spi->dev, "failed to set page %u\n", page);
return ret;
}
ctx->current_page = page;
return 0;
}
static int bme680_regmap_spi_write(void *context, const void *data,
size_t count)
{
struct bme680_spi_bus_context *ctx = context;
struct spi_device *spi = ctx->spi;
int ret;
u8 buf[2];
memcpy(buf, data, 2);
ret = bme680_regmap_spi_select_page(ctx, buf[0]);
if (ret)
return ret;
/*
* The SPI register address (= full register address without bit 7)
* and the write command (bit7 = RW = '0')
*/
buf[0] &= ~0x80;
return spi_write(spi, buf, 2);
}
static int bme680_regmap_spi_read(void *context, const void *reg,
size_t reg_size, void *val, size_t val_size)
{
struct bme680_spi_bus_context *ctx = context;
struct spi_device *spi = ctx->spi;
int ret;
u8 addr = *(const u8 *)reg;
ret = bme680_regmap_spi_select_page(ctx, addr);
if (ret)
return ret;
addr |= 0x80; /* bit7 = RW = '1' */
return spi_write_then_read(spi, &addr, 1, val, val_size);
}
static struct regmap_bus bme680_regmap_bus = {
.write = bme680_regmap_spi_write,
.read = bme680_regmap_spi_read,
.reg_format_endian_default = REGMAP_ENDIAN_BIG,
.val_format_endian_default = REGMAP_ENDIAN_BIG,
};
static int bme680_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct bme680_spi_bus_context *bus_context;
struct regmap *regmap;
int ret;
spi->bits_per_word = 8;
ret = spi_setup(spi);
if (ret < 0) {
dev_err(&spi->dev, "spi_setup failed!\n");
return ret;
}
bus_context = devm_kzalloc(&spi->dev, sizeof(*bus_context), GFP_KERNEL);
if (!bus_context)
return -ENOMEM;
bus_context->spi = spi;
bus_context->current_page = 0xff; /* Undefined on warm boot */
regmap = devm_regmap_init(&spi->dev, &bme680_regmap_bus,
bus_context, &bme680_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&spi->dev, "Failed to register spi regmap %ld\n", PTR_ERR(regmap));
return PTR_ERR(regmap);
}
return bme680_core_probe(&spi->dev, regmap, id->name);
}
static const struct spi_device_id bme680_spi_id[] = {
{"bme680", 0},
{},
};
MODULE_DEVICE_TABLE(spi, bme680_spi_id);
static const struct of_device_id bme680_of_spi_match[] = {
{ .compatible = "bosch,bme680", },
{},
};
MODULE_DEVICE_TABLE(of, bme680_of_spi_match);
static struct spi_driver bme680_spi_driver = {
.driver = {
.name = "bme680_spi",
.of_match_table = bme680_of_spi_match,
},
.probe = bme680_spi_probe,
.id_table = bme680_spi_id,
};
module_spi_driver(bme680_spi_driver);
MODULE_AUTHOR("Himanshu Jha <[email protected]>");
MODULE_DESCRIPTION("Bosch BME680 SPI driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_BME680);
| linux-master | drivers/iio/chemical/bme680_spi.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* atlas-ezo-sensor.c - Support for Atlas Scientific EZO sensors
*
* Copyright (C) 2020 Konsulko Group
* Author: Matt Ranostay <[email protected]>
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/property.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#define ATLAS_EZO_DRV_NAME "atlas-ezo-sensor"
#define ATLAS_INT_TIME_IN_MS 950
#define ATLAS_INT_HUM_TIME_IN_MS 350
enum {
ATLAS_CO2_EZO,
ATLAS_O2_EZO,
ATLAS_HUM_EZO,
};
struct atlas_ezo_device {
const struct iio_chan_spec *channels;
int num_channels;
int delay;
};
struct atlas_ezo_data {
struct i2c_client *client;
const struct atlas_ezo_device *chip;
/* lock to avoid multiple concurrent read calls */
struct mutex lock;
u8 buffer[8];
};
#define ATLAS_CONCENTRATION_CHANNEL(_modifier) \
{ \
.type = IIO_CONCENTRATION, \
.modified = 1,\
.channel2 = _modifier, \
.info_mask_separate = \
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), \
.scan_index = 0, \
.scan_type = { \
.sign = 'u', \
.realbits = 32, \
.storagebits = 32, \
.endianness = IIO_CPU, \
}, \
}
static const struct iio_chan_spec atlas_co2_ezo_channels[] = {
ATLAS_CONCENTRATION_CHANNEL(IIO_MOD_CO2),
};
static const struct iio_chan_spec atlas_o2_ezo_channels[] = {
ATLAS_CONCENTRATION_CHANNEL(IIO_MOD_O2),
};
static const struct iio_chan_spec atlas_hum_ezo_channels[] = {
{
.type = IIO_HUMIDITYRELATIVE,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 0,
.scan_type = {
.sign = 'u',
.realbits = 32,
.storagebits = 32,
.endianness = IIO_CPU,
},
},
};
static struct atlas_ezo_device atlas_ezo_devices[] = {
[ATLAS_CO2_EZO] = {
.channels = atlas_co2_ezo_channels,
.num_channels = 1,
.delay = ATLAS_INT_TIME_IN_MS,
},
[ATLAS_O2_EZO] = {
.channels = atlas_o2_ezo_channels,
.num_channels = 1,
.delay = ATLAS_INT_TIME_IN_MS,
},
[ATLAS_HUM_EZO] = {
.channels = atlas_hum_ezo_channels,
.num_channels = 1,
.delay = ATLAS_INT_HUM_TIME_IN_MS,
},
};
static void atlas_ezo_sanitize(char *buf)
{
char *ptr = strchr(buf, '.');
if (!ptr)
return;
memmove(ptr, ptr + 1, strlen(ptr));
}
static int atlas_ezo_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct atlas_ezo_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
if (chan->type != IIO_CONCENTRATION)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW: {
int ret;
long tmp;
mutex_lock(&data->lock);
tmp = i2c_smbus_write_byte(client, 'R');
if (tmp < 0) {
mutex_unlock(&data->lock);
return tmp;
}
msleep(data->chip->delay);
tmp = i2c_master_recv(client, data->buffer, sizeof(data->buffer));
if (tmp < 0 || data->buffer[0] != 1) {
mutex_unlock(&data->lock);
return -EBUSY;
}
/* removing floating point for fixed number representation */
atlas_ezo_sanitize(data->buffer + 2);
ret = kstrtol(data->buffer + 1, 10, &tmp);
*val = tmp;
mutex_unlock(&data->lock);
return ret ? ret : IIO_VAL_INT;
}
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_HUMIDITYRELATIVE:
*val = 10;
return IIO_VAL_INT;
case IIO_CONCENTRATION:
break;
default:
return -EINVAL;
}
/* IIO_CONCENTRATION modifiers */
switch (chan->channel2) {
case IIO_MOD_CO2:
*val = 0;
*val2 = 100; /* 0.0001 */
return IIO_VAL_INT_PLUS_MICRO;
case IIO_MOD_O2:
*val = 100;
return IIO_VAL_INT;
}
return -EINVAL;
}
return 0;
}
static const struct iio_info atlas_info = {
.read_raw = atlas_ezo_read_raw,
};
static const struct i2c_device_id atlas_ezo_id[] = {
{ "atlas-co2-ezo", (kernel_ulong_t)&atlas_ezo_devices[ATLAS_CO2_EZO] },
{ "atlas-o2-ezo", (kernel_ulong_t)&atlas_ezo_devices[ATLAS_O2_EZO] },
{ "atlas-hum-ezo", (kernel_ulong_t)&atlas_ezo_devices[ATLAS_HUM_EZO] },
{}
};
MODULE_DEVICE_TABLE(i2c, atlas_ezo_id);
static const struct of_device_id atlas_ezo_dt_ids[] = {
{ .compatible = "atlas,co2-ezo", .data = &atlas_ezo_devices[ATLAS_CO2_EZO], },
{ .compatible = "atlas,o2-ezo", .data = &atlas_ezo_devices[ATLAS_O2_EZO], },
{ .compatible = "atlas,hum-ezo", .data = &atlas_ezo_devices[ATLAS_HUM_EZO], },
{}
};
MODULE_DEVICE_TABLE(of, atlas_ezo_dt_ids);
static int atlas_ezo_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
const struct atlas_ezo_device *chip;
struct atlas_ezo_data *data;
struct iio_dev *indio_dev;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
if (dev_fwnode(&client->dev))
chip = device_get_match_data(&client->dev);
else
chip = (const struct atlas_ezo_device *)id->driver_data;
if (!chip)
return -EINVAL;
indio_dev->info = &atlas_info;
indio_dev->name = ATLAS_EZO_DRV_NAME;
indio_dev->channels = chip->channels;
indio_dev->num_channels = chip->num_channels;
indio_dev->modes = INDIO_DIRECT_MODE;
data = iio_priv(indio_dev);
data->client = client;
data->chip = chip;
mutex_init(&data->lock);
return devm_iio_device_register(&client->dev, indio_dev);
};
static struct i2c_driver atlas_ezo_driver = {
.driver = {
.name = ATLAS_EZO_DRV_NAME,
.of_match_table = atlas_ezo_dt_ids,
},
.probe = atlas_ezo_probe,
.id_table = atlas_ezo_id,
};
module_i2c_driver(atlas_ezo_driver);
MODULE_AUTHOR("Matt Ranostay <[email protected]>");
MODULE_DESCRIPTION("Atlas Scientific EZO sensors");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/chemical/atlas-ezo-sensor.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Sensirion SPS30 particulate matter sensor i2c driver
*
* Copyright (c) 2020 Tomasz Duszynski <[email protected]>
*
* I2C slave address: 0x69
*/
#include <asm/unaligned.h>
#include <linux/crc8.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/types.h>
#include "sps30.h"
#define SPS30_I2C_CRC8_POLYNOMIAL 0x31
/* max number of bytes needed to store PM measurements or serial string */
#define SPS30_I2C_MAX_BUF_SIZE 48
DECLARE_CRC8_TABLE(sps30_i2c_crc8_table);
#define SPS30_I2C_START_MEAS 0x0010
#define SPS30_I2C_STOP_MEAS 0x0104
#define SPS30_I2C_READ_MEAS 0x0300
#define SPS30_I2C_MEAS_READY 0x0202
#define SPS30_I2C_RESET 0xd304
#define SPS30_I2C_CLEAN_FAN 0x5607
#define SPS30_I2C_PERIOD 0x8004
#define SPS30_I2C_READ_SERIAL 0xd033
#define SPS30_I2C_READ_VERSION 0xd100
static int sps30_i2c_xfer(struct sps30_state *state, unsigned char *txbuf, size_t txsize,
unsigned char *rxbuf, size_t rxsize)
{
struct i2c_client *client = to_i2c_client(state->dev);
int ret;
/*
* Sensor does not support repeated start so instead of
* sending two i2c messages in a row we just send one by one.
*/
ret = i2c_master_send(client, txbuf, txsize);
if (ret < 0)
return ret;
if (ret != txsize)
return -EIO;
if (!rxsize)
return 0;
ret = i2c_master_recv(client, rxbuf, rxsize);
if (ret < 0)
return ret;
if (ret != rxsize)
return -EIO;
return 0;
}
static int sps30_i2c_command(struct sps30_state *state, u16 cmd, void *arg, size_t arg_size,
void *rsp, size_t rsp_size)
{
/*
* Internally sensor stores measurements in a following manner:
*
* PM1: upper two bytes, crc8, lower two bytes, crc8
* PM2P5: upper two bytes, crc8, lower two bytes, crc8
* PM4: upper two bytes, crc8, lower two bytes, crc8
* PM10: upper two bytes, crc8, lower two bytes, crc8
*
* What follows next are number concentration measurements and
* typical particle size measurement which we omit.
*/
unsigned char buf[SPS30_I2C_MAX_BUF_SIZE];
unsigned char *tmp;
unsigned char crc;
size_t i;
int ret;
put_unaligned_be16(cmd, buf);
i = 2;
if (rsp) {
/* each two bytes are followed by a crc8 */
rsp_size += rsp_size / 2;
} else {
tmp = arg;
while (arg_size) {
buf[i] = *tmp++;
buf[i + 1] = *tmp++;
buf[i + 2] = crc8(sps30_i2c_crc8_table, buf + i, 2, CRC8_INIT_VALUE);
arg_size -= 2;
i += 3;
}
}
ret = sps30_i2c_xfer(state, buf, i, buf, rsp_size);
if (ret)
return ret;
/* validate received data and strip off crc bytes */
tmp = rsp;
for (i = 0; i < rsp_size; i += 3) {
crc = crc8(sps30_i2c_crc8_table, buf + i, 2, CRC8_INIT_VALUE);
if (crc != buf[i + 2]) {
dev_err(state->dev, "data integrity check failed\n");
return -EIO;
}
*tmp++ = buf[i];
*tmp++ = buf[i + 1];
}
return 0;
}
static int sps30_i2c_start_meas(struct sps30_state *state)
{
/* request BE IEEE754 formatted data */
unsigned char buf[] = { 0x03, 0x00 };
return sps30_i2c_command(state, SPS30_I2C_START_MEAS, buf, sizeof(buf), NULL, 0);
}
static int sps30_i2c_stop_meas(struct sps30_state *state)
{
return sps30_i2c_command(state, SPS30_I2C_STOP_MEAS, NULL, 0, NULL, 0);
}
static int sps30_i2c_reset(struct sps30_state *state)
{
int ret;
ret = sps30_i2c_command(state, SPS30_I2C_RESET, NULL, 0, NULL, 0);
msleep(500);
/*
* Power-on-reset causes sensor to produce some glitch on i2c bus and
* some controllers end up in error state. Recover simply by placing
* some data on the bus, for example STOP_MEAS command, which
* is NOP in this case.
*/
sps30_i2c_stop_meas(state);
return ret;
}
static bool sps30_i2c_meas_ready(struct sps30_state *state)
{
unsigned char buf[2];
int ret;
ret = sps30_i2c_command(state, SPS30_I2C_MEAS_READY, NULL, 0, buf, sizeof(buf));
if (ret)
return false;
return buf[1];
}
static int sps30_i2c_read_meas(struct sps30_state *state, __be32 *meas, size_t num)
{
/* measurements are ready within a second */
if (msleep_interruptible(1000))
return -EINTR;
if (!sps30_i2c_meas_ready(state))
return -ETIMEDOUT;
return sps30_i2c_command(state, SPS30_I2C_READ_MEAS, NULL, 0, meas, sizeof(num) * num);
}
static int sps30_i2c_clean_fan(struct sps30_state *state)
{
return sps30_i2c_command(state, SPS30_I2C_CLEAN_FAN, NULL, 0, NULL, 0);
}
static int sps30_i2c_read_cleaning_period(struct sps30_state *state, __be32 *period)
{
return sps30_i2c_command(state, SPS30_I2C_PERIOD, NULL, 0, period, sizeof(*period));
}
static int sps30_i2c_write_cleaning_period(struct sps30_state *state, __be32 period)
{
return sps30_i2c_command(state, SPS30_I2C_PERIOD, &period, sizeof(period), NULL, 0);
}
static int sps30_i2c_show_info(struct sps30_state *state)
{
/* extra nul just in case */
unsigned char buf[32 + 1] = { 0x00 };
int ret;
ret = sps30_i2c_command(state, SPS30_I2C_READ_SERIAL, NULL, 0, buf, sizeof(buf) - 1);
if (ret)
return ret;
dev_info(state->dev, "serial number: %s\n", buf);
ret = sps30_i2c_command(state, SPS30_I2C_READ_VERSION, NULL, 0, buf, 2);
if (ret)
return ret;
dev_info(state->dev, "fw version: %u.%u\n", buf[0], buf[1]);
return 0;
}
static const struct sps30_ops sps30_i2c_ops = {
.start_meas = sps30_i2c_start_meas,
.stop_meas = sps30_i2c_stop_meas,
.read_meas = sps30_i2c_read_meas,
.reset = sps30_i2c_reset,
.clean_fan = sps30_i2c_clean_fan,
.read_cleaning_period = sps30_i2c_read_cleaning_period,
.write_cleaning_period = sps30_i2c_write_cleaning_period,
.show_info = sps30_i2c_show_info,
};
static int sps30_i2c_probe(struct i2c_client *client)
{
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -EOPNOTSUPP;
crc8_populate_msb(sps30_i2c_crc8_table, SPS30_I2C_CRC8_POLYNOMIAL);
return sps30_probe(&client->dev, client->name, NULL, &sps30_i2c_ops);
}
static const struct i2c_device_id sps30_i2c_id[] = {
{ "sps30" },
{ }
};
MODULE_DEVICE_TABLE(i2c, sps30_i2c_id);
static const struct of_device_id sps30_i2c_of_match[] = {
{ .compatible = "sensirion,sps30" },
{ }
};
MODULE_DEVICE_TABLE(of, sps30_i2c_of_match);
static struct i2c_driver sps30_i2c_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = sps30_i2c_of_match,
},
.id_table = sps30_i2c_id,
.probe = sps30_i2c_probe,
};
module_i2c_driver(sps30_i2c_driver);
MODULE_AUTHOR("Tomasz Duszynski <[email protected]>");
MODULE_DESCRIPTION("Sensirion SPS30 particulate matter sensor i2c driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_SPS30);
| linux-master | drivers/iio/chemical/sps30_i2c.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Sensirion SCD4X carbon dioxide sensor i2c driver
*
* Copyright (C) 2021 Protonic Holland
* Author: Roan van Dijk <[email protected]>
*
* I2C slave address: 0x62
*
* Datasheets:
* https://www.sensirion.com/file/datasheet_scd4x
*/
#include <asm/unaligned.h>
#include <linux/crc8.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/types.h>
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/string.h>
#include <linux/sysfs.h>
#include <linux/types.h>
#define SCD4X_CRC8_POLYNOMIAL 0x31
#define SCD4X_TIMEOUT_ERR 1000
#define SCD4X_READ_BUF_SIZE 9
#define SCD4X_COMMAND_BUF_SIZE 2
#define SCD4X_WRITE_BUF_SIZE 5
#define SCD4X_FRC_MIN_PPM 0
#define SCD4X_FRC_MAX_PPM 2000
#define SCD4X_PRESSURE_COMP_MIN_MBAR 700
#define SCD4X_PRESSURE_COMP_MAX_MBAR 1200
#define SCD4X_READY_MASK 0x01
/*Commands SCD4X*/
enum scd4x_cmd {
CMD_START_MEAS = 0x21b1,
CMD_READ_MEAS = 0xec05,
CMD_STOP_MEAS = 0x3f86,
CMD_SET_TEMP_OFFSET = 0x241d,
CMD_GET_TEMP_OFFSET = 0x2318,
CMD_SET_AMB_PRESSURE = 0xe000,
CMD_GET_AMB_PRESSURE = 0xe000,
CMD_FRC = 0x362f,
CMD_SET_ASC = 0x2416,
CMD_GET_ASC = 0x2313,
CMD_GET_DATA_READY = 0xe4b8,
};
enum scd4x_channel_idx {
SCD4X_CO2,
SCD4X_TEMP,
SCD4X_HR,
};
struct scd4x_state {
struct i2c_client *client;
/* maintain access to device, to prevent concurrent reads/writes */
struct mutex lock;
struct regulator *vdd;
};
DECLARE_CRC8_TABLE(scd4x_crc8_table);
static int scd4x_i2c_xfer(struct scd4x_state *state, char *txbuf, int txsize,
char *rxbuf, int rxsize)
{
struct i2c_client *client = state->client;
int ret;
ret = i2c_master_send(client, txbuf, txsize);
if (ret < 0)
return ret;
if (ret != txsize)
return -EIO;
if (rxsize == 0)
return 0;
ret = i2c_master_recv(client, rxbuf, rxsize);
if (ret < 0)
return ret;
if (ret != rxsize)
return -EIO;
return 0;
}
static int scd4x_send_command(struct scd4x_state *state, enum scd4x_cmd cmd)
{
char buf[SCD4X_COMMAND_BUF_SIZE];
int ret;
/*
* Measurement needs to be stopped before sending commands.
* Except stop and start command.
*/
if ((cmd != CMD_STOP_MEAS) && (cmd != CMD_START_MEAS)) {
ret = scd4x_send_command(state, CMD_STOP_MEAS);
if (ret)
return ret;
/* execution time for stopping measurement */
msleep_interruptible(500);
}
put_unaligned_be16(cmd, buf);
ret = scd4x_i2c_xfer(state, buf, 2, buf, 0);
if (ret)
return ret;
if ((cmd != CMD_STOP_MEAS) && (cmd != CMD_START_MEAS)) {
ret = scd4x_send_command(state, CMD_START_MEAS);
if (ret)
return ret;
}
return 0;
}
static int scd4x_read(struct scd4x_state *state, enum scd4x_cmd cmd,
void *response, int response_sz)
{
struct i2c_client *client = state->client;
char buf[SCD4X_READ_BUF_SIZE];
char *rsp = response;
int i, ret;
char crc;
/*
* Measurement needs to be stopped before sending commands.
* Except for reading measurement and data ready command.
*/
if ((cmd != CMD_GET_DATA_READY) && (cmd != CMD_READ_MEAS) &&
(cmd != CMD_GET_AMB_PRESSURE)) {
ret = scd4x_send_command(state, CMD_STOP_MEAS);
if (ret)
return ret;
/* execution time for stopping measurement */
msleep_interruptible(500);
}
/* CRC byte for every 2 bytes of data */
response_sz += response_sz / 2;
put_unaligned_be16(cmd, buf);
ret = scd4x_i2c_xfer(state, buf, 2, buf, response_sz);
if (ret)
return ret;
for (i = 0; i < response_sz; i += 3) {
crc = crc8(scd4x_crc8_table, buf + i, 2, CRC8_INIT_VALUE);
if (crc != buf[i + 2]) {
dev_err(&client->dev, "CRC error\n");
return -EIO;
}
*rsp++ = buf[i];
*rsp++ = buf[i + 1];
}
/* start measurement */
if ((cmd != CMD_GET_DATA_READY) && (cmd != CMD_READ_MEAS) &&
(cmd != CMD_GET_AMB_PRESSURE)) {
ret = scd4x_send_command(state, CMD_START_MEAS);
if (ret)
return ret;
}
return 0;
}
static int scd4x_write(struct scd4x_state *state, enum scd4x_cmd cmd, uint16_t arg)
{
char buf[SCD4X_WRITE_BUF_SIZE];
int ret;
char crc;
put_unaligned_be16(cmd, buf);
put_unaligned_be16(arg, buf + 2);
crc = crc8(scd4x_crc8_table, buf + 2, 2, CRC8_INIT_VALUE);
buf[4] = crc;
/* measurement needs to be stopped before sending commands */
if (cmd != CMD_SET_AMB_PRESSURE) {
ret = scd4x_send_command(state, CMD_STOP_MEAS);
if (ret)
return ret;
}
/* execution time */
msleep_interruptible(500);
ret = scd4x_i2c_xfer(state, buf, SCD4X_WRITE_BUF_SIZE, buf, 0);
if (ret)
return ret;
/* start measurement, except for forced calibration command */
if ((cmd != CMD_FRC) && (cmd != CMD_SET_AMB_PRESSURE)) {
ret = scd4x_send_command(state, CMD_START_MEAS);
if (ret)
return ret;
}
return 0;
}
static int scd4x_write_and_fetch(struct scd4x_state *state, enum scd4x_cmd cmd,
uint16_t arg, void *response, int response_sz)
{
struct i2c_client *client = state->client;
char buf[SCD4X_READ_BUF_SIZE];
char *rsp = response;
int i, ret;
char crc;
ret = scd4x_write(state, CMD_FRC, arg);
if (ret)
goto err;
/* execution time */
msleep_interruptible(400);
/* CRC byte for every 2 bytes of data */
response_sz += response_sz / 2;
ret = i2c_master_recv(client, buf, response_sz);
if (ret < 0)
goto err;
if (ret != response_sz) {
ret = -EIO;
goto err;
}
for (i = 0; i < response_sz; i += 3) {
crc = crc8(scd4x_crc8_table, buf + i, 2, CRC8_INIT_VALUE);
if (crc != buf[i + 2]) {
dev_err(&client->dev, "CRC error\n");
ret = -EIO;
goto err;
}
*rsp++ = buf[i];
*rsp++ = buf[i + 1];
}
return scd4x_send_command(state, CMD_START_MEAS);
err:
/*
* on error try to start the measurement,
* puts sensor back into continuous measurement
*/
scd4x_send_command(state, CMD_START_MEAS);
return ret;
}
static int scd4x_read_meas(struct scd4x_state *state, uint16_t *meas)
{
int i, ret;
__be16 buf[3];
ret = scd4x_read(state, CMD_READ_MEAS, buf, sizeof(buf));
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(buf); i++)
meas[i] = be16_to_cpu(buf[i]);
return 0;
}
static int scd4x_wait_meas_poll(struct scd4x_state *state)
{
struct i2c_client *client = state->client;
int tries = 6;
int ret;
do {
__be16 bval;
uint16_t val;
ret = scd4x_read(state, CMD_GET_DATA_READY, &bval, sizeof(bval));
if (ret)
return -EIO;
val = be16_to_cpu(bval);
/* new measurement available */
if (val & 0x7FF)
return 0;
msleep_interruptible(1000);
} while (--tries);
/* try to start sensor on timeout */
ret = scd4x_send_command(state, CMD_START_MEAS);
if (ret)
dev_err(&client->dev, "failed to start measurement: %d\n", ret);
return -ETIMEDOUT;
}
static int scd4x_read_poll(struct scd4x_state *state, uint16_t *buf)
{
int ret;
ret = scd4x_wait_meas_poll(state);
if (ret)
return ret;
return scd4x_read_meas(state, buf);
}
static int scd4x_read_channel(struct scd4x_state *state, int chan)
{
int ret;
uint16_t buf[3];
ret = scd4x_read_poll(state, buf);
if (ret)
return ret;
return buf[chan];
}
static int scd4x_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct scd4x_state *state = iio_priv(indio_dev);
int ret;
__be16 tmp;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (chan->output) {
mutex_lock(&state->lock);
ret = scd4x_read(state, CMD_GET_AMB_PRESSURE, &tmp, sizeof(tmp));
mutex_unlock(&state->lock);
if (ret)
return ret;
*val = be16_to_cpu(tmp);
return IIO_VAL_INT;
}
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
mutex_lock(&state->lock);
ret = scd4x_read_channel(state, chan->address);
mutex_unlock(&state->lock);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
if (chan->type == IIO_CONCENTRATION) {
*val = 0;
*val2 = 100;
return IIO_VAL_INT_PLUS_MICRO;
} else if (chan->type == IIO_TEMP) {
*val = 175000;
*val2 = 65536;
return IIO_VAL_FRACTIONAL;
} else if (chan->type == IIO_HUMIDITYRELATIVE) {
*val = 100000;
*val2 = 65536;
return IIO_VAL_FRACTIONAL;
}
return -EINVAL;
case IIO_CHAN_INFO_OFFSET:
*val = -16852;
*val2 = 114286;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_CALIBBIAS:
mutex_lock(&state->lock);
ret = scd4x_read(state, CMD_GET_TEMP_OFFSET, &tmp, sizeof(tmp));
mutex_unlock(&state->lock);
if (ret)
return ret;
*val = be16_to_cpu(tmp);
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static const int scd4x_pressure_calibbias_available[] = {
SCD4X_PRESSURE_COMP_MIN_MBAR, 1, SCD4X_PRESSURE_COMP_MAX_MBAR,
};
static int scd4x_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
const int **vals, int *type, int *length, long mask)
{
switch (mask) {
case IIO_CHAN_INFO_RAW:
*vals = scd4x_pressure_calibbias_available;
*type = IIO_VAL_INT;
return IIO_AVAIL_RANGE;
}
return -EINVAL;
}
static int scd4x_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct scd4x_state *state = iio_priv(indio_dev);
int ret = 0;
switch (mask) {
case IIO_CHAN_INFO_CALIBBIAS:
mutex_lock(&state->lock);
ret = scd4x_write(state, CMD_SET_TEMP_OFFSET, val);
mutex_unlock(&state->lock);
return ret;
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_PRESSURE:
if (val < SCD4X_PRESSURE_COMP_MIN_MBAR ||
val > SCD4X_PRESSURE_COMP_MAX_MBAR)
return -EINVAL;
mutex_lock(&state->lock);
ret = scd4x_write(state, CMD_SET_AMB_PRESSURE, val);
mutex_unlock(&state->lock);
return ret;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static ssize_t calibration_auto_enable_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct scd4x_state *state = iio_priv(indio_dev);
int ret;
__be16 bval;
u16 val;
mutex_lock(&state->lock);
ret = scd4x_read(state, CMD_GET_ASC, &bval, sizeof(bval));
mutex_unlock(&state->lock);
if (ret) {
dev_err(dev, "failed to read automatic calibration");
return ret;
}
val = (be16_to_cpu(bval) & SCD4X_READY_MASK) ? 1 : 0;
return sysfs_emit(buf, "%d\n", val);
}
static ssize_t calibration_auto_enable_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct scd4x_state *state = iio_priv(indio_dev);
bool val;
int ret;
uint16_t value;
ret = kstrtobool(buf, &val);
if (ret)
return ret;
value = val;
mutex_lock(&state->lock);
ret = scd4x_write(state, CMD_SET_ASC, value);
mutex_unlock(&state->lock);
if (ret)
dev_err(dev, "failed to set automatic calibration");
return ret ?: len;
}
static ssize_t calibration_forced_value_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct scd4x_state *state = iio_priv(indio_dev);
uint16_t val, arg;
int ret;
ret = kstrtou16(buf, 0, &arg);
if (ret)
return ret;
if (arg < SCD4X_FRC_MIN_PPM || arg > SCD4X_FRC_MAX_PPM)
return -EINVAL;
mutex_lock(&state->lock);
ret = scd4x_write_and_fetch(state, CMD_FRC, arg, &val, sizeof(val));
mutex_unlock(&state->lock);
if (ret)
return ret;
if (val == 0xff) {
dev_err(dev, "forced calibration has failed");
return -EINVAL;
}
return len;
}
static IIO_DEVICE_ATTR_RW(calibration_auto_enable, 0);
static IIO_DEVICE_ATTR_WO(calibration_forced_value, 0);
static IIO_CONST_ATTR(calibration_forced_value_available,
__stringify([SCD4X_FRC_MIN_PPM 1 SCD4X_FRC_MAX_PPM]));
static struct attribute *scd4x_attrs[] = {
&iio_dev_attr_calibration_auto_enable.dev_attr.attr,
&iio_dev_attr_calibration_forced_value.dev_attr.attr,
&iio_const_attr_calibration_forced_value_available.dev_attr.attr,
NULL
};
static const struct attribute_group scd4x_attr_group = {
.attrs = scd4x_attrs,
};
static const struct iio_info scd4x_info = {
.attrs = &scd4x_attr_group,
.read_raw = scd4x_read_raw,
.write_raw = scd4x_write_raw,
.read_avail = scd4x_read_avail,
};
static const struct iio_chan_spec scd4x_channels[] = {
{
/*
* this channel is special in a sense we are pretending that
* sensor is able to change measurement chamber pressure but in
* fact we're just setting pressure compensation value
*/
.type = IIO_PRESSURE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW),
.output = 1,
.scan_index = -1,
},
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_CO2,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.address = SCD4X_CO2,
.scan_index = SCD4X_CO2,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_BE,
},
},
{
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.address = SCD4X_TEMP,
.scan_index = SCD4X_TEMP,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_BE,
},
},
{
.type = IIO_HUMIDITYRELATIVE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.address = SCD4X_HR,
.scan_index = SCD4X_HR,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_BE,
},
},
};
static int scd4x_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct scd4x_state *state = iio_priv(indio_dev);
int ret;
ret = scd4x_send_command(state, CMD_STOP_MEAS);
if (ret)
return ret;
return regulator_disable(state->vdd);
}
static int scd4x_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct scd4x_state *state = iio_priv(indio_dev);
int ret;
ret = regulator_enable(state->vdd);
if (ret)
return ret;
return scd4x_send_command(state, CMD_START_MEAS);
}
static DEFINE_SIMPLE_DEV_PM_OPS(scd4x_pm_ops, scd4x_suspend, scd4x_resume);
static void scd4x_stop_meas(void *state)
{
scd4x_send_command(state, CMD_STOP_MEAS);
}
static void scd4x_disable_regulator(void *data)
{
struct scd4x_state *state = data;
regulator_disable(state->vdd);
}
static irqreturn_t scd4x_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct scd4x_state *state = iio_priv(indio_dev);
struct {
uint16_t data[3];
int64_t ts __aligned(8);
} scan;
int ret;
memset(&scan, 0, sizeof(scan));
mutex_lock(&state->lock);
ret = scd4x_read_poll(state, scan.data);
mutex_unlock(&state->lock);
if (ret)
goto out;
iio_push_to_buffers_with_timestamp(indio_dev, &scan, iio_get_time_ns(indio_dev));
out:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int scd4x_probe(struct i2c_client *client)
{
static const unsigned long scd4x_scan_masks[] = { 0x07, 0x00 };
struct device *dev = &client->dev;
struct iio_dev *indio_dev;
struct scd4x_state *state;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*state));
if (!indio_dev)
return -ENOMEM;
state = iio_priv(indio_dev);
mutex_init(&state->lock);
state->client = client;
crc8_populate_msb(scd4x_crc8_table, SCD4X_CRC8_POLYNOMIAL);
indio_dev->info = &scd4x_info;
indio_dev->name = client->name;
indio_dev->channels = scd4x_channels;
indio_dev->num_channels = ARRAY_SIZE(scd4x_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->available_scan_masks = scd4x_scan_masks;
state->vdd = devm_regulator_get(dev, "vdd");
if (IS_ERR(state->vdd))
return dev_err_probe(dev, PTR_ERR(state->vdd), "failed to get regulator\n");
ret = regulator_enable(state->vdd);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, scd4x_disable_regulator, state);
if (ret)
return ret;
ret = scd4x_send_command(state, CMD_STOP_MEAS);
if (ret) {
dev_err(dev, "failed to stop measurement: %d\n", ret);
return ret;
}
/* execution time */
msleep_interruptible(500);
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, scd4x_trigger_handler, NULL);
if (ret)
return ret;
ret = scd4x_send_command(state, CMD_START_MEAS);
if (ret) {
dev_err(dev, "failed to start measurement: %d\n", ret);
return ret;
}
ret = devm_add_action_or_reset(dev, scd4x_stop_meas, state);
if (ret)
return ret;
return devm_iio_device_register(dev, indio_dev);
}
static const struct of_device_id scd4x_dt_ids[] = {
{ .compatible = "sensirion,scd40" },
{ .compatible = "sensirion,scd41" },
{ }
};
MODULE_DEVICE_TABLE(of, scd4x_dt_ids);
static struct i2c_driver scd4x_i2c_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = scd4x_dt_ids,
.pm = pm_sleep_ptr(&scd4x_pm_ops),
},
.probe = scd4x_probe,
};
module_i2c_driver(scd4x_i2c_driver);
MODULE_AUTHOR("Roan van Dijk <[email protected]>");
MODULE_DESCRIPTION("Sensirion SCD4X carbon dioxide sensor core driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/chemical/scd4x.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* vz89x.c - Support for SGX Sensortech MiCS VZ89X VOC sensors
*
* Copyright (C) 2015-2018
* Author: Matt Ranostay <[email protected]>
*/
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define VZ89X_REG_MEASUREMENT 0x09
#define VZ89X_REG_MEASUREMENT_RD_SIZE 6
#define VZ89X_REG_MEASUREMENT_WR_SIZE 3
#define VZ89X_VOC_CO2_IDX 0
#define VZ89X_VOC_SHORT_IDX 1
#define VZ89X_VOC_TVOC_IDX 2
#define VZ89X_VOC_RESISTANCE_IDX 3
#define VZ89TE_REG_MEASUREMENT 0x0c
#define VZ89TE_REG_MEASUREMENT_RD_SIZE 7
#define VZ89TE_REG_MEASUREMENT_WR_SIZE 6
#define VZ89TE_VOC_TVOC_IDX 0
#define VZ89TE_VOC_CO2_IDX 1
#define VZ89TE_VOC_RESISTANCE_IDX 2
enum {
VZ89X,
VZ89TE,
};
struct vz89x_chip_data;
struct vz89x_data {
struct i2c_client *client;
const struct vz89x_chip_data *chip;
struct mutex lock;
int (*xfer)(struct vz89x_data *data, u8 cmd);
bool is_valid;
unsigned long last_update;
u8 buffer[VZ89TE_REG_MEASUREMENT_RD_SIZE];
};
struct vz89x_chip_data {
bool (*valid)(struct vz89x_data *data);
const struct iio_chan_spec *channels;
u8 num_channels;
u8 cmd;
u8 read_size;
u8 write_size;
};
static const struct iio_chan_spec vz89x_channels[] = {
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_CO2,
.modified = 1,
.info_mask_separate =
BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_RAW),
.address = VZ89X_VOC_CO2_IDX,
},
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_VOC,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.address = VZ89X_VOC_SHORT_IDX,
.extend_name = "short",
},
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_VOC,
.modified = 1,
.info_mask_separate =
BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_RAW),
.address = VZ89X_VOC_TVOC_IDX,
},
{
.type = IIO_RESISTANCE,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.address = VZ89X_VOC_RESISTANCE_IDX,
.scan_index = -1,
.scan_type = {
.endianness = IIO_LE,
},
},
};
static const struct iio_chan_spec vz89te_channels[] = {
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_VOC,
.modified = 1,
.info_mask_separate =
BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_RAW),
.address = VZ89TE_VOC_TVOC_IDX,
},
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_CO2,
.modified = 1,
.info_mask_separate =
BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_RAW),
.address = VZ89TE_VOC_CO2_IDX,
},
{
.type = IIO_RESISTANCE,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.address = VZ89TE_VOC_RESISTANCE_IDX,
.scan_index = -1,
.scan_type = {
.endianness = IIO_BE,
},
},
};
static IIO_CONST_ATTR(in_concentration_co2_scale, "0.00000698689");
static IIO_CONST_ATTR(in_concentration_voc_scale, "0.00000000436681223");
static struct attribute *vz89x_attributes[] = {
&iio_const_attr_in_concentration_co2_scale.dev_attr.attr,
&iio_const_attr_in_concentration_voc_scale.dev_attr.attr,
NULL,
};
static const struct attribute_group vz89x_attrs_group = {
.attrs = vz89x_attributes,
};
/*
* Chipset sometime updates in the middle of a reading causing it to reset the
* data pointer, and causing invalid reading of previous data.
* We can check for this by reading MSB of the resistance reading that is
* always zero, and by also confirming the VOC_short isn't zero.
*/
static bool vz89x_measurement_is_valid(struct vz89x_data *data)
{
if (data->buffer[VZ89X_VOC_SHORT_IDX] == 0)
return true;
return !!(data->buffer[data->chip->read_size - 1] > 0);
}
/* VZ89TE device has a modified CRC-8 two complement check */
static bool vz89te_measurement_is_valid(struct vz89x_data *data)
{
u8 crc = 0;
int i, sum = 0;
for (i = 0; i < (data->chip->read_size - 1); i++) {
sum = crc + data->buffer[i];
crc = sum;
crc += sum / 256;
}
return !((0xff - crc) == data->buffer[data->chip->read_size - 1]);
}
static int vz89x_i2c_xfer(struct vz89x_data *data, u8 cmd)
{
const struct vz89x_chip_data *chip = data->chip;
struct i2c_client *client = data->client;
struct i2c_msg msg[2];
int ret;
u8 buf[6] = { cmd, 0, 0, 0, 0, 0xf3 };
msg[0].addr = client->addr;
msg[0].flags = client->flags;
msg[0].len = chip->write_size;
msg[0].buf = (char *) &buf;
msg[1].addr = client->addr;
msg[1].flags = client->flags | I2C_M_RD;
msg[1].len = chip->read_size;
msg[1].buf = (char *) &data->buffer;
ret = i2c_transfer(client->adapter, msg, 2);
return (ret == 2) ? 0 : ret;
}
static int vz89x_smbus_xfer(struct vz89x_data *data, u8 cmd)
{
struct i2c_client *client = data->client;
int ret;
int i;
ret = i2c_smbus_write_word_data(client, cmd, 0);
if (ret < 0)
return ret;
for (i = 0; i < data->chip->read_size; i++) {
ret = i2c_smbus_read_byte(client);
if (ret < 0)
return ret;
data->buffer[i] = ret;
}
return 0;
}
static int vz89x_get_measurement(struct vz89x_data *data)
{
const struct vz89x_chip_data *chip = data->chip;
int ret;
/* sensor can only be polled once a second max per datasheet */
if (!time_after(jiffies, data->last_update + HZ))
return data->is_valid ? 0 : -EAGAIN;
data->is_valid = false;
data->last_update = jiffies;
ret = data->xfer(data, chip->cmd);
if (ret < 0)
return ret;
ret = chip->valid(data);
if (ret)
return -EAGAIN;
data->is_valid = true;
return 0;
}
static int vz89x_get_resistance_reading(struct vz89x_data *data,
struct iio_chan_spec const *chan,
int *val)
{
u8 *tmp = &data->buffer[chan->address];
switch (chan->scan_type.endianness) {
case IIO_LE:
*val = le32_to_cpup((__le32 *) tmp) & GENMASK(23, 0);
break;
case IIO_BE:
*val = be32_to_cpup((__be32 *) tmp) >> 8;
break;
default:
return -EINVAL;
}
return 0;
}
static int vz89x_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct vz89x_data *data = iio_priv(indio_dev);
int ret = -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&data->lock);
ret = vz89x_get_measurement(data);
mutex_unlock(&data->lock);
if (ret)
return ret;
switch (chan->type) {
case IIO_CONCENTRATION:
*val = data->buffer[chan->address];
return IIO_VAL_INT;
case IIO_RESISTANCE:
ret = vz89x_get_resistance_reading(data, chan, val);
if (!ret)
return IIO_VAL_INT;
break;
default:
return -EINVAL;
}
break;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_RESISTANCE:
*val = 10;
return IIO_VAL_INT;
default:
return -EINVAL;
}
break;
case IIO_CHAN_INFO_OFFSET:
switch (chan->channel2) {
case IIO_MOD_CO2:
*val = 44;
*val2 = 250000;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_MOD_VOC:
*val = -13;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
return ret;
}
static const struct iio_info vz89x_info = {
.attrs = &vz89x_attrs_group,
.read_raw = vz89x_read_raw,
};
static const struct vz89x_chip_data vz89x_chips[] = {
{
.valid = vz89x_measurement_is_valid,
.cmd = VZ89X_REG_MEASUREMENT,
.read_size = VZ89X_REG_MEASUREMENT_RD_SIZE,
.write_size = VZ89X_REG_MEASUREMENT_WR_SIZE,
.channels = vz89x_channels,
.num_channels = ARRAY_SIZE(vz89x_channels),
},
{
.valid = vz89te_measurement_is_valid,
.cmd = VZ89TE_REG_MEASUREMENT,
.read_size = VZ89TE_REG_MEASUREMENT_RD_SIZE,
.write_size = VZ89TE_REG_MEASUREMENT_WR_SIZE,
.channels = vz89te_channels,
.num_channels = ARRAY_SIZE(vz89te_channels),
},
};
static const struct of_device_id vz89x_dt_ids[] = {
{ .compatible = "sgx,vz89x", .data = (void *) VZ89X },
{ .compatible = "sgx,vz89te", .data = (void *) VZ89TE },
{ }
};
MODULE_DEVICE_TABLE(of, vz89x_dt_ids);
static int vz89x_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct device *dev = &client->dev;
struct iio_dev *indio_dev;
struct vz89x_data *data;
int chip_id;
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
data->xfer = vz89x_i2c_xfer;
else if (i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BYTE))
data->xfer = vz89x_smbus_xfer;
else
return -EOPNOTSUPP;
if (!dev_fwnode(dev))
chip_id = id->driver_data;
else
chip_id = (unsigned long)device_get_match_data(dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->chip = &vz89x_chips[chip_id];
data->last_update = jiffies - HZ;
mutex_init(&data->lock);
indio_dev->info = &vz89x_info;
indio_dev->name = dev_name(dev);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = data->chip->channels;
indio_dev->num_channels = data->chip->num_channels;
return devm_iio_device_register(dev, indio_dev);
}
static const struct i2c_device_id vz89x_id[] = {
{ "vz89x", VZ89X },
{ "vz89te", VZ89TE },
{ }
};
MODULE_DEVICE_TABLE(i2c, vz89x_id);
static struct i2c_driver vz89x_driver = {
.driver = {
.name = "vz89x",
.of_match_table = vz89x_dt_ids,
},
.probe = vz89x_probe,
.id_table = vz89x_id,
};
module_i2c_driver(vz89x_driver);
MODULE_AUTHOR("Matt Ranostay <[email protected]>");
MODULE_DESCRIPTION("SGX Sensortech MiCS VZ89X VOC sensors");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/chemical/vz89x.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Sensirion SCD30 carbon dioxide sensor i2c driver
*
* Copyright (c) 2020 Tomasz Duszynski <[email protected]>
*
* I2C slave address: 0x61
*/
#include <linux/crc8.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/types.h>
#include <asm/unaligned.h>
#include "scd30.h"
#define SCD30_I2C_MAX_BUF_SIZE 18
#define SCD30_I2C_CRC8_POLYNOMIAL 0x31
static u16 scd30_i2c_cmd_lookup_tbl[] = {
[CMD_START_MEAS] = 0x0010,
[CMD_STOP_MEAS] = 0x0104,
[CMD_MEAS_INTERVAL] = 0x4600,
[CMD_MEAS_READY] = 0x0202,
[CMD_READ_MEAS] = 0x0300,
[CMD_ASC] = 0x5306,
[CMD_FRC] = 0x5204,
[CMD_TEMP_OFFSET] = 0x5403,
[CMD_FW_VERSION] = 0xd100,
[CMD_RESET] = 0xd304,
};
DECLARE_CRC8_TABLE(scd30_i2c_crc8_tbl);
static int scd30_i2c_xfer(struct scd30_state *state, char *txbuf, int txsize,
char *rxbuf, int rxsize)
{
struct i2c_client *client = to_i2c_client(state->dev);
int ret;
/*
* repeated start is not supported hence instead of sending two i2c
* messages in a row we send one by one
*/
ret = i2c_master_send(client, txbuf, txsize);
if (ret < 0)
return ret;
if (ret != txsize)
return -EIO;
if (!rxbuf)
return 0;
ret = i2c_master_recv(client, rxbuf, rxsize);
if (ret < 0)
return ret;
if (ret != rxsize)
return -EIO;
return 0;
}
static int scd30_i2c_command(struct scd30_state *state, enum scd30_cmd cmd, u16 arg,
void *response, int size)
{
char buf[SCD30_I2C_MAX_BUF_SIZE];
char *rsp = response;
int i, ret;
char crc;
put_unaligned_be16(scd30_i2c_cmd_lookup_tbl[cmd], buf);
i = 2;
if (rsp) {
/* each two bytes are followed by a crc8 */
size += size / 2;
} else {
put_unaligned_be16(arg, buf + i);
crc = crc8(scd30_i2c_crc8_tbl, buf + i, 2, CRC8_INIT_VALUE);
i += 2;
buf[i] = crc;
i += 1;
/* commands below don't take an argument */
if ((cmd == CMD_STOP_MEAS) || (cmd == CMD_RESET))
i -= 3;
}
ret = scd30_i2c_xfer(state, buf, i, buf, size);
if (ret)
return ret;
/* validate received data and strip off crc bytes */
for (i = 0; i < size; i += 3) {
crc = crc8(scd30_i2c_crc8_tbl, buf + i, 2, CRC8_INIT_VALUE);
if (crc != buf[i + 2]) {
dev_err(state->dev, "data integrity check failed\n");
return -EIO;
}
*rsp++ = buf[i];
*rsp++ = buf[i + 1];
}
return 0;
}
static int scd30_i2c_probe(struct i2c_client *client)
{
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -EOPNOTSUPP;
crc8_populate_msb(scd30_i2c_crc8_tbl, SCD30_I2C_CRC8_POLYNOMIAL);
return scd30_probe(&client->dev, client->irq, client->name, NULL, scd30_i2c_command);
}
static const struct of_device_id scd30_i2c_of_match[] = {
{ .compatible = "sensirion,scd30" },
{ }
};
MODULE_DEVICE_TABLE(of, scd30_i2c_of_match);
static struct i2c_driver scd30_i2c_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = scd30_i2c_of_match,
.pm = pm_sleep_ptr(&scd30_pm_ops),
},
.probe = scd30_i2c_probe,
};
module_i2c_driver(scd30_i2c_driver);
MODULE_AUTHOR("Tomasz Duszynski <[email protected]>");
MODULE_DESCRIPTION("Sensirion SCD30 carbon dioxide sensor i2c driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_SCD30);
| linux-master | drivers/iio/chemical/scd30_i2c.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Sensirion SCD30 carbon dioxide sensor serial driver
*
* Copyright (c) 2020 Tomasz Duszynski <[email protected]>
*/
#include <linux/crc16.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/iio/iio.h>
#include <linux/jiffies.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/serdev.h>
#include <linux/string.h>
#include <linux/types.h>
#include <asm/unaligned.h>
#include "scd30.h"
#define SCD30_SERDEV_ADDR 0x61
#define SCD30_SERDEV_WRITE 0x06
#define SCD30_SERDEV_READ 0x03
#define SCD30_SERDEV_MAX_BUF_SIZE 17
#define SCD30_SERDEV_RX_HEADER_SIZE 3
#define SCD30_SERDEV_CRC_SIZE 2
#define SCD30_SERDEV_TIMEOUT msecs_to_jiffies(200)
struct scd30_serdev_priv {
struct completion meas_ready;
char *buf;
int num_expected;
int num;
};
static u16 scd30_serdev_cmd_lookup_tbl[] = {
[CMD_START_MEAS] = 0x0036,
[CMD_STOP_MEAS] = 0x0037,
[CMD_MEAS_INTERVAL] = 0x0025,
[CMD_MEAS_READY] = 0x0027,
[CMD_READ_MEAS] = 0x0028,
[CMD_ASC] = 0x003a,
[CMD_FRC] = 0x0039,
[CMD_TEMP_OFFSET] = 0x003b,
[CMD_FW_VERSION] = 0x0020,
[CMD_RESET] = 0x0034,
};
static u16 scd30_serdev_calc_crc(const char *buf, int size)
{
return crc16(0xffff, buf, size);
}
static int scd30_serdev_xfer(struct scd30_state *state, char *txbuf, int txsize,
char *rxbuf, int rxsize)
{
struct serdev_device *serdev = to_serdev_device(state->dev);
struct scd30_serdev_priv *priv = state->priv;
int ret;
priv->buf = rxbuf;
priv->num_expected = rxsize;
priv->num = 0;
ret = serdev_device_write(serdev, txbuf, txsize, SCD30_SERDEV_TIMEOUT);
if (ret < 0)
return ret;
if (ret != txsize)
return -EIO;
ret = wait_for_completion_interruptible_timeout(&priv->meas_ready, SCD30_SERDEV_TIMEOUT);
if (ret < 0)
return ret;
if (!ret)
return -ETIMEDOUT;
return 0;
}
static int scd30_serdev_command(struct scd30_state *state, enum scd30_cmd cmd, u16 arg,
void *response, int size)
{
/*
* Communication over serial line is based on modbus protocol (or rather
* its variation called modbus over serial to be precise). Upon
* receiving a request device should reply with response.
*
* Frame below represents a request message. Each field takes
* exactly one byte.
*
* +------+------+-----+-----+-------+-------+-----+-----+
* | dev | op | reg | reg | byte1 | byte0 | crc | crc |
* | addr | code | msb | lsb | | | lsb | msb |
* +------+------+-----+-----+-------+-------+-----+-----+
*
* The message device replies with depends on the 'op code' field from
* the request. In case it was set to SCD30_SERDEV_WRITE sensor should
* reply with unchanged request. Otherwise 'op code' was set to
* SCD30_SERDEV_READ and response looks like the one below. As with
* request, each field takes one byte.
*
* +------+------+--------+-------+-----+-------+-----+-----+
* | dev | op | num of | byte0 | ... | byteN | crc | crc |
* | addr | code | bytes | | | | lsb | msb |
* +------+------+--------+-------+-----+-------+-----+-----+
*/
char txbuf[SCD30_SERDEV_MAX_BUF_SIZE] = { SCD30_SERDEV_ADDR },
rxbuf[SCD30_SERDEV_MAX_BUF_SIZE];
int ret, rxsize, txsize = 2;
char *rsp = response;
u16 crc;
put_unaligned_be16(scd30_serdev_cmd_lookup_tbl[cmd], txbuf + txsize);
txsize += 2;
if (rsp) {
txbuf[1] = SCD30_SERDEV_READ;
if (cmd == CMD_READ_MEAS)
/* number of u16 words to read */
put_unaligned_be16(size / 2, txbuf + txsize);
else
put_unaligned_be16(0x0001, txbuf + txsize);
txsize += 2;
crc = scd30_serdev_calc_crc(txbuf, txsize);
put_unaligned_le16(crc, txbuf + txsize);
txsize += 2;
rxsize = SCD30_SERDEV_RX_HEADER_SIZE + size + SCD30_SERDEV_CRC_SIZE;
} else {
if ((cmd == CMD_STOP_MEAS) || (cmd == CMD_RESET))
arg = 0x0001;
txbuf[1] = SCD30_SERDEV_WRITE;
put_unaligned_be16(arg, txbuf + txsize);
txsize += 2;
crc = scd30_serdev_calc_crc(txbuf, txsize);
put_unaligned_le16(crc, txbuf + txsize);
txsize += 2;
rxsize = txsize;
}
ret = scd30_serdev_xfer(state, txbuf, txsize, rxbuf, rxsize);
if (ret)
return ret;
switch (txbuf[1]) {
case SCD30_SERDEV_WRITE:
if (memcmp(txbuf, rxbuf, txsize)) {
dev_err(state->dev, "wrong message received\n");
return -EIO;
}
break;
case SCD30_SERDEV_READ:
if (rxbuf[2] != (rxsize - SCD30_SERDEV_RX_HEADER_SIZE - SCD30_SERDEV_CRC_SIZE)) {
dev_err(state->dev, "received data size does not match header\n");
return -EIO;
}
rxsize -= SCD30_SERDEV_CRC_SIZE;
crc = get_unaligned_le16(rxbuf + rxsize);
if (crc != scd30_serdev_calc_crc(rxbuf, rxsize)) {
dev_err(state->dev, "data integrity check failed\n");
return -EIO;
}
rxsize -= SCD30_SERDEV_RX_HEADER_SIZE;
memcpy(rsp, rxbuf + SCD30_SERDEV_RX_HEADER_SIZE, rxsize);
break;
default:
dev_err(state->dev, "received unknown op code\n");
return -EIO;
}
return 0;
}
static int scd30_serdev_receive_buf(struct serdev_device *serdev,
const unsigned char *buf, size_t size)
{
struct iio_dev *indio_dev = serdev_device_get_drvdata(serdev);
struct scd30_serdev_priv *priv;
struct scd30_state *state;
int num;
if (!indio_dev)
return 0;
state = iio_priv(indio_dev);
priv = state->priv;
/* just in case sensor puts some unexpected bytes on the bus */
if (!priv->buf)
return 0;
if (priv->num + size >= priv->num_expected)
num = priv->num_expected - priv->num;
else
num = size;
memcpy(priv->buf + priv->num, buf, num);
priv->num += num;
if (priv->num == priv->num_expected) {
priv->buf = NULL;
complete(&priv->meas_ready);
}
return num;
}
static const struct serdev_device_ops scd30_serdev_ops = {
.receive_buf = scd30_serdev_receive_buf,
.write_wakeup = serdev_device_write_wakeup,
};
static int scd30_serdev_probe(struct serdev_device *serdev)
{
struct device *dev = &serdev->dev;
struct scd30_serdev_priv *priv;
int irq, ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
init_completion(&priv->meas_ready);
serdev_device_set_client_ops(serdev, &scd30_serdev_ops);
ret = devm_serdev_device_open(dev, serdev);
if (ret)
return ret;
serdev_device_set_baudrate(serdev, 19200);
serdev_device_set_flow_control(serdev, false);
ret = serdev_device_set_parity(serdev, SERDEV_PARITY_NONE);
if (ret)
return ret;
irq = fwnode_irq_get(dev_fwnode(dev), 0);
return scd30_probe(dev, irq, KBUILD_MODNAME, priv, scd30_serdev_command);
}
static const struct of_device_id scd30_serdev_of_match[] = {
{ .compatible = "sensirion,scd30" },
{ }
};
MODULE_DEVICE_TABLE(of, scd30_serdev_of_match);
static struct serdev_device_driver scd30_serdev_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = scd30_serdev_of_match,
.pm = pm_sleep_ptr(&scd30_pm_ops),
},
.probe = scd30_serdev_probe,
};
module_serdev_device_driver(scd30_serdev_driver);
MODULE_AUTHOR("Tomasz Duszynski <[email protected]>");
MODULE_DESCRIPTION("Sensirion SCD30 carbon dioxide sensor serial driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_SCD30);
| linux-master | drivers/iio/chemical/scd30_serial.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Bosch BME680 - Temperature, Pressure, Humidity & Gas Sensor
*
* Copyright (C) 2017 - 2018 Bosch Sensortec GmbH
* Copyright (C) 2018 Himanshu Jha <[email protected]>
*
* Datasheet:
* https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BME680-DS001-00.pdf
*/
#include <linux/acpi.h>
#include <linux/bitfield.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/log2.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include "bme680.h"
struct bme680_calib {
u16 par_t1;
s16 par_t2;
s8 par_t3;
u16 par_p1;
s16 par_p2;
s8 par_p3;
s16 par_p4;
s16 par_p5;
s8 par_p6;
s8 par_p7;
s16 par_p8;
s16 par_p9;
u8 par_p10;
u16 par_h1;
u16 par_h2;
s8 par_h3;
s8 par_h4;
s8 par_h5;
s8 par_h6;
s8 par_h7;
s8 par_gh1;
s16 par_gh2;
s8 par_gh3;
u8 res_heat_range;
s8 res_heat_val;
s8 range_sw_err;
};
struct bme680_data {
struct regmap *regmap;
struct bme680_calib bme680;
u8 oversampling_temp;
u8 oversampling_press;
u8 oversampling_humid;
u16 heater_dur;
u16 heater_temp;
/*
* Carryover value from temperature conversion, used in pressure
* and humidity compensation calculations.
*/
s32 t_fine;
};
static const struct regmap_range bme680_volatile_ranges[] = {
regmap_reg_range(BME680_REG_MEAS_STAT_0, BME680_REG_GAS_R_LSB),
regmap_reg_range(BME680_REG_STATUS, BME680_REG_STATUS),
regmap_reg_range(BME680_T2_LSB_REG, BME680_GH3_REG),
};
static const struct regmap_access_table bme680_volatile_table = {
.yes_ranges = bme680_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(bme680_volatile_ranges),
};
const struct regmap_config bme680_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xef,
.volatile_table = &bme680_volatile_table,
.cache_type = REGCACHE_RBTREE,
};
EXPORT_SYMBOL_NS(bme680_regmap_config, IIO_BME680);
static const struct iio_chan_spec bme680_channels[] = {
{
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
},
{
.type = IIO_PRESSURE,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
},
{
.type = IIO_HUMIDITYRELATIVE,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
},
{
.type = IIO_RESISTANCE,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
},
};
static int bme680_read_calib(struct bme680_data *data,
struct bme680_calib *calib)
{
struct device *dev = regmap_get_device(data->regmap);
unsigned int tmp, tmp_msb, tmp_lsb;
int ret;
__le16 buf;
/* Temperature related coefficients */
ret = regmap_bulk_read(data->regmap, BME680_T1_LSB_REG,
&buf, sizeof(buf));
if (ret < 0) {
dev_err(dev, "failed to read BME680_T1_LSB_REG\n");
return ret;
}
calib->par_t1 = le16_to_cpu(buf);
ret = regmap_bulk_read(data->regmap, BME680_T2_LSB_REG,
&buf, sizeof(buf));
if (ret < 0) {
dev_err(dev, "failed to read BME680_T2_LSB_REG\n");
return ret;
}
calib->par_t2 = le16_to_cpu(buf);
ret = regmap_read(data->regmap, BME680_T3_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_T3_REG\n");
return ret;
}
calib->par_t3 = tmp;
/* Pressure related coefficients */
ret = regmap_bulk_read(data->regmap, BME680_P1_LSB_REG,
&buf, sizeof(buf));
if (ret < 0) {
dev_err(dev, "failed to read BME680_P1_LSB_REG\n");
return ret;
}
calib->par_p1 = le16_to_cpu(buf);
ret = regmap_bulk_read(data->regmap, BME680_P2_LSB_REG,
&buf, sizeof(buf));
if (ret < 0) {
dev_err(dev, "failed to read BME680_P2_LSB_REG\n");
return ret;
}
calib->par_p2 = le16_to_cpu(buf);
ret = regmap_read(data->regmap, BME680_P3_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_P3_REG\n");
return ret;
}
calib->par_p3 = tmp;
ret = regmap_bulk_read(data->regmap, BME680_P4_LSB_REG,
&buf, sizeof(buf));
if (ret < 0) {
dev_err(dev, "failed to read BME680_P4_LSB_REG\n");
return ret;
}
calib->par_p4 = le16_to_cpu(buf);
ret = regmap_bulk_read(data->regmap, BME680_P5_LSB_REG,
&buf, sizeof(buf));
if (ret < 0) {
dev_err(dev, "failed to read BME680_P5_LSB_REG\n");
return ret;
}
calib->par_p5 = le16_to_cpu(buf);
ret = regmap_read(data->regmap, BME680_P6_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_P6_REG\n");
return ret;
}
calib->par_p6 = tmp;
ret = regmap_read(data->regmap, BME680_P7_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_P7_REG\n");
return ret;
}
calib->par_p7 = tmp;
ret = regmap_bulk_read(data->regmap, BME680_P8_LSB_REG,
&buf, sizeof(buf));
if (ret < 0) {
dev_err(dev, "failed to read BME680_P8_LSB_REG\n");
return ret;
}
calib->par_p8 = le16_to_cpu(buf);
ret = regmap_bulk_read(data->regmap, BME680_P9_LSB_REG,
&buf, sizeof(buf));
if (ret < 0) {
dev_err(dev, "failed to read BME680_P9_LSB_REG\n");
return ret;
}
calib->par_p9 = le16_to_cpu(buf);
ret = regmap_read(data->regmap, BME680_P10_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_P10_REG\n");
return ret;
}
calib->par_p10 = tmp;
/* Humidity related coefficients */
ret = regmap_read(data->regmap, BME680_H1_MSB_REG, &tmp_msb);
if (ret < 0) {
dev_err(dev, "failed to read BME680_H1_MSB_REG\n");
return ret;
}
ret = regmap_read(data->regmap, BME680_H1_LSB_REG, &tmp_lsb);
if (ret < 0) {
dev_err(dev, "failed to read BME680_H1_LSB_REG\n");
return ret;
}
calib->par_h1 = (tmp_msb << BME680_HUM_REG_SHIFT_VAL) |
(tmp_lsb & BME680_BIT_H1_DATA_MASK);
ret = regmap_read(data->regmap, BME680_H2_MSB_REG, &tmp_msb);
if (ret < 0) {
dev_err(dev, "failed to read BME680_H2_MSB_REG\n");
return ret;
}
ret = regmap_read(data->regmap, BME680_H2_LSB_REG, &tmp_lsb);
if (ret < 0) {
dev_err(dev, "failed to read BME680_H2_LSB_REG\n");
return ret;
}
calib->par_h2 = (tmp_msb << BME680_HUM_REG_SHIFT_VAL) |
(tmp_lsb >> BME680_HUM_REG_SHIFT_VAL);
ret = regmap_read(data->regmap, BME680_H3_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_H3_REG\n");
return ret;
}
calib->par_h3 = tmp;
ret = regmap_read(data->regmap, BME680_H4_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_H4_REG\n");
return ret;
}
calib->par_h4 = tmp;
ret = regmap_read(data->regmap, BME680_H5_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_H5_REG\n");
return ret;
}
calib->par_h5 = tmp;
ret = regmap_read(data->regmap, BME680_H6_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_H6_REG\n");
return ret;
}
calib->par_h6 = tmp;
ret = regmap_read(data->regmap, BME680_H7_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_H7_REG\n");
return ret;
}
calib->par_h7 = tmp;
/* Gas heater related coefficients */
ret = regmap_read(data->regmap, BME680_GH1_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_GH1_REG\n");
return ret;
}
calib->par_gh1 = tmp;
ret = regmap_bulk_read(data->regmap, BME680_GH2_LSB_REG,
&buf, sizeof(buf));
if (ret < 0) {
dev_err(dev, "failed to read BME680_GH2_LSB_REG\n");
return ret;
}
calib->par_gh2 = le16_to_cpu(buf);
ret = regmap_read(data->regmap, BME680_GH3_REG, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read BME680_GH3_REG\n");
return ret;
}
calib->par_gh3 = tmp;
/* Other coefficients */
ret = regmap_read(data->regmap, BME680_REG_RES_HEAT_RANGE, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read resistance heat range\n");
return ret;
}
calib->res_heat_range = FIELD_GET(BME680_RHRANGE_MASK, tmp);
ret = regmap_read(data->regmap, BME680_REG_RES_HEAT_VAL, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read resistance heat value\n");
return ret;
}
calib->res_heat_val = tmp;
ret = regmap_read(data->regmap, BME680_REG_RANGE_SW_ERR, &tmp);
if (ret < 0) {
dev_err(dev, "failed to read range software error\n");
return ret;
}
calib->range_sw_err = FIELD_GET(BME680_RSERROR_MASK, tmp);
return 0;
}
/*
* Taken from Bosch BME680 API:
* https://github.com/BoschSensortec/BME680_driver/blob/63bb5336/bme680.c#L876
*
* Returns temperature measurement in DegC, resolutions is 0.01 DegC. Therefore,
* output value of "3233" represents 32.33 DegC.
*/
static s16 bme680_compensate_temp(struct bme680_data *data,
s32 adc_temp)
{
struct bme680_calib *calib = &data->bme680;
s64 var1, var2, var3;
s16 calc_temp;
/* If the calibration is invalid, attempt to reload it */
if (!calib->par_t2)
bme680_read_calib(data, calib);
var1 = (adc_temp >> 3) - (calib->par_t1 << 1);
var2 = (var1 * calib->par_t2) >> 11;
var3 = ((var1 >> 1) * (var1 >> 1)) >> 12;
var3 = (var3 * (calib->par_t3 << 4)) >> 14;
data->t_fine = var2 + var3;
calc_temp = (data->t_fine * 5 + 128) >> 8;
return calc_temp;
}
/*
* Taken from Bosch BME680 API:
* https://github.com/BoschSensortec/BME680_driver/blob/63bb5336/bme680.c#L896
*
* Returns pressure measurement in Pa. Output value of "97356" represents
* 97356 Pa = 973.56 hPa.
*/
static u32 bme680_compensate_press(struct bme680_data *data,
u32 adc_press)
{
struct bme680_calib *calib = &data->bme680;
s32 var1, var2, var3, press_comp;
var1 = (data->t_fine >> 1) - 64000;
var2 = ((((var1 >> 2) * (var1 >> 2)) >> 11) * calib->par_p6) >> 2;
var2 = var2 + (var1 * calib->par_p5 << 1);
var2 = (var2 >> 2) + (calib->par_p4 << 16);
var1 = (((((var1 >> 2) * (var1 >> 2)) >> 13) *
(calib->par_p3 << 5)) >> 3) +
((calib->par_p2 * var1) >> 1);
var1 = var1 >> 18;
var1 = ((32768 + var1) * calib->par_p1) >> 15;
press_comp = 1048576 - adc_press;
press_comp = ((press_comp - (var2 >> 12)) * 3125);
if (press_comp >= BME680_MAX_OVERFLOW_VAL)
press_comp = ((press_comp / (u32)var1) << 1);
else
press_comp = ((press_comp << 1) / (u32)var1);
var1 = (calib->par_p9 * (((press_comp >> 3) *
(press_comp >> 3)) >> 13)) >> 12;
var2 = ((press_comp >> 2) * calib->par_p8) >> 13;
var3 = ((press_comp >> 8) * (press_comp >> 8) *
(press_comp >> 8) * calib->par_p10) >> 17;
press_comp += (var1 + var2 + var3 + (calib->par_p7 << 7)) >> 4;
return press_comp;
}
/*
* Taken from Bosch BME680 API:
* https://github.com/BoschSensortec/BME680_driver/blob/63bb5336/bme680.c#L937
*
* Returns humidity measurement in percent, resolution is 0.001 percent. Output
* value of "43215" represents 43.215 %rH.
*/
static u32 bme680_compensate_humid(struct bme680_data *data,
u16 adc_humid)
{
struct bme680_calib *calib = &data->bme680;
s32 var1, var2, var3, var4, var5, var6, temp_scaled, calc_hum;
temp_scaled = (data->t_fine * 5 + 128) >> 8;
var1 = (adc_humid - ((s32) ((s32) calib->par_h1 * 16))) -
(((temp_scaled * (s32) calib->par_h3) / 100) >> 1);
var2 = ((s32) calib->par_h2 *
(((temp_scaled * calib->par_h4) / 100) +
(((temp_scaled * ((temp_scaled * calib->par_h5) / 100))
>> 6) / 100) + (1 << 14))) >> 10;
var3 = var1 * var2;
var4 = calib->par_h6 << 7;
var4 = (var4 + ((temp_scaled * calib->par_h7) / 100)) >> 4;
var5 = ((var3 >> 14) * (var3 >> 14)) >> 10;
var6 = (var4 * var5) >> 1;
calc_hum = (((var3 + var6) >> 10) * 1000) >> 12;
calc_hum = clamp(calc_hum, 0, 100000); /* clamp between 0-100 %rH */
return calc_hum;
}
/*
* Taken from Bosch BME680 API:
* https://github.com/BoschSensortec/BME680_driver/blob/63bb5336/bme680.c#L973
*
* Returns gas measurement in Ohm. Output value of "82986" represent 82986 ohms.
*/
static u32 bme680_compensate_gas(struct bme680_data *data, u16 gas_res_adc,
u8 gas_range)
{
struct bme680_calib *calib = &data->bme680;
s64 var1;
u64 var2;
s64 var3;
u32 calc_gas_res;
/* Look up table for the possible gas range values */
const u32 lookupTable[16] = {2147483647u, 2147483647u,
2147483647u, 2147483647u, 2147483647u,
2126008810u, 2147483647u, 2130303777u,
2147483647u, 2147483647u, 2143188679u,
2136746228u, 2147483647u, 2126008810u,
2147483647u, 2147483647u};
var1 = ((1340 + (5 * (s64) calib->range_sw_err)) *
((s64) lookupTable[gas_range])) >> 16;
var2 = ((gas_res_adc << 15) - 16777216) + var1;
var3 = ((125000 << (15 - gas_range)) * var1) >> 9;
var3 += (var2 >> 1);
calc_gas_res = div64_s64(var3, (s64) var2);
return calc_gas_res;
}
/*
* Taken from Bosch BME680 API:
* https://github.com/BoschSensortec/BME680_driver/blob/63bb5336/bme680.c#L1002
*/
static u8 bme680_calc_heater_res(struct bme680_data *data, u16 temp)
{
struct bme680_calib *calib = &data->bme680;
s32 var1, var2, var3, var4, var5, heatr_res_x100;
u8 heatr_res;
if (temp > 400) /* Cap temperature */
temp = 400;
var1 = (((s32) BME680_AMB_TEMP * calib->par_gh3) / 1000) * 256;
var2 = (calib->par_gh1 + 784) * (((((calib->par_gh2 + 154009) *
temp * 5) / 100)
+ 3276800) / 10);
var3 = var1 + (var2 / 2);
var4 = (var3 / (calib->res_heat_range + 4));
var5 = 131 * calib->res_heat_val + 65536;
heatr_res_x100 = ((var4 / var5) - 250) * 34;
heatr_res = DIV_ROUND_CLOSEST(heatr_res_x100, 100);
return heatr_res;
}
/*
* Taken from Bosch BME680 API:
* https://github.com/BoschSensortec/BME680_driver/blob/63bb5336/bme680.c#L1188
*/
static u8 bme680_calc_heater_dur(u16 dur)
{
u8 durval, factor = 0;
if (dur >= 0xfc0) {
durval = 0xff; /* Max duration */
} else {
while (dur > 0x3F) {
dur = dur / 4;
factor += 1;
}
durval = dur + (factor * 64);
}
return durval;
}
static int bme680_set_mode(struct bme680_data *data, bool mode)
{
struct device *dev = regmap_get_device(data->regmap);
int ret;
if (mode) {
ret = regmap_write_bits(data->regmap, BME680_REG_CTRL_MEAS,
BME680_MODE_MASK, BME680_MODE_FORCED);
if (ret < 0)
dev_err(dev, "failed to set forced mode\n");
} else {
ret = regmap_write_bits(data->regmap, BME680_REG_CTRL_MEAS,
BME680_MODE_MASK, BME680_MODE_SLEEP);
if (ret < 0)
dev_err(dev, "failed to set sleep mode\n");
}
return ret;
}
static u8 bme680_oversampling_to_reg(u8 val)
{
return ilog2(val) + 1;
}
static int bme680_chip_config(struct bme680_data *data)
{
struct device *dev = regmap_get_device(data->regmap);
int ret;
u8 osrs;
osrs = FIELD_PREP(
BME680_OSRS_HUMIDITY_MASK,
bme680_oversampling_to_reg(data->oversampling_humid));
/*
* Highly recommended to set oversampling of humidity before
* temperature/pressure oversampling.
*/
ret = regmap_update_bits(data->regmap, BME680_REG_CTRL_HUMIDITY,
BME680_OSRS_HUMIDITY_MASK, osrs);
if (ret < 0) {
dev_err(dev, "failed to write ctrl_hum register\n");
return ret;
}
/* IIR filter settings */
ret = regmap_update_bits(data->regmap, BME680_REG_CONFIG,
BME680_FILTER_MASK,
BME680_FILTER_COEFF_VAL);
if (ret < 0) {
dev_err(dev, "failed to write config register\n");
return ret;
}
osrs = FIELD_PREP(BME680_OSRS_TEMP_MASK,
bme680_oversampling_to_reg(data->oversampling_temp)) |
FIELD_PREP(BME680_OSRS_PRESS_MASK,
bme680_oversampling_to_reg(data->oversampling_press));
ret = regmap_write_bits(data->regmap, BME680_REG_CTRL_MEAS,
BME680_OSRS_TEMP_MASK | BME680_OSRS_PRESS_MASK,
osrs);
if (ret < 0)
dev_err(dev, "failed to write ctrl_meas register\n");
return ret;
}
static int bme680_gas_config(struct bme680_data *data)
{
struct device *dev = regmap_get_device(data->regmap);
int ret;
u8 heatr_res, heatr_dur;
heatr_res = bme680_calc_heater_res(data, data->heater_temp);
/* set target heater temperature */
ret = regmap_write(data->regmap, BME680_REG_RES_HEAT_0, heatr_res);
if (ret < 0) {
dev_err(dev, "failed to write res_heat_0 register\n");
return ret;
}
heatr_dur = bme680_calc_heater_dur(data->heater_dur);
/* set target heating duration */
ret = regmap_write(data->regmap, BME680_REG_GAS_WAIT_0, heatr_dur);
if (ret < 0) {
dev_err(dev, "failed to write gas_wait_0 register\n");
return ret;
}
/* Enable the gas sensor and select heater profile set-point 0 */
ret = regmap_update_bits(data->regmap, BME680_REG_CTRL_GAS_1,
BME680_RUN_GAS_MASK | BME680_NB_CONV_MASK,
FIELD_PREP(BME680_RUN_GAS_MASK, 1) |
FIELD_PREP(BME680_NB_CONV_MASK, 0));
if (ret < 0)
dev_err(dev, "failed to write ctrl_gas_1 register\n");
return ret;
}
static int bme680_read_temp(struct bme680_data *data, int *val)
{
struct device *dev = regmap_get_device(data->regmap);
int ret;
__be32 tmp = 0;
s32 adc_temp;
s16 comp_temp;
/* set forced mode to trigger measurement */
ret = bme680_set_mode(data, true);
if (ret < 0)
return ret;
ret = regmap_bulk_read(data->regmap, BME680_REG_TEMP_MSB,
&tmp, 3);
if (ret < 0) {
dev_err(dev, "failed to read temperature\n");
return ret;
}
adc_temp = be32_to_cpu(tmp) >> 12;
if (adc_temp == BME680_MEAS_SKIPPED) {
/* reading was skipped */
dev_err(dev, "reading temperature skipped\n");
return -EINVAL;
}
comp_temp = bme680_compensate_temp(data, adc_temp);
/*
* val might be NULL if we're called by the read_press/read_humid
* routine which is called to get t_fine value used in
* compensate_press/compensate_humid to get compensated
* pressure/humidity readings.
*/
if (val) {
*val = comp_temp * 10; /* Centidegrees to millidegrees */
return IIO_VAL_INT;
}
return ret;
}
static int bme680_read_press(struct bme680_data *data,
int *val, int *val2)
{
struct device *dev = regmap_get_device(data->regmap);
int ret;
__be32 tmp = 0;
s32 adc_press;
/* Read and compensate temperature to get a reading of t_fine */
ret = bme680_read_temp(data, NULL);
if (ret < 0)
return ret;
ret = regmap_bulk_read(data->regmap, BME680_REG_PRESS_MSB,
&tmp, 3);
if (ret < 0) {
dev_err(dev, "failed to read pressure\n");
return ret;
}
adc_press = be32_to_cpu(tmp) >> 12;
if (adc_press == BME680_MEAS_SKIPPED) {
/* reading was skipped */
dev_err(dev, "reading pressure skipped\n");
return -EINVAL;
}
*val = bme680_compensate_press(data, adc_press);
*val2 = 100;
return IIO_VAL_FRACTIONAL;
}
static int bme680_read_humid(struct bme680_data *data,
int *val, int *val2)
{
struct device *dev = regmap_get_device(data->regmap);
int ret;
__be16 tmp = 0;
s32 adc_humidity;
u32 comp_humidity;
/* Read and compensate temperature to get a reading of t_fine */
ret = bme680_read_temp(data, NULL);
if (ret < 0)
return ret;
ret = regmap_bulk_read(data->regmap, BM6880_REG_HUMIDITY_MSB,
&tmp, sizeof(tmp));
if (ret < 0) {
dev_err(dev, "failed to read humidity\n");
return ret;
}
adc_humidity = be16_to_cpu(tmp);
if (adc_humidity == BME680_MEAS_SKIPPED) {
/* reading was skipped */
dev_err(dev, "reading humidity skipped\n");
return -EINVAL;
}
comp_humidity = bme680_compensate_humid(data, adc_humidity);
*val = comp_humidity;
*val2 = 1000;
return IIO_VAL_FRACTIONAL;
}
static int bme680_read_gas(struct bme680_data *data,
int *val)
{
struct device *dev = regmap_get_device(data->regmap);
int ret;
__be16 tmp = 0;
unsigned int check;
u16 adc_gas_res;
u8 gas_range;
/* Set heater settings */
ret = bme680_gas_config(data);
if (ret < 0) {
dev_err(dev, "failed to set gas config\n");
return ret;
}
/* set forced mode to trigger measurement */
ret = bme680_set_mode(data, true);
if (ret < 0)
return ret;
ret = regmap_read(data->regmap, BME680_REG_MEAS_STAT_0, &check);
if (check & BME680_GAS_MEAS_BIT) {
dev_err(dev, "gas measurement incomplete\n");
return -EBUSY;
}
ret = regmap_read(data->regmap, BME680_REG_GAS_R_LSB, &check);
if (ret < 0) {
dev_err(dev, "failed to read gas_r_lsb register\n");
return ret;
}
/*
* occurs if either the gas heating duration was insuffient
* to reach the target heater temperature or the target
* heater temperature was too high for the heater sink to
* reach.
*/
if ((check & BME680_GAS_STAB_BIT) == 0) {
dev_err(dev, "heater failed to reach the target temperature\n");
return -EINVAL;
}
ret = regmap_bulk_read(data->regmap, BME680_REG_GAS_MSB,
&tmp, sizeof(tmp));
if (ret < 0) {
dev_err(dev, "failed to read gas resistance\n");
return ret;
}
gas_range = check & BME680_GAS_RANGE_MASK;
adc_gas_res = be16_to_cpu(tmp) >> BME680_ADC_GAS_RES_SHIFT;
*val = bme680_compensate_gas(data, adc_gas_res, gas_range);
return IIO_VAL_INT;
}
static int bme680_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct bme680_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_TEMP:
return bme680_read_temp(data, val);
case IIO_PRESSURE:
return bme680_read_press(data, val, val2);
case IIO_HUMIDITYRELATIVE:
return bme680_read_humid(data, val, val2);
case IIO_RESISTANCE:
return bme680_read_gas(data, val);
default:
return -EINVAL;
}
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
switch (chan->type) {
case IIO_TEMP:
*val = data->oversampling_temp;
return IIO_VAL_INT;
case IIO_PRESSURE:
*val = data->oversampling_press;
return IIO_VAL_INT;
case IIO_HUMIDITYRELATIVE:
*val = data->oversampling_humid;
return IIO_VAL_INT;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static bool bme680_is_valid_oversampling(int rate)
{
return (rate > 0 && rate <= 16 && is_power_of_2(rate));
}
static int bme680_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct bme680_data *data = iio_priv(indio_dev);
if (val2 != 0)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
{
if (!bme680_is_valid_oversampling(val))
return -EINVAL;
switch (chan->type) {
case IIO_TEMP:
data->oversampling_temp = val;
break;
case IIO_PRESSURE:
data->oversampling_press = val;
break;
case IIO_HUMIDITYRELATIVE:
data->oversampling_humid = val;
break;
default:
return -EINVAL;
}
return bme680_chip_config(data);
}
default:
return -EINVAL;
}
}
static const char bme680_oversampling_ratio_show[] = "1 2 4 8 16";
static IIO_CONST_ATTR(oversampling_ratio_available,
bme680_oversampling_ratio_show);
static struct attribute *bme680_attributes[] = {
&iio_const_attr_oversampling_ratio_available.dev_attr.attr,
NULL,
};
static const struct attribute_group bme680_attribute_group = {
.attrs = bme680_attributes,
};
static const struct iio_info bme680_info = {
.read_raw = &bme680_read_raw,
.write_raw = &bme680_write_raw,
.attrs = &bme680_attribute_group,
};
static const char *bme680_match_acpi_device(struct device *dev)
{
const struct acpi_device_id *id;
id = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!id)
return NULL;
return dev_name(dev);
}
int bme680_core_probe(struct device *dev, struct regmap *regmap,
const char *name)
{
struct iio_dev *indio_dev;
struct bme680_data *data;
unsigned int val;
int ret;
ret = regmap_write(regmap, BME680_REG_SOFT_RESET,
BME680_CMD_SOFTRESET);
if (ret < 0) {
dev_err(dev, "Failed to reset chip\n");
return ret;
}
ret = regmap_read(regmap, BME680_REG_CHIP_ID, &val);
if (ret < 0) {
dev_err(dev, "Error reading chip ID\n");
return ret;
}
if (val != BME680_CHIP_ID_VAL) {
dev_err(dev, "Wrong chip ID, got %x expected %x\n",
val, BME680_CHIP_ID_VAL);
return -ENODEV;
}
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
if (!name && ACPI_HANDLE(dev))
name = bme680_match_acpi_device(dev);
data = iio_priv(indio_dev);
dev_set_drvdata(dev, indio_dev);
data->regmap = regmap;
indio_dev->name = name;
indio_dev->channels = bme680_channels;
indio_dev->num_channels = ARRAY_SIZE(bme680_channels);
indio_dev->info = &bme680_info;
indio_dev->modes = INDIO_DIRECT_MODE;
/* default values for the sensor */
data->oversampling_humid = 2; /* 2X oversampling rate */
data->oversampling_press = 4; /* 4X oversampling rate */
data->oversampling_temp = 8; /* 8X oversampling rate */
data->heater_temp = 320; /* degree Celsius */
data->heater_dur = 150; /* milliseconds */
ret = bme680_chip_config(data);
if (ret < 0) {
dev_err(dev, "failed to set chip_config data\n");
return ret;
}
ret = bme680_gas_config(data);
if (ret < 0) {
dev_err(dev, "failed to set gas config data\n");
return ret;
}
ret = bme680_read_calib(data, &data->bme680);
if (ret < 0) {
dev_err(dev,
"failed to read calibration coefficients at probe\n");
return ret;
}
return devm_iio_device_register(dev, indio_dev);
}
EXPORT_SYMBOL_NS_GPL(bme680_core_probe, IIO_BME680);
MODULE_AUTHOR("Himanshu Jha <[email protected]>");
MODULE_DESCRIPTION("Bosch BME680 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/chemical/bme680_core.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Sensirion SCD30 carbon dioxide sensor core driver
*
* Copyright (c) 2020 Tomasz Duszynski <[email protected]>
*/
#include <linux/bits.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/types.h>
#include <linux/interrupt.h>
#include <linux/irqreturn.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/regulator/consumer.h>
#include <linux/string.h>
#include <linux/sysfs.h>
#include <linux/types.h>
#include <asm/byteorder.h>
#include "scd30.h"
#define SCD30_PRESSURE_COMP_MIN_MBAR 700
#define SCD30_PRESSURE_COMP_MAX_MBAR 1400
#define SCD30_PRESSURE_COMP_DEFAULT 1013
#define SCD30_MEAS_INTERVAL_MIN_S 2
#define SCD30_MEAS_INTERVAL_MAX_S 1800
#define SCD30_MEAS_INTERVAL_DEFAULT SCD30_MEAS_INTERVAL_MIN_S
#define SCD30_FRC_MIN_PPM 400
#define SCD30_FRC_MAX_PPM 2000
#define SCD30_TEMP_OFFSET_MAX 655360
#define SCD30_EXTRA_TIMEOUT_PER_S 250
enum {
SCD30_CONC,
SCD30_TEMP,
SCD30_HR,
};
static int scd30_command_write(struct scd30_state *state, enum scd30_cmd cmd, u16 arg)
{
return state->command(state, cmd, arg, NULL, 0);
}
static int scd30_command_read(struct scd30_state *state, enum scd30_cmd cmd, u16 *val)
{
__be16 tmp;
int ret;
ret = state->command(state, cmd, 0, &tmp, sizeof(tmp));
*val = be16_to_cpup(&tmp);
return ret;
}
static int scd30_reset(struct scd30_state *state)
{
int ret;
u16 val;
ret = scd30_command_write(state, CMD_RESET, 0);
if (ret)
return ret;
/* sensor boots up within 2 secs */
msleep(2000);
/*
* Power-on-reset causes sensor to produce some glitch on i2c bus and
* some controllers end up in error state. Try to recover by placing
* any data on the bus.
*/
scd30_command_read(state, CMD_MEAS_READY, &val);
return 0;
}
/* simplified float to fixed point conversion with a scaling factor of 0.01 */
static int scd30_float_to_fp(int float32)
{
int fraction, shift,
mantissa = float32 & GENMASK(22, 0),
sign = (float32 & BIT(31)) ? -1 : 1,
exp = (float32 & ~BIT(31)) >> 23;
/* special case 0 */
if (!exp && !mantissa)
return 0;
exp -= 127;
if (exp < 0) {
exp = -exp;
/* return values ranging from 1 to 99 */
return sign * ((((BIT(23) + mantissa) * 100) >> 23) >> exp);
}
/* return values starting at 100 */
shift = 23 - exp;
float32 = BIT(exp) + (mantissa >> shift);
fraction = mantissa & GENMASK(shift - 1, 0);
return sign * (float32 * 100 + ((fraction * 100) >> shift));
}
static int scd30_read_meas(struct scd30_state *state)
{
int i, ret;
ret = state->command(state, CMD_READ_MEAS, 0, state->meas, sizeof(state->meas));
if (ret)
return ret;
be32_to_cpu_array(state->meas, (__be32 *)state->meas, ARRAY_SIZE(state->meas));
for (i = 0; i < ARRAY_SIZE(state->meas); i++)
state->meas[i] = scd30_float_to_fp(state->meas[i]);
/*
* co2 is left unprocessed while temperature and humidity are scaled
* to milli deg C and milli percent respectively.
*/
state->meas[SCD30_TEMP] *= 10;
state->meas[SCD30_HR] *= 10;
return 0;
}
static int scd30_wait_meas_irq(struct scd30_state *state)
{
int ret, timeout;
reinit_completion(&state->meas_ready);
enable_irq(state->irq);
timeout = msecs_to_jiffies(state->meas_interval * (1000 + SCD30_EXTRA_TIMEOUT_PER_S));
ret = wait_for_completion_interruptible_timeout(&state->meas_ready, timeout);
if (ret > 0)
ret = 0;
else if (!ret)
ret = -ETIMEDOUT;
disable_irq(state->irq);
return ret;
}
static int scd30_wait_meas_poll(struct scd30_state *state)
{
int timeout = state->meas_interval * SCD30_EXTRA_TIMEOUT_PER_S, tries = 5;
do {
int ret;
u16 val;
ret = scd30_command_read(state, CMD_MEAS_READY, &val);
if (ret)
return -EIO;
/* new measurement available */
if (val)
break;
msleep_interruptible(timeout);
} while (--tries);
return tries ? 0 : -ETIMEDOUT;
}
static int scd30_read_poll(struct scd30_state *state)
{
int ret;
ret = scd30_wait_meas_poll(state);
if (ret)
return ret;
return scd30_read_meas(state);
}
static int scd30_read(struct scd30_state *state)
{
if (state->irq > 0)
return scd30_wait_meas_irq(state);
return scd30_read_poll(state);
}
static int scd30_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct scd30_state *state = iio_priv(indio_dev);
int ret = -EINVAL;
u16 tmp;
mutex_lock(&state->lock);
switch (mask) {
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_PROCESSED:
if (chan->output) {
*val = state->pressure_comp;
ret = IIO_VAL_INT;
break;
}
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
break;
ret = scd30_read(state);
if (ret) {
iio_device_release_direct_mode(indio_dev);
break;
}
*val = state->meas[chan->address];
iio_device_release_direct_mode(indio_dev);
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SCALE:
*val = 0;
*val2 = 1;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
case IIO_CHAN_INFO_SAMP_FREQ:
ret = scd30_command_read(state, CMD_MEAS_INTERVAL, &tmp);
if (ret)
break;
*val = 0;
*val2 = 1000000000 / tmp;
ret = IIO_VAL_INT_PLUS_NANO;
break;
case IIO_CHAN_INFO_CALIBBIAS:
ret = scd30_command_read(state, CMD_TEMP_OFFSET, &tmp);
if (ret)
break;
*val = tmp;
ret = IIO_VAL_INT;
break;
}
mutex_unlock(&state->lock);
return ret;
}
static int scd30_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct scd30_state *state = iio_priv(indio_dev);
int ret = -EINVAL;
mutex_lock(&state->lock);
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
if (val)
break;
val = 1000000000 / val2;
if (val < SCD30_MEAS_INTERVAL_MIN_S || val > SCD30_MEAS_INTERVAL_MAX_S)
break;
ret = scd30_command_write(state, CMD_MEAS_INTERVAL, val);
if (ret)
break;
state->meas_interval = val;
break;
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_PRESSURE:
if (val < SCD30_PRESSURE_COMP_MIN_MBAR ||
val > SCD30_PRESSURE_COMP_MAX_MBAR)
break;
ret = scd30_command_write(state, CMD_START_MEAS, val);
if (ret)
break;
state->pressure_comp = val;
break;
default:
break;
}
break;
case IIO_CHAN_INFO_CALIBBIAS:
if (val < 0 || val > SCD30_TEMP_OFFSET_MAX)
break;
/*
* Manufacturer does not explicitly specify min/max sensible
* values hence check is omitted for simplicity.
*/
ret = scd30_command_write(state, CMD_TEMP_OFFSET / 10, val);
}
mutex_unlock(&state->lock);
return ret;
}
static int scd30_write_raw_get_fmt(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
return IIO_VAL_INT_PLUS_NANO;
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_CALIBBIAS:
return IIO_VAL_INT;
}
return -EINVAL;
}
static const int scd30_pressure_raw_available[] = {
SCD30_PRESSURE_COMP_MIN_MBAR, 1, SCD30_PRESSURE_COMP_MAX_MBAR,
};
static const int scd30_temp_calibbias_available[] = {
0, 10, SCD30_TEMP_OFFSET_MAX,
};
static int scd30_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
const int **vals, int *type, int *length, long mask)
{
switch (mask) {
case IIO_CHAN_INFO_RAW:
*vals = scd30_pressure_raw_available;
*type = IIO_VAL_INT;
return IIO_AVAIL_RANGE;
case IIO_CHAN_INFO_CALIBBIAS:
*vals = scd30_temp_calibbias_available;
*type = IIO_VAL_INT;
return IIO_AVAIL_RANGE;
}
return -EINVAL;
}
static ssize_t sampling_frequency_available_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int i = SCD30_MEAS_INTERVAL_MIN_S;
ssize_t len = 0;
do {
len += sysfs_emit_at(buf, len, "0.%09u ", 1000000000 / i);
/*
* Not all values fit PAGE_SIZE buffer hence print every 6th
* (each frequency differs by 6s in time domain from the
* adjacent). Unlisted but valid ones are still accepted.
*/
i += 6;
} while (i <= SCD30_MEAS_INTERVAL_MAX_S);
buf[len - 1] = '\n';
return len;
}
static ssize_t calibration_auto_enable_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct scd30_state *state = iio_priv(indio_dev);
int ret;
u16 val;
mutex_lock(&state->lock);
ret = scd30_command_read(state, CMD_ASC, &val);
mutex_unlock(&state->lock);
return ret ?: sysfs_emit(buf, "%d\n", val);
}
static ssize_t calibration_auto_enable_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct scd30_state *state = iio_priv(indio_dev);
bool val;
int ret;
ret = kstrtobool(buf, &val);
if (ret)
return ret;
mutex_lock(&state->lock);
ret = scd30_command_write(state, CMD_ASC, val);
mutex_unlock(&state->lock);
return ret ?: len;
}
static ssize_t calibration_forced_value_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct scd30_state *state = iio_priv(indio_dev);
int ret;
u16 val;
mutex_lock(&state->lock);
ret = scd30_command_read(state, CMD_FRC, &val);
mutex_unlock(&state->lock);
return ret ?: sysfs_emit(buf, "%d\n", val);
}
static ssize_t calibration_forced_value_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct scd30_state *state = iio_priv(indio_dev);
int ret;
u16 val;
ret = kstrtou16(buf, 0, &val);
if (ret)
return ret;
if (val < SCD30_FRC_MIN_PPM || val > SCD30_FRC_MAX_PPM)
return -EINVAL;
mutex_lock(&state->lock);
ret = scd30_command_write(state, CMD_FRC, val);
mutex_unlock(&state->lock);
return ret ?: len;
}
static IIO_DEVICE_ATTR_RO(sampling_frequency_available, 0);
static IIO_DEVICE_ATTR_RW(calibration_auto_enable, 0);
static IIO_DEVICE_ATTR_RW(calibration_forced_value, 0);
static struct attribute *scd30_attrs[] = {
&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
&iio_dev_attr_calibration_auto_enable.dev_attr.attr,
&iio_dev_attr_calibration_forced_value.dev_attr.attr,
NULL
};
static const struct attribute_group scd30_attr_group = {
.attrs = scd30_attrs,
};
static const struct iio_info scd30_info = {
.attrs = &scd30_attr_group,
.read_raw = scd30_read_raw,
.write_raw = scd30_write_raw,
.write_raw_get_fmt = scd30_write_raw_get_fmt,
.read_avail = scd30_read_avail,
};
#define SCD30_CHAN_SCAN_TYPE(_sign, _realbits) .scan_type = { \
.sign = _sign, \
.realbits = _realbits, \
.storagebits = 32, \
.endianness = IIO_CPU, \
}
static const struct iio_chan_spec scd30_channels[] = {
{
/*
* this channel is special in a sense we are pretending that
* sensor is able to change measurement chamber pressure but in
* fact we're just setting pressure compensation value
*/
.type = IIO_PRESSURE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW),
.output = 1,
.scan_index = -1,
},
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_CO2,
.address = SCD30_CONC,
.scan_index = SCD30_CONC,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.modified = 1,
SCD30_CHAN_SCAN_TYPE('u', 20),
},
{
.type = IIO_TEMP,
.address = SCD30_TEMP,
.scan_index = SCD30_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_CALIBBIAS),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
SCD30_CHAN_SCAN_TYPE('s', 18),
},
{
.type = IIO_HUMIDITYRELATIVE,
.address = SCD30_HR,
.scan_index = SCD30_HR,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
SCD30_CHAN_SCAN_TYPE('u', 17),
},
IIO_CHAN_SOFT_TIMESTAMP(3),
};
static int scd30_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct scd30_state *state = iio_priv(indio_dev);
int ret;
ret = scd30_command_write(state, CMD_STOP_MEAS, 0);
if (ret)
return ret;
return regulator_disable(state->vdd);
}
static int scd30_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct scd30_state *state = iio_priv(indio_dev);
int ret;
ret = regulator_enable(state->vdd);
if (ret)
return ret;
return scd30_command_write(state, CMD_START_MEAS, state->pressure_comp);
}
EXPORT_NS_SIMPLE_DEV_PM_OPS(scd30_pm_ops, scd30_suspend, scd30_resume, IIO_SCD30);
static void scd30_stop_meas(void *data)
{
struct scd30_state *state = data;
scd30_command_write(state, CMD_STOP_MEAS, 0);
}
static void scd30_disable_regulator(void *data)
{
struct scd30_state *state = data;
regulator_disable(state->vdd);
}
static irqreturn_t scd30_irq_handler(int irq, void *priv)
{
struct iio_dev *indio_dev = priv;
if (iio_buffer_enabled(indio_dev)) {
iio_trigger_poll(indio_dev->trig);
return IRQ_HANDLED;
}
return IRQ_WAKE_THREAD;
}
static irqreturn_t scd30_irq_thread_handler(int irq, void *priv)
{
struct iio_dev *indio_dev = priv;
struct scd30_state *state = iio_priv(indio_dev);
int ret;
ret = scd30_read_meas(state);
if (ret)
goto out;
complete_all(&state->meas_ready);
out:
return IRQ_HANDLED;
}
static irqreturn_t scd30_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct scd30_state *state = iio_priv(indio_dev);
struct {
int data[SCD30_MEAS_COUNT];
s64 ts __aligned(8);
} scan;
int ret;
mutex_lock(&state->lock);
if (!iio_trigger_using_own(indio_dev))
ret = scd30_read_poll(state);
else
ret = scd30_read_meas(state);
memset(&scan, 0, sizeof(scan));
memcpy(scan.data, state->meas, sizeof(state->meas));
mutex_unlock(&state->lock);
if (ret)
goto out;
iio_push_to_buffers_with_timestamp(indio_dev, &scan, iio_get_time_ns(indio_dev));
out:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int scd30_set_trigger_state(struct iio_trigger *trig, bool state)
{
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
struct scd30_state *st = iio_priv(indio_dev);
if (state)
enable_irq(st->irq);
else
disable_irq(st->irq);
return 0;
}
static const struct iio_trigger_ops scd30_trigger_ops = {
.set_trigger_state = scd30_set_trigger_state,
.validate_device = iio_trigger_validate_own_device,
};
static int scd30_setup_trigger(struct iio_dev *indio_dev)
{
struct scd30_state *state = iio_priv(indio_dev);
struct device *dev = indio_dev->dev.parent;
struct iio_trigger *trig;
int ret;
trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,
iio_device_id(indio_dev));
if (!trig)
return dev_err_probe(dev, -ENOMEM, "failed to allocate trigger\n");
trig->ops = &scd30_trigger_ops;
iio_trigger_set_drvdata(trig, indio_dev);
ret = devm_iio_trigger_register(dev, trig);
if (ret)
return ret;
indio_dev->trig = iio_trigger_get(trig);
/*
* Interrupt is enabled just before taking a fresh measurement
* and disabled afterwards. This means we need to ensure it is not
* enabled here to keep calls to enable/disable balanced.
*/
ret = devm_request_threaded_irq(dev, state->irq, scd30_irq_handler,
scd30_irq_thread_handler,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT |
IRQF_NO_AUTOEN,
indio_dev->name, indio_dev);
if (ret)
return dev_err_probe(dev, ret, "failed to request irq\n");
return 0;
}
int scd30_probe(struct device *dev, int irq, const char *name, void *priv,
scd30_command_t command)
{
static const unsigned long scd30_scan_masks[] = { 0x07, 0x00 };
struct scd30_state *state;
struct iio_dev *indio_dev;
int ret;
u16 val;
indio_dev = devm_iio_device_alloc(dev, sizeof(*state));
if (!indio_dev)
return -ENOMEM;
state = iio_priv(indio_dev);
state->dev = dev;
state->priv = priv;
state->irq = irq;
state->pressure_comp = SCD30_PRESSURE_COMP_DEFAULT;
state->meas_interval = SCD30_MEAS_INTERVAL_DEFAULT;
state->command = command;
mutex_init(&state->lock);
init_completion(&state->meas_ready);
dev_set_drvdata(dev, indio_dev);
indio_dev->info = &scd30_info;
indio_dev->name = name;
indio_dev->channels = scd30_channels;
indio_dev->num_channels = ARRAY_SIZE(scd30_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->available_scan_masks = scd30_scan_masks;
state->vdd = devm_regulator_get(dev, "vdd");
if (IS_ERR(state->vdd))
return dev_err_probe(dev, PTR_ERR(state->vdd), "failed to get regulator\n");
ret = regulator_enable(state->vdd);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, scd30_disable_regulator, state);
if (ret)
return ret;
ret = scd30_reset(state);
if (ret)
return dev_err_probe(dev, ret, "failed to reset device\n");
if (state->irq > 0) {
ret = scd30_setup_trigger(indio_dev);
if (ret)
return dev_err_probe(dev, ret, "failed to setup trigger\n");
}
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, scd30_trigger_handler, NULL);
if (ret)
return ret;
ret = scd30_command_read(state, CMD_FW_VERSION, &val);
if (ret)
return dev_err_probe(dev, ret, "failed to read firmware version\n");
dev_info(dev, "firmware version: %d.%d\n", val >> 8, (char)val);
ret = scd30_command_write(state, CMD_MEAS_INTERVAL, state->meas_interval);
if (ret)
return dev_err_probe(dev, ret, "failed to set measurement interval\n");
ret = scd30_command_write(state, CMD_START_MEAS, state->pressure_comp);
if (ret)
return dev_err_probe(dev, ret, "failed to start measurement\n");
ret = devm_add_action_or_reset(dev, scd30_stop_meas, state);
if (ret)
return ret;
return devm_iio_device_register(dev, indio_dev);
}
EXPORT_SYMBOL_NS(scd30_probe, IIO_SCD30);
MODULE_AUTHOR("Tomasz Duszynski <[email protected]>");
MODULE_DESCRIPTION("Sensirion SCD30 carbon dioxide sensor core driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/chemical/scd30_core.c |
// SPDX-License-Identifier: GPL-2.0
/*
* BME680 - I2C Driver
*
* Copyright (C) 2018 Himanshu Jha <[email protected]>
*
* 7-Bit I2C slave address is:
* - 0x76 if SDO is pulled to GND
* - 0x77 if SDO is pulled to VDDIO
*
* Note: SDO pin cannot be left floating otherwise I2C address
* will be undefined.
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include "bme680.h"
static int bme680_i2c_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct regmap *regmap;
const char *name = NULL;
regmap = devm_regmap_init_i2c(client, &bme680_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "Failed to register i2c regmap %ld\n", PTR_ERR(regmap));
return PTR_ERR(regmap);
}
if (id)
name = id->name;
return bme680_core_probe(&client->dev, regmap, name);
}
static const struct i2c_device_id bme680_i2c_id[] = {
{"bme680", 0},
{},
};
MODULE_DEVICE_TABLE(i2c, bme680_i2c_id);
static const struct of_device_id bme680_of_i2c_match[] = {
{ .compatible = "bosch,bme680", },
{},
};
MODULE_DEVICE_TABLE(of, bme680_of_i2c_match);
static struct i2c_driver bme680_i2c_driver = {
.driver = {
.name = "bme680_i2c",
.of_match_table = bme680_of_i2c_match,
},
.probe = bme680_i2c_probe,
.id_table = bme680_i2c_id,
};
module_i2c_driver(bme680_i2c_driver);
MODULE_AUTHOR("Himanshu Jha <[email protected]>");
MODULE_DESCRIPTION("BME680 I2C driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_BME680);
| linux-master | drivers/iio/chemical/bme680_i2c.c |
// SPDX-License-Identifier: GPL-2.0
/*
* sgp30.c - Support for Sensirion SGP Gas Sensors
*
* Copyright (C) 2018 Andreas Brauchli <[email protected]>
*
* I2C slave address: 0x58
*
* Datasheets:
* https://www.sensirion.com/file/datasheet_sgp30
* https://www.sensirion.com/file/datasheet_sgpc3
*
* TODO:
* - baseline support
* - humidity compensation
* - power mode switching (SGPC3)
*/
#include <linux/crc8.h>
#include <linux/delay.h>
#include <linux/kthread.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define SGP_WORD_LEN 2
#define SGP_CRC8_POLYNOMIAL 0x31
#define SGP_CRC8_INIT 0xff
#define SGP_CRC8_LEN 1
#define SGP_CMD(cmd_word) cpu_to_be16(cmd_word)
#define SGP_CMD_DURATION_US 12000
#define SGP_MEASUREMENT_DURATION_US 50000
#define SGP_CMD_LEN SGP_WORD_LEN
#define SGP_CMD_MAX_BUF_SIZE (SGP_CMD_LEN + 2 * SGP_WORD_LEN)
#define SGP_MEASUREMENT_LEN 2
#define SGP30_MEASURE_INTERVAL_HZ 1
#define SGPC3_MEASURE_INTERVAL_HZ 2
#define SGP_VERS_PRODUCT(data) ((((data)->feature_set) & 0xf000) >> 12)
#define SGP_VERS_RESERVED(data) ((((data)->feature_set) & 0x0800) >> 11)
#define SGP_VERS_GEN(data) ((((data)->feature_set) & 0x0600) >> 9)
#define SGP_VERS_ENG_BIT(data) ((((data)->feature_set) & 0x0100) >> 8)
#define SGP_VERS_MAJOR(data) ((((data)->feature_set) & 0x00e0) >> 5)
#define SGP_VERS_MINOR(data) (((data)->feature_set) & 0x001f)
DECLARE_CRC8_TABLE(sgp_crc8_table);
enum sgp_product_id {
SGP30 = 0,
SGPC3,
};
enum sgp30_channel_idx {
SGP30_IAQ_TVOC_IDX = 0,
SGP30_IAQ_CO2EQ_IDX,
SGP30_SIG_ETOH_IDX,
SGP30_SIG_H2_IDX,
};
enum sgpc3_channel_idx {
SGPC3_IAQ_TVOC_IDX = 10,
SGPC3_SIG_ETOH_IDX,
};
enum sgp_cmd {
SGP_CMD_IAQ_INIT = SGP_CMD(0x2003),
SGP_CMD_IAQ_MEASURE = SGP_CMD(0x2008),
SGP_CMD_GET_FEATURE_SET = SGP_CMD(0x202f),
SGP_CMD_GET_SERIAL_ID = SGP_CMD(0x3682),
SGP30_CMD_MEASURE_SIGNAL = SGP_CMD(0x2050),
SGPC3_CMD_MEASURE_RAW = SGP_CMD(0x2046),
};
struct sgp_version {
u8 major;
u8 minor;
};
struct sgp_crc_word {
__be16 value;
u8 crc8;
} __attribute__((__packed__));
union sgp_reading {
u8 start;
struct sgp_crc_word raw_words[4];
};
enum _iaq_buffer_state {
IAQ_BUFFER_EMPTY = 0,
IAQ_BUFFER_DEFAULT_VALS,
IAQ_BUFFER_VALID,
};
struct sgp_data {
struct i2c_client *client;
struct task_struct *iaq_thread;
struct mutex data_lock;
unsigned long iaq_init_start_jiffies;
unsigned long iaq_defval_skip_jiffies;
u16 product_id;
u16 feature_set;
unsigned long measure_interval_jiffies;
enum sgp_cmd iaq_init_cmd;
enum sgp_cmd measure_iaq_cmd;
enum sgp_cmd measure_gas_signals_cmd;
union sgp_reading buffer;
union sgp_reading iaq_buffer;
enum _iaq_buffer_state iaq_buffer_state;
};
struct sgp_device {
const struct iio_chan_spec *channels;
int num_channels;
};
static const struct sgp_version supported_versions_sgp30[] = {
{
.major = 1,
.minor = 0,
},
};
static const struct sgp_version supported_versions_sgpc3[] = {
{
.major = 0,
.minor = 4,
},
};
static const struct iio_chan_spec sgp30_channels[] = {
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_VOC,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.address = SGP30_IAQ_TVOC_IDX,
},
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_CO2,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.address = SGP30_IAQ_CO2EQ_IDX,
},
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_ETHANOL,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.address = SGP30_SIG_ETOH_IDX,
},
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_H2,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.address = SGP30_SIG_H2_IDX,
},
};
static const struct iio_chan_spec sgpc3_channels[] = {
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_VOC,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.address = SGPC3_IAQ_TVOC_IDX,
},
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_ETHANOL,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.address = SGPC3_SIG_ETOH_IDX,
},
};
static const struct sgp_device sgp_devices[] = {
[SGP30] = {
.channels = sgp30_channels,
.num_channels = ARRAY_SIZE(sgp30_channels),
},
[SGPC3] = {
.channels = sgpc3_channels,
.num_channels = ARRAY_SIZE(sgpc3_channels),
},
};
/**
* sgp_verify_buffer() - verify the checksums of the data buffer words
*
* @data: SGP data
* @buf: Raw data buffer
* @word_count: Num data words stored in the buffer, excluding CRC bytes
*
* Return: 0 on success, negative error otherwise.
*/
static int sgp_verify_buffer(const struct sgp_data *data,
union sgp_reading *buf, size_t word_count)
{
size_t size = word_count * (SGP_WORD_LEN + SGP_CRC8_LEN);
int i;
u8 crc;
u8 *data_buf = &buf->start;
for (i = 0; i < size; i += SGP_WORD_LEN + SGP_CRC8_LEN) {
crc = crc8(sgp_crc8_table, &data_buf[i], SGP_WORD_LEN,
SGP_CRC8_INIT);
if (crc != data_buf[i + SGP_WORD_LEN]) {
dev_err(&data->client->dev, "CRC error\n");
return -EIO;
}
}
return 0;
}
/**
* sgp_read_cmd() - reads data from sensor after issuing a command
* The caller must hold data->data_lock for the duration of the call.
* @data: SGP data
* @cmd: SGP Command to issue
* @buf: Raw data buffer to use
* @word_count: Num words to read, excluding CRC bytes
* @duration_us: Time taken to sensor to take a reading and data to be ready.
*
* Return: 0 on success, negative error otherwise.
*/
static int sgp_read_cmd(struct sgp_data *data, enum sgp_cmd cmd,
union sgp_reading *buf, size_t word_count,
unsigned long duration_us)
{
int ret;
struct i2c_client *client = data->client;
size_t size = word_count * (SGP_WORD_LEN + SGP_CRC8_LEN);
u8 *data_buf;
ret = i2c_master_send(client, (const char *)&cmd, SGP_CMD_LEN);
if (ret != SGP_CMD_LEN)
return -EIO;
usleep_range(duration_us, duration_us + 1000);
if (word_count == 0)
return 0;
data_buf = &buf->start;
ret = i2c_master_recv(client, data_buf, size);
if (ret < 0)
return ret;
if (ret != size)
return -EIO;
return sgp_verify_buffer(data, buf, word_count);
}
/**
* sgp_measure_iaq() - measure and retrieve IAQ values from sensor
* The caller must hold data->data_lock for the duration of the call.
* @data: SGP data
*
* Return: 0 on success, -EBUSY on default values, negative error
* otherwise.
*/
static int sgp_measure_iaq(struct sgp_data *data)
{
int ret;
/* data contains default values */
bool default_vals = !time_after(jiffies, data->iaq_init_start_jiffies +
data->iaq_defval_skip_jiffies);
ret = sgp_read_cmd(data, data->measure_iaq_cmd, &data->iaq_buffer,
SGP_MEASUREMENT_LEN, SGP_MEASUREMENT_DURATION_US);
if (ret < 0)
return ret;
data->iaq_buffer_state = IAQ_BUFFER_DEFAULT_VALS;
if (default_vals)
return -EBUSY;
data->iaq_buffer_state = IAQ_BUFFER_VALID;
return 0;
}
static void sgp_iaq_thread_sleep_until(const struct sgp_data *data,
unsigned long sleep_jiffies)
{
const long IAQ_POLL = 50000;
while (!time_after(jiffies, sleep_jiffies)) {
usleep_range(IAQ_POLL, IAQ_POLL + 10000);
if (kthread_should_stop() || data->iaq_init_start_jiffies == 0)
return;
}
}
static int sgp_iaq_threadfn(void *p)
{
struct sgp_data *data = (struct sgp_data *)p;
unsigned long next_update_jiffies;
int ret;
while (!kthread_should_stop()) {
mutex_lock(&data->data_lock);
if (data->iaq_init_start_jiffies == 0) {
ret = sgp_read_cmd(data, data->iaq_init_cmd, NULL, 0,
SGP_CMD_DURATION_US);
if (ret < 0)
goto unlock_sleep_continue;
data->iaq_init_start_jiffies = jiffies;
}
ret = sgp_measure_iaq(data);
if (ret && ret != -EBUSY) {
dev_warn(&data->client->dev,
"IAQ measurement error [%d]\n", ret);
}
unlock_sleep_continue:
next_update_jiffies = jiffies + data->measure_interval_jiffies;
mutex_unlock(&data->data_lock);
sgp_iaq_thread_sleep_until(data, next_update_jiffies);
}
return 0;
}
static int sgp_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct sgp_data *data = iio_priv(indio_dev);
struct sgp_crc_word *words;
int ret;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
mutex_lock(&data->data_lock);
if (data->iaq_buffer_state != IAQ_BUFFER_VALID) {
mutex_unlock(&data->data_lock);
return -EBUSY;
}
words = data->iaq_buffer.raw_words;
switch (chan->address) {
case SGP30_IAQ_TVOC_IDX:
case SGPC3_IAQ_TVOC_IDX:
*val = 0;
*val2 = be16_to_cpu(words[1].value);
ret = IIO_VAL_INT_PLUS_NANO;
break;
case SGP30_IAQ_CO2EQ_IDX:
*val = 0;
*val2 = be16_to_cpu(words[0].value);
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&data->data_lock);
break;
case IIO_CHAN_INFO_RAW:
mutex_lock(&data->data_lock);
if (chan->address == SGPC3_SIG_ETOH_IDX) {
if (data->iaq_buffer_state == IAQ_BUFFER_EMPTY)
ret = -EBUSY;
else
ret = 0;
words = data->iaq_buffer.raw_words;
} else {
ret = sgp_read_cmd(data, data->measure_gas_signals_cmd,
&data->buffer, SGP_MEASUREMENT_LEN,
SGP_MEASUREMENT_DURATION_US);
words = data->buffer.raw_words;
}
if (ret) {
mutex_unlock(&data->data_lock);
return ret;
}
switch (chan->address) {
case SGP30_SIG_ETOH_IDX:
*val = be16_to_cpu(words[1].value);
ret = IIO_VAL_INT;
break;
case SGPC3_SIG_ETOH_IDX:
case SGP30_SIG_H2_IDX:
*val = be16_to_cpu(words[0].value);
ret = IIO_VAL_INT;
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&data->data_lock);
break;
default:
return -EINVAL;
}
return ret;
}
static int sgp_check_compat(struct sgp_data *data,
unsigned int product_id)
{
struct device *dev = &data->client->dev;
const struct sgp_version *supported_versions;
u16 ix, num_fs;
u16 product, generation, major, minor;
/* driver does not match product */
generation = SGP_VERS_GEN(data);
if (generation != 0) {
dev_err(dev,
"incompatible product generation %d != 0", generation);
return -ENODEV;
}
product = SGP_VERS_PRODUCT(data);
if (product != product_id) {
dev_err(dev, "sensor reports a different product: 0x%04x\n",
product);
return -ENODEV;
}
if (SGP_VERS_RESERVED(data))
dev_warn(dev, "reserved bit is set\n");
/* engineering samples are not supported: no interface guarantees */
if (SGP_VERS_ENG_BIT(data))
return -ENODEV;
switch (product) {
case SGP30:
supported_versions = supported_versions_sgp30;
num_fs = ARRAY_SIZE(supported_versions_sgp30);
break;
case SGPC3:
supported_versions = supported_versions_sgpc3;
num_fs = ARRAY_SIZE(supported_versions_sgpc3);
break;
default:
return -ENODEV;
}
major = SGP_VERS_MAJOR(data);
minor = SGP_VERS_MINOR(data);
for (ix = 0; ix < num_fs; ix++) {
if (major == supported_versions[ix].major &&
minor >= supported_versions[ix].minor)
return 0;
}
dev_err(dev, "unsupported sgp version: %d.%d\n", major, minor);
return -ENODEV;
}
static void sgp_init(struct sgp_data *data)
{
data->iaq_init_cmd = SGP_CMD_IAQ_INIT;
data->iaq_init_start_jiffies = 0;
data->iaq_buffer_state = IAQ_BUFFER_EMPTY;
switch (SGP_VERS_PRODUCT(data)) {
case SGP30:
data->measure_interval_jiffies = SGP30_MEASURE_INTERVAL_HZ * HZ;
data->measure_iaq_cmd = SGP_CMD_IAQ_MEASURE;
data->measure_gas_signals_cmd = SGP30_CMD_MEASURE_SIGNAL;
data->product_id = SGP30;
data->iaq_defval_skip_jiffies = 15 * HZ;
break;
case SGPC3:
data->measure_interval_jiffies = SGPC3_MEASURE_INTERVAL_HZ * HZ;
data->measure_iaq_cmd = SGPC3_CMD_MEASURE_RAW;
data->measure_gas_signals_cmd = SGPC3_CMD_MEASURE_RAW;
data->product_id = SGPC3;
data->iaq_defval_skip_jiffies =
43 * data->measure_interval_jiffies;
break;
}
}
static const struct iio_info sgp_info = {
.read_raw = sgp_read_raw,
};
static const struct of_device_id sgp_dt_ids[] = {
{ .compatible = "sensirion,sgp30", .data = (void *)SGP30 },
{ .compatible = "sensirion,sgpc3", .data = (void *)SGPC3 },
{ }
};
static int sgp_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct device *dev = &client->dev;
struct iio_dev *indio_dev;
struct sgp_data *data;
unsigned long product_id;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
if (dev_fwnode(dev))
product_id = (unsigned long)device_get_match_data(dev);
else
product_id = id->driver_data;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
crc8_populate_msb(sgp_crc8_table, SGP_CRC8_POLYNOMIAL);
mutex_init(&data->data_lock);
/* get feature set version and write it to client data */
ret = sgp_read_cmd(data, SGP_CMD_GET_FEATURE_SET, &data->buffer, 1,
SGP_CMD_DURATION_US);
if (ret < 0)
return ret;
data->feature_set = be16_to_cpu(data->buffer.raw_words[0].value);
ret = sgp_check_compat(data, product_id);
if (ret)
return ret;
indio_dev->info = &sgp_info;
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = sgp_devices[product_id].channels;
indio_dev->num_channels = sgp_devices[product_id].num_channels;
sgp_init(data);
ret = devm_iio_device_register(dev, indio_dev);
if (ret) {
dev_err(dev, "failed to register iio device\n");
return ret;
}
data->iaq_thread = kthread_run(sgp_iaq_threadfn, data,
"%s-iaq", data->client->name);
return 0;
}
static void sgp_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct sgp_data *data = iio_priv(indio_dev);
if (data->iaq_thread)
kthread_stop(data->iaq_thread);
}
static const struct i2c_device_id sgp_id[] = {
{ "sgp30", SGP30 },
{ "sgpc3", SGPC3 },
{ }
};
MODULE_DEVICE_TABLE(i2c, sgp_id);
MODULE_DEVICE_TABLE(of, sgp_dt_ids);
static struct i2c_driver sgp_driver = {
.driver = {
.name = "sgp30",
.of_match_table = sgp_dt_ids,
},
.probe = sgp_probe,
.remove = sgp_remove,
.id_table = sgp_id,
};
module_i2c_driver(sgp_driver);
MODULE_AUTHOR("Andreas Brauchli <[email protected]>");
MODULE_AUTHOR("Pascal Sachs <[email protected]>");
MODULE_DESCRIPTION("Sensirion SGP gas sensors");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/chemical/sgp30.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Plantower PMS7003 particulate matter sensor driver
*
* Copyright (c) Tomasz Duszynski <[email protected]>
*/
#include <asm/unaligned.h>
#include <linux/completion.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/serdev.h>
#define PMS7003_DRIVER_NAME "pms7003"
#define PMS7003_MAGIC 0x424d
/* last 2 data bytes hold frame checksum */
#define PMS7003_MAX_DATA_LENGTH 28
#define PMS7003_CHECKSUM_LENGTH 2
#define PMS7003_PM10_OFFSET 10
#define PMS7003_PM2P5_OFFSET 8
#define PMS7003_PM1_OFFSET 6
#define PMS7003_TIMEOUT msecs_to_jiffies(6000)
#define PMS7003_CMD_LENGTH 7
#define PMS7003_PM_MAX 1000
#define PMS7003_PM_MIN 0
enum {
PM1,
PM2P5,
PM10,
};
enum pms7003_cmd {
CMD_WAKEUP,
CMD_ENTER_PASSIVE_MODE,
CMD_READ_PASSIVE,
CMD_SLEEP,
};
/*
* commands have following format:
*
* +------+------+-----+------+-----+-----------+-----------+
* | 0x42 | 0x4d | cmd | 0x00 | arg | cksum msb | cksum lsb |
* +------+------+-----+------+-----+-----------+-----------+
*/
static const u8 pms7003_cmd_tbl[][PMS7003_CMD_LENGTH] = {
[CMD_WAKEUP] = { 0x42, 0x4d, 0xe4, 0x00, 0x01, 0x01, 0x74 },
[CMD_ENTER_PASSIVE_MODE] = { 0x42, 0x4d, 0xe1, 0x00, 0x00, 0x01, 0x70 },
[CMD_READ_PASSIVE] = { 0x42, 0x4d, 0xe2, 0x00, 0x00, 0x01, 0x71 },
[CMD_SLEEP] = { 0x42, 0x4d, 0xe4, 0x00, 0x00, 0x01, 0x73 },
};
struct pms7003_frame {
u8 data[PMS7003_MAX_DATA_LENGTH];
u16 expected_length;
u16 length;
};
struct pms7003_state {
struct serdev_device *serdev;
struct pms7003_frame frame;
struct completion frame_ready;
struct mutex lock; /* must be held whenever state gets touched */
/* Used to construct scan to push to the IIO buffer */
struct {
u16 data[3]; /* PM1, PM2P5, PM10 */
s64 ts;
} scan;
};
static int pms7003_do_cmd(struct pms7003_state *state, enum pms7003_cmd cmd)
{
int ret;
ret = serdev_device_write(state->serdev, pms7003_cmd_tbl[cmd],
PMS7003_CMD_LENGTH, PMS7003_TIMEOUT);
if (ret < PMS7003_CMD_LENGTH)
return ret < 0 ? ret : -EIO;
ret = wait_for_completion_interruptible_timeout(&state->frame_ready,
PMS7003_TIMEOUT);
if (!ret)
ret = -ETIMEDOUT;
return ret < 0 ? ret : 0;
}
static u16 pms7003_get_pm(const u8 *data)
{
return clamp_val(get_unaligned_be16(data),
PMS7003_PM_MIN, PMS7003_PM_MAX);
}
static irqreturn_t pms7003_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct pms7003_state *state = iio_priv(indio_dev);
struct pms7003_frame *frame = &state->frame;
int ret;
mutex_lock(&state->lock);
ret = pms7003_do_cmd(state, CMD_READ_PASSIVE);
if (ret) {
mutex_unlock(&state->lock);
goto err;
}
state->scan.data[PM1] =
pms7003_get_pm(frame->data + PMS7003_PM1_OFFSET);
state->scan.data[PM2P5] =
pms7003_get_pm(frame->data + PMS7003_PM2P5_OFFSET);
state->scan.data[PM10] =
pms7003_get_pm(frame->data + PMS7003_PM10_OFFSET);
mutex_unlock(&state->lock);
iio_push_to_buffers_with_timestamp(indio_dev, &state->scan,
iio_get_time_ns(indio_dev));
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int pms7003_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct pms7003_state *state = iio_priv(indio_dev);
struct pms7003_frame *frame = &state->frame;
int ret;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_MASSCONCENTRATION:
mutex_lock(&state->lock);
ret = pms7003_do_cmd(state, CMD_READ_PASSIVE);
if (ret) {
mutex_unlock(&state->lock);
return ret;
}
*val = pms7003_get_pm(frame->data + chan->address);
mutex_unlock(&state->lock);
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
return -EINVAL;
}
static const struct iio_info pms7003_info = {
.read_raw = pms7003_read_raw,
};
#define PMS7003_CHAN(_index, _mod, _addr) { \
.type = IIO_MASSCONCENTRATION, \
.modified = 1, \
.channel2 = IIO_MOD_ ## _mod, \
.address = _addr, \
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
.scan_index = _index, \
.scan_type = { \
.sign = 'u', \
.realbits = 10, \
.storagebits = 16, \
.endianness = IIO_CPU, \
}, \
}
static const struct iio_chan_spec pms7003_channels[] = {
PMS7003_CHAN(0, PM1, PMS7003_PM1_OFFSET),
PMS7003_CHAN(1, PM2P5, PMS7003_PM2P5_OFFSET),
PMS7003_CHAN(2, PM10, PMS7003_PM10_OFFSET),
IIO_CHAN_SOFT_TIMESTAMP(3),
};
static u16 pms7003_calc_checksum(struct pms7003_frame *frame)
{
u16 checksum = (PMS7003_MAGIC >> 8) + (u8)(PMS7003_MAGIC & 0xff) +
(frame->length >> 8) + (u8)frame->length;
int i;
for (i = 0; i < frame->length - PMS7003_CHECKSUM_LENGTH; i++)
checksum += frame->data[i];
return checksum;
}
static bool pms7003_frame_is_okay(struct pms7003_frame *frame)
{
int offset = frame->length - PMS7003_CHECKSUM_LENGTH;
u16 checksum = get_unaligned_be16(frame->data + offset);
return checksum == pms7003_calc_checksum(frame);
}
static int pms7003_receive_buf(struct serdev_device *serdev,
const unsigned char *buf, size_t size)
{
struct iio_dev *indio_dev = serdev_device_get_drvdata(serdev);
struct pms7003_state *state = iio_priv(indio_dev);
struct pms7003_frame *frame = &state->frame;
int num;
if (!frame->expected_length) {
u16 magic;
/* wait for SOF and data length */
if (size < 4)
return 0;
magic = get_unaligned_be16(buf);
if (magic != PMS7003_MAGIC)
return 2;
num = get_unaligned_be16(buf + 2);
if (num <= PMS7003_MAX_DATA_LENGTH) {
frame->expected_length = num;
frame->length = 0;
}
return 4;
}
num = min(size, (size_t)(frame->expected_length - frame->length));
memcpy(frame->data + frame->length, buf, num);
frame->length += num;
if (frame->length == frame->expected_length) {
if (pms7003_frame_is_okay(frame))
complete(&state->frame_ready);
frame->expected_length = 0;
}
return num;
}
static const struct serdev_device_ops pms7003_serdev_ops = {
.receive_buf = pms7003_receive_buf,
.write_wakeup = serdev_device_write_wakeup,
};
static void pms7003_stop(void *data)
{
struct pms7003_state *state = data;
pms7003_do_cmd(state, CMD_SLEEP);
}
static const unsigned long pms7003_scan_masks[] = { 0x07, 0x00 };
static int pms7003_probe(struct serdev_device *serdev)
{
struct pms7003_state *state;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&serdev->dev, sizeof(*state));
if (!indio_dev)
return -ENOMEM;
state = iio_priv(indio_dev);
serdev_device_set_drvdata(serdev, indio_dev);
state->serdev = serdev;
indio_dev->info = &pms7003_info;
indio_dev->name = PMS7003_DRIVER_NAME;
indio_dev->channels = pms7003_channels;
indio_dev->num_channels = ARRAY_SIZE(pms7003_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->available_scan_masks = pms7003_scan_masks;
mutex_init(&state->lock);
init_completion(&state->frame_ready);
serdev_device_set_client_ops(serdev, &pms7003_serdev_ops);
ret = devm_serdev_device_open(&serdev->dev, serdev);
if (ret)
return ret;
serdev_device_set_baudrate(serdev, 9600);
serdev_device_set_flow_control(serdev, false);
ret = serdev_device_set_parity(serdev, SERDEV_PARITY_NONE);
if (ret)
return ret;
ret = pms7003_do_cmd(state, CMD_WAKEUP);
if (ret) {
dev_err(&serdev->dev, "failed to wakeup sensor\n");
return ret;
}
ret = pms7003_do_cmd(state, CMD_ENTER_PASSIVE_MODE);
if (ret) {
dev_err(&serdev->dev, "failed to enter passive mode\n");
return ret;
}
ret = devm_add_action_or_reset(&serdev->dev, pms7003_stop, state);
if (ret)
return ret;
ret = devm_iio_triggered_buffer_setup(&serdev->dev, indio_dev, NULL,
pms7003_trigger_handler, NULL);
if (ret)
return ret;
return devm_iio_device_register(&serdev->dev, indio_dev);
}
static const struct of_device_id pms7003_of_match[] = {
{ .compatible = "plantower,pms1003" },
{ .compatible = "plantower,pms3003" },
{ .compatible = "plantower,pms5003" },
{ .compatible = "plantower,pms6003" },
{ .compatible = "plantower,pms7003" },
{ .compatible = "plantower,pmsa003" },
{ }
};
MODULE_DEVICE_TABLE(of, pms7003_of_match);
static struct serdev_device_driver pms7003_driver = {
.driver = {
.name = PMS7003_DRIVER_NAME,
.of_match_table = pms7003_of_match,
},
.probe = pms7003_probe,
};
module_serdev_device_driver(pms7003_driver);
MODULE_AUTHOR("Tomasz Duszynski <[email protected]>");
MODULE_DESCRIPTION("Plantower PMS7003 particulate matter sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/chemical/pms7003.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Sensirion SPS30 particulate matter sensor driver
*
* Copyright (c) Tomasz Duszynski <[email protected]>
*/
#include <linux/crc8.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include "sps30.h"
/* sensor measures reliably up to 3000 ug / m3 */
#define SPS30_MAX_PM 3000
/* minimum and maximum self cleaning periods in seconds */
#define SPS30_AUTO_CLEANING_PERIOD_MIN 0
#define SPS30_AUTO_CLEANING_PERIOD_MAX 604800
enum {
PM1,
PM2P5,
PM4,
PM10,
};
enum {
RESET,
MEASURING,
};
static s32 sps30_float_to_int_clamped(__be32 *fp)
{
int val = be32_to_cpup(fp);
int mantissa = val & GENMASK(22, 0);
/* this is fine since passed float is always non-negative */
int exp = val >> 23;
int fraction, shift;
/* special case 0 */
if (!exp && !mantissa)
return 0;
exp -= 127;
if (exp < 0) {
/* return values ranging from 1 to 99 */
return ((((1 << 23) + mantissa) * 100) >> 23) >> (-exp);
}
/* return values ranging from 100 to 300000 */
shift = 23 - exp;
val = (1 << exp) + (mantissa >> shift);
if (val >= SPS30_MAX_PM)
return SPS30_MAX_PM * 100;
fraction = mantissa & GENMASK(shift - 1, 0);
return val * 100 + ((fraction * 100) >> shift);
}
static int sps30_do_meas(struct sps30_state *state, s32 *data, int size)
{
int i, ret;
if (state->state == RESET) {
ret = state->ops->start_meas(state);
if (ret)
return ret;
state->state = MEASURING;
}
ret = state->ops->read_meas(state, (__be32 *)data, size);
if (ret)
return ret;
for (i = 0; i < size; i++)
data[i] = sps30_float_to_int_clamped((__be32 *)&data[i]);
return 0;
}
static int sps30_do_reset(struct sps30_state *state)
{
int ret;
ret = state->ops->reset(state);
if (ret)
return ret;
state->state = RESET;
return 0;
}
static irqreturn_t sps30_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct sps30_state *state = iio_priv(indio_dev);
int ret;
struct {
s32 data[4]; /* PM1, PM2P5, PM4, PM10 */
s64 ts;
} scan;
mutex_lock(&state->lock);
ret = sps30_do_meas(state, scan.data, ARRAY_SIZE(scan.data));
mutex_unlock(&state->lock);
if (ret)
goto err;
iio_push_to_buffers_with_timestamp(indio_dev, &scan,
iio_get_time_ns(indio_dev));
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int sps30_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct sps30_state *state = iio_priv(indio_dev);
int data[4], ret = -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_MASSCONCENTRATION:
mutex_lock(&state->lock);
/* read up to the number of bytes actually needed */
switch (chan->channel2) {
case IIO_MOD_PM1:
ret = sps30_do_meas(state, data, 1);
break;
case IIO_MOD_PM2P5:
ret = sps30_do_meas(state, data, 2);
break;
case IIO_MOD_PM4:
ret = sps30_do_meas(state, data, 3);
break;
case IIO_MOD_PM10:
ret = sps30_do_meas(state, data, 4);
break;
}
mutex_unlock(&state->lock);
if (ret)
return ret;
*val = data[chan->address] / 100;
*val2 = (data[chan->address] % 100) * 10000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_MASSCONCENTRATION:
switch (chan->channel2) {
case IIO_MOD_PM1:
case IIO_MOD_PM2P5:
case IIO_MOD_PM4:
case IIO_MOD_PM10:
*val = 0;
*val2 = 10000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
return -EINVAL;
}
static ssize_t start_cleaning_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct sps30_state *state = iio_priv(indio_dev);
int val, ret;
if (kstrtoint(buf, 0, &val) || val != 1)
return -EINVAL;
mutex_lock(&state->lock);
ret = state->ops->clean_fan(state);
mutex_unlock(&state->lock);
if (ret)
return ret;
return len;
}
static ssize_t cleaning_period_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct sps30_state *state = iio_priv(indio_dev);
__be32 val;
int ret;
mutex_lock(&state->lock);
ret = state->ops->read_cleaning_period(state, &val);
mutex_unlock(&state->lock);
if (ret)
return ret;
return sysfs_emit(buf, "%d\n", be32_to_cpu(val));
}
static ssize_t cleaning_period_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct sps30_state *state = iio_priv(indio_dev);
int val, ret;
if (kstrtoint(buf, 0, &val))
return -EINVAL;
if ((val < SPS30_AUTO_CLEANING_PERIOD_MIN) ||
(val > SPS30_AUTO_CLEANING_PERIOD_MAX))
return -EINVAL;
mutex_lock(&state->lock);
ret = state->ops->write_cleaning_period(state, cpu_to_be32(val));
if (ret) {
mutex_unlock(&state->lock);
return ret;
}
msleep(20);
/*
* sensor requires reset in order to return up to date self cleaning
* period
*/
ret = sps30_do_reset(state);
if (ret)
dev_warn(dev,
"period changed but reads will return the old value\n");
mutex_unlock(&state->lock);
return len;
}
static ssize_t cleaning_period_available_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return sysfs_emit(buf, "[%d %d %d]\n",
SPS30_AUTO_CLEANING_PERIOD_MIN, 1,
SPS30_AUTO_CLEANING_PERIOD_MAX);
}
static IIO_DEVICE_ATTR_WO(start_cleaning, 0);
static IIO_DEVICE_ATTR_RW(cleaning_period, 0);
static IIO_DEVICE_ATTR_RO(cleaning_period_available, 0);
static struct attribute *sps30_attrs[] = {
&iio_dev_attr_start_cleaning.dev_attr.attr,
&iio_dev_attr_cleaning_period.dev_attr.attr,
&iio_dev_attr_cleaning_period_available.dev_attr.attr,
NULL
};
static const struct attribute_group sps30_attr_group = {
.attrs = sps30_attrs,
};
static const struct iio_info sps30_info = {
.attrs = &sps30_attr_group,
.read_raw = sps30_read_raw,
};
#define SPS30_CHAN(_index, _mod) { \
.type = IIO_MASSCONCENTRATION, \
.modified = 1, \
.channel2 = IIO_MOD_ ## _mod, \
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.address = _mod, \
.scan_index = _index, \
.scan_type = { \
.sign = 'u', \
.realbits = 19, \
.storagebits = 32, \
.endianness = IIO_CPU, \
}, \
}
static const struct iio_chan_spec sps30_channels[] = {
SPS30_CHAN(0, PM1),
SPS30_CHAN(1, PM2P5),
SPS30_CHAN(2, PM4),
SPS30_CHAN(3, PM10),
IIO_CHAN_SOFT_TIMESTAMP(4),
};
static void sps30_devm_stop_meas(void *data)
{
struct sps30_state *state = data;
if (state->state == MEASURING)
state->ops->stop_meas(state);
}
static const unsigned long sps30_scan_masks[] = { 0x0f, 0x00 };
int sps30_probe(struct device *dev, const char *name, void *priv, const struct sps30_ops *ops)
{
struct iio_dev *indio_dev;
struct sps30_state *state;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*state));
if (!indio_dev)
return -ENOMEM;
dev_set_drvdata(dev, indio_dev);
state = iio_priv(indio_dev);
state->dev = dev;
state->priv = priv;
state->ops = ops;
mutex_init(&state->lock);
indio_dev->info = &sps30_info;
indio_dev->name = name;
indio_dev->channels = sps30_channels;
indio_dev->num_channels = ARRAY_SIZE(sps30_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->available_scan_masks = sps30_scan_masks;
ret = sps30_do_reset(state);
if (ret) {
dev_err(dev, "failed to reset device\n");
return ret;
}
ret = state->ops->show_info(state);
if (ret) {
dev_err(dev, "failed to read device info\n");
return ret;
}
ret = devm_add_action_or_reset(dev, sps30_devm_stop_meas, state);
if (ret)
return ret;
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
sps30_trigger_handler, NULL);
if (ret)
return ret;
return devm_iio_device_register(dev, indio_dev);
}
EXPORT_SYMBOL_NS_GPL(sps30_probe, IIO_SPS30);
MODULE_AUTHOR("Tomasz Duszynski <[email protected]>");
MODULE_DESCRIPTION("Sensirion SPS30 particulate matter sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/chemical/sps30.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* sgp40.c - Support for Sensirion SGP40 Gas Sensor
*
* Copyright (C) 2021 Andreas Klinger <[email protected]>
*
* I2C slave address: 0x59
*
* Datasheet can be found here:
* https://www.sensirion.com/file/datasheet_sgp40
*
* There are two functionalities supported:
*
* 1) read raw logarithmic resistance value from sensor
* --> useful to pass it to the algorithm of the sensor vendor for
* measuring deteriorations and improvements of air quality.
*
* 2) calculate an estimated absolute voc index (0 - 500 index points) for
* measuring the air quality.
* For this purpose the value of the resistance for which the voc index
* will be 250 can be set up using calibbias.
*
* Compensation values of relative humidity and temperature can be set up
* by writing to the out values of temp and humidityrelative.
*/
#include <linux/delay.h>
#include <linux/crc8.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
/*
* floating point calculation of voc is done as integer
* where numbers are multiplied by 1 << SGP40_CALC_POWER
*/
#define SGP40_CALC_POWER 14
#define SGP40_CRC8_POLYNOMIAL 0x31
#define SGP40_CRC8_INIT 0xff
DECLARE_CRC8_TABLE(sgp40_crc8_table);
struct sgp40_data {
struct device *dev;
struct i2c_client *client;
int rht;
int temp;
int res_calibbias;
/* Prevent concurrent access to rht, tmp, calibbias */
struct mutex lock;
};
struct sgp40_tg_measure {
u8 command[2];
__be16 rht_ticks;
u8 rht_crc;
__be16 temp_ticks;
u8 temp_crc;
} __packed;
struct sgp40_tg_result {
__be16 res_ticks;
u8 res_crc;
} __packed;
static const struct iio_chan_spec sgp40_channels[] = {
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_VOC,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
},
{
.type = IIO_RESISTANCE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
},
{
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.output = 1,
},
{
.type = IIO_HUMIDITYRELATIVE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.output = 1,
},
};
/*
* taylor approximation of e^x:
* y = 1 + x + x^2 / 2 + x^3 / 6 + x^4 / 24 + ... + x^n / n!
*
* Because we are calculating x real value multiplied by 2^power we get
* an additional 2^power^n to divide for every element. For a reasonable
* precision this would overflow after a few iterations. Therefore we
* divide the x^n part whenever its about to overflow (xmax).
*/
static u32 sgp40_exp(int exp, u32 power, u32 rounds)
{
u32 x, y, xp;
u32 factorial, divider, xmax;
int sign = 1;
int i;
if (exp == 0)
return 1 << power;
else if (exp < 0) {
sign = -1;
exp *= -1;
}
xmax = 0x7FFFFFFF / exp;
x = exp;
xp = 1;
factorial = 1;
y = 1 << power;
divider = 0;
for (i = 1; i <= rounds; i++) {
xp *= x;
factorial *= i;
y += (xp >> divider) / factorial;
divider += power;
/* divide when next multiplication would overflow */
if (xp >= xmax) {
xp >>= power;
divider -= power;
}
}
if (sign == -1)
return (1 << (power * 2)) / y;
else
return y;
}
static int sgp40_calc_voc(struct sgp40_data *data, u16 resistance_raw, int *voc)
{
int x;
u32 exp = 0;
/* we calculate as a multiple of 16384 (2^14) */
mutex_lock(&data->lock);
x = ((int)resistance_raw - data->res_calibbias) * 106;
mutex_unlock(&data->lock);
/* voc = 500 / (1 + e^x) */
exp = sgp40_exp(x, SGP40_CALC_POWER, 18);
*voc = 500 * ((1 << (SGP40_CALC_POWER * 2)) / ((1<<SGP40_CALC_POWER) + exp));
dev_dbg(data->dev, "raw: %d res_calibbias: %d x: %d exp: %d voc: %d\n",
resistance_raw, data->res_calibbias, x, exp, *voc);
return 0;
}
static int sgp40_measure_resistance_raw(struct sgp40_data *data, u16 *resistance_raw)
{
int ret;
struct i2c_client *client = data->client;
u32 ticks;
u16 ticks16;
u8 crc;
struct sgp40_tg_measure tg = {.command = {0x26, 0x0F}};
struct sgp40_tg_result tgres;
mutex_lock(&data->lock);
ticks = (data->rht / 10) * 65535 / 10000;
ticks16 = (u16)clamp(ticks, 0u, 65535u); /* clamp between 0 .. 100 %rH */
tg.rht_ticks = cpu_to_be16(ticks16);
tg.rht_crc = crc8(sgp40_crc8_table, (u8 *)&tg.rht_ticks, 2, SGP40_CRC8_INIT);
ticks = ((data->temp + 45000) / 10 ) * 65535 / 17500;
ticks16 = (u16)clamp(ticks, 0u, 65535u); /* clamp between -45 .. +130 °C */
tg.temp_ticks = cpu_to_be16(ticks16);
tg.temp_crc = crc8(sgp40_crc8_table, (u8 *)&tg.temp_ticks, 2, SGP40_CRC8_INIT);
mutex_unlock(&data->lock);
ret = i2c_master_send(client, (const char *)&tg, sizeof(tg));
if (ret != sizeof(tg)) {
dev_warn(data->dev, "i2c_master_send ret: %d sizeof: %zu\n", ret, sizeof(tg));
return -EIO;
}
msleep(30);
ret = i2c_master_recv(client, (u8 *)&tgres, sizeof(tgres));
if (ret < 0)
return ret;
if (ret != sizeof(tgres)) {
dev_warn(data->dev, "i2c_master_recv ret: %d sizeof: %zu\n", ret, sizeof(tgres));
return -EIO;
}
crc = crc8(sgp40_crc8_table, (u8 *)&tgres.res_ticks, 2, SGP40_CRC8_INIT);
if (crc != tgres.res_crc) {
dev_err(data->dev, "CRC error while measure-raw\n");
return -EIO;
}
*resistance_raw = be16_to_cpu(tgres.res_ticks);
return 0;
}
static int sgp40_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct sgp40_data *data = iio_priv(indio_dev);
int ret, voc;
u16 resistance_raw;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_RESISTANCE:
ret = sgp40_measure_resistance_raw(data, &resistance_raw);
if (ret)
return ret;
*val = resistance_raw;
return IIO_VAL_INT;
case IIO_TEMP:
mutex_lock(&data->lock);
*val = data->temp;
mutex_unlock(&data->lock);
return IIO_VAL_INT;
case IIO_HUMIDITYRELATIVE:
mutex_lock(&data->lock);
*val = data->rht;
mutex_unlock(&data->lock);
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_PROCESSED:
ret = sgp40_measure_resistance_raw(data, &resistance_raw);
if (ret)
return ret;
ret = sgp40_calc_voc(data, resistance_raw, &voc);
if (ret)
return ret;
*val = voc / (1 << SGP40_CALC_POWER);
/*
* calculation should fit into integer, where:
* voc <= (500 * 2^SGP40_CALC_POWER) = 8192000
* (with SGP40_CALC_POWER = 14)
*/
*val2 = ((voc % (1 << SGP40_CALC_POWER)) * 244) / (1 << (SGP40_CALC_POWER - 12));
dev_dbg(data->dev, "voc: %d val: %d.%06d\n", voc, *val, *val2);
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_CALIBBIAS:
mutex_lock(&data->lock);
*val = data->res_calibbias;
mutex_unlock(&data->lock);
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int sgp40_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct sgp40_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_TEMP:
if ((val < -45000) || (val > 130000))
return -EINVAL;
mutex_lock(&data->lock);
data->temp = val;
mutex_unlock(&data->lock);
return 0;
case IIO_HUMIDITYRELATIVE:
if ((val < 0) || (val > 100000))
return -EINVAL;
mutex_lock(&data->lock);
data->rht = val;
mutex_unlock(&data->lock);
return 0;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_CALIBBIAS:
if ((val < 20000) || (val > 52768))
return -EINVAL;
mutex_lock(&data->lock);
data->res_calibbias = val;
mutex_unlock(&data->lock);
return 0;
}
return -EINVAL;
}
static const struct iio_info sgp40_info = {
.read_raw = sgp40_read_raw,
.write_raw = sgp40_write_raw,
};
static int sgp40_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct device *dev = &client->dev;
struct iio_dev *indio_dev;
struct sgp40_data *data;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->client = client;
data->dev = dev;
crc8_populate_msb(sgp40_crc8_table, SGP40_CRC8_POLYNOMIAL);
mutex_init(&data->lock);
/* set default values */
data->rht = 50000; /* 50 % */
data->temp = 25000; /* 25 °C */
data->res_calibbias = 30000; /* resistance raw value for voc index of 250 */
indio_dev->info = &sgp40_info;
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = sgp40_channels;
indio_dev->num_channels = ARRAY_SIZE(sgp40_channels);
ret = devm_iio_device_register(dev, indio_dev);
if (ret)
dev_err(dev, "failed to register iio device\n");
return ret;
}
static const struct i2c_device_id sgp40_id[] = {
{ "sgp40" },
{ }
};
MODULE_DEVICE_TABLE(i2c, sgp40_id);
static const struct of_device_id sgp40_dt_ids[] = {
{ .compatible = "sensirion,sgp40" },
{ }
};
MODULE_DEVICE_TABLE(of, sgp40_dt_ids);
static struct i2c_driver sgp40_driver = {
.driver = {
.name = "sgp40",
.of_match_table = sgp40_dt_ids,
},
.probe = sgp40_probe,
.id_table = sgp40_id,
};
module_i2c_driver(sgp40_driver);
MODULE_AUTHOR("Andreas Klinger <[email protected]>");
MODULE_DESCRIPTION("Sensirion SGP40 gas sensor");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/chemical/sgp40.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Senseair Sunrise 006-0-0007 CO2 sensor driver.
*
* Copyright (C) 2021 Jacopo Mondi
*
* List of features not yet supported by the driver:
* - controllable EN pin
* - single-shot operations using the nDRY pin.
* - ABC/target calibration
*/
#include <linux/bitops.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/regmap.h>
#include <linux/time64.h>
#include <linux/iio/iio.h>
#define DRIVER_NAME "sunrise_co2"
#define SUNRISE_ERROR_STATUS_REG 0x00
#define SUNRISE_CO2_FILTERED_COMP_REG 0x06
#define SUNRISE_CHIP_TEMPERATURE_REG 0x08
#define SUNRISE_CALIBRATION_STATUS_REG 0x81
#define SUNRISE_CALIBRATION_COMMAND_REG 0x82
#define SUNRISE_CALIBRATION_FACTORY_CMD 0x7c02
#define SUNRISE_CALIBRATION_BACKGROUND_CMD 0x7c06
/*
* The calibration timeout is not characterized in the datasheet.
* Use 30 seconds as a reasonable upper limit.
*/
#define SUNRISE_CALIBRATION_TIMEOUT_US (30 * USEC_PER_SEC)
struct sunrise_dev {
struct i2c_client *client;
struct regmap *regmap;
/* Protects access to IIO attributes. */
struct mutex lock;
bool ignore_nak;
};
/* Custom regmap read/write operations: perform unlocked access to the i2c bus. */
static int sunrise_regmap_read(void *context, const void *reg_buf,
size_t reg_size, void *val_buf, size_t val_size)
{
struct i2c_client *client = context;
struct sunrise_dev *sunrise = i2c_get_clientdata(client);
union i2c_smbus_data data;
int ret;
if (reg_size != 1 || !val_size)
return -EINVAL;
memset(&data, 0, sizeof(data));
data.block[0] = val_size;
/*
* Wake up sensor by sending sensor address: START, sensor address,
* STOP. Sensor will not ACK this byte.
*
* The chip enters a low power state after 15ms without
* communications or after a complete read/write sequence.
*/
__i2c_smbus_xfer(client->adapter, client->addr,
sunrise->ignore_nak ? I2C_M_IGNORE_NAK : 0,
I2C_SMBUS_WRITE, 0, I2C_SMBUS_BYTE_DATA, &data);
usleep_range(500, 1500);
ret = __i2c_smbus_xfer(client->adapter, client->addr, client->flags,
I2C_SMBUS_READ, ((u8 *)reg_buf)[0],
I2C_SMBUS_I2C_BLOCK_DATA, &data);
if (ret < 0)
return ret;
memcpy(val_buf, &data.block[1], data.block[0]);
return 0;
}
static int sunrise_regmap_write(void *context, const void *val_buf, size_t count)
{
struct i2c_client *client = context;
struct sunrise_dev *sunrise = i2c_get_clientdata(client);
union i2c_smbus_data data;
/* Discard reg address from values count. */
if (!count)
return -EINVAL;
count--;
memset(&data, 0, sizeof(data));
data.block[0] = count;
memcpy(&data.block[1], (u8 *)val_buf + 1, count);
__i2c_smbus_xfer(client->adapter, client->addr,
sunrise->ignore_nak ? I2C_M_IGNORE_NAK : 0,
I2C_SMBUS_WRITE, 0, I2C_SMBUS_BYTE_DATA, &data);
usleep_range(500, 1500);
return __i2c_smbus_xfer(client->adapter, client->addr, client->flags,
I2C_SMBUS_WRITE, ((u8 *)val_buf)[0],
I2C_SMBUS_I2C_BLOCK_DATA, &data);
}
/*
* Sunrise i2c read/write operations: lock the i2c segment to avoid losing the
* wake up session. Use custom regmap operations that perform unlocked access to
* the i2c bus.
*/
static int sunrise_read_byte(struct sunrise_dev *sunrise, u8 reg)
{
const struct i2c_client *client = sunrise->client;
const struct device *dev = &client->dev;
unsigned int val;
int ret;
i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
ret = regmap_read(sunrise->regmap, reg, &val);
i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
if (ret) {
dev_err(dev, "Read byte failed: reg 0x%02x (%d)\n", reg, ret);
return ret;
}
return val;
}
static int sunrise_read_word(struct sunrise_dev *sunrise, u8 reg, u16 *val)
{
const struct i2c_client *client = sunrise->client;
const struct device *dev = &client->dev;
__be16 be_val;
int ret;
i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
ret = regmap_bulk_read(sunrise->regmap, reg, &be_val, sizeof(be_val));
i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
if (ret) {
dev_err(dev, "Read word failed: reg 0x%02x (%d)\n", reg, ret);
return ret;
}
*val = be16_to_cpu(be_val);
return 0;
}
static int sunrise_write_byte(struct sunrise_dev *sunrise, u8 reg, u8 val)
{
const struct i2c_client *client = sunrise->client;
const struct device *dev = &client->dev;
int ret;
i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
ret = regmap_write(sunrise->regmap, reg, val);
i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
if (ret)
dev_err(dev, "Write byte failed: reg 0x%02x (%d)\n", reg, ret);
return ret;
}
static int sunrise_write_word(struct sunrise_dev *sunrise, u8 reg, u16 data)
{
const struct i2c_client *client = sunrise->client;
const struct device *dev = &client->dev;
__be16 be_data = cpu_to_be16(data);
int ret;
i2c_lock_bus(client->adapter, I2C_LOCK_SEGMENT);
ret = regmap_bulk_write(sunrise->regmap, reg, &be_data, sizeof(be_data));
i2c_unlock_bus(client->adapter, I2C_LOCK_SEGMENT);
if (ret)
dev_err(dev, "Write word failed: reg 0x%02x (%d)\n", reg, ret);
return ret;
}
/* Trigger a calibration cycle. */
enum {
SUNRISE_CALIBRATION_FACTORY,
SUNRISE_CALIBRATION_BACKGROUND,
};
static const struct sunrise_calib_data {
u16 cmd;
u8 bit;
const char * const name;
} calib_data[] = {
[SUNRISE_CALIBRATION_FACTORY] = {
SUNRISE_CALIBRATION_FACTORY_CMD,
BIT(2),
"factory_calibration",
},
[SUNRISE_CALIBRATION_BACKGROUND] = {
SUNRISE_CALIBRATION_BACKGROUND_CMD,
BIT(5),
"background_calibration",
},
};
static int sunrise_calibrate(struct sunrise_dev *sunrise,
const struct sunrise_calib_data *data)
{
unsigned int status;
int ret;
/* Reset the calibration status reg. */
ret = sunrise_write_byte(sunrise, SUNRISE_CALIBRATION_STATUS_REG, 0x00);
if (ret)
return ret;
/* Write a calibration command and poll the calibration status bit. */
ret = sunrise_write_word(sunrise, SUNRISE_CALIBRATION_COMMAND_REG, data->cmd);
if (ret)
return ret;
dev_dbg(&sunrise->client->dev, "%s in progress\n", data->name);
/*
* Calibration takes several seconds, so the sleep time between reads
* can be pretty relaxed.
*/
return read_poll_timeout(sunrise_read_byte, status, status & data->bit,
200000, SUNRISE_CALIBRATION_TIMEOUT_US, false,
sunrise, SUNRISE_CALIBRATION_STATUS_REG);
}
static ssize_t sunrise_cal_factory_write(struct iio_dev *iiodev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct sunrise_dev *sunrise = iio_priv(iiodev);
bool enable;
int ret;
ret = kstrtobool(buf, &enable);
if (ret)
return ret;
if (!enable)
return len;
mutex_lock(&sunrise->lock);
ret = sunrise_calibrate(sunrise, &calib_data[SUNRISE_CALIBRATION_FACTORY]);
mutex_unlock(&sunrise->lock);
if (ret)
return ret;
return len;
}
static ssize_t sunrise_cal_background_write(struct iio_dev *iiodev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct sunrise_dev *sunrise = iio_priv(iiodev);
bool enable;
int ret;
ret = kstrtobool(buf, &enable);
if (ret)
return ret;
if (!enable)
return len;
mutex_lock(&sunrise->lock);
ret = sunrise_calibrate(sunrise, &calib_data[SUNRISE_CALIBRATION_BACKGROUND]);
mutex_unlock(&sunrise->lock);
if (ret)
return ret;
return len;
}
/* Enumerate and retrieve the chip error status. */
enum {
SUNRISE_ERROR_FATAL,
SUNRISE_ERROR_I2C,
SUNRISE_ERROR_ALGORITHM,
SUNRISE_ERROR_CALIBRATION,
SUNRISE_ERROR_SELF_DIAGNOSTIC,
SUNRISE_ERROR_OUT_OF_RANGE,
SUNRISE_ERROR_MEMORY,
SUNRISE_ERROR_NO_MEASUREMENT,
SUNRISE_ERROR_LOW_VOLTAGE,
SUNRISE_ERROR_MEASUREMENT_TIMEOUT,
};
static const char * const sunrise_error_statuses[] = {
[SUNRISE_ERROR_FATAL] = "error_fatal",
[SUNRISE_ERROR_I2C] = "error_i2c",
[SUNRISE_ERROR_ALGORITHM] = "error_algorithm",
[SUNRISE_ERROR_CALIBRATION] = "error_calibration",
[SUNRISE_ERROR_SELF_DIAGNOSTIC] = "error_self_diagnostic",
[SUNRISE_ERROR_OUT_OF_RANGE] = "error_out_of_range",
[SUNRISE_ERROR_MEMORY] = "error_memory",
[SUNRISE_ERROR_NO_MEASUREMENT] = "error_no_measurement",
[SUNRISE_ERROR_LOW_VOLTAGE] = "error_low_voltage",
[SUNRISE_ERROR_MEASUREMENT_TIMEOUT] = "error_measurement_timeout",
};
static const struct iio_enum sunrise_error_statuses_enum = {
.items = sunrise_error_statuses,
.num_items = ARRAY_SIZE(sunrise_error_statuses),
};
static ssize_t sunrise_error_status_read(struct iio_dev *iiodev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct sunrise_dev *sunrise = iio_priv(iiodev);
unsigned long errors;
ssize_t len = 0;
u16 value;
int ret;
u8 i;
mutex_lock(&sunrise->lock);
ret = sunrise_read_word(sunrise, SUNRISE_ERROR_STATUS_REG, &value);
if (ret) {
mutex_unlock(&sunrise->lock);
return ret;
}
errors = value;
for_each_set_bit(i, &errors, ARRAY_SIZE(sunrise_error_statuses))
len += sysfs_emit_at(buf, len, "%s ", sunrise_error_statuses[i]);
if (len)
buf[len - 1] = '\n';
mutex_unlock(&sunrise->lock);
return len;
}
static const struct iio_chan_spec_ext_info sunrise_concentration_ext_info[] = {
/* Calibration triggers. */
{
.name = "calibration_factory",
.write = sunrise_cal_factory_write,
.shared = IIO_SEPARATE,
},
{
.name = "calibration_background",
.write = sunrise_cal_background_write,
.shared = IIO_SEPARATE,
},
/* Error statuses. */
{
.name = "error_status",
.read = sunrise_error_status_read,
.shared = IIO_SHARED_BY_ALL,
},
{
.name = "error_status_available",
.shared = IIO_SHARED_BY_ALL,
.read = iio_enum_available_read,
.private = (uintptr_t)&sunrise_error_statuses_enum,
},
{}
};
static const struct iio_chan_spec sunrise_channels[] = {
{
.type = IIO_CONCENTRATION,
.modified = 1,
.channel2 = IIO_MOD_CO2,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.ext_info = sunrise_concentration_ext_info,
},
{
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
};
static int sunrise_read_raw(struct iio_dev *iio_dev,
const struct iio_chan_spec *chan,
int *val, int *val2, long mask)
{
struct sunrise_dev *sunrise = iio_priv(iio_dev);
u16 value;
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_CONCENTRATION:
mutex_lock(&sunrise->lock);
ret = sunrise_read_word(sunrise, SUNRISE_CO2_FILTERED_COMP_REG,
&value);
mutex_unlock(&sunrise->lock);
if (ret)
return ret;
*val = value;
return IIO_VAL_INT;
case IIO_TEMP:
mutex_lock(&sunrise->lock);
ret = sunrise_read_word(sunrise, SUNRISE_CHIP_TEMPERATURE_REG,
&value);
mutex_unlock(&sunrise->lock);
if (ret)
return ret;
*val = value;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_CONCENTRATION:
/*
* 1 / 10^4 to comply with IIO scale for CO2
* (percentage). The chip CO2 reading range is [400 -
* 5000] ppm which corresponds to [0,004 - 0,5] %.
*/
*val = 1;
*val2 = 10000;
return IIO_VAL_FRACTIONAL;
case IIO_TEMP:
/* x10 to comply with IIO scale (millidegrees celsius). */
*val = 10;
return IIO_VAL_INT;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static const struct iio_info sunrise_info = {
.read_raw = sunrise_read_raw,
};
static const struct regmap_bus sunrise_regmap_bus = {
.read = sunrise_regmap_read,
.write = sunrise_regmap_write,
};
static const struct regmap_config sunrise_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static int sunrise_probe(struct i2c_client *client)
{
struct sunrise_dev *sunrise;
struct iio_dev *iio_dev;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_BLOCK_DATA)) {
dev_err(&client->dev,
"Adapter does not support required functionalities\n");
return -EOPNOTSUPP;
}
iio_dev = devm_iio_device_alloc(&client->dev, sizeof(*sunrise));
if (!iio_dev)
return -ENOMEM;
sunrise = iio_priv(iio_dev);
sunrise->client = client;
mutex_init(&sunrise->lock);
i2c_set_clientdata(client, sunrise);
sunrise->regmap = devm_regmap_init(&client->dev, &sunrise_regmap_bus,
client, &sunrise_regmap_config);
if (IS_ERR(sunrise->regmap)) {
dev_err(&client->dev, "Failed to initialize regmap\n");
return PTR_ERR(sunrise->regmap);
}
/*
* The chip nacks the wake up message. If the adapter does not support
* protocol mangling do not set the I2C_M_IGNORE_NAK flag at the expense
* of possible cruft in the logs.
*/
if (i2c_check_functionality(client->adapter, I2C_FUNC_PROTOCOL_MANGLING))
sunrise->ignore_nak = true;
iio_dev->info = &sunrise_info;
iio_dev->name = DRIVER_NAME;
iio_dev->channels = sunrise_channels;
iio_dev->num_channels = ARRAY_SIZE(sunrise_channels);
iio_dev->modes = INDIO_DIRECT_MODE;
return devm_iio_device_register(&client->dev, iio_dev);
}
static const struct of_device_id sunrise_of_match[] = {
{ .compatible = "senseair,sunrise-006-0-0007" },
{}
};
MODULE_DEVICE_TABLE(of, sunrise_of_match);
static struct i2c_driver sunrise_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = sunrise_of_match,
},
.probe = sunrise_probe,
};
module_i2c_driver(sunrise_driver);
MODULE_AUTHOR("Jacopo Mondi <[email protected]>");
MODULE_DESCRIPTION("Senseair Sunrise 006-0-0007 CO2 sensor IIO driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/chemical/sunrise_co2.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* ams-iaq-core.c - Support for AMS iAQ-Core VOC sensors
*
* Copyright (C) 2015, 2018
* Author: Matt Ranostay <[email protected]>
*/
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#define AMS_IAQCORE_DATA_SIZE 9
#define AMS_IAQCORE_VOC_CO2_IDX 0
#define AMS_IAQCORE_VOC_RESISTANCE_IDX 1
#define AMS_IAQCORE_VOC_TVOC_IDX 2
struct ams_iaqcore_reading {
__be16 co2_ppm;
u8 status;
__be32 resistance;
__be16 voc_ppb;
} __attribute__((__packed__));
struct ams_iaqcore_data {
struct i2c_client *client;
struct mutex lock;
unsigned long last_update;
struct ams_iaqcore_reading buffer;
};
static const struct iio_chan_spec ams_iaqcore_channels[] = {
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_CO2,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.address = AMS_IAQCORE_VOC_CO2_IDX,
},
{
.type = IIO_RESISTANCE,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.address = AMS_IAQCORE_VOC_RESISTANCE_IDX,
},
{
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_VOC,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.address = AMS_IAQCORE_VOC_TVOC_IDX,
},
};
static int ams_iaqcore_read_measurement(struct ams_iaqcore_data *data)
{
struct i2c_client *client = data->client;
int ret;
struct i2c_msg msg = {
.addr = client->addr,
.flags = client->flags | I2C_M_RD,
.len = AMS_IAQCORE_DATA_SIZE,
.buf = (char *) &data->buffer,
};
ret = i2c_transfer(client->adapter, &msg, 1);
return (ret == AMS_IAQCORE_DATA_SIZE) ? 0 : ret;
}
static int ams_iaqcore_get_measurement(struct ams_iaqcore_data *data)
{
int ret;
/* sensor can only be polled once a second max per datasheet */
if (!time_after(jiffies, data->last_update + HZ))
return 0;
ret = ams_iaqcore_read_measurement(data);
if (ret < 0)
return ret;
data->last_update = jiffies;
return 0;
}
static int ams_iaqcore_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct ams_iaqcore_data *data = iio_priv(indio_dev);
int ret;
if (mask != IIO_CHAN_INFO_PROCESSED)
return -EINVAL;
mutex_lock(&data->lock);
ret = ams_iaqcore_get_measurement(data);
if (ret)
goto err_out;
switch (chan->address) {
case AMS_IAQCORE_VOC_CO2_IDX:
*val = 0;
*val2 = be16_to_cpu(data->buffer.co2_ppm);
ret = IIO_VAL_INT_PLUS_MICRO;
break;
case AMS_IAQCORE_VOC_RESISTANCE_IDX:
*val = be32_to_cpu(data->buffer.resistance);
ret = IIO_VAL_INT;
break;
case AMS_IAQCORE_VOC_TVOC_IDX:
*val = 0;
*val2 = be16_to_cpu(data->buffer.voc_ppb);
ret = IIO_VAL_INT_PLUS_NANO;
break;
default:
ret = -EINVAL;
}
err_out:
mutex_unlock(&data->lock);
return ret;
}
static const struct iio_info ams_iaqcore_info = {
.read_raw = ams_iaqcore_read_raw,
};
static int ams_iaqcore_probe(struct i2c_client *client)
{
struct iio_dev *indio_dev;
struct ams_iaqcore_data *data;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
/* so initial reading will complete */
data->last_update = jiffies - HZ;
mutex_init(&data->lock);
indio_dev->info = &ams_iaqcore_info;
indio_dev->name = dev_name(&client->dev);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ams_iaqcore_channels;
indio_dev->num_channels = ARRAY_SIZE(ams_iaqcore_channels);
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id ams_iaqcore_id[] = {
{ "ams-iaq-core", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ams_iaqcore_id);
static const struct of_device_id ams_iaqcore_dt_ids[] = {
{ .compatible = "ams,iaq-core" },
{ }
};
MODULE_DEVICE_TABLE(of, ams_iaqcore_dt_ids);
static struct i2c_driver ams_iaqcore_driver = {
.driver = {
.name = "ams-iaq-core",
.of_match_table = ams_iaqcore_dt_ids,
},
.probe = ams_iaqcore_probe,
.id_table = ams_iaqcore_id,
};
module_i2c_driver(ams_iaqcore_driver);
MODULE_AUTHOR("Matt Ranostay <[email protected]>");
MODULE_DESCRIPTION("AMS iAQ-Core VOC sensors");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/chemical/ams-iaq-core.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* atlas-sensor.c - Support for Atlas Scientific OEM SM sensors
*
* Copyright (C) 2015-2019 Konsulko Group
* Author: Matt Ranostay <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/irq_work.h>
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/pm_runtime.h>
#define ATLAS_REGMAP_NAME "atlas_regmap"
#define ATLAS_DRV_NAME "atlas"
#define ATLAS_REG_DEV_TYPE 0x00
#define ATLAS_REG_DEV_VERSION 0x01
#define ATLAS_REG_INT_CONTROL 0x04
#define ATLAS_REG_INT_CONTROL_EN BIT(3)
#define ATLAS_REG_PWR_CONTROL 0x06
#define ATLAS_REG_PH_CALIB_STATUS 0x0d
#define ATLAS_REG_PH_CALIB_STATUS_MASK 0x07
#define ATLAS_REG_PH_CALIB_STATUS_LOW BIT(0)
#define ATLAS_REG_PH_CALIB_STATUS_MID BIT(1)
#define ATLAS_REG_PH_CALIB_STATUS_HIGH BIT(2)
#define ATLAS_REG_EC_CALIB_STATUS 0x0f
#define ATLAS_REG_EC_CALIB_STATUS_MASK 0x0f
#define ATLAS_REG_EC_CALIB_STATUS_DRY BIT(0)
#define ATLAS_REG_EC_CALIB_STATUS_SINGLE BIT(1)
#define ATLAS_REG_EC_CALIB_STATUS_LOW BIT(2)
#define ATLAS_REG_EC_CALIB_STATUS_HIGH BIT(3)
#define ATLAS_REG_DO_CALIB_STATUS 0x09
#define ATLAS_REG_DO_CALIB_STATUS_MASK 0x03
#define ATLAS_REG_DO_CALIB_STATUS_PRESSURE BIT(0)
#define ATLAS_REG_DO_CALIB_STATUS_DO BIT(1)
#define ATLAS_REG_RTD_DATA 0x0e
#define ATLAS_REG_PH_TEMP_DATA 0x0e
#define ATLAS_REG_PH_DATA 0x16
#define ATLAS_REG_EC_PROBE 0x08
#define ATLAS_REG_EC_TEMP_DATA 0x10
#define ATLAS_REG_EC_DATA 0x18
#define ATLAS_REG_TDS_DATA 0x1c
#define ATLAS_REG_PSS_DATA 0x20
#define ATLAS_REG_ORP_CALIB_STATUS 0x0d
#define ATLAS_REG_ORP_DATA 0x0e
#define ATLAS_REG_DO_TEMP_DATA 0x12
#define ATLAS_REG_DO_DATA 0x22
#define ATLAS_PH_INT_TIME_IN_MS 450
#define ATLAS_EC_INT_TIME_IN_MS 650
#define ATLAS_ORP_INT_TIME_IN_MS 450
#define ATLAS_DO_INT_TIME_IN_MS 450
#define ATLAS_RTD_INT_TIME_IN_MS 450
enum {
ATLAS_PH_SM,
ATLAS_EC_SM,
ATLAS_ORP_SM,
ATLAS_DO_SM,
ATLAS_RTD_SM,
};
struct atlas_data {
struct i2c_client *client;
struct iio_trigger *trig;
struct atlas_device *chip;
struct regmap *regmap;
struct irq_work work;
unsigned int interrupt_enabled;
/* 96-bit data + 32-bit pad + 64-bit timestamp */
__be32 buffer[6] __aligned(8);
};
static const struct regmap_config atlas_regmap_config = {
.name = ATLAS_REGMAP_NAME,
.reg_bits = 8,
.val_bits = 8,
};
static int atlas_buffer_num_channels(const struct iio_chan_spec *spec)
{
int idx = 0;
for (; spec->type != IIO_TIMESTAMP; spec++)
idx++;
return idx;
};
static const struct iio_chan_spec atlas_ph_channels[] = {
{
.type = IIO_PH,
.address = ATLAS_REG_PH_DATA,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 0,
.scan_type = {
.sign = 'u',
.realbits = 32,
.storagebits = 32,
.endianness = IIO_BE,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
{
.type = IIO_TEMP,
.address = ATLAS_REG_PH_TEMP_DATA,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.output = 1,
.scan_index = -1
},
};
#define ATLAS_CONCENTRATION_CHANNEL(_idx, _addr) \
{\
.type = IIO_CONCENTRATION, \
.indexed = 1, \
.channel = _idx, \
.address = _addr, \
.info_mask_separate = \
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), \
.scan_index = _idx + 1, \
.scan_type = { \
.sign = 'u', \
.realbits = 32, \
.storagebits = 32, \
.endianness = IIO_BE, \
}, \
}
static const struct iio_chan_spec atlas_ec_channels[] = {
{
.type = IIO_ELECTRICALCONDUCTIVITY,
.address = ATLAS_REG_EC_DATA,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 0,
.scan_type = {
.sign = 'u',
.realbits = 32,
.storagebits = 32,
.endianness = IIO_BE,
},
},
ATLAS_CONCENTRATION_CHANNEL(0, ATLAS_REG_TDS_DATA),
ATLAS_CONCENTRATION_CHANNEL(1, ATLAS_REG_PSS_DATA),
IIO_CHAN_SOFT_TIMESTAMP(3),
{
.type = IIO_TEMP,
.address = ATLAS_REG_EC_TEMP_DATA,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.output = 1,
.scan_index = -1
},
};
static const struct iio_chan_spec atlas_orp_channels[] = {
{
.type = IIO_VOLTAGE,
.address = ATLAS_REG_ORP_DATA,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 0,
.scan_type = {
.sign = 's',
.realbits = 32,
.storagebits = 32,
.endianness = IIO_BE,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static const struct iio_chan_spec atlas_do_channels[] = {
{
.type = IIO_CONCENTRATION,
.address = ATLAS_REG_DO_DATA,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 0,
.scan_type = {
.sign = 'u',
.realbits = 32,
.storagebits = 32,
.endianness = IIO_BE,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
{
.type = IIO_TEMP,
.address = ATLAS_REG_DO_TEMP_DATA,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.output = 1,
.scan_index = -1
},
};
static const struct iio_chan_spec atlas_rtd_channels[] = {
{
.type = IIO_TEMP,
.address = ATLAS_REG_RTD_DATA,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.scan_index = 0,
.scan_type = {
.sign = 's',
.realbits = 32,
.storagebits = 32,
.endianness = IIO_BE,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static int atlas_check_ph_calibration(struct atlas_data *data)
{
struct device *dev = &data->client->dev;
int ret;
unsigned int val;
ret = regmap_read(data->regmap, ATLAS_REG_PH_CALIB_STATUS, &val);
if (ret)
return ret;
if (!(val & ATLAS_REG_PH_CALIB_STATUS_MASK)) {
dev_warn(dev, "device has not been calibrated\n");
return 0;
}
if (!(val & ATLAS_REG_PH_CALIB_STATUS_LOW))
dev_warn(dev, "device missing low point calibration\n");
if (!(val & ATLAS_REG_PH_CALIB_STATUS_MID))
dev_warn(dev, "device missing mid point calibration\n");
if (!(val & ATLAS_REG_PH_CALIB_STATUS_HIGH))
dev_warn(dev, "device missing high point calibration\n");
return 0;
}
static int atlas_check_ec_calibration(struct atlas_data *data)
{
struct device *dev = &data->client->dev;
int ret;
unsigned int val;
__be16 rval;
ret = regmap_bulk_read(data->regmap, ATLAS_REG_EC_PROBE, &rval, 2);
if (ret)
return ret;
val = be16_to_cpu(rval);
dev_info(dev, "probe set to K = %d.%.2d", val / 100, val % 100);
ret = regmap_read(data->regmap, ATLAS_REG_EC_CALIB_STATUS, &val);
if (ret)
return ret;
if (!(val & ATLAS_REG_EC_CALIB_STATUS_MASK)) {
dev_warn(dev, "device has not been calibrated\n");
return 0;
}
if (!(val & ATLAS_REG_EC_CALIB_STATUS_DRY))
dev_warn(dev, "device missing dry point calibration\n");
if (val & ATLAS_REG_EC_CALIB_STATUS_SINGLE) {
dev_warn(dev, "device using single point calibration\n");
} else {
if (!(val & ATLAS_REG_EC_CALIB_STATUS_LOW))
dev_warn(dev, "device missing low point calibration\n");
if (!(val & ATLAS_REG_EC_CALIB_STATUS_HIGH))
dev_warn(dev, "device missing high point calibration\n");
}
return 0;
}
static int atlas_check_orp_calibration(struct atlas_data *data)
{
struct device *dev = &data->client->dev;
int ret;
unsigned int val;
ret = regmap_read(data->regmap, ATLAS_REG_ORP_CALIB_STATUS, &val);
if (ret)
return ret;
if (!val)
dev_warn(dev, "device has not been calibrated\n");
return 0;
}
static int atlas_check_do_calibration(struct atlas_data *data)
{
struct device *dev = &data->client->dev;
int ret;
unsigned int val;
ret = regmap_read(data->regmap, ATLAS_REG_DO_CALIB_STATUS, &val);
if (ret)
return ret;
if (!(val & ATLAS_REG_DO_CALIB_STATUS_MASK)) {
dev_warn(dev, "device has not been calibrated\n");
return 0;
}
if (!(val & ATLAS_REG_DO_CALIB_STATUS_PRESSURE))
dev_warn(dev, "device missing atmospheric pressure calibration\n");
if (!(val & ATLAS_REG_DO_CALIB_STATUS_DO))
dev_warn(dev, "device missing dissolved oxygen calibration\n");
return 0;
}
struct atlas_device {
const struct iio_chan_spec *channels;
int num_channels;
int data_reg;
int (*calibration)(struct atlas_data *data);
int delay;
};
static struct atlas_device atlas_devices[] = {
[ATLAS_PH_SM] = {
.channels = atlas_ph_channels,
.num_channels = 3,
.data_reg = ATLAS_REG_PH_DATA,
.calibration = &atlas_check_ph_calibration,
.delay = ATLAS_PH_INT_TIME_IN_MS,
},
[ATLAS_EC_SM] = {
.channels = atlas_ec_channels,
.num_channels = 5,
.data_reg = ATLAS_REG_EC_DATA,
.calibration = &atlas_check_ec_calibration,
.delay = ATLAS_EC_INT_TIME_IN_MS,
},
[ATLAS_ORP_SM] = {
.channels = atlas_orp_channels,
.num_channels = 2,
.data_reg = ATLAS_REG_ORP_DATA,
.calibration = &atlas_check_orp_calibration,
.delay = ATLAS_ORP_INT_TIME_IN_MS,
},
[ATLAS_DO_SM] = {
.channels = atlas_do_channels,
.num_channels = 3,
.data_reg = ATLAS_REG_DO_DATA,
.calibration = &atlas_check_do_calibration,
.delay = ATLAS_DO_INT_TIME_IN_MS,
},
[ATLAS_RTD_SM] = {
.channels = atlas_rtd_channels,
.num_channels = 2,
.data_reg = ATLAS_REG_RTD_DATA,
.delay = ATLAS_RTD_INT_TIME_IN_MS,
},
};
static int atlas_set_powermode(struct atlas_data *data, int on)
{
return regmap_write(data->regmap, ATLAS_REG_PWR_CONTROL, on);
}
static int atlas_set_interrupt(struct atlas_data *data, bool state)
{
if (!data->interrupt_enabled)
return 0;
return regmap_update_bits(data->regmap, ATLAS_REG_INT_CONTROL,
ATLAS_REG_INT_CONTROL_EN,
state ? ATLAS_REG_INT_CONTROL_EN : 0);
}
static int atlas_buffer_postenable(struct iio_dev *indio_dev)
{
struct atlas_data *data = iio_priv(indio_dev);
int ret;
ret = pm_runtime_resume_and_get(&data->client->dev);
if (ret)
return ret;
return atlas_set_interrupt(data, true);
}
static int atlas_buffer_predisable(struct iio_dev *indio_dev)
{
struct atlas_data *data = iio_priv(indio_dev);
int ret;
ret = atlas_set_interrupt(data, false);
if (ret)
return ret;
pm_runtime_mark_last_busy(&data->client->dev);
ret = pm_runtime_put_autosuspend(&data->client->dev);
if (ret)
return ret;
return 0;
}
static const struct iio_buffer_setup_ops atlas_buffer_setup_ops = {
.postenable = atlas_buffer_postenable,
.predisable = atlas_buffer_predisable,
};
static void atlas_work_handler(struct irq_work *work)
{
struct atlas_data *data = container_of(work, struct atlas_data, work);
iio_trigger_poll(data->trig);
}
static irqreturn_t atlas_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct atlas_data *data = iio_priv(indio_dev);
int channels = atlas_buffer_num_channels(data->chip->channels);
int ret;
ret = regmap_bulk_read(data->regmap, data->chip->data_reg,
&data->buffer, sizeof(__be32) * channels);
if (!ret)
iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
iio_get_time_ns(indio_dev));
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static irqreturn_t atlas_interrupt_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct atlas_data *data = iio_priv(indio_dev);
irq_work_queue(&data->work);
return IRQ_HANDLED;
}
static int atlas_read_measurement(struct atlas_data *data, int reg, __be32 *val)
{
struct device *dev = &data->client->dev;
int suspended = pm_runtime_suspended(dev);
int ret;
ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
if (suspended)
msleep(data->chip->delay);
ret = regmap_bulk_read(data->regmap, reg, val, sizeof(*val));
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
return ret;
}
static int atlas_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct atlas_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
case IIO_CHAN_INFO_RAW: {
int ret;
__be32 reg;
switch (chan->type) {
case IIO_TEMP:
ret = regmap_bulk_read(data->regmap, chan->address,
®, sizeof(reg));
break;
case IIO_PH:
case IIO_CONCENTRATION:
case IIO_ELECTRICALCONDUCTIVITY:
case IIO_VOLTAGE:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = atlas_read_measurement(data, chan->address, ®);
iio_device_release_direct_mode(indio_dev);
break;
default:
ret = -EINVAL;
}
if (!ret) {
*val = be32_to_cpu(reg);
ret = IIO_VAL_INT;
}
return ret;
}
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_TEMP:
*val = 10;
return IIO_VAL_INT;
case IIO_PH:
*val = 1; /* 0.001 */
*val2 = 1000;
break;
case IIO_ELECTRICALCONDUCTIVITY:
*val = 1; /* 0.00001 */
*val2 = 100000;
break;
case IIO_CONCENTRATION:
*val = 0; /* 0.000000001 */
*val2 = 1000;
return IIO_VAL_INT_PLUS_NANO;
case IIO_VOLTAGE:
*val = 1; /* 0.1 */
*val2 = 10;
break;
default:
return -EINVAL;
}
return IIO_VAL_FRACTIONAL;
}
return -EINVAL;
}
static int atlas_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct atlas_data *data = iio_priv(indio_dev);
__be32 reg = cpu_to_be32(val / 10);
if (val2 != 0 || val < 0 || val > 20000)
return -EINVAL;
if (mask != IIO_CHAN_INFO_RAW || chan->type != IIO_TEMP)
return -EINVAL;
return regmap_bulk_write(data->regmap, chan->address,
®, sizeof(reg));
}
static const struct iio_info atlas_info = {
.read_raw = atlas_read_raw,
.write_raw = atlas_write_raw,
};
static const struct i2c_device_id atlas_id[] = {
{ "atlas-ph-sm", ATLAS_PH_SM },
{ "atlas-ec-sm", ATLAS_EC_SM },
{ "atlas-orp-sm", ATLAS_ORP_SM },
{ "atlas-do-sm", ATLAS_DO_SM },
{ "atlas-rtd-sm", ATLAS_RTD_SM },
{}
};
MODULE_DEVICE_TABLE(i2c, atlas_id);
static const struct of_device_id atlas_dt_ids[] = {
{ .compatible = "atlas,ph-sm", .data = (void *)ATLAS_PH_SM, },
{ .compatible = "atlas,ec-sm", .data = (void *)ATLAS_EC_SM, },
{ .compatible = "atlas,orp-sm", .data = (void *)ATLAS_ORP_SM, },
{ .compatible = "atlas,do-sm", .data = (void *)ATLAS_DO_SM, },
{ .compatible = "atlas,rtd-sm", .data = (void *)ATLAS_RTD_SM, },
{ }
};
MODULE_DEVICE_TABLE(of, atlas_dt_ids);
static int atlas_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct atlas_data *data;
struct atlas_device *chip;
struct iio_trigger *trig;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
if (!dev_fwnode(&client->dev))
chip = &atlas_devices[id->driver_data];
else
chip = &atlas_devices[(unsigned long)device_get_match_data(&client->dev)];
indio_dev->info = &atlas_info;
indio_dev->name = ATLAS_DRV_NAME;
indio_dev->channels = chip->channels;
indio_dev->num_channels = chip->num_channels;
indio_dev->modes = INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE;
trig = devm_iio_trigger_alloc(&client->dev, "%s-dev%d",
indio_dev->name, iio_device_id(indio_dev));
if (!trig)
return -ENOMEM;
data = iio_priv(indio_dev);
data->client = client;
data->trig = trig;
data->chip = chip;
iio_trigger_set_drvdata(trig, indio_dev);
i2c_set_clientdata(client, indio_dev);
data->regmap = devm_regmap_init_i2c(client, &atlas_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(&client->dev, "regmap initialization failed\n");
return PTR_ERR(data->regmap);
}
ret = pm_runtime_set_active(&client->dev);
if (ret)
return ret;
ret = chip->calibration(data);
if (ret)
return ret;
ret = iio_trigger_register(trig);
if (ret) {
dev_err(&client->dev, "failed to register trigger\n");
return ret;
}
ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
&atlas_trigger_handler, &atlas_buffer_setup_ops);
if (ret) {
dev_err(&client->dev, "cannot setup iio trigger\n");
goto unregister_trigger;
}
init_irq_work(&data->work, atlas_work_handler);
if (client->irq > 0) {
/* interrupt pin toggles on new conversion */
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, atlas_interrupt_handler,
IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"atlas_irq",
indio_dev);
if (ret)
dev_warn(&client->dev,
"request irq (%d) failed\n", client->irq);
else
data->interrupt_enabled = 1;
}
ret = atlas_set_powermode(data, 1);
if (ret) {
dev_err(&client->dev, "cannot power device on");
goto unregister_buffer;
}
pm_runtime_enable(&client->dev);
pm_runtime_set_autosuspend_delay(&client->dev, 2500);
pm_runtime_use_autosuspend(&client->dev);
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&client->dev, "unable to register device\n");
goto unregister_pm;
}
return 0;
unregister_pm:
pm_runtime_disable(&client->dev);
atlas_set_powermode(data, 0);
unregister_buffer:
iio_triggered_buffer_cleanup(indio_dev);
unregister_trigger:
iio_trigger_unregister(data->trig);
return ret;
}
static void atlas_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct atlas_data *data = iio_priv(indio_dev);
int ret;
iio_device_unregister(indio_dev);
iio_triggered_buffer_cleanup(indio_dev);
iio_trigger_unregister(data->trig);
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
ret = atlas_set_powermode(data, 0);
if (ret)
dev_err(&client->dev, "Failed to power down device (%pe)\n",
ERR_PTR(ret));
}
static int atlas_runtime_suspend(struct device *dev)
{
struct atlas_data *data =
iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
return atlas_set_powermode(data, 0);
}
static int atlas_runtime_resume(struct device *dev)
{
struct atlas_data *data =
iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
return atlas_set_powermode(data, 1);
}
static const struct dev_pm_ops atlas_pm_ops = {
RUNTIME_PM_OPS(atlas_runtime_suspend, atlas_runtime_resume, NULL)
};
static struct i2c_driver atlas_driver = {
.driver = {
.name = ATLAS_DRV_NAME,
.of_match_table = atlas_dt_ids,
.pm = pm_ptr(&atlas_pm_ops),
},
.probe = atlas_probe,
.remove = atlas_remove,
.id_table = atlas_id,
};
module_i2c_driver(atlas_driver);
MODULE_AUTHOR("Matt Ranostay <[email protected]>");
MODULE_DESCRIPTION("Atlas Scientific SM sensors");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/chemical/atlas-sensor.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ccs811.c - Support for AMS CCS811 VOC Sensor
*
* Copyright (C) 2017 Narcisa Vasile <[email protected]>
*
* Datasheet: ams.com/content/download/951091/2269479/CCS811_DS000459_3-00.pdf
*
* IIO driver for AMS CCS811 (I2C address 0x5A/0x5B set by ADDR Low/High)
*
* TODO:
* 1. Make the drive mode selectable form userspace
* 2. Add support for interrupts
* 3. Adjust time to wait for data to be ready based on selected operation mode
* 4. Read error register and put the information in logs
*/
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/module.h>
#define CCS811_STATUS 0x00
#define CCS811_MEAS_MODE 0x01
#define CCS811_ALG_RESULT_DATA 0x02
#define CCS811_RAW_DATA 0x03
#define CCS811_HW_ID 0x20
#define CCS811_HW_ID_VALUE 0x81
#define CCS811_HW_VERSION 0x21
#define CCS811_HW_VERSION_VALUE 0x10
#define CCS811_HW_VERSION_MASK 0xF0
#define CCS811_ERR 0xE0
/* Used to transition from boot to application mode */
#define CCS811_APP_START 0xF4
#define CCS811_SW_RESET 0xFF
/* Status register flags */
#define CCS811_STATUS_ERROR BIT(0)
#define CCS811_STATUS_DATA_READY BIT(3)
#define CCS811_STATUS_APP_VALID_MASK BIT(4)
#define CCS811_STATUS_APP_VALID_LOADED BIT(4)
/*
* Value of FW_MODE bit of STATUS register describes the sensor's state:
* 0: Firmware is in boot mode, this allows new firmware to be loaded
* 1: Firmware is in application mode. CCS811 is ready to take ADC measurements
*/
#define CCS811_STATUS_FW_MODE_MASK BIT(7)
#define CCS811_STATUS_FW_MODE_APPLICATION BIT(7)
/* Measurement modes */
#define CCS811_MODE_IDLE 0x00
#define CCS811_MODE_IAQ_1SEC 0x10
#define CCS811_MODE_IAQ_10SEC 0x20
#define CCS811_MODE_IAQ_60SEC 0x30
#define CCS811_MODE_RAW_DATA 0x40
#define CCS811_MEAS_MODE_INTERRUPT BIT(3)
#define CCS811_VOLTAGE_MASK 0x3FF
struct ccs811_reading {
__be16 co2;
__be16 voc;
u8 status;
u8 error;
__be16 raw_data;
} __attribute__((__packed__));
struct ccs811_data {
struct i2c_client *client;
struct mutex lock; /* Protect readings */
struct ccs811_reading buffer;
struct iio_trigger *drdy_trig;
struct gpio_desc *wakeup_gpio;
bool drdy_trig_on;
/* Ensures correct alignment of timestamp if present */
struct {
s16 channels[2];
s64 ts __aligned(8);
} scan;
};
static const struct iio_chan_spec ccs811_channels[] = {
{
.type = IIO_CURRENT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.scan_index = -1,
}, {
.type = IIO_VOLTAGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.scan_index = -1,
}, {
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_CO2,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 0,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_BE,
},
}, {
.type = IIO_CONCENTRATION,
.channel2 = IIO_MOD_VOC,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 1,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_BE,
},
},
IIO_CHAN_SOFT_TIMESTAMP(2),
};
/*
* The CCS811 powers-up in boot mode. A setup write to CCS811_APP_START will
* transition the sensor to application mode.
*/
static int ccs811_start_sensor_application(struct i2c_client *client)
{
int ret;
ret = i2c_smbus_read_byte_data(client, CCS811_STATUS);
if (ret < 0)
return ret;
if ((ret & CCS811_STATUS_FW_MODE_APPLICATION))
return 0;
if ((ret & CCS811_STATUS_APP_VALID_MASK) !=
CCS811_STATUS_APP_VALID_LOADED)
return -EIO;
ret = i2c_smbus_write_byte(client, CCS811_APP_START);
if (ret < 0)
return ret;
ret = i2c_smbus_read_byte_data(client, CCS811_STATUS);
if (ret < 0)
return ret;
if ((ret & CCS811_STATUS_FW_MODE_MASK) !=
CCS811_STATUS_FW_MODE_APPLICATION) {
dev_err(&client->dev, "Application failed to start. Sensor is still in boot mode.\n");
return -EIO;
}
return 0;
}
static int ccs811_setup(struct i2c_client *client)
{
int ret;
ret = ccs811_start_sensor_application(client);
if (ret < 0)
return ret;
return i2c_smbus_write_byte_data(client, CCS811_MEAS_MODE,
CCS811_MODE_IAQ_1SEC);
}
static void ccs811_set_wakeup(struct ccs811_data *data, bool enable)
{
if (!data->wakeup_gpio)
return;
gpiod_set_value(data->wakeup_gpio, enable);
if (enable)
usleep_range(50, 60);
else
usleep_range(20, 30);
}
static int ccs811_get_measurement(struct ccs811_data *data)
{
int ret, tries = 11;
ccs811_set_wakeup(data, true);
/* Maximum waiting time: 1s, as measurements are made every second */
while (tries-- > 0) {
ret = i2c_smbus_read_byte_data(data->client, CCS811_STATUS);
if (ret < 0)
return ret;
if ((ret & CCS811_STATUS_DATA_READY) || tries == 0)
break;
msleep(100);
}
if (!(ret & CCS811_STATUS_DATA_READY))
return -EIO;
ret = i2c_smbus_read_i2c_block_data(data->client,
CCS811_ALG_RESULT_DATA, 8,
(char *)&data->buffer);
ccs811_set_wakeup(data, false);
return ret;
}
static int ccs811_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct ccs811_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
mutex_lock(&data->lock);
ret = ccs811_get_measurement(data);
if (ret < 0) {
mutex_unlock(&data->lock);
iio_device_release_direct_mode(indio_dev);
return ret;
}
switch (chan->type) {
case IIO_VOLTAGE:
*val = be16_to_cpu(data->buffer.raw_data) &
CCS811_VOLTAGE_MASK;
ret = IIO_VAL_INT;
break;
case IIO_CURRENT:
*val = be16_to_cpu(data->buffer.raw_data) >> 10;
ret = IIO_VAL_INT;
break;
case IIO_CONCENTRATION:
switch (chan->channel2) {
case IIO_MOD_CO2:
*val = be16_to_cpu(data->buffer.co2);
ret = IIO_VAL_INT;
break;
case IIO_MOD_VOC:
*val = be16_to_cpu(data->buffer.voc);
ret = IIO_VAL_INT;
break;
default:
ret = -EINVAL;
}
break;
default:
ret = -EINVAL;
}
mutex_unlock(&data->lock);
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_VOLTAGE:
*val = 1;
*val2 = 612903;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CURRENT:
*val = 0;
*val2 = 1000;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CONCENTRATION:
switch (chan->channel2) {
case IIO_MOD_CO2:
*val = 0;
*val2 = 100;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_MOD_VOC:
*val = 0;
*val2 = 100;
return IIO_VAL_INT_PLUS_NANO;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static const struct iio_info ccs811_info = {
.read_raw = ccs811_read_raw,
};
static int ccs811_set_trigger_state(struct iio_trigger *trig,
bool state)
{
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
struct ccs811_data *data = iio_priv(indio_dev);
int ret;
ret = i2c_smbus_read_byte_data(data->client, CCS811_MEAS_MODE);
if (ret < 0)
return ret;
if (state)
ret |= CCS811_MEAS_MODE_INTERRUPT;
else
ret &= ~CCS811_MEAS_MODE_INTERRUPT;
data->drdy_trig_on = state;
return i2c_smbus_write_byte_data(data->client, CCS811_MEAS_MODE, ret);
}
static const struct iio_trigger_ops ccs811_trigger_ops = {
.set_trigger_state = ccs811_set_trigger_state,
};
static irqreturn_t ccs811_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct ccs811_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
int ret;
ret = i2c_smbus_read_i2c_block_data(client, CCS811_ALG_RESULT_DATA,
sizeof(data->scan.channels),
(u8 *)data->scan.channels);
if (ret != 4) {
dev_err(&client->dev, "cannot read sensor data\n");
goto err;
}
iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
iio_get_time_ns(indio_dev));
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static irqreturn_t ccs811_data_rdy_trigger_poll(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct ccs811_data *data = iio_priv(indio_dev);
if (data->drdy_trig_on)
iio_trigger_poll(data->drdy_trig);
return IRQ_HANDLED;
}
static int ccs811_reset(struct i2c_client *client)
{
struct gpio_desc *reset_gpio;
int ret;
reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(reset_gpio))
return PTR_ERR(reset_gpio);
/* Try to reset using nRESET pin if available else do SW reset */
if (reset_gpio) {
gpiod_set_value(reset_gpio, 1);
usleep_range(20, 30);
gpiod_set_value(reset_gpio, 0);
} else {
/*
* As per the datasheet, this sequence of values needs to be
* written to the SW_RESET register for triggering the soft
* reset in the device and placing it in boot mode.
*/
static const u8 reset_seq[] = {
0x11, 0xE5, 0x72, 0x8A,
};
ret = i2c_smbus_write_i2c_block_data(client, CCS811_SW_RESET,
sizeof(reset_seq), reset_seq);
if (ret < 0) {
dev_err(&client->dev, "Failed to reset sensor\n");
return ret;
}
}
/* tSTART delay required after reset */
usleep_range(1000, 2000);
return 0;
}
static int ccs811_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct iio_dev *indio_dev;
struct ccs811_data *data;
int ret;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WRITE_BYTE
| I2C_FUNC_SMBUS_BYTE_DATA
| I2C_FUNC_SMBUS_READ_I2C_BLOCK))
return -EOPNOTSUPP;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->wakeup_gpio = devm_gpiod_get_optional(&client->dev, "wakeup",
GPIOD_OUT_HIGH);
if (IS_ERR(data->wakeup_gpio))
return PTR_ERR(data->wakeup_gpio);
ccs811_set_wakeup(data, true);
ret = ccs811_reset(client);
if (ret) {
ccs811_set_wakeup(data, false);
return ret;
}
/* Check hardware id (should be 0x81 for this family of devices) */
ret = i2c_smbus_read_byte_data(client, CCS811_HW_ID);
if (ret < 0) {
ccs811_set_wakeup(data, false);
return ret;
}
if (ret != CCS811_HW_ID_VALUE) {
dev_err(&client->dev, "hardware id doesn't match CCS81x\n");
ccs811_set_wakeup(data, false);
return -ENODEV;
}
ret = i2c_smbus_read_byte_data(client, CCS811_HW_VERSION);
if (ret < 0) {
ccs811_set_wakeup(data, false);
return ret;
}
if ((ret & CCS811_HW_VERSION_MASK) != CCS811_HW_VERSION_VALUE) {
dev_err(&client->dev, "no CCS811 sensor\n");
ccs811_set_wakeup(data, false);
return -ENODEV;
}
ret = ccs811_setup(client);
if (ret < 0) {
ccs811_set_wakeup(data, false);
return ret;
}
ccs811_set_wakeup(data, false);
mutex_init(&data->lock);
indio_dev->name = id->name;
indio_dev->info = &ccs811_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ccs811_channels;
indio_dev->num_channels = ARRAY_SIZE(ccs811_channels);
if (client->irq > 0) {
ret = devm_request_threaded_irq(&client->dev, client->irq,
ccs811_data_rdy_trigger_poll,
NULL,
IRQF_TRIGGER_FALLING |
IRQF_ONESHOT,
"ccs811_irq", indio_dev);
if (ret) {
dev_err(&client->dev, "irq request error %d\n", -ret);
goto err_poweroff;
}
data->drdy_trig = devm_iio_trigger_alloc(&client->dev,
"%s-dev%d",
indio_dev->name,
iio_device_id(indio_dev));
if (!data->drdy_trig) {
ret = -ENOMEM;
goto err_poweroff;
}
data->drdy_trig->ops = &ccs811_trigger_ops;
iio_trigger_set_drvdata(data->drdy_trig, indio_dev);
ret = iio_trigger_register(data->drdy_trig);
if (ret)
goto err_poweroff;
indio_dev->trig = iio_trigger_get(data->drdy_trig);
}
ret = iio_triggered_buffer_setup(indio_dev, NULL,
ccs811_trigger_handler, NULL);
if (ret < 0) {
dev_err(&client->dev, "triggered buffer setup failed\n");
goto err_trigger_unregister;
}
ret = iio_device_register(indio_dev);
if (ret < 0) {
dev_err(&client->dev, "unable to register iio device\n");
goto err_buffer_cleanup;
}
return 0;
err_buffer_cleanup:
iio_triggered_buffer_cleanup(indio_dev);
err_trigger_unregister:
if (data->drdy_trig)
iio_trigger_unregister(data->drdy_trig);
err_poweroff:
i2c_smbus_write_byte_data(client, CCS811_MEAS_MODE, CCS811_MODE_IDLE);
return ret;
}
static void ccs811_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct ccs811_data *data = iio_priv(indio_dev);
int ret;
iio_device_unregister(indio_dev);
iio_triggered_buffer_cleanup(indio_dev);
if (data->drdy_trig)
iio_trigger_unregister(data->drdy_trig);
ret = i2c_smbus_write_byte_data(client, CCS811_MEAS_MODE,
CCS811_MODE_IDLE);
if (ret)
dev_warn(&client->dev, "Failed to power down device (%pe)\n",
ERR_PTR(ret));
}
static const struct i2c_device_id ccs811_id[] = {
{"ccs811", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, ccs811_id);
static const struct of_device_id ccs811_dt_ids[] = {
{ .compatible = "ams,ccs811" },
{ }
};
MODULE_DEVICE_TABLE(of, ccs811_dt_ids);
static struct i2c_driver ccs811_driver = {
.driver = {
.name = "ccs811",
.of_match_table = ccs811_dt_ids,
},
.probe = ccs811_probe,
.remove = ccs811_remove,
.id_table = ccs811_id,
};
module_i2c_driver(ccs811_driver);
MODULE_AUTHOR("Narcisa Vasile <[email protected]>");
MODULE_DESCRIPTION("CCS811 volatile organic compounds sensor");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/chemical/ccs811.c |
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