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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Linaro Limited.
* Author: Caleb Connolly <[email protected]>
*
* This driver is for the Round Robin ADC found in the pmi8998 and pm660 PMICs.
*/
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/spmi.h>
#include <linux/types.h>
#include <linux/units.h>
#include <asm/unaligned.h>
#include <linux/iio/iio.h>
#include <linux/iio/types.h>
#include <soc/qcom/qcom-spmi-pmic.h>
#define DRIVER_NAME "qcom-spmi-rradc"
#define RR_ADC_EN_CTL 0x46
#define RR_ADC_SKIN_TEMP_LSB 0x50
#define RR_ADC_SKIN_TEMP_MSB 0x51
#define RR_ADC_CTL 0x52
#define RR_ADC_CTL_CONTINUOUS_SEL BIT(3)
#define RR_ADC_LOG 0x53
#define RR_ADC_LOG_CLR_CTRL BIT(0)
#define RR_ADC_FAKE_BATT_LOW_LSB 0x58
#define RR_ADC_FAKE_BATT_LOW_MSB 0x59
#define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A
#define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B
#define RR_ADC_BATT_ID_CTRL 0x60
#define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0)
#define RR_ADC_BATT_ID_TRIGGER 0x61
#define RR_ADC_BATT_ID_STS 0x62
#define RR_ADC_BATT_ID_CFG 0x63
#define BATT_ID_SETTLE_MASK GENMASK(7, 5)
#define RR_ADC_BATT_ID_5_LSB 0x66
#define RR_ADC_BATT_ID_5_MSB 0x67
#define RR_ADC_BATT_ID_15_LSB 0x68
#define RR_ADC_BATT_ID_15_MSB 0x69
#define RR_ADC_BATT_ID_150_LSB 0x6A
#define RR_ADC_BATT_ID_150_MSB 0x6B
#define RR_ADC_BATT_THERM_CTRL 0x70
#define RR_ADC_BATT_THERM_TRIGGER 0x71
#define RR_ADC_BATT_THERM_STS 0x72
#define RR_ADC_BATT_THERM_CFG 0x73
#define RR_ADC_BATT_THERM_LSB 0x74
#define RR_ADC_BATT_THERM_MSB 0x75
#define RR_ADC_BATT_THERM_FREQ 0x76
#define RR_ADC_AUX_THERM_CTRL 0x80
#define RR_ADC_AUX_THERM_TRIGGER 0x81
#define RR_ADC_AUX_THERM_STS 0x82
#define RR_ADC_AUX_THERM_CFG 0x83
#define RR_ADC_AUX_THERM_LSB 0x84
#define RR_ADC_AUX_THERM_MSB 0x85
#define RR_ADC_SKIN_HOT 0x86
#define RR_ADC_SKIN_TOO_HOT 0x87
#define RR_ADC_AUX_THERM_C1 0x88
#define RR_ADC_AUX_THERM_C2 0x89
#define RR_ADC_AUX_THERM_C3 0x8A
#define RR_ADC_AUX_THERM_HALF_RANGE 0x8B
#define RR_ADC_USB_IN_V_CTRL 0x90
#define RR_ADC_USB_IN_V_TRIGGER 0x91
#define RR_ADC_USB_IN_V_STS 0x92
#define RR_ADC_USB_IN_V_LSB 0x94
#define RR_ADC_USB_IN_V_MSB 0x95
#define RR_ADC_USB_IN_I_CTRL 0x98
#define RR_ADC_USB_IN_I_TRIGGER 0x99
#define RR_ADC_USB_IN_I_STS 0x9A
#define RR_ADC_USB_IN_I_LSB 0x9C
#define RR_ADC_USB_IN_I_MSB 0x9D
#define RR_ADC_DC_IN_V_CTRL 0xA0
#define RR_ADC_DC_IN_V_TRIGGER 0xA1
#define RR_ADC_DC_IN_V_STS 0xA2
#define RR_ADC_DC_IN_V_LSB 0xA4
#define RR_ADC_DC_IN_V_MSB 0xA5
#define RR_ADC_DC_IN_I_CTRL 0xA8
#define RR_ADC_DC_IN_I_TRIGGER 0xA9
#define RR_ADC_DC_IN_I_STS 0xAA
#define RR_ADC_DC_IN_I_LSB 0xAC
#define RR_ADC_DC_IN_I_MSB 0xAD
#define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0
#define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1
#define RR_ADC_PMI_DIE_TEMP_STS 0xB2
#define RR_ADC_PMI_DIE_TEMP_CFG 0xB3
#define RR_ADC_PMI_DIE_TEMP_LSB 0xB4
#define RR_ADC_PMI_DIE_TEMP_MSB 0xB5
#define RR_ADC_CHARGER_TEMP_CTRL 0xB8
#define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9
#define RR_ADC_CHARGER_TEMP_STS 0xBA
#define RR_ADC_CHARGER_TEMP_CFG 0xBB
#define RR_ADC_CHARGER_TEMP_LSB 0xBC
#define RR_ADC_CHARGER_TEMP_MSB 0xBD
#define RR_ADC_CHARGER_HOT 0xBE
#define RR_ADC_CHARGER_TOO_HOT 0xBF
#define RR_ADC_GPIO_CTRL 0xC0
#define RR_ADC_GPIO_TRIGGER 0xC1
#define RR_ADC_GPIO_STS 0xC2
#define RR_ADC_GPIO_LSB 0xC4
#define RR_ADC_GPIO_MSB 0xC5
#define RR_ADC_ATEST_CTRL 0xC8
#define RR_ADC_ATEST_TRIGGER 0xC9
#define RR_ADC_ATEST_STS 0xCA
#define RR_ADC_ATEST_LSB 0xCC
#define RR_ADC_ATEST_MSB 0xCD
#define RR_ADC_SEC_ACCESS 0xD0
#define RR_ADC_PERPH_RESET_CTL2 0xD9
#define RR_ADC_PERPH_RESET_CTL3 0xDA
#define RR_ADC_PERPH_RESET_CTL4 0xDB
#define RR_ADC_INT_TEST1 0xE0
#define RR_ADC_INT_TEST_VAL 0xE1
#define RR_ADC_TM_TRIGGER_CTRLS 0xE2
#define RR_ADC_TM_ADC_CTRLS 0xE3
#define RR_ADC_TM_CNL_CTRL 0xE4
#define RR_ADC_TM_BATT_ID_CTRL 0xE5
#define RR_ADC_TM_THERM_CTRL 0xE6
#define RR_ADC_TM_CONV_STS 0xE7
#define RR_ADC_TM_ADC_READ_LSB 0xE8
#define RR_ADC_TM_ADC_READ_MSB 0xE9
#define RR_ADC_TM_ATEST_MUX_1 0xEA
#define RR_ADC_TM_ATEST_MUX_2 0xEB
#define RR_ADC_TM_REFERENCES 0xED
#define RR_ADC_TM_MISC_CTL 0xEE
#define RR_ADC_TM_RR_CTRL 0xEF
#define RR_ADC_TRIGGER_EVERY_CYCLE BIT(7)
#define RR_ADC_TRIGGER_CTL BIT(0)
#define RR_ADC_BATT_ID_RANGE 820
#define RR_ADC_BITS 10
#define RR_ADC_CHAN_MSB (1 << RR_ADC_BITS)
#define RR_ADC_FS_VOLTAGE_MV 2500
/* BATT_THERM 0.25K/LSB */
#define RR_ADC_BATT_THERM_LSB_K 4
#define RR_ADC_TEMP_FS_VOLTAGE_NUM 5000000
#define RR_ADC_TEMP_FS_VOLTAGE_DEN 3
#define RR_ADC_DIE_TEMP_OFFSET 601400
#define RR_ADC_DIE_TEMP_SLOPE 2
#define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC 25000
#define RR_ADC_CHG_TEMP_GF_OFFSET_UV 1303168
#define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C 3784
#define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV 1338433
#define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655
#define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV 1309001
#define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C 3403
#define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV 1295898
#define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C 3596
#define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV 1314779
#define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C 3496
#define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC 25000
#define RR_ADC_CHG_THRESHOLD_SCALE 4
#define RR_ADC_VOLT_INPUT_FACTOR 8
#define RR_ADC_CURR_INPUT_FACTOR 2000
#define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL 1886
#define RR_ADC_CURR_USBIN_660_FACTOR_MIL 9
#define RR_ADC_CURR_USBIN_660_UV_VAL 579500
#define RR_ADC_GPIO_FS_RANGE 5000
#define RR_ADC_COHERENT_CHECK_RETRY 5
#define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN 16
#define RR_ADC_STS_CHANNEL_READING_MASK GENMASK(1, 0)
#define RR_ADC_STS_CHANNEL_STS BIT(1)
#define RR_ADC_TP_REV_VERSION1 21
#define RR_ADC_TP_REV_VERSION2 29
#define RR_ADC_TP_REV_VERSION3 32
#define RRADC_BATT_ID_DELAY_MAX 8
enum rradc_channel_id {
RR_ADC_BATT_ID = 0,
RR_ADC_BATT_THERM,
RR_ADC_SKIN_TEMP,
RR_ADC_USBIN_I,
RR_ADC_USBIN_V,
RR_ADC_DCIN_I,
RR_ADC_DCIN_V,
RR_ADC_DIE_TEMP,
RR_ADC_CHG_TEMP,
RR_ADC_GPIO,
RR_ADC_CHAN_MAX
};
struct rradc_chip;
/**
* struct rradc_channel - rradc channel data
* @label: channel label
* @lsb: Channel least significant byte
* @status: Channel status address
* @size: number of bytes to read
* @trigger_addr: Trigger address, trigger is only used on some channels
* @trigger_mask: Trigger mask
* @scale_fn: Post process callback for channels which can't be exposed
* as offset + scale.
*/
struct rradc_channel {
const char *label;
u8 lsb;
u8 status;
int size;
int trigger_addr;
int trigger_mask;
int (*scale_fn)(struct rradc_chip *chip, u16 adc_code, int *result);
};
struct rradc_chip {
struct device *dev;
const struct qcom_spmi_pmic *pmic;
/*
* Lock held while doing channel conversion
* involving multiple register read/writes
*/
struct mutex conversion_lock;
struct regmap *regmap;
u32 base;
int batt_id_delay;
u16 batt_id_data;
};
static const int batt_id_delays[] = { 0, 1, 4, 12, 20, 40, 60, 80 };
static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX];
static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX];
static int rradc_read(struct rradc_chip *chip, u16 addr, __le16 *buf, int len)
{
int ret, retry_cnt = 0;
__le16 data_check[RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN / 2];
if (len > RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN) {
dev_err(chip->dev,
"Can't read more than %d bytes, but asked to read %d bytes.\n",
RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN, len);
return -EINVAL;
}
while (retry_cnt < RR_ADC_COHERENT_CHECK_RETRY) {
ret = regmap_bulk_read(chip->regmap, chip->base + addr, buf,
len);
if (ret < 0) {
dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,
ret);
return ret;
}
ret = regmap_bulk_read(chip->regmap, chip->base + addr,
data_check, len);
if (ret < 0) {
dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,
ret);
return ret;
}
if (memcmp(buf, data_check, len) != 0) {
retry_cnt++;
dev_dbg(chip->dev,
"coherent read error, retry_cnt:%d\n",
retry_cnt);
continue;
}
break;
}
if (retry_cnt == RR_ADC_COHERENT_CHECK_RETRY)
dev_err(chip->dev, "Retry exceeded for coherency check\n");
return ret;
}
static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset,
int64_t *slope)
{
if (chip->pmic->subtype == PM660_SUBTYPE) {
switch (chip->pmic->fab_id) {
case PM660_FAB_ID_GF:
*offset = RR_ADC_CHG_TEMP_660_GF_OFFSET_UV;
*slope = RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C;
return 0;
case PM660_FAB_ID_TSMC:
*offset = RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV;
*slope = RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C;
return 0;
default:
*offset = RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV;
*slope = RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C;
}
} else if (chip->pmic->subtype == PMI8998_SUBTYPE) {
switch (chip->pmic->fab_id) {
case PMI8998_FAB_ID_GF:
*offset = RR_ADC_CHG_TEMP_GF_OFFSET_UV;
*slope = RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C;
return 0;
case PMI8998_FAB_ID_SMIC:
*offset = RR_ADC_CHG_TEMP_SMIC_OFFSET_UV;
*slope = RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C;
return 0;
default:
return -EINVAL;
}
}
return -EINVAL;
}
/*
* These functions explicitly cast int64_t to int.
* They will never overflow, as the values are small enough.
*/
static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_code,
int *result_ohms)
{
uint32_t current_value;
int64_t r_id;
current_value = chip->batt_id_data;
r_id = ((int64_t)adc_code * RR_ADC_FS_VOLTAGE_MV);
r_id = div64_s64(r_id, (RR_ADC_CHAN_MSB * current_value));
*result_ohms = (int)(r_id * MILLI);
return 0;
}
static int rradc_enable_continuous_mode(struct rradc_chip *chip)
{
int ret;
/* Clear channel log */
ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG,
RR_ADC_LOG_CLR_CTRL, RR_ADC_LOG_CLR_CTRL);
if (ret < 0) {
dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret);
return ret;
}
ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG,
RR_ADC_LOG_CLR_CTRL, 0);
if (ret < 0) {
dev_err(chip->dev, "log ctrl update to not clear failed:%d\n",
ret);
return ret;
}
/* Switch to continuous mode */
ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL,
RR_ADC_CTL_CONTINUOUS_SEL,
RR_ADC_CTL_CONTINUOUS_SEL);
if (ret < 0)
dev_err(chip->dev, "Update to continuous mode failed:%d\n",
ret);
return ret;
}
static int rradc_disable_continuous_mode(struct rradc_chip *chip)
{
int ret;
/* Switch to non continuous mode */
ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL,
RR_ADC_CTL_CONTINUOUS_SEL, 0);
if (ret < 0)
dev_err(chip->dev, "Update to non-continuous mode failed:%d\n",
ret);
return ret;
}
static bool rradc_is_ready(struct rradc_chip *chip,
enum rradc_channel_id chan_address)
{
const struct rradc_channel *chan = &rradc_chans[chan_address];
int ret;
unsigned int status, mask;
/* BATT_ID STS bit does not get set initially */
switch (chan_address) {
case RR_ADC_BATT_ID:
mask = RR_ADC_STS_CHANNEL_STS;
break;
default:
mask = RR_ADC_STS_CHANNEL_READING_MASK;
break;
}
ret = regmap_read(chip->regmap, chip->base + chan->status, &status);
if (ret < 0 || !(status & mask))
return false;
return true;
}
static int rradc_read_status_in_cont_mode(struct rradc_chip *chip,
enum rradc_channel_id chan_address)
{
const struct rradc_channel *chan = &rradc_chans[chan_address];
const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address];
int ret, i;
if (chan->trigger_mask == 0) {
dev_err(chip->dev, "Channel doesn't have a trigger mask\n");
return -EINVAL;
}
ret = regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr,
chan->trigger_mask, chan->trigger_mask);
if (ret < 0) {
dev_err(chip->dev,
"Failed to apply trigger for channel '%s' ret=%d\n",
iio_chan->extend_name, ret);
return ret;
}
ret = rradc_enable_continuous_mode(chip);
if (ret < 0) {
dev_err(chip->dev, "Failed to switch to continuous mode\n");
goto disable_trigger;
}
/*
* The wait/sleep values were found through trial and error,
* this is mostly for the battery ID channel which takes some
* time to settle.
*/
for (i = 0; i < 5; i++) {
if (rradc_is_ready(chip, chan_address))
break;
usleep_range(50000, 50000 + 500);
}
if (i == 5) {
dev_err(chip->dev, "Channel '%s' is not ready\n",
iio_chan->extend_name);
ret = -ETIMEDOUT;
}
rradc_disable_continuous_mode(chip);
disable_trigger:
regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr,
chan->trigger_mask, 0);
return ret;
}
static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip,
enum rradc_channel_id chan_address,
u16 *data)
{
int ret;
ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,
RR_ADC_BATT_ID_CTRL_CHANNEL_CONV,
RR_ADC_BATT_ID_CTRL_CHANNEL_CONV);
if (ret < 0) {
dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret);
return ret;
}
ret = regmap_update_bits(chip->regmap,
chip->base + RR_ADC_BATT_ID_TRIGGER,
RR_ADC_TRIGGER_CTL, RR_ADC_TRIGGER_CTL);
if (ret < 0) {
dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret);
goto out_disable_batt_id;
}
ret = rradc_read_status_in_cont_mode(chip, chan_address);
/* Reset registers back to default values */
regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER,
RR_ADC_TRIGGER_CTL, 0);
out_disable_batt_id:
regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,
RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, 0);
return ret;
}
static int rradc_do_conversion(struct rradc_chip *chip,
enum rradc_channel_id chan_address, u16 *data)
{
const struct rradc_channel *chan = &rradc_chans[chan_address];
const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address];
int ret;
__le16 buf[3];
mutex_lock(&chip->conversion_lock);
switch (chan_address) {
case RR_ADC_BATT_ID:
ret = rradc_prepare_batt_id_conversion(chip, chan_address, data);
if (ret < 0) {
dev_err(chip->dev, "Battery ID conversion failed:%d\n",
ret);
goto unlock_out;
}
break;
case RR_ADC_USBIN_V:
case RR_ADC_DIE_TEMP:
ret = rradc_read_status_in_cont_mode(chip, chan_address);
if (ret < 0) {
dev_err(chip->dev,
"Error reading in continuous mode:%d\n", ret);
goto unlock_out;
}
break;
default:
if (!rradc_is_ready(chip, chan_address)) {
/*
* Usually this means the channel isn't attached, for example
* the in_voltage_usbin_v_input channel will not be ready if
* no USB cable is attached
*/
dev_dbg(chip->dev, "channel '%s' is not ready\n",
iio_chan->extend_name);
ret = -ENODATA;
goto unlock_out;
}
break;
}
ret = rradc_read(chip, chan->lsb, buf, chan->size);
if (ret) {
dev_err(chip->dev, "read data failed\n");
goto unlock_out;
}
/*
* For the battery ID we read the register for every ID ADC and then
* see which one is actually connected.
*/
if (chan_address == RR_ADC_BATT_ID) {
u16 batt_id_150 = le16_to_cpu(buf[2]);
u16 batt_id_15 = le16_to_cpu(buf[1]);
u16 batt_id_5 = le16_to_cpu(buf[0]);
if (!batt_id_150 && !batt_id_15 && !batt_id_5) {
dev_err(chip->dev,
"Invalid batt_id values with all zeros\n");
ret = -EINVAL;
goto unlock_out;
}
if (batt_id_150 <= RR_ADC_BATT_ID_RANGE) {
*data = batt_id_150;
chip->batt_id_data = 150;
} else if (batt_id_15 <= RR_ADC_BATT_ID_RANGE) {
*data = batt_id_15;
chip->batt_id_data = 15;
} else {
*data = batt_id_5;
chip->batt_id_data = 5;
}
} else {
/*
* All of the other channels are either 1 or 2 bytes.
* We can rely on the second byte being 0 for 1-byte channels.
*/
*data = le16_to_cpu(buf[0]);
}
unlock_out:
mutex_unlock(&chip->conversion_lock);
return ret;
}
static int rradc_read_scale(struct rradc_chip *chip, int chan_address, int *val,
int *val2)
{
int64_t fab_offset, fab_slope;
int ret;
ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope);
if (ret < 0) {
dev_err(chip->dev, "Unable to get fab id coefficients\n");
return -EINVAL;
}
switch (chan_address) {
case RR_ADC_SKIN_TEMP:
*val = MILLI;
*val2 = RR_ADC_BATT_THERM_LSB_K;
return IIO_VAL_FRACTIONAL;
case RR_ADC_USBIN_I:
*val = RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL *
RR_ADC_FS_VOLTAGE_MV;
*val2 = RR_ADC_CHAN_MSB;
return IIO_VAL_FRACTIONAL;
case RR_ADC_DCIN_I:
*val = RR_ADC_CURR_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV;
*val2 = RR_ADC_CHAN_MSB;
return IIO_VAL_FRACTIONAL;
case RR_ADC_USBIN_V:
case RR_ADC_DCIN_V:
*val = RR_ADC_VOLT_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV * MILLI;
*val2 = RR_ADC_CHAN_MSB;
return IIO_VAL_FRACTIONAL;
case RR_ADC_GPIO:
*val = RR_ADC_GPIO_FS_RANGE;
*val2 = RR_ADC_CHAN_MSB;
return IIO_VAL_FRACTIONAL;
case RR_ADC_CHG_TEMP:
/*
* We divide val2 by MILLI instead of multiplying val
* to avoid an integer overflow.
*/
*val = -RR_ADC_TEMP_FS_VOLTAGE_NUM;
*val2 = div64_s64(RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
fab_slope,
MILLI);
return IIO_VAL_FRACTIONAL;
case RR_ADC_DIE_TEMP:
*val = RR_ADC_TEMP_FS_VOLTAGE_NUM;
*val2 = RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
RR_ADC_DIE_TEMP_SLOPE;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
}
static int rradc_read_offset(struct rradc_chip *chip, int chan_address, int *val)
{
int64_t fab_offset, fab_slope;
int64_t offset1, offset2;
int ret;
switch (chan_address) {
case RR_ADC_SKIN_TEMP:
/*
* Offset from kelvin to degC, divided by the
* scale factor (250). We lose some precision here.
* 273150 / 250 = 1092.6
*/
*val = div64_s64(ABSOLUTE_ZERO_MILLICELSIUS,
(MILLI / RR_ADC_BATT_THERM_LSB_K));
return IIO_VAL_INT;
case RR_ADC_CHG_TEMP:
ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope);
if (ret < 0) {
dev_err(chip->dev,
"Unable to get fab id coefficients\n");
return -EINVAL;
}
offset1 = -(fab_offset * RR_ADC_TEMP_FS_VOLTAGE_DEN *
RR_ADC_CHAN_MSB);
offset1 += (int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM / 2ULL;
offset1 = div64_s64(offset1,
(int64_t)(RR_ADC_TEMP_FS_VOLTAGE_NUM));
offset2 = (int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC *
RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
(int64_t)fab_slope;
offset2 += ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM) / 2;
offset2 = div64_s64(
offset2, ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM));
/*
* The -1 is to compensate for lost precision.
* It should actually be -0.7906976744186046.
* This works out to every value being off
* by about +0.091 degrees C after applying offset and scale.
*/
*val = (int)(offset1 - offset2 - 1);
return IIO_VAL_INT;
case RR_ADC_DIE_TEMP:
offset1 = -RR_ADC_DIE_TEMP_OFFSET *
(int64_t)RR_ADC_TEMP_FS_VOLTAGE_DEN *
(int64_t)RR_ADC_CHAN_MSB;
offset1 = div64_s64(offset1, RR_ADC_TEMP_FS_VOLTAGE_NUM);
offset2 = -(int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC *
RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
RR_ADC_DIE_TEMP_SLOPE;
offset2 = div64_s64(offset2,
((int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM));
/*
* The result is -339, it should be -338.69789, this results
* in the calculated die temp being off by
* -0.004 - -0.0175 degrees C
*/
*val = (int)(offset1 - offset2);
return IIO_VAL_INT;
default:
break;
}
return -EINVAL;
}
static int rradc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan_spec, int *val,
int *val2, long mask)
{
struct rradc_chip *chip = iio_priv(indio_dev);
const struct rradc_channel *chan;
int ret;
u16 adc_code;
if (chan_spec->address >= RR_ADC_CHAN_MAX) {
dev_err(chip->dev, "Invalid channel index:%lu\n",
chan_spec->address);
return -EINVAL;
}
switch (mask) {
case IIO_CHAN_INFO_SCALE:
return rradc_read_scale(chip, chan_spec->address, val, val2);
case IIO_CHAN_INFO_OFFSET:
return rradc_read_offset(chip, chan_spec->address, val);
case IIO_CHAN_INFO_RAW:
ret = rradc_do_conversion(chip, chan_spec->address, &adc_code);
if (ret < 0)
return ret;
*val = adc_code;
return IIO_VAL_INT;
case IIO_CHAN_INFO_PROCESSED:
chan = &rradc_chans[chan_spec->address];
if (!chan->scale_fn)
return -EINVAL;
ret = rradc_do_conversion(chip, chan_spec->address, &adc_code);
if (ret < 0)
return ret;
*val = chan->scale_fn(chip, adc_code, val);
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int rradc_read_label(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, char *label)
{
return snprintf(label, PAGE_SIZE, "%s\n",
rradc_chans[chan->address].label);
}
static const struct iio_info rradc_info = {
.read_raw = rradc_read_raw,
.read_label = rradc_read_label,
};
static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] = {
{
.label = "batt_id",
.scale_fn = rradc_post_process_batt_id,
.lsb = RR_ADC_BATT_ID_5_LSB,
.status = RR_ADC_BATT_ID_STS,
.size = 6,
.trigger_addr = RR_ADC_BATT_ID_TRIGGER,
.trigger_mask = BIT(0),
}, {
.label = "batt",
.lsb = RR_ADC_BATT_THERM_LSB,
.status = RR_ADC_BATT_THERM_STS,
.size = 2,
.trigger_addr = RR_ADC_BATT_THERM_TRIGGER,
}, {
.label = "pmi8998_skin",
.lsb = RR_ADC_SKIN_TEMP_LSB,
.status = RR_ADC_AUX_THERM_STS,
.size = 2,
.trigger_addr = RR_ADC_AUX_THERM_TRIGGER,
}, {
.label = "usbin_i",
.lsb = RR_ADC_USB_IN_I_LSB,
.status = RR_ADC_USB_IN_I_STS,
.size = 2,
.trigger_addr = RR_ADC_USB_IN_I_TRIGGER,
}, {
.label = "usbin_v",
.lsb = RR_ADC_USB_IN_V_LSB,
.status = RR_ADC_USB_IN_V_STS,
.size = 2,
.trigger_addr = RR_ADC_USB_IN_V_TRIGGER,
.trigger_mask = BIT(7),
}, {
.label = "dcin_i",
.lsb = RR_ADC_DC_IN_I_LSB,
.status = RR_ADC_DC_IN_I_STS,
.size = 2,
.trigger_addr = RR_ADC_DC_IN_I_TRIGGER,
}, {
.label = "dcin_v",
.lsb = RR_ADC_DC_IN_V_LSB,
.status = RR_ADC_DC_IN_V_STS,
.size = 2,
.trigger_addr = RR_ADC_DC_IN_V_TRIGGER,
}, {
.label = "pmi8998_die",
.lsb = RR_ADC_PMI_DIE_TEMP_LSB,
.status = RR_ADC_PMI_DIE_TEMP_STS,
.size = 2,
.trigger_addr = RR_ADC_PMI_DIE_TEMP_TRIGGER,
.trigger_mask = RR_ADC_TRIGGER_EVERY_CYCLE,
}, {
.label = "chg",
.lsb = RR_ADC_CHARGER_TEMP_LSB,
.status = RR_ADC_CHARGER_TEMP_STS,
.size = 2,
.trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER,
}, {
.label = "gpio",
.lsb = RR_ADC_GPIO_LSB,
.status = RR_ADC_GPIO_STS,
.size = 2,
.trigger_addr = RR_ADC_GPIO_TRIGGER,
},
};
static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] = {
{
.type = IIO_RESISTANCE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.address = RR_ADC_BATT_ID,
.channel = 0,
.indexed = 1,
}, {
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.address = RR_ADC_BATT_THERM,
.channel = 0,
.indexed = 1,
}, {
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET),
.address = RR_ADC_SKIN_TEMP,
.channel = 1,
.indexed = 1,
}, {
.type = IIO_CURRENT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.address = RR_ADC_USBIN_I,
.channel = 0,
.indexed = 1,
}, {
.type = IIO_VOLTAGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.address = RR_ADC_USBIN_V,
.channel = 0,
.indexed = 1,
}, {
.type = IIO_CURRENT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.address = RR_ADC_DCIN_I,
.channel = 1,
.indexed = 1,
}, {
.type = IIO_VOLTAGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.address = RR_ADC_DCIN_V,
.channel = 1,
.indexed = 1,
}, {
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET),
.address = RR_ADC_DIE_TEMP,
.channel = 2,
.indexed = 1,
}, {
.type = IIO_TEMP,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE),
.address = RR_ADC_CHG_TEMP,
.channel = 3,
.indexed = 1,
}, {
.type = IIO_VOLTAGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_SCALE),
.address = RR_ADC_GPIO,
.channel = 2,
.indexed = 1,
},
};
static int rradc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct iio_dev *indio_dev;
struct rradc_chip *chip;
int ret, i, batt_id_delay;
indio_dev = devm_iio_device_alloc(dev, sizeof(*chip));
if (!indio_dev)
return -ENOMEM;
chip = iio_priv(indio_dev);
chip->regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!chip->regmap) {
dev_err(dev, "Couldn't get parent's regmap\n");
return -EINVAL;
}
chip->dev = dev;
mutex_init(&chip->conversion_lock);
ret = device_property_read_u32(dev, "reg", &chip->base);
if (ret < 0) {
dev_err(chip->dev, "Couldn't find reg address, ret = %d\n",
ret);
return ret;
}
batt_id_delay = -1;
ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms",
&batt_id_delay);
if (!ret) {
for (i = 0; i < RRADC_BATT_ID_DELAY_MAX; i++) {
if (batt_id_delay == batt_id_delays[i])
break;
}
if (i == RRADC_BATT_ID_DELAY_MAX)
batt_id_delay = -1;
}
if (batt_id_delay >= 0) {
batt_id_delay = FIELD_PREP(BATT_ID_SETTLE_MASK, batt_id_delay);
ret = regmap_update_bits(chip->regmap,
chip->base + RR_ADC_BATT_ID_CFG,
batt_id_delay, batt_id_delay);
if (ret < 0) {
dev_err(chip->dev,
"BATT_ID settling time config failed:%d\n",
ret);
}
}
/* Get the PMIC revision, we need it to handle some varying coefficients */
chip->pmic = qcom_pmic_get(chip->dev);
if (IS_ERR(chip->pmic)) {
dev_err(chip->dev, "Unable to get reference to PMIC device\n");
return PTR_ERR(chip->pmic);
}
switch (chip->pmic->subtype) {
case PMI8998_SUBTYPE:
indio_dev->name = "pmi8998-rradc";
break;
case PM660_SUBTYPE:
indio_dev->name = "pm660-rradc";
break;
default:
indio_dev->name = DRIVER_NAME;
break;
}
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &rradc_info;
indio_dev->channels = rradc_iio_chans;
indio_dev->num_channels = ARRAY_SIZE(rradc_iio_chans);
return devm_iio_device_register(dev, indio_dev);
}
static const struct of_device_id rradc_match_table[] = {
{ .compatible = "qcom,pm660-rradc" },
{ .compatible = "qcom,pmi8998-rradc" },
{}
};
MODULE_DEVICE_TABLE(of, rradc_match_table);
static struct platform_driver rradc_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = rradc_match_table,
},
.probe = rradc_probe,
};
module_platform_driver(rradc_driver);
MODULE_DESCRIPTION("QCOM SPMI PMIC RR ADC driver");
MODULE_AUTHOR("Caleb Connolly <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/adc/qcom-spmi-rradc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices AD7466/7/8 AD7476/5/7/8 (A) SPI ADC driver
* TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
*
* Copyright 2010 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
struct ad7476_state;
struct ad7476_chip_info {
unsigned int int_vref_uv;
struct iio_chan_spec channel[2];
/* channels used when convst gpio is defined */
struct iio_chan_spec convst_channel[2];
void (*reset)(struct ad7476_state *);
bool has_vref;
bool has_vdrive;
};
struct ad7476_state {
struct spi_device *spi;
const struct ad7476_chip_info *chip_info;
struct regulator *ref_reg;
struct gpio_desc *convst_gpio;
struct spi_transfer xfer;
struct spi_message msg;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
* Make the buffer large enough for one 16 bit sample and one 64 bit
* aligned 64 bit timestamp.
*/
unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN);
};
enum ad7476_supported_device_ids {
ID_AD7091,
ID_AD7091R,
ID_AD7273,
ID_AD7274,
ID_AD7276,
ID_AD7277,
ID_AD7278,
ID_AD7466,
ID_AD7467,
ID_AD7468,
ID_AD7475,
ID_AD7495,
ID_AD7940,
ID_ADC081S,
ID_ADC101S,
ID_ADC121S,
ID_ADS7866,
ID_ADS7867,
ID_ADS7868,
ID_LTC2314_14,
};
static void ad7091_convst(struct ad7476_state *st)
{
if (!st->convst_gpio)
return;
gpiod_set_value(st->convst_gpio, 0);
udelay(1); /* CONVST pulse width: 10 ns min */
gpiod_set_value(st->convst_gpio, 1);
udelay(1); /* Conversion time: 650 ns max */
}
static irqreturn_t ad7476_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct ad7476_state *st = iio_priv(indio_dev);
int b_sent;
ad7091_convst(st);
b_sent = spi_sync(st->spi, &st->msg);
if (b_sent < 0)
goto done;
iio_push_to_buffers_with_timestamp(indio_dev, st->data,
iio_get_time_ns(indio_dev));
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static void ad7091_reset(struct ad7476_state *st)
{
/* Any transfers with 8 scl cycles will reset the device */
spi_read(st->spi, st->data, 1);
}
static int ad7476_scan_direct(struct ad7476_state *st)
{
int ret;
ad7091_convst(st);
ret = spi_sync(st->spi, &st->msg);
if (ret)
return ret;
return be16_to_cpup((__be16 *)st->data);
}
static int ad7476_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
int ret;
struct ad7476_state *st = iio_priv(indio_dev);
int scale_uv;
switch (m) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = ad7476_scan_direct(st);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = (ret >> st->chip_info->channel[0].scan_type.shift) &
GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
if (st->ref_reg) {
scale_uv = regulator_get_voltage(st->ref_reg);
if (scale_uv < 0)
return scale_uv;
} else {
scale_uv = st->chip_info->int_vref_uv;
}
*val = scale_uv / 1000;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
#define _AD7476_CHAN(bits, _shift, _info_mask_sep) \
{ \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.info_mask_separate = _info_mask_sep, \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.scan_type = { \
.sign = 'u', \
.realbits = (bits), \
.storagebits = 16, \
.shift = (_shift), \
.endianness = IIO_BE, \
}, \
}
#define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
BIT(IIO_CHAN_INFO_RAW))
#define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \
BIT(IIO_CHAN_INFO_RAW))
#define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \
BIT(IIO_CHAN_INFO_RAW))
#define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0)
#define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \
BIT(IIO_CHAN_INFO_RAW))
#define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
BIT(IIO_CHAN_INFO_RAW))
static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
[ID_AD7091] = {
.channel[0] = AD7091R_CHAN(12),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
.convst_channel[0] = AD7091R_CONVST_CHAN(12),
.convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
.reset = ad7091_reset,
},
[ID_AD7091R] = {
.channel[0] = AD7091R_CHAN(12),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
.convst_channel[0] = AD7091R_CONVST_CHAN(12),
.convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
.int_vref_uv = 2500000,
.has_vref = true,
.reset = ad7091_reset,
},
[ID_AD7273] = {
.channel[0] = AD7940_CHAN(10),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
.has_vref = true,
},
[ID_AD7274] = {
.channel[0] = AD7940_CHAN(12),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
.has_vref = true,
},
[ID_AD7276] = {
.channel[0] = AD7940_CHAN(12),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7277] = {
.channel[0] = AD7940_CHAN(10),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7278] = {
.channel[0] = AD7940_CHAN(8),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7466] = {
.channel[0] = AD7476_CHAN(12),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7467] = {
.channel[0] = AD7476_CHAN(10),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7468] = {
.channel[0] = AD7476_CHAN(8),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7475] = {
.channel[0] = AD7476_CHAN(12),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
.has_vref = true,
.has_vdrive = true,
},
[ID_AD7495] = {
.channel[0] = AD7476_CHAN(12),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
.int_vref_uv = 2500000,
.has_vdrive = true,
},
[ID_AD7940] = {
.channel[0] = AD7940_CHAN(14),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_ADC081S] = {
.channel[0] = ADC081S_CHAN(8),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_ADC101S] = {
.channel[0] = ADC081S_CHAN(10),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_ADC121S] = {
.channel[0] = ADC081S_CHAN(12),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_ADS7866] = {
.channel[0] = ADS786X_CHAN(12),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_ADS7867] = {
.channel[0] = ADS786X_CHAN(10),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_ADS7868] = {
.channel[0] = ADS786X_CHAN(8),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_LTC2314_14] = {
.channel[0] = AD7940_CHAN(14),
.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
.has_vref = true,
},
};
static const struct iio_info ad7476_info = {
.read_raw = &ad7476_read_raw,
};
static void ad7476_reg_disable(void *data)
{
struct regulator *reg = data;
regulator_disable(reg);
}
static int ad7476_probe(struct spi_device *spi)
{
struct ad7476_state *st;
struct iio_dev *indio_dev;
struct regulator *reg;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->chip_info =
&ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data];
reg = devm_regulator_get(&spi->dev, "vcc");
if (IS_ERR(reg))
return PTR_ERR(reg);
ret = regulator_enable(reg);
if (ret)
return ret;
ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable, reg);
if (ret)
return ret;
/* Either vcc or vref (below) as appropriate */
if (!st->chip_info->int_vref_uv)
st->ref_reg = reg;
if (st->chip_info->has_vref) {
/* If a device has an internal reference vref is optional */
if (st->chip_info->int_vref_uv) {
reg = devm_regulator_get_optional(&spi->dev, "vref");
if (IS_ERR(reg) && (PTR_ERR(reg) != -ENODEV))
return PTR_ERR(reg);
} else {
reg = devm_regulator_get(&spi->dev, "vref");
if (IS_ERR(reg))
return PTR_ERR(reg);
}
if (!IS_ERR(reg)) {
ret = regulator_enable(reg);
if (ret)
return ret;
ret = devm_add_action_or_reset(&spi->dev,
ad7476_reg_disable,
reg);
if (ret)
return ret;
st->ref_reg = reg;
} else {
/*
* Can only get here if device supports both internal
* and external reference, but the regulator connected
* to the external reference is not connected.
* Set the reference regulator pointer to NULL to
* indicate this.
*/
st->ref_reg = NULL;
}
}
if (st->chip_info->has_vdrive) {
ret = devm_regulator_get_enable(&spi->dev, "vdrive");
if (ret)
return ret;
}
st->convst_gpio = devm_gpiod_get_optional(&spi->dev,
"adi,conversion-start",
GPIOD_OUT_LOW);
if (IS_ERR(st->convst_gpio))
return PTR_ERR(st->convst_gpio);
st->spi = spi;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = st->chip_info->channel;
indio_dev->num_channels = 2;
indio_dev->info = &ad7476_info;
if (st->convst_gpio)
indio_dev->channels = st->chip_info->convst_channel;
/* Setup default message */
st->xfer.rx_buf = &st->data;
st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8;
spi_message_init(&st->msg);
spi_message_add_tail(&st->xfer, &st->msg);
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
&ad7476_trigger_handler, NULL);
if (ret)
return ret;
if (st->chip_info->reset)
st->chip_info->reset(st);
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id ad7476_id[] = {
{"ad7091", ID_AD7091},
{"ad7091r", ID_AD7091R},
{"ad7273", ID_AD7273},
{"ad7274", ID_AD7274},
{"ad7276", ID_AD7276},
{"ad7277", ID_AD7277},
{"ad7278", ID_AD7278},
{"ad7466", ID_AD7466},
{"ad7467", ID_AD7467},
{"ad7468", ID_AD7468},
{"ad7475", ID_AD7475},
{"ad7476", ID_AD7466},
{"ad7476a", ID_AD7466},
{"ad7477", ID_AD7467},
{"ad7477a", ID_AD7467},
{"ad7478", ID_AD7468},
{"ad7478a", ID_AD7468},
{"ad7495", ID_AD7495},
{"ad7910", ID_AD7467},
{"ad7920", ID_AD7466},
{"ad7940", ID_AD7940},
{"adc081s", ID_ADC081S},
{"adc101s", ID_ADC101S},
{"adc121s", ID_ADC121S},
{"ads7866", ID_ADS7866},
{"ads7867", ID_ADS7867},
{"ads7868", ID_ADS7868},
{"ltc2314-14", ID_LTC2314_14},
{}
};
MODULE_DEVICE_TABLE(spi, ad7476_id);
static struct spi_driver ad7476_driver = {
.driver = {
.name = "ad7476",
},
.probe = ad7476_probe,
.id_table = ad7476_id,
};
module_spi_driver(ad7476_driver);
MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ad7476.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Arun R Murthy <[email protected]>
* Author: Daniel Willerud <[email protected]>
* Author: Johan Palsson <[email protected]>
* Author: M'boumba Cedric Madianga
* Author: Linus Walleij <[email protected]>
*
* AB8500 General Purpose ADC driver. The AB8500 uses reference voltages:
* VinVADC, and VADC relative to GND to do its job. It monitors main and backup
* battery voltages, AC (mains) voltage, USB cable voltage, as well as voltages
* representing the temperature of the chip die and battery, accessory
* detection by resistance measurements using relative voltages and GSM burst
* information.
*
* Some of the voltages are measured on external pins on the IC, such as
* battery temperature or "ADC aux" 1 and 2. Other voltages are internal rails
* from other parts of the ASIC such as main charger voltage, main and battery
* backup voltage or USB VBUS voltage. For this reason drivers for other
* parts of the system are required to obtain handles to the ADC to do work
* for them and the IIO driver provides arbitration among these consumers.
*/
#include <linux/init.h>
#include <linux/bits.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/completion.h>
#include <linux/regulator/consumer.h>
#include <linux/random.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/mfd/abx500.h>
#include <linux/mfd/abx500/ab8500.h>
/* GPADC register offsets and bit definitions */
#define AB8500_GPADC_CTRL1_REG 0x00
/* GPADC control register 1 bits */
#define AB8500_GPADC_CTRL1_DISABLE 0x00
#define AB8500_GPADC_CTRL1_ENABLE BIT(0)
#define AB8500_GPADC_CTRL1_TRIG_ENA BIT(1)
#define AB8500_GPADC_CTRL1_START_SW_CONV BIT(2)
#define AB8500_GPADC_CTRL1_BTEMP_PULL_UP BIT(3)
/* 0 = use rising edge, 1 = use falling edge */
#define AB8500_GPADC_CTRL1_TRIG_EDGE BIT(4)
/* 0 = use VTVOUT, 1 = use VRTC as pull-up supply for battery temp NTC */
#define AB8500_GPADC_CTRL1_PUPSUPSEL BIT(5)
#define AB8500_GPADC_CTRL1_BUF_ENA BIT(6)
#define AB8500_GPADC_CTRL1_ICHAR_ENA BIT(7)
#define AB8500_GPADC_CTRL2_REG 0x01
#define AB8500_GPADC_CTRL3_REG 0x02
/*
* GPADC control register 2 and 3 bits
* the bit layout is the same for SW and HW conversion set-up
*/
#define AB8500_GPADC_CTRL2_AVG_1 0x00
#define AB8500_GPADC_CTRL2_AVG_4 BIT(5)
#define AB8500_GPADC_CTRL2_AVG_8 BIT(6)
#define AB8500_GPADC_CTRL2_AVG_16 (BIT(5) | BIT(6))
enum ab8500_gpadc_channel {
AB8500_GPADC_CHAN_UNUSED = 0x00,
AB8500_GPADC_CHAN_BAT_CTRL = 0x01,
AB8500_GPADC_CHAN_BAT_TEMP = 0x02,
/* This is not used on AB8505 */
AB8500_GPADC_CHAN_MAIN_CHARGER = 0x03,
AB8500_GPADC_CHAN_ACC_DET_1 = 0x04,
AB8500_GPADC_CHAN_ACC_DET_2 = 0x05,
AB8500_GPADC_CHAN_ADC_AUX_1 = 0x06,
AB8500_GPADC_CHAN_ADC_AUX_2 = 0x07,
AB8500_GPADC_CHAN_VBAT_A = 0x08,
AB8500_GPADC_CHAN_VBUS = 0x09,
AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT = 0x0a,
AB8500_GPADC_CHAN_USB_CHARGER_CURRENT = 0x0b,
AB8500_GPADC_CHAN_BACKUP_BAT = 0x0c,
/* Only on AB8505 */
AB8505_GPADC_CHAN_DIE_TEMP = 0x0d,
AB8500_GPADC_CHAN_ID = 0x0e,
AB8500_GPADC_CHAN_INTERNAL_TEST_1 = 0x0f,
AB8500_GPADC_CHAN_INTERNAL_TEST_2 = 0x10,
AB8500_GPADC_CHAN_INTERNAL_TEST_3 = 0x11,
/* FIXME: Applicable to all ASIC variants? */
AB8500_GPADC_CHAN_XTAL_TEMP = 0x12,
AB8500_GPADC_CHAN_VBAT_TRUE_MEAS = 0x13,
/* FIXME: Doesn't seem to work with pure AB8500 */
AB8500_GPADC_CHAN_BAT_CTRL_AND_IBAT = 0x1c,
AB8500_GPADC_CHAN_VBAT_MEAS_AND_IBAT = 0x1d,
AB8500_GPADC_CHAN_VBAT_TRUE_MEAS_AND_IBAT = 0x1e,
AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT = 0x1f,
/*
* Virtual channel used only for ibat conversion to ampere.
* Battery current conversion (ibat) cannot be requested as a
* single conversion but it is always requested in combination
* with other input requests.
*/
AB8500_GPADC_CHAN_IBAT_VIRTUAL = 0xFF,
};
#define AB8500_GPADC_AUTO_TIMER_REG 0x03
#define AB8500_GPADC_STAT_REG 0x04
#define AB8500_GPADC_STAT_BUSY BIT(0)
#define AB8500_GPADC_MANDATAL_REG 0x05
#define AB8500_GPADC_MANDATAH_REG 0x06
#define AB8500_GPADC_AUTODATAL_REG 0x07
#define AB8500_GPADC_AUTODATAH_REG 0x08
#define AB8500_GPADC_MUX_CTRL_REG 0x09
#define AB8540_GPADC_MANDATA2L_REG 0x09
#define AB8540_GPADC_MANDATA2H_REG 0x0A
#define AB8540_GPADC_APEAAX_REG 0x10
#define AB8540_GPADC_APEAAT_REG 0x11
#define AB8540_GPADC_APEAAM_REG 0x12
#define AB8540_GPADC_APEAAH_REG 0x13
#define AB8540_GPADC_APEAAL_REG 0x14
/*
* OTP register offsets
* Bank : 0x15
*/
#define AB8500_GPADC_CAL_1 0x0F
#define AB8500_GPADC_CAL_2 0x10
#define AB8500_GPADC_CAL_3 0x11
#define AB8500_GPADC_CAL_4 0x12
#define AB8500_GPADC_CAL_5 0x13
#define AB8500_GPADC_CAL_6 0x14
#define AB8500_GPADC_CAL_7 0x15
/* New calibration for 8540 */
#define AB8540_GPADC_OTP4_REG_7 0x38
#define AB8540_GPADC_OTP4_REG_6 0x39
#define AB8540_GPADC_OTP4_REG_5 0x3A
#define AB8540_GPADC_DIS_ZERO 0x00
#define AB8540_GPADC_EN_VBIAS_XTAL_TEMP 0x02
/* GPADC constants from AB8500 spec, UM0836 */
#define AB8500_ADC_RESOLUTION 1024
#define AB8500_ADC_CH_BTEMP_MIN 0
#define AB8500_ADC_CH_BTEMP_MAX 1350
#define AB8500_ADC_CH_DIETEMP_MIN 0
#define AB8500_ADC_CH_DIETEMP_MAX 1350
#define AB8500_ADC_CH_CHG_V_MIN 0
#define AB8500_ADC_CH_CHG_V_MAX 20030
#define AB8500_ADC_CH_ACCDET2_MIN 0
#define AB8500_ADC_CH_ACCDET2_MAX 2500
#define AB8500_ADC_CH_VBAT_MIN 2300
#define AB8500_ADC_CH_VBAT_MAX 4800
#define AB8500_ADC_CH_CHG_I_MIN 0
#define AB8500_ADC_CH_CHG_I_MAX 1500
#define AB8500_ADC_CH_BKBAT_MIN 0
#define AB8500_ADC_CH_BKBAT_MAX 3200
/* GPADC constants from AB8540 spec */
#define AB8500_ADC_CH_IBAT_MIN (-6000) /* mA range measured by ADC for ibat */
#define AB8500_ADC_CH_IBAT_MAX 6000
#define AB8500_ADC_CH_IBAT_MIN_V (-60) /* mV range measured by ADC for ibat */
#define AB8500_ADC_CH_IBAT_MAX_V 60
#define AB8500_GPADC_IBAT_VDROP_L (-56) /* mV */
#define AB8500_GPADC_IBAT_VDROP_H 56
/* This is used to not lose precision when dividing to get gain and offset */
#define AB8500_GPADC_CALIB_SCALE 1000
/*
* Number of bits shift used to not lose precision
* when dividing to get ibat gain.
*/
#define AB8500_GPADC_CALIB_SHIFT_IBAT 20
/* Time in ms before disabling regulator */
#define AB8500_GPADC_AUTOSUSPEND_DELAY 1
#define AB8500_GPADC_CONVERSION_TIME 500 /* ms */
enum ab8500_cal_channels {
AB8500_CAL_VMAIN = 0,
AB8500_CAL_BTEMP,
AB8500_CAL_VBAT,
AB8500_CAL_IBAT,
AB8500_CAL_NR,
};
/**
* struct ab8500_adc_cal_data - Table for storing gain and offset for the
* calibrated ADC channels
* @gain: Gain of the ADC channel
* @offset: Offset of the ADC channel
* @otp_calib_hi: Calibration from OTP
* @otp_calib_lo: Calibration from OTP
*/
struct ab8500_adc_cal_data {
s64 gain;
s64 offset;
u16 otp_calib_hi;
u16 otp_calib_lo;
};
/**
* struct ab8500_gpadc_chan_info - per-channel GPADC info
* @name: name of the channel
* @id: the internal AB8500 ID number for the channel
* @hardware_control: indicate that we want to use hardware ADC control
* on this channel, the default is software ADC control. Hardware control
* is normally only used to test the battery voltage during GSM bursts
* and needs a hardware trigger on the GPADCTrig pin of the ASIC.
* @falling_edge: indicate that we want to trigger on falling edge
* rather than rising edge, rising edge is the default
* @avg_sample: how many samples to average: must be 1, 4, 8 or 16.
* @trig_timer: how long to wait for the trigger, in 32kHz periods:
* 0 .. 255 periods
*/
struct ab8500_gpadc_chan_info {
const char *name;
u8 id;
bool hardware_control;
bool falling_edge;
u8 avg_sample;
u8 trig_timer;
};
/**
* struct ab8500_gpadc - AB8500 GPADC device information
* @dev: pointer to the containing device
* @ab8500: pointer to the parent AB8500 device
* @chans: internal per-channel information container
* @nchans: number of channels
* @complete: pointer to the completion that indicates
* the completion of an gpadc conversion cycle
* @vddadc: pointer to the regulator supplying VDDADC
* @irq_sw: interrupt number that is used by gpadc for software ADC conversion
* @irq_hw: interrupt number that is used by gpadc for hardware ADC conversion
* @cal_data: array of ADC calibration data structs
*/
struct ab8500_gpadc {
struct device *dev;
struct ab8500 *ab8500;
struct ab8500_gpadc_chan_info *chans;
unsigned int nchans;
struct completion complete;
struct regulator *vddadc;
int irq_sw;
int irq_hw;
struct ab8500_adc_cal_data cal_data[AB8500_CAL_NR];
};
static struct ab8500_gpadc_chan_info *
ab8500_gpadc_get_channel(struct ab8500_gpadc *gpadc, u8 chan)
{
struct ab8500_gpadc_chan_info *ch;
int i;
for (i = 0; i < gpadc->nchans; i++) {
ch = &gpadc->chans[i];
if (ch->id == chan)
break;
}
if (i == gpadc->nchans)
return NULL;
return ch;
}
/**
* ab8500_gpadc_ad_to_voltage() - Convert a raw ADC value to a voltage
* @gpadc: GPADC instance
* @ch: the sampled channel this raw value is coming from
* @ad_value: the raw value
*/
static int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc,
enum ab8500_gpadc_channel ch,
int ad_value)
{
int res;
switch (ch) {
case AB8500_GPADC_CHAN_MAIN_CHARGER:
/* No calibration data available: just interpolate */
if (!gpadc->cal_data[AB8500_CAL_VMAIN].gain) {
res = AB8500_ADC_CH_CHG_V_MIN + (AB8500_ADC_CH_CHG_V_MAX -
AB8500_ADC_CH_CHG_V_MIN) * ad_value /
AB8500_ADC_RESOLUTION;
break;
}
/* Here we can use calibration */
res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_VMAIN].gain +
gpadc->cal_data[AB8500_CAL_VMAIN].offset) / AB8500_GPADC_CALIB_SCALE;
break;
case AB8500_GPADC_CHAN_BAT_CTRL:
case AB8500_GPADC_CHAN_BAT_TEMP:
case AB8500_GPADC_CHAN_ACC_DET_1:
case AB8500_GPADC_CHAN_ADC_AUX_1:
case AB8500_GPADC_CHAN_ADC_AUX_2:
case AB8500_GPADC_CHAN_XTAL_TEMP:
/* No calibration data available: just interpolate */
if (!gpadc->cal_data[AB8500_CAL_BTEMP].gain) {
res = AB8500_ADC_CH_BTEMP_MIN + (AB8500_ADC_CH_BTEMP_MAX -
AB8500_ADC_CH_BTEMP_MIN) * ad_value /
AB8500_ADC_RESOLUTION;
break;
}
/* Here we can use calibration */
res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_BTEMP].gain +
gpadc->cal_data[AB8500_CAL_BTEMP].offset) / AB8500_GPADC_CALIB_SCALE;
break;
case AB8500_GPADC_CHAN_VBAT_A:
case AB8500_GPADC_CHAN_VBAT_TRUE_MEAS:
/* No calibration data available: just interpolate */
if (!gpadc->cal_data[AB8500_CAL_VBAT].gain) {
res = AB8500_ADC_CH_VBAT_MIN + (AB8500_ADC_CH_VBAT_MAX -
AB8500_ADC_CH_VBAT_MIN) * ad_value /
AB8500_ADC_RESOLUTION;
break;
}
/* Here we can use calibration */
res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_VBAT].gain +
gpadc->cal_data[AB8500_CAL_VBAT].offset) / AB8500_GPADC_CALIB_SCALE;
break;
case AB8505_GPADC_CHAN_DIE_TEMP:
res = AB8500_ADC_CH_DIETEMP_MIN +
(AB8500_ADC_CH_DIETEMP_MAX - AB8500_ADC_CH_DIETEMP_MIN) * ad_value /
AB8500_ADC_RESOLUTION;
break;
case AB8500_GPADC_CHAN_ACC_DET_2:
res = AB8500_ADC_CH_ACCDET2_MIN +
(AB8500_ADC_CH_ACCDET2_MAX - AB8500_ADC_CH_ACCDET2_MIN) * ad_value /
AB8500_ADC_RESOLUTION;
break;
case AB8500_GPADC_CHAN_VBUS:
res = AB8500_ADC_CH_CHG_V_MIN +
(AB8500_ADC_CH_CHG_V_MAX - AB8500_ADC_CH_CHG_V_MIN) * ad_value /
AB8500_ADC_RESOLUTION;
break;
case AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT:
case AB8500_GPADC_CHAN_USB_CHARGER_CURRENT:
res = AB8500_ADC_CH_CHG_I_MIN +
(AB8500_ADC_CH_CHG_I_MAX - AB8500_ADC_CH_CHG_I_MIN) * ad_value /
AB8500_ADC_RESOLUTION;
break;
case AB8500_GPADC_CHAN_BACKUP_BAT:
res = AB8500_ADC_CH_BKBAT_MIN +
(AB8500_ADC_CH_BKBAT_MAX - AB8500_ADC_CH_BKBAT_MIN) * ad_value /
AB8500_ADC_RESOLUTION;
break;
case AB8500_GPADC_CHAN_IBAT_VIRTUAL:
/* No calibration data available: just interpolate */
if (!gpadc->cal_data[AB8500_CAL_IBAT].gain) {
res = AB8500_ADC_CH_IBAT_MIN + (AB8500_ADC_CH_IBAT_MAX -
AB8500_ADC_CH_IBAT_MIN) * ad_value /
AB8500_ADC_RESOLUTION;
break;
}
/* Here we can use calibration */
res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_IBAT].gain +
gpadc->cal_data[AB8500_CAL_IBAT].offset)
>> AB8500_GPADC_CALIB_SHIFT_IBAT;
break;
default:
dev_err(gpadc->dev,
"unknown channel ID: %d, not possible to convert\n",
ch);
res = -EINVAL;
break;
}
return res;
}
static int ab8500_gpadc_read(struct ab8500_gpadc *gpadc,
const struct ab8500_gpadc_chan_info *ch,
int *ibat)
{
int ret;
int looplimit = 0;
unsigned long completion_timeout;
u8 val;
u8 low_data, high_data, low_data2, high_data2;
u8 ctrl1;
u8 ctrl23;
unsigned int delay_min = 0;
unsigned int delay_max = 0;
u8 data_low_addr, data_high_addr;
if (!gpadc)
return -ENODEV;
/* check if conversion is supported */
if ((gpadc->irq_sw <= 0) && !ch->hardware_control)
return -ENOTSUPP;
if ((gpadc->irq_hw <= 0) && ch->hardware_control)
return -ENOTSUPP;
/* Enable vddadc by grabbing PM runtime */
pm_runtime_get_sync(gpadc->dev);
/* Check if ADC is not busy, lock and proceed */
do {
ret = abx500_get_register_interruptible(gpadc->dev,
AB8500_GPADC, AB8500_GPADC_STAT_REG, &val);
if (ret < 0)
goto out;
if (!(val & AB8500_GPADC_STAT_BUSY))
break;
msleep(20);
} while (++looplimit < 10);
if (looplimit >= 10 && (val & AB8500_GPADC_STAT_BUSY)) {
dev_err(gpadc->dev, "gpadc_conversion: GPADC busy");
ret = -EINVAL;
goto out;
}
/* Enable GPADC */
ctrl1 = AB8500_GPADC_CTRL1_ENABLE;
/* Select the channel source and set average samples */
switch (ch->avg_sample) {
case 1:
ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_1;
break;
case 4:
ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_4;
break;
case 8:
ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_8;
break;
default:
ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_16;
break;
}
if (ch->hardware_control) {
ret = abx500_set_register_interruptible(gpadc->dev,
AB8500_GPADC, AB8500_GPADC_CTRL3_REG, ctrl23);
ctrl1 |= AB8500_GPADC_CTRL1_TRIG_ENA;
if (ch->falling_edge)
ctrl1 |= AB8500_GPADC_CTRL1_TRIG_EDGE;
} else {
ret = abx500_set_register_interruptible(gpadc->dev,
AB8500_GPADC, AB8500_GPADC_CTRL2_REG, ctrl23);
}
if (ret < 0) {
dev_err(gpadc->dev,
"gpadc_conversion: set avg samples failed\n");
goto out;
}
/*
* Enable ADC, buffering, select rising edge and enable ADC path
* charging current sense if it needed, ABB 3.0 needs some special
* treatment too.
*/
switch (ch->id) {
case AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT:
case AB8500_GPADC_CHAN_USB_CHARGER_CURRENT:
ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA |
AB8500_GPADC_CTRL1_ICHAR_ENA;
break;
case AB8500_GPADC_CHAN_BAT_TEMP:
if (!is_ab8500_2p0_or_earlier(gpadc->ab8500)) {
ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA |
AB8500_GPADC_CTRL1_BTEMP_PULL_UP;
/*
* Delay might be needed for ABB8500 cut 3.0, if not,
* remove when hardware will be available
*/
delay_min = 1000; /* Delay in micro seconds */
delay_max = 10000; /* large range optimises sleepmode */
break;
}
fallthrough;
default:
ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA;
break;
}
/* Write configuration to control register 1 */
ret = abx500_set_register_interruptible(gpadc->dev,
AB8500_GPADC, AB8500_GPADC_CTRL1_REG, ctrl1);
if (ret < 0) {
dev_err(gpadc->dev,
"gpadc_conversion: set Control register failed\n");
goto out;
}
if (delay_min != 0)
usleep_range(delay_min, delay_max);
if (ch->hardware_control) {
/* Set trigger delay timer */
ret = abx500_set_register_interruptible(gpadc->dev,
AB8500_GPADC, AB8500_GPADC_AUTO_TIMER_REG,
ch->trig_timer);
if (ret < 0) {
dev_err(gpadc->dev,
"gpadc_conversion: trig timer failed\n");
goto out;
}
completion_timeout = 2 * HZ;
data_low_addr = AB8500_GPADC_AUTODATAL_REG;
data_high_addr = AB8500_GPADC_AUTODATAH_REG;
} else {
/* Start SW conversion */
ret = abx500_mask_and_set_register_interruptible(gpadc->dev,
AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
AB8500_GPADC_CTRL1_START_SW_CONV,
AB8500_GPADC_CTRL1_START_SW_CONV);
if (ret < 0) {
dev_err(gpadc->dev,
"gpadc_conversion: start s/w conv failed\n");
goto out;
}
completion_timeout = msecs_to_jiffies(AB8500_GPADC_CONVERSION_TIME);
data_low_addr = AB8500_GPADC_MANDATAL_REG;
data_high_addr = AB8500_GPADC_MANDATAH_REG;
}
/* Wait for completion of conversion */
if (!wait_for_completion_timeout(&gpadc->complete,
completion_timeout)) {
dev_err(gpadc->dev,
"timeout didn't receive GPADC conv interrupt\n");
ret = -EINVAL;
goto out;
}
/* Read the converted RAW data */
ret = abx500_get_register_interruptible(gpadc->dev,
AB8500_GPADC, data_low_addr, &low_data);
if (ret < 0) {
dev_err(gpadc->dev,
"gpadc_conversion: read low data failed\n");
goto out;
}
ret = abx500_get_register_interruptible(gpadc->dev,
AB8500_GPADC, data_high_addr, &high_data);
if (ret < 0) {
dev_err(gpadc->dev,
"gpadc_conversion: read high data failed\n");
goto out;
}
/* Check if double conversion is required */
if ((ch->id == AB8500_GPADC_CHAN_BAT_CTRL_AND_IBAT) ||
(ch->id == AB8500_GPADC_CHAN_VBAT_MEAS_AND_IBAT) ||
(ch->id == AB8500_GPADC_CHAN_VBAT_TRUE_MEAS_AND_IBAT) ||
(ch->id == AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT)) {
if (ch->hardware_control) {
/* not supported */
ret = -ENOTSUPP;
dev_err(gpadc->dev,
"gpadc_conversion: only SW double conversion supported\n");
goto out;
} else {
/* Read the converted RAW data 2 */
ret = abx500_get_register_interruptible(gpadc->dev,
AB8500_GPADC, AB8540_GPADC_MANDATA2L_REG,
&low_data2);
if (ret < 0) {
dev_err(gpadc->dev,
"gpadc_conversion: read sw low data 2 failed\n");
goto out;
}
ret = abx500_get_register_interruptible(gpadc->dev,
AB8500_GPADC, AB8540_GPADC_MANDATA2H_REG,
&high_data2);
if (ret < 0) {
dev_err(gpadc->dev,
"gpadc_conversion: read sw high data 2 failed\n");
goto out;
}
if (ibat != NULL) {
*ibat = (high_data2 << 8) | low_data2;
} else {
dev_warn(gpadc->dev,
"gpadc_conversion: ibat not stored\n");
}
}
}
/* Disable GPADC */
ret = abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
AB8500_GPADC_CTRL1_REG, AB8500_GPADC_CTRL1_DISABLE);
if (ret < 0) {
dev_err(gpadc->dev, "gpadc_conversion: disable gpadc failed\n");
goto out;
}
/* This eventually drops the regulator */
pm_runtime_mark_last_busy(gpadc->dev);
pm_runtime_put_autosuspend(gpadc->dev);
return (high_data << 8) | low_data;
out:
/*
* It has shown to be needed to turn off the GPADC if an error occurs,
* otherwise we might have problem when waiting for the busy bit in the
* GPADC status register to go low. In V1.1 there wait_for_completion
* seems to timeout when waiting for an interrupt.. Not seen in V2.0
*/
(void) abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
AB8500_GPADC_CTRL1_REG, AB8500_GPADC_CTRL1_DISABLE);
pm_runtime_put(gpadc->dev);
dev_err(gpadc->dev,
"gpadc_conversion: Failed to AD convert channel %d\n", ch->id);
return ret;
}
/**
* ab8500_bm_gpadcconvend_handler() - isr for gpadc conversion completion
* @irq: irq number
* @data: pointer to the data passed during request irq
*
* This is a interrupt service routine for gpadc conversion completion.
* Notifies the gpadc completion is completed and the converted raw value
* can be read from the registers.
* Returns IRQ status(IRQ_HANDLED)
*/
static irqreturn_t ab8500_bm_gpadcconvend_handler(int irq, void *data)
{
struct ab8500_gpadc *gpadc = data;
complete(&gpadc->complete);
return IRQ_HANDLED;
}
static int otp_cal_regs[] = {
AB8500_GPADC_CAL_1,
AB8500_GPADC_CAL_2,
AB8500_GPADC_CAL_3,
AB8500_GPADC_CAL_4,
AB8500_GPADC_CAL_5,
AB8500_GPADC_CAL_6,
AB8500_GPADC_CAL_7,
};
static int otp4_cal_regs[] = {
AB8540_GPADC_OTP4_REG_7,
AB8540_GPADC_OTP4_REG_6,
AB8540_GPADC_OTP4_REG_5,
};
static void ab8500_gpadc_read_calibration_data(struct ab8500_gpadc *gpadc)
{
int i;
int ret[ARRAY_SIZE(otp_cal_regs)];
u8 gpadc_cal[ARRAY_SIZE(otp_cal_regs)];
int ret_otp4[ARRAY_SIZE(otp4_cal_regs)];
u8 gpadc_otp4[ARRAY_SIZE(otp4_cal_regs)];
int vmain_high, vmain_low;
int btemp_high, btemp_low;
int vbat_high, vbat_low;
int ibat_high, ibat_low;
s64 V_gain, V_offset, V2A_gain, V2A_offset;
/* First we read all OTP registers and store the error code */
for (i = 0; i < ARRAY_SIZE(otp_cal_regs); i++) {
ret[i] = abx500_get_register_interruptible(gpadc->dev,
AB8500_OTP_EMUL, otp_cal_regs[i], &gpadc_cal[i]);
if (ret[i] < 0) {
/* Continue anyway: maybe the other registers are OK */
dev_err(gpadc->dev, "%s: read otp reg 0x%02x failed\n",
__func__, otp_cal_regs[i]);
} else {
/* Put this in the entropy pool as device-unique */
add_device_randomness(&ret[i], sizeof(ret[i]));
}
}
/*
* The ADC calibration data is stored in OTP registers.
* The layout of the calibration data is outlined below and a more
* detailed description can be found in UM0836
*
* vm_h/l = vmain_high/low
* bt_h/l = btemp_high/low
* vb_h/l = vbat_high/low
*
* Data bits 8500/9540:
* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
* |.......|.......|.......|.......|.......|.......|.......|.......
* | | vm_h9 | vm_h8
* |.......|.......|.......|.......|.......|.......|.......|.......
* | | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
* |.......|.......|.......|.......|.......|.......|.......|.......
* | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
* |.......|.......|.......|.......|.......|.......|.......|.......
* | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
* |.......|.......|.......|.......|.......|.......|.......|.......
* | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
* |.......|.......|.......|.......|.......|.......|.......|.......
* | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
* |.......|.......|.......|.......|.......|.......|.......|.......
* | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
* |.......|.......|.......|.......|.......|.......|.......|.......
*
* Data bits 8540:
* OTP2
* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
* |.......|.......|.......|.......|.......|.......|.......|.......
* |
* |.......|.......|.......|.......|.......|.......|.......|.......
* | vm_h9 | vm_h8 | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
* |.......|.......|.......|.......|.......|.......|.......|.......
* | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
* |.......|.......|.......|.......|.......|.......|.......|.......
* | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
* |.......|.......|.......|.......|.......|.......|.......|.......
* | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
* |.......|.......|.......|.......|.......|.......|.......|.......
* | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
* |.......|.......|.......|.......|.......|.......|.......|.......
* | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
* |.......|.......|.......|.......|.......|.......|.......|.......
*
* Data bits 8540:
* OTP4
* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
* |.......|.......|.......|.......|.......|.......|.......|.......
* | | ib_h9 | ib_h8 | ib_h7
* |.......|.......|.......|.......|.......|.......|.......|.......
* | ib_h6 | ib_h5 | ib_h4 | ib_h3 | ib_h2 | ib_h1 | ib_h0 | ib_l5
* |.......|.......|.......|.......|.......|.......|.......|.......
* | ib_l4 | ib_l3 | ib_l2 | ib_l1 | ib_l0 |
*
*
* Ideal output ADC codes corresponding to injected input voltages
* during manufacturing is:
*
* vmain_high: Vin = 19500mV / ADC ideal code = 997
* vmain_low: Vin = 315mV / ADC ideal code = 16
* btemp_high: Vin = 1300mV / ADC ideal code = 985
* btemp_low: Vin = 21mV / ADC ideal code = 16
* vbat_high: Vin = 4700mV / ADC ideal code = 982
* vbat_low: Vin = 2380mV / ADC ideal code = 33
*/
if (is_ab8540(gpadc->ab8500)) {
/* Calculate gain and offset for VMAIN if all reads succeeded*/
if (!(ret[1] < 0 || ret[2] < 0)) {
vmain_high = (((gpadc_cal[1] & 0xFF) << 2) |
((gpadc_cal[2] & 0xC0) >> 6));
vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_hi =
(u16)vmain_high;
gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_lo =
(u16)vmain_low;
gpadc->cal_data[AB8500_CAL_VMAIN].gain = AB8500_GPADC_CALIB_SCALE *
(19500 - 315) / (vmain_high - vmain_low);
gpadc->cal_data[AB8500_CAL_VMAIN].offset = AB8500_GPADC_CALIB_SCALE *
19500 - (AB8500_GPADC_CALIB_SCALE * (19500 - 315) /
(vmain_high - vmain_low)) * vmain_high;
} else {
gpadc->cal_data[AB8500_CAL_VMAIN].gain = 0;
}
/* Read IBAT calibration Data */
for (i = 0; i < ARRAY_SIZE(otp4_cal_regs); i++) {
ret_otp4[i] = abx500_get_register_interruptible(
gpadc->dev, AB8500_OTP_EMUL,
otp4_cal_regs[i], &gpadc_otp4[i]);
if (ret_otp4[i] < 0)
dev_err(gpadc->dev,
"%s: read otp4 reg 0x%02x failed\n",
__func__, otp4_cal_regs[i]);
}
/* Calculate gain and offset for IBAT if all reads succeeded */
if (!(ret_otp4[0] < 0 || ret_otp4[1] < 0 || ret_otp4[2] < 0)) {
ibat_high = (((gpadc_otp4[0] & 0x07) << 7) |
((gpadc_otp4[1] & 0xFE) >> 1));
ibat_low = (((gpadc_otp4[1] & 0x01) << 5) |
((gpadc_otp4[2] & 0xF8) >> 3));
gpadc->cal_data[AB8500_CAL_IBAT].otp_calib_hi =
(u16)ibat_high;
gpadc->cal_data[AB8500_CAL_IBAT].otp_calib_lo =
(u16)ibat_low;
V_gain = ((AB8500_GPADC_IBAT_VDROP_H - AB8500_GPADC_IBAT_VDROP_L)
<< AB8500_GPADC_CALIB_SHIFT_IBAT) / (ibat_high - ibat_low);
V_offset = (AB8500_GPADC_IBAT_VDROP_H << AB8500_GPADC_CALIB_SHIFT_IBAT) -
(((AB8500_GPADC_IBAT_VDROP_H - AB8500_GPADC_IBAT_VDROP_L) <<
AB8500_GPADC_CALIB_SHIFT_IBAT) / (ibat_high - ibat_low))
* ibat_high;
/*
* Result obtained is in mV (at a scale factor),
* we need to calculate gain and offset to get mA
*/
V2A_gain = (AB8500_ADC_CH_IBAT_MAX - AB8500_ADC_CH_IBAT_MIN)/
(AB8500_ADC_CH_IBAT_MAX_V - AB8500_ADC_CH_IBAT_MIN_V);
V2A_offset = ((AB8500_ADC_CH_IBAT_MAX_V * AB8500_ADC_CH_IBAT_MIN -
AB8500_ADC_CH_IBAT_MAX * AB8500_ADC_CH_IBAT_MIN_V)
<< AB8500_GPADC_CALIB_SHIFT_IBAT)
/ (AB8500_ADC_CH_IBAT_MAX_V - AB8500_ADC_CH_IBAT_MIN_V);
gpadc->cal_data[AB8500_CAL_IBAT].gain =
V_gain * V2A_gain;
gpadc->cal_data[AB8500_CAL_IBAT].offset =
V_offset * V2A_gain + V2A_offset;
} else {
gpadc->cal_data[AB8500_CAL_IBAT].gain = 0;
}
} else {
/* Calculate gain and offset for VMAIN if all reads succeeded */
if (!(ret[0] < 0 || ret[1] < 0 || ret[2] < 0)) {
vmain_high = (((gpadc_cal[0] & 0x03) << 8) |
((gpadc_cal[1] & 0x3F) << 2) |
((gpadc_cal[2] & 0xC0) >> 6));
vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_hi =
(u16)vmain_high;
gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_lo =
(u16)vmain_low;
gpadc->cal_data[AB8500_CAL_VMAIN].gain = AB8500_GPADC_CALIB_SCALE *
(19500 - 315) / (vmain_high - vmain_low);
gpadc->cal_data[AB8500_CAL_VMAIN].offset = AB8500_GPADC_CALIB_SCALE *
19500 - (AB8500_GPADC_CALIB_SCALE * (19500 - 315) /
(vmain_high - vmain_low)) * vmain_high;
} else {
gpadc->cal_data[AB8500_CAL_VMAIN].gain = 0;
}
}
/* Calculate gain and offset for BTEMP if all reads succeeded */
if (!(ret[2] < 0 || ret[3] < 0 || ret[4] < 0)) {
btemp_high = (((gpadc_cal[2] & 0x01) << 9) |
(gpadc_cal[3] << 1) | ((gpadc_cal[4] & 0x80) >> 7));
btemp_low = ((gpadc_cal[4] & 0x7C) >> 2);
gpadc->cal_data[AB8500_CAL_BTEMP].otp_calib_hi = (u16)btemp_high;
gpadc->cal_data[AB8500_CAL_BTEMP].otp_calib_lo = (u16)btemp_low;
gpadc->cal_data[AB8500_CAL_BTEMP].gain =
AB8500_GPADC_CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low);
gpadc->cal_data[AB8500_CAL_BTEMP].offset = AB8500_GPADC_CALIB_SCALE * 1300 -
(AB8500_GPADC_CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low))
* btemp_high;
} else {
gpadc->cal_data[AB8500_CAL_BTEMP].gain = 0;
}
/* Calculate gain and offset for VBAT if all reads succeeded */
if (!(ret[4] < 0 || ret[5] < 0 || ret[6] < 0)) {
vbat_high = (((gpadc_cal[4] & 0x03) << 8) | gpadc_cal[5]);
vbat_low = ((gpadc_cal[6] & 0xFC) >> 2);
gpadc->cal_data[AB8500_CAL_VBAT].otp_calib_hi = (u16)vbat_high;
gpadc->cal_data[AB8500_CAL_VBAT].otp_calib_lo = (u16)vbat_low;
gpadc->cal_data[AB8500_CAL_VBAT].gain = AB8500_GPADC_CALIB_SCALE *
(4700 - 2380) / (vbat_high - vbat_low);
gpadc->cal_data[AB8500_CAL_VBAT].offset = AB8500_GPADC_CALIB_SCALE * 4700 -
(AB8500_GPADC_CALIB_SCALE * (4700 - 2380) /
(vbat_high - vbat_low)) * vbat_high;
} else {
gpadc->cal_data[AB8500_CAL_VBAT].gain = 0;
}
}
static int ab8500_gpadc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
const struct ab8500_gpadc_chan_info *ch;
int raw_val;
int processed;
ch = ab8500_gpadc_get_channel(gpadc, chan->address);
if (!ch) {
dev_err(gpadc->dev, "no such channel %lu\n",
chan->address);
return -EINVAL;
}
raw_val = ab8500_gpadc_read(gpadc, ch, NULL);
if (raw_val < 0)
return raw_val;
if (mask == IIO_CHAN_INFO_RAW) {
*val = raw_val;
return IIO_VAL_INT;
}
if (mask == IIO_CHAN_INFO_PROCESSED) {
processed = ab8500_gpadc_ad_to_voltage(gpadc, ch->id, raw_val);
if (processed < 0)
return processed;
/* Return millivolt or milliamps or millicentigrades */
*val = processed;
return IIO_VAL_INT;
}
return -EINVAL;
}
static int ab8500_gpadc_fwnode_xlate(struct iio_dev *indio_dev,
const struct fwnode_reference_args *iiospec)
{
int i;
for (i = 0; i < indio_dev->num_channels; i++)
if (indio_dev->channels[i].channel == iiospec->args[0])
return i;
return -EINVAL;
}
static const struct iio_info ab8500_gpadc_info = {
.fwnode_xlate = ab8500_gpadc_fwnode_xlate,
.read_raw = ab8500_gpadc_read_raw,
};
static int ab8500_gpadc_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
regulator_disable(gpadc->vddadc);
return 0;
}
static int ab8500_gpadc_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
int ret;
ret = regulator_enable(gpadc->vddadc);
if (ret)
dev_err(dev, "Failed to enable vddadc: %d\n", ret);
return ret;
}
/**
* ab8500_gpadc_parse_channel() - process devicetree channel configuration
* @dev: pointer to containing device
* @fwnode: fw node for the channel to configure
* @ch: channel info to fill in
* @iio_chan: IIO channel specification to fill in
*
* The devicetree will set up the channel for use with the specific device,
* and define usage for things like AUX GPADC inputs more precisely.
*/
static int ab8500_gpadc_parse_channel(struct device *dev,
struct fwnode_handle *fwnode,
struct ab8500_gpadc_chan_info *ch,
struct iio_chan_spec *iio_chan)
{
const char *name = fwnode_get_name(fwnode);
u32 chan;
int ret;
ret = fwnode_property_read_u32(fwnode, "reg", &chan);
if (ret) {
dev_err(dev, "invalid channel number %s\n", name);
return ret;
}
if (chan > AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT) {
dev_err(dev, "%s channel number out of range %d\n", name, chan);
return -EINVAL;
}
iio_chan->channel = chan;
iio_chan->datasheet_name = name;
iio_chan->indexed = 1;
iio_chan->address = chan;
iio_chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_PROCESSED);
/* Most are voltages (also temperatures), some are currents */
if ((chan == AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT) ||
(chan == AB8500_GPADC_CHAN_USB_CHARGER_CURRENT))
iio_chan->type = IIO_CURRENT;
else
iio_chan->type = IIO_VOLTAGE;
ch->id = chan;
/* Sensible defaults */
ch->avg_sample = 16;
ch->hardware_control = false;
ch->falling_edge = false;
ch->trig_timer = 0;
return 0;
}
/**
* ab8500_gpadc_parse_channels() - Parse the GPADC channels from DT
* @gpadc: the GPADC to configure the channels for
* @chans: the IIO channels we parsed
* @nchans: the number of IIO channels we parsed
*/
static int ab8500_gpadc_parse_channels(struct ab8500_gpadc *gpadc,
struct iio_chan_spec **chans_parsed,
unsigned int *nchans_parsed)
{
struct fwnode_handle *child;
struct ab8500_gpadc_chan_info *ch;
struct iio_chan_spec *iio_chans;
unsigned int nchans;
int i;
nchans = device_get_child_node_count(gpadc->dev);
if (!nchans) {
dev_err(gpadc->dev, "no channel children\n");
return -ENODEV;
}
dev_info(gpadc->dev, "found %d ADC channels\n", nchans);
iio_chans = devm_kcalloc(gpadc->dev, nchans,
sizeof(*iio_chans), GFP_KERNEL);
if (!iio_chans)
return -ENOMEM;
gpadc->chans = devm_kcalloc(gpadc->dev, nchans,
sizeof(*gpadc->chans), GFP_KERNEL);
if (!gpadc->chans)
return -ENOMEM;
i = 0;
device_for_each_child_node(gpadc->dev, child) {
struct iio_chan_spec *iio_chan;
int ret;
ch = &gpadc->chans[i];
iio_chan = &iio_chans[i];
ret = ab8500_gpadc_parse_channel(gpadc->dev, child, ch,
iio_chan);
if (ret) {
fwnode_handle_put(child);
return ret;
}
i++;
}
gpadc->nchans = nchans;
*chans_parsed = iio_chans;
*nchans_parsed = nchans;
return 0;
}
static int ab8500_gpadc_probe(struct platform_device *pdev)
{
struct ab8500_gpadc *gpadc;
struct iio_dev *indio_dev;
struct device *dev = &pdev->dev;
struct iio_chan_spec *iio_chans;
unsigned int n_iio_chans;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*gpadc));
if (!indio_dev)
return -ENOMEM;
platform_set_drvdata(pdev, indio_dev);
gpadc = iio_priv(indio_dev);
gpadc->dev = dev;
gpadc->ab8500 = dev_get_drvdata(dev->parent);
ret = ab8500_gpadc_parse_channels(gpadc, &iio_chans, &n_iio_chans);
if (ret)
return ret;
gpadc->irq_sw = platform_get_irq_byname(pdev, "SW_CONV_END");
if (gpadc->irq_sw < 0)
return gpadc->irq_sw;
if (is_ab8500(gpadc->ab8500)) {
gpadc->irq_hw = platform_get_irq_byname(pdev, "HW_CONV_END");
if (gpadc->irq_hw < 0)
return gpadc->irq_hw;
} else {
gpadc->irq_hw = 0;
}
/* Initialize completion used to notify completion of conversion */
init_completion(&gpadc->complete);
/* Request interrupts */
ret = devm_request_threaded_irq(dev, gpadc->irq_sw, NULL,
ab8500_bm_gpadcconvend_handler, IRQF_NO_SUSPEND | IRQF_ONESHOT,
"ab8500-gpadc-sw", gpadc);
if (ret < 0) {
dev_err(dev,
"failed to request sw conversion irq %d\n",
gpadc->irq_sw);
return ret;
}
if (gpadc->irq_hw) {
ret = devm_request_threaded_irq(dev, gpadc->irq_hw, NULL,
ab8500_bm_gpadcconvend_handler, IRQF_NO_SUSPEND | IRQF_ONESHOT,
"ab8500-gpadc-hw", gpadc);
if (ret < 0) {
dev_err(dev,
"Failed to request hw conversion irq: %d\n",
gpadc->irq_hw);
return ret;
}
}
/* The VTVout LDO used to power the AB8500 GPADC */
gpadc->vddadc = devm_regulator_get(dev, "vddadc");
if (IS_ERR(gpadc->vddadc))
return dev_err_probe(dev, PTR_ERR(gpadc->vddadc),
"failed to get vddadc\n");
ret = regulator_enable(gpadc->vddadc);
if (ret) {
dev_err(dev, "failed to enable vddadc: %d\n", ret);
return ret;
}
/* Enable runtime PM */
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_set_autosuspend_delay(dev, AB8500_GPADC_AUTOSUSPEND_DELAY);
pm_runtime_use_autosuspend(dev);
ab8500_gpadc_read_calibration_data(gpadc);
pm_runtime_put(dev);
indio_dev->name = "ab8500-gpadc";
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &ab8500_gpadc_info;
indio_dev->channels = iio_chans;
indio_dev->num_channels = n_iio_chans;
ret = devm_iio_device_register(dev, indio_dev);
if (ret)
goto out_dis_pm;
return 0;
out_dis_pm:
pm_runtime_get_sync(dev);
pm_runtime_put_noidle(dev);
pm_runtime_disable(dev);
regulator_disable(gpadc->vddadc);
return ret;
}
static int ab8500_gpadc_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct ab8500_gpadc *gpadc = iio_priv(indio_dev);
pm_runtime_get_sync(gpadc->dev);
pm_runtime_put_noidle(gpadc->dev);
pm_runtime_disable(gpadc->dev);
regulator_disable(gpadc->vddadc);
return 0;
}
static DEFINE_RUNTIME_DEV_PM_OPS(ab8500_gpadc_pm_ops,
ab8500_gpadc_runtime_suspend,
ab8500_gpadc_runtime_resume, NULL);
static struct platform_driver ab8500_gpadc_driver = {
.probe = ab8500_gpadc_probe,
.remove = ab8500_gpadc_remove,
.driver = {
.name = "ab8500-gpadc",
.pm = pm_ptr(&ab8500_gpadc_pm_ops),
},
};
builtin_platform_driver(ab8500_gpadc_driver);
| linux-master | drivers/iio/adc/ab8500-gpadc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* This file is part of STM32 ADC driver
*
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author: Fabrice Gasnier <[email protected]>.
*
* Inspired from: fsl-imx25-tsadc
*
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdesc.h>
#include <linux/irqdomain.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/units.h>
#include "stm32-adc-core.h"
#define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
/* SYSCFG registers */
#define STM32MP1_SYSCFG_PMCSETR 0x04
#define STM32MP1_SYSCFG_PMCCLRR 0x44
/* SYSCFG bit fields */
#define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9)
/* SYSCFG capability flags */
#define HAS_VBOOSTER BIT(0)
#define HAS_ANASWVDD BIT(1)
/**
* struct stm32_adc_common_regs - stm32 common registers
* @csr: common status register offset
* @ccr: common control register offset
* @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n
* @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n
* @ier: interrupt enable register offset for each adc
* @eocie_msk: end of conversion interrupt enable mask in @ier
*/
struct stm32_adc_common_regs {
u32 csr;
u32 ccr;
u32 eoc_msk[STM32_ADC_MAX_ADCS];
u32 ovr_msk[STM32_ADC_MAX_ADCS];
u32 ier;
u32 eocie_msk;
};
struct stm32_adc_priv;
/**
* struct stm32_adc_priv_cfg - stm32 core compatible configuration data
* @regs: common registers for all instances
* @clk_sel: clock selection routine
* @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
* @ipid: adc identification number
* @has_syscfg: SYSCFG capability flags
* @num_irqs: number of interrupt lines
* @num_adcs: maximum number of ADC instances in the common registers
*/
struct stm32_adc_priv_cfg {
const struct stm32_adc_common_regs *regs;
int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
u32 max_clk_rate_hz;
u32 ipid;
unsigned int has_syscfg;
unsigned int num_irqs;
unsigned int num_adcs;
};
/**
* struct stm32_adc_priv - stm32 ADC core private data
* @irq: irq(s) for ADC block
* @nb_adc_max: actual maximum number of instance per ADC block
* @domain: irq domain reference
* @aclk: clock reference for the analog circuitry
* @bclk: bus clock common for all ADCs, depends on part used
* @max_clk_rate: desired maximum clock rate
* @booster: booster supply reference
* @vdd: vdd supply reference
* @vdda: vdda analog supply reference
* @vref: regulator reference
* @vdd_uv: vdd supply voltage (microvolts)
* @vdda_uv: vdda supply voltage (microvolts)
* @cfg: compatible configuration data
* @common: common data for all ADC instances
* @ccr_bak: backup CCR in low power mode
* @syscfg: reference to syscon, system control registers
*/
struct stm32_adc_priv {
int irq[STM32_ADC_MAX_ADCS];
unsigned int nb_adc_max;
struct irq_domain *domain;
struct clk *aclk;
struct clk *bclk;
u32 max_clk_rate;
struct regulator *booster;
struct regulator *vdd;
struct regulator *vdda;
struct regulator *vref;
int vdd_uv;
int vdda_uv;
const struct stm32_adc_priv_cfg *cfg;
struct stm32_adc_common common;
u32 ccr_bak;
struct regmap *syscfg;
};
static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
{
return container_of(com, struct stm32_adc_priv, common);
}
/* STM32F4 ADC internal common clock prescaler division ratios */
static int stm32f4_pclk_div[] = {2, 4, 6, 8};
/**
* stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
* @pdev: platform device
* @priv: stm32 ADC core private data
* Select clock prescaler used for analog conversions, before using ADC.
*/
static int stm32f4_adc_clk_sel(struct platform_device *pdev,
struct stm32_adc_priv *priv)
{
unsigned long rate;
u32 val;
int i;
/* stm32f4 has one clk input for analog (mandatory), enforce it here */
if (!priv->aclk) {
dev_err(&pdev->dev, "No 'adc' clock found\n");
return -ENOENT;
}
rate = clk_get_rate(priv->aclk);
if (!rate) {
dev_err(&pdev->dev, "Invalid clock rate: 0\n");
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
break;
}
if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
dev_err(&pdev->dev, "adc clk selection failed\n");
return -EINVAL;
}
priv->common.rate = rate / stm32f4_pclk_div[i];
val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
val &= ~STM32F4_ADC_ADCPRE_MASK;
val |= i << STM32F4_ADC_ADCPRE_SHIFT;
writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
priv->common.rate / 1000);
return 0;
}
/**
* struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
* @ckmode: ADC clock mode, Async or sync with prescaler.
* @presc: prescaler bitfield for async clock mode
* @div: prescaler division ratio
*/
struct stm32h7_adc_ck_spec {
u32 ckmode;
u32 presc;
int div;
};
static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
/* 00: CK_ADC[1..3]: Asynchronous clock modes */
{ 0, 0, 1 },
{ 0, 1, 2 },
{ 0, 2, 4 },
{ 0, 3, 6 },
{ 0, 4, 8 },
{ 0, 5, 10 },
{ 0, 6, 12 },
{ 0, 7, 16 },
{ 0, 8, 32 },
{ 0, 9, 64 },
{ 0, 10, 128 },
{ 0, 11, 256 },
/* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
{ 1, 0, 1 },
{ 2, 0, 2 },
{ 3, 0, 4 },
};
static int stm32h7_adc_clk_sel(struct platform_device *pdev,
struct stm32_adc_priv *priv)
{
u32 ckmode, presc, val;
unsigned long rate;
int i, div, duty;
/* stm32h7 bus clock is common for all ADC instances (mandatory) */
if (!priv->bclk) {
dev_err(&pdev->dev, "No 'bus' clock found\n");
return -ENOENT;
}
/*
* stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
* So, choice is to have bus clock mandatory and adc clock optional.
* If optional 'adc' clock has been found, then try to use it first.
*/
if (priv->aclk) {
/*
* Asynchronous clock modes (e.g. ckmode == 0)
* From spec: PLL output musn't exceed max rate
*/
rate = clk_get_rate(priv->aclk);
if (!rate) {
dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
return -EINVAL;
}
/* If duty is an error, kindly use at least /2 divider */
duty = clk_get_scaled_duty_cycle(priv->aclk, 100);
if (duty < 0)
dev_warn(&pdev->dev, "adc clock duty: %d\n", duty);
for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
presc = stm32h7_adc_ckmodes_spec[i].presc;
div = stm32h7_adc_ckmodes_spec[i].div;
if (ckmode)
continue;
/*
* For proper operation, clock duty cycle range is 49%
* to 51%. Apply at least /2 prescaler otherwise.
*/
if (div == 1 && (duty < 49 || duty > 51))
continue;
if ((rate / div) <= priv->max_clk_rate)
goto out;
}
}
/* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
rate = clk_get_rate(priv->bclk);
if (!rate) {
dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
return -EINVAL;
}
duty = clk_get_scaled_duty_cycle(priv->bclk, 100);
if (duty < 0)
dev_warn(&pdev->dev, "bus clock duty: %d\n", duty);
for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
presc = stm32h7_adc_ckmodes_spec[i].presc;
div = stm32h7_adc_ckmodes_spec[i].div;
if (!ckmode)
continue;
if (div == 1 && (duty < 49 || duty > 51))
continue;
if ((rate / div) <= priv->max_clk_rate)
goto out;
}
dev_err(&pdev->dev, "adc clk selection failed\n");
return -EINVAL;
out:
/* rate used later by each ADC instance to control BOOST mode */
priv->common.rate = rate / div;
/* Set common clock mode and prescaler */
val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
val |= ckmode << STM32H7_CKMODE_SHIFT;
val |= presc << STM32H7_PRESC_SHIFT;
writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
return 0;
}
/* STM32F4 common registers definitions */
static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
.csr = STM32F4_ADC_CSR,
.ccr = STM32F4_ADC_CCR,
.eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3 },
.ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3 },
.ier = STM32F4_ADC_CR1,
.eocie_msk = STM32F4_EOCIE,
};
/* STM32H7 common registers definitions */
static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
.csr = STM32H7_ADC_CSR,
.ccr = STM32H7_ADC_CCR,
.eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV },
.ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV },
.ier = STM32H7_ADC_IER,
.eocie_msk = STM32H7_EOCIE,
};
/* STM32MP13 common registers definitions */
static const struct stm32_adc_common_regs stm32mp13_adc_common_regs = {
.csr = STM32H7_ADC_CSR,
.ccr = STM32H7_ADC_CCR,
.eoc_msk = { STM32H7_EOC_MST },
.ovr_msk = { STM32H7_OVR_MST },
.ier = STM32H7_ADC_IER,
.eocie_msk = STM32H7_EOCIE,
};
static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
};
static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
unsigned int adc)
{
u32 ier, offset = stm32_adc_offset[adc];
ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
return ier & priv->cfg->regs->eocie_msk;
}
/* ADC common interrupt for all instances */
static void stm32_adc_irq_handler(struct irq_desc *desc)
{
struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
int i;
u32 status;
chained_irq_enter(chip, desc);
status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
/*
* End of conversion may be handled by using IRQ or DMA. There may be a
* race here when two conversions complete at the same time on several
* ADCs. EOC may be read 'set' for several ADCs, with:
* - an ADC configured to use DMA (EOC triggers the DMA request, and
* is then automatically cleared by DR read in hardware)
* - an ADC configured to use IRQs (EOCIE bit is set. The handler must
* be called in this case)
* So both EOC status bit in CSR and EOCIE control bit must be checked
* before invoking the interrupt handler (e.g. call ISR only for
* IRQ-enabled ADCs).
*/
for (i = 0; i < priv->nb_adc_max; i++) {
if ((status & priv->cfg->regs->eoc_msk[i] &&
stm32_adc_eoc_enabled(priv, i)) ||
(status & priv->cfg->regs->ovr_msk[i]))
generic_handle_domain_irq(priv->domain, i);
}
chained_irq_exit(chip, desc);
};
static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
irq_set_chip_data(irq, d->host_data);
irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
return 0;
}
static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
{
irq_set_chip_and_handler(irq, NULL, NULL);
irq_set_chip_data(irq, NULL);
}
static const struct irq_domain_ops stm32_adc_domain_ops = {
.map = stm32_adc_domain_map,
.unmap = stm32_adc_domain_unmap,
.xlate = irq_domain_xlate_onecell,
};
static int stm32_adc_irq_probe(struct platform_device *pdev,
struct stm32_adc_priv *priv)
{
struct device_node *np = pdev->dev.of_node;
unsigned int i;
/*
* Interrupt(s) must be provided, depending on the compatible:
* - stm32f4/h7 shares a common interrupt line.
* - stm32mp1, has one line per ADC
*/
for (i = 0; i < priv->cfg->num_irqs; i++) {
priv->irq[i] = platform_get_irq(pdev, i);
if (priv->irq[i] < 0)
return priv->irq[i];
}
priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
&stm32_adc_domain_ops,
priv);
if (!priv->domain) {
dev_err(&pdev->dev, "Failed to add irq domain\n");
return -ENOMEM;
}
for (i = 0; i < priv->cfg->num_irqs; i++) {
irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
irq_set_handler_data(priv->irq[i], priv);
}
return 0;
}
static void stm32_adc_irq_remove(struct platform_device *pdev,
struct stm32_adc_priv *priv)
{
int hwirq;
unsigned int i;
for (hwirq = 0; hwirq < priv->nb_adc_max; hwirq++)
irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
irq_domain_remove(priv->domain);
for (i = 0; i < priv->cfg->num_irqs; i++)
irq_set_chained_handler(priv->irq[i], NULL);
}
static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
struct device *dev)
{
int ret;
/*
* On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
* switches (via PCSEL) which have reduced performances when their
* supply is below 2.7V (vdda by default):
* - Voltage booster can be used, to get full ADC performances
* (increases power consumption).
* - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
*
* Recommended settings for ANASWVDD and EN_BOOSTER:
* - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
* - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
* - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default)
*/
if (priv->vdda_uv < 2700000) {
if (priv->syscfg && priv->vdd_uv > 2700000) {
ret = regulator_enable(priv->vdd);
if (ret < 0) {
dev_err(dev, "vdd enable failed %d\n", ret);
return ret;
}
ret = regmap_write(priv->syscfg,
STM32MP1_SYSCFG_PMCSETR,
STM32MP1_SYSCFG_ANASWVDD_MASK);
if (ret < 0) {
regulator_disable(priv->vdd);
dev_err(dev, "vdd select failed, %d\n", ret);
return ret;
}
dev_dbg(dev, "analog switches supplied by vdd\n");
return 0;
}
if (priv->booster) {
/*
* This is optional, as this is a trade-off between
* analog performance and power consumption.
*/
ret = regulator_enable(priv->booster);
if (ret < 0) {
dev_err(dev, "booster enable failed %d\n", ret);
return ret;
}
dev_dbg(dev, "analog switches supplied by booster\n");
return 0;
}
}
/* Fallback using vdda (default), nothing to do */
dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
priv->vdda_uv);
return 0;
}
static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
{
if (priv->vdda_uv < 2700000) {
if (priv->syscfg && priv->vdd_uv > 2700000) {
regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
STM32MP1_SYSCFG_ANASWVDD_MASK);
regulator_disable(priv->vdd);
return;
}
if (priv->booster)
regulator_disable(priv->booster);
}
}
static int stm32_adc_core_hw_start(struct device *dev)
{
struct stm32_adc_common *common = dev_get_drvdata(dev);
struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
int ret;
ret = regulator_enable(priv->vdda);
if (ret < 0) {
dev_err(dev, "vdda enable failed %d\n", ret);
return ret;
}
ret = regulator_get_voltage(priv->vdda);
if (ret < 0) {
dev_err(dev, "vdda get voltage failed, %d\n", ret);
goto err_vdda_disable;
}
priv->vdda_uv = ret;
ret = stm32_adc_core_switches_supply_en(priv, dev);
if (ret < 0)
goto err_vdda_disable;
ret = regulator_enable(priv->vref);
if (ret < 0) {
dev_err(dev, "vref enable failed\n");
goto err_switches_dis;
}
ret = clk_prepare_enable(priv->bclk);
if (ret < 0) {
dev_err(dev, "bus clk enable failed\n");
goto err_regulator_disable;
}
ret = clk_prepare_enable(priv->aclk);
if (ret < 0) {
dev_err(dev, "adc clk enable failed\n");
goto err_bclk_disable;
}
writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
return 0;
err_bclk_disable:
clk_disable_unprepare(priv->bclk);
err_regulator_disable:
regulator_disable(priv->vref);
err_switches_dis:
stm32_adc_core_switches_supply_dis(priv);
err_vdda_disable:
regulator_disable(priv->vdda);
return ret;
}
static void stm32_adc_core_hw_stop(struct device *dev)
{
struct stm32_adc_common *common = dev_get_drvdata(dev);
struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
/* Backup CCR that may be lost (depends on power state to achieve) */
priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
clk_disable_unprepare(priv->aclk);
clk_disable_unprepare(priv->bclk);
regulator_disable(priv->vref);
stm32_adc_core_switches_supply_dis(priv);
regulator_disable(priv->vdda);
}
static int stm32_adc_core_switches_probe(struct device *dev,
struct stm32_adc_priv *priv)
{
struct device_node *np = dev->of_node;
int ret;
/* Analog switches supply can be controlled by syscfg (optional) */
priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
if (IS_ERR(priv->syscfg)) {
ret = PTR_ERR(priv->syscfg);
if (ret != -ENODEV)
return dev_err_probe(dev, ret, "Can't probe syscfg\n");
priv->syscfg = NULL;
}
/* Booster can be used to supply analog switches (optional) */
if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
of_property_read_bool(np, "booster-supply")) {
priv->booster = devm_regulator_get_optional(dev, "booster");
if (IS_ERR(priv->booster)) {
ret = PTR_ERR(priv->booster);
if (ret != -ENODEV)
return dev_err_probe(dev, ret, "can't get booster\n");
priv->booster = NULL;
}
}
/* Vdd can be used to supply analog switches (optional) */
if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
of_property_read_bool(np, "vdd-supply")) {
priv->vdd = devm_regulator_get_optional(dev, "vdd");
if (IS_ERR(priv->vdd)) {
ret = PTR_ERR(priv->vdd);
if (ret != -ENODEV)
return dev_err_probe(dev, ret, "can't get vdd\n");
priv->vdd = NULL;
}
}
if (priv->vdd) {
ret = regulator_enable(priv->vdd);
if (ret < 0) {
dev_err(dev, "vdd enable failed %d\n", ret);
return ret;
}
ret = regulator_get_voltage(priv->vdd);
if (ret < 0) {
dev_err(dev, "vdd get voltage failed %d\n", ret);
regulator_disable(priv->vdd);
return ret;
}
priv->vdd_uv = ret;
regulator_disable(priv->vdd);
}
return 0;
}
static int stm32_adc_probe_identification(struct platform_device *pdev,
struct stm32_adc_priv *priv)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
const char *compat;
int ret, count = 0;
u32 id, val;
if (!priv->cfg->ipid)
return 0;
id = FIELD_GET(STM32MP1_IPIDR_MASK,
readl_relaxed(priv->common.base + STM32MP1_ADC_IPDR));
if (id != priv->cfg->ipid) {
dev_err(&pdev->dev, "Unexpected IP version: 0x%x", id);
return -EINVAL;
}
for_each_child_of_node(np, child) {
ret = of_property_read_string(child, "compatible", &compat);
if (ret)
continue;
/* Count child nodes with stm32 adc compatible */
if (strstr(compat, "st,stm32") && strstr(compat, "adc"))
count++;
}
val = readl_relaxed(priv->common.base + STM32MP1_ADC_HWCFGR0);
priv->nb_adc_max = FIELD_GET(STM32MP1_ADCNUM_MASK, val);
if (count > priv->nb_adc_max) {
dev_err(&pdev->dev, "Unexpected child number: %d", count);
return -EINVAL;
}
val = readl_relaxed(priv->common.base + STM32MP1_ADC_VERR);
dev_dbg(&pdev->dev, "ADC version: %lu.%lu\n",
FIELD_GET(STM32MP1_MAJREV_MASK, val),
FIELD_GET(STM32MP1_MINREV_MASK, val));
return 0;
}
static int stm32_adc_probe(struct platform_device *pdev)
{
struct stm32_adc_priv *priv;
struct device *dev = &pdev->dev;
struct device_node *np = pdev->dev.of_node;
struct resource *res;
u32 max_rate;
int ret;
if (!pdev->dev.of_node)
return -ENODEV;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, &priv->common);
priv->cfg = (const struct stm32_adc_priv_cfg *)
of_match_device(dev->driver->of_match_table, dev)->data;
priv->nb_adc_max = priv->cfg->num_adcs;
spin_lock_init(&priv->common.lock);
priv->common.base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(priv->common.base))
return PTR_ERR(priv->common.base);
priv->common.phys_base = res->start;
priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
if (IS_ERR(priv->vdda))
return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda),
"vdda get failed\n");
priv->vref = devm_regulator_get(&pdev->dev, "vref");
if (IS_ERR(priv->vref))
return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref),
"vref get failed\n");
priv->aclk = devm_clk_get_optional(&pdev->dev, "adc");
if (IS_ERR(priv->aclk))
return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk),
"Can't get 'adc' clock\n");
priv->bclk = devm_clk_get_optional(&pdev->dev, "bus");
if (IS_ERR(priv->bclk))
return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk),
"Can't get 'bus' clock\n");
ret = stm32_adc_core_switches_probe(dev, priv);
if (ret)
return ret;
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
pm_runtime_use_autosuspend(dev);
pm_runtime_enable(dev);
ret = stm32_adc_core_hw_start(dev);
if (ret)
goto err_pm_stop;
ret = stm32_adc_probe_identification(pdev, priv);
if (ret < 0)
goto err_hw_stop;
ret = regulator_get_voltage(priv->vref);
if (ret < 0) {
dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
goto err_hw_stop;
}
priv->common.vref_mv = ret / 1000;
dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
&max_rate);
if (!ret)
priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
else
priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
ret = priv->cfg->clk_sel(pdev, priv);
if (ret < 0)
goto err_hw_stop;
ret = stm32_adc_irq_probe(pdev, priv);
if (ret < 0)
goto err_hw_stop;
ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "failed to populate DT children\n");
goto err_irq_remove;
}
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
return 0;
err_irq_remove:
stm32_adc_irq_remove(pdev, priv);
err_hw_stop:
stm32_adc_core_hw_stop(dev);
err_pm_stop:
pm_runtime_disable(dev);
pm_runtime_set_suspended(dev);
pm_runtime_put_noidle(dev);
return ret;
}
static int stm32_adc_remove(struct platform_device *pdev)
{
struct stm32_adc_common *common = platform_get_drvdata(pdev);
struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
pm_runtime_get_sync(&pdev->dev);
of_platform_depopulate(&pdev->dev);
stm32_adc_irq_remove(pdev, priv);
stm32_adc_core_hw_stop(&pdev->dev);
pm_runtime_disable(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
return 0;
}
static int stm32_adc_core_runtime_suspend(struct device *dev)
{
stm32_adc_core_hw_stop(dev);
return 0;
}
static int stm32_adc_core_runtime_resume(struct device *dev)
{
return stm32_adc_core_hw_start(dev);
}
static int stm32_adc_core_runtime_idle(struct device *dev)
{
pm_runtime_mark_last_busy(dev);
return 0;
}
static DEFINE_RUNTIME_DEV_PM_OPS(stm32_adc_core_pm_ops,
stm32_adc_core_runtime_suspend,
stm32_adc_core_runtime_resume,
stm32_adc_core_runtime_idle);
static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
.regs = &stm32f4_adc_common_regs,
.clk_sel = stm32f4_adc_clk_sel,
.max_clk_rate_hz = 36000000,
.num_irqs = 1,
.num_adcs = 3,
};
static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
.regs = &stm32h7_adc_common_regs,
.clk_sel = stm32h7_adc_clk_sel,
.max_clk_rate_hz = 36000000,
.has_syscfg = HAS_VBOOSTER,
.num_irqs = 1,
.num_adcs = 2,
};
static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
.regs = &stm32h7_adc_common_regs,
.clk_sel = stm32h7_adc_clk_sel,
.max_clk_rate_hz = 36000000,
.has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
.ipid = STM32MP15_IPIDR_NUMBER,
.num_irqs = 2,
};
static const struct stm32_adc_priv_cfg stm32mp13_adc_priv_cfg = {
.regs = &stm32mp13_adc_common_regs,
.clk_sel = stm32h7_adc_clk_sel,
.max_clk_rate_hz = 75 * HZ_PER_MHZ,
.ipid = STM32MP13_IPIDR_NUMBER,
.num_irqs = 1,
};
static const struct of_device_id stm32_adc_of_match[] = {
{
.compatible = "st,stm32f4-adc-core",
.data = (void *)&stm32f4_adc_priv_cfg
}, {
.compatible = "st,stm32h7-adc-core",
.data = (void *)&stm32h7_adc_priv_cfg
}, {
.compatible = "st,stm32mp1-adc-core",
.data = (void *)&stm32mp1_adc_priv_cfg
}, {
.compatible = "st,stm32mp13-adc-core",
.data = (void *)&stm32mp13_adc_priv_cfg
}, {
},
};
MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
static struct platform_driver stm32_adc_driver = {
.probe = stm32_adc_probe,
.remove = stm32_adc_remove,
.driver = {
.name = "stm32-adc-core",
.of_match_table = stm32_adc_of_match,
.pm = pm_ptr(&stm32_adc_core_pm_ops),
},
};
module_platform_driver(stm32_adc_driver);
MODULE_AUTHOR("Fabrice Gasnier <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:stm32-adc-core");
| linux-master | drivers/iio/adc/stm32-adc-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* palmas-adc.c -- TI PALMAS GPADC.
*
* Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
*
* Author: Pradeep Goudagunta <[email protected]>
*/
#include <linux/module.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/mfd/palmas.h>
#include <linux/completion.h>
#include <linux/of.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/machine.h>
#include <linux/iio/driver.h>
#define MOD_NAME "palmas-gpadc"
#define PALMAS_ADC_CONVERSION_TIMEOUT (msecs_to_jiffies(5000))
#define PALMAS_TO_BE_CALCULATED 0
#define PALMAS_GPADC_TRIMINVALID -1
struct palmas_gpadc_info {
/* calibration codes and regs */
int x1; /* lower ideal code */
int x2; /* higher ideal code */
int v1; /* expected lower volt reading */
int v2; /* expected higher volt reading */
u8 trim1_reg; /* register number for lower trim */
u8 trim2_reg; /* register number for upper trim */
int gain; /* calculated from above (after reading trim regs) */
int offset; /* calculated from above (after reading trim regs) */
int gain_error; /* calculated from above (after reading trim regs) */
bool is_uncalibrated; /* if channel has calibration data */
};
#define PALMAS_ADC_INFO(_chan, _x1, _x2, _v1, _v2, _t1, _t2, _is_uncalibrated) \
[PALMAS_ADC_CH_##_chan] = { \
.x1 = _x1, \
.x2 = _x2, \
.v1 = _v1, \
.v2 = _v2, \
.gain = PALMAS_TO_BE_CALCULATED, \
.offset = PALMAS_TO_BE_CALCULATED, \
.gain_error = PALMAS_TO_BE_CALCULATED, \
.trim1_reg = PALMAS_GPADC_TRIM##_t1, \
.trim2_reg = PALMAS_GPADC_TRIM##_t2, \
.is_uncalibrated = _is_uncalibrated \
}
static struct palmas_gpadc_info palmas_gpadc_info[] = {
PALMAS_ADC_INFO(IN0, 2064, 3112, 630, 950, 1, 2, false),
PALMAS_ADC_INFO(IN1, 2064, 3112, 630, 950, 1, 2, false),
PALMAS_ADC_INFO(IN2, 2064, 3112, 1260, 1900, 3, 4, false),
PALMAS_ADC_INFO(IN3, 2064, 3112, 630, 950, 1, 2, false),
PALMAS_ADC_INFO(IN4, 2064, 3112, 630, 950, 1, 2, false),
PALMAS_ADC_INFO(IN5, 2064, 3112, 630, 950, 1, 2, false),
PALMAS_ADC_INFO(IN6, 2064, 3112, 2520, 3800, 5, 6, false),
PALMAS_ADC_INFO(IN7, 2064, 3112, 2520, 3800, 7, 8, false),
PALMAS_ADC_INFO(IN8, 2064, 3112, 3150, 4750, 9, 10, false),
PALMAS_ADC_INFO(IN9, 2064, 3112, 5670, 8550, 11, 12, false),
PALMAS_ADC_INFO(IN10, 2064, 3112, 3465, 5225, 13, 14, false),
PALMAS_ADC_INFO(IN11, 0, 0, 0, 0, INVALID, INVALID, true),
PALMAS_ADC_INFO(IN12, 0, 0, 0, 0, INVALID, INVALID, true),
PALMAS_ADC_INFO(IN13, 0, 0, 0, 0, INVALID, INVALID, true),
PALMAS_ADC_INFO(IN14, 2064, 3112, 3645, 5225, 15, 16, false),
PALMAS_ADC_INFO(IN15, 0, 0, 0, 0, INVALID, INVALID, true),
};
struct palmas_adc_event {
bool enabled;
int channel;
enum iio_event_direction direction;
};
struct palmas_gpadc_thresholds {
int high;
int low;
};
/*
* struct palmas_gpadc - the palmas_gpadc structure
* @ch0_current: channel 0 current source setting
* 0: 0 uA
* 1: 5 uA
* 2: 15 uA
* 3: 20 uA
* @ch3_current: channel 0 current source setting
* 0: 0 uA
* 1: 10 uA
* 2: 400 uA
* 3: 800 uA
* @extended_delay: enable the gpadc extended delay mode
* @auto_conversion_period: define the auto_conversion_period
* @lock: Lock to protect the device state during a potential concurrent
* read access from userspace. Reading a raw value requires a sequence
* of register writes, then a wait for a completion callback,
* and finally a register read, during which userspace could issue
* another read request. This lock protects a read access from
* ocurring before another one has finished.
*
* This is the palmas_gpadc structure to store run-time information
* and pointers for this driver instance.
*/
struct palmas_gpadc {
struct device *dev;
struct palmas *palmas;
u8 ch0_current;
u8 ch3_current;
bool extended_delay;
int irq;
int irq_auto_0;
int irq_auto_1;
struct palmas_gpadc_info *adc_info;
struct completion conv_completion;
struct palmas_adc_event event0;
struct palmas_adc_event event1;
struct palmas_gpadc_thresholds thresholds[PALMAS_ADC_CH_MAX];
int auto_conversion_period;
struct mutex lock;
};
static struct palmas_adc_event *palmas_gpadc_get_event(struct palmas_gpadc *adc,
int adc_chan,
enum iio_event_direction dir)
{
if (adc_chan == adc->event0.channel && dir == adc->event0.direction)
return &adc->event0;
if (adc_chan == adc->event1.channel && dir == adc->event1.direction)
return &adc->event1;
return NULL;
}
static bool palmas_gpadc_channel_is_freerunning(struct palmas_gpadc *adc,
int adc_chan)
{
return palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_RISING) ||
palmas_gpadc_get_event(adc, adc_chan, IIO_EV_DIR_FALLING);
}
/*
* GPADC lock issue in AUTO mode.
* Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO
* mode feature.
* Details:
* When the AUTO mode is the only conversion mode enabled, if the AUTO
* mode feature is disabled with bit GPADC_AUTO_CTRL. AUTO_CONV1_EN = 0
* or bit GPADC_AUTO_CTRL. AUTO_CONV0_EN = 0 during a conversion, the
* conversion mechanism can be seen as locked meaning that all following
* conversion will give 0 as a result. Bit GPADC_STATUS.GPADC_AVAILABLE
* will stay at 0 meaning that GPADC is busy. An RT conversion can unlock
* the GPADC.
*
* Workaround(s):
* To avoid the lock mechanism, the workaround to follow before any stop
* conversion request is:
* Force the GPADC state machine to be ON by using the GPADC_CTRL1.
* GPADC_FORCE bit = 1
* Shutdown the GPADC AUTO conversion using
* GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0.
* After 100us, force the GPADC state machine to be OFF by using the
* GPADC_CTRL1. GPADC_FORCE bit = 0
*/
static int palmas_disable_auto_conversion(struct palmas_gpadc *adc)
{
int ret;
ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_CTRL1,
PALMAS_GPADC_CTRL1_GPADC_FORCE,
PALMAS_GPADC_CTRL1_GPADC_FORCE);
if (ret < 0) {
dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
return ret;
}
ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_AUTO_CTRL,
PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 |
PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0,
0);
if (ret < 0) {
dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret);
return ret;
}
udelay(100);
ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_CTRL1,
PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
if (ret < 0)
dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
return ret;
}
static irqreturn_t palmas_gpadc_irq(int irq, void *data)
{
struct palmas_gpadc *adc = data;
complete(&adc->conv_completion);
return IRQ_HANDLED;
}
static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data)
{
struct iio_dev *indio_dev = data;
struct palmas_gpadc *adc = iio_priv(indio_dev);
struct palmas_adc_event *ev;
dev_dbg(adc->dev, "Threshold interrupt %d occurs\n", irq);
palmas_disable_auto_conversion(adc);
ev = (irq == adc->irq_auto_0) ? &adc->event0 : &adc->event1;
if (ev->channel != -1) {
enum iio_event_direction dir;
u64 code;
dir = ev->direction;
code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, ev->channel,
IIO_EV_TYPE_THRESH, dir);
iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
}
return IRQ_HANDLED;
}
static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc,
bool mask)
{
int ret;
if (!mask)
ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
PALMAS_INT3_MASK,
PALMAS_INT3_MASK_GPADC_EOC_SW, 0);
else
ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
PALMAS_INT3_MASK,
PALMAS_INT3_MASK_GPADC_EOC_SW,
PALMAS_INT3_MASK_GPADC_EOC_SW);
if (ret < 0)
dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret);
return ret;
}
static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan,
int enable)
{
unsigned int mask, val;
int ret;
if (enable) {
val = (adc->extended_delay
<< PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT);
ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_RT_CTRL,
PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val);
if (ret < 0) {
dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret);
return ret;
}
mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK |
PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK |
PALMAS_GPADC_CTRL1_GPADC_FORCE);
val = (adc->ch0_current
<< PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT);
val |= (adc->ch3_current
<< PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT);
val |= PALMAS_GPADC_CTRL1_GPADC_FORCE;
ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_CTRL1, mask, val);
if (ret < 0) {
dev_err(adc->dev,
"Failed to update current setting: %d\n", ret);
return ret;
}
mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK |
PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_SW_SELECT, mask, val);
if (ret < 0) {
dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret);
return ret;
}
} else {
ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_SW_SELECT, 0);
if (ret < 0)
dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret);
ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_CTRL1,
PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
if (ret < 0) {
dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
return ret;
}
}
return ret;
}
static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan)
{
int ret;
if (palmas_gpadc_channel_is_freerunning(adc, adc_chan))
return 0; /* ADC already running */
ret = palmas_gpadc_enable(adc, adc_chan, true);
if (ret < 0)
return ret;
return palmas_gpadc_start_mask_interrupt(adc, 0);
}
static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan)
{
palmas_gpadc_start_mask_interrupt(adc, 1);
palmas_gpadc_enable(adc, adc_chan, false);
}
static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan)
{
int k;
int d1;
int d2;
int ret;
int gain;
int x1 = adc->adc_info[adc_chan].x1;
int x2 = adc->adc_info[adc_chan].x2;
int v1 = adc->adc_info[adc_chan].v1;
int v2 = adc->adc_info[adc_chan].v2;
ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
adc->adc_info[adc_chan].trim1_reg, &d1);
if (ret < 0) {
dev_err(adc->dev, "TRIM read failed: %d\n", ret);
goto scrub;
}
ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
adc->adc_info[adc_chan].trim2_reg, &d2);
if (ret < 0) {
dev_err(adc->dev, "TRIM read failed: %d\n", ret);
goto scrub;
}
/* gain error calculation */
k = (1000 + (1000 * (d2 - d1)) / (x2 - x1));
/* gain calculation */
gain = ((v2 - v1) * 1000) / (x2 - x1);
adc->adc_info[adc_chan].gain_error = k;
adc->adc_info[adc_chan].gain = gain;
/* offset Calculation */
adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1);
scrub:
return ret;
}
static int palmas_gpadc_start_conversion(struct palmas_gpadc *adc, int adc_chan)
{
unsigned int val;
int ret;
if (palmas_gpadc_channel_is_freerunning(adc, adc_chan)) {
int event = (adc_chan == adc->event0.channel) ? 0 : 1;
unsigned int reg = (event == 0) ?
PALMAS_GPADC_AUTO_CONV0_LSB :
PALMAS_GPADC_AUTO_CONV1_LSB;
ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
reg, &val, 2);
if (ret < 0) {
dev_err(adc->dev, "AUTO_CONV%x_LSB read failed: %d\n",
event, ret);
return ret;
}
} else {
init_completion(&adc->conv_completion);
ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_SW_SELECT,
PALMAS_GPADC_SW_SELECT_SW_START_CONV0,
PALMAS_GPADC_SW_SELECT_SW_START_CONV0);
if (ret < 0) {
dev_err(adc->dev, "SELECT_SW_START write failed: %d\n", ret);
return ret;
}
ret = wait_for_completion_timeout(&adc->conv_completion,
PALMAS_ADC_CONVERSION_TIMEOUT);
if (ret == 0) {
dev_err(adc->dev, "conversion not completed\n");
return -ETIMEDOUT;
}
ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_SW_CONV0_LSB, &val, 2);
if (ret < 0) {
dev_err(adc->dev, "SW_CONV0_LSB read failed: %d\n", ret);
return ret;
}
}
ret = val & 0xFFF;
return ret;
}
static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc,
int adc_chan, int val)
{
if (!adc->adc_info[adc_chan].is_uncalibrated)
val = (val*1000 - adc->adc_info[adc_chan].offset) /
adc->adc_info[adc_chan].gain_error;
if (val < 0) {
if (val < -10)
dev_err(adc->dev, "Mismatch with calibration var = %d\n", val);
return 0;
}
val = (val * adc->adc_info[adc_chan].gain) / 1000;
return val;
}
/*
* The high and low threshold values are calculated based on the advice given
* in TI Application Report SLIA087A, "Guide to Using the GPADC in PS65903x,
* TPS65917-Q1, TPS65919-Q1, and TPS65916 Devices". This document recommend
* taking ADC tolerances into account and is based on the device integral non-
* linearity (INL), offset error and gain error:
*
* raw high threshold = (ideal threshold + INL) * gain error + offset error
*
* The gain error include both gain error, as specified in the datasheet, and
* the gain error drift. These paramenters vary depending on device and whether
* the the channel is calibrated (trimmed) or not.
*/
static int palmas_gpadc_threshold_with_tolerance(int val, const int INL,
const int gain_error,
const int offset_error)
{
val = ((val + INL) * (1000 + gain_error)) / 1000 + offset_error;
return clamp(val, 0, 0xFFF);
}
/*
* The values below are taken from the datasheet of TWL6035, TWL6037.
* todo: get max INL, gain error, and offset error from OF.
*/
static int palmas_gpadc_get_high_threshold_raw(struct palmas_gpadc *adc,
struct palmas_adc_event *ev)
{
const int adc_chan = ev->channel;
int val = adc->thresholds[adc_chan].high;
/* integral nonlinearity, measured in LSB */
const int max_INL = 2;
/* measured in LSB */
int max_offset_error;
/* 0.2% when calibrated */
int max_gain_error = 2;
val = (val * 1000) / adc->adc_info[adc_chan].gain;
if (adc->adc_info[adc_chan].is_uncalibrated) {
/* 2% worse */
max_gain_error += 20;
max_offset_error = 36;
} else {
val = (val * adc->adc_info[adc_chan].gain_error +
adc->adc_info[adc_chan].offset) /
1000;
max_offset_error = 2;
}
return palmas_gpadc_threshold_with_tolerance(val,
max_INL,
max_gain_error,
max_offset_error);
}
/*
* The values below are taken from the datasheet of TWL6035, TWL6037.
* todo: get min INL, gain error, and offset error from OF.
*/
static int palmas_gpadc_get_low_threshold_raw(struct palmas_gpadc *adc,
struct palmas_adc_event *ev)
{
const int adc_chan = ev->channel;
int val = adc->thresholds[adc_chan].low;
/* integral nonlinearity, measured in LSB */
const int min_INL = -2;
/* measured in LSB */
int min_offset_error;
/* -0.6% when calibrated */
int min_gain_error = -6;
val = (val * 1000) / adc->adc_info[adc_chan].gain;
if (adc->adc_info[adc_chan].is_uncalibrated) {
/* 2% worse */
min_gain_error -= 20;
min_offset_error = -36;
} else {
val = (val * adc->adc_info[adc_chan].gain_error -
adc->adc_info[adc_chan].offset) /
1000;
min_offset_error = -2;
}
return palmas_gpadc_threshold_with_tolerance(val,
min_INL,
min_gain_error,
min_offset_error);
}
static int palmas_gpadc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long mask)
{
struct palmas_gpadc *adc = iio_priv(indio_dev);
int adc_chan = chan->channel;
int ret = 0;
if (adc_chan >= PALMAS_ADC_CH_MAX)
return -EINVAL;
mutex_lock(&adc->lock);
switch (mask) {
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_PROCESSED:
ret = palmas_gpadc_read_prepare(adc, adc_chan);
if (ret < 0)
goto out;
ret = palmas_gpadc_start_conversion(adc, adc_chan);
if (ret < 0) {
dev_err(adc->dev,
"ADC start conversion failed\n");
goto out;
}
if (mask == IIO_CHAN_INFO_PROCESSED)
ret = palmas_gpadc_get_calibrated_code(
adc, adc_chan, ret);
*val = ret;
ret = IIO_VAL_INT;
goto out;
}
mutex_unlock(&adc->lock);
return ret;
out:
palmas_gpadc_read_done(adc, adc_chan);
mutex_unlock(&adc->lock);
return ret;
}
static int palmas_gpadc_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct palmas_gpadc *adc = iio_priv(indio_dev);
int adc_chan = chan->channel;
int ret = 0;
if (adc_chan >= PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH)
return -EINVAL;
mutex_lock(&adc->lock);
if (palmas_gpadc_get_event(adc, adc_chan, dir))
ret = 1;
mutex_unlock(&adc->lock);
return ret;
}
static int palmas_adc_configure_events(struct palmas_gpadc *adc);
static int palmas_adc_reset_events(struct palmas_gpadc *adc);
static int palmas_gpadc_reconfigure_event_channels(struct palmas_gpadc *adc)
{
return (adc->event0.enabled || adc->event1.enabled) ?
palmas_adc_configure_events(adc) :
palmas_adc_reset_events(adc);
}
static int palmas_gpadc_enable_event_config(struct palmas_gpadc *adc,
const struct iio_chan_spec *chan,
enum iio_event_direction dir)
{
struct palmas_adc_event *ev;
int adc_chan = chan->channel;
if (palmas_gpadc_get_event(adc, adc_chan, dir))
/* already enabled */
return 0;
if (adc->event0.channel == -1) {
ev = &adc->event0;
} else if (adc->event1.channel == -1) {
/* event0 has to be the lowest channel */
if (adc_chan < adc->event0.channel) {
adc->event1 = adc->event0;
ev = &adc->event0;
} else {
ev = &adc->event1;
}
} else { /* both AUTO channels already in use */
dev_warn(adc->dev, "event0 - %d, event1 - %d\n",
adc->event0.channel, adc->event1.channel);
return -EBUSY;
}
ev->enabled = true;
ev->channel = adc_chan;
ev->direction = dir;
return palmas_gpadc_reconfigure_event_channels(adc);
}
static int palmas_gpadc_disable_event_config(struct palmas_gpadc *adc,
const struct iio_chan_spec *chan,
enum iio_event_direction dir)
{
int adc_chan = chan->channel;
struct palmas_adc_event *ev = palmas_gpadc_get_event(adc, adc_chan, dir);
if (!ev)
return 0;
if (ev == &adc->event0) {
adc->event0 = adc->event1;
ev = &adc->event1;
}
ev->enabled = false;
ev->channel = -1;
ev->direction = IIO_EV_DIR_NONE;
return palmas_gpadc_reconfigure_event_channels(adc);
}
static int palmas_gpadc_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
struct palmas_gpadc *adc = iio_priv(indio_dev);
int adc_chan = chan->channel;
int ret;
if (adc_chan >= PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH)
return -EINVAL;
mutex_lock(&adc->lock);
if (state)
ret = palmas_gpadc_enable_event_config(adc, chan, dir);
else
ret = palmas_gpadc_disable_event_config(adc, chan, dir);
mutex_unlock(&adc->lock);
return ret;
}
static int palmas_gpadc_read_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
struct palmas_gpadc *adc = iio_priv(indio_dev);
int adc_chan = chan->channel;
int ret;
if (adc_chan >= PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH)
return -EINVAL;
mutex_lock(&adc->lock);
switch (info) {
case IIO_EV_INFO_VALUE:
*val = (dir == IIO_EV_DIR_RISING) ?
adc->thresholds[adc_chan].high :
adc->thresholds[adc_chan].low;
ret = IIO_VAL_INT;
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&adc->lock);
return ret;
}
static int palmas_gpadc_write_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
struct palmas_gpadc *adc = iio_priv(indio_dev);
int adc_chan = chan->channel;
int old;
int ret;
if (adc_chan >= PALMAS_ADC_CH_MAX || type != IIO_EV_TYPE_THRESH)
return -EINVAL;
mutex_lock(&adc->lock);
switch (info) {
case IIO_EV_INFO_VALUE:
if (val < 0 || val > 0xFFF) {
ret = -EINVAL;
goto out_unlock;
}
if (dir == IIO_EV_DIR_RISING) {
old = adc->thresholds[adc_chan].high;
adc->thresholds[adc_chan].high = val;
} else {
old = adc->thresholds[adc_chan].low;
adc->thresholds[adc_chan].low = val;
}
ret = 0;
break;
default:
ret = -EINVAL;
goto out_unlock;
}
if (val != old && palmas_gpadc_get_event(adc, adc_chan, dir))
ret = palmas_gpadc_reconfigure_event_channels(adc);
out_unlock:
mutex_unlock(&adc->lock);
return ret;
}
static const struct iio_info palmas_gpadc_iio_info = {
.read_raw = palmas_gpadc_read_raw,
.read_event_config = palmas_gpadc_read_event_config,
.write_event_config = palmas_gpadc_write_event_config,
.read_event_value = palmas_gpadc_read_event_value,
.write_event_value = palmas_gpadc_write_event_value,
};
static const struct iio_event_spec palmas_gpadc_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
#define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info) \
{ \
.datasheet_name = PALMAS_DATASHEET_NAME(chan), \
.type = _type, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(chan_info), \
.indexed = 1, \
.channel = PALMAS_ADC_CH_##chan, \
.event_spec = palmas_gpadc_events, \
.num_event_specs = ARRAY_SIZE(palmas_gpadc_events) \
}
static const struct iio_chan_spec palmas_gpadc_iio_channel[] = {
PALMAS_ADC_CHAN_IIO(IN0, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
PALMAS_ADC_CHAN_IIO(IN1, IIO_TEMP, IIO_CHAN_INFO_RAW),
PALMAS_ADC_CHAN_IIO(IN2, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
PALMAS_ADC_CHAN_IIO(IN3, IIO_TEMP, IIO_CHAN_INFO_RAW),
PALMAS_ADC_CHAN_IIO(IN4, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
PALMAS_ADC_CHAN_IIO(IN5, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
PALMAS_ADC_CHAN_IIO(IN6, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
PALMAS_ADC_CHAN_IIO(IN7, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
PALMAS_ADC_CHAN_IIO(IN8, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
PALMAS_ADC_CHAN_IIO(IN9, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
PALMAS_ADC_CHAN_IIO(IN10, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
PALMAS_ADC_CHAN_IIO(IN11, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
PALMAS_ADC_CHAN_IIO(IN12, IIO_TEMP, IIO_CHAN_INFO_RAW),
PALMAS_ADC_CHAN_IIO(IN13, IIO_TEMP, IIO_CHAN_INFO_RAW),
PALMAS_ADC_CHAN_IIO(IN14, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
PALMAS_ADC_CHAN_IIO(IN15, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
};
static int palmas_gpadc_get_adc_dt_data(struct platform_device *pdev,
struct palmas_gpadc_platform_data **gpadc_pdata)
{
struct device_node *np = pdev->dev.of_node;
struct palmas_gpadc_platform_data *gp_data;
int ret;
u32 pval;
gp_data = devm_kzalloc(&pdev->dev, sizeof(*gp_data), GFP_KERNEL);
if (!gp_data)
return -ENOMEM;
ret = of_property_read_u32(np, "ti,channel0-current-microamp", &pval);
if (!ret)
gp_data->ch0_current = pval;
ret = of_property_read_u32(np, "ti,channel3-current-microamp", &pval);
if (!ret)
gp_data->ch3_current = pval;
gp_data->extended_delay = of_property_read_bool(np,
"ti,enable-extended-delay");
*gpadc_pdata = gp_data;
return 0;
}
static void palmas_gpadc_reset(void *data)
{
struct palmas_gpadc *adc = data;
if (adc->event0.enabled || adc->event1.enabled)
palmas_adc_reset_events(adc);
}
static int palmas_gpadc_probe(struct platform_device *pdev)
{
struct palmas_gpadc *adc;
struct palmas_platform_data *pdata;
struct palmas_gpadc_platform_data *gpadc_pdata = NULL;
struct iio_dev *indio_dev;
int ret, i;
pdata = dev_get_platdata(pdev->dev.parent);
if (pdata && pdata->gpadc_pdata)
gpadc_pdata = pdata->gpadc_pdata;
if (!gpadc_pdata && pdev->dev.of_node) {
ret = palmas_gpadc_get_adc_dt_data(pdev, &gpadc_pdata);
if (ret < 0)
return ret;
}
if (!gpadc_pdata)
return -EINVAL;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
if (!indio_dev) {
dev_err(&pdev->dev, "iio_device_alloc failed\n");
return -ENOMEM;
}
adc = iio_priv(indio_dev);
adc->dev = &pdev->dev;
adc->palmas = dev_get_drvdata(pdev->dev.parent);
adc->adc_info = palmas_gpadc_info;
mutex_init(&adc->lock);
init_completion(&adc->conv_completion);
platform_set_drvdata(pdev, indio_dev);
adc->auto_conversion_period = gpadc_pdata->auto_conversion_period_ms;
adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ);
if (adc->irq < 0)
return dev_err_probe(adc->dev, adc->irq, "get virq failed\n");
ret = devm_request_threaded_irq(&pdev->dev, adc->irq, NULL,
palmas_gpadc_irq,
IRQF_ONESHOT, dev_name(adc->dev),
adc);
if (ret < 0)
return dev_err_probe(adc->dev, ret,
"request irq %d failed\n", adc->irq);
adc->irq_auto_0 = platform_get_irq(pdev, 1);
if (adc->irq_auto_0 < 0)
return adc->irq_auto_0;
ret = devm_request_threaded_irq(&pdev->dev, adc->irq_auto_0, NULL,
palmas_gpadc_irq_auto, IRQF_ONESHOT,
"palmas-adc-auto-0", indio_dev);
if (ret < 0)
return dev_err_probe(adc->dev, ret,
"request auto0 irq %d failed\n",
adc->irq_auto_0);
adc->irq_auto_1 = platform_get_irq(pdev, 2);
if (adc->irq_auto_1 < 0)
return adc->irq_auto_1;
ret = devm_request_threaded_irq(&pdev->dev, adc->irq_auto_1, NULL,
palmas_gpadc_irq_auto, IRQF_ONESHOT,
"palmas-adc-auto-1", indio_dev);
if (ret < 0)
return dev_err_probe(adc->dev, ret,
"request auto1 irq %d failed\n",
adc->irq_auto_1);
adc->event0.enabled = false;
adc->event0.channel = -1;
adc->event0.direction = IIO_EV_DIR_NONE;
adc->event1.enabled = false;
adc->event1.channel = -1;
adc->event1.direction = IIO_EV_DIR_NONE;
/* set the current source 0 (value 0/5/15/20 uA => 0..3) */
if (gpadc_pdata->ch0_current <= 1)
adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0;
else if (gpadc_pdata->ch0_current <= 5)
adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5;
else if (gpadc_pdata->ch0_current <= 15)
adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15;
else
adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20;
/* set the current source 3 (value 0/10/400/800 uA => 0..3) */
if (gpadc_pdata->ch3_current <= 1)
adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0;
else if (gpadc_pdata->ch3_current <= 10)
adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10;
else if (gpadc_pdata->ch3_current <= 400)
adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400;
else
adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800;
adc->extended_delay = gpadc_pdata->extended_delay;
indio_dev->name = MOD_NAME;
indio_dev->info = &palmas_gpadc_iio_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = palmas_gpadc_iio_channel;
indio_dev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel);
ret = devm_iio_device_register(&pdev->dev, indio_dev);
if (ret < 0)
return dev_err_probe(adc->dev, ret,
"iio_device_register() failed\n");
device_set_wakeup_capable(&pdev->dev, 1);
for (i = 0; i < PALMAS_ADC_CH_MAX; i++) {
if (!(adc->adc_info[i].is_uncalibrated))
palmas_gpadc_calibrate(adc, i);
}
ret = devm_add_action(&pdev->dev, palmas_gpadc_reset, adc);
if (ret)
return ret;
return 0;
}
static int palmas_adc_configure_events(struct palmas_gpadc *adc)
{
int adc_period, conv;
int i;
int ch0 = 0, ch1 = 0;
int thres;
int ret;
adc_period = adc->auto_conversion_period;
for (i = 0; i < 16; ++i) {
if (((1000 * (1 << i)) / 32) >= adc_period)
break;
}
if (i > 0)
i--;
adc_period = i;
ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_AUTO_CTRL,
PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK,
adc_period);
if (ret < 0) {
dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
return ret;
}
conv = 0;
if (adc->event0.enabled) {
struct palmas_adc_event *ev = &adc->event0;
int polarity;
ch0 = ev->channel;
conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN;
switch (ev->direction) {
case IIO_EV_DIR_RISING:
thres = palmas_gpadc_get_high_threshold_raw(adc, ev);
polarity = 0;
break;
case IIO_EV_DIR_FALLING:
thres = palmas_gpadc_get_low_threshold_raw(adc, ev);
polarity = PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL;
break;
default:
return -EINVAL;
}
ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF);
if (ret < 0) {
dev_err(adc->dev,
"THRES_CONV0_LSB write failed: %d\n", ret);
return ret;
}
ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_THRES_CONV0_MSB,
((thres >> 8) & 0xF) | polarity);
if (ret < 0) {
dev_err(adc->dev,
"THRES_CONV0_MSB write failed: %d\n", ret);
return ret;
}
}
if (adc->event1.enabled) {
struct palmas_adc_event *ev = &adc->event1;
int polarity;
ch1 = ev->channel;
conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN;
switch (ev->direction) {
case IIO_EV_DIR_RISING:
thres = palmas_gpadc_get_high_threshold_raw(adc, ev);
polarity = 0;
break;
case IIO_EV_DIR_FALLING:
thres = palmas_gpadc_get_low_threshold_raw(adc, ev);
polarity = PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL;
break;
default:
return -EINVAL;
}
ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF);
if (ret < 0) {
dev_err(adc->dev,
"THRES_CONV1_LSB write failed: %d\n", ret);
return ret;
}
ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_THRES_CONV1_MSB,
((thres >> 8) & 0xF) | polarity);
if (ret < 0) {
dev_err(adc->dev,
"THRES_CONV1_MSB write failed: %d\n", ret);
return ret;
}
}
ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0);
if (ret < 0) {
dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
return ret;
}
ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_AUTO_CTRL,
PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN |
PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv);
if (ret < 0)
dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
return ret;
}
static int palmas_adc_reset_events(struct palmas_gpadc *adc)
{
int ret;
ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
PALMAS_GPADC_AUTO_SELECT, 0);
if (ret < 0) {
dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
return ret;
}
ret = palmas_disable_auto_conversion(adc);
if (ret < 0)
dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret);
return ret;
}
static int palmas_gpadc_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct palmas_gpadc *adc = iio_priv(indio_dev);
if (!device_may_wakeup(dev))
return 0;
if (adc->event0.enabled)
enable_irq_wake(adc->irq_auto_0);
if (adc->event1.enabled)
enable_irq_wake(adc->irq_auto_1);
return 0;
}
static int palmas_gpadc_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct palmas_gpadc *adc = iio_priv(indio_dev);
if (!device_may_wakeup(dev))
return 0;
if (adc->event0.enabled)
disable_irq_wake(adc->irq_auto_0);
if (adc->event1.enabled)
disable_irq_wake(adc->irq_auto_1);
return 0;
};
static DEFINE_SIMPLE_DEV_PM_OPS(palmas_pm_ops, palmas_gpadc_suspend,
palmas_gpadc_resume);
static const struct of_device_id of_palmas_gpadc_match_tbl[] = {
{ .compatible = "ti,palmas-gpadc", },
{ /* end */ }
};
MODULE_DEVICE_TABLE(of, of_palmas_gpadc_match_tbl);
static struct platform_driver palmas_gpadc_driver = {
.probe = palmas_gpadc_probe,
.driver = {
.name = MOD_NAME,
.pm = pm_sleep_ptr(&palmas_pm_ops),
.of_match_table = of_palmas_gpadc_match_tbl,
},
};
module_platform_driver(palmas_gpadc_driver);
MODULE_DESCRIPTION("palmas GPADC driver");
MODULE_AUTHOR("Pradeep Goudagunta<[email protected]>");
MODULE_ALIAS("platform:palmas-gpadc");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/palmas_gpadc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs
*
* Copyright (c) 2020 AVL DiTEST GmbH
* Tomislav Denis <[email protected]>
*
* Datasheet: https://www.ti.com/lit/ds/symlink/ads131e08.pdf
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <asm/unaligned.h>
/* Commands */
#define ADS131E08_CMD_RESET 0x06
#define ADS131E08_CMD_START 0x08
#define ADS131E08_CMD_STOP 0x0A
#define ADS131E08_CMD_OFFSETCAL 0x1A
#define ADS131E08_CMD_SDATAC 0x11
#define ADS131E08_CMD_RDATA 0x12
#define ADS131E08_CMD_RREG(r) (BIT(5) | (r & GENMASK(4, 0)))
#define ADS131E08_CMD_WREG(r) (BIT(6) | (r & GENMASK(4, 0)))
/* Registers */
#define ADS131E08_ADR_CFG1R 0x01
#define ADS131E08_ADR_CFG3R 0x03
#define ADS131E08_ADR_CH0R 0x05
/* Configuration register 1 */
#define ADS131E08_CFG1R_DR_MASK GENMASK(2, 0)
/* Configuration register 3 */
#define ADS131E08_CFG3R_PDB_REFBUF_MASK BIT(7)
#define ADS131E08_CFG3R_VREF_4V_MASK BIT(5)
/* Channel settings register */
#define ADS131E08_CHR_GAIN_MASK GENMASK(6, 4)
#define ADS131E08_CHR_MUX_MASK GENMASK(2, 0)
#define ADS131E08_CHR_PWD_MASK BIT(7)
/* ADC misc */
#define ADS131E08_DEFAULT_DATA_RATE 1
#define ADS131E08_DEFAULT_PGA_GAIN 1
#define ADS131E08_DEFAULT_MUX 0
#define ADS131E08_VREF_2V4_mV 2400
#define ADS131E08_VREF_4V_mV 4000
#define ADS131E08_WAIT_RESET_CYCLES 18
#define ADS131E08_WAIT_SDECODE_CYCLES 4
#define ADS131E08_WAIT_OFFSETCAL_MS 153
#define ADS131E08_MAX_SETTLING_TIME_MS 6
#define ADS131E08_NUM_STATUS_BYTES 3
#define ADS131E08_NUM_DATA_BYTES_MAX 24
#define ADS131E08_NUM_DATA_BYTES(dr) (((dr) >= 32) ? 2 : 3)
#define ADS131E08_NUM_DATA_BITS(dr) (ADS131E08_NUM_DATA_BYTES(dr) * 8)
#define ADS131E08_NUM_STORAGE_BYTES 4
enum ads131e08_ids {
ads131e04,
ads131e06,
ads131e08,
};
struct ads131e08_info {
unsigned int max_channels;
const char *name;
};
struct ads131e08_channel_config {
unsigned int pga_gain;
unsigned int mux;
};
struct ads131e08_state {
const struct ads131e08_info *info;
struct spi_device *spi;
struct iio_trigger *trig;
struct clk *adc_clk;
struct regulator *vref_reg;
struct ads131e08_channel_config *channel_config;
unsigned int data_rate;
unsigned int vref_mv;
unsigned int sdecode_delay_us;
unsigned int reset_delay_us;
unsigned int readback_len;
struct completion completion;
struct {
u8 data[ADS131E08_NUM_DATA_BYTES_MAX];
s64 ts __aligned(8);
} tmp_buf;
u8 tx_buf[3] __aligned(IIO_DMA_MINALIGN);
/*
* Add extra one padding byte to be able to access the last channel
* value using u32 pointer
*/
u8 rx_buf[ADS131E08_NUM_STATUS_BYTES +
ADS131E08_NUM_DATA_BYTES_MAX + 1];
};
static const struct ads131e08_info ads131e08_info_tbl[] = {
[ads131e04] = {
.max_channels = 4,
.name = "ads131e04",
},
[ads131e06] = {
.max_channels = 6,
.name = "ads131e06",
},
[ads131e08] = {
.max_channels = 8,
.name = "ads131e08",
},
};
struct ads131e08_data_rate_desc {
unsigned int rate; /* data rate in kSPS */
u8 reg; /* reg value */
};
static const struct ads131e08_data_rate_desc ads131e08_data_rate_tbl[] = {
{ .rate = 64, .reg = 0x00 },
{ .rate = 32, .reg = 0x01 },
{ .rate = 16, .reg = 0x02 },
{ .rate = 8, .reg = 0x03 },
{ .rate = 4, .reg = 0x04 },
{ .rate = 2, .reg = 0x05 },
{ .rate = 1, .reg = 0x06 },
};
struct ads131e08_pga_gain_desc {
unsigned int gain; /* PGA gain value */
u8 reg; /* field value */
};
static const struct ads131e08_pga_gain_desc ads131e08_pga_gain_tbl[] = {
{ .gain = 1, .reg = 0x01 },
{ .gain = 2, .reg = 0x02 },
{ .gain = 4, .reg = 0x04 },
{ .gain = 8, .reg = 0x05 },
{ .gain = 12, .reg = 0x06 },
};
static const u8 ads131e08_valid_channel_mux_values[] = { 0, 1, 3, 4 };
static int ads131e08_exec_cmd(struct ads131e08_state *st, u8 cmd)
{
int ret;
ret = spi_write_then_read(st->spi, &cmd, 1, NULL, 0);
if (ret)
dev_err(&st->spi->dev, "Exec cmd(%02x) failed\n", cmd);
return ret;
}
static int ads131e08_read_reg(struct ads131e08_state *st, u8 reg)
{
int ret;
struct spi_transfer transfer[] = {
{
.tx_buf = &st->tx_buf,
.len = 2,
.delay = {
.value = st->sdecode_delay_us,
.unit = SPI_DELAY_UNIT_USECS,
},
}, {
.rx_buf = &st->rx_buf,
.len = 1,
},
};
st->tx_buf[0] = ADS131E08_CMD_RREG(reg);
st->tx_buf[1] = 0;
ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
if (ret) {
dev_err(&st->spi->dev, "Read register failed\n");
return ret;
}
return st->rx_buf[0];
}
static int ads131e08_write_reg(struct ads131e08_state *st, u8 reg, u8 value)
{
int ret;
struct spi_transfer transfer[] = {
{
.tx_buf = &st->tx_buf,
.len = 3,
.delay = {
.value = st->sdecode_delay_us,
.unit = SPI_DELAY_UNIT_USECS,
},
}
};
st->tx_buf[0] = ADS131E08_CMD_WREG(reg);
st->tx_buf[1] = 0;
st->tx_buf[2] = value;
ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
if (ret)
dev_err(&st->spi->dev, "Write register failed\n");
return ret;
}
static int ads131e08_read_data(struct ads131e08_state *st, int rx_len)
{
int ret;
struct spi_transfer transfer[] = {
{
.tx_buf = &st->tx_buf,
.len = 1,
}, {
.rx_buf = &st->rx_buf,
.len = rx_len,
},
};
st->tx_buf[0] = ADS131E08_CMD_RDATA;
ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
if (ret)
dev_err(&st->spi->dev, "Read data failed\n");
return ret;
}
static int ads131e08_set_data_rate(struct ads131e08_state *st, int data_rate)
{
int i, reg, ret;
for (i = 0; i < ARRAY_SIZE(ads131e08_data_rate_tbl); i++) {
if (ads131e08_data_rate_tbl[i].rate == data_rate)
break;
}
if (i == ARRAY_SIZE(ads131e08_data_rate_tbl)) {
dev_err(&st->spi->dev, "invalid data rate value\n");
return -EINVAL;
}
reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG1R);
if (reg < 0)
return reg;
reg &= ~ADS131E08_CFG1R_DR_MASK;
reg |= FIELD_PREP(ADS131E08_CFG1R_DR_MASK,
ads131e08_data_rate_tbl[i].reg);
ret = ads131e08_write_reg(st, ADS131E08_ADR_CFG1R, reg);
if (ret)
return ret;
st->data_rate = data_rate;
st->readback_len = ADS131E08_NUM_STATUS_BYTES +
ADS131E08_NUM_DATA_BYTES(st->data_rate) *
st->info->max_channels;
return 0;
}
static int ads131e08_pga_gain_to_field_value(struct ads131e08_state *st,
unsigned int pga_gain)
{
int i;
for (i = 0; i < ARRAY_SIZE(ads131e08_pga_gain_tbl); i++) {
if (ads131e08_pga_gain_tbl[i].gain == pga_gain)
break;
}
if (i == ARRAY_SIZE(ads131e08_pga_gain_tbl)) {
dev_err(&st->spi->dev, "invalid PGA gain value\n");
return -EINVAL;
}
return ads131e08_pga_gain_tbl[i].reg;
}
static int ads131e08_set_pga_gain(struct ads131e08_state *st,
unsigned int channel, unsigned int pga_gain)
{
int field_value, reg;
field_value = ads131e08_pga_gain_to_field_value(st, pga_gain);
if (field_value < 0)
return field_value;
reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
if (reg < 0)
return reg;
reg &= ~ADS131E08_CHR_GAIN_MASK;
reg |= FIELD_PREP(ADS131E08_CHR_GAIN_MASK, field_value);
return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
}
static int ads131e08_validate_channel_mux(struct ads131e08_state *st,
unsigned int mux)
{
int i;
for (i = 0; i < ARRAY_SIZE(ads131e08_valid_channel_mux_values); i++) {
if (ads131e08_valid_channel_mux_values[i] == mux)
break;
}
if (i == ARRAY_SIZE(ads131e08_valid_channel_mux_values)) {
dev_err(&st->spi->dev, "invalid channel mux value\n");
return -EINVAL;
}
return 0;
}
static int ads131e08_set_channel_mux(struct ads131e08_state *st,
unsigned int channel, unsigned int mux)
{
int reg;
reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
if (reg < 0)
return reg;
reg &= ~ADS131E08_CHR_MUX_MASK;
reg |= FIELD_PREP(ADS131E08_CHR_MUX_MASK, mux);
return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
}
static int ads131e08_power_down_channel(struct ads131e08_state *st,
unsigned int channel, bool value)
{
int reg;
reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
if (reg < 0)
return reg;
reg &= ~ADS131E08_CHR_PWD_MASK;
reg |= FIELD_PREP(ADS131E08_CHR_PWD_MASK, value);
return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
}
static int ads131e08_config_reference_voltage(struct ads131e08_state *st)
{
int reg;
reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG3R);
if (reg < 0)
return reg;
reg &= ~ADS131E08_CFG3R_PDB_REFBUF_MASK;
if (!st->vref_reg) {
reg |= FIELD_PREP(ADS131E08_CFG3R_PDB_REFBUF_MASK, 1);
reg &= ~ADS131E08_CFG3R_VREF_4V_MASK;
reg |= FIELD_PREP(ADS131E08_CFG3R_VREF_4V_MASK,
st->vref_mv == ADS131E08_VREF_4V_mV);
}
return ads131e08_write_reg(st, ADS131E08_ADR_CFG3R, reg);
}
static int ads131e08_initial_config(struct iio_dev *indio_dev)
{
const struct iio_chan_spec *channel = indio_dev->channels;
struct ads131e08_state *st = iio_priv(indio_dev);
unsigned long active_channels = 0;
int ret, i;
ret = ads131e08_exec_cmd(st, ADS131E08_CMD_RESET);
if (ret)
return ret;
udelay(st->reset_delay_us);
/* Disable read data in continuous mode (enabled by default) */
ret = ads131e08_exec_cmd(st, ADS131E08_CMD_SDATAC);
if (ret)
return ret;
ret = ads131e08_set_data_rate(st, ADS131E08_DEFAULT_DATA_RATE);
if (ret)
return ret;
ret = ads131e08_config_reference_voltage(st);
if (ret)
return ret;
for (i = 0; i < indio_dev->num_channels; i++) {
ret = ads131e08_set_pga_gain(st, channel->channel,
st->channel_config[i].pga_gain);
if (ret)
return ret;
ret = ads131e08_set_channel_mux(st, channel->channel,
st->channel_config[i].mux);
if (ret)
return ret;
active_channels |= BIT(channel->channel);
channel++;
}
/* Power down unused channels */
for_each_clear_bit(i, &active_channels, st->info->max_channels) {
ret = ads131e08_power_down_channel(st, i, true);
if (ret)
return ret;
}
/* Request channel offset calibration */
ret = ads131e08_exec_cmd(st, ADS131E08_CMD_OFFSETCAL);
if (ret)
return ret;
/*
* Channel offset calibration is triggered with the first START
* command. Since calibration takes more time than settling operation,
* this causes timeout error when command START is sent first
* time (e.g. first call of the ads131e08_read_direct method).
* To avoid this problem offset calibration is triggered here.
*/
ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);
if (ret)
return ret;
msleep(ADS131E08_WAIT_OFFSETCAL_MS);
return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);
}
static int ads131e08_pool_data(struct ads131e08_state *st)
{
unsigned long timeout;
int ret;
reinit_completion(&st->completion);
ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);
if (ret)
return ret;
timeout = msecs_to_jiffies(ADS131E08_MAX_SETTLING_TIME_MS);
ret = wait_for_completion_timeout(&st->completion, timeout);
if (!ret)
return -ETIMEDOUT;
ret = ads131e08_read_data(st, st->readback_len);
if (ret)
return ret;
return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);
}
static int ads131e08_read_direct(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *value)
{
struct ads131e08_state *st = iio_priv(indio_dev);
u8 num_bits, *src;
int ret;
ret = ads131e08_pool_data(st);
if (ret)
return ret;
src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES +
channel->channel * ADS131E08_NUM_DATA_BYTES(st->data_rate);
num_bits = ADS131E08_NUM_DATA_BITS(st->data_rate);
*value = sign_extend32(get_unaligned_be32(src) >> (32 - num_bits), num_bits - 1);
return 0;
}
static int ads131e08_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *value,
int *value2, long mask)
{
struct ads131e08_state *st = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = ads131e08_read_direct(indio_dev, channel, value);
iio_device_release_direct_mode(indio_dev);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
if (st->vref_reg) {
ret = regulator_get_voltage(st->vref_reg);
if (ret < 0)
return ret;
*value = ret / 1000;
} else {
*value = st->vref_mv;
}
*value /= st->channel_config[channel->address].pga_gain;
*value2 = ADS131E08_NUM_DATA_BITS(st->data_rate) - 1;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_SAMP_FREQ:
*value = st->data_rate;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int ads131e08_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int value,
int value2, long mask)
{
struct ads131e08_state *st = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = ads131e08_set_data_rate(st, value);
iio_device_release_direct_mode(indio_dev);
return ret;
default:
return -EINVAL;
}
}
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("1 2 4 8 16 32 64");
static struct attribute *ads131e08_attributes[] = {
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL
};
static const struct attribute_group ads131e08_attribute_group = {
.attrs = ads131e08_attributes,
};
static int ads131e08_debugfs_reg_access(struct iio_dev *indio_dev,
unsigned int reg, unsigned int writeval, unsigned int *readval)
{
struct ads131e08_state *st = iio_priv(indio_dev);
if (readval) {
int ret = ads131e08_read_reg(st, reg);
*readval = ret;
return ret;
}
return ads131e08_write_reg(st, reg, writeval);
}
static const struct iio_info ads131e08_iio_info = {
.read_raw = ads131e08_read_raw,
.write_raw = ads131e08_write_raw,
.attrs = &ads131e08_attribute_group,
.debugfs_reg_access = &ads131e08_debugfs_reg_access,
};
static int ads131e08_set_trigger_state(struct iio_trigger *trig, bool state)
{
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
struct ads131e08_state *st = iio_priv(indio_dev);
u8 cmd = state ? ADS131E08_CMD_START : ADS131E08_CMD_STOP;
return ads131e08_exec_cmd(st, cmd);
}
static const struct iio_trigger_ops ads131e08_trigger_ops = {
.set_trigger_state = &ads131e08_set_trigger_state,
.validate_device = &iio_trigger_validate_own_device,
};
static irqreturn_t ads131e08_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct ads131e08_state *st = iio_priv(indio_dev);
unsigned int chn, i = 0;
u8 *src, *dest;
int ret;
/*
* The number of data bits per channel depends on the data rate.
* For 32 and 64 ksps data rates, number of data bits per channel
* is 16. This case is not compliant with used (fixed) scan element
* type (be:s24/32>>8). So we use a little tweak to pack properly
* 16 bits of data into the buffer.
*/
unsigned int num_bytes = ADS131E08_NUM_DATA_BYTES(st->data_rate);
u8 tweek_offset = num_bytes == 2 ? 1 : 0;
if (iio_trigger_using_own(indio_dev))
ret = ads131e08_read_data(st, st->readback_len);
else
ret = ads131e08_pool_data(st);
if (ret)
goto out;
for_each_set_bit(chn, indio_dev->active_scan_mask, indio_dev->masklength) {
src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES + chn * num_bytes;
dest = st->tmp_buf.data + i * ADS131E08_NUM_STORAGE_BYTES;
/*
* Tweek offset is 0:
* +---+---+---+---+
* |D0 |D1 |D2 | X | (3 data bytes)
* +---+---+---+---+
* a+0 a+1 a+2 a+3
*
* Tweek offset is 1:
* +---+---+---+---+
* |P0 |D0 |D1 | X | (one padding byte and 2 data bytes)
* +---+---+---+---+
* a+0 a+1 a+2 a+3
*/
memcpy(dest + tweek_offset, src, num_bytes);
/*
* Data conversion from 16 bits of data to 24 bits of data
* is done by sign extension (properly filling padding byte).
*/
if (tweek_offset)
*dest = *src & BIT(7) ? 0xff : 0x00;
i++;
}
iio_push_to_buffers_with_timestamp(indio_dev, st->tmp_buf.data,
iio_get_time_ns(indio_dev));
out:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static irqreturn_t ads131e08_interrupt(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct ads131e08_state *st = iio_priv(indio_dev);
if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev))
iio_trigger_poll(st->trig);
else
complete(&st->completion);
return IRQ_HANDLED;
}
static int ads131e08_alloc_channels(struct iio_dev *indio_dev)
{
struct ads131e08_state *st = iio_priv(indio_dev);
struct ads131e08_channel_config *channel_config;
struct device *dev = &st->spi->dev;
struct iio_chan_spec *channels;
struct fwnode_handle *node;
unsigned int channel, tmp;
int num_channels, i, ret;
ret = device_property_read_u32(dev, "ti,vref-internal", &tmp);
if (ret)
tmp = 0;
switch (tmp) {
case 0:
st->vref_mv = ADS131E08_VREF_2V4_mV;
break;
case 1:
st->vref_mv = ADS131E08_VREF_4V_mV;
break;
default:
dev_err(&st->spi->dev, "invalid internal voltage reference\n");
return -EINVAL;
}
num_channels = device_get_child_node_count(dev);
if (num_channels == 0) {
dev_err(&st->spi->dev, "no channel children\n");
return -ENODEV;
}
if (num_channels > st->info->max_channels) {
dev_err(&st->spi->dev, "num of channel children out of range\n");
return -EINVAL;
}
channels = devm_kcalloc(&st->spi->dev, num_channels,
sizeof(*channels), GFP_KERNEL);
if (!channels)
return -ENOMEM;
channel_config = devm_kcalloc(&st->spi->dev, num_channels,
sizeof(*channel_config), GFP_KERNEL);
if (!channel_config)
return -ENOMEM;
i = 0;
device_for_each_child_node(dev, node) {
ret = fwnode_property_read_u32(node, "reg", &channel);
if (ret)
goto err_child_out;
ret = fwnode_property_read_u32(node, "ti,gain", &tmp);
if (ret) {
channel_config[i].pga_gain = ADS131E08_DEFAULT_PGA_GAIN;
} else {
ret = ads131e08_pga_gain_to_field_value(st, tmp);
if (ret < 0)
goto err_child_out;
channel_config[i].pga_gain = tmp;
}
ret = fwnode_property_read_u32(node, "ti,mux", &tmp);
if (ret) {
channel_config[i].mux = ADS131E08_DEFAULT_MUX;
} else {
ret = ads131e08_validate_channel_mux(st, tmp);
if (ret)
goto err_child_out;
channel_config[i].mux = tmp;
}
channels[i].type = IIO_VOLTAGE;
channels[i].indexed = 1;
channels[i].channel = channel;
channels[i].address = i;
channels[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE);
channels[i].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ);
channels[i].scan_index = channel;
channels[i].scan_type.sign = 's';
channels[i].scan_type.realbits = 24;
channels[i].scan_type.storagebits = 32;
channels[i].scan_type.shift = 8;
channels[i].scan_type.endianness = IIO_BE;
i++;
}
indio_dev->channels = channels;
indio_dev->num_channels = num_channels;
st->channel_config = channel_config;
return 0;
err_child_out:
fwnode_handle_put(node);
return ret;
}
static void ads131e08_regulator_disable(void *data)
{
struct ads131e08_state *st = data;
regulator_disable(st->vref_reg);
}
static int ads131e08_probe(struct spi_device *spi)
{
const struct ads131e08_info *info;
struct ads131e08_state *st;
struct iio_dev *indio_dev;
unsigned long adc_clk_hz;
unsigned long adc_clk_ns;
int ret;
info = device_get_match_data(&spi->dev);
if (!info)
info = (void *)spi_get_device_id(spi)->driver_data;
if (!info) {
dev_err(&spi->dev, "failed to get match data\n");
return -ENODEV;
}
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev) {
dev_err(&spi->dev, "failed to allocate IIO device\n");
return -ENOMEM;
}
st = iio_priv(indio_dev);
st->info = info;
st->spi = spi;
ret = ads131e08_alloc_channels(indio_dev);
if (ret)
return ret;
indio_dev->name = st->info->name;
indio_dev->info = &ads131e08_iio_info;
indio_dev->modes = INDIO_DIRECT_MODE;
init_completion(&st->completion);
if (spi->irq) {
ret = devm_request_irq(&spi->dev, spi->irq,
ads131e08_interrupt,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
spi->dev.driver->name, indio_dev);
if (ret)
return dev_err_probe(&spi->dev, ret,
"request irq failed\n");
} else {
dev_err(&spi->dev, "data ready IRQ missing\n");
return -ENODEV;
}
st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
indio_dev->name, iio_device_id(indio_dev));
if (!st->trig) {
dev_err(&spi->dev, "failed to allocate IIO trigger\n");
return -ENOMEM;
}
st->trig->ops = &ads131e08_trigger_ops;
st->trig->dev.parent = &spi->dev;
iio_trigger_set_drvdata(st->trig, indio_dev);
ret = devm_iio_trigger_register(&spi->dev, st->trig);
if (ret) {
dev_err(&spi->dev, "failed to register IIO trigger\n");
return -ENOMEM;
}
indio_dev->trig = iio_trigger_get(st->trig);
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
NULL, &ads131e08_trigger_handler, NULL);
if (ret) {
dev_err(&spi->dev, "failed to setup IIO buffer\n");
return ret;
}
st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref");
if (!IS_ERR(st->vref_reg)) {
ret = regulator_enable(st->vref_reg);
if (ret) {
dev_err(&spi->dev,
"failed to enable external vref supply\n");
return ret;
}
ret = devm_add_action_or_reset(&spi->dev, ads131e08_regulator_disable, st);
if (ret)
return ret;
} else {
if (PTR_ERR(st->vref_reg) != -ENODEV)
return PTR_ERR(st->vref_reg);
st->vref_reg = NULL;
}
st->adc_clk = devm_clk_get_enabled(&spi->dev, "adc-clk");
if (IS_ERR(st->adc_clk))
return dev_err_probe(&spi->dev, PTR_ERR(st->adc_clk),
"failed to get the ADC clock\n");
adc_clk_hz = clk_get_rate(st->adc_clk);
if (!adc_clk_hz) {
dev_err(&spi->dev, "failed to get the ADC clock rate\n");
return -EINVAL;
}
adc_clk_ns = NSEC_PER_SEC / adc_clk_hz;
st->sdecode_delay_us = DIV_ROUND_UP(
ADS131E08_WAIT_SDECODE_CYCLES * adc_clk_ns, NSEC_PER_USEC);
st->reset_delay_us = DIV_ROUND_UP(
ADS131E08_WAIT_RESET_CYCLES * adc_clk_ns, NSEC_PER_USEC);
ret = ads131e08_initial_config(indio_dev);
if (ret) {
dev_err(&spi->dev, "initial configuration failed\n");
return ret;
}
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct of_device_id ads131e08_of_match[] = {
{ .compatible = "ti,ads131e04",
.data = &ads131e08_info_tbl[ads131e04], },
{ .compatible = "ti,ads131e06",
.data = &ads131e08_info_tbl[ads131e06], },
{ .compatible = "ti,ads131e08",
.data = &ads131e08_info_tbl[ads131e08], },
{}
};
MODULE_DEVICE_TABLE(of, ads131e08_of_match);
static const struct spi_device_id ads131e08_ids[] = {
{ "ads131e04", (kernel_ulong_t)&ads131e08_info_tbl[ads131e04] },
{ "ads131e06", (kernel_ulong_t)&ads131e08_info_tbl[ads131e06] },
{ "ads131e08", (kernel_ulong_t)&ads131e08_info_tbl[ads131e08] },
{}
};
MODULE_DEVICE_TABLE(spi, ads131e08_ids);
static struct spi_driver ads131e08_driver = {
.driver = {
.name = "ads131e08",
.of_match_table = ads131e08_of_match,
},
.probe = ads131e08_probe,
.id_table = ads131e08_ids,
};
module_spi_driver(ads131e08_driver);
MODULE_AUTHOR("Tomislav Denis <[email protected]>");
MODULE_DESCRIPTION("Driver for ADS131E0x ADC family");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ti-ads131e08.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* lpc32xx_adc.c - Support for ADC in LPC32XX
*
* 3-channel, 10-bit ADC
*
* Copyright (C) 2011, 2012 Roland Stigge <[email protected]>
*/
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/iio/iio.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
/*
* LPC32XX registers definitions
*/
#define LPC32XXAD_SELECT(x) ((x) + 0x04)
#define LPC32XXAD_CTRL(x) ((x) + 0x08)
#define LPC32XXAD_VALUE(x) ((x) + 0x48)
/* Bit definitions for LPC32XXAD_SELECT: */
/* constant, always write this value! */
#define LPC32XXAD_REFm 0x00000200
/* constant, always write this value! */
#define LPC32XXAD_REFp 0x00000080
/* multiple of this is the channel number: 0, 1, 2 */
#define LPC32XXAD_IN 0x00000010
/* constant, always write this value! */
#define LPC32XXAD_INTERNAL 0x00000004
/* Bit definitions for LPC32XXAD_CTRL: */
#define LPC32XXAD_STROBE 0x00000002
#define LPC32XXAD_PDN_CTRL 0x00000004
/* Bit definitions for LPC32XXAD_VALUE: */
#define LPC32XXAD_VALUE_MASK 0x000003FF
#define LPC32XXAD_NAME "lpc32xx-adc"
struct lpc32xx_adc_state {
void __iomem *adc_base;
struct clk *clk;
struct completion completion;
struct regulator *vref;
/* lock to protect against multiple access to the device */
struct mutex lock;
u32 value;
};
static int lpc32xx_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
struct lpc32xx_adc_state *st = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&st->lock);
ret = clk_prepare_enable(st->clk);
if (ret) {
mutex_unlock(&st->lock);
return ret;
}
/* Measurement setup */
__raw_writel(LPC32XXAD_INTERNAL | (chan->address) |
LPC32XXAD_REFp | LPC32XXAD_REFm,
LPC32XXAD_SELECT(st->adc_base));
/* Trigger conversion */
__raw_writel(LPC32XXAD_PDN_CTRL | LPC32XXAD_STROBE,
LPC32XXAD_CTRL(st->adc_base));
wait_for_completion(&st->completion); /* set by ISR */
clk_disable_unprepare(st->clk);
*val = st->value;
mutex_unlock(&st->lock);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = regulator_get_voltage(st->vref) / 1000;
*val2 = 10;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
}
static const struct iio_info lpc32xx_adc_iio_info = {
.read_raw = &lpc32xx_read_raw,
};
#define LPC32XX_ADC_CHANNEL_BASE(_index) \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = _index, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.address = LPC32XXAD_IN * _index, \
.scan_index = _index,
#define LPC32XX_ADC_CHANNEL(_index) { \
LPC32XX_ADC_CHANNEL_BASE(_index) \
}
#define LPC32XX_ADC_SCALE_CHANNEL(_index) { \
LPC32XX_ADC_CHANNEL_BASE(_index) \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
}
static const struct iio_chan_spec lpc32xx_adc_iio_channels[] = {
LPC32XX_ADC_CHANNEL(0),
LPC32XX_ADC_CHANNEL(1),
LPC32XX_ADC_CHANNEL(2),
};
static const struct iio_chan_spec lpc32xx_adc_iio_scale_channels[] = {
LPC32XX_ADC_SCALE_CHANNEL(0),
LPC32XX_ADC_SCALE_CHANNEL(1),
LPC32XX_ADC_SCALE_CHANNEL(2),
};
static irqreturn_t lpc32xx_adc_isr(int irq, void *dev_id)
{
struct lpc32xx_adc_state *st = dev_id;
/* Read value and clear irq */
st->value = __raw_readl(LPC32XXAD_VALUE(st->adc_base)) &
LPC32XXAD_VALUE_MASK;
complete(&st->completion);
return IRQ_HANDLED;
}
static int lpc32xx_adc_probe(struct platform_device *pdev)
{
struct lpc32xx_adc_state *st = NULL;
struct resource *res;
int retval = -ENODEV;
struct iio_dev *iodev = NULL;
int irq;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "failed to get platform I/O memory\n");
return -ENXIO;
}
iodev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
if (!iodev)
return -ENOMEM;
st = iio_priv(iodev);
st->adc_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!st->adc_base) {
dev_err(&pdev->dev, "failed mapping memory\n");
return -EBUSY;
}
st->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(st->clk)) {
dev_err(&pdev->dev, "failed getting clock\n");
return PTR_ERR(st->clk);
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
retval = devm_request_irq(&pdev->dev, irq, lpc32xx_adc_isr, 0,
LPC32XXAD_NAME, st);
if (retval < 0) {
dev_err(&pdev->dev, "failed requesting interrupt\n");
return retval;
}
st->vref = devm_regulator_get(&pdev->dev, "vref");
if (IS_ERR(st->vref)) {
iodev->channels = lpc32xx_adc_iio_channels;
dev_info(&pdev->dev,
"Missing vref regulator: No scaling available\n");
} else {
iodev->channels = lpc32xx_adc_iio_scale_channels;
}
platform_set_drvdata(pdev, iodev);
init_completion(&st->completion);
iodev->name = LPC32XXAD_NAME;
iodev->info = &lpc32xx_adc_iio_info;
iodev->modes = INDIO_DIRECT_MODE;
iodev->num_channels = ARRAY_SIZE(lpc32xx_adc_iio_channels);
mutex_init(&st->lock);
retval = devm_iio_device_register(&pdev->dev, iodev);
if (retval)
return retval;
dev_info(&pdev->dev, "LPC32XX ADC driver loaded, IRQ %d\n", irq);
return 0;
}
static const struct of_device_id lpc32xx_adc_match[] = {
{ .compatible = "nxp,lpc3220-adc" },
{},
};
MODULE_DEVICE_TABLE(of, lpc32xx_adc_match);
static struct platform_driver lpc32xx_adc_driver = {
.probe = lpc32xx_adc_probe,
.driver = {
.name = LPC32XXAD_NAME,
.of_match_table = lpc32xx_adc_match,
},
};
module_platform_driver(lpc32xx_adc_driver);
MODULE_AUTHOR("Roland Stigge <[email protected]>");
MODULE_DESCRIPTION("LPC32XX ADC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/adc/lpc32xx_adc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* This file is part the core part STM32 DFSDM driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Arnaud Pouliquen <[email protected]> for STMicroelectronics.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "stm32-dfsdm.h"
/**
* struct stm32_dfsdm_dev_data - DFSDM compatible configuration data
* @ipid: DFSDM identification number. Used only if hardware provides identification registers
* @num_filters: DFSDM number of filters. Unused if identification registers are available
* @num_channels: DFSDM number of channels. Unused if identification registers are available
* @regmap_cfg: SAI register map configuration pointer
*/
struct stm32_dfsdm_dev_data {
u32 ipid;
unsigned int num_filters;
unsigned int num_channels;
const struct regmap_config *regmap_cfg;
};
#define STM32H7_DFSDM_NUM_FILTERS 4
#define STM32H7_DFSDM_NUM_CHANNELS 8
static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
{
if (reg < DFSDM_FILTER_BASE_ADR)
return false;
/*
* Mask is done on register to avoid to list registers of all
* filter instances.
*/
switch (reg & DFSDM_FILTER_REG_MASK) {
case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK:
case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK:
case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK:
case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK:
return true;
}
return false;
}
static const struct regmap_config stm32h7_dfsdm_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = sizeof(u32),
.max_register = 0x2B8,
.volatile_reg = stm32_dfsdm_volatile_reg,
.fast_io = true,
};
static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data = {
.num_filters = STM32H7_DFSDM_NUM_FILTERS,
.num_channels = STM32H7_DFSDM_NUM_CHANNELS,
.regmap_cfg = &stm32h7_dfsdm_regmap_cfg,
};
static const struct regmap_config stm32mp1_dfsdm_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = sizeof(u32),
.max_register = 0x7fc,
.volatile_reg = stm32_dfsdm_volatile_reg,
.fast_io = true,
};
static const struct stm32_dfsdm_dev_data stm32mp1_dfsdm_data = {
.ipid = STM32MP15_IPIDR_NUMBER,
.regmap_cfg = &stm32mp1_dfsdm_regmap_cfg,
};
struct dfsdm_priv {
struct platform_device *pdev; /* platform device */
struct stm32_dfsdm dfsdm; /* common data exported for all instances */
unsigned int spi_clk_out_div; /* SPI clkout divider value */
atomic_t n_active_ch; /* number of current active channels */
struct clk *clk; /* DFSDM clock */
struct clk *aclk; /* audio clock */
};
static inline struct dfsdm_priv *to_stm32_dfsdm_priv(struct stm32_dfsdm *dfsdm)
{
return container_of(dfsdm, struct dfsdm_priv, dfsdm);
}
static int stm32_dfsdm_clk_prepare_enable(struct stm32_dfsdm *dfsdm)
{
struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
int ret;
ret = clk_prepare_enable(priv->clk);
if (ret || !priv->aclk)
return ret;
ret = clk_prepare_enable(priv->aclk);
if (ret)
clk_disable_unprepare(priv->clk);
return ret;
}
static void stm32_dfsdm_clk_disable_unprepare(struct stm32_dfsdm *dfsdm)
{
struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
clk_disable_unprepare(priv->aclk);
clk_disable_unprepare(priv->clk);
}
/**
* stm32_dfsdm_start_dfsdm - start global dfsdm interface.
*
* Enable interface if n_active_ch is not null.
* @dfsdm: Handle used to retrieve dfsdm context.
*/
int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm)
{
struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
struct device *dev = &priv->pdev->dev;
unsigned int clk_div = priv->spi_clk_out_div, clk_src;
int ret;
if (atomic_inc_return(&priv->n_active_ch) == 1) {
ret = pm_runtime_resume_and_get(dev);
if (ret < 0)
goto error_ret;
/* select clock source, e.g. 0 for "dfsdm" or 1 for "audio" */
clk_src = priv->aclk ? 1 : 0;
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_CKOUTSRC_MASK,
DFSDM_CHCFGR1_CKOUTSRC(clk_src));
if (ret < 0)
goto pm_put;
/* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_CKOUTDIV_MASK,
DFSDM_CHCFGR1_CKOUTDIV(clk_div));
if (ret < 0)
goto pm_put;
/* Global enable of DFSDM interface */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_DFSDMEN_MASK,
DFSDM_CHCFGR1_DFSDMEN(1));
if (ret < 0)
goto pm_put;
}
dev_dbg(dev, "%s: n_active_ch %d\n", __func__,
atomic_read(&priv->n_active_ch));
return 0;
pm_put:
pm_runtime_put_sync(dev);
error_ret:
atomic_dec(&priv->n_active_ch);
return ret;
}
EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm);
/**
* stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
*
* Disable interface if n_active_ch is null
* @dfsdm: Handle used to retrieve dfsdm context.
*/
int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm)
{
struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
int ret;
if (atomic_dec_and_test(&priv->n_active_ch)) {
/* Global disable of DFSDM interface */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_DFSDMEN_MASK,
DFSDM_CHCFGR1_DFSDMEN(0));
if (ret < 0)
return ret;
/* Stop SPI CLKOUT */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_CKOUTDIV_MASK,
DFSDM_CHCFGR1_CKOUTDIV(0));
if (ret < 0)
return ret;
pm_runtime_put_sync(&priv->pdev->dev);
}
dev_dbg(&priv->pdev->dev, "%s: n_active_ch %d\n", __func__,
atomic_read(&priv->n_active_ch));
return 0;
}
EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm);
static int stm32_dfsdm_parse_of(struct platform_device *pdev,
struct dfsdm_priv *priv)
{
struct device_node *node = pdev->dev.of_node;
struct resource *res;
unsigned long clk_freq, divider;
unsigned int spi_freq, rem;
int ret;
if (!node)
return -EINVAL;
priv->dfsdm.base = devm_platform_get_and_ioremap_resource(pdev, 0,
&res);
if (IS_ERR(priv->dfsdm.base))
return PTR_ERR(priv->dfsdm.base);
priv->dfsdm.phys_base = res->start;
/*
* "dfsdm" clock is mandatory for DFSDM peripheral clocking.
* "dfsdm" or "audio" clocks can be used as source clock for
* the SPI clock out signal and internal processing, depending
* on use case.
*/
priv->clk = devm_clk_get(&pdev->dev, "dfsdm");
if (IS_ERR(priv->clk))
return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
"Failed to get clock\n");
priv->aclk = devm_clk_get(&pdev->dev, "audio");
if (IS_ERR(priv->aclk))
priv->aclk = NULL;
if (priv->aclk)
clk_freq = clk_get_rate(priv->aclk);
else
clk_freq = clk_get_rate(priv->clk);
/* SPI clock out frequency */
ret = of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
&spi_freq);
if (ret < 0) {
/* No SPI master mode */
return 0;
}
divider = div_u64_rem(clk_freq, spi_freq, &rem);
/* Round up divider when ckout isn't precise, not to exceed spi_freq */
if (rem)
divider++;
/* programmable divider is in range of [2:256] */
if (divider < 2 || divider > 256) {
dev_err(&pdev->dev, "spi-max-frequency not achievable\n");
return -EINVAL;
}
/* SPI clock output divider is: divider = CKOUTDIV + 1 */
priv->spi_clk_out_div = divider - 1;
priv->dfsdm.spi_master_freq = clk_freq / (priv->spi_clk_out_div + 1);
if (rem) {
dev_warn(&pdev->dev, "SPI clock not accurate\n");
dev_warn(&pdev->dev, "%ld = %d * %d + %d\n",
clk_freq, spi_freq, priv->spi_clk_out_div + 1, rem);
}
return 0;
};
static const struct of_device_id stm32_dfsdm_of_match[] = {
{
.compatible = "st,stm32h7-dfsdm",
.data = &stm32h7_dfsdm_data,
},
{
.compatible = "st,stm32mp1-dfsdm",
.data = &stm32mp1_dfsdm_data,
},
{}
};
MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
static int stm32_dfsdm_probe_identification(struct platform_device *pdev,
struct dfsdm_priv *priv,
const struct stm32_dfsdm_dev_data *dev_data)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
struct stm32_dfsdm *dfsdm = &priv->dfsdm;
const char *compat;
int ret, count = 0;
u32 id, val;
if (!dev_data->ipid) {
dfsdm->num_fls = dev_data->num_filters;
dfsdm->num_chs = dev_data->num_channels;
return 0;
}
ret = regmap_read(dfsdm->regmap, DFSDM_IPIDR, &id);
if (ret)
return ret;
if (id != dev_data->ipid) {
dev_err(&pdev->dev, "Unexpected IP version: 0x%x", id);
return -EINVAL;
}
for_each_child_of_node(np, child) {
ret = of_property_read_string(child, "compatible", &compat);
if (ret)
continue;
/* Count only child nodes with dfsdm compatible */
if (strstr(compat, "dfsdm"))
count++;
}
ret = regmap_read(dfsdm->regmap, DFSDM_HWCFGR, &val);
if (ret)
return ret;
dfsdm->num_fls = FIELD_GET(DFSDM_HWCFGR_NBF_MASK, val);
dfsdm->num_chs = FIELD_GET(DFSDM_HWCFGR_NBT_MASK, val);
if (count > dfsdm->num_fls) {
dev_err(&pdev->dev, "Unexpected child number: %d", count);
return -EINVAL;
}
ret = regmap_read(dfsdm->regmap, DFSDM_VERR, &val);
if (ret)
return ret;
dev_dbg(&pdev->dev, "DFSDM version: %lu.%lu. %d channels/%d filters\n",
FIELD_GET(DFSDM_VERR_MAJREV_MASK, val),
FIELD_GET(DFSDM_VERR_MINREV_MASK, val),
dfsdm->num_chs, dfsdm->num_fls);
return 0;
}
static int stm32_dfsdm_probe(struct platform_device *pdev)
{
struct dfsdm_priv *priv;
const struct stm32_dfsdm_dev_data *dev_data;
struct stm32_dfsdm *dfsdm;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->pdev = pdev;
dev_data = of_device_get_match_data(&pdev->dev);
dfsdm = &priv->dfsdm;
ret = stm32_dfsdm_parse_of(pdev, priv);
if (ret < 0)
return ret;
dfsdm->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dfsdm",
dfsdm->base,
dev_data->regmap_cfg);
if (IS_ERR(dfsdm->regmap)) {
ret = PTR_ERR(dfsdm->regmap);
dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
__func__, ret);
return ret;
}
ret = stm32_dfsdm_probe_identification(pdev, priv, dev_data);
if (ret < 0)
return ret;
dfsdm->fl_list = devm_kcalloc(&pdev->dev, dfsdm->num_fls,
sizeof(*dfsdm->fl_list), GFP_KERNEL);
if (!dfsdm->fl_list)
return -ENOMEM;
dfsdm->ch_list = devm_kcalloc(&pdev->dev, dfsdm->num_chs,
sizeof(*dfsdm->ch_list), GFP_KERNEL);
if (!dfsdm->ch_list)
return -ENOMEM;
platform_set_drvdata(pdev, dfsdm);
ret = stm32_dfsdm_clk_prepare_enable(dfsdm);
if (ret) {
dev_err(&pdev->dev, "Failed to start clock\n");
return ret;
}
pm_runtime_get_noresume(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
if (ret)
goto pm_put;
pm_runtime_put(&pdev->dev);
return 0;
pm_put:
pm_runtime_disable(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
stm32_dfsdm_clk_disable_unprepare(dfsdm);
return ret;
}
static int stm32_dfsdm_core_remove(struct platform_device *pdev)
{
struct stm32_dfsdm *dfsdm = platform_get_drvdata(pdev);
pm_runtime_get_sync(&pdev->dev);
of_platform_depopulate(&pdev->dev);
pm_runtime_disable(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
stm32_dfsdm_clk_disable_unprepare(dfsdm);
return 0;
}
static int stm32_dfsdm_core_suspend(struct device *dev)
{
struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
int ret;
ret = pm_runtime_force_suspend(dev);
if (ret)
return ret;
/* Balance devm_regmap_init_mmio_clk() clk_prepare() */
clk_unprepare(priv->clk);
return pinctrl_pm_select_sleep_state(dev);
}
static int stm32_dfsdm_core_resume(struct device *dev)
{
struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
int ret;
ret = pinctrl_pm_select_default_state(dev);
if (ret)
return ret;
ret = clk_prepare(priv->clk);
if (ret)
return ret;
return pm_runtime_force_resume(dev);
}
static int stm32_dfsdm_core_runtime_suspend(struct device *dev)
{
struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
stm32_dfsdm_clk_disable_unprepare(dfsdm);
return 0;
}
static int stm32_dfsdm_core_runtime_resume(struct device *dev)
{
struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
return stm32_dfsdm_clk_prepare_enable(dfsdm);
}
static const struct dev_pm_ops stm32_dfsdm_core_pm_ops = {
SYSTEM_SLEEP_PM_OPS(stm32_dfsdm_core_suspend, stm32_dfsdm_core_resume)
RUNTIME_PM_OPS(stm32_dfsdm_core_runtime_suspend,
stm32_dfsdm_core_runtime_resume,
NULL)
};
static struct platform_driver stm32_dfsdm_driver = {
.probe = stm32_dfsdm_probe,
.remove = stm32_dfsdm_core_remove,
.driver = {
.name = "stm32-dfsdm",
.of_match_table = stm32_dfsdm_of_match,
.pm = pm_ptr(&stm32_dfsdm_core_pm_ops),
},
};
module_platform_driver(stm32_dfsdm_driver);
MODULE_AUTHOR("Arnaud Pouliquen <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/stm32-dfsdm-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ADS1015 - Texas Instruments Analog-to-Digital Converter
*
* Copyright (c) 2016, Intel Corporation.
*
* IIO driver for ADS1015 ADC 7-bit I2C slave address:
* * 0x48 - ADDR connected to Ground
* * 0x49 - ADDR connected to Vdd
* * 0x4A - ADDR connected to SDA
* * 0x4B - ADDR connected to SCL
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/i2c.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/pm_runtime.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/types.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#define ADS1015_DRV_NAME "ads1015"
#define ADS1015_CHANNELS 8
#define ADS1015_CONV_REG 0x00
#define ADS1015_CFG_REG 0x01
#define ADS1015_LO_THRESH_REG 0x02
#define ADS1015_HI_THRESH_REG 0x03
#define ADS1015_CFG_COMP_QUE_SHIFT 0
#define ADS1015_CFG_COMP_LAT_SHIFT 2
#define ADS1015_CFG_COMP_POL_SHIFT 3
#define ADS1015_CFG_COMP_MODE_SHIFT 4
#define ADS1015_CFG_DR_SHIFT 5
#define ADS1015_CFG_MOD_SHIFT 8
#define ADS1015_CFG_PGA_SHIFT 9
#define ADS1015_CFG_MUX_SHIFT 12
#define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
#define ADS1015_CFG_COMP_LAT_MASK BIT(2)
#define ADS1015_CFG_COMP_POL_MASK BIT(3)
#define ADS1015_CFG_COMP_MODE_MASK BIT(4)
#define ADS1015_CFG_DR_MASK GENMASK(7, 5)
#define ADS1015_CFG_MOD_MASK BIT(8)
#define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
#define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
/* Comparator queue and disable field */
#define ADS1015_CFG_COMP_DISABLE 3
/* Comparator polarity field */
#define ADS1015_CFG_COMP_POL_LOW 0
#define ADS1015_CFG_COMP_POL_HIGH 1
/* Comparator mode field */
#define ADS1015_CFG_COMP_MODE_TRAD 0
#define ADS1015_CFG_COMP_MODE_WINDOW 1
/* device operating modes */
#define ADS1015_CONTINUOUS 0
#define ADS1015_SINGLESHOT 1
#define ADS1015_SLEEP_DELAY_MS 2000
#define ADS1015_DEFAULT_PGA 2
#define ADS1015_DEFAULT_DATA_RATE 4
#define ADS1015_DEFAULT_CHAN 0
struct ads1015_chip_data {
struct iio_chan_spec const *channels;
int num_channels;
const struct iio_info *info;
const int *data_rate;
const int data_rate_len;
const int *scale;
const int scale_len;
bool has_comparator;
};
enum ads1015_channels {
ADS1015_AIN0_AIN1 = 0,
ADS1015_AIN0_AIN3,
ADS1015_AIN1_AIN3,
ADS1015_AIN2_AIN3,
ADS1015_AIN0,
ADS1015_AIN1,
ADS1015_AIN2,
ADS1015_AIN3,
ADS1015_TIMESTAMP,
};
static const int ads1015_data_rate[] = {
128, 250, 490, 920, 1600, 2400, 3300, 3300
};
static const int ads1115_data_rate[] = {
8, 16, 32, 64, 128, 250, 475, 860
};
/*
* Translation from PGA bits to full-scale positive and negative input voltage
* range in mV
*/
static const int ads1015_fullscale_range[] = {
6144, 4096, 2048, 1024, 512, 256, 256, 256
};
static const int ads1015_scale[] = { /* 12bit ADC */
256, 11,
512, 11,
1024, 11,
2048, 11,
4096, 11,
6144, 11
};
static const int ads1115_scale[] = { /* 16bit ADC */
256, 15,
512, 15,
1024, 15,
2048, 15,
4096, 15,
6144, 15
};
/*
* Translation from COMP_QUE field value to the number of successive readings
* exceed the threshold values before an interrupt is generated
*/
static const int ads1015_comp_queue[] = { 1, 2, 4 };
static const struct iio_event_spec ads1015_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
BIT(IIO_EV_INFO_PERIOD),
},
};
/*
* Compile-time check whether _fitbits can accommodate up to _testbits
* bits. Returns _fitbits on success, fails to compile otherwise.
*
* The test works such that it multiplies constant _fitbits by constant
* double-negation of size of a non-empty structure, i.e. it multiplies
* constant _fitbits by constant 1 in each successful compilation case.
* The non-empty structure may contain C11 _Static_assert(), make use of
* this and place the kernel variant of static assert in there, so that
* it performs the compile-time check for _testbits <= _fitbits. Note
* that it is not possible to directly use static_assert in compound
* statements, hence this convoluted construct.
*/
#define FIT_CHECK(_testbits, _fitbits) \
( \
(_fitbits) * \
!!sizeof(struct { \
static_assert((_testbits) <= (_fitbits)); \
int pad; \
}) \
)
#define ADS1015_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.address = _addr, \
.channel = _chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.info_mask_shared_by_all_available = \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.scan_index = _addr, \
.scan_type = { \
.sign = 's', \
.realbits = (_realbits), \
.storagebits = FIT_CHECK((_realbits) + (_shift), 16), \
.shift = (_shift), \
.endianness = IIO_CPU, \
}, \
.event_spec = (_event_spec), \
.num_event_specs = (_num_event_specs), \
.datasheet_name = "AIN"#_chan, \
}
#define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
.type = IIO_VOLTAGE, \
.differential = 1, \
.indexed = 1, \
.address = _addr, \
.channel = _chan, \
.channel2 = _chan2, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.info_mask_shared_by_all_available = \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.scan_index = _addr, \
.scan_type = { \
.sign = 's', \
.realbits = (_realbits), \
.storagebits = FIT_CHECK((_realbits) + (_shift), 16), \
.shift = (_shift), \
.endianness = IIO_CPU, \
}, \
.event_spec = (_event_spec), \
.num_event_specs = (_num_event_specs), \
.datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
}
struct ads1015_channel_data {
bool enabled;
unsigned int pga;
unsigned int data_rate;
};
struct ads1015_thresh_data {
unsigned int comp_queue;
int high_thresh;
int low_thresh;
};
struct ads1015_data {
struct regmap *regmap;
/*
* Protects ADC ops, e.g: concurrent sysfs/buffered
* data reads, configuration updates
*/
struct mutex lock;
struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
unsigned int event_channel;
unsigned int comp_mode;
struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
const struct ads1015_chip_data *chip;
/*
* Set to true when the ADC is switched to the continuous-conversion
* mode and exits from a power-down state. This flag is used to avoid
* getting the stale result from the conversion register.
*/
bool conv_invalid;
};
static bool ads1015_event_channel_enabled(struct ads1015_data *data)
{
return (data->event_channel != ADS1015_CHANNELS);
}
static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
int comp_mode)
{
WARN_ON(ads1015_event_channel_enabled(data));
data->event_channel = chan;
data->comp_mode = comp_mode;
}
static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
{
data->event_channel = ADS1015_CHANNELS;
}
static const struct regmap_range ads1015_writeable_ranges[] = {
regmap_reg_range(ADS1015_CFG_REG, ADS1015_HI_THRESH_REG),
};
static const struct regmap_access_table ads1015_writeable_table = {
.yes_ranges = ads1015_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(ads1015_writeable_ranges),
};
static const struct regmap_config ads1015_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.max_register = ADS1015_HI_THRESH_REG,
.wr_table = &ads1015_writeable_table,
};
static const struct regmap_range tla2024_writeable_ranges[] = {
regmap_reg_range(ADS1015_CFG_REG, ADS1015_CFG_REG),
};
static const struct regmap_access_table tla2024_writeable_table = {
.yes_ranges = tla2024_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(tla2024_writeable_ranges),
};
static const struct regmap_config tla2024_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.max_register = ADS1015_CFG_REG,
.wr_table = &tla2024_writeable_table,
};
static const struct iio_chan_spec ads1015_channels[] = {
ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4,
ads1015_events, ARRAY_SIZE(ads1015_events)),
IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
};
static const struct iio_chan_spec ads1115_channels[] = {
ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 16, 0,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 16, 0,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 16, 0,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 16, 0,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_CHAN(0, ADS1015_AIN0, 16, 0,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_CHAN(1, ADS1015_AIN1, 16, 0,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_CHAN(2, ADS1015_AIN2, 16, 0,
ads1015_events, ARRAY_SIZE(ads1015_events)),
ADS1015_V_CHAN(3, ADS1015_AIN3, 16, 0,
ads1015_events, ARRAY_SIZE(ads1015_events)),
IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
};
static const struct iio_chan_spec tla2024_channels[] = {
ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4, NULL, 0),
ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4, NULL, 0),
ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4, NULL, 0),
ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4, NULL, 0),
ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4, NULL, 0),
ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4, NULL, 0),
ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4, NULL, 0),
ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4, NULL, 0),
IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
};
#ifdef CONFIG_PM
static int ads1015_set_power_state(struct ads1015_data *data, bool on)
{
int ret;
struct device *dev = regmap_get_device(data->regmap);
if (on) {
ret = pm_runtime_resume_and_get(dev);
} else {
pm_runtime_mark_last_busy(dev);
ret = pm_runtime_put_autosuspend(dev);
}
return ret < 0 ? ret : 0;
}
#else /* !CONFIG_PM */
static int ads1015_set_power_state(struct ads1015_data *data, bool on)
{
return 0;
}
#endif /* !CONFIG_PM */
static
int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
{
const int *data_rate = data->chip->data_rate;
int ret, pga, dr, dr_old, conv_time;
unsigned int old, mask, cfg;
if (chan < 0 || chan >= ADS1015_CHANNELS)
return -EINVAL;
ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
if (ret)
return ret;
pga = data->channel_data[chan].pga;
dr = data->channel_data[chan].data_rate;
mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
ADS1015_CFG_DR_MASK;
cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
dr << ADS1015_CFG_DR_SHIFT;
if (ads1015_event_channel_enabled(data)) {
mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
cfg |= data->thresh_data[chan].comp_queue <<
ADS1015_CFG_COMP_QUE_SHIFT |
data->comp_mode <<
ADS1015_CFG_COMP_MODE_SHIFT;
}
cfg = (old & ~mask) | (cfg & mask);
if (old != cfg) {
ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
if (ret)
return ret;
data->conv_invalid = true;
}
if (data->conv_invalid) {
dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
conv_time = DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr_old]);
conv_time += DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr]);
conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
usleep_range(conv_time, conv_time + 1);
data->conv_invalid = false;
}
return regmap_read(data->regmap, ADS1015_CONV_REG, val);
}
static irqreturn_t ads1015_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct ads1015_data *data = iio_priv(indio_dev);
/* Ensure natural alignment of timestamp */
struct {
s16 chan;
s64 timestamp __aligned(8);
} scan;
int chan, ret, res;
memset(&scan, 0, sizeof(scan));
mutex_lock(&data->lock);
chan = find_first_bit(indio_dev->active_scan_mask,
indio_dev->masklength);
ret = ads1015_get_adc_result(data, chan, &res);
if (ret < 0) {
mutex_unlock(&data->lock);
goto err;
}
scan.chan = res;
mutex_unlock(&data->lock);
iio_push_to_buffers_with_timestamp(indio_dev, &scan,
iio_get_time_ns(indio_dev));
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int ads1015_set_scale(struct ads1015_data *data,
struct iio_chan_spec const *chan,
int scale, int uscale)
{
int i;
int fullscale = div_s64((scale * 1000000LL + uscale) <<
(chan->scan_type.realbits - 1), 1000000);
for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
if (ads1015_fullscale_range[i] == fullscale) {
data->channel_data[chan->address].pga = i;
return 0;
}
}
return -EINVAL;
}
static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
{
int i;
for (i = 0; i < data->chip->data_rate_len; i++) {
if (data->chip->data_rate[i] == rate) {
data->channel_data[chan].data_rate = i;
return 0;
}
}
return -EINVAL;
}
static int ads1015_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
struct ads1015_data *data = iio_priv(indio_dev);
if (chan->type != IIO_VOLTAGE)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
*type = IIO_VAL_FRACTIONAL_LOG2;
*vals = data->chip->scale;
*length = data->chip->scale_len;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_SAMP_FREQ:
*type = IIO_VAL_INT;
*vals = data->chip->data_rate;
*length = data->chip->data_rate_len;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static int ads1015_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
int ret, idx;
struct ads1015_data *data = iio_priv(indio_dev);
mutex_lock(&data->lock);
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
break;
if (ads1015_event_channel_enabled(data) &&
data->event_channel != chan->address) {
ret = -EBUSY;
goto release_direct;
}
ret = ads1015_set_power_state(data, true);
if (ret < 0)
goto release_direct;
ret = ads1015_get_adc_result(data, chan->address, val);
if (ret < 0) {
ads1015_set_power_state(data, false);
goto release_direct;
}
*val = sign_extend32(*val >> chan->scan_type.shift,
chan->scan_type.realbits - 1);
ret = ads1015_set_power_state(data, false);
if (ret < 0)
goto release_direct;
ret = IIO_VAL_INT;
release_direct:
iio_device_release_direct_mode(indio_dev);
break;
case IIO_CHAN_INFO_SCALE:
idx = data->channel_data[chan->address].pga;
*val = ads1015_fullscale_range[idx];
*val2 = chan->scan_type.realbits - 1;
ret = IIO_VAL_FRACTIONAL_LOG2;
break;
case IIO_CHAN_INFO_SAMP_FREQ:
idx = data->channel_data[chan->address].data_rate;
*val = data->chip->data_rate[idx];
ret = IIO_VAL_INT;
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&data->lock);
return ret;
}
static int ads1015_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct ads1015_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->lock);
switch (mask) {
case IIO_CHAN_INFO_SCALE:
ret = ads1015_set_scale(data, chan, val, val2);
break;
case IIO_CHAN_INFO_SAMP_FREQ:
ret = ads1015_set_data_rate(data, chan->address, val);
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&data->lock);
return ret;
}
static int ads1015_read_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info, int *val,
int *val2)
{
struct ads1015_data *data = iio_priv(indio_dev);
int ret;
unsigned int comp_queue;
int period;
int dr;
mutex_lock(&data->lock);
switch (info) {
case IIO_EV_INFO_VALUE:
*val = (dir == IIO_EV_DIR_RISING) ?
data->thresh_data[chan->address].high_thresh :
data->thresh_data[chan->address].low_thresh;
ret = IIO_VAL_INT;
break;
case IIO_EV_INFO_PERIOD:
dr = data->channel_data[chan->address].data_rate;
comp_queue = data->thresh_data[chan->address].comp_queue;
period = ads1015_comp_queue[comp_queue] *
USEC_PER_SEC / data->chip->data_rate[dr];
*val = period / USEC_PER_SEC;
*val2 = period % USEC_PER_SEC;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&data->lock);
return ret;
}
static int ads1015_write_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info, int val,
int val2)
{
struct ads1015_data *data = iio_priv(indio_dev);
const int *data_rate = data->chip->data_rate;
int realbits = chan->scan_type.realbits;
int ret = 0;
long long period;
int i;
int dr;
mutex_lock(&data->lock);
switch (info) {
case IIO_EV_INFO_VALUE:
if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
ret = -EINVAL;
break;
}
if (dir == IIO_EV_DIR_RISING)
data->thresh_data[chan->address].high_thresh = val;
else
data->thresh_data[chan->address].low_thresh = val;
break;
case IIO_EV_INFO_PERIOD:
dr = data->channel_data[chan->address].data_rate;
period = val * USEC_PER_SEC + val2;
for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
if (period <= ads1015_comp_queue[i] *
USEC_PER_SEC / data_rate[dr])
break;
}
data->thresh_data[chan->address].comp_queue = i;
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&data->lock);
return ret;
}
static int ads1015_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir)
{
struct ads1015_data *data = iio_priv(indio_dev);
int ret = 0;
mutex_lock(&data->lock);
if (data->event_channel == chan->address) {
switch (dir) {
case IIO_EV_DIR_RISING:
ret = 1;
break;
case IIO_EV_DIR_EITHER:
ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
break;
default:
ret = -EINVAL;
break;
}
}
mutex_unlock(&data->lock);
return ret;
}
static int ads1015_enable_event_config(struct ads1015_data *data,
const struct iio_chan_spec *chan, int comp_mode)
{
int low_thresh = data->thresh_data[chan->address].low_thresh;
int high_thresh = data->thresh_data[chan->address].high_thresh;
int ret;
unsigned int val;
if (ads1015_event_channel_enabled(data)) {
if (data->event_channel != chan->address ||
(data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
return -EBUSY;
return 0;
}
if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
low_thresh = max(-1 << (chan->scan_type.realbits - 1),
high_thresh - 1);
}
ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
low_thresh << chan->scan_type.shift);
if (ret)
return ret;
ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
high_thresh << chan->scan_type.shift);
if (ret)
return ret;
ret = ads1015_set_power_state(data, true);
if (ret < 0)
return ret;
ads1015_event_channel_enable(data, chan->address, comp_mode);
ret = ads1015_get_adc_result(data, chan->address, &val);
if (ret) {
ads1015_event_channel_disable(data, chan->address);
ads1015_set_power_state(data, false);
}
return ret;
}
static int ads1015_disable_event_config(struct ads1015_data *data,
const struct iio_chan_spec *chan, int comp_mode)
{
int ret;
if (!ads1015_event_channel_enabled(data))
return 0;
if (data->event_channel != chan->address)
return 0;
if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
return 0;
ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
ADS1015_CFG_COMP_QUE_MASK,
ADS1015_CFG_COMP_DISABLE <<
ADS1015_CFG_COMP_QUE_SHIFT);
if (ret)
return ret;
ads1015_event_channel_disable(data, chan->address);
return ads1015_set_power_state(data, false);
}
static int ads1015_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct ads1015_data *data = iio_priv(indio_dev);
int ret;
int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
mutex_lock(&data->lock);
/* Prevent from enabling both buffer and event at a time */
ret = iio_device_claim_direct_mode(indio_dev);
if (ret) {
mutex_unlock(&data->lock);
return ret;
}
if (state)
ret = ads1015_enable_event_config(data, chan, comp_mode);
else
ret = ads1015_disable_event_config(data, chan, comp_mode);
iio_device_release_direct_mode(indio_dev);
mutex_unlock(&data->lock);
return ret;
}
static irqreturn_t ads1015_event_handler(int irq, void *priv)
{
struct iio_dev *indio_dev = priv;
struct ads1015_data *data = iio_priv(indio_dev);
int val;
int ret;
/* Clear the latched ALERT/RDY pin */
ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
if (ret)
return IRQ_HANDLED;
if (ads1015_event_channel_enabled(data)) {
enum iio_event_direction dir;
u64 code;
dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
IIO_EV_TYPE_THRESH, dir);
iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
}
return IRQ_HANDLED;
}
static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
{
struct ads1015_data *data = iio_priv(indio_dev);
/* Prevent from enabling both buffer and event at a time */
if (ads1015_event_channel_enabled(data))
return -EBUSY;
return ads1015_set_power_state(iio_priv(indio_dev), true);
}
static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
{
return ads1015_set_power_state(iio_priv(indio_dev), false);
}
static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
.preenable = ads1015_buffer_preenable,
.postdisable = ads1015_buffer_postdisable,
.validate_scan_mask = &iio_validate_scan_mask_onehot,
};
static const struct iio_info ads1015_info = {
.read_avail = ads1015_read_avail,
.read_raw = ads1015_read_raw,
.write_raw = ads1015_write_raw,
.read_event_value = ads1015_read_event,
.write_event_value = ads1015_write_event,
.read_event_config = ads1015_read_event_config,
.write_event_config = ads1015_write_event_config,
};
static const struct iio_info tla2024_info = {
.read_avail = ads1015_read_avail,
.read_raw = ads1015_read_raw,
.write_raw = ads1015_write_raw,
};
static int ads1015_client_get_channels_config(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct ads1015_data *data = iio_priv(indio_dev);
struct device *dev = &client->dev;
struct fwnode_handle *node;
int i = -1;
device_for_each_child_node(dev, node) {
u32 pval;
unsigned int channel;
unsigned int pga = ADS1015_DEFAULT_PGA;
unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
if (fwnode_property_read_u32(node, "reg", &pval)) {
dev_err(dev, "invalid reg on %pfw\n", node);
continue;
}
channel = pval;
if (channel >= ADS1015_CHANNELS) {
dev_err(dev, "invalid channel index %d on %pfw\n",
channel, node);
continue;
}
if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
pga = pval;
if (pga > 6) {
dev_err(dev, "invalid gain on %pfw\n", node);
fwnode_handle_put(node);
return -EINVAL;
}
}
if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
data_rate = pval;
if (data_rate > 7) {
dev_err(dev, "invalid data_rate on %pfw\n", node);
fwnode_handle_put(node);
return -EINVAL;
}
}
data->channel_data[channel].pga = pga;
data->channel_data[channel].data_rate = data_rate;
i++;
}
return i < 0 ? -EINVAL : 0;
}
static void ads1015_get_channels_config(struct i2c_client *client)
{
unsigned int k;
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct ads1015_data *data = iio_priv(indio_dev);
if (!ads1015_client_get_channels_config(client))
return;
/* fallback on default configuration */
for (k = 0; k < ADS1015_CHANNELS; ++k) {
data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
}
}
static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
{
return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
ADS1015_CFG_MOD_MASK,
mode << ADS1015_CFG_MOD_SHIFT);
}
static int ads1015_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
const struct ads1015_chip_data *chip;
struct iio_dev *indio_dev;
struct ads1015_data *data;
int ret;
int i;
chip = device_get_match_data(&client->dev);
if (!chip)
chip = (const struct ads1015_chip_data *)id->driver_data;
if (!chip)
return dev_err_probe(&client->dev, -EINVAL, "Unknown chip\n");
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
mutex_init(&data->lock);
indio_dev->name = ADS1015_DRV_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = chip->channels;
indio_dev->num_channels = chip->num_channels;
indio_dev->info = chip->info;
data->chip = chip;
data->event_channel = ADS1015_CHANNELS;
/*
* Set default lower and upper threshold to min and max value
* respectively.
*/
for (i = 0; i < ADS1015_CHANNELS; i++) {
int realbits = indio_dev->channels[i].scan_type.realbits;
data->thresh_data[i].low_thresh = -1 << (realbits - 1);
data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
}
/* we need to keep this ABI the same as used by hwmon ADS1015 driver */
ads1015_get_channels_config(client);
data->regmap = devm_regmap_init_i2c(client, chip->has_comparator ?
&ads1015_regmap_config :
&tla2024_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(&client->dev, "Failed to allocate register map\n");
return PTR_ERR(data->regmap);
}
ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
ads1015_trigger_handler,
&ads1015_buffer_setup_ops);
if (ret < 0) {
dev_err(&client->dev, "iio triggered buffer setup failed\n");
return ret;
}
if (client->irq && chip->has_comparator) {
unsigned long irq_trig =
irqd_get_trigger_type(irq_get_irq_data(client->irq));
unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
unsigned int cfg_comp =
ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
1 << ADS1015_CFG_COMP_LAT_SHIFT;
switch (irq_trig) {
case IRQF_TRIGGER_LOW:
cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
ADS1015_CFG_COMP_POL_SHIFT;
break;
case IRQF_TRIGGER_HIGH:
cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
ADS1015_CFG_COMP_POL_SHIFT;
break;
default:
return -EINVAL;
}
ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
cfg_comp_mask, cfg_comp);
if (ret)
return ret;
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, ads1015_event_handler,
irq_trig | IRQF_ONESHOT,
client->name, indio_dev);
if (ret)
return ret;
}
ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
if (ret)
return ret;
data->conv_invalid = true;
ret = pm_runtime_set_active(&client->dev);
if (ret)
return ret;
pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
pm_runtime_use_autosuspend(&client->dev);
pm_runtime_enable(&client->dev);
ret = iio_device_register(indio_dev);
if (ret < 0) {
dev_err(&client->dev, "Failed to register IIO device\n");
return ret;
}
return 0;
}
static void ads1015_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct ads1015_data *data = iio_priv(indio_dev);
int ret;
iio_device_unregister(indio_dev);
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
/* power down single shot mode */
ret = ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
if (ret)
dev_warn(&client->dev, "Failed to power down (%pe)\n",
ERR_PTR(ret));
}
#ifdef CONFIG_PM
static int ads1015_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct ads1015_data *data = iio_priv(indio_dev);
return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
}
static int ads1015_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct ads1015_data *data = iio_priv(indio_dev);
int ret;
ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
if (!ret)
data->conv_invalid = true;
return ret;
}
#endif
static const struct dev_pm_ops ads1015_pm_ops = {
SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
ads1015_runtime_resume, NULL)
};
static const struct ads1015_chip_data ads1015_data = {
.channels = ads1015_channels,
.num_channels = ARRAY_SIZE(ads1015_channels),
.info = &ads1015_info,
.data_rate = ads1015_data_rate,
.data_rate_len = ARRAY_SIZE(ads1015_data_rate),
.scale = ads1015_scale,
.scale_len = ARRAY_SIZE(ads1015_scale),
.has_comparator = true,
};
static const struct ads1015_chip_data ads1115_data = {
.channels = ads1115_channels,
.num_channels = ARRAY_SIZE(ads1115_channels),
.info = &ads1015_info,
.data_rate = ads1115_data_rate,
.data_rate_len = ARRAY_SIZE(ads1115_data_rate),
.scale = ads1115_scale,
.scale_len = ARRAY_SIZE(ads1115_scale),
.has_comparator = true,
};
static const struct ads1015_chip_data tla2024_data = {
.channels = tla2024_channels,
.num_channels = ARRAY_SIZE(tla2024_channels),
.info = &tla2024_info,
.data_rate = ads1015_data_rate,
.data_rate_len = ARRAY_SIZE(ads1015_data_rate),
.scale = ads1015_scale,
.scale_len = ARRAY_SIZE(ads1015_scale),
.has_comparator = false,
};
static const struct i2c_device_id ads1015_id[] = {
{ "ads1015", (kernel_ulong_t)&ads1015_data },
{ "ads1115", (kernel_ulong_t)&ads1115_data },
{ "tla2024", (kernel_ulong_t)&tla2024_data },
{}
};
MODULE_DEVICE_TABLE(i2c, ads1015_id);
static const struct of_device_id ads1015_of_match[] = {
{ .compatible = "ti,ads1015", .data = &ads1015_data },
{ .compatible = "ti,ads1115", .data = &ads1115_data },
{ .compatible = "ti,tla2024", .data = &tla2024_data },
{}
};
MODULE_DEVICE_TABLE(of, ads1015_of_match);
static struct i2c_driver ads1015_driver = {
.driver = {
.name = ADS1015_DRV_NAME,
.of_match_table = ads1015_of_match,
.pm = &ads1015_pm_ops,
},
.probe = ads1015_probe,
.remove = ads1015_remove,
.id_table = ads1015_id,
};
module_i2c_driver(ads1015_driver);
MODULE_AUTHOR("Daniel Baluta <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ti-ads1015.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017 Axis Communications AB
*
* Driver for Texas Instruments' ADC084S021 ADC chip.
* Datasheets can be found here:
* https://www.ti.com/lit/ds/symlink/adc084s021.pdf
*/
#include <linux/err.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/interrupt.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/regulator/consumer.h>
#define ADC084S021_DRIVER_NAME "adc084s021"
struct adc084s021 {
struct spi_device *spi;
struct spi_message message;
struct spi_transfer spi_trans;
struct regulator *reg;
struct mutex lock;
/* Buffer used to align data */
struct {
__be16 channels[4];
s64 ts __aligned(8);
} scan;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache line.
*/
u16 tx_buf[4] __aligned(IIO_DMA_MINALIGN);
__be16 rx_buf[5]; /* First 16-bits are trash */
};
#define ADC084S021_VOLTAGE_CHANNEL(num) \
{ \
.type = IIO_VOLTAGE, \
.channel = (num), \
.indexed = 1, \
.scan_index = (num), \
.scan_type = { \
.sign = 'u', \
.realbits = 8, \
.storagebits = 16, \
.shift = 4, \
.endianness = IIO_BE, \
}, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\
}
static const struct iio_chan_spec adc084s021_channels[] = {
ADC084S021_VOLTAGE_CHANNEL(0),
ADC084S021_VOLTAGE_CHANNEL(1),
ADC084S021_VOLTAGE_CHANNEL(2),
ADC084S021_VOLTAGE_CHANNEL(3),
IIO_CHAN_SOFT_TIMESTAMP(4),
};
/**
* adc084s021_adc_conversion() - Read an ADC channel and return its value.
*
* @adc: The ADC SPI data.
* @data: Buffer for converted data.
*/
static int adc084s021_adc_conversion(struct adc084s021 *adc, __be16 *data)
{
int n_words = (adc->spi_trans.len >> 1) - 1; /* Discard first word */
int ret, i = 0;
/* Do the transfer */
ret = spi_sync(adc->spi, &adc->message);
if (ret < 0)
return ret;
for (; i < n_words; i++)
*(data + i) = adc->rx_buf[i + 1];
return ret;
}
static int adc084s021_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
struct adc084s021 *adc = iio_priv(indio_dev);
int ret;
__be16 be_val;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret < 0)
return ret;
ret = regulator_enable(adc->reg);
if (ret) {
iio_device_release_direct_mode(indio_dev);
return ret;
}
adc->tx_buf[0] = channel->channel << 3;
ret = adc084s021_adc_conversion(adc, &be_val);
iio_device_release_direct_mode(indio_dev);
regulator_disable(adc->reg);
if (ret < 0)
return ret;
*val = be16_to_cpu(be_val);
*val = (*val >> channel->scan_type.shift) & 0xff;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = regulator_enable(adc->reg);
if (ret)
return ret;
ret = regulator_get_voltage(adc->reg);
regulator_disable(adc->reg);
if (ret < 0)
return ret;
*val = ret / 1000;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
/**
* adc084s021_buffer_trigger_handler() - Read ADC channels and push to buffer.
*
* @irq: The interrupt number (not used).
* @pollfunc: Pointer to the poll func.
*/
static irqreturn_t adc084s021_buffer_trigger_handler(int irq, void *pollfunc)
{
struct iio_poll_func *pf = pollfunc;
struct iio_dev *indio_dev = pf->indio_dev;
struct adc084s021 *adc = iio_priv(indio_dev);
mutex_lock(&adc->lock);
if (adc084s021_adc_conversion(adc, adc->scan.channels) < 0)
dev_err(&adc->spi->dev, "Failed to read data\n");
iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan,
iio_get_time_ns(indio_dev));
mutex_unlock(&adc->lock);
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int adc084s021_buffer_preenable(struct iio_dev *indio_dev)
{
struct adc084s021 *adc = iio_priv(indio_dev);
int scan_index;
int i = 0;
for_each_set_bit(scan_index, indio_dev->active_scan_mask,
indio_dev->masklength) {
const struct iio_chan_spec *channel =
&indio_dev->channels[scan_index];
adc->tx_buf[i++] = channel->channel << 3;
}
adc->spi_trans.len = 2 + (i * sizeof(__be16)); /* Trash + channels */
return regulator_enable(adc->reg);
}
static int adc084s021_buffer_postdisable(struct iio_dev *indio_dev)
{
struct adc084s021 *adc = iio_priv(indio_dev);
adc->spi_trans.len = 4; /* Trash + single channel */
return regulator_disable(adc->reg);
}
static const struct iio_info adc084s021_info = {
.read_raw = adc084s021_read_raw,
};
static const struct iio_buffer_setup_ops adc084s021_buffer_setup_ops = {
.preenable = adc084s021_buffer_preenable,
.postdisable = adc084s021_buffer_postdisable,
};
static int adc084s021_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct adc084s021 *adc;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
if (!indio_dev) {
dev_err(&spi->dev, "Failed to allocate IIO device\n");
return -ENOMEM;
}
adc = iio_priv(indio_dev);
adc->spi = spi;
/* Initiate the Industrial I/O device */
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &adc084s021_info;
indio_dev->channels = adc084s021_channels;
indio_dev->num_channels = ARRAY_SIZE(adc084s021_channels);
/* Create SPI transfer for channel reads */
adc->spi_trans.tx_buf = adc->tx_buf;
adc->spi_trans.rx_buf = adc->rx_buf;
adc->spi_trans.len = 4; /* Trash + single channel */
spi_message_init_with_transfers(&adc->message, &adc->spi_trans, 1);
adc->reg = devm_regulator_get(&spi->dev, "vref");
if (IS_ERR(adc->reg))
return PTR_ERR(adc->reg);
mutex_init(&adc->lock);
/* Setup triggered buffer with pollfunction */
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
adc084s021_buffer_trigger_handler,
&adc084s021_buffer_setup_ops);
if (ret) {
dev_err(&spi->dev, "Failed to setup triggered buffer\n");
return ret;
}
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct of_device_id adc084s021_of_match[] = {
{ .compatible = "ti,adc084s021", },
{},
};
MODULE_DEVICE_TABLE(of, adc084s021_of_match);
static const struct spi_device_id adc084s021_id[] = {
{ ADC084S021_DRIVER_NAME, 0 },
{}
};
MODULE_DEVICE_TABLE(spi, adc084s021_id);
static struct spi_driver adc084s021_driver = {
.driver = {
.name = ADC084S021_DRIVER_NAME,
.of_match_table = adc084s021_of_match,
},
.probe = adc084s021_probe,
.id_table = adc084s021_id,
};
module_spi_driver(adc084s021_driver);
MODULE_AUTHOR("Mårten Lindahl <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments ADC084S021");
MODULE_LICENSE("GPL v2");
MODULE_VERSION("1.0");
| linux-master | drivers/iio/adc/ti-adc084s021.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Generic sigma delta modulator driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author: Arnaud Pouliquen <[email protected]>.
*/
#include <linux/iio/iio.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
static const struct iio_info iio_sd_mod_iio_info;
static const struct iio_chan_spec iio_sd_mod_ch = {
.type = IIO_VOLTAGE,
.indexed = 1,
.scan_type = {
.sign = 'u',
.realbits = 1,
.shift = 0,
},
};
static int iio_sd_mod_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct iio_dev *iio;
iio = devm_iio_device_alloc(dev, 0);
if (!iio)
return -ENOMEM;
iio->name = dev_name(dev);
iio->info = &iio_sd_mod_iio_info;
iio->modes = INDIO_BUFFER_HARDWARE;
iio->num_channels = 1;
iio->channels = &iio_sd_mod_ch;
platform_set_drvdata(pdev, iio);
return devm_iio_device_register(&pdev->dev, iio);
}
static const struct of_device_id sd_adc_of_match[] = {
{ .compatible = "sd-modulator" },
{ .compatible = "ads1201" },
{ }
};
MODULE_DEVICE_TABLE(of, sd_adc_of_match);
static struct platform_driver iio_sd_mod_adc = {
.driver = {
.name = "iio_sd_adc_mod",
.of_match_table = sd_adc_of_match,
},
.probe = iio_sd_mod_probe,
};
module_platform_driver(iio_sd_mod_adc);
MODULE_DESCRIPTION("Basic sigma delta modulator");
MODULE_AUTHOR("Arnaud Pouliquen <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/sd_adc_modulator.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for Microchip MCP3911, Two-channel Analog Front End
*
* Copyright (C) 2018 Marcus Folkesson <[email protected]>
* Copyright (C) 2018 Kent Gustavsson <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/trigger.h>
#include <asm/unaligned.h>
#define MCP3911_REG_CHANNEL0 0x00
#define MCP3911_REG_CHANNEL1 0x03
#define MCP3911_REG_MOD 0x06
#define MCP3911_REG_PHASE 0x07
#define MCP3911_REG_GAIN 0x09
#define MCP3911_GAIN_MASK(ch) (GENMASK(2, 0) << 3 * ch)
#define MCP3911_GAIN_VAL(ch, val) ((val << 3 * ch) & MCP3911_GAIN_MASK(ch))
#define MCP3911_REG_STATUSCOM 0x0a
#define MCP3911_STATUSCOM_DRHIZ BIT(12)
#define MCP3911_STATUSCOM_READ GENMASK(7, 6)
#define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4)
#define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3)
#define MCP3911_STATUSCOM_EN_OFFCAL BIT(2)
#define MCP3911_STATUSCOM_EN_GAINCAL BIT(1)
#define MCP3911_REG_CONFIG 0x0c
#define MCP3911_CONFIG_CLKEXT BIT(1)
#define MCP3911_CONFIG_VREFEXT BIT(2)
#define MCP3911_CONFIG_OSR GENMASK(13, 11)
#define MCP3911_REG_OFFCAL_CH0 0x0e
#define MCP3911_REG_GAINCAL_CH0 0x11
#define MCP3911_REG_OFFCAL_CH1 0x14
#define MCP3911_REG_GAINCAL_CH1 0x17
#define MCP3911_REG_VREFCAL 0x1a
#define MCP3911_CHANNEL(x) (MCP3911_REG_CHANNEL0 + x * 3)
#define MCP3911_OFFCAL(x) (MCP3911_REG_OFFCAL_CH0 + x * 6)
/* Internal voltage reference in mV */
#define MCP3911_INT_VREF_MV 1200
#define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 6) | (1 << 0)) & 0xff)
#define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff)
#define MCP3911_REG_MASK GENMASK(4, 1)
#define MCP3911_NUM_CHANNELS 2
#define MCP3911_NUM_SCALES 6
static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 };
static u32 mcp3911_scale_table[MCP3911_NUM_SCALES][2];
struct mcp3911 {
struct spi_device *spi;
struct mutex lock;
struct regulator *vref;
struct clk *clki;
u32 dev_addr;
struct iio_trigger *trig;
u32 gain[MCP3911_NUM_CHANNELS];
struct {
u32 channels[MCP3911_NUM_CHANNELS];
s64 ts __aligned(8);
} scan;
u8 tx_buf __aligned(IIO_DMA_MINALIGN);
u8 rx_buf[MCP3911_NUM_CHANNELS * 3];
};
static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len)
{
int ret;
reg = MCP3911_REG_READ(reg, adc->dev_addr);
ret = spi_write_then_read(adc->spi, ®, 1, val, len);
if (ret < 0)
return ret;
be32_to_cpus(val);
*val >>= ((4 - len) * 8);
dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val,
FIELD_GET(MCP3911_REG_MASK, reg));
return ret;
}
static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len)
{
dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg);
val <<= (3 - len) * 8;
cpu_to_be32s(&val);
val |= MCP3911_REG_WRITE(reg, adc->dev_addr);
return spi_write(adc->spi, &val, len + 1);
}
static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask,
u32 val, u8 len)
{
u32 tmp;
int ret;
ret = mcp3911_read(adc, reg, &tmp, len);
if (ret)
return ret;
val &= mask;
val |= tmp & ~mask;
return mcp3911_write(adc, reg, val, len);
}
static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_SCALE:
return IIO_VAL_INT_PLUS_NANO;
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
return IIO_VAL_INT;
default:
return IIO_VAL_INT_PLUS_NANO;
}
}
static int mcp3911_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long info)
{
switch (info) {
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
*type = IIO_VAL_INT;
*vals = mcp3911_osr_table;
*length = ARRAY_SIZE(mcp3911_osr_table);
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_SCALE:
*type = IIO_VAL_INT_PLUS_NANO;
*vals = (int *)mcp3911_scale_table;
*length = ARRAY_SIZE(mcp3911_scale_table) * 2;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static int mcp3911_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
struct mcp3911 *adc = iio_priv(indio_dev);
int ret = -EINVAL;
mutex_lock(&adc->lock);
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = mcp3911_read(adc,
MCP3911_CHANNEL(channel->channel), val, 3);
if (ret)
goto out;
*val = sign_extend32(*val, 23);
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_OFFSET:
ret = mcp3911_read(adc,
MCP3911_OFFCAL(channel->channel), val, 3);
if (ret)
goto out;
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2);
if (ret)
goto out;
*val = FIELD_GET(MCP3911_CONFIG_OSR, *val);
*val = 32 << *val;
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SCALE:
*val = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][0];
*val2 = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][1];
ret = IIO_VAL_INT_PLUS_NANO;
break;
}
out:
mutex_unlock(&adc->lock);
return ret;
}
static int mcp3911_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int val,
int val2, long mask)
{
struct mcp3911 *adc = iio_priv(indio_dev);
int ret = -EINVAL;
mutex_lock(&adc->lock);
switch (mask) {
case IIO_CHAN_INFO_SCALE:
for (int i = 0; i < MCP3911_NUM_SCALES; i++) {
if (val == mcp3911_scale_table[i][0] &&
val2 == mcp3911_scale_table[i][1]) {
adc->gain[channel->channel] = BIT(i);
ret = mcp3911_update(adc, MCP3911_REG_GAIN,
MCP3911_GAIN_MASK(channel->channel),
MCP3911_GAIN_VAL(channel->channel, i), 1);
}
}
break;
case IIO_CHAN_INFO_OFFSET:
if (val2 != 0) {
ret = -EINVAL;
goto out;
}
/* Write offset */
ret = mcp3911_write(adc, MCP3911_OFFCAL(channel->channel), val,
3);
if (ret)
goto out;
/* Enable offset*/
ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM,
MCP3911_STATUSCOM_EN_OFFCAL,
MCP3911_STATUSCOM_EN_OFFCAL, 2);
break;
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) {
if (val == mcp3911_osr_table[i]) {
val = FIELD_PREP(MCP3911_CONFIG_OSR, i);
ret = mcp3911_update(adc, MCP3911_REG_CONFIG, MCP3911_CONFIG_OSR,
val, 2);
break;
}
}
break;
}
out:
mutex_unlock(&adc->lock);
return ret;
}
static int mcp3911_calc_scale_table(struct mcp3911 *adc)
{
u32 ref = MCP3911_INT_VREF_MV;
u32 div;
int ret;
u64 tmp;
if (adc->vref) {
ret = regulator_get_voltage(adc->vref);
if (ret < 0) {
dev_err(&adc->spi->dev,
"failed to get vref voltage: %d\n",
ret);
return ret;
}
ref = ret / 1000;
}
/*
* For 24-bit Conversion
* Raw = ((Voltage)/(Vref) * 2^23 * Gain * 1.5
* Voltage = Raw * (Vref)/(2^23 * Gain * 1.5)
*
* ref = Reference voltage
* div = (2^23 * 1.5 * gain) = 12582912 * gain
*/
for (int i = 0; i < MCP3911_NUM_SCALES; i++) {
div = 12582912 * BIT(i);
tmp = div_s64((s64)ref * 1000000000LL, div);
mcp3911_scale_table[i][0] = 0;
mcp3911_scale_table[i][1] = tmp;
}
return 0;
}
#define MCP3911_CHAN(idx) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = idx, \
.scan_index = idx, \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_type_available = \
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.info_mask_separate_available = \
BIT(IIO_CHAN_INFO_SCALE), \
.scan_type = { \
.sign = 's', \
.realbits = 24, \
.storagebits = 32, \
.endianness = IIO_BE, \
}, \
}
static const struct iio_chan_spec mcp3911_channels[] = {
MCP3911_CHAN(0),
MCP3911_CHAN(1),
IIO_CHAN_SOFT_TIMESTAMP(2),
};
static irqreturn_t mcp3911_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct mcp3911 *adc = iio_priv(indio_dev);
struct spi_transfer xfer[] = {
{
.tx_buf = &adc->tx_buf,
.len = 1,
}, {
.rx_buf = adc->rx_buf,
.len = sizeof(adc->rx_buf),
},
};
int scan_index;
int i = 0;
int ret;
mutex_lock(&adc->lock);
adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr);
ret = spi_sync_transfer(adc->spi, xfer, ARRAY_SIZE(xfer));
if (ret < 0) {
dev_warn(&adc->spi->dev,
"failed to get conversion data\n");
goto out;
}
for_each_set_bit(scan_index, indio_dev->active_scan_mask, indio_dev->masklength) {
const struct iio_chan_spec *scan_chan = &indio_dev->channels[scan_index];
adc->scan.channels[i] = get_unaligned_be24(&adc->rx_buf[scan_chan->channel * 3]);
i++;
}
iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan,
iio_get_time_ns(indio_dev));
out:
mutex_unlock(&adc->lock);
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static const struct iio_info mcp3911_info = {
.read_raw = mcp3911_read_raw,
.write_raw = mcp3911_write_raw,
.read_avail = mcp3911_read_avail,
.write_raw_get_fmt = mcp3911_write_raw_get_fmt,
};
static int mcp3911_config(struct mcp3911 *adc)
{
struct device *dev = &adc->spi->dev;
u32 regval;
int ret;
ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr);
/*
* Fallback to "device-addr" due to historical mismatch between
* dt-bindings and implementation
*/
if (ret)
device_property_read_u32(dev, "device-addr", &adc->dev_addr);
if (adc->dev_addr > 3) {
dev_err(&adc->spi->dev,
"invalid device address (%i). Must be in range 0-3.\n",
adc->dev_addr);
return -EINVAL;
}
dev_dbg(&adc->spi->dev, "use device address %i\n", adc->dev_addr);
ret = mcp3911_read(adc, MCP3911_REG_CONFIG, ®val, 2);
if (ret)
return ret;
regval &= ~MCP3911_CONFIG_VREFEXT;
if (adc->vref) {
dev_dbg(&adc->spi->dev, "use external voltage reference\n");
regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1);
} else {
dev_dbg(&adc->spi->dev,
"use internal voltage reference (1.2V)\n");
regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0);
}
regval &= ~MCP3911_CONFIG_CLKEXT;
if (adc->clki) {
dev_dbg(&adc->spi->dev, "use external clock as clocksource\n");
regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1);
} else {
dev_dbg(&adc->spi->dev,
"use crystal oscillator as clocksource\n");
regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0);
}
ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2);
if (ret)
return ret;
ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, ®val, 2);
if (ret)
return ret;
/* Address counter incremented, cycle through register types */
regval &= ~MCP3911_STATUSCOM_READ;
regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02);
return mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2);
}
static void mcp3911_cleanup_regulator(void *vref)
{
regulator_disable(vref);
}
static int mcp3911_set_trigger_state(struct iio_trigger *trig, bool enable)
{
struct mcp3911 *adc = iio_trigger_get_drvdata(trig);
if (enable)
enable_irq(adc->spi->irq);
else
disable_irq(adc->spi->irq);
return 0;
}
static const struct iio_trigger_ops mcp3911_trigger_ops = {
.validate_device = iio_trigger_validate_own_device,
.set_trigger_state = mcp3911_set_trigger_state,
};
static int mcp3911_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct mcp3911 *adc;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
if (!indio_dev)
return -ENOMEM;
adc = iio_priv(indio_dev);
adc->spi = spi;
adc->vref = devm_regulator_get_optional(&adc->spi->dev, "vref");
if (IS_ERR(adc->vref)) {
if (PTR_ERR(adc->vref) == -ENODEV) {
adc->vref = NULL;
} else {
dev_err(&adc->spi->dev,
"failed to get regulator (%ld)\n",
PTR_ERR(adc->vref));
return PTR_ERR(adc->vref);
}
} else {
ret = regulator_enable(adc->vref);
if (ret)
return ret;
ret = devm_add_action_or_reset(&spi->dev,
mcp3911_cleanup_regulator, adc->vref);
if (ret)
return ret;
}
adc->clki = devm_clk_get_enabled(&adc->spi->dev, NULL);
if (IS_ERR(adc->clki)) {
if (PTR_ERR(adc->clki) == -ENOENT) {
adc->clki = NULL;
} else {
dev_err(&adc->spi->dev,
"failed to get adc clk (%ld)\n",
PTR_ERR(adc->clki));
return PTR_ERR(adc->clki);
}
}
ret = mcp3911_config(adc);
if (ret)
return ret;
if (device_property_read_bool(&adc->spi->dev, "microchip,data-ready-hiz"))
ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ,
0, 2);
else
ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ,
MCP3911_STATUSCOM_DRHIZ, 2);
if (ret)
return ret;
ret = mcp3911_calc_scale_table(adc);
if (ret)
return ret;
/* Set gain to 1 for all channels */
for (int i = 0; i < MCP3911_NUM_CHANNELS; i++) {
adc->gain[i] = 1;
ret = mcp3911_update(adc, MCP3911_REG_GAIN,
MCP3911_GAIN_MASK(i),
MCP3911_GAIN_VAL(i, 0), 1);
if (ret)
return ret;
}
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &mcp3911_info;
spi_set_drvdata(spi, indio_dev);
indio_dev->channels = mcp3911_channels;
indio_dev->num_channels = ARRAY_SIZE(mcp3911_channels);
mutex_init(&adc->lock);
if (spi->irq > 0) {
adc->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
indio_dev->name,
iio_device_id(indio_dev));
if (!adc->trig)
return -ENOMEM;
adc->trig->ops = &mcp3911_trigger_ops;
iio_trigger_set_drvdata(adc->trig, adc);
ret = devm_iio_trigger_register(&spi->dev, adc->trig);
if (ret)
return ret;
/*
* The device generates interrupts as long as it is powered up.
* Some platforms might not allow the option to power it down so
* don't enable the interrupt to avoid extra load on the system.
*/
ret = devm_request_irq(&spi->dev, spi->irq,
&iio_trigger_generic_data_rdy_poll, IRQF_NO_AUTOEN | IRQF_ONESHOT,
indio_dev->name, adc->trig);
if (ret)
return ret;
}
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
NULL,
mcp3911_trigger_handler, NULL);
if (ret)
return ret;
return devm_iio_device_register(&adc->spi->dev, indio_dev);
}
static const struct of_device_id mcp3911_dt_ids[] = {
{ .compatible = "microchip,mcp3911" },
{ }
};
MODULE_DEVICE_TABLE(of, mcp3911_dt_ids);
static const struct spi_device_id mcp3911_id[] = {
{ "mcp3911", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, mcp3911_id);
static struct spi_driver mcp3911_driver = {
.driver = {
.name = "mcp3911",
.of_match_table = mcp3911_dt_ids,
},
.probe = mcp3911_probe,
.id_table = mcp3911_id,
};
module_spi_driver(mcp3911_driver);
MODULE_AUTHOR("Marcus Folkesson <[email protected]>");
MODULE_AUTHOR("Kent Gustavsson <[email protected]>");
MODULE_DESCRIPTION("Microchip Technology MCP3911");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/mcp3911.c |
// SPDX-License-Identifier: GPL-2.0
/*
* AD7190 AD7192 AD7193 AD7195 SPI ADC driver
*
* Copyright 2011-2015 Analog Devices Inc.
*/
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/adc/ad_sigma_delta.h>
/* Registers */
#define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
#define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
#define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
#define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
#define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
#define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
#define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
#define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
/* (AD7792)/24-bit (AD7192)) */
#define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
/* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
/* Communications Register Bit Designations (AD7192_REG_COMM) */
#define AD7192_COMM_WEN BIT(7) /* Write Enable */
#define AD7192_COMM_WRITE 0 /* Write Operation */
#define AD7192_COMM_READ BIT(6) /* Read Operation */
#define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
#define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
/* Status Register Bit Designations (AD7192_REG_STAT) */
#define AD7192_STAT_RDY BIT(7) /* Ready */
#define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
#define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
#define AD7192_STAT_PARITY BIT(4) /* Parity */
#define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
#define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
#define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
/* Mode Register Bit Designations (AD7192_REG_MODE) */
#define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
#define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
#define AD7192_MODE_STA(x) (((x) & 0x1) << 20) /* Status Register transmission */
#define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */
#define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
#define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
#define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
#define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
#define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
#define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
#define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
/* Mode Register: AD7192_MODE_SEL options */
#define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
#define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
#define AD7192_MODE_IDLE 2 /* Idle Mode */
#define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
#define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
#define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
#define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
#define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
/* Mode Register: AD7192_MODE_CLKSRC options */
#define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
/* from MCLK1 to MCLK2 */
#define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
#define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
/* available at the MCLK2 pin */
#define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
/* at the MCLK2 pin */
/* Configuration Register Bit Designations (AD7192_REG_CONF) */
#define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
#define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */
#define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
#define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
#define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
#define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
#define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
#define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
#define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
#define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
#define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
#define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
#define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
#define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
#define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
#define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
#define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
#define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
#define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
#define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
#define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
#define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
#define AD7193_CH_TEMP 0x100 /* Temp senseor */
#define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
#define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
#define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
#define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
#define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
#define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
#define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
#define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
#define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
#define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
/* ID Register Bit Designations (AD7192_REG_ID) */
#define CHIPID_AD7190 0x4
#define CHIPID_AD7192 0x0
#define CHIPID_AD7193 0x2
#define CHIPID_AD7195 0x6
#define AD7192_ID_MASK 0x0F
/* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
#define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
#define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
#define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
#define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
#define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
#define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
#define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
#define AD7192_EXT_FREQ_MHZ_MIN 2457600
#define AD7192_EXT_FREQ_MHZ_MAX 5120000
#define AD7192_INT_FREQ_MHZ 4915200
#define AD7192_NO_SYNC_FILTER 1
#define AD7192_SYNC3_FILTER 3
#define AD7192_SYNC4_FILTER 4
/* NOTE:
* The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
* In order to avoid contentions on the SPI bus, it's therefore necessary
* to use spi bus locking.
*
* The DOUT/RDY output must also be wired to an interrupt capable GPIO.
*/
enum {
AD7192_SYSCALIB_ZERO_SCALE,
AD7192_SYSCALIB_FULL_SCALE,
};
enum {
ID_AD7190,
ID_AD7192,
ID_AD7193,
ID_AD7195,
};
struct ad7192_chip_info {
unsigned int chip_id;
const char *name;
};
struct ad7192_state {
const struct ad7192_chip_info *chip_info;
struct regulator *avdd;
struct clk *mclk;
u16 int_vref_mv;
u32 fclk;
u32 f_order;
u32 mode;
u32 conf;
u32 scale_avail[8][2];
u8 gpocon;
u8 clock_sel;
struct mutex lock; /* protect sensor state */
u8 syscalib_mode[8];
struct ad_sigma_delta sd;
};
static const char * const ad7192_syscalib_modes[] = {
[AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
[AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
};
static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int mode)
{
struct ad7192_state *st = iio_priv(indio_dev);
st->syscalib_mode[chan->channel] = mode;
return 0;
}
static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct ad7192_state *st = iio_priv(indio_dev);
return st->syscalib_mode[chan->channel];
}
static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct ad7192_state *st = iio_priv(indio_dev);
bool sys_calib;
int ret, temp;
ret = kstrtobool(buf, &sys_calib);
if (ret)
return ret;
temp = st->syscalib_mode[chan->channel];
if (sys_calib) {
if (temp == AD7192_SYSCALIB_ZERO_SCALE)
ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
chan->address);
else
ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
chan->address);
}
return ret ? ret : len;
}
static const struct iio_enum ad7192_syscalib_mode_enum = {
.items = ad7192_syscalib_modes,
.num_items = ARRAY_SIZE(ad7192_syscalib_modes),
.set = ad7192_set_syscalib_mode,
.get = ad7192_get_syscalib_mode
};
static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
{
.name = "sys_calibration",
.write = ad7192_write_syscalib,
.shared = IIO_SEPARATE,
},
IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
&ad7192_syscalib_mode_enum),
IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
&ad7192_syscalib_mode_enum),
{}
};
static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
{
return container_of(sd, struct ad7192_state, sd);
}
static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
{
struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
st->conf &= ~AD7192_CONF_CHAN_MASK;
st->conf |= AD7192_CONF_CHAN(channel);
return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
}
static int ad7192_set_mode(struct ad_sigma_delta *sd,
enum ad_sigma_delta_mode mode)
{
struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
st->mode &= ~AD7192_MODE_SEL_MASK;
st->mode |= AD7192_MODE_SEL(mode);
return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
}
static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)
{
struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
unsigned int mode = st->mode;
int ret;
mode &= ~AD7192_MODE_STA_MASK;
mode |= AD7192_MODE_STA(append);
ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);
if (ret < 0)
return ret;
st->mode = mode;
return 0;
}
static int ad7192_disable_all(struct ad_sigma_delta *sd)
{
struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
u32 conf = st->conf;
int ret;
conf &= ~AD7192_CONF_CHAN_MASK;
ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
if (ret < 0)
return ret;
st->conf = conf;
return 0;
}
static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
.set_channel = ad7192_set_channel,
.append_status = ad7192_append_status,
.disable_all = ad7192_disable_all,
.set_mode = ad7192_set_mode,
.has_registers = true,
.addr_shift = 3,
.read_mask = BIT(6),
.status_ch_mask = GENMASK(3, 0),
.num_slots = 4,
.irq_flags = IRQF_TRIGGER_FALLING,
};
static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
};
static int ad7192_calibrate_all(struct ad7192_state *st)
{
return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
ARRAY_SIZE(ad7192_calib_arr));
}
static inline bool ad7192_valid_external_frequency(u32 freq)
{
return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
freq <= AD7192_EXT_FREQ_MHZ_MAX);
}
static int ad7192_of_clock_select(struct ad7192_state *st)
{
struct device_node *np = st->sd.spi->dev.of_node;
unsigned int clock_sel;
clock_sel = AD7192_CLK_INT;
/* use internal clock */
if (!st->mclk) {
if (of_property_read_bool(np, "adi,int-clock-output-enable"))
clock_sel = AD7192_CLK_INT_CO;
} else {
if (of_property_read_bool(np, "adi,clock-xtal"))
clock_sel = AD7192_CLK_EXT_MCLK1_2;
else
clock_sel = AD7192_CLK_EXT_MCLK2;
}
return clock_sel;
}
static int ad7192_setup(struct iio_dev *indio_dev, struct device_node *np)
{
struct ad7192_state *st = iio_priv(indio_dev);
bool rej60_en, refin2_en;
bool buf_en, bipolar, burnout_curr_en;
unsigned long long scale_uv;
int i, ret, id;
/* reset the serial interface */
ret = ad_sd_reset(&st->sd, 48);
if (ret < 0)
return ret;
usleep_range(500, 1000); /* Wait for at least 500us */
/* write/read test for device presence */
ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
if (ret)
return ret;
id &= AD7192_ID_MASK;
if (id != st->chip_info->chip_id)
dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X != 0x%X)\n",
id, st->chip_info->chip_id);
st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
AD7192_MODE_CLKSRC(st->clock_sel) |
AD7192_MODE_RATE(480);
st->conf = AD7192_CONF_GAIN(0);
rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable");
if (rej60_en)
st->mode |= AD7192_MODE_REJ60;
refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable");
if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
st->conf |= AD7192_CONF_REFSEL;
st->conf &= ~AD7192_CONF_CHOP;
st->f_order = AD7192_NO_SYNC_FILTER;
buf_en = of_property_read_bool(np, "adi,buffer-enable");
if (buf_en)
st->conf |= AD7192_CONF_BUF;
bipolar = of_property_read_bool(np, "bipolar");
if (!bipolar)
st->conf |= AD7192_CONF_UNIPOLAR;
burnout_curr_en = of_property_read_bool(np,
"adi,burnout-currents-enable");
if (burnout_curr_en && buf_en) {
st->conf |= AD7192_CONF_BURN;
} else if (burnout_curr_en) {
dev_warn(&st->sd.spi->dev,
"Can't enable burnout currents: see CHOP or buffer\n");
}
ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
if (ret)
return ret;
ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
if (ret)
return ret;
ret = ad7192_calibrate_all(st);
if (ret)
return ret;
/* Populate available ADC input ranges */
for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
scale_uv = ((u64)st->int_vref_mv * 100000000)
>> (indio_dev->channels[0].scan_type.realbits -
((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
scale_uv >>= i;
st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
st->scale_avail[i][0] = scale_uv;
}
return 0;
}
static ssize_t ad7192_show_ac_excitation(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct ad7192_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", !!(st->conf & AD7192_CONF_ACX));
}
static ssize_t ad7192_show_bridge_switch(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct ad7192_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
}
static ssize_t ad7192_set(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct ad7192_state *st = iio_priv(indio_dev);
struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
int ret;
bool val;
ret = kstrtobool(buf, &val);
if (ret < 0)
return ret;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
switch ((u32)this_attr->address) {
case AD7192_REG_GPOCON:
if (val)
st->gpocon |= AD7192_GPOCON_BPDSW;
else
st->gpocon &= ~AD7192_GPOCON_BPDSW;
ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
break;
case AD7192_REG_CONF:
if (val)
st->conf |= AD7192_CONF_ACX;
else
st->conf &= ~AD7192_CONF_ACX;
ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
break;
default:
ret = -EINVAL;
}
iio_device_release_direct_mode(indio_dev);
return ret ? ret : len;
}
static void ad7192_get_available_filter_freq(struct ad7192_state *st,
int *freq)
{
unsigned int fadc;
/* Formulas for filter at page 25 of the datasheet */
fadc = DIV_ROUND_CLOSEST(st->fclk,
AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode));
freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
fadc = DIV_ROUND_CLOSEST(st->fclk,
AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode));
freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode));
freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
}
static ssize_t ad7192_show_filter_avail(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct ad7192_state *st = iio_priv(indio_dev);
unsigned int freq_avail[4], i;
size_t len = 0;
ad7192_get_available_filter_freq(st, freq_avail);
for (i = 0; i < ARRAY_SIZE(freq_avail); i++)
len += sysfs_emit_at(buf, len, "%d.%03d ", freq_avail[i] / 1000,
freq_avail[i] % 1000);
buf[len - 1] = '\n';
return len;
}
static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available,
0444, ad7192_show_filter_avail, NULL, 0);
static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
ad7192_show_bridge_switch, ad7192_set,
AD7192_REG_GPOCON);
static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
ad7192_show_ac_excitation, ad7192_set,
AD7192_REG_CONF);
static struct attribute *ad7192_attributes[] = {
&iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
&iio_dev_attr_bridge_switch_en.dev_attr.attr,
NULL
};
static const struct attribute_group ad7192_attribute_group = {
.attrs = ad7192_attributes,
};
static struct attribute *ad7195_attributes[] = {
&iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
&iio_dev_attr_bridge_switch_en.dev_attr.attr,
&iio_dev_attr_ac_excitation_en.dev_attr.attr,
NULL
};
static const struct attribute_group ad7195_attribute_group = {
.attrs = ad7195_attributes,
};
static unsigned int ad7192_get_temp_scale(bool unipolar)
{
return unipolar ? 2815 * 2 : 2815;
}
static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
int val, int val2)
{
int freq_avail[4], i, ret, freq;
unsigned int diff_new, diff_old;
int idx = 0;
diff_old = U32_MAX;
freq = val * 1000 + val2;
ad7192_get_available_filter_freq(st, freq_avail);
for (i = 0; i < ARRAY_SIZE(freq_avail); i++) {
diff_new = abs(freq - freq_avail[i]);
if (diff_new < diff_old) {
diff_old = diff_new;
idx = i;
}
}
switch (idx) {
case 0:
st->f_order = AD7192_SYNC4_FILTER;
st->mode &= ~AD7192_MODE_SINC3;
st->conf |= AD7192_CONF_CHOP;
break;
case 1:
st->f_order = AD7192_SYNC3_FILTER;
st->mode |= AD7192_MODE_SINC3;
st->conf |= AD7192_CONF_CHOP;
break;
case 2:
st->f_order = AD7192_NO_SYNC_FILTER;
st->mode &= ~AD7192_MODE_SINC3;
st->conf &= ~AD7192_CONF_CHOP;
break;
case 3:
st->f_order = AD7192_NO_SYNC_FILTER;
st->mode |= AD7192_MODE_SINC3;
st->conf &= ~AD7192_CONF_CHOP;
break;
}
ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
if (ret < 0)
return ret;
return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
}
static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
{
unsigned int fadc;
fadc = DIV_ROUND_CLOSEST(st->fclk,
st->f_order * AD7192_MODE_RATE(st->mode));
if (st->conf & AD7192_CONF_CHOP)
return DIV_ROUND_CLOSEST(fadc * 240, 1024);
if (st->mode & AD7192_MODE_SINC3)
return DIV_ROUND_CLOSEST(fadc * 272, 1024);
else
return DIV_ROUND_CLOSEST(fadc * 230, 1024);
}
static int ad7192_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct ad7192_state *st = iio_priv(indio_dev);
bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
switch (m) {
case IIO_CHAN_INFO_RAW:
return ad_sigma_delta_single_conversion(indio_dev, chan, val);
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_VOLTAGE:
mutex_lock(&st->lock);
*val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
*val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
mutex_unlock(&st->lock);
return IIO_VAL_INT_PLUS_NANO;
case IIO_TEMP:
*val = 0;
*val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
return IIO_VAL_INT_PLUS_NANO;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_OFFSET:
if (!unipolar)
*val = -(1 << (chan->scan_type.realbits - 1));
else
*val = 0;
/* Kelvin to Celsius */
if (chan->type == IIO_TEMP)
*val -= 273 * ad7192_get_temp_scale(unipolar);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SAMP_FREQ:
*val = st->fclk /
(st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
return IIO_VAL_INT;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
*val = ad7192_get_3db_filter_freq(st);
*val2 = 1000;
return IIO_VAL_FRACTIONAL;
}
return -EINVAL;
}
static int ad7192_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct ad7192_state *st = iio_priv(indio_dev);
int ret, i, div;
unsigned int tmp;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
ret = -EINVAL;
mutex_lock(&st->lock);
for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
if (val2 == st->scale_avail[i][1]) {
ret = 0;
tmp = st->conf;
st->conf &= ~AD7192_CONF_GAIN(-1);
st->conf |= AD7192_CONF_GAIN(i);
if (tmp == st->conf)
break;
ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
3, st->conf);
ad7192_calibrate_all(st);
break;
}
mutex_unlock(&st->lock);
break;
case IIO_CHAN_INFO_SAMP_FREQ:
if (!val) {
ret = -EINVAL;
break;
}
div = st->fclk / (val * st->f_order * 1024);
if (div < 1 || div > 1023) {
ret = -EINVAL;
break;
}
st->mode &= ~AD7192_MODE_RATE(-1);
st->mode |= AD7192_MODE_RATE(div);
ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
break;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
break;
default:
ret = -EINVAL;
}
iio_device_release_direct_mode(indio_dev);
return ret;
}
static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_SCALE:
return IIO_VAL_INT_PLUS_NANO;
case IIO_CHAN_INFO_SAMP_FREQ:
return IIO_VAL_INT;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int ad7192_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
struct ad7192_state *st = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_SCALE:
*vals = (int *)st->scale_avail;
*type = IIO_VAL_INT_PLUS_NANO;
/* Values are stored in a 2D matrix */
*length = ARRAY_SIZE(st->scale_avail) * 2;
return IIO_AVAIL_LIST;
}
return -EINVAL;
}
static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)
{
struct ad7192_state *st = iio_priv(indio_dev);
u32 conf = st->conf;
int ret;
int i;
conf &= ~AD7192_CONF_CHAN_MASK;
for_each_set_bit(i, scan_mask, 8)
conf |= AD7192_CONF_CHAN(i);
ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
if (ret < 0)
return ret;
st->conf = conf;
return 0;
}
static const struct iio_info ad7192_info = {
.read_raw = ad7192_read_raw,
.write_raw = ad7192_write_raw,
.write_raw_get_fmt = ad7192_write_raw_get_fmt,
.read_avail = ad7192_read_avail,
.attrs = &ad7192_attribute_group,
.validate_trigger = ad_sd_validate_trigger,
.update_scan_mode = ad7192_update_scan_mode,
};
static const struct iio_info ad7195_info = {
.read_raw = ad7192_read_raw,
.write_raw = ad7192_write_raw,
.write_raw_get_fmt = ad7192_write_raw_get_fmt,
.read_avail = ad7192_read_avail,
.attrs = &ad7195_attribute_group,
.validate_trigger = ad_sd_validate_trigger,
.update_scan_mode = ad7192_update_scan_mode,
};
#define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \
_type, _mask_type_av, _ext_info) \
{ \
.type = (_type), \
.differential = ((_channel2) == -1 ? 0 : 1), \
.indexed = 1, \
.channel = (_channel1), \
.channel2 = (_channel2), \
.address = (_address), \
.extend_name = (_extend_name), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_OFFSET), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
.info_mask_shared_by_type_available = (_mask_type_av), \
.ext_info = (_ext_info), \
.scan_index = (_si), \
.scan_type = { \
.sign = 'u', \
.realbits = 24, \
.storagebits = 32, \
.endianness = IIO_BE, \
}, \
}
#define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
__AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \
IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \
ad7192_calibsys_ext_info)
#define AD719x_CHANNEL(_si, _channel1, _address) \
__AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
#define AD719x_TEMP_CHANNEL(_si, _address) \
__AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
static const struct iio_chan_spec ad7192_channels[] = {
AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M),
AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
IIO_CHAN_SOFT_TIMESTAMP(8),
};
static const struct iio_chan_spec ad7193_channels[] = {
AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
AD719x_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M),
AD719x_CHANNEL(6, 1, AD7193_CH_AIN1),
AD719x_CHANNEL(7, 2, AD7193_CH_AIN2),
AD719x_CHANNEL(8, 3, AD7193_CH_AIN3),
AD719x_CHANNEL(9, 4, AD7193_CH_AIN4),
AD719x_CHANNEL(10, 5, AD7193_CH_AIN5),
AD719x_CHANNEL(11, 6, AD7193_CH_AIN6),
AD719x_CHANNEL(12, 7, AD7193_CH_AIN7),
AD719x_CHANNEL(13, 8, AD7193_CH_AIN8),
IIO_CHAN_SOFT_TIMESTAMP(14),
};
static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
[ID_AD7190] = {
.chip_id = CHIPID_AD7190,
.name = "ad7190",
},
[ID_AD7192] = {
.chip_id = CHIPID_AD7192,
.name = "ad7192",
},
[ID_AD7193] = {
.chip_id = CHIPID_AD7193,
.name = "ad7193",
},
[ID_AD7195] = {
.chip_id = CHIPID_AD7195,
.name = "ad7195",
},
};
static int ad7192_channels_config(struct iio_dev *indio_dev)
{
struct ad7192_state *st = iio_priv(indio_dev);
switch (st->chip_info->chip_id) {
case CHIPID_AD7193:
indio_dev->channels = ad7193_channels;
indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
break;
default:
indio_dev->channels = ad7192_channels;
indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
break;
}
return 0;
}
static void ad7192_reg_disable(void *reg)
{
regulator_disable(reg);
}
static int ad7192_probe(struct spi_device *spi)
{
struct ad7192_state *st;
struct iio_dev *indio_dev;
int ret;
if (!spi->irq) {
dev_err(&spi->dev, "no IRQ?\n");
return -ENODEV;
}
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
mutex_init(&st->lock);
st->avdd = devm_regulator_get(&spi->dev, "avdd");
if (IS_ERR(st->avdd))
return PTR_ERR(st->avdd);
ret = regulator_enable(st->avdd);
if (ret) {
dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
return ret;
}
ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd);
if (ret)
return ret;
ret = devm_regulator_get_enable(&spi->dev, "dvdd");
if (ret)
return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVdd supply\n");
ret = regulator_get_voltage(st->avdd);
if (ret < 0) {
dev_err(&spi->dev, "Device tree error, reference voltage undefined\n");
return ret;
}
st->int_vref_mv = ret / 1000;
st->chip_info = of_device_get_match_data(&spi->dev);
if (!st->chip_info)
st->chip_info = (void *)spi_get_device_id(spi)->driver_data;
indio_dev->name = st->chip_info->name;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = ad7192_channels_config(indio_dev);
if (ret < 0)
return ret;
if (st->chip_info->chip_id == CHIPID_AD7195)
indio_dev->info = &ad7195_info;
else
indio_dev->info = &ad7192_info;
ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
if (ret)
return ret;
ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
if (ret)
return ret;
st->fclk = AD7192_INT_FREQ_MHZ;
st->mclk = devm_clk_get_optional_enabled(&spi->dev, "mclk");
if (IS_ERR(st->mclk))
return PTR_ERR(st->mclk);
st->clock_sel = ad7192_of_clock_select(st);
if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
st->clock_sel == AD7192_CLK_EXT_MCLK2) {
st->fclk = clk_get_rate(st->mclk);
if (!ad7192_valid_external_frequency(st->fclk)) {
dev_err(&spi->dev,
"External clock frequency out of bounds\n");
return -EINVAL;
}
}
ret = ad7192_setup(indio_dev, spi->dev.of_node);
if (ret)
return ret;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct of_device_id ad7192_of_match[] = {
{ .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
{ .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
{ .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
{ .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
{}
};
MODULE_DEVICE_TABLE(of, ad7192_of_match);
static const struct spi_device_id ad7192_ids[] = {
{ "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] },
{ "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] },
{ "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] },
{ "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] },
{}
};
MODULE_DEVICE_TABLE(spi, ad7192_ids);
static struct spi_driver ad7192_driver = {
.driver = {
.name = "ad7192",
.of_match_table = ad7192_of_match,
},
.probe = ad7192_probe,
.id_table = ad7192_ids,
};
module_spi_driver(ad7192_driver);
MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
| linux-master | drivers/iio/adc/ad7192.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Atmel ADC driver for SAMA5D2 devices and compatible.
*
* Copyright (C) 2015 Atmel,
* 2015 Ludovic Desroches <[email protected]>
* 2021 Microchip Technology, Inc. and its subsidiaries
* 2021 Eugen Hristev <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/sched.h>
#include <linux/units.h>
#include <linux/wait.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/nvmem-consumer.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
struct at91_adc_reg_layout {
/* Control Register */
u16 CR;
/* Software Reset */
#define AT91_SAMA5D2_CR_SWRST BIT(0)
/* Start Conversion */
#define AT91_SAMA5D2_CR_START BIT(1)
/* Touchscreen Calibration */
#define AT91_SAMA5D2_CR_TSCALIB BIT(2)
/* Comparison Restart */
#define AT91_SAMA5D2_CR_CMPRST BIT(4)
/* Mode Register */
u16 MR;
/* Trigger Selection */
#define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
/* ADTRG */
#define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0
/* TIOA0 */
#define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1
/* TIOA1 */
#define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2
/* TIOA2 */
#define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3
/* PWM event line 0 */
#define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4
/* PWM event line 1 */
#define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5
/* TIOA3 */
#define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6
/* RTCOUT0 */
#define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7
/* Sleep Mode */
#define AT91_SAMA5D2_MR_SLEEP BIT(5)
/* Fast Wake Up */
#define AT91_SAMA5D2_MR_FWUP BIT(6)
/* Prescaler Rate Selection */
#define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
#define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8
#define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff
#define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8)
/* Startup Time */
#define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
#define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16)
/* Minimum startup time for temperature sensor */
#define AT91_SAMA5D2_MR_STARTUP_TS_MIN (50)
/* Analog Change */
#define AT91_SAMA5D2_MR_ANACH BIT(23)
/* Tracking Time */
#define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
#define AT91_SAMA5D2_MR_TRACKTIM_TS 6
#define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xf
/* Transfer Time */
#define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
#define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
/* Use Sequence Enable */
#define AT91_SAMA5D2_MR_USEQ BIT(31)
/* Channel Sequence Register 1 */
u16 SEQR1;
/* Channel Sequence Register 2 */
u16 SEQR2;
/* Channel Enable Register */
u16 CHER;
/* Channel Disable Register */
u16 CHDR;
/* Channel Status Register */
u16 CHSR;
/* Last Converted Data Register */
u16 LCDR;
/* Interrupt Enable Register */
u16 IER;
/* Interrupt Enable Register - TS X measurement ready */
#define AT91_SAMA5D2_IER_XRDY BIT(20)
/* Interrupt Enable Register - TS Y measurement ready */
#define AT91_SAMA5D2_IER_YRDY BIT(21)
/* Interrupt Enable Register - TS pressure measurement ready */
#define AT91_SAMA5D2_IER_PRDY BIT(22)
/* Interrupt Enable Register - Data ready */
#define AT91_SAMA5D2_IER_DRDY BIT(24)
/* Interrupt Enable Register - general overrun error */
#define AT91_SAMA5D2_IER_GOVRE BIT(25)
/* Interrupt Enable Register - Pen detect */
#define AT91_SAMA5D2_IER_PEN BIT(29)
/* Interrupt Enable Register - No pen detect */
#define AT91_SAMA5D2_IER_NOPEN BIT(30)
/* Interrupt Disable Register */
u16 IDR;
/* Interrupt Mask Register */
u16 IMR;
/* Interrupt Status Register */
u16 ISR;
/* End of Conversion Interrupt Enable Register */
u16 EOC_IER;
/* End of Conversion Interrupt Disable Register */
u16 EOC_IDR;
/* End of Conversion Interrupt Mask Register */
u16 EOC_IMR;
/* End of Conversion Interrupt Status Register */
u16 EOC_ISR;
/* Interrupt Status Register - Pen touching sense status */
#define AT91_SAMA5D2_ISR_PENS BIT(31)
/* Last Channel Trigger Mode Register */
u16 LCTMR;
/* Last Channel Compare Window Register */
u16 LCCWR;
/* Overrun Status Register */
u16 OVER;
/* Extended Mode Register */
u16 EMR;
/* Extended Mode Register - Oversampling rate */
#define AT91_SAMA5D2_EMR_OSR(V, M) (((V) << 16) & (M))
#define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0
#define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1
#define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2
#define AT91_SAMA5D2_EMR_OSR_64SAMPLES 3
#define AT91_SAMA5D2_EMR_OSR_256SAMPLES 4
/* Extended Mode Register - TRACKX */
#define AT91_SAMA5D2_TRACKX_MASK GENMASK(23, 22)
#define AT91_SAMA5D2_TRACKX(x) (((x) << 22) & \
AT91_SAMA5D2_TRACKX_MASK)
/* TRACKX for temperature sensor. */
#define AT91_SAMA5D2_TRACKX_TS (1)
/* Extended Mode Register - Averaging on single trigger event */
#define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20)
/* Compare Window Register */
u16 CWR;
/* Channel Gain Register */
u16 CGR;
/* Channel Offset Register */
u16 COR;
/* Channel Offset Register differential offset - constant, not a register */
u16 COR_diff_offset;
/* Analog Control Register */
u16 ACR;
/* Analog Control Register - Pen detect sensitivity mask */
#define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0)
/* Analog Control Register - Source last channel */
#define AT91_SAMA5D2_ACR_SRCLCH BIT(16)
/* Touchscreen Mode Register */
u16 TSMR;
/* Touchscreen Mode Register - No touch mode */
#define AT91_SAMA5D2_TSMR_TSMODE_NONE 0
/* Touchscreen Mode Register - 4 wire screen, no pressure measurement */
#define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1
/* Touchscreen Mode Register - 4 wire screen, pressure measurement */
#define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2
/* Touchscreen Mode Register - 5 wire screen */
#define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3
/* Touchscreen Mode Register - Average samples mask */
#define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4)
/* Touchscreen Mode Register - Average samples */
#define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4)
/* Touchscreen Mode Register - Touch/trigger frequency ratio mask */
#define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8)
/* Touchscreen Mode Register - Touch/trigger frequency ratio */
#define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8)
/* Touchscreen Mode Register - Pen Debounce Time mask */
#define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28)
/* Touchscreen Mode Register - Pen Debounce Time */
#define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28)
/* Touchscreen Mode Register - No DMA for touch measurements */
#define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22)
/* Touchscreen Mode Register - Disable pen detection */
#define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24)
/* Touchscreen Mode Register - Enable pen detection */
#define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24)
/* Touchscreen X Position Register */
u16 XPOSR;
/* Touchscreen Y Position Register */
u16 YPOSR;
/* Touchscreen Pressure Register */
u16 PRESSR;
/* Trigger Register */
u16 TRGR;
/* Mask for TRGMOD field of TRGR register */
#define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
/* No trigger, only software trigger can start conversions */
#define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
/* Trigger Mode external trigger rising edge */
#define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
/* Trigger Mode external trigger falling edge */
#define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
/* Trigger Mode external trigger any edge */
#define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
/* Trigger Mode internal periodic */
#define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5
/* Trigger Mode - trigger period mask */
#define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16)
/* Trigger Mode - trigger period */
#define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16)
/* Correction Select Register */
u16 COSR;
/* Correction Value Register */
u16 CVR;
/* Channel Error Correction Register */
u16 CECR;
/* Write Protection Mode Register */
u16 WPMR;
/* Write Protection Status Register */
u16 WPSR;
/* Version Register */
u16 VERSION;
/* Temperature Sensor Mode Register */
u16 TEMPMR;
/* Temperature Sensor Mode - Temperature sensor on */
#define AT91_SAMA5D2_TEMPMR_TEMPON BIT(0)
};
static const struct at91_adc_reg_layout sama5d2_layout = {
.CR = 0x00,
.MR = 0x04,
.SEQR1 = 0x08,
.SEQR2 = 0x0c,
.CHER = 0x10,
.CHDR = 0x14,
.CHSR = 0x18,
.LCDR = 0x20,
.IER = 0x24,
.IDR = 0x28,
.IMR = 0x2c,
.ISR = 0x30,
.LCTMR = 0x34,
.LCCWR = 0x38,
.OVER = 0x3c,
.EMR = 0x40,
.CWR = 0x44,
.CGR = 0x48,
.COR = 0x4c,
.COR_diff_offset = 16,
.ACR = 0x94,
.TSMR = 0xb0,
.XPOSR = 0xb4,
.YPOSR = 0xb8,
.PRESSR = 0xbc,
.TRGR = 0xc0,
.COSR = 0xd0,
.CVR = 0xd4,
.CECR = 0xd8,
.WPMR = 0xe4,
.WPSR = 0xe8,
.VERSION = 0xfc,
};
static const struct at91_adc_reg_layout sama7g5_layout = {
.CR = 0x00,
.MR = 0x04,
.SEQR1 = 0x08,
.SEQR2 = 0x0c,
.CHER = 0x10,
.CHDR = 0x14,
.CHSR = 0x18,
.LCDR = 0x20,
.IER = 0x24,
.IDR = 0x28,
.IMR = 0x2c,
.ISR = 0x30,
.EOC_IER = 0x34,
.EOC_IDR = 0x38,
.EOC_IMR = 0x3c,
.EOC_ISR = 0x40,
.TEMPMR = 0x44,
.OVER = 0x4c,
.EMR = 0x50,
.CWR = 0x54,
.COR = 0x5c,
.COR_diff_offset = 0,
.ACR = 0xe0,
.TRGR = 0x100,
.COSR = 0x104,
.CVR = 0x108,
.CECR = 0x10c,
.WPMR = 0x118,
.WPSR = 0x11c,
.VERSION = 0x130,
};
#define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
#define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200
#define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0)
#define AT91_SAMA5D2_MAX_POS_BITS 12
#define AT91_HWFIFO_MAX_SIZE_STR "128"
#define AT91_HWFIFO_MAX_SIZE 128
#define AT91_SAMA5D2_CHAN_SINGLE(index, num, addr) \
{ \
.type = IIO_VOLTAGE, \
.channel = num, \
.address = addr, \
.scan_index = index, \
.scan_type = { \
.sign = 'u', \
.realbits = 14, \
.storagebits = 16, \
}, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.info_mask_shared_by_all_available = \
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.datasheet_name = "CH"#num, \
.indexed = 1, \
}
#define AT91_SAMA5D2_CHAN_DIFF(index, num, num2, addr) \
{ \
.type = IIO_VOLTAGE, \
.differential = 1, \
.channel = num, \
.channel2 = num2, \
.address = addr, \
.scan_index = index, \
.scan_type = { \
.sign = 's', \
.realbits = 14, \
.storagebits = 16, \
}, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.info_mask_shared_by_all_available = \
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.datasheet_name = "CH"#num"-CH"#num2, \
.indexed = 1, \
}
#define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \
{ \
.type = IIO_POSITIONRELATIVE, \
.modified = 1, \
.channel = num, \
.channel2 = mod, \
.scan_index = num, \
.scan_type = { \
.sign = 'u', \
.realbits = 12, \
.storagebits = 16, \
}, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.info_mask_shared_by_all_available = \
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.datasheet_name = name, \
}
#define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \
{ \
.type = IIO_PRESSURE, \
.channel = num, \
.scan_index = num, \
.scan_type = { \
.sign = 'u', \
.realbits = 12, \
.storagebits = 16, \
}, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.info_mask_shared_by_all_available = \
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.datasheet_name = name, \
}
#define AT91_SAMA5D2_CHAN_TEMP(num, name, addr) \
{ \
.type = IIO_TEMP, \
.channel = num, \
.address = addr, \
.scan_index = num, \
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
.info_mask_shared_by_all = \
BIT(IIO_CHAN_INFO_PROCESSED) | \
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.info_mask_shared_by_all_available = \
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
.datasheet_name = name, \
}
#define at91_adc_readl(st, reg) \
readl_relaxed((st)->base + (st)->soc_info.platform->layout->reg)
#define at91_adc_read_chan(st, reg) \
readl_relaxed((st)->base + reg)
#define at91_adc_writel(st, reg, val) \
writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg)
/**
* struct at91_adc_platform - at91-sama5d2 platform information struct
* @layout: pointer to the reg layout struct
* @adc_channels: pointer to an array of channels for registering in
* the iio subsystem
* @nr_channels: number of physical channels available
* @touch_chan_x: index of the touchscreen X channel
* @touch_chan_y: index of the touchscreen Y channel
* @touch_chan_p: index of the touchscreen P channel
* @max_channels: number of total channels
* @max_index: highest channel index (highest index may be higher
* than the total channel number)
* @hw_trig_cnt: number of possible hardware triggers
* @osr_mask: oversampling ratio bitmask on EMR register
* @oversampling_avail: available oversampling values
* @oversampling_avail_no: number of available oversampling values
* @chan_realbits: realbits for registered channels
* @temp_chan: temperature channel index
* @temp_sensor: temperature sensor supported
*/
struct at91_adc_platform {
const struct at91_adc_reg_layout *layout;
const struct iio_chan_spec (*adc_channels)[];
unsigned int nr_channels;
unsigned int touch_chan_x;
unsigned int touch_chan_y;
unsigned int touch_chan_p;
unsigned int max_channels;
unsigned int max_index;
unsigned int hw_trig_cnt;
unsigned int osr_mask;
unsigned int oversampling_avail[5];
unsigned int oversampling_avail_no;
unsigned int chan_realbits;
unsigned int temp_chan;
bool temp_sensor;
};
/**
* struct at91_adc_temp_sensor_clb - at91-sama5d2 temperature sensor
* calibration data structure
* @p1: P1 calibration temperature
* @p4: P4 calibration voltage
* @p6: P6 calibration voltage
*/
struct at91_adc_temp_sensor_clb {
u32 p1;
u32 p4;
u32 p6;
};
/**
* enum at91_adc_ts_clb_idx - calibration indexes in NVMEM buffer
* @AT91_ADC_TS_CLB_IDX_P1: index for P1
* @AT91_ADC_TS_CLB_IDX_P4: index for P4
* @AT91_ADC_TS_CLB_IDX_P6: index for P6
* @AT91_ADC_TS_CLB_IDX_MAX: max index for temperature calibration packet in OTP
*/
enum at91_adc_ts_clb_idx {
AT91_ADC_TS_CLB_IDX_P1 = 2,
AT91_ADC_TS_CLB_IDX_P4 = 5,
AT91_ADC_TS_CLB_IDX_P6 = 7,
AT91_ADC_TS_CLB_IDX_MAX = 19,
};
/* Temperature sensor calibration - Vtemp voltage sensitivity to temperature. */
#define AT91_ADC_TS_VTEMP_DT (2080U)
/**
* struct at91_adc_soc_info - at91-sama5d2 soc information struct
* @startup_time: device startup time
* @min_sample_rate: minimum sample rate in Hz
* @max_sample_rate: maximum sample rate in Hz
* @platform: pointer to the platform structure
* @temp_sensor_clb: temperature sensor calibration data structure
*/
struct at91_adc_soc_info {
unsigned startup_time;
unsigned min_sample_rate;
unsigned max_sample_rate;
const struct at91_adc_platform *platform;
struct at91_adc_temp_sensor_clb temp_sensor_clb;
};
struct at91_adc_trigger {
char *name;
unsigned int trgmod_value;
unsigned int edge_type;
bool hw_trig;
};
/**
* struct at91_adc_dma - at91-sama5d2 dma information struct
* @dma_chan: the dma channel acquired
* @rx_buf: dma coherent allocated area
* @rx_dma_buf: dma handler for the buffer
* @phys_addr: physical address of the ADC base register
* @buf_idx: index inside the dma buffer where reading was last done
* @rx_buf_sz: size of buffer used by DMA operation
* @watermark: number of conversions to copy before DMA triggers irq
* @dma_ts: hold the start timestamp of dma operation
*/
struct at91_adc_dma {
struct dma_chan *dma_chan;
u8 *rx_buf;
dma_addr_t rx_dma_buf;
phys_addr_t phys_addr;
int buf_idx;
int rx_buf_sz;
int watermark;
s64 dma_ts;
};
/**
* struct at91_adc_touch - at91-sama5d2 touchscreen information struct
* @sample_period_val: the value for periodic trigger interval
* @touching: is the pen touching the screen or not
* @x_pos: temporary placeholder for pressure computation
* @channels_bitmask: bitmask with the touchscreen channels enabled
* @workq: workqueue for buffer data pushing
*/
struct at91_adc_touch {
u16 sample_period_val;
bool touching;
u16 x_pos;
unsigned long channels_bitmask;
struct work_struct workq;
};
/**
* struct at91_adc_temp - at91-sama5d2 temperature information structure
* @sample_period_val: sample period value
* @saved_sample_rate: saved sample rate
* @saved_oversampling: saved oversampling
*/
struct at91_adc_temp {
u16 sample_period_val;
u16 saved_sample_rate;
u16 saved_oversampling;
};
/*
* Buffer size requirements:
* No channels * bytes_per_channel(2) + timestamp bytes (8)
* Divided by 2 because we need half words.
* We assume 32 channels for now, has to be increased if needed.
* Nobody minds a buffer being too big.
*/
#define AT91_BUFFER_MAX_HWORDS ((32 * 2 + 8) / 2)
struct at91_adc_state {
void __iomem *base;
int irq;
struct clk *per_clk;
struct regulator *reg;
struct regulator *vref;
int vref_uv;
unsigned int current_sample_rate;
struct iio_trigger *trig;
const struct at91_adc_trigger *selected_trig;
const struct iio_chan_spec *chan;
bool conversion_done;
u32 conversion_value;
unsigned int oversampling_ratio;
struct at91_adc_soc_info soc_info;
wait_queue_head_t wq_data_available;
struct at91_adc_dma dma_st;
struct at91_adc_touch touch_st;
struct at91_adc_temp temp_st;
struct iio_dev *indio_dev;
struct device *dev;
/* Ensure naturally aligned timestamp */
u16 buffer[AT91_BUFFER_MAX_HWORDS] __aligned(8);
/*
* lock to prevent concurrent 'single conversion' requests through
* sysfs.
*/
struct mutex lock;
};
static const struct at91_adc_trigger at91_adc_trigger_list[] = {
{
.name = "external_rising",
.trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
.edge_type = IRQ_TYPE_EDGE_RISING,
.hw_trig = true,
},
{
.name = "external_falling",
.trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
.edge_type = IRQ_TYPE_EDGE_FALLING,
.hw_trig = true,
},
{
.name = "external_any",
.trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
.edge_type = IRQ_TYPE_EDGE_BOTH,
.hw_trig = true,
},
{
.name = "software",
.trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER,
.edge_type = IRQ_TYPE_NONE,
.hw_trig = false,
},
};
static const struct iio_chan_spec at91_sama5d2_adc_channels[] = {
AT91_SAMA5D2_CHAN_SINGLE(0, 0, 0x50),
AT91_SAMA5D2_CHAN_SINGLE(1, 1, 0x54),
AT91_SAMA5D2_CHAN_SINGLE(2, 2, 0x58),
AT91_SAMA5D2_CHAN_SINGLE(3, 3, 0x5c),
AT91_SAMA5D2_CHAN_SINGLE(4, 4, 0x60),
AT91_SAMA5D2_CHAN_SINGLE(5, 5, 0x64),
AT91_SAMA5D2_CHAN_SINGLE(6, 6, 0x68),
AT91_SAMA5D2_CHAN_SINGLE(7, 7, 0x6c),
AT91_SAMA5D2_CHAN_SINGLE(8, 8, 0x70),
AT91_SAMA5D2_CHAN_SINGLE(9, 9, 0x74),
AT91_SAMA5D2_CHAN_SINGLE(10, 10, 0x78),
AT91_SAMA5D2_CHAN_SINGLE(11, 11, 0x7c),
/* original ABI has the differential channels with a gap in between */
AT91_SAMA5D2_CHAN_DIFF(12, 0, 1, 0x50),
AT91_SAMA5D2_CHAN_DIFF(14, 2, 3, 0x58),
AT91_SAMA5D2_CHAN_DIFF(16, 4, 5, 0x60),
AT91_SAMA5D2_CHAN_DIFF(18, 6, 7, 0x68),
AT91_SAMA5D2_CHAN_DIFF(20, 8, 9, 0x70),
AT91_SAMA5D2_CHAN_DIFF(22, 10, 11, 0x78),
IIO_CHAN_SOFT_TIMESTAMP(23),
AT91_SAMA5D2_CHAN_TOUCH(24, "x", IIO_MOD_X),
AT91_SAMA5D2_CHAN_TOUCH(25, "y", IIO_MOD_Y),
AT91_SAMA5D2_CHAN_PRESSURE(26, "pressure"),
};
static const struct iio_chan_spec at91_sama7g5_adc_channels[] = {
AT91_SAMA5D2_CHAN_SINGLE(0, 0, 0x60),
AT91_SAMA5D2_CHAN_SINGLE(1, 1, 0x64),
AT91_SAMA5D2_CHAN_SINGLE(2, 2, 0x68),
AT91_SAMA5D2_CHAN_SINGLE(3, 3, 0x6c),
AT91_SAMA5D2_CHAN_SINGLE(4, 4, 0x70),
AT91_SAMA5D2_CHAN_SINGLE(5, 5, 0x74),
AT91_SAMA5D2_CHAN_SINGLE(6, 6, 0x78),
AT91_SAMA5D2_CHAN_SINGLE(7, 7, 0x7c),
AT91_SAMA5D2_CHAN_SINGLE(8, 8, 0x80),
AT91_SAMA5D2_CHAN_SINGLE(9, 9, 0x84),
AT91_SAMA5D2_CHAN_SINGLE(10, 10, 0x88),
AT91_SAMA5D2_CHAN_SINGLE(11, 11, 0x8c),
AT91_SAMA5D2_CHAN_SINGLE(12, 12, 0x90),
AT91_SAMA5D2_CHAN_SINGLE(13, 13, 0x94),
AT91_SAMA5D2_CHAN_SINGLE(14, 14, 0x98),
AT91_SAMA5D2_CHAN_SINGLE(15, 15, 0x9c),
AT91_SAMA5D2_CHAN_DIFF(16, 0, 1, 0x60),
AT91_SAMA5D2_CHAN_DIFF(17, 2, 3, 0x68),
AT91_SAMA5D2_CHAN_DIFF(18, 4, 5, 0x70),
AT91_SAMA5D2_CHAN_DIFF(19, 6, 7, 0x78),
AT91_SAMA5D2_CHAN_DIFF(20, 8, 9, 0x80),
AT91_SAMA5D2_CHAN_DIFF(21, 10, 11, 0x88),
AT91_SAMA5D2_CHAN_DIFF(22, 12, 13, 0x90),
AT91_SAMA5D2_CHAN_DIFF(23, 14, 15, 0x98),
IIO_CHAN_SOFT_TIMESTAMP(24),
AT91_SAMA5D2_CHAN_TEMP(AT91_SAMA7G5_ADC_TEMP_CHANNEL, "temp", 0xdc),
};
static const struct at91_adc_platform sama5d2_platform = {
.layout = &sama5d2_layout,
.adc_channels = &at91_sama5d2_adc_channels,
#define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
#define AT91_SAMA5D2_DIFF_CHAN_CNT 6
.nr_channels = AT91_SAMA5D2_SINGLE_CHAN_CNT +
AT91_SAMA5D2_DIFF_CHAN_CNT,
#define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
AT91_SAMA5D2_DIFF_CHAN_CNT * 2)
.touch_chan_x = AT91_SAMA5D2_TOUCH_X_CHAN_IDX,
#define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1)
.touch_chan_y = AT91_SAMA5D2_TOUCH_Y_CHAN_IDX,
#define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1)
.touch_chan_p = AT91_SAMA5D2_TOUCH_P_CHAN_IDX,
#define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX
.max_channels = ARRAY_SIZE(at91_sama5d2_adc_channels),
.max_index = AT91_SAMA5D2_MAX_CHAN_IDX,
#define AT91_SAMA5D2_HW_TRIG_CNT 3
.hw_trig_cnt = AT91_SAMA5D2_HW_TRIG_CNT,
.osr_mask = GENMASK(17, 16),
.oversampling_avail = { 1, 4, 16, },
.oversampling_avail_no = 3,
.chan_realbits = 14,
};
static const struct at91_adc_platform sama7g5_platform = {
.layout = &sama7g5_layout,
.adc_channels = &at91_sama7g5_adc_channels,
#define AT91_SAMA7G5_SINGLE_CHAN_CNT 16
#define AT91_SAMA7G5_DIFF_CHAN_CNT 8
#define AT91_SAMA7G5_TEMP_CHAN_CNT 1
.nr_channels = AT91_SAMA7G5_SINGLE_CHAN_CNT +
AT91_SAMA7G5_DIFF_CHAN_CNT +
AT91_SAMA7G5_TEMP_CHAN_CNT,
#define AT91_SAMA7G5_MAX_CHAN_IDX (AT91_SAMA7G5_SINGLE_CHAN_CNT + \
AT91_SAMA7G5_DIFF_CHAN_CNT + \
AT91_SAMA7G5_TEMP_CHAN_CNT)
.max_channels = ARRAY_SIZE(at91_sama7g5_adc_channels),
.max_index = AT91_SAMA7G5_MAX_CHAN_IDX,
#define AT91_SAMA7G5_HW_TRIG_CNT 3
.hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT,
.osr_mask = GENMASK(18, 16),
.oversampling_avail = { 1, 4, 16, 64, 256, },
.oversampling_avail_no = 5,
.chan_realbits = 16,
.temp_sensor = true,
.temp_chan = AT91_SAMA7G5_ADC_TEMP_CHANNEL,
};
static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
{
int i;
for (i = 0; i < indio_dev->num_channels; i++) {
if (indio_dev->channels[i].scan_index == chan)
return i;
}
return -EINVAL;
}
static inline struct iio_chan_spec const *
at91_adc_chan_get(struct iio_dev *indio_dev, int chan)
{
int index = at91_adc_chan_xlate(indio_dev, chan);
if (index < 0)
return NULL;
return indio_dev->channels + index;
}
static inline int at91_adc_fwnode_xlate(struct iio_dev *indio_dev,
const struct fwnode_reference_args *iiospec)
{
return at91_adc_chan_xlate(indio_dev, iiospec->args[0]);
}
static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev)
{
u32 mask = 0;
u8 bit;
struct at91_adc_state *st = iio_priv(indio_dev);
for_each_set_bit(bit, indio_dev->active_scan_mask,
indio_dev->num_channels) {
struct iio_chan_spec const *chan =
at91_adc_chan_get(indio_dev, bit);
mask |= BIT(chan->channel);
}
return mask & GENMASK(st->soc_info.platform->nr_channels, 0);
}
static void at91_adc_cor(struct at91_adc_state *st,
struct iio_chan_spec const *chan)
{
u32 cor, cur_cor;
cor = BIT(chan->channel) | BIT(chan->channel2);
cur_cor = at91_adc_readl(st, COR);
cor <<= st->soc_info.platform->layout->COR_diff_offset;
if (chan->differential)
at91_adc_writel(st, COR, cur_cor | cor);
else
at91_adc_writel(st, COR, cur_cor & ~cor);
}
static void at91_adc_irq_status(struct at91_adc_state *st, u32 *status,
u32 *eoc)
{
*status = at91_adc_readl(st, ISR);
if (st->soc_info.platform->layout->EOC_ISR)
*eoc = at91_adc_readl(st, EOC_ISR);
else
*eoc = *status;
}
static void at91_adc_irq_mask(struct at91_adc_state *st, u32 *status, u32 *eoc)
{
*status = at91_adc_readl(st, IMR);
if (st->soc_info.platform->layout->EOC_IMR)
*eoc = at91_adc_readl(st, EOC_IMR);
else
*eoc = *status;
}
static void at91_adc_eoc_dis(struct at91_adc_state *st, unsigned int channel)
{
/*
* On some products having the EOC bits in a separate register,
* errata recommends not writing this register (EOC_IDR).
* On products having the EOC bits in the IDR register, it's fine to write it.
*/
if (!st->soc_info.platform->layout->EOC_IDR)
at91_adc_writel(st, IDR, BIT(channel));
}
static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel)
{
if (!st->soc_info.platform->layout->EOC_IDR)
at91_adc_writel(st, IER, BIT(channel));
else
at91_adc_writel(st, EOC_IER, BIT(channel));
}
static int at91_adc_config_emr(struct at91_adc_state *st,
u32 oversampling_ratio, u32 trackx)
{
/* configure the extended mode register */
unsigned int emr, osr;
unsigned int osr_mask = st->soc_info.platform->osr_mask;
int i, ret;
/* Check against supported oversampling values. */
for (i = 0; i < st->soc_info.platform->oversampling_avail_no; i++) {
if (oversampling_ratio == st->soc_info.platform->oversampling_avail[i])
break;
}
if (i == st->soc_info.platform->oversampling_avail_no)
return -EINVAL;
/* select oversampling ratio from configuration */
switch (oversampling_ratio) {
case 1:
osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES,
osr_mask);
break;
case 4:
osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES,
osr_mask);
break;
case 16:
osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES,
osr_mask);
break;
case 64:
osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_64SAMPLES,
osr_mask);
break;
case 256:
osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_256SAMPLES,
osr_mask);
break;
}
ret = pm_runtime_resume_and_get(st->dev);
if (ret < 0)
return ret;
emr = at91_adc_readl(st, EMR);
/* select oversampling per single trigger event */
emr |= AT91_SAMA5D2_EMR_ASTE(1);
/* delete leftover content if it's the case */
emr &= ~(osr_mask | AT91_SAMA5D2_TRACKX_MASK);
/* Update osr and trackx. */
emr |= osr | AT91_SAMA5D2_TRACKX(trackx);
at91_adc_writel(st, EMR, emr);
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_autosuspend(st->dev);
st->oversampling_ratio = oversampling_ratio;
return 0;
}
static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
{
int nbits, diff;
if (st->oversampling_ratio == 1)
nbits = 12;
else if (st->oversampling_ratio == 4)
nbits = 13;
else if (st->oversampling_ratio == 16)
nbits = 14;
else if (st->oversampling_ratio == 64)
nbits = 15;
else if (st->oversampling_ratio == 256)
nbits = 16;
else
/* Should not happen. */
return -EINVAL;
/*
* We have nbits of real data and channel is registered as
* st->soc_info.platform->chan_realbits, so shift left diff bits.
*/
diff = st->soc_info.platform->chan_realbits - nbits;
*val <<= diff;
return IIO_VAL_INT;
}
static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf,
int len)
{
int i = 0, val;
u16 *buf_u16 = (u16 *) buf;
/*
* We are converting each two bytes (each sample).
* First convert the byte based array to u16, and convert each sample
* separately.
* Each value is two bytes in an array of chars, so to not shift
* more than we need, save the value separately.
* len is in bytes, so divide by two to get number of samples.
*/
while (i < len / 2) {
val = buf_u16[i];
at91_adc_adjust_val_osr(st, &val);
buf_u16[i] = val;
i++;
}
}
static int at91_adc_configure_touch(struct at91_adc_state *st, bool state)
{
u32 clk_khz = st->current_sample_rate / 1000;
int i = 0, ret;
u16 pendbc;
u32 tsmr, acr;
if (state) {
ret = pm_runtime_resume_and_get(st->dev);
if (ret < 0)
return ret;
} else {
/* disabling touch IRQs and setting mode to no touch enabled */
at91_adc_writel(st, IDR,
AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN);
at91_adc_writel(st, TSMR, 0);
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_autosuspend(st->dev);
return 0;
}
/*
* debounce time is in microseconds, we need it in milliseconds to
* multiply with kilohertz, so, divide by 1000, but after the multiply.
* round up to make sure pendbc is at least 1
*/
pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US *
clk_khz / 1000, 1);
/* get the required exponent */
while (pendbc >> i++)
;
pendbc = i;
tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS;
tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK;
tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) &
AT91_SAMA5D2_TSMR_PENDBC_MASK;
tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA;
tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA;
tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK;
at91_adc_writel(st, TSMR, tsmr);
acr = at91_adc_readl(st, ACR);
acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK;
acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK;
at91_adc_writel(st, ACR, acr);
/* Sample Period Time = (TRGPER + 1) / ADCClock */
st->touch_st.sample_period_val =
round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US *
clk_khz / 1000) - 1, 1);
/* enable pen detect IRQ */
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
return 0;
}
static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg)
{
u32 val = 0;
u32 scale, result, pos;
/*
* to obtain the actual position we must divide by scale
* and multiply with max, where
* max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1
*/
/* first half of register is the x or y, second half is the scale */
if (reg == st->soc_info.platform->layout->XPOSR)
val = at91_adc_readl(st, XPOSR);
else if (reg == st->soc_info.platform->layout->YPOSR)
val = at91_adc_readl(st, YPOSR);
if (!val)
dev_dbg(&st->indio_dev->dev, "pos is 0\n");
pos = val & AT91_SAMA5D2_XYZ_MASK;
result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos;
scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
if (scale == 0) {
dev_err(&st->indio_dev->dev, "scale is 0\n");
return 0;
}
result /= scale;
return result;
}
static u16 at91_adc_touch_x_pos(struct at91_adc_state *st)
{
st->touch_st.x_pos = at91_adc_touch_pos(st, st->soc_info.platform->layout->XPOSR);
return st->touch_st.x_pos;
}
static u16 at91_adc_touch_y_pos(struct at91_adc_state *st)
{
return at91_adc_touch_pos(st, st->soc_info.platform->layout->YPOSR);
}
static u16 at91_adc_touch_pressure(struct at91_adc_state *st)
{
u32 val;
u32 z1, z2;
u32 pres;
u32 rxp = 1;
u32 factor = 1000;
/* calculate the pressure */
val = at91_adc_readl(st, PRESSR);
z1 = val & AT91_SAMA5D2_XYZ_MASK;
z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
if (z1 != 0)
pres = rxp * (st->touch_st.x_pos * factor / 1024) *
(z2 * factor / z1 - factor) /
factor;
else
pres = 0xFFFF; /* no pen contact */
/*
* The pressure from device grows down, minimum is 0xFFFF, maximum 0x0.
* We compute it this way, but let's return it in the expected way,
* growing from 0 to 0xFFFF.
*/
return 0xFFFF - pres;
}
static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
{
*val = 0;
if (!st->touch_st.touching)
return -ENODATA;
if (chan == st->soc_info.platform->touch_chan_x)
*val = at91_adc_touch_x_pos(st);
else if (chan == st->soc_info.platform->touch_chan_y)
*val = at91_adc_touch_y_pos(st);
else
return -ENODATA;
return IIO_VAL_INT;
}
static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
{
*val = 0;
if (!st->touch_st.touching)
return -ENODATA;
if (chan == st->soc_info.platform->touch_chan_p)
*val = at91_adc_touch_pressure(st);
else
return -ENODATA;
return IIO_VAL_INT;
}
static void at91_adc_configure_trigger_registers(struct at91_adc_state *st,
bool state)
{
u32 status = at91_adc_readl(st, TRGR);
/* clear TRGMOD */
status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
if (state)
status |= st->selected_trig->trgmod_value;
/* set/unset hw trigger */
at91_adc_writel(st, TRGR, status);
}
static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
{
struct iio_dev *indio = iio_trigger_get_drvdata(trig);
struct at91_adc_state *st = iio_priv(indio);
int ret;
if (state) {
ret = pm_runtime_resume_and_get(st->dev);
if (ret < 0)
return ret;
}
at91_adc_configure_trigger_registers(st, state);
if (!state) {
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_autosuspend(st->dev);
}
return 0;
}
static void at91_adc_reenable_trigger(struct iio_trigger *trig)
{
struct iio_dev *indio = iio_trigger_get_drvdata(trig);
struct at91_adc_state *st = iio_priv(indio);
/* if we are using DMA, we must not reenable irq after each trigger */
if (st->dma_st.dma_chan)
return;
enable_irq(st->irq);
/* Needed to ACK the DRDY interruption */
at91_adc_readl(st, LCDR);
}
static const struct iio_trigger_ops at91_adc_trigger_ops = {
.set_trigger_state = &at91_adc_configure_trigger,
.reenable = &at91_adc_reenable_trigger,
.validate_device = iio_trigger_validate_own_device,
};
static int at91_adc_dma_size_done(struct at91_adc_state *st)
{
struct dma_tx_state state;
enum dma_status status;
int i, size;
status = dmaengine_tx_status(st->dma_st.dma_chan,
st->dma_st.dma_chan->cookie,
&state);
if (status != DMA_IN_PROGRESS)
return 0;
/* Transferred length is size in bytes from end of buffer */
i = st->dma_st.rx_buf_sz - state.residue;
/* Return available bytes */
if (i >= st->dma_st.buf_idx)
size = i - st->dma_st.buf_idx;
else
size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
return size;
}
static void at91_dma_buffer_done(void *data)
{
struct iio_dev *indio_dev = data;
iio_trigger_poll_nested(indio_dev->trig);
}
static int at91_adc_dma_start(struct iio_dev *indio_dev)
{
struct at91_adc_state *st = iio_priv(indio_dev);
struct dma_async_tx_descriptor *desc;
dma_cookie_t cookie;
int ret;
u8 bit;
if (!st->dma_st.dma_chan)
return 0;
/* we start a new DMA, so set buffer index to start */
st->dma_st.buf_idx = 0;
/*
* compute buffer size w.r.t. watermark and enabled channels.
* scan_bytes is aligned so we need an exact size for DMA
*/
st->dma_st.rx_buf_sz = 0;
for_each_set_bit(bit, indio_dev->active_scan_mask,
indio_dev->num_channels) {
struct iio_chan_spec const *chan =
at91_adc_chan_get(indio_dev, bit);
if (!chan)
continue;
st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
}
st->dma_st.rx_buf_sz *= st->dma_st.watermark;
/* Prepare a DMA cyclic transaction */
desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
st->dma_st.rx_dma_buf,
st->dma_st.rx_buf_sz,
st->dma_st.rx_buf_sz / 2,
DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
if (!desc) {
dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n");
return -EBUSY;
}
desc->callback = at91_dma_buffer_done;
desc->callback_param = indio_dev;
cookie = dmaengine_submit(desc);
ret = dma_submit_error(cookie);
if (ret) {
dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n");
dmaengine_terminate_async(st->dma_st.dma_chan);
return ret;
}
/* enable general overrun error signaling */
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_GOVRE);
/* Issue pending DMA requests */
dma_async_issue_pending(st->dma_st.dma_chan);
/* consider current time as DMA start time for timestamps */
st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
dev_dbg(&indio_dev->dev, "DMA cyclic started\n");
return 0;
}
static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio,
struct at91_adc_state *st)
{
/* if using DMA, we do not use our own IRQ (we use DMA-controller) */
if (st->dma_st.dma_chan)
return false;
/* if the trigger is not ours, then it has its own IRQ */
if (iio_trigger_validate_own_device(indio->trig, indio))
return false;
return true;
}
static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev)
{
struct at91_adc_state *st = iio_priv(indio_dev);
return !!bitmap_subset(indio_dev->active_scan_mask,
&st->touch_st.channels_bitmask,
st->soc_info.platform->max_index + 1);
}
static int at91_adc_buffer_prepare(struct iio_dev *indio_dev)
{
int ret;
u8 bit;
struct at91_adc_state *st = iio_priv(indio_dev);
/* check if we are enabling triggered buffer or the touchscreen */
if (at91_adc_current_chan_is_touch(indio_dev))
return at91_adc_configure_touch(st, true);
/* if we are not in triggered mode, we cannot enable the buffer. */
if (!(iio_device_get_current_mode(indio_dev) & INDIO_ALL_TRIGGERED_MODES))
return -EINVAL;
ret = pm_runtime_resume_and_get(st->dev);
if (ret < 0)
return ret;
/* we continue with the triggered buffer */
ret = at91_adc_dma_start(indio_dev);
if (ret) {
dev_err(&indio_dev->dev, "buffer prepare failed\n");
goto pm_runtime_put;
}
for_each_set_bit(bit, indio_dev->active_scan_mask,
indio_dev->num_channels) {
struct iio_chan_spec const *chan =
at91_adc_chan_get(indio_dev, bit);
if (!chan)
continue;
/* these channel types cannot be handled by this trigger */
if (chan->type == IIO_POSITIONRELATIVE ||
chan->type == IIO_PRESSURE ||
chan->type == IIO_TEMP)
continue;
at91_adc_cor(st, chan);
at91_adc_writel(st, CHER, BIT(chan->channel));
}
if (at91_adc_buffer_check_use_irq(indio_dev, st))
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_DRDY);
pm_runtime_put:
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_autosuspend(st->dev);
return ret;
}
static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev)
{
struct at91_adc_state *st = iio_priv(indio_dev);
int ret;
u8 bit;
/* check if we are disabling triggered buffer or the touchscreen */
if (at91_adc_current_chan_is_touch(indio_dev))
return at91_adc_configure_touch(st, false);
/* if we are not in triggered mode, nothing to do here */
if (!(iio_device_get_current_mode(indio_dev) & INDIO_ALL_TRIGGERED_MODES))
return -EINVAL;
ret = pm_runtime_resume_and_get(st->dev);
if (ret < 0)
return ret;
/*
* For each enable channel we must disable it in hardware.
* In the case of DMA, we must read the last converted value
* to clear EOC status and not get a possible interrupt later.
* This value is being read by DMA from LCDR anyway, so it's not lost.
*/
for_each_set_bit(bit, indio_dev->active_scan_mask,
indio_dev->num_channels) {
struct iio_chan_spec const *chan =
at91_adc_chan_get(indio_dev, bit);
if (!chan)
continue;
/* these channel types are virtual, no need to do anything */
if (chan->type == IIO_POSITIONRELATIVE ||
chan->type == IIO_PRESSURE ||
chan->type == IIO_TEMP)
continue;
at91_adc_writel(st, CHDR, BIT(chan->channel));
if (st->dma_st.dma_chan)
at91_adc_read_chan(st, chan->address);
}
if (at91_adc_buffer_check_use_irq(indio_dev, st))
at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_DRDY);
/* read overflow register to clear possible overflow status */
at91_adc_readl(st, OVER);
/* if we are using DMA we must clear registers and end DMA */
if (st->dma_st.dma_chan)
dmaengine_terminate_sync(st->dma_st.dma_chan);
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_autosuspend(st->dev);
return 0;
}
static const struct iio_buffer_setup_ops at91_buffer_setup_ops = {
.postdisable = &at91_adc_buffer_postdisable,
};
static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
char *trigger_name)
{
struct iio_trigger *trig;
int ret;
trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
iio_device_id(indio), trigger_name);
if (!trig)
return ERR_PTR(-ENOMEM);
trig->dev.parent = indio->dev.parent;
iio_trigger_set_drvdata(trig, indio);
trig->ops = &at91_adc_trigger_ops;
ret = devm_iio_trigger_register(&indio->dev, trig);
if (ret)
return ERR_PTR(ret);
return trig;
}
static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev,
struct iio_poll_func *pf)
{
struct at91_adc_state *st = iio_priv(indio_dev);
int i = 0;
int val;
u8 bit;
u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev);
unsigned int timeout = 50;
u32 status, imr, eoc = 0, eoc_imr;
/*
* Check if the conversion is ready. If not, wait a little bit, and
* in case of timeout exit with an error.
*/
while (((eoc & mask) != mask) && timeout) {
at91_adc_irq_status(st, &status, &eoc);
at91_adc_irq_mask(st, &imr, &eoc_imr);
usleep_range(50, 100);
timeout--;
}
/* Cannot read data, not ready. Continue without reporting data */
if (!timeout)
return;
for_each_set_bit(bit, indio_dev->active_scan_mask,
indio_dev->num_channels) {
struct iio_chan_spec const *chan =
at91_adc_chan_get(indio_dev, bit);
if (!chan)
continue;
/*
* Our external trigger only supports the voltage channels.
* In case someone requested a different type of channel
* just put zeroes to buffer.
* This should not happen because we check the scan mode
* and scan mask when we enable the buffer, and we don't allow
* the buffer to start with a mixed mask (voltage and something
* else).
* Thus, emit a warning.
*/
if (chan->type == IIO_VOLTAGE) {
val = at91_adc_read_chan(st, chan->address);
at91_adc_adjust_val_osr(st, &val);
st->buffer[i] = val;
} else {
st->buffer[i] = 0;
WARN(true, "This trigger cannot handle this type of channel");
}
i++;
}
iio_push_to_buffers_with_timestamp(indio_dev, st->buffer,
pf->timestamp);
}
static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev)
{
struct at91_adc_state *st = iio_priv(indio_dev);
int transferred_len = at91_adc_dma_size_done(st);
s64 ns = iio_get_time_ns(indio_dev);
s64 interval;
int sample_index = 0, sample_count, sample_size;
u32 status = at91_adc_readl(st, ISR);
/* if we reached this point, we cannot sample faster */
if (status & AT91_SAMA5D2_IER_GOVRE)
pr_info_ratelimited("%s: conversion overrun detected\n",
indio_dev->name);
sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
sample_count = div_s64(transferred_len, sample_size);
/*
* interval between samples is total time since last transfer handling
* divided by the number of samples (total size divided by sample size)
*/
interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
while (transferred_len >= sample_size) {
/*
* for all the values in the current sample,
* adjust the values inside the buffer for oversampling
*/
at91_adc_adjust_val_osr_array(st,
&st->dma_st.rx_buf[st->dma_st.buf_idx],
sample_size);
iio_push_to_buffers_with_timestamp(indio_dev,
(st->dma_st.rx_buf + st->dma_st.buf_idx),
(st->dma_st.dma_ts + interval * sample_index));
/* adjust remaining length */
transferred_len -= sample_size;
/* adjust buffer index */
st->dma_st.buf_idx += sample_size;
/* in case of reaching end of buffer, reset index */
if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
st->dma_st.buf_idx = 0;
sample_index++;
}
/* adjust saved time for next transfer handling */
st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
}
static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct at91_adc_state *st = iio_priv(indio_dev);
/*
* If it's not our trigger, start a conversion now, as we are
* actually polling the trigger now.
*/
if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev))
at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);
if (st->dma_st.dma_chan)
at91_adc_trigger_handler_dma(indio_dev);
else
at91_adc_trigger_handler_nodma(indio_dev, pf);
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static unsigned at91_adc_startup_time(unsigned startup_time_min,
unsigned adc_clk_khz)
{
static const unsigned int startup_lookup[] = {
0, 8, 16, 24,
64, 80, 96, 112,
512, 576, 640, 704,
768, 832, 896, 960
};
unsigned ticks_min, i;
/*
* Since the adc frequency is checked before, there is no reason
* to not meet the startup time constraint.
*/
ticks_min = startup_time_min * adc_clk_khz / 1000;
for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
if (startup_lookup[i] > ticks_min)
break;
return i;
}
static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq,
unsigned int startup_time,
unsigned int tracktim)
{
struct at91_adc_state *st = iio_priv(indio_dev);
unsigned f_per, prescal, startup, mr;
int ret;
f_per = clk_get_rate(st->per_clk);
prescal = (f_per / (2 * freq)) - 1;
startup = at91_adc_startup_time(startup_time, freq / 1000);
ret = pm_runtime_resume_and_get(st->dev);
if (ret < 0)
return;
mr = at91_adc_readl(st, MR);
mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
mr |= AT91_SAMA5D2_MR_STARTUP(startup);
mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
mr |= AT91_SAMA5D2_MR_TRACKTIM(tracktim);
at91_adc_writel(st, MR, mr);
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_autosuspend(st->dev);
dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u, tracktim=%u\n",
freq, startup, prescal, tracktim);
st->current_sample_rate = freq;
}
static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
{
return st->current_sample_rate;
}
static void at91_adc_touch_data_handler(struct iio_dev *indio_dev)
{
struct at91_adc_state *st = iio_priv(indio_dev);
u8 bit;
u16 val;
int i = 0;
for_each_set_bit(bit, indio_dev->active_scan_mask,
st->soc_info.platform->max_index + 1) {
struct iio_chan_spec const *chan =
at91_adc_chan_get(indio_dev, bit);
if (chan->type == IIO_POSITIONRELATIVE)
at91_adc_read_position(st, chan->channel, &val);
else if (chan->type == IIO_PRESSURE)
at91_adc_read_pressure(st, chan->channel, &val);
else
continue;
st->buffer[i] = val;
i++;
}
/*
* Schedule work to push to buffers.
* This is intended to push to the callback buffer that another driver
* registered. We are still in a handler from our IRQ. If we push
* directly, it means the other driver has it's callback called
* from our IRQ context. Which is something we better avoid.
* Let's schedule it after our IRQ is completed.
*/
schedule_work(&st->touch_st.workq);
}
static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st)
{
at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN);
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_NOPEN |
AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
AT91_SAMA5D2_IER_PRDY);
at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val));
st->touch_st.touching = true;
}
static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev)
{
struct at91_adc_state *st = iio_priv(indio_dev);
at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_NOPEN |
AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
AT91_SAMA5D2_IER_PRDY);
st->touch_st.touching = false;
at91_adc_touch_data_handler(indio_dev);
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
}
static void at91_adc_workq_handler(struct work_struct *workq)
{
struct at91_adc_touch *touch_st = container_of(workq,
struct at91_adc_touch, workq);
struct at91_adc_state *st = container_of(touch_st,
struct at91_adc_state, touch_st);
struct iio_dev *indio_dev = st->indio_dev;
iio_push_to_buffers(indio_dev, st->buffer);
}
static irqreturn_t at91_adc_interrupt(int irq, void *private)
{
struct iio_dev *indio = private;
struct at91_adc_state *st = iio_priv(indio);
u32 status, eoc, imr, eoc_imr;
u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
AT91_SAMA5D2_IER_PRDY;
at91_adc_irq_status(st, &status, &eoc);
at91_adc_irq_mask(st, &imr, &eoc_imr);
if (!(status & imr) && !(eoc & eoc_imr))
return IRQ_NONE;
if (status & AT91_SAMA5D2_IER_PEN) {
/* pen detected IRQ */
at91_adc_pen_detect_interrupt(st);
} else if ((status & AT91_SAMA5D2_IER_NOPEN)) {
/* nopen detected IRQ */
at91_adc_no_pen_detect_interrupt(indio);
} else if ((status & AT91_SAMA5D2_ISR_PENS) &&
((status & rdy_mask) == rdy_mask)) {
/* periodic trigger IRQ - during pen sense */
at91_adc_touch_data_handler(indio);
} else if (status & AT91_SAMA5D2_ISR_PENS) {
/*
* touching, but the measurements are not ready yet.
* read and ignore.
*/
status = at91_adc_readl(st, XPOSR);
status = at91_adc_readl(st, YPOSR);
status = at91_adc_readl(st, PRESSR);
} else if (iio_buffer_enabled(indio) &&
(status & AT91_SAMA5D2_IER_DRDY)) {
/* triggered buffer without DMA */
disable_irq_nosync(irq);
iio_trigger_poll(indio->trig);
} else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
/* triggered buffer with DMA - should not happen */
disable_irq_nosync(irq);
WARN(true, "Unexpected irq occurred\n");
} else if (!iio_buffer_enabled(indio)) {
/* software requested conversion */
st->conversion_value = at91_adc_read_chan(st, st->chan->address);
st->conversion_done = true;
wake_up_interruptible(&st->wq_data_available);
}
return IRQ_HANDLED;
}
/* This needs to be called with direct mode claimed and st->lock locked. */
static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val)
{
struct at91_adc_state *st = iio_priv(indio_dev);
u16 tmp_val;
int ret;
ret = pm_runtime_resume_and_get(st->dev);
if (ret < 0)
return ret;
/*
* Keep in mind that we cannot use software trigger or touchscreen
* if external trigger is enabled
*/
if (chan->type == IIO_POSITIONRELATIVE) {
ret = at91_adc_read_position(st, chan->channel,
&tmp_val);
*val = tmp_val;
if (ret > 0)
ret = at91_adc_adjust_val_osr(st, val);
goto pm_runtime_put;
}
if (chan->type == IIO_PRESSURE) {
ret = at91_adc_read_pressure(st, chan->channel,
&tmp_val);
*val = tmp_val;
if (ret > 0)
ret = at91_adc_adjust_val_osr(st, val);
goto pm_runtime_put;
}
/* in this case we have a voltage or temperature channel */
st->chan = chan;
at91_adc_cor(st, chan);
at91_adc_writel(st, CHER, BIT(chan->channel));
/*
* TEMPMR.TEMPON needs to update after CHER otherwise if none
* of the channels are enabled and TEMPMR.TEMPON = 1 will
* trigger DRDY interruption while preparing for temperature read.
*/
if (chan->type == IIO_TEMP)
at91_adc_writel(st, TEMPMR, AT91_SAMA5D2_TEMPMR_TEMPON);
at91_adc_eoc_ena(st, chan->channel);
at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);
ret = wait_event_interruptible_timeout(st->wq_data_available,
st->conversion_done,
msecs_to_jiffies(1000));
if (ret == 0)
ret = -ETIMEDOUT;
if (ret > 0) {
*val = st->conversion_value;
ret = at91_adc_adjust_val_osr(st, val);
if (chan->scan_type.sign == 's')
*val = sign_extend32(*val,
chan->scan_type.realbits - 1);
st->conversion_done = false;
}
at91_adc_eoc_dis(st, st->chan->channel);
if (chan->type == IIO_TEMP)
at91_adc_writel(st, TEMPMR, 0U);
at91_adc_writel(st, CHDR, BIT(chan->channel));
/* Needed to ACK the DRDY interruption */
at91_adc_readl(st, LCDR);
pm_runtime_put:
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_autosuspend(st->dev);
return ret;
}
static int at91_adc_read_info_locked(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val)
{
struct at91_adc_state *st = iio_priv(indio_dev);
int ret;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
mutex_lock(&st->lock);
ret = at91_adc_read_info_raw(indio_dev, chan, val);
mutex_unlock(&st->lock);
iio_device_release_direct_mode(indio_dev);
return ret;
}
static void at91_adc_temp_sensor_configure(struct at91_adc_state *st,
bool start)
{
u32 sample_rate, oversampling_ratio;
u32 startup_time, tracktim, trackx;
if (start) {
/*
* Configure the sensor for best accuracy: 10MHz frequency,
* oversampling rate of 256, tracktim=0xf and trackx=1.
*/
sample_rate = 10 * MEGA;
oversampling_ratio = 256;
startup_time = AT91_SAMA5D2_MR_STARTUP_TS_MIN;
tracktim = AT91_SAMA5D2_MR_TRACKTIM_TS;
trackx = AT91_SAMA5D2_TRACKX_TS;
st->temp_st.saved_sample_rate = st->current_sample_rate;
st->temp_st.saved_oversampling = st->oversampling_ratio;
} else {
/* Go back to previous settings. */
sample_rate = st->temp_st.saved_sample_rate;
oversampling_ratio = st->temp_st.saved_oversampling;
startup_time = st->soc_info.startup_time;
tracktim = 0;
trackx = 0;
}
at91_adc_setup_samp_freq(st->indio_dev, sample_rate, startup_time,
tracktim);
at91_adc_config_emr(st, oversampling_ratio, trackx);
}
static int at91_adc_read_temp(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val)
{
struct at91_adc_state *st = iio_priv(indio_dev);
struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb;
u64 div1, div2;
u32 tmp;
int ret, vbg, vtemp;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
mutex_lock(&st->lock);
ret = pm_runtime_resume_and_get(st->dev);
if (ret < 0)
goto unlock;
at91_adc_temp_sensor_configure(st, true);
/* Read VBG. */
tmp = at91_adc_readl(st, ACR);
tmp |= AT91_SAMA5D2_ACR_SRCLCH;
at91_adc_writel(st, ACR, tmp);
ret = at91_adc_read_info_raw(indio_dev, chan, &vbg);
if (ret < 0)
goto restore_config;
/* Read VTEMP. */
tmp &= ~AT91_SAMA5D2_ACR_SRCLCH;
at91_adc_writel(st, ACR, tmp);
ret = at91_adc_read_info_raw(indio_dev, chan, &vtemp);
restore_config:
/* Revert previous settings. */
at91_adc_temp_sensor_configure(st, false);
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_autosuspend(st->dev);
unlock:
mutex_unlock(&st->lock);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
/*
* Temp[milli] = p1[milli] + (vtemp * clb->p6 - clb->p4 * vbg)/
* (vbg * AT91_ADC_TS_VTEMP_DT)
*/
div1 = DIV_ROUND_CLOSEST_ULL(((u64)vtemp * clb->p6), vbg);
div1 = DIV_ROUND_CLOSEST_ULL((div1 * 1000), AT91_ADC_TS_VTEMP_DT);
div2 = DIV_ROUND_CLOSEST_ULL((u64)clb->p4, AT91_ADC_TS_VTEMP_DT);
div2 *= 1000;
*val = clb->p1 + (int)div1 - (int)div2;
return ret;
}
static int at91_adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct at91_adc_state *st = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
return at91_adc_read_info_locked(indio_dev, chan, val);
case IIO_CHAN_INFO_SCALE:
*val = st->vref_uv / 1000;
if (chan->differential)
*val *= 2;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_PROCESSED:
if (chan->type != IIO_TEMP)
return -EINVAL;
return at91_adc_read_temp(indio_dev, chan, val);
case IIO_CHAN_INFO_SAMP_FREQ:
*val = at91_adc_get_sample_freq(st);
return IIO_VAL_INT;
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
*val = st->oversampling_ratio;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int at91_adc_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct at91_adc_state *st = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
/* if no change, optimize out */
if (val == st->oversampling_ratio)
return 0;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
mutex_lock(&st->lock);
/* update ratio */
ret = at91_adc_config_emr(st, val, 0);
mutex_unlock(&st->lock);
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_SAMP_FREQ:
if (val < st->soc_info.min_sample_rate ||
val > st->soc_info.max_sample_rate)
return -EINVAL;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
mutex_lock(&st->lock);
at91_adc_setup_samp_freq(indio_dev, val,
st->soc_info.startup_time, 0);
mutex_unlock(&st->lock);
iio_device_release_direct_mode(indio_dev);
return 0;
default:
return -EINVAL;
}
}
static int at91_adc_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
struct at91_adc_state *st = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
*vals = (int *)st->soc_info.platform->oversampling_avail;
*type = IIO_VAL_INT;
*length = st->soc_info.platform->oversampling_avail_no;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static void at91_adc_dma_init(struct at91_adc_state *st)
{
struct device *dev = &st->indio_dev->dev;
struct dma_slave_config config = {0};
/* we have 2 bytes for each channel */
unsigned int sample_size = st->soc_info.platform->nr_channels * 2;
/*
* We make the buffer double the size of the fifo,
* such that DMA uses one half of the buffer (full fifo size)
* and the software uses the other half to read/write.
*/
unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
sample_size * 2, PAGE_SIZE);
if (st->dma_st.dma_chan)
return;
st->dma_st.dma_chan = dma_request_chan(dev, "rx");
if (IS_ERR(st->dma_st.dma_chan)) {
dev_info(dev, "can't get DMA channel\n");
st->dma_st.dma_chan = NULL;
goto dma_exit;
}
st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
pages * PAGE_SIZE,
&st->dma_st.rx_dma_buf,
GFP_KERNEL);
if (!st->dma_st.rx_buf) {
dev_info(dev, "can't allocate coherent DMA area\n");
goto dma_chan_disable;
}
/* Configure DMA channel to read data register */
config.direction = DMA_DEV_TO_MEM;
config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
+ st->soc_info.platform->layout->LCDR);
config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
config.src_maxburst = 1;
config.dst_maxburst = 1;
if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
dev_info(dev, "can't configure DMA slave\n");
goto dma_free_area;
}
dev_info(dev, "using %s for rx DMA transfers\n",
dma_chan_name(st->dma_st.dma_chan));
return;
dma_free_area:
dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
dma_chan_disable:
dma_release_channel(st->dma_st.dma_chan);
st->dma_st.dma_chan = NULL;
dma_exit:
dev_info(dev, "continuing without DMA support\n");
}
static void at91_adc_dma_disable(struct at91_adc_state *st)
{
struct device *dev = &st->indio_dev->dev;
/* we have 2 bytes for each channel */
unsigned int sample_size = st->soc_info.platform->nr_channels * 2;
unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
sample_size * 2, PAGE_SIZE);
/* if we are not using DMA, just return */
if (!st->dma_st.dma_chan)
return;
/* wait for all transactions to be terminated first*/
dmaengine_terminate_sync(st->dma_st.dma_chan);
dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
dma_release_channel(st->dma_st.dma_chan);
st->dma_st.dma_chan = NULL;
dev_info(dev, "continuing without DMA support\n");
}
static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
{
struct at91_adc_state *st = iio_priv(indio_dev);
int ret;
if (val > AT91_HWFIFO_MAX_SIZE)
val = AT91_HWFIFO_MAX_SIZE;
if (!st->selected_trig->hw_trig) {
dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n");
return 0;
}
dev_dbg(&indio_dev->dev, "new watermark is %u\n", val);
st->dma_st.watermark = val;
/*
* The logic here is: if we have watermark 1, it means we do
* each conversion with it's own IRQ, thus we don't need DMA.
* If the watermark is higher, we do DMA to do all the transfers in bulk
*/
if (val == 1)
at91_adc_dma_disable(st);
else if (val > 1)
at91_adc_dma_init(st);
/*
* We can start the DMA only after setting the watermark and
* having the DMA initialization completed
*/
ret = at91_adc_buffer_prepare(indio_dev);
if (ret)
at91_adc_dma_disable(st);
return ret;
}
static int at91_adc_update_scan_mode(struct iio_dev *indio_dev,
const unsigned long *scan_mask)
{
struct at91_adc_state *st = iio_priv(indio_dev);
if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask,
st->soc_info.platform->max_index + 1))
return 0;
/*
* if the new bitmap is a combination of touchscreen and regular
* channels, then we are not fine
*/
if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask,
st->soc_info.platform->max_index + 1))
return -EINVAL;
return 0;
}
static void at91_adc_hw_init(struct iio_dev *indio_dev)
{
struct at91_adc_state *st = iio_priv(indio_dev);
at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);
if (st->soc_info.platform->layout->EOC_IDR)
at91_adc_writel(st, EOC_IDR, 0xffffffff);
at91_adc_writel(st, IDR, 0xffffffff);
/*
* Transfer field must be set to 2 according to the datasheet and
* allows different analog settings for each channel.
*/
at91_adc_writel(st, MR,
AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate,
st->soc_info.startup_time, 0);
/* configure extended mode register */
at91_adc_config_emr(st, st->oversampling_ratio, 0);
}
static ssize_t at91_adc_get_fifo_state(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct at91_adc_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", !!st->dma_st.dma_chan);
}
static ssize_t at91_adc_get_watermark(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct at91_adc_state *st = iio_priv(indio_dev);
return sysfs_emit(buf, "%d\n", st->dma_st.watermark);
}
static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
at91_adc_get_fifo_state, NULL, 0);
static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
at91_adc_get_watermark, NULL, 0);
IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "2");
IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
static const struct iio_dev_attr *at91_adc_fifo_attributes[] = {
&iio_dev_attr_hwfifo_watermark_min,
&iio_dev_attr_hwfifo_watermark_max,
&iio_dev_attr_hwfifo_watermark,
&iio_dev_attr_hwfifo_enabled,
NULL,
};
static const struct iio_info at91_adc_info = {
.read_avail = &at91_adc_read_avail,
.read_raw = &at91_adc_read_raw,
.write_raw = &at91_adc_write_raw,
.update_scan_mode = &at91_adc_update_scan_mode,
.fwnode_xlate = &at91_adc_fwnode_xlate,
.hwfifo_set_watermark = &at91_adc_set_watermark,
};
static int at91_adc_buffer_and_trigger_init(struct device *dev,
struct iio_dev *indio)
{
struct at91_adc_state *st = iio_priv(indio);
const struct iio_dev_attr **fifo_attrs;
int ret;
if (st->selected_trig->hw_trig)
fifo_attrs = at91_adc_fifo_attributes;
else
fifo_attrs = NULL;
ret = devm_iio_triggered_buffer_setup_ext(&indio->dev, indio,
&iio_pollfunc_store_time, &at91_adc_trigger_handler,
IIO_BUFFER_DIRECTION_IN, &at91_buffer_setup_ops, fifo_attrs);
if (ret < 0) {
dev_err(dev, "couldn't initialize the buffer.\n");
return ret;
}
if (!st->selected_trig->hw_trig)
return 0;
st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
if (IS_ERR(st->trig)) {
dev_err(dev, "could not allocate trigger\n");
return PTR_ERR(st->trig);
}
/*
* Initially the iio buffer has a length of 2 and
* a watermark of 1
*/
st->dma_st.watermark = 1;
return 0;
}
static int at91_adc_temp_sensor_init(struct at91_adc_state *st,
struct device *dev)
{
struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb;
struct nvmem_cell *temp_calib;
u32 *buf;
size_t len;
int ret = 0;
if (!st->soc_info.platform->temp_sensor)
return 0;
/* Get the calibration data from NVMEM. */
temp_calib = devm_nvmem_cell_get(dev, "temperature_calib");
if (IS_ERR(temp_calib)) {
ret = PTR_ERR(temp_calib);
if (ret != -ENOENT)
dev_err(dev, "Failed to get temperature_calib cell!\n");
return ret;
}
buf = nvmem_cell_read(temp_calib, &len);
if (IS_ERR(buf)) {
dev_err(dev, "Failed to read calibration data!\n");
return PTR_ERR(buf);
}
if (len < AT91_ADC_TS_CLB_IDX_MAX * 4) {
dev_err(dev, "Invalid calibration data!\n");
ret = -EINVAL;
goto free_buf;
}
/* Store calibration data for later use. */
clb->p1 = buf[AT91_ADC_TS_CLB_IDX_P1];
clb->p4 = buf[AT91_ADC_TS_CLB_IDX_P4];
clb->p6 = buf[AT91_ADC_TS_CLB_IDX_P6];
/*
* We prepare here the conversion to milli to avoid doing it on hotpath.
*/
clb->p1 = clb->p1 * 1000;
free_buf:
kfree(buf);
return ret;
}
static int at91_adc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct iio_dev *indio_dev;
struct at91_adc_state *st;
struct resource *res;
int ret, i, num_channels;
u32 edge_type = IRQ_TYPE_NONE;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->indio_dev = indio_dev;
st->soc_info.platform = device_get_match_data(dev);
ret = at91_adc_temp_sensor_init(st, &pdev->dev);
/* Don't register temperature channel if initialization failed. */
if (ret)
num_channels = st->soc_info.platform->max_channels - 1;
else
num_channels = st->soc_info.platform->max_channels;
indio_dev->name = dev_name(&pdev->dev);
indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
indio_dev->info = &at91_adc_info;
indio_dev->channels = *st->soc_info.platform->adc_channels;
indio_dev->num_channels = num_channels;
bitmap_set(&st->touch_st.channels_bitmask,
st->soc_info.platform->touch_chan_x, 1);
bitmap_set(&st->touch_st.channels_bitmask,
st->soc_info.platform->touch_chan_y, 1);
bitmap_set(&st->touch_st.channels_bitmask,
st->soc_info.platform->touch_chan_p, 1);
st->oversampling_ratio = 1;
ret = device_property_read_u32(dev, "atmel,min-sample-rate-hz",
&st->soc_info.min_sample_rate);
if (ret) {
dev_err(&pdev->dev,
"invalid or missing value for atmel,min-sample-rate-hz\n");
return ret;
}
ret = device_property_read_u32(dev, "atmel,max-sample-rate-hz",
&st->soc_info.max_sample_rate);
if (ret) {
dev_err(&pdev->dev,
"invalid or missing value for atmel,max-sample-rate-hz\n");
return ret;
}
ret = device_property_read_u32(dev, "atmel,startup-time-ms",
&st->soc_info.startup_time);
if (ret) {
dev_err(&pdev->dev,
"invalid or missing value for atmel,startup-time-ms\n");
return ret;
}
ret = device_property_read_u32(dev, "atmel,trigger-edge-type",
&edge_type);
if (ret) {
dev_dbg(&pdev->dev,
"atmel,trigger-edge-type not specified, only software trigger available\n");
}
st->selected_trig = NULL;
/* find the right trigger, or no trigger at all */
for (i = 0; i < st->soc_info.platform->hw_trig_cnt + 1; i++)
if (at91_adc_trigger_list[i].edge_type == edge_type) {
st->selected_trig = &at91_adc_trigger_list[i];
break;
}
if (!st->selected_trig) {
dev_err(&pdev->dev, "invalid external trigger edge value\n");
return -EINVAL;
}
init_waitqueue_head(&st->wq_data_available);
mutex_init(&st->lock);
INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler);
st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(st->base))
return PTR_ERR(st->base);
/* if we plan to use DMA, we need the physical address of the regs */
st->dma_st.phys_addr = res->start;
st->irq = platform_get_irq(pdev, 0);
if (st->irq < 0)
return st->irq;
st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
if (IS_ERR(st->per_clk))
return PTR_ERR(st->per_clk);
st->reg = devm_regulator_get(&pdev->dev, "vddana");
if (IS_ERR(st->reg))
return PTR_ERR(st->reg);
st->vref = devm_regulator_get(&pdev->dev, "vref");
if (IS_ERR(st->vref))
return PTR_ERR(st->vref);
ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
pdev->dev.driver->name, indio_dev);
if (ret)
return ret;
ret = regulator_enable(st->reg);
if (ret)
return ret;
ret = regulator_enable(st->vref);
if (ret)
goto reg_disable;
st->vref_uv = regulator_get_voltage(st->vref);
if (st->vref_uv <= 0) {
ret = -EINVAL;
goto vref_disable;
}
ret = clk_prepare_enable(st->per_clk);
if (ret)
goto vref_disable;
platform_set_drvdata(pdev, indio_dev);
st->dev = &pdev->dev;
pm_runtime_set_autosuspend_delay(st->dev, 500);
pm_runtime_use_autosuspend(st->dev);
pm_runtime_set_active(st->dev);
pm_runtime_enable(st->dev);
pm_runtime_get_noresume(st->dev);
at91_adc_hw_init(indio_dev);
ret = at91_adc_buffer_and_trigger_init(&pdev->dev, indio_dev);
if (ret < 0)
goto err_pm_disable;
if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32)))
dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n");
ret = iio_device_register(indio_dev);
if (ret < 0)
goto dma_disable;
if (st->selected_trig->hw_trig)
dev_info(&pdev->dev, "setting up trigger as %s\n",
st->selected_trig->name);
dev_info(&pdev->dev, "version: %x\n",
readl_relaxed(st->base + st->soc_info.platform->layout->VERSION));
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_autosuspend(st->dev);
return 0;
dma_disable:
at91_adc_dma_disable(st);
err_pm_disable:
pm_runtime_put_noidle(st->dev);
pm_runtime_disable(st->dev);
pm_runtime_set_suspended(st->dev);
pm_runtime_dont_use_autosuspend(st->dev);
clk_disable_unprepare(st->per_clk);
vref_disable:
regulator_disable(st->vref);
reg_disable:
regulator_disable(st->reg);
return ret;
}
static int at91_adc_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct at91_adc_state *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
at91_adc_dma_disable(st);
pm_runtime_disable(st->dev);
pm_runtime_set_suspended(st->dev);
clk_disable_unprepare(st->per_clk);
regulator_disable(st->vref);
regulator_disable(st->reg);
return 0;
}
static int at91_adc_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct at91_adc_state *st = iio_priv(indio_dev);
int ret;
ret = pm_runtime_resume_and_get(st->dev);
if (ret < 0)
return ret;
if (iio_buffer_enabled(indio_dev))
at91_adc_buffer_postdisable(indio_dev);
/*
* Do a sofware reset of the ADC before we go to suspend.
* this will ensure that all pins are free from being muxed by the ADC
* and can be used by for other devices.
* Otherwise, ADC will hog them and we can't go to suspend mode.
*/
at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_noidle(st->dev);
clk_disable_unprepare(st->per_clk);
regulator_disable(st->vref);
regulator_disable(st->reg);
return pinctrl_pm_select_sleep_state(dev);
}
static int at91_adc_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct at91_adc_state *st = iio_priv(indio_dev);
int ret;
ret = pinctrl_pm_select_default_state(dev);
if (ret)
goto resume_failed;
ret = regulator_enable(st->reg);
if (ret)
goto resume_failed;
ret = regulator_enable(st->vref);
if (ret)
goto reg_disable_resume;
ret = clk_prepare_enable(st->per_clk);
if (ret)
goto vref_disable_resume;
pm_runtime_get_noresume(st->dev);
at91_adc_hw_init(indio_dev);
/* reconfiguring trigger hardware state */
if (iio_buffer_enabled(indio_dev)) {
ret = at91_adc_buffer_prepare(indio_dev);
if (ret)
goto pm_runtime_put;
at91_adc_configure_trigger_registers(st, true);
}
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_autosuspend(st->dev);
return 0;
pm_runtime_put:
pm_runtime_mark_last_busy(st->dev);
pm_runtime_put_noidle(st->dev);
clk_disable_unprepare(st->per_clk);
vref_disable_resume:
regulator_disable(st->vref);
reg_disable_resume:
regulator_disable(st->reg);
resume_failed:
dev_err(&indio_dev->dev, "failed to resume\n");
return ret;
}
static int at91_adc_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct at91_adc_state *st = iio_priv(indio_dev);
clk_disable(st->per_clk);
return 0;
}
static int at91_adc_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct at91_adc_state *st = iio_priv(indio_dev);
return clk_enable(st->per_clk);
}
static const struct dev_pm_ops at91_adc_pm_ops = {
SYSTEM_SLEEP_PM_OPS(at91_adc_suspend, at91_adc_resume)
RUNTIME_PM_OPS(at91_adc_runtime_suspend, at91_adc_runtime_resume,
NULL)
};
static const struct of_device_id at91_adc_dt_match[] = {
{
.compatible = "atmel,sama5d2-adc",
.data = (const void *)&sama5d2_platform,
}, {
.compatible = "microchip,sama7g5-adc",
.data = (const void *)&sama7g5_platform,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
static struct platform_driver at91_adc_driver = {
.probe = at91_adc_probe,
.remove = at91_adc_remove,
.driver = {
.name = "at91-sama5d2_adc",
.of_match_table = at91_adc_dt_match,
.pm = pm_ptr(&at91_adc_pm_ops),
},
};
module_platform_driver(at91_adc_driver)
MODULE_AUTHOR("Ludovic Desroches <[email protected]>");
MODULE_AUTHOR("Eugen Hristev <[email protected]");
MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/at91-sama5d2_adc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Xilinx XADC driver
*
* Copyright 2013 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/kernel.h>
#include "xilinx-xadc.h"
static const struct iio_chan_spec *xadc_event_to_channel(
struct iio_dev *indio_dev, unsigned int event)
{
switch (event) {
case XADC_THRESHOLD_OT_MAX:
case XADC_THRESHOLD_TEMP_MAX:
return &indio_dev->channels[0];
case XADC_THRESHOLD_VCCINT_MAX:
case XADC_THRESHOLD_VCCAUX_MAX:
return &indio_dev->channels[event];
default:
return &indio_dev->channels[event-1];
}
}
static void xadc_handle_event(struct iio_dev *indio_dev, unsigned int event)
{
const struct iio_chan_spec *chan;
/* Temperature threshold error, we don't handle this yet */
if (event == 0)
return;
chan = xadc_event_to_channel(indio_dev, event);
if (chan->type == IIO_TEMP) {
/*
* The temperature channel only supports over-temperature
* events.
*/
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
} else {
/*
* For other channels we don't know whether it is a upper or
* lower threshold event. Userspace will have to check the
* channel value if it wants to know.
*/
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER),
iio_get_time_ns(indio_dev));
}
}
void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events)
{
unsigned int i;
for_each_set_bit(i, &events, 8)
xadc_handle_event(indio_dev, i);
}
static unsigned int xadc_get_threshold_offset(const struct iio_chan_spec *chan,
enum iio_event_direction dir)
{
unsigned int offset;
if (chan->type == IIO_TEMP) {
offset = XADC_THRESHOLD_OT_MAX;
} else {
if (chan->channel < 2)
offset = chan->channel + 1;
else
offset = chan->channel + 6;
}
if (dir == IIO_EV_DIR_FALLING)
offset += 4;
return offset;
}
static unsigned int xadc_get_alarm_mask(const struct iio_chan_spec *chan)
{
if (chan->type == IIO_TEMP)
return XADC_ALARM_OT_MASK;
switch (chan->channel) {
case 0:
return XADC_ALARM_VCCINT_MASK;
case 1:
return XADC_ALARM_VCCAUX_MASK;
case 2:
return XADC_ALARM_VCCBRAM_MASK;
case 3:
return XADC_ALARM_VCCPINT_MASK;
case 4:
return XADC_ALARM_VCCPAUX_MASK;
case 5:
return XADC_ALARM_VCCODDR_MASK;
default:
/* We will never get here */
return 0;
}
}
int xadc_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir)
{
struct xadc *xadc = iio_priv(indio_dev);
return (bool)(xadc->alarm_mask & xadc_get_alarm_mask(chan));
}
int xadc_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, int state)
{
unsigned int alarm = xadc_get_alarm_mask(chan);
struct xadc *xadc = iio_priv(indio_dev);
uint16_t cfg, old_cfg;
int ret;
mutex_lock(&xadc->mutex);
if (state)
xadc->alarm_mask |= alarm;
else
xadc->alarm_mask &= ~alarm;
xadc->ops->update_alarm(xadc, xadc->alarm_mask);
ret = _xadc_read_adc_reg(xadc, XADC_REG_CONF1, &cfg);
if (ret)
goto err_out;
old_cfg = cfg;
cfg |= XADC_CONF1_ALARM_MASK;
cfg &= ~((xadc->alarm_mask & 0xf0) << 4); /* bram, pint, paux, ddr */
cfg &= ~((xadc->alarm_mask & 0x08) >> 3); /* ot */
cfg &= ~((xadc->alarm_mask & 0x07) << 1); /* temp, vccint, vccaux */
if (old_cfg != cfg)
ret = _xadc_write_adc_reg(xadc, XADC_REG_CONF1, cfg);
err_out:
mutex_unlock(&xadc->mutex);
return ret;
}
int xadc_read_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info,
int *val, int *val2)
{
unsigned int offset = xadc_get_threshold_offset(chan, dir);
struct xadc *xadc = iio_priv(indio_dev);
switch (info) {
case IIO_EV_INFO_VALUE:
*val = xadc->threshold[offset];
break;
case IIO_EV_INFO_HYSTERESIS:
*val = xadc->temp_hysteresis;
break;
default:
return -EINVAL;
}
/* MSB aligned */
*val >>= 16 - chan->scan_type.realbits;
return IIO_VAL_INT;
}
int xadc_write_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info,
int val, int val2)
{
unsigned int offset = xadc_get_threshold_offset(chan, dir);
struct xadc *xadc = iio_priv(indio_dev);
int ret = 0;
/* MSB aligned */
val <<= 16 - chan->scan_type.realbits;
if (val < 0 || val > 0xffff)
return -EINVAL;
mutex_lock(&xadc->mutex);
switch (info) {
case IIO_EV_INFO_VALUE:
xadc->threshold[offset] = val;
break;
case IIO_EV_INFO_HYSTERESIS:
xadc->temp_hysteresis = val;
break;
default:
mutex_unlock(&xadc->mutex);
return -EINVAL;
}
if (chan->type == IIO_TEMP) {
/*
* According to the datasheet we need to set the lower 4 bits to
* 0x3, otherwise 125 degree celsius will be used as the
* threshold.
*/
val |= 0x3;
/*
* Since we store the hysteresis as relative (to the threshold)
* value, but the hardware expects an absolute value we need to
* recalcualte this value whenever the hysteresis or the
* threshold changes.
*/
if (xadc->threshold[offset] < xadc->temp_hysteresis)
xadc->threshold[offset + 4] = 0;
else
xadc->threshold[offset + 4] = xadc->threshold[offset] -
xadc->temp_hysteresis;
ret = _xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(offset + 4),
xadc->threshold[offset + 4]);
if (ret)
goto out_unlock;
}
if (info == IIO_EV_INFO_VALUE)
ret = _xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(offset), val);
out_unlock:
mutex_unlock(&xadc->mutex);
return ret;
}
| linux-master | drivers/iio/adc/xilinx-xadc-events.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD7298 SPI ADC driver
*
* Copyright 2011 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#define AD7298_WRITE BIT(15) /* write to the control register */
#define AD7298_REPEAT BIT(14) /* repeated conversion enable */
#define AD7298_CH(x) BIT(13 - (x)) /* channel select */
#define AD7298_TSENSE BIT(5) /* temperature conversion enable */
#define AD7298_EXTREF BIT(2) /* external reference enable */
#define AD7298_TAVG BIT(1) /* temperature sensor averaging enable */
#define AD7298_PDD BIT(0) /* partial power down enable */
#define AD7298_MAX_CHAN 8
#define AD7298_INTREF_mV 2500
#define AD7298_CH_TEMP 9
struct ad7298_state {
struct spi_device *spi;
struct regulator *reg;
unsigned ext_ref;
struct spi_transfer ring_xfer[10];
struct spi_transfer scan_single_xfer[3];
struct spi_message ring_msg;
struct spi_message scan_single_msg;
/*
* DMA (thus cache coherency maintenance) requires the
* transfer buffers to live in their own cache lines.
*/
__be16 rx_buf[12] __aligned(IIO_DMA_MINALIGN);
__be16 tx_buf[2];
};
#define AD7298_V_CHAN(index) \
{ \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = index, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.address = index, \
.scan_index = index, \
.scan_type = { \
.sign = 'u', \
.realbits = 12, \
.storagebits = 16, \
.endianness = IIO_BE, \
}, \
}
static const struct iio_chan_spec ad7298_channels[] = {
{
.type = IIO_TEMP,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET),
.address = AD7298_CH_TEMP,
.scan_index = -1,
.scan_type = {
.sign = 's',
.realbits = 32,
.storagebits = 32,
},
},
AD7298_V_CHAN(0),
AD7298_V_CHAN(1),
AD7298_V_CHAN(2),
AD7298_V_CHAN(3),
AD7298_V_CHAN(4),
AD7298_V_CHAN(5),
AD7298_V_CHAN(6),
AD7298_V_CHAN(7),
IIO_CHAN_SOFT_TIMESTAMP(8),
};
/*
* ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask
*/
static int ad7298_update_scan_mode(struct iio_dev *indio_dev,
const unsigned long *active_scan_mask)
{
struct ad7298_state *st = iio_priv(indio_dev);
int i, m;
unsigned short command;
int scan_count;
/* Now compute overall size */
scan_count = bitmap_weight(active_scan_mask, indio_dev->masklength);
command = AD7298_WRITE | st->ext_ref;
for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1)
if (test_bit(i, active_scan_mask))
command |= m;
st->tx_buf[0] = cpu_to_be16(command);
/* build spi ring message */
st->ring_xfer[0].tx_buf = &st->tx_buf[0];
st->ring_xfer[0].len = 2;
st->ring_xfer[0].cs_change = 1;
st->ring_xfer[1].tx_buf = &st->tx_buf[1];
st->ring_xfer[1].len = 2;
st->ring_xfer[1].cs_change = 1;
spi_message_init(&st->ring_msg);
spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);
for (i = 0; i < scan_count; i++) {
st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i];
st->ring_xfer[i + 2].len = 2;
st->ring_xfer[i + 2].cs_change = 1;
spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg);
}
/* make sure last transfer cs_change is not set */
st->ring_xfer[i + 1].cs_change = 0;
return 0;
}
static irqreturn_t ad7298_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct ad7298_state *st = iio_priv(indio_dev);
int b_sent;
b_sent = spi_sync(st->spi, &st->ring_msg);
if (b_sent)
goto done;
iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
iio_get_time_ns(indio_dev));
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
{
int ret;
st->tx_buf[0] = cpu_to_be16(AD7298_WRITE | st->ext_ref |
(AD7298_CH(0) >> ch));
ret = spi_sync(st->spi, &st->scan_single_msg);
if (ret)
return ret;
return be16_to_cpu(st->rx_buf[0]);
}
static int ad7298_scan_temp(struct ad7298_state *st, int *val)
{
int ret;
__be16 buf;
buf = cpu_to_be16(AD7298_WRITE | AD7298_TSENSE |
AD7298_TAVG | st->ext_ref);
ret = spi_write(st->spi, (u8 *)&buf, 2);
if (ret)
return ret;
buf = cpu_to_be16(0);
ret = spi_write(st->spi, (u8 *)&buf, 2);
if (ret)
return ret;
usleep_range(101, 1000); /* sleep > 100us */
ret = spi_read(st->spi, (u8 *)&buf, 2);
if (ret)
return ret;
*val = sign_extend32(be16_to_cpu(buf), 11);
return 0;
}
static int ad7298_get_ref_voltage(struct ad7298_state *st)
{
int vref;
if (st->reg) {
vref = regulator_get_voltage(st->reg);
if (vref < 0)
return vref;
return vref / 1000;
} else {
return AD7298_INTREF_mV;
}
}
static int ad7298_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
int ret;
struct ad7298_state *st = iio_priv(indio_dev);
switch (m) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
if (chan->address == AD7298_CH_TEMP)
ret = ad7298_scan_temp(st, val);
else
ret = ad7298_scan_direct(st, chan->address);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
if (chan->address != AD7298_CH_TEMP)
*val = ret & GENMASK(chan->scan_type.realbits - 1, 0);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_VOLTAGE:
*val = ad7298_get_ref_voltage(st);
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_TEMP:
*val = ad7298_get_ref_voltage(st);
*val2 = 10;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_OFFSET:
*val = 1093 - 2732500 / ad7298_get_ref_voltage(st);
return IIO_VAL_INT;
}
return -EINVAL;
}
static const struct iio_info ad7298_info = {
.read_raw = &ad7298_read_raw,
.update_scan_mode = ad7298_update_scan_mode,
};
static void ad7298_reg_disable(void *data)
{
struct regulator *reg = data;
regulator_disable(reg);
}
static int ad7298_probe(struct spi_device *spi)
{
struct ad7298_state *st;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (indio_dev == NULL)
return -ENOMEM;
st = iio_priv(indio_dev);
st->reg = devm_regulator_get_optional(&spi->dev, "vref");
if (!IS_ERR(st->reg)) {
st->ext_ref = AD7298_EXTREF;
} else {
ret = PTR_ERR(st->reg);
if (ret != -ENODEV)
return ret;
st->reg = NULL;
}
if (st->reg) {
ret = regulator_enable(st->reg);
if (ret)
return ret;
ret = devm_add_action_or_reset(&spi->dev, ad7298_reg_disable,
st->reg);
if (ret)
return ret;
}
st->spi = spi;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ad7298_channels;
indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
indio_dev->info = &ad7298_info;
/* Setup default message */
st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
st->scan_single_xfer[0].len = 2;
st->scan_single_xfer[0].cs_change = 1;
st->scan_single_xfer[1].tx_buf = &st->tx_buf[1];
st->scan_single_xfer[1].len = 2;
st->scan_single_xfer[1].cs_change = 1;
st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
st->scan_single_xfer[2].len = 2;
spi_message_init(&st->scan_single_msg);
spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg);
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
&ad7298_trigger_handler, NULL);
if (ret)
return ret;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct acpi_device_id ad7298_acpi_ids[] = {
{ "INT3494", 0 },
{ }
};
MODULE_DEVICE_TABLE(acpi, ad7298_acpi_ids);
static const struct spi_device_id ad7298_id[] = {
{"ad7298", 0},
{}
};
MODULE_DEVICE_TABLE(spi, ad7298_id);
static struct spi_driver ad7298_driver = {
.driver = {
.name = "ad7298",
.acpi_match_table = ad7298_acpi_ids,
},
.probe = ad7298_probe,
.id_table = ad7298_id,
};
module_spi_driver(ad7298_driver);
MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD7298 ADC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ad7298.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for ADC module on the Cirrus Logic EP93xx series of SoCs
*
* Copyright (C) 2015 Alexander Sverdlin
*
* The driver uses polling to get the conversion status. According to EP93xx
* datasheets, reading ADCResult register starts the conversion, but user is also
* responsible for ensuring that delay between adjacent conversion triggers is
* long enough so that maximum allowed conversion rate is not exceeded. This
* basically renders IRQ mode unusable.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/iio/iio.h>
#include <linux/io.h>
#include <linux/irqflags.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/of.h>
/*
* This code could benefit from real HR Timers, but jiffy granularity would
* lower ADC conversion rate down to CONFIG_HZ, so we fallback to busy wait
* in such case.
*
* HR Timers-based version loads CPU only up to 10% during back to back ADC
* conversion, while busy wait-based version consumes whole CPU power.
*/
#ifdef CONFIG_HIGH_RES_TIMERS
#define ep93xx_adc_delay(usmin, usmax) usleep_range(usmin, usmax)
#else
#define ep93xx_adc_delay(usmin, usmax) udelay(usmin)
#endif
#define EP93XX_ADC_RESULT 0x08
#define EP93XX_ADC_SDR BIT(31)
#define EP93XX_ADC_SWITCH 0x18
#define EP93XX_ADC_SW_LOCK 0x20
struct ep93xx_adc_priv {
struct clk *clk;
void __iomem *base;
int lastch;
struct mutex lock;
};
#define EP93XX_ADC_CH(index, dname, swcfg) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = index, \
.address = swcfg, \
.datasheet_name = dname, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET), \
}
/*
* Numbering scheme for channels 0..4 is defined in EP9301 and EP9302 datasheets.
* EP9307, EP9312 and EP9312 have 3 channels more (total 8), but the numbering is
* not defined. So the last three are numbered randomly, let's say.
*/
static const struct iio_chan_spec ep93xx_adc_channels[8] = {
EP93XX_ADC_CH(0, "YM", 0x608),
EP93XX_ADC_CH(1, "SXP", 0x680),
EP93XX_ADC_CH(2, "SXM", 0x640),
EP93XX_ADC_CH(3, "SYP", 0x620),
EP93XX_ADC_CH(4, "SYM", 0x610),
EP93XX_ADC_CH(5, "XP", 0x601),
EP93XX_ADC_CH(6, "XM", 0x602),
EP93XX_ADC_CH(7, "YP", 0x604),
};
static int ep93xx_read_raw(struct iio_dev *iiodev,
struct iio_chan_spec const *channel, int *value,
int *shift, long mask)
{
struct ep93xx_adc_priv *priv = iio_priv(iiodev);
unsigned long timeout;
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&priv->lock);
if (priv->lastch != channel->channel) {
priv->lastch = channel->channel;
/*
* Switch register is software-locked, unlocking must be
* immediately followed by write
*/
local_irq_disable();
writel_relaxed(0xAA, priv->base + EP93XX_ADC_SW_LOCK);
writel_relaxed(channel->address,
priv->base + EP93XX_ADC_SWITCH);
local_irq_enable();
/*
* Settling delay depends on module clock and could be
* 2ms or 500us
*/
ep93xx_adc_delay(2000, 2000);
}
/* Start the conversion, eventually discarding old result */
readl_relaxed(priv->base + EP93XX_ADC_RESULT);
/* Ensure maximum conversion rate is not exceeded */
ep93xx_adc_delay(DIV_ROUND_UP(1000000, 925),
DIV_ROUND_UP(1000000, 925));
/* At this point conversion must be completed, but anyway... */
ret = IIO_VAL_INT;
timeout = jiffies + msecs_to_jiffies(1) + 1;
while (1) {
u32 t;
t = readl_relaxed(priv->base + EP93XX_ADC_RESULT);
if (t & EP93XX_ADC_SDR) {
*value = sign_extend32(t, 15);
break;
}
if (time_after(jiffies, timeout)) {
dev_err(&iiodev->dev, "Conversion timeout\n");
ret = -ETIMEDOUT;
break;
}
cpu_relax();
}
mutex_unlock(&priv->lock);
return ret;
case IIO_CHAN_INFO_OFFSET:
/* According to datasheet, range is -25000..25000 */
*value = 25000;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/* Typical supply voltage is 3.3v */
*value = (1ULL << 32) * 3300 / 50000;
*shift = 32;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
static const struct iio_info ep93xx_adc_info = {
.read_raw = ep93xx_read_raw,
};
static int ep93xx_adc_probe(struct platform_device *pdev)
{
int ret;
struct iio_dev *iiodev;
struct ep93xx_adc_priv *priv;
struct clk *pclk;
iiodev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
if (!iiodev)
return -ENOMEM;
priv = iio_priv(iiodev);
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
iiodev->name = dev_name(&pdev->dev);
iiodev->modes = INDIO_DIRECT_MODE;
iiodev->info = &ep93xx_adc_info;
iiodev->num_channels = ARRAY_SIZE(ep93xx_adc_channels);
iiodev->channels = ep93xx_adc_channels;
priv->lastch = -1;
mutex_init(&priv->lock);
platform_set_drvdata(pdev, iiodev);
priv->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(priv->clk)) {
dev_err(&pdev->dev, "Cannot obtain clock\n");
return PTR_ERR(priv->clk);
}
pclk = clk_get_parent(priv->clk);
if (!pclk) {
dev_warn(&pdev->dev, "Cannot obtain parent clock\n");
} else {
/*
* This is actually a place for improvement:
* EP93xx ADC supports two clock divisors -- 4 and 16,
* resulting in conversion rates 3750 and 925 samples per second
* with 500us or 2ms settling time respectively.
* One might find this interesting enough to be configurable.
*/
ret = clk_set_rate(priv->clk, clk_get_rate(pclk) / 16);
if (ret)
dev_warn(&pdev->dev, "Cannot set clock rate\n");
/*
* We can tolerate rate setting failure because the module should
* work in any case.
*/
}
ret = clk_prepare_enable(priv->clk);
if (ret) {
dev_err(&pdev->dev, "Cannot enable clock\n");
return ret;
}
ret = iio_device_register(iiodev);
if (ret)
clk_disable_unprepare(priv->clk);
return ret;
}
static int ep93xx_adc_remove(struct platform_device *pdev)
{
struct iio_dev *iiodev = platform_get_drvdata(pdev);
struct ep93xx_adc_priv *priv = iio_priv(iiodev);
iio_device_unregister(iiodev);
clk_disable_unprepare(priv->clk);
return 0;
}
static const struct of_device_id ep93xx_adc_of_ids[] = {
{ .compatible = "cirrus,ep9301-adc" },
{}
};
MODULE_DEVICE_TABLE(of, ep93xx_adc_of_ids);
static struct platform_driver ep93xx_adc_driver = {
.driver = {
.name = "ep93xx-adc",
.of_match_table = ep93xx_adc_of_ids,
},
.probe = ep93xx_adc_probe,
.remove = ep93xx_adc_remove,
};
module_platform_driver(ep93xx_adc_driver);
MODULE_AUTHOR("Alexander Sverdlin <[email protected]>");
MODULE_DESCRIPTION("Cirrus Logic EP93XX ADC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ep93xx-adc");
| linux-master | drivers/iio/adc/ep93xx_adc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices AD7292 SPI ADC driver
*
* Copyright 2019 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#define ADI_VENDOR_ID 0x0018
/* AD7292 registers definition */
#define AD7292_REG_VENDOR_ID 0x00
#define AD7292_REG_CONF_BANK 0x05
#define AD7292_REG_CONV_COMM 0x0E
#define AD7292_REG_ADC_CH(x) (0x10 + (x))
/* AD7292 configuration bank subregisters definition */
#define AD7292_BANK_REG_VIN_RNG0 0x10
#define AD7292_BANK_REG_VIN_RNG1 0x11
#define AD7292_BANK_REG_SAMP_MODE 0x12
#define AD7292_RD_FLAG_MSK(x) (BIT(7) | ((x) & 0x3F))
/* AD7292_REG_ADC_CONVERSION */
#define AD7292_ADC_DATA_MASK GENMASK(15, 6)
#define AD7292_ADC_DATA(x) FIELD_GET(AD7292_ADC_DATA_MASK, x)
/* AD7292_CHANNEL_SAMPLING_MODE */
#define AD7292_CH_SAMP_MODE(reg, ch) (((reg) >> 8) & BIT(ch))
/* AD7292_CHANNEL_VIN_RANGE */
#define AD7292_CH_VIN_RANGE(reg, ch) ((reg) & BIT(ch))
#define AD7292_VOLTAGE_CHAN(_chan) \
{ \
.type = IIO_VOLTAGE, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.indexed = 1, \
.channel = _chan, \
}
static const struct iio_chan_spec ad7292_channels[] = {
AD7292_VOLTAGE_CHAN(0),
AD7292_VOLTAGE_CHAN(1),
AD7292_VOLTAGE_CHAN(2),
AD7292_VOLTAGE_CHAN(3),
AD7292_VOLTAGE_CHAN(4),
AD7292_VOLTAGE_CHAN(5),
AD7292_VOLTAGE_CHAN(6),
AD7292_VOLTAGE_CHAN(7)
};
static const struct iio_chan_spec ad7292_channels_diff[] = {
{
.type = IIO_VOLTAGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.indexed = 1,
.differential = 1,
.channel = 0,
.channel2 = 1,
},
AD7292_VOLTAGE_CHAN(2),
AD7292_VOLTAGE_CHAN(3),
AD7292_VOLTAGE_CHAN(4),
AD7292_VOLTAGE_CHAN(5),
AD7292_VOLTAGE_CHAN(6),
AD7292_VOLTAGE_CHAN(7)
};
struct ad7292_state {
struct spi_device *spi;
struct regulator *reg;
unsigned short vref_mv;
__be16 d16 __aligned(IIO_DMA_MINALIGN);
u8 d8[2];
};
static int ad7292_spi_reg_read(struct ad7292_state *st, unsigned int addr)
{
int ret;
st->d8[0] = AD7292_RD_FLAG_MSK(addr);
ret = spi_write_then_read(st->spi, st->d8, 1, &st->d16, 2);
if (ret < 0)
return ret;
return be16_to_cpu(st->d16);
}
static int ad7292_spi_subreg_read(struct ad7292_state *st, unsigned int addr,
unsigned int sub_addr, unsigned int len)
{
unsigned int shift = 16 - (8 * len);
int ret;
st->d8[0] = AD7292_RD_FLAG_MSK(addr);
st->d8[1] = sub_addr;
ret = spi_write_then_read(st->spi, st->d8, 2, &st->d16, len);
if (ret < 0)
return ret;
return (be16_to_cpu(st->d16) >> shift);
}
static int ad7292_single_conversion(struct ad7292_state *st,
unsigned int chan_addr)
{
int ret;
struct spi_transfer t[] = {
{
.tx_buf = &st->d8,
.len = 4,
.delay = {
.value = 6,
.unit = SPI_DELAY_UNIT_USECS
},
}, {
.rx_buf = &st->d16,
.len = 2,
},
};
st->d8[0] = chan_addr;
st->d8[1] = AD7292_RD_FLAG_MSK(AD7292_REG_CONV_COMM);
ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
if (ret < 0)
return ret;
return be16_to_cpu(st->d16);
}
static int ad7292_vin_range_multiplier(struct ad7292_state *st, int channel)
{
int samp_mode, range0, range1, factor = 1;
/*
* Every AD7292 ADC channel may have its input range adjusted according
* to the settings at the ADC sampling mode and VIN range subregisters.
* For a given channel, the minimum input range is equal to Vref, and it
* may be increased by a multiplier factor of 2 or 4 according to the
* following rule:
* If channel is being sampled with respect to AGND:
* factor = 4 if VIN range0 and VIN range1 equal 0
* factor = 2 if only one of VIN ranges equal 1
* factor = 1 if both VIN range0 and VIN range1 equal 1
* If channel is being sampled with respect to AVDD:
* factor = 4 if VIN range0 and VIN range1 equal 0
* Behavior is undefined if any of VIN range doesn't equal 0
*/
samp_mode = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
AD7292_BANK_REG_SAMP_MODE, 2);
if (samp_mode < 0)
return samp_mode;
range0 = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
AD7292_BANK_REG_VIN_RNG0, 2);
if (range0 < 0)
return range0;
range1 = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
AD7292_BANK_REG_VIN_RNG1, 2);
if (range1 < 0)
return range1;
if (AD7292_CH_SAMP_MODE(samp_mode, channel)) {
/* Sampling with respect to AGND */
if (!AD7292_CH_VIN_RANGE(range0, channel))
factor *= 2;
if (!AD7292_CH_VIN_RANGE(range1, channel))
factor *= 2;
} else {
/* Sampling with respect to AVDD */
if (AD7292_CH_VIN_RANGE(range0, channel) ||
AD7292_CH_VIN_RANGE(range1, channel))
return -EPERM;
factor = 4;
}
return factor;
}
static int ad7292_read_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
int *val, int *val2, long info)
{
struct ad7292_state *st = iio_priv(indio_dev);
unsigned int ch_addr;
int ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
ch_addr = AD7292_REG_ADC_CH(chan->channel);
ret = ad7292_single_conversion(st, ch_addr);
if (ret < 0)
return ret;
*val = AD7292_ADC_DATA(ret);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/*
* To convert a raw value to standard units, the IIO defines
* this formula: Scaled value = (raw + offset) * scale.
* For the scale to be a correct multiplier for (raw + offset),
* it must be calculated as the input range divided by the
* number of possible distinct input values. Given the ADC data
* is 10 bit long, it may assume 2^10 distinct values.
* Hence, scale = range / 2^10. The IIO_VAL_FRACTIONAL_LOG2
* return type indicates to the IIO API to divide *val by 2 to
* the power of *val2 when returning from read_raw.
*/
ret = ad7292_vin_range_multiplier(st, chan->channel);
if (ret < 0)
return ret;
*val = st->vref_mv * ret;
*val2 = 10;
return IIO_VAL_FRACTIONAL_LOG2;
default:
break;
}
return -EINVAL;
}
static const struct iio_info ad7292_info = {
.read_raw = ad7292_read_raw,
};
static void ad7292_regulator_disable(void *data)
{
struct ad7292_state *st = data;
regulator_disable(st->reg);
}
static int ad7292_probe(struct spi_device *spi)
{
struct ad7292_state *st;
struct iio_dev *indio_dev;
struct device_node *child;
bool diff_channels = false;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->spi = spi;
ret = ad7292_spi_reg_read(st, AD7292_REG_VENDOR_ID);
if (ret != ADI_VENDOR_ID) {
dev_err(&spi->dev, "Wrong vendor id 0x%x\n", ret);
return -EINVAL;
}
st->reg = devm_regulator_get_optional(&spi->dev, "vref");
if (!IS_ERR(st->reg)) {
ret = regulator_enable(st->reg);
if (ret) {
dev_err(&spi->dev,
"Failed to enable external vref supply\n");
return ret;
}
ret = devm_add_action_or_reset(&spi->dev,
ad7292_regulator_disable, st);
if (ret)
return ret;
ret = regulator_get_voltage(st->reg);
if (ret < 0)
return ret;
st->vref_mv = ret / 1000;
} else {
/* Use the internal voltage reference. */
st->vref_mv = 1250;
}
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &ad7292_info;
for_each_available_child_of_node(spi->dev.of_node, child) {
diff_channels = of_property_read_bool(child, "diff-channels");
if (diff_channels) {
of_node_put(child);
break;
}
}
if (diff_channels) {
indio_dev->num_channels = ARRAY_SIZE(ad7292_channels_diff);
indio_dev->channels = ad7292_channels_diff;
} else {
indio_dev->num_channels = ARRAY_SIZE(ad7292_channels);
indio_dev->channels = ad7292_channels;
}
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id ad7292_id_table[] = {
{ "ad7292", 0 },
{}
};
MODULE_DEVICE_TABLE(spi, ad7292_id_table);
static const struct of_device_id ad7292_of_match[] = {
{ .compatible = "adi,ad7292" },
{ },
};
MODULE_DEVICE_TABLE(of, ad7292_of_match);
static struct spi_driver ad7292_driver = {
.driver = {
.name = "ad7292",
.of_match_table = ad7292_of_match,
},
.probe = ad7292_probe,
.id_table = ad7292_id_table,
};
module_spi_driver(ad7292_driver);
MODULE_AUTHOR("Marcelo Schmitt <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD7292 ADC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ad7292.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2022 Analog Devices, Inc.
* ADI MAX77541 ADC Driver with IIO interface
*/
#include <linux/bitfield.h>
#include <linux/iio/iio.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/units.h>
#include <linux/mfd/max77541.h>
enum max77541_adc_range {
LOW_RANGE,
MID_RANGE,
HIGH_RANGE,
};
enum max77541_adc_channel {
MAX77541_ADC_VSYS_V,
MAX77541_ADC_VOUT1_V,
MAX77541_ADC_VOUT2_V,
MAX77541_ADC_TEMP,
};
static int max77541_adc_offset(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2)
{
switch (chan->channel) {
case MAX77541_ADC_TEMP:
*val = DIV_ROUND_CLOSEST(ABSOLUTE_ZERO_MILLICELSIUS, 1725);
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int max77541_adc_scale(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2)
{
struct regmap **regmap = iio_priv(indio_dev);
unsigned int reg_val;
int ret;
switch (chan->channel) {
case MAX77541_ADC_VSYS_V:
*val = 25;
return IIO_VAL_INT;
case MAX77541_ADC_VOUT1_V:
case MAX77541_ADC_VOUT2_V:
ret = regmap_read(*regmap, MAX77541_REG_M2_CFG1, ®_val);
if (ret)
return ret;
reg_val = FIELD_GET(MAX77541_BITS_MX_CFG1_RNG, reg_val);
switch (reg_val) {
case LOW_RANGE:
*val = 6;
*val2 = 250000;
break;
case MID_RANGE:
*val = 12;
*val2 = 500000;
break;
case HIGH_RANGE:
*val = 25;
return IIO_VAL_INT;
default:
return -EINVAL;
}
return IIO_VAL_INT_PLUS_MICRO;
case MAX77541_ADC_TEMP:
*val = 1725;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int max77541_adc_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val)
{
struct regmap **regmap = iio_priv(indio_dev);
int ret;
ret = regmap_read(*regmap, chan->address, val);
if (ret)
return ret;
return IIO_VAL_INT;
}
#define MAX77541_ADC_CHANNEL_V(_channel, _name, _type, _reg) \
{ \
.type = _type, \
.indexed = 1, \
.channel = _channel, \
.address = _reg, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.datasheet_name = _name, \
}
#define MAX77541_ADC_CHANNEL_TEMP(_channel, _name, _type, _reg) \
{ \
.type = _type, \
.indexed = 1, \
.channel = _channel, \
.address = _reg, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) |\
BIT(IIO_CHAN_INFO_OFFSET),\
.datasheet_name = _name, \
}
static const struct iio_chan_spec max77541_adc_channels[] = {
MAX77541_ADC_CHANNEL_V(MAX77541_ADC_VSYS_V, "vsys_v", IIO_VOLTAGE,
MAX77541_REG_ADC_DATA_CH1),
MAX77541_ADC_CHANNEL_V(MAX77541_ADC_VOUT1_V, "vout1_v", IIO_VOLTAGE,
MAX77541_REG_ADC_DATA_CH2),
MAX77541_ADC_CHANNEL_V(MAX77541_ADC_VOUT2_V, "vout2_v", IIO_VOLTAGE,
MAX77541_REG_ADC_DATA_CH3),
MAX77541_ADC_CHANNEL_TEMP(MAX77541_ADC_TEMP, "temp", IIO_TEMP,
MAX77541_REG_ADC_DATA_CH6),
};
static int max77541_adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
switch (mask) {
case IIO_CHAN_INFO_OFFSET:
return max77541_adc_offset(indio_dev, chan, val, val2);
case IIO_CHAN_INFO_SCALE:
return max77541_adc_scale(indio_dev, chan, val, val2);
case IIO_CHAN_INFO_RAW:
return max77541_adc_raw(indio_dev, chan, val);
default:
return -EINVAL;
}
}
static const struct iio_info max77541_adc_info = {
.read_raw = max77541_adc_read_raw,
};
static int max77541_adc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct iio_dev *indio_dev;
struct regmap **regmap;
indio_dev = devm_iio_device_alloc(dev, sizeof(*regmap));
if (!indio_dev)
return -ENOMEM;
regmap = iio_priv(indio_dev);
*regmap = dev_get_regmap(dev->parent, NULL);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->name = "max77541";
indio_dev->info = &max77541_adc_info;
indio_dev->channels = max77541_adc_channels;
indio_dev->num_channels = ARRAY_SIZE(max77541_adc_channels);
return devm_iio_device_register(dev, indio_dev);
}
static const struct platform_device_id max77541_adc_platform_id[] = {
{ "max77541-adc" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, max77541_adc_platform_id);
static struct platform_driver max77541_adc_driver = {
.driver = {
.name = "max77541-adc",
},
.probe = max77541_adc_probe,
.id_table = max77541_adc_platform_id,
};
module_platform_driver(max77541_adc_driver);
MODULE_AUTHOR("Okan Sahin <[email protected]>");
MODULE_DESCRIPTION("MAX77541 ADC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/adc/max77541-adc.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/fixp-arith.h>
#include <linux/iio/adc/qcom-vadc-common.h>
#include <linux/math64.h>
#include <linux/log2.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/units.h>
/**
* struct vadc_map_pt - Map the graph representation for ADC channel
* @x: Represent the ADC digitized code.
* @y: Represent the physical data which can be temperature, voltage,
* resistance.
*/
struct vadc_map_pt {
s32 x;
s32 y;
};
/* Voltage to temperature */
static const struct vadc_map_pt adcmap_100k_104ef_104fb[] = {
{1758, -40000 },
{1742, -35000 },
{1719, -30000 },
{1691, -25000 },
{1654, -20000 },
{1608, -15000 },
{1551, -10000 },
{1483, -5000 },
{1404, 0 },
{1315, 5000 },
{1218, 10000 },
{1114, 15000 },
{1007, 20000 },
{900, 25000 },
{795, 30000 },
{696, 35000 },
{605, 40000 },
{522, 45000 },
{448, 50000 },
{383, 55000 },
{327, 60000 },
{278, 65000 },
{237, 70000 },
{202, 75000 },
{172, 80000 },
{146, 85000 },
{125, 90000 },
{107, 95000 },
{92, 100000 },
{79, 105000 },
{68, 110000 },
{59, 115000 },
{51, 120000 },
{44, 125000 }
};
/*
* Voltage to temperature table for 100k pull up for NTCG104EF104 with
* 1.875V reference.
*/
static const struct vadc_map_pt adcmap_100k_104ef_104fb_1875_vref[] = {
{ 1831, -40000 },
{ 1814, -35000 },
{ 1791, -30000 },
{ 1761, -25000 },
{ 1723, -20000 },
{ 1675, -15000 },
{ 1616, -10000 },
{ 1545, -5000 },
{ 1463, 0 },
{ 1370, 5000 },
{ 1268, 10000 },
{ 1160, 15000 },
{ 1049, 20000 },
{ 937, 25000 },
{ 828, 30000 },
{ 726, 35000 },
{ 630, 40000 },
{ 544, 45000 },
{ 467, 50000 },
{ 399, 55000 },
{ 340, 60000 },
{ 290, 65000 },
{ 247, 70000 },
{ 209, 75000 },
{ 179, 80000 },
{ 153, 85000 },
{ 130, 90000 },
{ 112, 95000 },
{ 96, 100000 },
{ 82, 105000 },
{ 71, 110000 },
{ 62, 115000 },
{ 53, 120000 },
{ 46, 125000 },
};
static const struct vadc_map_pt adcmap7_die_temp[] = {
{ 857300, 160000 },
{ 820100, 140000 },
{ 782500, 120000 },
{ 744600, 100000 },
{ 706400, 80000 },
{ 667900, 60000 },
{ 629300, 40000 },
{ 590500, 20000 },
{ 551500, 0 },
{ 512400, -20000 },
{ 473100, -40000 },
{ 433700, -60000 },
};
/*
* Resistance to temperature table for 100k pull up for NTCG104EF104.
*/
static const struct vadc_map_pt adcmap7_100k[] = {
{ 4250657, -40960 },
{ 3962085, -39936 },
{ 3694875, -38912 },
{ 3447322, -37888 },
{ 3217867, -36864 },
{ 3005082, -35840 },
{ 2807660, -34816 },
{ 2624405, -33792 },
{ 2454218, -32768 },
{ 2296094, -31744 },
{ 2149108, -30720 },
{ 2012414, -29696 },
{ 1885232, -28672 },
{ 1766846, -27648 },
{ 1656598, -26624 },
{ 1553884, -25600 },
{ 1458147, -24576 },
{ 1368873, -23552 },
{ 1285590, -22528 },
{ 1207863, -21504 },
{ 1135290, -20480 },
{ 1067501, -19456 },
{ 1004155, -18432 },
{ 944935, -17408 },
{ 889550, -16384 },
{ 837731, -15360 },
{ 789229, -14336 },
{ 743813, -13312 },
{ 701271, -12288 },
{ 661405, -11264 },
{ 624032, -10240 },
{ 588982, -9216 },
{ 556100, -8192 },
{ 525239, -7168 },
{ 496264, -6144 },
{ 469050, -5120 },
{ 443480, -4096 },
{ 419448, -3072 },
{ 396851, -2048 },
{ 375597, -1024 },
{ 355598, 0 },
{ 336775, 1024 },
{ 319052, 2048 },
{ 302359, 3072 },
{ 286630, 4096 },
{ 271806, 5120 },
{ 257829, 6144 },
{ 244646, 7168 },
{ 232209, 8192 },
{ 220471, 9216 },
{ 209390, 10240 },
{ 198926, 11264 },
{ 189040, 12288 },
{ 179698, 13312 },
{ 170868, 14336 },
{ 162519, 15360 },
{ 154622, 16384 },
{ 147150, 17408 },
{ 140079, 18432 },
{ 133385, 19456 },
{ 127046, 20480 },
{ 121042, 21504 },
{ 115352, 22528 },
{ 109960, 23552 },
{ 104848, 24576 },
{ 100000, 25600 },
{ 95402, 26624 },
{ 91038, 27648 },
{ 86897, 28672 },
{ 82965, 29696 },
{ 79232, 30720 },
{ 75686, 31744 },
{ 72316, 32768 },
{ 69114, 33792 },
{ 66070, 34816 },
{ 63176, 35840 },
{ 60423, 36864 },
{ 57804, 37888 },
{ 55312, 38912 },
{ 52940, 39936 },
{ 50681, 40960 },
{ 48531, 41984 },
{ 46482, 43008 },
{ 44530, 44032 },
{ 42670, 45056 },
{ 40897, 46080 },
{ 39207, 47104 },
{ 37595, 48128 },
{ 36057, 49152 },
{ 34590, 50176 },
{ 33190, 51200 },
{ 31853, 52224 },
{ 30577, 53248 },
{ 29358, 54272 },
{ 28194, 55296 },
{ 27082, 56320 },
{ 26020, 57344 },
{ 25004, 58368 },
{ 24033, 59392 },
{ 23104, 60416 },
{ 22216, 61440 },
{ 21367, 62464 },
{ 20554, 63488 },
{ 19776, 64512 },
{ 19031, 65536 },
{ 18318, 66560 },
{ 17636, 67584 },
{ 16982, 68608 },
{ 16355, 69632 },
{ 15755, 70656 },
{ 15180, 71680 },
{ 14628, 72704 },
{ 14099, 73728 },
{ 13592, 74752 },
{ 13106, 75776 },
{ 12640, 76800 },
{ 12192, 77824 },
{ 11762, 78848 },
{ 11350, 79872 },
{ 10954, 80896 },
{ 10574, 81920 },
{ 10209, 82944 },
{ 9858, 83968 },
{ 9521, 84992 },
{ 9197, 86016 },
{ 8886, 87040 },
{ 8587, 88064 },
{ 8299, 89088 },
{ 8023, 90112 },
{ 7757, 91136 },
{ 7501, 92160 },
{ 7254, 93184 },
{ 7017, 94208 },
{ 6789, 95232 },
{ 6570, 96256 },
{ 6358, 97280 },
{ 6155, 98304 },
{ 5959, 99328 },
{ 5770, 100352 },
{ 5588, 101376 },
{ 5412, 102400 },
{ 5243, 103424 },
{ 5080, 104448 },
{ 4923, 105472 },
{ 4771, 106496 },
{ 4625, 107520 },
{ 4484, 108544 },
{ 4348, 109568 },
{ 4217, 110592 },
{ 4090, 111616 },
{ 3968, 112640 },
{ 3850, 113664 },
{ 3736, 114688 },
{ 3626, 115712 },
{ 3519, 116736 },
{ 3417, 117760 },
{ 3317, 118784 },
{ 3221, 119808 },
{ 3129, 120832 },
{ 3039, 121856 },
{ 2952, 122880 },
{ 2868, 123904 },
{ 2787, 124928 },
{ 2709, 125952 },
{ 2633, 126976 },
{ 2560, 128000 },
{ 2489, 129024 },
{ 2420, 130048 }
};
static const struct u32_fract adc5_prescale_ratios[] = {
{ .numerator = 1, .denominator = 1 },
{ .numerator = 1, .denominator = 3 },
{ .numerator = 1, .denominator = 4 },
{ .numerator = 1, .denominator = 6 },
{ .numerator = 1, .denominator = 20 },
{ .numerator = 1, .denominator = 8 },
{ .numerator = 10, .denominator = 81 },
{ .numerator = 1, .denominator = 10 },
{ .numerator = 1, .denominator = 16 },
};
static int qcom_vadc_scale_hw_calib_volt(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_uv);
static int qcom_vadc_scale_hw_calib_therm(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec);
static int qcom_vadc7_scale_hw_calib_therm(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec);
static int qcom_vadc_scale_hw_smb_temp(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec);
static int qcom_vadc_scale_hw_chg5_temp(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec);
static int qcom_vadc_scale_hw_calib_die_temp(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec);
static int qcom_vadc7_scale_hw_calib_die_temp(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec);
static struct qcom_adc5_scale_type scale_adc5_fn[] = {
[SCALE_HW_CALIB_DEFAULT] = {qcom_vadc_scale_hw_calib_volt},
[SCALE_HW_CALIB_THERM_100K_PULLUP] = {qcom_vadc_scale_hw_calib_therm},
[SCALE_HW_CALIB_XOTHERM] = {qcom_vadc_scale_hw_calib_therm},
[SCALE_HW_CALIB_THERM_100K_PU_PM7] = {
qcom_vadc7_scale_hw_calib_therm},
[SCALE_HW_CALIB_PMIC_THERM] = {qcom_vadc_scale_hw_calib_die_temp},
[SCALE_HW_CALIB_PMIC_THERM_PM7] = {
qcom_vadc7_scale_hw_calib_die_temp},
[SCALE_HW_CALIB_PM5_CHG_TEMP] = {qcom_vadc_scale_hw_chg5_temp},
[SCALE_HW_CALIB_PM5_SMB_TEMP] = {qcom_vadc_scale_hw_smb_temp},
};
static int qcom_vadc_map_voltage_temp(const struct vadc_map_pt *pts,
u32 tablesize, s32 input, int *output)
{
u32 i = 0;
if (!pts)
return -EINVAL;
while (i < tablesize && pts[i].x > input)
i++;
if (i == 0) {
*output = pts[0].y;
} else if (i == tablesize) {
*output = pts[tablesize - 1].y;
} else {
/* interpolate linearly */
*output = fixp_linear_interpolate(pts[i - 1].x, pts[i - 1].y,
pts[i].x, pts[i].y,
input);
}
return 0;
}
static s32 qcom_vadc_map_temp_voltage(const struct vadc_map_pt *pts,
u32 tablesize, int input)
{
u32 i = 0;
/*
* Table must be sorted, find the interval of 'y' which contains value
* 'input' and map it to proper 'x' value
*/
while (i < tablesize && pts[i].y < input)
i++;
if (i == 0)
return pts[0].x;
if (i == tablesize)
return pts[tablesize - 1].x;
/* interpolate linearly */
return fixp_linear_interpolate(pts[i - 1].y, pts[i - 1].x,
pts[i].y, pts[i].x, input);
}
static void qcom_vadc_scale_calib(const struct vadc_linear_graph *calib_graph,
u16 adc_code,
bool absolute,
s64 *scale_voltage)
{
*scale_voltage = (adc_code - calib_graph->gnd);
*scale_voltage *= calib_graph->dx;
*scale_voltage = div64_s64(*scale_voltage, calib_graph->dy);
if (absolute)
*scale_voltage += calib_graph->dx;
if (*scale_voltage < 0)
*scale_voltage = 0;
}
static int qcom_vadc_scale_volt(const struct vadc_linear_graph *calib_graph,
const struct u32_fract *prescale,
bool absolute, u16 adc_code,
int *result_uv)
{
s64 voltage = 0, result = 0;
qcom_vadc_scale_calib(calib_graph, adc_code, absolute, &voltage);
voltage *= prescale->denominator;
result = div64_s64(voltage, prescale->numerator);
*result_uv = result;
return 0;
}
static int qcom_vadc_scale_therm(const struct vadc_linear_graph *calib_graph,
const struct u32_fract *prescale,
bool absolute, u16 adc_code,
int *result_mdec)
{
s64 voltage = 0;
int ret;
qcom_vadc_scale_calib(calib_graph, adc_code, absolute, &voltage);
if (absolute)
voltage = div64_s64(voltage, 1000);
ret = qcom_vadc_map_voltage_temp(adcmap_100k_104ef_104fb,
ARRAY_SIZE(adcmap_100k_104ef_104fb),
voltage, result_mdec);
if (ret)
return ret;
return 0;
}
static int qcom_vadc_scale_die_temp(const struct vadc_linear_graph *calib_graph,
const struct u32_fract *prescale,
bool absolute,
u16 adc_code, int *result_mdec)
{
s64 voltage = 0;
u64 temp; /* Temporary variable for do_div */
qcom_vadc_scale_calib(calib_graph, adc_code, absolute, &voltage);
if (voltage > 0) {
temp = voltage * prescale->denominator;
do_div(temp, prescale->numerator * 2);
voltage = temp;
} else {
voltage = 0;
}
*result_mdec = milli_kelvin_to_millicelsius(voltage);
return 0;
}
static int qcom_vadc_scale_chg_temp(const struct vadc_linear_graph *calib_graph,
const struct u32_fract *prescale,
bool absolute,
u16 adc_code, int *result_mdec)
{
s64 voltage = 0, result = 0;
qcom_vadc_scale_calib(calib_graph, adc_code, absolute, &voltage);
voltage *= prescale->denominator;
voltage = div64_s64(voltage, prescale->numerator);
voltage = ((PMI_CHG_SCALE_1) * (voltage * 2));
voltage = (voltage + PMI_CHG_SCALE_2);
result = div64_s64(voltage, 1000000);
*result_mdec = result;
return 0;
}
/* convert voltage to ADC code, using 1.875V reference */
static u16 qcom_vadc_scale_voltage_code(s32 voltage,
const struct u32_fract *prescale,
const u32 full_scale_code_volt,
unsigned int factor)
{
s64 volt = voltage;
s64 adc_vdd_ref_mv = 1875; /* reference voltage */
volt *= prescale->numerator * factor * full_scale_code_volt;
volt = div64_s64(volt, (s64)prescale->denominator * adc_vdd_ref_mv * 1000);
return volt;
}
static int qcom_vadc_scale_code_voltage_factor(u16 adc_code,
const struct u32_fract *prescale,
const struct adc5_data *data,
unsigned int factor)
{
s64 voltage, temp, adc_vdd_ref_mv = 1875;
/*
* The normal data range is between 0V to 1.875V. On cases where
* we read low voltage values, the ADC code can go beyond the
* range and the scale result is incorrect so we clamp the values
* for the cases where the code represents a value below 0V
*/
if (adc_code > VADC5_MAX_CODE)
adc_code = 0;
/* (ADC code * vref_vadc (1.875V)) / full_scale_code */
voltage = (s64) adc_code * adc_vdd_ref_mv * 1000;
voltage = div64_s64(voltage, data->full_scale_code_volt);
if (voltage > 0) {
voltage *= prescale->denominator;
temp = prescale->numerator * factor;
voltage = div64_s64(voltage, temp);
} else {
voltage = 0;
}
return (int) voltage;
}
static int qcom_vadc7_scale_hw_calib_therm(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec)
{
s64 resistance = adc_code;
int ret, result;
if (adc_code >= RATIO_MAX_ADC7)
return -EINVAL;
/* (ADC code * R_PULLUP (100Kohm)) / (full_scale_code - ADC code)*/
resistance *= R_PU_100K;
resistance = div64_s64(resistance, RATIO_MAX_ADC7 - adc_code);
ret = qcom_vadc_map_voltage_temp(adcmap7_100k,
ARRAY_SIZE(adcmap7_100k),
resistance, &result);
if (ret)
return ret;
*result_mdec = result;
return 0;
}
static int qcom_vadc_scale_hw_calib_volt(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_uv)
{
*result_uv = qcom_vadc_scale_code_voltage_factor(adc_code,
prescale, data, 1);
return 0;
}
static int qcom_vadc_scale_hw_calib_therm(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec)
{
int voltage;
voltage = qcom_vadc_scale_code_voltage_factor(adc_code,
prescale, data, 1000);
/* Map voltage to temperature from look-up table */
return qcom_vadc_map_voltage_temp(adcmap_100k_104ef_104fb_1875_vref,
ARRAY_SIZE(adcmap_100k_104ef_104fb_1875_vref),
voltage, result_mdec);
}
static int qcom_vadc_scale_hw_calib_die_temp(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec)
{
*result_mdec = qcom_vadc_scale_code_voltage_factor(adc_code,
prescale, data, 2);
*result_mdec = milli_kelvin_to_millicelsius(*result_mdec);
return 0;
}
static int qcom_vadc7_scale_hw_calib_die_temp(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec)
{
int voltage;
voltage = qcom_vadc_scale_code_voltage_factor(adc_code,
prescale, data, 1);
return qcom_vadc_map_voltage_temp(adcmap7_die_temp, ARRAY_SIZE(adcmap7_die_temp),
voltage, result_mdec);
}
static int qcom_vadc_scale_hw_smb_temp(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec)
{
*result_mdec = qcom_vadc_scale_code_voltage_factor(adc_code * 100,
prescale, data, PMIC5_SMB_TEMP_SCALE_FACTOR);
*result_mdec = PMIC5_SMB_TEMP_CONSTANT - *result_mdec;
return 0;
}
static int qcom_vadc_scale_hw_chg5_temp(
const struct u32_fract *prescale,
const struct adc5_data *data,
u16 adc_code, int *result_mdec)
{
*result_mdec = qcom_vadc_scale_code_voltage_factor(adc_code,
prescale, data, 4);
*result_mdec = PMIC5_CHG_TEMP_SCALE_FACTOR - *result_mdec;
return 0;
}
int qcom_vadc_scale(enum vadc_scale_fn_type scaletype,
const struct vadc_linear_graph *calib_graph,
const struct u32_fract *prescale,
bool absolute,
u16 adc_code, int *result)
{
switch (scaletype) {
case SCALE_DEFAULT:
return qcom_vadc_scale_volt(calib_graph, prescale,
absolute, adc_code,
result);
case SCALE_THERM_100K_PULLUP:
case SCALE_XOTHERM:
return qcom_vadc_scale_therm(calib_graph, prescale,
absolute, adc_code,
result);
case SCALE_PMIC_THERM:
return qcom_vadc_scale_die_temp(calib_graph, prescale,
absolute, adc_code,
result);
case SCALE_PMI_CHG_TEMP:
return qcom_vadc_scale_chg_temp(calib_graph, prescale,
absolute, adc_code,
result);
default:
return -EINVAL;
}
}
EXPORT_SYMBOL(qcom_vadc_scale);
u16 qcom_adc_tm5_temp_volt_scale(unsigned int prescale_ratio,
u32 full_scale_code_volt, int temp)
{
const struct u32_fract *prescale = &adc5_prescale_ratios[prescale_ratio];
s32 voltage;
voltage = qcom_vadc_map_temp_voltage(adcmap_100k_104ef_104fb_1875_vref,
ARRAY_SIZE(adcmap_100k_104ef_104fb_1875_vref),
temp);
return qcom_vadc_scale_voltage_code(voltage, prescale, full_scale_code_volt, 1000);
}
EXPORT_SYMBOL(qcom_adc_tm5_temp_volt_scale);
u16 qcom_adc_tm5_gen2_temp_res_scale(int temp)
{
int64_t resistance;
resistance = qcom_vadc_map_temp_voltage(adcmap7_100k,
ARRAY_SIZE(adcmap7_100k), temp);
return div64_s64(resistance * RATIO_MAX_ADC7, resistance + R_PU_100K);
}
EXPORT_SYMBOL(qcom_adc_tm5_gen2_temp_res_scale);
int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype,
unsigned int prescale_ratio,
const struct adc5_data *data,
u16 adc_code, int *result)
{
const struct u32_fract *prescale = &adc5_prescale_ratios[prescale_ratio];
if (!(scaletype >= SCALE_HW_CALIB_DEFAULT &&
scaletype < SCALE_HW_CALIB_INVALID)) {
pr_err("Invalid scale type %d\n", scaletype);
return -EINVAL;
}
return scale_adc5_fn[scaletype].scale_fn(prescale, data,
adc_code, result);
}
EXPORT_SYMBOL(qcom_adc5_hw_scale);
int qcom_adc5_prescaling_from_dt(u32 numerator, u32 denominator)
{
unsigned int pre;
for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++)
if (adc5_prescale_ratios[pre].numerator == numerator &&
adc5_prescale_ratios[pre].denominator == denominator)
break;
if (pre == ARRAY_SIZE(adc5_prescale_ratios))
return -EINVAL;
return pre;
}
EXPORT_SYMBOL(qcom_adc5_prescaling_from_dt);
int qcom_adc5_hw_settle_time_from_dt(u32 value,
const unsigned int *hw_settle)
{
unsigned int i;
for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) {
if (value == hw_settle[i])
return i;
}
return -EINVAL;
}
EXPORT_SYMBOL(qcom_adc5_hw_settle_time_from_dt);
int qcom_adc5_avg_samples_from_dt(u32 value)
{
if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX)
return -EINVAL;
return __ffs(value);
}
EXPORT_SYMBOL(qcom_adc5_avg_samples_from_dt);
int qcom_adc5_decimation_from_dt(u32 value, const unsigned int *decimation)
{
unsigned int i;
for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) {
if (value == decimation[i])
return i;
}
return -EINVAL;
}
EXPORT_SYMBOL(qcom_adc5_decimation_from_dt);
int qcom_vadc_decimation_from_dt(u32 value)
{
if (!is_power_of_2(value) || value < VADC_DECIMATION_MIN ||
value > VADC_DECIMATION_MAX)
return -EINVAL;
return __ffs64(value / VADC_DECIMATION_MIN);
}
EXPORT_SYMBOL(qcom_vadc_decimation_from_dt);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Qualcomm ADC common functionality");
| linux-master | drivers/iio/adc/qcom-vadc-common.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* ti-adc161s626.c - Texas Instruments ADC161S626 1-channel differential ADC
*
* ADC Devices Supported:
* adc141s626 - 14-bit ADC
* adc161s626 - 16-bit ADC
*
* Copyright (C) 2016-2018
* Author: Matt Ranostay <[email protected]>
*/
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#include <linux/iio/trigger.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/regulator/consumer.h>
#define TI_ADC_DRV_NAME "ti-adc161s626"
enum {
TI_ADC141S626,
TI_ADC161S626,
};
static const struct iio_chan_spec ti_adc141s626_channels[] = {
{
.type = IIO_VOLTAGE,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET),
.scan_index = 0,
.scan_type = {
.sign = 's',
.realbits = 14,
.storagebits = 16,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static const struct iio_chan_spec ti_adc161s626_channels[] = {
{
.type = IIO_VOLTAGE,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET),
.scan_index = 0,
.scan_type = {
.sign = 's',
.realbits = 16,
.storagebits = 16,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
struct ti_adc_data {
struct iio_dev *indio_dev;
struct spi_device *spi;
struct regulator *ref;
u8 read_size;
u8 shift;
u8 buffer[16] __aligned(IIO_DMA_MINALIGN);
};
static int ti_adc_read_measurement(struct ti_adc_data *data,
struct iio_chan_spec const *chan, int *val)
{
int ret;
switch (data->read_size) {
case 2: {
__be16 buf;
ret = spi_read(data->spi, (void *) &buf, 2);
if (ret)
return ret;
*val = be16_to_cpu(buf);
break;
}
case 3: {
__be32 buf;
ret = spi_read(data->spi, (void *) &buf, 3);
if (ret)
return ret;
*val = be32_to_cpu(buf) >> 8;
break;
}
default:
return -EINVAL;
}
*val = sign_extend32(*val >> data->shift, chan->scan_type.realbits - 1);
return 0;
}
static irqreturn_t ti_adc_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct ti_adc_data *data = iio_priv(indio_dev);
int ret;
ret = ti_adc_read_measurement(data, &indio_dev->channels[0],
(int *) &data->buffer);
if (!ret)
iio_push_to_buffers_with_timestamp(indio_dev,
data->buffer,
iio_get_time_ns(indio_dev));
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int ti_adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct ti_adc_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = ti_adc_read_measurement(data, chan, val);
iio_device_release_direct_mode(indio_dev);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = regulator_get_voltage(data->ref);
if (ret < 0)
return ret;
*val = ret / 1000;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_OFFSET:
*val = 1 << (chan->scan_type.realbits - 1);
return IIO_VAL_INT;
}
return 0;
}
static const struct iio_info ti_adc_info = {
.read_raw = ti_adc_read_raw,
};
static void ti_adc_reg_disable(void *reg)
{
regulator_disable(reg);
}
static int ti_adc_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct ti_adc_data *data;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
indio_dev->info = &ti_adc_info;
indio_dev->name = TI_ADC_DRV_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
data = iio_priv(indio_dev);
data->spi = spi;
switch (spi_get_device_id(spi)->driver_data) {
case TI_ADC141S626:
indio_dev->channels = ti_adc141s626_channels;
indio_dev->num_channels = ARRAY_SIZE(ti_adc141s626_channels);
data->shift = 0;
data->read_size = 2;
break;
case TI_ADC161S626:
indio_dev->channels = ti_adc161s626_channels;
indio_dev->num_channels = ARRAY_SIZE(ti_adc161s626_channels);
data->shift = 6;
data->read_size = 3;
break;
}
data->ref = devm_regulator_get(&spi->dev, "vdda");
if (IS_ERR(data->ref))
return PTR_ERR(data->ref);
ret = regulator_enable(data->ref);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&spi->dev, ti_adc_reg_disable,
data->ref);
if (ret)
return ret;
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
ti_adc_trigger_handler, NULL);
if (ret)
return ret;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct of_device_id ti_adc_dt_ids[] = {
{ .compatible = "ti,adc141s626", },
{ .compatible = "ti,adc161s626", },
{}
};
MODULE_DEVICE_TABLE(of, ti_adc_dt_ids);
static const struct spi_device_id ti_adc_id[] = {
{"adc141s626", TI_ADC141S626},
{"adc161s626", TI_ADC161S626},
{},
};
MODULE_DEVICE_TABLE(spi, ti_adc_id);
static struct spi_driver ti_adc_driver = {
.driver = {
.name = TI_ADC_DRV_NAME,
.of_match_table = ti_adc_dt_ids,
},
.probe = ti_adc_probe,
.id_table = ti_adc_id,
};
module_spi_driver(ti_adc_driver);
MODULE_AUTHOR("Matt Ranostay <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments ADC1x1S 1-channel differential ADC");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/adc/ti-adc161s626.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2022 Richtek Technology Corp.
*
* Author: ChiaEn Wu <[email protected]>
*/
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/iio/iio.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/sysfs.h>
#include <linux/units.h>
#include <dt-bindings/iio/adc/mediatek,mt6370_adc.h>
#define MT6370_REG_DEV_INFO 0x100
#define MT6370_REG_CHG_CTRL3 0x113
#define MT6370_REG_CHG_CTRL7 0x117
#define MT6370_REG_CHG_ADC 0x121
#define MT6370_REG_ADC_DATA_H 0x14C
#define MT6370_ADC_START_MASK BIT(0)
#define MT6370_ADC_IN_SEL_MASK GENMASK(7, 4)
#define MT6370_AICR_ICHG_MASK GENMASK(7, 2)
#define MT6370_VENID_MASK GENMASK(7, 4)
#define MT6370_AICR_100_mA 0x0
#define MT6370_AICR_150_mA 0x1
#define MT6370_AICR_200_mA 0x2
#define MT6370_AICR_250_mA 0x3
#define MT6370_AICR_300_mA 0x4
#define MT6370_AICR_350_mA 0x5
#define MT6370_ICHG_100_mA 0x0
#define MT6370_ICHG_200_mA 0x1
#define MT6370_ICHG_300_mA 0x2
#define MT6370_ICHG_400_mA 0x3
#define MT6370_ICHG_500_mA 0x4
#define MT6370_ICHG_600_mA 0x5
#define MT6370_ICHG_700_mA 0x6
#define MT6370_ICHG_800_mA 0x7
#define ADC_CONV_TIME_MS 35
#define ADC_CONV_POLLING_TIME_US 1000
#define MT6370_VID_RT5081 0x8
#define MT6370_VID_RT5081A 0xA
#define MT6370_VID_MT6370 0xE
struct mt6370_adc_data {
struct device *dev;
struct regmap *regmap;
/*
* This mutex lock is for preventing the different ADC channels
* from being read at the same time.
*/
struct mutex adc_lock;
unsigned int vid;
};
static int mt6370_adc_read_channel(struct mt6370_adc_data *priv, int chan,
unsigned long addr, int *val)
{
unsigned int reg_val;
__be16 be_val;
int ret;
mutex_lock(&priv->adc_lock);
reg_val = MT6370_ADC_START_MASK |
FIELD_PREP(MT6370_ADC_IN_SEL_MASK, addr);
ret = regmap_write(priv->regmap, MT6370_REG_CHG_ADC, reg_val);
if (ret)
goto adc_unlock;
msleep(ADC_CONV_TIME_MS);
ret = regmap_read_poll_timeout(priv->regmap,
MT6370_REG_CHG_ADC, reg_val,
!(reg_val & MT6370_ADC_START_MASK),
ADC_CONV_POLLING_TIME_US,
ADC_CONV_TIME_MS * MILLI * 3);
if (ret) {
dev_err(priv->dev, "Failed to read ADC register (%d)\n", ret);
goto adc_unlock;
}
ret = regmap_raw_read(priv->regmap, MT6370_REG_ADC_DATA_H,
&be_val, sizeof(be_val));
if (ret)
goto adc_unlock;
*val = be16_to_cpu(be_val);
ret = IIO_VAL_INT;
adc_unlock:
mutex_unlock(&priv->adc_lock);
return ret;
}
static int mt6370_adc_get_ibus_scale(struct mt6370_adc_data *priv)
{
switch (priv->vid) {
case MT6370_VID_RT5081:
case MT6370_VID_RT5081A:
case MT6370_VID_MT6370:
return 3350;
default:
return 3875;
}
}
static int mt6370_adc_get_ibat_scale(struct mt6370_adc_data *priv)
{
switch (priv->vid) {
case MT6370_VID_RT5081:
case MT6370_VID_RT5081A:
case MT6370_VID_MT6370:
return 2680;
default:
return 3870;
}
}
static int mt6370_adc_read_scale(struct mt6370_adc_data *priv,
int chan, int *val1, int *val2)
{
unsigned int reg_val;
int ret;
switch (chan) {
case MT6370_CHAN_VBAT:
case MT6370_CHAN_VSYS:
case MT6370_CHAN_CHG_VDDP:
*val1 = 5;
return IIO_VAL_INT;
case MT6370_CHAN_IBUS:
ret = regmap_read(priv->regmap, MT6370_REG_CHG_CTRL3, ®_val);
if (ret)
return ret;
reg_val = FIELD_GET(MT6370_AICR_ICHG_MASK, reg_val);
switch (reg_val) {
case MT6370_AICR_100_mA:
case MT6370_AICR_150_mA:
case MT6370_AICR_200_mA:
case MT6370_AICR_250_mA:
case MT6370_AICR_300_mA:
case MT6370_AICR_350_mA:
*val1 = mt6370_adc_get_ibus_scale(priv);
break;
default:
*val1 = 5000;
break;
}
*val2 = 100;
return IIO_VAL_FRACTIONAL;
case MT6370_CHAN_IBAT:
ret = regmap_read(priv->regmap, MT6370_REG_CHG_CTRL7, ®_val);
if (ret)
return ret;
reg_val = FIELD_GET(MT6370_AICR_ICHG_MASK, reg_val);
switch (reg_val) {
case MT6370_ICHG_100_mA:
case MT6370_ICHG_200_mA:
case MT6370_ICHG_300_mA:
case MT6370_ICHG_400_mA:
*val1 = 2375;
break;
case MT6370_ICHG_500_mA:
case MT6370_ICHG_600_mA:
case MT6370_ICHG_700_mA:
case MT6370_ICHG_800_mA:
*val1 = mt6370_adc_get_ibat_scale(priv);
break;
default:
*val1 = 5000;
break;
}
*val2 = 100;
return IIO_VAL_FRACTIONAL;
case MT6370_CHAN_VBUSDIV5:
*val1 = 25;
return IIO_VAL_INT;
case MT6370_CHAN_VBUSDIV2:
*val1 = 10;
return IIO_VAL_INT;
case MT6370_CHAN_TS_BAT:
*val1 = 25;
*val2 = 10000;
return IIO_VAL_FRACTIONAL;
case MT6370_CHAN_TEMP_JC:
*val1 = 2000;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int mt6370_adc_read_offset(struct mt6370_adc_data *priv,
int chan, int *val)
{
*val = -20;
return IIO_VAL_INT;
}
static int mt6370_adc_read_raw(struct iio_dev *iio_dev,
const struct iio_chan_spec *chan,
int *val, int *val2, long mask)
{
struct mt6370_adc_data *priv = iio_priv(iio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
return mt6370_adc_read_channel(priv, chan->channel,
chan->address, val);
case IIO_CHAN_INFO_SCALE:
return mt6370_adc_read_scale(priv, chan->channel, val, val2);
case IIO_CHAN_INFO_OFFSET:
return mt6370_adc_read_offset(priv, chan->channel, val);
default:
return -EINVAL;
}
}
static const char * const mt6370_channel_labels[MT6370_CHAN_MAX] = {
[MT6370_CHAN_VBUSDIV5] = "vbusdiv5",
[MT6370_CHAN_VBUSDIV2] = "vbusdiv2",
[MT6370_CHAN_VSYS] = "vsys",
[MT6370_CHAN_VBAT] = "vbat",
[MT6370_CHAN_TS_BAT] = "ts_bat",
[MT6370_CHAN_IBUS] = "ibus",
[MT6370_CHAN_IBAT] = "ibat",
[MT6370_CHAN_CHG_VDDP] = "chg_vddp",
[MT6370_CHAN_TEMP_JC] = "temp_jc",
};
static int mt6370_adc_read_label(struct iio_dev *iio_dev,
struct iio_chan_spec const *chan, char *label)
{
return sysfs_emit(label, "%s\n", mt6370_channel_labels[chan->channel]);
}
static const struct iio_info mt6370_adc_iio_info = {
.read_raw = mt6370_adc_read_raw,
.read_label = mt6370_adc_read_label,
};
#define MT6370_ADC_CHAN(_idx, _type, _addr, _extra_info) { \
.type = _type, \
.channel = MT6370_CHAN_##_idx, \
.address = _addr, \
.scan_index = MT6370_CHAN_##_idx, \
.indexed = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
_extra_info, \
}
static const struct iio_chan_spec mt6370_adc_channels[] = {
MT6370_ADC_CHAN(VBUSDIV5, IIO_VOLTAGE, 1, 0),
MT6370_ADC_CHAN(VBUSDIV2, IIO_VOLTAGE, 2, 0),
MT6370_ADC_CHAN(VSYS, IIO_VOLTAGE, 3, 0),
MT6370_ADC_CHAN(VBAT, IIO_VOLTAGE, 4, 0),
MT6370_ADC_CHAN(TS_BAT, IIO_VOLTAGE, 6, 0),
MT6370_ADC_CHAN(IBUS, IIO_CURRENT, 8, 0),
MT6370_ADC_CHAN(IBAT, IIO_CURRENT, 9, 0),
MT6370_ADC_CHAN(CHG_VDDP, IIO_VOLTAGE, 11, 0),
MT6370_ADC_CHAN(TEMP_JC, IIO_TEMP, 12, BIT(IIO_CHAN_INFO_OFFSET)),
};
static int mt6370_get_vendor_info(struct mt6370_adc_data *priv)
{
unsigned int dev_info;
int ret;
ret = regmap_read(priv->regmap, MT6370_REG_DEV_INFO, &dev_info);
if (ret)
return ret;
priv->vid = FIELD_GET(MT6370_VENID_MASK, dev_info);
return 0;
}
static int mt6370_adc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mt6370_adc_data *priv;
struct iio_dev *indio_dev;
struct regmap *regmap;
int ret;
regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!regmap)
return dev_err_probe(dev, -ENODEV, "Failed to get regmap\n");
indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
if (!indio_dev)
return -ENOMEM;
priv = iio_priv(indio_dev);
priv->dev = dev;
priv->regmap = regmap;
mutex_init(&priv->adc_lock);
ret = mt6370_get_vendor_info(priv);
if (ret)
return dev_err_probe(dev, ret, "Failed to get vid\n");
ret = regmap_write(priv->regmap, MT6370_REG_CHG_ADC, 0);
if (ret)
return dev_err_probe(dev, ret, "Failed to reset ADC\n");
indio_dev->name = "mt6370-adc";
indio_dev->info = &mt6370_adc_iio_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = mt6370_adc_channels;
indio_dev->num_channels = ARRAY_SIZE(mt6370_adc_channels);
return devm_iio_device_register(dev, indio_dev);
}
static const struct of_device_id mt6370_adc_of_id[] = {
{ .compatible = "mediatek,mt6370-adc", },
{}
};
MODULE_DEVICE_TABLE(of, mt6370_adc_of_id);
static struct platform_driver mt6370_adc_driver = {
.driver = {
.name = "mt6370-adc",
.of_match_table = mt6370_adc_of_id,
},
.probe = mt6370_adc_probe,
};
module_platform_driver(mt6370_adc_driver);
MODULE_AUTHOR("ChiaEn Wu <[email protected]>");
MODULE_DESCRIPTION("MT6370 ADC Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/mt6370-adc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ltc2485.c - Driver for Linear Technology LTC2485 ADC
*
* Copyright (C) 2016 Alison Schofield <[email protected]>
*
* Datasheet: http://cds.linear.com/docs/en/datasheet/2485fd.pdf
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
/* Power-on configuration: rejects both 50/60Hz, operates at 1x speed */
#define LTC2485_CONFIG_DEFAULT 0
struct ltc2485_data {
struct i2c_client *client;
ktime_t time_prev; /* last conversion */
};
static void ltc2485_wait_conv(struct ltc2485_data *data)
{
const unsigned int conv_time = 147; /* conversion time ms */
unsigned int time_elapsed;
/* delay if conversion time not passed since last read or write */
time_elapsed = ktime_ms_delta(ktime_get(), data->time_prev);
if (time_elapsed < conv_time)
msleep(conv_time - time_elapsed);
}
static int ltc2485_read(struct ltc2485_data *data, int *val)
{
struct i2c_client *client = data->client;
__be32 buf = 0;
int ret;
ltc2485_wait_conv(data);
ret = i2c_master_recv(client, (char *)&buf, 4);
if (ret < 0) {
dev_err(&client->dev, "i2c_master_recv failed\n");
return ret;
}
data->time_prev = ktime_get();
*val = sign_extend32(be32_to_cpu(buf) >> 6, 24);
return ret;
}
static int ltc2485_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct ltc2485_data *data = iio_priv(indio_dev);
int ret;
if (mask == IIO_CHAN_INFO_RAW) {
ret = ltc2485_read(data, val);
if (ret < 0)
return ret;
return IIO_VAL_INT;
} else if (mask == IIO_CHAN_INFO_SCALE) {
*val = 5000; /* on board vref millivolts */
*val2 = 25; /* 25 (24 + sign) data bits */
return IIO_VAL_FRACTIONAL_LOG2;
} else {
return -EINVAL;
}
}
static const struct iio_chan_spec ltc2485_channel[] = {
{
.type = IIO_VOLTAGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE)
},
};
static const struct iio_info ltc2485_info = {
.read_raw = ltc2485_read_raw,
};
static int ltc2485_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct iio_dev *indio_dev;
struct ltc2485_data *data;
int ret;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
I2C_FUNC_SMBUS_WRITE_BYTE))
return -EOPNOTSUPP;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
indio_dev->name = id->name;
indio_dev->info = <c2485_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ltc2485_channel;
indio_dev->num_channels = ARRAY_SIZE(ltc2485_channel);
ret = i2c_smbus_write_byte(data->client, LTC2485_CONFIG_DEFAULT);
if (ret < 0)
return ret;
data->time_prev = ktime_get();
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id ltc2485_id[] = {
{ "ltc2485", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ltc2485_id);
static struct i2c_driver ltc2485_driver = {
.driver = {
.name = "ltc2485",
},
.probe = ltc2485_probe,
.id_table = ltc2485_id,
};
module_i2c_driver(ltc2485_driver);
MODULE_AUTHOR("Alison Schofield <[email protected]>");
MODULE_DESCRIPTION("Linear Technology LTC2485 ADC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ltc2485.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI LP8788 MFD - ADC driver
*
* Copyright 2012 Texas Instruments
*
* Author: Milo(Woogyom) Kim <[email protected]>
*/
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/driver.h>
#include <linux/iio/machine.h>
#include <linux/mfd/lp8788.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
/* register address */
#define LP8788_ADC_CONF 0x60
#define LP8788_ADC_RAW 0x61
#define LP8788_ADC_DONE 0x63
#define ADC_CONV_START 1
struct lp8788_adc {
struct lp8788 *lp;
struct iio_map *map;
struct mutex lock;
};
static const int lp8788_scale[LPADC_MAX] = {
[LPADC_VBATT_5P5] = 1343101,
[LPADC_VIN_CHG] = 3052503,
[LPADC_IBATT] = 610500,
[LPADC_IC_TEMP] = 61050,
[LPADC_VBATT_6P0] = 1465201,
[LPADC_VBATT_5P0] = 1221001,
[LPADC_ADC1] = 610500,
[LPADC_ADC2] = 610500,
[LPADC_VDD] = 1025641,
[LPADC_VCOIN] = 757020,
[LPADC_ADC3] = 610500,
[LPADC_ADC4] = 610500,
};
static int lp8788_get_adc_result(struct lp8788_adc *adc, enum lp8788_adc_id id,
int *val)
{
unsigned int msb;
unsigned int lsb;
unsigned int result;
u8 data;
u8 rawdata[2];
int size = ARRAY_SIZE(rawdata);
int retry = 5;
int ret;
data = (id << 1) | ADC_CONV_START;
ret = lp8788_write_byte(adc->lp, LP8788_ADC_CONF, data);
if (ret)
goto err_io;
/* retry until adc conversion is done */
data = 0;
while (retry--) {
usleep_range(100, 200);
ret = lp8788_read_byte(adc->lp, LP8788_ADC_DONE, &data);
if (ret)
goto err_io;
/* conversion done */
if (data)
break;
}
ret = lp8788_read_multi_bytes(adc->lp, LP8788_ADC_RAW, rawdata, size);
if (ret)
goto err_io;
msb = (rawdata[0] << 4) & 0x00000ff0;
lsb = (rawdata[1] >> 4) & 0x0000000f;
result = msb | lsb;
*val = result;
return 0;
err_io:
return ret;
}
static int lp8788_adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct lp8788_adc *adc = iio_priv(indio_dev);
enum lp8788_adc_id id = chan->channel;
int ret;
mutex_lock(&adc->lock);
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = lp8788_get_adc_result(adc, id, val) ? -EIO : IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SCALE:
*val = lp8788_scale[id] / 1000000;
*val2 = lp8788_scale[id] % 1000000;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&adc->lock);
return ret;
}
static const struct iio_info lp8788_adc_info = {
.read_raw = &lp8788_adc_read_raw,
};
#define LP8788_CHAN(_id, _type) { \
.type = _type, \
.indexed = 1, \
.channel = LPADC_##_id, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.datasheet_name = #_id, \
}
static const struct iio_chan_spec lp8788_adc_channels[] = {
[LPADC_VBATT_5P5] = LP8788_CHAN(VBATT_5P5, IIO_VOLTAGE),
[LPADC_VIN_CHG] = LP8788_CHAN(VIN_CHG, IIO_VOLTAGE),
[LPADC_IBATT] = LP8788_CHAN(IBATT, IIO_CURRENT),
[LPADC_IC_TEMP] = LP8788_CHAN(IC_TEMP, IIO_TEMP),
[LPADC_VBATT_6P0] = LP8788_CHAN(VBATT_6P0, IIO_VOLTAGE),
[LPADC_VBATT_5P0] = LP8788_CHAN(VBATT_5P0, IIO_VOLTAGE),
[LPADC_ADC1] = LP8788_CHAN(ADC1, IIO_VOLTAGE),
[LPADC_ADC2] = LP8788_CHAN(ADC2, IIO_VOLTAGE),
[LPADC_VDD] = LP8788_CHAN(VDD, IIO_VOLTAGE),
[LPADC_VCOIN] = LP8788_CHAN(VCOIN, IIO_VOLTAGE),
[LPADC_ADC3] = LP8788_CHAN(ADC3, IIO_VOLTAGE),
[LPADC_ADC4] = LP8788_CHAN(ADC4, IIO_VOLTAGE),
};
/* default maps used by iio consumer (lp8788-charger driver) */
static struct iio_map lp8788_default_iio_maps[] = {
{
.consumer_dev_name = "lp8788-charger",
.consumer_channel = "lp8788_vbatt_5p0",
.adc_channel_label = "VBATT_5P0",
},
{
.consumer_dev_name = "lp8788-charger",
.consumer_channel = "lp8788_adc1",
.adc_channel_label = "ADC1",
},
{ }
};
static int lp8788_iio_map_register(struct device *dev,
struct iio_dev *indio_dev,
struct lp8788_platform_data *pdata,
struct lp8788_adc *adc)
{
struct iio_map *map;
int ret;
map = (!pdata || !pdata->adc_pdata) ?
lp8788_default_iio_maps : pdata->adc_pdata;
ret = devm_iio_map_array_register(dev, indio_dev, map);
if (ret) {
dev_err(&indio_dev->dev, "iio map err: %d\n", ret);
return ret;
}
adc->map = map;
return 0;
}
static int lp8788_adc_probe(struct platform_device *pdev)
{
struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
struct iio_dev *indio_dev;
struct lp8788_adc *adc;
int ret;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
if (!indio_dev)
return -ENOMEM;
adc = iio_priv(indio_dev);
adc->lp = lp;
ret = lp8788_iio_map_register(&pdev->dev, indio_dev, lp->pdata, adc);
if (ret)
return ret;
mutex_init(&adc->lock);
indio_dev->name = pdev->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &lp8788_adc_info;
indio_dev->channels = lp8788_adc_channels;
indio_dev->num_channels = ARRAY_SIZE(lp8788_adc_channels);
return devm_iio_device_register(&pdev->dev, indio_dev);
}
static struct platform_driver lp8788_adc_driver = {
.probe = lp8788_adc_probe,
.driver = {
.name = LP8788_DEV_ADC,
},
};
module_platform_driver(lp8788_adc_driver);
MODULE_DESCRIPTION("Texas Instruments LP8788 ADC Driver");
MODULE_AUTHOR("Milo Kim");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:lp8788-adc");
| linux-master | drivers/iio/adc/lp8788_adc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AD7887 SPI ADC driver
*
* Copyright 2010-2011 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/platform_data/ad7887.h>
#define AD7887_REF_DIS BIT(5) /* on-chip reference disable */
#define AD7887_DUAL BIT(4) /* dual-channel mode */
#define AD7887_CH_AIN1 BIT(3) /* convert on channel 1, DUAL=1 */
#define AD7887_CH_AIN0 0 /* convert on channel 0, DUAL=0,1 */
#define AD7887_PM_MODE1 0 /* CS based shutdown */
#define AD7887_PM_MODE2 1 /* full on */
#define AD7887_PM_MODE3 2 /* auto shutdown after conversion */
#define AD7887_PM_MODE4 3 /* standby mode */
enum ad7887_channels {
AD7887_CH0,
AD7887_CH0_CH1,
AD7887_CH1,
};
/**
* struct ad7887_chip_info - chip specifc information
* @int_vref_mv: the internal reference voltage
* @channels: channels specification
* @num_channels: number of channels
* @dual_channels: channels specification in dual mode
* @num_dual_channels: number of channels in dual mode
*/
struct ad7887_chip_info {
u16 int_vref_mv;
const struct iio_chan_spec *channels;
unsigned int num_channels;
const struct iio_chan_spec *dual_channels;
unsigned int num_dual_channels;
};
struct ad7887_state {
struct spi_device *spi;
const struct ad7887_chip_info *chip_info;
struct regulator *reg;
struct spi_transfer xfer[4];
struct spi_message msg[3];
struct spi_message *ring_msg;
unsigned char tx_cmd_buf[4];
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
* Buffer needs to be large enough to hold two 16 bit samples and a
* 64 bit aligned 64 bit timestamp.
*/
unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN);
};
enum ad7887_supported_device_ids {
ID_AD7887
};
static int ad7887_ring_preenable(struct iio_dev *indio_dev)
{
struct ad7887_state *st = iio_priv(indio_dev);
/* We know this is a single long so can 'cheat' */
switch (*indio_dev->active_scan_mask) {
case (1 << 0):
st->ring_msg = &st->msg[AD7887_CH0];
break;
case (1 << 1):
st->ring_msg = &st->msg[AD7887_CH1];
/* Dummy read: push CH1 setting down to hardware */
spi_sync(st->spi, st->ring_msg);
break;
case ((1 << 1) | (1 << 0)):
st->ring_msg = &st->msg[AD7887_CH0_CH1];
break;
}
return 0;
}
static int ad7887_ring_postdisable(struct iio_dev *indio_dev)
{
struct ad7887_state *st = iio_priv(indio_dev);
/* dummy read: restore default CH0 settin */
return spi_sync(st->spi, &st->msg[AD7887_CH0]);
}
static irqreturn_t ad7887_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct ad7887_state *st = iio_priv(indio_dev);
int b_sent;
b_sent = spi_sync(st->spi, st->ring_msg);
if (b_sent)
goto done;
iio_push_to_buffers_with_timestamp(indio_dev, st->data,
iio_get_time_ns(indio_dev));
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = {
.preenable = &ad7887_ring_preenable,
.postdisable = &ad7887_ring_postdisable,
};
static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch)
{
int ret = spi_sync(st->spi, &st->msg[ch]);
if (ret)
return ret;
return (st->data[(ch * 2)] << 8) | st->data[(ch * 2) + 1];
}
static int ad7887_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
int ret;
struct ad7887_state *st = iio_priv(indio_dev);
switch (m) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = ad7887_scan_direct(st, chan->address);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = ret >> chan->scan_type.shift;
*val &= GENMASK(chan->scan_type.realbits - 1, 0);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
if (st->reg) {
*val = regulator_get_voltage(st->reg);
if (*val < 0)
return *val;
*val /= 1000;
} else {
*val = st->chip_info->int_vref_mv;
}
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
}
return -EINVAL;
}
#define AD7887_CHANNEL(x) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = (x), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.address = (x), \
.scan_index = (x), \
.scan_type = { \
.sign = 'u', \
.realbits = 12, \
.storagebits = 16, \
.shift = 0, \
.endianness = IIO_BE, \
}, \
}
static const struct iio_chan_spec ad7887_channels[] = {
AD7887_CHANNEL(0),
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static const struct iio_chan_spec ad7887_dual_channels[] = {
AD7887_CHANNEL(0),
AD7887_CHANNEL(1),
IIO_CHAN_SOFT_TIMESTAMP(2),
};
static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
/*
* More devices added in future
*/
[ID_AD7887] = {
.channels = ad7887_channels,
.num_channels = ARRAY_SIZE(ad7887_channels),
.dual_channels = ad7887_dual_channels,
.num_dual_channels = ARRAY_SIZE(ad7887_dual_channels),
.int_vref_mv = 2500,
},
};
static const struct iio_info ad7887_info = {
.read_raw = &ad7887_read_raw,
};
static void ad7887_reg_disable(void *data)
{
struct regulator *reg = data;
regulator_disable(reg);
}
static int ad7887_probe(struct spi_device *spi)
{
struct ad7887_platform_data *pdata = spi->dev.platform_data;
struct ad7887_state *st;
struct iio_dev *indio_dev;
uint8_t mode;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (indio_dev == NULL)
return -ENOMEM;
st = iio_priv(indio_dev);
st->reg = devm_regulator_get_optional(&spi->dev, "vref");
if (IS_ERR(st->reg)) {
if (PTR_ERR(st->reg) != -ENODEV)
return PTR_ERR(st->reg);
st->reg = NULL;
}
if (st->reg) {
ret = regulator_enable(st->reg);
if (ret)
return ret;
ret = devm_add_action_or_reset(&spi->dev, ad7887_reg_disable, st->reg);
if (ret)
return ret;
}
st->chip_info =
&ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];
st->spi = spi;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->info = &ad7887_info;
indio_dev->modes = INDIO_DIRECT_MODE;
/* Setup default message */
mode = AD7887_PM_MODE4;
if (!st->reg)
mode |= AD7887_REF_DIS;
if (pdata && pdata->en_dual)
mode |= AD7887_DUAL;
st->tx_cmd_buf[0] = AD7887_CH_AIN0 | mode;
st->xfer[0].rx_buf = &st->data[0];
st->xfer[0].tx_buf = &st->tx_cmd_buf[0];
st->xfer[0].len = 2;
spi_message_init(&st->msg[AD7887_CH0]);
spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]);
if (pdata && pdata->en_dual) {
st->tx_cmd_buf[2] = AD7887_CH_AIN1 | mode;
st->xfer[1].rx_buf = &st->data[0];
st->xfer[1].tx_buf = &st->tx_cmd_buf[2];
st->xfer[1].len = 2;
st->xfer[2].rx_buf = &st->data[2];
st->xfer[2].tx_buf = &st->tx_cmd_buf[0];
st->xfer[2].len = 2;
spi_message_init(&st->msg[AD7887_CH0_CH1]);
spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]);
spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]);
st->xfer[3].rx_buf = &st->data[2];
st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
st->xfer[3].len = 2;
spi_message_init(&st->msg[AD7887_CH1]);
spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);
indio_dev->channels = st->chip_info->dual_channels;
indio_dev->num_channels = st->chip_info->num_dual_channels;
} else {
indio_dev->channels = st->chip_info->channels;
indio_dev->num_channels = st->chip_info->num_channels;
}
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
&iio_pollfunc_store_time,
&ad7887_trigger_handler, &ad7887_ring_setup_ops);
if (ret)
return ret;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id ad7887_id[] = {
{"ad7887", ID_AD7887},
{}
};
MODULE_DEVICE_TABLE(spi, ad7887_id);
static struct spi_driver ad7887_driver = {
.driver = {
.name = "ad7887",
},
.probe = ad7887_probe,
.id_table = ad7887_id,
};
module_spi_driver(ad7887_driver);
MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD7887 ADC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ad7887.c |
// SPDX-License-Identifier: GPL-2.0
/*
* iio/adc/max11100.c
* Maxim max11100 ADC Driver with IIO interface
*
* Copyright (C) 2016-17 Renesas Electronics Corporation
* Copyright (C) 2016-17 Jacopo Mondi
*/
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <asm/unaligned.h>
#include <linux/iio/iio.h>
#include <linux/iio/driver.h>
/*
* LSB is the ADC single digital step
* 1 LSB = (vref_mv / 2 ^ 16)
*
* LSB is used to calculate analog voltage value
* from the number of ADC steps count
*
* Ain = (count * LSB)
*/
#define MAX11100_LSB_DIV (1 << 16)
struct max11100_state {
struct regulator *vref_reg;
struct spi_device *spi;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
u8 buffer[3] __aligned(IIO_DMA_MINALIGN);
};
static const struct iio_chan_spec max11100_channels[] = {
{ /* [0] */
.type = IIO_VOLTAGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
};
static int max11100_read_single(struct iio_dev *indio_dev, int *val)
{
int ret;
struct max11100_state *state = iio_priv(indio_dev);
ret = spi_read(state->spi, state->buffer, sizeof(state->buffer));
if (ret) {
dev_err(&indio_dev->dev, "SPI transfer failed\n");
return ret;
}
/* the first 8 bits sent out from ADC must be 0s */
if (state->buffer[0]) {
dev_err(&indio_dev->dev, "Invalid value: buffer[0] != 0\n");
return -EINVAL;
}
*val = get_unaligned_be16(&state->buffer[1]);
return 0;
}
static int max11100_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
{
int ret, vref_uv;
struct max11100_state *state = iio_priv(indio_dev);
switch (info) {
case IIO_CHAN_INFO_RAW:
ret = max11100_read_single(indio_dev, val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
vref_uv = regulator_get_voltage(state->vref_reg);
if (vref_uv < 0)
/* dummy regulator "get_voltage" returns -EINVAL */
return -EINVAL;
*val = vref_uv / 1000;
*val2 = MAX11100_LSB_DIV;
return IIO_VAL_FRACTIONAL;
}
return -EINVAL;
}
static const struct iio_info max11100_info = {
.read_raw = max11100_read_raw,
};
static void max11100_regulator_disable(void *reg)
{
regulator_disable(reg);
}
static int max11100_probe(struct spi_device *spi)
{
int ret;
struct iio_dev *indio_dev;
struct max11100_state *state;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state));
if (!indio_dev)
return -ENOMEM;
state = iio_priv(indio_dev);
state->spi = spi;
indio_dev->name = "max11100";
indio_dev->info = &max11100_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = max11100_channels;
indio_dev->num_channels = ARRAY_SIZE(max11100_channels);
state->vref_reg = devm_regulator_get(&spi->dev, "vref");
if (IS_ERR(state->vref_reg))
return PTR_ERR(state->vref_reg);
ret = regulator_enable(state->vref_reg);
if (ret)
return ret;
ret = devm_add_action_or_reset(&spi->dev, max11100_regulator_disable,
state->vref_reg);
if (ret)
return ret;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct of_device_id max11100_ids[] = {
{.compatible = "maxim,max11100"},
{ },
};
MODULE_DEVICE_TABLE(of, max11100_ids);
static struct spi_driver max11100_driver = {
.driver = {
.name = "max11100",
.of_match_table = max11100_ids,
},
.probe = max11100_probe,
};
module_spi_driver(max11100_driver);
MODULE_AUTHOR("Jacopo Mondi <[email protected]>");
MODULE_DESCRIPTION("Maxim max11100 ADC Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/max11100.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MAX11410 SPI ADC driver
*
* Copyright 2022 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <asm/unaligned.h>
#include <linux/iio/buffer.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#define MAX11410_REG_CONV_START 0x01
#define MAX11410_CONV_TYPE_SINGLE 0x00
#define MAX11410_CONV_TYPE_CONTINUOUS 0x01
#define MAX11410_REG_CAL_START 0x03
#define MAX11410_CAL_START_SELF 0x00
#define MAX11410_CAL_START_PGA 0x01
#define MAX11410_REG_GPIO_CTRL(ch) ((ch) ? 0x05 : 0x04)
#define MAX11410_GPIO_INTRB 0xC1
#define MAX11410_REG_FILTER 0x08
#define MAX11410_FILTER_RATE_MASK GENMASK(3, 0)
#define MAX11410_FILTER_RATE_MAX 0x0F
#define MAX11410_FILTER_LINEF_MASK GENMASK(5, 4)
#define MAX11410_FILTER_50HZ BIT(5)
#define MAX11410_FILTER_60HZ BIT(4)
#define MAX11410_REG_CTRL 0x09
#define MAX11410_CTRL_REFSEL_MASK GENMASK(2, 0)
#define MAX11410_CTRL_VREFN_BUF_BIT BIT(3)
#define MAX11410_CTRL_VREFP_BUF_BIT BIT(4)
#define MAX11410_CTRL_FORMAT_BIT BIT(5)
#define MAX11410_CTRL_UNIPOLAR_BIT BIT(6)
#define MAX11410_REG_MUX_CTRL0 0x0B
#define MAX11410_REG_PGA 0x0E
#define MAX11410_PGA_GAIN_MASK GENMASK(2, 0)
#define MAX11410_PGA_SIG_PATH_MASK GENMASK(5, 4)
#define MAX11410_PGA_SIG_PATH_BUFFERED 0x00
#define MAX11410_PGA_SIG_PATH_BYPASS 0x01
#define MAX11410_PGA_SIG_PATH_PGA 0x02
#define MAX11410_REG_DATA0 0x30
#define MAX11410_REG_STATUS 0x38
#define MAX11410_STATUS_CONV_READY_BIT BIT(0)
#define MAX11410_STATUS_CAL_READY_BIT BIT(2)
#define MAX11410_REFSEL_AVDD_AGND 0x03
#define MAX11410_REFSEL_MAX 0x06
#define MAX11410_SIG_PATH_MAX 0x02
#define MAX11410_CHANNEL_INDEX_MAX 0x0A
#define MAX11410_AINP_AVDD 0x0A
#define MAX11410_AINN_GND 0x0A
#define MAX11410_CONVERSION_TIMEOUT_MS 2000
#define MAX11410_CALIB_TIMEOUT_MS 2000
#define MAX11410_SCALE_AVAIL_SIZE 8
enum max11410_filter {
MAX11410_FILTER_FIR5060,
MAX11410_FILTER_FIR50,
MAX11410_FILTER_FIR60,
MAX11410_FILTER_SINC4,
};
static const u8 max11410_sampling_len[] = {
[MAX11410_FILTER_FIR5060] = 5,
[MAX11410_FILTER_FIR50] = 6,
[MAX11410_FILTER_FIR60] = 6,
[MAX11410_FILTER_SINC4] = 10,
};
static const int max11410_sampling_rates[4][10][2] = {
[MAX11410_FILTER_FIR5060] = {
{ 1, 100000 },
{ 2, 100000 },
{ 4, 200000 },
{ 8, 400000 },
{ 16, 800000 }
},
[MAX11410_FILTER_FIR50] = {
{ 1, 300000 },
{ 2, 700000 },
{ 5, 300000 },
{ 10, 700000 },
{ 21, 300000 },
{ 40 }
},
[MAX11410_FILTER_FIR60] = {
{ 1, 300000 },
{ 2, 700000 },
{ 5, 300000 },
{ 10, 700000 },
{ 21, 300000 },
{ 40 }
},
[MAX11410_FILTER_SINC4] = {
{ 4 },
{ 10 },
{ 20 },
{ 40 },
{ 60 },
{ 120 },
{ 240 },
{ 480 },
{ 960 },
{ 1920 }
}
};
struct max11410_channel_config {
u32 settling_time_us;
u32 *scale_avail;
u8 refsel;
u8 sig_path;
u8 gain;
bool bipolar;
bool buffered_vrefp;
bool buffered_vrefn;
};
struct max11410_state {
struct spi_device *spi_dev;
struct iio_trigger *trig;
struct completion completion;
struct mutex lock; /* Prevent changing channel config during sampling */
struct regmap *regmap;
struct regulator *avdd;
struct regulator *vrefp[3];
struct regulator *vrefn[3];
struct max11410_channel_config *channels;
int irq;
struct {
u32 data __aligned(IIO_DMA_MINALIGN);
s64 ts __aligned(8);
} scan;
};
static const struct iio_chan_spec chanspec_template = {
.type = IIO_VOLTAGE,
.indexed = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.scan_type = {
.sign = 's',
.realbits = 24,
.storagebits = 32,
.endianness = IIO_LE,
},
};
static unsigned int max11410_reg_size(unsigned int reg)
{
/* Registers from 0x00 to 0x10 are 1 byte, the rest are 3 bytes long. */
return reg <= 0x10 ? 1 : 3;
}
static int max11410_write_reg(struct max11410_state *st, unsigned int reg,
unsigned int val)
{
/* This driver only needs to write 8-bit registers */
if (max11410_reg_size(reg) != 1)
return -EINVAL;
return regmap_write(st->regmap, reg, val);
}
static int max11410_read_reg(struct max11410_state *st, unsigned int reg,
int *val)
{
int ret;
if (max11410_reg_size(reg) == 3) {
ret = regmap_bulk_read(st->regmap, reg, &st->scan.data, 3);
if (ret)
return ret;
*val = get_unaligned_be24(&st->scan.data);
return 0;
}
return regmap_read(st->regmap, reg, val);
}
static struct regulator *max11410_get_vrefp(struct max11410_state *st,
u8 refsel)
{
refsel = refsel % 4;
if (refsel == 3)
return st->avdd;
return st->vrefp[refsel];
}
static struct regulator *max11410_get_vrefn(struct max11410_state *st,
u8 refsel)
{
if (refsel > 2)
return NULL;
return st->vrefn[refsel];
}
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x39,
};
static ssize_t max11410_notch_en_show(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct max11410_state *state = iio_priv(indio_dev);
struct iio_dev_attr *iio_attr = to_iio_dev_attr(devattr);
unsigned int val;
int ret;
ret = max11410_read_reg(state, MAX11410_REG_FILTER, &val);
if (ret)
return ret;
switch (iio_attr->address) {
case 0:
val = !FIELD_GET(MAX11410_FILTER_50HZ, val);
break;
case 1:
val = !FIELD_GET(MAX11410_FILTER_60HZ, val);
break;
case 2:
val = FIELD_GET(MAX11410_FILTER_LINEF_MASK, val) == 3;
break;
default:
return -EINVAL;
}
return sysfs_emit(buf, "%d\n", val);
}
static ssize_t max11410_notch_en_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct iio_dev_attr *iio_attr = to_iio_dev_attr(devattr);
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct max11410_state *state = iio_priv(indio_dev);
unsigned int filter_bits;
bool enable;
int ret;
ret = kstrtobool(buf, &enable);
if (ret)
return ret;
switch (iio_attr->address) {
case 0:
filter_bits = MAX11410_FILTER_50HZ;
break;
case 1:
filter_bits = MAX11410_FILTER_60HZ;
break;
case 2:
default:
filter_bits = MAX11410_FILTER_50HZ | MAX11410_FILTER_60HZ;
enable = !enable;
break;
}
if (enable)
ret = regmap_clear_bits(state->regmap, MAX11410_REG_FILTER,
filter_bits);
else
ret = regmap_set_bits(state->regmap, MAX11410_REG_FILTER,
filter_bits);
if (ret)
return ret;
return count;
}
static ssize_t in_voltage_filter2_notch_center_show(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct max11410_state *state = iio_priv(indio_dev);
int ret, reg, rate, filter;
ret = regmap_read(state->regmap, MAX11410_REG_FILTER, ®);
if (ret)
return ret;
rate = FIELD_GET(MAX11410_FILTER_RATE_MASK, reg);
rate = clamp_val(rate, 0,
max11410_sampling_len[MAX11410_FILTER_SINC4] - 1);
filter = max11410_sampling_rates[MAX11410_FILTER_SINC4][rate][0];
return sysfs_emit(buf, "%d\n", filter);
}
static IIO_CONST_ATTR(in_voltage_filter0_notch_center, "50");
static IIO_CONST_ATTR(in_voltage_filter1_notch_center, "60");
static IIO_DEVICE_ATTR_RO(in_voltage_filter2_notch_center, 2);
static IIO_DEVICE_ATTR(in_voltage_filter0_notch_en, 0644,
max11410_notch_en_show, max11410_notch_en_store, 0);
static IIO_DEVICE_ATTR(in_voltage_filter1_notch_en, 0644,
max11410_notch_en_show, max11410_notch_en_store, 1);
static IIO_DEVICE_ATTR(in_voltage_filter2_notch_en, 0644,
max11410_notch_en_show, max11410_notch_en_store, 2);
static struct attribute *max11410_attributes[] = {
&iio_const_attr_in_voltage_filter0_notch_center.dev_attr.attr,
&iio_const_attr_in_voltage_filter1_notch_center.dev_attr.attr,
&iio_dev_attr_in_voltage_filter2_notch_center.dev_attr.attr,
&iio_dev_attr_in_voltage_filter0_notch_en.dev_attr.attr,
&iio_dev_attr_in_voltage_filter1_notch_en.dev_attr.attr,
&iio_dev_attr_in_voltage_filter2_notch_en.dev_attr.attr,
NULL
};
static const struct attribute_group max11410_attribute_group = {
.attrs = max11410_attributes,
};
static int max11410_set_input_mux(struct max11410_state *st, u8 ainp, u8 ainn)
{
if (ainp > MAX11410_CHANNEL_INDEX_MAX ||
ainn > MAX11410_CHANNEL_INDEX_MAX)
return -EINVAL;
return max11410_write_reg(st, MAX11410_REG_MUX_CTRL0,
(ainp << 4) | ainn);
}
static int max11410_configure_channel(struct max11410_state *st,
struct iio_chan_spec const *chan)
{
struct max11410_channel_config cfg = st->channels[chan->address];
unsigned int regval;
int ret;
if (chan->differential)
ret = max11410_set_input_mux(st, chan->channel, chan->channel2);
else
ret = max11410_set_input_mux(st, chan->channel,
MAX11410_AINN_GND);
if (ret)
return ret;
regval = FIELD_PREP(MAX11410_CTRL_VREFP_BUF_BIT, cfg.buffered_vrefp) |
FIELD_PREP(MAX11410_CTRL_VREFN_BUF_BIT, cfg.buffered_vrefn) |
FIELD_PREP(MAX11410_CTRL_REFSEL_MASK, cfg.refsel) |
FIELD_PREP(MAX11410_CTRL_UNIPOLAR_BIT, cfg.bipolar ? 0 : 1);
ret = regmap_update_bits(st->regmap, MAX11410_REG_CTRL,
MAX11410_CTRL_REFSEL_MASK |
MAX11410_CTRL_VREFP_BUF_BIT |
MAX11410_CTRL_VREFN_BUF_BIT |
MAX11410_CTRL_UNIPOLAR_BIT, regval);
if (ret)
return ret;
regval = FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK, cfg.sig_path) |
FIELD_PREP(MAX11410_PGA_GAIN_MASK, cfg.gain);
ret = regmap_write(st->regmap, MAX11410_REG_PGA, regval);
if (ret)
return ret;
if (cfg.settling_time_us)
fsleep(cfg.settling_time_us);
return 0;
}
static int max11410_sample(struct max11410_state *st, int *sample_raw,
struct iio_chan_spec const *chan)
{
int val, ret;
ret = max11410_configure_channel(st, chan);
if (ret)
return ret;
if (st->irq > 0)
reinit_completion(&st->completion);
/* Start Conversion */
ret = max11410_write_reg(st, MAX11410_REG_CONV_START,
MAX11410_CONV_TYPE_SINGLE);
if (ret)
return ret;
if (st->irq > 0) {
/* Wait for an interrupt. */
ret = wait_for_completion_timeout(&st->completion,
msecs_to_jiffies(MAX11410_CONVERSION_TIMEOUT_MS));
if (!ret)
return -ETIMEDOUT;
} else {
int ret2;
/* Wait for status register Conversion Ready flag */
ret = read_poll_timeout(max11410_read_reg, ret2,
ret2 || (val & MAX11410_STATUS_CONV_READY_BIT),
5000, MAX11410_CONVERSION_TIMEOUT_MS * 1000,
true, st, MAX11410_REG_STATUS, &val);
if (ret)
return ret;
if (ret2)
return ret2;
}
/* Read ADC Data */
return max11410_read_reg(st, MAX11410_REG_DATA0, sample_raw);
}
static int max11410_get_scale(struct max11410_state *state,
struct max11410_channel_config cfg)
{
struct regulator *vrefp, *vrefn;
int scale;
vrefp = max11410_get_vrefp(state, cfg.refsel);
scale = regulator_get_voltage(vrefp) / 1000;
vrefn = max11410_get_vrefn(state, cfg.refsel);
if (vrefn)
scale -= regulator_get_voltage(vrefn) / 1000;
if (cfg.bipolar)
scale *= 2;
return scale >> cfg.gain;
}
static int max11410_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
{
struct max11410_state *state = iio_priv(indio_dev);
struct max11410_channel_config cfg = state->channels[chan->address];
int ret, reg_val, filter, rate;
switch (info) {
case IIO_CHAN_INFO_SCALE:
*val = max11410_get_scale(state, cfg);
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_OFFSET:
if (cfg.bipolar)
*val = -BIT(chan->scan_type.realbits - 1);
else
*val = 0;
return IIO_VAL_INT;
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
mutex_lock(&state->lock);
ret = max11410_sample(state, ®_val, chan);
mutex_unlock(&state->lock);
iio_device_release_direct_mode(indio_dev);
if (ret)
return ret;
*val = reg_val;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SAMP_FREQ:
ret = regmap_read(state->regmap, MAX11410_REG_FILTER, ®_val);
if (ret)
return ret;
filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val);
rate = reg_val & MAX11410_FILTER_RATE_MASK;
if (rate >= max11410_sampling_len[filter])
rate = max11410_sampling_len[filter] - 1;
*val = max11410_sampling_rates[filter][rate][0];
*val2 = max11410_sampling_rates[filter][rate][1];
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
}
static int max11410_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct max11410_state *st = iio_priv(indio_dev);
int i, ret, reg_val, filter, gain;
u32 *scale_avail;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
scale_avail = st->channels[chan->address].scale_avail;
if (!scale_avail)
return -EOPNOTSUPP;
/* Accept values in range 0.000001 <= scale < 1.000000 */
if (val != 0 || val2 == 0)
return -EINVAL;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
/* Convert from INT_PLUS_MICRO to FRACTIONAL_LOG2 */
val2 = val2 * DIV_ROUND_CLOSEST(BIT(24), 1000000);
val2 = DIV_ROUND_CLOSEST(scale_avail[0], val2);
gain = order_base_2(val2);
st->channels[chan->address].gain = clamp_val(gain, 0, 7);
iio_device_release_direct_mode(indio_dev);
return 0;
case IIO_CHAN_INFO_SAMP_FREQ:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
mutex_lock(&st->lock);
ret = regmap_read(st->regmap, MAX11410_REG_FILTER, ®_val);
if (ret)
goto out;
filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val);
for (i = 0; i < max11410_sampling_len[filter]; ++i) {
if (val == max11410_sampling_rates[filter][i][0] &&
val2 == max11410_sampling_rates[filter][i][1])
break;
}
if (i == max11410_sampling_len[filter]) {
ret = -EINVAL;
goto out;
}
ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER,
MAX11410_FILTER_RATE_MASK, i);
out:
mutex_unlock(&st->lock);
iio_device_release_direct_mode(indio_dev);
return ret;
default:
return -EINVAL;
}
}
static int max11410_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long info)
{
struct max11410_state *st = iio_priv(indio_dev);
struct max11410_channel_config cfg;
int ret, reg_val, filter;
switch (info) {
case IIO_CHAN_INFO_SAMP_FREQ:
ret = regmap_read(st->regmap, MAX11410_REG_FILTER, ®_val);
if (ret)
return ret;
filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val);
*vals = (const int *)max11410_sampling_rates[filter];
*length = max11410_sampling_len[filter] * 2;
*type = IIO_VAL_INT_PLUS_MICRO;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_SCALE:
cfg = st->channels[chan->address];
if (!cfg.scale_avail)
return -EINVAL;
*vals = cfg.scale_avail;
*length = MAX11410_SCALE_AVAIL_SIZE * 2;
*type = IIO_VAL_FRACTIONAL_LOG2;
return IIO_AVAIL_LIST;
}
return -EINVAL;
}
static const struct iio_info max11410_info = {
.read_raw = max11410_read_raw,
.write_raw = max11410_write_raw,
.read_avail = max11410_read_avail,
.attrs = &max11410_attribute_group,
};
static irqreturn_t max11410_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct max11410_state *st = iio_priv(indio_dev);
int ret;
ret = max11410_read_reg(st, MAX11410_REG_DATA0, &st->scan.data);
if (ret) {
dev_err(&indio_dev->dev, "cannot read data\n");
goto out;
}
iio_push_to_buffers_with_timestamp(indio_dev, &st->scan,
iio_get_time_ns(indio_dev));
out:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int max11410_buffer_postenable(struct iio_dev *indio_dev)
{
struct max11410_state *st = iio_priv(indio_dev);
int scan_ch, ret;
scan_ch = ffs(*indio_dev->active_scan_mask) - 1;
ret = max11410_configure_channel(st, &indio_dev->channels[scan_ch]);
if (ret)
return ret;
/* Start continuous conversion. */
return max11410_write_reg(st, MAX11410_REG_CONV_START,
MAX11410_CONV_TYPE_CONTINUOUS);
}
static int max11410_buffer_predisable(struct iio_dev *indio_dev)
{
struct max11410_state *st = iio_priv(indio_dev);
/* Stop continuous conversion. */
return max11410_write_reg(st, MAX11410_REG_CONV_START,
MAX11410_CONV_TYPE_SINGLE);
}
static const struct iio_buffer_setup_ops max11410_buffer_ops = {
.postenable = &max11410_buffer_postenable,
.predisable = &max11410_buffer_predisable,
.validate_scan_mask = &iio_validate_scan_mask_onehot,
};
static const struct iio_trigger_ops max11410_trigger_ops = {
.validate_device = iio_trigger_validate_own_device,
};
static irqreturn_t max11410_interrupt(int irq, void *dev_id)
{
struct iio_dev *indio_dev = dev_id;
struct max11410_state *st = iio_priv(indio_dev);
if (iio_buffer_enabled(indio_dev))
iio_trigger_poll_nested(st->trig);
else
complete(&st->completion);
return IRQ_HANDLED;
};
static int max11410_parse_channels(struct max11410_state *st,
struct iio_dev *indio_dev)
{
struct iio_chan_spec chanspec = chanspec_template;
struct device *dev = &st->spi_dev->dev;
struct max11410_channel_config *cfg;
struct iio_chan_spec *channels;
struct fwnode_handle *child;
u32 reference, sig_path;
const char *node_name;
u32 inputs[2], scale;
unsigned int num_ch;
int chan_idx = 0;
int ret, i;
num_ch = device_get_child_node_count(dev);
if (num_ch == 0)
return dev_err_probe(&indio_dev->dev, -ENODEV,
"FW has no channels defined\n");
/* Reserve space for soft timestamp channel */
num_ch++;
channels = devm_kcalloc(dev, num_ch, sizeof(*channels), GFP_KERNEL);
if (!channels)
return -ENOMEM;
st->channels = devm_kcalloc(dev, num_ch, sizeof(*st->channels),
GFP_KERNEL);
if (!st->channels)
return -ENOMEM;
device_for_each_child_node(dev, child) {
node_name = fwnode_get_name(child);
if (fwnode_property_present(child, "diff-channels")) {
ret = fwnode_property_read_u32_array(child,
"diff-channels",
inputs,
ARRAY_SIZE(inputs));
chanspec.differential = 1;
} else {
ret = fwnode_property_read_u32(child, "reg", &inputs[0]);
inputs[1] = 0;
chanspec.differential = 0;
}
if (ret) {
fwnode_handle_put(child);
return ret;
}
if (inputs[0] > MAX11410_CHANNEL_INDEX_MAX ||
inputs[1] > MAX11410_CHANNEL_INDEX_MAX) {
fwnode_handle_put(child);
return dev_err_probe(&indio_dev->dev, -EINVAL,
"Invalid channel index for %s, should be less than %d\n",
node_name,
MAX11410_CHANNEL_INDEX_MAX + 1);
}
cfg = &st->channels[chan_idx];
reference = MAX11410_REFSEL_AVDD_AGND;
fwnode_property_read_u32(child, "adi,reference", &reference);
if (reference > MAX11410_REFSEL_MAX) {
fwnode_handle_put(child);
return dev_err_probe(&indio_dev->dev, -EINVAL,
"Invalid adi,reference value for %s, should be less than %d.\n",
node_name, MAX11410_REFSEL_MAX + 1);
}
if (!max11410_get_vrefp(st, reference) ||
(!max11410_get_vrefn(st, reference) && reference <= 2)) {
fwnode_handle_put(child);
return dev_err_probe(&indio_dev->dev, -EINVAL,
"Invalid VREF configuration for %s, either specify corresponding VREF regulators or change adi,reference property.\n",
node_name);
}
sig_path = MAX11410_PGA_SIG_PATH_BUFFERED;
fwnode_property_read_u32(child, "adi,input-mode", &sig_path);
if (sig_path > MAX11410_SIG_PATH_MAX) {
fwnode_handle_put(child);
return dev_err_probe(&indio_dev->dev, -EINVAL,
"Invalid adi,input-mode value for %s, should be less than %d.\n",
node_name, MAX11410_SIG_PATH_MAX + 1);
}
fwnode_property_read_u32(child, "settling-time-us",
&cfg->settling_time_us);
cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
cfg->buffered_vrefp = fwnode_property_read_bool(child, "adi,buffered-vrefp");
cfg->buffered_vrefn = fwnode_property_read_bool(child, "adi,buffered-vrefn");
cfg->refsel = reference;
cfg->sig_path = sig_path;
cfg->gain = 0;
/* Enable scale_available property if input mode is PGA */
if (sig_path == MAX11410_PGA_SIG_PATH_PGA) {
__set_bit(IIO_CHAN_INFO_SCALE,
&chanspec.info_mask_separate_available);
cfg->scale_avail = devm_kcalloc(dev, MAX11410_SCALE_AVAIL_SIZE * 2,
sizeof(*cfg->scale_avail),
GFP_KERNEL);
if (!cfg->scale_avail) {
fwnode_handle_put(child);
return -ENOMEM;
}
scale = max11410_get_scale(st, *cfg);
for (i = 0; i < MAX11410_SCALE_AVAIL_SIZE; i++) {
cfg->scale_avail[2 * i] = scale >> i;
cfg->scale_avail[2 * i + 1] = chanspec.scan_type.realbits;
}
} else {
__clear_bit(IIO_CHAN_INFO_SCALE,
&chanspec.info_mask_separate_available);
}
chanspec.address = chan_idx;
chanspec.scan_index = chan_idx;
chanspec.channel = inputs[0];
chanspec.channel2 = inputs[1];
channels[chan_idx] = chanspec;
chan_idx++;
}
channels[chan_idx] = (struct iio_chan_spec)IIO_CHAN_SOFT_TIMESTAMP(chan_idx);
indio_dev->num_channels = chan_idx + 1;
indio_dev->channels = channels;
return 0;
}
static void max11410_disable_reg(void *reg)
{
regulator_disable(reg);
}
static int max11410_init_vref(struct device *dev,
struct regulator **vref,
const char *id)
{
struct regulator *reg;
int ret;
reg = devm_regulator_get_optional(dev, id);
if (PTR_ERR(reg) == -ENODEV) {
*vref = NULL;
return 0;
} else if (IS_ERR(reg)) {
return PTR_ERR(reg);
}
ret = regulator_enable(reg);
if (ret)
return dev_err_probe(dev, ret,
"Failed to enable regulator %s\n", id);
*vref = reg;
return devm_add_action_or_reset(dev, max11410_disable_reg, reg);
}
static int max11410_calibrate(struct max11410_state *st, u32 cal_type)
{
int ret, ret2, val;
ret = max11410_write_reg(st, MAX11410_REG_CAL_START, cal_type);
if (ret)
return ret;
/* Wait for status register Calibration Ready flag */
ret = read_poll_timeout(max11410_read_reg, ret2,
ret2 || (val & MAX11410_STATUS_CAL_READY_BIT),
50000, MAX11410_CALIB_TIMEOUT_MS * 1000, true,
st, MAX11410_REG_STATUS, &val);
if (ret)
return ret;
return ret2;
}
static int max11410_self_calibrate(struct max11410_state *st)
{
int ret, i;
ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER,
MAX11410_FILTER_RATE_MASK,
FIELD_PREP(MAX11410_FILTER_RATE_MASK,
MAX11410_FILTER_RATE_MAX));
if (ret)
return ret;
ret = max11410_calibrate(st, MAX11410_CAL_START_SELF);
if (ret)
return ret;
ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA,
MAX11410_PGA_SIG_PATH_MASK,
FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK,
MAX11410_PGA_SIG_PATH_PGA));
if (ret)
return ret;
/* PGA calibrations */
for (i = 1; i < 8; ++i) {
ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA,
MAX11410_PGA_GAIN_MASK, i);
if (ret)
return ret;
ret = max11410_calibrate(st, MAX11410_CAL_START_PGA);
if (ret)
return ret;
}
/* Cleanup */
ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA,
MAX11410_PGA_GAIN_MASK, 0);
if (ret)
return ret;
ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER,
MAX11410_FILTER_RATE_MASK, 0);
if (ret)
return ret;
return regmap_write_bits(st->regmap, MAX11410_REG_PGA,
MAX11410_PGA_SIG_PATH_MASK,
FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK,
MAX11410_PGA_SIG_PATH_BUFFERED));
}
static int max11410_probe(struct spi_device *spi)
{
const char *vrefp_regs[] = { "vref0p", "vref1p", "vref2p" };
const char *vrefn_regs[] = { "vref0n", "vref1n", "vref2n" };
struct device *dev = &spi->dev;
struct max11410_state *st;
struct iio_dev *indio_dev;
int ret, irqs[2];
int i;
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->spi_dev = spi;
init_completion(&st->completion);
mutex_init(&st->lock);
indio_dev->name = "max11410";
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &max11410_info;
st->regmap = devm_regmap_init_spi(spi, ®map_config);
if (IS_ERR(st->regmap))
return dev_err_probe(dev, PTR_ERR(st->regmap),
"regmap initialization failed\n");
ret = max11410_init_vref(dev, &st->avdd, "avdd");
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(vrefp_regs); i++) {
ret = max11410_init_vref(dev, &st->vrefp[i], vrefp_regs[i]);
if (ret)
return ret;
ret = max11410_init_vref(dev, &st->vrefn[i], vrefn_regs[i]);
if (ret)
return ret;
}
/*
* Regulators must be configured before parsing channels for
* validating "adi,reference" property of each channel.
*/
ret = max11410_parse_channels(st, indio_dev);
if (ret)
return ret;
irqs[0] = fwnode_irq_get_byname(dev_fwnode(dev), "gpio0");
irqs[1] = fwnode_irq_get_byname(dev_fwnode(dev), "gpio1");
if (irqs[0] > 0) {
st->irq = irqs[0];
ret = regmap_write(st->regmap, MAX11410_REG_GPIO_CTRL(0),
MAX11410_GPIO_INTRB);
} else if (irqs[1] > 0) {
st->irq = irqs[1];
ret = regmap_write(st->regmap, MAX11410_REG_GPIO_CTRL(1),
MAX11410_GPIO_INTRB);
} else if (spi->irq > 0) {
return dev_err_probe(dev, -ENODEV,
"no interrupt name specified");
}
if (ret)
return ret;
ret = regmap_set_bits(st->regmap, MAX11410_REG_CTRL,
MAX11410_CTRL_FORMAT_BIT);
if (ret)
return ret;
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
&max11410_trigger_handler,
&max11410_buffer_ops);
if (ret)
return ret;
if (st->irq > 0) {
st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
indio_dev->name,
iio_device_id(indio_dev));
if (!st->trig)
return -ENOMEM;
st->trig->ops = &max11410_trigger_ops;
ret = devm_iio_trigger_register(dev, st->trig);
if (ret)
return ret;
ret = devm_request_threaded_irq(dev, st->irq, NULL,
&max11410_interrupt,
IRQF_ONESHOT, "max11410",
indio_dev);
if (ret)
return ret;
}
ret = max11410_self_calibrate(st);
if (ret)
return dev_err_probe(dev, ret,
"cannot perform device self calibration\n");
return devm_iio_device_register(dev, indio_dev);
}
static const struct of_device_id max11410_spi_of_id[] = {
{ .compatible = "adi,max11410" },
{ }
};
MODULE_DEVICE_TABLE(of, max11410_spi_of_id);
static const struct spi_device_id max11410_id[] = {
{ "max11410" },
{ }
};
MODULE_DEVICE_TABLE(spi, max11410_id);
static struct spi_driver max11410_driver = {
.driver = {
.name = "max11410",
.of_match_table = max11410_spi_of_id,
},
.probe = max11410_probe,
.id_table = max11410_id,
};
module_spi_driver(max11410_driver);
MODULE_AUTHOR("David Jung <[email protected]>");
MODULE_AUTHOR("Ibrahim Tilki <[email protected]>");
MODULE_DESCRIPTION("Analog Devices MAX11410 ADC");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/adc/max11410.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ltc2497-core.c - Common code for Analog Devices/Linear Technology
* LTC2496 and LTC2497 ADCs
*
* Copyright (C) 2017 Analog Devices Inc.
*/
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/driver.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/regulator/consumer.h>
#include "ltc2497.h"
#define LTC2497_SGL BIT(4)
#define LTC2497_DIFF 0
#define LTC2497_SIGN BIT(3)
static int ltc2497core_wait_conv(struct ltc2497core_driverdata *ddata)
{
s64 time_elapsed;
time_elapsed = ktime_ms_delta(ktime_get(), ddata->time_prev);
if (time_elapsed < LTC2497_CONVERSION_TIME_MS) {
/* delay if conversion time not passed
* since last read or write
*/
if (msleep_interruptible(
LTC2497_CONVERSION_TIME_MS - time_elapsed))
return -ERESTARTSYS;
return 0;
}
if (time_elapsed - LTC2497_CONVERSION_TIME_MS <= 0) {
/* We're in automatic mode -
* so the last reading is still not outdated
*/
return 0;
}
return 1;
}
static int ltc2497core_read(struct ltc2497core_driverdata *ddata, u8 address, int *val)
{
int ret;
ret = ltc2497core_wait_conv(ddata);
if (ret < 0)
return ret;
if (ret || ddata->addr_prev != address) {
ret = ddata->result_and_measure(ddata, address, NULL);
if (ret < 0)
return ret;
ddata->addr_prev = address;
if (msleep_interruptible(LTC2497_CONVERSION_TIME_MS))
return -ERESTARTSYS;
}
ret = ddata->result_and_measure(ddata, address, val);
if (ret < 0)
return ret;
ddata->time_prev = ktime_get();
return ret;
}
static int ltc2497core_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct ltc2497core_driverdata *ddata = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&ddata->lock);
ret = ltc2497core_read(ddata, chan->address, val);
mutex_unlock(&ddata->lock);
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = regulator_get_voltage(ddata->ref);
if (ret < 0)
return ret;
*val = ret / 1000;
*val2 = ddata->chip_info->resolution + 1;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
}
#define LTC2497_CHAN(_chan, _addr, _ds_name) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = (_chan), \
.address = (_addr | (_chan / 2) | ((_chan & 1) ? LTC2497_SIGN : 0)), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.datasheet_name = (_ds_name), \
}
#define LTC2497_CHAN_DIFF(_chan, _addr) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 1 : 0), \
.channel2 = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 0 : 1),\
.address = (_addr | _chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.differential = 1, \
}
static const struct iio_chan_spec ltc2497core_channel[] = {
LTC2497_CHAN(0, LTC2497_SGL, "CH0"),
LTC2497_CHAN(1, LTC2497_SGL, "CH1"),
LTC2497_CHAN(2, LTC2497_SGL, "CH2"),
LTC2497_CHAN(3, LTC2497_SGL, "CH3"),
LTC2497_CHAN(4, LTC2497_SGL, "CH4"),
LTC2497_CHAN(5, LTC2497_SGL, "CH5"),
LTC2497_CHAN(6, LTC2497_SGL, "CH6"),
LTC2497_CHAN(7, LTC2497_SGL, "CH7"),
LTC2497_CHAN(8, LTC2497_SGL, "CH8"),
LTC2497_CHAN(9, LTC2497_SGL, "CH9"),
LTC2497_CHAN(10, LTC2497_SGL, "CH10"),
LTC2497_CHAN(11, LTC2497_SGL, "CH11"),
LTC2497_CHAN(12, LTC2497_SGL, "CH12"),
LTC2497_CHAN(13, LTC2497_SGL, "CH13"),
LTC2497_CHAN(14, LTC2497_SGL, "CH14"),
LTC2497_CHAN(15, LTC2497_SGL, "CH15"),
LTC2497_CHAN_DIFF(0, LTC2497_DIFF),
LTC2497_CHAN_DIFF(1, LTC2497_DIFF),
LTC2497_CHAN_DIFF(2, LTC2497_DIFF),
LTC2497_CHAN_DIFF(3, LTC2497_DIFF),
LTC2497_CHAN_DIFF(4, LTC2497_DIFF),
LTC2497_CHAN_DIFF(5, LTC2497_DIFF),
LTC2497_CHAN_DIFF(6, LTC2497_DIFF),
LTC2497_CHAN_DIFF(7, LTC2497_DIFF),
LTC2497_CHAN_DIFF(0, LTC2497_DIFF | LTC2497_SIGN),
LTC2497_CHAN_DIFF(1, LTC2497_DIFF | LTC2497_SIGN),
LTC2497_CHAN_DIFF(2, LTC2497_DIFF | LTC2497_SIGN),
LTC2497_CHAN_DIFF(3, LTC2497_DIFF | LTC2497_SIGN),
LTC2497_CHAN_DIFF(4, LTC2497_DIFF | LTC2497_SIGN),
LTC2497_CHAN_DIFF(5, LTC2497_DIFF | LTC2497_SIGN),
LTC2497_CHAN_DIFF(6, LTC2497_DIFF | LTC2497_SIGN),
LTC2497_CHAN_DIFF(7, LTC2497_DIFF | LTC2497_SIGN),
};
static const struct iio_info ltc2497core_info = {
.read_raw = ltc2497core_read_raw,
};
int ltc2497core_probe(struct device *dev, struct iio_dev *indio_dev)
{
struct ltc2497core_driverdata *ddata = iio_priv(indio_dev);
int ret;
/*
* Keep using dev_name() for the iio_dev's name on some of the parts,
* since updating it would result in a ABI breakage.
*/
if (ddata->chip_info->name)
indio_dev->name = ddata->chip_info->name;
else
indio_dev->name = dev_name(dev);
indio_dev->info = <c2497core_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ltc2497core_channel;
indio_dev->num_channels = ARRAY_SIZE(ltc2497core_channel);
ret = ddata->result_and_measure(ddata, LTC2497_CONFIG_DEFAULT, NULL);
if (ret < 0)
return ret;
ddata->ref = devm_regulator_get(dev, "vref");
if (IS_ERR(ddata->ref))
return dev_err_probe(dev, PTR_ERR(ddata->ref),
"Failed to get vref regulator\n");
ret = regulator_enable(ddata->ref);
if (ret < 0) {
dev_err(dev, "Failed to enable vref regulator: %pe\n",
ERR_PTR(ret));
return ret;
}
if (dev->platform_data) {
struct iio_map *plat_data;
plat_data = (struct iio_map *)dev->platform_data;
ret = iio_map_array_register(indio_dev, plat_data);
if (ret) {
dev_err(&indio_dev->dev, "iio map err: %d\n", ret);
goto err_regulator_disable;
}
}
ddata->addr_prev = LTC2497_CONFIG_DEFAULT;
ddata->time_prev = ktime_get();
mutex_init(&ddata->lock);
ret = iio_device_register(indio_dev);
if (ret < 0)
goto err_array_unregister;
return 0;
err_array_unregister:
iio_map_array_unregister(indio_dev);
err_regulator_disable:
regulator_disable(ddata->ref);
return ret;
}
EXPORT_SYMBOL_NS(ltc2497core_probe, LTC2497);
void ltc2497core_remove(struct iio_dev *indio_dev)
{
struct ltc2497core_driverdata *ddata = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
iio_map_array_unregister(indio_dev);
regulator_disable(ddata->ref);
}
EXPORT_SYMBOL_NS(ltc2497core_remove, LTC2497);
MODULE_DESCRIPTION("common code for LTC2496/LTC2497 drivers");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ltc2497-core.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices AD7768-1 SPI ADC driver
*
* Copyright 2017 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
/* AD7768 registers definition */
#define AD7768_REG_CHIP_TYPE 0x3
#define AD7768_REG_PROD_ID_L 0x4
#define AD7768_REG_PROD_ID_H 0x5
#define AD7768_REG_CHIP_GRADE 0x6
#define AD7768_REG_SCRATCH_PAD 0x0A
#define AD7768_REG_VENDOR_L 0x0C
#define AD7768_REG_VENDOR_H 0x0D
#define AD7768_REG_INTERFACE_FORMAT 0x14
#define AD7768_REG_POWER_CLOCK 0x15
#define AD7768_REG_ANALOG 0x16
#define AD7768_REG_ANALOG2 0x17
#define AD7768_REG_CONVERSION 0x18
#define AD7768_REG_DIGITAL_FILTER 0x19
#define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A
#define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B
#define AD7768_REG_DUTY_CYCLE_RATIO 0x1C
#define AD7768_REG_SYNC_RESET 0x1D
#define AD7768_REG_GPIO_CONTROL 0x1E
#define AD7768_REG_GPIO_WRITE 0x1F
#define AD7768_REG_GPIO_READ 0x20
#define AD7768_REG_OFFSET_HI 0x21
#define AD7768_REG_OFFSET_MID 0x22
#define AD7768_REG_OFFSET_LO 0x23
#define AD7768_REG_GAIN_HI 0x24
#define AD7768_REG_GAIN_MID 0x25
#define AD7768_REG_GAIN_LO 0x26
#define AD7768_REG_SPI_DIAG_ENABLE 0x28
#define AD7768_REG_ADC_DIAG_ENABLE 0x29
#define AD7768_REG_DIG_DIAG_ENABLE 0x2A
#define AD7768_REG_ADC_DATA 0x2C
#define AD7768_REG_MASTER_STATUS 0x2D
#define AD7768_REG_SPI_DIAG_STATUS 0x2E
#define AD7768_REG_ADC_DIAG_STATUS 0x2F
#define AD7768_REG_DIG_DIAG_STATUS 0x30
#define AD7768_REG_MCLK_COUNTER 0x31
/* AD7768_REG_POWER_CLOCK */
#define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4)
#define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x)
#define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0)
#define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x)
/* AD7768_REG_DIGITAL_FILTER */
#define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4)
#define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x)
#define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0)
#define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x)
/* AD7768_REG_CONVERSION */
#define AD7768_CONV_MODE_MSK GENMASK(2, 0)
#define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x)
#define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F))
#define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F)
enum ad7768_conv_mode {
AD7768_CONTINUOUS,
AD7768_ONE_SHOT,
AD7768_SINGLE,
AD7768_PERIODIC,
AD7768_STANDBY
};
enum ad7768_pwrmode {
AD7768_ECO_MODE = 0,
AD7768_MED_MODE = 2,
AD7768_FAST_MODE = 3
};
enum ad7768_mclk_div {
AD7768_MCLK_DIV_16,
AD7768_MCLK_DIV_8,
AD7768_MCLK_DIV_4,
AD7768_MCLK_DIV_2
};
enum ad7768_dec_rate {
AD7768_DEC_RATE_32 = 0,
AD7768_DEC_RATE_64 = 1,
AD7768_DEC_RATE_128 = 2,
AD7768_DEC_RATE_256 = 3,
AD7768_DEC_RATE_512 = 4,
AD7768_DEC_RATE_1024 = 5,
AD7768_DEC_RATE_8 = 9,
AD7768_DEC_RATE_16 = 10
};
struct ad7768_clk_configuration {
enum ad7768_mclk_div mclk_div;
enum ad7768_dec_rate dec_rate;
unsigned int clk_div;
enum ad7768_pwrmode pwrmode;
};
static const struct ad7768_clk_configuration ad7768_clk_config[] = {
{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE },
{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE },
{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE },
{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE },
{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE },
{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE },
{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE },
{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE },
{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE },
{ AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE },
{ AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE },
};
static const struct iio_chan_spec ad7768_channels[] = {
{
.type = IIO_VOLTAGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.indexed = 1,
.channel = 0,
.scan_index = 0,
.scan_type = {
.sign = 'u',
.realbits = 24,
.storagebits = 32,
.shift = 8,
.endianness = IIO_BE,
},
},
};
struct ad7768_state {
struct spi_device *spi;
struct regulator *vref;
struct mutex lock;
struct clk *mclk;
unsigned int mclk_freq;
unsigned int samp_freq;
struct completion completion;
struct iio_trigger *trig;
struct gpio_desc *gpio_sync_in;
const char *labels[ARRAY_SIZE(ad7768_channels)];
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
union {
struct {
__be32 chan;
s64 timestamp;
} scan;
__be32 d32;
u8 d8[2];
} data __aligned(IIO_DMA_MINALIGN);
};
static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr,
unsigned int len)
{
unsigned int shift;
int ret;
shift = 32 - (8 * len);
st->data.d8[0] = AD7768_RD_FLAG_MSK(addr);
ret = spi_write_then_read(st->spi, st->data.d8, 1,
&st->data.d32, len);
if (ret < 0)
return ret;
return (be32_to_cpu(st->data.d32) >> shift);
}
static int ad7768_spi_reg_write(struct ad7768_state *st,
unsigned int addr,
unsigned int val)
{
st->data.d8[0] = AD7768_WR_FLAG_MSK(addr);
st->data.d8[1] = val & 0xFF;
return spi_write(st->spi, st->data.d8, 2);
}
static int ad7768_set_mode(struct ad7768_state *st,
enum ad7768_conv_mode mode)
{
int regval;
regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1);
if (regval < 0)
return regval;
regval &= ~AD7768_CONV_MODE_MSK;
regval |= AD7768_CONV_MODE(mode);
return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval);
}
static int ad7768_scan_direct(struct iio_dev *indio_dev)
{
struct ad7768_state *st = iio_priv(indio_dev);
int readval, ret;
reinit_completion(&st->completion);
ret = ad7768_set_mode(st, AD7768_ONE_SHOT);
if (ret < 0)
return ret;
ret = wait_for_completion_timeout(&st->completion,
msecs_to_jiffies(1000));
if (!ret)
return -ETIMEDOUT;
readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
if (readval < 0)
return readval;
/*
* Any SPI configuration of the AD7768-1 can only be
* performed in continuous conversion mode.
*/
ret = ad7768_set_mode(st, AD7768_CONTINUOUS);
if (ret < 0)
return ret;
return readval;
}
static int ad7768_reg_access(struct iio_dev *indio_dev,
unsigned int reg,
unsigned int writeval,
unsigned int *readval)
{
struct ad7768_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
if (readval) {
ret = ad7768_spi_reg_read(st, reg, 1);
if (ret < 0)
goto err_unlock;
*readval = ret;
ret = 0;
} else {
ret = ad7768_spi_reg_write(st, reg, writeval);
}
err_unlock:
mutex_unlock(&st->lock);
return ret;
}
static int ad7768_set_dig_fil(struct ad7768_state *st,
enum ad7768_dec_rate dec_rate)
{
unsigned int mode;
int ret;
if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16)
mode = AD7768_DIG_FIL_FIL(dec_rate);
else
mode = AD7768_DIG_FIL_DEC_RATE(dec_rate);
ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode);
if (ret < 0)
return ret;
/* A sync-in pulse is required every time the filter dec rate changes */
gpiod_set_value(st->gpio_sync_in, 1);
gpiod_set_value(st->gpio_sync_in, 0);
return 0;
}
static int ad7768_set_freq(struct ad7768_state *st,
unsigned int freq)
{
unsigned int diff_new, diff_old, pwr_mode, i, idx;
int res, ret;
diff_old = U32_MAX;
idx = 0;
res = DIV_ROUND_CLOSEST(st->mclk_freq, freq);
/* Find the closest match for the desired sampling frequency */
for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
diff_new = abs(res - ad7768_clk_config[i].clk_div);
if (diff_new < diff_old) {
diff_old = diff_new;
idx = i;
}
}
/*
* Set both the mclk_div and pwrmode with a single write to the
* POWER_CLOCK register
*/
pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) |
AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode);
ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode);
if (ret < 0)
return ret;
ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate);
if (ret < 0)
return ret;
st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq,
ad7768_clk_config[idx].clk_div);
return 0;
}
static ssize_t ad7768_sampling_freq_avail(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct ad7768_state *st = iio_priv(indio_dev);
unsigned int freq;
int i, len = 0;
for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
freq = DIV_ROUND_CLOSEST(st->mclk_freq,
ad7768_clk_config[i].clk_div);
len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq);
}
buf[len - 1] = '\n';
return len;
}
static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail);
static int ad7768_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
{
struct ad7768_state *st = iio_priv(indio_dev);
int scale_uv, ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = ad7768_scan_direct(indio_dev);
if (ret >= 0)
*val = ret;
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
scale_uv = regulator_get_voltage(st->vref);
if (scale_uv < 0)
return scale_uv;
*val = (scale_uv * 2) / 1000;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_SAMP_FREQ:
*val = st->samp_freq;
return IIO_VAL_INT;
}
return -EINVAL;
}
static int ad7768_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long info)
{
struct ad7768_state *st = iio_priv(indio_dev);
switch (info) {
case IIO_CHAN_INFO_SAMP_FREQ:
return ad7768_set_freq(st, val);
default:
return -EINVAL;
}
}
static int ad7768_read_label(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, char *label)
{
struct ad7768_state *st = iio_priv(indio_dev);
return sprintf(label, "%s\n", st->labels[chan->channel]);
}
static struct attribute *ad7768_attributes[] = {
&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
NULL
};
static const struct attribute_group ad7768_group = {
.attrs = ad7768_attributes,
};
static const struct iio_info ad7768_info = {
.attrs = &ad7768_group,
.read_raw = &ad7768_read_raw,
.write_raw = &ad7768_write_raw,
.read_label = ad7768_read_label,
.debugfs_reg_access = &ad7768_reg_access,
};
static int ad7768_setup(struct ad7768_state *st)
{
int ret;
/*
* Two writes to the SPI_RESET[1:0] bits are required to initiate
* a software reset. The bits must first be set to 11, and then
* to 10. When the sequence is detected, the reset occurs.
* See the datasheet, page 70.
*/
ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3);
if (ret)
return ret;
ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2);
if (ret)
return ret;
st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in",
GPIOD_OUT_LOW);
if (IS_ERR(st->gpio_sync_in))
return PTR_ERR(st->gpio_sync_in);
/* Set the default sampling frequency to 32000 kSPS */
return ad7768_set_freq(st, 32000);
}
static irqreturn_t ad7768_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct ad7768_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
ret = spi_read(st->spi, &st->data.scan.chan, 3);
if (ret < 0)
goto err_unlock;
iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan,
iio_get_time_ns(indio_dev));
err_unlock:
iio_trigger_notify_done(indio_dev->trig);
mutex_unlock(&st->lock);
return IRQ_HANDLED;
}
static irqreturn_t ad7768_interrupt(int irq, void *dev_id)
{
struct iio_dev *indio_dev = dev_id;
struct ad7768_state *st = iio_priv(indio_dev);
if (iio_buffer_enabled(indio_dev))
iio_trigger_poll(st->trig);
else
complete(&st->completion);
return IRQ_HANDLED;
};
static int ad7768_buffer_postenable(struct iio_dev *indio_dev)
{
struct ad7768_state *st = iio_priv(indio_dev);
/*
* Write a 1 to the LSB of the INTERFACE_FORMAT register to enter
* continuous read mode. Subsequent data reads do not require an
* initial 8-bit write to query the ADC_DATA register.
*/
return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01);
}
static int ad7768_buffer_predisable(struct iio_dev *indio_dev)
{
struct ad7768_state *st = iio_priv(indio_dev);
/*
* To exit continuous read mode, perform a single read of the ADC_DATA
* reg (0x2C), which allows further configuration of the device.
*/
return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
}
static const struct iio_buffer_setup_ops ad7768_buffer_ops = {
.postenable = &ad7768_buffer_postenable,
.predisable = &ad7768_buffer_predisable,
};
static const struct iio_trigger_ops ad7768_trigger_ops = {
.validate_device = iio_trigger_validate_own_device,
};
static void ad7768_regulator_disable(void *data)
{
struct ad7768_state *st = data;
regulator_disable(st->vref);
}
static int ad7768_set_channel_label(struct iio_dev *indio_dev,
int num_channels)
{
struct ad7768_state *st = iio_priv(indio_dev);
struct device *device = indio_dev->dev.parent;
struct fwnode_handle *fwnode;
struct fwnode_handle *child;
const char *label;
int crt_ch = 0;
fwnode = dev_fwnode(device);
fwnode_for_each_child_node(fwnode, child) {
if (fwnode_property_read_u32(child, "reg", &crt_ch))
continue;
if (crt_ch >= num_channels)
continue;
if (fwnode_property_read_string(child, "label", &label))
continue;
st->labels[crt_ch] = label;
}
return 0;
}
static int ad7768_probe(struct spi_device *spi)
{
struct ad7768_state *st;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->spi = spi;
st->vref = devm_regulator_get(&spi->dev, "vref");
if (IS_ERR(st->vref))
return PTR_ERR(st->vref);
ret = regulator_enable(st->vref);
if (ret) {
dev_err(&spi->dev, "Failed to enable specified vref supply\n");
return ret;
}
ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st);
if (ret)
return ret;
st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
if (IS_ERR(st->mclk))
return PTR_ERR(st->mclk);
st->mclk_freq = clk_get_rate(st->mclk);
mutex_init(&st->lock);
indio_dev->channels = ad7768_channels;
indio_dev->num_channels = ARRAY_SIZE(ad7768_channels);
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->info = &ad7768_info;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = ad7768_setup(st);
if (ret < 0) {
dev_err(&spi->dev, "AD7768 setup failed\n");
return ret;
}
st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
indio_dev->name,
iio_device_id(indio_dev));
if (!st->trig)
return -ENOMEM;
st->trig->ops = &ad7768_trigger_ops;
iio_trigger_set_drvdata(st->trig, indio_dev);
ret = devm_iio_trigger_register(&spi->dev, st->trig);
if (ret)
return ret;
indio_dev->trig = iio_trigger_get(st->trig);
init_completion(&st->completion);
ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels));
if (ret)
return ret;
ret = devm_request_irq(&spi->dev, spi->irq,
&ad7768_interrupt,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
indio_dev->name, indio_dev);
if (ret)
return ret;
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
&iio_pollfunc_store_time,
&ad7768_trigger_handler,
&ad7768_buffer_ops);
if (ret)
return ret;
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id ad7768_id_table[] = {
{ "ad7768-1", 0 },
{}
};
MODULE_DEVICE_TABLE(spi, ad7768_id_table);
static const struct of_device_id ad7768_of_match[] = {
{ .compatible = "adi,ad7768-1" },
{ },
};
MODULE_DEVICE_TABLE(of, ad7768_of_match);
static struct spi_driver ad7768_driver = {
.driver = {
.name = "ad7768-1",
.of_match_table = ad7768_of_match,
},
.probe = ad7768_probe,
.id_table = ad7768_id_table,
};
module_spi_driver(ad7768_driver);
MODULE_AUTHOR("Stefan Popa <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ad7768-1.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2014 Angelo Compagnucci <[email protected]>
*
* Driver for Texas Instruments' ADC128S052, ADC122S021 and ADC124S021 ADC chip.
* Datasheets can be found here:
* https://www.ti.com/lit/ds/symlink/adc128s052.pdf
* https://www.ti.com/lit/ds/symlink/adc122s021.pdf
* https://www.ti.com/lit/ds/symlink/adc124s021.pdf
*/
#include <linux/err.h>
#include <linux/iio/iio.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
struct adc128_configuration {
const struct iio_chan_spec *channels;
u8 num_channels;
};
struct adc128 {
struct spi_device *spi;
struct regulator *reg;
struct mutex lock;
u8 buffer[2] __aligned(IIO_DMA_MINALIGN);
};
static int adc128_adc_conversion(struct adc128 *adc, u8 channel)
{
int ret;
mutex_lock(&adc->lock);
adc->buffer[0] = channel << 3;
adc->buffer[1] = 0;
ret = spi_write(adc->spi, &adc->buffer, 2);
if (ret < 0) {
mutex_unlock(&adc->lock);
return ret;
}
ret = spi_read(adc->spi, &adc->buffer, 2);
mutex_unlock(&adc->lock);
if (ret < 0)
return ret;
return ((adc->buffer[0] << 8 | adc->buffer[1]) & 0xFFF);
}
static int adc128_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
struct adc128 *adc = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = adc128_adc_conversion(adc, channel->channel);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = regulator_get_voltage(adc->reg);
if (ret < 0)
return ret;
*val = ret / 1000;
*val2 = 12;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
}
#define ADC128_VOLTAGE_CHANNEL(num) \
{ \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = (num), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
}
static const struct iio_chan_spec adc128s052_channels[] = {
ADC128_VOLTAGE_CHANNEL(0),
ADC128_VOLTAGE_CHANNEL(1),
ADC128_VOLTAGE_CHANNEL(2),
ADC128_VOLTAGE_CHANNEL(3),
ADC128_VOLTAGE_CHANNEL(4),
ADC128_VOLTAGE_CHANNEL(5),
ADC128_VOLTAGE_CHANNEL(6),
ADC128_VOLTAGE_CHANNEL(7),
};
static const struct iio_chan_spec adc122s021_channels[] = {
ADC128_VOLTAGE_CHANNEL(0),
ADC128_VOLTAGE_CHANNEL(1),
};
static const struct iio_chan_spec adc124s021_channels[] = {
ADC128_VOLTAGE_CHANNEL(0),
ADC128_VOLTAGE_CHANNEL(1),
ADC128_VOLTAGE_CHANNEL(2),
ADC128_VOLTAGE_CHANNEL(3),
};
static const struct adc128_configuration adc128_config[] = {
{ adc128s052_channels, ARRAY_SIZE(adc128s052_channels) },
{ adc122s021_channels, ARRAY_SIZE(adc122s021_channels) },
{ adc124s021_channels, ARRAY_SIZE(adc124s021_channels) },
};
static const struct iio_info adc128_info = {
.read_raw = adc128_read_raw,
};
static void adc128_disable_regulator(void *reg)
{
regulator_disable(reg);
}
static int adc128_probe(struct spi_device *spi)
{
const struct adc128_configuration *config;
struct iio_dev *indio_dev;
struct adc128 *adc;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
if (!indio_dev)
return -ENOMEM;
adc = iio_priv(indio_dev);
adc->spi = spi;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &adc128_info;
config = spi_get_device_match_data(spi);
indio_dev->channels = config->channels;
indio_dev->num_channels = config->num_channels;
adc->reg = devm_regulator_get(&spi->dev, "vref");
if (IS_ERR(adc->reg))
return PTR_ERR(adc->reg);
ret = regulator_enable(adc->reg);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&spi->dev, adc128_disable_regulator,
adc->reg);
if (ret)
return ret;
mutex_init(&adc->lock);
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct of_device_id adc128_of_match[] = {
{ .compatible = "ti,adc128s052", .data = &adc128_config[0] },
{ .compatible = "ti,adc122s021", .data = &adc128_config[1] },
{ .compatible = "ti,adc122s051", .data = &adc128_config[1] },
{ .compatible = "ti,adc122s101", .data = &adc128_config[1] },
{ .compatible = "ti,adc124s021", .data = &adc128_config[2] },
{ .compatible = "ti,adc124s051", .data = &adc128_config[2] },
{ .compatible = "ti,adc124s101", .data = &adc128_config[2] },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, adc128_of_match);
static const struct spi_device_id adc128_id[] = {
{ "adc128s052", (kernel_ulong_t)&adc128_config[0] },
{ "adc122s021", (kernel_ulong_t)&adc128_config[1] },
{ "adc122s051", (kernel_ulong_t)&adc128_config[1] },
{ "adc122s101", (kernel_ulong_t)&adc128_config[1] },
{ "adc124s021", (kernel_ulong_t)&adc128_config[2] },
{ "adc124s051", (kernel_ulong_t)&adc128_config[2] },
{ "adc124s101", (kernel_ulong_t)&adc128_config[2] },
{ }
};
MODULE_DEVICE_TABLE(spi, adc128_id);
static const struct acpi_device_id adc128_acpi_match[] = {
{ "AANT1280", (kernel_ulong_t)&adc128_config[2] },
{ }
};
MODULE_DEVICE_TABLE(acpi, adc128_acpi_match);
static struct spi_driver adc128_driver = {
.driver = {
.name = "adc128s052",
.of_match_table = adc128_of_match,
.acpi_match_table = adc128_acpi_match,
},
.probe = adc128_probe,
.id_table = adc128_id,
};
module_spi_driver(adc128_driver);
MODULE_AUTHOR("Angelo Compagnucci <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments ADC128S052");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ti-adc128s052.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for the Diolan DLN-2 USB-ADC adapter
*
* Copyright (c) 2017 Jack Andersen
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/mfd/dln2.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/buffer.h>
#include <linux/iio/kfifo_buf.h>
#define DLN2_ADC_MOD_NAME "dln2-adc"
#define DLN2_ADC_ID 0x06
#define DLN2_ADC_GET_CHANNEL_COUNT DLN2_CMD(0x01, DLN2_ADC_ID)
#define DLN2_ADC_ENABLE DLN2_CMD(0x02, DLN2_ADC_ID)
#define DLN2_ADC_DISABLE DLN2_CMD(0x03, DLN2_ADC_ID)
#define DLN2_ADC_CHANNEL_ENABLE DLN2_CMD(0x05, DLN2_ADC_ID)
#define DLN2_ADC_CHANNEL_DISABLE DLN2_CMD(0x06, DLN2_ADC_ID)
#define DLN2_ADC_SET_RESOLUTION DLN2_CMD(0x08, DLN2_ADC_ID)
#define DLN2_ADC_CHANNEL_GET_VAL DLN2_CMD(0x0A, DLN2_ADC_ID)
#define DLN2_ADC_CHANNEL_GET_ALL_VAL DLN2_CMD(0x0B, DLN2_ADC_ID)
#define DLN2_ADC_CHANNEL_SET_CFG DLN2_CMD(0x0C, DLN2_ADC_ID)
#define DLN2_ADC_CHANNEL_GET_CFG DLN2_CMD(0x0D, DLN2_ADC_ID)
#define DLN2_ADC_CONDITION_MET_EV DLN2_CMD(0x10, DLN2_ADC_ID)
#define DLN2_ADC_EVENT_NONE 0
#define DLN2_ADC_EVENT_BELOW 1
#define DLN2_ADC_EVENT_LEVEL_ABOVE 2
#define DLN2_ADC_EVENT_OUTSIDE 3
#define DLN2_ADC_EVENT_INSIDE 4
#define DLN2_ADC_EVENT_ALWAYS 5
#define DLN2_ADC_MAX_CHANNELS 8
#define DLN2_ADC_DATA_BITS 10
/*
* Plays similar role to iio_demux_table in subsystem core; except allocated
* in a fixed 8-element array.
*/
struct dln2_adc_demux_table {
unsigned int from;
unsigned int to;
unsigned int length;
};
struct dln2_adc {
struct platform_device *pdev;
struct iio_chan_spec iio_channels[DLN2_ADC_MAX_CHANNELS + 1];
int port, trigger_chan;
struct iio_trigger *trig;
struct mutex mutex;
/* Cached sample period in milliseconds */
unsigned int sample_period;
/* Demux table */
unsigned int demux_count;
struct dln2_adc_demux_table demux[DLN2_ADC_MAX_CHANNELS];
/* Precomputed timestamp padding offset and length */
unsigned int ts_pad_offset, ts_pad_length;
};
struct dln2_adc_port_chan {
u8 port;
u8 chan;
};
struct dln2_adc_get_all_vals {
__le16 channel_mask;
__le16 values[DLN2_ADC_MAX_CHANNELS];
};
static void dln2_adc_add_demux(struct dln2_adc *dln2,
unsigned int in_loc, unsigned int out_loc,
unsigned int length)
{
struct dln2_adc_demux_table *p = dln2->demux_count ?
&dln2->demux[dln2->demux_count - 1] : NULL;
if (p && p->from + p->length == in_loc &&
p->to + p->length == out_loc) {
p->length += length;
} else if (dln2->demux_count < DLN2_ADC_MAX_CHANNELS) {
p = &dln2->demux[dln2->demux_count++];
p->from = in_loc;
p->to = out_loc;
p->length = length;
}
}
static void dln2_adc_update_demux(struct dln2_adc *dln2)
{
int in_ind = -1, out_ind;
unsigned int in_loc = 0, out_loc = 0;
struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev);
/* Clear out any old demux */
dln2->demux_count = 0;
/* Optimize all 8-channels case */
if (indio_dev->masklength &&
(*indio_dev->active_scan_mask & 0xff) == 0xff) {
dln2_adc_add_demux(dln2, 0, 0, 16);
dln2->ts_pad_offset = 0;
dln2->ts_pad_length = 0;
return;
}
/* Build demux table from fixed 8-channels to active_scan_mask */
for_each_set_bit(out_ind,
indio_dev->active_scan_mask,
indio_dev->masklength) {
/* Handle timestamp separately */
if (out_ind == DLN2_ADC_MAX_CHANNELS)
break;
for (++in_ind; in_ind != out_ind; ++in_ind)
in_loc += 2;
dln2_adc_add_demux(dln2, in_loc, out_loc, 2);
out_loc += 2;
in_loc += 2;
}
if (indio_dev->scan_timestamp) {
size_t ts_offset = indio_dev->scan_bytes / sizeof(int64_t) - 1;
dln2->ts_pad_offset = out_loc;
dln2->ts_pad_length = ts_offset * sizeof(int64_t) - out_loc;
} else {
dln2->ts_pad_offset = 0;
dln2->ts_pad_length = 0;
}
}
static int dln2_adc_get_chan_count(struct dln2_adc *dln2)
{
int ret;
u8 port = dln2->port;
u8 count;
int olen = sizeof(count);
ret = dln2_transfer(dln2->pdev, DLN2_ADC_GET_CHANNEL_COUNT,
&port, sizeof(port), &count, &olen);
if (ret < 0) {
dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
return ret;
}
if (olen < sizeof(count))
return -EPROTO;
return count;
}
static int dln2_adc_set_port_resolution(struct dln2_adc *dln2)
{
int ret;
struct dln2_adc_port_chan port_chan = {
.port = dln2->port,
.chan = DLN2_ADC_DATA_BITS,
};
ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_SET_RESOLUTION,
&port_chan, sizeof(port_chan));
if (ret < 0)
dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
return ret;
}
static int dln2_adc_set_chan_enabled(struct dln2_adc *dln2,
int channel, bool enable)
{
int ret;
struct dln2_adc_port_chan port_chan = {
.port = dln2->port,
.chan = channel,
};
u16 cmd = enable ? DLN2_ADC_CHANNEL_ENABLE : DLN2_ADC_CHANNEL_DISABLE;
ret = dln2_transfer_tx(dln2->pdev, cmd, &port_chan, sizeof(port_chan));
if (ret < 0)
dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
return ret;
}
static int dln2_adc_set_port_enabled(struct dln2_adc *dln2, bool enable,
u16 *conflict_out)
{
int ret;
u8 port = dln2->port;
__le16 conflict;
int olen = sizeof(conflict);
u16 cmd = enable ? DLN2_ADC_ENABLE : DLN2_ADC_DISABLE;
if (conflict_out)
*conflict_out = 0;
ret = dln2_transfer(dln2->pdev, cmd, &port, sizeof(port),
&conflict, &olen);
if (ret < 0) {
dev_dbg(&dln2->pdev->dev, "Problem in %s(%d)\n",
__func__, (int)enable);
if (conflict_out && enable && olen >= sizeof(conflict))
*conflict_out = le16_to_cpu(conflict);
return ret;
}
if (enable && olen < sizeof(conflict))
return -EPROTO;
return ret;
}
static int dln2_adc_set_chan_period(struct dln2_adc *dln2,
unsigned int channel, unsigned int period)
{
int ret;
struct {
struct dln2_adc_port_chan port_chan;
__u8 type;
__le16 period;
__le16 low;
__le16 high;
} __packed set_cfg = {
.port_chan.port = dln2->port,
.port_chan.chan = channel,
.type = period ? DLN2_ADC_EVENT_ALWAYS : DLN2_ADC_EVENT_NONE,
.period = cpu_to_le16(period)
};
ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_CHANNEL_SET_CFG,
&set_cfg, sizeof(set_cfg));
if (ret < 0)
dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
return ret;
}
static int dln2_adc_read(struct dln2_adc *dln2, unsigned int channel)
{
int ret, i;
u16 conflict;
__le16 value;
int olen = sizeof(value);
struct dln2_adc_port_chan port_chan = {
.port = dln2->port,
.chan = channel,
};
ret = dln2_adc_set_chan_enabled(dln2, channel, true);
if (ret < 0)
return ret;
ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
if (ret < 0) {
if (conflict) {
dev_err(&dln2->pdev->dev,
"ADC pins conflict with mask %04X\n",
(int)conflict);
ret = -EBUSY;
}
goto disable_chan;
}
/*
* Call GET_VAL twice due to initial zero-return immediately after
* enabling channel.
*/
for (i = 0; i < 2; ++i) {
ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_VAL,
&port_chan, sizeof(port_chan),
&value, &olen);
if (ret < 0) {
dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
goto disable_port;
}
if (olen < sizeof(value)) {
ret = -EPROTO;
goto disable_port;
}
}
ret = le16_to_cpu(value);
disable_port:
dln2_adc_set_port_enabled(dln2, false, NULL);
disable_chan:
dln2_adc_set_chan_enabled(dln2, channel, false);
return ret;
}
static int dln2_adc_read_all(struct dln2_adc *dln2,
struct dln2_adc_get_all_vals *get_all_vals)
{
int ret;
__u8 port = dln2->port;
int olen = sizeof(*get_all_vals);
ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_ALL_VAL,
&port, sizeof(port), get_all_vals, &olen);
if (ret < 0) {
dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
return ret;
}
if (olen < sizeof(*get_all_vals))
return -EPROTO;
return ret;
}
static int dln2_adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
int ret;
unsigned int microhertz;
struct dln2_adc *dln2 = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret < 0)
return ret;
mutex_lock(&dln2->mutex);
ret = dln2_adc_read(dln2, chan->channel);
mutex_unlock(&dln2->mutex);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/*
* Voltage reference is fixed at 3.3v
* 3.3 / (1 << 10) * 1000000000
*/
*val = 0;
*val2 = 3222656;
return IIO_VAL_INT_PLUS_NANO;
case IIO_CHAN_INFO_SAMP_FREQ:
if (dln2->sample_period) {
microhertz = 1000000000 / dln2->sample_period;
*val = microhertz / 1000000;
*val2 = microhertz % 1000000;
} else {
*val = 0;
*val2 = 0;
}
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int dln2_adc_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
int ret;
unsigned int microhertz;
struct dln2_adc *dln2 = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
microhertz = 1000000 * val + val2;
mutex_lock(&dln2->mutex);
dln2->sample_period =
microhertz ? 1000000000 / microhertz : UINT_MAX;
if (dln2->sample_period > 65535) {
dln2->sample_period = 65535;
dev_warn(&dln2->pdev->dev,
"clamping period to 65535ms\n");
}
/*
* The first requested channel is arbitrated as a shared
* trigger source, so only one event is registered with the
* DLN. The event handler will then read all enabled channel
* values using DLN2_ADC_CHANNEL_GET_ALL_VAL to maintain
* synchronization between ADC readings.
*/
if (dln2->trigger_chan != -1)
ret = dln2_adc_set_chan_period(dln2,
dln2->trigger_chan, dln2->sample_period);
else
ret = 0;
mutex_unlock(&dln2->mutex);
return ret;
default:
return -EINVAL;
}
}
static int dln2_update_scan_mode(struct iio_dev *indio_dev,
const unsigned long *scan_mask)
{
struct dln2_adc *dln2 = iio_priv(indio_dev);
int chan_count = indio_dev->num_channels - 1;
int ret, i, j;
mutex_lock(&dln2->mutex);
for (i = 0; i < chan_count; ++i) {
ret = dln2_adc_set_chan_enabled(dln2, i,
test_bit(i, scan_mask));
if (ret < 0) {
for (j = 0; j < i; ++j)
dln2_adc_set_chan_enabled(dln2, j, false);
mutex_unlock(&dln2->mutex);
dev_err(&dln2->pdev->dev,
"Unable to enable ADC channel %d\n", i);
return -EBUSY;
}
}
dln2_adc_update_demux(dln2);
mutex_unlock(&dln2->mutex);
return 0;
}
#define DLN2_ADC_CHAN(lval, idx) { \
lval.type = IIO_VOLTAGE; \
lval.channel = idx; \
lval.indexed = 1; \
lval.info_mask_separate = BIT(IIO_CHAN_INFO_RAW); \
lval.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ); \
lval.scan_index = idx; \
lval.scan_type.sign = 'u'; \
lval.scan_type.realbits = DLN2_ADC_DATA_BITS; \
lval.scan_type.storagebits = 16; \
lval.scan_type.endianness = IIO_LE; \
}
/* Assignment version of IIO_CHAN_SOFT_TIMESTAMP */
#define IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(lval, _si) { \
lval.type = IIO_TIMESTAMP; \
lval.channel = -1; \
lval.scan_index = _si; \
lval.scan_type.sign = 's'; \
lval.scan_type.realbits = 64; \
lval.scan_type.storagebits = 64; \
}
static const struct iio_info dln2_adc_info = {
.read_raw = dln2_adc_read_raw,
.write_raw = dln2_adc_write_raw,
.update_scan_mode = dln2_update_scan_mode,
};
static irqreturn_t dln2_adc_trigger_h(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct {
__le16 values[DLN2_ADC_MAX_CHANNELS];
int64_t timestamp_space;
} data;
struct dln2_adc_get_all_vals dev_data;
struct dln2_adc *dln2 = iio_priv(indio_dev);
const struct dln2_adc_demux_table *t;
int ret, i;
mutex_lock(&dln2->mutex);
ret = dln2_adc_read_all(dln2, &dev_data);
mutex_unlock(&dln2->mutex);
if (ret < 0)
goto done;
/* Demux operation */
for (i = 0; i < dln2->demux_count; ++i) {
t = &dln2->demux[i];
memcpy((void *)data.values + t->to,
(void *)dev_data.values + t->from, t->length);
}
/* Zero padding space between values and timestamp */
if (dln2->ts_pad_length)
memset((void *)data.values + dln2->ts_pad_offset,
0, dln2->ts_pad_length);
iio_push_to_buffers_with_timestamp(indio_dev, &data,
iio_get_time_ns(indio_dev));
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int dln2_adc_triggered_buffer_postenable(struct iio_dev *indio_dev)
{
int ret;
struct dln2_adc *dln2 = iio_priv(indio_dev);
u16 conflict;
unsigned int trigger_chan;
mutex_lock(&dln2->mutex);
/* Enable ADC */
ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
if (ret < 0) {
mutex_unlock(&dln2->mutex);
dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
if (conflict) {
dev_err(&dln2->pdev->dev,
"ADC pins conflict with mask %04X\n",
(int)conflict);
ret = -EBUSY;
}
return ret;
}
/* Assign trigger channel based on first enabled channel */
trigger_chan = find_first_bit(indio_dev->active_scan_mask,
indio_dev->masklength);
if (trigger_chan < DLN2_ADC_MAX_CHANNELS) {
dln2->trigger_chan = trigger_chan;
ret = dln2_adc_set_chan_period(dln2, dln2->trigger_chan,
dln2->sample_period);
mutex_unlock(&dln2->mutex);
if (ret < 0) {
dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
return ret;
}
} else {
dln2->trigger_chan = -1;
mutex_unlock(&dln2->mutex);
}
return 0;
}
static int dln2_adc_triggered_buffer_predisable(struct iio_dev *indio_dev)
{
int ret;
struct dln2_adc *dln2 = iio_priv(indio_dev);
mutex_lock(&dln2->mutex);
/* Disable trigger channel */
if (dln2->trigger_chan != -1) {
dln2_adc_set_chan_period(dln2, dln2->trigger_chan, 0);
dln2->trigger_chan = -1;
}
/* Disable ADC */
ret = dln2_adc_set_port_enabled(dln2, false, NULL);
mutex_unlock(&dln2->mutex);
if (ret < 0)
dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
return ret;
}
static const struct iio_buffer_setup_ops dln2_adc_buffer_setup_ops = {
.postenable = dln2_adc_triggered_buffer_postenable,
.predisable = dln2_adc_triggered_buffer_predisable,
};
static void dln2_adc_event(struct platform_device *pdev, u16 echo,
const void *data, int len)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct dln2_adc *dln2 = iio_priv(indio_dev);
/* Called via URB completion handler */
iio_trigger_poll(dln2->trig);
}
static int dln2_adc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct dln2_adc *dln2;
struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
struct iio_dev *indio_dev;
int i, ret, chans;
indio_dev = devm_iio_device_alloc(dev, sizeof(*dln2));
if (!indio_dev) {
dev_err(dev, "failed allocating iio device\n");
return -ENOMEM;
}
dln2 = iio_priv(indio_dev);
dln2->pdev = pdev;
dln2->port = pdata->port;
dln2->trigger_chan = -1;
mutex_init(&dln2->mutex);
platform_set_drvdata(pdev, indio_dev);
ret = dln2_adc_set_port_resolution(dln2);
if (ret < 0) {
dev_err(dev, "failed to set ADC resolution to 10 bits\n");
return ret;
}
chans = dln2_adc_get_chan_count(dln2);
if (chans < 0) {
dev_err(dev, "failed to get channel count: %d\n", chans);
return chans;
}
if (chans > DLN2_ADC_MAX_CHANNELS) {
chans = DLN2_ADC_MAX_CHANNELS;
dev_warn(dev, "clamping channels to %d\n",
DLN2_ADC_MAX_CHANNELS);
}
for (i = 0; i < chans; ++i)
DLN2_ADC_CHAN(dln2->iio_channels[i], i)
IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(dln2->iio_channels[i], i);
indio_dev->name = DLN2_ADC_MOD_NAME;
indio_dev->info = &dln2_adc_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = dln2->iio_channels;
indio_dev->num_channels = chans + 1;
indio_dev->setup_ops = &dln2_adc_buffer_setup_ops;
dln2->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
indio_dev->name,
iio_device_id(indio_dev));
if (!dln2->trig) {
dev_err(dev, "failed to allocate trigger\n");
return -ENOMEM;
}
iio_trigger_set_drvdata(dln2->trig, dln2);
ret = devm_iio_trigger_register(dev, dln2->trig);
if (ret) {
dev_err(dev, "failed to register trigger: %d\n", ret);
return ret;
}
iio_trigger_set_immutable(indio_dev, dln2->trig);
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
dln2_adc_trigger_h,
&dln2_adc_buffer_setup_ops);
if (ret) {
dev_err(dev, "failed to allocate triggered buffer: %d\n", ret);
return ret;
}
ret = dln2_register_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV,
dln2_adc_event);
if (ret) {
dev_err(dev, "failed to setup DLN2 periodic event: %d\n", ret);
return ret;
}
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(dev, "failed to register iio device: %d\n", ret);
goto unregister_event;
}
return ret;
unregister_event:
dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
return ret;
}
static int dln2_adc_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
iio_device_unregister(indio_dev);
dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
return 0;
}
static struct platform_driver dln2_adc_driver = {
.driver.name = DLN2_ADC_MOD_NAME,
.probe = dln2_adc_probe,
.remove = dln2_adc_remove,
};
module_platform_driver(dln2_adc_driver);
MODULE_AUTHOR("Jack Andersen <[email protected]");
MODULE_DESCRIPTION("Driver for the Diolan DLN2 ADC interface");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dln2-adc");
| linux-master | drivers/iio/adc/dln2-adc.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* NXP i.MX8QXP ADC driver
*
* Based on the work of Haibo Chen <[email protected]>
* The initial developer of the original code is Haibo Chen.
* Portions created by Haibo Chen are Copyright (C) 2018 NXP.
* All Rights Reserved.
*
* Copyright (C) 2018 NXP
* Copyright (C) 2021 Cai Huoqing
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#define ADC_DRIVER_NAME "imx8qxp-adc"
/* Register map definition */
#define IMX8QXP_ADR_ADC_CTRL 0x10
#define IMX8QXP_ADR_ADC_STAT 0x14
#define IMX8QXP_ADR_ADC_IE 0x18
#define IMX8QXP_ADR_ADC_DE 0x1c
#define IMX8QXP_ADR_ADC_CFG 0x20
#define IMX8QXP_ADR_ADC_FCTRL 0x30
#define IMX8QXP_ADR_ADC_SWTRIG 0x34
#define IMX8QXP_ADR_ADC_TCTRL(tid) (0xc0 + (tid) * 4)
#define IMX8QXP_ADR_ADC_CMDH(cid) (0x100 + (cid) * 8)
#define IMX8QXP_ADR_ADC_CMDL(cid) (0x104 + (cid) * 8)
#define IMX8QXP_ADR_ADC_RESFIFO 0x300
#define IMX8QXP_ADR_ADC_TST 0xffc
/* ADC bit shift */
#define IMX8QXP_ADC_IE_FWMIE_MASK GENMASK(1, 0)
#define IMX8QXP_ADC_CTRL_FIFO_RESET_MASK BIT(8)
#define IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK BIT(1)
#define IMX8QXP_ADC_CTRL_ADC_EN_MASK BIT(0)
#define IMX8QXP_ADC_TCTRL_TCMD_MASK GENMASK(31, 24)
#define IMX8QXP_ADC_TCTRL_TDLY_MASK GENMASK(23, 16)
#define IMX8QXP_ADC_TCTRL_TPRI_MASK GENMASK(15, 8)
#define IMX8QXP_ADC_TCTRL_HTEN_MASK GENMASK(7, 0)
#define IMX8QXP_ADC_CMDL_CSCALE_MASK GENMASK(13, 8)
#define IMX8QXP_ADC_CMDL_MODE_MASK BIT(7)
#define IMX8QXP_ADC_CMDL_DIFF_MASK BIT(6)
#define IMX8QXP_ADC_CMDL_ABSEL_MASK BIT(5)
#define IMX8QXP_ADC_CMDL_ADCH_MASK GENMASK(2, 0)
#define IMX8QXP_ADC_CMDH_NEXT_MASK GENMASK(31, 24)
#define IMX8QXP_ADC_CMDH_LOOP_MASK GENMASK(23, 16)
#define IMX8QXP_ADC_CMDH_AVGS_MASK GENMASK(15, 12)
#define IMX8QXP_ADC_CMDH_STS_MASK BIT(8)
#define IMX8QXP_ADC_CMDH_LWI_MASK GENMASK(7, 7)
#define IMX8QXP_ADC_CMDH_CMPEN_MASK GENMASK(0, 0)
#define IMX8QXP_ADC_CFG_PWREN_MASK BIT(28)
#define IMX8QXP_ADC_CFG_PUDLY_MASK GENMASK(23, 16)
#define IMX8QXP_ADC_CFG_REFSEL_MASK GENMASK(7, 6)
#define IMX8QXP_ADC_CFG_PWRSEL_MASK GENMASK(5, 4)
#define IMX8QXP_ADC_CFG_TPRICTRL_MASK GENMASK(3, 0)
#define IMX8QXP_ADC_FCTRL_FWMARK_MASK GENMASK(20, 16)
#define IMX8QXP_ADC_FCTRL_FCOUNT_MASK GENMASK(4, 0)
#define IMX8QXP_ADC_RESFIFO_VAL_MASK GENMASK(18, 3)
/* ADC PARAMETER*/
#define IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL GENMASK(5, 0)
#define IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL 0
#define IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION 0
#define IMX8QXP_ADC_CMDL_MODE_SINGLE 0
#define IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS 0
#define IMX8QXP_ADC_CMDH_CMPEN_DIS 0
#define IMX8QXP_ADC_PAUSE_EN BIT(31)
#define IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH 0
#define IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS 0
#define IMX8QXP_ADC_TIMEOUT msecs_to_jiffies(100)
#define IMX8QXP_ADC_MAX_FIFO_SIZE 16
struct imx8qxp_adc {
struct device *dev;
void __iomem *regs;
struct clk *clk;
struct clk *ipg_clk;
struct regulator *vref;
/* Serialise ADC channel reads */
struct mutex lock;
struct completion completion;
u32 fifo[IMX8QXP_ADC_MAX_FIFO_SIZE];
};
#define IMX8QXP_ADC_CHAN(_idx) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = (_idx), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
}
static const struct iio_chan_spec imx8qxp_adc_iio_channels[] = {
IMX8QXP_ADC_CHAN(0),
IMX8QXP_ADC_CHAN(1),
IMX8QXP_ADC_CHAN(2),
IMX8QXP_ADC_CHAN(3),
IMX8QXP_ADC_CHAN(4),
IMX8QXP_ADC_CHAN(5),
IMX8QXP_ADC_CHAN(6),
IMX8QXP_ADC_CHAN(7),
};
static void imx8qxp_adc_reset(struct imx8qxp_adc *adc)
{
u32 ctrl;
/*software reset, need to clear the set bit*/
ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1);
writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
udelay(10);
ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1);
writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
/* reset the fifo */
ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_FIFO_RESET_MASK, 1);
writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
}
static void imx8qxp_adc_reg_config(struct imx8qxp_adc *adc, int channel)
{
u32 adc_cfg, adc_tctrl, adc_cmdl, adc_cmdh;
/* ADC configuration */
adc_cfg = FIELD_PREP(IMX8QXP_ADC_CFG_PWREN_MASK, 1) |
FIELD_PREP(IMX8QXP_ADC_CFG_PUDLY_MASK, 0x80)|
FIELD_PREP(IMX8QXP_ADC_CFG_REFSEL_MASK, 0) |
FIELD_PREP(IMX8QXP_ADC_CFG_PWRSEL_MASK, 3) |
FIELD_PREP(IMX8QXP_ADC_CFG_TPRICTRL_MASK, 0);
writel(adc_cfg, adc->regs + IMX8QXP_ADR_ADC_CFG);
/* config the trigger control */
adc_tctrl = FIELD_PREP(IMX8QXP_ADC_TCTRL_TCMD_MASK, 1) |
FIELD_PREP(IMX8QXP_ADC_TCTRL_TDLY_MASK, 0) |
FIELD_PREP(IMX8QXP_ADC_TCTRL_TPRI_MASK, IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH) |
FIELD_PREP(IMX8QXP_ADC_TCTRL_HTEN_MASK, IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS);
writel(adc_tctrl, adc->regs + IMX8QXP_ADR_ADC_TCTRL(0));
/* config the cmd */
adc_cmdl = FIELD_PREP(IMX8QXP_ADC_CMDL_CSCALE_MASK, IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL) |
FIELD_PREP(IMX8QXP_ADC_CMDL_MODE_MASK, IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION) |
FIELD_PREP(IMX8QXP_ADC_CMDL_DIFF_MASK, IMX8QXP_ADC_CMDL_MODE_SINGLE) |
FIELD_PREP(IMX8QXP_ADC_CMDL_ABSEL_MASK, IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL) |
FIELD_PREP(IMX8QXP_ADC_CMDL_ADCH_MASK, channel);
writel(adc_cmdl, adc->regs + IMX8QXP_ADR_ADC_CMDL(0));
adc_cmdh = FIELD_PREP(IMX8QXP_ADC_CMDH_NEXT_MASK, 0) |
FIELD_PREP(IMX8QXP_ADC_CMDH_LOOP_MASK, 0) |
FIELD_PREP(IMX8QXP_ADC_CMDH_AVGS_MASK, 7) |
FIELD_PREP(IMX8QXP_ADC_CMDH_STS_MASK, 0) |
FIELD_PREP(IMX8QXP_ADC_CMDH_LWI_MASK, IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS) |
FIELD_PREP(IMX8QXP_ADC_CMDH_CMPEN_MASK, IMX8QXP_ADC_CMDH_CMPEN_DIS);
writel(adc_cmdh, adc->regs + IMX8QXP_ADR_ADC_CMDH(0));
}
static void imx8qxp_adc_fifo_config(struct imx8qxp_adc *adc)
{
u32 fifo_ctrl, interrupt_en;
fifo_ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL);
fifo_ctrl &= ~IMX8QXP_ADC_FCTRL_FWMARK_MASK;
/* set the watermark level to 1 */
fifo_ctrl |= FIELD_PREP(IMX8QXP_ADC_FCTRL_FWMARK_MASK, 0);
writel(fifo_ctrl, adc->regs + IMX8QXP_ADR_ADC_FCTRL);
/* FIFO Watermark Interrupt Enable */
interrupt_en = readl(adc->regs + IMX8QXP_ADR_ADC_IE);
interrupt_en |= FIELD_PREP(IMX8QXP_ADC_IE_FWMIE_MASK, 1);
writel(interrupt_en, adc->regs + IMX8QXP_ADR_ADC_IE);
}
static void imx8qxp_adc_disable(struct imx8qxp_adc *adc)
{
u32 ctrl;
ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1);
writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
}
static int imx8qxp_adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct imx8qxp_adc *adc = iio_priv(indio_dev);
struct device *dev = adc->dev;
u32 ctrl;
long ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
pm_runtime_get_sync(dev);
mutex_lock(&adc->lock);
reinit_completion(&adc->completion);
imx8qxp_adc_reg_config(adc, chan->channel);
imx8qxp_adc_fifo_config(adc);
/* adc enable */
ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL);
ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1);
writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
/* adc start */
writel(1, adc->regs + IMX8QXP_ADR_ADC_SWTRIG);
ret = wait_for_completion_interruptible_timeout(&adc->completion,
IMX8QXP_ADC_TIMEOUT);
pm_runtime_mark_last_busy(dev);
pm_runtime_put_sync_autosuspend(dev);
if (ret == 0) {
mutex_unlock(&adc->lock);
return -ETIMEDOUT;
}
if (ret < 0) {
mutex_unlock(&adc->lock);
return ret;
}
*val = adc->fifo[0];
mutex_unlock(&adc->lock);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = regulator_get_voltage(adc->vref);
if (ret < 0)
return ret;
*val = ret / 1000;
*val2 = 12;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_SAMP_FREQ:
*val = clk_get_rate(adc->clk) / 3;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static irqreturn_t imx8qxp_adc_isr(int irq, void *dev_id)
{
struct imx8qxp_adc *adc = dev_id;
u32 fifo_count;
int i;
fifo_count = FIELD_GET(IMX8QXP_ADC_FCTRL_FCOUNT_MASK,
readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL));
for (i = 0; i < fifo_count; i++)
adc->fifo[i] = FIELD_GET(IMX8QXP_ADC_RESFIFO_VAL_MASK,
readl_relaxed(adc->regs + IMX8QXP_ADR_ADC_RESFIFO));
if (fifo_count)
complete(&adc->completion);
return IRQ_HANDLED;
}
static int imx8qxp_adc_reg_access(struct iio_dev *indio_dev, unsigned int reg,
unsigned int writeval, unsigned int *readval)
{
struct imx8qxp_adc *adc = iio_priv(indio_dev);
struct device *dev = adc->dev;
if (!readval || reg % 4 || reg > IMX8QXP_ADR_ADC_TST)
return -EINVAL;
pm_runtime_get_sync(dev);
*readval = readl(adc->regs + reg);
pm_runtime_mark_last_busy(dev);
pm_runtime_put_sync_autosuspend(dev);
return 0;
}
static const struct iio_info imx8qxp_adc_iio_info = {
.read_raw = &imx8qxp_adc_read_raw,
.debugfs_reg_access = &imx8qxp_adc_reg_access,
};
static int imx8qxp_adc_probe(struct platform_device *pdev)
{
struct imx8qxp_adc *adc;
struct iio_dev *indio_dev;
struct device *dev = &pdev->dev;
int irq;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
if (!indio_dev) {
dev_err(dev, "Failed allocating iio device\n");
return -ENOMEM;
}
adc = iio_priv(indio_dev);
adc->dev = dev;
mutex_init(&adc->lock);
adc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(adc->regs))
return PTR_ERR(adc->regs);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
adc->clk = devm_clk_get(dev, "per");
if (IS_ERR(adc->clk))
return dev_err_probe(dev, PTR_ERR(adc->clk), "Failed getting clock\n");
adc->ipg_clk = devm_clk_get(dev, "ipg");
if (IS_ERR(adc->ipg_clk))
return dev_err_probe(dev, PTR_ERR(adc->ipg_clk), "Failed getting clock\n");
adc->vref = devm_regulator_get(dev, "vref");
if (IS_ERR(adc->vref))
return dev_err_probe(dev, PTR_ERR(adc->vref), "Failed getting reference voltage\n");
ret = regulator_enable(adc->vref);
if (ret) {
dev_err(dev, "Can't enable adc reference top voltage\n");
return ret;
}
platform_set_drvdata(pdev, indio_dev);
init_completion(&adc->completion);
indio_dev->name = ADC_DRIVER_NAME;
indio_dev->info = &imx8qxp_adc_iio_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = imx8qxp_adc_iio_channels;
indio_dev->num_channels = ARRAY_SIZE(imx8qxp_adc_iio_channels);
ret = clk_prepare_enable(adc->clk);
if (ret) {
dev_err(&pdev->dev, "Could not prepare or enable the clock.\n");
goto error_regulator_disable;
}
ret = clk_prepare_enable(adc->ipg_clk);
if (ret) {
dev_err(&pdev->dev, "Could not prepare or enable the clock.\n");
goto error_adc_clk_disable;
}
ret = devm_request_irq(dev, irq, imx8qxp_adc_isr, 0, ADC_DRIVER_NAME, adc);
if (ret < 0) {
dev_err(dev, "Failed requesting irq, irq = %d\n", irq);
goto error_ipg_clk_disable;
}
imx8qxp_adc_reset(adc);
ret = iio_device_register(indio_dev);
if (ret) {
imx8qxp_adc_disable(adc);
dev_err(dev, "Couldn't register the device.\n");
goto error_ipg_clk_disable;
}
pm_runtime_set_active(dev);
pm_runtime_set_autosuspend_delay(dev, 50);
pm_runtime_use_autosuspend(dev);
pm_runtime_enable(dev);
return 0;
error_ipg_clk_disable:
clk_disable_unprepare(adc->ipg_clk);
error_adc_clk_disable:
clk_disable_unprepare(adc->clk);
error_regulator_disable:
regulator_disable(adc->vref);
return ret;
}
static int imx8qxp_adc_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct imx8qxp_adc *adc = iio_priv(indio_dev);
struct device *dev = adc->dev;
pm_runtime_get_sync(dev);
iio_device_unregister(indio_dev);
imx8qxp_adc_disable(adc);
clk_disable_unprepare(adc->clk);
clk_disable_unprepare(adc->ipg_clk);
regulator_disable(adc->vref);
pm_runtime_disable(dev);
pm_runtime_put_noidle(dev);
return 0;
}
static int imx8qxp_adc_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct imx8qxp_adc *adc = iio_priv(indio_dev);
imx8qxp_adc_disable(adc);
clk_disable_unprepare(adc->clk);
clk_disable_unprepare(adc->ipg_clk);
regulator_disable(adc->vref);
return 0;
}
static int imx8qxp_adc_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct imx8qxp_adc *adc = iio_priv(indio_dev);
int ret;
ret = regulator_enable(adc->vref);
if (ret) {
dev_err(dev, "Can't enable adc reference top voltage, err = %d\n", ret);
return ret;
}
ret = clk_prepare_enable(adc->clk);
if (ret) {
dev_err(dev, "Could not prepare or enable clock.\n");
goto err_disable_reg;
}
ret = clk_prepare_enable(adc->ipg_clk);
if (ret) {
dev_err(dev, "Could not prepare or enable clock.\n");
goto err_unprepare_clk;
}
imx8qxp_adc_reset(adc);
return 0;
err_unprepare_clk:
clk_disable_unprepare(adc->clk);
err_disable_reg:
regulator_disable(adc->vref);
return ret;
}
static DEFINE_RUNTIME_DEV_PM_OPS(imx8qxp_adc_pm_ops,
imx8qxp_adc_runtime_suspend,
imx8qxp_adc_runtime_resume, NULL);
static const struct of_device_id imx8qxp_adc_match[] = {
{ .compatible = "nxp,imx8qxp-adc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx8qxp_adc_match);
static struct platform_driver imx8qxp_adc_driver = {
.probe = imx8qxp_adc_probe,
.remove = imx8qxp_adc_remove,
.driver = {
.name = ADC_DRIVER_NAME,
.of_match_table = imx8qxp_adc_match,
.pm = pm_ptr(&imx8qxp_adc_pm_ops),
},
};
module_platform_driver(imx8qxp_adc_driver);
MODULE_DESCRIPTION("i.MX8QuadXPlus ADC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/imx8qxp-adc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* GPADC driver for sunxi platforms (D1, T113-S3 and R329)
* Copyright (c) 2023 Maksim Kiselev <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/reset.h>
#include <linux/iio/iio.h>
#define SUN20I_GPADC_DRIVER_NAME "sun20i-gpadc"
/* Register map definition */
#define SUN20I_GPADC_SR 0x00
#define SUN20I_GPADC_CTRL 0x04
#define SUN20I_GPADC_CS_EN 0x08
#define SUN20I_GPADC_FIFO_INTC 0x0c
#define SUN20I_GPADC_FIFO_INTS 0x10
#define SUN20I_GPADC_FIFO_DATA 0X14
#define SUN20I_GPADC_CB_DATA 0X18
#define SUN20I_GPADC_DATAL_INTC 0x20
#define SUN20I_GPADC_DATAH_INTC 0x24
#define SUN20I_GPADC_DATA_INTC 0x28
#define SUN20I_GPADC_DATAL_INTS 0x30
#define SUN20I_GPADC_DATAH_INTS 0x34
#define SUN20I_GPADC_DATA_INTS 0x38
#define SUN20I_GPADC_CH_CMP_DATA(x) (0x40 + (x) * 4)
#define SUN20I_GPADC_CH_DATA(x) (0x80 + (x) * 4)
#define SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK BIT(23)
#define SUN20I_GPADC_CTRL_WORK_MODE_MASK GENMASK(19, 18)
#define SUN20I_GPADC_CTRL_ADC_EN_MASK BIT(16)
#define SUN20I_GPADC_CS_EN_ADC_CH(x) BIT(x)
#define SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(x) BIT(x)
#define SUN20I_GPADC_WORK_MODE_SINGLE 0
struct sun20i_gpadc_iio {
void __iomem *regs;
struct completion completion;
int last_channel;
/*
* Lock to protect the device state during a potential concurrent
* read access from userspace. Reading a raw value requires a sequence
* of register writes, then a wait for a completion callback,
* and finally a register read, during which userspace could issue
* another read request. This lock protects a read access from
* ocurring before another one has finished.
*/
struct mutex lock;
};
static int sun20i_gpadc_adc_read(struct sun20i_gpadc_iio *info,
struct iio_chan_spec const *chan, int *val)
{
u32 ctrl;
int ret = IIO_VAL_INT;
mutex_lock(&info->lock);
reinit_completion(&info->completion);
if (info->last_channel != chan->channel) {
info->last_channel = chan->channel;
/* enable the analog input channel */
writel(SUN20I_GPADC_CS_EN_ADC_CH(chan->channel),
info->regs + SUN20I_GPADC_CS_EN);
/* enable the data irq for input channel */
writel(SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(chan->channel),
info->regs + SUN20I_GPADC_DATA_INTC);
}
/* enable the ADC function */
ctrl = readl(info->regs + SUN20I_GPADC_CTRL);
ctrl |= FIELD_PREP(SUN20I_GPADC_CTRL_ADC_EN_MASK, 1);
writel(ctrl, info->regs + SUN20I_GPADC_CTRL);
/*
* According to the datasheet maximum acquire time(TACQ) can be
* (65535+1)/24Mhz and conversion time(CONV_TIME) is always constant
* and equal to 14/24Mhz, so (TACQ+CONV_TIME) <= 2.73125ms.
* A 10ms delay should be enough to make sure an interrupt occurs in
* normal conditions. If it doesn't occur, then there is a timeout.
*/
if (!wait_for_completion_timeout(&info->completion, msecs_to_jiffies(10))) {
ret = -ETIMEDOUT;
goto err_unlock;
}
/* read the ADC data */
*val = readl(info->regs + SUN20I_GPADC_CH_DATA(chan->channel));
err_unlock:
mutex_unlock(&info->lock);
return ret;
}
static int sun20i_gpadc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct sun20i_gpadc_iio *info = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
return sun20i_gpadc_adc_read(info, chan, val);
case IIO_CHAN_INFO_SCALE:
/* value in mv = 1800mV / 4096 raw */
*val = 1800;
*val2 = 12;
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
}
static irqreturn_t sun20i_gpadc_irq_handler(int irq, void *data)
{
struct sun20i_gpadc_iio *info = data;
/* clear data interrupt status register */
writel(GENMASK(31, 0), info->regs + SUN20I_GPADC_DATA_INTS);
complete(&info->completion);
return IRQ_HANDLED;
}
static const struct iio_info sun20i_gpadc_iio_info = {
.read_raw = sun20i_gpadc_read_raw,
};
static void sun20i_gpadc_reset_assert(void *data)
{
struct reset_control *rst = data;
reset_control_assert(rst);
}
static int sun20i_gpadc_alloc_channels(struct iio_dev *indio_dev,
struct device *dev)
{
unsigned int channel;
int num_channels, i, ret;
struct iio_chan_spec *channels;
struct fwnode_handle *node;
num_channels = device_get_child_node_count(dev);
if (num_channels == 0)
return dev_err_probe(dev, -ENODEV, "no channel children\n");
channels = devm_kcalloc(dev, num_channels, sizeof(*channels),
GFP_KERNEL);
if (!channels)
return -ENOMEM;
i = 0;
device_for_each_child_node(dev, node) {
ret = fwnode_property_read_u32(node, "reg", &channel);
if (ret) {
fwnode_handle_put(node);
return dev_err_probe(dev, ret, "invalid channel number\n");
}
channels[i].type = IIO_VOLTAGE;
channels[i].indexed = 1;
channels[i].channel = channel;
channels[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
channels[i].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
i++;
}
indio_dev->channels = channels;
indio_dev->num_channels = num_channels;
return 0;
}
static int sun20i_gpadc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct iio_dev *indio_dev;
struct sun20i_gpadc_iio *info;
struct reset_control *rst;
struct clk *clk;
int irq;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*info));
if (!indio_dev)
return -ENOMEM;
info = iio_priv(indio_dev);
info->last_channel = -1;
mutex_init(&info->lock);
init_completion(&info->completion);
ret = sun20i_gpadc_alloc_channels(indio_dev, dev);
if (ret)
return ret;
indio_dev->info = &sun20i_gpadc_iio_info;
indio_dev->name = SUN20I_GPADC_DRIVER_NAME;
info->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(info->regs))
return PTR_ERR(info->regs);
clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(clk))
return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock\n");
rst = devm_reset_control_get_exclusive(dev, NULL);
if (IS_ERR(rst))
return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n");
ret = reset_control_deassert(rst);
if (ret)
return dev_err_probe(dev, ret, "failed to deassert reset\n");
ret = devm_add_action_or_reset(dev, sun20i_gpadc_reset_assert, rst);
if (ret)
return ret;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(dev, irq, sun20i_gpadc_irq_handler, 0,
dev_name(dev), info);
if (ret)
return dev_err_probe(dev, ret, "failed requesting irq %d\n", irq);
writel(FIELD_PREP(SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK, 1) |
FIELD_PREP(SUN20I_GPADC_CTRL_WORK_MODE_MASK, SUN20I_GPADC_WORK_MODE_SINGLE),
info->regs + SUN20I_GPADC_CTRL);
ret = devm_iio_device_register(dev, indio_dev);
if (ret)
return dev_err_probe(dev, ret, "could not register the device\n");
return 0;
}
static const struct of_device_id sun20i_gpadc_of_id[] = {
{ .compatible = "allwinner,sun20i-d1-gpadc" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun20i_gpadc_of_id);
static struct platform_driver sun20i_gpadc_driver = {
.driver = {
.name = SUN20I_GPADC_DRIVER_NAME,
.of_match_table = sun20i_gpadc_of_id,
},
.probe = sun20i_gpadc_probe,
};
module_platform_driver(sun20i_gpadc_driver);
MODULE_DESCRIPTION("ADC driver for sunxi platforms");
MODULE_AUTHOR("Maksim Kiselev <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/adc/sun20i-gpadc-iio.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* exynos_adc.c - Support for ADC in EXYNOS SoCs
*
* 8 ~ 10 channel, 10/12-bit ADC
*
* Copyright (C) 2013 Naveen Krishna Chatradhi <[email protected]>
*/
#include <linux/compiler.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/regulator/consumer.h>
#include <linux/of_platform.h>
#include <linux/err.h>
#include <linux/input.h>
#include <linux/iio/iio.h>
#include <linux/iio/machine.h>
#include <linux/iio/driver.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/platform_data/touchscreen-s3c2410.h>
/* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
#define ADC_V1_CON(x) ((x) + 0x00)
#define ADC_V1_TSC(x) ((x) + 0x04)
#define ADC_V1_DLY(x) ((x) + 0x08)
#define ADC_V1_DATX(x) ((x) + 0x0C)
#define ADC_V1_DATY(x) ((x) + 0x10)
#define ADC_V1_UPDN(x) ((x) + 0x14)
#define ADC_V1_INTCLR(x) ((x) + 0x18)
#define ADC_V1_MUX(x) ((x) + 0x1c)
#define ADC_V1_CLRINTPNDNUP(x) ((x) + 0x20)
/* S3C2410 ADC registers definitions */
#define ADC_S3C2410_MUX(x) ((x) + 0x18)
/* Future ADC_V2 registers definitions */
#define ADC_V2_CON1(x) ((x) + 0x00)
#define ADC_V2_CON2(x) ((x) + 0x04)
#define ADC_V2_STAT(x) ((x) + 0x08)
#define ADC_V2_INT_EN(x) ((x) + 0x10)
#define ADC_V2_INT_ST(x) ((x) + 0x14)
#define ADC_V2_VER(x) ((x) + 0x20)
/* Bit definitions for ADC_V1 */
#define ADC_V1_CON_RES (1u << 16)
#define ADC_V1_CON_PRSCEN (1u << 14)
#define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6)
#define ADC_V1_CON_STANDBY (1u << 2)
/* Bit definitions for S3C2410 ADC */
#define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
#define ADC_S3C2410_DATX_MASK 0x3FF
#define ADC_S3C2416_CON_RES_SEL (1u << 3)
/* touch screen always uses channel 0 */
#define ADC_S3C2410_MUX_TS 0
/* ADCTSC Register Bits */
#define ADC_S3C2443_TSC_UD_SEN (1u << 8)
#define ADC_S3C2410_TSC_YM_SEN (1u << 7)
#define ADC_S3C2410_TSC_YP_SEN (1u << 6)
#define ADC_S3C2410_TSC_XM_SEN (1u << 5)
#define ADC_S3C2410_TSC_XP_SEN (1u << 4)
#define ADC_S3C2410_TSC_PULL_UP_DISABLE (1u << 3)
#define ADC_S3C2410_TSC_AUTO_PST (1u << 2)
#define ADC_S3C2410_TSC_XY_PST(x) (((x) & 0x3) << 0)
#define ADC_TSC_WAIT4INT (ADC_S3C2410_TSC_YM_SEN | \
ADC_S3C2410_TSC_YP_SEN | \
ADC_S3C2410_TSC_XP_SEN | \
ADC_S3C2410_TSC_XY_PST(3))
#define ADC_TSC_AUTOPST (ADC_S3C2410_TSC_YM_SEN | \
ADC_S3C2410_TSC_YP_SEN | \
ADC_S3C2410_TSC_XP_SEN | \
ADC_S3C2410_TSC_AUTO_PST | \
ADC_S3C2410_TSC_XY_PST(0))
/* Bit definitions for ADC_V2 */
#define ADC_V2_CON1_SOFT_RESET (1u << 2)
#define ADC_V2_CON2_OSEL (1u << 10)
#define ADC_V2_CON2_ESEL (1u << 9)
#define ADC_V2_CON2_HIGHF (1u << 8)
#define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4)
#define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0)
#define ADC_V2_CON2_ACH_MASK 0xF
#define MAX_ADC_V2_CHANNELS 10
#define MAX_ADC_V1_CHANNELS 8
#define MAX_EXYNOS3250_ADC_CHANNELS 2
#define MAX_EXYNOS4212_ADC_CHANNELS 4
#define MAX_S5PV210_ADC_CHANNELS 10
/* Bit definitions common for ADC_V1 and ADC_V2 */
#define ADC_CON_EN_START (1u << 0)
#define ADC_CON_EN_START_MASK (0x3 << 0)
#define ADC_DATX_PRESSED (1u << 15)
#define ADC_DATX_MASK 0xFFF
#define ADC_DATY_MASK 0xFFF
#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
#define EXYNOS_ADCV1_PHY_OFFSET 0x0718
#define EXYNOS_ADCV2_PHY_OFFSET 0x0720
struct exynos_adc {
struct exynos_adc_data *data;
struct device *dev;
struct input_dev *input;
void __iomem *regs;
struct regmap *pmu_map;
struct clk *clk;
struct clk *sclk;
unsigned int irq;
unsigned int tsirq;
unsigned int delay;
struct regulator *vdd;
struct completion completion;
u32 value;
unsigned int version;
bool ts_enabled;
bool read_ts;
u32 ts_x;
u32 ts_y;
/*
* Lock to protect from potential concurrent access to the
* completion callback during a manual conversion. For this driver
* a wait-callback is used to wait for the conversion result,
* so in the meantime no other read request (or conversion start)
* must be performed, otherwise it would interfere with the
* current conversion result.
*/
struct mutex lock;
};
struct exynos_adc_data {
int num_channels;
bool needs_sclk;
bool needs_adc_phy;
int phy_offset;
u32 mask;
void (*init_hw)(struct exynos_adc *info);
void (*exit_hw)(struct exynos_adc *info);
void (*clear_irq)(struct exynos_adc *info);
void (*start_conv)(struct exynos_adc *info, unsigned long addr);
};
static void exynos_adc_unprepare_clk(struct exynos_adc *info)
{
if (info->data->needs_sclk)
clk_unprepare(info->sclk);
clk_unprepare(info->clk);
}
static int exynos_adc_prepare_clk(struct exynos_adc *info)
{
int ret;
ret = clk_prepare(info->clk);
if (ret) {
dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
return ret;
}
if (info->data->needs_sclk) {
ret = clk_prepare(info->sclk);
if (ret) {
clk_unprepare(info->clk);
dev_err(info->dev,
"failed preparing sclk_adc clock: %d\n", ret);
return ret;
}
}
return 0;
}
static void exynos_adc_disable_clk(struct exynos_adc *info)
{
if (info->data->needs_sclk)
clk_disable(info->sclk);
clk_disable(info->clk);
}
static int exynos_adc_enable_clk(struct exynos_adc *info)
{
int ret;
ret = clk_enable(info->clk);
if (ret) {
dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
return ret;
}
if (info->data->needs_sclk) {
ret = clk_enable(info->sclk);
if (ret) {
clk_disable(info->clk);
dev_err(info->dev,
"failed enabling sclk_adc clock: %d\n", ret);
return ret;
}
}
return 0;
}
static void exynos_adc_v1_init_hw(struct exynos_adc *info)
{
u32 con1;
if (info->data->needs_adc_phy)
regmap_write(info->pmu_map, info->data->phy_offset, 1);
/* set default prescaler values and Enable prescaler */
con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
/* Enable 12-bit ADC resolution */
con1 |= ADC_V1_CON_RES;
writel(con1, ADC_V1_CON(info->regs));
/* set touchscreen delay */
writel(info->delay, ADC_V1_DLY(info->regs));
}
static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
{
u32 con;
if (info->data->needs_adc_phy)
regmap_write(info->pmu_map, info->data->phy_offset, 0);
con = readl(ADC_V1_CON(info->regs));
con |= ADC_V1_CON_STANDBY;
writel(con, ADC_V1_CON(info->regs));
}
static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
{
writel(1, ADC_V1_INTCLR(info->regs));
}
static void exynos_adc_v1_start_conv(struct exynos_adc *info,
unsigned long addr)
{
u32 con1;
writel(addr, ADC_V1_MUX(info->regs));
con1 = readl(ADC_V1_CON(info->regs));
writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
}
/* Exynos4212 and 4412 is like ADCv1 but with four channels only */
static const struct exynos_adc_data exynos4212_adc_data = {
.num_channels = MAX_EXYNOS4212_ADC_CHANNELS,
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.needs_adc_phy = true,
.phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
.clear_irq = exynos_adc_v1_clear_irq,
.start_conv = exynos_adc_v1_start_conv,
};
static const struct exynos_adc_data exynos_adc_v1_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.needs_adc_phy = true,
.phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
.clear_irq = exynos_adc_v1_clear_irq,
.start_conv = exynos_adc_v1_start_conv,
};
static const struct exynos_adc_data exynos_adc_s5pv210_data = {
.num_channels = MAX_S5PV210_ADC_CHANNELS,
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
.clear_irq = exynos_adc_v1_clear_irq,
.start_conv = exynos_adc_v1_start_conv,
};
static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
unsigned long addr)
{
u32 con1;
/* Enable 12 bit ADC resolution */
con1 = readl(ADC_V1_CON(info->regs));
con1 |= ADC_S3C2416_CON_RES_SEL;
writel(con1, ADC_V1_CON(info->regs));
/* Select channel for S3C2416 */
writel(addr, ADC_S3C2410_MUX(info->regs));
con1 = readl(ADC_V1_CON(info->regs));
writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
}
static struct exynos_adc_data const exynos_adc_s3c2416_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
.start_conv = exynos_adc_s3c2416_start_conv,
};
static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
unsigned long addr)
{
u32 con1;
/* Select channel for S3C2433 */
writel(addr, ADC_S3C2410_MUX(info->regs));
con1 = readl(ADC_V1_CON(info->regs));
writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
}
static struct exynos_adc_data const exynos_adc_s3c2443_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
.mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
.start_conv = exynos_adc_s3c2443_start_conv,
};
static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
unsigned long addr)
{
u32 con1;
con1 = readl(ADC_V1_CON(info->regs));
con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
con1 |= ADC_S3C2410_CON_SELMUX(addr);
writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
}
static struct exynos_adc_data const exynos_adc_s3c24xx_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
.mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
.start_conv = exynos_adc_s3c64xx_start_conv,
};
static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
.clear_irq = exynos_adc_v1_clear_irq,
.start_conv = exynos_adc_s3c64xx_start_conv,
};
static void exynos_adc_v2_init_hw(struct exynos_adc *info)
{
u32 con1, con2;
if (info->data->needs_adc_phy)
regmap_write(info->pmu_map, info->data->phy_offset, 1);
con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info->regs));
con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
writel(con2, ADC_V2_CON2(info->regs));
/* Enable interrupts */
writel(1, ADC_V2_INT_EN(info->regs));
}
static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
{
u32 con;
if (info->data->needs_adc_phy)
regmap_write(info->pmu_map, info->data->phy_offset, 0);
con = readl(ADC_V2_CON1(info->regs));
con &= ~ADC_CON_EN_START;
writel(con, ADC_V2_CON1(info->regs));
}
static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
{
writel(1, ADC_V2_INT_ST(info->regs));
}
static void exynos_adc_v2_start_conv(struct exynos_adc *info,
unsigned long addr)
{
u32 con1, con2;
con2 = readl(ADC_V2_CON2(info->regs));
con2 &= ~ADC_V2_CON2_ACH_MASK;
con2 |= ADC_V2_CON2_ACH_SEL(addr);
writel(con2, ADC_V2_CON2(info->regs));
con1 = readl(ADC_V2_CON1(info->regs));
writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
}
static const struct exynos_adc_data exynos_adc_v2_data = {
.num_channels = MAX_ADC_V2_CHANNELS,
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.needs_adc_phy = true,
.phy_offset = EXYNOS_ADCV2_PHY_OFFSET,
.init_hw = exynos_adc_v2_init_hw,
.exit_hw = exynos_adc_v2_exit_hw,
.clear_irq = exynos_adc_v2_clear_irq,
.start_conv = exynos_adc_v2_start_conv,
};
static const struct exynos_adc_data exynos3250_adc_data = {
.num_channels = MAX_EXYNOS3250_ADC_CHANNELS,
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.needs_sclk = true,
.needs_adc_phy = true,
.phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.init_hw = exynos_adc_v2_init_hw,
.exit_hw = exynos_adc_v2_exit_hw,
.clear_irq = exynos_adc_v2_clear_irq,
.start_conv = exynos_adc_v2_start_conv,
};
static void exynos_adc_exynos7_init_hw(struct exynos_adc *info)
{
u32 con1, con2;
con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info->regs));
con2 = readl(ADC_V2_CON2(info->regs));
con2 &= ~ADC_V2_CON2_C_TIME(7);
con2 |= ADC_V2_CON2_C_TIME(0);
writel(con2, ADC_V2_CON2(info->regs));
/* Enable interrupts */
writel(1, ADC_V2_INT_EN(info->regs));
}
static const struct exynos_adc_data exynos7_adc_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.init_hw = exynos_adc_exynos7_init_hw,
.exit_hw = exynos_adc_v2_exit_hw,
.clear_irq = exynos_adc_v2_clear_irq,
.start_conv = exynos_adc_v2_start_conv,
};
static const struct of_device_id exynos_adc_match[] = {
{
.compatible = "samsung,s3c2410-adc",
.data = &exynos_adc_s3c24xx_data,
}, {
.compatible = "samsung,s3c2416-adc",
.data = &exynos_adc_s3c2416_data,
}, {
.compatible = "samsung,s3c2440-adc",
.data = &exynos_adc_s3c24xx_data,
}, {
.compatible = "samsung,s3c2443-adc",
.data = &exynos_adc_s3c2443_data,
}, {
.compatible = "samsung,s3c6410-adc",
.data = &exynos_adc_s3c64xx_data,
}, {
.compatible = "samsung,s5pv210-adc",
.data = &exynos_adc_s5pv210_data,
}, {
.compatible = "samsung,exynos4212-adc",
.data = &exynos4212_adc_data,
}, {
.compatible = "samsung,exynos-adc-v1",
.data = &exynos_adc_v1_data,
}, {
.compatible = "samsung,exynos-adc-v2",
.data = &exynos_adc_v2_data,
}, {
.compatible = "samsung,exynos3250-adc",
.data = &exynos3250_adc_data,
}, {
.compatible = "samsung,exynos7-adc",
.data = &exynos7_adc_data,
},
{},
};
MODULE_DEVICE_TABLE(of, exynos_adc_match);
static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
{
const struct of_device_id *match;
match = of_match_node(exynos_adc_match, pdev->dev.of_node);
return (struct exynos_adc_data *)match->data;
}
static int exynos_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
struct exynos_adc *info = iio_priv(indio_dev);
unsigned long timeout;
int ret;
if (mask == IIO_CHAN_INFO_SCALE) {
ret = regulator_get_voltage(info->vdd);
if (ret < 0)
return ret;
/* Regulator voltage is in uV, but need mV */
*val = ret / 1000;
*val2 = info->data->mask;
return IIO_VAL_FRACTIONAL;
} else if (mask != IIO_CHAN_INFO_RAW) {
return -EINVAL;
}
mutex_lock(&info->lock);
reinit_completion(&info->completion);
/* Select the channel to be used and Trigger conversion */
if (info->data->start_conv)
info->data->start_conv(info, chan->address);
timeout = wait_for_completion_timeout(&info->completion,
EXYNOS_ADC_TIMEOUT);
if (timeout == 0) {
dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
if (info->data->init_hw)
info->data->init_hw(info);
ret = -ETIMEDOUT;
} else {
*val = info->value;
*val2 = 0;
ret = IIO_VAL_INT;
}
mutex_unlock(&info->lock);
return ret;
}
static int exynos_read_s3c64xx_ts(struct iio_dev *indio_dev, int *x, int *y)
{
struct exynos_adc *info = iio_priv(indio_dev);
unsigned long timeout;
int ret;
mutex_lock(&info->lock);
info->read_ts = true;
reinit_completion(&info->completion);
writel(ADC_S3C2410_TSC_PULL_UP_DISABLE | ADC_TSC_AUTOPST,
ADC_V1_TSC(info->regs));
/* Select the ts channel to be used and Trigger conversion */
info->data->start_conv(info, ADC_S3C2410_MUX_TS);
timeout = wait_for_completion_timeout(&info->completion,
EXYNOS_ADC_TIMEOUT);
if (timeout == 0) {
dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
if (info->data->init_hw)
info->data->init_hw(info);
ret = -ETIMEDOUT;
} else {
*x = info->ts_x;
*y = info->ts_y;
ret = 0;
}
info->read_ts = false;
mutex_unlock(&info->lock);
return ret;
}
static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
{
struct exynos_adc *info = dev_id;
u32 mask = info->data->mask;
/* Read value */
if (info->read_ts) {
info->ts_x = readl(ADC_V1_DATX(info->regs));
info->ts_y = readl(ADC_V1_DATY(info->regs));
writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs));
} else {
info->value = readl(ADC_V1_DATX(info->regs)) & mask;
}
/* clear irq */
if (info->data->clear_irq)
info->data->clear_irq(info);
complete(&info->completion);
return IRQ_HANDLED;
}
/*
* Here we (ab)use a threaded interrupt handler to stay running
* for as long as the touchscreen remains pressed, we report
* a new event with the latest data and then sleep until the
* next timer tick. This mirrors the behavior of the old
* driver, with much less code.
*/
static irqreturn_t exynos_ts_isr(int irq, void *dev_id)
{
struct exynos_adc *info = dev_id;
struct iio_dev *dev = dev_get_drvdata(info->dev);
u32 x, y;
bool pressed;
int ret;
while (READ_ONCE(info->ts_enabled)) {
ret = exynos_read_s3c64xx_ts(dev, &x, &y);
if (ret == -ETIMEDOUT)
break;
pressed = x & y & ADC_DATX_PRESSED;
if (!pressed) {
input_report_key(info->input, BTN_TOUCH, 0);
input_sync(info->input);
break;
}
input_report_abs(info->input, ABS_X, x & ADC_DATX_MASK);
input_report_abs(info->input, ABS_Y, y & ADC_DATY_MASK);
input_report_key(info->input, BTN_TOUCH, 1);
input_sync(info->input);
usleep_range(1000, 1100);
}
writel(0, ADC_V1_CLRINTPNDNUP(info->regs));
return IRQ_HANDLED;
}
static int exynos_adc_reg_access(struct iio_dev *indio_dev,
unsigned reg, unsigned writeval,
unsigned *readval)
{
struct exynos_adc *info = iio_priv(indio_dev);
if (readval == NULL)
return -EINVAL;
*readval = readl(info->regs + reg);
return 0;
}
static const struct iio_info exynos_adc_iio_info = {
.read_raw = &exynos_read_raw,
.debugfs_reg_access = &exynos_adc_reg_access,
};
#define ADC_CHANNEL(_index, _id) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = _index, \
.address = _index, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \
.datasheet_name = _id, \
}
static const struct iio_chan_spec exynos_adc_iio_channels[] = {
ADC_CHANNEL(0, "adc0"),
ADC_CHANNEL(1, "adc1"),
ADC_CHANNEL(2, "adc2"),
ADC_CHANNEL(3, "adc3"),
ADC_CHANNEL(4, "adc4"),
ADC_CHANNEL(5, "adc5"),
ADC_CHANNEL(6, "adc6"),
ADC_CHANNEL(7, "adc7"),
ADC_CHANNEL(8, "adc8"),
ADC_CHANNEL(9, "adc9"),
};
static int exynos_adc_remove_devices(struct device *dev, void *c)
{
struct platform_device *pdev = to_platform_device(dev);
platform_device_unregister(pdev);
return 0;
}
static int exynos_adc_ts_open(struct input_dev *dev)
{
struct exynos_adc *info = input_get_drvdata(dev);
WRITE_ONCE(info->ts_enabled, true);
enable_irq(info->tsirq);
return 0;
}
static void exynos_adc_ts_close(struct input_dev *dev)
{
struct exynos_adc *info = input_get_drvdata(dev);
WRITE_ONCE(info->ts_enabled, false);
disable_irq(info->tsirq);
}
static int exynos_adc_ts_init(struct exynos_adc *info)
{
int ret;
if (info->tsirq <= 0)
return -ENODEV;
info->input = input_allocate_device();
if (!info->input)
return -ENOMEM;
info->input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
info->input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
input_set_abs_params(info->input, ABS_X, 0, 0x3FF, 0, 0);
input_set_abs_params(info->input, ABS_Y, 0, 0x3FF, 0, 0);
info->input->name = "S3C24xx TouchScreen";
info->input->id.bustype = BUS_HOST;
info->input->open = exynos_adc_ts_open;
info->input->close = exynos_adc_ts_close;
input_set_drvdata(info->input, info);
ret = input_register_device(info->input);
if (ret) {
input_free_device(info->input);
return ret;
}
ret = request_threaded_irq(info->tsirq, NULL, exynos_ts_isr,
IRQF_ONESHOT | IRQF_NO_AUTOEN,
"touchscreen", info);
if (ret)
input_unregister_device(info->input);
return ret;
}
static int exynos_adc_probe(struct platform_device *pdev)
{
struct exynos_adc *info = NULL;
struct device_node *np = pdev->dev.of_node;
struct s3c2410_ts_mach_info *pdata = dev_get_platdata(&pdev->dev);
struct iio_dev *indio_dev = NULL;
bool has_ts = false;
int ret;
int irq;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
if (!indio_dev) {
dev_err(&pdev->dev, "failed allocating iio device\n");
return -ENOMEM;
}
info = iio_priv(indio_dev);
info->data = exynos_adc_get_data(pdev);
if (!info->data) {
dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
return -EINVAL;
}
info->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(info->regs))
return PTR_ERR(info->regs);
if (info->data->needs_adc_phy) {
info->pmu_map = syscon_regmap_lookup_by_phandle(
pdev->dev.of_node,
"samsung,syscon-phandle");
if (IS_ERR(info->pmu_map)) {
dev_err(&pdev->dev, "syscon regmap lookup failed.\n");
return PTR_ERR(info->pmu_map);
}
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
info->irq = irq;
irq = platform_get_irq(pdev, 1);
if (irq == -EPROBE_DEFER)
return irq;
info->tsirq = irq;
info->dev = &pdev->dev;
init_completion(&info->completion);
info->clk = devm_clk_get(&pdev->dev, "adc");
if (IS_ERR(info->clk)) {
dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
PTR_ERR(info->clk));
return PTR_ERR(info->clk);
}
if (info->data->needs_sclk) {
info->sclk = devm_clk_get(&pdev->dev, "sclk");
if (IS_ERR(info->sclk)) {
dev_err(&pdev->dev,
"failed getting sclk clock, err = %ld\n",
PTR_ERR(info->sclk));
return PTR_ERR(info->sclk);
}
}
info->vdd = devm_regulator_get(&pdev->dev, "vdd");
if (IS_ERR(info->vdd))
return dev_err_probe(&pdev->dev, PTR_ERR(info->vdd),
"failed getting regulator");
ret = regulator_enable(info->vdd);
if (ret)
return ret;
ret = exynos_adc_prepare_clk(info);
if (ret)
goto err_disable_reg;
ret = exynos_adc_enable_clk(info);
if (ret)
goto err_unprepare_clk;
platform_set_drvdata(pdev, indio_dev);
indio_dev->name = dev_name(&pdev->dev);
indio_dev->info = &exynos_adc_iio_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = exynos_adc_iio_channels;
indio_dev->num_channels = info->data->num_channels;
mutex_init(&info->lock);
ret = request_irq(info->irq, exynos_adc_isr,
0, dev_name(&pdev->dev), info);
if (ret < 0) {
dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
info->irq);
goto err_disable_clk;
}
ret = iio_device_register(indio_dev);
if (ret)
goto err_irq;
if (info->data->init_hw)
info->data->init_hw(info);
/* leave out any TS related code if unreachable */
if (IS_REACHABLE(CONFIG_INPUT)) {
has_ts = of_property_read_bool(pdev->dev.of_node,
"has-touchscreen") || pdata;
}
if (pdata)
info->delay = pdata->delay;
else
info->delay = 10000;
if (has_ts)
ret = exynos_adc_ts_init(info);
if (ret)
goto err_iio;
ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "failed adding child nodes\n");
goto err_of_populate;
}
return 0;
err_of_populate:
device_for_each_child(&indio_dev->dev, NULL,
exynos_adc_remove_devices);
if (has_ts) {
input_unregister_device(info->input);
free_irq(info->tsirq, info);
}
err_iio:
iio_device_unregister(indio_dev);
err_irq:
free_irq(info->irq, info);
err_disable_clk:
if (info->data->exit_hw)
info->data->exit_hw(info);
exynos_adc_disable_clk(info);
err_unprepare_clk:
exynos_adc_unprepare_clk(info);
err_disable_reg:
regulator_disable(info->vdd);
return ret;
}
static int exynos_adc_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct exynos_adc *info = iio_priv(indio_dev);
if (IS_REACHABLE(CONFIG_INPUT) && info->input) {
free_irq(info->tsirq, info);
input_unregister_device(info->input);
}
device_for_each_child(&indio_dev->dev, NULL,
exynos_adc_remove_devices);
iio_device_unregister(indio_dev);
free_irq(info->irq, info);
if (info->data->exit_hw)
info->data->exit_hw(info);
exynos_adc_disable_clk(info);
exynos_adc_unprepare_clk(info);
regulator_disable(info->vdd);
return 0;
}
static int exynos_adc_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct exynos_adc *info = iio_priv(indio_dev);
if (info->data->exit_hw)
info->data->exit_hw(info);
exynos_adc_disable_clk(info);
regulator_disable(info->vdd);
return 0;
}
static int exynos_adc_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct exynos_adc *info = iio_priv(indio_dev);
int ret;
ret = regulator_enable(info->vdd);
if (ret)
return ret;
ret = exynos_adc_enable_clk(info);
if (ret)
return ret;
if (info->data->init_hw)
info->data->init_hw(info);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops, exynos_adc_suspend,
exynos_adc_resume);
static struct platform_driver exynos_adc_driver = {
.probe = exynos_adc_probe,
.remove = exynos_adc_remove,
.driver = {
.name = "exynos-adc",
.of_match_table = exynos_adc_match,
.pm = pm_sleep_ptr(&exynos_adc_pm_ops),
},
};
module_platform_driver(exynos_adc_driver);
MODULE_AUTHOR("Naveen Krishna Chatradhi <[email protected]>");
MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/exynos_adc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Freescale MXS LRADC ADC driver
*
* Copyright (c) 2012 DENX Software Engineering, GmbH.
* Copyright (c) 2017 Ksenija Stanojevic <[email protected]>
*
* Authors:
* Marek Vasut <[email protected]>
* Ksenija Stanojevic <[email protected]>
*/
#include <linux/completion.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mxs-lradc.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/sysfs.h>
/*
* Make this runtime configurable if necessary. Currently, if the buffered mode
* is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
* triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
* seconds. The result is that the samples arrive every 500mS.
*/
#define LRADC_DELAY_TIMER_PER 200
#define LRADC_DELAY_TIMER_LOOP 5
#define VREF_MV_BASE 1850
static const char *mx23_lradc_adc_irq_names[] = {
"mxs-lradc-channel0",
"mxs-lradc-channel1",
"mxs-lradc-channel2",
"mxs-lradc-channel3",
"mxs-lradc-channel4",
"mxs-lradc-channel5",
};
static const char *mx28_lradc_adc_irq_names[] = {
"mxs-lradc-thresh0",
"mxs-lradc-thresh1",
"mxs-lradc-channel0",
"mxs-lradc-channel1",
"mxs-lradc-channel2",
"mxs-lradc-channel3",
"mxs-lradc-channel4",
"mxs-lradc-channel5",
"mxs-lradc-button0",
"mxs-lradc-button1",
};
static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = {
[IMX23_LRADC] = {
VREF_MV_BASE, /* CH0 */
VREF_MV_BASE, /* CH1 */
VREF_MV_BASE, /* CH2 */
VREF_MV_BASE, /* CH3 */
VREF_MV_BASE, /* CH4 */
VREF_MV_BASE, /* CH5 */
VREF_MV_BASE * 2, /* CH6 VDDIO */
VREF_MV_BASE * 4, /* CH7 VBATT */
VREF_MV_BASE, /* CH8 Temp sense 0 */
VREF_MV_BASE, /* CH9 Temp sense 1 */
VREF_MV_BASE, /* CH10 */
VREF_MV_BASE, /* CH11 */
VREF_MV_BASE, /* CH12 USB_DP */
VREF_MV_BASE, /* CH13 USB_DN */
VREF_MV_BASE, /* CH14 VBG */
VREF_MV_BASE * 4, /* CH15 VDD5V */
},
[IMX28_LRADC] = {
VREF_MV_BASE, /* CH0 */
VREF_MV_BASE, /* CH1 */
VREF_MV_BASE, /* CH2 */
VREF_MV_BASE, /* CH3 */
VREF_MV_BASE, /* CH4 */
VREF_MV_BASE, /* CH5 */
VREF_MV_BASE, /* CH6 */
VREF_MV_BASE * 4, /* CH7 VBATT */
VREF_MV_BASE, /* CH8 Temp sense 0 */
VREF_MV_BASE, /* CH9 Temp sense 1 */
VREF_MV_BASE * 2, /* CH10 VDDIO */
VREF_MV_BASE, /* CH11 VTH */
VREF_MV_BASE * 2, /* CH12 VDDA */
VREF_MV_BASE, /* CH13 VDDD */
VREF_MV_BASE, /* CH14 VBG */
VREF_MV_BASE * 4, /* CH15 VDD5V */
},
};
enum mxs_lradc_divbytwo {
MXS_LRADC_DIV_DISABLED = 0,
MXS_LRADC_DIV_ENABLED,
};
struct mxs_lradc_scale {
unsigned int integer;
unsigned int nano;
};
struct mxs_lradc_adc {
struct mxs_lradc *lradc;
struct device *dev;
void __iomem *base;
/* Maximum of 8 channels + 8 byte ts */
u32 buffer[10] __aligned(8);
struct iio_trigger *trig;
struct completion completion;
spinlock_t lock;
const u32 *vref_mv;
struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
unsigned long is_divided;
};
/* Raw I/O operations */
static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan,
int *val)
{
struct mxs_lradc_adc *adc = iio_priv(iio_dev);
struct mxs_lradc *lradc = adc->lradc;
int ret;
/*
* See if there is no buffered operation in progress. If there is simply
* bail out. This can be improved to support both buffered and raw IO at
* the same time, yet the code becomes horribly complicated. Therefore I
* applied KISS principle here.
*/
ret = iio_device_claim_direct_mode(iio_dev);
if (ret)
return ret;
reinit_completion(&adc->completion);
/*
* No buffered operation in progress, map the channel and trigger it.
* Virtual channel 0 is always used here as the others are always not
* used if doing raw sampling.
*/
if (lradc->soc == IMX28_LRADC)
writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
/* Enable / disable the divider per requirement */
if (test_bit(chan, &adc->is_divided))
writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
else
writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
/* Clean the slot's previous content, then set new one. */
writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
writel(0, adc->base + LRADC_CH(0));
/* Enable the IRQ and start sampling the channel. */
writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
/* Wait for completion on the channel, 1 second max. */
ret = wait_for_completion_killable_timeout(&adc->completion, HZ);
if (!ret)
ret = -ETIMEDOUT;
if (ret < 0)
goto err;
/* Read the data. */
*val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
ret = IIO_VAL_INT;
err:
writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
iio_device_release_direct_mode(iio_dev);
return ret;
}
static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val)
{
int ret, min, max;
ret = mxs_lradc_adc_read_single(iio_dev, 8, &min);
if (ret != IIO_VAL_INT)
return ret;
ret = mxs_lradc_adc_read_single(iio_dev, 9, &max);
if (ret != IIO_VAL_INT)
return ret;
*val = max - min;
return IIO_VAL_INT;
}
static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev,
const struct iio_chan_spec *chan,
int *val, int *val2, long m)
{
struct mxs_lradc_adc *adc = iio_priv(iio_dev);
switch (m) {
case IIO_CHAN_INFO_RAW:
if (chan->type == IIO_TEMP)
return mxs_lradc_adc_read_temp(iio_dev, val);
return mxs_lradc_adc_read_single(iio_dev, chan->channel, val);
case IIO_CHAN_INFO_SCALE:
if (chan->type == IIO_TEMP) {
/*
* From the datasheet, we have to multiply by 1.012 and
* divide by 4
*/
*val = 0;
*val2 = 253000;
return IIO_VAL_INT_PLUS_MICRO;
}
*val = adc->vref_mv[chan->channel];
*val2 = chan->scan_type.realbits -
test_bit(chan->channel, &adc->is_divided);
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_OFFSET:
if (chan->type == IIO_TEMP) {
/*
* The calculated value from the ADC is in Kelvin, we
* want Celsius for hwmon so the offset is -273.15
* The offset is applied before scaling so it is
* actually -213.15 * 4 / 1.012 = -1079.644268
*/
*val = -1079;
*val2 = 644268;
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
default:
break;
}
return -EINVAL;
}
static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev,
const struct iio_chan_spec *chan,
int val, int val2, long m)
{
struct mxs_lradc_adc *adc = iio_priv(iio_dev);
struct mxs_lradc_scale *scale_avail =
adc->scale_avail[chan->channel];
int ret;
ret = iio_device_claim_direct_mode(iio_dev);
if (ret)
return ret;
switch (m) {
case IIO_CHAN_INFO_SCALE:
ret = -EINVAL;
if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
/* divider by two disabled */
clear_bit(chan->channel, &adc->is_divided);
ret = 0;
} else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
/* divider by two enabled */
set_bit(chan->channel, &adc->is_divided);
ret = 0;
}
break;
default:
ret = -EINVAL;
break;
}
iio_device_release_direct_mode(iio_dev);
return ret;
}
static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev,
const struct iio_chan_spec *chan,
long m)
{
return IIO_VAL_INT_PLUS_NANO;
}
static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *iio = dev_to_iio_dev(dev);
struct mxs_lradc_adc *adc = iio_priv(iio);
struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
int i, ch, len = 0;
ch = iio_attr->address;
for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++)
len += sprintf(buf + len, "%u.%09u ",
adc->scale_avail[ch][i].integer,
adc->scale_avail[ch][i].nano);
len += sprintf(buf + len, "\n");
return len;
}
#define SHOW_SCALE_AVAILABLE_ATTR(ch)\
IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\
mxs_lradc_adc_show_scale_avail, NULL, ch)
static SHOW_SCALE_AVAILABLE_ATTR(0);
static SHOW_SCALE_AVAILABLE_ATTR(1);
static SHOW_SCALE_AVAILABLE_ATTR(2);
static SHOW_SCALE_AVAILABLE_ATTR(3);
static SHOW_SCALE_AVAILABLE_ATTR(4);
static SHOW_SCALE_AVAILABLE_ATTR(5);
static SHOW_SCALE_AVAILABLE_ATTR(6);
static SHOW_SCALE_AVAILABLE_ATTR(7);
static SHOW_SCALE_AVAILABLE_ATTR(10);
static SHOW_SCALE_AVAILABLE_ATTR(11);
static SHOW_SCALE_AVAILABLE_ATTR(12);
static SHOW_SCALE_AVAILABLE_ATTR(13);
static SHOW_SCALE_AVAILABLE_ATTR(14);
static SHOW_SCALE_AVAILABLE_ATTR(15);
static struct attribute *mxs_lradc_adc_attributes[] = {
&iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
&iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
NULL
};
static const struct attribute_group mxs_lradc_adc_attribute_group = {
.attrs = mxs_lradc_adc_attributes,
};
static const struct iio_info mxs_lradc_adc_iio_info = {
.read_raw = mxs_lradc_adc_read_raw,
.write_raw = mxs_lradc_adc_write_raw,
.write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt,
.attrs = &mxs_lradc_adc_attribute_group,
};
/* IRQ Handling */
static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data)
{
struct iio_dev *iio = data;
struct mxs_lradc_adc *adc = iio_priv(iio);
struct mxs_lradc *lradc = adc->lradc;
unsigned long reg = readl(adc->base + LRADC_CTRL1);
unsigned long flags;
if (!(reg & mxs_lradc_irq_mask(lradc)))
return IRQ_NONE;
if (iio_buffer_enabled(iio)) {
if (reg & lradc->buffer_vchans) {
spin_lock_irqsave(&adc->lock, flags);
iio_trigger_poll(iio->trig);
spin_unlock_irqrestore(&adc->lock, flags);
}
} else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
complete(&adc->completion);
}
writel(reg & mxs_lradc_irq_mask(lradc),
adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
return IRQ_HANDLED;
}
/* Trigger handling */
static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *iio = pf->indio_dev;
struct mxs_lradc_adc *adc = iio_priv(iio);
const u32 chan_value = LRADC_CH_ACCUMULATE |
((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
unsigned int i, j = 0;
for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
adc->buffer[j] = readl(adc->base + LRADC_CH(j));
writel(chan_value, adc->base + LRADC_CH(j));
adc->buffer[j] &= LRADC_CH_VALUE_MASK;
adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
j++;
}
iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp);
iio_trigger_notify_done(iio->trig);
return IRQ_HANDLED;
}
static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
{
struct iio_dev *iio = iio_trigger_get_drvdata(trig);
struct mxs_lradc_adc *adc = iio_priv(iio);
const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st));
return 0;
}
static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
.set_trigger_state = &mxs_lradc_adc_configure_trigger,
};
static int mxs_lradc_adc_trigger_init(struct iio_dev *iio)
{
int ret;
struct iio_trigger *trig;
struct mxs_lradc_adc *adc = iio_priv(iio);
trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name,
iio_device_id(iio));
if (!trig)
return -ENOMEM;
trig->dev.parent = adc->dev;
iio_trigger_set_drvdata(trig, iio);
trig->ops = &mxs_lradc_adc_trigger_ops;
ret = iio_trigger_register(trig);
if (ret)
return ret;
adc->trig = trig;
return 0;
}
static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio)
{
struct mxs_lradc_adc *adc = iio_priv(iio);
iio_trigger_unregister(adc->trig);
}
static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio)
{
struct mxs_lradc_adc *adc = iio_priv(iio);
struct mxs_lradc *lradc = adc->lradc;
int chan, ofs = 0;
unsigned long enable = 0;
u32 ctrl4_set = 0;
u32 ctrl4_clr = 0;
u32 ctrl1_irq = 0;
const u32 chan_value = LRADC_CH_ACCUMULATE |
((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
if (lradc->soc == IMX28_LRADC)
writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
writel(lradc->buffer_vchans,
adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
writel(chan_value, adc->base + LRADC_CH(ofs));
bitmap_set(&enable, ofs, 1);
ofs++;
}
writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
return 0;
}
static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio)
{
struct mxs_lradc_adc *adc = iio_priv(iio);
struct mxs_lradc *lradc = adc->lradc;
writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
writel(lradc->buffer_vchans,
adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
if (lradc->soc == IMX28_LRADC)
writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
return 0;
}
static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio,
const unsigned long *mask)
{
struct mxs_lradc_adc *adc = iio_priv(iio);
struct mxs_lradc *lradc = adc->lradc;
const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
int rsvd_chans = 0;
unsigned long rsvd_mask = 0;
if (lradc->use_touchbutton)
rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE)
rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE)
rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
if (lradc->use_touchbutton)
rsvd_chans++;
if (lradc->touchscreen_wire)
rsvd_chans += 2;
/* Test for attempts to map channels with special mode of operation. */
if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
return false;
/* Test for attempts to map more channels then available slots. */
if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
return false;
return true;
}
static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = {
.preenable = &mxs_lradc_adc_buffer_preenable,
.postdisable = &mxs_lradc_adc_buffer_postdisable,
.validate_scan_mask = &mxs_lradc_adc_validate_scan_mask,
};
/* Driver initialization */
#define MXS_ADC_CHAN(idx, chan_type, name) { \
.type = (chan_type), \
.indexed = 1, \
.scan_index = (idx), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.channel = (idx), \
.address = (idx), \
.scan_type = { \
.sign = 'u', \
.realbits = LRADC_RESOLUTION, \
.storagebits = 32, \
}, \
.datasheet_name = (name), \
}
static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
/* Combined Temperature sensors */
{
.type = IIO_TEMP,
.indexed = 1,
.scan_index = 8,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE),
.channel = 8,
.scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
.datasheet_name = "TEMP_DIE",
},
/* Hidden channel to keep indexes */
{
.type = IIO_TEMP,
.indexed = 1,
.scan_index = -1,
.channel = 9,
},
MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
};
static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
/* Combined Temperature sensors */
{
.type = IIO_TEMP,
.indexed = 1,
.scan_index = 8,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE),
.channel = 8,
.scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
.datasheet_name = "TEMP_DIE",
},
/* Hidden channel to keep indexes */
{
.type = IIO_TEMP,
.indexed = 1,
.scan_index = -1,
.channel = 9,
},
MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
};
static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc)
{
/* The ADC always uses DELAY CHANNEL 0. */
const u32 adc_cfg =
(1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
(LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
/* Configure DELAY CHANNEL 0 for generic ADC sampling. */
writel(adc_cfg, adc->base + LRADC_DELAY(0));
/*
* Start internal temperature sensing by clearing bit
* HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared
* after power up.
*/
writel(0, adc->base + LRADC_CTRL2);
}
static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc)
{
writel(0, adc->base + LRADC_DELAY(0));
}
static int mxs_lradc_adc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mxs_lradc *lradc = dev_get_drvdata(dev->parent);
struct mxs_lradc_adc *adc;
struct iio_dev *iio;
struct resource *iores;
int ret, irq, virq, i, s, n;
u64 scale_uv;
const char **irq_name;
/* Allocate the IIO device. */
iio = devm_iio_device_alloc(dev, sizeof(*adc));
if (!iio) {
dev_err(dev, "Failed to allocate IIO device\n");
return -ENOMEM;
}
adc = iio_priv(iio);
adc->lradc = lradc;
adc->dev = dev;
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!iores)
return -EINVAL;
adc->base = devm_ioremap(dev, iores->start, resource_size(iores));
if (!adc->base)
return -ENOMEM;
init_completion(&adc->completion);
spin_lock_init(&adc->lock);
platform_set_drvdata(pdev, iio);
iio->name = pdev->name;
iio->dev.of_node = dev->parent->of_node;
iio->info = &mxs_lradc_adc_iio_info;
iio->modes = INDIO_DIRECT_MODE;
iio->masklength = LRADC_MAX_TOTAL_CHANS;
if (lradc->soc == IMX23_LRADC) {
iio->channels = mx23_lradc_chan_spec;
iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
irq_name = mx23_lradc_adc_irq_names;
n = ARRAY_SIZE(mx23_lradc_adc_irq_names);
} else {
iio->channels = mx28_lradc_chan_spec;
iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
irq_name = mx28_lradc_adc_irq_names;
n = ARRAY_SIZE(mx28_lradc_adc_irq_names);
}
ret = stmp_reset_block(adc->base);
if (ret)
return ret;
for (i = 0; i < n; i++) {
irq = platform_get_irq_byname(pdev, irq_name[i]);
if (irq < 0)
return irq;
virq = irq_of_parse_and_map(dev->parent->of_node, irq);
ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq,
0, irq_name[i], iio);
if (ret)
return ret;
}
ret = mxs_lradc_adc_trigger_init(iio);
if (ret)
return ret;
ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
&mxs_lradc_adc_trigger_handler,
&mxs_lradc_adc_buffer_ops);
if (ret)
goto err_trig;
adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc];
/* Populate available ADC input ranges */
for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) {
/*
* [s=0] = optional divider by two disabled (default)
* [s=1] = optional divider by two enabled
*
* The scale is calculated by doing:
* Vref >> (realbits - s)
* which multiplies by two on the second component
* of the array.
*/
scale_uv = ((u64)adc->vref_mv[i] * 100000000) >>
(LRADC_RESOLUTION - s);
adc->scale_avail[i][s].nano =
do_div(scale_uv, 100000000) * 10;
adc->scale_avail[i][s].integer = scale_uv;
}
}
/* Configure the hardware. */
mxs_lradc_adc_hw_init(adc);
/* Register IIO device. */
ret = iio_device_register(iio);
if (ret) {
dev_err(dev, "Failed to register IIO device\n");
goto err_dev;
}
return 0;
err_dev:
mxs_lradc_adc_hw_stop(adc);
iio_triggered_buffer_cleanup(iio);
err_trig:
mxs_lradc_adc_trigger_remove(iio);
return ret;
}
static int mxs_lradc_adc_remove(struct platform_device *pdev)
{
struct iio_dev *iio = platform_get_drvdata(pdev);
struct mxs_lradc_adc *adc = iio_priv(iio);
iio_device_unregister(iio);
mxs_lradc_adc_hw_stop(adc);
iio_triggered_buffer_cleanup(iio);
mxs_lradc_adc_trigger_remove(iio);
return 0;
}
static struct platform_driver mxs_lradc_adc_driver = {
.driver = {
.name = "mxs-lradc-adc",
},
.probe = mxs_lradc_adc_probe,
.remove = mxs_lradc_adc_remove,
};
module_platform_driver(mxs_lradc_adc_driver);
MODULE_AUTHOR("Marek Vasut <[email protected]>");
MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mxs-lradc-adc");
| linux-master | drivers/iio/adc/mxs-lradc-adc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DA9150 GPADC Driver
*
* Copyright (c) 2014 Dialog Semiconductor
*
* Author: Adam Thomson <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/completion.h>
#include <linux/iio/iio.h>
#include <linux/iio/machine.h>
#include <linux/iio/driver.h>
#include <linux/mfd/da9150/core.h>
#include <linux/mfd/da9150/registers.h>
/* Channels */
enum da9150_gpadc_hw_channel {
DA9150_GPADC_HW_CHAN_GPIOA_2V = 0,
DA9150_GPADC_HW_CHAN_GPIOA_2V_,
DA9150_GPADC_HW_CHAN_GPIOB_2V,
DA9150_GPADC_HW_CHAN_GPIOB_2V_,
DA9150_GPADC_HW_CHAN_GPIOC_2V,
DA9150_GPADC_HW_CHAN_GPIOC_2V_,
DA9150_GPADC_HW_CHAN_GPIOD_2V,
DA9150_GPADC_HW_CHAN_GPIOD_2V_,
DA9150_GPADC_HW_CHAN_IBUS_SENSE,
DA9150_GPADC_HW_CHAN_IBUS_SENSE_,
DA9150_GPADC_HW_CHAN_VBUS_DIV,
DA9150_GPADC_HW_CHAN_VBUS_DIV_,
DA9150_GPADC_HW_CHAN_ID,
DA9150_GPADC_HW_CHAN_ID_,
DA9150_GPADC_HW_CHAN_VSYS,
DA9150_GPADC_HW_CHAN_VSYS_,
DA9150_GPADC_HW_CHAN_GPIOA_6V,
DA9150_GPADC_HW_CHAN_GPIOA_6V_,
DA9150_GPADC_HW_CHAN_GPIOB_6V,
DA9150_GPADC_HW_CHAN_GPIOB_6V_,
DA9150_GPADC_HW_CHAN_GPIOC_6V,
DA9150_GPADC_HW_CHAN_GPIOC_6V_,
DA9150_GPADC_HW_CHAN_GPIOD_6V,
DA9150_GPADC_HW_CHAN_GPIOD_6V_,
DA9150_GPADC_HW_CHAN_VBAT,
DA9150_GPADC_HW_CHAN_VBAT_,
DA9150_GPADC_HW_CHAN_TBAT,
DA9150_GPADC_HW_CHAN_TBAT_,
DA9150_GPADC_HW_CHAN_TJUNC_CORE,
DA9150_GPADC_HW_CHAN_TJUNC_CORE_,
DA9150_GPADC_HW_CHAN_TJUNC_OVP,
DA9150_GPADC_HW_CHAN_TJUNC_OVP_,
};
enum da9150_gpadc_channel {
DA9150_GPADC_CHAN_GPIOA = 0,
DA9150_GPADC_CHAN_GPIOB,
DA9150_GPADC_CHAN_GPIOC,
DA9150_GPADC_CHAN_GPIOD,
DA9150_GPADC_CHAN_IBUS,
DA9150_GPADC_CHAN_VBUS,
DA9150_GPADC_CHAN_VSYS,
DA9150_GPADC_CHAN_VBAT,
DA9150_GPADC_CHAN_TBAT,
DA9150_GPADC_CHAN_TJUNC_CORE,
DA9150_GPADC_CHAN_TJUNC_OVP,
};
/* Private data */
struct da9150_gpadc {
struct da9150 *da9150;
struct device *dev;
struct mutex lock;
struct completion complete;
};
static irqreturn_t da9150_gpadc_irq(int irq, void *data)
{
struct da9150_gpadc *gpadc = data;
complete(&gpadc->complete);
return IRQ_HANDLED;
}
static int da9150_gpadc_read_adc(struct da9150_gpadc *gpadc, int hw_chan)
{
u8 result_regs[2];
int result;
mutex_lock(&gpadc->lock);
/* Set channel & enable measurement */
da9150_reg_write(gpadc->da9150, DA9150_GPADC_MAN,
(DA9150_GPADC_EN_MASK |
hw_chan << DA9150_GPADC_MUX_SHIFT));
/* Consume left-over completion from a previous timeout */
try_wait_for_completion(&gpadc->complete);
/* Check for actual completion */
wait_for_completion_timeout(&gpadc->complete, msecs_to_jiffies(5));
/* Read result and status from device */
da9150_bulk_read(gpadc->da9150, DA9150_GPADC_RES_A, 2, result_regs);
mutex_unlock(&gpadc->lock);
/* Check to make sure device really has completed reading */
if (result_regs[1] & DA9150_GPADC_RUN_MASK) {
dev_err(gpadc->dev, "Timeout on channel %d of GPADC\n",
hw_chan);
return -ETIMEDOUT;
}
/* LSBs - 2 bits */
result = (result_regs[1] & DA9150_GPADC_RES_L_MASK) >>
DA9150_GPADC_RES_L_SHIFT;
/* MSBs - 8 bits */
result |= result_regs[0] << DA9150_GPADC_RES_L_BITS;
return result;
}
static inline int da9150_gpadc_gpio_6v_voltage_now(int raw_val)
{
/* Convert to mV */
return (6 * ((raw_val * 1000) + 500)) / 1024;
}
static inline int da9150_gpadc_ibus_current_avg(int raw_val)
{
/* Convert to mA */
return (4 * ((raw_val * 1000) + 500)) / 2048;
}
static inline int da9150_gpadc_vbus_21v_voltage_now(int raw_val)
{
/* Convert to mV */
return (21 * ((raw_val * 1000) + 500)) / 1024;
}
static inline int da9150_gpadc_vsys_6v_voltage_now(int raw_val)
{
/* Convert to mV */
return (3 * ((raw_val * 1000) + 500)) / 512;
}
static int da9150_gpadc_read_processed(struct da9150_gpadc *gpadc, int channel,
int hw_chan, int *val)
{
int raw_val;
raw_val = da9150_gpadc_read_adc(gpadc, hw_chan);
if (raw_val < 0)
return raw_val;
switch (channel) {
case DA9150_GPADC_CHAN_GPIOA:
case DA9150_GPADC_CHAN_GPIOB:
case DA9150_GPADC_CHAN_GPIOC:
case DA9150_GPADC_CHAN_GPIOD:
*val = da9150_gpadc_gpio_6v_voltage_now(raw_val);
break;
case DA9150_GPADC_CHAN_IBUS:
*val = da9150_gpadc_ibus_current_avg(raw_val);
break;
case DA9150_GPADC_CHAN_VBUS:
*val = da9150_gpadc_vbus_21v_voltage_now(raw_val);
break;
case DA9150_GPADC_CHAN_VSYS:
*val = da9150_gpadc_vsys_6v_voltage_now(raw_val);
break;
default:
/* No processing for other channels so return raw value */
*val = raw_val;
break;
}
return IIO_VAL_INT;
}
static int da9150_gpadc_read_scale(int channel, int *val, int *val2)
{
switch (channel) {
case DA9150_GPADC_CHAN_VBAT:
*val = 2932;
*val2 = 1000;
return IIO_VAL_FRACTIONAL;
case DA9150_GPADC_CHAN_TJUNC_CORE:
case DA9150_GPADC_CHAN_TJUNC_OVP:
*val = 1000000;
*val2 = 4420;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
}
static int da9150_gpadc_read_offset(int channel, int *val)
{
switch (channel) {
case DA9150_GPADC_CHAN_VBAT:
*val = 1500000 / 2932;
return IIO_VAL_INT;
case DA9150_GPADC_CHAN_TJUNC_CORE:
case DA9150_GPADC_CHAN_TJUNC_OVP:
*val = -144;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int da9150_gpadc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct da9150_gpadc *gpadc = iio_priv(indio_dev);
if ((chan->channel < DA9150_GPADC_CHAN_GPIOA) ||
(chan->channel > DA9150_GPADC_CHAN_TJUNC_OVP))
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_PROCESSED:
return da9150_gpadc_read_processed(gpadc, chan->channel,
chan->address, val);
case IIO_CHAN_INFO_SCALE:
return da9150_gpadc_read_scale(chan->channel, val, val2);
case IIO_CHAN_INFO_OFFSET:
return da9150_gpadc_read_offset(chan->channel, val);
default:
return -EINVAL;
}
}
static const struct iio_info da9150_gpadc_info = {
.read_raw = &da9150_gpadc_read_raw,
};
#define DA9150_GPADC_CHANNEL(_id, _hw_id, _type, chan_info, \
_ext_name) { \
.type = _type, \
.indexed = 1, \
.channel = DA9150_GPADC_CHAN_##_id, \
.address = DA9150_GPADC_HW_CHAN_##_hw_id, \
.info_mask_separate = chan_info, \
.extend_name = _ext_name, \
.datasheet_name = #_id, \
}
#define DA9150_GPADC_CHANNEL_RAW(_id, _hw_id, _type, _ext_name) \
DA9150_GPADC_CHANNEL(_id, _hw_id, _type, \
BIT(IIO_CHAN_INFO_RAW), _ext_name)
#define DA9150_GPADC_CHANNEL_SCALED(_id, _hw_id, _type, _ext_name) \
DA9150_GPADC_CHANNEL(_id, _hw_id, _type, \
BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET), \
_ext_name)
#define DA9150_GPADC_CHANNEL_PROCESSED(_id, _hw_id, _type, _ext_name) \
DA9150_GPADC_CHANNEL(_id, _hw_id, _type, \
BIT(IIO_CHAN_INFO_PROCESSED), _ext_name)
/* Supported channels */
static const struct iio_chan_spec da9150_gpadc_channels[] = {
DA9150_GPADC_CHANNEL_PROCESSED(GPIOA, GPIOA_6V, IIO_VOLTAGE, NULL),
DA9150_GPADC_CHANNEL_PROCESSED(GPIOB, GPIOB_6V, IIO_VOLTAGE, NULL),
DA9150_GPADC_CHANNEL_PROCESSED(GPIOC, GPIOC_6V, IIO_VOLTAGE, NULL),
DA9150_GPADC_CHANNEL_PROCESSED(GPIOD, GPIOD_6V, IIO_VOLTAGE, NULL),
DA9150_GPADC_CHANNEL_PROCESSED(IBUS, IBUS_SENSE, IIO_CURRENT, "ibus"),
DA9150_GPADC_CHANNEL_PROCESSED(VBUS, VBUS_DIV_, IIO_VOLTAGE, "vbus"),
DA9150_GPADC_CHANNEL_PROCESSED(VSYS, VSYS, IIO_VOLTAGE, "vsys"),
DA9150_GPADC_CHANNEL_SCALED(VBAT, VBAT, IIO_VOLTAGE, "vbat"),
DA9150_GPADC_CHANNEL_RAW(TBAT, TBAT, IIO_VOLTAGE, "tbat"),
DA9150_GPADC_CHANNEL_SCALED(TJUNC_CORE, TJUNC_CORE, IIO_TEMP,
"tjunc_core"),
DA9150_GPADC_CHANNEL_SCALED(TJUNC_OVP, TJUNC_OVP, IIO_TEMP,
"tjunc_ovp"),
};
/* Default maps used by da9150-charger */
static struct iio_map da9150_gpadc_default_maps[] = {
{
.consumer_dev_name = "da9150-charger",
.consumer_channel = "CHAN_IBUS",
.adc_channel_label = "IBUS",
},
{
.consumer_dev_name = "da9150-charger",
.consumer_channel = "CHAN_VBUS",
.adc_channel_label = "VBUS",
},
{
.consumer_dev_name = "da9150-charger",
.consumer_channel = "CHAN_TJUNC",
.adc_channel_label = "TJUNC_CORE",
},
{
.consumer_dev_name = "da9150-charger",
.consumer_channel = "CHAN_VBAT",
.adc_channel_label = "VBAT",
},
{},
};
static int da9150_gpadc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct da9150 *da9150 = dev_get_drvdata(dev->parent);
struct da9150_gpadc *gpadc;
struct iio_dev *indio_dev;
int irq, ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*gpadc));
if (!indio_dev) {
dev_err(&pdev->dev, "Failed to allocate IIO device\n");
return -ENOMEM;
}
gpadc = iio_priv(indio_dev);
gpadc->da9150 = da9150;
gpadc->dev = dev;
mutex_init(&gpadc->lock);
init_completion(&gpadc->complete);
irq = platform_get_irq_byname(pdev, "GPADC");
if (irq < 0)
return irq;
ret = devm_request_threaded_irq(dev, irq, NULL, da9150_gpadc_irq,
IRQF_ONESHOT, "GPADC", gpadc);
if (ret) {
dev_err(dev, "Failed to request IRQ %d: %d\n", irq, ret);
return ret;
}
ret = devm_iio_map_array_register(&pdev->dev, indio_dev, da9150_gpadc_default_maps);
if (ret) {
dev_err(dev, "Failed to register IIO maps: %d\n", ret);
return ret;
}
indio_dev->name = dev_name(dev);
indio_dev->info = &da9150_gpadc_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = da9150_gpadc_channels;
indio_dev->num_channels = ARRAY_SIZE(da9150_gpadc_channels);
return devm_iio_device_register(&pdev->dev, indio_dev);
}
static struct platform_driver da9150_gpadc_driver = {
.driver = {
.name = "da9150-gpadc",
},
.probe = da9150_gpadc_probe,
};
module_platform_driver(da9150_gpadc_driver);
MODULE_DESCRIPTION("GPADC Driver for DA9150");
MODULE_AUTHOR("Adam Thomson <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/adc/da9150-gpadc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Oskar Andero <[email protected]>
* Copyright (C) 2014 Rose Technology
* Allan Bendorff Jensen <[email protected]>
* Soren Andersen <[email protected]>
*
* Driver for following ADC chips from Microchip Technology's:
* 10 Bit converter
* MCP3001
* MCP3002
* MCP3004
* MCP3008
* ------------
* 12 bit converter
* MCP3201
* MCP3202
* MCP3204
* MCP3208
* ------------
* 13 bit converter
* MCP3301
* ------------
* 22 bit converter
* MCP3550
* MCP3551
* MCP3553
*
* Datasheet can be found here:
* https://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf mcp3001
* https://ww1.microchip.com/downloads/en/DeviceDoc/21294E.pdf mcp3002
* https://ww1.microchip.com/downloads/en/DeviceDoc/21295d.pdf mcp3004/08
* http://ww1.microchip.com/downloads/en/DeviceDoc/21290D.pdf mcp3201
* http://ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf mcp3202
* http://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf mcp3204/08
* https://ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf mcp3301
* http://ww1.microchip.com/downloads/en/DeviceDoc/21950D.pdf mcp3550/1/3
*/
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/iio/iio.h>
#include <linux/regulator/consumer.h>
enum {
mcp3001,
mcp3002,
mcp3004,
mcp3008,
mcp3201,
mcp3202,
mcp3204,
mcp3208,
mcp3301,
mcp3550_50,
mcp3550_60,
mcp3551,
mcp3553,
};
struct mcp320x_chip_info {
const struct iio_chan_spec *channels;
unsigned int num_channels;
unsigned int resolution;
unsigned int conv_time; /* usec */
};
/**
* struct mcp320x - Microchip SPI ADC instance
* @spi: SPI slave (parent of the IIO device)
* @msg: SPI message to select a channel and receive a value from the ADC
* @transfer: SPI transfers used by @msg
* @start_conv_msg: SPI message to start a conversion by briefly asserting CS
* @start_conv_transfer: SPI transfer used by @start_conv_msg
* @reg: regulator generating Vref
* @lock: protects read sequences
* @chip_info: ADC properties
* @tx_buf: buffer for @transfer[0] (not used on single-channel converters)
* @rx_buf: buffer for @transfer[1]
*/
struct mcp320x {
struct spi_device *spi;
struct spi_message msg;
struct spi_transfer transfer[2];
struct spi_message start_conv_msg;
struct spi_transfer start_conv_transfer;
struct regulator *reg;
struct mutex lock;
const struct mcp320x_chip_info *chip_info;
u8 tx_buf __aligned(IIO_DMA_MINALIGN);
u8 rx_buf[4];
};
static int mcp320x_channel_to_tx_data(int device_index,
const unsigned int channel, bool differential)
{
int start_bit = 1;
switch (device_index) {
case mcp3002:
case mcp3202:
return ((start_bit << 4) | (!differential << 3) |
(channel << 2));
case mcp3004:
case mcp3204:
case mcp3008:
case mcp3208:
return ((start_bit << 6) | (!differential << 5) |
(channel << 2));
default:
return -EINVAL;
}
}
static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel,
bool differential, int device_index, int *val)
{
int ret;
if (adc->chip_info->conv_time) {
ret = spi_sync(adc->spi, &adc->start_conv_msg);
if (ret < 0)
return ret;
usleep_range(adc->chip_info->conv_time,
adc->chip_info->conv_time + 100);
}
memset(&adc->rx_buf, 0, sizeof(adc->rx_buf));
if (adc->chip_info->num_channels > 1)
adc->tx_buf = mcp320x_channel_to_tx_data(device_index, channel,
differential);
ret = spi_sync(adc->spi, &adc->msg);
if (ret < 0)
return ret;
switch (device_index) {
case mcp3001:
*val = (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3);
return 0;
case mcp3002:
case mcp3004:
case mcp3008:
*val = (adc->rx_buf[0] << 2 | adc->rx_buf[1] >> 6);
return 0;
case mcp3201:
*val = (adc->rx_buf[0] << 7 | adc->rx_buf[1] >> 1);
return 0;
case mcp3202:
case mcp3204:
case mcp3208:
*val = (adc->rx_buf[0] << 4 | adc->rx_buf[1] >> 4);
return 0;
case mcp3301:
*val = sign_extend32((adc->rx_buf[0] & 0x1f) << 8
| adc->rx_buf[1], 12);
return 0;
case mcp3550_50:
case mcp3550_60:
case mcp3551:
case mcp3553: {
u32 raw = be32_to_cpup((__be32 *)adc->rx_buf);
if (!(adc->spi->mode & SPI_CPOL))
raw <<= 1; /* strip Data Ready bit in SPI mode 0,0 */
/*
* If the input is within -vref and vref, bit 21 is the sign.
* Up to 12% overrange or underrange are allowed, in which case
* bit 23 is the sign and bit 0 to 21 is the value.
*/
raw >>= 8;
if (raw & BIT(22) && raw & BIT(23))
return -EIO; /* cannot have overrange AND underrange */
else if (raw & BIT(22))
raw &= ~BIT(22); /* overrange */
else if (raw & BIT(23) || raw & BIT(21))
raw |= GENMASK(31, 22); /* underrange or negative */
*val = (s32)raw;
return 0;
}
default:
return -EINVAL;
}
}
static int mcp320x_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
struct mcp320x *adc = iio_priv(indio_dev);
int ret = -EINVAL;
int device_index = 0;
mutex_lock(&adc->lock);
device_index = spi_get_device_id(adc->spi)->driver_data;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = mcp320x_adc_conversion(adc, channel->address,
channel->differential, device_index, val);
if (ret < 0)
goto out;
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SCALE:
ret = regulator_get_voltage(adc->reg);
if (ret < 0)
goto out;
/* convert regulator output voltage to mV */
*val = ret / 1000;
*val2 = adc->chip_info->resolution;
ret = IIO_VAL_FRACTIONAL_LOG2;
break;
}
out:
mutex_unlock(&adc->lock);
return ret;
}
#define MCP320X_VOLTAGE_CHANNEL(num) \
{ \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = (num), \
.address = (num), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
}
#define MCP320X_VOLTAGE_CHANNEL_DIFF(chan1, chan2) \
{ \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = (chan1), \
.channel2 = (chan2), \
.address = (chan1), \
.differential = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
}
static const struct iio_chan_spec mcp3201_channels[] = {
MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
};
static const struct iio_chan_spec mcp3202_channels[] = {
MCP320X_VOLTAGE_CHANNEL(0),
MCP320X_VOLTAGE_CHANNEL(1),
MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
};
static const struct iio_chan_spec mcp3204_channels[] = {
MCP320X_VOLTAGE_CHANNEL(0),
MCP320X_VOLTAGE_CHANNEL(1),
MCP320X_VOLTAGE_CHANNEL(2),
MCP320X_VOLTAGE_CHANNEL(3),
MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3),
MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2),
};
static const struct iio_chan_spec mcp3208_channels[] = {
MCP320X_VOLTAGE_CHANNEL(0),
MCP320X_VOLTAGE_CHANNEL(1),
MCP320X_VOLTAGE_CHANNEL(2),
MCP320X_VOLTAGE_CHANNEL(3),
MCP320X_VOLTAGE_CHANNEL(4),
MCP320X_VOLTAGE_CHANNEL(5),
MCP320X_VOLTAGE_CHANNEL(6),
MCP320X_VOLTAGE_CHANNEL(7),
MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3),
MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2),
MCP320X_VOLTAGE_CHANNEL_DIFF(4, 5),
MCP320X_VOLTAGE_CHANNEL_DIFF(5, 4),
MCP320X_VOLTAGE_CHANNEL_DIFF(6, 7),
MCP320X_VOLTAGE_CHANNEL_DIFF(7, 6),
};
static const struct iio_info mcp320x_info = {
.read_raw = mcp320x_read_raw,
};
static const struct mcp320x_chip_info mcp320x_chip_infos[] = {
[mcp3001] = {
.channels = mcp3201_channels,
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 10
},
[mcp3002] = {
.channels = mcp3202_channels,
.num_channels = ARRAY_SIZE(mcp3202_channels),
.resolution = 10
},
[mcp3004] = {
.channels = mcp3204_channels,
.num_channels = ARRAY_SIZE(mcp3204_channels),
.resolution = 10
},
[mcp3008] = {
.channels = mcp3208_channels,
.num_channels = ARRAY_SIZE(mcp3208_channels),
.resolution = 10
},
[mcp3201] = {
.channels = mcp3201_channels,
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 12
},
[mcp3202] = {
.channels = mcp3202_channels,
.num_channels = ARRAY_SIZE(mcp3202_channels),
.resolution = 12
},
[mcp3204] = {
.channels = mcp3204_channels,
.num_channels = ARRAY_SIZE(mcp3204_channels),
.resolution = 12
},
[mcp3208] = {
.channels = mcp3208_channels,
.num_channels = ARRAY_SIZE(mcp3208_channels),
.resolution = 12
},
[mcp3301] = {
.channels = mcp3201_channels,
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 13
},
[mcp3550_50] = {
.channels = mcp3201_channels,
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 21,
/* 2% max deviation + 144 clock periods to exit shutdown */
.conv_time = 80000 * 1.02 + 144000 / 102.4,
},
[mcp3550_60] = {
.channels = mcp3201_channels,
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 21,
.conv_time = 66670 * 1.02 + 144000 / 122.88,
},
[mcp3551] = {
.channels = mcp3201_channels,
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 21,
.conv_time = 73100 * 1.02 + 144000 / 112.64,
},
[mcp3553] = {
.channels = mcp3201_channels,
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 21,
.conv_time = 16670 * 1.02 + 144000 / 122.88,
},
};
static int mcp320x_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct mcp320x *adc;
const struct mcp320x_chip_info *chip_info;
int ret, device_index;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
if (!indio_dev)
return -ENOMEM;
adc = iio_priv(indio_dev);
adc->spi = spi;
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &mcp320x_info;
spi_set_drvdata(spi, indio_dev);
device_index = spi_get_device_id(spi)->driver_data;
chip_info = &mcp320x_chip_infos[device_index];
indio_dev->channels = chip_info->channels;
indio_dev->num_channels = chip_info->num_channels;
adc->chip_info = chip_info;
adc->transfer[0].tx_buf = &adc->tx_buf;
adc->transfer[0].len = sizeof(adc->tx_buf);
adc->transfer[1].rx_buf = adc->rx_buf;
adc->transfer[1].len = DIV_ROUND_UP(chip_info->resolution, 8);
if (chip_info->num_channels == 1)
/* single-channel converters are rx only (no MOSI pin) */
spi_message_init_with_transfers(&adc->msg,
&adc->transfer[1], 1);
else
spi_message_init_with_transfers(&adc->msg, adc->transfer,
ARRAY_SIZE(adc->transfer));
switch (device_index) {
case mcp3550_50:
case mcp3550_60:
case mcp3551:
case mcp3553:
/* rx len increases from 24 to 25 bit in SPI mode 0,0 */
if (!(spi->mode & SPI_CPOL))
adc->transfer[1].len++;
/* conversions are started by asserting CS pin for 8 usec */
adc->start_conv_transfer.delay.value = 8;
adc->start_conv_transfer.delay.unit = SPI_DELAY_UNIT_USECS;
spi_message_init_with_transfers(&adc->start_conv_msg,
&adc->start_conv_transfer, 1);
/*
* If CS was previously kept low (continuous conversion mode)
* and then changed to high, the chip is in shutdown.
* Sometimes it fails to wake from shutdown and clocks out
* only 0xffffff. The magic sequence of performing two
* conversions without delay between them resets the chip
* and ensures all subsequent conversions succeed.
*/
mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
}
adc->reg = devm_regulator_get(&spi->dev, "vref");
if (IS_ERR(adc->reg))
return PTR_ERR(adc->reg);
ret = regulator_enable(adc->reg);
if (ret < 0)
return ret;
mutex_init(&adc->lock);
ret = iio_device_register(indio_dev);
if (ret < 0)
goto reg_disable;
return 0;
reg_disable:
regulator_disable(adc->reg);
return ret;
}
static void mcp320x_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct mcp320x *adc = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
regulator_disable(adc->reg);
}
static const struct of_device_id mcp320x_dt_ids[] = {
/* NOTE: The use of compatibles with no vendor prefix is deprecated. */
{ .compatible = "mcp3001" },
{ .compatible = "mcp3002" },
{ .compatible = "mcp3004" },
{ .compatible = "mcp3008" },
{ .compatible = "mcp3201" },
{ .compatible = "mcp3202" },
{ .compatible = "mcp3204" },
{ .compatible = "mcp3208" },
{ .compatible = "mcp3301" },
{ .compatible = "microchip,mcp3001" },
{ .compatible = "microchip,mcp3002" },
{ .compatible = "microchip,mcp3004" },
{ .compatible = "microchip,mcp3008" },
{ .compatible = "microchip,mcp3201" },
{ .compatible = "microchip,mcp3202" },
{ .compatible = "microchip,mcp3204" },
{ .compatible = "microchip,mcp3208" },
{ .compatible = "microchip,mcp3301" },
{ .compatible = "microchip,mcp3550-50" },
{ .compatible = "microchip,mcp3550-60" },
{ .compatible = "microchip,mcp3551" },
{ .compatible = "microchip,mcp3553" },
{ }
};
MODULE_DEVICE_TABLE(of, mcp320x_dt_ids);
static const struct spi_device_id mcp320x_id[] = {
{ "mcp3001", mcp3001 },
{ "mcp3002", mcp3002 },
{ "mcp3004", mcp3004 },
{ "mcp3008", mcp3008 },
{ "mcp3201", mcp3201 },
{ "mcp3202", mcp3202 },
{ "mcp3204", mcp3204 },
{ "mcp3208", mcp3208 },
{ "mcp3301", mcp3301 },
{ "mcp3550-50", mcp3550_50 },
{ "mcp3550-60", mcp3550_60 },
{ "mcp3551", mcp3551 },
{ "mcp3553", mcp3553 },
{ }
};
MODULE_DEVICE_TABLE(spi, mcp320x_id);
static struct spi_driver mcp320x_driver = {
.driver = {
.name = "mcp320x",
.of_match_table = mcp320x_dt_ids,
},
.probe = mcp320x_probe,
.remove = mcp320x_remove,
.id_table = mcp320x_id,
};
module_spi_driver(mcp320x_driver);
MODULE_AUTHOR("Oskar Andero <[email protected]>");
MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/mcp320x.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Texas Instruments LMP92064 SPI ADC driver
*
* Copyright (c) 2022 Leonard Göhrs <[email protected]>, Pengutronix
*
* Based on linux/drivers/iio/adc/ti-tsc2046.c
* Copyright (c) 2021 Oleksij Rempel <[email protected]>, Pengutronix
*/
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/driver.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#define TI_LMP92064_REG_CONFIG_A 0x0000
#define TI_LMP92064_REG_CONFIG_B 0x0001
#define TI_LMP92064_REG_CHIP_REV 0x0006
#define TI_LMP92064_REG_MFR_ID1 0x000C
#define TI_LMP92064_REG_MFR_ID2 0x000D
#define TI_LMP92064_REG_REG_UPDATE 0x000F
#define TI_LMP92064_REG_CONFIG_REG 0x0100
#define TI_LMP92064_REG_STATUS 0x0103
#define TI_LMP92064_REG_DATA_VOUT_LSB 0x0200
#define TI_LMP92064_REG_DATA_VOUT_MSB 0x0201
#define TI_LMP92064_REG_DATA_COUT_LSB 0x0202
#define TI_LMP92064_REG_DATA_COUT_MSB 0x0203
#define TI_LMP92064_VAL_CONFIG_A 0x99
#define TI_LMP92064_VAL_CONFIG_B 0x00
#define TI_LMP92064_VAL_STATUS_OK 0x01
/*
* Channel number definitions for the two channels of the device
* - IN Current (INC)
* - IN Voltage (INV)
*/
#define TI_LMP92064_CHAN_INC 0
#define TI_LMP92064_CHAN_INV 1
static const struct regmap_range lmp92064_readable_reg_ranges[] = {
regmap_reg_range(TI_LMP92064_REG_CONFIG_A, TI_LMP92064_REG_CHIP_REV),
regmap_reg_range(TI_LMP92064_REG_MFR_ID1, TI_LMP92064_REG_MFR_ID2),
regmap_reg_range(TI_LMP92064_REG_REG_UPDATE, TI_LMP92064_REG_REG_UPDATE),
regmap_reg_range(TI_LMP92064_REG_CONFIG_REG, TI_LMP92064_REG_CONFIG_REG),
regmap_reg_range(TI_LMP92064_REG_STATUS, TI_LMP92064_REG_STATUS),
regmap_reg_range(TI_LMP92064_REG_DATA_VOUT_LSB, TI_LMP92064_REG_DATA_COUT_MSB),
};
static const struct regmap_access_table lmp92064_readable_regs = {
.yes_ranges = lmp92064_readable_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(lmp92064_readable_reg_ranges),
};
static const struct regmap_range lmp92064_writable_reg_ranges[] = {
regmap_reg_range(TI_LMP92064_REG_CONFIG_A, TI_LMP92064_REG_CONFIG_B),
regmap_reg_range(TI_LMP92064_REG_REG_UPDATE, TI_LMP92064_REG_REG_UPDATE),
regmap_reg_range(TI_LMP92064_REG_CONFIG_REG, TI_LMP92064_REG_CONFIG_REG),
};
static const struct regmap_access_table lmp92064_writable_regs = {
.yes_ranges = lmp92064_writable_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(lmp92064_writable_reg_ranges),
};
static const struct regmap_config lmp92064_spi_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = TI_LMP92064_REG_DATA_COUT_MSB,
.rd_table = &lmp92064_readable_regs,
.wr_table = &lmp92064_writable_regs,
};
struct lmp92064_adc_priv {
int shunt_resistor_uohm;
struct spi_device *spi;
struct regmap *regmap;
};
static const struct iio_chan_spec lmp92064_adc_channels[] = {
{
.type = IIO_CURRENT,
.address = TI_LMP92064_CHAN_INC,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = TI_LMP92064_CHAN_INC,
.scan_type = {
.sign = 'u',
.realbits = 12,
.storagebits = 16,
},
.datasheet_name = "INC",
},
{
.type = IIO_VOLTAGE,
.address = TI_LMP92064_CHAN_INV,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = TI_LMP92064_CHAN_INV,
.scan_type = {
.sign = 'u',
.realbits = 12,
.storagebits = 16,
},
.datasheet_name = "INV",
},
IIO_CHAN_SOFT_TIMESTAMP(2),
};
static const unsigned long lmp92064_scan_masks[] = {
BIT(TI_LMP92064_CHAN_INC) | BIT(TI_LMP92064_CHAN_INV),
0
};
static int lmp92064_read_meas(struct lmp92064_adc_priv *priv, u16 *res)
{
__be16 raw[2];
int ret;
/*
* The ADC only latches in new samples if all DATA registers are read
* in descending sequential order.
* The ADC auto-decrements the register index with each clocked byte.
* Read both channels in single SPI transfer by selecting the highest
* register using the command below and clocking out all four data
* bytes.
*/
ret = regmap_bulk_read(priv->regmap, TI_LMP92064_REG_DATA_COUT_MSB,
&raw, sizeof(raw));
if (ret) {
dev_err(&priv->spi->dev, "regmap_bulk_read failed: %pe\n",
ERR_PTR(ret));
return ret;
}
res[0] = be16_to_cpu(raw[0]);
res[1] = be16_to_cpu(raw[1]);
return 0;
}
static int lmp92064_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct lmp92064_adc_priv *priv = iio_priv(indio_dev);
u16 raw[2];
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = lmp92064_read_meas(priv, raw);
if (ret < 0)
return ret;
*val = (chan->address == TI_LMP92064_CHAN_INC) ? raw[0] : raw[1];
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
if (chan->address == TI_LMP92064_CHAN_INC) {
/*
* processed (mA) = raw * current_lsb (mA)
* current_lsb (mA) = shunt_voltage_lsb (nV) / shunt_resistor (uOhm)
* shunt_voltage_lsb (nV) = 81920000 / 4096 = 20000
*/
*val = 20000;
*val2 = priv->shunt_resistor_uohm;
} else {
/*
* processed (mV) = raw * voltage_lsb (mV)
* voltage_lsb (mV) = 2048 / 4096
*/
*val = 2048;
*val2 = 4096;
}
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
}
static irqreturn_t lmp92064_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct lmp92064_adc_priv *priv = iio_priv(indio_dev);
struct {
u16 values[2];
int64_t timestamp __aligned(8);
} data;
int ret;
memset(&data, 0, sizeof(data));
ret = lmp92064_read_meas(priv, data.values);
if (ret)
goto err;
iio_push_to_buffers_with_timestamp(indio_dev, &data,
iio_get_time_ns(indio_dev));
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int lmp92064_reset(struct lmp92064_adc_priv *priv,
struct gpio_desc *gpio_reset)
{
unsigned int status;
int ret, i;
if (gpio_reset) {
/*
* Perform a hard reset if gpio_reset is available.
* The datasheet specifies a very low 3.5ns reset pulse duration and does not
* specify how long to wait after a reset to access the device.
* Use more conservative pulse lengths to allow analog RC filtering of the
* reset line at the board level (as recommended in the datasheet).
*/
gpiod_set_value_cansleep(gpio_reset, 1);
usleep_range(1, 10);
gpiod_set_value_cansleep(gpio_reset, 0);
usleep_range(500, 750);
} else {
/*
* Perform a soft-reset if not.
* Also write default values to the config registers that are not
* affected by soft reset.
*/
ret = regmap_write(priv->regmap, TI_LMP92064_REG_CONFIG_A,
TI_LMP92064_VAL_CONFIG_A);
if (ret < 0)
return ret;
ret = regmap_write(priv->regmap, TI_LMP92064_REG_CONFIG_B,
TI_LMP92064_VAL_CONFIG_B);
if (ret < 0)
return ret;
}
/*
* Wait for the device to signal readiness to prevent reading bogus data
* and make sure device is actually connected.
* The datasheet does not specify how long this takes but usually it is
* not more than 3-4 iterations of this loop.
*/
for (i = 0; i < 10; i++) {
ret = regmap_read(priv->regmap, TI_LMP92064_REG_STATUS, &status);
if (ret < 0)
return ret;
if (status == TI_LMP92064_VAL_STATUS_OK)
return 0;
usleep_range(1000, 2000);
}
/*
* No (correct) response received.
* Device is mostly likely not connected to the bus.
*/
return -ENXIO;
}
static const struct iio_info lmp92064_adc_info = {
.read_raw = lmp92064_read_raw,
};
static int lmp92064_adc_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct lmp92064_adc_priv *priv;
struct gpio_desc *gpio_reset;
struct iio_dev *indio_dev;
u32 shunt_resistor_uohm;
struct regmap *regmap;
int ret;
ret = spi_setup(spi);
if (ret < 0)
return dev_err_probe(dev, ret, "Error in SPI setup\n");
regmap = devm_regmap_init_spi(spi, &lmp92064_spi_regmap_config);
if (IS_ERR(regmap))
return dev_err_probe(dev, PTR_ERR(regmap),
"Failed to set up SPI regmap\n");
indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
if (!indio_dev)
return -ENOMEM;
priv = iio_priv(indio_dev);
priv->spi = spi;
priv->regmap = regmap;
ret = device_property_read_u32(dev, "shunt-resistor-micro-ohms",
&shunt_resistor_uohm);
if (ret < 0)
return dev_err_probe(dev, ret,
"Failed to get shunt-resistor value\n");
/*
* The shunt resistance is passed to userspace as the denominator of an iio
* fraction. Make sure it is in range for that.
*/
if (shunt_resistor_uohm == 0 || shunt_resistor_uohm > INT_MAX) {
dev_err(dev, "Shunt resistance is out of range\n");
return -EINVAL;
}
priv->shunt_resistor_uohm = shunt_resistor_uohm;
ret = devm_regulator_get_enable(dev, "vdd");
if (ret)
return ret;
ret = devm_regulator_get_enable(dev, "vdig");
if (ret)
return ret;
gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(gpio_reset))
return dev_err_probe(dev, PTR_ERR(gpio_reset),
"Failed to get GPIO reset pin\n");
ret = lmp92064_reset(priv, gpio_reset);
if (ret < 0)
return dev_err_probe(dev, ret, "Failed to reset device\n");
indio_dev->name = "lmp92064";
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = lmp92064_adc_channels;
indio_dev->num_channels = ARRAY_SIZE(lmp92064_adc_channels);
indio_dev->info = &lmp92064_adc_info;
indio_dev->available_scan_masks = lmp92064_scan_masks;
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
lmp92064_trigger_handler, NULL);
if (ret)
return dev_err_probe(dev, ret, "Failed to setup buffered read\n");
return devm_iio_device_register(dev, indio_dev);
}
static const struct spi_device_id lmp92064_id_table[] = {
{ "lmp92064" },
{}
};
MODULE_DEVICE_TABLE(spi, lmp92064_id_table);
static const struct of_device_id lmp92064_of_table[] = {
{ .compatible = "ti,lmp92064" },
{}
};
MODULE_DEVICE_TABLE(of, lmp92064_of_table);
static struct spi_driver lmp92064_adc_driver = {
.driver = {
.name = "lmp92064",
.of_match_table = lmp92064_of_table,
},
.probe = lmp92064_adc_probe,
.id_table = lmp92064_id_table,
};
module_spi_driver(lmp92064_adc_driver);
MODULE_AUTHOR("Leonard Göhrs <[email protected]>");
MODULE_DESCRIPTION("TI LMP92064 ADC");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/adc/ti-lmp92064.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 Analog Devices, Inc.
* Author: Cosmin Tanislav <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/units.h>
#include <asm/div64.h>
#include <asm/unaligned.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/kfifo_buf.h>
#include <linux/iio/sysfs.h>
#define AD4130_NAME "ad4130"
#define AD4130_COMMS_READ_MASK BIT(6)
#define AD4130_STATUS_REG 0x00
#define AD4130_ADC_CONTROL_REG 0x01
#define AD4130_ADC_CONTROL_BIPOLAR_MASK BIT(14)
#define AD4130_ADC_CONTROL_INT_REF_VAL_MASK BIT(13)
#define AD4130_INT_REF_2_5V 2500000
#define AD4130_INT_REF_1_25V 1250000
#define AD4130_ADC_CONTROL_CSB_EN_MASK BIT(9)
#define AD4130_ADC_CONTROL_INT_REF_EN_MASK BIT(8)
#define AD4130_ADC_CONTROL_MODE_MASK GENMASK(5, 2)
#define AD4130_ADC_CONTROL_MCLK_SEL_MASK GENMASK(1, 0)
#define AD4130_MCLK_FREQ_76_8KHZ 76800
#define AD4130_MCLK_FREQ_153_6KHZ 153600
#define AD4130_DATA_REG 0x02
#define AD4130_IO_CONTROL_REG 0x03
#define AD4130_IO_CONTROL_INT_PIN_SEL_MASK GENMASK(9, 8)
#define AD4130_IO_CONTROL_GPIO_DATA_MASK GENMASK(7, 4)
#define AD4130_IO_CONTROL_GPIO_CTRL_MASK GENMASK(3, 0)
#define AD4130_VBIAS_REG 0x04
#define AD4130_ID_REG 0x05
#define AD4130_ERROR_REG 0x06
#define AD4130_ERROR_EN_REG 0x07
#define AD4130_MCLK_COUNT_REG 0x08
#define AD4130_CHANNEL_X_REG(x) (0x09 + (x))
#define AD4130_CHANNEL_EN_MASK BIT(23)
#define AD4130_CHANNEL_SETUP_MASK GENMASK(22, 20)
#define AD4130_CHANNEL_AINP_MASK GENMASK(17, 13)
#define AD4130_CHANNEL_AINM_MASK GENMASK(12, 8)
#define AD4130_CHANNEL_IOUT1_MASK GENMASK(7, 4)
#define AD4130_CHANNEL_IOUT2_MASK GENMASK(3, 0)
#define AD4130_CONFIG_X_REG(x) (0x19 + (x))
#define AD4130_CONFIG_IOUT1_VAL_MASK GENMASK(15, 13)
#define AD4130_CONFIG_IOUT2_VAL_MASK GENMASK(12, 10)
#define AD4130_CONFIG_BURNOUT_MASK GENMASK(9, 8)
#define AD4130_CONFIG_REF_BUFP_MASK BIT(7)
#define AD4130_CONFIG_REF_BUFM_MASK BIT(6)
#define AD4130_CONFIG_REF_SEL_MASK GENMASK(5, 4)
#define AD4130_CONFIG_PGA_MASK GENMASK(3, 1)
#define AD4130_FILTER_X_REG(x) (0x21 + (x))
#define AD4130_FILTER_MODE_MASK GENMASK(15, 12)
#define AD4130_FILTER_SELECT_MASK GENMASK(10, 0)
#define AD4130_FILTER_SELECT_MIN 1
#define AD4130_OFFSET_X_REG(x) (0x29 + (x))
#define AD4130_GAIN_X_REG(x) (0x31 + (x))
#define AD4130_MISC_REG 0x39
#define AD4130_FIFO_CONTROL_REG 0x3a
#define AD4130_FIFO_CONTROL_HEADER_MASK BIT(18)
#define AD4130_FIFO_CONTROL_MODE_MASK GENMASK(17, 16)
#define AD4130_FIFO_CONTROL_WM_INT_EN_MASK BIT(9)
#define AD4130_FIFO_CONTROL_WM_MASK GENMASK(7, 0)
#define AD4130_WATERMARK_256 0
#define AD4130_FIFO_STATUS_REG 0x3b
#define AD4130_FIFO_THRESHOLD_REG 0x3c
#define AD4130_FIFO_DATA_REG 0x3d
#define AD4130_FIFO_SIZE 256
#define AD4130_FIFO_MAX_SAMPLE_SIZE 3
#define AD4130_MAX_ANALOG_PINS 16
#define AD4130_MAX_CHANNELS 16
#define AD4130_MAX_DIFF_INPUTS 30
#define AD4130_MAX_GPIOS 4
#define AD4130_MAX_ODR 2400
#define AD4130_MAX_PGA 8
#define AD4130_MAX_SETUPS 8
#define AD4130_AIN2_P1 0x2
#define AD4130_AIN3_P2 0x3
#define AD4130_RESET_BUF_SIZE 8
#define AD4130_RESET_SLEEP_US (160 * MICRO / AD4130_MCLK_FREQ_76_8KHZ)
#define AD4130_INVALID_SLOT -1
static const unsigned int ad4130_reg_size[] = {
[AD4130_STATUS_REG] = 1,
[AD4130_ADC_CONTROL_REG] = 2,
[AD4130_DATA_REG] = 3,
[AD4130_IO_CONTROL_REG] = 2,
[AD4130_VBIAS_REG] = 2,
[AD4130_ID_REG] = 1,
[AD4130_ERROR_REG] = 2,
[AD4130_ERROR_EN_REG] = 2,
[AD4130_MCLK_COUNT_REG] = 1,
[AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
[AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
[AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
[AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
[AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
[AD4130_MISC_REG] = 2,
[AD4130_FIFO_CONTROL_REG] = 3,
[AD4130_FIFO_STATUS_REG] = 1,
[AD4130_FIFO_THRESHOLD_REG] = 3,
[AD4130_FIFO_DATA_REG] = 3,
};
enum ad4130_int_ref_val {
AD4130_INT_REF_VAL_2_5V,
AD4130_INT_REF_VAL_1_25V,
};
enum ad4130_mclk_sel {
AD4130_MCLK_76_8KHZ,
AD4130_MCLK_76_8KHZ_OUT,
AD4130_MCLK_76_8KHZ_EXT,
AD4130_MCLK_153_6KHZ_EXT,
};
enum ad4130_int_pin_sel {
AD4130_INT_PIN_INT,
AD4130_INT_PIN_CLK,
AD4130_INT_PIN_P2,
AD4130_INT_PIN_DOUT,
};
enum ad4130_iout {
AD4130_IOUT_OFF,
AD4130_IOUT_10000NA,
AD4130_IOUT_20000NA,
AD4130_IOUT_50000NA,
AD4130_IOUT_100000NA,
AD4130_IOUT_150000NA,
AD4130_IOUT_200000NA,
AD4130_IOUT_100NA,
AD4130_IOUT_MAX
};
enum ad4130_burnout {
AD4130_BURNOUT_OFF,
AD4130_BURNOUT_500NA,
AD4130_BURNOUT_2000NA,
AD4130_BURNOUT_4000NA,
AD4130_BURNOUT_MAX
};
enum ad4130_ref_sel {
AD4130_REF_REFIN1,
AD4130_REF_REFIN2,
AD4130_REF_REFOUT_AVSS,
AD4130_REF_AVDD_AVSS,
AD4130_REF_SEL_MAX
};
enum ad4130_fifo_mode {
AD4130_FIFO_MODE_DISABLED = 0b00,
AD4130_FIFO_MODE_WM = 0b01,
};
enum ad4130_mode {
AD4130_MODE_CONTINUOUS = 0b0000,
AD4130_MODE_IDLE = 0b0100,
};
enum ad4130_filter_mode {
AD4130_FILTER_SINC4,
AD4130_FILTER_SINC4_SINC1,
AD4130_FILTER_SINC3,
AD4130_FILTER_SINC3_REJ60,
AD4130_FILTER_SINC3_SINC1,
AD4130_FILTER_SINC3_PF1,
AD4130_FILTER_SINC3_PF2,
AD4130_FILTER_SINC3_PF3,
AD4130_FILTER_SINC3_PF4,
};
enum ad4130_pin_function {
AD4130_PIN_FN_NONE,
AD4130_PIN_FN_SPECIAL = BIT(0),
AD4130_PIN_FN_DIFF = BIT(1),
AD4130_PIN_FN_EXCITATION = BIT(2),
AD4130_PIN_FN_VBIAS = BIT(3),
};
struct ad4130_setup_info {
unsigned int iout0_val;
unsigned int iout1_val;
unsigned int burnout;
unsigned int pga;
unsigned int fs;
u32 ref_sel;
enum ad4130_filter_mode filter_mode;
bool ref_bufp;
bool ref_bufm;
};
struct ad4130_slot_info {
struct ad4130_setup_info setup;
unsigned int enabled_channels;
unsigned int channels;
};
struct ad4130_chan_info {
struct ad4130_setup_info setup;
u32 iout0;
u32 iout1;
int slot;
bool enabled;
bool initialized;
};
struct ad4130_filter_config {
enum ad4130_filter_mode filter_mode;
unsigned int odr_div;
unsigned int fs_max;
enum iio_available_type samp_freq_avail_type;
int samp_freq_avail_len;
int samp_freq_avail[3][2];
};
struct ad4130_state {
struct regmap *regmap;
struct spi_device *spi;
struct clk *mclk;
struct regulator_bulk_data regulators[4];
u32 irq_trigger;
u32 inv_irq_trigger;
/*
* Synchronize access to members the of driver state, and ensure
* atomicity of consecutive regmap operations.
*/
struct mutex lock;
struct completion completion;
struct iio_chan_spec chans[AD4130_MAX_CHANNELS];
struct ad4130_chan_info chans_info[AD4130_MAX_CHANNELS];
struct ad4130_slot_info slots_info[AD4130_MAX_SETUPS];
enum ad4130_pin_function pins_fn[AD4130_MAX_ANALOG_PINS];
u32 vbias_pins[AD4130_MAX_ANALOG_PINS];
u32 num_vbias_pins;
int scale_tbls[AD4130_REF_SEL_MAX][AD4130_MAX_PGA][2];
struct gpio_chip gc;
struct clk_hw int_clk_hw;
u32 int_pin_sel;
u32 int_ref_uv;
u32 mclk_sel;
bool int_ref_en;
bool bipolar;
unsigned int num_enabled_channels;
unsigned int effective_watermark;
unsigned int watermark;
struct spi_message fifo_msg;
struct spi_transfer fifo_xfer[2];
/*
* DMA (thus cache coherency maintenance) requires any transfer
* buffers to live in their own cache lines. As the use of these
* buffers is synchronous, all of the buffers used for DMA in this
* driver may share a cache line.
*/
u8 reset_buf[AD4130_RESET_BUF_SIZE] __aligned(IIO_DMA_MINALIGN);
u8 reg_write_tx_buf[4];
u8 reg_read_tx_buf[1];
u8 reg_read_rx_buf[3];
u8 fifo_tx_buf[2];
u8 fifo_rx_buf[AD4130_FIFO_SIZE *
AD4130_FIFO_MAX_SAMPLE_SIZE];
};
static const char * const ad4130_int_pin_names[] = {
[AD4130_INT_PIN_INT] = "int",
[AD4130_INT_PIN_CLK] = "clk",
[AD4130_INT_PIN_P2] = "p2",
[AD4130_INT_PIN_DOUT] = "dout",
};
static const unsigned int ad4130_iout_current_na_tbl[AD4130_IOUT_MAX] = {
[AD4130_IOUT_OFF] = 0,
[AD4130_IOUT_100NA] = 100,
[AD4130_IOUT_10000NA] = 10000,
[AD4130_IOUT_20000NA] = 20000,
[AD4130_IOUT_50000NA] = 50000,
[AD4130_IOUT_100000NA] = 100000,
[AD4130_IOUT_150000NA] = 150000,
[AD4130_IOUT_200000NA] = 200000,
};
static const unsigned int ad4130_burnout_current_na_tbl[AD4130_BURNOUT_MAX] = {
[AD4130_BURNOUT_OFF] = 0,
[AD4130_BURNOUT_500NA] = 500,
[AD4130_BURNOUT_2000NA] = 2000,
[AD4130_BURNOUT_4000NA] = 4000,
};
#define AD4130_VARIABLE_ODR_CONFIG(_filter_mode, _odr_div, _fs_max) \
{ \
.filter_mode = (_filter_mode), \
.odr_div = (_odr_div), \
.fs_max = (_fs_max), \
.samp_freq_avail_type = IIO_AVAIL_RANGE, \
.samp_freq_avail = { \
{ AD4130_MAX_ODR, (_odr_div) * (_fs_max) }, \
{ AD4130_MAX_ODR, (_odr_div) * (_fs_max) }, \
{ AD4130_MAX_ODR, (_odr_div) }, \
}, \
}
#define AD4130_FIXED_ODR_CONFIG(_filter_mode, _odr_div) \
{ \
.filter_mode = (_filter_mode), \
.odr_div = (_odr_div), \
.fs_max = AD4130_FILTER_SELECT_MIN, \
.samp_freq_avail_type = IIO_AVAIL_LIST, \
.samp_freq_avail_len = 1, \
.samp_freq_avail = { \
{ AD4130_MAX_ODR, (_odr_div) }, \
}, \
}
static const struct ad4130_filter_config ad4130_filter_configs[] = {
AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4, 1, 10),
AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4_SINC1, 11, 10),
AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3, 1, 2047),
AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_REJ60, 1, 2047),
AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_SINC1, 10, 2047),
AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF1, 92),
AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF2, 100),
AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF3, 124),
AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF4, 148),
};
static const char * const ad4130_filter_modes_str[] = {
[AD4130_FILTER_SINC4] = "sinc4",
[AD4130_FILTER_SINC4_SINC1] = "sinc4+sinc1",
[AD4130_FILTER_SINC3] = "sinc3",
[AD4130_FILTER_SINC3_REJ60] = "sinc3+rej60",
[AD4130_FILTER_SINC3_SINC1] = "sinc3+sinc1",
[AD4130_FILTER_SINC3_PF1] = "sinc3+pf1",
[AD4130_FILTER_SINC3_PF2] = "sinc3+pf2",
[AD4130_FILTER_SINC3_PF3] = "sinc3+pf3",
[AD4130_FILTER_SINC3_PF4] = "sinc3+pf4",
};
static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg,
unsigned int *size)
{
if (reg >= ARRAY_SIZE(ad4130_reg_size))
return -EINVAL;
*size = ad4130_reg_size[reg];
return 0;
}
static unsigned int ad4130_data_reg_size(struct ad4130_state *st)
{
unsigned int data_reg_size;
int ret;
ret = ad4130_get_reg_size(st, AD4130_DATA_REG, &data_reg_size);
if (ret)
return 0;
return data_reg_size;
}
static unsigned int ad4130_resolution(struct ad4130_state *st)
{
return ad4130_data_reg_size(st) * BITS_PER_BYTE;
}
static int ad4130_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct ad4130_state *st = context;
unsigned int size;
int ret;
ret = ad4130_get_reg_size(st, reg, &size);
if (ret)
return ret;
st->reg_write_tx_buf[0] = reg;
switch (size) {
case 3:
put_unaligned_be24(val, &st->reg_write_tx_buf[1]);
break;
case 2:
put_unaligned_be16(val, &st->reg_write_tx_buf[1]);
break;
case 1:
st->reg_write_tx_buf[1] = val;
break;
default:
return -EINVAL;
}
return spi_write(st->spi, st->reg_write_tx_buf, size + 1);
}
static int ad4130_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct ad4130_state *st = context;
struct spi_transfer t[] = {
{
.tx_buf = st->reg_read_tx_buf,
.len = sizeof(st->reg_read_tx_buf),
},
{
.rx_buf = st->reg_read_rx_buf,
},
};
unsigned int size;
int ret;
ret = ad4130_get_reg_size(st, reg, &size);
if (ret)
return ret;
st->reg_read_tx_buf[0] = AD4130_COMMS_READ_MASK | reg;
t[1].len = size;
ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
if (ret)
return ret;
switch (size) {
case 3:
*val = get_unaligned_be24(st->reg_read_rx_buf);
break;
case 2:
*val = get_unaligned_be16(st->reg_read_rx_buf);
break;
case 1:
*val = st->reg_read_rx_buf[0];
break;
default:
return -EINVAL;
}
return 0;
}
static const struct regmap_config ad4130_regmap_config = {
.reg_read = ad4130_reg_read,
.reg_write = ad4130_reg_write,
};
static int ad4130_gpio_init_valid_mask(struct gpio_chip *gc,
unsigned long *valid_mask,
unsigned int ngpios)
{
struct ad4130_state *st = gpiochip_get_data(gc);
unsigned int i;
/*
* Output-only GPIO functionality is available on pins AIN2 through
* AIN5. If these pins are used for anything else, do not expose them.
*/
for (i = 0; i < ngpios; i++) {
unsigned int pin = i + AD4130_AIN2_P1;
bool valid = st->pins_fn[pin] == AD4130_PIN_FN_NONE;
__assign_bit(i, valid_mask, valid);
}
return 0;
}
static int ad4130_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
return GPIO_LINE_DIRECTION_OUT;
}
static void ad4130_gpio_set(struct gpio_chip *gc, unsigned int offset,
int value)
{
struct ad4130_state *st = gpiochip_get_data(gc);
unsigned int mask = FIELD_PREP(AD4130_IO_CONTROL_GPIO_DATA_MASK,
BIT(offset));
regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask,
value ? mask : 0);
}
static int ad4130_set_mode(struct ad4130_state *st, enum ad4130_mode mode)
{
return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG,
AD4130_ADC_CONTROL_MODE_MASK,
FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, mode));
}
static int ad4130_set_watermark_interrupt_en(struct ad4130_state *st, bool en)
{
return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
AD4130_FIFO_CONTROL_WM_INT_EN_MASK,
FIELD_PREP(AD4130_FIFO_CONTROL_WM_INT_EN_MASK, en));
}
static unsigned int ad4130_watermark_reg_val(unsigned int val)
{
if (val == AD4130_FIFO_SIZE)
val = AD4130_WATERMARK_256;
return val;
}
static int ad4130_set_fifo_mode(struct ad4130_state *st,
enum ad4130_fifo_mode mode)
{
return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
AD4130_FIFO_CONTROL_MODE_MASK,
FIELD_PREP(AD4130_FIFO_CONTROL_MODE_MASK, mode));
}
static void ad4130_push_fifo_data(struct iio_dev *indio_dev)
{
struct ad4130_state *st = iio_priv(indio_dev);
unsigned int data_reg_size = ad4130_data_reg_size(st);
unsigned int transfer_len = st->effective_watermark * data_reg_size;
unsigned int set_size = st->num_enabled_channels * data_reg_size;
unsigned int i;
int ret;
st->fifo_tx_buf[1] = ad4130_watermark_reg_val(st->effective_watermark);
st->fifo_xfer[1].len = transfer_len;
ret = spi_sync(st->spi, &st->fifo_msg);
if (ret)
return;
for (i = 0; i < transfer_len; i += set_size)
iio_push_to_buffers(indio_dev, &st->fifo_rx_buf[i]);
}
static irqreturn_t ad4130_irq_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct ad4130_state *st = iio_priv(indio_dev);
if (iio_buffer_enabled(indio_dev))
ad4130_push_fifo_data(indio_dev);
else
complete(&st->completion);
return IRQ_HANDLED;
}
static int ad4130_find_slot(struct ad4130_state *st,
struct ad4130_setup_info *target_setup_info,
unsigned int *slot, bool *overwrite)
{
unsigned int i;
*slot = AD4130_INVALID_SLOT;
*overwrite = false;
for (i = 0; i < AD4130_MAX_SETUPS; i++) {
struct ad4130_slot_info *slot_info = &st->slots_info[i];
/* Immediately accept a matching setup info. */
if (!memcmp(target_setup_info, &slot_info->setup,
sizeof(*target_setup_info))) {
*slot = i;
return 0;
}
/* Ignore all setups which are used by enabled channels. */
if (slot_info->enabled_channels)
continue;
/* Find the least used slot. */
if (*slot == AD4130_INVALID_SLOT ||
slot_info->channels < st->slots_info[*slot].channels)
*slot = i;
}
if (*slot == AD4130_INVALID_SLOT)
return -EINVAL;
*overwrite = true;
return 0;
}
static void ad4130_unlink_channel(struct ad4130_state *st, unsigned int channel)
{
struct ad4130_chan_info *chan_info = &st->chans_info[channel];
struct ad4130_slot_info *slot_info = &st->slots_info[chan_info->slot];
chan_info->slot = AD4130_INVALID_SLOT;
slot_info->channels--;
}
static int ad4130_unlink_slot(struct ad4130_state *st, unsigned int slot)
{
unsigned int i;
for (i = 0; i < AD4130_MAX_CHANNELS; i++) {
struct ad4130_chan_info *chan_info = &st->chans_info[i];
if (!chan_info->initialized || chan_info->slot != slot)
continue;
ad4130_unlink_channel(st, i);
}
return 0;
}
static int ad4130_link_channel_slot(struct ad4130_state *st,
unsigned int channel, unsigned int slot)
{
struct ad4130_slot_info *slot_info = &st->slots_info[slot];
struct ad4130_chan_info *chan_info = &st->chans_info[channel];
int ret;
ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel),
AD4130_CHANNEL_SETUP_MASK,
FIELD_PREP(AD4130_CHANNEL_SETUP_MASK, slot));
if (ret)
return ret;
chan_info->slot = slot;
slot_info->channels++;
return 0;
}
static int ad4130_write_slot_setup(struct ad4130_state *st,
unsigned int slot,
struct ad4130_setup_info *setup_info)
{
unsigned int val;
int ret;
val = FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout0_val) |
FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout1_val) |
FIELD_PREP(AD4130_CONFIG_BURNOUT_MASK, setup_info->burnout) |
FIELD_PREP(AD4130_CONFIG_REF_BUFP_MASK, setup_info->ref_bufp) |
FIELD_PREP(AD4130_CONFIG_REF_BUFM_MASK, setup_info->ref_bufm) |
FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, setup_info->ref_sel) |
FIELD_PREP(AD4130_CONFIG_PGA_MASK, setup_info->pga);
ret = regmap_write(st->regmap, AD4130_CONFIG_X_REG(slot), val);
if (ret)
return ret;
val = FIELD_PREP(AD4130_FILTER_MODE_MASK, setup_info->filter_mode) |
FIELD_PREP(AD4130_FILTER_SELECT_MASK, setup_info->fs);
ret = regmap_write(st->regmap, AD4130_FILTER_X_REG(slot), val);
if (ret)
return ret;
memcpy(&st->slots_info[slot].setup, setup_info, sizeof(*setup_info));
return 0;
}
static int ad4130_write_channel_setup(struct ad4130_state *st,
unsigned int channel, bool on_enable)
{
struct ad4130_chan_info *chan_info = &st->chans_info[channel];
struct ad4130_setup_info *setup_info = &chan_info->setup;
bool overwrite;
int slot;
int ret;
/*
* The following cases need to be handled.
*
* 1. Enabled and linked channel with setup changes:
* - Find a slot. If not possible, return error.
* - Unlink channel from current slot.
* - If the slot has channels linked to it, unlink all channels, and
* write the new setup to it.
* - Link channel to new slot.
*
* 2. Soon to be enabled and unlinked channel:
* - Find a slot. If not possible, return error.
* - If the slot has channels linked to it, unlink all channels, and
* write the new setup to it.
* - Link channel to the slot.
*
* 3. Disabled and linked channel with setup changes:
* - Unlink channel from current slot.
*
* 4. Soon to be enabled and linked channel:
* 5. Disabled and unlinked channel with setup changes:
* - Do nothing.
*/
/* Case 4 */
if (on_enable && chan_info->slot != AD4130_INVALID_SLOT)
return 0;
if (!on_enable && !chan_info->enabled) {
if (chan_info->slot != AD4130_INVALID_SLOT)
/* Case 3 */
ad4130_unlink_channel(st, channel);
/* Cases 3 & 5 */
return 0;
}
/* Cases 1 & 2 */
ret = ad4130_find_slot(st, setup_info, &slot, &overwrite);
if (ret)
return ret;
if (chan_info->slot != AD4130_INVALID_SLOT)
/* Case 1 */
ad4130_unlink_channel(st, channel);
if (overwrite) {
ret = ad4130_unlink_slot(st, slot);
if (ret)
return ret;
ret = ad4130_write_slot_setup(st, slot, setup_info);
if (ret)
return ret;
}
return ad4130_link_channel_slot(st, channel, slot);
}
static int ad4130_set_channel_enable(struct ad4130_state *st,
unsigned int channel, bool status)
{
struct ad4130_chan_info *chan_info = &st->chans_info[channel];
struct ad4130_slot_info *slot_info;
int ret;
if (chan_info->enabled == status)
return 0;
if (status) {
ret = ad4130_write_channel_setup(st, channel, true);
if (ret)
return ret;
}
slot_info = &st->slots_info[chan_info->slot];
ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel),
AD4130_CHANNEL_EN_MASK,
FIELD_PREP(AD4130_CHANNEL_EN_MASK, status));
if (ret)
return ret;
slot_info->enabled_channels += status ? 1 : -1;
chan_info->enabled = status;
return 0;
}
/*
* Table 58. FILTER_MODE_n bits and Filter Types of the datasheet describes
* the relation between filter mode, ODR and FS.
*
* Notice that the max ODR of each filter mode is not necessarily the
* absolute max ODR supported by the chip.
*
* The ODR divider is not explicitly specified, but it can be deduced based
* on the ODR range of each filter mode.
*
* For example, for Sinc4+Sinc1, max ODR is 218.18. That means that the
* absolute max ODR is divided by 11 to achieve the max ODR of this filter
* mode.
*
* The formulas for converting between ODR and FS for a specific filter
* mode can be deduced from the same table.
*
* Notice that FS = 1 actually means max ODR, and that ODR decreases by
* (maximum ODR / maximum FS) for each increment of FS.
*
* odr = MAX_ODR / odr_div * (1 - (fs - 1) / fs_max) <=>
* odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
* odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
* odr = MAX_ODR * (fs_max - fs + 1) / (fs_max * odr_div)
* (used in ad4130_fs_to_freq)
*
* For the opposite formula, FS can be extracted from the last one.
*
* MAX_ODR * (fs_max - fs + 1) = fs_max * odr_div * odr <=>
* fs_max - fs + 1 = fs_max * odr_div * odr / MAX_ODR <=>
* fs = 1 + fs_max - fs_max * odr_div * odr / MAX_ODR
* (used in ad4130_fs_to_freq)
*/
static void ad4130_freq_to_fs(enum ad4130_filter_mode filter_mode,
int val, int val2, unsigned int *fs)
{
const struct ad4130_filter_config *filter_config =
&ad4130_filter_configs[filter_mode];
u64 dividend, divisor;
int temp;
dividend = filter_config->fs_max * filter_config->odr_div *
((u64)val * NANO + val2);
divisor = (u64)AD4130_MAX_ODR * NANO;
temp = AD4130_FILTER_SELECT_MIN + filter_config->fs_max -
DIV64_U64_ROUND_CLOSEST(dividend, divisor);
if (temp < AD4130_FILTER_SELECT_MIN)
temp = AD4130_FILTER_SELECT_MIN;
else if (temp > filter_config->fs_max)
temp = filter_config->fs_max;
*fs = temp;
}
static void ad4130_fs_to_freq(enum ad4130_filter_mode filter_mode,
unsigned int fs, int *val, int *val2)
{
const struct ad4130_filter_config *filter_config =
&ad4130_filter_configs[filter_mode];
unsigned int dividend, divisor;
u64 temp;
dividend = (filter_config->fs_max - fs + AD4130_FILTER_SELECT_MIN) *
AD4130_MAX_ODR;
divisor = filter_config->fs_max * filter_config->odr_div;
temp = div_u64((u64)dividend * NANO, divisor);
*val = div_u64_rem(temp, NANO, val2);
}
static int ad4130_set_filter_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
unsigned int val)
{
struct ad4130_state *st = iio_priv(indio_dev);
unsigned int channel = chan->scan_index;
struct ad4130_chan_info *chan_info = &st->chans_info[channel];
struct ad4130_setup_info *setup_info = &chan_info->setup;
enum ad4130_filter_mode old_filter_mode;
int freq_val, freq_val2;
unsigned int old_fs;
int ret = 0;
mutex_lock(&st->lock);
if (setup_info->filter_mode == val)
goto out;
old_fs = setup_info->fs;
old_filter_mode = setup_info->filter_mode;
/*
* When switching between filter modes, try to match the ODR as
* close as possible. To do this, convert the current FS into ODR
* using the old filter mode, then convert it back into FS using
* the new filter mode.
*/
ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs,
&freq_val, &freq_val2);
ad4130_freq_to_fs(val, freq_val, freq_val2, &setup_info->fs);
setup_info->filter_mode = val;
ret = ad4130_write_channel_setup(st, channel, false);
if (ret) {
setup_info->fs = old_fs;
setup_info->filter_mode = old_filter_mode;
}
out:
mutex_unlock(&st->lock);
return ret;
}
static int ad4130_get_filter_mode(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan)
{
struct ad4130_state *st = iio_priv(indio_dev);
unsigned int channel = chan->scan_index;
struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
enum ad4130_filter_mode filter_mode;
mutex_lock(&st->lock);
filter_mode = setup_info->filter_mode;
mutex_unlock(&st->lock);
return filter_mode;
}
static const struct iio_enum ad4130_filter_mode_enum = {
.items = ad4130_filter_modes_str,
.num_items = ARRAY_SIZE(ad4130_filter_modes_str),
.set = ad4130_set_filter_mode,
.get = ad4130_get_filter_mode,
};
static const struct iio_chan_spec_ext_info ad4130_filter_mode_ext_info[] = {
IIO_ENUM("filter_mode", IIO_SEPARATE, &ad4130_filter_mode_enum),
IIO_ENUM_AVAILABLE("filter_mode", IIO_SHARED_BY_TYPE,
&ad4130_filter_mode_enum),
{ }
};
static const struct iio_chan_spec ad4130_channel_template = {
.type = IIO_VOLTAGE,
.indexed = 1,
.differential = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
.ext_info = ad4130_filter_mode_ext_info,
.scan_type = {
.sign = 'u',
.endianness = IIO_BE,
},
};
static int ad4130_set_channel_pga(struct ad4130_state *st, unsigned int channel,
int val, int val2)
{
struct ad4130_chan_info *chan_info = &st->chans_info[channel];
struct ad4130_setup_info *setup_info = &chan_info->setup;
unsigned int pga, old_pga;
int ret = 0;
for (pga = 0; pga < AD4130_MAX_PGA; pga++)
if (val == st->scale_tbls[setup_info->ref_sel][pga][0] &&
val2 == st->scale_tbls[setup_info->ref_sel][pga][1])
break;
if (pga == AD4130_MAX_PGA)
return -EINVAL;
mutex_lock(&st->lock);
if (pga == setup_info->pga)
goto out;
old_pga = setup_info->pga;
setup_info->pga = pga;
ret = ad4130_write_channel_setup(st, channel, false);
if (ret)
setup_info->pga = old_pga;
out:
mutex_unlock(&st->lock);
return ret;
}
static int ad4130_set_channel_freq(struct ad4130_state *st,
unsigned int channel, int val, int val2)
{
struct ad4130_chan_info *chan_info = &st->chans_info[channel];
struct ad4130_setup_info *setup_info = &chan_info->setup;
unsigned int fs, old_fs;
int ret = 0;
mutex_lock(&st->lock);
old_fs = setup_info->fs;
ad4130_freq_to_fs(setup_info->filter_mode, val, val2, &fs);
if (fs == setup_info->fs)
goto out;
setup_info->fs = fs;
ret = ad4130_write_channel_setup(st, channel, false);
if (ret)
setup_info->fs = old_fs;
out:
mutex_unlock(&st->lock);
return ret;
}
static int _ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel,
int *val)
{
struct ad4130_state *st = iio_priv(indio_dev);
int ret;
ret = ad4130_set_channel_enable(st, channel, true);
if (ret)
return ret;
reinit_completion(&st->completion);
ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS);
if (ret)
return ret;
ret = wait_for_completion_timeout(&st->completion,
msecs_to_jiffies(1000));
if (!ret)
return -ETIMEDOUT;
ret = ad4130_set_mode(st, AD4130_MODE_IDLE);
if (ret)
return ret;
ret = regmap_read(st->regmap, AD4130_DATA_REG, val);
if (ret)
return ret;
ret = ad4130_set_channel_enable(st, channel, false);
if (ret)
return ret;
return IIO_VAL_INT;
}
static int ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel,
int *val)
{
struct ad4130_state *st = iio_priv(indio_dev);
int ret;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
mutex_lock(&st->lock);
ret = _ad4130_read_sample(indio_dev, channel, val);
mutex_unlock(&st->lock);
iio_device_release_direct_mode(indio_dev);
return ret;
}
static int ad4130_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
{
struct ad4130_state *st = iio_priv(indio_dev);
unsigned int channel = chan->scan_index;
struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
switch (info) {
case IIO_CHAN_INFO_RAW:
return ad4130_read_sample(indio_dev, channel, val);
case IIO_CHAN_INFO_SCALE:
mutex_lock(&st->lock);
*val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0];
*val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1];
mutex_unlock(&st->lock);
return IIO_VAL_INT_PLUS_NANO;
case IIO_CHAN_INFO_OFFSET:
*val = st->bipolar ? -BIT(chan->scan_type.realbits - 1) : 0;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SAMP_FREQ:
mutex_lock(&st->lock);
ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs,
val, val2);
mutex_unlock(&st->lock);
return IIO_VAL_INT_PLUS_NANO;
default:
return -EINVAL;
}
}
static int ad4130_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long info)
{
struct ad4130_state *st = iio_priv(indio_dev);
unsigned int channel = chan->scan_index;
struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
const struct ad4130_filter_config *filter_config;
switch (info) {
case IIO_CHAN_INFO_SCALE:
*vals = (int *)st->scale_tbls[setup_info->ref_sel];
*length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2;
*type = IIO_VAL_INT_PLUS_NANO;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_SAMP_FREQ:
mutex_lock(&st->lock);
filter_config = &ad4130_filter_configs[setup_info->filter_mode];
mutex_unlock(&st->lock);
*vals = (int *)filter_config->samp_freq_avail;
*length = filter_config->samp_freq_avail_len * 2;
*type = IIO_VAL_FRACTIONAL;
return filter_config->samp_freq_avail_type;
default:
return -EINVAL;
}
}
static int ad4130_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
long info)
{
switch (info) {
case IIO_CHAN_INFO_SCALE:
case IIO_CHAN_INFO_SAMP_FREQ:
return IIO_VAL_INT_PLUS_NANO;
default:
return -EINVAL;
}
}
static int ad4130_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long info)
{
struct ad4130_state *st = iio_priv(indio_dev);
unsigned int channel = chan->scan_index;
switch (info) {
case IIO_CHAN_INFO_SCALE:
return ad4130_set_channel_pga(st, channel, val, val2);
case IIO_CHAN_INFO_SAMP_FREQ:
return ad4130_set_channel_freq(st, channel, val, val2);
default:
return -EINVAL;
}
}
static int ad4130_reg_access(struct iio_dev *indio_dev, unsigned int reg,
unsigned int writeval, unsigned int *readval)
{
struct ad4130_state *st = iio_priv(indio_dev);
if (readval)
return regmap_read(st->regmap, reg, readval);
return regmap_write(st->regmap, reg, writeval);
}
static int ad4130_update_scan_mode(struct iio_dev *indio_dev,
const unsigned long *scan_mask)
{
struct ad4130_state *st = iio_priv(indio_dev);
unsigned int channel;
unsigned int val = 0;
int ret;
mutex_lock(&st->lock);
for_each_set_bit(channel, scan_mask, indio_dev->num_channels) {
ret = ad4130_set_channel_enable(st, channel, true);
if (ret)
goto out;
val++;
}
st->num_enabled_channels = val;
out:
mutex_unlock(&st->lock);
return 0;
}
static int ad4130_set_fifo_watermark(struct iio_dev *indio_dev, unsigned int val)
{
struct ad4130_state *st = iio_priv(indio_dev);
unsigned int eff;
int ret;
if (val > AD4130_FIFO_SIZE)
return -EINVAL;
eff = val * st->num_enabled_channels;
if (eff > AD4130_FIFO_SIZE)
/*
* Always set watermark to a multiple of the number of
* enabled channels to avoid making the FIFO unaligned.
*/
eff = rounddown(AD4130_FIFO_SIZE, st->num_enabled_channels);
mutex_lock(&st->lock);
ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
AD4130_FIFO_CONTROL_WM_MASK,
FIELD_PREP(AD4130_FIFO_CONTROL_WM_MASK,
ad4130_watermark_reg_val(eff)));
if (ret)
goto out;
st->effective_watermark = eff;
st->watermark = val;
out:
mutex_unlock(&st->lock);
return ret;
}
static const struct iio_info ad4130_info = {
.read_raw = ad4130_read_raw,
.read_avail = ad4130_read_avail,
.write_raw_get_fmt = ad4130_write_raw_get_fmt,
.write_raw = ad4130_write_raw,
.update_scan_mode = ad4130_update_scan_mode,
.hwfifo_set_watermark = ad4130_set_fifo_watermark,
.debugfs_reg_access = ad4130_reg_access,
};
static int ad4130_buffer_postenable(struct iio_dev *indio_dev)
{
struct ad4130_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
ret = ad4130_set_watermark_interrupt_en(st, true);
if (ret)
goto out;
ret = irq_set_irq_type(st->spi->irq, st->inv_irq_trigger);
if (ret)
goto out;
ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM);
if (ret)
goto out;
ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS);
out:
mutex_unlock(&st->lock);
return ret;
}
static int ad4130_buffer_predisable(struct iio_dev *indio_dev)
{
struct ad4130_state *st = iio_priv(indio_dev);
unsigned int i;
int ret;
mutex_lock(&st->lock);
ret = ad4130_set_mode(st, AD4130_MODE_IDLE);
if (ret)
goto out;
ret = irq_set_irq_type(st->spi->irq, st->irq_trigger);
if (ret)
goto out;
ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED);
if (ret)
goto out;
ret = ad4130_set_watermark_interrupt_en(st, false);
if (ret)
goto out;
/*
* update_scan_mode() is not called in the disable path, disable all
* channels here.
*/
for (i = 0; i < indio_dev->num_channels; i++) {
ret = ad4130_set_channel_enable(st, i, false);
if (ret)
goto out;
}
out:
mutex_unlock(&st->lock);
return ret;
}
static const struct iio_buffer_setup_ops ad4130_buffer_ops = {
.postenable = ad4130_buffer_postenable,
.predisable = ad4130_buffer_predisable,
};
static ssize_t hwfifo_watermark_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev));
unsigned int val;
mutex_lock(&st->lock);
val = st->watermark;
mutex_unlock(&st->lock);
return sysfs_emit(buf, "%d\n", val);
}
static ssize_t hwfifo_enabled_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev));
unsigned int val;
int ret;
ret = regmap_read(st->regmap, AD4130_FIFO_CONTROL_REG, &val);
if (ret)
return ret;
val = FIELD_GET(AD4130_FIFO_CONTROL_MODE_MASK, val);
return sysfs_emit(buf, "%d\n", val != AD4130_FIFO_MODE_DISABLED);
}
static ssize_t hwfifo_watermark_min_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return sysfs_emit(buf, "%s\n", "1");
}
static ssize_t hwfifo_watermark_max_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return sysfs_emit(buf, "%s\n", __stringify(AD4130_FIFO_SIZE));
}
static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0);
static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0);
static const struct iio_dev_attr *ad4130_fifo_attributes[] = {
&iio_dev_attr_hwfifo_watermark_min,
&iio_dev_attr_hwfifo_watermark_max,
&iio_dev_attr_hwfifo_watermark,
&iio_dev_attr_hwfifo_enabled,
NULL
};
static int _ad4130_find_table_index(const unsigned int *tbl, size_t len,
unsigned int val)
{
unsigned int i;
for (i = 0; i < len; i++)
if (tbl[i] == val)
return i;
return -EINVAL;
}
#define ad4130_find_table_index(table, val) \
_ad4130_find_table_index(table, ARRAY_SIZE(table), val)
static int ad4130_get_ref_voltage(struct ad4130_state *st,
enum ad4130_ref_sel ref_sel)
{
switch (ref_sel) {
case AD4130_REF_REFIN1:
return regulator_get_voltage(st->regulators[2].consumer);
case AD4130_REF_REFIN2:
return regulator_get_voltage(st->regulators[3].consumer);
case AD4130_REF_AVDD_AVSS:
return regulator_get_voltage(st->regulators[0].consumer);
case AD4130_REF_REFOUT_AVSS:
return st->int_ref_uv;
default:
return -EINVAL;
}
}
static int ad4130_parse_fw_setup(struct ad4130_state *st,
struct fwnode_handle *child,
struct ad4130_setup_info *setup_info)
{
struct device *dev = &st->spi->dev;
u32 tmp;
int ret;
tmp = 0;
fwnode_property_read_u32(child, "adi,excitation-current-0-nanoamp", &tmp);
ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp);
if (ret < 0)
return dev_err_probe(dev, ret,
"Invalid excitation current %unA\n", tmp);
setup_info->iout0_val = ret;
tmp = 0;
fwnode_property_read_u32(child, "adi,excitation-current-1-nanoamp", &tmp);
ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp);
if (ret < 0)
return dev_err_probe(dev, ret,
"Invalid excitation current %unA\n", tmp);
setup_info->iout1_val = ret;
tmp = 0;
fwnode_property_read_u32(child, "adi,burnout-current-nanoamp", &tmp);
ret = ad4130_find_table_index(ad4130_burnout_current_na_tbl, tmp);
if (ret < 0)
return dev_err_probe(dev, ret,
"Invalid burnout current %unA\n", tmp);
setup_info->burnout = ret;
setup_info->ref_bufp = fwnode_property_read_bool(child, "adi,buffered-positive");
setup_info->ref_bufm = fwnode_property_read_bool(child, "adi,buffered-negative");
setup_info->ref_sel = AD4130_REF_REFIN1;
fwnode_property_read_u32(child, "adi,reference-select",
&setup_info->ref_sel);
if (setup_info->ref_sel >= AD4130_REF_SEL_MAX)
return dev_err_probe(dev, -EINVAL,
"Invalid reference selected %u\n",
setup_info->ref_sel);
if (setup_info->ref_sel == AD4130_REF_REFOUT_AVSS)
st->int_ref_en = true;
ret = ad4130_get_ref_voltage(st, setup_info->ref_sel);
if (ret < 0)
return dev_err_probe(dev, ret, "Cannot use reference %u\n",
setup_info->ref_sel);
return 0;
}
static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin)
{
struct device *dev = &st->spi->dev;
if (pin >= AD4130_MAX_DIFF_INPUTS)
return dev_err_probe(dev, -EINVAL,
"Invalid differential channel %u\n", pin);
if (pin >= AD4130_MAX_ANALOG_PINS)
return 0;
if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
return dev_err_probe(dev, -EINVAL,
"Pin %u already used with fn %u\n", pin,
st->pins_fn[pin]);
st->pins_fn[pin] |= AD4130_PIN_FN_DIFF;
return 0;
}
static int ad4130_validate_diff_channels(struct ad4130_state *st,
u32 *pins, unsigned int len)
{
unsigned int i;
int ret;
for (i = 0; i < len; i++) {
ret = ad4130_validate_diff_channel(st, pins[i]);
if (ret)
return ret;
}
return 0;
}
static int ad4130_validate_excitation_pin(struct ad4130_state *st, u32 pin)
{
struct device *dev = &st->spi->dev;
if (pin >= AD4130_MAX_ANALOG_PINS)
return dev_err_probe(dev, -EINVAL,
"Invalid excitation pin %u\n", pin);
if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
return dev_err_probe(dev, -EINVAL,
"Pin %u already used with fn %u\n", pin,
st->pins_fn[pin]);
st->pins_fn[pin] |= AD4130_PIN_FN_EXCITATION;
return 0;
}
static int ad4130_validate_vbias_pin(struct ad4130_state *st, u32 pin)
{
struct device *dev = &st->spi->dev;
if (pin >= AD4130_MAX_ANALOG_PINS)
return dev_err_probe(dev, -EINVAL, "Invalid vbias pin %u\n",
pin);
if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
return dev_err_probe(dev, -EINVAL,
"Pin %u already used with fn %u\n", pin,
st->pins_fn[pin]);
st->pins_fn[pin] |= AD4130_PIN_FN_VBIAS;
return 0;
}
static int ad4130_validate_vbias_pins(struct ad4130_state *st,
u32 *pins, unsigned int len)
{
unsigned int i;
int ret;
for (i = 0; i < st->num_vbias_pins; i++) {
ret = ad4130_validate_vbias_pin(st, pins[i]);
if (ret)
return ret;
}
return 0;
}
static int ad4130_parse_fw_channel(struct iio_dev *indio_dev,
struct fwnode_handle *child)
{
struct ad4130_state *st = iio_priv(indio_dev);
unsigned int resolution = ad4130_resolution(st);
unsigned int index = indio_dev->num_channels++;
struct device *dev = &st->spi->dev;
struct ad4130_chan_info *chan_info;
struct iio_chan_spec *chan;
u32 pins[2];
int ret;
if (index >= AD4130_MAX_CHANNELS)
return dev_err_probe(dev, -EINVAL, "Too many channels\n");
chan = &st->chans[index];
chan_info = &st->chans_info[index];
*chan = ad4130_channel_template;
chan->scan_type.realbits = resolution;
chan->scan_type.storagebits = resolution;
chan->scan_index = index;
chan_info->slot = AD4130_INVALID_SLOT;
chan_info->setup.fs = AD4130_FILTER_SELECT_MIN;
chan_info->initialized = true;
ret = fwnode_property_read_u32_array(child, "diff-channels", pins,
ARRAY_SIZE(pins));
if (ret)
return ret;
ret = ad4130_validate_diff_channels(st, pins, ARRAY_SIZE(pins));
if (ret)
return ret;
chan->channel = pins[0];
chan->channel2 = pins[1];
ret = ad4130_parse_fw_setup(st, child, &chan_info->setup);
if (ret)
return ret;
fwnode_property_read_u32(child, "adi,excitation-pin-0",
&chan_info->iout0);
if (chan_info->setup.iout0_val != AD4130_IOUT_OFF) {
ret = ad4130_validate_excitation_pin(st, chan_info->iout0);
if (ret)
return ret;
}
fwnode_property_read_u32(child, "adi,excitation-pin-1",
&chan_info->iout1);
if (chan_info->setup.iout1_val != AD4130_IOUT_OFF) {
ret = ad4130_validate_excitation_pin(st, chan_info->iout1);
if (ret)
return ret;
}
return 0;
}
static int ad4130_parse_fw_children(struct iio_dev *indio_dev)
{
struct ad4130_state *st = iio_priv(indio_dev);
struct device *dev = &st->spi->dev;
struct fwnode_handle *child;
int ret;
indio_dev->channels = st->chans;
device_for_each_child_node(dev, child) {
ret = ad4130_parse_fw_channel(indio_dev, child);
if (ret) {
fwnode_handle_put(child);
return ret;
}
}
return 0;
}
static int ad4310_parse_fw(struct iio_dev *indio_dev)
{
struct ad4130_state *st = iio_priv(indio_dev);
struct device *dev = &st->spi->dev;
u32 ext_clk_freq = AD4130_MCLK_FREQ_76_8KHZ;
unsigned int i;
int avdd_uv;
int irq;
int ret;
st->mclk = devm_clk_get_optional(dev, "mclk");
if (IS_ERR(st->mclk))
return dev_err_probe(dev, PTR_ERR(st->mclk),
"Failed to get mclk\n");
st->int_pin_sel = AD4130_INT_PIN_INT;
for (i = 0; i < ARRAY_SIZE(ad4130_int_pin_names); i++) {
irq = fwnode_irq_get_byname(dev_fwnode(dev),
ad4130_int_pin_names[i]);
if (irq > 0) {
st->int_pin_sel = i;
break;
}
}
if (st->int_pin_sel == AD4130_INT_PIN_DOUT)
return dev_err_probe(dev, -EINVAL,
"Cannot use DOUT as interrupt pin\n");
if (st->int_pin_sel == AD4130_INT_PIN_P2)
st->pins_fn[AD4130_AIN3_P2] = AD4130_PIN_FN_SPECIAL;
device_property_read_u32(dev, "adi,ext-clk-freq-hz", &ext_clk_freq);
if (ext_clk_freq != AD4130_MCLK_FREQ_153_6KHZ &&
ext_clk_freq != AD4130_MCLK_FREQ_76_8KHZ)
return dev_err_probe(dev, -EINVAL,
"Invalid external clock frequency %u\n",
ext_clk_freq);
if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ)
st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT;
else if (st->mclk)
st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT;
else
st->mclk_sel = AD4130_MCLK_76_8KHZ;
if (st->int_pin_sel == AD4130_INT_PIN_CLK &&
st->mclk_sel != AD4130_MCLK_76_8KHZ)
return dev_err_probe(dev, -EINVAL,
"Invalid clock %u for interrupt pin %u\n",
st->mclk_sel, st->int_pin_sel);
st->int_ref_uv = AD4130_INT_REF_2_5V;
/*
* When the AVDD supply is set to below 2.5V the internal reference of
* 1.25V should be selected.
* See datasheet page 37, section ADC REFERENCE.
*/
avdd_uv = regulator_get_voltage(st->regulators[0].consumer);
if (avdd_uv > 0 && avdd_uv < AD4130_INT_REF_2_5V)
st->int_ref_uv = AD4130_INT_REF_1_25V;
st->bipolar = device_property_read_bool(dev, "adi,bipolar");
ret = device_property_count_u32(dev, "adi,vbias-pins");
if (ret > 0) {
if (ret > AD4130_MAX_ANALOG_PINS)
return dev_err_probe(dev, -EINVAL,
"Too many vbias pins %u\n", ret);
st->num_vbias_pins = ret;
ret = device_property_read_u32_array(dev, "adi,vbias-pins",
st->vbias_pins,
st->num_vbias_pins);
if (ret)
return dev_err_probe(dev, ret,
"Failed to read vbias pins\n");
ret = ad4130_validate_vbias_pins(st, st->vbias_pins,
st->num_vbias_pins);
if (ret)
return ret;
}
ret = ad4130_parse_fw_children(indio_dev);
if (ret)
return ret;
return 0;
}
static void ad4130_fill_scale_tbls(struct ad4130_state *st)
{
unsigned int pow = ad4130_resolution(st) - st->bipolar;
unsigned int i, j;
for (i = 0; i < AD4130_REF_SEL_MAX; i++) {
int ret;
u64 nv;
ret = ad4130_get_ref_voltage(st, i);
if (ret < 0)
continue;
nv = (u64)ret * NANO;
for (j = 0; j < AD4130_MAX_PGA; j++)
st->scale_tbls[i][j][1] = div_u64(nv >> (pow + j), MILLI);
}
}
static void ad4130_clk_disable_unprepare(void *clk)
{
clk_disable_unprepare(clk);
}
static int ad4130_set_mclk_sel(struct ad4130_state *st,
enum ad4130_mclk_sel mclk_sel)
{
return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG,
AD4130_ADC_CONTROL_MCLK_SEL_MASK,
FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK,
mclk_sel));
}
static unsigned long ad4130_int_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
return AD4130_MCLK_FREQ_76_8KHZ;
}
static int ad4130_int_clk_is_enabled(struct clk_hw *hw)
{
struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT;
}
static int ad4130_int_clk_prepare(struct clk_hw *hw)
{
struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
int ret;
ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ_OUT);
if (ret)
return ret;
st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT;
return 0;
}
static void ad4130_int_clk_unprepare(struct clk_hw *hw)
{
struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
int ret;
ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ);
if (ret)
return;
st->mclk_sel = AD4130_MCLK_76_8KHZ;
}
static const struct clk_ops ad4130_int_clk_ops = {
.recalc_rate = ad4130_int_clk_recalc_rate,
.is_enabled = ad4130_int_clk_is_enabled,
.prepare = ad4130_int_clk_prepare,
.unprepare = ad4130_int_clk_unprepare,
};
static void ad4130_clk_del_provider(void *of_node)
{
of_clk_del_provider(of_node);
}
static int ad4130_setup_int_clk(struct ad4130_state *st)
{
struct device *dev = &st->spi->dev;
struct device_node *of_node = dev_of_node(dev);
struct clk_init_data init;
const char *clk_name;
struct clk *clk;
int ret;
if (st->int_pin_sel == AD4130_INT_PIN_CLK ||
st->mclk_sel != AD4130_MCLK_76_8KHZ)
return 0;
if (!of_node)
return 0;
clk_name = of_node->name;
of_property_read_string(of_node, "clock-output-names", &clk_name);
init.name = clk_name;
init.ops = &ad4130_int_clk_ops;
st->int_clk_hw.init = &init;
clk = devm_clk_register(dev, &st->int_clk_hw);
if (IS_ERR(clk))
return PTR_ERR(clk);
ret = of_clk_add_provider(of_node, of_clk_src_simple_get, clk);
if (ret)
return ret;
return devm_add_action_or_reset(dev, ad4130_clk_del_provider, of_node);
}
static int ad4130_setup(struct iio_dev *indio_dev)
{
struct ad4130_state *st = iio_priv(indio_dev);
struct device *dev = &st->spi->dev;
unsigned int int_ref_val;
unsigned long rate = AD4130_MCLK_FREQ_76_8KHZ;
unsigned int val;
unsigned int i;
int ret;
if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT)
rate = AD4130_MCLK_FREQ_153_6KHZ;
ret = clk_set_rate(st->mclk, rate);
if (ret)
return ret;
ret = clk_prepare_enable(st->mclk);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, ad4130_clk_disable_unprepare,
st->mclk);
if (ret)
return ret;
if (st->int_ref_uv == AD4130_INT_REF_2_5V)
int_ref_val = AD4130_INT_REF_VAL_2_5V;
else
int_ref_val = AD4130_INT_REF_VAL_1_25V;
/* Switch to SPI 4-wire mode. */
val = FIELD_PREP(AD4130_ADC_CONTROL_CSB_EN_MASK, 1);
val |= FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, st->bipolar);
val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, st->int_ref_en);
val |= FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, AD4130_MODE_IDLE);
val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel);
val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_VAL_MASK, int_ref_val);
ret = regmap_write(st->regmap, AD4130_ADC_CONTROL_REG, val);
if (ret)
return ret;
/*
* Configure all GPIOs for output. If configured, the interrupt function
* of P2 takes priority over the GPIO out function.
*/
val = AD4130_IO_CONTROL_GPIO_CTRL_MASK;
val |= FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel);
ret = regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val);
if (ret)
return ret;
val = 0;
for (i = 0; i < st->num_vbias_pins; i++)
val |= BIT(st->vbias_pins[i]);
ret = regmap_write(st->regmap, AD4130_VBIAS_REG, val);
if (ret)
return ret;
ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
AD4130_FIFO_CONTROL_HEADER_MASK, 0);
if (ret)
return ret;
/* FIFO watermark interrupt starts out as enabled, disable it. */
ret = ad4130_set_watermark_interrupt_en(st, false);
if (ret)
return ret;
/* Setup channels. */
for (i = 0; i < indio_dev->num_channels; i++) {
struct ad4130_chan_info *chan_info = &st->chans_info[i];
struct iio_chan_spec *chan = &st->chans[i];
unsigned int val;
val = FIELD_PREP(AD4130_CHANNEL_AINP_MASK, chan->channel) |
FIELD_PREP(AD4130_CHANNEL_AINM_MASK, chan->channel2) |
FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, chan_info->iout0) |
FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, chan_info->iout1);
ret = regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val);
if (ret)
return ret;
}
return 0;
}
static int ad4130_soft_reset(struct ad4130_state *st)
{
int ret;
ret = spi_write(st->spi, st->reset_buf, sizeof(st->reset_buf));
if (ret)
return ret;
fsleep(AD4130_RESET_SLEEP_US);
return 0;
}
static void ad4130_disable_regulators(void *data)
{
struct ad4130_state *st = data;
regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
}
static int ad4130_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct iio_dev *indio_dev;
struct ad4130_state *st;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
memset(st->reset_buf, 0xff, sizeof(st->reset_buf));
init_completion(&st->completion);
mutex_init(&st->lock);
st->spi = spi;
/*
* Xfer: [ XFR1 ] [ XFR2 ]
* Master: 0x7D N ......................
* Slave: ...... DATA1 DATA2 ... DATAN
*/
st->fifo_tx_buf[0] = AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG;
st->fifo_xfer[0].tx_buf = st->fifo_tx_buf;
st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf);
st->fifo_xfer[1].rx_buf = st->fifo_rx_buf;
spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer,
ARRAY_SIZE(st->fifo_xfer));
indio_dev->name = AD4130_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &ad4130_info;
st->regmap = devm_regmap_init(dev, NULL, st, &ad4130_regmap_config);
if (IS_ERR(st->regmap))
return PTR_ERR(st->regmap);
st->regulators[0].supply = "avdd";
st->regulators[1].supply = "iovdd";
st->regulators[2].supply = "refin1";
st->regulators[3].supply = "refin2";
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
st->regulators);
if (ret)
return dev_err_probe(dev, ret, "Failed to get regulators\n");
ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable regulators\n");
ret = devm_add_action_or_reset(dev, ad4130_disable_regulators, st);
if (ret)
return dev_err_probe(dev, ret,
"Failed to add regulators disable action\n");
ret = ad4130_soft_reset(st);
if (ret)
return ret;
ret = ad4310_parse_fw(indio_dev);
if (ret)
return ret;
ret = ad4130_setup(indio_dev);
if (ret)
return ret;
ret = ad4130_setup_int_clk(st);
if (ret)
return ret;
ad4130_fill_scale_tbls(st);
st->gc.owner = THIS_MODULE;
st->gc.label = AD4130_NAME;
st->gc.base = -1;
st->gc.ngpio = AD4130_MAX_GPIOS;
st->gc.parent = dev;
st->gc.can_sleep = true;
st->gc.init_valid_mask = ad4130_gpio_init_valid_mask;
st->gc.get_direction = ad4130_gpio_get_direction;
st->gc.set = ad4130_gpio_set;
ret = devm_gpiochip_add_data(dev, &st->gc, st);
if (ret)
return ret;
ret = devm_iio_kfifo_buffer_setup_ext(dev, indio_dev,
&ad4130_buffer_ops,
ad4130_fifo_attributes);
if (ret)
return ret;
ret = devm_request_threaded_irq(dev, spi->irq, NULL,
ad4130_irq_handler, IRQF_ONESHOT,
indio_dev->name, indio_dev);
if (ret)
return dev_err_probe(dev, ret, "Failed to request irq\n");
/*
* When the chip enters FIFO mode, IRQ polarity is inverted.
* When the chip exits FIFO mode, IRQ polarity returns to normal.
* See datasheet pages: 65, FIFO Watermark Interrupt section,
* and 71, Bit Descriptions for STATUS Register, RDYB.
* Cache the normal and inverted IRQ triggers to set them when
* entering and exiting FIFO mode.
*/
st->irq_trigger = irq_get_trigger_type(spi->irq);
if (st->irq_trigger & IRQF_TRIGGER_RISING)
st->inv_irq_trigger = IRQF_TRIGGER_FALLING;
else if (st->irq_trigger & IRQF_TRIGGER_FALLING)
st->inv_irq_trigger = IRQF_TRIGGER_RISING;
else
return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n",
st->irq_trigger);
return devm_iio_device_register(dev, indio_dev);
}
static const struct of_device_id ad4130_of_match[] = {
{
.compatible = "adi,ad4130",
},
{ }
};
MODULE_DEVICE_TABLE(of, ad4130_of_match);
static struct spi_driver ad4130_driver = {
.driver = {
.name = AD4130_NAME,
.of_match_table = ad4130_of_match,
},
.probe = ad4130_probe,
};
module_spi_driver(ad4130_driver);
MODULE_AUTHOR("Cosmin Tanislav <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD4130 SPI driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/adc/ad4130.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI ADC108S102 SPI ADC driver
*
* Copyright (c) 2013-2015 Intel Corporation.
* Copyright (c) 2017 Siemens AG
*
* This IIO device driver is designed to work with the following
* analog to digital converters from Texas Instruments:
* ADC108S102
* ADC128S102
* The communication with ADC chip is via the SPI bus (mode 3).
*/
#include <linux/acpi.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/types.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
/*
* In case of ACPI, we use the hard-wired 5000 mV of the Galileo and IOT2000
* boards as default for the reference pin VA. Device tree users encode that
* via the vref-supply regulator.
*/
#define ADC108S102_VA_MV_ACPI_DEFAULT 5000
/*
* Defining the ADC resolution being 12 bits, we can use the same driver for
* both ADC108S102 (10 bits resolution) and ADC128S102 (12 bits resolution)
* chips. The ADC108S102 effectively returns a 12-bit result with the 2
* least-significant bits unset.
*/
#define ADC108S102_BITS 12
#define ADC108S102_MAX_CHANNELS 8
/*
* 16-bit SPI command format:
* [15:14] Ignored
* [13:11] 3-bit channel address
* [10:0] Ignored
*/
#define ADC108S102_CMD(ch) ((u16)(ch) << 11)
/*
* 16-bit SPI response format:
* [15:12] Zeros
* [11:0] 12-bit ADC sample (for ADC108S102, [1:0] will always be 0).
*/
#define ADC108S102_RES_DATA(res) ((u16)res & GENMASK(11, 0))
struct adc108s102_state {
struct spi_device *spi;
struct regulator *reg;
u32 va_millivolt;
/* SPI transfer used by triggered buffer handler*/
struct spi_transfer ring_xfer;
/* SPI transfer used by direct scan */
struct spi_transfer scan_single_xfer;
/* SPI message used by ring_xfer SPI transfer */
struct spi_message ring_msg;
/* SPI message used by scan_single_xfer SPI transfer */
struct spi_message scan_single_msg;
/*
* SPI message buffers:
* tx_buf: |C0|C1|C2|C3|C4|C5|C6|C7|XX|
* rx_buf: |XX|R0|R1|R2|R3|R4|R5|R6|R7|tt|tt|tt|tt|
*
* tx_buf: 8 channel read commands, plus 1 dummy command
* rx_buf: 1 dummy response, 8 channel responses
*/
__be16 rx_buf[9] __aligned(IIO_DMA_MINALIGN);
__be16 tx_buf[9] __aligned(IIO_DMA_MINALIGN);
};
#define ADC108S102_V_CHAN(index) \
{ \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = index, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.address = index, \
.scan_index = index, \
.scan_type = { \
.sign = 'u', \
.realbits = ADC108S102_BITS, \
.storagebits = 16, \
.endianness = IIO_BE, \
}, \
}
static const struct iio_chan_spec adc108s102_channels[] = {
ADC108S102_V_CHAN(0),
ADC108S102_V_CHAN(1),
ADC108S102_V_CHAN(2),
ADC108S102_V_CHAN(3),
ADC108S102_V_CHAN(4),
ADC108S102_V_CHAN(5),
ADC108S102_V_CHAN(6),
ADC108S102_V_CHAN(7),
IIO_CHAN_SOFT_TIMESTAMP(8),
};
static int adc108s102_update_scan_mode(struct iio_dev *indio_dev,
unsigned long const *active_scan_mask)
{
struct adc108s102_state *st = iio_priv(indio_dev);
unsigned int bit, cmds;
/*
* Fill in the first x shorts of tx_buf with the number of channels
* enabled for sampling by the triggered buffer.
*/
cmds = 0;
for_each_set_bit(bit, active_scan_mask, ADC108S102_MAX_CHANNELS)
st->tx_buf[cmds++] = cpu_to_be16(ADC108S102_CMD(bit));
/* One dummy command added, to clock in the last response */
st->tx_buf[cmds++] = 0x00;
/* build SPI ring message */
st->ring_xfer.tx_buf = &st->tx_buf[0];
st->ring_xfer.rx_buf = &st->rx_buf[0];
st->ring_xfer.len = cmds * sizeof(st->tx_buf[0]);
spi_message_init_with_transfers(&st->ring_msg, &st->ring_xfer, 1);
return 0;
}
static irqreturn_t adc108s102_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct adc108s102_state *st = iio_priv(indio_dev);
int ret;
ret = spi_sync(st->spi, &st->ring_msg);
if (ret < 0)
goto out_notify;
/* Skip the dummy response in the first slot */
iio_push_to_buffers_with_ts_unaligned(indio_dev,
&st->rx_buf[1],
st->ring_xfer.len - sizeof(st->rx_buf[1]),
iio_get_time_ns(indio_dev));
out_notify:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int adc108s102_scan_direct(struct adc108s102_state *st, unsigned int ch)
{
int ret;
st->tx_buf[0] = cpu_to_be16(ADC108S102_CMD(ch));
ret = spi_sync(st->spi, &st->scan_single_msg);
if (ret)
return ret;
/* Skip the dummy response in the first slot */
return be16_to_cpu(st->rx_buf[1]);
}
static int adc108s102_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long m)
{
struct adc108s102_state *st = iio_priv(indio_dev);
int ret;
switch (m) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = adc108s102_scan_direct(st, chan->address);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = ADC108S102_RES_DATA(ret);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
if (chan->type != IIO_VOLTAGE)
break;
*val = st->va_millivolt;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
default:
break;
}
return -EINVAL;
}
static const struct iio_info adc108s102_info = {
.read_raw = &adc108s102_read_raw,
.update_scan_mode = &adc108s102_update_scan_mode,
};
static void adc108s102_reg_disable(void *reg)
{
regulator_disable(reg);
}
static int adc108s102_probe(struct spi_device *spi)
{
struct adc108s102_state *st;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
if (ACPI_COMPANION(&spi->dev)) {
st->va_millivolt = ADC108S102_VA_MV_ACPI_DEFAULT;
} else {
st->reg = devm_regulator_get(&spi->dev, "vref");
if (IS_ERR(st->reg))
return PTR_ERR(st->reg);
ret = regulator_enable(st->reg);
if (ret < 0) {
dev_err(&spi->dev, "Cannot enable vref regulator\n");
return ret;
}
ret = devm_add_action_or_reset(&spi->dev, adc108s102_reg_disable,
st->reg);
if (ret)
return ret;
ret = regulator_get_voltage(st->reg);
if (ret < 0) {
dev_err(&spi->dev, "vref get voltage failed\n");
return ret;
}
st->va_millivolt = ret / 1000;
}
st->spi = spi;
indio_dev->name = spi->modalias;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = adc108s102_channels;
indio_dev->num_channels = ARRAY_SIZE(adc108s102_channels);
indio_dev->info = &adc108s102_info;
/* Setup default message */
st->scan_single_xfer.tx_buf = st->tx_buf;
st->scan_single_xfer.rx_buf = st->rx_buf;
st->scan_single_xfer.len = 2 * sizeof(st->tx_buf[0]);
spi_message_init_with_transfers(&st->scan_single_msg,
&st->scan_single_xfer, 1);
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
&adc108s102_trigger_handler,
NULL);
if (ret)
return ret;
ret = devm_iio_device_register(&spi->dev, indio_dev);
if (ret)
dev_err(&spi->dev, "Failed to register IIO device\n");
return ret;
}
static const struct of_device_id adc108s102_of_match[] = {
{ .compatible = "ti,adc108s102" },
{ }
};
MODULE_DEVICE_TABLE(of, adc108s102_of_match);
#ifdef CONFIG_ACPI
static const struct acpi_device_id adc108s102_acpi_ids[] = {
{ "INT3495", 0 },
{ }
};
MODULE_DEVICE_TABLE(acpi, adc108s102_acpi_ids);
#endif
static const struct spi_device_id adc108s102_id[] = {
{ "adc108s102", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, adc108s102_id);
static struct spi_driver adc108s102_driver = {
.driver = {
.name = "adc108s102",
.of_match_table = adc108s102_of_match,
.acpi_match_table = ACPI_PTR(adc108s102_acpi_ids),
},
.probe = adc108s102_probe,
.id_table = adc108s102_id,
};
module_spi_driver(adc108s102_driver);
MODULE_AUTHOR("Bogdan Pricop <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments ADC108S102 and ADC128S102 driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ti-adc108s102.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Support code for Analog Devices Sigma-Delta ADCs
*
* Copyright 2012 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/align.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/adc/ad_sigma_delta.h>
#include <asm/unaligned.h>
#define AD_SD_COMM_CHAN_MASK 0x3
#define AD_SD_REG_COMM 0x00
#define AD_SD_REG_DATA 0x03
/**
* ad_sd_set_comm() - Set communications register
*
* @sigma_delta: The sigma delta device
* @comm: New value for the communications register
*/
void ad_sd_set_comm(struct ad_sigma_delta *sigma_delta, uint8_t comm)
{
/* Some variants use the lower two bits of the communications register
* to select the channel */
sigma_delta->comm = comm & AD_SD_COMM_CHAN_MASK;
}
EXPORT_SYMBOL_NS_GPL(ad_sd_set_comm, IIO_AD_SIGMA_DELTA);
/**
* ad_sd_write_reg() - Write a register
*
* @sigma_delta: The sigma delta device
* @reg: Address of the register
* @size: Size of the register (0-3)
* @val: Value to write to the register
*
* Returns 0 on success, an error code otherwise.
**/
int ad_sd_write_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg,
unsigned int size, unsigned int val)
{
uint8_t *data = sigma_delta->tx_buf;
struct spi_transfer t = {
.tx_buf = data,
.len = size + 1,
.cs_change = sigma_delta->keep_cs_asserted,
};
struct spi_message m;
int ret;
data[0] = (reg << sigma_delta->info->addr_shift) | sigma_delta->comm;
switch (size) {
case 3:
put_unaligned_be24(val, &data[1]);
break;
case 2:
put_unaligned_be16(val, &data[1]);
break;
case 1:
data[1] = val;
break;
case 0:
break;
default:
return -EINVAL;
}
spi_message_init(&m);
spi_message_add_tail(&t, &m);
if (sigma_delta->bus_locked)
ret = spi_sync_locked(sigma_delta->spi, &m);
else
ret = spi_sync(sigma_delta->spi, &m);
return ret;
}
EXPORT_SYMBOL_NS_GPL(ad_sd_write_reg, IIO_AD_SIGMA_DELTA);
static int ad_sd_read_reg_raw(struct ad_sigma_delta *sigma_delta,
unsigned int reg, unsigned int size, uint8_t *val)
{
uint8_t *data = sigma_delta->tx_buf;
int ret;
struct spi_transfer t[] = {
{
.tx_buf = data,
.len = 1,
}, {
.rx_buf = val,
.len = size,
.cs_change = sigma_delta->bus_locked,
},
};
struct spi_message m;
spi_message_init(&m);
if (sigma_delta->info->has_registers) {
data[0] = reg << sigma_delta->info->addr_shift;
data[0] |= sigma_delta->info->read_mask;
data[0] |= sigma_delta->comm;
spi_message_add_tail(&t[0], &m);
}
spi_message_add_tail(&t[1], &m);
if (sigma_delta->bus_locked)
ret = spi_sync_locked(sigma_delta->spi, &m);
else
ret = spi_sync(sigma_delta->spi, &m);
return ret;
}
/**
* ad_sd_read_reg() - Read a register
*
* @sigma_delta: The sigma delta device
* @reg: Address of the register
* @size: Size of the register (1-4)
* @val: Read value
*
* Returns 0 on success, an error code otherwise.
**/
int ad_sd_read_reg(struct ad_sigma_delta *sigma_delta,
unsigned int reg, unsigned int size, unsigned int *val)
{
int ret;
ret = ad_sd_read_reg_raw(sigma_delta, reg, size, sigma_delta->rx_buf);
if (ret < 0)
goto out;
switch (size) {
case 4:
*val = get_unaligned_be32(sigma_delta->rx_buf);
break;
case 3:
*val = get_unaligned_be24(sigma_delta->rx_buf);
break;
case 2:
*val = get_unaligned_be16(sigma_delta->rx_buf);
break;
case 1:
*val = sigma_delta->rx_buf[0];
break;
default:
ret = -EINVAL;
break;
}
out:
return ret;
}
EXPORT_SYMBOL_NS_GPL(ad_sd_read_reg, IIO_AD_SIGMA_DELTA);
/**
* ad_sd_reset() - Reset the serial interface
*
* @sigma_delta: The sigma delta device
* @reset_length: Number of SCLKs with DIN = 1
*
* Returns 0 on success, an error code otherwise.
**/
int ad_sd_reset(struct ad_sigma_delta *sigma_delta,
unsigned int reset_length)
{
uint8_t *buf;
unsigned int size;
int ret;
size = DIV_ROUND_UP(reset_length, 8);
buf = kcalloc(size, sizeof(*buf), GFP_KERNEL);
if (!buf)
return -ENOMEM;
memset(buf, 0xff, size);
ret = spi_write(sigma_delta->spi, buf, size);
kfree(buf);
return ret;
}
EXPORT_SYMBOL_NS_GPL(ad_sd_reset, IIO_AD_SIGMA_DELTA);
int ad_sd_calibrate(struct ad_sigma_delta *sigma_delta,
unsigned int mode, unsigned int channel)
{
int ret;
unsigned long timeout;
ret = ad_sigma_delta_set_channel(sigma_delta, channel);
if (ret)
return ret;
spi_bus_lock(sigma_delta->spi->master);
sigma_delta->bus_locked = true;
sigma_delta->keep_cs_asserted = true;
reinit_completion(&sigma_delta->completion);
ret = ad_sigma_delta_set_mode(sigma_delta, mode);
if (ret < 0)
goto out;
sigma_delta->irq_dis = false;
enable_irq(sigma_delta->spi->irq);
timeout = wait_for_completion_timeout(&sigma_delta->completion, 2 * HZ);
if (timeout == 0) {
sigma_delta->irq_dis = true;
disable_irq_nosync(sigma_delta->spi->irq);
ret = -EIO;
} else {
ret = 0;
}
out:
sigma_delta->keep_cs_asserted = false;
ad_sigma_delta_set_mode(sigma_delta, AD_SD_MODE_IDLE);
sigma_delta->bus_locked = false;
spi_bus_unlock(sigma_delta->spi->master);
return ret;
}
EXPORT_SYMBOL_NS_GPL(ad_sd_calibrate, IIO_AD_SIGMA_DELTA);
/**
* ad_sd_calibrate_all() - Performs channel calibration
* @sigma_delta: The sigma delta device
* @cb: Array of channels and calibration type to perform
* @n: Number of items in cb
*
* Returns 0 on success, an error code otherwise.
**/
int ad_sd_calibrate_all(struct ad_sigma_delta *sigma_delta,
const struct ad_sd_calib_data *cb, unsigned int n)
{
unsigned int i;
int ret;
for (i = 0; i < n; i++) {
ret = ad_sd_calibrate(sigma_delta, cb[i].mode, cb[i].channel);
if (ret)
return ret;
}
return 0;
}
EXPORT_SYMBOL_NS_GPL(ad_sd_calibrate_all, IIO_AD_SIGMA_DELTA);
/**
* ad_sigma_delta_single_conversion() - Performs a single data conversion
* @indio_dev: The IIO device
* @chan: The conversion is done for this channel
* @val: Pointer to the location where to store the read value
*
* Returns: 0 on success, an error value otherwise.
*/
int ad_sigma_delta_single_conversion(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, int *val)
{
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
unsigned int sample, raw_sample;
unsigned int data_reg;
int ret = 0;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ad_sigma_delta_set_channel(sigma_delta, chan->address);
spi_bus_lock(sigma_delta->spi->master);
sigma_delta->bus_locked = true;
sigma_delta->keep_cs_asserted = true;
reinit_completion(&sigma_delta->completion);
ad_sigma_delta_set_mode(sigma_delta, AD_SD_MODE_SINGLE);
sigma_delta->irq_dis = false;
enable_irq(sigma_delta->spi->irq);
ret = wait_for_completion_interruptible_timeout(
&sigma_delta->completion, HZ);
if (ret == 0)
ret = -EIO;
if (ret < 0)
goto out;
if (sigma_delta->info->data_reg != 0)
data_reg = sigma_delta->info->data_reg;
else
data_reg = AD_SD_REG_DATA;
ret = ad_sd_read_reg(sigma_delta, data_reg,
DIV_ROUND_UP(chan->scan_type.realbits + chan->scan_type.shift, 8),
&raw_sample);
out:
if (!sigma_delta->irq_dis) {
disable_irq_nosync(sigma_delta->spi->irq);
sigma_delta->irq_dis = true;
}
sigma_delta->keep_cs_asserted = false;
ad_sigma_delta_set_mode(sigma_delta, AD_SD_MODE_IDLE);
sigma_delta->bus_locked = false;
spi_bus_unlock(sigma_delta->spi->master);
iio_device_release_direct_mode(indio_dev);
if (ret)
return ret;
sample = raw_sample >> chan->scan_type.shift;
sample &= (1 << chan->scan_type.realbits) - 1;
*val = sample;
ret = ad_sigma_delta_postprocess_sample(sigma_delta, raw_sample);
if (ret)
return ret;
return IIO_VAL_INT;
}
EXPORT_SYMBOL_NS_GPL(ad_sigma_delta_single_conversion, IIO_AD_SIGMA_DELTA);
static int ad_sd_buffer_postenable(struct iio_dev *indio_dev)
{
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
unsigned int i, slot, samples_buf_size;
unsigned int channel;
uint8_t *samples_buf;
int ret;
if (sigma_delta->num_slots == 1) {
channel = find_first_bit(indio_dev->active_scan_mask,
indio_dev->masklength);
ret = ad_sigma_delta_set_channel(sigma_delta,
indio_dev->channels[channel].address);
if (ret)
return ret;
slot = 1;
} else {
/*
* At this point update_scan_mode already enabled the required channels.
* For sigma-delta sequencer drivers with multiple slots, an update_scan_mode
* implementation is mandatory.
*/
slot = 0;
for_each_set_bit(i, indio_dev->active_scan_mask, indio_dev->masklength) {
sigma_delta->slots[slot] = indio_dev->channels[i].address;
slot++;
}
}
sigma_delta->active_slots = slot;
sigma_delta->current_slot = 0;
if (sigma_delta->active_slots > 1) {
ret = ad_sigma_delta_append_status(sigma_delta, true);
if (ret)
return ret;
}
samples_buf_size = ALIGN(slot * indio_dev->channels[0].scan_type.storagebits, 8);
samples_buf_size += sizeof(int64_t);
samples_buf = devm_krealloc(&sigma_delta->spi->dev, sigma_delta->samples_buf,
samples_buf_size, GFP_KERNEL);
if (!samples_buf)
return -ENOMEM;
sigma_delta->samples_buf = samples_buf;
spi_bus_lock(sigma_delta->spi->master);
sigma_delta->bus_locked = true;
sigma_delta->keep_cs_asserted = true;
ret = ad_sigma_delta_set_mode(sigma_delta, AD_SD_MODE_CONTINUOUS);
if (ret)
goto err_unlock;
sigma_delta->irq_dis = false;
enable_irq(sigma_delta->spi->irq);
return 0;
err_unlock:
spi_bus_unlock(sigma_delta->spi->master);
return ret;
}
static int ad_sd_buffer_postdisable(struct iio_dev *indio_dev)
{
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
reinit_completion(&sigma_delta->completion);
wait_for_completion_timeout(&sigma_delta->completion, HZ);
if (!sigma_delta->irq_dis) {
disable_irq_nosync(sigma_delta->spi->irq);
sigma_delta->irq_dis = true;
}
sigma_delta->keep_cs_asserted = false;
ad_sigma_delta_set_mode(sigma_delta, AD_SD_MODE_IDLE);
if (sigma_delta->status_appended)
ad_sigma_delta_append_status(sigma_delta, false);
ad_sigma_delta_disable_all(sigma_delta);
sigma_delta->bus_locked = false;
return spi_bus_unlock(sigma_delta->spi->master);
}
static irqreturn_t ad_sd_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
uint8_t *data = sigma_delta->rx_buf;
unsigned int transfer_size;
unsigned int sample_size;
unsigned int sample_pos;
unsigned int status_pos;
unsigned int reg_size;
unsigned int data_reg;
reg_size = indio_dev->channels[0].scan_type.realbits +
indio_dev->channels[0].scan_type.shift;
reg_size = DIV_ROUND_UP(reg_size, 8);
if (sigma_delta->info->data_reg != 0)
data_reg = sigma_delta->info->data_reg;
else
data_reg = AD_SD_REG_DATA;
/* Status word will be appended to the sample during transfer */
if (sigma_delta->status_appended)
transfer_size = reg_size + 1;
else
transfer_size = reg_size;
switch (reg_size) {
case 4:
case 2:
case 1:
status_pos = reg_size;
ad_sd_read_reg_raw(sigma_delta, data_reg, transfer_size, &data[0]);
break;
case 3:
/*
* Data array after transfer will look like (if status is appended):
* data[] = { [0][sample][sample][sample][status] }
* Keeping the first byte 0 shifts the status postion by 1 byte to the right.
*/
status_pos = reg_size + 1;
/* We store 24 bit samples in a 32 bit word. Keep the upper
* byte set to zero. */
ad_sd_read_reg_raw(sigma_delta, data_reg, transfer_size, &data[1]);
break;
}
/*
* For devices sampling only one channel at
* once, there is no need for sample number tracking.
*/
if (sigma_delta->active_slots == 1) {
iio_push_to_buffers_with_timestamp(indio_dev, data, pf->timestamp);
goto irq_handled;
}
if (sigma_delta->status_appended) {
u8 converted_channel;
converted_channel = data[status_pos] & sigma_delta->info->status_ch_mask;
if (converted_channel != sigma_delta->slots[sigma_delta->current_slot]) {
/*
* Desync occurred during continuous sampling of multiple channels.
* Drop this incomplete sample and start from first channel again.
*/
sigma_delta->current_slot = 0;
goto irq_handled;
}
}
sample_size = indio_dev->channels[0].scan_type.storagebits / 8;
sample_pos = sample_size * sigma_delta->current_slot;
memcpy(&sigma_delta->samples_buf[sample_pos], data, sample_size);
sigma_delta->current_slot++;
if (sigma_delta->current_slot == sigma_delta->active_slots) {
sigma_delta->current_slot = 0;
iio_push_to_buffers_with_timestamp(indio_dev, sigma_delta->samples_buf,
pf->timestamp);
}
irq_handled:
iio_trigger_notify_done(indio_dev->trig);
sigma_delta->irq_dis = false;
enable_irq(sigma_delta->spi->irq);
return IRQ_HANDLED;
}
static bool ad_sd_validate_scan_mask(struct iio_dev *indio_dev, const unsigned long *mask)
{
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
return bitmap_weight(mask, indio_dev->masklength) <= sigma_delta->num_slots;
}
static const struct iio_buffer_setup_ops ad_sd_buffer_setup_ops = {
.postenable = &ad_sd_buffer_postenable,
.postdisable = &ad_sd_buffer_postdisable,
.validate_scan_mask = &ad_sd_validate_scan_mask,
};
static irqreturn_t ad_sd_data_rdy_trig_poll(int irq, void *private)
{
struct ad_sigma_delta *sigma_delta = private;
complete(&sigma_delta->completion);
disable_irq_nosync(irq);
sigma_delta->irq_dis = true;
iio_trigger_poll(sigma_delta->trig);
return IRQ_HANDLED;
}
/**
* ad_sd_validate_trigger() - validate_trigger callback for ad_sigma_delta devices
* @indio_dev: The IIO device
* @trig: The new trigger
*
* Returns: 0 if the 'trig' matches the trigger registered by the ad_sigma_delta
* device, -EINVAL otherwise.
*/
int ad_sd_validate_trigger(struct iio_dev *indio_dev, struct iio_trigger *trig)
{
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
if (sigma_delta->trig != trig)
return -EINVAL;
return 0;
}
EXPORT_SYMBOL_NS_GPL(ad_sd_validate_trigger, IIO_AD_SIGMA_DELTA);
static int devm_ad_sd_probe_trigger(struct device *dev, struct iio_dev *indio_dev)
{
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
int ret;
if (dev != &sigma_delta->spi->dev) {
dev_err(dev, "Trigger parent should be '%s', got '%s'\n",
dev_name(dev), dev_name(&sigma_delta->spi->dev));
return -EFAULT;
}
sigma_delta->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,
iio_device_id(indio_dev));
if (sigma_delta->trig == NULL)
return -ENOMEM;
init_completion(&sigma_delta->completion);
sigma_delta->irq_dis = true;
/* the IRQ core clears IRQ_DISABLE_UNLAZY flag when freeing an IRQ */
irq_set_status_flags(sigma_delta->spi->irq, IRQ_DISABLE_UNLAZY);
ret = devm_request_irq(dev, sigma_delta->spi->irq,
ad_sd_data_rdy_trig_poll,
sigma_delta->info->irq_flags | IRQF_NO_AUTOEN,
indio_dev->name,
sigma_delta);
if (ret)
return ret;
iio_trigger_set_drvdata(sigma_delta->trig, sigma_delta);
ret = devm_iio_trigger_register(dev, sigma_delta->trig);
if (ret)
return ret;
/* select default trigger */
indio_dev->trig = iio_trigger_get(sigma_delta->trig);
return 0;
}
/**
* devm_ad_sd_setup_buffer_and_trigger() - Device-managed buffer & trigger setup
* @dev: Device object to which to bind the life-time of the resources attached
* @indio_dev: The IIO device
*/
int devm_ad_sd_setup_buffer_and_trigger(struct device *dev, struct iio_dev *indio_dev)
{
struct ad_sigma_delta *sigma_delta = iio_device_get_drvdata(indio_dev);
int ret;
sigma_delta->slots = devm_kcalloc(dev, sigma_delta->num_slots,
sizeof(*sigma_delta->slots), GFP_KERNEL);
if (!sigma_delta->slots)
return -ENOMEM;
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
&iio_pollfunc_store_time,
&ad_sd_trigger_handler,
&ad_sd_buffer_setup_ops);
if (ret)
return ret;
return devm_ad_sd_probe_trigger(dev, indio_dev);
}
EXPORT_SYMBOL_NS_GPL(devm_ad_sd_setup_buffer_and_trigger, IIO_AD_SIGMA_DELTA);
/**
* ad_sd_init() - Initializes a ad_sigma_delta struct
* @sigma_delta: The ad_sigma_delta device
* @indio_dev: The IIO device which the Sigma Delta device is used for
* @spi: The SPI device for the ad_sigma_delta device
* @info: Device specific callbacks and options
*
* This function needs to be called before any other operations are performed on
* the ad_sigma_delta struct.
*/
int ad_sd_init(struct ad_sigma_delta *sigma_delta, struct iio_dev *indio_dev,
struct spi_device *spi, const struct ad_sigma_delta_info *info)
{
sigma_delta->spi = spi;
sigma_delta->info = info;
/* If the field is unset in ad_sigma_delta_info, asume there can only be 1 slot. */
if (!info->num_slots)
sigma_delta->num_slots = 1;
else
sigma_delta->num_slots = info->num_slots;
if (sigma_delta->num_slots > 1) {
if (!indio_dev->info->update_scan_mode) {
dev_err(&spi->dev, "iio_dev lacks update_scan_mode().\n");
return -EINVAL;
}
if (!info->disable_all) {
dev_err(&spi->dev, "ad_sigma_delta_info lacks disable_all().\n");
return -EINVAL;
}
}
iio_device_set_drvdata(indio_dev, sigma_delta);
return 0;
}
EXPORT_SYMBOL_NS_GPL(ad_sd_init, IIO_AD_SIGMA_DELTA);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("Analog Devices Sigma-Delta ADCs");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/adc/ad_sigma_delta.c |
// SPDX-License-Identifier: GPL-2.0
/*
* AD8366 and similar Gain Amplifiers
* This driver supports the following gain amplifiers:
* AD8366 Dual-Digital Variable Gain Amplifier (VGA)
* ADA4961 BiCMOS RF Digital Gain Amplifier (DGA)
* ADL5240 Digitally controlled variable gain amplifier (VGA)
* HMC792A 0.25 dB LSB GaAs MMIC 6-Bit Digital Attenuator
* HMC1119 0.25 dB LSB, 7-Bit, Silicon Digital Attenuator
*
* Copyright 2012-2019 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/bitrev.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
enum ad8366_type {
ID_AD8366,
ID_ADA4961,
ID_ADL5240,
ID_HMC792,
ID_HMC1119,
};
struct ad8366_info {
int gain_min;
int gain_max;
};
struct ad8366_state {
struct spi_device *spi;
struct regulator *reg;
struct mutex lock; /* protect sensor state */
struct gpio_desc *reset_gpio;
unsigned char ch[2];
enum ad8366_type type;
struct ad8366_info *info;
/*
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
unsigned char data[2] __aligned(IIO_DMA_MINALIGN);
};
static struct ad8366_info ad8366_infos[] = {
[ID_AD8366] = {
.gain_min = 4500,
.gain_max = 20500,
},
[ID_ADA4961] = {
.gain_min = -6000,
.gain_max = 15000,
},
[ID_ADL5240] = {
.gain_min = -11500,
.gain_max = 20000,
},
[ID_HMC792] = {
.gain_min = -15750,
.gain_max = 0,
},
[ID_HMC1119] = {
.gain_min = -31750,
.gain_max = 0,
},
};
static int ad8366_write(struct iio_dev *indio_dev,
unsigned char ch_a, unsigned char ch_b)
{
struct ad8366_state *st = iio_priv(indio_dev);
int ret;
switch (st->type) {
case ID_AD8366:
ch_a = bitrev8(ch_a & 0x3F);
ch_b = bitrev8(ch_b & 0x3F);
st->data[0] = ch_b >> 4;
st->data[1] = (ch_b << 4) | (ch_a >> 2);
break;
case ID_ADA4961:
st->data[0] = ch_a & 0x1F;
break;
case ID_ADL5240:
st->data[0] = (ch_a & 0x3F);
break;
case ID_HMC792:
case ID_HMC1119:
st->data[0] = ch_a;
break;
}
ret = spi_write(st->spi, st->data, indio_dev->num_channels);
if (ret < 0)
dev_err(&indio_dev->dev, "write failed (%d)", ret);
return ret;
}
static int ad8366_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct ad8366_state *st = iio_priv(indio_dev);
int ret;
int code, gain = 0;
mutex_lock(&st->lock);
switch (m) {
case IIO_CHAN_INFO_HARDWAREGAIN:
code = st->ch[chan->channel];
switch (st->type) {
case ID_AD8366:
gain = code * 253 + 4500;
break;
case ID_ADA4961:
gain = 15000 - code * 1000;
break;
case ID_ADL5240:
gain = 20000 - 31500 + code * 500;
break;
case ID_HMC792:
gain = -1 * code * 500;
break;
case ID_HMC1119:
gain = -1 * code * 250;
break;
}
/* Values in dB */
*val = gain / 1000;
*val2 = (gain % 1000) * 1000;
ret = IIO_VAL_INT_PLUS_MICRO_DB;
break;
default:
ret = -EINVAL;
}
mutex_unlock(&st->lock);
return ret;
};
static int ad8366_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct ad8366_state *st = iio_priv(indio_dev);
struct ad8366_info *inf = st->info;
int code = 0, gain;
int ret;
/* Values in dB */
if (val < 0)
gain = (val * 1000) - (val2 / 1000);
else
gain = (val * 1000) + (val2 / 1000);
if (gain > inf->gain_max || gain < inf->gain_min)
return -EINVAL;
switch (st->type) {
case ID_AD8366:
code = (gain - 4500) / 253;
break;
case ID_ADA4961:
code = (15000 - gain) / 1000;
break;
case ID_ADL5240:
code = ((gain - 500 - 20000) / 500) & 0x3F;
break;
case ID_HMC792:
code = (abs(gain) / 500) & 0x3F;
break;
case ID_HMC1119:
code = (abs(gain) / 250) & 0x7F;
break;
}
mutex_lock(&st->lock);
switch (mask) {
case IIO_CHAN_INFO_HARDWAREGAIN:
st->ch[chan->channel] = code;
ret = ad8366_write(indio_dev, st->ch[0], st->ch[1]);
break;
default:
ret = -EINVAL;
}
mutex_unlock(&st->lock);
return ret;
}
static int ad8366_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_HARDWAREGAIN:
return IIO_VAL_INT_PLUS_MICRO_DB;
default:
return -EINVAL;
}
}
static const struct iio_info ad8366_info = {
.read_raw = &ad8366_read_raw,
.write_raw = &ad8366_write_raw,
.write_raw_get_fmt = &ad8366_write_raw_get_fmt,
};
#define AD8366_CHAN(_channel) { \
.type = IIO_VOLTAGE, \
.output = 1, \
.indexed = 1, \
.channel = _channel, \
.info_mask_separate = BIT(IIO_CHAN_INFO_HARDWAREGAIN),\
}
static const struct iio_chan_spec ad8366_channels[] = {
AD8366_CHAN(0),
AD8366_CHAN(1),
};
static const struct iio_chan_spec ada4961_channels[] = {
AD8366_CHAN(0),
};
static int ad8366_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct ad8366_state *st;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (indio_dev == NULL)
return -ENOMEM;
st = iio_priv(indio_dev);
st->reg = devm_regulator_get(&spi->dev, "vcc");
if (!IS_ERR(st->reg)) {
ret = regulator_enable(st->reg);
if (ret)
return ret;
}
spi_set_drvdata(spi, indio_dev);
mutex_init(&st->lock);
st->spi = spi;
st->type = spi_get_device_id(spi)->driver_data;
switch (st->type) {
case ID_AD8366:
indio_dev->channels = ad8366_channels;
indio_dev->num_channels = ARRAY_SIZE(ad8366_channels);
break;
case ID_ADA4961:
case ID_ADL5240:
case ID_HMC792:
case ID_HMC1119:
st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(st->reset_gpio)) {
ret = PTR_ERR(st->reset_gpio);
goto error_disable_reg;
}
indio_dev->channels = ada4961_channels;
indio_dev->num_channels = ARRAY_SIZE(ada4961_channels);
break;
default:
dev_err(&spi->dev, "Invalid device ID\n");
ret = -EINVAL;
goto error_disable_reg;
}
st->info = &ad8366_infos[st->type];
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->info = &ad8366_info;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = ad8366_write(indio_dev, 0, 0);
if (ret < 0)
goto error_disable_reg;
ret = iio_device_register(indio_dev);
if (ret)
goto error_disable_reg;
return 0;
error_disable_reg:
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
return ret;
}
static void ad8366_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct ad8366_state *st = iio_priv(indio_dev);
struct regulator *reg = st->reg;
iio_device_unregister(indio_dev);
if (!IS_ERR(reg))
regulator_disable(reg);
}
static const struct spi_device_id ad8366_id[] = {
{"ad8366", ID_AD8366},
{"ada4961", ID_ADA4961},
{"adl5240", ID_ADL5240},
{"hmc792a", ID_HMC792},
{"hmc1119", ID_HMC1119},
{}
};
MODULE_DEVICE_TABLE(spi, ad8366_id);
static struct spi_driver ad8366_driver = {
.driver = {
.name = KBUILD_MODNAME,
},
.probe = ad8366_probe,
.remove = ad8366_remove,
.id_table = ad8366_id,
};
module_spi_driver(ad8366_driver);
MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("Analog Devices AD8366 and similar Gain Amplifiers");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/amplifiers/ad8366.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ADA4250 driver
*
* Copyright 2022 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <asm/unaligned.h>
/* ADA4250 Register Map */
#define ADA4250_REG_GAIN_MUX 0x00
#define ADA4250_REG_REFBUF_EN 0x01
#define ADA4250_REG_RESET 0x02
#define ADA4250_REG_SNSR_CAL_VAL 0x04
#define ADA4250_REG_SNSR_CAL_CNFG 0x05
#define ADA4250_REG_DIE_REV 0x18
#define ADA4250_REG_CHIP_ID 0x19
/* ADA4250_REG_GAIN_MUX Map */
#define ADA4250_GAIN_MUX_MSK GENMASK(2, 0)
/* ADA4250_REG_REFBUF Map */
#define ADA4250_REFBUF_MSK BIT(0)
/* ADA4250_REG_RESET Map */
#define ADA4250_RESET_MSK BIT(0)
/* ADA4250_REG_SNSR_CAL_VAL Map */
#define ADA4250_CAL_CFG_BIAS_MSK GENMASK(7, 0)
/* ADA4250_REG_SNSR_CAL_CNFG Bit Definition */
#define ADA4250_BIAS_SET_MSK GENMASK(3, 2)
#define ADA4250_RANGE_SET_MSK GENMASK(1, 0)
/* Miscellaneous definitions */
#define ADA4250_CHIP_ID 0x4250
#define ADA4250_RANGE1 0
#define ADA4250_RANGE4 3
/* ADA4250 current bias set */
enum ada4250_current_bias {
ADA4250_BIAS_DISABLED,
ADA4250_BIAS_BANDGAP,
ADA4250_BIAS_AVDD,
};
struct ada4250_state {
struct spi_device *spi;
struct regmap *regmap;
struct regulator *reg;
/* Protect against concurrent accesses to the device and data content */
struct mutex lock;
u8 bias;
u8 gain;
int offset_uv;
bool refbuf_en;
};
/* ADA4250 Current Bias Source Settings: Disabled, Bandgap Reference, AVDD */
static const int calibbias_table[] = {0, 1, 2};
/* ADA4250 Gain (V/V) values: 1, 2, 4, 8, 16, 32, 64, 128 */
static const int hwgain_table[] = {1, 2, 4, 8, 16, 32, 64, 128};
static const struct regmap_config ada4250_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.read_flag_mask = BIT(7),
.max_register = 0x1A,
};
static int ada4250_set_offset_uv(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
int offset_uv)
{
struct ada4250_state *st = iio_priv(indio_dev);
int i, ret, x[8], max_vos, min_vos, voltage_v, vlsb = 0;
u8 offset_raw, range = ADA4250_RANGE1;
u32 lsb_coeff[6] = {1333, 2301, 4283, 8289, 16311, 31599};
if (st->bias == 0 || st->bias == 3)
return -EINVAL;
voltage_v = regulator_get_voltage(st->reg);
voltage_v = DIV_ROUND_CLOSEST(voltage_v, 1000000);
if (st->bias == ADA4250_BIAS_AVDD)
x[0] = voltage_v;
else
x[0] = 5;
x[1] = 126 * (x[0] - 1);
for (i = 0; i < 6; i++)
x[i + 2] = DIV_ROUND_CLOSEST(x[1] * 1000, lsb_coeff[i]);
if (st->gain == 0)
return -EINVAL;
/*
* Compute Range and Voltage per LSB for the Sensor Offset Calibration
* Example of computation for Range 1 and Range 2 (Curren Bias Set = AVDD):
* Range 1 Range 2
* Gain | Max Vos(mV) | LSB(mV) | Max Vos(mV) | LSB(mV) |
* 2 | X1*127 | X1=0.126(AVDD-1) | X1*3*127 | X1*3 |
* 4 | X2*127 | X2=X1/1.3333 | X2*3*127 | X2*3 |
* 8 | X3*127 | X3=X1/2.301 | X3*3*127 | X3*3 |
* 16 | X4*127 | X4=X1/4.283 | X4*3*127 | X4*3 |
* 32 | X5*127 | X5=X1/8.289 | X5*3*127 | X5*3 |
* 64 | X6*127 | X6=X1/16.311 | X6*3*127 | X6*3 |
* 128 | X7*127 | X7=X1/31.599 | X7*3*127 | X7*3 |
*/
for (i = ADA4250_RANGE1; i <= ADA4250_RANGE4; i++) {
max_vos = x[st->gain] * 127 * ((1 << (i + 1)) - 1);
min_vos = -1 * max_vos;
if (offset_uv > min_vos && offset_uv < max_vos) {
range = i;
vlsb = x[st->gain] * ((1 << (i + 1)) - 1);
break;
}
}
if (vlsb <= 0)
return -EINVAL;
offset_raw = DIV_ROUND_CLOSEST(abs(offset_uv), vlsb);
mutex_lock(&st->lock);
ret = regmap_update_bits(st->regmap, ADA4250_REG_SNSR_CAL_CNFG,
ADA4250_RANGE_SET_MSK,
FIELD_PREP(ADA4250_RANGE_SET_MSK, range));
if (ret)
goto exit;
st->offset_uv = offset_raw * vlsb;
/*
* To set the offset calibration value, use bits [6:0] and bit 7 as the
* polarity bit (set to "0" for a negative offset and "1" for a positive
* offset).
*/
if (offset_uv < 0) {
offset_raw |= BIT(7);
st->offset_uv *= (-1);
}
ret = regmap_write(st->regmap, ADA4250_REG_SNSR_CAL_VAL, offset_raw);
exit:
mutex_unlock(&st->lock);
return ret;
}
static int ada4250_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long info)
{
struct ada4250_state *st = iio_priv(indio_dev);
int ret;
switch (info) {
case IIO_CHAN_INFO_HARDWAREGAIN:
ret = regmap_read(st->regmap, ADA4250_REG_GAIN_MUX, val);
if (ret)
return ret;
*val = BIT(*val);
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
*val = st->offset_uv;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBBIAS:
ret = regmap_read(st->regmap, ADA4250_REG_SNSR_CAL_CNFG, val);
if (ret)
return ret;
*val = FIELD_GET(ADA4250_BIAS_SET_MSK, *val);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 1;
*val2 = 1000000;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
}
static int ada4250_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long info)
{
struct ada4250_state *st = iio_priv(indio_dev);
int ret;
switch (info) {
case IIO_CHAN_INFO_HARDWAREGAIN:
ret = regmap_write(st->regmap, ADA4250_REG_GAIN_MUX,
FIELD_PREP(ADA4250_GAIN_MUX_MSK, ilog2(val)));
if (ret)
return ret;
st->gain = ilog2(val);
return ret;
case IIO_CHAN_INFO_OFFSET:
return ada4250_set_offset_uv(indio_dev, chan, val);
case IIO_CHAN_INFO_CALIBBIAS:
ret = regmap_update_bits(st->regmap, ADA4250_REG_SNSR_CAL_CNFG,
ADA4250_BIAS_SET_MSK,
FIELD_PREP(ADA4250_BIAS_SET_MSK, val));
if (ret)
return ret;
st->bias = val;
return ret;
default:
return -EINVAL;
}
}
static int ada4250_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_CALIBBIAS:
*vals = calibbias_table;
*type = IIO_VAL_INT;
*length = ARRAY_SIZE(calibbias_table);
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_HARDWAREGAIN:
*vals = hwgain_table;
*type = IIO_VAL_INT;
*length = ARRAY_SIZE(hwgain_table);
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static int ada4250_reg_access(struct iio_dev *indio_dev,
unsigned int reg,
unsigned int write_val,
unsigned int *read_val)
{
struct ada4250_state *st = iio_priv(indio_dev);
if (read_val)
return regmap_read(st->regmap, reg, read_val);
else
return regmap_write(st->regmap, reg, write_val);
}
static const struct iio_info ada4250_info = {
.read_raw = ada4250_read_raw,
.write_raw = ada4250_write_raw,
.read_avail = &ada4250_read_avail,
.debugfs_reg_access = &ada4250_reg_access,
};
static const struct iio_chan_spec ada4250_channels[] = {
{
.type = IIO_VOLTAGE,
.output = 1,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_HARDWAREGAIN) |
BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_CALIBBIAS) |
BIT(IIO_CHAN_INFO_SCALE),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_CALIBBIAS) |
BIT(IIO_CHAN_INFO_HARDWAREGAIN),
}
};
static void ada4250_reg_disable(void *data)
{
regulator_disable(data);
}
static int ada4250_init(struct ada4250_state *st)
{
int ret;
u16 chip_id;
u8 data[2] __aligned(8) = {};
struct spi_device *spi = st->spi;
st->refbuf_en = device_property_read_bool(&spi->dev, "adi,refbuf-enable");
st->reg = devm_regulator_get(&spi->dev, "avdd");
if (IS_ERR(st->reg))
return dev_err_probe(&spi->dev, PTR_ERR(st->reg),
"failed to get the AVDD voltage\n");
ret = regulator_enable(st->reg);
if (ret) {
dev_err(&spi->dev, "Failed to enable specified AVDD supply\n");
return ret;
}
ret = devm_add_action_or_reset(&spi->dev, ada4250_reg_disable, st->reg);
if (ret)
return ret;
ret = regmap_write(st->regmap, ADA4250_REG_RESET,
FIELD_PREP(ADA4250_RESET_MSK, 1));
if (ret)
return ret;
ret = regmap_bulk_read(st->regmap, ADA4250_REG_CHIP_ID, data, 2);
if (ret)
return ret;
chip_id = get_unaligned_le16(data);
if (chip_id != ADA4250_CHIP_ID) {
dev_err(&spi->dev, "Invalid chip ID.\n");
return -EINVAL;
}
return regmap_write(st->regmap, ADA4250_REG_REFBUF_EN,
FIELD_PREP(ADA4250_REFBUF_MSK, st->refbuf_en));
}
static int ada4250_probe(struct spi_device *spi)
{
struct iio_dev *indio_dev;
struct regmap *regmap;
struct ada4250_state *st;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
regmap = devm_regmap_init_spi(spi, &ada4250_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
st = iio_priv(indio_dev);
st->regmap = regmap;
st->spi = spi;
indio_dev->info = &ada4250_info;
indio_dev->name = "ada4250";
indio_dev->channels = ada4250_channels;
indio_dev->num_channels = ARRAY_SIZE(ada4250_channels);
mutex_init(&st->lock);
ret = ada4250_init(st);
if (ret) {
dev_err(&spi->dev, "ADA4250 init failed\n");
return ret;
}
return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id ada4250_id[] = {
{ "ada4250", 0 },
{}
};
MODULE_DEVICE_TABLE(spi, ada4250_id);
static const struct of_device_id ada4250_of_match[] = {
{ .compatible = "adi,ada4250" },
{},
};
MODULE_DEVICE_TABLE(of, ada4250_of_match);
static struct spi_driver ada4250_driver = {
.driver = {
.name = "ada4250",
.of_match_table = ada4250_of_match,
},
.probe = ada4250_probe,
.id_table = ada4250_id,
};
module_spi_driver(ada4250_driver);
MODULE_AUTHOR("Antoniu Miclaus <[email protected]");
MODULE_DESCRIPTION("Analog Devices ADA4250");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/amplifiers/ada4250.c |
// SPDX-License-Identifier: GPL-2.0
/*
* HMC425A and similar Gain Amplifiers
*
* Copyright 2020 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
#include <linux/sysfs.h>
enum hmc425a_type {
ID_HMC425A,
};
struct hmc425a_chip_info {
const char *name;
const struct iio_chan_spec *channels;
unsigned int num_channels;
unsigned int num_gpios;
int gain_min;
int gain_max;
int default_gain;
};
struct hmc425a_state {
struct mutex lock; /* protect sensor state */
struct hmc425a_chip_info *chip_info;
struct gpio_descs *gpios;
enum hmc425a_type type;
u32 gain;
};
static int hmc425a_write(struct iio_dev *indio_dev, u32 value)
{
struct hmc425a_state *st = iio_priv(indio_dev);
DECLARE_BITMAP(values, BITS_PER_TYPE(value));
values[0] = value;
gpiod_set_array_value_cansleep(st->gpios->ndescs, st->gpios->desc,
NULL, values);
return 0;
}
static int hmc425a_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long m)
{
struct hmc425a_state *st = iio_priv(indio_dev);
int code, gain = 0;
int ret;
mutex_lock(&st->lock);
switch (m) {
case IIO_CHAN_INFO_HARDWAREGAIN:
code = st->gain;
switch (st->type) {
case ID_HMC425A:
gain = ~code * -500;
break;
}
*val = gain / 1000;
*val2 = (gain % 1000) * 1000;
ret = IIO_VAL_INT_PLUS_MICRO_DB;
break;
default:
ret = -EINVAL;
}
mutex_unlock(&st->lock);
return ret;
};
static int hmc425a_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct hmc425a_state *st = iio_priv(indio_dev);
struct hmc425a_chip_info *inf = st->chip_info;
int code = 0, gain;
int ret;
if (val < 0)
gain = (val * 1000) - (val2 / 1000);
else
gain = (val * 1000) + (val2 / 1000);
if (gain > inf->gain_max || gain < inf->gain_min)
return -EINVAL;
switch (st->type) {
case ID_HMC425A:
code = ~((abs(gain) / 500) & 0x3F);
break;
}
mutex_lock(&st->lock);
switch (mask) {
case IIO_CHAN_INFO_HARDWAREGAIN:
st->gain = code;
ret = hmc425a_write(indio_dev, st->gain);
break;
default:
ret = -EINVAL;
}
mutex_unlock(&st->lock);
return ret;
}
static int hmc425a_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_HARDWAREGAIN:
return IIO_VAL_INT_PLUS_MICRO_DB;
default:
return -EINVAL;
}
}
static const struct iio_info hmc425a_info = {
.read_raw = &hmc425a_read_raw,
.write_raw = &hmc425a_write_raw,
.write_raw_get_fmt = &hmc425a_write_raw_get_fmt,
};
#define HMC425A_CHAN(_channel) \
{ \
.type = IIO_VOLTAGE, \
.output = 1, \
.indexed = 1, \
.channel = _channel, \
.info_mask_separate = BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
}
static const struct iio_chan_spec hmc425a_channels[] = {
HMC425A_CHAN(0),
};
/* Match table for of_platform binding */
static const struct of_device_id hmc425a_of_match[] = {
{ .compatible = "adi,hmc425a", .data = (void *)ID_HMC425A },
{},
};
MODULE_DEVICE_TABLE(of, hmc425a_of_match);
static struct hmc425a_chip_info hmc425a_chip_info_tbl[] = {
[ID_HMC425A] = {
.name = "hmc425a",
.channels = hmc425a_channels,
.num_channels = ARRAY_SIZE(hmc425a_channels),
.num_gpios = 6,
.gain_min = -31500,
.gain_max = 0,
.default_gain = -0x40, /* set default gain -31.5db*/
},
};
static int hmc425a_probe(struct platform_device *pdev)
{
struct iio_dev *indio_dev;
struct hmc425a_state *st;
int ret;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->type = (uintptr_t)device_get_match_data(&pdev->dev);
st->chip_info = &hmc425a_chip_info_tbl[st->type];
indio_dev->num_channels = st->chip_info->num_channels;
indio_dev->channels = st->chip_info->channels;
indio_dev->name = st->chip_info->name;
st->gain = st->chip_info->default_gain;
st->gpios = devm_gpiod_get_array(&pdev->dev, "ctrl", GPIOD_OUT_LOW);
if (IS_ERR(st->gpios))
return dev_err_probe(&pdev->dev, PTR_ERR(st->gpios),
"failed to get gpios\n");
if (st->gpios->ndescs != st->chip_info->num_gpios) {
dev_err(&pdev->dev, "%d GPIOs needed to operate\n",
st->chip_info->num_gpios);
return -ENODEV;
}
ret = devm_regulator_get_enable(&pdev->dev, "vcc-supply");
if (ret)
return ret;
mutex_init(&st->lock);
indio_dev->info = &hmc425a_info;
indio_dev->modes = INDIO_DIRECT_MODE;
return devm_iio_device_register(&pdev->dev, indio_dev);
}
static struct platform_driver hmc425a_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = hmc425a_of_match,
},
.probe = hmc425a_probe,
};
module_platform_driver(hmc425a_driver);
MODULE_AUTHOR("Michael Hennerich <[email protected]>");
MODULE_DESCRIPTION("Analog Devices HMC425A and similar GPIO control Gain Amplifiers");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/amplifiers/hmc425a.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* srf08.c - Support for Devantech SRFxx ultrasonic ranger
* with i2c interface
* actually supported are srf02, srf08, srf10
*
* Copyright (c) 2016, 2017 Andreas Klinger <[email protected]>
*
* For details about the device see:
* https://www.robot-electronics.co.uk/htm/srf08tech.html
* https://www.robot-electronics.co.uk/htm/srf10tech.htm
* https://www.robot-electronics.co.uk/htm/srf02tech.htm
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
/* registers of SRF08 device */
#define SRF08_WRITE_COMMAND 0x00 /* Command Register */
#define SRF08_WRITE_MAX_GAIN 0x01 /* Max Gain Register: 0 .. 31 */
#define SRF08_WRITE_RANGE 0x02 /* Range Register: 0 .. 255 */
#define SRF08_READ_SW_REVISION 0x00 /* Software Revision */
#define SRF08_READ_LIGHT 0x01 /* Light Sensor during last echo */
#define SRF08_READ_ECHO_1_HIGH 0x02 /* Range of first echo received */
#define SRF08_READ_ECHO_1_LOW 0x03 /* Range of first echo received */
#define SRF08_CMD_RANGING_CM 0x51 /* Ranging Mode - Result in cm */
enum srf08_sensor_type {
SRF02,
SRF08,
SRF10,
SRF_MAX_TYPE
};
struct srf08_chip_info {
const int *sensitivity_avail;
int num_sensitivity_avail;
int sensitivity_default;
/* default value of Range in mm */
int range_default;
};
struct srf08_data {
struct i2c_client *client;
/*
* Gain in the datasheet is called sensitivity here to distinct it
* from the gain used with amplifiers of adc's
*/
int sensitivity;
/* max. Range in mm */
int range_mm;
struct mutex lock;
/* Ensure timestamp is naturally aligned */
struct {
s16 chan;
s64 timestamp __aligned(8);
} scan;
/* Sensor-Type */
enum srf08_sensor_type sensor_type;
/* Chip-specific information */
const struct srf08_chip_info *chip_info;
};
/*
* in the documentation one can read about the "Gain" of the device
* which is used here for amplifying the signal and filtering out unwanted
* ones.
* But with ADC's this term is already used differently and that's why it
* is called "Sensitivity" here.
*/
static const struct srf08_chip_info srf02_chip_info = {
.sensitivity_avail = NULL,
.num_sensitivity_avail = 0,
.sensitivity_default = 0,
.range_default = 0,
};
static const int srf08_sensitivity_avail[] = {
94, 97, 100, 103, 107, 110, 114, 118,
123, 128, 133, 139, 145, 152, 159, 168,
177, 187, 199, 212, 227, 245, 265, 288,
317, 352, 395, 450, 524, 626, 777, 1025
};
static const struct srf08_chip_info srf08_chip_info = {
.sensitivity_avail = srf08_sensitivity_avail,
.num_sensitivity_avail = ARRAY_SIZE(srf08_sensitivity_avail),
.sensitivity_default = 1025,
.range_default = 6020,
};
static const int srf10_sensitivity_avail[] = {
40, 40, 50, 60, 70, 80, 100, 120,
140, 200, 250, 300, 350, 400, 500, 600,
700,
};
static const struct srf08_chip_info srf10_chip_info = {
.sensitivity_avail = srf10_sensitivity_avail,
.num_sensitivity_avail = ARRAY_SIZE(srf10_sensitivity_avail),
.sensitivity_default = 700,
.range_default = 6020,
};
static int srf08_read_ranging(struct srf08_data *data)
{
struct i2c_client *client = data->client;
int ret, i;
int waittime;
mutex_lock(&data->lock);
ret = i2c_smbus_write_byte_data(data->client,
SRF08_WRITE_COMMAND, SRF08_CMD_RANGING_CM);
if (ret < 0) {
dev_err(&client->dev, "write command - err: %d\n", ret);
mutex_unlock(&data->lock);
return ret;
}
/*
* we read here until a correct version number shows up as
* suggested by the documentation
*
* with an ultrasonic speed of 343 m/s and a roundtrip of it
* sleep the expected duration and try to read from the device
* if nothing useful is read try it in a shorter grid
*
* polling for not more than 20 ms should be enough
*/
waittime = 1 + data->range_mm / 172;
msleep(waittime);
for (i = 0; i < 4; i++) {
ret = i2c_smbus_read_byte_data(data->client,
SRF08_READ_SW_REVISION);
/* check if a valid version number is read */
if (ret < 255 && ret > 0)
break;
msleep(5);
}
if (ret >= 255 || ret <= 0) {
dev_err(&client->dev, "device not ready\n");
mutex_unlock(&data->lock);
return -EIO;
}
ret = i2c_smbus_read_word_swapped(data->client,
SRF08_READ_ECHO_1_HIGH);
if (ret < 0) {
dev_err(&client->dev, "cannot read distance: ret=%d\n", ret);
mutex_unlock(&data->lock);
return ret;
}
mutex_unlock(&data->lock);
return ret;
}
static irqreturn_t srf08_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct srf08_data *data = iio_priv(indio_dev);
s16 sensor_data;
sensor_data = srf08_read_ranging(data);
if (sensor_data < 0)
goto err;
mutex_lock(&data->lock);
data->scan.chan = sensor_data;
iio_push_to_buffers_with_timestamp(indio_dev,
&data->scan, pf->timestamp);
mutex_unlock(&data->lock);
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int srf08_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
struct srf08_data *data = iio_priv(indio_dev);
int ret;
if (channel->type != IIO_DISTANCE)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = srf08_read_ranging(data);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/* 1 LSB is 1 cm */
*val = 0;
*val2 = 10000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static ssize_t srf08_show_range_mm_available(struct device *dev,
struct device_attribute *attr, char *buf)
{
return sprintf(buf, "[0.043 0.043 11.008]\n");
}
static IIO_DEVICE_ATTR(sensor_max_range_available, S_IRUGO,
srf08_show_range_mm_available, NULL, 0);
static ssize_t srf08_show_range_mm(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct srf08_data *data = iio_priv(indio_dev);
return sprintf(buf, "%d.%03d\n", data->range_mm / 1000,
data->range_mm % 1000);
}
/*
* set the range of the sensor to an even multiple of 43 mm
* which corresponds to 1 LSB in the register
*
* register value corresponding range
* 0x00 43 mm
* 0x01 86 mm
* 0x02 129 mm
* ...
* 0xFF 11008 mm
*/
static ssize_t srf08_write_range_mm(struct srf08_data *data, unsigned int val)
{
int ret;
struct i2c_client *client = data->client;
unsigned int mod;
u8 regval;
ret = val / 43 - 1;
mod = val % 43;
if (mod || (ret < 0) || (ret > 255))
return -EINVAL;
regval = ret;
mutex_lock(&data->lock);
ret = i2c_smbus_write_byte_data(client, SRF08_WRITE_RANGE, regval);
if (ret < 0) {
dev_err(&client->dev, "write_range - err: %d\n", ret);
mutex_unlock(&data->lock);
return ret;
}
data->range_mm = val;
mutex_unlock(&data->lock);
return 0;
}
static ssize_t srf08_store_range_mm(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct srf08_data *data = iio_priv(indio_dev);
int ret;
int integer, fract;
ret = iio_str_to_fixpoint(buf, 100, &integer, &fract);
if (ret)
return ret;
ret = srf08_write_range_mm(data, integer * 1000 + fract);
if (ret < 0)
return ret;
return len;
}
static IIO_DEVICE_ATTR(sensor_max_range, S_IRUGO | S_IWUSR,
srf08_show_range_mm, srf08_store_range_mm, 0);
static ssize_t srf08_show_sensitivity_available(struct device *dev,
struct device_attribute *attr, char *buf)
{
int i, len = 0;
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct srf08_data *data = iio_priv(indio_dev);
for (i = 0; i < data->chip_info->num_sensitivity_avail; i++)
if (data->chip_info->sensitivity_avail[i])
len += sprintf(buf + len, "%d ",
data->chip_info->sensitivity_avail[i]);
len += sprintf(buf + len, "\n");
return len;
}
static IIO_DEVICE_ATTR(sensor_sensitivity_available, S_IRUGO,
srf08_show_sensitivity_available, NULL, 0);
static ssize_t srf08_show_sensitivity(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct srf08_data *data = iio_priv(indio_dev);
int len;
len = sprintf(buf, "%d\n", data->sensitivity);
return len;
}
static ssize_t srf08_write_sensitivity(struct srf08_data *data,
unsigned int val)
{
struct i2c_client *client = data->client;
int ret, i;
u8 regval;
if (!val)
return -EINVAL;
for (i = 0; i < data->chip_info->num_sensitivity_avail; i++)
if (val == data->chip_info->sensitivity_avail[i]) {
regval = i;
break;
}
if (i >= data->chip_info->num_sensitivity_avail)
return -EINVAL;
mutex_lock(&data->lock);
ret = i2c_smbus_write_byte_data(client, SRF08_WRITE_MAX_GAIN, regval);
if (ret < 0) {
dev_err(&client->dev, "write_sensitivity - err: %d\n", ret);
mutex_unlock(&data->lock);
return ret;
}
data->sensitivity = val;
mutex_unlock(&data->lock);
return 0;
}
static ssize_t srf08_store_sensitivity(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct srf08_data *data = iio_priv(indio_dev);
int ret;
unsigned int val;
ret = kstrtouint(buf, 10, &val);
if (ret)
return ret;
ret = srf08_write_sensitivity(data, val);
if (ret < 0)
return ret;
return len;
}
static IIO_DEVICE_ATTR(sensor_sensitivity, S_IRUGO | S_IWUSR,
srf08_show_sensitivity, srf08_store_sensitivity, 0);
static struct attribute *srf08_attributes[] = {
&iio_dev_attr_sensor_max_range.dev_attr.attr,
&iio_dev_attr_sensor_max_range_available.dev_attr.attr,
&iio_dev_attr_sensor_sensitivity.dev_attr.attr,
&iio_dev_attr_sensor_sensitivity_available.dev_attr.attr,
NULL,
};
static const struct attribute_group srf08_attribute_group = {
.attrs = srf08_attributes,
};
static const struct iio_chan_spec srf08_channels[] = {
{
.type = IIO_DISTANCE,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 0,
.scan_type = {
.sign = 's',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_CPU,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static const struct iio_info srf08_info = {
.read_raw = srf08_read_raw,
.attrs = &srf08_attribute_group,
};
/*
* srf02 don't have an adjustable range or sensitivity,
* so we don't need attributes at all
*/
static const struct iio_info srf02_info = {
.read_raw = srf08_read_raw,
};
static int srf08_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct iio_dev *indio_dev;
struct srf08_data *data;
int ret;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_READ_BYTE_DATA |
I2C_FUNC_SMBUS_WRITE_BYTE_DATA |
I2C_FUNC_SMBUS_READ_WORD_DATA))
return -ENODEV;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->sensor_type = (enum srf08_sensor_type)id->driver_data;
switch (data->sensor_type) {
case SRF02:
data->chip_info = &srf02_chip_info;
indio_dev->info = &srf02_info;
break;
case SRF08:
data->chip_info = &srf08_chip_info;
indio_dev->info = &srf08_info;
break;
case SRF10:
data->chip_info = &srf10_chip_info;
indio_dev->info = &srf08_info;
break;
default:
return -EINVAL;
}
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = srf08_channels;
indio_dev->num_channels = ARRAY_SIZE(srf08_channels);
mutex_init(&data->lock);
ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev,
iio_pollfunc_store_time, srf08_trigger_handler, NULL);
if (ret < 0) {
dev_err(&client->dev, "setup of iio triggered buffer failed\n");
return ret;
}
if (data->chip_info->range_default) {
/*
* set default range of device in mm here
* these register values cannot be read from the hardware
* therefore set driver specific default values
*
* srf02 don't have a default value so it'll be omitted
*/
ret = srf08_write_range_mm(data,
data->chip_info->range_default);
if (ret < 0)
return ret;
}
if (data->chip_info->sensitivity_default) {
/*
* set default sensitivity of device here
* these register values cannot be read from the hardware
* therefore set driver specific default values
*
* srf02 don't have a default value so it'll be omitted
*/
ret = srf08_write_sensitivity(data,
data->chip_info->sensitivity_default);
if (ret < 0)
return ret;
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct of_device_id of_srf08_match[] = {
{ .compatible = "devantech,srf02", (void *)SRF02 },
{ .compatible = "devantech,srf08", (void *)SRF08 },
{ .compatible = "devantech,srf10", (void *)SRF10 },
{},
};
MODULE_DEVICE_TABLE(of, of_srf08_match);
static const struct i2c_device_id srf08_id[] = {
{ "srf02", SRF02 },
{ "srf08", SRF08 },
{ "srf10", SRF10 },
{ }
};
MODULE_DEVICE_TABLE(i2c, srf08_id);
static struct i2c_driver srf08_driver = {
.driver = {
.name = "srf08",
.of_match_table = of_srf08_match,
},
.probe = srf08_probe,
.id_table = srf08_id,
};
module_i2c_driver(srf08_driver);
MODULE_AUTHOR("Andreas Klinger <[email protected]>");
MODULE_DESCRIPTION("Devantech SRF02/SRF08/SRF10 i2c ultrasonic ranger driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/proximity/srf08.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 Intel Corporation
*
* Driver for Semtech's SX9500 capacitive proximity/button solution.
* Datasheet available at
* <http://www.semtech.com/images/datasheet/sx9500.pdf>.
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/acpi.h>
#include <linux/gpio/consumer.h>
#include <linux/regmap.h>
#include <linux/pm.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#define SX9500_DRIVER_NAME "sx9500"
#define SX9500_IRQ_NAME "sx9500_event"
/* Register definitions. */
#define SX9500_REG_IRQ_SRC 0x00
#define SX9500_REG_STAT 0x01
#define SX9500_REG_IRQ_MSK 0x03
#define SX9500_REG_PROX_CTRL0 0x06
#define SX9500_REG_PROX_CTRL1 0x07
#define SX9500_REG_PROX_CTRL2 0x08
#define SX9500_REG_PROX_CTRL3 0x09
#define SX9500_REG_PROX_CTRL4 0x0a
#define SX9500_REG_PROX_CTRL5 0x0b
#define SX9500_REG_PROX_CTRL6 0x0c
#define SX9500_REG_PROX_CTRL7 0x0d
#define SX9500_REG_PROX_CTRL8 0x0e
#define SX9500_REG_SENSOR_SEL 0x20
#define SX9500_REG_USE_MSB 0x21
#define SX9500_REG_USE_LSB 0x22
#define SX9500_REG_AVG_MSB 0x23
#define SX9500_REG_AVG_LSB 0x24
#define SX9500_REG_DIFF_MSB 0x25
#define SX9500_REG_DIFF_LSB 0x26
#define SX9500_REG_OFFSET_MSB 0x27
#define SX9500_REG_OFFSET_LSB 0x28
#define SX9500_REG_RESET 0x7f
/* Write this to REG_RESET to do a soft reset. */
#define SX9500_SOFT_RESET 0xde
#define SX9500_SCAN_PERIOD_MASK GENMASK(6, 4)
#define SX9500_SCAN_PERIOD_SHIFT 4
/*
* These serve for identifying IRQ source in the IRQ_SRC register, and
* also for masking the IRQs in the IRQ_MSK register.
*/
#define SX9500_CLOSE_IRQ BIT(6)
#define SX9500_FAR_IRQ BIT(5)
#define SX9500_CONVDONE_IRQ BIT(3)
#define SX9500_PROXSTAT_SHIFT 4
#define SX9500_COMPSTAT_MASK GENMASK(3, 0)
#define SX9500_NUM_CHANNELS 4
#define SX9500_CHAN_MASK GENMASK(SX9500_NUM_CHANNELS - 1, 0)
struct sx9500_data {
struct mutex mutex;
struct i2c_client *client;
struct iio_trigger *trig;
struct regmap *regmap;
struct gpio_desc *gpiod_rst;
/*
* Last reading of the proximity status for each channel. We
* only send an event to user space when this changes.
*/
bool prox_stat[SX9500_NUM_CHANNELS];
bool event_enabled[SX9500_NUM_CHANNELS];
bool trigger_enabled;
u16 *buffer;
/* Remember enabled channels and sample rate during suspend. */
unsigned int suspend_ctrl0;
struct completion completion;
int data_rdy_users, close_far_users;
int channel_users[SX9500_NUM_CHANNELS];
};
static const struct iio_event_spec sx9500_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
},
};
#define SX9500_CHANNEL(idx) \
{ \
.type = IIO_PROXIMITY, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.indexed = 1, \
.channel = idx, \
.event_spec = sx9500_events, \
.num_event_specs = ARRAY_SIZE(sx9500_events), \
.scan_index = idx, \
.scan_type = { \
.sign = 'u', \
.realbits = 16, \
.storagebits = 16, \
.shift = 0, \
}, \
}
static const struct iio_chan_spec sx9500_channels[] = {
SX9500_CHANNEL(0),
SX9500_CHANNEL(1),
SX9500_CHANNEL(2),
SX9500_CHANNEL(3),
IIO_CHAN_SOFT_TIMESTAMP(4),
};
static const struct {
int val;
int val2;
} sx9500_samp_freq_table[] = {
{33, 333333},
{16, 666666},
{11, 111111},
{8, 333333},
{6, 666666},
{5, 0},
{3, 333333},
{2, 500000},
};
static const unsigned int sx9500_scan_period_table[] = {
30, 60, 90, 120, 150, 200, 300, 400,
};
static const struct regmap_range sx9500_writable_reg_ranges[] = {
regmap_reg_range(SX9500_REG_IRQ_MSK, SX9500_REG_IRQ_MSK),
regmap_reg_range(SX9500_REG_PROX_CTRL0, SX9500_REG_PROX_CTRL8),
regmap_reg_range(SX9500_REG_SENSOR_SEL, SX9500_REG_SENSOR_SEL),
regmap_reg_range(SX9500_REG_OFFSET_MSB, SX9500_REG_OFFSET_LSB),
regmap_reg_range(SX9500_REG_RESET, SX9500_REG_RESET),
};
static const struct regmap_access_table sx9500_writeable_regs = {
.yes_ranges = sx9500_writable_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(sx9500_writable_reg_ranges),
};
/*
* All allocated registers are readable, so we just list unallocated
* ones.
*/
static const struct regmap_range sx9500_non_readable_reg_ranges[] = {
regmap_reg_range(SX9500_REG_STAT + 1, SX9500_REG_STAT + 1),
regmap_reg_range(SX9500_REG_IRQ_MSK + 1, SX9500_REG_PROX_CTRL0 - 1),
regmap_reg_range(SX9500_REG_PROX_CTRL8 + 1, SX9500_REG_SENSOR_SEL - 1),
regmap_reg_range(SX9500_REG_OFFSET_LSB + 1, SX9500_REG_RESET - 1),
};
static const struct regmap_access_table sx9500_readable_regs = {
.no_ranges = sx9500_non_readable_reg_ranges,
.n_no_ranges = ARRAY_SIZE(sx9500_non_readable_reg_ranges),
};
static const struct regmap_range sx9500_volatile_reg_ranges[] = {
regmap_reg_range(SX9500_REG_IRQ_SRC, SX9500_REG_STAT),
regmap_reg_range(SX9500_REG_USE_MSB, SX9500_REG_OFFSET_LSB),
regmap_reg_range(SX9500_REG_RESET, SX9500_REG_RESET),
};
static const struct regmap_access_table sx9500_volatile_regs = {
.yes_ranges = sx9500_volatile_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(sx9500_volatile_reg_ranges),
};
static const struct regmap_config sx9500_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = SX9500_REG_RESET,
.cache_type = REGCACHE_RBTREE,
.wr_table = &sx9500_writeable_regs,
.rd_table = &sx9500_readable_regs,
.volatile_table = &sx9500_volatile_regs,
};
static int sx9500_inc_users(struct sx9500_data *data, int *counter,
unsigned int reg, unsigned int bitmask)
{
(*counter)++;
if (*counter != 1)
/* Bit is already active, nothing to do. */
return 0;
return regmap_update_bits(data->regmap, reg, bitmask, bitmask);
}
static int sx9500_dec_users(struct sx9500_data *data, int *counter,
unsigned int reg, unsigned int bitmask)
{
(*counter)--;
if (*counter != 0)
/* There are more users, do not deactivate. */
return 0;
return regmap_update_bits(data->regmap, reg, bitmask, 0);
}
static int sx9500_inc_chan_users(struct sx9500_data *data, int chan)
{
return sx9500_inc_users(data, &data->channel_users[chan],
SX9500_REG_PROX_CTRL0, BIT(chan));
}
static int sx9500_dec_chan_users(struct sx9500_data *data, int chan)
{
return sx9500_dec_users(data, &data->channel_users[chan],
SX9500_REG_PROX_CTRL0, BIT(chan));
}
static int sx9500_inc_data_rdy_users(struct sx9500_data *data)
{
return sx9500_inc_users(data, &data->data_rdy_users,
SX9500_REG_IRQ_MSK, SX9500_CONVDONE_IRQ);
}
static int sx9500_dec_data_rdy_users(struct sx9500_data *data)
{
return sx9500_dec_users(data, &data->data_rdy_users,
SX9500_REG_IRQ_MSK, SX9500_CONVDONE_IRQ);
}
static int sx9500_inc_close_far_users(struct sx9500_data *data)
{
return sx9500_inc_users(data, &data->close_far_users,
SX9500_REG_IRQ_MSK,
SX9500_CLOSE_IRQ | SX9500_FAR_IRQ);
}
static int sx9500_dec_close_far_users(struct sx9500_data *data)
{
return sx9500_dec_users(data, &data->close_far_users,
SX9500_REG_IRQ_MSK,
SX9500_CLOSE_IRQ | SX9500_FAR_IRQ);
}
static int sx9500_read_prox_data(struct sx9500_data *data,
const struct iio_chan_spec *chan,
int *val)
{
int ret;
__be16 regval;
ret = regmap_write(data->regmap, SX9500_REG_SENSOR_SEL, chan->channel);
if (ret < 0)
return ret;
ret = regmap_bulk_read(data->regmap, SX9500_REG_USE_MSB, ®val, 2);
if (ret < 0)
return ret;
*val = be16_to_cpu(regval);
return IIO_VAL_INT;
}
/*
* If we have no interrupt support, we have to wait for a scan period
* after enabling a channel to get a result.
*/
static int sx9500_wait_for_sample(struct sx9500_data *data)
{
int ret;
unsigned int val;
ret = regmap_read(data->regmap, SX9500_REG_PROX_CTRL0, &val);
if (ret < 0)
return ret;
val = (val & SX9500_SCAN_PERIOD_MASK) >> SX9500_SCAN_PERIOD_SHIFT;
msleep(sx9500_scan_period_table[val]);
return 0;
}
static int sx9500_read_proximity(struct sx9500_data *data,
const struct iio_chan_spec *chan,
int *val)
{
int ret;
mutex_lock(&data->mutex);
ret = sx9500_inc_chan_users(data, chan->channel);
if (ret < 0)
goto out;
ret = sx9500_inc_data_rdy_users(data);
if (ret < 0)
goto out_dec_chan;
mutex_unlock(&data->mutex);
if (data->client->irq > 0)
ret = wait_for_completion_interruptible(&data->completion);
else
ret = sx9500_wait_for_sample(data);
mutex_lock(&data->mutex);
if (ret < 0)
goto out_dec_data_rdy;
ret = sx9500_read_prox_data(data, chan, val);
if (ret < 0)
goto out_dec_data_rdy;
ret = sx9500_dec_data_rdy_users(data);
if (ret < 0)
goto out_dec_chan;
ret = sx9500_dec_chan_users(data, chan->channel);
if (ret < 0)
goto out;
ret = IIO_VAL_INT;
goto out;
out_dec_data_rdy:
sx9500_dec_data_rdy_users(data);
out_dec_chan:
sx9500_dec_chan_users(data, chan->channel);
out:
mutex_unlock(&data->mutex);
reinit_completion(&data->completion);
return ret;
}
static int sx9500_read_samp_freq(struct sx9500_data *data,
int *val, int *val2)
{
int ret;
unsigned int regval;
mutex_lock(&data->mutex);
ret = regmap_read(data->regmap, SX9500_REG_PROX_CTRL0, ®val);
mutex_unlock(&data->mutex);
if (ret < 0)
return ret;
regval = (regval & SX9500_SCAN_PERIOD_MASK) >> SX9500_SCAN_PERIOD_SHIFT;
*val = sx9500_samp_freq_table[regval].val;
*val2 = sx9500_samp_freq_table[regval].val2;
return IIO_VAL_INT_PLUS_MICRO;
}
static int sx9500_read_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
int *val, int *val2, long mask)
{
struct sx9500_data *data = iio_priv(indio_dev);
int ret;
switch (chan->type) {
case IIO_PROXIMITY:
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = sx9500_read_proximity(data, chan, val);
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_SAMP_FREQ:
return sx9500_read_samp_freq(data, val, val2);
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int sx9500_set_samp_freq(struct sx9500_data *data,
int val, int val2)
{
int i, ret;
for (i = 0; i < ARRAY_SIZE(sx9500_samp_freq_table); i++)
if (val == sx9500_samp_freq_table[i].val &&
val2 == sx9500_samp_freq_table[i].val2)
break;
if (i == ARRAY_SIZE(sx9500_samp_freq_table))
return -EINVAL;
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9500_REG_PROX_CTRL0,
SX9500_SCAN_PERIOD_MASK,
i << SX9500_SCAN_PERIOD_SHIFT);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9500_write_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
int val, int val2, long mask)
{
struct sx9500_data *data = iio_priv(indio_dev);
switch (chan->type) {
case IIO_PROXIMITY:
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
return sx9500_set_samp_freq(data, val, val2);
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static irqreturn_t sx9500_irq_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct sx9500_data *data = iio_priv(indio_dev);
if (data->trigger_enabled)
iio_trigger_poll(data->trig);
/*
* Even if no event is enabled, we need to wake the thread to
* clear the interrupt state by reading SX9500_REG_IRQ_SRC. It
* is not possible to do that here because regmap_read takes a
* mutex.
*/
return IRQ_WAKE_THREAD;
}
static void sx9500_push_events(struct iio_dev *indio_dev)
{
int ret;
unsigned int val, chan;
struct sx9500_data *data = iio_priv(indio_dev);
ret = regmap_read(data->regmap, SX9500_REG_STAT, &val);
if (ret < 0) {
dev_err(&data->client->dev, "i2c transfer error in irq\n");
return;
}
val >>= SX9500_PROXSTAT_SHIFT;
for (chan = 0; chan < SX9500_NUM_CHANNELS; chan++) {
int dir;
u64 ev;
bool new_prox = val & BIT(chan);
if (!data->event_enabled[chan])
continue;
if (new_prox == data->prox_stat[chan])
/* No change on this channel. */
continue;
dir = new_prox ? IIO_EV_DIR_FALLING : IIO_EV_DIR_RISING;
ev = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, chan,
IIO_EV_TYPE_THRESH, dir);
iio_push_event(indio_dev, ev, iio_get_time_ns(indio_dev));
data->prox_stat[chan] = new_prox;
}
}
static irqreturn_t sx9500_irq_thread_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct sx9500_data *data = iio_priv(indio_dev);
int ret;
unsigned int val;
mutex_lock(&data->mutex);
ret = regmap_read(data->regmap, SX9500_REG_IRQ_SRC, &val);
if (ret < 0) {
dev_err(&data->client->dev, "i2c transfer error in irq\n");
goto out;
}
if (val & (SX9500_CLOSE_IRQ | SX9500_FAR_IRQ))
sx9500_push_events(indio_dev);
if (val & SX9500_CONVDONE_IRQ)
complete(&data->completion);
out:
mutex_unlock(&data->mutex);
return IRQ_HANDLED;
}
static int sx9500_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct sx9500_data *data = iio_priv(indio_dev);
if (chan->type != IIO_PROXIMITY || type != IIO_EV_TYPE_THRESH ||
dir != IIO_EV_DIR_EITHER)
return -EINVAL;
return data->event_enabled[chan->channel];
}
static int sx9500_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
struct sx9500_data *data = iio_priv(indio_dev);
int ret;
if (chan->type != IIO_PROXIMITY || type != IIO_EV_TYPE_THRESH ||
dir != IIO_EV_DIR_EITHER)
return -EINVAL;
mutex_lock(&data->mutex);
if (state == 1) {
ret = sx9500_inc_chan_users(data, chan->channel);
if (ret < 0)
goto out_unlock;
ret = sx9500_inc_close_far_users(data);
if (ret < 0)
goto out_undo_chan;
} else {
ret = sx9500_dec_chan_users(data, chan->channel);
if (ret < 0)
goto out_unlock;
ret = sx9500_dec_close_far_users(data);
if (ret < 0)
goto out_undo_chan;
}
data->event_enabled[chan->channel] = state;
goto out_unlock;
out_undo_chan:
if (state == 1)
sx9500_dec_chan_users(data, chan->channel);
else
sx9500_inc_chan_users(data, chan->channel);
out_unlock:
mutex_unlock(&data->mutex);
return ret;
}
static int sx9500_update_scan_mode(struct iio_dev *indio_dev,
const unsigned long *scan_mask)
{
struct sx9500_data *data = iio_priv(indio_dev);
mutex_lock(&data->mutex);
kfree(data->buffer);
data->buffer = kzalloc(indio_dev->scan_bytes, GFP_KERNEL);
mutex_unlock(&data->mutex);
if (data->buffer == NULL)
return -ENOMEM;
return 0;
}
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
"2.500000 3.333333 5 6.666666 8.333333 11.111111 16.666666 33.333333");
static struct attribute *sx9500_attributes[] = {
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL,
};
static const struct attribute_group sx9500_attribute_group = {
.attrs = sx9500_attributes,
};
static const struct iio_info sx9500_info = {
.attrs = &sx9500_attribute_group,
.read_raw = &sx9500_read_raw,
.write_raw = &sx9500_write_raw,
.read_event_config = &sx9500_read_event_config,
.write_event_config = &sx9500_write_event_config,
.update_scan_mode = &sx9500_update_scan_mode,
};
static int sx9500_set_trigger_state(struct iio_trigger *trig,
bool state)
{
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
struct sx9500_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->mutex);
if (state)
ret = sx9500_inc_data_rdy_users(data);
else
ret = sx9500_dec_data_rdy_users(data);
if (ret < 0)
goto out;
data->trigger_enabled = state;
out:
mutex_unlock(&data->mutex);
return ret;
}
static const struct iio_trigger_ops sx9500_trigger_ops = {
.set_trigger_state = sx9500_set_trigger_state,
};
static irqreturn_t sx9500_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct sx9500_data *data = iio_priv(indio_dev);
int val, bit, ret, i = 0;
mutex_lock(&data->mutex);
for_each_set_bit(bit, indio_dev->active_scan_mask,
indio_dev->masklength) {
ret = sx9500_read_prox_data(data, &indio_dev->channels[bit],
&val);
if (ret < 0)
goto out;
data->buffer[i++] = val;
}
iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
iio_get_time_ns(indio_dev));
out:
mutex_unlock(&data->mutex);
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int sx9500_buffer_postenable(struct iio_dev *indio_dev)
{
struct sx9500_data *data = iio_priv(indio_dev);
int ret = 0, i;
mutex_lock(&data->mutex);
for (i = 0; i < SX9500_NUM_CHANNELS; i++)
if (test_bit(i, indio_dev->active_scan_mask)) {
ret = sx9500_inc_chan_users(data, i);
if (ret)
break;
}
if (ret)
for (i = i - 1; i >= 0; i--)
if (test_bit(i, indio_dev->active_scan_mask))
sx9500_dec_chan_users(data, i);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9500_buffer_predisable(struct iio_dev *indio_dev)
{
struct sx9500_data *data = iio_priv(indio_dev);
int ret = 0, i;
mutex_lock(&data->mutex);
for (i = 0; i < SX9500_NUM_CHANNELS; i++)
if (test_bit(i, indio_dev->active_scan_mask)) {
ret = sx9500_dec_chan_users(data, i);
if (ret)
break;
}
if (ret)
for (i = i - 1; i >= 0; i--)
if (test_bit(i, indio_dev->active_scan_mask))
sx9500_inc_chan_users(data, i);
mutex_unlock(&data->mutex);
return ret;
}
static const struct iio_buffer_setup_ops sx9500_buffer_setup_ops = {
.postenable = sx9500_buffer_postenable,
.predisable = sx9500_buffer_predisable,
};
struct sx9500_reg_default {
u8 reg;
u8 def;
};
static const struct sx9500_reg_default sx9500_default_regs[] = {
{
.reg = SX9500_REG_PROX_CTRL1,
/* Shield enabled, small range. */
.def = 0x43,
},
{
.reg = SX9500_REG_PROX_CTRL2,
/* x8 gain, 167kHz frequency, finest resolution. */
.def = 0x77,
},
{
.reg = SX9500_REG_PROX_CTRL3,
/* Doze enabled, 2x scan period doze, no raw filter. */
.def = 0x40,
},
{
.reg = SX9500_REG_PROX_CTRL4,
/* Average threshold. */
.def = 0x30,
},
{
.reg = SX9500_REG_PROX_CTRL5,
/*
* Debouncer off, lowest average negative filter,
* highest average positive filter.
*/
.def = 0x0f,
},
{
.reg = SX9500_REG_PROX_CTRL6,
/* Proximity detection threshold: 280 */
.def = 0x0e,
},
{
.reg = SX9500_REG_PROX_CTRL7,
/*
* No automatic compensation, compensate each pin
* independently, proximity hysteresis: 32, close
* debouncer off, far debouncer off.
*/
.def = 0x00,
},
{
.reg = SX9500_REG_PROX_CTRL8,
/* No stuck timeout, no periodic compensation. */
.def = 0x00,
},
{
.reg = SX9500_REG_PROX_CTRL0,
/* Scan period: 30ms, all sensors disabled. */
.def = 0x00,
},
};
/* Activate all channels and perform an initial compensation. */
static int sx9500_init_compensation(struct iio_dev *indio_dev)
{
struct sx9500_data *data = iio_priv(indio_dev);
int i, ret;
unsigned int val;
ret = regmap_update_bits(data->regmap, SX9500_REG_PROX_CTRL0,
SX9500_CHAN_MASK, SX9500_CHAN_MASK);
if (ret < 0)
return ret;
for (i = 10; i >= 0; i--) {
usleep_range(10000, 20000);
ret = regmap_read(data->regmap, SX9500_REG_STAT, &val);
if (ret < 0)
goto out;
if (!(val & SX9500_COMPSTAT_MASK))
break;
}
if (i < 0) {
dev_err(&data->client->dev, "initial compensation timed out");
ret = -ETIMEDOUT;
}
out:
regmap_update_bits(data->regmap, SX9500_REG_PROX_CTRL0,
SX9500_CHAN_MASK, 0);
return ret;
}
static int sx9500_init_device(struct iio_dev *indio_dev)
{
struct sx9500_data *data = iio_priv(indio_dev);
int ret, i;
unsigned int val;
if (data->gpiod_rst) {
gpiod_set_value_cansleep(data->gpiod_rst, 0);
usleep_range(1000, 2000);
gpiod_set_value_cansleep(data->gpiod_rst, 1);
usleep_range(1000, 2000);
}
ret = regmap_write(data->regmap, SX9500_REG_IRQ_MSK, 0);
if (ret < 0)
return ret;
ret = regmap_write(data->regmap, SX9500_REG_RESET,
SX9500_SOFT_RESET);
if (ret < 0)
return ret;
ret = regmap_read(data->regmap, SX9500_REG_IRQ_SRC, &val);
if (ret < 0)
return ret;
for (i = 0; i < ARRAY_SIZE(sx9500_default_regs); i++) {
ret = regmap_write(data->regmap,
sx9500_default_regs[i].reg,
sx9500_default_regs[i].def);
if (ret < 0)
return ret;
}
return sx9500_init_compensation(indio_dev);
}
static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
static const struct acpi_gpio_params interrupt_gpios = { 2, 0, false };
static const struct acpi_gpio_mapping acpi_sx9500_gpios[] = {
{ "reset-gpios", &reset_gpios, 1 },
/*
* Some platforms have a bug in ACPI GPIO description making IRQ
* GPIO to be output only. Ask the GPIO core to ignore this limit.
*/
{ "interrupt-gpios", &interrupt_gpios, 1, ACPI_GPIO_QUIRK_NO_IO_RESTRICTION },
{ },
};
static void sx9500_gpio_probe(struct i2c_client *client,
struct sx9500_data *data)
{
struct gpio_desc *gpiod_int;
struct device *dev;
int ret;
if (!client)
return;
dev = &client->dev;
ret = devm_acpi_dev_add_driver_gpios(dev, acpi_sx9500_gpios);
if (ret)
dev_dbg(dev, "Unable to add GPIO mapping table\n");
if (client->irq <= 0) {
gpiod_int = devm_gpiod_get(dev, "interrupt", GPIOD_IN);
if (IS_ERR(gpiod_int))
dev_err(dev, "gpio get irq failed\n");
else
client->irq = gpiod_to_irq(gpiod_int);
}
data->gpiod_rst = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(data->gpiod_rst)) {
dev_warn(dev, "gpio get reset pin failed\n");
data->gpiod_rst = NULL;
}
}
static int sx9500_probe(struct i2c_client *client)
{
int ret;
struct iio_dev *indio_dev;
struct sx9500_data *data;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (indio_dev == NULL)
return -ENOMEM;
data = iio_priv(indio_dev);
data->client = client;
mutex_init(&data->mutex);
init_completion(&data->completion);
data->trigger_enabled = false;
data->regmap = devm_regmap_init_i2c(client, &sx9500_regmap_config);
if (IS_ERR(data->regmap))
return PTR_ERR(data->regmap);
indio_dev->name = SX9500_DRIVER_NAME;
indio_dev->channels = sx9500_channels;
indio_dev->num_channels = ARRAY_SIZE(sx9500_channels);
indio_dev->info = &sx9500_info;
indio_dev->modes = INDIO_DIRECT_MODE;
i2c_set_clientdata(client, indio_dev);
sx9500_gpio_probe(client, data);
ret = sx9500_init_device(indio_dev);
if (ret < 0)
return ret;
if (client->irq <= 0)
dev_warn(&client->dev, "no valid irq found\n");
else {
ret = devm_request_threaded_irq(&client->dev, client->irq,
sx9500_irq_handler, sx9500_irq_thread_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
SX9500_IRQ_NAME, indio_dev);
if (ret < 0)
return ret;
data->trig = devm_iio_trigger_alloc(&client->dev,
"%s-dev%d", indio_dev->name, iio_device_id(indio_dev));
if (!data->trig)
return -ENOMEM;
data->trig->ops = &sx9500_trigger_ops;
iio_trigger_set_drvdata(data->trig, indio_dev);
ret = iio_trigger_register(data->trig);
if (ret)
return ret;
}
ret = iio_triggered_buffer_setup(indio_dev, NULL,
sx9500_trigger_handler,
&sx9500_buffer_setup_ops);
if (ret < 0)
goto out_trigger_unregister;
ret = iio_device_register(indio_dev);
if (ret < 0)
goto out_buffer_cleanup;
return 0;
out_buffer_cleanup:
iio_triggered_buffer_cleanup(indio_dev);
out_trigger_unregister:
if (client->irq > 0)
iio_trigger_unregister(data->trig);
return ret;
}
static void sx9500_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct sx9500_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
iio_triggered_buffer_cleanup(indio_dev);
if (client->irq > 0)
iio_trigger_unregister(data->trig);
kfree(data->buffer);
}
static int sx9500_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct sx9500_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->mutex);
ret = regmap_read(data->regmap, SX9500_REG_PROX_CTRL0,
&data->suspend_ctrl0);
if (ret < 0)
goto out;
/*
* Scan period doesn't matter because when all the sensors are
* deactivated the device is in sleep mode.
*/
ret = regmap_write(data->regmap, SX9500_REG_PROX_CTRL0, 0);
out:
mutex_unlock(&data->mutex);
return ret;
}
static int sx9500_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct sx9500_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->mutex);
ret = regmap_write(data->regmap, SX9500_REG_PROX_CTRL0,
data->suspend_ctrl0);
mutex_unlock(&data->mutex);
return ret;
}
static DEFINE_SIMPLE_DEV_PM_OPS(sx9500_pm_ops, sx9500_suspend, sx9500_resume);
static const struct acpi_device_id sx9500_acpi_match[] = {
{"SSX9500", 0},
{"SASX9500", 0},
{ },
};
MODULE_DEVICE_TABLE(acpi, sx9500_acpi_match);
static const struct of_device_id sx9500_of_match[] = {
{ .compatible = "semtech,sx9500", },
{ }
};
MODULE_DEVICE_TABLE(of, sx9500_of_match);
static const struct i2c_device_id sx9500_id[] = {
{"sx9500", 0},
{ },
};
MODULE_DEVICE_TABLE(i2c, sx9500_id);
static struct i2c_driver sx9500_driver = {
.driver = {
.name = SX9500_DRIVER_NAME,
.acpi_match_table = sx9500_acpi_match,
.of_match_table = sx9500_of_match,
.pm = pm_sleep_ptr(&sx9500_pm_ops),
},
.probe = sx9500_probe,
.remove = sx9500_remove,
.id_table = sx9500_id,
};
module_i2c_driver(sx9500_driver);
MODULE_AUTHOR("Vlad Dogaru <[email protected]>");
MODULE_DESCRIPTION("Driver for Semtech SX9500 proximity sensor");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/proximity/sx9500.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2021 Google LLC.
*
* Common part of most Semtech SAR sensor.
*/
#include <linux/bitops.h>
#include <linux/byteorder/generic.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/irqreturn.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <vdso/bits.h>
#include <linux/iio/buffer.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include "sx_common.h"
/* All Semtech SAR sensors have IRQ bit in the same order. */
#define SX_COMMON_CONVDONE_IRQ BIT(0)
#define SX_COMMON_FAR_IRQ BIT(2)
#define SX_COMMON_CLOSE_IRQ BIT(3)
const struct iio_event_spec sx_common_events[3] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
BIT(IIO_EV_INFO_HYSTERESIS) |
BIT(IIO_EV_INFO_VALUE),
},
};
EXPORT_SYMBOL_NS_GPL(sx_common_events, SEMTECH_PROX);
static irqreturn_t sx_common_irq_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct sx_common_data *data = iio_priv(indio_dev);
if (data->trigger_enabled)
iio_trigger_poll(data->trig);
/*
* Even if no event is enabled, we need to wake the thread to clear the
* interrupt state by reading SX_COMMON_REG_IRQ_SRC.
* It is not possible to do that here because regmap_read takes a mutex.
*/
return IRQ_WAKE_THREAD;
}
static void sx_common_push_events(struct iio_dev *indio_dev)
{
int ret;
unsigned int val, chan;
struct sx_common_data *data = iio_priv(indio_dev);
s64 timestamp = iio_get_time_ns(indio_dev);
unsigned long prox_changed;
/* Read proximity state on all channels */
ret = regmap_read(data->regmap, data->chip_info->reg_stat, &val);
if (ret) {
dev_err(&data->client->dev, "i2c transfer error in irq\n");
return;
}
val >>= data->chip_info->stat_offset;
/*
* Only iterate over channels with changes on proximity status that have
* events enabled.
*/
prox_changed = (data->chan_prox_stat ^ val) & data->chan_event;
for_each_set_bit(chan, &prox_changed, data->chip_info->num_channels) {
int dir;
u64 ev;
dir = (val & BIT(chan)) ? IIO_EV_DIR_FALLING : IIO_EV_DIR_RISING;
ev = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, chan,
IIO_EV_TYPE_THRESH, dir);
iio_push_event(indio_dev, ev, timestamp);
}
data->chan_prox_stat = val;
}
static int sx_common_enable_irq(struct sx_common_data *data, unsigned int irq)
{
if (!data->client->irq)
return 0;
return regmap_update_bits(data->regmap, data->chip_info->reg_irq_msk,
irq << data->chip_info->irq_msk_offset,
irq << data->chip_info->irq_msk_offset);
}
static int sx_common_disable_irq(struct sx_common_data *data, unsigned int irq)
{
if (!data->client->irq)
return 0;
return regmap_update_bits(data->regmap, data->chip_info->reg_irq_msk,
irq << data->chip_info->irq_msk_offset, 0);
}
static int sx_common_update_chan_en(struct sx_common_data *data,
unsigned long chan_read,
unsigned long chan_event)
{
int ret;
unsigned long channels = chan_read | chan_event;
if ((data->chan_read | data->chan_event) != channels) {
ret = regmap_update_bits(data->regmap,
data->chip_info->reg_enable_chan,
data->chip_info->mask_enable_chan,
channels);
if (ret)
return ret;
}
data->chan_read = chan_read;
data->chan_event = chan_event;
return 0;
}
static int sx_common_get_read_channel(struct sx_common_data *data, int channel)
{
return sx_common_update_chan_en(data, data->chan_read | BIT(channel),
data->chan_event);
}
static int sx_common_put_read_channel(struct sx_common_data *data, int channel)
{
return sx_common_update_chan_en(data, data->chan_read & ~BIT(channel),
data->chan_event);
}
static int sx_common_get_event_channel(struct sx_common_data *data, int channel)
{
return sx_common_update_chan_en(data, data->chan_read,
data->chan_event | BIT(channel));
}
static int sx_common_put_event_channel(struct sx_common_data *data, int channel)
{
return sx_common_update_chan_en(data, data->chan_read,
data->chan_event & ~BIT(channel));
}
/**
* sx_common_read_proximity() - Read raw proximity value.
* @data: Internal data
* @chan: Channel to read
* @val: pointer to return read value.
*
* Request a conversion, wait for the sensor to be ready and
* return the raw proximity value.
*/
int sx_common_read_proximity(struct sx_common_data *data,
const struct iio_chan_spec *chan, int *val)
{
int ret;
__be16 rawval;
mutex_lock(&data->mutex);
ret = sx_common_get_read_channel(data, chan->channel);
if (ret)
goto out;
ret = sx_common_enable_irq(data, SX_COMMON_CONVDONE_IRQ);
if (ret)
goto out_put_channel;
mutex_unlock(&data->mutex);
if (data->client->irq) {
ret = wait_for_completion_interruptible(&data->completion);
reinit_completion(&data->completion);
} else {
ret = data->chip_info->ops.wait_for_sample(data);
}
mutex_lock(&data->mutex);
if (ret)
goto out_disable_irq;
ret = data->chip_info->ops.read_prox_data(data, chan, &rawval);
if (ret)
goto out_disable_irq;
*val = sign_extend32(be16_to_cpu(rawval), chan->scan_type.realbits - 1);
ret = sx_common_disable_irq(data, SX_COMMON_CONVDONE_IRQ);
if (ret)
goto out_put_channel;
ret = sx_common_put_read_channel(data, chan->channel);
if (ret)
goto out;
mutex_unlock(&data->mutex);
return IIO_VAL_INT;
out_disable_irq:
sx_common_disable_irq(data, SX_COMMON_CONVDONE_IRQ);
out_put_channel:
sx_common_put_read_channel(data, chan->channel);
out:
mutex_unlock(&data->mutex);
return ret;
}
EXPORT_SYMBOL_NS_GPL(sx_common_read_proximity, SEMTECH_PROX);
/**
* sx_common_read_event_config() - Configure event setting.
* @indio_dev: iio device object
* @chan: Channel to read
* @type: Type of event (unused)
* @dir: Direction of event (unused)
*
* return if the given channel is used for event gathering.
*/
int sx_common_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct sx_common_data *data = iio_priv(indio_dev);
return !!(data->chan_event & BIT(chan->channel));
}
EXPORT_SYMBOL_NS_GPL(sx_common_read_event_config, SEMTECH_PROX);
/**
* sx_common_write_event_config() - Configure event setting.
* @indio_dev: iio device object
* @chan: Channel to enable
* @type: Type of event (unused)
* @dir: Direction of event (unused)
* @state: State of the event.
*
* Enable/Disable event on a given channel.
*/
int sx_common_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct sx_common_data *data = iio_priv(indio_dev);
unsigned int eventirq = SX_COMMON_FAR_IRQ | SX_COMMON_CLOSE_IRQ;
int ret;
/* If the state hasn't changed, there's nothing to do. */
if (!!(data->chan_event & BIT(chan->channel)) == state)
return 0;
mutex_lock(&data->mutex);
if (state) {
ret = sx_common_get_event_channel(data, chan->channel);
if (ret)
goto out_unlock;
if (!(data->chan_event & ~BIT(chan->channel))) {
ret = sx_common_enable_irq(data, eventirq);
if (ret)
sx_common_put_event_channel(data, chan->channel);
}
} else {
ret = sx_common_put_event_channel(data, chan->channel);
if (ret)
goto out_unlock;
if (!data->chan_event) {
ret = sx_common_disable_irq(data, eventirq);
if (ret)
sx_common_get_event_channel(data, chan->channel);
}
}
out_unlock:
mutex_unlock(&data->mutex);
return ret;
}
EXPORT_SYMBOL_NS_GPL(sx_common_write_event_config, SEMTECH_PROX);
static int sx_common_set_trigger_state(struct iio_trigger *trig, bool state)
{
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
struct sx_common_data *data = iio_priv(indio_dev);
int ret = 0;
mutex_lock(&data->mutex);
if (state)
ret = sx_common_enable_irq(data, SX_COMMON_CONVDONE_IRQ);
else if (!data->chan_read)
ret = sx_common_disable_irq(data, SX_COMMON_CONVDONE_IRQ);
if (ret)
goto out;
data->trigger_enabled = state;
out:
mutex_unlock(&data->mutex);
return ret;
}
static const struct iio_trigger_ops sx_common_trigger_ops = {
.set_trigger_state = sx_common_set_trigger_state,
};
static irqreturn_t sx_common_irq_thread_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct sx_common_data *data = iio_priv(indio_dev);
int ret;
unsigned int val;
mutex_lock(&data->mutex);
ret = regmap_read(data->regmap, SX_COMMON_REG_IRQ_SRC, &val);
if (ret) {
dev_err(&data->client->dev, "i2c transfer error in irq\n");
goto out;
}
if (val & ((SX_COMMON_FAR_IRQ | SX_COMMON_CLOSE_IRQ) << data->chip_info->irq_msk_offset))
sx_common_push_events(indio_dev);
if (val & (SX_COMMON_CONVDONE_IRQ << data->chip_info->irq_msk_offset))
complete(&data->completion);
out:
mutex_unlock(&data->mutex);
return IRQ_HANDLED;
}
static irqreturn_t sx_common_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct sx_common_data *data = iio_priv(indio_dev);
__be16 val;
int bit, ret, i = 0;
mutex_lock(&data->mutex);
for_each_set_bit(bit, indio_dev->active_scan_mask,
indio_dev->masklength) {
ret = data->chip_info->ops.read_prox_data(data,
&indio_dev->channels[bit],
&val);
if (ret)
goto out;
data->buffer.channels[i++] = val;
}
iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
pf->timestamp);
out:
mutex_unlock(&data->mutex);
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int sx_common_buffer_preenable(struct iio_dev *indio_dev)
{
struct sx_common_data *data = iio_priv(indio_dev);
unsigned long channels = 0;
int bit, ret;
mutex_lock(&data->mutex);
for_each_set_bit(bit, indio_dev->active_scan_mask,
indio_dev->masklength)
__set_bit(indio_dev->channels[bit].channel, &channels);
ret = sx_common_update_chan_en(data, channels, data->chan_event);
mutex_unlock(&data->mutex);
return ret;
}
static int sx_common_buffer_postdisable(struct iio_dev *indio_dev)
{
struct sx_common_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->mutex);
ret = sx_common_update_chan_en(data, 0, data->chan_event);
mutex_unlock(&data->mutex);
return ret;
}
static const struct iio_buffer_setup_ops sx_common_buffer_setup_ops = {
.preenable = sx_common_buffer_preenable,
.postdisable = sx_common_buffer_postdisable,
};
void sx_common_get_raw_register_config(struct device *dev,
struct sx_common_reg_default *reg_def)
{
#ifdef CONFIG_ACPI
struct acpi_device *adev = ACPI_COMPANION(dev);
u32 raw = 0, ret;
char prop[80];
if (!reg_def->property || !adev)
return;
snprintf(prop, ARRAY_SIZE(prop), "%s,reg_%s", acpi_device_hid(adev), reg_def->property);
ret = device_property_read_u32(dev, prop, &raw);
if (ret)
return;
reg_def->def = raw;
#endif
}
EXPORT_SYMBOL_NS_GPL(sx_common_get_raw_register_config, SEMTECH_PROX);
#define SX_COMMON_SOFT_RESET 0xde
static int sx_common_init_device(struct device *dev, struct iio_dev *indio_dev)
{
struct sx_common_data *data = iio_priv(indio_dev);
struct sx_common_reg_default tmp;
const struct sx_common_reg_default *initval;
int ret;
unsigned int i, val;
ret = regmap_write(data->regmap, data->chip_info->reg_reset,
SX_COMMON_SOFT_RESET);
if (ret)
return ret;
usleep_range(1000, 2000); /* power-up time is ~1ms. */
/* Clear reset interrupt state by reading SX_COMMON_REG_IRQ_SRC. */
ret = regmap_read(data->regmap, SX_COMMON_REG_IRQ_SRC, &val);
if (ret)
return ret;
/* Program defaults from constant or BIOS. */
for (i = 0; i < data->chip_info->num_default_regs; i++) {
initval = data->chip_info->ops.get_default_reg(dev, i, &tmp);
ret = regmap_write(data->regmap, initval->reg, initval->def);
if (ret)
return ret;
}
return data->chip_info->ops.init_compensation(indio_dev);
}
/**
* sx_common_probe() - Common setup for Semtech SAR sensor
* @client: I2C client object
* @chip_info: Semtech sensor chip information.
* @regmap_config: Sensor registers map configuration.
*/
int sx_common_probe(struct i2c_client *client,
const struct sx_common_chip_info *chip_info,
const struct regmap_config *regmap_config)
{
static const char * const regulator_names[] = { "vdd", "svdd" };
struct device *dev = &client->dev;
struct iio_dev *indio_dev;
struct sx_common_data *data;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->chip_info = chip_info;
data->client = client;
mutex_init(&data->mutex);
init_completion(&data->completion);
data->regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(data->regmap))
return dev_err_probe(dev, PTR_ERR(data->regmap),
"Could init register map\n");
ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names),
regulator_names);
if (ret)
return dev_err_probe(dev, ret, "Unable to get regulators\n");
/* Must wait for Tpor time after initial power up */
usleep_range(1000, 1100);
ret = data->chip_info->ops.check_whoami(dev, indio_dev);
if (ret)
return dev_err_probe(dev, ret, "error reading WHOAMI\n");
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = data->chip_info->iio_channels;
indio_dev->num_channels = data->chip_info->num_iio_channels;
indio_dev->info = &data->chip_info->iio_info;
i2c_set_clientdata(client, indio_dev);
ret = sx_common_init_device(dev, indio_dev);
if (ret)
return dev_err_probe(dev, ret, "Unable to initialize sensor\n");
if (client->irq) {
ret = devm_request_threaded_irq(dev, client->irq,
sx_common_irq_handler,
sx_common_irq_thread_handler,
IRQF_ONESHOT,
"sx_event", indio_dev);
if (ret)
return dev_err_probe(dev, ret, "No IRQ\n");
data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
indio_dev->name,
iio_device_id(indio_dev));
if (!data->trig)
return -ENOMEM;
data->trig->ops = &sx_common_trigger_ops;
iio_trigger_set_drvdata(data->trig, indio_dev);
ret = devm_iio_trigger_register(dev, data->trig);
if (ret)
return ret;
}
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
iio_pollfunc_store_time,
sx_common_trigger_handler,
&sx_common_buffer_setup_ops);
if (ret)
return ret;
return devm_iio_device_register(dev, indio_dev);
}
EXPORT_SYMBOL_NS_GPL(sx_common_probe, SEMTECH_PROX);
MODULE_AUTHOR("Gwendal Grignou <[email protected]>");
MODULE_DESCRIPTION("Common functions and structures for Semtech sensor");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/proximity/sx_common.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2018 Google LLC.
*
* Driver for Semtech's SX9310/SX9311 capacitive proximity/button solution.
* Based on SX9500 driver and Semtech driver using the input framework
* <https://my.syncplicity.com/share/teouwsim8niiaud/
* linux-driver-SX9310_NoSmartHSensing>.
* Reworked in April 2019 by Evan Green <[email protected]>
* and in January 2020 by Daniel Campello <[email protected]>.
*/
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include "sx_common.h"
/* Register definitions. */
#define SX9310_REG_IRQ_SRC SX_COMMON_REG_IRQ_SRC
#define SX9310_REG_STAT0 0x01
#define SX9310_REG_STAT1 0x02
#define SX9310_REG_STAT1_COMPSTAT_MASK GENMASK(3, 0)
#define SX9310_REG_IRQ_MSK 0x03
#define SX9310_CONVDONE_IRQ BIT(3)
#define SX9310_FAR_IRQ BIT(5)
#define SX9310_CLOSE_IRQ BIT(6)
#define SX9310_REG_IRQ_FUNC 0x04
#define SX9310_REG_PROX_CTRL0 0x10
#define SX9310_REG_PROX_CTRL0_SENSOREN_MASK GENMASK(3, 0)
#define SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK GENMASK(7, 4)
#define SX9310_REG_PROX_CTRL0_SCANPERIOD_15MS 0x01
#define SX9310_REG_PROX_CTRL1 0x11
#define SX9310_REG_PROX_CTRL2 0x12
#define SX9310_REG_PROX_CTRL2_COMBMODE_MASK GENMASK(7, 6)
#define SX9310_REG_PROX_CTRL2_COMBMODE_CS0_CS1_CS2_CS3 (0x03 << 6)
#define SX9310_REG_PROX_CTRL2_COMBMODE_CS1_CS2 (0x02 << 6)
#define SX9310_REG_PROX_CTRL2_COMBMODE_CS0_CS1 (0x01 << 6)
#define SX9310_REG_PROX_CTRL2_COMBMODE_CS3 (0x00 << 6)
#define SX9310_REG_PROX_CTRL2_SHIELDEN_MASK GENMASK(3, 2)
#define SX9310_REG_PROX_CTRL2_SHIELDEN_DYNAMIC (0x01 << 2)
#define SX9310_REG_PROX_CTRL2_SHIELDEN_GROUND (0x02 << 2)
#define SX9310_REG_PROX_CTRL3 0x13
#define SX9310_REG_PROX_CTRL3_GAIN0_MASK GENMASK(3, 2)
#define SX9310_REG_PROX_CTRL3_GAIN0_X8 (0x03 << 2)
#define SX9310_REG_PROX_CTRL3_GAIN12_MASK GENMASK(1, 0)
#define SX9310_REG_PROX_CTRL3_GAIN12_X4 0x02
#define SX9310_REG_PROX_CTRL4 0x14
#define SX9310_REG_PROX_CTRL4_RESOLUTION_MASK GENMASK(2, 0)
#define SX9310_REG_PROX_CTRL4_RESOLUTION_FINEST 0x07
#define SX9310_REG_PROX_CTRL4_RESOLUTION_VERY_FINE 0x06
#define SX9310_REG_PROX_CTRL4_RESOLUTION_FINE 0x05
#define SX9310_REG_PROX_CTRL4_RESOLUTION_MEDIUM 0x04
#define SX9310_REG_PROX_CTRL4_RESOLUTION_MEDIUM_COARSE 0x03
#define SX9310_REG_PROX_CTRL4_RESOLUTION_COARSE 0x02
#define SX9310_REG_PROX_CTRL4_RESOLUTION_VERY_COARSE 0x01
#define SX9310_REG_PROX_CTRL4_RESOLUTION_COARSEST 0x00
#define SX9310_REG_PROX_CTRL5 0x15
#define SX9310_REG_PROX_CTRL5_RANGE_SMALL (0x03 << 6)
#define SX9310_REG_PROX_CTRL5_STARTUPSENS_MASK GENMASK(3, 2)
#define SX9310_REG_PROX_CTRL5_STARTUPSENS_CS1 (0x01 << 2)
#define SX9310_REG_PROX_CTRL5_RAWFILT_MASK GENMASK(1, 0)
#define SX9310_REG_PROX_CTRL5_RAWFILT_SHIFT 0
#define SX9310_REG_PROX_CTRL5_RAWFILT_1P25 0x02
#define SX9310_REG_PROX_CTRL6 0x16
#define SX9310_REG_PROX_CTRL6_AVGTHRESH_DEFAULT 0x20
#define SX9310_REG_PROX_CTRL7 0x17
#define SX9310_REG_PROX_CTRL7_AVGNEGFILT_2 (0x01 << 3)
#define SX9310_REG_PROX_CTRL7_AVGPOSFILT_MASK GENMASK(2, 0)
#define SX9310_REG_PROX_CTRL7_AVGPOSFILT_SHIFT 0
#define SX9310_REG_PROX_CTRL7_AVGPOSFILT_512 0x05
#define SX9310_REG_PROX_CTRL8 0x18
#define SX9310_REG_PROX_CTRL8_9_PTHRESH_MASK GENMASK(7, 3)
#define SX9310_REG_PROX_CTRL9 0x19
#define SX9310_REG_PROX_CTRL8_9_PTHRESH_28 (0x08 << 3)
#define SX9310_REG_PROX_CTRL8_9_PTHRESH_96 (0x11 << 3)
#define SX9310_REG_PROX_CTRL8_9_BODYTHRESH_900 0x03
#define SX9310_REG_PROX_CTRL8_9_BODYTHRESH_1500 0x05
#define SX9310_REG_PROX_CTRL10 0x1a
#define SX9310_REG_PROX_CTRL10_HYST_MASK GENMASK(5, 4)
#define SX9310_REG_PROX_CTRL10_HYST_6PCT (0x01 << 4)
#define SX9310_REG_PROX_CTRL10_CLOSE_DEBOUNCE_MASK GENMASK(3, 2)
#define SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_MASK GENMASK(1, 0)
#define SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_2 0x01
#define SX9310_REG_PROX_CTRL11 0x1b
#define SX9310_REG_PROX_CTRL12 0x1c
#define SX9310_REG_PROX_CTRL13 0x1d
#define SX9310_REG_PROX_CTRL14 0x1e
#define SX9310_REG_PROX_CTRL15 0x1f
#define SX9310_REG_PROX_CTRL16 0x20
#define SX9310_REG_PROX_CTRL17 0x21
#define SX9310_REG_PROX_CTRL18 0x22
#define SX9310_REG_PROX_CTRL19 0x23
#define SX9310_REG_SAR_CTRL0 0x2a
#define SX9310_REG_SAR_CTRL0_SARDEB_4_SAMPLES (0x02 << 5)
#define SX9310_REG_SAR_CTRL0_SARHYST_8 (0x02 << 3)
#define SX9310_REG_SAR_CTRL1 0x2b
/* Each increment of the slope register is 0.0078125. */
#define SX9310_REG_SAR_CTRL1_SLOPE(_hnslope) (_hnslope / 78125)
#define SX9310_REG_SAR_CTRL2 0x2c
#define SX9310_REG_SAR_CTRL2_SAROFFSET_DEFAULT 0x3c
#define SX9310_REG_SENSOR_SEL 0x30
#define SX9310_REG_USE_MSB 0x31
#define SX9310_REG_USE_LSB 0x32
#define SX9310_REG_AVG_MSB 0x33
#define SX9310_REG_AVG_LSB 0x34
#define SX9310_REG_DIFF_MSB 0x35
#define SX9310_REG_DIFF_LSB 0x36
#define SX9310_REG_OFFSET_MSB 0x37
#define SX9310_REG_OFFSET_LSB 0x38
#define SX9310_REG_SAR_MSB 0x39
#define SX9310_REG_SAR_LSB 0x3a
#define SX9310_REG_I2C_ADDR 0x40
#define SX9310_REG_PAUSE 0x41
#define SX9310_REG_WHOAMI 0x42
#define SX9310_WHOAMI_VALUE 0x01
#define SX9311_WHOAMI_VALUE 0x02
#define SX9310_REG_RESET 0x7f
/* 4 hardware channels, as defined in STAT0: COMB, CS2, CS1 and CS0. */
#define SX9310_NUM_CHANNELS 4
static_assert(SX9310_NUM_CHANNELS <= SX_COMMON_MAX_NUM_CHANNELS);
#define SX9310_NAMED_CHANNEL(idx, name) \
{ \
.type = IIO_PROXIMITY, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.info_mask_separate_available = \
BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
.info_mask_shared_by_all_available = \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.indexed = 1, \
.channel = idx, \
.extend_name = name, \
.address = SX9310_REG_DIFF_MSB, \
.event_spec = sx_common_events, \
.num_event_specs = ARRAY_SIZE(sx_common_events), \
.scan_index = idx, \
.scan_type = { \
.sign = 's', \
.realbits = 12, \
.storagebits = 16, \
.endianness = IIO_BE, \
}, \
}
#define SX9310_CHANNEL(idx) SX9310_NAMED_CHANNEL(idx, NULL)
static const struct iio_chan_spec sx9310_channels[] = {
SX9310_CHANNEL(0), /* CS0 */
SX9310_CHANNEL(1), /* CS1 */
SX9310_CHANNEL(2), /* CS2 */
SX9310_NAMED_CHANNEL(3, "comb"), /* COMB */
IIO_CHAN_SOFT_TIMESTAMP(4),
};
/*
* Each entry contains the integer part (val) and the fractional part, in micro
* seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO.
*/
static const struct {
int val;
int val2;
} sx9310_samp_freq_table[] = {
{ 500, 0 }, /* 0000: Min (no idle time) */
{ 66, 666666 }, /* 0001: 15 ms */
{ 33, 333333 }, /* 0010: 30 ms (Typ.) */
{ 22, 222222 }, /* 0011: 45 ms */
{ 16, 666666 }, /* 0100: 60 ms */
{ 11, 111111 }, /* 0101: 90 ms */
{ 8, 333333 }, /* 0110: 120 ms */
{ 5, 0 }, /* 0111: 200 ms */
{ 2, 500000 }, /* 1000: 400 ms */
{ 1, 666666 }, /* 1001: 600 ms */
{ 1, 250000 }, /* 1010: 800 ms */
{ 1, 0 }, /* 1011: 1 s */
{ 0, 500000 }, /* 1100: 2 s */
{ 0, 333333 }, /* 1101: 3 s */
{ 0, 250000 }, /* 1110: 4 s */
{ 0, 200000 }, /* 1111: 5 s */
};
static const unsigned int sx9310_scan_period_table[] = {
2, 15, 30, 45, 60, 90, 120, 200,
400, 600, 800, 1000, 2000, 3000, 4000, 5000,
};
static const struct regmap_range sx9310_writable_reg_ranges[] = {
regmap_reg_range(SX9310_REG_IRQ_MSK, SX9310_REG_IRQ_FUNC),
regmap_reg_range(SX9310_REG_PROX_CTRL0, SX9310_REG_PROX_CTRL19),
regmap_reg_range(SX9310_REG_SAR_CTRL0, SX9310_REG_SAR_CTRL2),
regmap_reg_range(SX9310_REG_SENSOR_SEL, SX9310_REG_SENSOR_SEL),
regmap_reg_range(SX9310_REG_OFFSET_MSB, SX9310_REG_OFFSET_LSB),
regmap_reg_range(SX9310_REG_PAUSE, SX9310_REG_PAUSE),
regmap_reg_range(SX9310_REG_RESET, SX9310_REG_RESET),
};
static const struct regmap_access_table sx9310_writeable_regs = {
.yes_ranges = sx9310_writable_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(sx9310_writable_reg_ranges),
};
static const struct regmap_range sx9310_readable_reg_ranges[] = {
regmap_reg_range(SX9310_REG_IRQ_SRC, SX9310_REG_IRQ_FUNC),
regmap_reg_range(SX9310_REG_PROX_CTRL0, SX9310_REG_PROX_CTRL19),
regmap_reg_range(SX9310_REG_SAR_CTRL0, SX9310_REG_SAR_CTRL2),
regmap_reg_range(SX9310_REG_SENSOR_SEL, SX9310_REG_SAR_LSB),
regmap_reg_range(SX9310_REG_I2C_ADDR, SX9310_REG_WHOAMI),
regmap_reg_range(SX9310_REG_RESET, SX9310_REG_RESET),
};
static const struct regmap_access_table sx9310_readable_regs = {
.yes_ranges = sx9310_readable_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(sx9310_readable_reg_ranges),
};
static const struct regmap_range sx9310_volatile_reg_ranges[] = {
regmap_reg_range(SX9310_REG_IRQ_SRC, SX9310_REG_STAT1),
regmap_reg_range(SX9310_REG_USE_MSB, SX9310_REG_DIFF_LSB),
regmap_reg_range(SX9310_REG_SAR_MSB, SX9310_REG_SAR_LSB),
regmap_reg_range(SX9310_REG_RESET, SX9310_REG_RESET),
};
static const struct regmap_access_table sx9310_volatile_regs = {
.yes_ranges = sx9310_volatile_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(sx9310_volatile_reg_ranges),
};
static const struct regmap_config sx9310_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = SX9310_REG_RESET,
.cache_type = REGCACHE_RBTREE,
.wr_table = &sx9310_writeable_regs,
.rd_table = &sx9310_readable_regs,
.volatile_table = &sx9310_volatile_regs,
};
static int sx9310_read_prox_data(struct sx_common_data *data,
const struct iio_chan_spec *chan, __be16 *val)
{
int ret;
ret = regmap_write(data->regmap, SX9310_REG_SENSOR_SEL, chan->channel);
if (ret)
return ret;
return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val));
}
/*
* If we have no interrupt support, we have to wait for a scan period
* after enabling a channel to get a result.
*/
static int sx9310_wait_for_sample(struct sx_common_data *data)
{
int ret;
unsigned int val;
ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &val);
if (ret)
return ret;
val = FIELD_GET(SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK, val);
msleep(sx9310_scan_period_table[val]);
return 0;
}
static int sx9310_read_gain(struct sx_common_data *data,
const struct iio_chan_spec *chan, int *val)
{
unsigned int regval, gain;
int ret;
ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL3, ®val);
if (ret)
return ret;
switch (chan->channel) {
case 0:
case 3:
gain = FIELD_GET(SX9310_REG_PROX_CTRL3_GAIN0_MASK, regval);
break;
case 1:
case 2:
gain = FIELD_GET(SX9310_REG_PROX_CTRL3_GAIN12_MASK, regval);
break;
default:
return -EINVAL;
}
*val = 1 << gain;
return IIO_VAL_INT;
}
static int sx9310_read_samp_freq(struct sx_common_data *data, int *val, int *val2)
{
unsigned int regval;
int ret;
ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK, regval);
*val = sx9310_samp_freq_table[regval].val;
*val2 = sx9310_samp_freq_table[regval].val2;
return IIO_VAL_INT_PLUS_MICRO;
}
static int sx9310_read_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, int *val,
int *val2, long mask)
{
struct sx_common_data *data = iio_priv(indio_dev);
int ret;
if (chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = sx_common_read_proximity(data, chan, val);
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_HARDWAREGAIN:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = sx9310_read_gain(data, chan, val);
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_SAMP_FREQ:
return sx9310_read_samp_freq(data, val, val2);
default:
return -EINVAL;
}
}
static const int sx9310_gain_vals[] = { 1, 2, 4, 8 };
static int sx9310_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
if (chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_HARDWAREGAIN:
*type = IIO_VAL_INT;
*length = ARRAY_SIZE(sx9310_gain_vals);
*vals = sx9310_gain_vals;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_SAMP_FREQ:
*type = IIO_VAL_INT_PLUS_MICRO;
*length = ARRAY_SIZE(sx9310_samp_freq_table) * 2;
*vals = (int *)sx9310_samp_freq_table;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static const unsigned int sx9310_pthresh_codes[] = {
2, 4, 6, 8, 12, 16, 20, 24, 28, 32, 40, 48, 56, 64, 72, 80, 88, 96, 112,
128, 144, 160, 192, 224, 256, 320, 384, 512, 640, 768, 1024, 1536
};
static int sx9310_get_thresh_reg(unsigned int channel)
{
switch (channel) {
case 0:
case 3:
return SX9310_REG_PROX_CTRL8;
case 1:
case 2:
return SX9310_REG_PROX_CTRL9;
default:
return -EINVAL;
}
}
static int sx9310_read_thresh(struct sx_common_data *data,
const struct iio_chan_spec *chan, int *val)
{
unsigned int reg;
unsigned int regval;
int ret;
reg = ret = sx9310_get_thresh_reg(chan->channel);
if (ret < 0)
return ret;
ret = regmap_read(data->regmap, reg, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9310_REG_PROX_CTRL8_9_PTHRESH_MASK, regval);
if (regval >= ARRAY_SIZE(sx9310_pthresh_codes))
return -EINVAL;
*val = sx9310_pthresh_codes[regval];
return IIO_VAL_INT;
}
static int sx9310_read_hysteresis(struct sx_common_data *data,
const struct iio_chan_spec *chan, int *val)
{
unsigned int regval, pthresh;
int ret;
ret = sx9310_read_thresh(data, chan, &pthresh);
if (ret < 0)
return ret;
ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL10, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9310_REG_PROX_CTRL10_HYST_MASK, regval);
if (!regval)
regval = 5;
/* regval is at most 5 */
*val = pthresh >> (5 - regval);
return IIO_VAL_INT;
}
static int sx9310_read_far_debounce(struct sx_common_data *data, int *val)
{
unsigned int regval;
int ret;
ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL10, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_MASK, regval);
if (regval)
*val = 1 << regval;
else
*val = 0;
return IIO_VAL_INT;
}
static int sx9310_read_close_debounce(struct sx_common_data *data, int *val)
{
unsigned int regval;
int ret;
ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL10, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9310_REG_PROX_CTRL10_CLOSE_DEBOUNCE_MASK, regval);
if (regval)
*val = 1 << regval;
else
*val = 0;
return IIO_VAL_INT;
}
static int sx9310_read_event_val(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int *val, int *val2)
{
struct sx_common_data *data = iio_priv(indio_dev);
if (chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (info) {
case IIO_EV_INFO_VALUE:
return sx9310_read_thresh(data, chan, val);
case IIO_EV_INFO_PERIOD:
switch (dir) {
case IIO_EV_DIR_RISING:
return sx9310_read_far_debounce(data, val);
case IIO_EV_DIR_FALLING:
return sx9310_read_close_debounce(data, val);
default:
return -EINVAL;
}
case IIO_EV_INFO_HYSTERESIS:
return sx9310_read_hysteresis(data, chan, val);
default:
return -EINVAL;
}
}
static int sx9310_write_thresh(struct sx_common_data *data,
const struct iio_chan_spec *chan, int val)
{
unsigned int reg;
unsigned int regval;
int ret, i;
reg = ret = sx9310_get_thresh_reg(chan->channel);
if (ret < 0)
return ret;
for (i = 0; i < ARRAY_SIZE(sx9310_pthresh_codes); i++) {
if (sx9310_pthresh_codes[i] == val) {
regval = i;
break;
}
}
if (i == ARRAY_SIZE(sx9310_pthresh_codes))
return -EINVAL;
regval = FIELD_PREP(SX9310_REG_PROX_CTRL8_9_PTHRESH_MASK, regval);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, reg,
SX9310_REG_PROX_CTRL8_9_PTHRESH_MASK, regval);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9310_write_hysteresis(struct sx_common_data *data,
const struct iio_chan_spec *chan, int _val)
{
unsigned int hyst, val = _val;
int ret, pthresh;
ret = sx9310_read_thresh(data, chan, &pthresh);
if (ret < 0)
return ret;
if (val == 0)
hyst = 0;
else if (val == pthresh >> 2)
hyst = 3;
else if (val == pthresh >> 3)
hyst = 2;
else if (val == pthresh >> 4)
hyst = 1;
else
return -EINVAL;
hyst = FIELD_PREP(SX9310_REG_PROX_CTRL10_HYST_MASK, hyst);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9310_REG_PROX_CTRL10,
SX9310_REG_PROX_CTRL10_HYST_MASK, hyst);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9310_write_far_debounce(struct sx_common_data *data, int val)
{
int ret;
unsigned int regval;
if (val > 0)
val = ilog2(val);
if (!FIELD_FIT(SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_MASK, val))
return -EINVAL;
regval = FIELD_PREP(SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_MASK, val);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9310_REG_PROX_CTRL10,
SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_MASK,
regval);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9310_write_close_debounce(struct sx_common_data *data, int val)
{
int ret;
unsigned int regval;
if (val > 0)
val = ilog2(val);
if (!FIELD_FIT(SX9310_REG_PROX_CTRL10_CLOSE_DEBOUNCE_MASK, val))
return -EINVAL;
regval = FIELD_PREP(SX9310_REG_PROX_CTRL10_CLOSE_DEBOUNCE_MASK, val);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9310_REG_PROX_CTRL10,
SX9310_REG_PROX_CTRL10_CLOSE_DEBOUNCE_MASK,
regval);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9310_write_event_val(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int val, int val2)
{
struct sx_common_data *data = iio_priv(indio_dev);
if (chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (info) {
case IIO_EV_INFO_VALUE:
return sx9310_write_thresh(data, chan, val);
case IIO_EV_INFO_PERIOD:
switch (dir) {
case IIO_EV_DIR_RISING:
return sx9310_write_far_debounce(data, val);
case IIO_EV_DIR_FALLING:
return sx9310_write_close_debounce(data, val);
default:
return -EINVAL;
}
case IIO_EV_INFO_HYSTERESIS:
return sx9310_write_hysteresis(data, chan, val);
default:
return -EINVAL;
}
}
static int sx9310_set_samp_freq(struct sx_common_data *data, int val, int val2)
{
int i, ret;
for (i = 0; i < ARRAY_SIZE(sx9310_samp_freq_table); i++)
if (val == sx9310_samp_freq_table[i].val &&
val2 == sx9310_samp_freq_table[i].val2)
break;
if (i == ARRAY_SIZE(sx9310_samp_freq_table))
return -EINVAL;
mutex_lock(&data->mutex);
ret = regmap_update_bits(
data->regmap, SX9310_REG_PROX_CTRL0,
SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK,
FIELD_PREP(SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK, i));
mutex_unlock(&data->mutex);
return ret;
}
static int sx9310_write_gain(struct sx_common_data *data,
const struct iio_chan_spec *chan, int val)
{
unsigned int gain, mask;
int ret;
gain = ilog2(val);
switch (chan->channel) {
case 0:
case 3:
mask = SX9310_REG_PROX_CTRL3_GAIN0_MASK;
gain = FIELD_PREP(SX9310_REG_PROX_CTRL3_GAIN0_MASK, gain);
break;
case 1:
case 2:
mask = SX9310_REG_PROX_CTRL3_GAIN12_MASK;
gain = FIELD_PREP(SX9310_REG_PROX_CTRL3_GAIN12_MASK, gain);
break;
default:
return -EINVAL;
}
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9310_REG_PROX_CTRL3, mask,
gain);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9310_write_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, int val, int val2,
long mask)
{
struct sx_common_data *data = iio_priv(indio_dev);
if (chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
return sx9310_set_samp_freq(data, val, val2);
case IIO_CHAN_INFO_HARDWAREGAIN:
return sx9310_write_gain(data, chan, val);
default:
return -EINVAL;
}
}
static const struct sx_common_reg_default sx9310_default_regs[] = {
{ SX9310_REG_IRQ_MSK, 0x00 },
{ SX9310_REG_IRQ_FUNC, 0x00 },
/*
* The lower 4 bits should not be set as it enable sensors measurements.
* Turning the detection on before the configuration values are set to
* good values can cause the device to return erroneous readings.
*/
{ SX9310_REG_PROX_CTRL0, SX9310_REG_PROX_CTRL0_SCANPERIOD_15MS },
{ SX9310_REG_PROX_CTRL1, 0x00 },
{ SX9310_REG_PROX_CTRL2, SX9310_REG_PROX_CTRL2_COMBMODE_CS1_CS2 |
SX9310_REG_PROX_CTRL2_SHIELDEN_DYNAMIC },
{ SX9310_REG_PROX_CTRL3, SX9310_REG_PROX_CTRL3_GAIN0_X8 |
SX9310_REG_PROX_CTRL3_GAIN12_X4 },
{ SX9310_REG_PROX_CTRL4, SX9310_REG_PROX_CTRL4_RESOLUTION_FINEST },
{ SX9310_REG_PROX_CTRL5, SX9310_REG_PROX_CTRL5_RANGE_SMALL |
SX9310_REG_PROX_CTRL5_STARTUPSENS_CS1 |
SX9310_REG_PROX_CTRL5_RAWFILT_1P25 },
{ SX9310_REG_PROX_CTRL6, SX9310_REG_PROX_CTRL6_AVGTHRESH_DEFAULT },
{ SX9310_REG_PROX_CTRL7, SX9310_REG_PROX_CTRL7_AVGNEGFILT_2 |
SX9310_REG_PROX_CTRL7_AVGPOSFILT_512 },
{ SX9310_REG_PROX_CTRL8, SX9310_REG_PROX_CTRL8_9_PTHRESH_96 |
SX9310_REG_PROX_CTRL8_9_BODYTHRESH_1500 },
{ SX9310_REG_PROX_CTRL9, SX9310_REG_PROX_CTRL8_9_PTHRESH_28 |
SX9310_REG_PROX_CTRL8_9_BODYTHRESH_900 },
{ SX9310_REG_PROX_CTRL10, SX9310_REG_PROX_CTRL10_HYST_6PCT |
SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_2 },
{ SX9310_REG_PROX_CTRL11, 0x00 },
{ SX9310_REG_PROX_CTRL12, 0x00 },
{ SX9310_REG_PROX_CTRL13, 0x00 },
{ SX9310_REG_PROX_CTRL14, 0x00 },
{ SX9310_REG_PROX_CTRL15, 0x00 },
{ SX9310_REG_PROX_CTRL16, 0x00 },
{ SX9310_REG_PROX_CTRL17, 0x00 },
{ SX9310_REG_PROX_CTRL18, 0x00 },
{ SX9310_REG_PROX_CTRL19, 0x00 },
{ SX9310_REG_SAR_CTRL0, SX9310_REG_SAR_CTRL0_SARDEB_4_SAMPLES |
SX9310_REG_SAR_CTRL0_SARHYST_8 },
{ SX9310_REG_SAR_CTRL1, SX9310_REG_SAR_CTRL1_SLOPE(10781250) },
{ SX9310_REG_SAR_CTRL2, SX9310_REG_SAR_CTRL2_SAROFFSET_DEFAULT },
};
/* Activate all channels and perform an initial compensation. */
static int sx9310_init_compensation(struct iio_dev *indio_dev)
{
struct sx_common_data *data = iio_priv(indio_dev);
int ret;
unsigned int val;
unsigned int ctrl0;
ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &ctrl0);
if (ret)
return ret;
/* run the compensation phase on all channels */
ret = regmap_write(data->regmap, SX9310_REG_PROX_CTRL0,
ctrl0 | SX9310_REG_PROX_CTRL0_SENSOREN_MASK);
if (ret)
return ret;
ret = regmap_read_poll_timeout(data->regmap, SX9310_REG_STAT1, val,
!(val & SX9310_REG_STAT1_COMPSTAT_MASK),
20000, 2000000);
if (ret)
return ret;
regmap_write(data->regmap, SX9310_REG_PROX_CTRL0, ctrl0);
return ret;
}
static const struct sx_common_reg_default *
sx9310_get_default_reg(struct device *dev, int idx,
struct sx_common_reg_default *reg_def)
{
u32 combined[SX9310_NUM_CHANNELS];
u32 start = 0, raw = 0, pos = 0;
unsigned long comb_mask = 0;
int ret, i, count;
const char *res;
memcpy(reg_def, &sx9310_default_regs[idx], sizeof(*reg_def));
switch (reg_def->reg) {
case SX9310_REG_PROX_CTRL2:
if (device_property_read_bool(dev, "semtech,cs0-ground")) {
reg_def->def &= ~SX9310_REG_PROX_CTRL2_SHIELDEN_MASK;
reg_def->def |= SX9310_REG_PROX_CTRL2_SHIELDEN_GROUND;
}
count = device_property_count_u32(dev, "semtech,combined-sensors");
if (count < 0 || count > ARRAY_SIZE(combined))
break;
ret = device_property_read_u32_array(dev, "semtech,combined-sensors",
combined, count);
if (ret)
break;
for (i = 0; i < count; i++)
comb_mask |= BIT(combined[i]);
reg_def->def &= ~SX9310_REG_PROX_CTRL2_COMBMODE_MASK;
if (comb_mask == (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
reg_def->def |= SX9310_REG_PROX_CTRL2_COMBMODE_CS0_CS1_CS2_CS3;
else if (comb_mask == (BIT(1) | BIT(2)))
reg_def->def |= SX9310_REG_PROX_CTRL2_COMBMODE_CS1_CS2;
else if (comb_mask == (BIT(0) | BIT(1)))
reg_def->def |= SX9310_REG_PROX_CTRL2_COMBMODE_CS0_CS1;
else if (comb_mask == BIT(3))
reg_def->def |= SX9310_REG_PROX_CTRL2_COMBMODE_CS3;
break;
case SX9310_REG_PROX_CTRL4:
ret = device_property_read_string(dev, "semtech,resolution", &res);
if (ret)
break;
reg_def->def &= ~SX9310_REG_PROX_CTRL4_RESOLUTION_MASK;
if (!strcmp(res, "coarsest"))
reg_def->def |= SX9310_REG_PROX_CTRL4_RESOLUTION_COARSEST;
else if (!strcmp(res, "very-coarse"))
reg_def->def |= SX9310_REG_PROX_CTRL4_RESOLUTION_VERY_COARSE;
else if (!strcmp(res, "coarse"))
reg_def->def |= SX9310_REG_PROX_CTRL4_RESOLUTION_COARSE;
else if (!strcmp(res, "medium-coarse"))
reg_def->def |= SX9310_REG_PROX_CTRL4_RESOLUTION_MEDIUM_COARSE;
else if (!strcmp(res, "medium"))
reg_def->def |= SX9310_REG_PROX_CTRL4_RESOLUTION_MEDIUM;
else if (!strcmp(res, "fine"))
reg_def->def |= SX9310_REG_PROX_CTRL4_RESOLUTION_FINE;
else if (!strcmp(res, "very-fine"))
reg_def->def |= SX9310_REG_PROX_CTRL4_RESOLUTION_VERY_FINE;
else if (!strcmp(res, "finest"))
reg_def->def |= SX9310_REG_PROX_CTRL4_RESOLUTION_FINEST;
break;
case SX9310_REG_PROX_CTRL5:
ret = device_property_read_u32(dev, "semtech,startup-sensor", &start);
if (ret) {
start = FIELD_GET(SX9310_REG_PROX_CTRL5_STARTUPSENS_MASK,
reg_def->def);
}
reg_def->def &= ~SX9310_REG_PROX_CTRL5_STARTUPSENS_MASK;
reg_def->def |= FIELD_PREP(SX9310_REG_PROX_CTRL5_STARTUPSENS_MASK,
start);
ret = device_property_read_u32(dev, "semtech,proxraw-strength", &raw);
if (ret) {
raw = FIELD_GET(SX9310_REG_PROX_CTRL5_RAWFILT_MASK,
reg_def->def);
} else {
raw = ilog2(raw);
}
reg_def->def &= ~SX9310_REG_PROX_CTRL5_RAWFILT_MASK;
reg_def->def |= FIELD_PREP(SX9310_REG_PROX_CTRL5_RAWFILT_MASK,
raw);
break;
case SX9310_REG_PROX_CTRL7:
ret = device_property_read_u32(dev, "semtech,avg-pos-strength", &pos);
if (ret)
break;
/* Powers of 2, except for a gap between 16 and 64 */
pos = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3);
reg_def->def &= ~SX9310_REG_PROX_CTRL7_AVGPOSFILT_MASK;
reg_def->def |= FIELD_PREP(SX9310_REG_PROX_CTRL7_AVGPOSFILT_MASK,
pos);
break;
}
return reg_def;
}
static int sx9310_check_whoami(struct device *dev,
struct iio_dev *indio_dev)
{
struct sx_common_data *data = iio_priv(indio_dev);
unsigned int long ddata;
unsigned int whoami;
int ret;
ret = regmap_read(data->regmap, SX9310_REG_WHOAMI, &whoami);
if (ret)
return ret;
ddata = (uintptr_t)device_get_match_data(dev);
if (ddata != whoami)
return -EINVAL;
switch (whoami) {
case SX9310_WHOAMI_VALUE:
indio_dev->name = "sx9310";
break;
case SX9311_WHOAMI_VALUE:
indio_dev->name = "sx9311";
break;
default:
return -ENODEV;
}
return 0;
}
static const struct sx_common_chip_info sx9310_chip_info = {
.reg_stat = SX9310_REG_STAT0,
.reg_irq_msk = SX9310_REG_IRQ_MSK,
.reg_enable_chan = SX9310_REG_PROX_CTRL0,
.reg_reset = SX9310_REG_RESET,
.mask_enable_chan = SX9310_REG_STAT1_COMPSTAT_MASK,
.irq_msk_offset = 3,
.num_channels = SX9310_NUM_CHANNELS,
.num_default_regs = ARRAY_SIZE(sx9310_default_regs),
.ops = {
.read_prox_data = sx9310_read_prox_data,
.check_whoami = sx9310_check_whoami,
.init_compensation = sx9310_init_compensation,
.wait_for_sample = sx9310_wait_for_sample,
.get_default_reg = sx9310_get_default_reg,
},
.iio_channels = sx9310_channels,
.num_iio_channels = ARRAY_SIZE(sx9310_channels),
.iio_info = {
.read_raw = sx9310_read_raw,
.read_avail = sx9310_read_avail,
.read_event_value = sx9310_read_event_val,
.write_event_value = sx9310_write_event_val,
.write_raw = sx9310_write_raw,
.read_event_config = sx_common_read_event_config,
.write_event_config = sx_common_write_event_config,
},
};
static int sx9310_probe(struct i2c_client *client)
{
return sx_common_probe(client, &sx9310_chip_info, &sx9310_regmap_config);
}
static int sx9310_suspend(struct device *dev)
{
struct sx_common_data *data = iio_priv(dev_get_drvdata(dev));
u8 ctrl0;
int ret;
disable_irq_nosync(data->client->irq);
mutex_lock(&data->mutex);
ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0,
&data->suspend_ctrl);
if (ret)
goto out;
ctrl0 = data->suspend_ctrl & ~SX9310_REG_PROX_CTRL0_SENSOREN_MASK;
ret = regmap_write(data->regmap, SX9310_REG_PROX_CTRL0, ctrl0);
if (ret)
goto out;
ret = regmap_write(data->regmap, SX9310_REG_PAUSE, 0);
out:
mutex_unlock(&data->mutex);
return ret;
}
static int sx9310_resume(struct device *dev)
{
struct sx_common_data *data = iio_priv(dev_get_drvdata(dev));
int ret;
mutex_lock(&data->mutex);
ret = regmap_write(data->regmap, SX9310_REG_PAUSE, 1);
if (ret)
goto out;
ret = regmap_write(data->regmap, SX9310_REG_PROX_CTRL0,
data->suspend_ctrl);
out:
mutex_unlock(&data->mutex);
if (ret)
return ret;
enable_irq(data->client->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(sx9310_pm_ops, sx9310_suspend, sx9310_resume);
static const struct acpi_device_id sx9310_acpi_match[] = {
{ "STH9310", SX9310_WHOAMI_VALUE },
{ "STH9311", SX9311_WHOAMI_VALUE },
{}
};
MODULE_DEVICE_TABLE(acpi, sx9310_acpi_match);
static const struct of_device_id sx9310_of_match[] = {
{ .compatible = "semtech,sx9310", (void *)SX9310_WHOAMI_VALUE },
{ .compatible = "semtech,sx9311", (void *)SX9311_WHOAMI_VALUE },
{}
};
MODULE_DEVICE_TABLE(of, sx9310_of_match);
static const struct i2c_device_id sx9310_id[] = {
{ "sx9310", SX9310_WHOAMI_VALUE },
{ "sx9311", SX9311_WHOAMI_VALUE },
{}
};
MODULE_DEVICE_TABLE(i2c, sx9310_id);
static struct i2c_driver sx9310_driver = {
.driver = {
.name = "sx9310",
.acpi_match_table = sx9310_acpi_match,
.of_match_table = sx9310_of_match,
.pm = pm_sleep_ptr(&sx9310_pm_ops),
/*
* Lots of i2c transfers in probe + over 200 ms waiting in
* sx9310_init_compensation() mean a slow probe; prefer async
* so we don't delay boot if we're builtin to the kernel.
*/
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
.probe = sx9310_probe,
.id_table = sx9310_id,
};
module_i2c_driver(sx9310_driver);
MODULE_AUTHOR("Gwendal Grignou <[email protected]>");
MODULE_AUTHOR("Daniel Campello <[email protected]>");
MODULE_DESCRIPTION("Driver for Semtech SX9310/SX9311 proximity sensor");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(SEMTECH_PROX);
| linux-master | drivers/iio/proximity/sx9310.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Support for Vishay VCNL3020 proximity sensor on i2c bus.
* Based on Vishay VCNL4000 driver code.
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/interrupt.h>
#include <linux/iio/iio.h>
#include <linux/iio/events.h>
#define VCNL3020_PROD_ID 0x21
#define VCNL_COMMAND 0x80 /* Command register */
#define VCNL_PROD_REV 0x81 /* Product ID and Revision ID */
#define VCNL_PROXIMITY_RATE 0x82 /* Rate of Proximity Measurement */
#define VCNL_LED_CURRENT 0x83 /* IR LED current for proximity mode */
#define VCNL_PS_RESULT_HI 0x87 /* Proximity result register, MSB */
#define VCNL_PS_RESULT_LO 0x88 /* Proximity result register, LSB */
#define VCNL_PS_ICR 0x89 /* Interrupt Control Register */
#define VCNL_PS_LO_THR_HI 0x8a /* High byte of low threshold value */
#define VCNL_PS_LO_THR_LO 0x8b /* Low byte of low threshold value */
#define VCNL_PS_HI_THR_HI 0x8c /* High byte of high threshold value */
#define VCNL_PS_HI_THR_LO 0x8d /* Low byte of high threshold value */
#define VCNL_ISR 0x8e /* Interrupt Status Register */
#define VCNL_PS_MOD_ADJ 0x8f /* Proximity Modulator Timing Adjustment */
/* Bit masks for COMMAND register */
#define VCNL_PS_RDY BIT(5) /* proximity data ready? */
#define VCNL_PS_OD BIT(3) /* start on-demand proximity
* measurement
*/
/* Enables periodic proximity measurement */
#define VCNL_PS_EN BIT(1)
/* Enables state machine and LP oscillator for self timed measurements */
#define VCNL_PS_SELFTIMED_EN BIT(0)
/* Bit masks for ICR */
/* Enable interrupts on low or high thresholds */
#define VCNL_ICR_THRES_EN BIT(1)
/* Bit masks for ISR */
#define VCNL_INT_TH_HI BIT(0) /* High threshold hit */
#define VCNL_INT_TH_LOW BIT(1) /* Low threshold hit */
#define VCNL_ON_DEMAND_TIMEOUT_US 100000
#define VCNL_POLL_US 20000
static const int vcnl3020_prox_sampling_frequency[][2] = {
{1, 950000},
{3, 906250},
{7, 812500},
{16, 625000},
{31, 250000},
{62, 500000},
{125, 0},
{250, 0},
};
/**
* struct vcnl3020_data - vcnl3020 specific data.
* @regmap: device register map.
* @dev: vcnl3020 device.
* @rev: revision id.
* @lock: lock for protecting access to device hardware registers.
* @buf: __be16 buffer.
*/
struct vcnl3020_data {
struct regmap *regmap;
struct device *dev;
u8 rev;
struct mutex lock;
__be16 buf;
};
/**
* struct vcnl3020_property - vcnl3020 property.
* @name: property name.
* @reg: i2c register offset.
* @conversion_func: conversion function.
*/
struct vcnl3020_property {
const char *name;
u32 reg;
u32 (*conversion_func)(u32 *val);
};
static u32 microamp_to_reg(u32 *val)
{
/*
* An example of conversion from uA to reg val:
* 200000 uA == 200 mA == 20
*/
return *val /= 10000;
};
static struct vcnl3020_property vcnl3020_led_current_property = {
.name = "vishay,led-current-microamp",
.reg = VCNL_LED_CURRENT,
.conversion_func = microamp_to_reg,
};
static int vcnl3020_get_and_apply_property(struct vcnl3020_data *data,
struct vcnl3020_property prop)
{
int rc;
u32 val;
rc = device_property_read_u32(data->dev, prop.name, &val);
if (rc)
return 0;
if (prop.conversion_func)
prop.conversion_func(&val);
rc = regmap_write(data->regmap, prop.reg, val);
if (rc) {
dev_err(data->dev, "Error (%d) setting property (%s)\n",
rc, prop.name);
}
return rc;
}
static int vcnl3020_init(struct vcnl3020_data *data)
{
int rc;
unsigned int reg;
rc = regmap_read(data->regmap, VCNL_PROD_REV, ®);
if (rc) {
dev_err(data->dev,
"Error (%d) reading product revision\n", rc);
return rc;
}
if (reg != VCNL3020_PROD_ID) {
dev_err(data->dev,
"Product id (%x) did not match vcnl3020 (%x)\n", reg,
VCNL3020_PROD_ID);
return -ENODEV;
}
data->rev = reg;
mutex_init(&data->lock);
return vcnl3020_get_and_apply_property(data,
vcnl3020_led_current_property);
};
static bool vcnl3020_is_in_periodic_mode(struct vcnl3020_data *data)
{
int rc;
unsigned int cmd;
rc = regmap_read(data->regmap, VCNL_COMMAND, &cmd);
if (rc) {
dev_err(data->dev,
"Error (%d) reading command register\n", rc);
return false;
}
return !!(cmd & VCNL_PS_SELFTIMED_EN);
}
static int vcnl3020_measure_proximity(struct vcnl3020_data *data, int *val)
{
int rc;
unsigned int reg;
mutex_lock(&data->lock);
/* Protect against event capture. */
if (vcnl3020_is_in_periodic_mode(data)) {
rc = -EBUSY;
goto err_unlock;
}
rc = regmap_write(data->regmap, VCNL_COMMAND, VCNL_PS_OD);
if (rc)
goto err_unlock;
/* wait for data to become ready */
rc = regmap_read_poll_timeout(data->regmap, VCNL_COMMAND, reg,
reg & VCNL_PS_RDY, VCNL_POLL_US,
VCNL_ON_DEMAND_TIMEOUT_US);
if (rc) {
dev_err(data->dev,
"Error (%d) reading vcnl3020 command register\n", rc);
goto err_unlock;
}
/* high & low result bytes read */
rc = regmap_bulk_read(data->regmap, VCNL_PS_RESULT_HI, &data->buf,
sizeof(data->buf));
if (rc)
goto err_unlock;
*val = be16_to_cpu(data->buf);
err_unlock:
mutex_unlock(&data->lock);
return rc;
}
static int vcnl3020_read_proxy_samp_freq(struct vcnl3020_data *data, int *val,
int *val2)
{
int rc;
unsigned int prox_rate;
rc = regmap_read(data->regmap, VCNL_PROXIMITY_RATE, &prox_rate);
if (rc)
return rc;
if (prox_rate >= ARRAY_SIZE(vcnl3020_prox_sampling_frequency))
return -EINVAL;
*val = vcnl3020_prox_sampling_frequency[prox_rate][0];
*val2 = vcnl3020_prox_sampling_frequency[prox_rate][1];
return 0;
}
static int vcnl3020_write_proxy_samp_freq(struct vcnl3020_data *data, int val,
int val2)
{
unsigned int i;
int index = -1;
int rc;
mutex_lock(&data->lock);
/* Protect against event capture. */
if (vcnl3020_is_in_periodic_mode(data)) {
rc = -EBUSY;
goto err_unlock;
}
for (i = 0; i < ARRAY_SIZE(vcnl3020_prox_sampling_frequency); i++) {
if (val == vcnl3020_prox_sampling_frequency[i][0] &&
val2 == vcnl3020_prox_sampling_frequency[i][1]) {
index = i;
break;
}
}
if (index < 0) {
rc = -EINVAL;
goto err_unlock;
}
rc = regmap_write(data->regmap, VCNL_PROXIMITY_RATE, index);
if (rc)
dev_err(data->dev,
"Error (%d) writing proximity rate register\n", rc);
err_unlock:
mutex_unlock(&data->lock);
return rc;
}
static bool vcnl3020_is_thr_enabled(struct vcnl3020_data *data)
{
int rc;
unsigned int icr;
rc = regmap_read(data->regmap, VCNL_PS_ICR, &icr);
if (rc) {
dev_err(data->dev,
"Error (%d) reading ICR register\n", rc);
return false;
}
return !!(icr & VCNL_ICR_THRES_EN);
}
static int vcnl3020_read_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
int rc;
struct vcnl3020_data *data = iio_priv(indio_dev);
switch (info) {
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
rc = regmap_bulk_read(data->regmap, VCNL_PS_HI_THR_HI,
&data->buf, sizeof(data->buf));
if (rc < 0)
return rc;
*val = be16_to_cpu(data->buf);
return IIO_VAL_INT;
case IIO_EV_DIR_FALLING:
rc = regmap_bulk_read(data->regmap, VCNL_PS_LO_THR_HI,
&data->buf, sizeof(data->buf));
if (rc < 0)
return rc;
*val = be16_to_cpu(data->buf);
return IIO_VAL_INT;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int vcnl3020_write_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
int rc;
struct vcnl3020_data *data = iio_priv(indio_dev);
mutex_lock(&data->lock);
switch (info) {
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
/* 16 bit word/ low * high */
data->buf = cpu_to_be16(val);
rc = regmap_bulk_write(data->regmap, VCNL_PS_HI_THR_HI,
&data->buf, sizeof(data->buf));
if (rc < 0)
goto err_unlock;
rc = IIO_VAL_INT;
goto err_unlock;
case IIO_EV_DIR_FALLING:
data->buf = cpu_to_be16(val);
rc = regmap_bulk_write(data->regmap, VCNL_PS_LO_THR_HI,
&data->buf, sizeof(data->buf));
if (rc < 0)
goto err_unlock;
rc = IIO_VAL_INT;
goto err_unlock;
default:
rc = -EINVAL;
goto err_unlock;
}
default:
rc = -EINVAL;
goto err_unlock;
}
err_unlock:
mutex_unlock(&data->lock);
return rc;
}
static int vcnl3020_enable_periodic(struct iio_dev *indio_dev,
struct vcnl3020_data *data)
{
int rc;
int cmd;
mutex_lock(&data->lock);
/* Enable periodic measurement of proximity data. */
cmd = VCNL_PS_EN | VCNL_PS_SELFTIMED_EN;
rc = regmap_write(data->regmap, VCNL_COMMAND, cmd);
if (rc) {
dev_err(data->dev,
"Error (%d) writing command register\n", rc);
goto err_unlock;
}
/*
* Enable interrupts on threshold, for proximity data by
* default.
*/
rc = regmap_write(data->regmap, VCNL_PS_ICR, VCNL_ICR_THRES_EN);
if (rc)
dev_err(data->dev,
"Error (%d) reading ICR register\n", rc);
err_unlock:
mutex_unlock(&data->lock);
return rc;
}
static int vcnl3020_disable_periodic(struct iio_dev *indio_dev,
struct vcnl3020_data *data)
{
int rc;
mutex_lock(&data->lock);
rc = regmap_write(data->regmap, VCNL_COMMAND, 0);
if (rc) {
dev_err(data->dev,
"Error (%d) writing command register\n", rc);
goto err_unlock;
}
rc = regmap_write(data->regmap, VCNL_PS_ICR, 0);
if (rc) {
dev_err(data->dev,
"Error (%d) writing ICR register\n", rc);
goto err_unlock;
}
/* Clear interrupt flag bit */
rc = regmap_write(data->regmap, VCNL_ISR, 0);
if (rc)
dev_err(data->dev,
"Error (%d) writing ISR register\n", rc);
err_unlock:
mutex_unlock(&data->lock);
return rc;
}
static int vcnl3020_config_threshold(struct iio_dev *indio_dev, bool state)
{
struct vcnl3020_data *data = iio_priv(indio_dev);
if (state) {
return vcnl3020_enable_periodic(indio_dev, data);
} else {
if (!vcnl3020_is_thr_enabled(data))
return 0;
return vcnl3020_disable_periodic(indio_dev, data);
}
}
static int vcnl3020_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
switch (chan->type) {
case IIO_PROXIMITY:
return vcnl3020_config_threshold(indio_dev, state);
default:
return -EINVAL;
}
}
static int vcnl3020_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct vcnl3020_data *data = iio_priv(indio_dev);
switch (chan->type) {
case IIO_PROXIMITY:
return vcnl3020_is_thr_enabled(data);
default:
return -EINVAL;
}
}
static const struct iio_event_spec vcnl3020_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec vcnl3020_channels[] = {
{
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.event_spec = vcnl3020_event_spec,
.num_event_specs = ARRAY_SIZE(vcnl3020_event_spec),
},
};
static int vcnl3020_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
int rc;
struct vcnl3020_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
rc = vcnl3020_measure_proximity(data, val);
if (rc)
return rc;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SAMP_FREQ:
rc = vcnl3020_read_proxy_samp_freq(data, val, val2);
if (rc < 0)
return rc;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int vcnl3020_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct vcnl3020_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
return vcnl3020_write_proxy_samp_freq(data, val, val2);
default:
return -EINVAL;
}
}
static int vcnl3020_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
*vals = (int *)vcnl3020_prox_sampling_frequency;
*type = IIO_VAL_INT_PLUS_MICRO;
*length = 2 * ARRAY_SIZE(vcnl3020_prox_sampling_frequency);
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static const struct iio_info vcnl3020_info = {
.read_raw = vcnl3020_read_raw,
.write_raw = vcnl3020_write_raw,
.read_avail = vcnl3020_read_avail,
.read_event_value = vcnl3020_read_event,
.write_event_value = vcnl3020_write_event,
.read_event_config = vcnl3020_read_event_config,
.write_event_config = vcnl3020_write_event_config,
};
static const struct regmap_config vcnl3020_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = VCNL_PS_MOD_ADJ,
};
static irqreturn_t vcnl3020_handle_irq_thread(int irq, void *p)
{
struct iio_dev *indio_dev = p;
struct vcnl3020_data *data = iio_priv(indio_dev);
unsigned int isr;
int rc;
rc = regmap_read(data->regmap, VCNL_ISR, &isr);
if (rc) {
dev_err(data->dev, "Error (%d) reading reg (0x%x)\n",
rc, VCNL_ISR);
return IRQ_HANDLED;
}
if (!(isr & VCNL_ICR_THRES_EN))
return IRQ_NONE;
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 1,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
rc = regmap_write(data->regmap, VCNL_ISR, isr & VCNL_ICR_THRES_EN);
if (rc)
dev_err(data->dev, "Error (%d) writing in reg (0x%x)\n",
rc, VCNL_ISR);
return IRQ_HANDLED;
}
static int vcnl3020_probe(struct i2c_client *client)
{
struct vcnl3020_data *data;
struct iio_dev *indio_dev;
struct regmap *regmap;
int rc;
regmap = devm_regmap_init_i2c(client, &vcnl3020_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "regmap_init failed\n");
return PTR_ERR(regmap);
}
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->regmap = regmap;
data->dev = &client->dev;
rc = vcnl3020_init(data);
if (rc)
return rc;
indio_dev->info = &vcnl3020_info;
indio_dev->channels = vcnl3020_channels;
indio_dev->num_channels = ARRAY_SIZE(vcnl3020_channels);
indio_dev->name = "vcnl3020";
indio_dev->modes = INDIO_DIRECT_MODE;
if (client->irq) {
rc = devm_request_threaded_irq(&client->dev, client->irq,
NULL, vcnl3020_handle_irq_thread,
IRQF_ONESHOT, indio_dev->name,
indio_dev);
if (rc) {
dev_err(&client->dev,
"Error (%d) irq request failed (%u)\n", rc,
client->irq);
return rc;
}
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct of_device_id vcnl3020_of_match[] = {
{
.compatible = "vishay,vcnl3020",
},
{}
};
MODULE_DEVICE_TABLE(of, vcnl3020_of_match);
static struct i2c_driver vcnl3020_driver = {
.driver = {
.name = "vcnl3020",
.of_match_table = vcnl3020_of_match,
},
.probe = vcnl3020_probe,
};
module_i2c_driver(vcnl3020_driver);
MODULE_AUTHOR("Ivan Mikhaylov <[email protected]>");
MODULE_DESCRIPTION("Vishay VCNL3020 proximity sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/proximity/vcnl3020.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* PING: ultrasonic sensor for distance measuring by using only one GPIOs
*
* Copyright (c) 2019 Andreas Klinger <[email protected]>
*
* For details about the devices see:
* http://parallax.com/sites/default/files/downloads/28041-LaserPING-2m-Rangefinder-Guide.pdf
* http://parallax.com/sites/default/files/downloads/28015-PING-Documentation-v1.6.pdf
*
* the measurement cycle as timing diagram looks like:
*
* GPIO ___ ________________________
* ping: __/ \____________/ \________________
* ^ ^ ^ ^
* |<->| interrupt interrupt
* udelay(5) (ts_rising) (ts_falling)
* |<---------------------->|
* . pulse time measured .
* . --> one round trip of ultra sonic waves
* ultra . .
* sonic _ _ _. .
* burst: _________/ \_/ \_/ \_________________________________________
* .
* ultra .
* sonic _ _ _.
* echo: __________________________________/ \_/ \_/ \________________
*/
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
struct ping_cfg {
unsigned long trigger_pulse_us; /* length of trigger pulse */
int laserping_error; /* support error code in */
/* pulse width of laser */
/* ping sensors */
s64 timeout_ns; /* timeout in ns */
};
struct ping_data {
struct device *dev;
struct gpio_desc *gpiod_ping;
struct mutex lock;
int irqnr;
ktime_t ts_rising;
ktime_t ts_falling;
struct completion rising;
struct completion falling;
const struct ping_cfg *cfg;
};
static const struct ping_cfg pa_ping_cfg = {
.trigger_pulse_us = 5,
.laserping_error = 0,
.timeout_ns = 18500000, /* 3 meters */
};
static const struct ping_cfg pa_laser_ping_cfg = {
.trigger_pulse_us = 5,
.laserping_error = 1,
.timeout_ns = 15500000, /* 2 meters plus error codes */
};
static irqreturn_t ping_handle_irq(int irq, void *dev_id)
{
struct iio_dev *indio_dev = dev_id;
struct ping_data *data = iio_priv(indio_dev);
ktime_t now = ktime_get();
if (gpiod_get_value(data->gpiod_ping)) {
data->ts_rising = now;
complete(&data->rising);
} else {
data->ts_falling = now;
complete(&data->falling);
}
return IRQ_HANDLED;
}
static int ping_read(struct iio_dev *indio_dev)
{
struct ping_data *data = iio_priv(indio_dev);
int ret;
ktime_t ktime_dt;
s64 dt_ns;
u32 time_ns, distance_mm;
struct platform_device *pdev = to_platform_device(data->dev);
/*
* just one read-echo-cycle can take place at a time
* ==> lock against concurrent reading calls
*/
mutex_lock(&data->lock);
reinit_completion(&data->rising);
reinit_completion(&data->falling);
gpiod_set_value(data->gpiod_ping, 1);
udelay(data->cfg->trigger_pulse_us);
gpiod_set_value(data->gpiod_ping, 0);
ret = gpiod_direction_input(data->gpiod_ping);
if (ret < 0) {
mutex_unlock(&data->lock);
return ret;
}
data->irqnr = gpiod_to_irq(data->gpiod_ping);
if (data->irqnr < 0) {
dev_err(data->dev, "gpiod_to_irq: %d\n", data->irqnr);
mutex_unlock(&data->lock);
return data->irqnr;
}
ret = request_irq(data->irqnr, ping_handle_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
pdev->name, indio_dev);
if (ret < 0) {
dev_err(data->dev, "request_irq: %d\n", ret);
mutex_unlock(&data->lock);
return ret;
}
/* it should not take more than 20 ms until echo is rising */
ret = wait_for_completion_killable_timeout(&data->rising, HZ/50);
if (ret < 0)
goto err_reset_direction;
else if (ret == 0) {
ret = -ETIMEDOUT;
goto err_reset_direction;
}
/* it cannot take more than 50 ms until echo is falling */
ret = wait_for_completion_killable_timeout(&data->falling, HZ/20);
if (ret < 0)
goto err_reset_direction;
else if (ret == 0) {
ret = -ETIMEDOUT;
goto err_reset_direction;
}
ktime_dt = ktime_sub(data->ts_falling, data->ts_rising);
free_irq(data->irqnr, indio_dev);
ret = gpiod_direction_output(data->gpiod_ping, GPIOD_OUT_LOW);
if (ret < 0) {
mutex_unlock(&data->lock);
return ret;
}
mutex_unlock(&data->lock);
dt_ns = ktime_to_ns(ktime_dt);
if (dt_ns > data->cfg->timeout_ns) {
dev_dbg(data->dev, "distance out of range: dt=%lldns\n",
dt_ns);
return -EIO;
}
time_ns = dt_ns;
/*
* read error code of laser ping sensor and give users chance to
* figure out error by using dynamic debugging
*/
if (data->cfg->laserping_error) {
if ((time_ns > 12500000) && (time_ns <= 13500000)) {
dev_dbg(data->dev, "target too close or to far\n");
return -EIO;
}
if ((time_ns > 13500000) && (time_ns <= 14500000)) {
dev_dbg(data->dev, "internal sensor error\n");
return -EIO;
}
if ((time_ns > 14500000) && (time_ns <= 15500000)) {
dev_dbg(data->dev, "internal sensor timeout\n");
return -EIO;
}
}
/*
* the speed as function of the temperature is approximately:
*
* speed = 331,5 + 0,6 * Temp
* with Temp in °C
* and speed in m/s
*
* use 343,5 m/s as ultrasonic speed at 20 °C here in absence of the
* temperature
*
* therefore:
* time 343,5 time * 232
* distance = ------ * ------- = ------------
* 10^6 2 1350800
* with time in ns
* and distance in mm (one way)
*
* because we limit to 3 meters the multiplication with 232 just
* fits into 32 bit
*/
distance_mm = time_ns * 232 / 1350800;
return distance_mm;
err_reset_direction:
free_irq(data->irqnr, indio_dev);
mutex_unlock(&data->lock);
if (gpiod_direction_output(data->gpiod_ping, GPIOD_OUT_LOW))
dev_dbg(data->dev, "error in gpiod_direction_output\n");
return ret;
}
static int ping_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long info)
{
int ret;
if (channel->type != IIO_DISTANCE)
return -EINVAL;
switch (info) {
case IIO_CHAN_INFO_RAW:
ret = ping_read(indio_dev);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/*
* maximum resolution in datasheet is 1 mm
* 1 LSB is 1 mm
*/
*val = 0;
*val2 = 1000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static const struct iio_info ping_iio_info = {
.read_raw = ping_read_raw,
};
static const struct iio_chan_spec ping_chan_spec[] = {
{
.type = IIO_DISTANCE,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
};
static const struct of_device_id of_ping_match[] = {
{ .compatible = "parallax,ping", .data = &pa_ping_cfg },
{ .compatible = "parallax,laserping", .data = &pa_laser_ping_cfg },
{},
};
MODULE_DEVICE_TABLE(of, of_ping_match);
static int ping_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ping_data *data;
struct iio_dev *indio_dev;
indio_dev = devm_iio_device_alloc(dev, sizeof(struct ping_data));
if (!indio_dev) {
dev_err(dev, "failed to allocate IIO device\n");
return -ENOMEM;
}
data = iio_priv(indio_dev);
data->dev = dev;
data->cfg = device_get_match_data(dev);
mutex_init(&data->lock);
init_completion(&data->rising);
init_completion(&data->falling);
data->gpiod_ping = devm_gpiod_get(dev, "ping", GPIOD_OUT_LOW);
if (IS_ERR(data->gpiod_ping)) {
dev_err(dev, "failed to get ping-gpios: err=%ld\n",
PTR_ERR(data->gpiod_ping));
return PTR_ERR(data->gpiod_ping);
}
if (gpiod_cansleep(data->gpiod_ping)) {
dev_err(data->dev, "cansleep-GPIOs not supported\n");
return -ENODEV;
}
platform_set_drvdata(pdev, indio_dev);
indio_dev->name = "ping";
indio_dev->info = &ping_iio_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = ping_chan_spec;
indio_dev->num_channels = ARRAY_SIZE(ping_chan_spec);
return devm_iio_device_register(dev, indio_dev);
}
static struct platform_driver ping_driver = {
.probe = ping_probe,
.driver = {
.name = "ping-gpio",
.of_match_table = of_ping_match,
},
};
module_platform_driver(ping_driver);
MODULE_AUTHOR("Andreas Klinger <[email protected]>");
MODULE_DESCRIPTION("PING sensors for distance measuring using one GPIOs");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ping");
| linux-master | drivers/iio/proximity/ping.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for cros-ec proximity sensor exposed through MKBP switch
*
* Copyright 2021 Google LLC.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/notifier.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/platform_data/cros_ec_commands.h>
#include <linux/platform_data/cros_ec_proto.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <asm/unaligned.h>
struct cros_ec_mkbp_proximity_data {
struct cros_ec_device *ec;
struct iio_dev *indio_dev;
struct mutex lock;
struct notifier_block notifier;
int last_proximity;
bool enabled;
};
static const struct iio_event_spec cros_ec_mkbp_proximity_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec cros_ec_mkbp_proximity_chan_spec[] = {
{
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.event_spec = cros_ec_mkbp_proximity_events,
.num_event_specs = ARRAY_SIZE(cros_ec_mkbp_proximity_events),
},
};
static int cros_ec_mkbp_proximity_parse_state(const void *data)
{
u32 switches = get_unaligned_le32(data);
return !!(switches & BIT(EC_MKBP_FRONT_PROXIMITY));
}
static int cros_ec_mkbp_proximity_query(struct cros_ec_device *ec_dev,
int *state)
{
struct {
struct cros_ec_command msg;
union {
struct ec_params_mkbp_info params;
u32 switches;
};
} __packed buf = { };
struct ec_params_mkbp_info *params = &buf.params;
struct cros_ec_command *msg = &buf.msg;
u32 *switches = &buf.switches;
size_t insize = sizeof(*switches);
int ret;
msg->command = EC_CMD_MKBP_INFO;
msg->version = 1;
msg->outsize = sizeof(*params);
msg->insize = insize;
params->info_type = EC_MKBP_INFO_CURRENT;
params->event_type = EC_MKBP_EVENT_SWITCH;
ret = cros_ec_cmd_xfer_status(ec_dev, msg);
if (ret < 0)
return ret;
if (ret != insize) {
dev_warn(ec_dev->dev, "wrong result size: %d != %zu\n", ret,
insize);
return -EPROTO;
}
*state = cros_ec_mkbp_proximity_parse_state(switches);
return IIO_VAL_INT;
}
static void cros_ec_mkbp_proximity_push_event(struct cros_ec_mkbp_proximity_data *data, int state)
{
s64 timestamp;
u64 ev;
int dir;
struct iio_dev *indio_dev = data->indio_dev;
struct cros_ec_device *ec = data->ec;
mutex_lock(&data->lock);
if (state != data->last_proximity) {
if (data->enabled) {
timestamp = ktime_to_ns(ec->last_event_time);
if (iio_device_get_clock(indio_dev) != CLOCK_BOOTTIME)
timestamp = iio_get_time_ns(indio_dev);
dir = state ? IIO_EV_DIR_FALLING : IIO_EV_DIR_RISING;
ev = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
IIO_EV_TYPE_THRESH, dir);
iio_push_event(indio_dev, ev, timestamp);
}
data->last_proximity = state;
}
mutex_unlock(&data->lock);
}
static int cros_ec_mkbp_proximity_notify(struct notifier_block *nb,
unsigned long queued_during_suspend,
void *_ec)
{
struct cros_ec_mkbp_proximity_data *data;
struct cros_ec_device *ec = _ec;
u8 event_type = ec->event_data.event_type & EC_MKBP_EVENT_TYPE_MASK;
void *switches;
int state;
if (event_type == EC_MKBP_EVENT_SWITCH) {
data = container_of(nb, struct cros_ec_mkbp_proximity_data,
notifier);
switches = &ec->event_data.data.switches;
state = cros_ec_mkbp_proximity_parse_state(switches);
cros_ec_mkbp_proximity_push_event(data, state);
}
return NOTIFY_OK;
}
static int cros_ec_mkbp_proximity_read_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, int *val,
int *val2, long mask)
{
struct cros_ec_mkbp_proximity_data *data = iio_priv(indio_dev);
struct cros_ec_device *ec = data->ec;
if (chan->type == IIO_PROXIMITY && mask == IIO_CHAN_INFO_RAW)
return cros_ec_mkbp_proximity_query(ec, val);
return -EINVAL;
}
static int cros_ec_mkbp_proximity_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct cros_ec_mkbp_proximity_data *data = iio_priv(indio_dev);
return data->enabled;
}
static int cros_ec_mkbp_proximity_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct cros_ec_mkbp_proximity_data *data = iio_priv(indio_dev);
mutex_lock(&data->lock);
data->enabled = state;
mutex_unlock(&data->lock);
return 0;
}
static const struct iio_info cros_ec_mkbp_proximity_info = {
.read_raw = cros_ec_mkbp_proximity_read_raw,
.read_event_config = cros_ec_mkbp_proximity_read_event_config,
.write_event_config = cros_ec_mkbp_proximity_write_event_config,
};
static int cros_ec_mkbp_proximity_resume(struct device *dev)
{
struct cros_ec_mkbp_proximity_data *data = dev_get_drvdata(dev);
struct cros_ec_device *ec = data->ec;
int ret, state;
ret = cros_ec_mkbp_proximity_query(ec, &state);
if (ret < 0) {
dev_warn(dev, "failed to fetch proximity state on resume: %d\n",
ret);
} else {
cros_ec_mkbp_proximity_push_event(data, state);
}
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(cros_ec_mkbp_proximity_pm_ops, NULL,
cros_ec_mkbp_proximity_resume);
static int cros_ec_mkbp_proximity_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct cros_ec_device *ec = dev_get_drvdata(dev->parent);
struct iio_dev *indio_dev;
struct cros_ec_mkbp_proximity_data *data;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->ec = ec;
data->indio_dev = indio_dev;
data->last_proximity = -1; /* Unknown to start */
mutex_init(&data->lock);
platform_set_drvdata(pdev, data);
indio_dev->name = dev->driver->name;
indio_dev->info = &cros_ec_mkbp_proximity_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = cros_ec_mkbp_proximity_chan_spec;
indio_dev->num_channels = ARRAY_SIZE(cros_ec_mkbp_proximity_chan_spec);
ret = devm_iio_device_register(dev, indio_dev);
if (ret)
return ret;
data->notifier.notifier_call = cros_ec_mkbp_proximity_notify;
blocking_notifier_chain_register(&ec->event_notifier, &data->notifier);
return 0;
}
static int cros_ec_mkbp_proximity_remove(struct platform_device *pdev)
{
struct cros_ec_mkbp_proximity_data *data = platform_get_drvdata(pdev);
struct cros_ec_device *ec = data->ec;
blocking_notifier_chain_unregister(&ec->event_notifier,
&data->notifier);
return 0;
}
static const struct of_device_id cros_ec_mkbp_proximity_of_match[] = {
{ .compatible = "google,cros-ec-mkbp-proximity" },
{}
};
MODULE_DEVICE_TABLE(of, cros_ec_mkbp_proximity_of_match);
static struct platform_driver cros_ec_mkbp_proximity_driver = {
.driver = {
.name = "cros-ec-mkbp-proximity",
.of_match_table = cros_ec_mkbp_proximity_of_match,
.pm = pm_sleep_ptr(&cros_ec_mkbp_proximity_pm_ops),
},
.probe = cros_ec_mkbp_proximity_probe,
.remove = cros_ec_mkbp_proximity_remove,
};
module_platform_driver(cros_ec_mkbp_proximity_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("ChromeOS EC MKBP proximity sensor driver");
| linux-master | drivers/iio/proximity/cros_ec_mkbp_proximity.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* as3935.c - Support for AS3935 Franklin lightning sensor
*
* Copyright (C) 2014, 2017-2018
* Author: Matt Ranostay <[email protected]>
*/
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/devm-helpers.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/spi/spi.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#define AS3935_AFE_GAIN 0x00
#define AS3935_AFE_MASK 0x3F
#define AS3935_AFE_GAIN_MAX 0x1F
#define AS3935_AFE_PWR_BIT BIT(0)
#define AS3935_NFLWDTH 0x01
#define AS3935_NFLWDTH_MASK 0x7f
#define AS3935_INT 0x03
#define AS3935_INT_MASK 0x0f
#define AS3935_DISTURB_INT BIT(2)
#define AS3935_EVENT_INT BIT(3)
#define AS3935_NOISE_INT BIT(0)
#define AS3935_DATA 0x07
#define AS3935_DATA_MASK 0x3F
#define AS3935_TUNE_CAP 0x08
#define AS3935_DEFAULTS 0x3C
#define AS3935_CALIBRATE 0x3D
#define AS3935_READ_DATA BIT(14)
#define AS3935_ADDRESS(x) ((x) << 8)
#define MAX_PF_CAP 120
#define TUNE_CAP_DIV 8
struct as3935_state {
struct spi_device *spi;
struct iio_trigger *trig;
struct mutex lock;
struct delayed_work work;
unsigned long noise_tripped;
u32 tune_cap;
u32 nflwdth_reg;
/* Ensure timestamp is naturally aligned */
struct {
u8 chan;
s64 timestamp __aligned(8);
} scan;
u8 buf[2] __aligned(IIO_DMA_MINALIGN);
};
static const struct iio_chan_spec as3935_channels[] = {
{
.type = IIO_PROXIMITY,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 0,
.scan_type = {
.sign = 'u',
.realbits = 6,
.storagebits = 8,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static int as3935_read(struct as3935_state *st, unsigned int reg, int *val)
{
u8 cmd;
int ret;
cmd = (AS3935_READ_DATA | AS3935_ADDRESS(reg)) >> 8;
ret = spi_w8r8(st->spi, cmd);
if (ret < 0)
return ret;
*val = ret;
return 0;
}
static int as3935_write(struct as3935_state *st,
unsigned int reg,
unsigned int val)
{
u8 *buf = st->buf;
buf[0] = AS3935_ADDRESS(reg) >> 8;
buf[1] = val;
return spi_write(st->spi, buf, 2);
}
static ssize_t as3935_sensor_sensitivity_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct as3935_state *st = iio_priv(dev_to_iio_dev(dev));
int val, ret;
ret = as3935_read(st, AS3935_AFE_GAIN, &val);
if (ret)
return ret;
val = (val & AS3935_AFE_MASK) >> 1;
return sysfs_emit(buf, "%d\n", val);
}
static ssize_t as3935_sensor_sensitivity_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct as3935_state *st = iio_priv(dev_to_iio_dev(dev));
unsigned long val;
int ret;
ret = kstrtoul(buf, 10, &val);
if (ret)
return -EINVAL;
if (val > AS3935_AFE_GAIN_MAX)
return -EINVAL;
as3935_write(st, AS3935_AFE_GAIN, val << 1);
return len;
}
static ssize_t as3935_noise_level_tripped_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct as3935_state *st = iio_priv(dev_to_iio_dev(dev));
int ret;
mutex_lock(&st->lock);
ret = sysfs_emit(buf, "%d\n", !time_after(jiffies, st->noise_tripped + HZ));
mutex_unlock(&st->lock);
return ret;
}
static IIO_DEVICE_ATTR(sensor_sensitivity, S_IRUGO | S_IWUSR,
as3935_sensor_sensitivity_show, as3935_sensor_sensitivity_store, 0);
static IIO_DEVICE_ATTR(noise_level_tripped, S_IRUGO,
as3935_noise_level_tripped_show, NULL, 0);
static struct attribute *as3935_attributes[] = {
&iio_dev_attr_sensor_sensitivity.dev_attr.attr,
&iio_dev_attr_noise_level_tripped.dev_attr.attr,
NULL,
};
static const struct attribute_group as3935_attribute_group = {
.attrs = as3935_attributes,
};
static int as3935_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct as3935_state *st = iio_priv(indio_dev);
int ret;
switch (m) {
case IIO_CHAN_INFO_PROCESSED:
case IIO_CHAN_INFO_RAW:
*val2 = 0;
ret = as3935_read(st, AS3935_DATA, val);
if (ret)
return ret;
/* storm out of range */
if (*val == AS3935_DATA_MASK)
return -EINVAL;
if (m == IIO_CHAN_INFO_RAW)
return IIO_VAL_INT;
if (m == IIO_CHAN_INFO_PROCESSED)
*val *= 1000;
break;
case IIO_CHAN_INFO_SCALE:
*val = 1000;
break;
default:
return -EINVAL;
}
return IIO_VAL_INT;
}
static const struct iio_info as3935_info = {
.attrs = &as3935_attribute_group,
.read_raw = &as3935_read_raw,
};
static irqreturn_t as3935_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct as3935_state *st = iio_priv(indio_dev);
int val, ret;
ret = as3935_read(st, AS3935_DATA, &val);
if (ret)
goto err_read;
st->scan.chan = val & AS3935_DATA_MASK;
iio_push_to_buffers_with_timestamp(indio_dev, &st->scan,
iio_get_time_ns(indio_dev));
err_read:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static void as3935_event_work(struct work_struct *work)
{
struct as3935_state *st;
int val;
int ret;
st = container_of(work, struct as3935_state, work.work);
ret = as3935_read(st, AS3935_INT, &val);
if (ret) {
dev_warn(&st->spi->dev, "read error\n");
return;
}
val &= AS3935_INT_MASK;
switch (val) {
case AS3935_EVENT_INT:
iio_trigger_poll_nested(st->trig);
break;
case AS3935_DISTURB_INT:
case AS3935_NOISE_INT:
mutex_lock(&st->lock);
st->noise_tripped = jiffies;
mutex_unlock(&st->lock);
dev_warn(&st->spi->dev, "noise level is too high\n");
break;
}
}
static irqreturn_t as3935_interrupt_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct as3935_state *st = iio_priv(indio_dev);
/*
* Delay work for >2 milliseconds after an interrupt to allow
* estimated distance to recalculated.
*/
schedule_delayed_work(&st->work, msecs_to_jiffies(3));
return IRQ_HANDLED;
}
static void calibrate_as3935(struct as3935_state *st)
{
as3935_write(st, AS3935_DEFAULTS, 0x96);
as3935_write(st, AS3935_CALIBRATE, 0x96);
as3935_write(st, AS3935_TUNE_CAP,
BIT(5) | (st->tune_cap / TUNE_CAP_DIV));
mdelay(2);
as3935_write(st, AS3935_TUNE_CAP, (st->tune_cap / TUNE_CAP_DIV));
as3935_write(st, AS3935_NFLWDTH, st->nflwdth_reg);
}
static int as3935_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct as3935_state *st = iio_priv(indio_dev);
int val, ret;
mutex_lock(&st->lock);
ret = as3935_read(st, AS3935_AFE_GAIN, &val);
if (ret)
goto err_suspend;
val |= AS3935_AFE_PWR_BIT;
ret = as3935_write(st, AS3935_AFE_GAIN, val);
err_suspend:
mutex_unlock(&st->lock);
return ret;
}
static int as3935_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct as3935_state *st = iio_priv(indio_dev);
int val, ret;
mutex_lock(&st->lock);
ret = as3935_read(st, AS3935_AFE_GAIN, &val);
if (ret)
goto err_resume;
val &= ~AS3935_AFE_PWR_BIT;
ret = as3935_write(st, AS3935_AFE_GAIN, val);
calibrate_as3935(st);
err_resume:
mutex_unlock(&st->lock);
return ret;
}
static DEFINE_SIMPLE_DEV_PM_OPS(as3935_pm_ops, as3935_suspend, as3935_resume);
static int as3935_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct iio_dev *indio_dev;
struct iio_trigger *trig;
struct as3935_state *st;
int ret;
/* Be sure lightning event interrupt is specified */
if (!spi->irq) {
dev_err(dev, "unable to get event interrupt\n");
return -EINVAL;
}
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
if (!indio_dev)
return -ENOMEM;
st = iio_priv(indio_dev);
st->spi = spi;
spi_set_drvdata(spi, indio_dev);
mutex_init(&st->lock);
ret = device_property_read_u32(dev,
"ams,tuning-capacitor-pf", &st->tune_cap);
if (ret) {
st->tune_cap = 0;
dev_warn(dev, "no tuning-capacitor-pf set, defaulting to %d",
st->tune_cap);
}
if (st->tune_cap > MAX_PF_CAP) {
dev_err(dev, "wrong tuning-capacitor-pf setting of %d\n",
st->tune_cap);
return -EINVAL;
}
ret = device_property_read_u32(dev,
"ams,nflwdth", &st->nflwdth_reg);
if (!ret && st->nflwdth_reg > AS3935_NFLWDTH_MASK) {
dev_err(dev, "invalid nflwdth setting of %d\n",
st->nflwdth_reg);
return -EINVAL;
}
indio_dev->name = spi_get_device_id(spi)->name;
indio_dev->channels = as3935_channels;
indio_dev->num_channels = ARRAY_SIZE(as3935_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &as3935_info;
trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
indio_dev->name,
iio_device_id(indio_dev));
if (!trig)
return -ENOMEM;
st->trig = trig;
st->noise_tripped = jiffies - HZ;
iio_trigger_set_drvdata(trig, indio_dev);
ret = devm_iio_trigger_register(dev, trig);
if (ret) {
dev_err(dev, "failed to register trigger\n");
return ret;
}
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
iio_pollfunc_store_time,
as3935_trigger_handler, NULL);
if (ret) {
dev_err(dev, "cannot setup iio trigger\n");
return ret;
}
calibrate_as3935(st);
ret = devm_delayed_work_autocancel(dev, &st->work, as3935_event_work);
if (ret)
return ret;
ret = devm_request_irq(dev, spi->irq,
&as3935_interrupt_handler,
IRQF_TRIGGER_RISING,
dev_name(dev),
indio_dev);
if (ret) {
dev_err(dev, "unable to request irq\n");
return ret;
}
ret = devm_iio_device_register(dev, indio_dev);
if (ret < 0) {
dev_err(dev, "unable to register device\n");
return ret;
}
return 0;
}
static const struct of_device_id as3935_of_match[] = {
{ .compatible = "ams,as3935", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, as3935_of_match);
static const struct spi_device_id as3935_id[] = {
{"as3935", 0},
{},
};
MODULE_DEVICE_TABLE(spi, as3935_id);
static struct spi_driver as3935_driver = {
.driver = {
.name = "as3935",
.of_match_table = as3935_of_match,
.pm = pm_sleep_ptr(&as3935_pm_ops),
},
.probe = as3935_probe,
.id_table = as3935_id,
};
module_spi_driver(as3935_driver);
MODULE_AUTHOR("Matt Ranostay <[email protected]>");
MODULE_DESCRIPTION("AS3935 lightning sensor");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/proximity/as3935.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for Murata IRS-D200 PIR sensor.
*
* Copyright (C) 2023 Axis Communications AB
*/
#include <asm/unaligned.h>
#include <linux/bitfield.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/iio/buffer.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/types.h>
#define IRS_DRV_NAME "irsd200"
/* Registers. */
#define IRS_REG_OP 0x00 /* Operation mode. */
#define IRS_REG_DATA_LO 0x02 /* Sensor data LSB. */
#define IRS_REG_DATA_HI 0x03 /* Sensor data MSB. */
#define IRS_REG_STATUS 0x04 /* Interrupt status. */
#define IRS_REG_COUNT 0x05 /* Count of exceeding threshold. */
#define IRS_REG_DATA_RATE 0x06 /* Output data rate. */
#define IRS_REG_FILTER 0x07 /* High-pass and low-pass filter. */
#define IRS_REG_INTR 0x09 /* Interrupt mode. */
#define IRS_REG_NR_COUNT 0x0a /* Number of counts before interrupt. */
#define IRS_REG_THR_HI 0x0b /* Upper threshold. */
#define IRS_REG_THR_LO 0x0c /* Lower threshold. */
#define IRS_REG_TIMER_LO 0x0d /* Timer setting LSB. */
#define IRS_REG_TIMER_HI 0x0e /* Timer setting MSB. */
/* Interrupt status bits. */
#define IRS_INTR_DATA 0 /* Data update. */
#define IRS_INTR_TIMER 1 /* Timer expiration. */
#define IRS_INTR_COUNT_THR_AND 2 /* Count "AND" threshold. */
#define IRS_INTR_COUNT_THR_OR 3 /* Count "OR" threshold. */
/* Operation states. */
#define IRS_OP_ACTIVE 0x00
#define IRS_OP_SLEEP 0x01
/*
* Quantization scale value for threshold. Used for conversion from/to register
* value.
*/
#define IRS_THR_QUANT_SCALE 128
#define IRS_UPPER_COUNT(count) FIELD_GET(GENMASK(7, 4), count)
#define IRS_LOWER_COUNT(count) FIELD_GET(GENMASK(3, 0), count)
/* Index corresponds to the value of IRS_REG_DATA_RATE register. */
static const int irsd200_data_rates[] = {
50,
100,
};
/* Index corresponds to the (field) value of IRS_REG_FILTER register. */
static const unsigned int irsd200_lp_filter_freq[] = {
10,
7,
};
/*
* Index corresponds to the (field) value of IRS_REG_FILTER register. Note that
* this represents a fractional value (e.g the first value corresponds to 3 / 10
* = 0.3 Hz).
*/
static const unsigned int irsd200_hp_filter_freq[][2] = {
{ 3, 10 },
{ 5, 10 },
};
/* Register fields. */
enum irsd200_regfield {
/* Data interrupt. */
IRS_REGF_INTR_DATA,
/* Timer interrupt. */
IRS_REGF_INTR_TIMER,
/* AND count threshold interrupt. */
IRS_REGF_INTR_COUNT_THR_AND,
/* OR count threshold interrupt. */
IRS_REGF_INTR_COUNT_THR_OR,
/* Low-pass filter frequency. */
IRS_REGF_LP_FILTER,
/* High-pass filter frequency. */
IRS_REGF_HP_FILTER,
/* Sentinel value. */
IRS_REGF_MAX
};
static const struct reg_field irsd200_regfields[] = {
[IRS_REGF_INTR_DATA] =
REG_FIELD(IRS_REG_INTR, IRS_INTR_DATA, IRS_INTR_DATA),
[IRS_REGF_INTR_TIMER] =
REG_FIELD(IRS_REG_INTR, IRS_INTR_TIMER, IRS_INTR_TIMER),
[IRS_REGF_INTR_COUNT_THR_AND] = REG_FIELD(
IRS_REG_INTR, IRS_INTR_COUNT_THR_AND, IRS_INTR_COUNT_THR_AND),
[IRS_REGF_INTR_COUNT_THR_OR] = REG_FIELD(
IRS_REG_INTR, IRS_INTR_COUNT_THR_OR, IRS_INTR_COUNT_THR_OR),
[IRS_REGF_LP_FILTER] = REG_FIELD(IRS_REG_FILTER, 1, 1),
[IRS_REGF_HP_FILTER] = REG_FIELD(IRS_REG_FILTER, 0, 0),
};
static const struct regmap_config irsd200_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = IRS_REG_TIMER_HI,
};
struct irsd200_data {
struct regmap *regmap;
struct regmap_field *regfields[IRS_REGF_MAX];
struct device *dev;
};
static int irsd200_setup(struct irsd200_data *data)
{
unsigned int val;
int ret;
/* Disable all interrupt sources. */
ret = regmap_write(data->regmap, IRS_REG_INTR, 0);
if (ret) {
dev_err(data->dev, "Could not set interrupt sources (%d)\n",
ret);
return ret;
}
/* Set operation to active. */
ret = regmap_write(data->regmap, IRS_REG_OP, IRS_OP_ACTIVE);
if (ret) {
dev_err(data->dev, "Could not set operation mode (%d)\n", ret);
return ret;
}
/* Clear threshold count. */
ret = regmap_read(data->regmap, IRS_REG_COUNT, &val);
if (ret) {
dev_err(data->dev, "Could not clear threshold count (%d)\n",
ret);
return ret;
}
/* Clear status. */
ret = regmap_write(data->regmap, IRS_REG_STATUS, 0x0f);
if (ret) {
dev_err(data->dev, "Could not clear status (%d)\n", ret);
return ret;
}
return 0;
}
static int irsd200_read_threshold(struct irsd200_data *data,
enum iio_event_direction dir, int *val)
{
unsigned int regval;
unsigned int reg;
int scale;
int ret;
/* Set quantization scale. */
if (dir == IIO_EV_DIR_RISING) {
scale = IRS_THR_QUANT_SCALE;
reg = IRS_REG_THR_HI;
} else if (dir == IIO_EV_DIR_FALLING) {
scale = -IRS_THR_QUANT_SCALE;
reg = IRS_REG_THR_LO;
} else {
return -EINVAL;
}
ret = regmap_read(data->regmap, reg, ®val);
if (ret) {
dev_err(data->dev, "Could not read threshold (%d)\n", ret);
return ret;
}
*val = ((int)regval) * scale;
return 0;
}
static int irsd200_write_threshold(struct irsd200_data *data,
enum iio_event_direction dir, int val)
{
unsigned int regval;
unsigned int reg;
int scale;
int ret;
/* Set quantization scale. */
if (dir == IIO_EV_DIR_RISING) {
if (val < 0)
return -ERANGE;
scale = IRS_THR_QUANT_SCALE;
reg = IRS_REG_THR_HI;
} else if (dir == IIO_EV_DIR_FALLING) {
if (val > 0)
return -ERANGE;
scale = -IRS_THR_QUANT_SCALE;
reg = IRS_REG_THR_LO;
} else {
return -EINVAL;
}
regval = val / scale;
if (regval >= BIT(8))
return -ERANGE;
ret = regmap_write(data->regmap, reg, regval);
if (ret) {
dev_err(data->dev, "Could not write threshold (%d)\n", ret);
return ret;
}
return 0;
}
static int irsd200_read_data(struct irsd200_data *data, s16 *val)
{
__le16 buf;
int ret;
ret = regmap_bulk_read(data->regmap, IRS_REG_DATA_LO, &buf,
sizeof(buf));
if (ret) {
dev_err(data->dev, "Could not bulk read data (%d)\n", ret);
return ret;
}
*val = le16_to_cpu(buf);
return 0;
}
static int irsd200_read_data_rate(struct irsd200_data *data, int *val)
{
unsigned int regval;
int ret;
ret = regmap_read(data->regmap, IRS_REG_DATA_RATE, ®val);
if (ret) {
dev_err(data->dev, "Could not read data rate (%d)\n", ret);
return ret;
}
if (regval >= ARRAY_SIZE(irsd200_data_rates))
return -ERANGE;
*val = irsd200_data_rates[regval];
return 0;
}
static int irsd200_write_data_rate(struct irsd200_data *data, int val)
{
size_t idx;
int ret;
for (idx = 0; idx < ARRAY_SIZE(irsd200_data_rates); ++idx) {
if (irsd200_data_rates[idx] == val)
break;
}
if (idx == ARRAY_SIZE(irsd200_data_rates))
return -ERANGE;
ret = regmap_write(data->regmap, IRS_REG_DATA_RATE, idx);
if (ret) {
dev_err(data->dev, "Could not write data rate (%d)\n", ret);
return ret;
}
/*
* Data sheet says the device needs 3 seconds of settling time. The
* device operates normally during this period though. This is more of a
* "guarantee" than trying to prevent other user space reads/writes.
*/
ssleep(3);
return 0;
}
static int irsd200_read_timer(struct irsd200_data *data, int *val, int *val2)
{
__le16 buf;
int ret;
ret = regmap_bulk_read(data->regmap, IRS_REG_TIMER_LO, &buf,
sizeof(buf));
if (ret) {
dev_err(data->dev, "Could not bulk read timer (%d)\n", ret);
return ret;
}
ret = irsd200_read_data_rate(data, val2);
if (ret)
return ret;
*val = le16_to_cpu(buf);
return 0;
}
static int irsd200_write_timer(struct irsd200_data *data, int val, int val2)
{
unsigned int regval;
int data_rate;
__le16 buf;
int ret;
if (val < 0 || val2 < 0)
return -ERANGE;
ret = irsd200_read_data_rate(data, &data_rate);
if (ret)
return ret;
/* Quantize from seconds. */
regval = val * data_rate + (val2 * data_rate) / 1000000;
/* Value is 10 bits. */
if (regval >= BIT(10))
return -ERANGE;
buf = cpu_to_le16((u16)regval);
ret = regmap_bulk_write(data->regmap, IRS_REG_TIMER_LO, &buf,
sizeof(buf));
if (ret) {
dev_err(data->dev, "Could not bulk write timer (%d)\n", ret);
return ret;
}
return 0;
}
static int irsd200_read_nr_count(struct irsd200_data *data, int *val)
{
unsigned int regval;
int ret;
ret = regmap_read(data->regmap, IRS_REG_NR_COUNT, ®val);
if (ret) {
dev_err(data->dev, "Could not read nr count (%d)\n", ret);
return ret;
}
*val = regval;
return 0;
}
static int irsd200_write_nr_count(struct irsd200_data *data, int val)
{
unsigned int regval;
int ret;
/* A value of zero means that IRS_REG_STATUS is never set. */
if (val <= 0 || val >= 8)
return -ERANGE;
regval = val;
if (regval >= 2) {
/*
* According to the data sheet, timer must be also set in this
* case (i.e. be non-zero). Check and enforce that.
*/
ret = irsd200_read_timer(data, &val, &val);
if (ret)
return ret;
if (val == 0) {
dev_err(data->dev,
"Timer must be non-zero when nr count is %u\n",
regval);
return -EPERM;
}
}
ret = regmap_write(data->regmap, IRS_REG_NR_COUNT, regval);
if (ret) {
dev_err(data->dev, "Could not write nr count (%d)\n", ret);
return ret;
}
return 0;
}
static int irsd200_read_lp_filter(struct irsd200_data *data, int *val)
{
unsigned int regval;
int ret;
ret = regmap_field_read(data->regfields[IRS_REGF_LP_FILTER], ®val);
if (ret) {
dev_err(data->dev, "Could not read lp filter frequency (%d)\n",
ret);
return ret;
}
*val = irsd200_lp_filter_freq[regval];
return 0;
}
static int irsd200_write_lp_filter(struct irsd200_data *data, int val)
{
size_t idx;
int ret;
for (idx = 0; idx < ARRAY_SIZE(irsd200_lp_filter_freq); ++idx) {
if (irsd200_lp_filter_freq[idx] == val)
break;
}
if (idx == ARRAY_SIZE(irsd200_lp_filter_freq))
return -ERANGE;
ret = regmap_field_write(data->regfields[IRS_REGF_LP_FILTER], idx);
if (ret) {
dev_err(data->dev, "Could not write lp filter frequency (%d)\n",
ret);
return ret;
}
return 0;
}
static int irsd200_read_hp_filter(struct irsd200_data *data, int *val,
int *val2)
{
unsigned int regval;
int ret;
ret = regmap_field_read(data->regfields[IRS_REGF_HP_FILTER], ®val);
if (ret) {
dev_err(data->dev, "Could not read hp filter frequency (%d)\n",
ret);
return ret;
}
*val = irsd200_hp_filter_freq[regval][0];
*val2 = irsd200_hp_filter_freq[regval][1];
return 0;
}
static int irsd200_write_hp_filter(struct irsd200_data *data, int val, int val2)
{
size_t idx;
int ret;
/* Truncate fractional part to one digit. */
val2 /= 100000;
for (idx = 0; idx < ARRAY_SIZE(irsd200_hp_filter_freq); ++idx) {
if (irsd200_hp_filter_freq[idx][0] == val2)
break;
}
if (idx == ARRAY_SIZE(irsd200_hp_filter_freq) || val != 0)
return -ERANGE;
ret = regmap_field_write(data->regfields[IRS_REGF_HP_FILTER], idx);
if (ret) {
dev_err(data->dev, "Could not write hp filter frequency (%d)\n",
ret);
return ret;
}
return 0;
}
static int irsd200_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct irsd200_data *data = iio_priv(indio_dev);
int ret;
s16 buf;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = irsd200_read_data(data, &buf);
if (ret)
return ret;
*val = buf;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SAMP_FREQ:
ret = irsd200_read_data_rate(data, val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
ret = irsd200_read_lp_filter(data, val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
ret = irsd200_read_hp_filter(data, val, val2);
if (ret)
return ret;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
}
static int irsd200_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
*vals = irsd200_data_rates;
*type = IIO_VAL_INT;
*length = ARRAY_SIZE(irsd200_data_rates);
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
*vals = irsd200_lp_filter_freq;
*type = IIO_VAL_INT;
*length = ARRAY_SIZE(irsd200_lp_filter_freq);
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
*vals = (int *)irsd200_hp_filter_freq;
*type = IIO_VAL_FRACTIONAL;
*length = 2 * ARRAY_SIZE(irsd200_hp_filter_freq);
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static int irsd200_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct irsd200_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
return irsd200_write_data_rate(data, val);
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
return irsd200_write_lp_filter(data, val);
case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
return irsd200_write_hp_filter(data, val, val2);
default:
return -EINVAL;
}
}
static int irsd200_read_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int *val, int *val2)
{
struct irsd200_data *data = iio_priv(indio_dev);
int ret;
switch (info) {
case IIO_EV_INFO_VALUE:
ret = irsd200_read_threshold(data, dir, val);
if (ret)
return ret;
return IIO_VAL_INT;
case IIO_EV_INFO_RUNNING_PERIOD:
ret = irsd200_read_timer(data, val, val2);
if (ret)
return ret;
return IIO_VAL_FRACTIONAL;
case IIO_EV_INFO_RUNNING_COUNT:
ret = irsd200_read_nr_count(data, val);
if (ret)
return ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int irsd200_write_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int val, int val2)
{
struct irsd200_data *data = iio_priv(indio_dev);
switch (info) {
case IIO_EV_INFO_VALUE:
return irsd200_write_threshold(data, dir, val);
case IIO_EV_INFO_RUNNING_PERIOD:
return irsd200_write_timer(data, val, val2);
case IIO_EV_INFO_RUNNING_COUNT:
return irsd200_write_nr_count(data, val);
default:
return -EINVAL;
}
}
static int irsd200_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct irsd200_data *data = iio_priv(indio_dev);
unsigned int val;
int ret;
switch (type) {
case IIO_EV_TYPE_THRESH:
ret = regmap_field_read(
data->regfields[IRS_REGF_INTR_COUNT_THR_OR], &val);
if (ret)
return ret;
return val;
default:
return -EINVAL;
}
}
static int irsd200_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct irsd200_data *data = iio_priv(indio_dev);
unsigned int tmp;
int ret;
switch (type) {
case IIO_EV_TYPE_THRESH:
/* Clear the count register (by reading from it). */
ret = regmap_read(data->regmap, IRS_REG_COUNT, &tmp);
if (ret)
return ret;
return regmap_field_write(
data->regfields[IRS_REGF_INTR_COUNT_THR_OR], !!state);
default:
return -EINVAL;
}
}
static irqreturn_t irsd200_irq_thread(int irq, void *dev_id)
{
struct iio_dev *indio_dev = dev_id;
struct irsd200_data *data = iio_priv(indio_dev);
enum iio_event_direction dir;
unsigned int lower_count;
unsigned int upper_count;
unsigned int status = 0;
unsigned int source = 0;
unsigned int clear = 0;
unsigned int count = 0;
int ret;
ret = regmap_read(data->regmap, IRS_REG_INTR, &source);
if (ret) {
dev_err(data->dev, "Could not read interrupt source (%d)\n",
ret);
return IRQ_HANDLED;
}
ret = regmap_read(data->regmap, IRS_REG_STATUS, &status);
if (ret) {
dev_err(data->dev, "Could not acknowledge interrupt (%d)\n",
ret);
return IRQ_HANDLED;
}
if (status & BIT(IRS_INTR_DATA) && iio_buffer_enabled(indio_dev)) {
iio_trigger_poll_nested(indio_dev->trig);
clear |= BIT(IRS_INTR_DATA);
}
if (status & BIT(IRS_INTR_COUNT_THR_OR) &&
source & BIT(IRS_INTR_COUNT_THR_OR)) {
/*
* The register value resets to zero after reading. We therefore
* need to read once and manually extract the lower and upper
* count register fields.
*/
ret = regmap_read(data->regmap, IRS_REG_COUNT, &count);
if (ret)
dev_err(data->dev, "Could not read count (%d)\n", ret);
upper_count = IRS_UPPER_COUNT(count);
lower_count = IRS_LOWER_COUNT(count);
/*
* We only check the OR mode to be able to push events for
* rising and falling thresholds. AND mode is covered when both
* upper and lower count is non-zero, and is signaled with
* IIO_EV_DIR_EITHER.
*/
if (upper_count && !lower_count)
dir = IIO_EV_DIR_RISING;
else if (!upper_count && lower_count)
dir = IIO_EV_DIR_FALLING;
else
dir = IIO_EV_DIR_EITHER;
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
IIO_EV_TYPE_THRESH, dir),
iio_get_time_ns(indio_dev));
/*
* The OR mode will always trigger when the AND mode does, but
* not vice versa. However, it seems like the AND bit needs to
* be cleared if data capture _and_ threshold count interrupts
* are desirable, even though it hasn't explicitly been selected
* (with IRS_REG_INTR). Either way, it doesn't hurt...
*/
clear |= BIT(IRS_INTR_COUNT_THR_OR) |
BIT(IRS_INTR_COUNT_THR_AND);
}
if (!clear)
return IRQ_NONE;
ret = regmap_write(data->regmap, IRS_REG_STATUS, clear);
if (ret)
dev_err(data->dev,
"Could not clear interrupt status (%d)\n", ret);
return IRQ_HANDLED;
}
static irqreturn_t irsd200_trigger_handler(int irq, void *pollf)
{
struct iio_dev *indio_dev = ((struct iio_poll_func *)pollf)->indio_dev;
struct irsd200_data *data = iio_priv(indio_dev);
s16 buf = 0;
int ret;
ret = irsd200_read_data(data, &buf);
if (ret)
goto end;
iio_push_to_buffers_with_timestamp(indio_dev, &buf,
iio_get_time_ns(indio_dev));
end:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int irsd200_set_trigger_state(struct iio_trigger *trig, bool state)
{
struct irsd200_data *data = iio_trigger_get_drvdata(trig);
int ret;
ret = regmap_field_write(data->regfields[IRS_REGF_INTR_DATA], state);
if (ret) {
dev_err(data->dev, "Could not %s data interrupt source (%d)\n",
state ? "enable" : "disable", ret);
}
return ret;
}
static const struct iio_info irsd200_info = {
.read_raw = irsd200_read_raw,
.read_avail = irsd200_read_avail,
.write_raw = irsd200_write_raw,
.read_event_value = irsd200_read_event,
.write_event_value = irsd200_write_event,
.read_event_config = irsd200_read_event_config,
.write_event_config = irsd200_write_event_config,
};
static const struct iio_trigger_ops irsd200_trigger_ops = {
.set_trigger_state = irsd200_set_trigger_state,
.validate_device = iio_trigger_validate_own_device,
};
static const struct iio_event_spec irsd200_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate =
BIT(IIO_EV_INFO_RUNNING_PERIOD) |
BIT(IIO_EV_INFO_RUNNING_COUNT) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec irsd200_channels[] = {
{
.type = IIO_PROXIMITY,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SAMP_FREQ) |
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_SAMP_FREQ) |
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY),
.event_spec = irsd200_event_spec,
.num_event_specs = ARRAY_SIZE(irsd200_event_spec),
.scan_type = {
.sign = 's',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_CPU,
},
},
};
static int irsd200_probe(struct i2c_client *client)
{
struct iio_trigger *trigger;
struct irsd200_data *data;
struct iio_dev *indio_dev;
size_t i;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return dev_err_probe(&client->dev, -ENOMEM,
"Could not allocate iio device\n");
data = iio_priv(indio_dev);
data->dev = &client->dev;
data->regmap = devm_regmap_init_i2c(client, &irsd200_regmap_config);
if (IS_ERR(data->regmap))
return dev_err_probe(data->dev, PTR_ERR(data->regmap),
"Could not initialize regmap\n");
for (i = 0; i < IRS_REGF_MAX; ++i) {
data->regfields[i] = devm_regmap_field_alloc(
data->dev, data->regmap, irsd200_regfields[i]);
if (IS_ERR(data->regfields[i]))
return dev_err_probe(
data->dev, PTR_ERR(data->regfields[i]),
"Could not allocate register field %zu\n", i);
}
ret = devm_regulator_get_enable(data->dev, "vdd");
if (ret)
return dev_err_probe(
data->dev, ret,
"Could not get and enable regulator (%d)\n", ret);
ret = irsd200_setup(data);
if (ret)
return ret;
indio_dev->info = &irsd200_info;
indio_dev->name = IRS_DRV_NAME;
indio_dev->channels = irsd200_channels;
indio_dev->num_channels = ARRAY_SIZE(irsd200_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
if (!client->irq)
return dev_err_probe(data->dev, -ENXIO, "No irq available\n");
ret = devm_iio_triggered_buffer_setup(data->dev, indio_dev, NULL,
irsd200_trigger_handler, NULL);
if (ret)
return dev_err_probe(
data->dev, ret,
"Could not setup iio triggered buffer (%d)\n", ret);
ret = devm_request_threaded_irq(data->dev, client->irq, NULL,
irsd200_irq_thread,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
NULL, indio_dev);
if (ret)
return dev_err_probe(data->dev, ret,
"Could not request irq (%d)\n", ret);
trigger = devm_iio_trigger_alloc(data->dev, "%s-dev%d", indio_dev->name,
iio_device_id(indio_dev));
if (!trigger)
return dev_err_probe(data->dev, -ENOMEM,
"Could not allocate iio trigger\n");
trigger->ops = &irsd200_trigger_ops;
iio_trigger_set_drvdata(trigger, data);
ret = devm_iio_trigger_register(data->dev, trigger);
if (ret)
return dev_err_probe(data->dev, ret,
"Could not register iio trigger (%d)\n",
ret);
ret = devm_iio_device_register(data->dev, indio_dev);
if (ret)
return dev_err_probe(data->dev, ret,
"Could not register iio device (%d)\n",
ret);
return 0;
}
static const struct of_device_id irsd200_of_match[] = {
{
.compatible = "murata,irsd200",
},
{}
};
MODULE_DEVICE_TABLE(of, irsd200_of_match);
static struct i2c_driver irsd200_driver = {
.driver = {
.name = IRS_DRV_NAME,
.of_match_table = irsd200_of_match,
},
.probe = irsd200_probe,
};
module_i2c_driver(irsd200_driver);
MODULE_AUTHOR("Waqar Hameed <[email protected]>");
MODULE_DESCRIPTION("Murata IRS-D200 PIR sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/proximity/irsd200.c |
// SPDX-License-Identifier: GPL-2.0
/*
* isl29501.c: ISL29501 Time of Flight sensor driver.
*
* Copyright (C) 2018
* Author: Mathieu Othacehe <[email protected]>
*
* 7-bit I2C slave address: 0x57
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/mod_devicetable.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
/* Control, setting and status registers */
#define ISL29501_DEVICE_ID 0x00
#define ISL29501_ID 0x0A
/* Sampling control registers */
#define ISL29501_INTEGRATION_PERIOD 0x10
#define ISL29501_SAMPLE_PERIOD 0x11
/* Closed loop calibration registers */
#define ISL29501_CROSSTALK_I_MSB 0x24
#define ISL29501_CROSSTALK_I_LSB 0x25
#define ISL29501_CROSSTALK_I_EXPONENT 0x26
#define ISL29501_CROSSTALK_Q_MSB 0x27
#define ISL29501_CROSSTALK_Q_LSB 0x28
#define ISL29501_CROSSTALK_Q_EXPONENT 0x29
#define ISL29501_CROSSTALK_GAIN_MSB 0x2A
#define ISL29501_CROSSTALK_GAIN_LSB 0x2B
#define ISL29501_MAGNITUDE_REF_EXP 0x2C
#define ISL29501_MAGNITUDE_REF_MSB 0x2D
#define ISL29501_MAGNITUDE_REF_LSB 0x2E
#define ISL29501_PHASE_OFFSET_MSB 0x2F
#define ISL29501_PHASE_OFFSET_LSB 0x30
/* Analog control registers */
#define ISL29501_DRIVER_RANGE 0x90
#define ISL29501_EMITTER_DAC 0x91
#define ISL29501_COMMAND_REGISTER 0xB0
/* Commands */
#define ISL29501_EMUL_SAMPLE_START_PIN 0x49
#define ISL29501_RESET_ALL_REGISTERS 0xD7
#define ISL29501_RESET_INT_SM 0xD1
/* Ambiant light and temperature corrections */
#define ISL29501_TEMP_REFERENCE 0x31
#define ISL29501_PHASE_EXPONENT 0x33
#define ISL29501_TEMP_COEFF_A 0x34
#define ISL29501_TEMP_COEFF_B 0x39
#define ISL29501_AMBIANT_COEFF_A 0x36
#define ISL29501_AMBIANT_COEFF_B 0x3B
/* Data output registers */
#define ISL29501_DISTANCE_MSB_DATA 0xD1
#define ISL29501_DISTANCE_LSB_DATA 0xD2
#define ISL29501_PRECISION_MSB 0xD3
#define ISL29501_PRECISION_LSB 0xD4
#define ISL29501_MAGNITUDE_EXPONENT 0xD5
#define ISL29501_MAGNITUDE_MSB 0xD6
#define ISL29501_MAGNITUDE_LSB 0xD7
#define ISL29501_PHASE_MSB 0xD8
#define ISL29501_PHASE_LSB 0xD9
#define ISL29501_I_RAW_EXPONENT 0xDA
#define ISL29501_I_RAW_MSB 0xDB
#define ISL29501_I_RAW_LSB 0xDC
#define ISL29501_Q_RAW_EXPONENT 0xDD
#define ISL29501_Q_RAW_MSB 0xDE
#define ISL29501_Q_RAW_LSB 0xDF
#define ISL29501_DIE_TEMPERATURE 0xE2
#define ISL29501_AMBIENT_LIGHT 0xE3
#define ISL29501_GAIN_MSB 0xE6
#define ISL29501_GAIN_LSB 0xE7
#define ISL29501_MAX_EXP_VAL 15
#define ISL29501_INT_TIME_AVAILABLE \
"0.00007 0.00014 0.00028 0.00057 0.00114 " \
"0.00228 0.00455 0.00910 0.01820 0.03640 " \
"0.07281 0.14561"
#define ISL29501_CURRENT_SCALE_AVAILABLE \
"0.0039 0.0078 0.0118 0.0157 0.0196 " \
"0.0235 0.0275 0.0314 0.0352 0.0392 " \
"0.0431 0.0471 0.0510 0.0549 0.0588"
enum isl29501_correction_coeff {
COEFF_TEMP_A,
COEFF_TEMP_B,
COEFF_LIGHT_A,
COEFF_LIGHT_B,
COEFF_MAX,
};
struct isl29501_private {
struct i2c_client *client;
struct mutex lock;
/* Exact representation of correction coefficients. */
unsigned int shadow_coeffs[COEFF_MAX];
};
enum isl29501_register_name {
REG_DISTANCE,
REG_PHASE,
REG_TEMPERATURE,
REG_AMBIENT_LIGHT,
REG_GAIN,
REG_GAIN_BIAS,
REG_PHASE_EXP,
REG_CALIB_PHASE_TEMP_A,
REG_CALIB_PHASE_TEMP_B,
REG_CALIB_PHASE_LIGHT_A,
REG_CALIB_PHASE_LIGHT_B,
REG_DISTANCE_BIAS,
REG_TEMPERATURE_BIAS,
REG_INT_TIME,
REG_SAMPLE_TIME,
REG_DRIVER_RANGE,
REG_EMITTER_DAC,
};
struct isl29501_register_desc {
u8 msb;
u8 lsb;
};
static const struct isl29501_register_desc isl29501_registers[] = {
[REG_DISTANCE] = {
.msb = ISL29501_DISTANCE_MSB_DATA,
.lsb = ISL29501_DISTANCE_LSB_DATA,
},
[REG_PHASE] = {
.msb = ISL29501_PHASE_MSB,
.lsb = ISL29501_PHASE_LSB,
},
[REG_TEMPERATURE] = {
.lsb = ISL29501_DIE_TEMPERATURE,
},
[REG_AMBIENT_LIGHT] = {
.lsb = ISL29501_AMBIENT_LIGHT,
},
[REG_GAIN] = {
.msb = ISL29501_GAIN_MSB,
.lsb = ISL29501_GAIN_LSB,
},
[REG_GAIN_BIAS] = {
.msb = ISL29501_CROSSTALK_GAIN_MSB,
.lsb = ISL29501_CROSSTALK_GAIN_LSB,
},
[REG_PHASE_EXP] = {
.lsb = ISL29501_PHASE_EXPONENT,
},
[REG_CALIB_PHASE_TEMP_A] = {
.lsb = ISL29501_TEMP_COEFF_A,
},
[REG_CALIB_PHASE_TEMP_B] = {
.lsb = ISL29501_TEMP_COEFF_B,
},
[REG_CALIB_PHASE_LIGHT_A] = {
.lsb = ISL29501_AMBIANT_COEFF_A,
},
[REG_CALIB_PHASE_LIGHT_B] = {
.lsb = ISL29501_AMBIANT_COEFF_B,
},
[REG_DISTANCE_BIAS] = {
.msb = ISL29501_PHASE_OFFSET_MSB,
.lsb = ISL29501_PHASE_OFFSET_LSB,
},
[REG_TEMPERATURE_BIAS] = {
.lsb = ISL29501_TEMP_REFERENCE,
},
[REG_INT_TIME] = {
.lsb = ISL29501_INTEGRATION_PERIOD,
},
[REG_SAMPLE_TIME] = {
.lsb = ISL29501_SAMPLE_PERIOD,
},
[REG_DRIVER_RANGE] = {
.lsb = ISL29501_DRIVER_RANGE,
},
[REG_EMITTER_DAC] = {
.lsb = ISL29501_EMITTER_DAC,
},
};
static int isl29501_register_read(struct isl29501_private *isl29501,
enum isl29501_register_name name,
u32 *val)
{
const struct isl29501_register_desc *reg = &isl29501_registers[name];
u8 msb = 0, lsb = 0;
s32 ret;
mutex_lock(&isl29501->lock);
if (reg->msb) {
ret = i2c_smbus_read_byte_data(isl29501->client, reg->msb);
if (ret < 0)
goto err;
msb = ret;
}
if (reg->lsb) {
ret = i2c_smbus_read_byte_data(isl29501->client, reg->lsb);
if (ret < 0)
goto err;
lsb = ret;
}
mutex_unlock(&isl29501->lock);
*val = (msb << 8) + lsb;
return 0;
err:
mutex_unlock(&isl29501->lock);
return ret;
}
static u32 isl29501_register_write(struct isl29501_private *isl29501,
enum isl29501_register_name name,
u32 value)
{
const struct isl29501_register_desc *reg = &isl29501_registers[name];
int ret;
if (!reg->msb && value > U8_MAX)
return -ERANGE;
if (value > U16_MAX)
return -ERANGE;
mutex_lock(&isl29501->lock);
if (reg->msb) {
ret = i2c_smbus_write_byte_data(isl29501->client,
reg->msb, value >> 8);
if (ret < 0)
goto err;
}
ret = i2c_smbus_write_byte_data(isl29501->client, reg->lsb, value);
err:
mutex_unlock(&isl29501->lock);
return ret;
}
static ssize_t isl29501_read_ext(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct isl29501_private *isl29501 = iio_priv(indio_dev);
enum isl29501_register_name reg = private;
int ret;
u32 value, gain, coeff, exp;
switch (reg) {
case REG_GAIN:
case REG_GAIN_BIAS:
ret = isl29501_register_read(isl29501, reg, &gain);
if (ret < 0)
return ret;
value = gain;
break;
case REG_CALIB_PHASE_TEMP_A:
case REG_CALIB_PHASE_TEMP_B:
case REG_CALIB_PHASE_LIGHT_A:
case REG_CALIB_PHASE_LIGHT_B:
ret = isl29501_register_read(isl29501, REG_PHASE_EXP, &exp);
if (ret < 0)
return ret;
ret = isl29501_register_read(isl29501, reg, &coeff);
if (ret < 0)
return ret;
value = coeff << exp;
break;
default:
return -EINVAL;
}
return sprintf(buf, "%u\n", value);
}
static int isl29501_set_shadow_coeff(struct isl29501_private *isl29501,
enum isl29501_register_name reg,
unsigned int val)
{
enum isl29501_correction_coeff coeff;
switch (reg) {
case REG_CALIB_PHASE_TEMP_A:
coeff = COEFF_TEMP_A;
break;
case REG_CALIB_PHASE_TEMP_B:
coeff = COEFF_TEMP_B;
break;
case REG_CALIB_PHASE_LIGHT_A:
coeff = COEFF_LIGHT_A;
break;
case REG_CALIB_PHASE_LIGHT_B:
coeff = COEFF_LIGHT_B;
break;
default:
return -EINVAL;
}
isl29501->shadow_coeffs[coeff] = val;
return 0;
}
static int isl29501_write_coeff(struct isl29501_private *isl29501,
enum isl29501_correction_coeff coeff,
int val)
{
enum isl29501_register_name reg;
switch (coeff) {
case COEFF_TEMP_A:
reg = REG_CALIB_PHASE_TEMP_A;
break;
case COEFF_TEMP_B:
reg = REG_CALIB_PHASE_TEMP_B;
break;
case COEFF_LIGHT_A:
reg = REG_CALIB_PHASE_LIGHT_A;
break;
case COEFF_LIGHT_B:
reg = REG_CALIB_PHASE_LIGHT_B;
break;
default:
return -EINVAL;
}
return isl29501_register_write(isl29501, reg, val);
}
static unsigned int isl29501_find_corr_exp(unsigned int val,
unsigned int max_exp,
unsigned int max_mantissa)
{
unsigned int exp = 1;
/*
* Correction coefficients are represented under
* mantissa * 2^exponent form, where mantissa and exponent
* are stored in two separate registers of the sensor.
*
* Compute and return the lowest exponent such as:
* mantissa = value / 2^exponent
*
* where mantissa < max_mantissa.
*/
if (val <= max_mantissa)
return 0;
while ((val >> exp) > max_mantissa) {
exp++;
if (exp > max_exp)
return max_exp;
}
return exp;
}
static ssize_t isl29501_write_ext(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
const char *buf, size_t len)
{
struct isl29501_private *isl29501 = iio_priv(indio_dev);
enum isl29501_register_name reg = private;
unsigned int val;
int max_exp = 0;
int ret;
int i;
ret = kstrtouint(buf, 10, &val);
if (ret)
return ret;
switch (reg) {
case REG_GAIN_BIAS:
if (val > U16_MAX)
return -ERANGE;
ret = isl29501_register_write(isl29501, reg, val);
if (ret < 0)
return ret;
break;
case REG_CALIB_PHASE_TEMP_A:
case REG_CALIB_PHASE_TEMP_B:
case REG_CALIB_PHASE_LIGHT_A:
case REG_CALIB_PHASE_LIGHT_B:
if (val > (U8_MAX << ISL29501_MAX_EXP_VAL))
return -ERANGE;
/* Store the correction coefficient under its exact form. */
ret = isl29501_set_shadow_coeff(isl29501, reg, val);
if (ret < 0)
return ret;
/*
* Find the highest exponent needed to represent
* correction coefficients.
*/
for (i = 0; i < COEFF_MAX; i++) {
int corr;
int corr_exp;
corr = isl29501->shadow_coeffs[i];
corr_exp = isl29501_find_corr_exp(corr,
ISL29501_MAX_EXP_VAL,
U8_MAX / 2);
dev_dbg(&isl29501->client->dev,
"found exp of corr(%d) = %d\n", corr, corr_exp);
max_exp = max(max_exp, corr_exp);
}
/*
* Represent every correction coefficient under
* mantissa * 2^max_exponent form and force the
* writing of those coefficients on the sensor.
*/
for (i = 0; i < COEFF_MAX; i++) {
int corr;
int mantissa;
corr = isl29501->shadow_coeffs[i];
if (!corr)
continue;
mantissa = corr >> max_exp;
ret = isl29501_write_coeff(isl29501, i, mantissa);
if (ret < 0)
return ret;
}
ret = isl29501_register_write(isl29501, REG_PHASE_EXP, max_exp);
if (ret < 0)
return ret;
break;
default:
return -EINVAL;
}
return len;
}
#define _ISL29501_EXT_INFO(_name, _ident) { \
.name = _name, \
.read = isl29501_read_ext, \
.write = isl29501_write_ext, \
.private = _ident, \
.shared = IIO_SEPARATE, \
}
static const struct iio_chan_spec_ext_info isl29501_ext_info[] = {
_ISL29501_EXT_INFO("agc_gain", REG_GAIN),
_ISL29501_EXT_INFO("agc_gain_bias", REG_GAIN_BIAS),
_ISL29501_EXT_INFO("calib_phase_temp_a", REG_CALIB_PHASE_TEMP_A),
_ISL29501_EXT_INFO("calib_phase_temp_b", REG_CALIB_PHASE_TEMP_B),
_ISL29501_EXT_INFO("calib_phase_light_a", REG_CALIB_PHASE_LIGHT_A),
_ISL29501_EXT_INFO("calib_phase_light_b", REG_CALIB_PHASE_LIGHT_B),
{ },
};
#define ISL29501_DISTANCE_SCAN_INDEX 0
#define ISL29501_TIMESTAMP_SCAN_INDEX 1
static const struct iio_chan_spec isl29501_channels[] = {
{
.type = IIO_PROXIMITY,
.scan_index = ISL29501_DISTANCE_SCAN_INDEX,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_CPU,
},
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
.ext_info = isl29501_ext_info,
},
{
.type = IIO_PHASE,
.scan_index = -1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
{
.type = IIO_CURRENT,
.scan_index = -1,
.output = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
{
.type = IIO_TEMP,
.scan_index = -1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
},
{
.type = IIO_INTENSITY,
.scan_index = -1,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_CLEAR,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
IIO_CHAN_SOFT_TIMESTAMP(ISL29501_TIMESTAMP_SCAN_INDEX),
};
static int isl29501_reset_registers(struct isl29501_private *isl29501)
{
int ret;
ret = i2c_smbus_write_byte_data(isl29501->client,
ISL29501_COMMAND_REGISTER,
ISL29501_RESET_ALL_REGISTERS);
if (ret < 0) {
dev_err(&isl29501->client->dev,
"cannot reset registers %d\n", ret);
return ret;
}
ret = i2c_smbus_write_byte_data(isl29501->client,
ISL29501_COMMAND_REGISTER,
ISL29501_RESET_INT_SM);
if (ret < 0)
dev_err(&isl29501->client->dev,
"cannot reset state machine %d\n", ret);
return ret;
}
static int isl29501_begin_acquisition(struct isl29501_private *isl29501)
{
int ret;
ret = i2c_smbus_write_byte_data(isl29501->client,
ISL29501_COMMAND_REGISTER,
ISL29501_EMUL_SAMPLE_START_PIN);
if (ret < 0)
dev_err(&isl29501->client->dev,
"cannot begin acquisition %d\n", ret);
return ret;
}
static IIO_CONST_ATTR_INT_TIME_AVAIL(ISL29501_INT_TIME_AVAILABLE);
static IIO_CONST_ATTR(out_current_scale_available,
ISL29501_CURRENT_SCALE_AVAILABLE);
static struct attribute *isl29501_attributes[] = {
&iio_const_attr_integration_time_available.dev_attr.attr,
&iio_const_attr_out_current_scale_available.dev_attr.attr,
NULL
};
static const struct attribute_group isl29501_attribute_group = {
.attrs = isl29501_attributes,
};
static const int isl29501_current_scale_table[][2] = {
{0, 3900}, {0, 7800}, {0, 11800}, {0, 15700},
{0, 19600}, {0, 23500}, {0, 27500}, {0, 31400},
{0, 35200}, {0, 39200}, {0, 43100}, {0, 47100},
{0, 51000}, {0, 54900}, {0, 58800},
};
static const int isl29501_int_time[][2] = {
{0, 70}, /* 0.07 ms */
{0, 140}, /* 0.14 ms */
{0, 280}, /* 0.28 ms */
{0, 570}, /* 0.57 ms */
{0, 1140}, /* 1.14 ms */
{0, 2280}, /* 2.28 ms */
{0, 4550}, /* 4.55 ms */
{0, 9100}, /* 9.11 ms */
{0, 18200}, /* 18.2 ms */
{0, 36400}, /* 36.4 ms */
{0, 72810}, /* 72.81 ms */
{0, 145610} /* 145.28 ms */
};
static int isl29501_get_raw(struct isl29501_private *isl29501,
const struct iio_chan_spec *chan,
int *raw)
{
int ret;
switch (chan->type) {
case IIO_PROXIMITY:
ret = isl29501_register_read(isl29501, REG_DISTANCE, raw);
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_INTENSITY:
ret = isl29501_register_read(isl29501,
REG_AMBIENT_LIGHT,
raw);
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_PHASE:
ret = isl29501_register_read(isl29501, REG_PHASE, raw);
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_CURRENT:
ret = isl29501_register_read(isl29501, REG_EMITTER_DAC, raw);
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_TEMP:
ret = isl29501_register_read(isl29501, REG_TEMPERATURE, raw);
if (ret < 0)
return ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int isl29501_get_scale(struct isl29501_private *isl29501,
const struct iio_chan_spec *chan,
int *val, int *val2)
{
int ret;
u32 current_scale;
switch (chan->type) {
case IIO_PROXIMITY:
/* distance = raw_distance * 33.31 / 65536 (m) */
*val = 3331;
*val2 = 6553600;
return IIO_VAL_FRACTIONAL;
case IIO_PHASE:
/* phase = raw_phase * 2pi / 65536 (rad) */
*val = 0;
*val2 = 95874;
return IIO_VAL_INT_PLUS_NANO;
case IIO_INTENSITY:
/* light = raw_light * 35 / 10000 (mA) */
*val = 35;
*val2 = 10000;
return IIO_VAL_FRACTIONAL;
case IIO_CURRENT:
ret = isl29501_register_read(isl29501,
REG_DRIVER_RANGE,
¤t_scale);
if (ret < 0)
return ret;
if (current_scale > ARRAY_SIZE(isl29501_current_scale_table))
return -EINVAL;
if (!current_scale) {
*val = 0;
*val2 = 0;
return IIO_VAL_INT;
}
*val = isl29501_current_scale_table[current_scale - 1][0];
*val2 = isl29501_current_scale_table[current_scale - 1][1];
return IIO_VAL_INT_PLUS_MICRO;
case IIO_TEMP:
/* temperature = raw_temperature * 125 / 100000 (milli °C) */
*val = 125;
*val2 = 100000;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
}
static int isl29501_get_calibbias(struct isl29501_private *isl29501,
const struct iio_chan_spec *chan,
int *bias)
{
switch (chan->type) {
case IIO_PROXIMITY:
return isl29501_register_read(isl29501,
REG_DISTANCE_BIAS,
bias);
case IIO_TEMP:
return isl29501_register_read(isl29501,
REG_TEMPERATURE_BIAS,
bias);
default:
return -EINVAL;
}
}
static int isl29501_get_inttime(struct isl29501_private *isl29501,
int *val, int *val2)
{
int ret;
u32 inttime;
ret = isl29501_register_read(isl29501, REG_INT_TIME, &inttime);
if (ret < 0)
return ret;
if (inttime >= ARRAY_SIZE(isl29501_int_time))
return -EINVAL;
*val = isl29501_int_time[inttime][0];
*val2 = isl29501_int_time[inttime][1];
return IIO_VAL_INT_PLUS_MICRO;
}
static int isl29501_get_freq(struct isl29501_private *isl29501,
int *val, int *val2)
{
int ret;
int sample_time;
unsigned long long freq;
u32 temp;
ret = isl29501_register_read(isl29501, REG_SAMPLE_TIME, &sample_time);
if (ret < 0)
return ret;
/* freq = 1 / (0.000450 * (sample_time + 1) * 10^-6) */
freq = 1000000ULL * 1000000ULL;
do_div(freq, 450 * (sample_time + 1));
temp = do_div(freq, 1000000);
*val = freq;
*val2 = temp;
return IIO_VAL_INT_PLUS_MICRO;
}
static int isl29501_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct isl29501_private *isl29501 = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
return isl29501_get_raw(isl29501, chan, val);
case IIO_CHAN_INFO_SCALE:
return isl29501_get_scale(isl29501, chan, val, val2);
case IIO_CHAN_INFO_INT_TIME:
return isl29501_get_inttime(isl29501, val, val2);
case IIO_CHAN_INFO_SAMP_FREQ:
return isl29501_get_freq(isl29501, val, val2);
case IIO_CHAN_INFO_CALIBBIAS:
return isl29501_get_calibbias(isl29501, chan, val);
default:
return -EINVAL;
}
}
static int isl29501_set_raw(struct isl29501_private *isl29501,
const struct iio_chan_spec *chan,
int raw)
{
switch (chan->type) {
case IIO_CURRENT:
return isl29501_register_write(isl29501, REG_EMITTER_DAC, raw);
default:
return -EINVAL;
}
}
static int isl29501_set_inttime(struct isl29501_private *isl29501,
int val, int val2)
{
int i;
for (i = 0; i < ARRAY_SIZE(isl29501_int_time); i++) {
if (isl29501_int_time[i][0] == val &&
isl29501_int_time[i][1] == val2) {
return isl29501_register_write(isl29501,
REG_INT_TIME,
i);
}
}
return -EINVAL;
}
static int isl29501_set_scale(struct isl29501_private *isl29501,
const struct iio_chan_spec *chan,
int val, int val2)
{
int i;
if (chan->type != IIO_CURRENT)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(isl29501_current_scale_table); i++) {
if (isl29501_current_scale_table[i][0] == val &&
isl29501_current_scale_table[i][1] == val2) {
return isl29501_register_write(isl29501,
REG_DRIVER_RANGE,
i + 1);
}
}
return -EINVAL;
}
static int isl29501_set_calibbias(struct isl29501_private *isl29501,
const struct iio_chan_spec *chan,
int bias)
{
switch (chan->type) {
case IIO_PROXIMITY:
return isl29501_register_write(isl29501,
REG_DISTANCE_BIAS,
bias);
case IIO_TEMP:
return isl29501_register_write(isl29501,
REG_TEMPERATURE_BIAS,
bias);
default:
return -EINVAL;
}
}
static int isl29501_set_freq(struct isl29501_private *isl29501,
int val, int val2)
{
int freq;
unsigned long long sample_time;
/* sample_freq = 1 / (0.000450 * (sample_time + 1) * 10^-6) */
freq = val * 1000000 + val2 % 1000000;
sample_time = 2222ULL * 1000000ULL;
do_div(sample_time, freq);
sample_time -= 1;
if (sample_time > 255)
return -ERANGE;
return isl29501_register_write(isl29501, REG_SAMPLE_TIME, sample_time);
}
static int isl29501_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct isl29501_private *isl29501 = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
return isl29501_set_raw(isl29501, chan, val);
case IIO_CHAN_INFO_INT_TIME:
return isl29501_set_inttime(isl29501, val, val2);
case IIO_CHAN_INFO_SAMP_FREQ:
return isl29501_set_freq(isl29501, val, val2);
case IIO_CHAN_INFO_SCALE:
return isl29501_set_scale(isl29501, chan, val, val2);
case IIO_CHAN_INFO_CALIBBIAS:
return isl29501_set_calibbias(isl29501, chan, val);
default:
return -EINVAL;
}
}
static const struct iio_info isl29501_info = {
.read_raw = &isl29501_read_raw,
.write_raw = &isl29501_write_raw,
.attrs = &isl29501_attribute_group,
};
static int isl29501_init_chip(struct isl29501_private *isl29501)
{
int ret;
ret = i2c_smbus_read_byte_data(isl29501->client, ISL29501_DEVICE_ID);
if (ret < 0) {
dev_err(&isl29501->client->dev, "Error reading device id\n");
return ret;
}
if (ret != ISL29501_ID) {
dev_err(&isl29501->client->dev,
"Wrong chip id, got %x expected %x\n",
ret, ISL29501_DEVICE_ID);
return -ENODEV;
}
ret = isl29501_reset_registers(isl29501);
if (ret < 0)
return ret;
return isl29501_begin_acquisition(isl29501);
}
static irqreturn_t isl29501_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct isl29501_private *isl29501 = iio_priv(indio_dev);
const unsigned long *active_mask = indio_dev->active_scan_mask;
u32 buffer[4] __aligned(8) = {}; /* 1x16-bit + naturally aligned ts */
if (test_bit(ISL29501_DISTANCE_SCAN_INDEX, active_mask))
isl29501_register_read(isl29501, REG_DISTANCE, buffer);
iio_push_to_buffers_with_timestamp(indio_dev, buffer, pf->timestamp);
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int isl29501_probe(struct i2c_client *client)
{
struct iio_dev *indio_dev;
struct isl29501_private *isl29501;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*isl29501));
if (!indio_dev)
return -ENOMEM;
isl29501 = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
isl29501->client = client;
mutex_init(&isl29501->lock);
ret = isl29501_init_chip(isl29501);
if (ret < 0)
return ret;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = isl29501_channels;
indio_dev->num_channels = ARRAY_SIZE(isl29501_channels);
indio_dev->name = client->name;
indio_dev->info = &isl29501_info;
ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev,
iio_pollfunc_store_time,
isl29501_trigger_handler,
NULL);
if (ret < 0) {
dev_err(&client->dev, "unable to setup iio triggered buffer\n");
return ret;
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id isl29501_id[] = {
{"isl29501", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, isl29501_id);
#if defined(CONFIG_OF)
static const struct of_device_id isl29501_i2c_matches[] = {
{ .compatible = "renesas,isl29501" },
{ }
};
MODULE_DEVICE_TABLE(of, isl29501_i2c_matches);
#endif
static struct i2c_driver isl29501_driver = {
.driver = {
.name = "isl29501",
},
.id_table = isl29501_id,
.probe = isl29501_probe,
};
module_i2c_driver(isl29501_driver);
MODULE_AUTHOR("Mathieu Othacehe <[email protected]>");
MODULE_DESCRIPTION("ISL29501 Time of Flight sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/proximity/isl29501.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SRF04: ultrasonic sensor for distance measuring by using GPIOs
*
* Copyright (c) 2017 Andreas Klinger <[email protected]>
*
* For details about the device see:
* https://www.robot-electronics.co.uk/htm/srf04tech.htm
*
* the measurement cycle as timing diagram looks like:
*
* +---+
* GPIO | |
* trig: --+ +------------------------------------------------------
* ^ ^
* |<->|
* udelay(trigger_pulse_us)
*
* ultra +-+ +-+ +-+
* sonic | | | | | |
* burst: ---------+ +-+ +-+ +-----------------------------------------
* .
* ultra . +-+ +-+ +-+
* sonic . | | | | | |
* echo: ----------------------------------+ +-+ +-+ +----------------
* . .
* +------------------------+
* GPIO | |
* echo: -------------------+ +---------------
* ^ ^
* interrupt interrupt
* (ts_rising) (ts_falling)
* |<---------------------->|
* pulse time measured
* --> one round trip of ultra sonic waves
*/
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
struct srf04_cfg {
unsigned long trigger_pulse_us;
};
struct srf04_data {
struct device *dev;
struct gpio_desc *gpiod_trig;
struct gpio_desc *gpiod_echo;
struct gpio_desc *gpiod_power;
struct mutex lock;
int irqnr;
ktime_t ts_rising;
ktime_t ts_falling;
struct completion rising;
struct completion falling;
const struct srf04_cfg *cfg;
int startup_time_ms;
};
static const struct srf04_cfg srf04_cfg = {
.trigger_pulse_us = 10,
};
static const struct srf04_cfg mb_lv_cfg = {
.trigger_pulse_us = 20,
};
static irqreturn_t srf04_handle_irq(int irq, void *dev_id)
{
struct iio_dev *indio_dev = dev_id;
struct srf04_data *data = iio_priv(indio_dev);
ktime_t now = ktime_get();
if (gpiod_get_value(data->gpiod_echo)) {
data->ts_rising = now;
complete(&data->rising);
} else {
data->ts_falling = now;
complete(&data->falling);
}
return IRQ_HANDLED;
}
static int srf04_read(struct srf04_data *data)
{
int ret;
ktime_t ktime_dt;
u64 dt_ns;
u32 time_ns, distance_mm;
if (data->gpiod_power) {
ret = pm_runtime_resume_and_get(data->dev);
if (ret < 0)
return ret;
}
/*
* just one read-echo-cycle can take place at a time
* ==> lock against concurrent reading calls
*/
mutex_lock(&data->lock);
reinit_completion(&data->rising);
reinit_completion(&data->falling);
gpiod_set_value(data->gpiod_trig, 1);
udelay(data->cfg->trigger_pulse_us);
gpiod_set_value(data->gpiod_trig, 0);
if (data->gpiod_power) {
pm_runtime_mark_last_busy(data->dev);
pm_runtime_put_autosuspend(data->dev);
}
/* it should not take more than 20 ms until echo is rising */
ret = wait_for_completion_killable_timeout(&data->rising, HZ/50);
if (ret < 0) {
mutex_unlock(&data->lock);
return ret;
} else if (ret == 0) {
mutex_unlock(&data->lock);
return -ETIMEDOUT;
}
/* it cannot take more than 50 ms until echo is falling */
ret = wait_for_completion_killable_timeout(&data->falling, HZ/20);
if (ret < 0) {
mutex_unlock(&data->lock);
return ret;
} else if (ret == 0) {
mutex_unlock(&data->lock);
return -ETIMEDOUT;
}
ktime_dt = ktime_sub(data->ts_falling, data->ts_rising);
mutex_unlock(&data->lock);
dt_ns = ktime_to_ns(ktime_dt);
/*
* measuring more than 6,45 meters is beyond the capabilities of
* the supported sensors
* ==> filter out invalid results for not measuring echos of
* another us sensor
*
* formula:
* distance 6,45 * 2 m
* time = ---------- = ------------ = 40438871 ns
* speed 319 m/s
*
* using a minimum speed at -20 °C of 319 m/s
*/
if (dt_ns > 40438871)
return -EIO;
time_ns = dt_ns;
/*
* the speed as function of the temperature is approximately:
*
* speed = 331,5 + 0,6 * Temp
* with Temp in °C
* and speed in m/s
*
* use 343,5 m/s as ultrasonic speed at 20 °C here in absence of the
* temperature
*
* therefore:
* time 343,5 time * 106
* distance = ------ * ------- = ------------
* 10^6 2 617176
* with time in ns
* and distance in mm (one way)
*
* because we limit to 6,45 meters the multiplication with 106 just
* fits into 32 bit
*/
distance_mm = time_ns * 106 / 617176;
return distance_mm;
}
static int srf04_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long info)
{
struct srf04_data *data = iio_priv(indio_dev);
int ret;
if (channel->type != IIO_DISTANCE)
return -EINVAL;
switch (info) {
case IIO_CHAN_INFO_RAW:
ret = srf04_read(data);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/*
* theoretical maximum resolution is 3 mm
* 1 LSB is 1 mm
*/
*val = 0;
*val2 = 1000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static const struct iio_info srf04_iio_info = {
.read_raw = srf04_read_raw,
};
static const struct iio_chan_spec srf04_chan_spec[] = {
{
.type = IIO_DISTANCE,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
};
static const struct of_device_id of_srf04_match[] = {
{ .compatible = "devantech,srf04", .data = &srf04_cfg },
{ .compatible = "maxbotix,mb1000", .data = &mb_lv_cfg },
{ .compatible = "maxbotix,mb1010", .data = &mb_lv_cfg },
{ .compatible = "maxbotix,mb1020", .data = &mb_lv_cfg },
{ .compatible = "maxbotix,mb1030", .data = &mb_lv_cfg },
{ .compatible = "maxbotix,mb1040", .data = &mb_lv_cfg },
{},
};
MODULE_DEVICE_TABLE(of, of_srf04_match);
static int srf04_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct srf04_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(struct srf04_data));
if (!indio_dev) {
dev_err(dev, "failed to allocate IIO device\n");
return -ENOMEM;
}
data = iio_priv(indio_dev);
data->dev = dev;
data->cfg = device_get_match_data(dev);
mutex_init(&data->lock);
init_completion(&data->rising);
init_completion(&data->falling);
data->gpiod_trig = devm_gpiod_get(dev, "trig", GPIOD_OUT_LOW);
if (IS_ERR(data->gpiod_trig)) {
dev_err(dev, "failed to get trig-gpios: err=%ld\n",
PTR_ERR(data->gpiod_trig));
return PTR_ERR(data->gpiod_trig);
}
data->gpiod_echo = devm_gpiod_get(dev, "echo", GPIOD_IN);
if (IS_ERR(data->gpiod_echo)) {
dev_err(dev, "failed to get echo-gpios: err=%ld\n",
PTR_ERR(data->gpiod_echo));
return PTR_ERR(data->gpiod_echo);
}
data->gpiod_power = devm_gpiod_get_optional(dev, "power",
GPIOD_OUT_LOW);
if (IS_ERR(data->gpiod_power)) {
dev_err(dev, "failed to get power-gpios: err=%ld\n",
PTR_ERR(data->gpiod_power));
return PTR_ERR(data->gpiod_power);
}
if (data->gpiod_power) {
data->startup_time_ms = 100;
device_property_read_u32(dev, "startup-time-ms", &data->startup_time_ms);
dev_dbg(dev, "using power gpio: startup-time-ms=%d\n",
data->startup_time_ms);
}
if (gpiod_cansleep(data->gpiod_echo)) {
dev_err(data->dev, "cansleep-GPIOs not supported\n");
return -ENODEV;
}
data->irqnr = gpiod_to_irq(data->gpiod_echo);
if (data->irqnr < 0) {
dev_err(data->dev, "gpiod_to_irq: %d\n", data->irqnr);
return data->irqnr;
}
ret = devm_request_irq(dev, data->irqnr, srf04_handle_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
pdev->name, indio_dev);
if (ret < 0) {
dev_err(data->dev, "request_irq: %d\n", ret);
return ret;
}
platform_set_drvdata(pdev, indio_dev);
indio_dev->name = "srf04";
indio_dev->info = &srf04_iio_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = srf04_chan_spec;
indio_dev->num_channels = ARRAY_SIZE(srf04_chan_spec);
ret = iio_device_register(indio_dev);
if (ret < 0) {
dev_err(data->dev, "iio_device_register: %d\n", ret);
return ret;
}
if (data->gpiod_power) {
pm_runtime_set_autosuspend_delay(data->dev, 1000);
pm_runtime_use_autosuspend(data->dev);
ret = pm_runtime_set_active(data->dev);
if (ret) {
dev_err(data->dev, "pm_runtime_set_active: %d\n", ret);
iio_device_unregister(indio_dev);
}
pm_runtime_enable(data->dev);
pm_runtime_idle(data->dev);
}
return ret;
}
static int srf04_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct srf04_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (data->gpiod_power) {
pm_runtime_disable(data->dev);
pm_runtime_set_suspended(data->dev);
}
return 0;
}
static int srf04_pm_runtime_suspend(struct device *dev)
{
struct platform_device *pdev = container_of(dev,
struct platform_device, dev);
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct srf04_data *data = iio_priv(indio_dev);
gpiod_set_value(data->gpiod_power, 0);
return 0;
}
static int srf04_pm_runtime_resume(struct device *dev)
{
struct platform_device *pdev = container_of(dev,
struct platform_device, dev);
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct srf04_data *data = iio_priv(indio_dev);
gpiod_set_value(data->gpiod_power, 1);
msleep(data->startup_time_ms);
return 0;
}
static const struct dev_pm_ops srf04_pm_ops = {
RUNTIME_PM_OPS(srf04_pm_runtime_suspend,
srf04_pm_runtime_resume, NULL)
};
static struct platform_driver srf04_driver = {
.probe = srf04_probe,
.remove = srf04_remove,
.driver = {
.name = "srf04-gpio",
.of_match_table = of_srf04_match,
.pm = pm_ptr(&srf04_pm_ops),
},
};
module_platform_driver(srf04_driver);
MODULE_AUTHOR("Andreas Klinger <[email protected]>");
MODULE_DESCRIPTION("SRF04 ultrasonic sensor for distance measuring using GPIOs");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:srf04");
| linux-master | drivers/iio/proximity/srf04.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Support for ST VL53L0X FlightSense ToF Ranging Sensor on a i2c bus.
*
* Copyright (C) 2016 STMicroelectronics Imaging Division.
* Copyright (C) 2018 Song Qiang <[email protected]>
* Copyright (C) 2020 Ivan Drobyshevskyi <[email protected]>
*
* Datasheet available at
* <https://www.st.com/resource/en/datasheet/vl53l0x.pdf>
*
* Default 7-bit i2c slave address 0x29.
*
* TODO: FIFO buffer, continuous mode, range selection, sensor ID check.
*/
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#define VL_REG_SYSRANGE_START 0x00
#define VL_REG_SYSRANGE_MODE_MASK GENMASK(3, 0)
#define VL_REG_SYSRANGE_MODE_SINGLESHOT 0x00
#define VL_REG_SYSRANGE_MODE_START_STOP BIT(0)
#define VL_REG_SYSRANGE_MODE_BACKTOBACK BIT(1)
#define VL_REG_SYSRANGE_MODE_TIMED BIT(2)
#define VL_REG_SYSRANGE_MODE_HISTOGRAM BIT(3)
#define VL_REG_SYSTEM_INTERRUPT_CONFIG_GPIO 0x0A
#define VL_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY BIT(2)
#define VL_REG_SYSTEM_INTERRUPT_CLEAR 0x0B
#define VL_REG_RESULT_INT_STATUS 0x13
#define VL_REG_RESULT_RANGE_STATUS 0x14
#define VL_REG_RESULT_RANGE_STATUS_COMPLETE BIT(0)
struct vl53l0x_data {
struct i2c_client *client;
struct completion completion;
struct regulator *vdd_supply;
struct gpio_desc *reset_gpio;
};
static irqreturn_t vl53l0x_handle_irq(int irq, void *priv)
{
struct iio_dev *indio_dev = priv;
struct vl53l0x_data *data = iio_priv(indio_dev);
complete(&data->completion);
return IRQ_HANDLED;
}
static int vl53l0x_configure_irq(struct i2c_client *client,
struct iio_dev *indio_dev)
{
int irq_flags = irq_get_trigger_type(client->irq);
struct vl53l0x_data *data = iio_priv(indio_dev);
int ret;
if (!irq_flags)
irq_flags = IRQF_TRIGGER_FALLING;
ret = devm_request_irq(&client->dev, client->irq, vl53l0x_handle_irq,
irq_flags, indio_dev->name, indio_dev);
if (ret) {
dev_err(&client->dev, "devm_request_irq error: %d\n", ret);
return ret;
}
ret = i2c_smbus_write_byte_data(data->client,
VL_REG_SYSTEM_INTERRUPT_CONFIG_GPIO,
VL_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY);
if (ret < 0)
dev_err(&client->dev, "failed to configure IRQ: %d\n", ret);
return ret;
}
static void vl53l0x_clear_irq(struct vl53l0x_data *data)
{
struct device *dev = &data->client->dev;
int ret;
ret = i2c_smbus_write_byte_data(data->client,
VL_REG_SYSTEM_INTERRUPT_CLEAR, 1);
if (ret < 0)
dev_err(dev, "failed to clear error irq: %d\n", ret);
ret = i2c_smbus_write_byte_data(data->client,
VL_REG_SYSTEM_INTERRUPT_CLEAR, 0);
if (ret < 0)
dev_err(dev, "failed to clear range irq: %d\n", ret);
ret = i2c_smbus_read_byte_data(data->client, VL_REG_RESULT_INT_STATUS);
if (ret < 0 || ret & 0x07)
dev_err(dev, "failed to clear irq: %d\n", ret);
}
static int vl53l0x_read_proximity(struct vl53l0x_data *data,
const struct iio_chan_spec *chan,
int *val)
{
struct i2c_client *client = data->client;
u16 tries = 20;
u8 buffer[12];
int ret;
unsigned long time_left;
ret = i2c_smbus_write_byte_data(client, VL_REG_SYSRANGE_START, 1);
if (ret < 0)
return ret;
if (data->client->irq) {
reinit_completion(&data->completion);
time_left = wait_for_completion_timeout(&data->completion, HZ/10);
if (time_left == 0)
return -ETIMEDOUT;
vl53l0x_clear_irq(data);
} else {
do {
ret = i2c_smbus_read_byte_data(client,
VL_REG_RESULT_RANGE_STATUS);
if (ret < 0)
return ret;
if (ret & VL_REG_RESULT_RANGE_STATUS_COMPLETE)
break;
usleep_range(1000, 5000);
} while (--tries);
if (!tries)
return -ETIMEDOUT;
}
ret = i2c_smbus_read_i2c_block_data(client, VL_REG_RESULT_RANGE_STATUS,
12, buffer);
if (ret < 0)
return ret;
else if (ret != 12)
return -EREMOTEIO;
/* Values should be between 30~1200 in millimeters. */
*val = (buffer[10] << 8) + buffer[11];
return 0;
}
static const struct iio_chan_spec vl53l0x_channels[] = {
{
.type = IIO_DISTANCE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
};
static int vl53l0x_read_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
int *val, int *val2, long mask)
{
struct vl53l0x_data *data = iio_priv(indio_dev);
int ret;
if (chan->type != IIO_DISTANCE)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = vl53l0x_read_proximity(data, chan, val);
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 0;
*val2 = 1000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static const struct iio_info vl53l0x_info = {
.read_raw = vl53l0x_read_raw,
};
static void vl53l0x_power_off(void *_data)
{
struct vl53l0x_data *data = _data;
gpiod_set_value_cansleep(data->reset_gpio, 1);
regulator_disable(data->vdd_supply);
}
static int vl53l0x_power_on(struct vl53l0x_data *data)
{
int ret;
ret = regulator_enable(data->vdd_supply);
if (ret)
return ret;
gpiod_set_value_cansleep(data->reset_gpio, 0);
usleep_range(3200, 5000);
return 0;
}
static int vl53l0x_probe(struct i2c_client *client)
{
struct vl53l0x_data *data;
struct iio_dev *indio_dev;
int error;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->client = client;
i2c_set_clientdata(client, indio_dev);
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_READ_I2C_BLOCK |
I2C_FUNC_SMBUS_BYTE_DATA))
return -EOPNOTSUPP;
data->vdd_supply = devm_regulator_get(&client->dev, "vdd");
if (IS_ERR(data->vdd_supply))
return dev_err_probe(&client->dev, PTR_ERR(data->vdd_supply),
"Unable to get VDD regulator\n");
data->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(data->reset_gpio))
return dev_err_probe(&client->dev, PTR_ERR(data->reset_gpio),
"Cannot get reset GPIO\n");
error = vl53l0x_power_on(data);
if (error)
return dev_err_probe(&client->dev, error,
"Failed to power on the chip\n");
error = devm_add_action_or_reset(&client->dev, vl53l0x_power_off, data);
if (error)
return dev_err_probe(&client->dev, error,
"Failed to install poweroff action\n");
indio_dev->name = "vl53l0x";
indio_dev->info = &vl53l0x_info;
indio_dev->channels = vl53l0x_channels;
indio_dev->num_channels = ARRAY_SIZE(vl53l0x_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
/* usage of interrupt is optional */
if (client->irq) {
int ret;
init_completion(&data->completion);
ret = vl53l0x_configure_irq(client, indio_dev);
if (ret)
return ret;
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id vl53l0x_id[] = {
{ "vl53l0x", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, vl53l0x_id);
static const struct of_device_id st_vl53l0x_dt_match[] = {
{ .compatible = "st,vl53l0x", },
{ }
};
MODULE_DEVICE_TABLE(of, st_vl53l0x_dt_match);
static struct i2c_driver vl53l0x_driver = {
.driver = {
.name = "vl53l0x-i2c",
.of_match_table = st_vl53l0x_dt_match,
},
.probe = vl53l0x_probe,
.id_table = vl53l0x_id,
};
module_i2c_driver(vl53l0x_driver);
MODULE_AUTHOR("Song Qiang <[email protected]>");
MODULE_DESCRIPTION("ST vl53l0x ToF ranging sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/proximity/vl53l0x-i2c.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2021 Google LLC.
*
* Driver for Semtech's SX9360 capacitive proximity/button solution.
* Based on SX9360 driver and copy of datasheet at:
* https://edit.wpgdadawant.com/uploads/news_file/program/2019/30184/tech_files/program_30184_suggest_other_file.pdf
*/
#include <linux/acpi.h>
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include "sx_common.h"
/* Nominal Oscillator Frequency. */
#define SX9360_FOSC_MHZ 4
#define SX9360_FOSC_HZ (SX9360_FOSC_MHZ * 1000000)
/* Register definitions. */
#define SX9360_REG_IRQ_SRC SX_COMMON_REG_IRQ_SRC
#define SX9360_REG_STAT 0x01
#define SX9360_REG_STAT_COMPSTAT_MASK GENMASK(2, 1)
#define SX9360_REG_IRQ_MSK 0x02
#define SX9360_CONVDONE_IRQ BIT(0)
#define SX9360_FAR_IRQ BIT(2)
#define SX9360_CLOSE_IRQ BIT(3)
#define SX9360_REG_IRQ_CFG 0x03
#define SX9360_REG_GNRL_CTRL0 0x10
#define SX9360_REG_GNRL_CTRL0_PHEN_MASK GENMASK(1, 0)
#define SX9360_REG_GNRL_CTRL1 0x11
#define SX9360_REG_GNRL_CTRL1_SCANPERIOD_MASK GENMASK(2, 0)
#define SX9360_REG_GNRL_CTRL2 0x12
#define SX9360_REG_GNRL_CTRL2_PERIOD_102MS 0x32
#define SX9360_REG_GNRL_REG_2_PERIOD_MS(_r) \
(((_r) * 8192) / (SX9360_FOSC_HZ / 1000))
#define SX9360_REG_GNRL_FREQ_2_REG(_f) (((_f) * 8192) / SX9360_FOSC_HZ)
#define SX9360_REG_GNRL_REG_2_FREQ(_r) (SX9360_FOSC_HZ / ((_r) * 8192))
#define SX9360_REG_AFE_CTRL1 0x21
#define SX9360_REG_AFE_CTRL1_RESFILTIN_MASK GENMASK(3, 0)
#define SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS 0
#define SX9360_REG_AFE_PARAM0_PHR 0x22
#define SX9360_REG_AFE_PARAM1_PHR 0x23
#define SX9360_REG_AFE_PARAM0_PHM 0x24
#define SX9360_REG_AFE_PARAM0_RSVD 0x08
#define SX9360_REG_AFE_PARAM0_RESOLUTION_MASK GENMASK(2, 0)
#define SX9360_REG_AFE_PARAM0_RESOLUTION_128 0x02
#define SX9360_REG_AFE_PARAM1_PHM 0x25
#define SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF 0x40
#define SX9360_REG_AFE_PARAM1_FREQ_83_33HZ 0x06
#define SX9360_REG_PROX_CTRL0_PHR 0x40
#define SX9360_REG_PROX_CTRL0_PHM 0x41
#define SX9360_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3)
#define SX9360_REG_PROX_CTRL0_GAIN_1 0x80
#define SX9360_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0)
#define SX9360_REG_PROX_CTRL0_RAWFILT_1P50 0x01
#define SX9360_REG_PROX_CTRL1 0x42
#define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_MASK GENMASK(5, 3)
#define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_16K 0x20
#define SX9360_REG_PROX_CTRL2 0x43
#define SX9360_REG_PROX_CTRL2_AVGDEB_MASK GENMASK(7, 6)
#define SX9360_REG_PROX_CTRL2_AVGDEB_2SAMPLES 0x40
#define SX9360_REG_PROX_CTRL2_AVGPOS_THRESH_16K 0x20
#define SX9360_REG_PROX_CTRL3 0x44
#define SX9360_REG_PROX_CTRL3_AVGNEG_FILT_MASK GENMASK(5, 3)
#define SX9360_REG_PROX_CTRL3_AVGNEG_FILT_2 0x08
#define SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK GENMASK(2, 0)
#define SX9360_REG_PROX_CTRL3_AVGPOS_FILT_256 0x04
#define SX9360_REG_PROX_CTRL4 0x45
#define SX9360_REG_PROX_CTRL4_HYST_MASK GENMASK(5, 4)
#define SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK GENMASK(3, 2)
#define SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK GENMASK(1, 0)
#define SX9360_REG_PROX_CTRL5 0x46
#define SX9360_REG_PROX_CTRL5_PROXTHRESH_32 0x08
#define SX9360_REG_REF_CORR0 0x60
#define SX9360_REG_REF_CORR1 0x61
#define SX9360_REG_USEFUL_PHR_MSB 0x90
#define SX9360_REG_USEFUL_PHR_LSB 0x91
#define SX9360_REG_OFFSET_PMR_MSB 0x92
#define SX9360_REG_OFFSET_PMR_LSB 0x93
#define SX9360_REG_USEFUL_PHM_MSB 0x94
#define SX9360_REG_USEFUL_PHM_LSB 0x95
#define SX9360_REG_AVG_PHM_MSB 0x96
#define SX9360_REG_AVG_PHM_LSB 0x97
#define SX9360_REG_DIFF_PHM_MSB 0x98
#define SX9360_REG_DIFF_PHM_LSB 0x99
#define SX9360_REG_OFFSET_PHM_MSB 0x9a
#define SX9360_REG_OFFSET_PHM_LSB 0x9b
#define SX9360_REG_USE_FILTER_MSB 0x9a
#define SX9360_REG_USE_FILTER_LSB 0x9b
#define SX9360_REG_RESET 0xcf
/* Write this to REG_RESET to do a soft reset. */
#define SX9360_SOFT_RESET 0xde
#define SX9360_REG_WHOAMI 0xfa
#define SX9360_WHOAMI_VALUE 0x60
#define SX9360_REG_REVISION 0xfe
/* 2 channels, Phase Reference and Measurement. */
#define SX9360_NUM_CHANNELS 2
static const struct iio_chan_spec sx9360_channels[] = {
{
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_HARDWAREGAIN),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_HARDWAREGAIN),
.info_mask_shared_by_all_available =
BIT(IIO_CHAN_INFO_SAMP_FREQ),
.indexed = 1,
.address = SX9360_REG_USEFUL_PHR_MSB,
.channel = 0,
.scan_index = 0,
.scan_type = {
.sign = 's',
.realbits = 12,
.storagebits = 16,
.endianness = IIO_BE,
},
},
{
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_HARDWAREGAIN),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_HARDWAREGAIN),
.info_mask_shared_by_all_available =
BIT(IIO_CHAN_INFO_SAMP_FREQ),
.indexed = 1,
.address = SX9360_REG_USEFUL_PHM_MSB,
.event_spec = sx_common_events,
.num_event_specs = ARRAY_SIZE(sx_common_events),
.channel = 1,
.scan_index = 1,
.scan_type = {
.sign = 's',
.realbits = 12,
.storagebits = 16,
.endianness = IIO_BE,
},
},
IIO_CHAN_SOFT_TIMESTAMP(2),
};
/*
* Each entry contains the integer part (val) and the fractional part, in micro
* seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO.
*
* The frequency control register holds the period, with a ~2ms increment.
* Therefore the smallest frequency is 4MHz / (2047 * 8192),
* The fastest is 4MHz / 8192.
* The interval is not linear, but given there is 2047 possible value,
* Returns the fake increment of (Max-Min)/2047
*/
static const struct {
int val;
int val2;
} sx9360_samp_freq_interval[] = {
{ 0, 281250 }, /* 4MHz / (8192 * 2047) */
{ 0, 281250 },
{ 448, 281250 }, /* 4MHz / 8192 */
};
static const struct regmap_range sx9360_writable_reg_ranges[] = {
/*
* To set COMPSTAT for compensation, even if datasheet says register is
* RO.
*/
regmap_reg_range(SX9360_REG_STAT, SX9360_REG_IRQ_CFG),
regmap_reg_range(SX9360_REG_GNRL_CTRL0, SX9360_REG_GNRL_CTRL2),
regmap_reg_range(SX9360_REG_AFE_CTRL1, SX9360_REG_AFE_PARAM1_PHM),
regmap_reg_range(SX9360_REG_PROX_CTRL0_PHR, SX9360_REG_PROX_CTRL5),
regmap_reg_range(SX9360_REG_REF_CORR0, SX9360_REG_REF_CORR1),
regmap_reg_range(SX9360_REG_OFFSET_PMR_MSB, SX9360_REG_OFFSET_PMR_LSB),
regmap_reg_range(SX9360_REG_RESET, SX9360_REG_RESET),
};
static const struct regmap_access_table sx9360_writeable_regs = {
.yes_ranges = sx9360_writable_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(sx9360_writable_reg_ranges),
};
/*
* All allocated registers are readable, so we just list unallocated
* ones.
*/
static const struct regmap_range sx9360_non_readable_reg_ranges[] = {
regmap_reg_range(SX9360_REG_IRQ_CFG + 1, SX9360_REG_GNRL_CTRL0 - 1),
regmap_reg_range(SX9360_REG_GNRL_CTRL2 + 1, SX9360_REG_AFE_CTRL1 - 1),
regmap_reg_range(SX9360_REG_AFE_PARAM1_PHM + 1,
SX9360_REG_PROX_CTRL0_PHR - 1),
regmap_reg_range(SX9360_REG_PROX_CTRL5 + 1, SX9360_REG_REF_CORR0 - 1),
regmap_reg_range(SX9360_REG_REF_CORR1 + 1,
SX9360_REG_USEFUL_PHR_MSB - 1),
regmap_reg_range(SX9360_REG_USE_FILTER_LSB + 1, SX9360_REG_RESET - 1),
regmap_reg_range(SX9360_REG_RESET + 1, SX9360_REG_WHOAMI - 1),
regmap_reg_range(SX9360_REG_WHOAMI + 1, SX9360_REG_REVISION - 1),
};
static const struct regmap_access_table sx9360_readable_regs = {
.no_ranges = sx9360_non_readable_reg_ranges,
.n_no_ranges = ARRAY_SIZE(sx9360_non_readable_reg_ranges),
};
static const struct regmap_range sx9360_volatile_reg_ranges[] = {
regmap_reg_range(SX9360_REG_IRQ_SRC, SX9360_REG_STAT),
regmap_reg_range(SX9360_REG_USEFUL_PHR_MSB, SX9360_REG_USE_FILTER_LSB),
regmap_reg_range(SX9360_REG_WHOAMI, SX9360_REG_WHOAMI),
regmap_reg_range(SX9360_REG_REVISION, SX9360_REG_REVISION),
};
static const struct regmap_access_table sx9360_volatile_regs = {
.yes_ranges = sx9360_volatile_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(sx9360_volatile_reg_ranges),
};
static const struct regmap_config sx9360_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = SX9360_REG_REVISION,
.cache_type = REGCACHE_RBTREE,
.wr_table = &sx9360_writeable_regs,
.rd_table = &sx9360_readable_regs,
.volatile_table = &sx9360_volatile_regs,
};
static int sx9360_read_prox_data(struct sx_common_data *data,
const struct iio_chan_spec *chan,
__be16 *val)
{
return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val));
}
/*
* If we have no interrupt support, we have to wait for a scan period
* after enabling a channel to get a result.
*/
static int sx9360_wait_for_sample(struct sx_common_data *data)
{
int ret;
__be16 buf;
ret = regmap_bulk_read(data->regmap, SX9360_REG_GNRL_CTRL1,
&buf, sizeof(buf));
if (ret < 0)
return ret;
msleep(SX9360_REG_GNRL_REG_2_PERIOD_MS(be16_to_cpu(buf)));
return 0;
}
static int sx9360_read_gain(struct sx_common_data *data,
const struct iio_chan_spec *chan, int *val)
{
unsigned int reg, regval;
int ret;
reg = SX9360_REG_PROX_CTRL0_PHR + chan->channel;
ret = regmap_read(data->regmap, reg, ®val);
if (ret)
return ret;
*val = 1 << FIELD_GET(SX9360_REG_PROX_CTRL0_GAIN_MASK, regval);
return IIO_VAL_INT;
}
static int sx9360_read_samp_freq(struct sx_common_data *data,
int *val, int *val2)
{
int ret, divisor;
__be16 buf;
ret = regmap_bulk_read(data->regmap, SX9360_REG_GNRL_CTRL1,
&buf, sizeof(buf));
if (ret < 0)
return ret;
divisor = be16_to_cpu(buf);
if (divisor == 0) {
*val = 0;
return IIO_VAL_INT;
}
*val = SX9360_FOSC_HZ;
*val2 = divisor * 8192;
return IIO_VAL_FRACTIONAL;
}
static int sx9360_read_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
int *val, int *val2, long mask)
{
struct sx_common_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = sx_common_read_proximity(data, chan, val);
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_HARDWAREGAIN:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = sx9360_read_gain(data, chan, val);
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_SAMP_FREQ:
return sx9360_read_samp_freq(data, val, val2);
default:
return -EINVAL;
}
}
static const char *sx9360_channel_labels[SX9360_NUM_CHANNELS] = {
"reference", "main",
};
static int sx9360_read_label(struct iio_dev *iio_dev, const struct iio_chan_spec *chan,
char *label)
{
return sysfs_emit(label, "%s\n", sx9360_channel_labels[chan->channel]);
}
static const int sx9360_gain_vals[] = { 1, 2, 4, 8 };
static int sx9360_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
if (chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_HARDWAREGAIN:
*type = IIO_VAL_INT;
*length = ARRAY_SIZE(sx9360_gain_vals);
*vals = sx9360_gain_vals;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_SAMP_FREQ:
*type = IIO_VAL_INT_PLUS_MICRO;
*length = ARRAY_SIZE(sx9360_samp_freq_interval) * 2;
*vals = (int *)sx9360_samp_freq_interval;
return IIO_AVAIL_RANGE;
default:
return -EINVAL;
}
}
static int sx9360_set_samp_freq(struct sx_common_data *data,
int val, int val2)
{
int ret, reg;
__be16 buf;
reg = val * 8192 / SX9360_FOSC_HZ + val2 * 8192 / (SX9360_FOSC_MHZ);
buf = cpu_to_be16(reg);
mutex_lock(&data->mutex);
ret = regmap_bulk_write(data->regmap, SX9360_REG_GNRL_CTRL1, &buf,
sizeof(buf));
mutex_unlock(&data->mutex);
return ret;
}
static int sx9360_read_thresh(struct sx_common_data *data, int *val)
{
unsigned int regval;
int ret;
ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL5, ®val);
if (ret)
return ret;
if (regval <= 1)
*val = regval;
else
*val = (regval * regval) / 2;
return IIO_VAL_INT;
}
static int sx9360_read_hysteresis(struct sx_common_data *data, int *val)
{
unsigned int regval, pthresh;
int ret;
ret = sx9360_read_thresh(data, &pthresh);
if (ret < 0)
return ret;
ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9360_REG_PROX_CTRL4_HYST_MASK, regval);
if (!regval)
*val = 0;
else
*val = pthresh >> (5 - regval);
return IIO_VAL_INT;
}
static int sx9360_read_far_debounce(struct sx_common_data *data, int *val)
{
unsigned int regval;
int ret;
ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, regval);
if (regval)
*val = 1 << regval;
else
*val = 0;
return IIO_VAL_INT;
}
static int sx9360_read_close_debounce(struct sx_common_data *data, int *val)
{
unsigned int regval;
int ret;
ret = regmap_read(data->regmap, SX9360_REG_PROX_CTRL4, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, regval);
if (regval)
*val = 1 << regval;
else
*val = 0;
return IIO_VAL_INT;
}
static int sx9360_read_event_val(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int *val, int *val2)
{
struct sx_common_data *data = iio_priv(indio_dev);
if (chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (info) {
case IIO_EV_INFO_VALUE:
return sx9360_read_thresh(data, val);
case IIO_EV_INFO_PERIOD:
switch (dir) {
case IIO_EV_DIR_RISING:
return sx9360_read_far_debounce(data, val);
case IIO_EV_DIR_FALLING:
return sx9360_read_close_debounce(data, val);
default:
return -EINVAL;
}
case IIO_EV_INFO_HYSTERESIS:
return sx9360_read_hysteresis(data, val);
default:
return -EINVAL;
}
}
static int sx9360_write_thresh(struct sx_common_data *data, int _val)
{
unsigned int val = _val;
int ret;
if (val >= 1)
val = int_sqrt(2 * val);
if (val > 0xff)
return -EINVAL;
mutex_lock(&data->mutex);
ret = regmap_write(data->regmap, SX9360_REG_PROX_CTRL5, val);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9360_write_hysteresis(struct sx_common_data *data, int _val)
{
unsigned int hyst, val = _val;
int ret, pthresh;
ret = sx9360_read_thresh(data, &pthresh);
if (ret < 0)
return ret;
if (val == 0)
hyst = 0;
else if (val >= pthresh >> 2)
hyst = 3;
else if (val >= pthresh >> 3)
hyst = 2;
else if (val >= pthresh >> 4)
hyst = 1;
else
return -EINVAL;
hyst = FIELD_PREP(SX9360_REG_PROX_CTRL4_HYST_MASK, hyst);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4,
SX9360_REG_PROX_CTRL4_HYST_MASK, hyst);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9360_write_far_debounce(struct sx_common_data *data, int _val)
{
unsigned int regval, val = _val;
int ret;
if (val > 0)
val = ilog2(val);
if (!FIELD_FIT(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, val))
return -EINVAL;
regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK, val);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4,
SX9360_REG_PROX_CTRL4_FAR_DEBOUNCE_MASK,
regval);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9360_write_close_debounce(struct sx_common_data *data, int _val)
{
unsigned int regval, val = _val;
int ret;
if (val > 0)
val = ilog2(val);
if (!FIELD_FIT(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, val))
return -EINVAL;
regval = FIELD_PREP(SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK, val);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9360_REG_PROX_CTRL4,
SX9360_REG_PROX_CTRL4_CLOSE_DEBOUNCE_MASK,
regval);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9360_write_event_val(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int val, int val2)
{
struct sx_common_data *data = iio_priv(indio_dev);
if (chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (info) {
case IIO_EV_INFO_VALUE:
return sx9360_write_thresh(data, val);
case IIO_EV_INFO_PERIOD:
switch (dir) {
case IIO_EV_DIR_RISING:
return sx9360_write_far_debounce(data, val);
case IIO_EV_DIR_FALLING:
return sx9360_write_close_debounce(data, val);
default:
return -EINVAL;
}
case IIO_EV_INFO_HYSTERESIS:
return sx9360_write_hysteresis(data, val);
default:
return -EINVAL;
}
}
static int sx9360_write_gain(struct sx_common_data *data,
const struct iio_chan_spec *chan, int val)
{
unsigned int gain, reg;
int ret;
gain = ilog2(val);
reg = SX9360_REG_PROX_CTRL0_PHR + chan->channel;
gain = FIELD_PREP(SX9360_REG_PROX_CTRL0_GAIN_MASK, gain);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, reg,
SX9360_REG_PROX_CTRL0_GAIN_MASK,
gain);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9360_write_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, int val, int val2,
long mask)
{
struct sx_common_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
return sx9360_set_samp_freq(data, val, val2);
case IIO_CHAN_INFO_HARDWAREGAIN:
return sx9360_write_gain(data, chan, val);
default:
return -EINVAL;
}
}
static const struct sx_common_reg_default sx9360_default_regs[] = {
{ SX9360_REG_IRQ_MSK, 0x00 },
{ SX9360_REG_IRQ_CFG, 0x00, "irq_cfg" },
/*
* The lower 2 bits should not be set as it enable sensors measurements.
* Turning the detection on before the configuration values are set to
* good values can cause the device to return erroneous readings.
*/
{ SX9360_REG_GNRL_CTRL0, 0x00, "gnrl_ctrl0" },
{ SX9360_REG_GNRL_CTRL1, 0x00, "gnrl_ctrl1" },
{ SX9360_REG_GNRL_CTRL2, SX9360_REG_GNRL_CTRL2_PERIOD_102MS, "gnrl_ctrl2" },
{ SX9360_REG_AFE_CTRL1, SX9360_REG_AFE_CTRL1_RESFILTIN_0OHMS, "afe_ctrl0" },
{ SX9360_REG_AFE_PARAM0_PHR, SX9360_REG_AFE_PARAM0_RSVD |
SX9360_REG_AFE_PARAM0_RESOLUTION_128, "afe_param0_phr" },
{ SX9360_REG_AFE_PARAM1_PHR, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF |
SX9360_REG_AFE_PARAM1_FREQ_83_33HZ, "afe_param1_phr" },
{ SX9360_REG_AFE_PARAM0_PHM, SX9360_REG_AFE_PARAM0_RSVD |
SX9360_REG_AFE_PARAM0_RESOLUTION_128, "afe_param0_phm" },
{ SX9360_REG_AFE_PARAM1_PHM, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF |
SX9360_REG_AFE_PARAM1_FREQ_83_33HZ, "afe_param1_phm" },
{ SX9360_REG_PROX_CTRL0_PHR, SX9360_REG_PROX_CTRL0_GAIN_1 |
SX9360_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl0_phr" },
{ SX9360_REG_PROX_CTRL0_PHM, SX9360_REG_PROX_CTRL0_GAIN_1 |
SX9360_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl0_phm" },
{ SX9360_REG_PROX_CTRL1, SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_16K, "prox_ctrl1" },
{ SX9360_REG_PROX_CTRL2, SX9360_REG_PROX_CTRL2_AVGDEB_2SAMPLES |
SX9360_REG_PROX_CTRL2_AVGPOS_THRESH_16K, "prox_ctrl2" },
{ SX9360_REG_PROX_CTRL3, SX9360_REG_PROX_CTRL3_AVGNEG_FILT_2 |
SX9360_REG_PROX_CTRL3_AVGPOS_FILT_256, "prox_ctrl3" },
{ SX9360_REG_PROX_CTRL4, 0x00, "prox_ctrl4" },
{ SX9360_REG_PROX_CTRL5, SX9360_REG_PROX_CTRL5_PROXTHRESH_32, "prox_ctrl5" },
};
/* Activate all channels and perform an initial compensation. */
static int sx9360_init_compensation(struct iio_dev *indio_dev)
{
struct sx_common_data *data = iio_priv(indio_dev);
unsigned int val;
int ret;
/* run the compensation phase on all channels */
ret = regmap_update_bits(data->regmap, SX9360_REG_STAT,
SX9360_REG_STAT_COMPSTAT_MASK,
SX9360_REG_STAT_COMPSTAT_MASK);
if (ret)
return ret;
return regmap_read_poll_timeout(data->regmap, SX9360_REG_STAT, val,
!(val & SX9360_REG_STAT_COMPSTAT_MASK),
20000, 2000000);
}
static const struct sx_common_reg_default *
sx9360_get_default_reg(struct device *dev, int idx,
struct sx_common_reg_default *reg_def)
{
u32 raw = 0, pos = 0;
int ret;
memcpy(reg_def, &sx9360_default_regs[idx], sizeof(*reg_def));
switch (reg_def->reg) {
case SX9360_REG_AFE_CTRL1:
ret = device_property_read_u32(dev,
"semtech,input-precharge-resistor-ohms",
&raw);
if (ret)
break;
reg_def->def &= ~SX9360_REG_AFE_CTRL1_RESFILTIN_MASK;
reg_def->def |= FIELD_PREP(SX9360_REG_AFE_CTRL1_RESFILTIN_MASK,
raw / 2000);
break;
case SX9360_REG_AFE_PARAM0_PHR:
case SX9360_REG_AFE_PARAM0_PHM:
ret = device_property_read_u32(dev, "semtech,resolution", &raw);
if (ret)
break;
raw = ilog2(raw) - 3;
reg_def->def &= ~SX9360_REG_AFE_PARAM0_RESOLUTION_MASK;
reg_def->def |= FIELD_PREP(SX9360_REG_AFE_PARAM0_RESOLUTION_MASK, raw);
break;
case SX9360_REG_PROX_CTRL0_PHR:
case SX9360_REG_PROX_CTRL0_PHM:
ret = device_property_read_u32(dev, "semtech,proxraw-strength", &raw);
if (ret)
break;
reg_def->def &= ~SX9360_REG_PROX_CTRL0_RAWFILT_MASK;
reg_def->def |= FIELD_PREP(SX9360_REG_PROX_CTRL0_RAWFILT_MASK, raw);
break;
case SX9360_REG_PROX_CTRL3:
ret = device_property_read_u32(dev, "semtech,avg-pos-strength",
&pos);
if (ret)
break;
/* Powers of 2, except for a gap between 16 and 64 */
raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3);
reg_def->def &= ~SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK;
reg_def->def |= FIELD_PREP(SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK, raw);
break;
}
return reg_def;
}
static int sx9360_check_whoami(struct device *dev, struct iio_dev *indio_dev)
{
/*
* Only one sensor for this driver. Assuming the device tree
* is correct, just set the sensor name.
*/
indio_dev->name = "sx9360";
return 0;
}
static const struct sx_common_chip_info sx9360_chip_info = {
.reg_stat = SX9360_REG_STAT,
.reg_irq_msk = SX9360_REG_IRQ_MSK,
.reg_enable_chan = SX9360_REG_GNRL_CTRL0,
.reg_reset = SX9360_REG_RESET,
.mask_enable_chan = SX9360_REG_GNRL_CTRL0_PHEN_MASK,
.stat_offset = 2,
.num_channels = SX9360_NUM_CHANNELS,
.num_default_regs = ARRAY_SIZE(sx9360_default_regs),
.ops = {
.read_prox_data = sx9360_read_prox_data,
.check_whoami = sx9360_check_whoami,
.init_compensation = sx9360_init_compensation,
.wait_for_sample = sx9360_wait_for_sample,
.get_default_reg = sx9360_get_default_reg,
},
.iio_channels = sx9360_channels,
.num_iio_channels = ARRAY_SIZE(sx9360_channels),
.iio_info = {
.read_raw = sx9360_read_raw,
.read_avail = sx9360_read_avail,
.read_label = sx9360_read_label,
.read_event_value = sx9360_read_event_val,
.write_event_value = sx9360_write_event_val,
.write_raw = sx9360_write_raw,
.read_event_config = sx_common_read_event_config,
.write_event_config = sx_common_write_event_config,
},
};
static int sx9360_probe(struct i2c_client *client)
{
return sx_common_probe(client, &sx9360_chip_info, &sx9360_regmap_config);
}
static int sx9360_suspend(struct device *dev)
{
struct sx_common_data *data = iio_priv(dev_get_drvdata(dev));
unsigned int regval;
int ret;
disable_irq_nosync(data->client->irq);
mutex_lock(&data->mutex);
ret = regmap_read(data->regmap, SX9360_REG_GNRL_CTRL0, ®val);
data->suspend_ctrl =
FIELD_GET(SX9360_REG_GNRL_CTRL0_PHEN_MASK, regval);
if (ret < 0)
goto out;
/* Disable all phases, send the device to sleep. */
ret = regmap_write(data->regmap, SX9360_REG_GNRL_CTRL0, 0);
out:
mutex_unlock(&data->mutex);
return ret;
}
static int sx9360_resume(struct device *dev)
{
struct sx_common_data *data = iio_priv(dev_get_drvdata(dev));
int ret;
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9360_REG_GNRL_CTRL0,
SX9360_REG_GNRL_CTRL0_PHEN_MASK,
data->suspend_ctrl);
mutex_unlock(&data->mutex);
if (ret)
return ret;
enable_irq(data->client->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(sx9360_pm_ops, sx9360_suspend, sx9360_resume);
static const struct acpi_device_id sx9360_acpi_match[] = {
{ "STH9360", SX9360_WHOAMI_VALUE },
{ "SAMM0208", SX9360_WHOAMI_VALUE },
{ }
};
MODULE_DEVICE_TABLE(acpi, sx9360_acpi_match);
static const struct of_device_id sx9360_of_match[] = {
{ .compatible = "semtech,sx9360", (void *)SX9360_WHOAMI_VALUE },
{ }
};
MODULE_DEVICE_TABLE(of, sx9360_of_match);
static const struct i2c_device_id sx9360_id[] = {
{"sx9360", SX9360_WHOAMI_VALUE },
{ }
};
MODULE_DEVICE_TABLE(i2c, sx9360_id);
static struct i2c_driver sx9360_driver = {
.driver = {
.name = "sx9360",
.acpi_match_table = sx9360_acpi_match,
.of_match_table = sx9360_of_match,
.pm = pm_sleep_ptr(&sx9360_pm_ops),
/*
* Lots of i2c transfers in probe + over 200 ms waiting in
* sx9360_init_compensation() mean a slow probe; prefer async
* so we don't delay boot if we're builtin to the kernel.
*/
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
.probe = sx9360_probe,
.id_table = sx9360_id,
};
module_i2c_driver(sx9360_driver);
MODULE_AUTHOR("Gwendal Grignou <[email protected]>");
MODULE_DESCRIPTION("Driver for Semtech SX9360 proximity sensor");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(SEMTECH_PROX);
| linux-master | drivers/iio/proximity/sx9360.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2021 Google LLC.
*
* Driver for Semtech's SX9324 capacitive proximity/button solution.
* Based on SX9324 driver and copy of datasheet at:
* https://edit.wpgdadawant.com/uploads/news_file/program/2019/30184/tech_files/program_30184_suggest_other_file.pdf
*/
#include <linux/acpi.h>
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include "sx_common.h"
/* Register definitions. */
#define SX9324_REG_IRQ_SRC SX_COMMON_REG_IRQ_SRC
#define SX9324_REG_STAT0 0x01
#define SX9324_REG_STAT1 0x02
#define SX9324_REG_STAT2 0x03
#define SX9324_REG_STAT2_COMPSTAT_MASK GENMASK(3, 0)
#define SX9324_REG_STAT3 0x04
#define SX9324_REG_IRQ_MSK 0x05
#define SX9324_CONVDONE_IRQ BIT(3)
#define SX9324_FAR_IRQ BIT(5)
#define SX9324_CLOSE_IRQ BIT(6)
#define SX9324_REG_IRQ_CFG0 0x06
#define SX9324_REG_IRQ_CFG1 0x07
#define SX9324_REG_IRQ_CFG1_FAILCOND 0x80
#define SX9324_REG_IRQ_CFG2 0x08
#define SX9324_REG_GNRL_CTRL0 0x10
#define SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK GENMASK(4, 0)
#define SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS 0x16
#define SX9324_REG_GNRL_CTRL1 0x11
#define SX9324_REG_GNRL_CTRL1_PHEN_MASK GENMASK(3, 0)
#define SX9324_REG_GNRL_CTRL1_PAUSECTRL 0x20
#define SX9324_REG_I2C_ADDR 0x14
#define SX9324_REG_CLK_SPRD 0x15
#define SX9324_REG_AFE_CTRL0 0x20
#define SX9324_REG_AFE_CTRL0_RINT_SHIFT 6
#define SX9324_REG_AFE_CTRL0_RINT_MASK \
GENMASK(SX9324_REG_AFE_CTRL0_RINT_SHIFT + 1, \
SX9324_REG_AFE_CTRL0_RINT_SHIFT)
#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00
#define SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT 4
#define SX9324_REG_AFE_CTRL0_CSIDLE_MASK \
GENMASK(SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT + 1, \
SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT)
#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00
#define SX9324_REG_AFE_CTRL1 0x21
#define SX9324_REG_AFE_CTRL2 0x22
#define SX9324_REG_AFE_CTRL3 0x23
#define SX9324_REG_AFE_CTRL4 0x24
#define SX9324_REG_AFE_CTRL4_FREQ_83_33HZ 0x40
#define SX9324_REG_AFE_CTRL4_RESOLUTION_MASK GENMASK(2, 0)
#define SX9324_REG_AFE_CTRL4_RES_100 0x04
#define SX9324_REG_AFE_CTRL5 0x25
#define SX9324_REG_AFE_CTRL6 0x26
#define SX9324_REG_AFE_CTRL7 0x27
#define SX9324_REG_AFE_PH0 0x28
#define SX9324_REG_AFE_PH0_PIN_MASK(_pin) \
GENMASK(2 * (_pin) + 1, 2 * (_pin))
#define SX9324_REG_AFE_PH1 0x29
#define SX9324_REG_AFE_PH2 0x2a
#define SX9324_REG_AFE_PH3 0x2b
#define SX9324_REG_AFE_CTRL8 0x2c
#define SX9324_REG_AFE_CTRL8_RESERVED 0x10
#define SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM 0x02
#define SX9324_REG_AFE_CTRL8_RESFILTIN_MASK GENMASK(3, 0)
#define SX9324_REG_AFE_CTRL9 0x2d
#define SX9324_REG_AFE_CTRL9_AGAIN_MASK GENMASK(3, 0)
#define SX9324_REG_AFE_CTRL9_AGAIN_1 0x08
#define SX9324_REG_PROX_CTRL0 0x30
#define SX9324_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3)
#define SX9324_REG_PROX_CTRL0_GAIN_SHIFT 3
#define SX9324_REG_PROX_CTRL0_GAIN_RSVD 0x0
#define SX9324_REG_PROX_CTRL0_GAIN_1 0x1
#define SX9324_REG_PROX_CTRL0_GAIN_8 0x4
#define SX9324_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0)
#define SX9324_REG_PROX_CTRL0_RAWFILT_1P50 0x01
#define SX9324_REG_PROX_CTRL1 0x31
#define SX9324_REG_PROX_CTRL2 0x32
#define SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K 0x20
#define SX9324_REG_PROX_CTRL3 0x33
#define SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES 0x40
#define SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K 0x20
#define SX9324_REG_PROX_CTRL4 0x34
#define SX9324_REG_PROX_CTRL4_AVGNEGFILT_MASK GENMASK(5, 3)
#define SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 0x08
#define SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK GENMASK(2, 0)
#define SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256 0x04
#define SX9324_REG_PROX_CTRL5 0x35
#define SX9324_REG_PROX_CTRL5_HYST_MASK GENMASK(5, 4)
#define SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK GENMASK(3, 2)
#define SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK GENMASK(1, 0)
#define SX9324_REG_PROX_CTRL6 0x36
#define SX9324_REG_PROX_CTRL6_PROXTHRESH_32 0x08
#define SX9324_REG_PROX_CTRL7 0x37
#define SX9324_REG_ADV_CTRL0 0x40
#define SX9324_REG_ADV_CTRL1 0x41
#define SX9324_REG_ADV_CTRL2 0x42
#define SX9324_REG_ADV_CTRL3 0x43
#define SX9324_REG_ADV_CTRL4 0x44
#define SX9324_REG_ADV_CTRL5 0x45
#define SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK GENMASK(3, 2)
#define SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 0x04
#define SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1 0x01
#define SX9324_REG_ADV_CTRL6 0x46
#define SX9324_REG_ADV_CTRL7 0x47
#define SX9324_REG_ADV_CTRL8 0x48
#define SX9324_REG_ADV_CTRL9 0x49
#define SX9324_REG_ADV_CTRL10 0x4a
#define SX9324_REG_ADV_CTRL11 0x4b
#define SX9324_REG_ADV_CTRL12 0x4c
#define SX9324_REG_ADV_CTRL13 0x4d
#define SX9324_REG_ADV_CTRL14 0x4e
#define SX9324_REG_ADV_CTRL15 0x4f
#define SX9324_REG_ADV_CTRL16 0x50
#define SX9324_REG_ADV_CTRL17 0x51
#define SX9324_REG_ADV_CTRL18 0x52
#define SX9324_REG_ADV_CTRL19 0x53
#define SX9324_REG_ADV_CTRL20 0x54
#define SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION 0xf0
#define SX9324_REG_PHASE_SEL 0x60
#define SX9324_REG_USEFUL_MSB 0x61
#define SX9324_REG_USEFUL_LSB 0x62
#define SX9324_REG_AVG_MSB 0x63
#define SX9324_REG_AVG_LSB 0x64
#define SX9324_REG_DIFF_MSB 0x65
#define SX9324_REG_DIFF_LSB 0x66
#define SX9324_REG_OFFSET_MSB 0x67
#define SX9324_REG_OFFSET_LSB 0x68
#define SX9324_REG_SAR_MSB 0x69
#define SX9324_REG_SAR_LSB 0x6a
#define SX9324_REG_RESET 0x9f
/* Write this to REG_RESET to do a soft reset. */
#define SX9324_SOFT_RESET 0xde
#define SX9324_REG_WHOAMI 0xfa
#define SX9324_WHOAMI_VALUE 0x23
#define SX9324_REG_REVISION 0xfe
/* 4 channels, as defined in STAT0: PH0, PH1, PH2 and PH3. */
#define SX9324_NUM_CHANNELS 4
/* 3 CS pins: CS0, CS1, CS2. */
#define SX9324_NUM_PINS 3
static const char * const sx9324_cs_pin_usage[] = { "HZ", "MI", "DS", "GD" };
static ssize_t sx9324_phase_configuration_show(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct sx_common_data *data = iio_priv(indio_dev);
unsigned int val;
int i, ret, pin_idx;
size_t len = 0;
ret = regmap_read(data->regmap, SX9324_REG_AFE_PH0 + chan->channel, &val);
if (ret < 0)
return ret;
for (i = 0; i < SX9324_NUM_PINS; i++) {
pin_idx = (val & SX9324_REG_AFE_PH0_PIN_MASK(i)) >> (2 * i);
len += sysfs_emit_at(buf, len, "%s,",
sx9324_cs_pin_usage[pin_idx]);
}
buf[len - 1] = '\n';
return len;
}
static const struct iio_chan_spec_ext_info sx9324_channel_ext_info[] = {
{
.name = "setup",
.shared = IIO_SEPARATE,
.read = sx9324_phase_configuration_show,
},
{}
};
#define SX9324_CHANNEL(idx) \
{ \
.type = IIO_PROXIMITY, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.info_mask_separate_available = \
BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
.info_mask_shared_by_all_available = \
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.indexed = 1, \
.channel = idx, \
.address = SX9324_REG_DIFF_MSB, \
.event_spec = sx_common_events, \
.num_event_specs = ARRAY_SIZE(sx_common_events), \
.scan_index = idx, \
.scan_type = { \
.sign = 's', \
.realbits = 12, \
.storagebits = 16, \
.endianness = IIO_BE, \
}, \
.ext_info = sx9324_channel_ext_info, \
}
static const struct iio_chan_spec sx9324_channels[] = {
SX9324_CHANNEL(0), /* Phase 0 */
SX9324_CHANNEL(1), /* Phase 1 */
SX9324_CHANNEL(2), /* Phase 2 */
SX9324_CHANNEL(3), /* Phase 3 */
IIO_CHAN_SOFT_TIMESTAMP(4),
};
/*
* Each entry contains the integer part (val) and the fractional part, in micro
* seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO.
*/
static const struct {
int val;
int val2;
} sx9324_samp_freq_table[] = {
{ 1000, 0 }, /* 00000: Min (no idle time) */
{ 500, 0 }, /* 00001: 2 ms */
{ 250, 0 }, /* 00010: 4 ms */
{ 166, 666666 }, /* 00011: 6 ms */
{ 125, 0 }, /* 00100: 8 ms */
{ 100, 0 }, /* 00101: 10 ms */
{ 71, 428571 }, /* 00110: 14 ms */
{ 55, 555556 }, /* 00111: 18 ms */
{ 45, 454545 }, /* 01000: 22 ms */
{ 38, 461538 }, /* 01001: 26 ms */
{ 33, 333333 }, /* 01010: 30 ms */
{ 29, 411765 }, /* 01011: 34 ms */
{ 26, 315789 }, /* 01100: 38 ms */
{ 23, 809524 }, /* 01101: 42 ms */
{ 21, 739130 }, /* 01110: 46 ms */
{ 20, 0 }, /* 01111: 50 ms */
{ 17, 857143 }, /* 10000: 56 ms */
{ 16, 129032 }, /* 10001: 62 ms */
{ 14, 705882 }, /* 10010: 68 ms */
{ 13, 513514 }, /* 10011: 74 ms */
{ 12, 500000 }, /* 10100: 80 ms */
{ 11, 111111 }, /* 10101: 90 ms */
{ 10, 0 }, /* 10110: 100 ms (Typ.) */
{ 5, 0 }, /* 10111: 200 ms */
{ 3, 333333 }, /* 11000: 300 ms */
{ 2, 500000 }, /* 11001: 400 ms */
{ 1, 666667 }, /* 11010: 600 ms */
{ 1, 250000 }, /* 11011: 800 ms */
{ 1, 0 }, /* 11100: 1 s */
{ 0, 500000 }, /* 11101: 2 s */
{ 0, 333333 }, /* 11110: 3 s */
{ 0, 250000 }, /* 11111: 4 s */
};
static const unsigned int sx9324_scan_period_table[] = {
2, 15, 30, 45, 60, 90, 120, 200,
400, 600, 800, 1000, 2000, 3000, 4000, 5000,
};
static const struct regmap_range sx9324_writable_reg_ranges[] = {
/*
* To set COMPSTAT for compensation, even if datasheet says register is
* RO.
*/
regmap_reg_range(SX9324_REG_STAT2, SX9324_REG_STAT2),
regmap_reg_range(SX9324_REG_IRQ_MSK, SX9324_REG_IRQ_CFG2),
regmap_reg_range(SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL1),
/* Leave i2c and clock spreading as unavailable */
regmap_reg_range(SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL9),
regmap_reg_range(SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL7),
regmap_reg_range(SX9324_REG_ADV_CTRL0, SX9324_REG_ADV_CTRL20),
regmap_reg_range(SX9324_REG_PHASE_SEL, SX9324_REG_PHASE_SEL),
regmap_reg_range(SX9324_REG_OFFSET_MSB, SX9324_REG_OFFSET_LSB),
regmap_reg_range(SX9324_REG_RESET, SX9324_REG_RESET),
};
static const struct regmap_access_table sx9324_writeable_regs = {
.yes_ranges = sx9324_writable_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(sx9324_writable_reg_ranges),
};
/*
* All allocated registers are readable, so we just list unallocated
* ones.
*/
static const struct regmap_range sx9324_non_readable_reg_ranges[] = {
regmap_reg_range(SX9324_REG_IRQ_CFG2 + 1, SX9324_REG_GNRL_CTRL0 - 1),
regmap_reg_range(SX9324_REG_GNRL_CTRL1 + 1, SX9324_REG_AFE_CTRL0 - 1),
regmap_reg_range(SX9324_REG_AFE_CTRL9 + 1, SX9324_REG_PROX_CTRL0 - 1),
regmap_reg_range(SX9324_REG_PROX_CTRL7 + 1, SX9324_REG_ADV_CTRL0 - 1),
regmap_reg_range(SX9324_REG_ADV_CTRL20 + 1, SX9324_REG_PHASE_SEL - 1),
regmap_reg_range(SX9324_REG_SAR_LSB + 1, SX9324_REG_RESET - 1),
regmap_reg_range(SX9324_REG_RESET + 1, SX9324_REG_WHOAMI - 1),
regmap_reg_range(SX9324_REG_WHOAMI + 1, SX9324_REG_REVISION - 1),
};
static const struct regmap_access_table sx9324_readable_regs = {
.no_ranges = sx9324_non_readable_reg_ranges,
.n_no_ranges = ARRAY_SIZE(sx9324_non_readable_reg_ranges),
};
static const struct regmap_range sx9324_volatile_reg_ranges[] = {
regmap_reg_range(SX9324_REG_IRQ_SRC, SX9324_REG_STAT3),
regmap_reg_range(SX9324_REG_USEFUL_MSB, SX9324_REG_DIFF_LSB),
regmap_reg_range(SX9324_REG_SAR_MSB, SX9324_REG_SAR_LSB),
regmap_reg_range(SX9324_REG_WHOAMI, SX9324_REG_WHOAMI),
regmap_reg_range(SX9324_REG_REVISION, SX9324_REG_REVISION),
};
static const struct regmap_access_table sx9324_volatile_regs = {
.yes_ranges = sx9324_volatile_reg_ranges,
.n_yes_ranges = ARRAY_SIZE(sx9324_volatile_reg_ranges),
};
static const struct regmap_config sx9324_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = SX9324_REG_REVISION,
.cache_type = REGCACHE_RBTREE,
.wr_table = &sx9324_writeable_regs,
.rd_table = &sx9324_readable_regs,
.volatile_table = &sx9324_volatile_regs,
};
static int sx9324_read_prox_data(struct sx_common_data *data,
const struct iio_chan_spec *chan,
__be16 *val)
{
int ret;
ret = regmap_write(data->regmap, SX9324_REG_PHASE_SEL, chan->channel);
if (ret < 0)
return ret;
return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val));
}
/*
* If we have no interrupt support, we have to wait for a scan period
* after enabling a channel to get a result.
*/
static int sx9324_wait_for_sample(struct sx_common_data *data)
{
int ret;
unsigned int val;
ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL0, &val);
if (ret < 0)
return ret;
val = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, val);
msleep(sx9324_scan_period_table[val]);
return 0;
}
static int sx9324_read_gain(struct sx_common_data *data,
const struct iio_chan_spec *chan, int *val)
{
unsigned int reg, regval;
int ret;
reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
ret = regmap_read(data->regmap, reg, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval);
if (regval)
regval--;
else if (regval == SX9324_REG_PROX_CTRL0_GAIN_RSVD ||
regval > SX9324_REG_PROX_CTRL0_GAIN_8)
return -EINVAL;
*val = 1 << regval;
return IIO_VAL_INT;
}
static int sx9324_read_samp_freq(struct sx_common_data *data,
int *val, int *val2)
{
int ret;
unsigned int regval;
ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL0, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, regval);
*val = sx9324_samp_freq_table[regval].val;
*val2 = sx9324_samp_freq_table[regval].val2;
return IIO_VAL_INT_PLUS_MICRO;
}
static int sx9324_read_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
int *val, int *val2, long mask)
{
struct sx_common_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = sx_common_read_proximity(data, chan, val);
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_HARDWAREGAIN:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = sx9324_read_gain(data, chan, val);
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_SAMP_FREQ:
return sx9324_read_samp_freq(data, val, val2);
default:
return -EINVAL;
}
}
static const int sx9324_gain_vals[] = { 1, 2, 4, 8 };
static int sx9324_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
if (chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_HARDWAREGAIN:
*type = IIO_VAL_INT;
*length = ARRAY_SIZE(sx9324_gain_vals);
*vals = sx9324_gain_vals;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_SAMP_FREQ:
*type = IIO_VAL_INT_PLUS_MICRO;
*length = ARRAY_SIZE(sx9324_samp_freq_table) * 2;
*vals = (int *)sx9324_samp_freq_table;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static int sx9324_set_samp_freq(struct sx_common_data *data,
int val, int val2)
{
int i, ret;
for (i = 0; i < ARRAY_SIZE(sx9324_samp_freq_table); i++)
if (val == sx9324_samp_freq_table[i].val &&
val2 == sx9324_samp_freq_table[i].val2)
break;
if (i == ARRAY_SIZE(sx9324_samp_freq_table))
return -EINVAL;
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap,
SX9324_REG_GNRL_CTRL0,
SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, i);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9324_read_thresh(struct sx_common_data *data,
const struct iio_chan_spec *chan, int *val)
{
unsigned int regval;
unsigned int reg;
int ret;
/*
* TODO(gwendal): Depending on the phase function
* (proximity/table/body), retrieve the right threshold.
* For now, return the proximity threshold.
*/
reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2;
ret = regmap_read(data->regmap, reg, ®val);
if (ret)
return ret;
if (regval <= 1)
*val = regval;
else
*val = (regval * regval) / 2;
return IIO_VAL_INT;
}
static int sx9324_read_hysteresis(struct sx_common_data *data,
const struct iio_chan_spec *chan, int *val)
{
unsigned int regval, pthresh;
int ret;
ret = sx9324_read_thresh(data, chan, &pthresh);
if (ret < 0)
return ret;
ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9324_REG_PROX_CTRL5_HYST_MASK, regval);
if (!regval)
*val = 0;
else
*val = pthresh >> (5 - regval);
return IIO_VAL_INT;
}
static int sx9324_read_far_debounce(struct sx_common_data *data, int *val)
{
unsigned int regval;
int ret;
ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, regval);
if (regval)
*val = 1 << regval;
else
*val = 0;
return IIO_VAL_INT;
}
static int sx9324_read_close_debounce(struct sx_common_data *data, int *val)
{
unsigned int regval;
int ret;
ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, ®val);
if (ret)
return ret;
regval = FIELD_GET(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, regval);
if (regval)
*val = 1 << regval;
else
*val = 0;
return IIO_VAL_INT;
}
static int sx9324_read_event_val(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int *val, int *val2)
{
struct sx_common_data *data = iio_priv(indio_dev);
if (chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (info) {
case IIO_EV_INFO_VALUE:
return sx9324_read_thresh(data, chan, val);
case IIO_EV_INFO_PERIOD:
switch (dir) {
case IIO_EV_DIR_RISING:
return sx9324_read_far_debounce(data, val);
case IIO_EV_DIR_FALLING:
return sx9324_read_close_debounce(data, val);
default:
return -EINVAL;
}
case IIO_EV_INFO_HYSTERESIS:
return sx9324_read_hysteresis(data, chan, val);
default:
return -EINVAL;
}
}
static int sx9324_write_thresh(struct sx_common_data *data,
const struct iio_chan_spec *chan, int _val)
{
unsigned int reg, val = _val;
int ret;
reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2;
if (val >= 1)
val = int_sqrt(2 * val);
if (val > 0xff)
return -EINVAL;
mutex_lock(&data->mutex);
ret = regmap_write(data->regmap, reg, val);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9324_write_hysteresis(struct sx_common_data *data,
const struct iio_chan_spec *chan, int _val)
{
unsigned int hyst, val = _val;
int ret, pthresh;
ret = sx9324_read_thresh(data, chan, &pthresh);
if (ret < 0)
return ret;
if (val == 0)
hyst = 0;
else if (val >= pthresh >> 2)
hyst = 3;
else if (val >= pthresh >> 3)
hyst = 2;
else if (val >= pthresh >> 4)
hyst = 1;
else
return -EINVAL;
hyst = FIELD_PREP(SX9324_REG_PROX_CTRL5_HYST_MASK, hyst);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5,
SX9324_REG_PROX_CTRL5_HYST_MASK, hyst);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9324_write_far_debounce(struct sx_common_data *data, int _val)
{
unsigned int regval, val = _val;
int ret;
if (val > 0)
val = ilog2(val);
if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val))
return -EINVAL;
regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5,
SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK,
regval);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9324_write_close_debounce(struct sx_common_data *data, int _val)
{
unsigned int regval, val = _val;
int ret;
if (val > 0)
val = ilog2(val);
if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val))
return -EINVAL;
regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5,
SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK,
regval);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9324_write_event_val(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int val, int val2)
{
struct sx_common_data *data = iio_priv(indio_dev);
if (chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (info) {
case IIO_EV_INFO_VALUE:
return sx9324_write_thresh(data, chan, val);
case IIO_EV_INFO_PERIOD:
switch (dir) {
case IIO_EV_DIR_RISING:
return sx9324_write_far_debounce(data, val);
case IIO_EV_DIR_FALLING:
return sx9324_write_close_debounce(data, val);
default:
return -EINVAL;
}
case IIO_EV_INFO_HYSTERESIS:
return sx9324_write_hysteresis(data, chan, val);
default:
return -EINVAL;
}
}
static int sx9324_write_gain(struct sx_common_data *data,
const struct iio_chan_spec *chan, int val)
{
unsigned int gain, reg;
int ret;
reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
gain = ilog2(val) + 1;
if (val <= 0 || gain > SX9324_REG_PROX_CTRL0_GAIN_8)
return -EINVAL;
gain = FIELD_PREP(SX9324_REG_PROX_CTRL0_GAIN_MASK, gain);
mutex_lock(&data->mutex);
ret = regmap_update_bits(data->regmap, reg,
SX9324_REG_PROX_CTRL0_GAIN_MASK,
gain);
mutex_unlock(&data->mutex);
return ret;
}
static int sx9324_write_raw(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, int val, int val2,
long mask)
{
struct sx_common_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
return sx9324_set_samp_freq(data, val, val2);
case IIO_CHAN_INFO_HARDWAREGAIN:
return sx9324_write_gain(data, chan, val);
default:
return -EINVAL;
}
}
static const struct sx_common_reg_default sx9324_default_regs[] = {
{ SX9324_REG_IRQ_MSK, 0x00 },
{ SX9324_REG_IRQ_CFG0, 0x00, "irq_cfg0" },
{ SX9324_REG_IRQ_CFG1, SX9324_REG_IRQ_CFG1_FAILCOND, "irq_cfg1" },
{ SX9324_REG_IRQ_CFG2, 0x00, "irq_cfg2" },
{ SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS, "gnrl_ctrl0" },
/*
* The lower 4 bits should not be set as it enable sensors measurements.
* Turning the detection on before the configuration values are set to
* good values can cause the device to return erroneous readings.
*/
{ SX9324_REG_GNRL_CTRL1, SX9324_REG_GNRL_CTRL1_PAUSECTRL, "gnrl_ctrl1" },
{ SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL0_RINT_LOWEST, "afe_ctrl0" },
{ SX9324_REG_AFE_CTRL3, 0x00, "afe_ctrl3" },
{ SX9324_REG_AFE_CTRL4, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
SX9324_REG_AFE_CTRL4_RES_100, "afe_ctrl4" },
{ SX9324_REG_AFE_CTRL6, 0x00, "afe_ctrl6" },
{ SX9324_REG_AFE_CTRL7, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
SX9324_REG_AFE_CTRL4_RES_100, "afe_ctrl7" },
/* TODO(gwendal): PHx use chip default or all grounded? */
{ SX9324_REG_AFE_PH0, 0x29, "afe_ph0" },
{ SX9324_REG_AFE_PH1, 0x26, "afe_ph1" },
{ SX9324_REG_AFE_PH2, 0x1a, "afe_ph2" },
{ SX9324_REG_AFE_PH3, 0x16, "afe_ph3" },
{ SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESERVED |
SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM, "afe_ctrl8" },
{ SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1, "afe_ctrl9" },
{ SX9324_REG_PROX_CTRL0,
SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
SX9324_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl0" },
{ SX9324_REG_PROX_CTRL1,
SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
SX9324_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl1" },
{ SX9324_REG_PROX_CTRL2, SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K, "prox_ctrl2" },
{ SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES |
SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K, "prox_ctrl3" },
{ SX9324_REG_PROX_CTRL4, SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 |
SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256, "prox_ctrl4" },
{ SX9324_REG_PROX_CTRL5, 0x00, "prox_ctrl5" },
{ SX9324_REG_PROX_CTRL6, SX9324_REG_PROX_CTRL6_PROXTHRESH_32, "prox_ctrl6" },
{ SX9324_REG_PROX_CTRL7, SX9324_REG_PROX_CTRL6_PROXTHRESH_32, "prox_ctrl7" },
{ SX9324_REG_ADV_CTRL0, 0x00, "adv_ctrl0" },
{ SX9324_REG_ADV_CTRL1, 0x00, "adv_ctrl1" },
{ SX9324_REG_ADV_CTRL2, 0x00, "adv_ctrl2" },
{ SX9324_REG_ADV_CTRL3, 0x00, "adv_ctrl3" },
{ SX9324_REG_ADV_CTRL4, 0x00, "adv_ctrl4" },
{ SX9324_REG_ADV_CTRL5, SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 |
SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1, "adv_ctrl5" },
{ SX9324_REG_ADV_CTRL6, 0x00, "adv_ctrl6" },
{ SX9324_REG_ADV_CTRL7, 0x00, "adv_ctrl7" },
{ SX9324_REG_ADV_CTRL8, 0x00, "adv_ctrl8" },
{ SX9324_REG_ADV_CTRL9, 0x00, "adv_ctrl9" },
/* Body/Table threshold */
{ SX9324_REG_ADV_CTRL10, 0x00, "adv_ctrl10" },
{ SX9324_REG_ADV_CTRL11, 0x00, "adv_ctrl11" },
{ SX9324_REG_ADV_CTRL12, 0x00, "adv_ctrl12" },
/* TODO(gwendal): SAR currenly disabled */
{ SX9324_REG_ADV_CTRL13, 0x00, "adv_ctrl13" },
{ SX9324_REG_ADV_CTRL14, 0x00, "adv_ctrl14" },
{ SX9324_REG_ADV_CTRL15, 0x00, "adv_ctrl15" },
{ SX9324_REG_ADV_CTRL16, 0x00, "adv_ctrl16" },
{ SX9324_REG_ADV_CTRL17, 0x00, "adv_ctrl17" },
{ SX9324_REG_ADV_CTRL18, 0x00, "adv_ctrl18" },
{ SX9324_REG_ADV_CTRL19,
SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION, "adv_ctrl19" },
{ SX9324_REG_ADV_CTRL20,
SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION, "adv_ctrl20" },
};
/* Activate all channels and perform an initial compensation. */
static int sx9324_init_compensation(struct iio_dev *indio_dev)
{
struct sx_common_data *data = iio_priv(indio_dev);
unsigned int val;
int ret;
/* run the compensation phase on all channels */
ret = regmap_update_bits(data->regmap, SX9324_REG_STAT2,
SX9324_REG_STAT2_COMPSTAT_MASK,
SX9324_REG_STAT2_COMPSTAT_MASK);
if (ret)
return ret;
return regmap_read_poll_timeout(data->regmap, SX9324_REG_STAT2, val,
!(val & SX9324_REG_STAT2_COMPSTAT_MASK),
20000, 2000000);
}
static const struct sx_common_reg_default *
sx9324_get_default_reg(struct device *dev, int idx,
struct sx_common_reg_default *reg_def)
{
static const char * const sx9324_rints[] = { "lowest", "low", "high",
"highest" };
static const char * const sx9324_csidle[] = { "hi-z", "hi-z", "gnd",
"vdd" };
#define SX9324_PIN_DEF "semtech,ph0-pin"
#define SX9324_RESOLUTION_DEF "semtech,ph01-resolution"
#define SX9324_PROXRAW_DEF "semtech,ph01-proxraw-strength"
unsigned int pin_defs[SX9324_NUM_PINS];
char prop[] = SX9324_PROXRAW_DEF;
u32 start = 0, raw = 0, pos = 0;
int ret, count, ph, pin;
const char *res;
memcpy(reg_def, &sx9324_default_regs[idx], sizeof(*reg_def));
sx_common_get_raw_register_config(dev, reg_def);
switch (reg_def->reg) {
case SX9324_REG_AFE_PH0:
case SX9324_REG_AFE_PH1:
case SX9324_REG_AFE_PH2:
case SX9324_REG_AFE_PH3:
ph = reg_def->reg - SX9324_REG_AFE_PH0;
snprintf(prop, ARRAY_SIZE(prop), "semtech,ph%d-pin", ph);
count = device_property_count_u32(dev, prop);
if (count != ARRAY_SIZE(pin_defs))
break;
ret = device_property_read_u32_array(dev, prop, pin_defs,
ARRAY_SIZE(pin_defs));
if (ret)
break;
for (pin = 0; pin < SX9324_NUM_PINS; pin++)
raw |= (pin_defs[pin] << (2 * pin)) &
SX9324_REG_AFE_PH0_PIN_MASK(pin);
reg_def->def = raw;
break;
case SX9324_REG_AFE_CTRL0:
ret = device_property_read_string(dev,
"semtech,cs-idle-sleep", &res);
if (!ret)
ret = match_string(sx9324_csidle, ARRAY_SIZE(sx9324_csidle), res);
if (ret >= 0) {
reg_def->def &= ~SX9324_REG_AFE_CTRL0_CSIDLE_MASK;
reg_def->def |= ret << SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT;
}
ret = device_property_read_string(dev,
"semtech,int-comp-resistor", &res);
if (ret)
break;
ret = match_string(sx9324_rints, ARRAY_SIZE(sx9324_rints), res);
if (ret < 0)
break;
reg_def->def &= ~SX9324_REG_AFE_CTRL0_RINT_MASK;
reg_def->def |= ret << SX9324_REG_AFE_CTRL0_RINT_SHIFT;
break;
case SX9324_REG_AFE_CTRL4:
case SX9324_REG_AFE_CTRL7:
if (reg_def->reg == SX9324_REG_AFE_CTRL4)
strncpy(prop, "semtech,ph01-resolution",
ARRAY_SIZE(prop));
else
strncpy(prop, "semtech,ph23-resolution",
ARRAY_SIZE(prop));
ret = device_property_read_u32(dev, prop, &raw);
if (ret)
break;
raw = ilog2(raw) - 3;
reg_def->def &= ~SX9324_REG_AFE_CTRL4_RESOLUTION_MASK;
reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL4_RESOLUTION_MASK,
raw);
break;
case SX9324_REG_AFE_CTRL8:
ret = device_property_read_u32(dev,
"semtech,input-precharge-resistor-ohms",
&raw);
if (ret)
break;
reg_def->def &= ~SX9324_REG_AFE_CTRL8_RESFILTIN_MASK;
reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL8_RESFILTIN_MASK,
raw / 2000);
break;
case SX9324_REG_AFE_CTRL9:
ret = device_property_read_u32(dev,
"semtech,input-analog-gain", &raw);
if (ret)
break;
/*
* The analog gain has the following setting:
* +---------+----------------+----------------+
* | dt(raw) | physical value | register value |
* +---------+----------------+----------------+
* | 0 | x1.247 | 6 |
* | 1 | x1 | 8 |
* | 2 | x0.768 | 11 |
* | 3 | x0.552 | 15 |
* +---------+----------------+----------------+
*/
reg_def->def &= ~SX9324_REG_AFE_CTRL9_AGAIN_MASK;
reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL9_AGAIN_MASK,
6 + raw * (raw + 3) / 2);
break;
case SX9324_REG_ADV_CTRL5:
ret = device_property_read_u32(dev, "semtech,startup-sensor",
&start);
if (ret)
break;
reg_def->def &= ~SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK;
reg_def->def |= FIELD_PREP(SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK,
start);
break;
case SX9324_REG_PROX_CTRL4:
ret = device_property_read_u32(dev, "semtech,avg-pos-strength",
&pos);
if (ret)
break;
/* Powers of 2, except for a gap between 16 and 64 */
raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3);
reg_def->def &= ~SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK;
reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK,
raw);
break;
case SX9324_REG_PROX_CTRL0:
case SX9324_REG_PROX_CTRL1:
if (reg_def->reg == SX9324_REG_PROX_CTRL0)
strncpy(prop, "semtech,ph01-proxraw-strength",
ARRAY_SIZE(prop));
else
strncpy(prop, "semtech,ph23-proxraw-strength",
ARRAY_SIZE(prop));
ret = device_property_read_u32(dev, prop, &raw);
if (ret)
break;
reg_def->def &= ~SX9324_REG_PROX_CTRL0_RAWFILT_MASK;
reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL0_RAWFILT_MASK,
raw);
break;
}
return reg_def;
}
static int sx9324_check_whoami(struct device *dev,
struct iio_dev *indio_dev)
{
/*
* Only one sensor for this driver. Assuming the device tree
* is correct, just set the sensor name.
*/
indio_dev->name = "sx9324";
return 0;
}
static const struct sx_common_chip_info sx9324_chip_info = {
.reg_stat = SX9324_REG_STAT0,
.reg_irq_msk = SX9324_REG_IRQ_MSK,
.reg_enable_chan = SX9324_REG_GNRL_CTRL1,
.reg_reset = SX9324_REG_RESET,
.mask_enable_chan = SX9324_REG_GNRL_CTRL1_PHEN_MASK,
.irq_msk_offset = 3,
.num_channels = SX9324_NUM_CHANNELS,
.num_default_regs = ARRAY_SIZE(sx9324_default_regs),
.ops = {
.read_prox_data = sx9324_read_prox_data,
.check_whoami = sx9324_check_whoami,
.init_compensation = sx9324_init_compensation,
.wait_for_sample = sx9324_wait_for_sample,
.get_default_reg = sx9324_get_default_reg,
},
.iio_channels = sx9324_channels,
.num_iio_channels = ARRAY_SIZE(sx9324_channels),
.iio_info = {
.read_raw = sx9324_read_raw,
.read_avail = sx9324_read_avail,
.read_event_value = sx9324_read_event_val,
.write_event_value = sx9324_write_event_val,
.write_raw = sx9324_write_raw,
.read_event_config = sx_common_read_event_config,
.write_event_config = sx_common_write_event_config,
},
};
static int sx9324_probe(struct i2c_client *client)
{
return sx_common_probe(client, &sx9324_chip_info, &sx9324_regmap_config);
}
static int sx9324_suspend(struct device *dev)
{
struct sx_common_data *data = iio_priv(dev_get_drvdata(dev));
unsigned int regval;
int ret;
disable_irq_nosync(data->client->irq);
mutex_lock(&data->mutex);
ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL1, ®val);
data->suspend_ctrl =
FIELD_GET(SX9324_REG_GNRL_CTRL1_PHEN_MASK, regval);
if (ret < 0)
goto out;
/* Disable all phases, send the device to sleep. */
ret = regmap_write(data->regmap, SX9324_REG_GNRL_CTRL1, 0);
out:
mutex_unlock(&data->mutex);
return ret;
}
static int sx9324_resume(struct device *dev)
{
struct sx_common_data *data = iio_priv(dev_get_drvdata(dev));
int ret;
mutex_lock(&data->mutex);
ret = regmap_write(data->regmap, SX9324_REG_GNRL_CTRL1,
data->suspend_ctrl | SX9324_REG_GNRL_CTRL1_PAUSECTRL);
mutex_unlock(&data->mutex);
if (ret)
return ret;
enable_irq(data->client->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(sx9324_pm_ops, sx9324_suspend, sx9324_resume);
static const struct acpi_device_id sx9324_acpi_match[] = {
{ "STH9324", SX9324_WHOAMI_VALUE },
{ }
};
MODULE_DEVICE_TABLE(acpi, sx9324_acpi_match);
static const struct of_device_id sx9324_of_match[] = {
{ .compatible = "semtech,sx9324", (void *)SX9324_WHOAMI_VALUE },
{ }
};
MODULE_DEVICE_TABLE(of, sx9324_of_match);
static const struct i2c_device_id sx9324_id[] = {
{ "sx9324", SX9324_WHOAMI_VALUE },
{ }
};
MODULE_DEVICE_TABLE(i2c, sx9324_id);
static struct i2c_driver sx9324_driver = {
.driver = {
.name = "sx9324",
.acpi_match_table = sx9324_acpi_match,
.of_match_table = sx9324_of_match,
.pm = pm_sleep_ptr(&sx9324_pm_ops),
/*
* Lots of i2c transfers in probe + over 200 ms waiting in
* sx9324_init_compensation() mean a slow probe; prefer async
* so we don't delay boot if we're builtin to the kernel.
*/
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
.probe = sx9324_probe,
.id_table = sx9324_id,
};
module_i2c_driver(sx9324_driver);
MODULE_AUTHOR("Gwendal Grignou <[email protected]>");
MODULE_DESCRIPTION("Driver for Semtech SX9324 proximity sensor");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(SEMTECH_PROX);
| linux-master | drivers/iio/proximity/sx9324.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* pulsedlight-lidar-lite-v2.c - Support for PulsedLight LIDAR sensor
*
* Copyright (C) 2015, 2017-2018
* Author: Matt Ranostay <[email protected]>
*
* TODO: interrupt mode, and signal strength reporting
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/pm_runtime.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#define LIDAR_REG_CONTROL 0x00
#define LIDAR_REG_CONTROL_ACQUIRE BIT(2)
#define LIDAR_REG_STATUS 0x01
#define LIDAR_REG_STATUS_INVALID BIT(3)
#define LIDAR_REG_STATUS_READY BIT(0)
#define LIDAR_REG_DATA_HBYTE 0x0f
#define LIDAR_REG_DATA_LBYTE 0x10
#define LIDAR_REG_DATA_WORD_READ BIT(7)
#define LIDAR_REG_PWR_CONTROL 0x65
#define LIDAR_DRV_NAME "lidar"
struct lidar_data {
struct iio_dev *indio_dev;
struct i2c_client *client;
int (*xfer)(struct lidar_data *data, u8 reg, u8 *val, int len);
int i2c_enabled;
/* Ensure timestamp is naturally aligned */
struct {
u16 chan;
s64 timestamp __aligned(8);
} scan;
};
static const struct iio_chan_spec lidar_channels[] = {
{
.type = IIO_DISTANCE,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 0,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static int lidar_i2c_xfer(struct lidar_data *data, u8 reg, u8 *val, int len)
{
struct i2c_client *client = data->client;
struct i2c_msg msg[2];
int ret;
msg[0].addr = client->addr;
msg[0].flags = client->flags | I2C_M_STOP;
msg[0].len = 1;
msg[0].buf = (char *) ®
msg[1].addr = client->addr;
msg[1].flags = client->flags | I2C_M_RD;
msg[1].len = len;
msg[1].buf = (char *) val;
ret = i2c_transfer(client->adapter, msg, 2);
return (ret == 2) ? 0 : -EIO;
}
static int lidar_smbus_xfer(struct lidar_data *data, u8 reg, u8 *val, int len)
{
struct i2c_client *client = data->client;
int ret;
/*
* Device needs a STOP condition between address write, and data read
* so in turn i2c_smbus_read_byte_data cannot be used
*/
while (len--) {
ret = i2c_smbus_write_byte(client, reg++);
if (ret < 0) {
dev_err(&client->dev, "cannot write addr value");
return ret;
}
ret = i2c_smbus_read_byte(client);
if (ret < 0) {
dev_err(&client->dev, "cannot read data value");
return ret;
}
*(val++) = ret;
}
return 0;
}
static int lidar_read_byte(struct lidar_data *data, u8 reg)
{
int ret;
u8 val;
ret = data->xfer(data, reg, &val, 1);
if (ret < 0)
return ret;
return val;
}
static inline int lidar_write_control(struct lidar_data *data, int val)
{
return i2c_smbus_write_byte_data(data->client, LIDAR_REG_CONTROL, val);
}
static inline int lidar_write_power(struct lidar_data *data, int val)
{
return i2c_smbus_write_byte_data(data->client,
LIDAR_REG_PWR_CONTROL, val);
}
static int lidar_read_measurement(struct lidar_data *data, u16 *reg)
{
__be16 value;
int ret = data->xfer(data, LIDAR_REG_DATA_HBYTE |
(data->i2c_enabled ? LIDAR_REG_DATA_WORD_READ : 0),
(u8 *) &value, 2);
if (!ret)
*reg = be16_to_cpu(value);
return ret;
}
static int lidar_get_measurement(struct lidar_data *data, u16 *reg)
{
struct i2c_client *client = data->client;
int tries = 10;
int ret;
ret = pm_runtime_resume_and_get(&client->dev);
if (ret < 0)
return ret;
/* start sample */
ret = lidar_write_control(data, LIDAR_REG_CONTROL_ACQUIRE);
if (ret < 0) {
dev_err(&client->dev, "cannot send start measurement command");
pm_runtime_put_noidle(&client->dev);
return ret;
}
while (tries--) {
usleep_range(1000, 2000);
ret = lidar_read_byte(data, LIDAR_REG_STATUS);
if (ret < 0)
break;
/* return -EINVAL since laser is likely pointed out of range */
if (ret & LIDAR_REG_STATUS_INVALID) {
*reg = 0;
ret = -EINVAL;
break;
}
/* sample ready to read */
if (!(ret & LIDAR_REG_STATUS_READY)) {
ret = lidar_read_measurement(data, reg);
break;
}
ret = -EIO;
}
pm_runtime_mark_last_busy(&client->dev);
pm_runtime_put_autosuspend(&client->dev);
return ret;
}
static int lidar_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct lidar_data *data = iio_priv(indio_dev);
int ret = -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW: {
u16 reg;
if (iio_device_claim_direct_mode(indio_dev))
return -EBUSY;
ret = lidar_get_measurement(data, ®);
if (!ret) {
*val = reg;
ret = IIO_VAL_INT;
}
iio_device_release_direct_mode(indio_dev);
break;
}
case IIO_CHAN_INFO_SCALE:
*val = 0;
*val2 = 10000;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
}
return ret;
}
static irqreturn_t lidar_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct lidar_data *data = iio_priv(indio_dev);
int ret;
ret = lidar_get_measurement(data, &data->scan.chan);
if (!ret) {
iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
iio_get_time_ns(indio_dev));
} else if (ret != -EINVAL) {
dev_err(&data->client->dev, "cannot read LIDAR measurement");
}
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static const struct iio_info lidar_info = {
.read_raw = lidar_read_raw,
};
static int lidar_probe(struct i2c_client *client)
{
struct lidar_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
data->xfer = lidar_i2c_xfer;
data->i2c_enabled = 1;
} else if (i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BYTE))
data->xfer = lidar_smbus_xfer;
else
return -EOPNOTSUPP;
indio_dev->info = &lidar_info;
indio_dev->name = LIDAR_DRV_NAME;
indio_dev->channels = lidar_channels;
indio_dev->num_channels = ARRAY_SIZE(lidar_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->indio_dev = indio_dev;
ret = iio_triggered_buffer_setup(indio_dev, NULL,
lidar_trigger_handler, NULL);
if (ret)
return ret;
ret = iio_device_register(indio_dev);
if (ret)
goto error_unreg_buffer;
pm_runtime_set_autosuspend_delay(&client->dev, 1000);
pm_runtime_use_autosuspend(&client->dev);
ret = pm_runtime_set_active(&client->dev);
if (ret)
goto error_unreg_buffer;
pm_runtime_enable(&client->dev);
pm_runtime_idle(&client->dev);
return 0;
error_unreg_buffer:
iio_triggered_buffer_cleanup(indio_dev);
return ret;
}
static void lidar_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
iio_device_unregister(indio_dev);
iio_triggered_buffer_cleanup(indio_dev);
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
}
static const struct i2c_device_id lidar_id[] = {
{"lidar-lite-v2", 0},
{"lidar-lite-v3", 0},
{ },
};
MODULE_DEVICE_TABLE(i2c, lidar_id);
static const struct of_device_id lidar_dt_ids[] = {
{ .compatible = "pulsedlight,lidar-lite-v2" },
{ .compatible = "grmn,lidar-lite-v3" },
{ }
};
MODULE_DEVICE_TABLE(of, lidar_dt_ids);
static int lidar_pm_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct lidar_data *data = iio_priv(indio_dev);
return lidar_write_power(data, 0x0f);
}
static int lidar_pm_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct lidar_data *data = iio_priv(indio_dev);
int ret = lidar_write_power(data, 0);
/* regulator and FPGA needs settling time */
usleep_range(15000, 20000);
return ret;
}
static const struct dev_pm_ops lidar_pm_ops = {
RUNTIME_PM_OPS(lidar_pm_runtime_suspend, lidar_pm_runtime_resume, NULL)
};
static struct i2c_driver lidar_driver = {
.driver = {
.name = LIDAR_DRV_NAME,
.of_match_table = lidar_dt_ids,
.pm = pm_ptr(&lidar_pm_ops),
},
.probe = lidar_probe,
.remove = lidar_remove,
.id_table = lidar_id,
};
module_i2c_driver(lidar_driver);
MODULE_AUTHOR("Matt Ranostay <[email protected]>");
MODULE_DESCRIPTION("PulsedLight LIDAR sensor");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/proximity/pulsedlight-lidar-lite-v2.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* mb1232.c - Support for MaxBotix I2CXL-MaxSonar-EZ series ultrasonic
* ranger with i2c interface
* actually tested with mb1232 type
*
* Copyright (c) 2019 Andreas Klinger <[email protected]>
*
* For details about the device see:
* https://www.maxbotix.com/documents/I2CXL-MaxSonar-EZ_Datasheet.pdf
*/
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
/* registers of MaxSonar device */
#define MB1232_RANGE_COMMAND 0x51 /* Command for reading range */
#define MB1232_ADDR_UNLOCK_1 0xAA /* Command 1 for changing address */
#define MB1232_ADDR_UNLOCK_2 0xA5 /* Command 2 for changing address */
struct mb1232_data {
struct i2c_client *client;
struct mutex lock;
/*
* optionally a gpio can be used to announce when ranging has
* finished
* since we are just using the falling trigger of it we request
* only the interrupt for announcing when data is ready to be read
*/
struct completion ranging;
int irqnr;
/* Ensure correct alignment of data to push to IIO buffer */
struct {
s16 distance;
s64 ts __aligned(8);
} scan;
};
static irqreturn_t mb1232_handle_irq(int irq, void *dev_id)
{
struct iio_dev *indio_dev = dev_id;
struct mb1232_data *data = iio_priv(indio_dev);
complete(&data->ranging);
return IRQ_HANDLED;
}
static s16 mb1232_read_distance(struct mb1232_data *data)
{
struct i2c_client *client = data->client;
int ret;
s16 distance;
__be16 buf;
mutex_lock(&data->lock);
reinit_completion(&data->ranging);
ret = i2c_smbus_write_byte(client, MB1232_RANGE_COMMAND);
if (ret < 0) {
dev_err(&client->dev, "write command - err: %d\n", ret);
goto error_unlock;
}
if (data->irqnr > 0) {
/* it cannot take more than 100 ms */
ret = wait_for_completion_killable_timeout(&data->ranging,
HZ/10);
if (ret < 0)
goto error_unlock;
else if (ret == 0) {
ret = -ETIMEDOUT;
goto error_unlock;
}
} else {
/* use simple sleep if announce irq is not connected */
msleep(15);
}
ret = i2c_master_recv(client, (char *)&buf, sizeof(buf));
if (ret < 0) {
dev_err(&client->dev, "i2c_master_recv: ret=%d\n", ret);
goto error_unlock;
}
distance = __be16_to_cpu(buf);
/* check for not returning misleading error codes */
if (distance < 0) {
dev_err(&client->dev, "distance=%d\n", distance);
ret = -EINVAL;
goto error_unlock;
}
mutex_unlock(&data->lock);
return distance;
error_unlock:
mutex_unlock(&data->lock);
return ret;
}
static irqreturn_t mb1232_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct mb1232_data *data = iio_priv(indio_dev);
data->scan.distance = mb1232_read_distance(data);
if (data->scan.distance < 0)
goto err;
iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
pf->timestamp);
err:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int mb1232_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *channel, int *val,
int *val2, long mask)
{
struct mb1232_data *data = iio_priv(indio_dev);
int ret;
if (channel->type != IIO_DISTANCE)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = mb1232_read_distance(data);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/* 1 LSB is 1 cm */
*val = 0;
*val2 = 10000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static const struct iio_chan_spec mb1232_channels[] = {
{
.type = IIO_DISTANCE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 0,
.scan_type = {
.sign = 's',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_CPU,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static const struct iio_info mb1232_info = {
.read_raw = mb1232_read_raw,
};
static int mb1232_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct iio_dev *indio_dev;
struct mb1232_data *data;
int ret;
struct device *dev = &client->dev;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_READ_BYTE |
I2C_FUNC_SMBUS_WRITE_BYTE))
return -ENODEV;
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
indio_dev->info = &mb1232_info;
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = mb1232_channels;
indio_dev->num_channels = ARRAY_SIZE(mb1232_channels);
mutex_init(&data->lock);
init_completion(&data->ranging);
data->irqnr = fwnode_irq_get(dev_fwnode(&client->dev), 0);
if (data->irqnr > 0) {
ret = devm_request_irq(dev, data->irqnr, mb1232_handle_irq,
IRQF_TRIGGER_FALLING, id->name, indio_dev);
if (ret < 0) {
dev_err(dev, "request_irq: %d\n", ret);
return ret;
}
}
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
iio_pollfunc_store_time, mb1232_trigger_handler, NULL);
if (ret < 0) {
dev_err(dev, "setup of iio triggered buffer failed\n");
return ret;
}
return devm_iio_device_register(dev, indio_dev);
}
static const struct of_device_id of_mb1232_match[] = {
{ .compatible = "maxbotix,mb1202", },
{ .compatible = "maxbotix,mb1212", },
{ .compatible = "maxbotix,mb1222", },
{ .compatible = "maxbotix,mb1232", },
{ .compatible = "maxbotix,mb1242", },
{ .compatible = "maxbotix,mb7040", },
{ .compatible = "maxbotix,mb7137", },
{},
};
MODULE_DEVICE_TABLE(of, of_mb1232_match);
static const struct i2c_device_id mb1232_id[] = {
{ "maxbotix-mb1202", },
{ "maxbotix-mb1212", },
{ "maxbotix-mb1222", },
{ "maxbotix-mb1232", },
{ "maxbotix-mb1242", },
{ "maxbotix-mb7040", },
{ "maxbotix-mb7137", },
{ }
};
MODULE_DEVICE_TABLE(i2c, mb1232_id);
static struct i2c_driver mb1232_driver = {
.driver = {
.name = "maxbotix-mb1232",
.of_match_table = of_mb1232_match,
},
.probe = mb1232_probe,
.id_table = mb1232_id,
};
module_i2c_driver(mb1232_driver);
MODULE_AUTHOR("Andreas Klinger <[email protected]>");
MODULE_DESCRIPTION("Maxbotix I2CXL-MaxSonar i2c ultrasonic ranger driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/proximity/mb1232.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rfd77402.c - Support for RF Digital RFD77402 Time-of-Flight (distance) sensor
*
* Copyright 2017 Peter Meerwald-Stadler <[email protected]>
*
* 7-bit I2C slave address 0x4c
*
* TODO: interrupt
* https://media.digikey.com/pdf/Data%20Sheets/RF%20Digital%20PDFs/RFD77402.pdf
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#define RFD77402_DRV_NAME "rfd77402"
#define RFD77402_ICSR 0x00 /* Interrupt Control Status Register */
#define RFD77402_ICSR_INT_MODE BIT(2)
#define RFD77402_ICSR_INT_POL BIT(3)
#define RFD77402_ICSR_RESULT BIT(4)
#define RFD77402_ICSR_M2H_MSG BIT(5)
#define RFD77402_ICSR_H2M_MSG BIT(6)
#define RFD77402_ICSR_RESET BIT(7)
#define RFD77402_CMD_R 0x04
#define RFD77402_CMD_SINGLE 0x01
#define RFD77402_CMD_STANDBY 0x10
#define RFD77402_CMD_MCPU_OFF 0x11
#define RFD77402_CMD_MCPU_ON 0x12
#define RFD77402_CMD_RESET BIT(6)
#define RFD77402_CMD_VALID BIT(7)
#define RFD77402_STATUS_R 0x06
#define RFD77402_STATUS_PM_MASK GENMASK(4, 0)
#define RFD77402_STATUS_STANDBY 0x00
#define RFD77402_STATUS_MCPU_OFF 0x10
#define RFD77402_STATUS_MCPU_ON 0x18
#define RFD77402_RESULT_R 0x08
#define RFD77402_RESULT_DIST_MASK GENMASK(12, 2)
#define RFD77402_RESULT_ERR_MASK GENMASK(14, 13)
#define RFD77402_RESULT_VALID BIT(15)
#define RFD77402_PMU_CFG 0x14
#define RFD77402_PMU_MCPU_INIT BIT(9)
#define RFD77402_I2C_INIT_CFG 0x1c
#define RFD77402_I2C_ADDR_INCR BIT(0)
#define RFD77402_I2C_DATA_INCR BIT(2)
#define RFD77402_I2C_HOST_DEBUG BIT(5)
#define RFD77402_I2C_MCPU_DEBUG BIT(6)
#define RFD77402_CMD_CFGR_A 0x0c
#define RFD77402_CMD_CFGR_B 0x0e
#define RFD77402_HFCFG_0 0x20
#define RFD77402_HFCFG_1 0x22
#define RFD77402_HFCFG_2 0x24
#define RFD77402_HFCFG_3 0x26
#define RFD77402_MOD_CHIP_ID 0x28
/* magic configuration values from datasheet */
static const struct {
u8 reg;
u16 val;
} rf77402_tof_config[] = {
{RFD77402_CMD_CFGR_A, 0xe100},
{RFD77402_CMD_CFGR_B, 0x10ff},
{RFD77402_HFCFG_0, 0x07d0},
{RFD77402_HFCFG_1, 0x5008},
{RFD77402_HFCFG_2, 0xa041},
{RFD77402_HFCFG_3, 0x45d4},
};
struct rfd77402_data {
struct i2c_client *client;
/* Serialize reads from the sensor */
struct mutex lock;
};
static const struct iio_chan_spec rfd77402_channels[] = {
{
.type = IIO_DISTANCE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
};
static int rfd77402_set_state(struct i2c_client *client, u8 state, u16 check)
{
int ret;
ret = i2c_smbus_write_byte_data(client, RFD77402_CMD_R,
state | RFD77402_CMD_VALID);
if (ret < 0)
return ret;
usleep_range(10000, 20000);
ret = i2c_smbus_read_word_data(client, RFD77402_STATUS_R);
if (ret < 0)
return ret;
if ((ret & RFD77402_STATUS_PM_MASK) != check)
return -ENODEV;
return 0;
}
static int rfd77402_measure(struct i2c_client *client)
{
int ret;
int tries = 10;
ret = rfd77402_set_state(client, RFD77402_CMD_MCPU_ON,
RFD77402_STATUS_MCPU_ON);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(client, RFD77402_CMD_R,
RFD77402_CMD_SINGLE |
RFD77402_CMD_VALID);
if (ret < 0)
goto err;
while (tries-- > 0) {
ret = i2c_smbus_read_byte_data(client, RFD77402_ICSR);
if (ret < 0)
goto err;
if (ret & RFD77402_ICSR_RESULT)
break;
msleep(20);
}
if (tries < 0) {
ret = -ETIMEDOUT;
goto err;
}
ret = i2c_smbus_read_word_data(client, RFD77402_RESULT_R);
if (ret < 0)
goto err;
if ((ret & RFD77402_RESULT_ERR_MASK) ||
!(ret & RFD77402_RESULT_VALID)) {
ret = -EIO;
goto err;
}
return (ret & RFD77402_RESULT_DIST_MASK) >> 2;
err:
rfd77402_set_state(client, RFD77402_CMD_MCPU_OFF,
RFD77402_STATUS_MCPU_OFF);
return ret;
}
static int rfd77402_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct rfd77402_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&data->lock);
ret = rfd77402_measure(data->client);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/* 1 LSB is 1 mm */
*val = 0;
*val2 = 1000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static const struct iio_info rfd77402_info = {
.read_raw = rfd77402_read_raw,
};
static int rfd77402_init(struct i2c_client *client)
{
int ret, i;
ret = rfd77402_set_state(client, RFD77402_CMD_STANDBY,
RFD77402_STATUS_STANDBY);
if (ret < 0)
return ret;
/* configure INT pad as push-pull, active low */
ret = i2c_smbus_write_byte_data(client, RFD77402_ICSR,
RFD77402_ICSR_INT_MODE);
if (ret < 0)
return ret;
/* I2C configuration */
ret = i2c_smbus_write_word_data(client, RFD77402_I2C_INIT_CFG,
RFD77402_I2C_ADDR_INCR |
RFD77402_I2C_DATA_INCR |
RFD77402_I2C_HOST_DEBUG |
RFD77402_I2C_MCPU_DEBUG);
if (ret < 0)
return ret;
/* set initialization */
ret = i2c_smbus_write_word_data(client, RFD77402_PMU_CFG, 0x0500);
if (ret < 0)
return ret;
ret = rfd77402_set_state(client, RFD77402_CMD_MCPU_OFF,
RFD77402_STATUS_MCPU_OFF);
if (ret < 0)
return ret;
/* set initialization */
ret = i2c_smbus_write_word_data(client, RFD77402_PMU_CFG, 0x0600);
if (ret < 0)
return ret;
ret = rfd77402_set_state(client, RFD77402_CMD_MCPU_ON,
RFD77402_STATUS_MCPU_ON);
if (ret < 0)
return ret;
for (i = 0; i < ARRAY_SIZE(rf77402_tof_config); i++) {
ret = i2c_smbus_write_word_data(client,
rf77402_tof_config[i].reg,
rf77402_tof_config[i].val);
if (ret < 0)
return ret;
}
ret = rfd77402_set_state(client, RFD77402_CMD_STANDBY,
RFD77402_STATUS_STANDBY);
return ret;
}
static int rfd77402_powerdown(struct i2c_client *client)
{
return rfd77402_set_state(client, RFD77402_CMD_STANDBY,
RFD77402_STATUS_STANDBY);
}
static void rfd77402_disable(void *client)
{
rfd77402_powerdown(client);
}
static int rfd77402_probe(struct i2c_client *client)
{
struct rfd77402_data *data;
struct iio_dev *indio_dev;
int ret;
ret = i2c_smbus_read_word_data(client, RFD77402_MOD_CHIP_ID);
if (ret < 0)
return ret;
if (ret != 0xad01 && ret != 0xad02) /* known chip ids */
return -ENODEV;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->client = client;
mutex_init(&data->lock);
indio_dev->info = &rfd77402_info;
indio_dev->channels = rfd77402_channels;
indio_dev->num_channels = ARRAY_SIZE(rfd77402_channels);
indio_dev->name = RFD77402_DRV_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = rfd77402_init(client);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&client->dev, rfd77402_disable, client);
if (ret)
return ret;
return devm_iio_device_register(&client->dev, indio_dev);
}
static int rfd77402_suspend(struct device *dev)
{
return rfd77402_powerdown(to_i2c_client(dev));
}
static int rfd77402_resume(struct device *dev)
{
return rfd77402_init(to_i2c_client(dev));
}
static DEFINE_SIMPLE_DEV_PM_OPS(rfd77402_pm_ops, rfd77402_suspend,
rfd77402_resume);
static const struct i2c_device_id rfd77402_id[] = {
{ "rfd77402", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rfd77402_id);
static struct i2c_driver rfd77402_driver = {
.driver = {
.name = RFD77402_DRV_NAME,
.pm = pm_sleep_ptr(&rfd77402_pm_ops),
},
.probe = rfd77402_probe,
.id_table = rfd77402_id,
};
module_i2c_driver(rfd77402_driver);
MODULE_AUTHOR("Peter Meerwald-Stadler <[email protected]>");
MODULE_DESCRIPTION("RFD77402 Time-of-Flight sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/proximity/rfd77402.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Sensortek STK3310/STK3311 Ambient Light and Proximity Sensor
*
* Copyright (c) 2015, Intel Corporation.
*
* IIO driver for STK3310/STK3311. 7-bit I2C address: 0x48.
*/
#include <linux/acpi.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define STK3310_REG_STATE 0x00
#define STK3310_REG_PSCTRL 0x01
#define STK3310_REG_ALSCTRL 0x02
#define STK3310_REG_INT 0x04
#define STK3310_REG_THDH_PS 0x06
#define STK3310_REG_THDL_PS 0x08
#define STK3310_REG_FLAG 0x10
#define STK3310_REG_PS_DATA_MSB 0x11
#define STK3310_REG_PS_DATA_LSB 0x12
#define STK3310_REG_ALS_DATA_MSB 0x13
#define STK3310_REG_ALS_DATA_LSB 0x14
#define STK3310_REG_ID 0x3E
#define STK3310_MAX_REG 0x80
#define STK3310_STATE_EN_PS BIT(0)
#define STK3310_STATE_EN_ALS BIT(1)
#define STK3310_STATE_STANDBY 0x00
#define STK3310_CHIP_ID_VAL 0x13
#define STK3311_CHIP_ID_VAL 0x1D
#define STK3311X_CHIP_ID_VAL 0x12
#define STK3335_CHIP_ID_VAL 0x51
#define STK3310_PSINT_EN 0x01
#define STK3310_PS_MAX_VAL 0xFFFF
#define STK3310_DRIVER_NAME "stk3310"
#define STK3310_REGMAP_NAME "stk3310_regmap"
#define STK3310_EVENT "stk3310_event"
#define STK3310_SCALE_AVAILABLE "6.4 1.6 0.4 0.1"
#define STK3310_IT_AVAILABLE \
"0.000185 0.000370 0.000741 0.001480 0.002960 0.005920 0.011840 " \
"0.023680 0.047360 0.094720 0.189440 0.378880 0.757760 1.515520 " \
"3.031040 6.062080"
#define STK3310_REGFIELD(name) \
do { \
data->reg_##name = \
devm_regmap_field_alloc(&client->dev, regmap, \
stk3310_reg_field_##name); \
if (IS_ERR(data->reg_##name)) { \
dev_err(&client->dev, "reg field alloc failed.\n"); \
return PTR_ERR(data->reg_##name); \
} \
} while (0)
static const struct reg_field stk3310_reg_field_state =
REG_FIELD(STK3310_REG_STATE, 0, 2);
static const struct reg_field stk3310_reg_field_als_gain =
REG_FIELD(STK3310_REG_ALSCTRL, 4, 5);
static const struct reg_field stk3310_reg_field_ps_gain =
REG_FIELD(STK3310_REG_PSCTRL, 4, 5);
static const struct reg_field stk3310_reg_field_als_it =
REG_FIELD(STK3310_REG_ALSCTRL, 0, 3);
static const struct reg_field stk3310_reg_field_ps_it =
REG_FIELD(STK3310_REG_PSCTRL, 0, 3);
static const struct reg_field stk3310_reg_field_int_ps =
REG_FIELD(STK3310_REG_INT, 0, 2);
static const struct reg_field stk3310_reg_field_flag_psint =
REG_FIELD(STK3310_REG_FLAG, 4, 4);
static const struct reg_field stk3310_reg_field_flag_nf =
REG_FIELD(STK3310_REG_FLAG, 0, 0);
/* Estimate maximum proximity values with regard to measurement scale. */
static const int stk3310_ps_max[4] = {
STK3310_PS_MAX_VAL / 640,
STK3310_PS_MAX_VAL / 160,
STK3310_PS_MAX_VAL / 40,
STK3310_PS_MAX_VAL / 10
};
static const int stk3310_scale_table[][2] = {
{6, 400000}, {1, 600000}, {0, 400000}, {0, 100000}
};
/* Integration time in seconds, microseconds */
static const int stk3310_it_table[][2] = {
{0, 185}, {0, 370}, {0, 741}, {0, 1480},
{0, 2960}, {0, 5920}, {0, 11840}, {0, 23680},
{0, 47360}, {0, 94720}, {0, 189440}, {0, 378880},
{0, 757760}, {1, 515520}, {3, 31040}, {6, 62080},
};
struct stk3310_data {
struct i2c_client *client;
struct mutex lock;
bool als_enabled;
bool ps_enabled;
uint32_t ps_near_level;
u64 timestamp;
struct regmap *regmap;
struct regmap_field *reg_state;
struct regmap_field *reg_als_gain;
struct regmap_field *reg_ps_gain;
struct regmap_field *reg_als_it;
struct regmap_field *reg_ps_it;
struct regmap_field *reg_int_ps;
struct regmap_field *reg_flag_psint;
struct regmap_field *reg_flag_nf;
};
static const struct iio_event_spec stk3310_events[] = {
/* Proximity event */
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
/* Out-of-proximity event */
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static ssize_t stk3310_read_near_level(struct iio_dev *indio_dev,
uintptr_t priv,
const struct iio_chan_spec *chan,
char *buf)
{
struct stk3310_data *data = iio_priv(indio_dev);
return sprintf(buf, "%u\n", data->ps_near_level);
}
static const struct iio_chan_spec_ext_info stk3310_ext_info[] = {
{
.name = "nearlevel",
.shared = IIO_SEPARATE,
.read = stk3310_read_near_level,
},
{ /* sentinel */ }
};
static const struct iio_chan_spec stk3310_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_INT_TIME),
},
{
.type = IIO_PROXIMITY,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_INT_TIME),
.event_spec = stk3310_events,
.num_event_specs = ARRAY_SIZE(stk3310_events),
.ext_info = stk3310_ext_info,
}
};
static IIO_CONST_ATTR(in_illuminance_scale_available, STK3310_SCALE_AVAILABLE);
static IIO_CONST_ATTR(in_proximity_scale_available, STK3310_SCALE_AVAILABLE);
static IIO_CONST_ATTR(in_illuminance_integration_time_available,
STK3310_IT_AVAILABLE);
static IIO_CONST_ATTR(in_proximity_integration_time_available,
STK3310_IT_AVAILABLE);
static struct attribute *stk3310_attributes[] = {
&iio_const_attr_in_illuminance_scale_available.dev_attr.attr,
&iio_const_attr_in_proximity_scale_available.dev_attr.attr,
&iio_const_attr_in_illuminance_integration_time_available.dev_attr.attr,
&iio_const_attr_in_proximity_integration_time_available.dev_attr.attr,
NULL,
};
static const struct attribute_group stk3310_attribute_group = {
.attrs = stk3310_attributes
};
static int stk3310_get_index(const int table[][2], int table_size,
int val, int val2)
{
int i;
for (i = 0; i < table_size; i++) {
if (val == table[i][0] && val2 == table[i][1])
return i;
}
return -EINVAL;
}
static int stk3310_read_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
u8 reg;
__be16 buf;
int ret;
struct stk3310_data *data = iio_priv(indio_dev);
if (info != IIO_EV_INFO_VALUE)
return -EINVAL;
/* Only proximity interrupts are implemented at the moment. */
if (dir == IIO_EV_DIR_RISING)
reg = STK3310_REG_THDH_PS;
else if (dir == IIO_EV_DIR_FALLING)
reg = STK3310_REG_THDL_PS;
else
return -EINVAL;
mutex_lock(&data->lock);
ret = regmap_bulk_read(data->regmap, reg, &buf, 2);
mutex_unlock(&data->lock);
if (ret < 0) {
dev_err(&data->client->dev, "register read failed\n");
return ret;
}
*val = be16_to_cpu(buf);
return IIO_VAL_INT;
}
static int stk3310_write_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
u8 reg;
__be16 buf;
int ret;
unsigned int index;
struct stk3310_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
ret = regmap_field_read(data->reg_ps_gain, &index);
if (ret < 0)
return ret;
if (val < 0 || val > stk3310_ps_max[index])
return -EINVAL;
if (dir == IIO_EV_DIR_RISING)
reg = STK3310_REG_THDH_PS;
else if (dir == IIO_EV_DIR_FALLING)
reg = STK3310_REG_THDL_PS;
else
return -EINVAL;
buf = cpu_to_be16(val);
ret = regmap_bulk_write(data->regmap, reg, &buf, 2);
if (ret < 0)
dev_err(&client->dev, "failed to set PS threshold!\n");
return ret;
}
static int stk3310_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
unsigned int event_val;
int ret;
struct stk3310_data *data = iio_priv(indio_dev);
ret = regmap_field_read(data->reg_int_ps, &event_val);
if (ret < 0)
return ret;
return event_val;
}
static int stk3310_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
int ret;
struct stk3310_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
if (state < 0 || state > 7)
return -EINVAL;
/* Set INT_PS value */
mutex_lock(&data->lock);
ret = regmap_field_write(data->reg_int_ps, state);
if (ret < 0)
dev_err(&client->dev, "failed to set interrupt mode\n");
mutex_unlock(&data->lock);
return ret;
}
static int stk3310_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
u8 reg;
__be16 buf;
int ret;
unsigned int index;
struct stk3310_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
if (chan->type != IIO_LIGHT && chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (chan->type == IIO_LIGHT)
reg = STK3310_REG_ALS_DATA_MSB;
else
reg = STK3310_REG_PS_DATA_MSB;
mutex_lock(&data->lock);
ret = regmap_bulk_read(data->regmap, reg, &buf, 2);
if (ret < 0) {
dev_err(&client->dev, "register read failed\n");
mutex_unlock(&data->lock);
return ret;
}
*val = be16_to_cpu(buf);
mutex_unlock(&data->lock);
return IIO_VAL_INT;
case IIO_CHAN_INFO_INT_TIME:
if (chan->type == IIO_LIGHT)
ret = regmap_field_read(data->reg_als_it, &index);
else
ret = regmap_field_read(data->reg_ps_it, &index);
if (ret < 0)
return ret;
*val = stk3310_it_table[index][0];
*val2 = stk3310_it_table[index][1];
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_SCALE:
if (chan->type == IIO_LIGHT)
ret = regmap_field_read(data->reg_als_gain, &index);
else
ret = regmap_field_read(data->reg_ps_gain, &index);
if (ret < 0)
return ret;
*val = stk3310_scale_table[index][0];
*val2 = stk3310_scale_table[index][1];
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
}
static int stk3310_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
int ret;
int index;
struct stk3310_data *data = iio_priv(indio_dev);
if (chan->type != IIO_LIGHT && chan->type != IIO_PROXIMITY)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
index = stk3310_get_index(stk3310_it_table,
ARRAY_SIZE(stk3310_it_table),
val, val2);
if (index < 0)
return -EINVAL;
mutex_lock(&data->lock);
if (chan->type == IIO_LIGHT)
ret = regmap_field_write(data->reg_als_it, index);
else
ret = regmap_field_write(data->reg_ps_it, index);
if (ret < 0)
dev_err(&data->client->dev,
"sensor configuration failed\n");
mutex_unlock(&data->lock);
return ret;
case IIO_CHAN_INFO_SCALE:
index = stk3310_get_index(stk3310_scale_table,
ARRAY_SIZE(stk3310_scale_table),
val, val2);
if (index < 0)
return -EINVAL;
mutex_lock(&data->lock);
if (chan->type == IIO_LIGHT)
ret = regmap_field_write(data->reg_als_gain, index);
else
ret = regmap_field_write(data->reg_ps_gain, index);
if (ret < 0)
dev_err(&data->client->dev,
"sensor configuration failed\n");
mutex_unlock(&data->lock);
return ret;
}
return -EINVAL;
}
static const struct iio_info stk3310_info = {
.read_raw = stk3310_read_raw,
.write_raw = stk3310_write_raw,
.attrs = &stk3310_attribute_group,
.read_event_value = stk3310_read_event,
.write_event_value = stk3310_write_event,
.read_event_config = stk3310_read_event_config,
.write_event_config = stk3310_write_event_config,
};
static int stk3310_set_state(struct stk3310_data *data, u8 state)
{
int ret;
struct i2c_client *client = data->client;
/* 3-bit state; 0b100 is not supported. */
if (state > 7 || state == 4)
return -EINVAL;
mutex_lock(&data->lock);
ret = regmap_field_write(data->reg_state, state);
if (ret < 0) {
dev_err(&client->dev, "failed to change sensor state\n");
} else if (state != STK3310_STATE_STANDBY) {
/* Don't reset the 'enabled' flags if we're going in standby */
data->ps_enabled = !!(state & STK3310_STATE_EN_PS);
data->als_enabled = !!(state & STK3310_STATE_EN_ALS);
}
mutex_unlock(&data->lock);
return ret;
}
static int stk3310_init(struct iio_dev *indio_dev)
{
int ret;
int chipid;
u8 state;
struct stk3310_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
ret = regmap_read(data->regmap, STK3310_REG_ID, &chipid);
if (ret < 0)
return ret;
if (chipid != STK3310_CHIP_ID_VAL &&
chipid != STK3311_CHIP_ID_VAL &&
chipid != STK3311X_CHIP_ID_VAL &&
chipid != STK3335_CHIP_ID_VAL) {
dev_err(&client->dev, "invalid chip id: 0x%x\n", chipid);
return -ENODEV;
}
state = STK3310_STATE_EN_ALS | STK3310_STATE_EN_PS;
ret = stk3310_set_state(data, state);
if (ret < 0) {
dev_err(&client->dev, "failed to enable sensor");
return ret;
}
/* Enable PS interrupts */
ret = regmap_field_write(data->reg_int_ps, STK3310_PSINT_EN);
if (ret < 0)
dev_err(&client->dev, "failed to enable interrupts!\n");
return ret;
}
static bool stk3310_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case STK3310_REG_ALS_DATA_MSB:
case STK3310_REG_ALS_DATA_LSB:
case STK3310_REG_PS_DATA_LSB:
case STK3310_REG_PS_DATA_MSB:
case STK3310_REG_FLAG:
return true;
default:
return false;
}
}
static const struct regmap_config stk3310_regmap_config = {
.name = STK3310_REGMAP_NAME,
.reg_bits = 8,
.val_bits = 8,
.max_register = STK3310_MAX_REG,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = stk3310_is_volatile_reg,
};
static int stk3310_regmap_init(struct stk3310_data *data)
{
struct regmap *regmap;
struct i2c_client *client;
client = data->client;
regmap = devm_regmap_init_i2c(client, &stk3310_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "regmap initialization failed.\n");
return PTR_ERR(regmap);
}
data->regmap = regmap;
STK3310_REGFIELD(state);
STK3310_REGFIELD(als_gain);
STK3310_REGFIELD(ps_gain);
STK3310_REGFIELD(als_it);
STK3310_REGFIELD(ps_it);
STK3310_REGFIELD(int_ps);
STK3310_REGFIELD(flag_psint);
STK3310_REGFIELD(flag_nf);
return 0;
}
static irqreturn_t stk3310_irq_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct stk3310_data *data = iio_priv(indio_dev);
data->timestamp = iio_get_time_ns(indio_dev);
return IRQ_WAKE_THREAD;
}
static irqreturn_t stk3310_irq_event_handler(int irq, void *private)
{
int ret;
unsigned int dir;
u64 event;
struct iio_dev *indio_dev = private;
struct stk3310_data *data = iio_priv(indio_dev);
/* Read FLAG_NF to figure out what threshold has been met. */
mutex_lock(&data->lock);
ret = regmap_field_read(data->reg_flag_nf, &dir);
if (ret < 0) {
dev_err(&data->client->dev, "register read failed: %d\n", ret);
goto out;
}
event = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 1,
IIO_EV_TYPE_THRESH,
(dir ? IIO_EV_DIR_FALLING :
IIO_EV_DIR_RISING));
iio_push_event(indio_dev, event, data->timestamp);
/* Reset the interrupt flag */
ret = regmap_field_write(data->reg_flag_psint, 0);
if (ret < 0)
dev_err(&data->client->dev, "failed to reset interrupts\n");
out:
mutex_unlock(&data->lock);
return IRQ_HANDLED;
}
static int stk3310_probe(struct i2c_client *client)
{
int ret;
struct iio_dev *indio_dev;
struct stk3310_data *data;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev) {
dev_err(&client->dev, "iio allocation failed!\n");
return -ENOMEM;
}
data = iio_priv(indio_dev);
data->client = client;
i2c_set_clientdata(client, indio_dev);
device_property_read_u32(&client->dev, "proximity-near-level",
&data->ps_near_level);
mutex_init(&data->lock);
ret = stk3310_regmap_init(data);
if (ret < 0)
return ret;
indio_dev->info = &stk3310_info;
indio_dev->name = STK3310_DRIVER_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = stk3310_channels;
indio_dev->num_channels = ARRAY_SIZE(stk3310_channels);
ret = stk3310_init(indio_dev);
if (ret < 0)
return ret;
if (client->irq > 0) {
ret = devm_request_threaded_irq(&client->dev, client->irq,
stk3310_irq_handler,
stk3310_irq_event_handler,
IRQF_TRIGGER_FALLING |
IRQF_ONESHOT,
STK3310_EVENT, indio_dev);
if (ret < 0) {
dev_err(&client->dev, "request irq %d failed\n",
client->irq);
goto err_standby;
}
}
ret = iio_device_register(indio_dev);
if (ret < 0) {
dev_err(&client->dev, "device_register failed\n");
goto err_standby;
}
return 0;
err_standby:
stk3310_set_state(data, STK3310_STATE_STANDBY);
return ret;
}
static void stk3310_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
iio_device_unregister(indio_dev);
stk3310_set_state(iio_priv(indio_dev), STK3310_STATE_STANDBY);
}
static int stk3310_suspend(struct device *dev)
{
struct stk3310_data *data;
data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
return stk3310_set_state(data, STK3310_STATE_STANDBY);
}
static int stk3310_resume(struct device *dev)
{
u8 state = 0;
struct stk3310_data *data;
data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
if (data->ps_enabled)
state |= STK3310_STATE_EN_PS;
if (data->als_enabled)
state |= STK3310_STATE_EN_ALS;
return stk3310_set_state(data, state);
}
static DEFINE_SIMPLE_DEV_PM_OPS(stk3310_pm_ops, stk3310_suspend,
stk3310_resume);
static const struct i2c_device_id stk3310_i2c_id[] = {
{"STK3310", 0},
{"STK3311", 0},
{"STK3335", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, stk3310_i2c_id);
static const struct acpi_device_id stk3310_acpi_id[] = {
{"STK3310", 0},
{"STK3311", 0},
{"STK3335", 0},
{}
};
MODULE_DEVICE_TABLE(acpi, stk3310_acpi_id);
static const struct of_device_id stk3310_of_match[] = {
{ .compatible = "sensortek,stk3310", },
{ .compatible = "sensortek,stk3311", },
{ .compatible = "sensortek,stk3335", },
{}
};
MODULE_DEVICE_TABLE(of, stk3310_of_match);
static struct i2c_driver stk3310_driver = {
.driver = {
.name = "stk3310",
.of_match_table = stk3310_of_match,
.pm = pm_sleep_ptr(&stk3310_pm_ops),
.acpi_match_table = ACPI_PTR(stk3310_acpi_id),
},
.probe = stk3310_probe,
.remove = stk3310_remove,
.id_table = stk3310_i2c_id,
};
module_i2c_driver(stk3310_driver);
MODULE_AUTHOR("Tiberiu Breana <[email protected]>");
MODULE_DESCRIPTION("STK3310 Ambient Light and Proximity Sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/stk3310.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tcs3472.c - Support for TAOS TCS3472 color light-to-digital converter
*
* Copyright (c) 2013 Peter Meerwald <[email protected]>
*
* Color light sensor with 16-bit channels for red, green, blue, clear);
* 7-bit I2C slave address 0x39 (TCS34721, TCS34723) or 0x29 (TCS34725,
* TCS34727)
*
* Datasheet: http://ams.com/eng/content/download/319364/1117183/file/TCS3472_Datasheet_EN_v2.pdf
*
* TODO: wait time
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#define TCS3472_DRV_NAME "tcs3472"
#define TCS3472_COMMAND BIT(7)
#define TCS3472_AUTO_INCR BIT(5)
#define TCS3472_SPECIAL_FUNC (BIT(5) | BIT(6))
#define TCS3472_INTR_CLEAR (TCS3472_COMMAND | TCS3472_SPECIAL_FUNC | 0x06)
#define TCS3472_ENABLE (TCS3472_COMMAND | 0x00)
#define TCS3472_ATIME (TCS3472_COMMAND | 0x01)
#define TCS3472_WTIME (TCS3472_COMMAND | 0x03)
#define TCS3472_AILT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x04)
#define TCS3472_AIHT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x06)
#define TCS3472_PERS (TCS3472_COMMAND | 0x0c)
#define TCS3472_CONFIG (TCS3472_COMMAND | 0x0d)
#define TCS3472_CONTROL (TCS3472_COMMAND | 0x0f)
#define TCS3472_ID (TCS3472_COMMAND | 0x12)
#define TCS3472_STATUS (TCS3472_COMMAND | 0x13)
#define TCS3472_CDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x14)
#define TCS3472_RDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x16)
#define TCS3472_GDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x18)
#define TCS3472_BDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x1a)
#define TCS3472_STATUS_AINT BIT(4)
#define TCS3472_STATUS_AVALID BIT(0)
#define TCS3472_ENABLE_AIEN BIT(4)
#define TCS3472_ENABLE_AEN BIT(1)
#define TCS3472_ENABLE_PON BIT(0)
#define TCS3472_CONTROL_AGAIN_MASK (BIT(0) | BIT(1))
struct tcs3472_data {
struct i2c_client *client;
struct mutex lock;
u16 low_thresh;
u16 high_thresh;
u8 enable;
u8 control;
u8 atime;
u8 apers;
/* Ensure timestamp is naturally aligned */
struct {
u16 chans[4];
s64 timestamp __aligned(8);
} scan;
};
static const struct iio_event_spec tcs3472_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
BIT(IIO_EV_INFO_PERIOD),
},
};
#define TCS3472_CHANNEL(_color, _si, _addr) { \
.type = IIO_INTENSITY, \
.modified = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
BIT(IIO_CHAN_INFO_INT_TIME), \
.channel2 = IIO_MOD_LIGHT_##_color, \
.address = _addr, \
.scan_index = _si, \
.scan_type = { \
.sign = 'u', \
.realbits = 16, \
.storagebits = 16, \
.endianness = IIO_CPU, \
}, \
.event_spec = _si ? NULL : tcs3472_events, \
.num_event_specs = _si ? 0 : ARRAY_SIZE(tcs3472_events), \
}
static const int tcs3472_agains[] = { 1, 4, 16, 60 };
static const struct iio_chan_spec tcs3472_channels[] = {
TCS3472_CHANNEL(CLEAR, 0, TCS3472_CDATA),
TCS3472_CHANNEL(RED, 1, TCS3472_RDATA),
TCS3472_CHANNEL(GREEN, 2, TCS3472_GDATA),
TCS3472_CHANNEL(BLUE, 3, TCS3472_BDATA),
IIO_CHAN_SOFT_TIMESTAMP(4),
};
static int tcs3472_req_data(struct tcs3472_data *data)
{
int tries = 50;
int ret;
while (tries--) {
ret = i2c_smbus_read_byte_data(data->client, TCS3472_STATUS);
if (ret < 0)
return ret;
if (ret & TCS3472_STATUS_AVALID)
break;
msleep(20);
}
if (tries < 0) {
dev_err(&data->client->dev, "data not ready\n");
return -EIO;
}
return 0;
}
static int tcs3472_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct tcs3472_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = tcs3472_req_data(data);
if (ret < 0) {
iio_device_release_direct_mode(indio_dev);
return ret;
}
ret = i2c_smbus_read_word_data(data->client, chan->address);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBSCALE:
*val = tcs3472_agains[data->control &
TCS3472_CONTROL_AGAIN_MASK];
return IIO_VAL_INT;
case IIO_CHAN_INFO_INT_TIME:
*val = 0;
*val2 = (256 - data->atime) * 2400;
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
}
static int tcs3472_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct tcs3472_data *data = iio_priv(indio_dev);
int i;
switch (mask) {
case IIO_CHAN_INFO_CALIBSCALE:
if (val2 != 0)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(tcs3472_agains); i++) {
if (val == tcs3472_agains[i]) {
data->control &= ~TCS3472_CONTROL_AGAIN_MASK;
data->control |= i;
return i2c_smbus_write_byte_data(
data->client, TCS3472_CONTROL,
data->control);
}
}
return -EINVAL;
case IIO_CHAN_INFO_INT_TIME:
if (val != 0)
return -EINVAL;
for (i = 0; i < 256; i++) {
if (val2 == (256 - i) * 2400) {
data->atime = i;
return i2c_smbus_write_byte_data(
data->client, TCS3472_ATIME,
data->atime);
}
}
return -EINVAL;
}
return -EINVAL;
}
/*
* Translation from APERS field value to the number of consecutive out-of-range
* clear channel values before an interrupt is generated
*/
static const int tcs3472_intr_pers[] = {
0, 1, 2, 3, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60
};
static int tcs3472_read_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info, int *val,
int *val2)
{
struct tcs3472_data *data = iio_priv(indio_dev);
int ret;
unsigned int period;
mutex_lock(&data->lock);
switch (info) {
case IIO_EV_INFO_VALUE:
*val = (dir == IIO_EV_DIR_RISING) ?
data->high_thresh : data->low_thresh;
ret = IIO_VAL_INT;
break;
case IIO_EV_INFO_PERIOD:
period = (256 - data->atime) * 2400 *
tcs3472_intr_pers[data->apers];
*val = period / USEC_PER_SEC;
*val2 = period % USEC_PER_SEC;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&data->lock);
return ret;
}
static int tcs3472_write_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info, int val,
int val2)
{
struct tcs3472_data *data = iio_priv(indio_dev);
int ret;
u8 command;
int period;
int i;
mutex_lock(&data->lock);
switch (info) {
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
command = TCS3472_AIHT;
break;
case IIO_EV_DIR_FALLING:
command = TCS3472_AILT;
break;
default:
ret = -EINVAL;
goto error;
}
ret = i2c_smbus_write_word_data(data->client, command, val);
if (ret)
goto error;
if (dir == IIO_EV_DIR_RISING)
data->high_thresh = val;
else
data->low_thresh = val;
break;
case IIO_EV_INFO_PERIOD:
period = val * USEC_PER_SEC + val2;
for (i = 1; i < ARRAY_SIZE(tcs3472_intr_pers) - 1; i++) {
if (period <= (256 - data->atime) * 2400 *
tcs3472_intr_pers[i])
break;
}
ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS, i);
if (ret)
goto error;
data->apers = i;
break;
default:
ret = -EINVAL;
break;
}
error:
mutex_unlock(&data->lock);
return ret;
}
static int tcs3472_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir)
{
struct tcs3472_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->lock);
ret = !!(data->enable & TCS3472_ENABLE_AIEN);
mutex_unlock(&data->lock);
return ret;
}
static int tcs3472_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct tcs3472_data *data = iio_priv(indio_dev);
int ret = 0;
u8 enable_old;
mutex_lock(&data->lock);
enable_old = data->enable;
if (state)
data->enable |= TCS3472_ENABLE_AIEN;
else
data->enable &= ~TCS3472_ENABLE_AIEN;
if (enable_old != data->enable) {
ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
data->enable);
if (ret)
data->enable = enable_old;
}
mutex_unlock(&data->lock);
return ret;
}
static irqreturn_t tcs3472_event_handler(int irq, void *priv)
{
struct iio_dev *indio_dev = priv;
struct tcs3472_data *data = iio_priv(indio_dev);
int ret;
ret = i2c_smbus_read_byte_data(data->client, TCS3472_STATUS);
if (ret >= 0 && (ret & TCS3472_STATUS_AINT)) {
iio_push_event(indio_dev, IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(indio_dev));
i2c_smbus_read_byte_data(data->client, TCS3472_INTR_CLEAR);
}
return IRQ_HANDLED;
}
static irqreturn_t tcs3472_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct tcs3472_data *data = iio_priv(indio_dev);
int i, j = 0;
int ret = tcs3472_req_data(data);
if (ret < 0)
goto done;
for_each_set_bit(i, indio_dev->active_scan_mask,
indio_dev->masklength) {
ret = i2c_smbus_read_word_data(data->client,
TCS3472_CDATA + 2*i);
if (ret < 0)
goto done;
data->scan.chans[j++] = ret;
}
iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
iio_get_time_ns(indio_dev));
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static ssize_t tcs3472_show_int_time_available(struct device *dev,
struct device_attribute *attr,
char *buf)
{
size_t len = 0;
int i;
for (i = 1; i <= 256; i++)
len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06d ",
2400 * i);
/* replace trailing space by newline */
buf[len - 1] = '\n';
return len;
}
static IIO_CONST_ATTR(calibscale_available, "1 4 16 60");
static IIO_DEV_ATTR_INT_TIME_AVAIL(tcs3472_show_int_time_available);
static struct attribute *tcs3472_attributes[] = {
&iio_const_attr_calibscale_available.dev_attr.attr,
&iio_dev_attr_integration_time_available.dev_attr.attr,
NULL
};
static const struct attribute_group tcs3472_attribute_group = {
.attrs = tcs3472_attributes,
};
static const struct iio_info tcs3472_info = {
.read_raw = tcs3472_read_raw,
.write_raw = tcs3472_write_raw,
.read_event_value = tcs3472_read_event,
.write_event_value = tcs3472_write_event,
.read_event_config = tcs3472_read_event_config,
.write_event_config = tcs3472_write_event_config,
.attrs = &tcs3472_attribute_group,
};
static int tcs3472_probe(struct i2c_client *client)
{
struct tcs3472_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (indio_dev == NULL)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
mutex_init(&data->lock);
indio_dev->info = &tcs3472_info;
indio_dev->name = TCS3472_DRV_NAME;
indio_dev->channels = tcs3472_channels;
indio_dev->num_channels = ARRAY_SIZE(tcs3472_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = i2c_smbus_read_byte_data(data->client, TCS3472_ID);
if (ret < 0)
return ret;
if (ret == 0x44)
dev_info(&client->dev, "TCS34721/34725 found\n");
else if (ret == 0x4d)
dev_info(&client->dev, "TCS34723/34727 found\n");
else
return -ENODEV;
ret = i2c_smbus_read_byte_data(data->client, TCS3472_CONTROL);
if (ret < 0)
return ret;
data->control = ret;
ret = i2c_smbus_read_byte_data(data->client, TCS3472_ATIME);
if (ret < 0)
return ret;
data->atime = ret;
ret = i2c_smbus_read_word_data(data->client, TCS3472_AILT);
if (ret < 0)
return ret;
data->low_thresh = ret;
ret = i2c_smbus_read_word_data(data->client, TCS3472_AIHT);
if (ret < 0)
return ret;
data->high_thresh = ret;
data->apers = 1;
ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS,
data->apers);
if (ret < 0)
return ret;
ret = i2c_smbus_read_byte_data(data->client, TCS3472_ENABLE);
if (ret < 0)
return ret;
/* enable device */
data->enable = ret | TCS3472_ENABLE_PON | TCS3472_ENABLE_AEN;
data->enable &= ~TCS3472_ENABLE_AIEN;
ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
data->enable);
if (ret < 0)
return ret;
ret = iio_triggered_buffer_setup(indio_dev, NULL,
tcs3472_trigger_handler, NULL);
if (ret < 0)
return ret;
if (client->irq) {
ret = request_threaded_irq(client->irq, NULL,
tcs3472_event_handler,
IRQF_TRIGGER_FALLING | IRQF_SHARED |
IRQF_ONESHOT,
client->name, indio_dev);
if (ret)
goto buffer_cleanup;
}
ret = iio_device_register(indio_dev);
if (ret < 0)
goto free_irq;
return 0;
free_irq:
if (client->irq)
free_irq(client->irq, indio_dev);
buffer_cleanup:
iio_triggered_buffer_cleanup(indio_dev);
return ret;
}
static int tcs3472_powerdown(struct tcs3472_data *data)
{
int ret;
u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON;
mutex_lock(&data->lock);
ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
data->enable & ~enable_mask);
if (!ret)
data->enable &= ~enable_mask;
mutex_unlock(&data->lock);
return ret;
}
static void tcs3472_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
iio_device_unregister(indio_dev);
if (client->irq)
free_irq(client->irq, indio_dev);
iio_triggered_buffer_cleanup(indio_dev);
tcs3472_powerdown(iio_priv(indio_dev));
}
static int tcs3472_suspend(struct device *dev)
{
struct tcs3472_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
return tcs3472_powerdown(data);
}
static int tcs3472_resume(struct device *dev)
{
struct tcs3472_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
int ret;
u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON;
mutex_lock(&data->lock);
ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
data->enable | enable_mask);
if (!ret)
data->enable |= enable_mask;
mutex_unlock(&data->lock);
return ret;
}
static DEFINE_SIMPLE_DEV_PM_OPS(tcs3472_pm_ops, tcs3472_suspend,
tcs3472_resume);
static const struct i2c_device_id tcs3472_id[] = {
{ "tcs3472", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tcs3472_id);
static struct i2c_driver tcs3472_driver = {
.driver = {
.name = TCS3472_DRV_NAME,
.pm = pm_sleep_ptr(&tcs3472_pm_ops),
},
.probe = tcs3472_probe,
.remove = tcs3472_remove,
.id_table = tcs3472_id,
};
module_i2c_driver(tcs3472_driver);
MODULE_AUTHOR("Peter Meerwald <[email protected]>");
MODULE_DESCRIPTION("TCS3472 color light sensors driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/tcs3472.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MAX44000 Ambient and Infrared Proximity Sensor
*
* Copyright (c) 2016, Intel Corporation.
*
* Data sheet: https://datasheets.maximintegrated.com/en/ds/MAX44000.pdf
*
* 7-bit I2C slave address 0x4a
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/util_macros.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/acpi.h>
#define MAX44000_DRV_NAME "max44000"
/* Registers in datasheet order */
#define MAX44000_REG_STATUS 0x00
#define MAX44000_REG_CFG_MAIN 0x01
#define MAX44000_REG_CFG_RX 0x02
#define MAX44000_REG_CFG_TX 0x03
#define MAX44000_REG_ALS_DATA_HI 0x04
#define MAX44000_REG_ALS_DATA_LO 0x05
#define MAX44000_REG_PRX_DATA 0x16
#define MAX44000_REG_ALS_UPTHR_HI 0x06
#define MAX44000_REG_ALS_UPTHR_LO 0x07
#define MAX44000_REG_ALS_LOTHR_HI 0x08
#define MAX44000_REG_ALS_LOTHR_LO 0x09
#define MAX44000_REG_PST 0x0a
#define MAX44000_REG_PRX_IND 0x0b
#define MAX44000_REG_PRX_THR 0x0c
#define MAX44000_REG_TRIM_GAIN_GREEN 0x0f
#define MAX44000_REG_TRIM_GAIN_IR 0x10
/* REG_CFG bits */
#define MAX44000_CFG_ALSINTE 0x01
#define MAX44000_CFG_PRXINTE 0x02
#define MAX44000_CFG_MASK 0x1c
#define MAX44000_CFG_MODE_SHUTDOWN 0x00
#define MAX44000_CFG_MODE_ALS_GIR 0x04
#define MAX44000_CFG_MODE_ALS_G 0x08
#define MAX44000_CFG_MODE_ALS_IR 0x0c
#define MAX44000_CFG_MODE_ALS_PRX 0x10
#define MAX44000_CFG_MODE_PRX 0x14
#define MAX44000_CFG_TRIM 0x20
/*
* Upper 4 bits are not documented but start as 1 on powerup
* Setting them to 0 causes proximity to misbehave so set them to 1
*/
#define MAX44000_REG_CFG_RX_DEFAULT 0xf0
/* REG_RX bits */
#define MAX44000_CFG_RX_ALSTIM_MASK 0x0c
#define MAX44000_CFG_RX_ALSTIM_SHIFT 2
#define MAX44000_CFG_RX_ALSPGA_MASK 0x03
#define MAX44000_CFG_RX_ALSPGA_SHIFT 0
/* REG_TX bits */
#define MAX44000_LED_CURRENT_MASK 0xf
#define MAX44000_LED_CURRENT_MAX 11
#define MAX44000_LED_CURRENT_DEFAULT 6
#define MAX44000_ALSDATA_OVERFLOW 0x4000
struct max44000_data {
struct mutex lock;
struct regmap *regmap;
/* Ensure naturally aligned timestamp */
struct {
u16 channels[2];
s64 ts __aligned(8);
} scan;
};
/* Default scale is set to the minimum of 0.03125 or 1 / (1 << 5) lux */
#define MAX44000_ALS_TO_LUX_DEFAULT_FRACTION_LOG2 5
/* Scale can be multiplied by up to 128x via ALSPGA for measurement gain */
static const int max44000_alspga_shift[] = {0, 2, 4, 7};
#define MAX44000_ALSPGA_MAX_SHIFT 7
/*
* Scale can be multiplied by up to 64x via ALSTIM because of lost resolution
*
* This scaling factor is hidden from userspace and instead accounted for when
* reading raw values from the device.
*
* This makes it possible to cleanly expose ALSPGA as IIO_CHAN_INFO_SCALE and
* ALSTIM as IIO_CHAN_INFO_INT_TIME without the values affecting each other.
*
* Handling this internally is also required for buffer support because the
* channel's scan_type can't be modified dynamically.
*/
#define MAX44000_ALSTIM_SHIFT(alstim) (2 * (alstim))
/* Available integration times with pretty manual alignment: */
static const int max44000_int_time_avail_ns_array[] = {
100000000,
25000000,
6250000,
1562500,
};
static const char max44000_int_time_avail_str[] =
"0.100 "
"0.025 "
"0.00625 "
"0.0015625";
/* Available scales (internal to ulux) with pretty manual alignment: */
static const int max44000_scale_avail_ulux_array[] = {
31250,
125000,
500000,
4000000,
};
static const char max44000_scale_avail_str[] =
"0.03125 "
"0.125 "
"0.5 "
"4";
#define MAX44000_SCAN_INDEX_ALS 0
#define MAX44000_SCAN_INDEX_PRX 1
static const struct iio_chan_spec max44000_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_INT_TIME),
.scan_index = MAX44000_SCAN_INDEX_ALS,
.scan_type = {
.sign = 'u',
.realbits = 14,
.storagebits = 16,
}
},
{
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.scan_index = MAX44000_SCAN_INDEX_PRX,
.scan_type = {
.sign = 'u',
.realbits = 8,
.storagebits = 16,
}
},
IIO_CHAN_SOFT_TIMESTAMP(2),
{
.type = IIO_CURRENT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.extend_name = "led",
.output = 1,
.scan_index = -1,
},
};
static int max44000_read_alstim(struct max44000_data *data)
{
unsigned int val;
int ret;
ret = regmap_read(data->regmap, MAX44000_REG_CFG_RX, &val);
if (ret < 0)
return ret;
return (val & MAX44000_CFG_RX_ALSTIM_MASK) >> MAX44000_CFG_RX_ALSTIM_SHIFT;
}
static int max44000_write_alstim(struct max44000_data *data, int val)
{
return regmap_write_bits(data->regmap, MAX44000_REG_CFG_RX,
MAX44000_CFG_RX_ALSTIM_MASK,
val << MAX44000_CFG_RX_ALSTIM_SHIFT);
}
static int max44000_read_alspga(struct max44000_data *data)
{
unsigned int val;
int ret;
ret = regmap_read(data->regmap, MAX44000_REG_CFG_RX, &val);
if (ret < 0)
return ret;
return (val & MAX44000_CFG_RX_ALSPGA_MASK) >> MAX44000_CFG_RX_ALSPGA_SHIFT;
}
static int max44000_write_alspga(struct max44000_data *data, int val)
{
return regmap_write_bits(data->regmap, MAX44000_REG_CFG_RX,
MAX44000_CFG_RX_ALSPGA_MASK,
val << MAX44000_CFG_RX_ALSPGA_SHIFT);
}
static int max44000_read_alsval(struct max44000_data *data)
{
u16 regval;
__be16 val;
int alstim, ret;
ret = regmap_bulk_read(data->regmap, MAX44000_REG_ALS_DATA_HI,
&val, sizeof(val));
if (ret < 0)
return ret;
alstim = ret = max44000_read_alstim(data);
if (ret < 0)
return ret;
regval = be16_to_cpu(val);
/*
* Overflow is explained on datasheet page 17.
*
* It's a warning that either the G or IR channel has become saturated
* and that the value in the register is likely incorrect.
*
* The recommendation is to change the scale (ALSPGA).
* The driver just returns the max representable value.
*/
if (regval & MAX44000_ALSDATA_OVERFLOW)
return 0x3FFF;
return regval << MAX44000_ALSTIM_SHIFT(alstim);
}
static int max44000_write_led_current_raw(struct max44000_data *data, int val)
{
/* Maybe we should clamp the value instead? */
if (val < 0 || val > MAX44000_LED_CURRENT_MAX)
return -ERANGE;
if (val >= 8)
val += 4;
return regmap_write_bits(data->regmap, MAX44000_REG_CFG_TX,
MAX44000_LED_CURRENT_MASK, val);
}
static int max44000_read_led_current_raw(struct max44000_data *data)
{
unsigned int regval;
int ret;
ret = regmap_read(data->regmap, MAX44000_REG_CFG_TX, ®val);
if (ret < 0)
return ret;
regval &= MAX44000_LED_CURRENT_MASK;
if (regval >= 8)
regval -= 4;
return regval;
}
static int max44000_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct max44000_data *data = iio_priv(indio_dev);
int alstim, alspga;
unsigned int regval;
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_LIGHT:
mutex_lock(&data->lock);
ret = max44000_read_alsval(data);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_PROXIMITY:
mutex_lock(&data->lock);
ret = regmap_read(data->regmap, MAX44000_REG_PRX_DATA, ®val);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
*val = regval;
return IIO_VAL_INT;
case IIO_CURRENT:
mutex_lock(&data->lock);
ret = max44000_read_led_current_raw(data);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_CURRENT:
/* Output register is in 10s of miliamps */
*val = 10;
return IIO_VAL_INT;
case IIO_LIGHT:
mutex_lock(&data->lock);
alspga = ret = max44000_read_alspga(data);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
/* Avoid negative shifts */
*val = (1 << MAX44000_ALSPGA_MAX_SHIFT);
*val2 = MAX44000_ALS_TO_LUX_DEFAULT_FRACTION_LOG2
+ MAX44000_ALSPGA_MAX_SHIFT
- max44000_alspga_shift[alspga];
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_INT_TIME:
mutex_lock(&data->lock);
alstim = ret = max44000_read_alstim(data);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
*val = 0;
*val2 = max44000_int_time_avail_ns_array[alstim];
return IIO_VAL_INT_PLUS_NANO;
default:
return -EINVAL;
}
}
static int max44000_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct max44000_data *data = iio_priv(indio_dev);
int ret;
if (mask == IIO_CHAN_INFO_RAW && chan->type == IIO_CURRENT) {
mutex_lock(&data->lock);
ret = max44000_write_led_current_raw(data, val);
mutex_unlock(&data->lock);
return ret;
} else if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT) {
s64 valns = val * NSEC_PER_SEC + val2;
int alstim = find_closest_descending(valns,
max44000_int_time_avail_ns_array,
ARRAY_SIZE(max44000_int_time_avail_ns_array));
mutex_lock(&data->lock);
ret = max44000_write_alstim(data, alstim);
mutex_unlock(&data->lock);
return ret;
} else if (mask == IIO_CHAN_INFO_SCALE && chan->type == IIO_LIGHT) {
s64 valus = val * USEC_PER_SEC + val2;
int alspga = find_closest(valus,
max44000_scale_avail_ulux_array,
ARRAY_SIZE(max44000_scale_avail_ulux_array));
mutex_lock(&data->lock);
ret = max44000_write_alspga(data, alspga);
mutex_unlock(&data->lock);
return ret;
}
return -EINVAL;
}
static int max44000_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
long mask)
{
if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT)
return IIO_VAL_INT_PLUS_NANO;
else if (mask == IIO_CHAN_INFO_SCALE && chan->type == IIO_LIGHT)
return IIO_VAL_INT_PLUS_MICRO;
else
return IIO_VAL_INT;
}
static IIO_CONST_ATTR(illuminance_integration_time_available, max44000_int_time_avail_str);
static IIO_CONST_ATTR(illuminance_scale_available, max44000_scale_avail_str);
static struct attribute *max44000_attributes[] = {
&iio_const_attr_illuminance_integration_time_available.dev_attr.attr,
&iio_const_attr_illuminance_scale_available.dev_attr.attr,
NULL
};
static const struct attribute_group max44000_attribute_group = {
.attrs = max44000_attributes,
};
static const struct iio_info max44000_info = {
.read_raw = max44000_read_raw,
.write_raw = max44000_write_raw,
.write_raw_get_fmt = max44000_write_raw_get_fmt,
.attrs = &max44000_attribute_group,
};
static bool max44000_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX44000_REG_STATUS:
case MAX44000_REG_CFG_MAIN:
case MAX44000_REG_CFG_RX:
case MAX44000_REG_CFG_TX:
case MAX44000_REG_ALS_DATA_HI:
case MAX44000_REG_ALS_DATA_LO:
case MAX44000_REG_PRX_DATA:
case MAX44000_REG_ALS_UPTHR_HI:
case MAX44000_REG_ALS_UPTHR_LO:
case MAX44000_REG_ALS_LOTHR_HI:
case MAX44000_REG_ALS_LOTHR_LO:
case MAX44000_REG_PST:
case MAX44000_REG_PRX_IND:
case MAX44000_REG_PRX_THR:
case MAX44000_REG_TRIM_GAIN_GREEN:
case MAX44000_REG_TRIM_GAIN_IR:
return true;
default:
return false;
}
}
static bool max44000_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX44000_REG_CFG_MAIN:
case MAX44000_REG_CFG_RX:
case MAX44000_REG_CFG_TX:
case MAX44000_REG_ALS_UPTHR_HI:
case MAX44000_REG_ALS_UPTHR_LO:
case MAX44000_REG_ALS_LOTHR_HI:
case MAX44000_REG_ALS_LOTHR_LO:
case MAX44000_REG_PST:
case MAX44000_REG_PRX_IND:
case MAX44000_REG_PRX_THR:
case MAX44000_REG_TRIM_GAIN_GREEN:
case MAX44000_REG_TRIM_GAIN_IR:
return true;
default:
return false;
}
}
static bool max44000_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX44000_REG_STATUS:
case MAX44000_REG_ALS_DATA_HI:
case MAX44000_REG_ALS_DATA_LO:
case MAX44000_REG_PRX_DATA:
return true;
default:
return false;
}
}
static bool max44000_precious_reg(struct device *dev, unsigned int reg)
{
return reg == MAX44000_REG_STATUS;
}
static const struct regmap_config max44000_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX44000_REG_PRX_DATA,
.readable_reg = max44000_readable_reg,
.writeable_reg = max44000_writeable_reg,
.volatile_reg = max44000_volatile_reg,
.precious_reg = max44000_precious_reg,
.use_single_read = true,
.use_single_write = true,
.cache_type = REGCACHE_RBTREE,
};
static irqreturn_t max44000_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct max44000_data *data = iio_priv(indio_dev);
int index = 0;
unsigned int regval;
int ret;
mutex_lock(&data->lock);
if (test_bit(MAX44000_SCAN_INDEX_ALS, indio_dev->active_scan_mask)) {
ret = max44000_read_alsval(data);
if (ret < 0)
goto out_unlock;
data->scan.channels[index++] = ret;
}
if (test_bit(MAX44000_SCAN_INDEX_PRX, indio_dev->active_scan_mask)) {
ret = regmap_read(data->regmap, MAX44000_REG_PRX_DATA, ®val);
if (ret < 0)
goto out_unlock;
data->scan.channels[index] = regval;
}
mutex_unlock(&data->lock);
iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
iio_get_time_ns(indio_dev));
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
out_unlock:
mutex_unlock(&data->lock);
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int max44000_probe(struct i2c_client *client)
{
struct max44000_data *data;
struct iio_dev *indio_dev;
int ret, reg;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->regmap = devm_regmap_init_i2c(client, &max44000_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(&client->dev, "regmap_init failed!\n");
return PTR_ERR(data->regmap);
}
mutex_init(&data->lock);
indio_dev->info = &max44000_info;
indio_dev->name = MAX44000_DRV_NAME;
indio_dev->channels = max44000_channels;
indio_dev->num_channels = ARRAY_SIZE(max44000_channels);
/*
* The device doesn't have a reset function so we just clear some
* important bits at probe time to ensure sane operation.
*
* Since we don't support interrupts/events the threshold values are
* not important. We also don't touch trim values.
*/
/* Reset ALS scaling bits */
ret = regmap_write(data->regmap, MAX44000_REG_CFG_RX,
MAX44000_REG_CFG_RX_DEFAULT);
if (ret < 0) {
dev_err(&client->dev, "failed to write default CFG_RX: %d\n",
ret);
return ret;
}
/*
* By default the LED pulse used for the proximity sensor is disabled.
* Set a middle value so that we get some sort of valid data by default.
*/
ret = max44000_write_led_current_raw(data, MAX44000_LED_CURRENT_DEFAULT);
if (ret < 0) {
dev_err(&client->dev, "failed to write init config: %d\n", ret);
return ret;
}
/* Reset CFG bits to ALS_PRX mode which allows easy reading of both values. */
reg = MAX44000_CFG_TRIM | MAX44000_CFG_MODE_ALS_PRX;
ret = regmap_write(data->regmap, MAX44000_REG_CFG_MAIN, reg);
if (ret < 0) {
dev_err(&client->dev, "failed to write init config: %d\n", ret);
return ret;
}
/* Read status at least once to clear any stale interrupt bits. */
ret = regmap_read(data->regmap, MAX44000_REG_STATUS, ®);
if (ret < 0) {
dev_err(&client->dev, "failed to read init status: %d\n", ret);
return ret;
}
ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
max44000_trigger_handler, NULL);
if (ret < 0) {
dev_err(&client->dev, "iio triggered buffer setup failed\n");
return ret;
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id max44000_id[] = {
{"max44000", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, max44000_id);
#ifdef CONFIG_ACPI
static const struct acpi_device_id max44000_acpi_match[] = {
{"MAX44000", 0},
{ }
};
MODULE_DEVICE_TABLE(acpi, max44000_acpi_match);
#endif
static struct i2c_driver max44000_driver = {
.driver = {
.name = MAX44000_DRV_NAME,
.acpi_match_table = ACPI_PTR(max44000_acpi_match),
},
.probe = max44000_probe,
.id_table = max44000_id,
};
module_i2c_driver(max44000_driver);
MODULE_AUTHOR("Crestez Dan Leonard <[email protected]>");
MODULE_DESCRIPTION("MAX44000 Ambient and Infrared Proximity Sensor");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/max44000.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* CM3605 Ambient Light and Proximity Sensor
*
* Copyright (C) 2016 Linaro Ltd.
* Author: Linus Walleij <[email protected]>
*
* This hardware was found in the very first Nexus One handset from Google/HTC
* and an early endavour into mobile light and proximity sensors.
*/
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
#include <linux/iio/consumer.h> /* To get our ADC channel */
#include <linux/iio/types.h> /* To deal with our ADC channel */
#include <linux/init.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/math64.h>
#include <linux/pm.h>
#define CM3605_PROX_CHANNEL 0
#define CM3605_ALS_CHANNEL 1
#define CM3605_AOUT_TYP_MAX_MV 1550
/* It should not go above 1.650V according to the data sheet */
#define CM3605_AOUT_MAX_MV 1650
/**
* struct cm3605 - CM3605 state
* @dev: pointer to parent device
* @vdd: regulator controlling VDD
* @aset: sleep enable GPIO, high = sleep
* @aout: IIO ADC channel to convert the AOUT signal
* @als_max: maximum LUX detection (depends on RSET)
* @dir: proximity direction: start as FALLING
* @led: trigger for the infrared LED used by the proximity sensor
*/
struct cm3605 {
struct device *dev;
struct regulator *vdd;
struct gpio_desc *aset;
struct iio_channel *aout;
s32 als_max;
enum iio_event_direction dir;
struct led_trigger *led;
};
static irqreturn_t cm3605_prox_irq(int irq, void *d)
{
struct iio_dev *indio_dev = d;
struct cm3605 *cm3605 = iio_priv(indio_dev);
u64 ev;
ev = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, CM3605_PROX_CHANNEL,
IIO_EV_TYPE_THRESH, cm3605->dir);
iio_push_event(indio_dev, ev, iio_get_time_ns(indio_dev));
/* Invert the edge for each event */
if (cm3605->dir == IIO_EV_DIR_RISING)
cm3605->dir = IIO_EV_DIR_FALLING;
else
cm3605->dir = IIO_EV_DIR_RISING;
return IRQ_HANDLED;
}
static int cm3605_get_lux(struct cm3605 *cm3605)
{
int ret, res;
s64 lux;
ret = iio_read_channel_processed(cm3605->aout, &res);
if (ret < 0)
return ret;
dev_dbg(cm3605->dev, "read %d mV from ADC\n", res);
/*
* AOUT has an offset of ~30mV then linear at dark
* then goes from 2.54 up to 650 LUX yielding 1.55V
* (1550 mV) so scale the returned value to this interval
* using simple linear interpolation.
*/
if (res < 30)
return 0;
if (res > CM3605_AOUT_MAX_MV)
dev_err(cm3605->dev, "device out of range\n");
/* Remove bias */
lux = res - 30;
/* Linear interpolation between 0 and ALS typ max */
lux *= cm3605->als_max;
lux = div64_s64(lux, CM3605_AOUT_TYP_MAX_MV);
return lux;
}
static int cm3605_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct cm3605 *cm3605 = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_LIGHT:
ret = cm3605_get_lux(cm3605);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static const struct iio_info cm3605_info = {
.read_raw = cm3605_read_raw,
};
static const struct iio_event_spec cm3605_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec cm3605_channels[] = {
{
.type = IIO_PROXIMITY,
.event_spec = cm3605_events,
.num_event_specs = ARRAY_SIZE(cm3605_events),
},
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.channel = CM3605_ALS_CHANNEL,
},
};
static int cm3605_probe(struct platform_device *pdev)
{
struct cm3605 *cm3605;
struct iio_dev *indio_dev;
struct device *dev = &pdev->dev;
enum iio_chan_type ch_type;
u32 rset;
int irq;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*cm3605));
if (!indio_dev)
return -ENOMEM;
platform_set_drvdata(pdev, indio_dev);
cm3605 = iio_priv(indio_dev);
cm3605->dev = dev;
cm3605->dir = IIO_EV_DIR_FALLING;
ret = device_property_read_u32(dev, "capella,aset-resistance-ohms", &rset);
if (ret) {
dev_info(dev, "no RSET specified, assuming 100K\n");
rset = 100000;
}
switch (rset) {
case 50000:
cm3605->als_max = 650;
break;
case 100000:
cm3605->als_max = 300;
break;
case 300000:
cm3605->als_max = 100;
break;
case 600000:
cm3605->als_max = 50;
break;
default:
dev_info(dev, "non-standard resistance\n");
return -EINVAL;
}
cm3605->aout = devm_iio_channel_get(dev, "aout");
if (IS_ERR(cm3605->aout)) {
ret = PTR_ERR(cm3605->aout);
ret = (ret == -ENODEV) ? -EPROBE_DEFER : ret;
return dev_err_probe(dev, ret, "failed to get AOUT ADC channel\n");
}
ret = iio_get_channel_type(cm3605->aout, &ch_type);
if (ret < 0)
return ret;
if (ch_type != IIO_VOLTAGE) {
dev_err(dev, "wrong type of IIO channel specified for AOUT\n");
return -EINVAL;
}
cm3605->vdd = devm_regulator_get(dev, "vdd");
if (IS_ERR(cm3605->vdd))
return dev_err_probe(dev, PTR_ERR(cm3605->vdd),
"failed to get VDD regulator\n");
ret = regulator_enable(cm3605->vdd);
if (ret) {
dev_err(dev, "failed to enable VDD regulator\n");
return ret;
}
cm3605->aset = devm_gpiod_get(dev, "aset", GPIOD_OUT_HIGH);
if (IS_ERR(cm3605->aset)) {
ret = dev_err_probe(dev, PTR_ERR(cm3605->aset), "no ASET GPIO\n");
goto out_disable_vdd;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = irq;
goto out_disable_aset;
}
ret = devm_request_threaded_irq(dev, irq, cm3605_prox_irq,
NULL, 0, "cm3605", indio_dev);
if (ret) {
dev_err(dev, "unable to request IRQ\n");
goto out_disable_aset;
}
/* Just name the trigger the same as the driver */
led_trigger_register_simple("cm3605", &cm3605->led);
led_trigger_event(cm3605->led, LED_FULL);
indio_dev->info = &cm3605_info;
indio_dev->name = "cm3605";
indio_dev->channels = cm3605_channels;
indio_dev->num_channels = ARRAY_SIZE(cm3605_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(indio_dev);
if (ret)
goto out_remove_trigger;
dev_info(dev, "Capella Microsystems CM3605 enabled range 0..%d LUX\n",
cm3605->als_max);
return 0;
out_remove_trigger:
led_trigger_event(cm3605->led, LED_OFF);
led_trigger_unregister_simple(cm3605->led);
out_disable_aset:
gpiod_set_value_cansleep(cm3605->aset, 0);
out_disable_vdd:
regulator_disable(cm3605->vdd);
return ret;
}
static int cm3605_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct cm3605 *cm3605 = iio_priv(indio_dev);
led_trigger_event(cm3605->led, LED_OFF);
led_trigger_unregister_simple(cm3605->led);
gpiod_set_value_cansleep(cm3605->aset, 0);
iio_device_unregister(indio_dev);
regulator_disable(cm3605->vdd);
return 0;
}
static int cm3605_pm_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct cm3605 *cm3605 = iio_priv(indio_dev);
led_trigger_event(cm3605->led, LED_OFF);
regulator_disable(cm3605->vdd);
return 0;
}
static int cm3605_pm_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct cm3605 *cm3605 = iio_priv(indio_dev);
int ret;
ret = regulator_enable(cm3605->vdd);
if (ret)
dev_err(dev, "failed to enable regulator in resume path\n");
led_trigger_event(cm3605->led, LED_FULL);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(cm3605_dev_pm_ops, cm3605_pm_suspend,
cm3605_pm_resume);
static const struct of_device_id cm3605_of_match[] = {
{.compatible = "capella,cm3605"},
{ },
};
MODULE_DEVICE_TABLE(of, cm3605_of_match);
static struct platform_driver cm3605_driver = {
.driver = {
.name = "cm3605",
.of_match_table = cm3605_of_match,
.pm = pm_sleep_ptr(&cm3605_dev_pm_ops),
},
.probe = cm3605_probe,
.remove = cm3605_remove,
};
module_platform_driver(cm3605_driver);
MODULE_AUTHOR("Linus Walleij <[email protected]>");
MODULE_DESCRIPTION("CM3605 ambient light and proximity sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/cm3605.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* vl6180.c - Support for STMicroelectronics VL6180 ALS, range and proximity
* sensor
*
* Copyright 2017 Peter Meerwald-Stadler <[email protected]>
* Copyright 2017 Manivannan Sadhasivam <[email protected]>
*
* IIO driver for VL6180 (7-bit I2C slave address 0x29)
*
* Range: 0 to 100mm
* ALS: < 1 Lux up to 100 kLux
* IR: 850nm
*
* TODO: irq, threshold events, continuous mode, hardware buffer
*/
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/util_macros.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define VL6180_DRV_NAME "vl6180"
/* Device identification register and value */
#define VL6180_MODEL_ID 0x000
#define VL6180_MODEL_ID_VAL 0xb4
/* Configuration registers */
#define VL6180_INTR_CONFIG 0x014
#define VL6180_INTR_CLEAR 0x015
#define VL6180_OUT_OF_RESET 0x016
#define VL6180_HOLD 0x017
#define VL6180_RANGE_START 0x018
#define VL6180_ALS_START 0x038
#define VL6180_ALS_GAIN 0x03f
#define VL6180_ALS_IT 0x040
/* Status registers */
#define VL6180_RANGE_STATUS 0x04d
#define VL6180_ALS_STATUS 0x04e
#define VL6180_INTR_STATUS 0x04f
/* Result value registers */
#define VL6180_ALS_VALUE 0x050
#define VL6180_RANGE_VALUE 0x062
#define VL6180_RANGE_RATE 0x066
/* bits of the RANGE_START and ALS_START register */
#define VL6180_MODE_CONT BIT(1) /* continuous mode */
#define VL6180_STARTSTOP BIT(0) /* start measurement, auto-reset */
/* bits of the INTR_STATUS and INTR_CONFIG register */
#define VL6180_ALS_READY BIT(5)
#define VL6180_RANGE_READY BIT(2)
/* bits of the INTR_CLEAR register */
#define VL6180_CLEAR_ERROR BIT(2)
#define VL6180_CLEAR_ALS BIT(1)
#define VL6180_CLEAR_RANGE BIT(0)
/* bits of the HOLD register */
#define VL6180_HOLD_ON BIT(0)
/* default value for the ALS_IT register */
#define VL6180_ALS_IT_100 0x63 /* 100 ms */
/* values for the ALS_GAIN register */
#define VL6180_ALS_GAIN_1 0x46
#define VL6180_ALS_GAIN_1_25 0x45
#define VL6180_ALS_GAIN_1_67 0x44
#define VL6180_ALS_GAIN_2_5 0x43
#define VL6180_ALS_GAIN_5 0x42
#define VL6180_ALS_GAIN_10 0x41
#define VL6180_ALS_GAIN_20 0x40
#define VL6180_ALS_GAIN_40 0x47
struct vl6180_data {
struct i2c_client *client;
struct mutex lock;
unsigned int als_gain_milli;
unsigned int als_it_ms;
};
enum { VL6180_ALS, VL6180_RANGE, VL6180_PROX };
/**
* struct vl6180_chan_regs - Registers for accessing channels
* @drdy_mask: Data ready bit in status register
* @start_reg: Conversion start register
* @value_reg: Result value register
* @word: Register word length
*/
struct vl6180_chan_regs {
u8 drdy_mask;
u16 start_reg, value_reg;
bool word;
};
static const struct vl6180_chan_regs vl6180_chan_regs_table[] = {
[VL6180_ALS] = {
.drdy_mask = VL6180_ALS_READY,
.start_reg = VL6180_ALS_START,
.value_reg = VL6180_ALS_VALUE,
.word = true,
},
[VL6180_RANGE] = {
.drdy_mask = VL6180_RANGE_READY,
.start_reg = VL6180_RANGE_START,
.value_reg = VL6180_RANGE_VALUE,
.word = false,
},
[VL6180_PROX] = {
.drdy_mask = VL6180_RANGE_READY,
.start_reg = VL6180_RANGE_START,
.value_reg = VL6180_RANGE_RATE,
.word = true,
},
};
static int vl6180_read(struct i2c_client *client, u16 cmd, void *databuf,
u8 len)
{
__be16 cmdbuf = cpu_to_be16(cmd);
struct i2c_msg msgs[2] = {
{ .addr = client->addr, .len = sizeof(cmdbuf), .buf = (u8 *) &cmdbuf },
{ .addr = client->addr, .len = len, .buf = databuf,
.flags = I2C_M_RD } };
int ret;
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret < 0)
dev_err(&client->dev, "failed reading register 0x%04x\n", cmd);
return ret;
}
static int vl6180_read_byte(struct i2c_client *client, u16 cmd)
{
u8 data;
int ret;
ret = vl6180_read(client, cmd, &data, sizeof(data));
if (ret < 0)
return ret;
return data;
}
static int vl6180_read_word(struct i2c_client *client, u16 cmd)
{
__be16 data;
int ret;
ret = vl6180_read(client, cmd, &data, sizeof(data));
if (ret < 0)
return ret;
return be16_to_cpu(data);
}
static int vl6180_write_byte(struct i2c_client *client, u16 cmd, u8 val)
{
u8 buf[3];
struct i2c_msg msgs[1] = {
{ .addr = client->addr, .len = sizeof(buf), .buf = (u8 *) &buf } };
int ret;
buf[0] = cmd >> 8;
buf[1] = cmd & 0xff;
buf[2] = val;
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret < 0) {
dev_err(&client->dev, "failed writing register 0x%04x\n", cmd);
return ret;
}
return 0;
}
static int vl6180_write_word(struct i2c_client *client, u16 cmd, u16 val)
{
__be16 buf[2];
struct i2c_msg msgs[1] = {
{ .addr = client->addr, .len = sizeof(buf), .buf = (u8 *) &buf } };
int ret;
buf[0] = cpu_to_be16(cmd);
buf[1] = cpu_to_be16(val);
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret < 0) {
dev_err(&client->dev, "failed writing register 0x%04x\n", cmd);
return ret;
}
return 0;
}
static int vl6180_measure(struct vl6180_data *data, int addr)
{
struct i2c_client *client = data->client;
int tries = 20, ret;
u16 value;
mutex_lock(&data->lock);
/* Start single shot measurement */
ret = vl6180_write_byte(client,
vl6180_chan_regs_table[addr].start_reg, VL6180_STARTSTOP);
if (ret < 0)
goto fail;
while (tries--) {
ret = vl6180_read_byte(client, VL6180_INTR_STATUS);
if (ret < 0)
goto fail;
if (ret & vl6180_chan_regs_table[addr].drdy_mask)
break;
msleep(20);
}
if (tries < 0) {
ret = -EIO;
goto fail;
}
/* Read result value from appropriate registers */
ret = vl6180_chan_regs_table[addr].word ?
vl6180_read_word(client, vl6180_chan_regs_table[addr].value_reg) :
vl6180_read_byte(client, vl6180_chan_regs_table[addr].value_reg);
if (ret < 0)
goto fail;
value = ret;
/* Clear the interrupt flag after data read */
ret = vl6180_write_byte(client, VL6180_INTR_CLEAR,
VL6180_CLEAR_ERROR | VL6180_CLEAR_ALS | VL6180_CLEAR_RANGE);
if (ret < 0)
goto fail;
ret = value;
fail:
mutex_unlock(&data->lock);
return ret;
}
static const struct iio_chan_spec vl6180_channels[] = {
{
.type = IIO_LIGHT,
.address = VL6180_ALS,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_HARDWAREGAIN),
}, {
.type = IIO_DISTANCE,
.address = VL6180_RANGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
}, {
.type = IIO_PROXIMITY,
.address = VL6180_PROX,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
}
};
/*
* Available Ambient Light Sensor gain settings, 1/1000th, and
* corresponding setting for the VL6180_ALS_GAIN register
*/
static const int vl6180_als_gain_tab[8] = {
1000, 1250, 1670, 2500, 5000, 10000, 20000, 40000
};
static const u8 vl6180_als_gain_tab_bits[8] = {
VL6180_ALS_GAIN_1, VL6180_ALS_GAIN_1_25,
VL6180_ALS_GAIN_1_67, VL6180_ALS_GAIN_2_5,
VL6180_ALS_GAIN_5, VL6180_ALS_GAIN_10,
VL6180_ALS_GAIN_20, VL6180_ALS_GAIN_40
};
static int vl6180_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct vl6180_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = vl6180_measure(data, chan->address);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_INT_TIME:
*val = data->als_it_ms;
*val2 = 1000;
return IIO_VAL_FRACTIONAL;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_LIGHT:
/* one ALS count is 0.32 Lux @ gain 1, IT 100 ms */
*val = 32000; /* 0.32 * 1000 * 100 */
*val2 = data->als_gain_milli * data->als_it_ms;
return IIO_VAL_FRACTIONAL;
case IIO_DISTANCE:
*val = 0; /* sensor reports mm, scale to meter */
*val2 = 1000;
break;
default:
return -EINVAL;
}
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_HARDWAREGAIN:
*val = data->als_gain_milli;
*val2 = 1000;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
}
static IIO_CONST_ATTR(als_gain_available, "1 1.25 1.67 2.5 5 10 20 40");
static struct attribute *vl6180_attributes[] = {
&iio_const_attr_als_gain_available.dev_attr.attr,
NULL
};
static const struct attribute_group vl6180_attribute_group = {
.attrs = vl6180_attributes,
};
/* HOLD is needed before updating any config registers */
static int vl6180_hold(struct vl6180_data *data, bool hold)
{
return vl6180_write_byte(data->client, VL6180_HOLD,
hold ? VL6180_HOLD_ON : 0);
}
static int vl6180_set_als_gain(struct vl6180_data *data, int val, int val2)
{
int i, ret, gain;
if (val < 1 || val > 40)
return -EINVAL;
gain = (val * 1000000 + val2) / 1000;
if (gain < 1 || gain > 40000)
return -EINVAL;
i = find_closest(gain, vl6180_als_gain_tab,
ARRAY_SIZE(vl6180_als_gain_tab));
mutex_lock(&data->lock);
ret = vl6180_hold(data, true);
if (ret < 0)
goto fail;
ret = vl6180_write_byte(data->client, VL6180_ALS_GAIN,
vl6180_als_gain_tab_bits[i]);
if (ret >= 0)
data->als_gain_milli = vl6180_als_gain_tab[i];
fail:
vl6180_hold(data, false);
mutex_unlock(&data->lock);
return ret;
}
static int vl6180_set_it(struct vl6180_data *data, int val, int val2)
{
int ret, it_ms;
it_ms = DIV_ROUND_CLOSEST(val2, 1000); /* round to ms */
if (val != 0 || it_ms < 1 || it_ms > 512)
return -EINVAL;
mutex_lock(&data->lock);
ret = vl6180_hold(data, true);
if (ret < 0)
goto fail;
ret = vl6180_write_word(data->client, VL6180_ALS_IT, it_ms - 1);
if (ret >= 0)
data->als_it_ms = it_ms;
fail:
vl6180_hold(data, false);
mutex_unlock(&data->lock);
return ret;
}
static int vl6180_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct vl6180_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
return vl6180_set_it(data, val, val2);
case IIO_CHAN_INFO_HARDWAREGAIN:
if (chan->type != IIO_LIGHT)
return -EINVAL;
return vl6180_set_als_gain(data, val, val2);
default:
return -EINVAL;
}
}
static const struct iio_info vl6180_info = {
.read_raw = vl6180_read_raw,
.write_raw = vl6180_write_raw,
.attrs = &vl6180_attribute_group,
};
static int vl6180_init(struct vl6180_data *data)
{
struct i2c_client *client = data->client;
int ret;
ret = vl6180_read_byte(client, VL6180_MODEL_ID);
if (ret < 0)
return ret;
if (ret != VL6180_MODEL_ID_VAL) {
dev_err(&client->dev, "invalid model ID %02x\n", ret);
return -ENODEV;
}
ret = vl6180_hold(data, true);
if (ret < 0)
return ret;
ret = vl6180_read_byte(client, VL6180_OUT_OF_RESET);
if (ret < 0)
return ret;
/*
* Detect false reset condition here. This bit is always set when the
* system comes out of reset.
*/
if (ret != 0x01)
dev_info(&client->dev, "device is not fresh out of reset\n");
/* Enable ALS and Range ready interrupts */
ret = vl6180_write_byte(client, VL6180_INTR_CONFIG,
VL6180_ALS_READY | VL6180_RANGE_READY);
if (ret < 0)
return ret;
/* ALS integration time: 100ms */
data->als_it_ms = 100;
ret = vl6180_write_word(client, VL6180_ALS_IT, VL6180_ALS_IT_100);
if (ret < 0)
return ret;
/* ALS gain: 1 */
data->als_gain_milli = 1000;
ret = vl6180_write_byte(client, VL6180_ALS_GAIN, VL6180_ALS_GAIN_1);
if (ret < 0)
return ret;
ret = vl6180_write_byte(client, VL6180_OUT_OF_RESET, 0x00);
if (ret < 0)
return ret;
return vl6180_hold(data, false);
}
static int vl6180_probe(struct i2c_client *client)
{
struct vl6180_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
mutex_init(&data->lock);
indio_dev->info = &vl6180_info;
indio_dev->channels = vl6180_channels;
indio_dev->num_channels = ARRAY_SIZE(vl6180_channels);
indio_dev->name = VL6180_DRV_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = vl6180_init(data);
if (ret < 0)
return ret;
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct of_device_id vl6180_of_match[] = {
{ .compatible = "st,vl6180", },
{ },
};
MODULE_DEVICE_TABLE(of, vl6180_of_match);
static const struct i2c_device_id vl6180_id[] = {
{ "vl6180", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, vl6180_id);
static struct i2c_driver vl6180_driver = {
.driver = {
.name = VL6180_DRV_NAME,
.of_match_table = vl6180_of_match,
},
.probe = vl6180_probe,
.id_table = vl6180_id,
};
module_i2c_driver(vl6180_driver);
MODULE_AUTHOR("Peter Meerwald-Stadler <[email protected]>");
MODULE_AUTHOR("Manivannan Sadhasivam <[email protected]>");
MODULE_DESCRIPTION("STMicro VL6180 ALS, range and proximity sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/vl6180.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AL3320A - Dyna Image Ambient Light Sensor
*
* Copyright (c) 2014, Intel Corporation.
*
* IIO driver for AL3320A (7-bit I2C slave address 0x1C).
*
* TODO: interrupt support, thresholds
* When the driver will get support for interrupt handling, then interrupt
* will need to be disabled before turning sensor OFF in order to avoid
* potential races with the interrupt handling.
*/
#include <linux/bitfield.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/mod_devicetable.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define AL3320A_DRV_NAME "al3320a"
#define AL3320A_REG_CONFIG 0x00
#define AL3320A_REG_STATUS 0x01
#define AL3320A_REG_INT 0x02
#define AL3320A_REG_WAIT 0x06
#define AL3320A_REG_CONFIG_RANGE 0x07
#define AL3320A_REG_PERSIST 0x08
#define AL3320A_REG_MEAN_TIME 0x09
#define AL3320A_REG_ADUMMY 0x0A
#define AL3320A_REG_DATA_LOW 0x22
#define AL3320A_REG_LOW_THRESH_LOW 0x30
#define AL3320A_REG_LOW_THRESH_HIGH 0x31
#define AL3320A_REG_HIGH_THRESH_LOW 0x32
#define AL3320A_REG_HIGH_THRESH_HIGH 0x33
#define AL3320A_CONFIG_DISABLE 0x00
#define AL3320A_CONFIG_ENABLE 0x01
#define AL3320A_GAIN_MASK GENMASK(2, 1)
/* chip params default values */
#define AL3320A_DEFAULT_MEAN_TIME 4
#define AL3320A_DEFAULT_WAIT_TIME 0 /* no waiting */
#define AL3320A_SCALE_AVAILABLE "0.512 0.128 0.032 0.01"
enum al3320a_range {
AL3320A_RANGE_1, /* 33.28 Klx */
AL3320A_RANGE_2, /* 8.32 Klx */
AL3320A_RANGE_3, /* 2.08 Klx */
AL3320A_RANGE_4 /* 0.65 Klx */
};
static const int al3320a_scales[][2] = {
{0, 512000}, {0, 128000}, {0, 32000}, {0, 10000}
};
struct al3320a_data {
struct i2c_client *client;
};
static const struct iio_chan_spec al3320a_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
}
};
static IIO_CONST_ATTR(in_illuminance_scale_available, AL3320A_SCALE_AVAILABLE);
static struct attribute *al3320a_attributes[] = {
&iio_const_attr_in_illuminance_scale_available.dev_attr.attr,
NULL,
};
static const struct attribute_group al3320a_attribute_group = {
.attrs = al3320a_attributes,
};
static int al3320a_set_pwr(struct i2c_client *client, bool pwr)
{
u8 val = pwr ? AL3320A_CONFIG_ENABLE : AL3320A_CONFIG_DISABLE;
return i2c_smbus_write_byte_data(client, AL3320A_REG_CONFIG, val);
}
static void al3320a_set_pwr_off(void *_data)
{
struct al3320a_data *data = _data;
al3320a_set_pwr(data->client, false);
}
static int al3320a_init(struct al3320a_data *data)
{
int ret;
ret = al3320a_set_pwr(data->client, true);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client, AL3320A_REG_CONFIG_RANGE,
FIELD_PREP(AL3320A_GAIN_MASK,
AL3320A_RANGE_3));
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client, AL3320A_REG_MEAN_TIME,
AL3320A_DEFAULT_MEAN_TIME);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client, AL3320A_REG_WAIT,
AL3320A_DEFAULT_WAIT_TIME);
if (ret < 0)
return ret;
return 0;
}
static int al3320a_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct al3320a_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
/*
* ALS ADC value is stored in two adjacent registers:
* - low byte of output is stored at AL3320A_REG_DATA_LOW
* - high byte of output is stored at AL3320A_REG_DATA_LOW + 1
*/
ret = i2c_smbus_read_word_data(data->client,
AL3320A_REG_DATA_LOW);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = i2c_smbus_read_byte_data(data->client,
AL3320A_REG_CONFIG_RANGE);
if (ret < 0)
return ret;
ret = FIELD_GET(AL3320A_GAIN_MASK, ret);
*val = al3320a_scales[ret][0];
*val2 = al3320a_scales[ret][1];
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
}
static int al3320a_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct al3320a_data *data = iio_priv(indio_dev);
int i;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
for (i = 0; i < ARRAY_SIZE(al3320a_scales); i++) {
if (val != al3320a_scales[i][0] ||
val2 != al3320a_scales[i][1])
continue;
return i2c_smbus_write_byte_data(data->client,
AL3320A_REG_CONFIG_RANGE,
FIELD_PREP(AL3320A_GAIN_MASK, i));
}
break;
}
return -EINVAL;
}
static const struct iio_info al3320a_info = {
.read_raw = al3320a_read_raw,
.write_raw = al3320a_write_raw,
.attrs = &al3320a_attribute_group,
};
static int al3320a_probe(struct i2c_client *client)
{
struct al3320a_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
indio_dev->info = &al3320a_info;
indio_dev->name = AL3320A_DRV_NAME;
indio_dev->channels = al3320a_channels;
indio_dev->num_channels = ARRAY_SIZE(al3320a_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = al3320a_init(data);
if (ret < 0) {
dev_err(&client->dev, "al3320a chip init failed\n");
return ret;
}
ret = devm_add_action_or_reset(&client->dev,
al3320a_set_pwr_off,
data);
if (ret < 0)
return ret;
return devm_iio_device_register(&client->dev, indio_dev);
}
static int al3320a_suspend(struct device *dev)
{
return al3320a_set_pwr(to_i2c_client(dev), false);
}
static int al3320a_resume(struct device *dev)
{
return al3320a_set_pwr(to_i2c_client(dev), true);
}
static DEFINE_SIMPLE_DEV_PM_OPS(al3320a_pm_ops, al3320a_suspend,
al3320a_resume);
static const struct i2c_device_id al3320a_id[] = {
{"al3320a", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, al3320a_id);
static const struct of_device_id al3320a_of_match[] = {
{ .compatible = "dynaimage,al3320a", },
{},
};
MODULE_DEVICE_TABLE(of, al3320a_of_match);
static const struct acpi_device_id al3320a_acpi_match[] = {
{"CALS0001"},
{ },
};
MODULE_DEVICE_TABLE(acpi, al3320a_acpi_match);
static struct i2c_driver al3320a_driver = {
.driver = {
.name = AL3320A_DRV_NAME,
.of_match_table = al3320a_of_match,
.pm = pm_sleep_ptr(&al3320a_pm_ops),
.acpi_match_table = al3320a_acpi_match,
},
.probe = al3320a_probe,
.id_table = al3320a_id,
};
module_i2c_driver(al3320a_driver);
MODULE_AUTHOR("Daniel Baluta <[email protected]>");
MODULE_DESCRIPTION("AL3320A Ambient Light Sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/al3320a.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
* Author: Jacek Anaszewski <[email protected]>
*
* IIO features supported by the driver:
*
* Read-only raw channels:
* - illuminance_clear [lux]
* - illuminance_ir
* - proximity
*
* Triggered buffer:
* - illuminance_clear
* - illuminance_ir
* - proximity
*
* Events:
* - illuminance_clear (rising and falling)
* - proximity (rising and falling)
* - both falling and rising thresholds for the proximity events
* must be set to the values greater than 0.
*
* The driver supports triggered buffers for all the three
* channels as well as high and low threshold events for the
* illuminance_clear and proxmimity channels. Triggers
* can be enabled simultaneously with both illuminance_clear
* events. Proximity events cannot be enabled simultaneously
* with any triggers or illuminance events. Enabling/disabling
* one of the proximity events automatically enables/disables
* the other one.
*/
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irq_work.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <asm/unaligned.h>
#include <linux/iio/buffer.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#define GP2A_I2C_NAME "gp2ap020a00f"
/* Registers */
#define GP2AP020A00F_OP_REG 0x00 /* Basic operations */
#define GP2AP020A00F_ALS_REG 0x01 /* ALS related settings */
#define GP2AP020A00F_PS_REG 0x02 /* PS related settings */
#define GP2AP020A00F_LED_REG 0x03 /* LED reg */
#define GP2AP020A00F_TL_L_REG 0x04 /* ALS: Threshold low LSB */
#define GP2AP020A00F_TL_H_REG 0x05 /* ALS: Threshold low MSB */
#define GP2AP020A00F_TH_L_REG 0x06 /* ALS: Threshold high LSB */
#define GP2AP020A00F_TH_H_REG 0x07 /* ALS: Threshold high MSB */
#define GP2AP020A00F_PL_L_REG 0x08 /* PS: Threshold low LSB */
#define GP2AP020A00F_PL_H_REG 0x09 /* PS: Threshold low MSB */
#define GP2AP020A00F_PH_L_REG 0x0a /* PS: Threshold high LSB */
#define GP2AP020A00F_PH_H_REG 0x0b /* PS: Threshold high MSB */
#define GP2AP020A00F_D0_L_REG 0x0c /* ALS result: Clear/Illuminance LSB */
#define GP2AP020A00F_D0_H_REG 0x0d /* ALS result: Clear/Illuminance MSB */
#define GP2AP020A00F_D1_L_REG 0x0e /* ALS result: IR LSB */
#define GP2AP020A00F_D1_H_REG 0x0f /* ALS result: IR LSB */
#define GP2AP020A00F_D2_L_REG 0x10 /* PS result LSB */
#define GP2AP020A00F_D2_H_REG 0x11 /* PS result MSB */
#define GP2AP020A00F_NUM_REGS 0x12 /* Number of registers */
/* OP_REG bits */
#define GP2AP020A00F_OP3_MASK 0x80 /* Software shutdown */
#define GP2AP020A00F_OP3_SHUTDOWN 0x00
#define GP2AP020A00F_OP3_OPERATION 0x80
#define GP2AP020A00F_OP2_MASK 0x40 /* Auto shutdown/Continuous mode */
#define GP2AP020A00F_OP2_AUTO_SHUTDOWN 0x00
#define GP2AP020A00F_OP2_CONT_OPERATION 0x40
#define GP2AP020A00F_OP_MASK 0x30 /* Operating mode selection */
#define GP2AP020A00F_OP_ALS_AND_PS 0x00
#define GP2AP020A00F_OP_ALS 0x10
#define GP2AP020A00F_OP_PS 0x20
#define GP2AP020A00F_OP_DEBUG 0x30
#define GP2AP020A00F_PROX_MASK 0x08 /* PS: detection/non-detection */
#define GP2AP020A00F_PROX_NON_DETECT 0x00
#define GP2AP020A00F_PROX_DETECT 0x08
#define GP2AP020A00F_FLAG_P 0x04 /* PS: interrupt result */
#define GP2AP020A00F_FLAG_A 0x02 /* ALS: interrupt result */
#define GP2AP020A00F_TYPE_MASK 0x01 /* Output data type selection */
#define GP2AP020A00F_TYPE_MANUAL_CALC 0x00
#define GP2AP020A00F_TYPE_AUTO_CALC 0x01
/* ALS_REG bits */
#define GP2AP020A00F_PRST_MASK 0xc0 /* Number of measurement cycles */
#define GP2AP020A00F_PRST_ONCE 0x00
#define GP2AP020A00F_PRST_4_CYCLES 0x40
#define GP2AP020A00F_PRST_8_CYCLES 0x80
#define GP2AP020A00F_PRST_16_CYCLES 0xc0
#define GP2AP020A00F_RES_A_MASK 0x38 /* ALS: Resolution */
#define GP2AP020A00F_RES_A_800ms 0x00
#define GP2AP020A00F_RES_A_400ms 0x08
#define GP2AP020A00F_RES_A_200ms 0x10
#define GP2AP020A00F_RES_A_100ms 0x18
#define GP2AP020A00F_RES_A_25ms 0x20
#define GP2AP020A00F_RES_A_6_25ms 0x28
#define GP2AP020A00F_RES_A_1_56ms 0x30
#define GP2AP020A00F_RES_A_0_39ms 0x38
#define GP2AP020A00F_RANGE_A_MASK 0x07 /* ALS: Max measurable range */
#define GP2AP020A00F_RANGE_A_x1 0x00
#define GP2AP020A00F_RANGE_A_x2 0x01
#define GP2AP020A00F_RANGE_A_x4 0x02
#define GP2AP020A00F_RANGE_A_x8 0x03
#define GP2AP020A00F_RANGE_A_x16 0x04
#define GP2AP020A00F_RANGE_A_x32 0x05
#define GP2AP020A00F_RANGE_A_x64 0x06
#define GP2AP020A00F_RANGE_A_x128 0x07
/* PS_REG bits */
#define GP2AP020A00F_ALC_MASK 0x80 /* Auto light cancel */
#define GP2AP020A00F_ALC_ON 0x80
#define GP2AP020A00F_ALC_OFF 0x00
#define GP2AP020A00F_INTTYPE_MASK 0x40 /* Interrupt type setting */
#define GP2AP020A00F_INTTYPE_LEVEL 0x00
#define GP2AP020A00F_INTTYPE_PULSE 0x40
#define GP2AP020A00F_RES_P_MASK 0x38 /* PS: Resolution */
#define GP2AP020A00F_RES_P_800ms_x2 0x00
#define GP2AP020A00F_RES_P_400ms_x2 0x08
#define GP2AP020A00F_RES_P_200ms_x2 0x10
#define GP2AP020A00F_RES_P_100ms_x2 0x18
#define GP2AP020A00F_RES_P_25ms_x2 0x20
#define GP2AP020A00F_RES_P_6_25ms_x2 0x28
#define GP2AP020A00F_RES_P_1_56ms_x2 0x30
#define GP2AP020A00F_RES_P_0_39ms_x2 0x38
#define GP2AP020A00F_RANGE_P_MASK 0x07 /* PS: Max measurable range */
#define GP2AP020A00F_RANGE_P_x1 0x00
#define GP2AP020A00F_RANGE_P_x2 0x01
#define GP2AP020A00F_RANGE_P_x4 0x02
#define GP2AP020A00F_RANGE_P_x8 0x03
#define GP2AP020A00F_RANGE_P_x16 0x04
#define GP2AP020A00F_RANGE_P_x32 0x05
#define GP2AP020A00F_RANGE_P_x64 0x06
#define GP2AP020A00F_RANGE_P_x128 0x07
/* LED reg bits */
#define GP2AP020A00F_INTVAL_MASK 0xc0 /* Intermittent operating */
#define GP2AP020A00F_INTVAL_0 0x00
#define GP2AP020A00F_INTVAL_4 0x40
#define GP2AP020A00F_INTVAL_8 0x80
#define GP2AP020A00F_INTVAL_16 0xc0
#define GP2AP020A00F_IS_MASK 0x30 /* ILED drive peak current */
#define GP2AP020A00F_IS_13_8mA 0x00
#define GP2AP020A00F_IS_27_5mA 0x10
#define GP2AP020A00F_IS_55mA 0x20
#define GP2AP020A00F_IS_110mA 0x30
#define GP2AP020A00F_PIN_MASK 0x0c /* INT terminal setting */
#define GP2AP020A00F_PIN_ALS_OR_PS 0x00
#define GP2AP020A00F_PIN_ALS 0x04
#define GP2AP020A00F_PIN_PS 0x08
#define GP2AP020A00F_PIN_PS_DETECT 0x0c
#define GP2AP020A00F_FREQ_MASK 0x02 /* LED modulation frequency */
#define GP2AP020A00F_FREQ_327_5kHz 0x00
#define GP2AP020A00F_FREQ_81_8kHz 0x02
#define GP2AP020A00F_RST 0x01 /* Software reset */
#define GP2AP020A00F_SCAN_MODE_LIGHT_CLEAR 0
#define GP2AP020A00F_SCAN_MODE_LIGHT_IR 1
#define GP2AP020A00F_SCAN_MODE_PROXIMITY 2
#define GP2AP020A00F_CHAN_TIMESTAMP 3
#define GP2AP020A00F_DATA_READY_TIMEOUT msecs_to_jiffies(1000)
#define GP2AP020A00F_DATA_REG(chan) (GP2AP020A00F_D0_L_REG + \
(chan) * 2)
#define GP2AP020A00F_THRESH_REG(th_val_id) (GP2AP020A00F_TL_L_REG + \
(th_val_id) * 2)
#define GP2AP020A00F_THRESH_VAL_ID(reg_addr) ((reg_addr - 4) / 2)
#define GP2AP020A00F_SUBTRACT_MODE 0
#define GP2AP020A00F_ADD_MODE 1
#define GP2AP020A00F_MAX_CHANNELS 3
enum gp2ap020a00f_opmode {
GP2AP020A00F_OPMODE_READ_RAW_CLEAR,
GP2AP020A00F_OPMODE_READ_RAW_IR,
GP2AP020A00F_OPMODE_READ_RAW_PROXIMITY,
GP2AP020A00F_OPMODE_ALS,
GP2AP020A00F_OPMODE_PS,
GP2AP020A00F_OPMODE_ALS_AND_PS,
GP2AP020A00F_OPMODE_PROX_DETECT,
GP2AP020A00F_OPMODE_SHUTDOWN,
GP2AP020A00F_NUM_OPMODES,
};
enum gp2ap020a00f_cmd {
GP2AP020A00F_CMD_READ_RAW_CLEAR,
GP2AP020A00F_CMD_READ_RAW_IR,
GP2AP020A00F_CMD_READ_RAW_PROXIMITY,
GP2AP020A00F_CMD_TRIGGER_CLEAR_EN,
GP2AP020A00F_CMD_TRIGGER_CLEAR_DIS,
GP2AP020A00F_CMD_TRIGGER_IR_EN,
GP2AP020A00F_CMD_TRIGGER_IR_DIS,
GP2AP020A00F_CMD_TRIGGER_PROX_EN,
GP2AP020A00F_CMD_TRIGGER_PROX_DIS,
GP2AP020A00F_CMD_ALS_HIGH_EV_EN,
GP2AP020A00F_CMD_ALS_HIGH_EV_DIS,
GP2AP020A00F_CMD_ALS_LOW_EV_EN,
GP2AP020A00F_CMD_ALS_LOW_EV_DIS,
GP2AP020A00F_CMD_PROX_HIGH_EV_EN,
GP2AP020A00F_CMD_PROX_HIGH_EV_DIS,
GP2AP020A00F_CMD_PROX_LOW_EV_EN,
GP2AP020A00F_CMD_PROX_LOW_EV_DIS,
};
enum gp2ap020a00f_flags {
GP2AP020A00F_FLAG_ALS_CLEAR_TRIGGER,
GP2AP020A00F_FLAG_ALS_IR_TRIGGER,
GP2AP020A00F_FLAG_PROX_TRIGGER,
GP2AP020A00F_FLAG_PROX_RISING_EV,
GP2AP020A00F_FLAG_PROX_FALLING_EV,
GP2AP020A00F_FLAG_ALS_RISING_EV,
GP2AP020A00F_FLAG_ALS_FALLING_EV,
GP2AP020A00F_FLAG_LUX_MODE_HI,
GP2AP020A00F_FLAG_DATA_READY,
};
enum gp2ap020a00f_thresh_val_id {
GP2AP020A00F_THRESH_TL,
GP2AP020A00F_THRESH_TH,
GP2AP020A00F_THRESH_PL,
GP2AP020A00F_THRESH_PH,
};
struct gp2ap020a00f_data {
const struct gp2ap020a00f_platform_data *pdata;
struct i2c_client *client;
struct mutex lock;
char *buffer;
struct regulator *vled_reg;
unsigned long flags;
enum gp2ap020a00f_opmode cur_opmode;
struct iio_trigger *trig;
struct regmap *regmap;
unsigned int thresh_val[4];
u8 debug_reg_addr;
struct irq_work work;
wait_queue_head_t data_ready_queue;
};
static const u8 gp2ap020a00f_reg_init_tab[] = {
[GP2AP020A00F_OP_REG] = GP2AP020A00F_OP3_SHUTDOWN,
[GP2AP020A00F_ALS_REG] = GP2AP020A00F_RES_A_25ms |
GP2AP020A00F_RANGE_A_x8,
[GP2AP020A00F_PS_REG] = GP2AP020A00F_ALC_ON |
GP2AP020A00F_RES_P_1_56ms_x2 |
GP2AP020A00F_RANGE_P_x4,
[GP2AP020A00F_LED_REG] = GP2AP020A00F_INTVAL_0 |
GP2AP020A00F_IS_110mA |
GP2AP020A00F_FREQ_327_5kHz,
[GP2AP020A00F_TL_L_REG] = 0,
[GP2AP020A00F_TL_H_REG] = 0,
[GP2AP020A00F_TH_L_REG] = 0,
[GP2AP020A00F_TH_H_REG] = 0,
[GP2AP020A00F_PL_L_REG] = 0,
[GP2AP020A00F_PL_H_REG] = 0,
[GP2AP020A00F_PH_L_REG] = 0,
[GP2AP020A00F_PH_H_REG] = 0,
};
static bool gp2ap020a00f_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case GP2AP020A00F_OP_REG:
case GP2AP020A00F_D0_L_REG:
case GP2AP020A00F_D0_H_REG:
case GP2AP020A00F_D1_L_REG:
case GP2AP020A00F_D1_H_REG:
case GP2AP020A00F_D2_L_REG:
case GP2AP020A00F_D2_H_REG:
return true;
default:
return false;
}
}
static const struct regmap_config gp2ap020a00f_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = GP2AP020A00F_D2_H_REG,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = gp2ap020a00f_is_volatile_reg,
};
static const struct gp2ap020a00f_mutable_config_regs {
u8 op_reg;
u8 als_reg;
u8 ps_reg;
u8 led_reg;
} opmode_regs_settings[GP2AP020A00F_NUM_OPMODES] = {
[GP2AP020A00F_OPMODE_READ_RAW_CLEAR] = {
GP2AP020A00F_OP_ALS | GP2AP020A00F_OP2_CONT_OPERATION
| GP2AP020A00F_OP3_OPERATION
| GP2AP020A00F_TYPE_AUTO_CALC,
GP2AP020A00F_PRST_ONCE,
GP2AP020A00F_INTTYPE_LEVEL,
GP2AP020A00F_PIN_ALS
},
[GP2AP020A00F_OPMODE_READ_RAW_IR] = {
GP2AP020A00F_OP_ALS | GP2AP020A00F_OP2_CONT_OPERATION
| GP2AP020A00F_OP3_OPERATION
| GP2AP020A00F_TYPE_MANUAL_CALC,
GP2AP020A00F_PRST_ONCE,
GP2AP020A00F_INTTYPE_LEVEL,
GP2AP020A00F_PIN_ALS
},
[GP2AP020A00F_OPMODE_READ_RAW_PROXIMITY] = {
GP2AP020A00F_OP_PS | GP2AP020A00F_OP2_CONT_OPERATION
| GP2AP020A00F_OP3_OPERATION
| GP2AP020A00F_TYPE_MANUAL_CALC,
GP2AP020A00F_PRST_ONCE,
GP2AP020A00F_INTTYPE_LEVEL,
GP2AP020A00F_PIN_PS
},
[GP2AP020A00F_OPMODE_PROX_DETECT] = {
GP2AP020A00F_OP_PS | GP2AP020A00F_OP2_CONT_OPERATION
| GP2AP020A00F_OP3_OPERATION
| GP2AP020A00F_TYPE_MANUAL_CALC,
GP2AP020A00F_PRST_4_CYCLES,
GP2AP020A00F_INTTYPE_PULSE,
GP2AP020A00F_PIN_PS_DETECT
},
[GP2AP020A00F_OPMODE_ALS] = {
GP2AP020A00F_OP_ALS | GP2AP020A00F_OP2_CONT_OPERATION
| GP2AP020A00F_OP3_OPERATION
| GP2AP020A00F_TYPE_AUTO_CALC,
GP2AP020A00F_PRST_ONCE,
GP2AP020A00F_INTTYPE_LEVEL,
GP2AP020A00F_PIN_ALS
},
[GP2AP020A00F_OPMODE_PS] = {
GP2AP020A00F_OP_PS | GP2AP020A00F_OP2_CONT_OPERATION
| GP2AP020A00F_OP3_OPERATION
| GP2AP020A00F_TYPE_MANUAL_CALC,
GP2AP020A00F_PRST_4_CYCLES,
GP2AP020A00F_INTTYPE_LEVEL,
GP2AP020A00F_PIN_PS
},
[GP2AP020A00F_OPMODE_ALS_AND_PS] = {
GP2AP020A00F_OP_ALS_AND_PS
| GP2AP020A00F_OP2_CONT_OPERATION
| GP2AP020A00F_OP3_OPERATION
| GP2AP020A00F_TYPE_AUTO_CALC,
GP2AP020A00F_PRST_4_CYCLES,
GP2AP020A00F_INTTYPE_LEVEL,
GP2AP020A00F_PIN_ALS_OR_PS
},
[GP2AP020A00F_OPMODE_SHUTDOWN] = { GP2AP020A00F_OP3_SHUTDOWN, },
};
static int gp2ap020a00f_set_operation_mode(struct gp2ap020a00f_data *data,
enum gp2ap020a00f_opmode op)
{
unsigned int op_reg_val;
int err;
if (op != GP2AP020A00F_OPMODE_SHUTDOWN) {
err = regmap_read(data->regmap, GP2AP020A00F_OP_REG,
&op_reg_val);
if (err < 0)
return err;
/*
* Shutdown the device if the operation being executed entails
* mode transition.
*/
if ((opmode_regs_settings[op].op_reg & GP2AP020A00F_OP_MASK) !=
(op_reg_val & GP2AP020A00F_OP_MASK)) {
/* set shutdown mode */
err = regmap_update_bits(data->regmap,
GP2AP020A00F_OP_REG, GP2AP020A00F_OP3_MASK,
GP2AP020A00F_OP3_SHUTDOWN);
if (err < 0)
return err;
}
err = regmap_update_bits(data->regmap, GP2AP020A00F_ALS_REG,
GP2AP020A00F_PRST_MASK, opmode_regs_settings[op]
.als_reg);
if (err < 0)
return err;
err = regmap_update_bits(data->regmap, GP2AP020A00F_PS_REG,
GP2AP020A00F_INTTYPE_MASK, opmode_regs_settings[op]
.ps_reg);
if (err < 0)
return err;
err = regmap_update_bits(data->regmap, GP2AP020A00F_LED_REG,
GP2AP020A00F_PIN_MASK, opmode_regs_settings[op]
.led_reg);
if (err < 0)
return err;
}
/* Set OP_REG and apply operation mode (power on / off) */
err = regmap_update_bits(data->regmap,
GP2AP020A00F_OP_REG,
GP2AP020A00F_OP_MASK | GP2AP020A00F_OP2_MASK |
GP2AP020A00F_OP3_MASK | GP2AP020A00F_TYPE_MASK,
opmode_regs_settings[op].op_reg);
if (err < 0)
return err;
data->cur_opmode = op;
return 0;
}
static bool gp2ap020a00f_als_enabled(struct gp2ap020a00f_data *data)
{
return test_bit(GP2AP020A00F_FLAG_ALS_CLEAR_TRIGGER, &data->flags) ||
test_bit(GP2AP020A00F_FLAG_ALS_IR_TRIGGER, &data->flags) ||
test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &data->flags) ||
test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &data->flags);
}
static bool gp2ap020a00f_prox_detect_enabled(struct gp2ap020a00f_data *data)
{
return test_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, &data->flags) ||
test_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, &data->flags);
}
static int gp2ap020a00f_write_event_threshold(struct gp2ap020a00f_data *data,
enum gp2ap020a00f_thresh_val_id th_val_id,
bool enable)
{
__le16 thresh_buf = 0;
unsigned int thresh_reg_val;
if (!enable)
thresh_reg_val = 0;
else if (test_bit(GP2AP020A00F_FLAG_LUX_MODE_HI, &data->flags) &&
th_val_id != GP2AP020A00F_THRESH_PL &&
th_val_id != GP2AP020A00F_THRESH_PH)
/*
* For the high lux mode ALS threshold has to be scaled down
* to allow for proper comparison with the output value.
*/
thresh_reg_val = data->thresh_val[th_val_id] / 16;
else
thresh_reg_val = data->thresh_val[th_val_id] > 16000 ?
16000 :
data->thresh_val[th_val_id];
thresh_buf = cpu_to_le16(thresh_reg_val);
return regmap_bulk_write(data->regmap,
GP2AP020A00F_THRESH_REG(th_val_id),
(u8 *)&thresh_buf, 2);
}
static int gp2ap020a00f_alter_opmode(struct gp2ap020a00f_data *data,
enum gp2ap020a00f_opmode diff_mode, int add_sub)
{
enum gp2ap020a00f_opmode new_mode;
if (diff_mode != GP2AP020A00F_OPMODE_ALS &&
diff_mode != GP2AP020A00F_OPMODE_PS)
return -EINVAL;
if (add_sub == GP2AP020A00F_ADD_MODE) {
if (data->cur_opmode == GP2AP020A00F_OPMODE_SHUTDOWN)
new_mode = diff_mode;
else
new_mode = GP2AP020A00F_OPMODE_ALS_AND_PS;
} else {
if (data->cur_opmode == GP2AP020A00F_OPMODE_ALS_AND_PS)
new_mode = (diff_mode == GP2AP020A00F_OPMODE_ALS) ?
GP2AP020A00F_OPMODE_PS :
GP2AP020A00F_OPMODE_ALS;
else
new_mode = GP2AP020A00F_OPMODE_SHUTDOWN;
}
return gp2ap020a00f_set_operation_mode(data, new_mode);
}
static int gp2ap020a00f_exec_cmd(struct gp2ap020a00f_data *data,
enum gp2ap020a00f_cmd cmd)
{
int err = 0;
switch (cmd) {
case GP2AP020A00F_CMD_READ_RAW_CLEAR:
if (data->cur_opmode != GP2AP020A00F_OPMODE_SHUTDOWN)
return -EBUSY;
err = gp2ap020a00f_set_operation_mode(data,
GP2AP020A00F_OPMODE_READ_RAW_CLEAR);
break;
case GP2AP020A00F_CMD_READ_RAW_IR:
if (data->cur_opmode != GP2AP020A00F_OPMODE_SHUTDOWN)
return -EBUSY;
err = gp2ap020a00f_set_operation_mode(data,
GP2AP020A00F_OPMODE_READ_RAW_IR);
break;
case GP2AP020A00F_CMD_READ_RAW_PROXIMITY:
if (data->cur_opmode != GP2AP020A00F_OPMODE_SHUTDOWN)
return -EBUSY;
err = gp2ap020a00f_set_operation_mode(data,
GP2AP020A00F_OPMODE_READ_RAW_PROXIMITY);
break;
case GP2AP020A00F_CMD_TRIGGER_CLEAR_EN:
if (data->cur_opmode == GP2AP020A00F_OPMODE_PROX_DETECT)
return -EBUSY;
if (!gp2ap020a00f_als_enabled(data))
err = gp2ap020a00f_alter_opmode(data,
GP2AP020A00F_OPMODE_ALS,
GP2AP020A00F_ADD_MODE);
set_bit(GP2AP020A00F_FLAG_ALS_CLEAR_TRIGGER, &data->flags);
break;
case GP2AP020A00F_CMD_TRIGGER_CLEAR_DIS:
clear_bit(GP2AP020A00F_FLAG_ALS_CLEAR_TRIGGER, &data->flags);
if (gp2ap020a00f_als_enabled(data))
break;
err = gp2ap020a00f_alter_opmode(data,
GP2AP020A00F_OPMODE_ALS,
GP2AP020A00F_SUBTRACT_MODE);
break;
case GP2AP020A00F_CMD_TRIGGER_IR_EN:
if (data->cur_opmode == GP2AP020A00F_OPMODE_PROX_DETECT)
return -EBUSY;
if (!gp2ap020a00f_als_enabled(data))
err = gp2ap020a00f_alter_opmode(data,
GP2AP020A00F_OPMODE_ALS,
GP2AP020A00F_ADD_MODE);
set_bit(GP2AP020A00F_FLAG_ALS_IR_TRIGGER, &data->flags);
break;
case GP2AP020A00F_CMD_TRIGGER_IR_DIS:
clear_bit(GP2AP020A00F_FLAG_ALS_IR_TRIGGER, &data->flags);
if (gp2ap020a00f_als_enabled(data))
break;
err = gp2ap020a00f_alter_opmode(data,
GP2AP020A00F_OPMODE_ALS,
GP2AP020A00F_SUBTRACT_MODE);
break;
case GP2AP020A00F_CMD_TRIGGER_PROX_EN:
if (data->cur_opmode == GP2AP020A00F_OPMODE_PROX_DETECT)
return -EBUSY;
err = gp2ap020a00f_alter_opmode(data,
GP2AP020A00F_OPMODE_PS,
GP2AP020A00F_ADD_MODE);
set_bit(GP2AP020A00F_FLAG_PROX_TRIGGER, &data->flags);
break;
case GP2AP020A00F_CMD_TRIGGER_PROX_DIS:
clear_bit(GP2AP020A00F_FLAG_PROX_TRIGGER, &data->flags);
err = gp2ap020a00f_alter_opmode(data,
GP2AP020A00F_OPMODE_PS,
GP2AP020A00F_SUBTRACT_MODE);
break;
case GP2AP020A00F_CMD_ALS_HIGH_EV_EN:
if (test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &data->flags))
return 0;
if (data->cur_opmode == GP2AP020A00F_OPMODE_PROX_DETECT)
return -EBUSY;
if (!gp2ap020a00f_als_enabled(data)) {
err = gp2ap020a00f_alter_opmode(data,
GP2AP020A00F_OPMODE_ALS,
GP2AP020A00F_ADD_MODE);
if (err < 0)
return err;
}
set_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &data->flags);
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_TH, true);
break;
case GP2AP020A00F_CMD_ALS_HIGH_EV_DIS:
if (!test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &data->flags))
return 0;
clear_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &data->flags);
if (!gp2ap020a00f_als_enabled(data)) {
err = gp2ap020a00f_alter_opmode(data,
GP2AP020A00F_OPMODE_ALS,
GP2AP020A00F_SUBTRACT_MODE);
if (err < 0)
return err;
}
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_TH, false);
break;
case GP2AP020A00F_CMD_ALS_LOW_EV_EN:
if (test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &data->flags))
return 0;
if (data->cur_opmode == GP2AP020A00F_OPMODE_PROX_DETECT)
return -EBUSY;
if (!gp2ap020a00f_als_enabled(data)) {
err = gp2ap020a00f_alter_opmode(data,
GP2AP020A00F_OPMODE_ALS,
GP2AP020A00F_ADD_MODE);
if (err < 0)
return err;
}
set_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &data->flags);
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_TL, true);
break;
case GP2AP020A00F_CMD_ALS_LOW_EV_DIS:
if (!test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &data->flags))
return 0;
clear_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &data->flags);
if (!gp2ap020a00f_als_enabled(data)) {
err = gp2ap020a00f_alter_opmode(data,
GP2AP020A00F_OPMODE_ALS,
GP2AP020A00F_SUBTRACT_MODE);
if (err < 0)
return err;
}
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_TL, false);
break;
case GP2AP020A00F_CMD_PROX_HIGH_EV_EN:
if (test_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, &data->flags))
return 0;
if (gp2ap020a00f_als_enabled(data) ||
data->cur_opmode == GP2AP020A00F_OPMODE_PS)
return -EBUSY;
if (!gp2ap020a00f_prox_detect_enabled(data)) {
err = gp2ap020a00f_set_operation_mode(data,
GP2AP020A00F_OPMODE_PROX_DETECT);
if (err < 0)
return err;
}
set_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, &data->flags);
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_PH, true);
break;
case GP2AP020A00F_CMD_PROX_HIGH_EV_DIS:
if (!test_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, &data->flags))
return 0;
clear_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, &data->flags);
err = gp2ap020a00f_set_operation_mode(data,
GP2AP020A00F_OPMODE_SHUTDOWN);
if (err < 0)
return err;
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_PH, false);
break;
case GP2AP020A00F_CMD_PROX_LOW_EV_EN:
if (test_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, &data->flags))
return 0;
if (gp2ap020a00f_als_enabled(data) ||
data->cur_opmode == GP2AP020A00F_OPMODE_PS)
return -EBUSY;
if (!gp2ap020a00f_prox_detect_enabled(data)) {
err = gp2ap020a00f_set_operation_mode(data,
GP2AP020A00F_OPMODE_PROX_DETECT);
if (err < 0)
return err;
}
set_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, &data->flags);
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_PL, true);
break;
case GP2AP020A00F_CMD_PROX_LOW_EV_DIS:
if (!test_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, &data->flags))
return 0;
clear_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, &data->flags);
err = gp2ap020a00f_set_operation_mode(data,
GP2AP020A00F_OPMODE_SHUTDOWN);
if (err < 0)
return err;
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_PL, false);
break;
}
return err;
}
static int wait_conversion_complete_irq(struct gp2ap020a00f_data *data)
{
int ret;
ret = wait_event_timeout(data->data_ready_queue,
test_bit(GP2AP020A00F_FLAG_DATA_READY,
&data->flags),
GP2AP020A00F_DATA_READY_TIMEOUT);
clear_bit(GP2AP020A00F_FLAG_DATA_READY, &data->flags);
return ret > 0 ? 0 : -ETIME;
}
static int gp2ap020a00f_read_output(struct gp2ap020a00f_data *data,
unsigned int output_reg, int *val)
{
u8 reg_buf[2];
int err;
err = wait_conversion_complete_irq(data);
if (err < 0)
dev_dbg(&data->client->dev, "data ready timeout\n");
err = regmap_bulk_read(data->regmap, output_reg, reg_buf, 2);
if (err < 0)
return err;
*val = le16_to_cpup((__le16 *)reg_buf);
return err;
}
static bool gp2ap020a00f_adjust_lux_mode(struct gp2ap020a00f_data *data,
int output_val)
{
u8 new_range = 0xff;
int err;
if (!test_bit(GP2AP020A00F_FLAG_LUX_MODE_HI, &data->flags)) {
if (output_val > 16000) {
set_bit(GP2AP020A00F_FLAG_LUX_MODE_HI, &data->flags);
new_range = GP2AP020A00F_RANGE_A_x128;
}
} else {
if (output_val < 1000) {
clear_bit(GP2AP020A00F_FLAG_LUX_MODE_HI, &data->flags);
new_range = GP2AP020A00F_RANGE_A_x8;
}
}
if (new_range != 0xff) {
/* Clear als threshold registers to avoid spurious
* events caused by lux mode transition.
*/
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_TH, false);
if (err < 0) {
dev_err(&data->client->dev,
"Clearing als threshold register failed.\n");
return false;
}
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_TL, false);
if (err < 0) {
dev_err(&data->client->dev,
"Clearing als threshold register failed.\n");
return false;
}
/* Change lux mode */
err = regmap_update_bits(data->regmap,
GP2AP020A00F_OP_REG,
GP2AP020A00F_OP3_MASK,
GP2AP020A00F_OP3_SHUTDOWN);
if (err < 0) {
dev_err(&data->client->dev,
"Shutting down the device failed.\n");
return false;
}
err = regmap_update_bits(data->regmap,
GP2AP020A00F_ALS_REG,
GP2AP020A00F_RANGE_A_MASK,
new_range);
if (err < 0) {
dev_err(&data->client->dev,
"Adjusting device lux mode failed.\n");
return false;
}
err = regmap_update_bits(data->regmap,
GP2AP020A00F_OP_REG,
GP2AP020A00F_OP3_MASK,
GP2AP020A00F_OP3_OPERATION);
if (err < 0) {
dev_err(&data->client->dev,
"Powering up the device failed.\n");
return false;
}
/* Adjust als threshold register values to the new lux mode */
if (test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &data->flags)) {
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_TH, true);
if (err < 0) {
dev_err(&data->client->dev,
"Adjusting als threshold value failed.\n");
return false;
}
}
if (test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &data->flags)) {
err = gp2ap020a00f_write_event_threshold(data,
GP2AP020A00F_THRESH_TL, true);
if (err < 0) {
dev_err(&data->client->dev,
"Adjusting als threshold value failed.\n");
return false;
}
}
return true;
}
return false;
}
static void gp2ap020a00f_output_to_lux(struct gp2ap020a00f_data *data,
int *output_val)
{
if (test_bit(GP2AP020A00F_FLAG_LUX_MODE_HI, &data->flags))
*output_val *= 16;
}
static void gp2ap020a00f_iio_trigger_work(struct irq_work *work)
{
struct gp2ap020a00f_data *data =
container_of(work, struct gp2ap020a00f_data, work);
iio_trigger_poll(data->trig);
}
static irqreturn_t gp2ap020a00f_prox_sensing_handler(int irq, void *data)
{
struct iio_dev *indio_dev = data;
struct gp2ap020a00f_data *priv = iio_priv(indio_dev);
unsigned int op_reg_val;
int ret;
/* Read interrupt flags */
ret = regmap_read(priv->regmap, GP2AP020A00F_OP_REG, &op_reg_val);
if (ret < 0)
return IRQ_HANDLED;
if (gp2ap020a00f_prox_detect_enabled(priv)) {
if (op_reg_val & GP2AP020A00F_PROX_DETECT) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(
IIO_PROXIMITY,
GP2AP020A00F_SCAN_MODE_PROXIMITY,
IIO_EV_TYPE_ROC,
IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
} else {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(
IIO_PROXIMITY,
GP2AP020A00F_SCAN_MODE_PROXIMITY,
IIO_EV_TYPE_ROC,
IIO_EV_DIR_FALLING),
iio_get_time_ns(indio_dev));
}
}
return IRQ_HANDLED;
}
static irqreturn_t gp2ap020a00f_thresh_event_handler(int irq, void *data)
{
struct iio_dev *indio_dev = data;
struct gp2ap020a00f_data *priv = iio_priv(indio_dev);
u8 op_reg_flags, d0_reg_buf[2];
unsigned int output_val, op_reg_val;
int thresh_val_id, ret;
/* Read interrupt flags */
ret = regmap_read(priv->regmap, GP2AP020A00F_OP_REG,
&op_reg_val);
if (ret < 0)
goto done;
op_reg_flags = op_reg_val & (GP2AP020A00F_FLAG_A | GP2AP020A00F_FLAG_P
| GP2AP020A00F_PROX_DETECT);
op_reg_val &= (~GP2AP020A00F_FLAG_A & ~GP2AP020A00F_FLAG_P
& ~GP2AP020A00F_PROX_DETECT);
/* Clear interrupt flags (if not in INTTYPE_PULSE mode) */
if (priv->cur_opmode != GP2AP020A00F_OPMODE_PROX_DETECT) {
ret = regmap_write(priv->regmap, GP2AP020A00F_OP_REG,
op_reg_val);
if (ret < 0)
goto done;
}
if (op_reg_flags & GP2AP020A00F_FLAG_A) {
/* Check D0 register to assess if the lux mode
* transition is required.
*/
ret = regmap_bulk_read(priv->regmap, GP2AP020A00F_D0_L_REG,
d0_reg_buf, 2);
if (ret < 0)
goto done;
output_val = le16_to_cpup((__le16 *)d0_reg_buf);
if (gp2ap020a00f_adjust_lux_mode(priv, output_val))
goto done;
gp2ap020a00f_output_to_lux(priv, &output_val);
/*
* We need to check output value to distinguish
* between high and low ambient light threshold event.
*/
if (test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &priv->flags)) {
thresh_val_id =
GP2AP020A00F_THRESH_VAL_ID(GP2AP020A00F_TH_L_REG);
if (output_val > priv->thresh_val[thresh_val_id])
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(
IIO_LIGHT,
GP2AP020A00F_SCAN_MODE_LIGHT_CLEAR,
IIO_MOD_LIGHT_CLEAR,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
}
if (test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &priv->flags)) {
thresh_val_id =
GP2AP020A00F_THRESH_VAL_ID(GP2AP020A00F_TL_L_REG);
if (output_val < priv->thresh_val[thresh_val_id])
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(
IIO_LIGHT,
GP2AP020A00F_SCAN_MODE_LIGHT_CLEAR,
IIO_MOD_LIGHT_CLEAR,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
iio_get_time_ns(indio_dev));
}
}
if (priv->cur_opmode == GP2AP020A00F_OPMODE_READ_RAW_CLEAR ||
priv->cur_opmode == GP2AP020A00F_OPMODE_READ_RAW_IR ||
priv->cur_opmode == GP2AP020A00F_OPMODE_READ_RAW_PROXIMITY) {
set_bit(GP2AP020A00F_FLAG_DATA_READY, &priv->flags);
wake_up(&priv->data_ready_queue);
goto done;
}
if (test_bit(GP2AP020A00F_FLAG_ALS_CLEAR_TRIGGER, &priv->flags) ||
test_bit(GP2AP020A00F_FLAG_ALS_IR_TRIGGER, &priv->flags) ||
test_bit(GP2AP020A00F_FLAG_PROX_TRIGGER, &priv->flags))
/* This fires off the trigger. */
irq_work_queue(&priv->work);
done:
return IRQ_HANDLED;
}
static irqreturn_t gp2ap020a00f_trigger_handler(int irq, void *data)
{
struct iio_poll_func *pf = data;
struct iio_dev *indio_dev = pf->indio_dev;
struct gp2ap020a00f_data *priv = iio_priv(indio_dev);
size_t d_size = 0;
int i, out_val, ret;
for_each_set_bit(i, indio_dev->active_scan_mask,
indio_dev->masklength) {
ret = regmap_bulk_read(priv->regmap,
GP2AP020A00F_DATA_REG(i),
&priv->buffer[d_size], 2);
if (ret < 0)
goto done;
if (i == GP2AP020A00F_SCAN_MODE_LIGHT_CLEAR ||
i == GP2AP020A00F_SCAN_MODE_LIGHT_IR) {
out_val = le16_to_cpup((__le16 *)&priv->buffer[d_size]);
gp2ap020a00f_output_to_lux(priv, &out_val);
put_unaligned_le32(out_val, &priv->buffer[d_size]);
d_size += 4;
} else {
d_size += 2;
}
}
iio_push_to_buffers_with_timestamp(indio_dev, priv->buffer,
pf->timestamp);
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static u8 gp2ap020a00f_get_thresh_reg(const struct iio_chan_spec *chan,
enum iio_event_direction event_dir)
{
switch (chan->type) {
case IIO_PROXIMITY:
if (event_dir == IIO_EV_DIR_RISING)
return GP2AP020A00F_PH_L_REG;
else
return GP2AP020A00F_PL_L_REG;
case IIO_LIGHT:
if (event_dir == IIO_EV_DIR_RISING)
return GP2AP020A00F_TH_L_REG;
else
return GP2AP020A00F_TL_L_REG;
default:
break;
}
return -EINVAL;
}
static int gp2ap020a00f_write_event_val(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
struct gp2ap020a00f_data *data = iio_priv(indio_dev);
bool event_en = false;
u8 thresh_val_id;
u8 thresh_reg_l;
int err = 0;
mutex_lock(&data->lock);
thresh_reg_l = gp2ap020a00f_get_thresh_reg(chan, dir);
thresh_val_id = GP2AP020A00F_THRESH_VAL_ID(thresh_reg_l);
if (thresh_val_id > GP2AP020A00F_THRESH_PH) {
err = -EINVAL;
goto error_unlock;
}
switch (thresh_reg_l) {
case GP2AP020A00F_TH_L_REG:
event_en = test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV,
&data->flags);
break;
case GP2AP020A00F_TL_L_REG:
event_en = test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV,
&data->flags);
break;
case GP2AP020A00F_PH_L_REG:
if (val == 0) {
err = -EINVAL;
goto error_unlock;
}
event_en = test_bit(GP2AP020A00F_FLAG_PROX_RISING_EV,
&data->flags);
break;
case GP2AP020A00F_PL_L_REG:
if (val == 0) {
err = -EINVAL;
goto error_unlock;
}
event_en = test_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV,
&data->flags);
break;
}
data->thresh_val[thresh_val_id] = val;
err = gp2ap020a00f_write_event_threshold(data, thresh_val_id,
event_en);
error_unlock:
mutex_unlock(&data->lock);
return err;
}
static int gp2ap020a00f_read_event_val(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
struct gp2ap020a00f_data *data = iio_priv(indio_dev);
u8 thresh_reg_l;
int err = IIO_VAL_INT;
mutex_lock(&data->lock);
thresh_reg_l = gp2ap020a00f_get_thresh_reg(chan, dir);
if (thresh_reg_l > GP2AP020A00F_PH_L_REG) {
err = -EINVAL;
goto error_unlock;
}
*val = data->thresh_val[GP2AP020A00F_THRESH_VAL_ID(thresh_reg_l)];
error_unlock:
mutex_unlock(&data->lock);
return err;
}
static int gp2ap020a00f_write_prox_event_config(struct iio_dev *indio_dev,
int state)
{
struct gp2ap020a00f_data *data = iio_priv(indio_dev);
enum gp2ap020a00f_cmd cmd_high_ev, cmd_low_ev;
int err;
cmd_high_ev = state ? GP2AP020A00F_CMD_PROX_HIGH_EV_EN :
GP2AP020A00F_CMD_PROX_HIGH_EV_DIS;
cmd_low_ev = state ? GP2AP020A00F_CMD_PROX_LOW_EV_EN :
GP2AP020A00F_CMD_PROX_LOW_EV_DIS;
/*
* In order to enable proximity detection feature in the device
* both high and low threshold registers have to be written
* with different values, greater than zero.
*/
if (state) {
if (data->thresh_val[GP2AP020A00F_THRESH_PL] == 0)
return -EINVAL;
if (data->thresh_val[GP2AP020A00F_THRESH_PH] == 0)
return -EINVAL;
}
err = gp2ap020a00f_exec_cmd(data, cmd_high_ev);
if (err < 0)
return err;
err = gp2ap020a00f_exec_cmd(data, cmd_low_ev);
if (err < 0)
return err;
free_irq(data->client->irq, indio_dev);
if (state)
err = request_threaded_irq(data->client->irq, NULL,
&gp2ap020a00f_prox_sensing_handler,
IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING |
IRQF_ONESHOT,
"gp2ap020a00f_prox_sensing",
indio_dev);
else {
err = request_threaded_irq(data->client->irq, NULL,
&gp2ap020a00f_thresh_event_handler,
IRQF_TRIGGER_FALLING |
IRQF_ONESHOT,
"gp2ap020a00f_thresh_event",
indio_dev);
}
return err;
}
static int gp2ap020a00f_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
struct gp2ap020a00f_data *data = iio_priv(indio_dev);
enum gp2ap020a00f_cmd cmd;
int err;
mutex_lock(&data->lock);
switch (chan->type) {
case IIO_PROXIMITY:
err = gp2ap020a00f_write_prox_event_config(indio_dev, state);
break;
case IIO_LIGHT:
if (dir == IIO_EV_DIR_RISING) {
cmd = state ? GP2AP020A00F_CMD_ALS_HIGH_EV_EN :
GP2AP020A00F_CMD_ALS_HIGH_EV_DIS;
err = gp2ap020a00f_exec_cmd(data, cmd);
} else {
cmd = state ? GP2AP020A00F_CMD_ALS_LOW_EV_EN :
GP2AP020A00F_CMD_ALS_LOW_EV_DIS;
err = gp2ap020a00f_exec_cmd(data, cmd);
}
break;
default:
err = -EINVAL;
}
mutex_unlock(&data->lock);
return err;
}
static int gp2ap020a00f_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct gp2ap020a00f_data *data = iio_priv(indio_dev);
int event_en = 0;
mutex_lock(&data->lock);
switch (chan->type) {
case IIO_PROXIMITY:
if (dir == IIO_EV_DIR_RISING)
event_en = test_bit(GP2AP020A00F_FLAG_PROX_RISING_EV,
&data->flags);
else
event_en = test_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV,
&data->flags);
break;
case IIO_LIGHT:
if (dir == IIO_EV_DIR_RISING)
event_en = test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV,
&data->flags);
else
event_en = test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV,
&data->flags);
break;
default:
event_en = -EINVAL;
break;
}
mutex_unlock(&data->lock);
return event_en;
}
static int gp2ap020a00f_read_channel(struct gp2ap020a00f_data *data,
struct iio_chan_spec const *chan, int *val)
{
enum gp2ap020a00f_cmd cmd;
int err;
switch (chan->scan_index) {
case GP2AP020A00F_SCAN_MODE_LIGHT_CLEAR:
cmd = GP2AP020A00F_CMD_READ_RAW_CLEAR;
break;
case GP2AP020A00F_SCAN_MODE_LIGHT_IR:
cmd = GP2AP020A00F_CMD_READ_RAW_IR;
break;
case GP2AP020A00F_SCAN_MODE_PROXIMITY:
cmd = GP2AP020A00F_CMD_READ_RAW_PROXIMITY;
break;
default:
return -EINVAL;
}
err = gp2ap020a00f_exec_cmd(data, cmd);
if (err < 0) {
dev_err(&data->client->dev,
"gp2ap020a00f_exec_cmd failed\n");
goto error_ret;
}
err = gp2ap020a00f_read_output(data, chan->address, val);
if (err < 0)
dev_err(&data->client->dev,
"gp2ap020a00f_read_output failed\n");
err = gp2ap020a00f_set_operation_mode(data,
GP2AP020A00F_OPMODE_SHUTDOWN);
if (err < 0)
dev_err(&data->client->dev,
"Failed to shut down the device.\n");
if (cmd == GP2AP020A00F_CMD_READ_RAW_CLEAR ||
cmd == GP2AP020A00F_CMD_READ_RAW_IR)
gp2ap020a00f_output_to_lux(data, val);
error_ret:
return err;
}
static int gp2ap020a00f_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2,
long mask)
{
struct gp2ap020a00f_data *data = iio_priv(indio_dev);
int err = -EINVAL;
if (mask == IIO_CHAN_INFO_RAW) {
err = iio_device_claim_direct_mode(indio_dev);
if (err)
return err;
err = gp2ap020a00f_read_channel(data, chan, val);
iio_device_release_direct_mode(indio_dev);
}
return err < 0 ? err : IIO_VAL_INT;
}
static const struct iio_event_spec gp2ap020a00f_event_spec_light[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_event_spec gp2ap020a00f_event_spec_prox[] = {
{
.type = IIO_EV_TYPE_ROC,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
}, {
.type = IIO_EV_TYPE_ROC,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec gp2ap020a00f_channels[] = {
{
.type = IIO_LIGHT,
.channel2 = IIO_MOD_LIGHT_CLEAR,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.scan_type = {
.sign = 'u',
.realbits = 24,
.shift = 0,
.storagebits = 32,
.endianness = IIO_LE,
},
.scan_index = GP2AP020A00F_SCAN_MODE_LIGHT_CLEAR,
.address = GP2AP020A00F_D0_L_REG,
.event_spec = gp2ap020a00f_event_spec_light,
.num_event_specs = ARRAY_SIZE(gp2ap020a00f_event_spec_light),
},
{
.type = IIO_LIGHT,
.channel2 = IIO_MOD_LIGHT_IR,
.modified = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.scan_type = {
.sign = 'u',
.realbits = 24,
.shift = 0,
.storagebits = 32,
.endianness = IIO_LE,
},
.scan_index = GP2AP020A00F_SCAN_MODE_LIGHT_IR,
.address = GP2AP020A00F_D1_L_REG,
},
{
.type = IIO_PROXIMITY,
.modified = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.scan_type = {
.sign = 'u',
.realbits = 16,
.shift = 0,
.storagebits = 16,
.endianness = IIO_LE,
},
.scan_index = GP2AP020A00F_SCAN_MODE_PROXIMITY,
.address = GP2AP020A00F_D2_L_REG,
.event_spec = gp2ap020a00f_event_spec_prox,
.num_event_specs = ARRAY_SIZE(gp2ap020a00f_event_spec_prox),
},
IIO_CHAN_SOFT_TIMESTAMP(GP2AP020A00F_CHAN_TIMESTAMP),
};
static const struct iio_info gp2ap020a00f_info = {
.read_raw = &gp2ap020a00f_read_raw,
.read_event_value = &gp2ap020a00f_read_event_val,
.read_event_config = &gp2ap020a00f_read_event_config,
.write_event_value = &gp2ap020a00f_write_event_val,
.write_event_config = &gp2ap020a00f_write_event_config,
};
static int gp2ap020a00f_buffer_postenable(struct iio_dev *indio_dev)
{
struct gp2ap020a00f_data *data = iio_priv(indio_dev);
int i, err = 0;
mutex_lock(&data->lock);
/*
* Enable triggers according to the scan_mask. Enabling either
* LIGHT_CLEAR or LIGHT_IR scan mode results in enabling ALS
* module in the device, which generates samples in both D0 (clear)
* and D1 (ir) registers. As the two registers are bound to the
* two separate IIO channels they are treated in the driver logic
* as if they were controlled independently.
*/
for_each_set_bit(i, indio_dev->active_scan_mask,
indio_dev->masklength) {
switch (i) {
case GP2AP020A00F_SCAN_MODE_LIGHT_CLEAR:
err = gp2ap020a00f_exec_cmd(data,
GP2AP020A00F_CMD_TRIGGER_CLEAR_EN);
break;
case GP2AP020A00F_SCAN_MODE_LIGHT_IR:
err = gp2ap020a00f_exec_cmd(data,
GP2AP020A00F_CMD_TRIGGER_IR_EN);
break;
case GP2AP020A00F_SCAN_MODE_PROXIMITY:
err = gp2ap020a00f_exec_cmd(data,
GP2AP020A00F_CMD_TRIGGER_PROX_EN);
break;
}
}
if (err < 0)
goto error_unlock;
data->buffer = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
if (!data->buffer)
err = -ENOMEM;
error_unlock:
mutex_unlock(&data->lock);
return err;
}
static int gp2ap020a00f_buffer_predisable(struct iio_dev *indio_dev)
{
struct gp2ap020a00f_data *data = iio_priv(indio_dev);
int i, err = 0;
mutex_lock(&data->lock);
for_each_set_bit(i, indio_dev->active_scan_mask,
indio_dev->masklength) {
switch (i) {
case GP2AP020A00F_SCAN_MODE_LIGHT_CLEAR:
err = gp2ap020a00f_exec_cmd(data,
GP2AP020A00F_CMD_TRIGGER_CLEAR_DIS);
break;
case GP2AP020A00F_SCAN_MODE_LIGHT_IR:
err = gp2ap020a00f_exec_cmd(data,
GP2AP020A00F_CMD_TRIGGER_IR_DIS);
break;
case GP2AP020A00F_SCAN_MODE_PROXIMITY:
err = gp2ap020a00f_exec_cmd(data,
GP2AP020A00F_CMD_TRIGGER_PROX_DIS);
break;
}
}
if (err == 0)
kfree(data->buffer);
mutex_unlock(&data->lock);
return err;
}
static const struct iio_buffer_setup_ops gp2ap020a00f_buffer_setup_ops = {
.postenable = &gp2ap020a00f_buffer_postenable,
.predisable = &gp2ap020a00f_buffer_predisable,
};
static int gp2ap020a00f_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct gp2ap020a00f_data *data;
struct iio_dev *indio_dev;
struct regmap *regmap;
int err;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->vled_reg = devm_regulator_get(&client->dev, "vled");
if (IS_ERR(data->vled_reg))
return PTR_ERR(data->vled_reg);
err = regulator_enable(data->vled_reg);
if (err)
return err;
regmap = devm_regmap_init_i2c(client, &gp2ap020a00f_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "Regmap initialization failed.\n");
err = PTR_ERR(regmap);
goto error_regulator_disable;
}
/* Initialize device registers */
err = regmap_bulk_write(regmap, GP2AP020A00F_OP_REG,
gp2ap020a00f_reg_init_tab,
ARRAY_SIZE(gp2ap020a00f_reg_init_tab));
if (err < 0) {
dev_err(&client->dev, "Device initialization failed.\n");
goto error_regulator_disable;
}
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->cur_opmode = GP2AP020A00F_OPMODE_SHUTDOWN;
data->regmap = regmap;
init_waitqueue_head(&data->data_ready_queue);
mutex_init(&data->lock);
indio_dev->channels = gp2ap020a00f_channels;
indio_dev->num_channels = ARRAY_SIZE(gp2ap020a00f_channels);
indio_dev->info = &gp2ap020a00f_info;
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
/* Allocate buffer */
err = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
&gp2ap020a00f_trigger_handler, &gp2ap020a00f_buffer_setup_ops);
if (err < 0)
goto error_regulator_disable;
/* Allocate trigger */
data->trig = devm_iio_trigger_alloc(&client->dev, "%s-trigger",
indio_dev->name);
if (data->trig == NULL) {
err = -ENOMEM;
dev_err(&indio_dev->dev, "Failed to allocate iio trigger.\n");
goto error_uninit_buffer;
}
/* This needs to be requested here for read_raw calls to work. */
err = request_threaded_irq(client->irq, NULL,
&gp2ap020a00f_thresh_event_handler,
IRQF_TRIGGER_FALLING |
IRQF_ONESHOT,
"gp2ap020a00f_als_event",
indio_dev);
if (err < 0) {
dev_err(&client->dev, "Irq request failed.\n");
goto error_uninit_buffer;
}
init_irq_work(&data->work, gp2ap020a00f_iio_trigger_work);
err = iio_trigger_register(data->trig);
if (err < 0) {
dev_err(&client->dev, "Failed to register iio trigger.\n");
goto error_free_irq;
}
err = iio_device_register(indio_dev);
if (err < 0)
goto error_trigger_unregister;
return 0;
error_trigger_unregister:
iio_trigger_unregister(data->trig);
error_free_irq:
free_irq(client->irq, indio_dev);
error_uninit_buffer:
iio_triggered_buffer_cleanup(indio_dev);
error_regulator_disable:
regulator_disable(data->vled_reg);
return err;
}
static void gp2ap020a00f_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct gp2ap020a00f_data *data = iio_priv(indio_dev);
int err;
err = gp2ap020a00f_set_operation_mode(data,
GP2AP020A00F_OPMODE_SHUTDOWN);
if (err < 0)
dev_err(&indio_dev->dev, "Failed to power off the device.\n");
iio_device_unregister(indio_dev);
iio_trigger_unregister(data->trig);
free_irq(client->irq, indio_dev);
iio_triggered_buffer_cleanup(indio_dev);
regulator_disable(data->vled_reg);
}
static const struct i2c_device_id gp2ap020a00f_id[] = {
{ GP2A_I2C_NAME, 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, gp2ap020a00f_id);
static const struct of_device_id gp2ap020a00f_of_match[] = {
{ .compatible = "sharp,gp2ap020a00f" },
{ }
};
MODULE_DEVICE_TABLE(of, gp2ap020a00f_of_match);
static struct i2c_driver gp2ap020a00f_driver = {
.driver = {
.name = GP2A_I2C_NAME,
.of_match_table = gp2ap020a00f_of_match,
},
.probe = gp2ap020a00f_probe,
.remove = gp2ap020a00f_remove,
.id_table = gp2ap020a00f_id,
};
module_i2c_driver(gp2ap020a00f_driver);
MODULE_AUTHOR("Jacek Anaszewski <[email protected]>");
MODULE_DESCRIPTION("Sharp GP2AP020A00F Proximity/ALS sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/gp2ap020a00f.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* IIO driver for the light sensor ISL29028.
* ISL29028 is Concurrent Ambient Light and Proximity Sensor
*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2017 Brian Masney <[email protected]>
*
* Datasheets:
* - http://www.intersil.com/content/dam/Intersil/documents/isl2/isl29028.pdf
* - http://www.intersil.com/content/dam/Intersil/documents/isl2/isl29030.pdf
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/pm_runtime.h>
#define ISL29028_CONV_TIME_MS 100
#define ISL29028_REG_CONFIGURE 0x01
#define ISL29028_CONF_ALS_IR_MODE_ALS 0
#define ISL29028_CONF_ALS_IR_MODE_IR BIT(0)
#define ISL29028_CONF_ALS_IR_MODE_MASK BIT(0)
#define ISL29028_CONF_ALS_RANGE_LOW_LUX 0
#define ISL29028_CONF_ALS_RANGE_HIGH_LUX BIT(1)
#define ISL29028_CONF_ALS_RANGE_MASK BIT(1)
#define ISL29028_CONF_ALS_DIS 0
#define ISL29028_CONF_ALS_EN BIT(2)
#define ISL29028_CONF_ALS_EN_MASK BIT(2)
#define ISL29028_CONF_PROX_SLP_SH 4
#define ISL29028_CONF_PROX_SLP_MASK (7 << ISL29028_CONF_PROX_SLP_SH)
#define ISL29028_CONF_PROX_EN BIT(7)
#define ISL29028_CONF_PROX_EN_MASK BIT(7)
#define ISL29028_REG_INTERRUPT 0x02
#define ISL29028_REG_PROX_DATA 0x08
#define ISL29028_REG_ALSIR_L 0x09
#define ISL29028_REG_ALSIR_U 0x0A
#define ISL29028_REG_TEST1_MODE 0x0E
#define ISL29028_REG_TEST2_MODE 0x0F
#define ISL29028_NUM_REGS (ISL29028_REG_TEST2_MODE + 1)
#define ISL29028_POWER_OFF_DELAY_MS 2000
struct isl29028_prox_data {
int sampling_int;
int sampling_fract;
int sleep_time;
};
static const struct isl29028_prox_data isl29028_prox_data[] = {
{ 1, 250000, 800 },
{ 2, 500000, 400 },
{ 5, 0, 200 },
{ 10, 0, 100 },
{ 13, 300000, 75 },
{ 20, 0, 50 },
{ 80, 0, 13 }, /*
* Note: Data sheet lists 12.5 ms sleep time.
* Round up a half millisecond for msleep().
*/
{ 100, 0, 0 }
};
enum isl29028_als_ir_mode {
ISL29028_MODE_NONE = 0,
ISL29028_MODE_ALS,
ISL29028_MODE_IR,
};
struct isl29028_chip {
struct mutex lock;
struct regmap *regmap;
int prox_sampling_int;
int prox_sampling_frac;
bool enable_prox;
int lux_scale;
enum isl29028_als_ir_mode als_ir_mode;
};
static int isl29028_find_prox_sleep_index(int sampling_int, int sampling_fract)
{
int i;
for (i = 0; i < ARRAY_SIZE(isl29028_prox_data); ++i) {
if (isl29028_prox_data[i].sampling_int == sampling_int &&
isl29028_prox_data[i].sampling_fract == sampling_fract)
return i;
}
return -EINVAL;
}
static int isl29028_set_proxim_sampling(struct isl29028_chip *chip,
int sampling_int, int sampling_fract)
{
struct device *dev = regmap_get_device(chip->regmap);
int sleep_index, ret;
sleep_index = isl29028_find_prox_sleep_index(sampling_int,
sampling_fract);
if (sleep_index < 0)
return sleep_index;
ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
ISL29028_CONF_PROX_SLP_MASK,
sleep_index << ISL29028_CONF_PROX_SLP_SH);
if (ret < 0) {
dev_err(dev, "%s(): Error %d setting the proximity sampling\n",
__func__, ret);
return ret;
}
chip->prox_sampling_int = sampling_int;
chip->prox_sampling_frac = sampling_fract;
return ret;
}
static int isl29028_enable_proximity(struct isl29028_chip *chip)
{
int prox_index, ret;
ret = isl29028_set_proxim_sampling(chip, chip->prox_sampling_int,
chip->prox_sampling_frac);
if (ret < 0)
return ret;
ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
ISL29028_CONF_PROX_EN_MASK,
ISL29028_CONF_PROX_EN);
if (ret < 0)
return ret;
/* Wait for conversion to be complete for first sample */
prox_index = isl29028_find_prox_sleep_index(chip->prox_sampling_int,
chip->prox_sampling_frac);
if (prox_index < 0)
return prox_index;
msleep(isl29028_prox_data[prox_index].sleep_time);
return 0;
}
static int isl29028_set_als_scale(struct isl29028_chip *chip, int lux_scale)
{
struct device *dev = regmap_get_device(chip->regmap);
int val = (lux_scale == 2000) ? ISL29028_CONF_ALS_RANGE_HIGH_LUX :
ISL29028_CONF_ALS_RANGE_LOW_LUX;
int ret;
ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
ISL29028_CONF_ALS_RANGE_MASK, val);
if (ret < 0) {
dev_err(dev, "%s(): Error %d setting the ALS scale\n", __func__,
ret);
return ret;
}
chip->lux_scale = lux_scale;
return ret;
}
static int isl29028_set_als_ir_mode(struct isl29028_chip *chip,
enum isl29028_als_ir_mode mode)
{
int ret;
if (chip->als_ir_mode == mode)
return 0;
ret = isl29028_set_als_scale(chip, chip->lux_scale);
if (ret < 0)
return ret;
switch (mode) {
case ISL29028_MODE_ALS:
ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
ISL29028_CONF_ALS_IR_MODE_MASK,
ISL29028_CONF_ALS_IR_MODE_ALS);
if (ret < 0)
return ret;
ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
ISL29028_CONF_ALS_RANGE_MASK,
ISL29028_CONF_ALS_RANGE_HIGH_LUX);
break;
case ISL29028_MODE_IR:
ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
ISL29028_CONF_ALS_IR_MODE_MASK,
ISL29028_CONF_ALS_IR_MODE_IR);
break;
case ISL29028_MODE_NONE:
return regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
ISL29028_CONF_ALS_EN_MASK,
ISL29028_CONF_ALS_DIS);
}
if (ret < 0)
return ret;
/* Enable the ALS/IR */
ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
ISL29028_CONF_ALS_EN_MASK,
ISL29028_CONF_ALS_EN);
if (ret < 0)
return ret;
/* Need to wait for conversion time if ALS/IR mode enabled */
msleep(ISL29028_CONV_TIME_MS);
chip->als_ir_mode = mode;
return 0;
}
static int isl29028_read_als_ir(struct isl29028_chip *chip, int *als_ir)
{
struct device *dev = regmap_get_device(chip->regmap);
unsigned int lsb;
unsigned int msb;
int ret;
ret = regmap_read(chip->regmap, ISL29028_REG_ALSIR_L, &lsb);
if (ret < 0) {
dev_err(dev,
"%s(): Error %d reading register ALSIR_L\n",
__func__, ret);
return ret;
}
ret = regmap_read(chip->regmap, ISL29028_REG_ALSIR_U, &msb);
if (ret < 0) {
dev_err(dev,
"%s(): Error %d reading register ALSIR_U\n",
__func__, ret);
return ret;
}
*als_ir = ((msb & 0xF) << 8) | (lsb & 0xFF);
return 0;
}
static int isl29028_read_proxim(struct isl29028_chip *chip, int *prox)
{
struct device *dev = regmap_get_device(chip->regmap);
unsigned int data;
int ret;
if (!chip->enable_prox) {
ret = isl29028_enable_proximity(chip);
if (ret < 0)
return ret;
chip->enable_prox = true;
}
ret = regmap_read(chip->regmap, ISL29028_REG_PROX_DATA, &data);
if (ret < 0) {
dev_err(dev, "%s(): Error %d reading register PROX_DATA\n",
__func__, ret);
return ret;
}
*prox = data;
return 0;
}
static int isl29028_als_get(struct isl29028_chip *chip, int *als_data)
{
struct device *dev = regmap_get_device(chip->regmap);
int ret;
int als_ir_data;
ret = isl29028_set_als_ir_mode(chip, ISL29028_MODE_ALS);
if (ret < 0) {
dev_err(dev, "%s(): Error %d enabling ALS mode\n", __func__,
ret);
return ret;
}
ret = isl29028_read_als_ir(chip, &als_ir_data);
if (ret < 0)
return ret;
/*
* convert als data count to lux.
* if lux_scale = 125, lux = count * 0.031
* if lux_scale = 2000, lux = count * 0.49
*/
if (chip->lux_scale == 125)
als_ir_data = (als_ir_data * 31) / 1000;
else
als_ir_data = (als_ir_data * 49) / 100;
*als_data = als_ir_data;
return 0;
}
static int isl29028_ir_get(struct isl29028_chip *chip, int *ir_data)
{
struct device *dev = regmap_get_device(chip->regmap);
int ret;
ret = isl29028_set_als_ir_mode(chip, ISL29028_MODE_IR);
if (ret < 0) {
dev_err(dev, "%s(): Error %d enabling IR mode\n", __func__,
ret);
return ret;
}
return isl29028_read_als_ir(chip, ir_data);
}
static int isl29028_set_pm_runtime_busy(struct isl29028_chip *chip, bool on)
{
struct device *dev = regmap_get_device(chip->regmap);
int ret;
if (on) {
ret = pm_runtime_resume_and_get(dev);
} else {
pm_runtime_mark_last_busy(dev);
ret = pm_runtime_put_autosuspend(dev);
}
return ret;
}
/* Channel IO */
static int isl29028_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct isl29028_chip *chip = iio_priv(indio_dev);
struct device *dev = regmap_get_device(chip->regmap);
int ret;
ret = isl29028_set_pm_runtime_busy(chip, true);
if (ret < 0)
return ret;
mutex_lock(&chip->lock);
ret = -EINVAL;
switch (chan->type) {
case IIO_PROXIMITY:
if (mask != IIO_CHAN_INFO_SAMP_FREQ) {
dev_err(dev,
"%s(): proximity: Mask value 0x%08lx is not supported\n",
__func__, mask);
break;
}
if (val < 1 || val > 100) {
dev_err(dev,
"%s(): proximity: Sampling frequency %d is not in the range [1:100]\n",
__func__, val);
break;
}
ret = isl29028_set_proxim_sampling(chip, val, val2);
break;
case IIO_LIGHT:
if (mask != IIO_CHAN_INFO_SCALE) {
dev_err(dev,
"%s(): light: Mask value 0x%08lx is not supported\n",
__func__, mask);
break;
}
if (val != 125 && val != 2000) {
dev_err(dev,
"%s(): light: Lux scale %d is not in the set {125, 2000}\n",
__func__, val);
break;
}
ret = isl29028_set_als_scale(chip, val);
break;
default:
dev_err(dev, "%s(): Unsupported channel type %x\n",
__func__, chan->type);
break;
}
mutex_unlock(&chip->lock);
if (ret < 0)
return ret;
ret = isl29028_set_pm_runtime_busy(chip, false);
if (ret < 0)
return ret;
return ret;
}
static int isl29028_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct isl29028_chip *chip = iio_priv(indio_dev);
struct device *dev = regmap_get_device(chip->regmap);
int ret, pm_ret;
ret = isl29028_set_pm_runtime_busy(chip, true);
if (ret < 0)
return ret;
mutex_lock(&chip->lock);
ret = -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_LIGHT:
ret = isl29028_als_get(chip, val);
break;
case IIO_INTENSITY:
ret = isl29028_ir_get(chip, val);
break;
case IIO_PROXIMITY:
ret = isl29028_read_proxim(chip, val);
break;
default:
break;
}
if (ret < 0)
break;
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SAMP_FREQ:
if (chan->type != IIO_PROXIMITY)
break;
*val = chip->prox_sampling_int;
*val2 = chip->prox_sampling_frac;
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SCALE:
if (chan->type != IIO_LIGHT)
break;
*val = chip->lux_scale;
ret = IIO_VAL_INT;
break;
default:
dev_err(dev, "%s(): mask value 0x%08lx is not supported\n",
__func__, mask);
break;
}
mutex_unlock(&chip->lock);
if (ret < 0)
return ret;
/**
* Preserve the ret variable if the call to
* isl29028_set_pm_runtime_busy() is successful so the reading
* (if applicable) is returned to user space.
*/
pm_ret = isl29028_set_pm_runtime_busy(chip, false);
if (pm_ret < 0)
return pm_ret;
return ret;
}
static IIO_CONST_ATTR(in_proximity_sampling_frequency_available,
"1.25 2.5 5 10 13.3 20 80 100");
static IIO_CONST_ATTR(in_illuminance_scale_available, "125 2000");
#define ISL29028_CONST_ATTR(name) (&iio_const_attr_##name.dev_attr.attr)
static struct attribute *isl29028_attributes[] = {
ISL29028_CONST_ATTR(in_proximity_sampling_frequency_available),
ISL29028_CONST_ATTR(in_illuminance_scale_available),
NULL,
};
static const struct attribute_group isl29108_group = {
.attrs = isl29028_attributes,
};
static const struct iio_chan_spec isl29028_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_SCALE),
}, {
.type = IIO_INTENSITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
}, {
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
}
};
static const struct iio_info isl29028_info = {
.attrs = &isl29108_group,
.read_raw = isl29028_read_raw,
.write_raw = isl29028_write_raw,
};
static int isl29028_clear_configure_reg(struct isl29028_chip *chip)
{
struct device *dev = regmap_get_device(chip->regmap);
int ret;
ret = regmap_write(chip->regmap, ISL29028_REG_CONFIGURE, 0x0);
if (ret < 0)
dev_err(dev, "%s(): Error %d clearing the CONFIGURE register\n",
__func__, ret);
chip->als_ir_mode = ISL29028_MODE_NONE;
chip->enable_prox = false;
return ret;
}
static bool isl29028_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case ISL29028_REG_INTERRUPT:
case ISL29028_REG_PROX_DATA:
case ISL29028_REG_ALSIR_L:
case ISL29028_REG_ALSIR_U:
return true;
default:
return false;
}
}
static const struct regmap_config isl29028_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = isl29028_is_volatile_reg,
.max_register = ISL29028_NUM_REGS - 1,
.num_reg_defaults_raw = ISL29028_NUM_REGS,
.cache_type = REGCACHE_RBTREE,
};
static int isl29028_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct isl29028_chip *chip;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
if (!indio_dev)
return -ENOMEM;
chip = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
mutex_init(&chip->lock);
chip->regmap = devm_regmap_init_i2c(client, &isl29028_regmap_config);
if (IS_ERR(chip->regmap)) {
ret = PTR_ERR(chip->regmap);
dev_err(&client->dev, "%s: Error %d initializing regmap\n",
__func__, ret);
return ret;
}
chip->enable_prox = false;
chip->prox_sampling_int = 20;
chip->prox_sampling_frac = 0;
chip->lux_scale = 2000;
ret = regmap_write(chip->regmap, ISL29028_REG_TEST1_MODE, 0x0);
if (ret < 0) {
dev_err(&client->dev,
"%s(): Error %d writing to TEST1_MODE register\n",
__func__, ret);
return ret;
}
ret = regmap_write(chip->regmap, ISL29028_REG_TEST2_MODE, 0x0);
if (ret < 0) {
dev_err(&client->dev,
"%s(): Error %d writing to TEST2_MODE register\n",
__func__, ret);
return ret;
}
ret = isl29028_clear_configure_reg(chip);
if (ret < 0)
return ret;
indio_dev->info = &isl29028_info;
indio_dev->channels = isl29028_channels;
indio_dev->num_channels = ARRAY_SIZE(isl29028_channels);
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
pm_runtime_enable(&client->dev);
pm_runtime_set_autosuspend_delay(&client->dev,
ISL29028_POWER_OFF_DELAY_MS);
pm_runtime_use_autosuspend(&client->dev);
ret = iio_device_register(indio_dev);
if (ret < 0) {
dev_err(&client->dev,
"%s(): iio registration failed with error %d\n",
__func__, ret);
return ret;
}
return 0;
}
static void isl29028_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct isl29028_chip *chip = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
isl29028_clear_configure_reg(chip);
}
static int isl29028_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct isl29028_chip *chip = iio_priv(indio_dev);
int ret;
mutex_lock(&chip->lock);
ret = isl29028_clear_configure_reg(chip);
mutex_unlock(&chip->lock);
return ret;
}
static int isl29028_resume(struct device *dev)
{
/**
* The specific component (ALS/IR or proximity) will enable itself as
* needed the next time that the user requests a reading. This is done
* above in isl29028_set_als_ir_mode() and isl29028_enable_proximity().
*/
return 0;
}
static DEFINE_RUNTIME_DEV_PM_OPS(isl29028_pm_ops, isl29028_suspend,
isl29028_resume, NULL);
static const struct i2c_device_id isl29028_id[] = {
{"isl29028", 0},
{"isl29030", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, isl29028_id);
static const struct of_device_id isl29028_of_match[] = {
{ .compatible = "isl,isl29028", }, /* for backward compat., don't use */
{ .compatible = "isil,isl29028", },
{ .compatible = "isil,isl29030", },
{ },
};
MODULE_DEVICE_TABLE(of, isl29028_of_match);
static struct i2c_driver isl29028_driver = {
.driver = {
.name = "isl29028",
.pm = pm_ptr(&isl29028_pm_ops),
.of_match_table = isl29028_of_match,
},
.probe = isl29028_probe,
.remove = isl29028_remove,
.id_table = isl29028_id,
};
module_i2c_driver(isl29028_driver);
MODULE_DESCRIPTION("ISL29028 Ambient Light and Proximity Sensor driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Laxman Dewangan <[email protected]>");
| linux-master | drivers/iio/light/isl29028.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Azoteq IQS621/622 Ambient Light Sensors
*
* Copyright (C) 2019 Jeff LaBundy <[email protected]>
*/
#include <linux/device.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/kernel.h>
#include <linux/mfd/iqs62x.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/notifier.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define IQS621_ALS_FLAGS_LIGHT BIT(7)
#define IQS621_ALS_FLAGS_RANGE GENMASK(3, 0)
#define IQS621_ALS_UI_OUT 0x17
#define IQS621_ALS_THRESH_DARK 0x80
#define IQS621_ALS_THRESH_LIGHT 0x81
#define IQS622_IR_RANGE 0x15
#define IQS622_IR_FLAGS 0x16
#define IQS622_IR_FLAGS_TOUCH BIT(1)
#define IQS622_IR_FLAGS_PROX BIT(0)
#define IQS622_IR_UI_OUT 0x17
#define IQS622_IR_THRESH_PROX 0x91
#define IQS622_IR_THRESH_TOUCH 0x92
struct iqs621_als_private {
struct iqs62x_core *iqs62x;
struct iio_dev *indio_dev;
struct notifier_block notifier;
struct mutex lock;
bool light_en;
bool range_en;
bool prox_en;
u8 als_flags;
u8 ir_flags_mask;
u8 ir_flags;
u8 thresh_light;
u8 thresh_dark;
u8 thresh_prox;
};
static int iqs621_als_init(struct iqs621_als_private *iqs621_als)
{
struct iqs62x_core *iqs62x = iqs621_als->iqs62x;
unsigned int event_mask = 0;
int ret;
switch (iqs621_als->ir_flags_mask) {
case IQS622_IR_FLAGS_TOUCH:
ret = regmap_write(iqs62x->regmap, IQS622_IR_THRESH_TOUCH,
iqs621_als->thresh_prox);
break;
case IQS622_IR_FLAGS_PROX:
ret = regmap_write(iqs62x->regmap, IQS622_IR_THRESH_PROX,
iqs621_als->thresh_prox);
break;
default:
ret = regmap_write(iqs62x->regmap, IQS621_ALS_THRESH_LIGHT,
iqs621_als->thresh_light);
if (ret)
return ret;
ret = regmap_write(iqs62x->regmap, IQS621_ALS_THRESH_DARK,
iqs621_als->thresh_dark);
}
if (ret)
return ret;
if (iqs621_als->light_en || iqs621_als->range_en)
event_mask |= iqs62x->dev_desc->als_mask;
if (iqs621_als->prox_en)
event_mask |= iqs62x->dev_desc->ir_mask;
return regmap_update_bits(iqs62x->regmap, IQS620_GLBL_EVENT_MASK,
event_mask, 0);
}
static int iqs621_als_notifier(struct notifier_block *notifier,
unsigned long event_flags, void *context)
{
struct iqs62x_event_data *event_data = context;
struct iqs621_als_private *iqs621_als;
struct iio_dev *indio_dev;
bool light_new, light_old;
bool prox_new, prox_old;
u8 range_new, range_old;
s64 timestamp;
int ret;
iqs621_als = container_of(notifier, struct iqs621_als_private,
notifier);
indio_dev = iqs621_als->indio_dev;
timestamp = iio_get_time_ns(indio_dev);
mutex_lock(&iqs621_als->lock);
if (event_flags & BIT(IQS62X_EVENT_SYS_RESET)) {
ret = iqs621_als_init(iqs621_als);
if (ret) {
dev_err(indio_dev->dev.parent,
"Failed to re-initialize device: %d\n", ret);
ret = NOTIFY_BAD;
} else {
ret = NOTIFY_OK;
}
goto err_mutex;
}
if (!iqs621_als->light_en && !iqs621_als->range_en &&
!iqs621_als->prox_en) {
ret = NOTIFY_DONE;
goto err_mutex;
}
/* IQS621 only */
light_new = event_data->als_flags & IQS621_ALS_FLAGS_LIGHT;
light_old = iqs621_als->als_flags & IQS621_ALS_FLAGS_LIGHT;
if (iqs621_als->light_en && light_new && !light_old)
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
timestamp);
else if (iqs621_als->light_en && !light_new && light_old)
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
timestamp);
/* IQS621 and IQS622 */
range_new = event_data->als_flags & IQS621_ALS_FLAGS_RANGE;
range_old = iqs621_als->als_flags & IQS621_ALS_FLAGS_RANGE;
if (iqs621_als->range_en && (range_new > range_old))
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0,
IIO_EV_TYPE_CHANGE,
IIO_EV_DIR_RISING),
timestamp);
else if (iqs621_als->range_en && (range_new < range_old))
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0,
IIO_EV_TYPE_CHANGE,
IIO_EV_DIR_FALLING),
timestamp);
/* IQS622 only */
prox_new = event_data->ir_flags & iqs621_als->ir_flags_mask;
prox_old = iqs621_als->ir_flags & iqs621_als->ir_flags_mask;
if (iqs621_als->prox_en && prox_new && !prox_old)
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
timestamp);
else if (iqs621_als->prox_en && !prox_new && prox_old)
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
timestamp);
iqs621_als->als_flags = event_data->als_flags;
iqs621_als->ir_flags = event_data->ir_flags;
ret = NOTIFY_OK;
err_mutex:
mutex_unlock(&iqs621_als->lock);
return ret;
}
static void iqs621_als_notifier_unregister(void *context)
{
struct iqs621_als_private *iqs621_als = context;
struct iio_dev *indio_dev = iqs621_als->indio_dev;
int ret;
ret = blocking_notifier_chain_unregister(&iqs621_als->iqs62x->nh,
&iqs621_als->notifier);
if (ret)
dev_err(indio_dev->dev.parent,
"Failed to unregister notifier: %d\n", ret);
}
static int iqs621_als_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct iqs621_als_private *iqs621_als = iio_priv(indio_dev);
struct iqs62x_core *iqs62x = iqs621_als->iqs62x;
int ret;
__le16 val_buf;
switch (chan->type) {
case IIO_INTENSITY:
ret = regmap_read(iqs62x->regmap, chan->address, val);
if (ret)
return ret;
*val &= IQS621_ALS_FLAGS_RANGE;
return IIO_VAL_INT;
case IIO_PROXIMITY:
case IIO_LIGHT:
ret = regmap_raw_read(iqs62x->regmap, chan->address, &val_buf,
sizeof(val_buf));
if (ret)
return ret;
*val = le16_to_cpu(val_buf);
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int iqs621_als_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct iqs621_als_private *iqs621_als = iio_priv(indio_dev);
int ret;
mutex_lock(&iqs621_als->lock);
switch (chan->type) {
case IIO_LIGHT:
ret = iqs621_als->light_en;
break;
case IIO_INTENSITY:
ret = iqs621_als->range_en;
break;
case IIO_PROXIMITY:
ret = iqs621_als->prox_en;
break;
default:
ret = -EINVAL;
}
mutex_unlock(&iqs621_als->lock);
return ret;
}
static int iqs621_als_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
struct iqs621_als_private *iqs621_als = iio_priv(indio_dev);
struct iqs62x_core *iqs62x = iqs621_als->iqs62x;
unsigned int val;
int ret;
mutex_lock(&iqs621_als->lock);
ret = regmap_read(iqs62x->regmap, iqs62x->dev_desc->als_flags, &val);
if (ret)
goto err_mutex;
iqs621_als->als_flags = val;
switch (chan->type) {
case IIO_LIGHT:
ret = regmap_update_bits(iqs62x->regmap, IQS620_GLBL_EVENT_MASK,
iqs62x->dev_desc->als_mask,
iqs621_als->range_en || state ? 0 :
0xFF);
if (!ret)
iqs621_als->light_en = state;
break;
case IIO_INTENSITY:
ret = regmap_update_bits(iqs62x->regmap, IQS620_GLBL_EVENT_MASK,
iqs62x->dev_desc->als_mask,
iqs621_als->light_en || state ? 0 :
0xFF);
if (!ret)
iqs621_als->range_en = state;
break;
case IIO_PROXIMITY:
ret = regmap_read(iqs62x->regmap, IQS622_IR_FLAGS, &val);
if (ret)
goto err_mutex;
iqs621_als->ir_flags = val;
ret = regmap_update_bits(iqs62x->regmap, IQS620_GLBL_EVENT_MASK,
iqs62x->dev_desc->ir_mask,
state ? 0 : 0xFF);
if (!ret)
iqs621_als->prox_en = state;
break;
default:
ret = -EINVAL;
}
err_mutex:
mutex_unlock(&iqs621_als->lock);
return ret;
}
static int iqs621_als_read_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
struct iqs621_als_private *iqs621_als = iio_priv(indio_dev);
int ret = IIO_VAL_INT;
mutex_lock(&iqs621_als->lock);
switch (dir) {
case IIO_EV_DIR_RISING:
*val = iqs621_als->thresh_light * 16;
break;
case IIO_EV_DIR_FALLING:
*val = iqs621_als->thresh_dark * 4;
break;
case IIO_EV_DIR_EITHER:
if (iqs621_als->ir_flags_mask == IQS622_IR_FLAGS_TOUCH)
*val = iqs621_als->thresh_prox * 4;
else
*val = iqs621_als->thresh_prox;
break;
default:
ret = -EINVAL;
}
mutex_unlock(&iqs621_als->lock);
return ret;
}
static int iqs621_als_write_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
struct iqs621_als_private *iqs621_als = iio_priv(indio_dev);
struct iqs62x_core *iqs62x = iqs621_als->iqs62x;
unsigned int thresh_reg, thresh_val;
u8 ir_flags_mask, *thresh_cache;
int ret = -EINVAL;
mutex_lock(&iqs621_als->lock);
switch (dir) {
case IIO_EV_DIR_RISING:
thresh_reg = IQS621_ALS_THRESH_LIGHT;
thresh_val = val / 16;
thresh_cache = &iqs621_als->thresh_light;
ir_flags_mask = 0;
break;
case IIO_EV_DIR_FALLING:
thresh_reg = IQS621_ALS_THRESH_DARK;
thresh_val = val / 4;
thresh_cache = &iqs621_als->thresh_dark;
ir_flags_mask = 0;
break;
case IIO_EV_DIR_EITHER:
/*
* The IQS622 supports two detection thresholds, both measured
* in the same arbitrary units reported by read_raw: proximity
* (0 through 255 in steps of 1), and touch (0 through 1020 in
* steps of 4).
*
* Based on the single detection threshold chosen by the user,
* select the hardware threshold that gives the best trade-off
* between range and resolution.
*
* By default, the close-range (but coarse) touch threshold is
* chosen during probe.
*/
switch (val) {
case 0 ... 255:
thresh_reg = IQS622_IR_THRESH_PROX;
thresh_val = val;
ir_flags_mask = IQS622_IR_FLAGS_PROX;
break;
case 256 ... 1020:
thresh_reg = IQS622_IR_THRESH_TOUCH;
thresh_val = val / 4;
ir_flags_mask = IQS622_IR_FLAGS_TOUCH;
break;
default:
goto err_mutex;
}
thresh_cache = &iqs621_als->thresh_prox;
break;
default:
goto err_mutex;
}
if (thresh_val > 0xFF)
goto err_mutex;
ret = regmap_write(iqs62x->regmap, thresh_reg, thresh_val);
if (ret)
goto err_mutex;
*thresh_cache = thresh_val;
iqs621_als->ir_flags_mask = ir_flags_mask;
err_mutex:
mutex_unlock(&iqs621_als->lock);
return ret;
}
static const struct iio_info iqs621_als_info = {
.read_raw = &iqs621_als_read_raw,
.read_event_config = iqs621_als_read_event_config,
.write_event_config = iqs621_als_write_event_config,
.read_event_value = iqs621_als_read_event_value,
.write_event_value = iqs621_als_write_event_value,
};
static const struct iio_event_spec iqs621_als_range_events[] = {
{
.type = IIO_EV_TYPE_CHANGE,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_event_spec iqs621_als_light_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
},
};
static const struct iio_chan_spec iqs621_als_channels[] = {
{
.type = IIO_INTENSITY,
.address = IQS621_ALS_FLAGS,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.event_spec = iqs621_als_range_events,
.num_event_specs = ARRAY_SIZE(iqs621_als_range_events),
},
{
.type = IIO_LIGHT,
.address = IQS621_ALS_UI_OUT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.event_spec = iqs621_als_light_events,
.num_event_specs = ARRAY_SIZE(iqs621_als_light_events),
},
};
static const struct iio_event_spec iqs622_als_prox_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
BIT(IIO_EV_INFO_VALUE),
},
};
static const struct iio_chan_spec iqs622_als_channels[] = {
{
.type = IIO_INTENSITY,
.channel2 = IIO_MOD_LIGHT_BOTH,
.address = IQS622_ALS_FLAGS,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.event_spec = iqs621_als_range_events,
.num_event_specs = ARRAY_SIZE(iqs621_als_range_events),
.modified = true,
},
{
.type = IIO_INTENSITY,
.channel2 = IIO_MOD_LIGHT_IR,
.address = IQS622_IR_RANGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.modified = true,
},
{
.type = IIO_PROXIMITY,
.address = IQS622_IR_UI_OUT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.event_spec = iqs622_als_prox_events,
.num_event_specs = ARRAY_SIZE(iqs622_als_prox_events),
},
};
static int iqs621_als_probe(struct platform_device *pdev)
{
struct iqs62x_core *iqs62x = dev_get_drvdata(pdev->dev.parent);
struct iqs621_als_private *iqs621_als;
struct iio_dev *indio_dev;
unsigned int val;
int ret;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*iqs621_als));
if (!indio_dev)
return -ENOMEM;
iqs621_als = iio_priv(indio_dev);
iqs621_als->iqs62x = iqs62x;
iqs621_als->indio_dev = indio_dev;
if (iqs62x->dev_desc->prod_num == IQS622_PROD_NUM) {
ret = regmap_read(iqs62x->regmap, IQS622_IR_THRESH_TOUCH,
&val);
if (ret)
return ret;
iqs621_als->thresh_prox = val;
iqs621_als->ir_flags_mask = IQS622_IR_FLAGS_TOUCH;
indio_dev->channels = iqs622_als_channels;
indio_dev->num_channels = ARRAY_SIZE(iqs622_als_channels);
} else {
ret = regmap_read(iqs62x->regmap, IQS621_ALS_THRESH_LIGHT,
&val);
if (ret)
return ret;
iqs621_als->thresh_light = val;
ret = regmap_read(iqs62x->regmap, IQS621_ALS_THRESH_DARK,
&val);
if (ret)
return ret;
iqs621_als->thresh_dark = val;
indio_dev->channels = iqs621_als_channels;
indio_dev->num_channels = ARRAY_SIZE(iqs621_als_channels);
}
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->name = iqs62x->dev_desc->dev_name;
indio_dev->info = &iqs621_als_info;
mutex_init(&iqs621_als->lock);
iqs621_als->notifier.notifier_call = iqs621_als_notifier;
ret = blocking_notifier_chain_register(&iqs621_als->iqs62x->nh,
&iqs621_als->notifier);
if (ret) {
dev_err(&pdev->dev, "Failed to register notifier: %d\n", ret);
return ret;
}
ret = devm_add_action_or_reset(&pdev->dev,
iqs621_als_notifier_unregister,
iqs621_als);
if (ret)
return ret;
return devm_iio_device_register(&pdev->dev, indio_dev);
}
static struct platform_driver iqs621_als_platform_driver = {
.driver = {
.name = "iqs621-als",
},
.probe = iqs621_als_probe,
};
module_platform_driver(iqs621_als_platform_driver);
MODULE_AUTHOR("Jeff LaBundy <[email protected]>");
MODULE_DESCRIPTION("Azoteq IQS621/622 Ambient Light Sensors");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:iqs621-als");
| linux-master | drivers/iio/light/iqs621-als.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* lm3533-als.c -- LM3533 Ambient Light Sensor driver
*
* Copyright (C) 2011-2012 Texas Instruments
*
* Author: Johan Hovold <[email protected]>
*/
#include <linux/atomic.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/mfd/lm3533.h>
#define LM3533_ALS_RESISTOR_MIN 1
#define LM3533_ALS_RESISTOR_MAX 127
#define LM3533_ALS_CHANNEL_CURRENT_MAX 2
#define LM3533_ALS_THRESH_MAX 3
#define LM3533_ALS_ZONE_MAX 4
#define LM3533_REG_ALS_RESISTOR_SELECT 0x30
#define LM3533_REG_ALS_CONF 0x31
#define LM3533_REG_ALS_ZONE_INFO 0x34
#define LM3533_REG_ALS_READ_ADC_RAW 0x37
#define LM3533_REG_ALS_READ_ADC_AVERAGE 0x38
#define LM3533_REG_ALS_BOUNDARY_BASE 0x50
#define LM3533_REG_ALS_TARGET_BASE 0x60
#define LM3533_ALS_ENABLE_MASK 0x01
#define LM3533_ALS_INPUT_MODE_MASK 0x02
#define LM3533_ALS_INT_ENABLE_MASK 0x01
#define LM3533_ALS_ZONE_SHIFT 2
#define LM3533_ALS_ZONE_MASK 0x1c
#define LM3533_ALS_FLAG_INT_ENABLED 1
struct lm3533_als {
struct lm3533 *lm3533;
struct platform_device *pdev;
unsigned long flags;
int irq;
atomic_t zone;
struct mutex thresh_mutex;
};
static int lm3533_als_get_adc(struct iio_dev *indio_dev, bool average,
int *adc)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 reg;
u8 val;
int ret;
if (average)
reg = LM3533_REG_ALS_READ_ADC_AVERAGE;
else
reg = LM3533_REG_ALS_READ_ADC_RAW;
ret = lm3533_read(als->lm3533, reg, &val);
if (ret) {
dev_err(&indio_dev->dev, "failed to read adc\n");
return ret;
}
*adc = val;
return 0;
}
static int _lm3533_als_get_zone(struct iio_dev *indio_dev, u8 *zone)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 val;
int ret;
ret = lm3533_read(als->lm3533, LM3533_REG_ALS_ZONE_INFO, &val);
if (ret) {
dev_err(&indio_dev->dev, "failed to read zone\n");
return ret;
}
val = (val & LM3533_ALS_ZONE_MASK) >> LM3533_ALS_ZONE_SHIFT;
*zone = min_t(u8, val, LM3533_ALS_ZONE_MAX);
return 0;
}
static int lm3533_als_get_zone(struct iio_dev *indio_dev, u8 *zone)
{
struct lm3533_als *als = iio_priv(indio_dev);
int ret;
if (test_bit(LM3533_ALS_FLAG_INT_ENABLED, &als->flags)) {
*zone = atomic_read(&als->zone);
} else {
ret = _lm3533_als_get_zone(indio_dev, zone);
if (ret)
return ret;
}
return 0;
}
/*
* channel output channel 0..2
* zone zone 0..4
*/
static inline u8 lm3533_als_get_target_reg(unsigned channel, unsigned zone)
{
return LM3533_REG_ALS_TARGET_BASE + 5 * channel + zone;
}
static int lm3533_als_get_target(struct iio_dev *indio_dev, unsigned channel,
unsigned zone, u8 *val)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 reg;
int ret;
if (channel > LM3533_ALS_CHANNEL_CURRENT_MAX)
return -EINVAL;
if (zone > LM3533_ALS_ZONE_MAX)
return -EINVAL;
reg = lm3533_als_get_target_reg(channel, zone);
ret = lm3533_read(als->lm3533, reg, val);
if (ret)
dev_err(&indio_dev->dev, "failed to get target current\n");
return ret;
}
static int lm3533_als_set_target(struct iio_dev *indio_dev, unsigned channel,
unsigned zone, u8 val)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 reg;
int ret;
if (channel > LM3533_ALS_CHANNEL_CURRENT_MAX)
return -EINVAL;
if (zone > LM3533_ALS_ZONE_MAX)
return -EINVAL;
reg = lm3533_als_get_target_reg(channel, zone);
ret = lm3533_write(als->lm3533, reg, val);
if (ret)
dev_err(&indio_dev->dev, "failed to set target current\n");
return ret;
}
static int lm3533_als_get_current(struct iio_dev *indio_dev, unsigned channel,
int *val)
{
u8 zone;
u8 target;
int ret;
ret = lm3533_als_get_zone(indio_dev, &zone);
if (ret)
return ret;
ret = lm3533_als_get_target(indio_dev, channel, zone, &target);
if (ret)
return ret;
*val = target;
return 0;
}
static int lm3533_als_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_LIGHT:
ret = lm3533_als_get_adc(indio_dev, false, val);
break;
case IIO_CURRENT:
ret = lm3533_als_get_current(indio_dev, chan->channel,
val);
break;
default:
return -EINVAL;
}
break;
case IIO_CHAN_INFO_AVERAGE_RAW:
ret = lm3533_als_get_adc(indio_dev, true, val);
break;
default:
return -EINVAL;
}
if (ret)
return ret;
return IIO_VAL_INT;
}
#define CHANNEL_CURRENT(_channel) \
{ \
.type = IIO_CURRENT, \
.channel = _channel, \
.indexed = true, \
.output = true, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
}
static const struct iio_chan_spec lm3533_als_channels[] = {
{
.type = IIO_LIGHT,
.channel = 0,
.indexed = true,
.info_mask_separate = BIT(IIO_CHAN_INFO_AVERAGE_RAW) |
BIT(IIO_CHAN_INFO_RAW),
},
CHANNEL_CURRENT(0),
CHANNEL_CURRENT(1),
CHANNEL_CURRENT(2),
};
static irqreturn_t lm3533_als_isr(int irq, void *dev_id)
{
struct iio_dev *indio_dev = dev_id;
struct lm3533_als *als = iio_priv(indio_dev);
u8 zone;
int ret;
/* Clear interrupt by reading the ALS zone register. */
ret = _lm3533_als_get_zone(indio_dev, &zone);
if (ret)
goto out;
atomic_set(&als->zone, zone);
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_LIGHT,
0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(indio_dev));
out:
return IRQ_HANDLED;
}
static int lm3533_als_set_int_mode(struct iio_dev *indio_dev, int enable)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 mask = LM3533_ALS_INT_ENABLE_MASK;
u8 val;
int ret;
if (enable)
val = mask;
else
val = 0;
ret = lm3533_update(als->lm3533, LM3533_REG_ALS_ZONE_INFO, val, mask);
if (ret) {
dev_err(&indio_dev->dev, "failed to set int mode %d\n",
enable);
return ret;
}
return 0;
}
static int lm3533_als_get_int_mode(struct iio_dev *indio_dev, int *enable)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 mask = LM3533_ALS_INT_ENABLE_MASK;
u8 val;
int ret;
ret = lm3533_read(als->lm3533, LM3533_REG_ALS_ZONE_INFO, &val);
if (ret) {
dev_err(&indio_dev->dev, "failed to get int mode\n");
return ret;
}
*enable = !!(val & mask);
return 0;
}
static inline u8 lm3533_als_get_threshold_reg(unsigned nr, bool raising)
{
u8 offset = !raising;
return LM3533_REG_ALS_BOUNDARY_BASE + 2 * nr + offset;
}
static int lm3533_als_get_threshold(struct iio_dev *indio_dev, unsigned nr,
bool raising, u8 *val)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 reg;
int ret;
if (nr > LM3533_ALS_THRESH_MAX)
return -EINVAL;
reg = lm3533_als_get_threshold_reg(nr, raising);
ret = lm3533_read(als->lm3533, reg, val);
if (ret)
dev_err(&indio_dev->dev, "failed to get threshold\n");
return ret;
}
static int lm3533_als_set_threshold(struct iio_dev *indio_dev, unsigned nr,
bool raising, u8 val)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 val2;
u8 reg, reg2;
int ret;
if (nr > LM3533_ALS_THRESH_MAX)
return -EINVAL;
reg = lm3533_als_get_threshold_reg(nr, raising);
reg2 = lm3533_als_get_threshold_reg(nr, !raising);
mutex_lock(&als->thresh_mutex);
ret = lm3533_read(als->lm3533, reg2, &val2);
if (ret) {
dev_err(&indio_dev->dev, "failed to get threshold\n");
goto out;
}
/*
* This device does not allow negative hysteresis (in fact, it uses
* whichever value is smaller as the lower bound) so we need to make
* sure that thresh_falling <= thresh_raising.
*/
if ((raising && (val < val2)) || (!raising && (val > val2))) {
ret = -EINVAL;
goto out;
}
ret = lm3533_write(als->lm3533, reg, val);
if (ret) {
dev_err(&indio_dev->dev, "failed to set threshold\n");
goto out;
}
out:
mutex_unlock(&als->thresh_mutex);
return ret;
}
static int lm3533_als_get_hysteresis(struct iio_dev *indio_dev, unsigned nr,
u8 *val)
{
struct lm3533_als *als = iio_priv(indio_dev);
u8 falling;
u8 raising;
int ret;
if (nr > LM3533_ALS_THRESH_MAX)
return -EINVAL;
mutex_lock(&als->thresh_mutex);
ret = lm3533_als_get_threshold(indio_dev, nr, false, &falling);
if (ret)
goto out;
ret = lm3533_als_get_threshold(indio_dev, nr, true, &raising);
if (ret)
goto out;
*val = raising - falling;
out:
mutex_unlock(&als->thresh_mutex);
return ret;
}
static ssize_t show_thresh_either_en(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct lm3533_als *als = iio_priv(indio_dev);
int enable;
int ret;
if (als->irq) {
ret = lm3533_als_get_int_mode(indio_dev, &enable);
if (ret)
return ret;
} else {
enable = 0;
}
return sysfs_emit(buf, "%u\n", enable);
}
static ssize_t store_thresh_either_en(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct lm3533_als *als = iio_priv(indio_dev);
unsigned long enable;
bool int_enabled;
u8 zone;
int ret;
if (!als->irq)
return -EBUSY;
if (kstrtoul(buf, 0, &enable))
return -EINVAL;
int_enabled = test_bit(LM3533_ALS_FLAG_INT_ENABLED, &als->flags);
if (enable && !int_enabled) {
ret = lm3533_als_get_zone(indio_dev, &zone);
if (ret)
return ret;
atomic_set(&als->zone, zone);
set_bit(LM3533_ALS_FLAG_INT_ENABLED, &als->flags);
}
ret = lm3533_als_set_int_mode(indio_dev, enable);
if (ret) {
if (!int_enabled)
clear_bit(LM3533_ALS_FLAG_INT_ENABLED, &als->flags);
return ret;
}
if (!enable)
clear_bit(LM3533_ALS_FLAG_INT_ENABLED, &als->flags);
return len;
}
static ssize_t show_zone(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
u8 zone;
int ret;
ret = lm3533_als_get_zone(indio_dev, &zone);
if (ret)
return ret;
return sysfs_emit(buf, "%u\n", zone);
}
enum lm3533_als_attribute_type {
LM3533_ATTR_TYPE_HYSTERESIS,
LM3533_ATTR_TYPE_TARGET,
LM3533_ATTR_TYPE_THRESH_FALLING,
LM3533_ATTR_TYPE_THRESH_RAISING,
};
struct lm3533_als_attribute {
struct device_attribute dev_attr;
enum lm3533_als_attribute_type type;
u8 val1;
u8 val2;
};
static inline struct lm3533_als_attribute *
to_lm3533_als_attr(struct device_attribute *attr)
{
return container_of(attr, struct lm3533_als_attribute, dev_attr);
}
static ssize_t show_als_attr(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct lm3533_als_attribute *als_attr = to_lm3533_als_attr(attr);
u8 val;
int ret;
switch (als_attr->type) {
case LM3533_ATTR_TYPE_HYSTERESIS:
ret = lm3533_als_get_hysteresis(indio_dev, als_attr->val1,
&val);
break;
case LM3533_ATTR_TYPE_TARGET:
ret = lm3533_als_get_target(indio_dev, als_attr->val1,
als_attr->val2, &val);
break;
case LM3533_ATTR_TYPE_THRESH_FALLING:
ret = lm3533_als_get_threshold(indio_dev, als_attr->val1,
false, &val);
break;
case LM3533_ATTR_TYPE_THRESH_RAISING:
ret = lm3533_als_get_threshold(indio_dev, als_attr->val1,
true, &val);
break;
default:
ret = -ENXIO;
}
if (ret)
return ret;
return sysfs_emit(buf, "%u\n", val);
}
static ssize_t store_als_attr(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct lm3533_als_attribute *als_attr = to_lm3533_als_attr(attr);
u8 val;
int ret;
if (kstrtou8(buf, 0, &val))
return -EINVAL;
switch (als_attr->type) {
case LM3533_ATTR_TYPE_TARGET:
ret = lm3533_als_set_target(indio_dev, als_attr->val1,
als_attr->val2, val);
break;
case LM3533_ATTR_TYPE_THRESH_FALLING:
ret = lm3533_als_set_threshold(indio_dev, als_attr->val1,
false, val);
break;
case LM3533_ATTR_TYPE_THRESH_RAISING:
ret = lm3533_als_set_threshold(indio_dev, als_attr->val1,
true, val);
break;
default:
ret = -ENXIO;
}
if (ret)
return ret;
return len;
}
#define ALS_ATTR(_name, _mode, _show, _store, _type, _val1, _val2) \
{ .dev_attr = __ATTR(_name, _mode, _show, _store), \
.type = _type, \
.val1 = _val1, \
.val2 = _val2 }
#define LM3533_ALS_ATTR(_name, _mode, _show, _store, _type, _val1, _val2) \
struct lm3533_als_attribute lm3533_als_attr_##_name = \
ALS_ATTR(_name, _mode, _show, _store, _type, _val1, _val2)
#define ALS_TARGET_ATTR_RW(_channel, _zone) \
LM3533_ALS_ATTR(out_current##_channel##_current##_zone##_raw, \
S_IRUGO | S_IWUSR, \
show_als_attr, store_als_attr, \
LM3533_ATTR_TYPE_TARGET, _channel, _zone)
/*
* ALS output current values (ALS mapper targets)
*
* out_current[0-2]_current[0-4]_raw 0-255
*/
static ALS_TARGET_ATTR_RW(0, 0);
static ALS_TARGET_ATTR_RW(0, 1);
static ALS_TARGET_ATTR_RW(0, 2);
static ALS_TARGET_ATTR_RW(0, 3);
static ALS_TARGET_ATTR_RW(0, 4);
static ALS_TARGET_ATTR_RW(1, 0);
static ALS_TARGET_ATTR_RW(1, 1);
static ALS_TARGET_ATTR_RW(1, 2);
static ALS_TARGET_ATTR_RW(1, 3);
static ALS_TARGET_ATTR_RW(1, 4);
static ALS_TARGET_ATTR_RW(2, 0);
static ALS_TARGET_ATTR_RW(2, 1);
static ALS_TARGET_ATTR_RW(2, 2);
static ALS_TARGET_ATTR_RW(2, 3);
static ALS_TARGET_ATTR_RW(2, 4);
#define ALS_THRESH_FALLING_ATTR_RW(_nr) \
LM3533_ALS_ATTR(in_illuminance0_thresh##_nr##_falling_value, \
S_IRUGO | S_IWUSR, \
show_als_attr, store_als_attr, \
LM3533_ATTR_TYPE_THRESH_FALLING, _nr, 0)
#define ALS_THRESH_RAISING_ATTR_RW(_nr) \
LM3533_ALS_ATTR(in_illuminance0_thresh##_nr##_raising_value, \
S_IRUGO | S_IWUSR, \
show_als_attr, store_als_attr, \
LM3533_ATTR_TYPE_THRESH_RAISING, _nr, 0)
/*
* ALS Zone thresholds (boundaries)
*
* in_illuminance0_thresh[0-3]_falling_value 0-255
* in_illuminance0_thresh[0-3]_raising_value 0-255
*/
static ALS_THRESH_FALLING_ATTR_RW(0);
static ALS_THRESH_FALLING_ATTR_RW(1);
static ALS_THRESH_FALLING_ATTR_RW(2);
static ALS_THRESH_FALLING_ATTR_RW(3);
static ALS_THRESH_RAISING_ATTR_RW(0);
static ALS_THRESH_RAISING_ATTR_RW(1);
static ALS_THRESH_RAISING_ATTR_RW(2);
static ALS_THRESH_RAISING_ATTR_RW(3);
#define ALS_HYSTERESIS_ATTR_RO(_nr) \
LM3533_ALS_ATTR(in_illuminance0_thresh##_nr##_hysteresis, \
S_IRUGO, show_als_attr, NULL, \
LM3533_ATTR_TYPE_HYSTERESIS, _nr, 0)
/*
* ALS Zone threshold hysteresis
*
* threshY_hysteresis = threshY_raising - threshY_falling
*
* in_illuminance0_thresh[0-3]_hysteresis 0-255
* in_illuminance0_thresh[0-3]_hysteresis 0-255
*/
static ALS_HYSTERESIS_ATTR_RO(0);
static ALS_HYSTERESIS_ATTR_RO(1);
static ALS_HYSTERESIS_ATTR_RO(2);
static ALS_HYSTERESIS_ATTR_RO(3);
#define ILLUMINANCE_ATTR_RO(_name) \
DEVICE_ATTR(in_illuminance0_##_name, S_IRUGO, show_##_name, NULL)
#define ILLUMINANCE_ATTR_RW(_name) \
DEVICE_ATTR(in_illuminance0_##_name, S_IRUGO | S_IWUSR, \
show_##_name, store_##_name)
/*
* ALS Zone threshold-event enable
*
* in_illuminance0_thresh_either_en 0,1
*/
static ILLUMINANCE_ATTR_RW(thresh_either_en);
/*
* ALS Current Zone
*
* in_illuminance0_zone 0-4
*/
static ILLUMINANCE_ATTR_RO(zone);
static struct attribute *lm3533_als_event_attributes[] = {
&dev_attr_in_illuminance0_thresh_either_en.attr,
&lm3533_als_attr_in_illuminance0_thresh0_falling_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh0_hysteresis.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh0_raising_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh1_falling_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh1_hysteresis.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh1_raising_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh2_falling_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh2_hysteresis.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh2_raising_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh3_falling_value.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh3_hysteresis.dev_attr.attr,
&lm3533_als_attr_in_illuminance0_thresh3_raising_value.dev_attr.attr,
NULL
};
static const struct attribute_group lm3533_als_event_attribute_group = {
.attrs = lm3533_als_event_attributes
};
static struct attribute *lm3533_als_attributes[] = {
&dev_attr_in_illuminance0_zone.attr,
&lm3533_als_attr_out_current0_current0_raw.dev_attr.attr,
&lm3533_als_attr_out_current0_current1_raw.dev_attr.attr,
&lm3533_als_attr_out_current0_current2_raw.dev_attr.attr,
&lm3533_als_attr_out_current0_current3_raw.dev_attr.attr,
&lm3533_als_attr_out_current0_current4_raw.dev_attr.attr,
&lm3533_als_attr_out_current1_current0_raw.dev_attr.attr,
&lm3533_als_attr_out_current1_current1_raw.dev_attr.attr,
&lm3533_als_attr_out_current1_current2_raw.dev_attr.attr,
&lm3533_als_attr_out_current1_current3_raw.dev_attr.attr,
&lm3533_als_attr_out_current1_current4_raw.dev_attr.attr,
&lm3533_als_attr_out_current2_current0_raw.dev_attr.attr,
&lm3533_als_attr_out_current2_current1_raw.dev_attr.attr,
&lm3533_als_attr_out_current2_current2_raw.dev_attr.attr,
&lm3533_als_attr_out_current2_current3_raw.dev_attr.attr,
&lm3533_als_attr_out_current2_current4_raw.dev_attr.attr,
NULL
};
static const struct attribute_group lm3533_als_attribute_group = {
.attrs = lm3533_als_attributes
};
static int lm3533_als_set_input_mode(struct lm3533_als *als, bool pwm_mode)
{
u8 mask = LM3533_ALS_INPUT_MODE_MASK;
u8 val;
int ret;
if (pwm_mode)
val = mask; /* pwm input */
else
val = 0; /* analog input */
ret = lm3533_update(als->lm3533, LM3533_REG_ALS_CONF, val, mask);
if (ret) {
dev_err(&als->pdev->dev, "failed to set input mode %d\n",
pwm_mode);
return ret;
}
return 0;
}
static int lm3533_als_set_resistor(struct lm3533_als *als, u8 val)
{
int ret;
if (val < LM3533_ALS_RESISTOR_MIN || val > LM3533_ALS_RESISTOR_MAX) {
dev_err(&als->pdev->dev, "invalid resistor value\n");
return -EINVAL;
}
ret = lm3533_write(als->lm3533, LM3533_REG_ALS_RESISTOR_SELECT, val);
if (ret) {
dev_err(&als->pdev->dev, "failed to set resistor\n");
return ret;
}
return 0;
}
static int lm3533_als_setup(struct lm3533_als *als,
struct lm3533_als_platform_data *pdata)
{
int ret;
ret = lm3533_als_set_input_mode(als, pdata->pwm_mode);
if (ret)
return ret;
/* ALS input is always high impedance in PWM-mode. */
if (!pdata->pwm_mode) {
ret = lm3533_als_set_resistor(als, pdata->r_select);
if (ret)
return ret;
}
return 0;
}
static int lm3533_als_setup_irq(struct lm3533_als *als, void *dev)
{
u8 mask = LM3533_ALS_INT_ENABLE_MASK;
int ret;
/* Make sure interrupts are disabled. */
ret = lm3533_update(als->lm3533, LM3533_REG_ALS_ZONE_INFO, 0, mask);
if (ret) {
dev_err(&als->pdev->dev, "failed to disable interrupts\n");
return ret;
}
ret = request_threaded_irq(als->irq, NULL, lm3533_als_isr,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
dev_name(&als->pdev->dev), dev);
if (ret) {
dev_err(&als->pdev->dev, "failed to request irq %d\n",
als->irq);
return ret;
}
return 0;
}
static int lm3533_als_enable(struct lm3533_als *als)
{
u8 mask = LM3533_ALS_ENABLE_MASK;
int ret;
ret = lm3533_update(als->lm3533, LM3533_REG_ALS_CONF, mask, mask);
if (ret)
dev_err(&als->pdev->dev, "failed to enable ALS\n");
return ret;
}
static int lm3533_als_disable(struct lm3533_als *als)
{
u8 mask = LM3533_ALS_ENABLE_MASK;
int ret;
ret = lm3533_update(als->lm3533, LM3533_REG_ALS_CONF, 0, mask);
if (ret)
dev_err(&als->pdev->dev, "failed to disable ALS\n");
return ret;
}
static const struct iio_info lm3533_als_info = {
.attrs = &lm3533_als_attribute_group,
.event_attrs = &lm3533_als_event_attribute_group,
.read_raw = &lm3533_als_read_raw,
};
static int lm3533_als_probe(struct platform_device *pdev)
{
struct lm3533 *lm3533;
struct lm3533_als_platform_data *pdata;
struct lm3533_als *als;
struct iio_dev *indio_dev;
int ret;
lm3533 = dev_get_drvdata(pdev->dev.parent);
if (!lm3533)
return -EINVAL;
pdata = pdev->dev.platform_data;
if (!pdata) {
dev_err(&pdev->dev, "no platform data\n");
return -EINVAL;
}
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*als));
if (!indio_dev)
return -ENOMEM;
indio_dev->info = &lm3533_als_info;
indio_dev->channels = lm3533_als_channels;
indio_dev->num_channels = ARRAY_SIZE(lm3533_als_channels);
indio_dev->name = dev_name(&pdev->dev);
iio_device_set_parent(indio_dev, pdev->dev.parent);
indio_dev->modes = INDIO_DIRECT_MODE;
als = iio_priv(indio_dev);
als->lm3533 = lm3533;
als->pdev = pdev;
als->irq = lm3533->irq;
atomic_set(&als->zone, 0);
mutex_init(&als->thresh_mutex);
platform_set_drvdata(pdev, indio_dev);
if (als->irq) {
ret = lm3533_als_setup_irq(als, indio_dev);
if (ret)
return ret;
}
ret = lm3533_als_setup(als, pdata);
if (ret)
goto err_free_irq;
ret = lm3533_als_enable(als);
if (ret)
goto err_free_irq;
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&pdev->dev, "failed to register ALS\n");
goto err_disable;
}
return 0;
err_disable:
lm3533_als_disable(als);
err_free_irq:
if (als->irq)
free_irq(als->irq, indio_dev);
return ret;
}
static int lm3533_als_remove(struct platform_device *pdev)
{
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct lm3533_als *als = iio_priv(indio_dev);
lm3533_als_set_int_mode(indio_dev, false);
iio_device_unregister(indio_dev);
lm3533_als_disable(als);
if (als->irq)
free_irq(als->irq, indio_dev);
return 0;
}
static struct platform_driver lm3533_als_driver = {
.driver = {
.name = "lm3533-als",
},
.probe = lm3533_als_probe,
.remove = lm3533_als_remove,
};
module_platform_driver(lm3533_als_driver);
MODULE_AUTHOR("Johan Hovold <[email protected]>");
MODULE_DESCRIPTION("LM3533 Ambient Light Sensor driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:lm3533-als");
| linux-master | drivers/iio/light/lm3533-als.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tcs3414.c - Support for TAOS TCS3414 digital color sensor
*
* Copyright (c) 2014 Peter Meerwald <[email protected]>
*
* Digital color sensor with 16-bit channels for red, green, blue, clear);
* 7-bit I2C slave address 0x39 (TCS3414) or 0x29, 0x49, 0x59 (TCS3413,
* TCS3415, TCS3416, resp.)
*
* TODO: sync, interrupt support, thresholds, prescaler
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#define TCS3414_DRV_NAME "tcs3414"
#define TCS3414_COMMAND BIT(7)
#define TCS3414_COMMAND_WORD (TCS3414_COMMAND | BIT(5))
#define TCS3414_CONTROL (TCS3414_COMMAND | 0x00)
#define TCS3414_TIMING (TCS3414_COMMAND | 0x01)
#define TCS3414_ID (TCS3414_COMMAND | 0x04)
#define TCS3414_GAIN (TCS3414_COMMAND | 0x07)
#define TCS3414_DATA_GREEN (TCS3414_COMMAND_WORD | 0x10)
#define TCS3414_DATA_RED (TCS3414_COMMAND_WORD | 0x12)
#define TCS3414_DATA_BLUE (TCS3414_COMMAND_WORD | 0x14)
#define TCS3414_DATA_CLEAR (TCS3414_COMMAND_WORD | 0x16)
#define TCS3414_CONTROL_ADC_VALID BIT(4)
#define TCS3414_CONTROL_ADC_EN BIT(1)
#define TCS3414_CONTROL_POWER BIT(0)
#define TCS3414_INTEG_MASK GENMASK(1, 0)
#define TCS3414_INTEG_12MS 0x0
#define TCS3414_INTEG_100MS 0x1
#define TCS3414_INTEG_400MS 0x2
#define TCS3414_GAIN_MASK GENMASK(5, 4)
#define TCS3414_GAIN_SHIFT 4
struct tcs3414_data {
struct i2c_client *client;
u8 control;
u8 gain;
u8 timing;
/* Ensure timestamp is naturally aligned */
struct {
u16 chans[4];
s64 timestamp __aligned(8);
} scan;
};
#define TCS3414_CHANNEL(_color, _si, _addr) { \
.type = IIO_INTENSITY, \
.modified = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_INT_TIME), \
.channel2 = IIO_MOD_LIGHT_##_color, \
.address = _addr, \
.scan_index = _si, \
.scan_type = { \
.sign = 'u', \
.realbits = 16, \
.storagebits = 16, \
.endianness = IIO_CPU, \
}, \
}
/* scale factors: 1/gain */
static const int tcs3414_scales[][2] = {
{1, 0}, {0, 250000}, {0, 62500}, {0, 15625}
};
/* integration time in ms */
static const int tcs3414_times[] = { 12, 100, 400 };
static const struct iio_chan_spec tcs3414_channels[] = {
TCS3414_CHANNEL(GREEN, 0, TCS3414_DATA_GREEN),
TCS3414_CHANNEL(RED, 1, TCS3414_DATA_RED),
TCS3414_CHANNEL(BLUE, 2, TCS3414_DATA_BLUE),
TCS3414_CHANNEL(CLEAR, 3, TCS3414_DATA_CLEAR),
IIO_CHAN_SOFT_TIMESTAMP(4),
};
static int tcs3414_req_data(struct tcs3414_data *data)
{
int tries = 25;
int ret;
ret = i2c_smbus_write_byte_data(data->client, TCS3414_CONTROL,
data->control | TCS3414_CONTROL_ADC_EN);
if (ret < 0)
return ret;
while (tries--) {
ret = i2c_smbus_read_byte_data(data->client, TCS3414_CONTROL);
if (ret < 0)
return ret;
if (ret & TCS3414_CONTROL_ADC_VALID)
break;
msleep(20);
}
ret = i2c_smbus_write_byte_data(data->client, TCS3414_CONTROL,
data->control);
if (ret < 0)
return ret;
if (tries < 0) {
dev_err(&data->client->dev, "data not ready\n");
return -EIO;
}
return 0;
}
static int tcs3414_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct tcs3414_data *data = iio_priv(indio_dev);
int i, ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = tcs3414_req_data(data);
if (ret < 0) {
iio_device_release_direct_mode(indio_dev);
return ret;
}
ret = i2c_smbus_read_word_data(data->client, chan->address);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
i = (data->gain & TCS3414_GAIN_MASK) >> TCS3414_GAIN_SHIFT;
*val = tcs3414_scales[i][0];
*val2 = tcs3414_scales[i][1];
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_INT_TIME:
*val = 0;
*val2 = tcs3414_times[data->timing & TCS3414_INTEG_MASK] * 1000;
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
}
static int tcs3414_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct tcs3414_data *data = iio_priv(indio_dev);
int i;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
for (i = 0; i < ARRAY_SIZE(tcs3414_scales); i++) {
if (val == tcs3414_scales[i][0] &&
val2 == tcs3414_scales[i][1]) {
data->gain &= ~TCS3414_GAIN_MASK;
data->gain |= i << TCS3414_GAIN_SHIFT;
return i2c_smbus_write_byte_data(
data->client, TCS3414_GAIN,
data->gain);
}
}
return -EINVAL;
case IIO_CHAN_INFO_INT_TIME:
if (val != 0)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(tcs3414_times); i++) {
if (val2 == tcs3414_times[i] * 1000) {
data->timing &= ~TCS3414_INTEG_MASK;
data->timing |= i;
return i2c_smbus_write_byte_data(
data->client, TCS3414_TIMING,
data->timing);
}
}
return -EINVAL;
default:
return -EINVAL;
}
}
static irqreturn_t tcs3414_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct tcs3414_data *data = iio_priv(indio_dev);
int i, j = 0;
for_each_set_bit(i, indio_dev->active_scan_mask,
indio_dev->masklength) {
int ret = i2c_smbus_read_word_data(data->client,
TCS3414_DATA_GREEN + 2*i);
if (ret < 0)
goto done;
data->scan.chans[j++] = ret;
}
iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
iio_get_time_ns(indio_dev));
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static IIO_CONST_ATTR(scale_available, "1 0.25 0.0625 0.015625");
static IIO_CONST_ATTR_INT_TIME_AVAIL("0.012 0.1 0.4");
static struct attribute *tcs3414_attributes[] = {
&iio_const_attr_scale_available.dev_attr.attr,
&iio_const_attr_integration_time_available.dev_attr.attr,
NULL
};
static const struct attribute_group tcs3414_attribute_group = {
.attrs = tcs3414_attributes,
};
static const struct iio_info tcs3414_info = {
.read_raw = tcs3414_read_raw,
.write_raw = tcs3414_write_raw,
.attrs = &tcs3414_attribute_group,
};
static int tcs3414_buffer_postenable(struct iio_dev *indio_dev)
{
struct tcs3414_data *data = iio_priv(indio_dev);
data->control |= TCS3414_CONTROL_ADC_EN;
return i2c_smbus_write_byte_data(data->client, TCS3414_CONTROL,
data->control);
}
static int tcs3414_buffer_predisable(struct iio_dev *indio_dev)
{
struct tcs3414_data *data = iio_priv(indio_dev);
data->control &= ~TCS3414_CONTROL_ADC_EN;
return i2c_smbus_write_byte_data(data->client, TCS3414_CONTROL,
data->control);
}
static const struct iio_buffer_setup_ops tcs3414_buffer_setup_ops = {
.postenable = tcs3414_buffer_postenable,
.predisable = tcs3414_buffer_predisable,
};
static int tcs3414_powerdown(struct tcs3414_data *data)
{
return i2c_smbus_write_byte_data(data->client, TCS3414_CONTROL,
data->control & ~(TCS3414_CONTROL_POWER |
TCS3414_CONTROL_ADC_EN));
}
static void tcs3414_powerdown_cleanup(void *data)
{
tcs3414_powerdown(data);
}
static int tcs3414_probe(struct i2c_client *client)
{
struct tcs3414_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (indio_dev == NULL)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
indio_dev->info = &tcs3414_info;
indio_dev->name = TCS3414_DRV_NAME;
indio_dev->channels = tcs3414_channels;
indio_dev->num_channels = ARRAY_SIZE(tcs3414_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = i2c_smbus_read_byte_data(data->client, TCS3414_ID);
if (ret < 0)
return ret;
switch (ret & 0xf0) {
case 0x00:
dev_info(&client->dev, "TCS3404 found\n");
break;
case 0x10:
dev_info(&client->dev, "TCS3413/14/15/16 found\n");
break;
default:
return -ENODEV;
}
data->control = TCS3414_CONTROL_POWER;
ret = i2c_smbus_write_byte_data(data->client, TCS3414_CONTROL,
data->control);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&client->dev, tcs3414_powerdown_cleanup,
data);
if (ret < 0)
return ret;
data->timing = TCS3414_INTEG_12MS; /* free running */
ret = i2c_smbus_write_byte_data(data->client, TCS3414_TIMING,
data->timing);
if (ret < 0)
return ret;
ret = i2c_smbus_read_byte_data(data->client, TCS3414_GAIN);
if (ret < 0)
return ret;
data->gain = ret;
ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
tcs3414_trigger_handler, &tcs3414_buffer_setup_ops);
if (ret < 0)
return ret;
return devm_iio_device_register(&client->dev, indio_dev);
}
static int tcs3414_suspend(struct device *dev)
{
struct tcs3414_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
return tcs3414_powerdown(data);
}
static int tcs3414_resume(struct device *dev)
{
struct tcs3414_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
return i2c_smbus_write_byte_data(data->client, TCS3414_CONTROL,
data->control);
}
static DEFINE_SIMPLE_DEV_PM_OPS(tcs3414_pm_ops, tcs3414_suspend,
tcs3414_resume);
static const struct i2c_device_id tcs3414_id[] = {
{ "tcs3414", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tcs3414_id);
static struct i2c_driver tcs3414_driver = {
.driver = {
.name = TCS3414_DRV_NAME,
.pm = pm_sleep_ptr(&tcs3414_pm_ops),
},
.probe = tcs3414_probe,
.id_table = tcs3414_id,
};
module_i2c_driver(tcs3414_driver);
MODULE_AUTHOR("Peter Meerwald <[email protected]>");
MODULE_DESCRIPTION("TCS3414 digital color sensors driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/tcs3414.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Capella Microsystems Inc.
* Author: Kevin Tsai <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/interrupt.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
#include <linux/init.h>
/* Registers Address */
#define CM32181_REG_ADDR_CMD 0x00
#define CM32181_REG_ADDR_WH 0x01
#define CM32181_REG_ADDR_WL 0x02
#define CM32181_REG_ADDR_TEST 0x03
#define CM32181_REG_ADDR_ALS 0x04
#define CM32181_REG_ADDR_STATUS 0x06
#define CM32181_REG_ADDR_ID 0x07
/* Number of Configurable Registers */
#define CM32181_CONF_REG_NUM 4
/* CMD register */
#define CM32181_CMD_ALS_DISABLE BIT(0)
#define CM32181_CMD_ALS_INT_EN BIT(1)
#define CM32181_CMD_ALS_THRES_WINDOW BIT(2)
#define CM32181_CMD_ALS_PERS_SHIFT 4
#define CM32181_CMD_ALS_PERS_MASK (0x03 << CM32181_CMD_ALS_PERS_SHIFT)
#define CM32181_CMD_ALS_PERS_DEFAULT (0x01 << CM32181_CMD_ALS_PERS_SHIFT)
#define CM32181_CMD_ALS_IT_SHIFT 6
#define CM32181_CMD_ALS_IT_MASK (0x0F << CM32181_CMD_ALS_IT_SHIFT)
#define CM32181_CMD_ALS_IT_DEFAULT (0x00 << CM32181_CMD_ALS_IT_SHIFT)
#define CM32181_CMD_ALS_SM_SHIFT 11
#define CM32181_CMD_ALS_SM_MASK (0x03 << CM32181_CMD_ALS_SM_SHIFT)
#define CM32181_CMD_ALS_SM_DEFAULT (0x01 << CM32181_CMD_ALS_SM_SHIFT)
#define CM32181_LUX_PER_BIT 500 /* ALS_SM=01 IT=800ms */
#define CM32181_LUX_PER_BIT_RESOLUTION 100000
#define CM32181_LUX_PER_BIT_BASE_IT 800000 /* Based on IT=800ms */
#define CM32181_CALIBSCALE_DEFAULT 100000
#define CM32181_CALIBSCALE_RESOLUTION 100000
#define SMBUS_ALERT_RESPONSE_ADDRESS 0x0c
/* CPM0 Index 0: device-id (3218 or 32181), 1: Unknown, 2: init_regs_bitmap */
#define CPM0_REGS_BITMAP 2
#define CPM0_HEADER_SIZE 3
/* CPM1 Index 0: lux_per_bit, 1: calibscale, 2: resolution (100000) */
#define CPM1_LUX_PER_BIT 0
#define CPM1_CALIBSCALE 1
#define CPM1_SIZE 3
/* CM3218 Family */
static const int cm3218_als_it_bits[] = { 0, 1, 2, 3 };
static const int cm3218_als_it_values[] = { 100000, 200000, 400000, 800000 };
/* CM32181 Family */
static const int cm32181_als_it_bits[] = { 12, 8, 0, 1, 2, 3 };
static const int cm32181_als_it_values[] = {
25000, 50000, 100000, 200000, 400000, 800000
};
struct cm32181_chip {
struct i2c_client *client;
struct device *dev;
struct mutex lock;
u16 conf_regs[CM32181_CONF_REG_NUM];
unsigned long init_regs_bitmap;
int calibscale;
int lux_per_bit;
int lux_per_bit_base_it;
int num_als_it;
const int *als_it_bits;
const int *als_it_values;
};
static int cm32181_read_als_it(struct cm32181_chip *cm32181, int *val2);
#ifdef CONFIG_ACPI
/**
* cm32181_acpi_get_cpm() - Get CPM object from ACPI
* @dev: pointer of struct device.
* @obj_name: pointer of ACPI object name.
* @values: pointer of array for return elements.
* @count: maximum size of return array.
*
* Convert ACPI CPM table to array.
*
* Return: -ENODEV for fail. Otherwise is number of elements.
*/
static int cm32181_acpi_get_cpm(struct device *dev, char *obj_name,
u64 *values, int count)
{
struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
union acpi_object *cpm, *elem;
acpi_handle handle;
acpi_status status;
int i;
handle = ACPI_HANDLE(dev);
if (!handle)
return -ENODEV;
status = acpi_evaluate_object(handle, obj_name, NULL, &buffer);
if (ACPI_FAILURE(status)) {
dev_err(dev, "object %s not found\n", obj_name);
return -ENODEV;
}
cpm = buffer.pointer;
if (cpm->package.count > count)
dev_warn(dev, "%s table contains %u values, only using first %d values\n",
obj_name, cpm->package.count, count);
count = min_t(int, cpm->package.count, count);
for (i = 0; i < count; i++) {
elem = &(cpm->package.elements[i]);
values[i] = elem->integer.value;
}
kfree(buffer.pointer);
return count;
}
static void cm32181_acpi_parse_cpm_tables(struct cm32181_chip *cm32181)
{
u64 vals[CPM0_HEADER_SIZE + CM32181_CONF_REG_NUM];
struct device *dev = cm32181->dev;
int i, count;
count = cm32181_acpi_get_cpm(dev, "CPM0", vals, ARRAY_SIZE(vals));
if (count <= CPM0_HEADER_SIZE)
return;
count -= CPM0_HEADER_SIZE;
cm32181->init_regs_bitmap = vals[CPM0_REGS_BITMAP];
cm32181->init_regs_bitmap &= GENMASK(count - 1, 0);
for_each_set_bit(i, &cm32181->init_regs_bitmap, count)
cm32181->conf_regs[i] = vals[CPM0_HEADER_SIZE + i];
count = cm32181_acpi_get_cpm(dev, "CPM1", vals, ARRAY_SIZE(vals));
if (count != CPM1_SIZE)
return;
cm32181->lux_per_bit = vals[CPM1_LUX_PER_BIT];
/* Check for uncalibrated devices */
if (vals[CPM1_CALIBSCALE] == CM32181_CALIBSCALE_DEFAULT)
return;
cm32181->calibscale = vals[CPM1_CALIBSCALE];
/* CPM1 lux_per_bit is for the current it value */
cm32181_read_als_it(cm32181, &cm32181->lux_per_bit_base_it);
}
#else
static void cm32181_acpi_parse_cpm_tables(struct cm32181_chip *cm32181)
{
}
#endif /* CONFIG_ACPI */
/**
* cm32181_reg_init() - Initialize CM32181 registers
* @cm32181: pointer of struct cm32181.
*
* Initialize CM32181 ambient light sensor register to default values.
*
* Return: 0 for success; otherwise for error code.
*/
static int cm32181_reg_init(struct cm32181_chip *cm32181)
{
struct i2c_client *client = cm32181->client;
int i;
s32 ret;
ret = i2c_smbus_read_word_data(client, CM32181_REG_ADDR_ID);
if (ret < 0)
return ret;
/* check device ID */
switch (ret & 0xFF) {
case 0x18: /* CM3218 */
cm32181->num_als_it = ARRAY_SIZE(cm3218_als_it_bits);
cm32181->als_it_bits = cm3218_als_it_bits;
cm32181->als_it_values = cm3218_als_it_values;
break;
case 0x81: /* CM32181 */
case 0x82: /* CM32182, fully compat. with CM32181 */
cm32181->num_als_it = ARRAY_SIZE(cm32181_als_it_bits);
cm32181->als_it_bits = cm32181_als_it_bits;
cm32181->als_it_values = cm32181_als_it_values;
break;
default:
return -ENODEV;
}
/* Default Values */
cm32181->conf_regs[CM32181_REG_ADDR_CMD] =
CM32181_CMD_ALS_IT_DEFAULT | CM32181_CMD_ALS_SM_DEFAULT;
cm32181->init_regs_bitmap = BIT(CM32181_REG_ADDR_CMD);
cm32181->calibscale = CM32181_CALIBSCALE_DEFAULT;
cm32181->lux_per_bit = CM32181_LUX_PER_BIT;
cm32181->lux_per_bit_base_it = CM32181_LUX_PER_BIT_BASE_IT;
if (ACPI_HANDLE(cm32181->dev))
cm32181_acpi_parse_cpm_tables(cm32181);
/* Initialize registers*/
for_each_set_bit(i, &cm32181->init_regs_bitmap, CM32181_CONF_REG_NUM) {
ret = i2c_smbus_write_word_data(client, i,
cm32181->conf_regs[i]);
if (ret < 0)
return ret;
}
return 0;
}
/**
* cm32181_read_als_it() - Get sensor integration time (ms)
* @cm32181: pointer of struct cm32181
* @val2: pointer of int to load the als_it value.
*
* Report the current integration time in milliseconds.
*
* Return: IIO_VAL_INT_PLUS_MICRO for success, otherwise -EINVAL.
*/
static int cm32181_read_als_it(struct cm32181_chip *cm32181, int *val2)
{
u16 als_it;
int i;
als_it = cm32181->conf_regs[CM32181_REG_ADDR_CMD];
als_it &= CM32181_CMD_ALS_IT_MASK;
als_it >>= CM32181_CMD_ALS_IT_SHIFT;
for (i = 0; i < cm32181->num_als_it; i++) {
if (als_it == cm32181->als_it_bits[i]) {
*val2 = cm32181->als_it_values[i];
return IIO_VAL_INT_PLUS_MICRO;
}
}
return -EINVAL;
}
/**
* cm32181_write_als_it() - Write sensor integration time
* @cm32181: pointer of struct cm32181.
* @val: integration time by millisecond.
*
* Convert integration time (ms) to sensor value.
*
* Return: i2c_smbus_write_word_data command return value.
*/
static int cm32181_write_als_it(struct cm32181_chip *cm32181, int val)
{
struct i2c_client *client = cm32181->client;
u16 als_it;
int ret, i, n;
n = cm32181->num_als_it;
for (i = 0; i < n; i++)
if (val <= cm32181->als_it_values[i])
break;
if (i >= n)
i = n - 1;
als_it = cm32181->als_it_bits[i];
als_it <<= CM32181_CMD_ALS_IT_SHIFT;
mutex_lock(&cm32181->lock);
cm32181->conf_regs[CM32181_REG_ADDR_CMD] &=
~CM32181_CMD_ALS_IT_MASK;
cm32181->conf_regs[CM32181_REG_ADDR_CMD] |=
als_it;
ret = i2c_smbus_write_word_data(client, CM32181_REG_ADDR_CMD,
cm32181->conf_regs[CM32181_REG_ADDR_CMD]);
mutex_unlock(&cm32181->lock);
return ret;
}
/**
* cm32181_get_lux() - report current lux value
* @cm32181: pointer of struct cm32181.
*
* Convert sensor raw data to lux. It depends on integration
* time and calibscale variable.
*
* Return: Positive value is lux, otherwise is error code.
*/
static int cm32181_get_lux(struct cm32181_chip *cm32181)
{
struct i2c_client *client = cm32181->client;
int ret;
int als_it;
u64 lux;
ret = cm32181_read_als_it(cm32181, &als_it);
if (ret < 0)
return -EINVAL;
lux = cm32181->lux_per_bit;
lux *= cm32181->lux_per_bit_base_it;
lux = div_u64(lux, als_it);
ret = i2c_smbus_read_word_data(client, CM32181_REG_ADDR_ALS);
if (ret < 0)
return ret;
lux *= ret;
lux *= cm32181->calibscale;
lux = div_u64(lux, CM32181_CALIBSCALE_RESOLUTION);
lux = div_u64(lux, CM32181_LUX_PER_BIT_RESOLUTION);
if (lux > 0xFFFF)
lux = 0xFFFF;
return lux;
}
static int cm32181_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct cm32181_chip *cm32181 = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
ret = cm32181_get_lux(cm32181);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBSCALE:
*val = cm32181->calibscale;
return IIO_VAL_INT;
case IIO_CHAN_INFO_INT_TIME:
*val = 0;
ret = cm32181_read_als_it(cm32181, val2);
return ret;
}
return -EINVAL;
}
static int cm32181_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct cm32181_chip *cm32181 = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_CALIBSCALE:
cm32181->calibscale = val;
return val;
case IIO_CHAN_INFO_INT_TIME:
ret = cm32181_write_als_it(cm32181, val2);
return ret;
}
return -EINVAL;
}
/**
* cm32181_get_it_available() - Get available ALS IT value
* @dev: pointer of struct device.
* @attr: pointer of struct device_attribute.
* @buf: pointer of return string buffer.
*
* Display the available integration time values by millisecond.
*
* Return: string length.
*/
static ssize_t cm32181_get_it_available(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct cm32181_chip *cm32181 = iio_priv(dev_to_iio_dev(dev));
int i, n, len;
n = cm32181->num_als_it;
for (i = 0, len = 0; i < n; i++)
len += sprintf(buf + len, "0.%06u ", cm32181->als_it_values[i]);
return len + sprintf(buf + len, "\n");
}
static const struct iio_chan_spec cm32181_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate =
BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_INT_TIME),
}
};
static IIO_DEVICE_ATTR(in_illuminance_integration_time_available,
S_IRUGO, cm32181_get_it_available, NULL, 0);
static struct attribute *cm32181_attributes[] = {
&iio_dev_attr_in_illuminance_integration_time_available.dev_attr.attr,
NULL,
};
static const struct attribute_group cm32181_attribute_group = {
.attrs = cm32181_attributes
};
static const struct iio_info cm32181_info = {
.read_raw = &cm32181_read_raw,
.write_raw = &cm32181_write_raw,
.attrs = &cm32181_attribute_group,
};
static void cm32181_unregister_dummy_client(void *data)
{
struct i2c_client *client = data;
/* Unregister the dummy client */
i2c_unregister_device(client);
}
static int cm32181_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct cm32181_chip *cm32181;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*cm32181));
if (!indio_dev)
return -ENOMEM;
i2c_set_clientdata(client, indio_dev);
/*
* Some ACPI systems list 2 I2C resources for the CM3218 sensor, the
* SMBus Alert Response Address (ARA, 0x0c) and the actual I2C address.
* Detect this and take the following step to deal with it:
* 1. When a SMBus Alert capable sensor has an Alert asserted, it will
* not respond on its actual I2C address. Read a byte from the ARA
* to clear any pending Alerts.
* 2. Create a "dummy" client for the actual I2C address and
* use that client to communicate with the sensor.
*/
if (ACPI_HANDLE(dev) && client->addr == SMBUS_ALERT_RESPONSE_ADDRESS) {
struct i2c_board_info board_info = { .type = "dummy" };
i2c_smbus_read_byte(client);
client = i2c_acpi_new_device(dev, 1, &board_info);
if (IS_ERR(client))
return PTR_ERR(client);
ret = devm_add_action_or_reset(dev, cm32181_unregister_dummy_client, client);
if (ret)
return ret;
}
cm32181 = iio_priv(indio_dev);
cm32181->client = client;
cm32181->dev = dev;
mutex_init(&cm32181->lock);
indio_dev->channels = cm32181_channels;
indio_dev->num_channels = ARRAY_SIZE(cm32181_channels);
indio_dev->info = &cm32181_info;
indio_dev->name = dev_name(dev);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = cm32181_reg_init(cm32181);
if (ret) {
dev_err(dev, "%s: register init failed\n", __func__);
return ret;
}
ret = devm_iio_device_register(dev, indio_dev);
if (ret) {
dev_err(dev, "%s: regist device failed\n", __func__);
return ret;
}
return 0;
}
static int cm32181_suspend(struct device *dev)
{
struct cm32181_chip *cm32181 = iio_priv(dev_get_drvdata(dev));
struct i2c_client *client = cm32181->client;
return i2c_smbus_write_word_data(client, CM32181_REG_ADDR_CMD,
CM32181_CMD_ALS_DISABLE);
}
static int cm32181_resume(struct device *dev)
{
struct cm32181_chip *cm32181 = iio_priv(dev_get_drvdata(dev));
struct i2c_client *client = cm32181->client;
return i2c_smbus_write_word_data(client, CM32181_REG_ADDR_CMD,
cm32181->conf_regs[CM32181_REG_ADDR_CMD]);
}
static DEFINE_SIMPLE_DEV_PM_OPS(cm32181_pm_ops, cm32181_suspend, cm32181_resume);
static const struct of_device_id cm32181_of_match[] = {
{ .compatible = "capella,cm3218" },
{ .compatible = "capella,cm32181" },
{ }
};
MODULE_DEVICE_TABLE(of, cm32181_of_match);
#ifdef CONFIG_ACPI
static const struct acpi_device_id cm32181_acpi_match[] = {
{ "CPLM3218", 0 },
{ }
};
MODULE_DEVICE_TABLE(acpi, cm32181_acpi_match);
#endif
static struct i2c_driver cm32181_driver = {
.driver = {
.name = "cm32181",
.acpi_match_table = ACPI_PTR(cm32181_acpi_match),
.of_match_table = cm32181_of_match,
.pm = pm_sleep_ptr(&cm32181_pm_ops),
},
.probe = cm32181_probe,
};
module_i2c_driver(cm32181_driver);
MODULE_AUTHOR("Kevin Tsai <[email protected]>");
MODULE_DESCRIPTION("CM32181 ambient light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/cm32181.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ROHM 1780GLI Ambient Light Sensor Driver
*
* Copyright (C) 2016 Linaro Ltd.
* Author: Linus Walleij <[email protected]>
* Loosely based on the previous BH1780 ALS misc driver
* Copyright (C) 2010 Texas Instruments
* Author: Hemanth V <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/pm_runtime.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/bitops.h>
#define BH1780_CMD_BIT BIT(7)
#define BH1780_REG_CONTROL 0x00
#define BH1780_REG_PARTID 0x0A
#define BH1780_REG_MANFID 0x0B
#define BH1780_REG_DLOW 0x0C
#define BH1780_REG_DHIGH 0x0D
#define BH1780_REVMASK GENMASK(3,0)
#define BH1780_POWMASK GENMASK(1,0)
#define BH1780_POFF (0x0)
#define BH1780_PON (0x3)
/* power on settling time in ms */
#define BH1780_PON_DELAY 2
/* max time before value available in ms */
#define BH1780_INTERVAL 250
struct bh1780_data {
struct i2c_client *client;
};
static int bh1780_write(struct bh1780_data *bh1780, u8 reg, u8 val)
{
int ret = i2c_smbus_write_byte_data(bh1780->client,
BH1780_CMD_BIT | reg,
val);
if (ret < 0)
dev_err(&bh1780->client->dev,
"i2c_smbus_write_byte_data failed error "
"%d, register %01x\n",
ret, reg);
return ret;
}
static int bh1780_read(struct bh1780_data *bh1780, u8 reg)
{
int ret = i2c_smbus_read_byte_data(bh1780->client,
BH1780_CMD_BIT | reg);
if (ret < 0)
dev_err(&bh1780->client->dev,
"i2c_smbus_read_byte_data failed error "
"%d, register %01x\n",
ret, reg);
return ret;
}
static int bh1780_read_word(struct bh1780_data *bh1780, u8 reg)
{
int ret = i2c_smbus_read_word_data(bh1780->client,
BH1780_CMD_BIT | reg);
if (ret < 0)
dev_err(&bh1780->client->dev,
"i2c_smbus_read_word_data failed error "
"%d, register %01x\n",
ret, reg);
return ret;
}
static int bh1780_debugfs_reg_access(struct iio_dev *indio_dev,
unsigned int reg, unsigned int writeval,
unsigned int *readval)
{
struct bh1780_data *bh1780 = iio_priv(indio_dev);
int ret;
if (!readval)
return bh1780_write(bh1780, (u8)reg, (u8)writeval);
ret = bh1780_read(bh1780, (u8)reg);
if (ret < 0)
return ret;
*readval = ret;
return 0;
}
static int bh1780_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct bh1780_data *bh1780 = iio_priv(indio_dev);
int value;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_LIGHT:
pm_runtime_get_sync(&bh1780->client->dev);
value = bh1780_read_word(bh1780, BH1780_REG_DLOW);
if (value < 0)
return value;
pm_runtime_mark_last_busy(&bh1780->client->dev);
pm_runtime_put_autosuspend(&bh1780->client->dev);
*val = value;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_INT_TIME:
*val = 0;
*val2 = BH1780_INTERVAL * 1000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static const struct iio_info bh1780_info = {
.read_raw = bh1780_read_raw,
.debugfs_reg_access = bh1780_debugfs_reg_access,
};
static const struct iio_chan_spec bh1780_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_INT_TIME)
}
};
static int bh1780_probe(struct i2c_client *client)
{
int ret;
struct bh1780_data *bh1780;
struct i2c_adapter *adapter = client->adapter;
struct iio_dev *indio_dev;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE))
return -EIO;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*bh1780));
if (!indio_dev)
return -ENOMEM;
bh1780 = iio_priv(indio_dev);
bh1780->client = client;
i2c_set_clientdata(client, indio_dev);
/* Power up the device */
ret = bh1780_write(bh1780, BH1780_REG_CONTROL, BH1780_PON);
if (ret < 0)
return ret;
msleep(BH1780_PON_DELAY);
pm_runtime_get_noresume(&client->dev);
pm_runtime_set_active(&client->dev);
pm_runtime_enable(&client->dev);
ret = bh1780_read(bh1780, BH1780_REG_PARTID);
if (ret < 0)
goto out_disable_pm;
dev_info(&client->dev,
"Ambient Light Sensor, Rev : %lu\n",
(ret & BH1780_REVMASK));
/*
* As the device takes 250 ms to even come up with a fresh
* measurement after power-on, do not shut it down unnecessarily.
* Set autosuspend to a five seconds.
*/
pm_runtime_set_autosuspend_delay(&client->dev, 5000);
pm_runtime_use_autosuspend(&client->dev);
pm_runtime_put(&client->dev);
indio_dev->info = &bh1780_info;
indio_dev->name = "bh1780";
indio_dev->channels = bh1780_channels;
indio_dev->num_channels = ARRAY_SIZE(bh1780_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(indio_dev);
if (ret)
goto out_disable_pm;
return 0;
out_disable_pm:
pm_runtime_put_noidle(&client->dev);
pm_runtime_disable(&client->dev);
return ret;
}
static void bh1780_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct bh1780_data *bh1780 = iio_priv(indio_dev);
int ret;
iio_device_unregister(indio_dev);
pm_runtime_get_sync(&client->dev);
pm_runtime_put_noidle(&client->dev);
pm_runtime_disable(&client->dev);
ret = bh1780_write(bh1780, BH1780_REG_CONTROL, BH1780_POFF);
if (ret < 0)
dev_err(&client->dev, "failed to power off (%pe)\n",
ERR_PTR(ret));
}
static int bh1780_runtime_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct bh1780_data *bh1780 = iio_priv(indio_dev);
int ret;
ret = bh1780_write(bh1780, BH1780_REG_CONTROL, BH1780_POFF);
if (ret < 0) {
dev_err(dev, "failed to runtime suspend\n");
return ret;
}
return 0;
}
static int bh1780_runtime_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct bh1780_data *bh1780 = iio_priv(indio_dev);
int ret;
ret = bh1780_write(bh1780, BH1780_REG_CONTROL, BH1780_PON);
if (ret < 0) {
dev_err(dev, "failed to runtime resume\n");
return ret;
}
/* Wait for power on, then for a value to be available */
msleep(BH1780_PON_DELAY + BH1780_INTERVAL);
return 0;
}
static DEFINE_RUNTIME_DEV_PM_OPS(bh1780_dev_pm_ops, bh1780_runtime_suspend,
bh1780_runtime_resume, NULL);
static const struct i2c_device_id bh1780_id[] = {
{ "bh1780", 0 },
{ },
};
MODULE_DEVICE_TABLE(i2c, bh1780_id);
static const struct of_device_id of_bh1780_match[] = {
{ .compatible = "rohm,bh1780gli", },
{},
};
MODULE_DEVICE_TABLE(of, of_bh1780_match);
static struct i2c_driver bh1780_driver = {
.probe = bh1780_probe,
.remove = bh1780_remove,
.id_table = bh1780_id,
.driver = {
.name = "bh1780",
.pm = pm_ptr(&bh1780_dev_pm_ops),
.of_match_table = of_bh1780_match,
},
};
module_i2c_driver(bh1780_driver);
MODULE_DESCRIPTION("ROHM BH1780GLI Ambient Light Sensor Driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Linus Walleij <[email protected]>");
| linux-master | drivers/iio/light/bh1780.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
* Author: Beomho Seo <[email protected]>
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
/* Slave address 0x19 for PS of 7 bit addressing protocol for I2C */
#define CM36651_I2C_ADDR_PS 0x19
/* Alert Response Address */
#define CM36651_ARA 0x0C
/* Ambient light sensor */
#define CM36651_CS_CONF1 0x00
#define CM36651_CS_CONF2 0x01
#define CM36651_ALS_WH_M 0x02
#define CM36651_ALS_WH_L 0x03
#define CM36651_ALS_WL_M 0x04
#define CM36651_ALS_WL_L 0x05
#define CM36651_CS_CONF3 0x06
#define CM36651_CS_CONF_REG_NUM 0x02
/* Proximity sensor */
#define CM36651_PS_CONF1 0x00
#define CM36651_PS_THD 0x01
#define CM36651_PS_CANC 0x02
#define CM36651_PS_CONF2 0x03
#define CM36651_PS_REG_NUM 0x04
/* CS_CONF1 command code */
#define CM36651_ALS_ENABLE 0x00
#define CM36651_ALS_DISABLE 0x01
#define CM36651_ALS_INT_EN 0x02
#define CM36651_ALS_THRES 0x04
/* CS_CONF2 command code */
#define CM36651_CS_CONF2_DEFAULT_BIT 0x08
/* CS_CONF3 channel integration time */
#define CM36651_CS_IT1 0x00 /* Integration time 80 msec */
#define CM36651_CS_IT2 0x40 /* Integration time 160 msec */
#define CM36651_CS_IT3 0x80 /* Integration time 320 msec */
#define CM36651_CS_IT4 0xC0 /* Integration time 640 msec */
/* PS_CONF1 command code */
#define CM36651_PS_ENABLE 0x00
#define CM36651_PS_DISABLE 0x01
#define CM36651_PS_INT_EN 0x02
#define CM36651_PS_PERS2 0x04
#define CM36651_PS_PERS3 0x08
#define CM36651_PS_PERS4 0x0C
/* PS_CONF1 command code: integration time */
#define CM36651_PS_IT1 0x00 /* Integration time 0.32 msec */
#define CM36651_PS_IT2 0x10 /* Integration time 0.42 msec */
#define CM36651_PS_IT3 0x20 /* Integration time 0.52 msec */
#define CM36651_PS_IT4 0x30 /* Integration time 0.64 msec */
/* PS_CONF1 command code: duty ratio */
#define CM36651_PS_DR1 0x00 /* Duty ratio 1/80 */
#define CM36651_PS_DR2 0x40 /* Duty ratio 1/160 */
#define CM36651_PS_DR3 0x80 /* Duty ratio 1/320 */
#define CM36651_PS_DR4 0xC0 /* Duty ratio 1/640 */
/* PS_THD command code */
#define CM36651_PS_INITIAL_THD 0x05
/* PS_CANC command code */
#define CM36651_PS_CANC_DEFAULT 0x00
/* PS_CONF2 command code */
#define CM36651_PS_HYS1 0x00
#define CM36651_PS_HYS2 0x01
#define CM36651_PS_SMART_PERS_EN 0x02
#define CM36651_PS_DIR_INT 0x04
#define CM36651_PS_MS 0x10
#define CM36651_CS_COLOR_NUM 4
#define CM36651_CLOSE_PROXIMITY 0x32
#define CM36651_FAR_PROXIMITY 0x33
#define CM36651_CS_INT_TIME_AVAIL "0.08 0.16 0.32 0.64"
#define CM36651_PS_INT_TIME_AVAIL "0.000320 0.000420 0.000520 0.000640"
enum cm36651_operation_mode {
CM36651_LIGHT_EN,
CM36651_PROXIMITY_EN,
CM36651_PROXIMITY_EV_EN,
};
enum cm36651_light_channel_idx {
CM36651_LIGHT_CHANNEL_IDX_RED,
CM36651_LIGHT_CHANNEL_IDX_GREEN,
CM36651_LIGHT_CHANNEL_IDX_BLUE,
CM36651_LIGHT_CHANNEL_IDX_CLEAR,
};
enum cm36651_command {
CM36651_CMD_READ_RAW_LIGHT,
CM36651_CMD_READ_RAW_PROXIMITY,
CM36651_CMD_PROX_EV_EN,
CM36651_CMD_PROX_EV_DIS,
};
static const u8 cm36651_cs_reg[CM36651_CS_CONF_REG_NUM] = {
CM36651_CS_CONF1,
CM36651_CS_CONF2,
};
static const u8 cm36651_ps_reg[CM36651_PS_REG_NUM] = {
CM36651_PS_CONF1,
CM36651_PS_THD,
CM36651_PS_CANC,
CM36651_PS_CONF2,
};
struct cm36651_data {
const struct cm36651_platform_data *pdata;
struct i2c_client *client;
struct i2c_client *ps_client;
struct i2c_client *ara_client;
struct mutex lock;
struct regulator *vled_reg;
unsigned long flags;
int cs_int_time[CM36651_CS_COLOR_NUM];
int ps_int_time;
u8 cs_ctrl_regs[CM36651_CS_CONF_REG_NUM];
u8 ps_ctrl_regs[CM36651_PS_REG_NUM];
u16 color[CM36651_CS_COLOR_NUM];
};
static int cm36651_setup_reg(struct cm36651_data *cm36651)
{
struct i2c_client *client = cm36651->client;
struct i2c_client *ps_client = cm36651->ps_client;
int i, ret;
/* CS initialization */
cm36651->cs_ctrl_regs[CM36651_CS_CONF1] = CM36651_ALS_ENABLE |
CM36651_ALS_THRES;
cm36651->cs_ctrl_regs[CM36651_CS_CONF2] = CM36651_CS_CONF2_DEFAULT_BIT;
for (i = 0; i < CM36651_CS_CONF_REG_NUM; i++) {
ret = i2c_smbus_write_byte_data(client, cm36651_cs_reg[i],
cm36651->cs_ctrl_regs[i]);
if (ret < 0)
return ret;
}
/* PS initialization */
cm36651->ps_ctrl_regs[CM36651_PS_CONF1] = CM36651_PS_ENABLE |
CM36651_PS_IT2;
cm36651->ps_ctrl_regs[CM36651_PS_THD] = CM36651_PS_INITIAL_THD;
cm36651->ps_ctrl_regs[CM36651_PS_CANC] = CM36651_PS_CANC_DEFAULT;
cm36651->ps_ctrl_regs[CM36651_PS_CONF2] = CM36651_PS_HYS2 |
CM36651_PS_DIR_INT | CM36651_PS_SMART_PERS_EN;
for (i = 0; i < CM36651_PS_REG_NUM; i++) {
ret = i2c_smbus_write_byte_data(ps_client, cm36651_ps_reg[i],
cm36651->ps_ctrl_regs[i]);
if (ret < 0)
return ret;
}
/* Set shutdown mode */
ret = i2c_smbus_write_byte_data(client, CM36651_CS_CONF1,
CM36651_ALS_DISABLE);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(cm36651->ps_client,
CM36651_PS_CONF1, CM36651_PS_DISABLE);
if (ret < 0)
return ret;
return 0;
}
static int cm36651_read_output(struct cm36651_data *cm36651,
struct iio_chan_spec const *chan, int *val)
{
struct i2c_client *client = cm36651->client;
int ret = -EINVAL;
switch (chan->type) {
case IIO_LIGHT:
*val = i2c_smbus_read_word_data(client, chan->address);
if (*val < 0)
return ret;
ret = i2c_smbus_write_byte_data(client, CM36651_CS_CONF1,
CM36651_ALS_DISABLE);
if (ret < 0)
return ret;
ret = IIO_VAL_INT;
break;
case IIO_PROXIMITY:
*val = i2c_smbus_read_byte(cm36651->ps_client);
if (*val < 0)
return ret;
if (!test_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags)) {
ret = i2c_smbus_write_byte_data(cm36651->ps_client,
CM36651_PS_CONF1, CM36651_PS_DISABLE);
if (ret < 0)
return ret;
}
ret = IIO_VAL_INT;
break;
default:
break;
}
return ret;
}
static irqreturn_t cm36651_irq_handler(int irq, void *data)
{
struct iio_dev *indio_dev = data;
struct cm36651_data *cm36651 = iio_priv(indio_dev);
struct i2c_client *client = cm36651->client;
int ev_dir, ret;
u64 ev_code;
/*
* The PS INT pin is an active low signal that PS INT move logic low
* when the object is detect. Once the MCU host received the PS INT
* "LOW" signal, the Host needs to read the data at Alert Response
* Address(ARA) to clear the PS INT signal. After clearing the PS
* INT pin, the PS INT signal toggles from low to high.
*/
ret = i2c_smbus_read_byte(cm36651->ara_client);
if (ret < 0) {
dev_err(&client->dev,
"%s: Data read failed: %d\n", __func__, ret);
return IRQ_HANDLED;
}
switch (ret) {
case CM36651_CLOSE_PROXIMITY:
ev_dir = IIO_EV_DIR_RISING;
break;
case CM36651_FAR_PROXIMITY:
ev_dir = IIO_EV_DIR_FALLING;
break;
default:
dev_err(&client->dev,
"%s: Data read wrong: %d\n", __func__, ret);
return IRQ_HANDLED;
}
ev_code = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY,
CM36651_CMD_READ_RAW_PROXIMITY,
IIO_EV_TYPE_THRESH, ev_dir);
iio_push_event(indio_dev, ev_code, iio_get_time_ns(indio_dev));
return IRQ_HANDLED;
}
static int cm36651_set_operation_mode(struct cm36651_data *cm36651, int cmd)
{
struct i2c_client *client = cm36651->client;
struct i2c_client *ps_client = cm36651->ps_client;
int ret = -EINVAL;
switch (cmd) {
case CM36651_CMD_READ_RAW_LIGHT:
ret = i2c_smbus_write_byte_data(client, CM36651_CS_CONF1,
cm36651->cs_ctrl_regs[CM36651_CS_CONF1]);
break;
case CM36651_CMD_READ_RAW_PROXIMITY:
if (test_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags))
return CM36651_PROXIMITY_EV_EN;
ret = i2c_smbus_write_byte_data(ps_client, CM36651_PS_CONF1,
cm36651->ps_ctrl_regs[CM36651_PS_CONF1]);
break;
case CM36651_CMD_PROX_EV_EN:
if (test_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags)) {
dev_err(&client->dev,
"Already proximity event enable state\n");
return ret;
}
set_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags);
ret = i2c_smbus_write_byte_data(ps_client,
cm36651_ps_reg[CM36651_PS_CONF1],
CM36651_PS_INT_EN | CM36651_PS_PERS2 | CM36651_PS_IT2);
if (ret < 0) {
dev_err(&client->dev, "Proximity enable event failed\n");
return ret;
}
break;
case CM36651_CMD_PROX_EV_DIS:
if (!test_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags)) {
dev_err(&client->dev,
"Already proximity event disable state\n");
return ret;
}
clear_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags);
ret = i2c_smbus_write_byte_data(ps_client,
CM36651_PS_CONF1, CM36651_PS_DISABLE);
break;
}
if (ret < 0)
dev_err(&client->dev, "Write register failed\n");
return ret;
}
static int cm36651_read_channel(struct cm36651_data *cm36651,
struct iio_chan_spec const *chan, int *val)
{
struct i2c_client *client = cm36651->client;
int cmd, ret;
if (chan->type == IIO_LIGHT)
cmd = CM36651_CMD_READ_RAW_LIGHT;
else if (chan->type == IIO_PROXIMITY)
cmd = CM36651_CMD_READ_RAW_PROXIMITY;
else
return -EINVAL;
ret = cm36651_set_operation_mode(cm36651, cmd);
if (ret < 0) {
dev_err(&client->dev, "CM36651 set operation mode failed\n");
return ret;
}
/* Delay for work after enable operation */
msleep(50);
ret = cm36651_read_output(cm36651, chan, val);
if (ret < 0) {
dev_err(&client->dev, "CM36651 read output failed\n");
return ret;
}
return ret;
}
static int cm36651_read_int_time(struct cm36651_data *cm36651,
struct iio_chan_spec const *chan, int *val2)
{
switch (chan->type) {
case IIO_LIGHT:
if (cm36651->cs_int_time[chan->address] == CM36651_CS_IT1)
*val2 = 80000;
else if (cm36651->cs_int_time[chan->address] == CM36651_CS_IT2)
*val2 = 160000;
else if (cm36651->cs_int_time[chan->address] == CM36651_CS_IT3)
*val2 = 320000;
else if (cm36651->cs_int_time[chan->address] == CM36651_CS_IT4)
*val2 = 640000;
else
return -EINVAL;
break;
case IIO_PROXIMITY:
if (cm36651->ps_int_time == CM36651_PS_IT1)
*val2 = 320;
else if (cm36651->ps_int_time == CM36651_PS_IT2)
*val2 = 420;
else if (cm36651->ps_int_time == CM36651_PS_IT3)
*val2 = 520;
else if (cm36651->ps_int_time == CM36651_PS_IT4)
*val2 = 640;
else
return -EINVAL;
break;
default:
return -EINVAL;
}
return IIO_VAL_INT_PLUS_MICRO;
}
static int cm36651_write_int_time(struct cm36651_data *cm36651,
struct iio_chan_spec const *chan, int val)
{
struct i2c_client *client = cm36651->client;
struct i2c_client *ps_client = cm36651->ps_client;
int int_time, ret;
switch (chan->type) {
case IIO_LIGHT:
if (val == 80000)
int_time = CM36651_CS_IT1;
else if (val == 160000)
int_time = CM36651_CS_IT2;
else if (val == 320000)
int_time = CM36651_CS_IT3;
else if (val == 640000)
int_time = CM36651_CS_IT4;
else
return -EINVAL;
ret = i2c_smbus_write_byte_data(client, CM36651_CS_CONF3,
int_time >> 2 * (chan->address));
if (ret < 0) {
dev_err(&client->dev, "CS integration time write failed\n");
return ret;
}
cm36651->cs_int_time[chan->address] = int_time;
break;
case IIO_PROXIMITY:
if (val == 320)
int_time = CM36651_PS_IT1;
else if (val == 420)
int_time = CM36651_PS_IT2;
else if (val == 520)
int_time = CM36651_PS_IT3;
else if (val == 640)
int_time = CM36651_PS_IT4;
else
return -EINVAL;
ret = i2c_smbus_write_byte_data(ps_client,
CM36651_PS_CONF1, int_time);
if (ret < 0) {
dev_err(&client->dev, "PS integration time write failed\n");
return ret;
}
cm36651->ps_int_time = int_time;
break;
default:
return -EINVAL;
}
return ret;
}
static int cm36651_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct cm36651_data *cm36651 = iio_priv(indio_dev);
int ret;
mutex_lock(&cm36651->lock);
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = cm36651_read_channel(cm36651, chan, val);
break;
case IIO_CHAN_INFO_INT_TIME:
*val = 0;
ret = cm36651_read_int_time(cm36651, chan, val2);
break;
default:
ret = -EINVAL;
}
mutex_unlock(&cm36651->lock);
return ret;
}
static int cm36651_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct cm36651_data *cm36651 = iio_priv(indio_dev);
struct i2c_client *client = cm36651->client;
int ret = -EINVAL;
if (mask == IIO_CHAN_INFO_INT_TIME) {
ret = cm36651_write_int_time(cm36651, chan, val2);
if (ret < 0)
dev_err(&client->dev, "Integration time write failed\n");
}
return ret;
}
static int cm36651_read_prox_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
struct cm36651_data *cm36651 = iio_priv(indio_dev);
*val = cm36651->ps_ctrl_regs[CM36651_PS_THD];
return 0;
}
static int cm36651_write_prox_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
struct cm36651_data *cm36651 = iio_priv(indio_dev);
struct i2c_client *client = cm36651->client;
int ret;
if (val < 3 || val > 255)
return -EINVAL;
cm36651->ps_ctrl_regs[CM36651_PS_THD] = val;
ret = i2c_smbus_write_byte_data(cm36651->ps_client, CM36651_PS_THD,
cm36651->ps_ctrl_regs[CM36651_PS_THD]);
if (ret < 0) {
dev_err(&client->dev, "PS threshold write failed: %d\n", ret);
return ret;
}
return 0;
}
static int cm36651_write_prox_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
struct cm36651_data *cm36651 = iio_priv(indio_dev);
int cmd, ret;
mutex_lock(&cm36651->lock);
cmd = state ? CM36651_CMD_PROX_EV_EN : CM36651_CMD_PROX_EV_DIS;
ret = cm36651_set_operation_mode(cm36651, cmd);
mutex_unlock(&cm36651->lock);
return ret;
}
static int cm36651_read_prox_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct cm36651_data *cm36651 = iio_priv(indio_dev);
int event_en;
mutex_lock(&cm36651->lock);
event_en = test_bit(CM36651_PROXIMITY_EV_EN, &cm36651->flags);
mutex_unlock(&cm36651->lock);
return event_en;
}
#define CM36651_LIGHT_CHANNEL(_color, _idx) { \
.type = IIO_LIGHT, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_INT_TIME), \
.address = _idx, \
.modified = 1, \
.channel2 = IIO_MOD_LIGHT_##_color, \
} \
static const struct iio_event_spec cm36651_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
}
};
static const struct iio_chan_spec cm36651_channels[] = {
{
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_INT_TIME),
.event_spec = cm36651_event_spec,
.num_event_specs = ARRAY_SIZE(cm36651_event_spec),
},
CM36651_LIGHT_CHANNEL(RED, CM36651_LIGHT_CHANNEL_IDX_RED),
CM36651_LIGHT_CHANNEL(GREEN, CM36651_LIGHT_CHANNEL_IDX_GREEN),
CM36651_LIGHT_CHANNEL(BLUE, CM36651_LIGHT_CHANNEL_IDX_BLUE),
CM36651_LIGHT_CHANNEL(CLEAR, CM36651_LIGHT_CHANNEL_IDX_CLEAR),
};
static IIO_CONST_ATTR(in_illuminance_integration_time_available,
CM36651_CS_INT_TIME_AVAIL);
static IIO_CONST_ATTR(in_proximity_integration_time_available,
CM36651_PS_INT_TIME_AVAIL);
static struct attribute *cm36651_attributes[] = {
&iio_const_attr_in_illuminance_integration_time_available.dev_attr.attr,
&iio_const_attr_in_proximity_integration_time_available.dev_attr.attr,
NULL,
};
static const struct attribute_group cm36651_attribute_group = {
.attrs = cm36651_attributes
};
static const struct iio_info cm36651_info = {
.read_raw = &cm36651_read_raw,
.write_raw = &cm36651_write_raw,
.read_event_value = &cm36651_read_prox_thresh,
.write_event_value = &cm36651_write_prox_thresh,
.read_event_config = &cm36651_read_prox_event_config,
.write_event_config = &cm36651_write_prox_event_config,
.attrs = &cm36651_attribute_group,
};
static int cm36651_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct cm36651_data *cm36651;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*cm36651));
if (!indio_dev)
return -ENOMEM;
cm36651 = iio_priv(indio_dev);
cm36651->vled_reg = devm_regulator_get(&client->dev, "vled");
if (IS_ERR(cm36651->vled_reg))
return dev_err_probe(&client->dev, PTR_ERR(cm36651->vled_reg),
"get regulator vled failed\n");
ret = regulator_enable(cm36651->vled_reg);
if (ret) {
dev_err(&client->dev, "enable regulator vled failed\n");
return ret;
}
i2c_set_clientdata(client, indio_dev);
cm36651->client = client;
cm36651->ps_client = i2c_new_dummy_device(client->adapter,
CM36651_I2C_ADDR_PS);
if (IS_ERR(cm36651->ps_client)) {
dev_err(&client->dev, "%s: new i2c device failed\n", __func__);
ret = PTR_ERR(cm36651->ps_client);
goto error_disable_reg;
}
cm36651->ara_client = i2c_new_dummy_device(client->adapter, CM36651_ARA);
if (IS_ERR(cm36651->ara_client)) {
dev_err(&client->dev, "%s: new i2c device failed\n", __func__);
ret = PTR_ERR(cm36651->ara_client);
goto error_i2c_unregister_ps;
}
mutex_init(&cm36651->lock);
indio_dev->channels = cm36651_channels;
indio_dev->num_channels = ARRAY_SIZE(cm36651_channels);
indio_dev->info = &cm36651_info;
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = cm36651_setup_reg(cm36651);
if (ret) {
dev_err(&client->dev, "%s: register setup failed\n", __func__);
goto error_i2c_unregister_ara;
}
ret = request_threaded_irq(client->irq, NULL, cm36651_irq_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"cm36651", indio_dev);
if (ret) {
dev_err(&client->dev, "%s: request irq failed\n", __func__);
goto error_i2c_unregister_ara;
}
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&client->dev, "%s: regist device failed\n", __func__);
goto error_free_irq;
}
return 0;
error_free_irq:
free_irq(client->irq, indio_dev);
error_i2c_unregister_ara:
i2c_unregister_device(cm36651->ara_client);
error_i2c_unregister_ps:
i2c_unregister_device(cm36651->ps_client);
error_disable_reg:
regulator_disable(cm36651->vled_reg);
return ret;
}
static void cm36651_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct cm36651_data *cm36651 = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
regulator_disable(cm36651->vled_reg);
free_irq(client->irq, indio_dev);
i2c_unregister_device(cm36651->ps_client);
i2c_unregister_device(cm36651->ara_client);
}
static const struct i2c_device_id cm36651_id[] = {
{ "cm36651", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, cm36651_id);
static const struct of_device_id cm36651_of_match[] = {
{ .compatible = "capella,cm36651" },
{ }
};
MODULE_DEVICE_TABLE(of, cm36651_of_match);
static struct i2c_driver cm36651_driver = {
.driver = {
.name = "cm36651",
.of_match_table = cm36651_of_match,
},
.probe = cm36651_probe,
.remove = cm36651_remove,
.id_table = cm36651_id,
};
module_i2c_driver(cm36651_driver);
MODULE_AUTHOR("Beomho Seo <[email protected]>");
MODULE_DESCRIPTION("CM36651 proximity/ambient light sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/cm36651.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* CM3323 - Capella Color Light Sensor
*
* Copyright (c) 2015, Intel Corporation.
*
* IIO driver for CM3323 (7-bit I2C slave address 0x10)
*
* TODO: calibscale to correct the lens factor
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define CM3323_DRV_NAME "cm3323"
#define CM3323_CMD_CONF 0x00
#define CM3323_CMD_RED_DATA 0x08
#define CM3323_CMD_GREEN_DATA 0x09
#define CM3323_CMD_BLUE_DATA 0x0A
#define CM3323_CMD_CLEAR_DATA 0x0B
#define CM3323_CONF_SD_BIT BIT(0) /* sensor disable */
#define CM3323_CONF_AF_BIT BIT(1) /* auto/manual force mode */
#define CM3323_CONF_IT_MASK GENMASK(6, 4)
#define CM3323_CONF_IT_SHIFT 4
#define CM3323_INT_TIME_AVAILABLE "0.04 0.08 0.16 0.32 0.64 1.28"
static const struct {
int val;
int val2;
} cm3323_int_time[] = {
{0, 40000}, /* 40 ms */
{0, 80000}, /* 80 ms */
{0, 160000}, /* 160 ms */
{0, 320000}, /* 320 ms */
{0, 640000}, /* 640 ms */
{1, 280000}, /* 1280 ms */
};
struct cm3323_data {
struct i2c_client *client;
u16 reg_conf;
struct mutex mutex;
};
#define CM3323_COLOR_CHANNEL(_color, _addr) { \
.type = IIO_INTENSITY, \
.modified = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME), \
.channel2 = IIO_MOD_LIGHT_##_color, \
.address = _addr, \
}
static const struct iio_chan_spec cm3323_channels[] = {
CM3323_COLOR_CHANNEL(RED, CM3323_CMD_RED_DATA),
CM3323_COLOR_CHANNEL(GREEN, CM3323_CMD_GREEN_DATA),
CM3323_COLOR_CHANNEL(BLUE, CM3323_CMD_BLUE_DATA),
CM3323_COLOR_CHANNEL(CLEAR, CM3323_CMD_CLEAR_DATA),
};
static IIO_CONST_ATTR_INT_TIME_AVAIL(CM3323_INT_TIME_AVAILABLE);
static struct attribute *cm3323_attributes[] = {
&iio_const_attr_integration_time_available.dev_attr.attr,
NULL
};
static const struct attribute_group cm3323_attribute_group = {
.attrs = cm3323_attributes,
};
static int cm3323_init(struct iio_dev *indio_dev)
{
int ret;
struct cm3323_data *data = iio_priv(indio_dev);
ret = i2c_smbus_read_word_data(data->client, CM3323_CMD_CONF);
if (ret < 0) {
dev_err(&data->client->dev, "Error reading reg_conf\n");
return ret;
}
/* enable sensor and set auto force mode */
ret &= ~(CM3323_CONF_SD_BIT | CM3323_CONF_AF_BIT);
ret = i2c_smbus_write_word_data(data->client, CM3323_CMD_CONF, ret);
if (ret < 0) {
dev_err(&data->client->dev, "Error writing reg_conf\n");
return ret;
}
data->reg_conf = ret;
return 0;
}
static void cm3323_disable(void *data)
{
int ret;
struct iio_dev *indio_dev = data;
struct cm3323_data *cm_data = iio_priv(indio_dev);
ret = i2c_smbus_write_word_data(cm_data->client, CM3323_CMD_CONF,
CM3323_CONF_SD_BIT);
if (ret < 0)
dev_err(&cm_data->client->dev, "Error writing reg_conf\n");
}
static int cm3323_set_it_bits(struct cm3323_data *data, int val, int val2)
{
int i, ret;
u16 reg_conf;
for (i = 0; i < ARRAY_SIZE(cm3323_int_time); i++) {
if (val == cm3323_int_time[i].val &&
val2 == cm3323_int_time[i].val2) {
reg_conf = data->reg_conf & ~CM3323_CONF_IT_MASK;
reg_conf |= i << CM3323_CONF_IT_SHIFT;
ret = i2c_smbus_write_word_data(data->client,
CM3323_CMD_CONF,
reg_conf);
if (ret < 0)
return ret;
data->reg_conf = reg_conf;
return 0;
}
}
return -EINVAL;
}
static int cm3323_get_it_bits(struct cm3323_data *data)
{
int bits;
bits = (data->reg_conf & CM3323_CONF_IT_MASK) >>
CM3323_CONF_IT_SHIFT;
if (bits >= ARRAY_SIZE(cm3323_int_time))
return -EINVAL;
return bits;
}
static int cm3323_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
int ret;
struct cm3323_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&data->mutex);
ret = i2c_smbus_read_word_data(data->client, chan->address);
if (ret < 0) {
mutex_unlock(&data->mutex);
return ret;
}
*val = ret;
mutex_unlock(&data->mutex);
return IIO_VAL_INT;
case IIO_CHAN_INFO_INT_TIME:
mutex_lock(&data->mutex);
ret = cm3323_get_it_bits(data);
if (ret < 0) {
mutex_unlock(&data->mutex);
return ret;
}
*val = cm3323_int_time[ret].val;
*val2 = cm3323_int_time[ret].val2;
mutex_unlock(&data->mutex);
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int cm3323_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct cm3323_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
mutex_lock(&data->mutex);
ret = cm3323_set_it_bits(data, val, val2);
mutex_unlock(&data->mutex);
return ret;
default:
return -EINVAL;
}
}
static const struct iio_info cm3323_info = {
.read_raw = cm3323_read_raw,
.write_raw = cm3323_write_raw,
.attrs = &cm3323_attribute_group,
};
static int cm3323_probe(struct i2c_client *client)
{
struct cm3323_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
mutex_init(&data->mutex);
indio_dev->info = &cm3323_info;
indio_dev->name = CM3323_DRV_NAME;
indio_dev->channels = cm3323_channels;
indio_dev->num_channels = ARRAY_SIZE(cm3323_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = cm3323_init(indio_dev);
if (ret < 0) {
dev_err(&client->dev, "cm3323 chip init failed\n");
return ret;
}
ret = devm_add_action_or_reset(&client->dev, cm3323_disable, indio_dev);
if (ret < 0)
return ret;
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id cm3323_id[] = {
{"cm3323", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cm3323_id);
static const struct of_device_id cm3323_of_match[] = {
{ .compatible = "capella,cm3323", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, cm3323_of_match);
static struct i2c_driver cm3323_driver = {
.driver = {
.name = CM3323_DRV_NAME,
.of_match_table = cm3323_of_match,
},
.probe = cm3323_probe,
.id_table = cm3323_id,
};
module_i2c_driver(cm3323_driver);
MODULE_AUTHOR("Daniel Baluta <[email protected]>");
MODULE_DESCRIPTION("Capella CM3323 Color Light Sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/cm3323.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* lv0104cs.c: LV0104CS Ambient Light Sensor Driver
*
* Copyright (C) 2018
* Author: Jeff LaBundy <[email protected]>
*
* 7-bit I2C slave address: 0x13
*
* Link to data sheet: https://www.onsemi.com/pub/Collateral/LV0104CS-D.PDF
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define LV0104CS_REGVAL_MEASURE 0xE0
#define LV0104CS_REGVAL_SLEEP 0x00
#define LV0104CS_SCALE_0_25X 0
#define LV0104CS_SCALE_1X 1
#define LV0104CS_SCALE_2X 2
#define LV0104CS_SCALE_8X 3
#define LV0104CS_SCALE_SHIFT 3
#define LV0104CS_INTEG_12_5MS 0
#define LV0104CS_INTEG_100MS 1
#define LV0104CS_INTEG_200MS 2
#define LV0104CS_INTEG_SHIFT 1
#define LV0104CS_CALIBSCALE_UNITY 31
struct lv0104cs_private {
struct i2c_client *client;
struct mutex lock;
u8 calibscale;
u8 scale;
u8 int_time;
};
struct lv0104cs_mapping {
int val;
int val2;
u8 regval;
};
static const struct lv0104cs_mapping lv0104cs_calibscales[] = {
{ 0, 666666, 0x81 },
{ 0, 800000, 0x82 },
{ 0, 857142, 0x83 },
{ 0, 888888, 0x84 },
{ 0, 909090, 0x85 },
{ 0, 923076, 0x86 },
{ 0, 933333, 0x87 },
{ 0, 941176, 0x88 },
{ 0, 947368, 0x89 },
{ 0, 952380, 0x8A },
{ 0, 956521, 0x8B },
{ 0, 960000, 0x8C },
{ 0, 962962, 0x8D },
{ 0, 965517, 0x8E },
{ 0, 967741, 0x8F },
{ 0, 969696, 0x90 },
{ 0, 971428, 0x91 },
{ 0, 972972, 0x92 },
{ 0, 974358, 0x93 },
{ 0, 975609, 0x94 },
{ 0, 976744, 0x95 },
{ 0, 977777, 0x96 },
{ 0, 978723, 0x97 },
{ 0, 979591, 0x98 },
{ 0, 980392, 0x99 },
{ 0, 981132, 0x9A },
{ 0, 981818, 0x9B },
{ 0, 982456, 0x9C },
{ 0, 983050, 0x9D },
{ 0, 983606, 0x9E },
{ 0, 984126, 0x9F },
{ 1, 0, 0x80 },
{ 1, 16129, 0xBF },
{ 1, 16666, 0xBE },
{ 1, 17241, 0xBD },
{ 1, 17857, 0xBC },
{ 1, 18518, 0xBB },
{ 1, 19230, 0xBA },
{ 1, 20000, 0xB9 },
{ 1, 20833, 0xB8 },
{ 1, 21739, 0xB7 },
{ 1, 22727, 0xB6 },
{ 1, 23809, 0xB5 },
{ 1, 24999, 0xB4 },
{ 1, 26315, 0xB3 },
{ 1, 27777, 0xB2 },
{ 1, 29411, 0xB1 },
{ 1, 31250, 0xB0 },
{ 1, 33333, 0xAF },
{ 1, 35714, 0xAE },
{ 1, 38461, 0xAD },
{ 1, 41666, 0xAC },
{ 1, 45454, 0xAB },
{ 1, 50000, 0xAA },
{ 1, 55555, 0xA9 },
{ 1, 62500, 0xA8 },
{ 1, 71428, 0xA7 },
{ 1, 83333, 0xA6 },
{ 1, 100000, 0xA5 },
{ 1, 125000, 0xA4 },
{ 1, 166666, 0xA3 },
{ 1, 250000, 0xA2 },
{ 1, 500000, 0xA1 },
};
static const struct lv0104cs_mapping lv0104cs_scales[] = {
{ 0, 250000, LV0104CS_SCALE_0_25X << LV0104CS_SCALE_SHIFT },
{ 1, 0, LV0104CS_SCALE_1X << LV0104CS_SCALE_SHIFT },
{ 2, 0, LV0104CS_SCALE_2X << LV0104CS_SCALE_SHIFT },
{ 8, 0, LV0104CS_SCALE_8X << LV0104CS_SCALE_SHIFT },
};
static const struct lv0104cs_mapping lv0104cs_int_times[] = {
{ 0, 12500, LV0104CS_INTEG_12_5MS << LV0104CS_INTEG_SHIFT },
{ 0, 100000, LV0104CS_INTEG_100MS << LV0104CS_INTEG_SHIFT },
{ 0, 200000, LV0104CS_INTEG_200MS << LV0104CS_INTEG_SHIFT },
};
static int lv0104cs_write_reg(struct i2c_client *client, u8 regval)
{
int ret;
ret = i2c_master_send(client, (char *)®val, sizeof(regval));
if (ret < 0)
return ret;
if (ret != sizeof(regval))
return -EIO;
return 0;
}
static int lv0104cs_read_adc(struct i2c_client *client, u16 *adc_output)
{
__be16 regval;
int ret;
ret = i2c_master_recv(client, (char *)®val, sizeof(regval));
if (ret < 0)
return ret;
if (ret != sizeof(regval))
return -EIO;
*adc_output = be16_to_cpu(regval);
return 0;
}
static int lv0104cs_get_lux(struct lv0104cs_private *lv0104cs,
int *val, int *val2)
{
u8 regval = LV0104CS_REGVAL_MEASURE;
u16 adc_output;
int ret;
regval |= lv0104cs_scales[lv0104cs->scale].regval;
regval |= lv0104cs_int_times[lv0104cs->int_time].regval;
ret = lv0104cs_write_reg(lv0104cs->client, regval);
if (ret)
return ret;
/* wait for integration time to pass (with margin) */
switch (lv0104cs->int_time) {
case LV0104CS_INTEG_12_5MS:
msleep(50);
break;
case LV0104CS_INTEG_100MS:
msleep(150);
break;
case LV0104CS_INTEG_200MS:
msleep(250);
break;
default:
return -EINVAL;
}
ret = lv0104cs_read_adc(lv0104cs->client, &adc_output);
if (ret)
return ret;
ret = lv0104cs_write_reg(lv0104cs->client, LV0104CS_REGVAL_SLEEP);
if (ret)
return ret;
/* convert ADC output to lux */
switch (lv0104cs->scale) {
case LV0104CS_SCALE_0_25X:
*val = adc_output * 4;
*val2 = 0;
return 0;
case LV0104CS_SCALE_1X:
*val = adc_output;
*val2 = 0;
return 0;
case LV0104CS_SCALE_2X:
*val = adc_output / 2;
*val2 = (adc_output % 2) * 500000;
return 0;
case LV0104CS_SCALE_8X:
*val = adc_output / 8;
*val2 = (adc_output % 8) * 125000;
return 0;
default:
return -EINVAL;
}
}
static int lv0104cs_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct lv0104cs_private *lv0104cs = iio_priv(indio_dev);
int ret;
if (chan->type != IIO_LIGHT)
return -EINVAL;
mutex_lock(&lv0104cs->lock);
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
ret = lv0104cs_get_lux(lv0104cs, val, val2);
if (ret)
goto err_mutex;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
case IIO_CHAN_INFO_CALIBSCALE:
*val = lv0104cs_calibscales[lv0104cs->calibscale].val;
*val2 = lv0104cs_calibscales[lv0104cs->calibscale].val2;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
case IIO_CHAN_INFO_SCALE:
*val = lv0104cs_scales[lv0104cs->scale].val;
*val2 = lv0104cs_scales[lv0104cs->scale].val2;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
case IIO_CHAN_INFO_INT_TIME:
*val = lv0104cs_int_times[lv0104cs->int_time].val;
*val2 = lv0104cs_int_times[lv0104cs->int_time].val2;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
ret = -EINVAL;
}
err_mutex:
mutex_unlock(&lv0104cs->lock);
return ret;
}
static int lv0104cs_set_calibscale(struct lv0104cs_private *lv0104cs,
int val, int val2)
{
int calibscale = val * 1000000 + val2;
int floor, ceil, mid;
int ret, i, index;
/* round to nearest quantized calibscale (sensitivity) */
for (i = 0; i < ARRAY_SIZE(lv0104cs_calibscales) - 1; i++) {
floor = lv0104cs_calibscales[i].val * 1000000
+ lv0104cs_calibscales[i].val2;
ceil = lv0104cs_calibscales[i + 1].val * 1000000
+ lv0104cs_calibscales[i + 1].val2;
mid = (floor + ceil) / 2;
/* round down */
if (calibscale >= floor && calibscale < mid) {
index = i;
break;
}
/* round up */
if (calibscale >= mid && calibscale <= ceil) {
index = i + 1;
break;
}
}
if (i == ARRAY_SIZE(lv0104cs_calibscales) - 1)
return -EINVAL;
mutex_lock(&lv0104cs->lock);
/* set calibscale (sensitivity) */
ret = lv0104cs_write_reg(lv0104cs->client,
lv0104cs_calibscales[index].regval);
if (ret)
goto err_mutex;
lv0104cs->calibscale = index;
err_mutex:
mutex_unlock(&lv0104cs->lock);
return ret;
}
static int lv0104cs_set_scale(struct lv0104cs_private *lv0104cs,
int val, int val2)
{
int i;
/* hard matching */
for (i = 0; i < ARRAY_SIZE(lv0104cs_scales); i++) {
if (val != lv0104cs_scales[i].val)
continue;
if (val2 == lv0104cs_scales[i].val2)
break;
}
if (i == ARRAY_SIZE(lv0104cs_scales))
return -EINVAL;
mutex_lock(&lv0104cs->lock);
lv0104cs->scale = i;
mutex_unlock(&lv0104cs->lock);
return 0;
}
static int lv0104cs_set_int_time(struct lv0104cs_private *lv0104cs,
int val, int val2)
{
int i;
/* hard matching */
for (i = 0; i < ARRAY_SIZE(lv0104cs_int_times); i++) {
if (val != lv0104cs_int_times[i].val)
continue;
if (val2 == lv0104cs_int_times[i].val2)
break;
}
if (i == ARRAY_SIZE(lv0104cs_int_times))
return -EINVAL;
mutex_lock(&lv0104cs->lock);
lv0104cs->int_time = i;
mutex_unlock(&lv0104cs->lock);
return 0;
}
static int lv0104cs_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct lv0104cs_private *lv0104cs = iio_priv(indio_dev);
if (chan->type != IIO_LIGHT)
return -EINVAL;
switch (mask) {
case IIO_CHAN_INFO_CALIBSCALE:
return lv0104cs_set_calibscale(lv0104cs, val, val2);
case IIO_CHAN_INFO_SCALE:
return lv0104cs_set_scale(lv0104cs, val, val2);
case IIO_CHAN_INFO_INT_TIME:
return lv0104cs_set_int_time(lv0104cs, val, val2);
default:
return -EINVAL;
}
}
static ssize_t lv0104cs_show_calibscale_avail(struct device *dev,
struct device_attribute *attr, char *buf)
{
ssize_t len = 0;
int i;
for (i = 0; i < ARRAY_SIZE(lv0104cs_calibscales); i++) {
len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
lv0104cs_calibscales[i].val,
lv0104cs_calibscales[i].val2);
}
buf[len - 1] = '\n';
return len;
}
static ssize_t lv0104cs_show_scale_avail(struct device *dev,
struct device_attribute *attr, char *buf)
{
ssize_t len = 0;
int i;
for (i = 0; i < ARRAY_SIZE(lv0104cs_scales); i++) {
len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
lv0104cs_scales[i].val,
lv0104cs_scales[i].val2);
}
buf[len - 1] = '\n';
return len;
}
static ssize_t lv0104cs_show_int_time_avail(struct device *dev,
struct device_attribute *attr, char *buf)
{
ssize_t len = 0;
int i;
for (i = 0; i < ARRAY_SIZE(lv0104cs_int_times); i++) {
len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
lv0104cs_int_times[i].val,
lv0104cs_int_times[i].val2);
}
buf[len - 1] = '\n';
return len;
}
static IIO_DEVICE_ATTR(calibscale_available, 0444,
lv0104cs_show_calibscale_avail, NULL, 0);
static IIO_DEVICE_ATTR(scale_available, 0444,
lv0104cs_show_scale_avail, NULL, 0);
static IIO_DEV_ATTR_INT_TIME_AVAIL(lv0104cs_show_int_time_avail);
static struct attribute *lv0104cs_attributes[] = {
&iio_dev_attr_calibscale_available.dev_attr.attr,
&iio_dev_attr_scale_available.dev_attr.attr,
&iio_dev_attr_integration_time_available.dev_attr.attr,
NULL
};
static const struct attribute_group lv0104cs_attribute_group = {
.attrs = lv0104cs_attributes,
};
static const struct iio_info lv0104cs_info = {
.attrs = &lv0104cs_attribute_group,
.read_raw = &lv0104cs_read_raw,
.write_raw = &lv0104cs_write_raw,
};
static const struct iio_chan_spec lv0104cs_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_INT_TIME),
},
};
static int lv0104cs_probe(struct i2c_client *client)
{
struct iio_dev *indio_dev;
struct lv0104cs_private *lv0104cs;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*lv0104cs));
if (!indio_dev)
return -ENOMEM;
lv0104cs = iio_priv(indio_dev);
i2c_set_clientdata(client, lv0104cs);
lv0104cs->client = client;
mutex_init(&lv0104cs->lock);
lv0104cs->calibscale = LV0104CS_CALIBSCALE_UNITY;
lv0104cs->scale = LV0104CS_SCALE_1X;
lv0104cs->int_time = LV0104CS_INTEG_200MS;
ret = lv0104cs_write_reg(lv0104cs->client,
lv0104cs_calibscales[LV0104CS_CALIBSCALE_UNITY].regval);
if (ret)
return ret;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = lv0104cs_channels;
indio_dev->num_channels = ARRAY_SIZE(lv0104cs_channels);
indio_dev->name = client->name;
indio_dev->info = &lv0104cs_info;
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id lv0104cs_id[] = {
{ "lv0104cs", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, lv0104cs_id);
static struct i2c_driver lv0104cs_i2c_driver = {
.driver = {
.name = "lv0104cs",
},
.id_table = lv0104cs_id,
.probe = lv0104cs_probe,
};
module_i2c_driver(lv0104cs_i2c_driver);
MODULE_AUTHOR("Jeff LaBundy <[email protected]>");
MODULE_DESCRIPTION("LV0104CS Ambient Light Sensor Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/lv0104cs.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* isl29125.c - Support for Intersil ISL29125 RGB light sensor
*
* Copyright (c) 2014 Peter Meerwald <[email protected]>
*
* RGB light sensor with 16-bit channels for red, green, blue);
* 7-bit I2C slave address 0x44
*
* TODO: interrupt support, IR compensation, thresholds, 12bit
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#define ISL29125_DRV_NAME "isl29125"
#define ISL29125_DEVICE_ID 0x00
#define ISL29125_CONF1 0x01
#define ISL29125_CONF2 0x02
#define ISL29125_CONF3 0x03
#define ISL29125_STATUS 0x08
#define ISL29125_GREEN_DATA 0x09
#define ISL29125_RED_DATA 0x0b
#define ISL29125_BLUE_DATA 0x0d
#define ISL29125_ID 0x7d
#define ISL29125_MODE_MASK GENMASK(2, 0)
#define ISL29125_MODE_PD 0x0
#define ISL29125_MODE_G 0x1
#define ISL29125_MODE_R 0x2
#define ISL29125_MODE_B 0x3
#define ISL29125_MODE_RGB 0x5
#define ISL29125_SENSING_RANGE_0 5722 /* 375 lux full range */
#define ISL29125_SENSING_RANGE_1 152590 /* 10k lux full range */
#define ISL29125_MODE_RANGE BIT(3)
#define ISL29125_STATUS_CONV BIT(1)
struct isl29125_data {
struct i2c_client *client;
u8 conf1;
/* Ensure timestamp is naturally aligned */
struct {
u16 chans[3];
s64 timestamp __aligned(8);
} scan;
};
#define ISL29125_CHANNEL(_color, _si) { \
.type = IIO_INTENSITY, \
.modified = 1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
.channel2 = IIO_MOD_LIGHT_##_color, \
.scan_index = _si, \
.scan_type = { \
.sign = 'u', \
.realbits = 16, \
.storagebits = 16, \
.endianness = IIO_CPU, \
}, \
}
static const struct iio_chan_spec isl29125_channels[] = {
ISL29125_CHANNEL(GREEN, 0),
ISL29125_CHANNEL(RED, 1),
ISL29125_CHANNEL(BLUE, 2),
IIO_CHAN_SOFT_TIMESTAMP(3),
};
static const struct {
u8 mode, data;
} isl29125_regs[] = {
{ISL29125_MODE_G, ISL29125_GREEN_DATA},
{ISL29125_MODE_R, ISL29125_RED_DATA},
{ISL29125_MODE_B, ISL29125_BLUE_DATA},
};
static int isl29125_read_data(struct isl29125_data *data, int si)
{
int tries = 5;
int ret;
ret = i2c_smbus_write_byte_data(data->client, ISL29125_CONF1,
data->conf1 | isl29125_regs[si].mode);
if (ret < 0)
return ret;
msleep(101);
while (tries--) {
ret = i2c_smbus_read_byte_data(data->client, ISL29125_STATUS);
if (ret < 0)
goto fail;
if (ret & ISL29125_STATUS_CONV)
break;
msleep(20);
}
if (tries < 0) {
dev_err(&data->client->dev, "data not ready\n");
ret = -EIO;
goto fail;
}
ret = i2c_smbus_read_word_data(data->client, isl29125_regs[si].data);
fail:
i2c_smbus_write_byte_data(data->client, ISL29125_CONF1, data->conf1);
return ret;
}
static int isl29125_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct isl29125_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = isl29125_read_data(data, chan->scan_index);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 0;
if (data->conf1 & ISL29125_MODE_RANGE)
*val2 = ISL29125_SENSING_RANGE_1; /*10k lux full range*/
else
*val2 = ISL29125_SENSING_RANGE_0; /*375 lux full range*/
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
}
static int isl29125_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct isl29125_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_SCALE:
if (val != 0)
return -EINVAL;
if (val2 == ISL29125_SENSING_RANGE_1)
data->conf1 |= ISL29125_MODE_RANGE;
else if (val2 == ISL29125_SENSING_RANGE_0)
data->conf1 &= ~ISL29125_MODE_RANGE;
else
return -EINVAL;
return i2c_smbus_write_byte_data(data->client, ISL29125_CONF1,
data->conf1);
default:
return -EINVAL;
}
}
static irqreturn_t isl29125_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct isl29125_data *data = iio_priv(indio_dev);
int i, j = 0;
for_each_set_bit(i, indio_dev->active_scan_mask,
indio_dev->masklength) {
int ret = i2c_smbus_read_word_data(data->client,
isl29125_regs[i].data);
if (ret < 0)
goto done;
data->scan.chans[j++] = ret;
}
iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
iio_get_time_ns(indio_dev));
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static IIO_CONST_ATTR(scale_available, "0.005722 0.152590");
static struct attribute *isl29125_attributes[] = {
&iio_const_attr_scale_available.dev_attr.attr,
NULL
};
static const struct attribute_group isl29125_attribute_group = {
.attrs = isl29125_attributes,
};
static const struct iio_info isl29125_info = {
.read_raw = isl29125_read_raw,
.write_raw = isl29125_write_raw,
.attrs = &isl29125_attribute_group,
};
static int isl29125_buffer_postenable(struct iio_dev *indio_dev)
{
struct isl29125_data *data = iio_priv(indio_dev);
data->conf1 |= ISL29125_MODE_RGB;
return i2c_smbus_write_byte_data(data->client, ISL29125_CONF1,
data->conf1);
}
static int isl29125_buffer_predisable(struct iio_dev *indio_dev)
{
struct isl29125_data *data = iio_priv(indio_dev);
data->conf1 &= ~ISL29125_MODE_MASK;
data->conf1 |= ISL29125_MODE_PD;
return i2c_smbus_write_byte_data(data->client, ISL29125_CONF1,
data->conf1);
}
static const struct iio_buffer_setup_ops isl29125_buffer_setup_ops = {
.postenable = isl29125_buffer_postenable,
.predisable = isl29125_buffer_predisable,
};
static int isl29125_probe(struct i2c_client *client)
{
struct isl29125_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (indio_dev == NULL)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
indio_dev->info = &isl29125_info;
indio_dev->name = ISL29125_DRV_NAME;
indio_dev->channels = isl29125_channels;
indio_dev->num_channels = ARRAY_SIZE(isl29125_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = i2c_smbus_read_byte_data(data->client, ISL29125_DEVICE_ID);
if (ret < 0)
return ret;
if (ret != ISL29125_ID)
return -ENODEV;
data->conf1 = ISL29125_MODE_PD | ISL29125_MODE_RANGE;
ret = i2c_smbus_write_byte_data(data->client, ISL29125_CONF1,
data->conf1);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client, ISL29125_STATUS, 0);
if (ret < 0)
return ret;
ret = iio_triggered_buffer_setup(indio_dev, NULL,
isl29125_trigger_handler, &isl29125_buffer_setup_ops);
if (ret < 0)
return ret;
ret = iio_device_register(indio_dev);
if (ret < 0)
goto buffer_cleanup;
return 0;
buffer_cleanup:
iio_triggered_buffer_cleanup(indio_dev);
return ret;
}
static int isl29125_powerdown(struct isl29125_data *data)
{
return i2c_smbus_write_byte_data(data->client, ISL29125_CONF1,
(data->conf1 & ~ISL29125_MODE_MASK) | ISL29125_MODE_PD);
}
static void isl29125_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
iio_device_unregister(indio_dev);
iio_triggered_buffer_cleanup(indio_dev);
isl29125_powerdown(iio_priv(indio_dev));
}
static int isl29125_suspend(struct device *dev)
{
struct isl29125_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
return isl29125_powerdown(data);
}
static int isl29125_resume(struct device *dev)
{
struct isl29125_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
return i2c_smbus_write_byte_data(data->client, ISL29125_CONF1,
data->conf1);
}
static DEFINE_SIMPLE_DEV_PM_OPS(isl29125_pm_ops, isl29125_suspend,
isl29125_resume);
static const struct i2c_device_id isl29125_id[] = {
{ "isl29125", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, isl29125_id);
static struct i2c_driver isl29125_driver = {
.driver = {
.name = ISL29125_DRV_NAME,
.pm = pm_sleep_ptr(&isl29125_pm_ops),
},
.probe = isl29125_probe,
.remove = isl29125_remove,
.id_table = isl29125_id,
};
module_i2c_driver(isl29125_driver);
MODULE_AUTHOR("Peter Meerwald <[email protected]>");
MODULE_DESCRIPTION("ISL29125 RGB light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/isl29125.c |
// SPDX-License-Identifier: GPL-2.0
/*
* max44009.c - Support for MAX44009 Ambient Light Sensor
*
* Copyright (c) 2019 Robert Eshleman <[email protected]>
*
* Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX44009.pdf
*
* TODO: Support continuous mode and configuring from manual mode to
* automatic mode.
*
* Default I2C address: 0x4a
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/bits.h>
#include <linux/i2c.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/util_macros.h>
#define MAX44009_DRV_NAME "max44009"
/* Registers in datasheet order */
#define MAX44009_REG_INT_STATUS 0x0
#define MAX44009_REG_INT_EN 0x1
#define MAX44009_REG_CFG 0x2
#define MAX44009_REG_LUX_HI 0x3
#define MAX44009_REG_LUX_LO 0x4
#define MAX44009_REG_UPPER_THR 0x5
#define MAX44009_REG_LOWER_THR 0x6
#define MAX44009_REG_THR_TIMER 0x7
#define MAX44009_CFG_TIM_MASK GENMASK(2, 0)
#define MAX44009_CFG_MAN_MODE_MASK BIT(6)
/* The maximum rising threshold for the max44009 */
#define MAX44009_MAXIMUM_THRESHOLD 7520256
#define MAX44009_THRESH_EXP_MASK (0xf << 4)
#define MAX44009_THRESH_EXP_RSHIFT 4
#define MAX44009_THRESH_MANT_LSHIFT 4
#define MAX44009_THRESH_MANT_MASK 0xf
#define MAX44009_UPPER_THR_MINIMUM 15
/* The max44009 always scales raw readings by 0.045 and is non-configurable */
#define MAX44009_SCALE_NUMERATOR 45
#define MAX44009_SCALE_DENOMINATOR 1000
/* The fixed-point fractional multiplier for de-scaling threshold values */
#define MAX44009_FRACT_MULT 1000000
static const u32 max44009_int_time_ns_array[] = {
800000000,
400000000,
200000000,
100000000,
50000000, /* Manual mode only */
25000000, /* Manual mode only */
12500000, /* Manual mode only */
6250000, /* Manual mode only */
};
static const char max44009_int_time_str[] =
"0.8 "
"0.4 "
"0.2 "
"0.1 "
"0.05 "
"0.025 "
"0.0125 "
"0.00625";
struct max44009_data {
struct i2c_client *client;
struct mutex lock;
};
static const struct iio_event_spec max44009_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec max44009_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_INT_TIME),
.event_spec = max44009_event_spec,
.num_event_specs = ARRAY_SIZE(max44009_event_spec),
},
};
static int max44009_read_int_time(struct max44009_data *data)
{
int ret = i2c_smbus_read_byte_data(data->client, MAX44009_REG_CFG);
if (ret < 0)
return ret;
return max44009_int_time_ns_array[ret & MAX44009_CFG_TIM_MASK];
}
static int max44009_write_int_time(struct max44009_data *data,
int val, int val2)
{
struct i2c_client *client = data->client;
int ret, int_time, config;
s64 ns;
ns = val * NSEC_PER_SEC + val2;
int_time = find_closest_descending(
ns,
max44009_int_time_ns_array,
ARRAY_SIZE(max44009_int_time_ns_array));
ret = i2c_smbus_read_byte_data(client, MAX44009_REG_CFG);
if (ret < 0)
return ret;
config = ret;
config &= int_time;
/*
* To set the integration time, the device must also be in manual
* mode.
*/
config |= MAX44009_CFG_MAN_MODE_MASK;
return i2c_smbus_write_byte_data(client, MAX44009_REG_CFG, config);
}
static int max44009_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct max44009_data *data = iio_priv(indio_dev);
int ret;
if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT) {
mutex_lock(&data->lock);
ret = max44009_write_int_time(data, val, val2);
mutex_unlock(&data->lock);
return ret;
}
return -EINVAL;
}
static int max44009_write_raw_get_fmt(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
long mask)
{
return IIO_VAL_INT_PLUS_NANO;
}
static int max44009_lux_raw(u8 hi, u8 lo)
{
int mantissa;
int exponent;
/*
* The mantissa consists of the low nibble of the Lux High Byte
* and the low nibble of the Lux Low Byte.
*/
mantissa = ((hi & 0xf) << 4) | (lo & 0xf);
/* The exponent byte is just the upper nibble of the Lux High Byte */
exponent = (hi >> 4) & 0xf;
/*
* The exponent value is base 2 to the power of the raw exponent byte.
*/
exponent = 1 << exponent;
return exponent * mantissa;
}
#define MAX44009_READ_LUX_XFER_LEN (4)
static int max44009_read_lux_raw(struct max44009_data *data)
{
int ret;
u8 hireg = MAX44009_REG_LUX_HI;
u8 loreg = MAX44009_REG_LUX_LO;
u8 lo = 0;
u8 hi = 0;
struct i2c_msg msgs[] = {
{
.addr = data->client->addr,
.flags = 0,
.len = sizeof(hireg),
.buf = &hireg,
},
{
.addr = data->client->addr,
.flags = I2C_M_RD,
.len = sizeof(hi),
.buf = &hi,
},
{
.addr = data->client->addr,
.flags = 0,
.len = sizeof(loreg),
.buf = &loreg,
},
{
.addr = data->client->addr,
.flags = I2C_M_RD,
.len = sizeof(lo),
.buf = &lo,
}
};
/*
* Use i2c_transfer instead of smbus read because i2c_transfer
* does NOT use a stop bit between address write and data read.
* Using a stop bit causes disjoint upper/lower byte reads and
* reduces accuracy.
*/
ret = i2c_transfer(data->client->adapter,
msgs, MAX44009_READ_LUX_XFER_LEN);
if (ret != MAX44009_READ_LUX_XFER_LEN)
return -EIO;
return max44009_lux_raw(hi, lo);
}
static int max44009_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct max44009_data *data = iio_priv(indio_dev);
int lux_raw;
int ret;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_LIGHT:
ret = max44009_read_lux_raw(data);
if (ret < 0)
return ret;
lux_raw = ret;
*val = lux_raw * MAX44009_SCALE_NUMERATOR;
*val2 = MAX44009_SCALE_DENOMINATOR;
return IIO_VAL_FRACTIONAL;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_INT_TIME:
switch (chan->type) {
case IIO_LIGHT:
ret = max44009_read_int_time(data);
if (ret < 0)
return ret;
*val2 = ret;
*val = 0;
return IIO_VAL_INT_PLUS_NANO;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static IIO_CONST_ATTR(illuminance_integration_time_available,
max44009_int_time_str);
static struct attribute *max44009_attributes[] = {
&iio_const_attr_illuminance_integration_time_available.dev_attr.attr,
NULL,
};
static const struct attribute_group max44009_attribute_group = {
.attrs = max44009_attributes,
};
static int max44009_threshold_byte_from_fraction(int integral, int fractional)
{
int mantissa, exp;
if ((integral <= 0 && fractional <= 0) ||
integral > MAX44009_MAXIMUM_THRESHOLD ||
(integral == MAX44009_MAXIMUM_THRESHOLD && fractional != 0))
return -EINVAL;
/* Reverse scaling of fixed-point integral */
mantissa = integral * MAX44009_SCALE_DENOMINATOR;
mantissa /= MAX44009_SCALE_NUMERATOR;
/* Reverse scaling of fixed-point fractional */
mantissa += fractional / MAX44009_FRACT_MULT *
(MAX44009_SCALE_DENOMINATOR / MAX44009_SCALE_NUMERATOR);
for (exp = 0; mantissa > 0xff; exp++)
mantissa >>= 1;
mantissa >>= 4;
mantissa &= 0xf;
exp <<= 4;
return exp | mantissa;
}
static int max44009_get_thr_reg(enum iio_event_direction dir)
{
switch (dir) {
case IIO_EV_DIR_RISING:
return MAX44009_REG_UPPER_THR;
case IIO_EV_DIR_FALLING:
return MAX44009_REG_LOWER_THR;
default:
return -EINVAL;
}
}
static int max44009_write_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
struct max44009_data *data = iio_priv(indio_dev);
int reg, threshold;
if (info != IIO_EV_INFO_VALUE || chan->type != IIO_LIGHT)
return -EINVAL;
threshold = max44009_threshold_byte_from_fraction(val, val2);
if (threshold < 0)
return threshold;
reg = max44009_get_thr_reg(dir);
if (reg < 0)
return reg;
return i2c_smbus_write_byte_data(data->client, reg, threshold);
}
static int max44009_read_threshold(struct iio_dev *indio_dev,
enum iio_event_direction dir)
{
struct max44009_data *data = iio_priv(indio_dev);
int byte, reg;
int mantissa, exponent;
reg = max44009_get_thr_reg(dir);
if (reg < 0)
return reg;
byte = i2c_smbus_read_byte_data(data->client, reg);
if (byte < 0)
return byte;
mantissa = byte & MAX44009_THRESH_MANT_MASK;
mantissa <<= MAX44009_THRESH_MANT_LSHIFT;
/*
* To get the upper threshold, always adds the minimum upper threshold
* value to the shifted byte value (see datasheet).
*/
if (dir == IIO_EV_DIR_RISING)
mantissa += MAX44009_UPPER_THR_MINIMUM;
/*
* Exponent is base 2 to the power of the threshold exponent byte
* value
*/
exponent = byte & MAX44009_THRESH_EXP_MASK;
exponent >>= MAX44009_THRESH_EXP_RSHIFT;
return (1 << exponent) * mantissa;
}
static int max44009_read_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
int ret;
int threshold;
if (chan->type != IIO_LIGHT || type != IIO_EV_TYPE_THRESH)
return -EINVAL;
ret = max44009_read_threshold(indio_dev, dir);
if (ret < 0)
return ret;
threshold = ret;
*val = threshold * MAX44009_SCALE_NUMERATOR;
*val2 = MAX44009_SCALE_DENOMINATOR;
return IIO_VAL_FRACTIONAL;
}
static int max44009_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
struct max44009_data *data = iio_priv(indio_dev);
int ret;
if (chan->type != IIO_LIGHT || type != IIO_EV_TYPE_THRESH)
return -EINVAL;
ret = i2c_smbus_write_byte_data(data->client,
MAX44009_REG_INT_EN, state);
if (ret < 0)
return ret;
/*
* Set device to trigger interrupt immediately upon exceeding
* the threshold limit.
*/
return i2c_smbus_write_byte_data(data->client,
MAX44009_REG_THR_TIMER, 0);
}
static int max44009_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct max44009_data *data = iio_priv(indio_dev);
if (chan->type != IIO_LIGHT || type != IIO_EV_TYPE_THRESH)
return -EINVAL;
return i2c_smbus_read_byte_data(data->client, MAX44009_REG_INT_EN);
}
static const struct iio_info max44009_info = {
.read_raw = max44009_read_raw,
.write_raw = max44009_write_raw,
.write_raw_get_fmt = max44009_write_raw_get_fmt,
.read_event_value = max44009_read_event_value,
.read_event_config = max44009_read_event_config,
.write_event_value = max44009_write_event_value,
.write_event_config = max44009_write_event_config,
.attrs = &max44009_attribute_group,
};
static irqreturn_t max44009_threaded_irq_handler(int irq, void *p)
{
struct iio_dev *indio_dev = p;
struct max44009_data *data = iio_priv(indio_dev);
int ret;
ret = i2c_smbus_read_byte_data(data->client, MAX44009_REG_INT_STATUS);
if (ret) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(indio_dev));
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static int max44009_probe(struct i2c_client *client)
{
struct max44009_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
indio_dev->info = &max44009_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->name = MAX44009_DRV_NAME;
indio_dev->channels = max44009_channels;
indio_dev->num_channels = ARRAY_SIZE(max44009_channels);
mutex_init(&data->lock);
/* Clear any stale interrupt bit */
ret = i2c_smbus_read_byte_data(client, MAX44009_REG_CFG);
if (ret < 0)
return ret;
if (client->irq > 0) {
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL,
max44009_threaded_irq_handler,
IRQF_TRIGGER_FALLING |
IRQF_ONESHOT | IRQF_SHARED,
"max44009_event",
indio_dev);
if (ret < 0)
return ret;
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct of_device_id max44009_of_match[] = {
{ .compatible = "maxim,max44009" },
{ }
};
MODULE_DEVICE_TABLE(of, max44009_of_match);
static const struct i2c_device_id max44009_id[] = {
{ "max44009", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max44009_id);
static struct i2c_driver max44009_driver = {
.driver = {
.name = MAX44009_DRV_NAME,
.of_match_table = max44009_of_match,
},
.probe = max44009_probe,
.id_table = max44009_id,
};
module_i2c_driver(max44009_driver);
MODULE_AUTHOR("Robert Eshleman <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MAX44009 ambient light sensor driver");
| linux-master | drivers/iio/light/max44009.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* STMicroelectronics uvis25 sensor driver
*
* Copyright 2017 STMicroelectronics Inc.
*
* Lorenzo Bianconi <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/iio/sysfs.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/interrupt.h>
#include <linux/irqreturn.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/buffer.h>
#include <linux/regmap.h>
#include "st_uvis25.h"
#define ST_UVIS25_REG_WHOAMI_ADDR 0x0f
#define ST_UVIS25_REG_WHOAMI_VAL 0xca
#define ST_UVIS25_REG_CTRL1_ADDR 0x20
#define ST_UVIS25_REG_ODR_MASK BIT(0)
#define ST_UVIS25_REG_BDU_MASK BIT(1)
#define ST_UVIS25_REG_CTRL2_ADDR 0x21
#define ST_UVIS25_REG_BOOT_MASK BIT(7)
#define ST_UVIS25_REG_CTRL3_ADDR 0x22
#define ST_UVIS25_REG_HL_MASK BIT(7)
#define ST_UVIS25_REG_STATUS_ADDR 0x27
#define ST_UVIS25_REG_UV_DA_MASK BIT(0)
#define ST_UVIS25_REG_OUT_ADDR 0x28
static const struct iio_chan_spec st_uvis25_channels[] = {
{
.type = IIO_UVINDEX,
.address = ST_UVIS25_REG_OUT_ADDR,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.scan_index = 0,
.scan_type = {
.sign = 'u',
.realbits = 8,
.storagebits = 8,
},
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static int st_uvis25_check_whoami(struct st_uvis25_hw *hw)
{
int err, data;
err = regmap_read(hw->regmap, ST_UVIS25_REG_WHOAMI_ADDR, &data);
if (err < 0) {
dev_err(regmap_get_device(hw->regmap),
"failed to read whoami register\n");
return err;
}
if (data != ST_UVIS25_REG_WHOAMI_VAL) {
dev_err(regmap_get_device(hw->regmap),
"wrong whoami {%02x vs %02x}\n",
data, ST_UVIS25_REG_WHOAMI_VAL);
return -ENODEV;
}
return 0;
}
static int st_uvis25_set_enable(struct st_uvis25_hw *hw, bool enable)
{
int err;
err = regmap_update_bits(hw->regmap, ST_UVIS25_REG_CTRL1_ADDR,
ST_UVIS25_REG_ODR_MASK, enable);
if (err < 0)
return err;
hw->enabled = enable;
return 0;
}
static int st_uvis25_read_oneshot(struct st_uvis25_hw *hw, u8 addr, int *val)
{
int err;
err = st_uvis25_set_enable(hw, true);
if (err < 0)
return err;
msleep(1500);
/*
* in order to avoid possible race conditions with interrupt
* generation, disable the sensor first and then poll output
* register. That sequence guarantees the interrupt will be reset
* when irq line is unmasked
*/
err = st_uvis25_set_enable(hw, false);
if (err < 0)
return err;
err = regmap_read(hw->regmap, addr, val);
return err < 0 ? err : IIO_VAL_INT;
}
static int st_uvis25_read_raw(struct iio_dev *iio_dev,
struct iio_chan_spec const *ch,
int *val, int *val2, long mask)
{
int ret;
ret = iio_device_claim_direct_mode(iio_dev);
if (ret)
return ret;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED: {
struct st_uvis25_hw *hw = iio_priv(iio_dev);
/*
* mask irq line during oneshot read since the sensor
* does not export the capability to disable data-ready line
* in the register map and it is enabled by default.
* If the line is unmasked during read_raw() it will be set
* active and never reset since the trigger is disabled
*/
if (hw->irq > 0)
disable_irq(hw->irq);
ret = st_uvis25_read_oneshot(hw, ch->address, val);
if (hw->irq > 0)
enable_irq(hw->irq);
break;
}
default:
ret = -EINVAL;
break;
}
iio_device_release_direct_mode(iio_dev);
return ret;
}
static irqreturn_t st_uvis25_trigger_handler_thread(int irq, void *private)
{
struct st_uvis25_hw *hw = private;
int err, status;
err = regmap_read(hw->regmap, ST_UVIS25_REG_STATUS_ADDR, &status);
if (err < 0)
return IRQ_HANDLED;
if (!(status & ST_UVIS25_REG_UV_DA_MASK))
return IRQ_NONE;
iio_trigger_poll_nested(hw->trig);
return IRQ_HANDLED;
}
static int st_uvis25_allocate_trigger(struct iio_dev *iio_dev)
{
struct st_uvis25_hw *hw = iio_priv(iio_dev);
struct device *dev = regmap_get_device(hw->regmap);
bool irq_active_low = false;
unsigned long irq_type;
int err;
irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq));
switch (irq_type) {
case IRQF_TRIGGER_HIGH:
case IRQF_TRIGGER_RISING:
break;
case IRQF_TRIGGER_LOW:
case IRQF_TRIGGER_FALLING:
irq_active_low = true;
break;
default:
dev_info(dev, "mode %lx unsupported\n", irq_type);
return -EINVAL;
}
err = regmap_update_bits(hw->regmap, ST_UVIS25_REG_CTRL3_ADDR,
ST_UVIS25_REG_HL_MASK, irq_active_low);
if (err < 0)
return err;
err = devm_request_threaded_irq(dev, hw->irq, NULL,
st_uvis25_trigger_handler_thread,
irq_type | IRQF_ONESHOT,
iio_dev->name, hw);
if (err) {
dev_err(dev, "failed to request trigger irq %d\n",
hw->irq);
return err;
}
hw->trig = devm_iio_trigger_alloc(dev, "%s-trigger",
iio_dev->name);
if (!hw->trig)
return -ENOMEM;
iio_trigger_set_drvdata(hw->trig, iio_dev);
return devm_iio_trigger_register(dev, hw->trig);
}
static int st_uvis25_buffer_preenable(struct iio_dev *iio_dev)
{
return st_uvis25_set_enable(iio_priv(iio_dev), true);
}
static int st_uvis25_buffer_postdisable(struct iio_dev *iio_dev)
{
return st_uvis25_set_enable(iio_priv(iio_dev), false);
}
static const struct iio_buffer_setup_ops st_uvis25_buffer_ops = {
.preenable = st_uvis25_buffer_preenable,
.postdisable = st_uvis25_buffer_postdisable,
};
static irqreturn_t st_uvis25_buffer_handler_thread(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *iio_dev = pf->indio_dev;
struct st_uvis25_hw *hw = iio_priv(iio_dev);
unsigned int val;
int err;
err = regmap_read(hw->regmap, ST_UVIS25_REG_OUT_ADDR, &val);
if (err < 0)
goto out;
hw->scan.chan = val;
iio_push_to_buffers_with_timestamp(iio_dev, &hw->scan,
iio_get_time_ns(iio_dev));
out:
iio_trigger_notify_done(hw->trig);
return IRQ_HANDLED;
}
static int st_uvis25_allocate_buffer(struct iio_dev *iio_dev)
{
struct st_uvis25_hw *hw = iio_priv(iio_dev);
return devm_iio_triggered_buffer_setup(regmap_get_device(hw->regmap),
iio_dev, NULL,
st_uvis25_buffer_handler_thread,
&st_uvis25_buffer_ops);
}
static const struct iio_info st_uvis25_info = {
.read_raw = st_uvis25_read_raw,
};
static int st_uvis25_init_sensor(struct st_uvis25_hw *hw)
{
int err;
err = regmap_update_bits(hw->regmap, ST_UVIS25_REG_CTRL2_ADDR,
ST_UVIS25_REG_BOOT_MASK, 1);
if (err < 0)
return err;
msleep(2000);
return regmap_update_bits(hw->regmap, ST_UVIS25_REG_CTRL1_ADDR,
ST_UVIS25_REG_BDU_MASK, 1);
}
int st_uvis25_probe(struct device *dev, int irq, struct regmap *regmap)
{
struct st_uvis25_hw *hw;
struct iio_dev *iio_dev;
int err;
iio_dev = devm_iio_device_alloc(dev, sizeof(*hw));
if (!iio_dev)
return -ENOMEM;
dev_set_drvdata(dev, (void *)iio_dev);
hw = iio_priv(iio_dev);
hw->irq = irq;
hw->regmap = regmap;
err = st_uvis25_check_whoami(hw);
if (err < 0)
return err;
iio_dev->modes = INDIO_DIRECT_MODE;
iio_dev->channels = st_uvis25_channels;
iio_dev->num_channels = ARRAY_SIZE(st_uvis25_channels);
iio_dev->name = ST_UVIS25_DEV_NAME;
iio_dev->info = &st_uvis25_info;
err = st_uvis25_init_sensor(hw);
if (err < 0)
return err;
if (hw->irq > 0) {
err = st_uvis25_allocate_buffer(iio_dev);
if (err < 0)
return err;
err = st_uvis25_allocate_trigger(iio_dev);
if (err)
return err;
}
return devm_iio_device_register(dev, iio_dev);
}
EXPORT_SYMBOL_NS(st_uvis25_probe, IIO_UVIS25);
static int st_uvis25_suspend(struct device *dev)
{
struct iio_dev *iio_dev = dev_get_drvdata(dev);
struct st_uvis25_hw *hw = iio_priv(iio_dev);
return regmap_update_bits(hw->regmap, ST_UVIS25_REG_CTRL1_ADDR,
ST_UVIS25_REG_ODR_MASK, 0);
}
static int st_uvis25_resume(struct device *dev)
{
struct iio_dev *iio_dev = dev_get_drvdata(dev);
struct st_uvis25_hw *hw = iio_priv(iio_dev);
if (hw->enabled)
return regmap_update_bits(hw->regmap, ST_UVIS25_REG_CTRL1_ADDR,
ST_UVIS25_REG_ODR_MASK, 1);
return 0;
}
EXPORT_NS_SIMPLE_DEV_PM_OPS(st_uvis25_pm_ops, st_uvis25_suspend, st_uvis25_resume, IIO_UVIS25);
MODULE_AUTHOR("Lorenzo Bianconi <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics uvis25 sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/st_uvis25_core.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Device driver for monitoring ambient light intensity in (lux) and proximity
* detection (prox) within the TAOS TSL2571, TSL2671, TMD2671, TSL2771, TMD2771,
* TSL2572, TSL2672, TMD2672, TSL2772, and TMD2772 devices.
*
* Copyright (c) 2012, TAOS Corporation.
* Copyright (c) 2017-2018 Brian Masney <[email protected]>
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/platform_data/tsl2772.h>
#include <linux/regulator/consumer.h>
/* Cal defs */
#define PROX_STAT_CAL 0
#define PROX_STAT_SAMP 1
#define MAX_SAMPLES_CAL 200
/* TSL2772 Device ID */
#define TRITON_ID 0x00
#define SWORDFISH_ID 0x30
#define HALIBUT_ID 0x20
/* Lux calculation constants */
#define TSL2772_LUX_CALC_OVER_FLOW 65535
/*
* TAOS Register definitions - Note: depending on device, some of these register
* are not used and the register address is benign.
*/
/* Register offsets */
#define TSL2772_MAX_CONFIG_REG 16
/* Device Registers and Masks */
#define TSL2772_CNTRL 0x00
#define TSL2772_ALS_TIME 0X01
#define TSL2772_PRX_TIME 0x02
#define TSL2772_WAIT_TIME 0x03
#define TSL2772_ALS_MINTHRESHLO 0X04
#define TSL2772_ALS_MINTHRESHHI 0X05
#define TSL2772_ALS_MAXTHRESHLO 0X06
#define TSL2772_ALS_MAXTHRESHHI 0X07
#define TSL2772_PRX_MINTHRESHLO 0X08
#define TSL2772_PRX_MINTHRESHHI 0X09
#define TSL2772_PRX_MAXTHRESHLO 0X0A
#define TSL2772_PRX_MAXTHRESHHI 0X0B
#define TSL2772_PERSISTENCE 0x0C
#define TSL2772_ALS_PRX_CONFIG 0x0D
#define TSL2772_PRX_COUNT 0x0E
#define TSL2772_GAIN 0x0F
#define TSL2772_NOTUSED 0x10
#define TSL2772_REVID 0x11
#define TSL2772_CHIPID 0x12
#define TSL2772_STATUS 0x13
#define TSL2772_ALS_CHAN0LO 0x14
#define TSL2772_ALS_CHAN0HI 0x15
#define TSL2772_ALS_CHAN1LO 0x16
#define TSL2772_ALS_CHAN1HI 0x17
#define TSL2772_PRX_LO 0x18
#define TSL2772_PRX_HI 0x19
/* tsl2772 cmd reg masks */
#define TSL2772_CMD_REG 0x80
#define TSL2772_CMD_SPL_FN 0x60
#define TSL2772_CMD_REPEAT_PROTO 0x00
#define TSL2772_CMD_AUTOINC_PROTO 0x20
#define TSL2772_CMD_PROX_INT_CLR 0X05
#define TSL2772_CMD_ALS_INT_CLR 0x06
#define TSL2772_CMD_PROXALS_INT_CLR 0X07
/* tsl2772 cntrl reg masks */
#define TSL2772_CNTL_ADC_ENBL 0x02
#define TSL2772_CNTL_PWR_ON 0x01
/* tsl2772 status reg masks */
#define TSL2772_STA_ADC_VALID 0x01
#define TSL2772_STA_PRX_VALID 0x02
#define TSL2772_STA_ADC_PRX_VALID (TSL2772_STA_ADC_VALID | \
TSL2772_STA_PRX_VALID)
#define TSL2772_STA_ALS_INTR 0x10
#define TSL2772_STA_PRX_INTR 0x20
/* tsl2772 cntrl reg masks */
#define TSL2772_CNTL_REG_CLEAR 0x00
#define TSL2772_CNTL_PROX_INT_ENBL 0X20
#define TSL2772_CNTL_ALS_INT_ENBL 0X10
#define TSL2772_CNTL_WAIT_TMR_ENBL 0X08
#define TSL2772_CNTL_PROX_DET_ENBL 0X04
#define TSL2772_CNTL_PWRON 0x01
#define TSL2772_CNTL_ALSPON_ENBL 0x03
#define TSL2772_CNTL_INTALSPON_ENBL 0x13
#define TSL2772_CNTL_PROXPON_ENBL 0x0F
#define TSL2772_CNTL_INTPROXPON_ENBL 0x2F
#define TSL2772_ALS_GAIN_TRIM_MIN 250
#define TSL2772_ALS_GAIN_TRIM_MAX 4000
#define TSL2772_MAX_PROX_LEDS 2
#define TSL2772_BOOT_MIN_SLEEP_TIME 10000
#define TSL2772_BOOT_MAX_SLEEP_TIME 28000
/* Device family members */
enum {
tsl2571,
tsl2671,
tmd2671,
tsl2771,
tmd2771,
tsl2572,
tsl2672,
tmd2672,
tsl2772,
tmd2772,
apds9930,
};
enum {
TSL2772_CHIP_UNKNOWN = 0,
TSL2772_CHIP_WORKING = 1,
TSL2772_CHIP_SUSPENDED = 2
};
enum {
TSL2772_SUPPLY_VDD = 0,
TSL2772_SUPPLY_VDDIO = 1,
TSL2772_NUM_SUPPLIES = 2
};
/* Per-device data */
struct tsl2772_als_info {
u16 als_ch0;
u16 als_ch1;
u16 lux;
};
struct tsl2772_chip_info {
int chan_table_elements;
struct iio_chan_spec channel_with_events[4];
struct iio_chan_spec channel_without_events[4];
const struct iio_info *info;
};
static const int tsl2772_led_currents[][2] = {
{ 100000, TSL2772_100_mA },
{ 50000, TSL2772_50_mA },
{ 25000, TSL2772_25_mA },
{ 13000, TSL2772_13_mA },
{ 0, 0 }
};
struct tsl2772_chip {
kernel_ulong_t id;
struct mutex prox_mutex;
struct mutex als_mutex;
struct i2c_client *client;
struct regulator_bulk_data supplies[TSL2772_NUM_SUPPLIES];
u16 prox_data;
struct tsl2772_als_info als_cur_info;
struct tsl2772_settings settings;
struct tsl2772_platform_data *pdata;
int als_gain_time_scale;
int als_saturation;
int tsl2772_chip_status;
u8 tsl2772_config[TSL2772_MAX_CONFIG_REG];
const struct tsl2772_chip_info *chip_info;
const struct iio_info *info;
s64 event_timestamp;
/*
* This structure is intentionally large to accommodate
* updates via sysfs.
* Sized to 9 = max 8 segments + 1 termination segment
*/
struct tsl2772_lux tsl2772_device_lux[TSL2772_MAX_LUX_TABLE_SIZE];
};
/*
* Different devices require different coefficents, and these numbers were
* derived from the 'Lux Equation' section of the various device datasheets.
* All of these coefficients assume a Glass Attenuation (GA) factor of 1.
* The coefficients are multiplied by 1000 to avoid floating point operations.
* The two rows in each table correspond to the Lux1 and Lux2 equations from
* the datasheets.
*/
static const struct tsl2772_lux tsl2x71_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
{ 53000, 106000 },
{ 31800, 53000 },
{ 0, 0 },
};
static const struct tsl2772_lux tmd2x71_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
{ 24000, 48000 },
{ 14400, 24000 },
{ 0, 0 },
};
static const struct tsl2772_lux tsl2x72_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
{ 60000, 112200 },
{ 37800, 60000 },
{ 0, 0 },
};
static const struct tsl2772_lux tmd2x72_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
{ 20000, 35000 },
{ 12600, 20000 },
{ 0, 0 },
};
static const struct tsl2772_lux apds9930_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
{ 52000, 96824 },
{ 38792, 67132 },
{ 0, 0 },
};
static const struct tsl2772_lux *tsl2772_default_lux_table_group[] = {
[tsl2571] = tsl2x71_lux_table,
[tsl2671] = tsl2x71_lux_table,
[tmd2671] = tmd2x71_lux_table,
[tsl2771] = tsl2x71_lux_table,
[tmd2771] = tmd2x71_lux_table,
[tsl2572] = tsl2x72_lux_table,
[tsl2672] = tsl2x72_lux_table,
[tmd2672] = tmd2x72_lux_table,
[tsl2772] = tsl2x72_lux_table,
[tmd2772] = tmd2x72_lux_table,
[apds9930] = apds9930_lux_table,
};
static const struct tsl2772_settings tsl2772_default_settings = {
.als_time = 255, /* 2.72 / 2.73 ms */
.als_gain = 0,
.prox_time = 255, /* 2.72 / 2.73 ms */
.prox_gain = 0,
.wait_time = 255,
.als_prox_config = 0,
.als_gain_trim = 1000,
.als_cal_target = 150,
.als_persistence = 1,
.als_interrupt_en = false,
.als_thresh_low = 200,
.als_thresh_high = 256,
.prox_persistence = 1,
.prox_interrupt_en = false,
.prox_thres_low = 0,
.prox_thres_high = 512,
.prox_max_samples_cal = 30,
.prox_pulse_count = 8,
.prox_diode = TSL2772_DIODE1,
.prox_power = TSL2772_100_mA
};
static const s16 tsl2772_als_gain[] = {
1,
8,
16,
120
};
static const s16 tsl2772_prox_gain[] = {
1,
2,
4,
8
};
static const int tsl2772_int_time_avail[][6] = {
[tsl2571] = { 0, 2720, 0, 2720, 0, 696000 },
[tsl2671] = { 0, 2720, 0, 2720, 0, 696000 },
[tmd2671] = { 0, 2720, 0, 2720, 0, 696000 },
[tsl2771] = { 0, 2720, 0, 2720, 0, 696000 },
[tmd2771] = { 0, 2720, 0, 2720, 0, 696000 },
[tsl2572] = { 0, 2730, 0, 2730, 0, 699000 },
[tsl2672] = { 0, 2730, 0, 2730, 0, 699000 },
[tmd2672] = { 0, 2730, 0, 2730, 0, 699000 },
[tsl2772] = { 0, 2730, 0, 2730, 0, 699000 },
[tmd2772] = { 0, 2730, 0, 2730, 0, 699000 },
[apds9930] = { 0, 2730, 0, 2730, 0, 699000 },
};
static int tsl2772_int_calibscale_avail[] = { 1, 8, 16, 120 };
static int tsl2772_prox_calibscale_avail[] = { 1, 2, 4, 8 };
/* Channel variations */
enum {
ALS,
PRX,
ALSPRX,
PRX2,
ALSPRX2,
};
static const u8 device_channel_config[] = {
[tsl2571] = ALS,
[tsl2671] = PRX,
[tmd2671] = PRX,
[tsl2771] = ALSPRX,
[tmd2771] = ALSPRX,
[tsl2572] = ALS,
[tsl2672] = PRX2,
[tmd2672] = PRX2,
[tsl2772] = ALSPRX2,
[tmd2772] = ALSPRX2,
[apds9930] = ALSPRX2,
};
static int tsl2772_read_status(struct tsl2772_chip *chip)
{
int ret;
ret = i2c_smbus_read_byte_data(chip->client,
TSL2772_CMD_REG | TSL2772_STATUS);
if (ret < 0)
dev_err(&chip->client->dev,
"%s: failed to read STATUS register: %d\n", __func__,
ret);
return ret;
}
static int tsl2772_write_control_reg(struct tsl2772_chip *chip, u8 data)
{
int ret;
ret = i2c_smbus_write_byte_data(chip->client,
TSL2772_CMD_REG | TSL2772_CNTRL, data);
if (ret < 0) {
dev_err(&chip->client->dev,
"%s: failed to write to control register %x: %d\n",
__func__, data, ret);
}
return ret;
}
static int tsl2772_read_autoinc_regs(struct tsl2772_chip *chip, int lower_reg,
int upper_reg)
{
u8 buf[2];
int ret;
ret = i2c_smbus_write_byte(chip->client,
TSL2772_CMD_REG | TSL2772_CMD_AUTOINC_PROTO |
lower_reg);
if (ret < 0) {
dev_err(&chip->client->dev,
"%s: failed to enable auto increment protocol: %d\n",
__func__, ret);
return ret;
}
ret = i2c_smbus_read_byte_data(chip->client,
TSL2772_CMD_REG | lower_reg);
if (ret < 0) {
dev_err(&chip->client->dev,
"%s: failed to read from register %x: %d\n", __func__,
lower_reg, ret);
return ret;
}
buf[0] = ret;
ret = i2c_smbus_read_byte_data(chip->client,
TSL2772_CMD_REG | upper_reg);
if (ret < 0) {
dev_err(&chip->client->dev,
"%s: failed to read from register %x: %d\n", __func__,
upper_reg, ret);
return ret;
}
buf[1] = ret;
ret = i2c_smbus_write_byte(chip->client,
TSL2772_CMD_REG | TSL2772_CMD_REPEAT_PROTO |
lower_reg);
if (ret < 0) {
dev_err(&chip->client->dev,
"%s: failed to enable repeated byte protocol: %d\n",
__func__, ret);
return ret;
}
return le16_to_cpup((const __le16 *)&buf[0]);
}
/**
* tsl2772_get_lux() - Reads and calculates current lux value.
* @indio_dev: pointer to IIO device
*
* The raw ch0 and ch1 values of the ambient light sensed in the last
* integration cycle are read from the device. The raw values are multiplied
* by a device-specific scale factor, and divided by the integration time and
* device gain. The code supports multiple lux equations through the lux table
* coefficients. A lux gain trim is applied to each lux equation, and then the
* maximum lux within the interval 0..65535 is selected.
*/
static int tsl2772_get_lux(struct iio_dev *indio_dev)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
struct tsl2772_lux *p;
int max_lux, ret;
bool overflow;
mutex_lock(&chip->als_mutex);
if (chip->tsl2772_chip_status != TSL2772_CHIP_WORKING) {
dev_err(&chip->client->dev, "%s: device is not enabled\n",
__func__);
ret = -EBUSY;
goto out_unlock;
}
ret = tsl2772_read_status(chip);
if (ret < 0)
goto out_unlock;
if (!(ret & TSL2772_STA_ADC_VALID)) {
dev_err(&chip->client->dev,
"%s: data not valid yet\n", __func__);
ret = chip->als_cur_info.lux; /* return LAST VALUE */
goto out_unlock;
}
ret = tsl2772_read_autoinc_regs(chip, TSL2772_ALS_CHAN0LO,
TSL2772_ALS_CHAN0HI);
if (ret < 0)
goto out_unlock;
chip->als_cur_info.als_ch0 = ret;
ret = tsl2772_read_autoinc_regs(chip, TSL2772_ALS_CHAN1LO,
TSL2772_ALS_CHAN1HI);
if (ret < 0)
goto out_unlock;
chip->als_cur_info.als_ch1 = ret;
if (chip->als_cur_info.als_ch0 >= chip->als_saturation) {
max_lux = TSL2772_LUX_CALC_OVER_FLOW;
goto update_struct_with_max_lux;
}
if (!chip->als_cur_info.als_ch0) {
/* have no data, so return LAST VALUE */
ret = chip->als_cur_info.lux;
goto out_unlock;
}
max_lux = 0;
overflow = false;
for (p = (struct tsl2772_lux *)chip->tsl2772_device_lux; p->ch0 != 0;
p++) {
int lux;
lux = ((chip->als_cur_info.als_ch0 * p->ch0) -
(chip->als_cur_info.als_ch1 * p->ch1)) /
chip->als_gain_time_scale;
/*
* The als_gain_trim can have a value within the range 250..4000
* and is a multiplier for the lux. A trim of 1000 makes no
* changes to the lux, less than 1000 scales it down, and
* greater than 1000 scales it up.
*/
lux = (lux * chip->settings.als_gain_trim) / 1000;
if (lux > TSL2772_LUX_CALC_OVER_FLOW) {
overflow = true;
continue;
}
max_lux = max(max_lux, lux);
}
if (overflow && max_lux == 0)
max_lux = TSL2772_LUX_CALC_OVER_FLOW;
update_struct_with_max_lux:
chip->als_cur_info.lux = max_lux;
ret = max_lux;
out_unlock:
mutex_unlock(&chip->als_mutex);
return ret;
}
/**
* tsl2772_get_prox() - Reads proximity data registers and updates
* chip->prox_data.
*
* @indio_dev: pointer to IIO device
*/
static int tsl2772_get_prox(struct iio_dev *indio_dev)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
int ret;
mutex_lock(&chip->prox_mutex);
ret = tsl2772_read_status(chip);
if (ret < 0)
goto prox_poll_err;
switch (chip->id) {
case tsl2571:
case tsl2671:
case tmd2671:
case tsl2771:
case tmd2771:
if (!(ret & TSL2772_STA_ADC_VALID)) {
ret = -EINVAL;
goto prox_poll_err;
}
break;
case tsl2572:
case tsl2672:
case tmd2672:
case tsl2772:
case tmd2772:
case apds9930:
if (!(ret & TSL2772_STA_PRX_VALID)) {
ret = -EINVAL;
goto prox_poll_err;
}
break;
}
ret = tsl2772_read_autoinc_regs(chip, TSL2772_PRX_LO, TSL2772_PRX_HI);
if (ret < 0)
goto prox_poll_err;
chip->prox_data = ret;
prox_poll_err:
mutex_unlock(&chip->prox_mutex);
return ret;
}
static int tsl2772_read_prox_led_current(struct tsl2772_chip *chip)
{
struct device *dev = &chip->client->dev;
int ret, tmp, i;
ret = device_property_read_u32(dev, "led-max-microamp", &tmp);
if (ret < 0)
return ret;
for (i = 0; tsl2772_led_currents[i][0] != 0; i++) {
if (tmp == tsl2772_led_currents[i][0]) {
chip->settings.prox_power = tsl2772_led_currents[i][1];
return 0;
}
}
dev_err(dev, "Invalid value %d for led-max-microamp\n", tmp);
return -EINVAL;
}
static int tsl2772_read_prox_diodes(struct tsl2772_chip *chip)
{
struct device *dev = &chip->client->dev;
int i, ret, num_leds, prox_diode_mask;
u32 leds[TSL2772_MAX_PROX_LEDS];
ret = device_property_count_u32(dev, "amstaos,proximity-diodes");
if (ret < 0)
return ret;
num_leds = ret;
if (num_leds > TSL2772_MAX_PROX_LEDS)
num_leds = TSL2772_MAX_PROX_LEDS;
ret = device_property_read_u32_array(dev, "amstaos,proximity-diodes", leds, num_leds);
if (ret < 0) {
dev_err(dev, "Invalid value for amstaos,proximity-diodes: %d.\n", ret);
return ret;
}
prox_diode_mask = 0;
for (i = 0; i < num_leds; i++) {
if (leds[i] == 0)
prox_diode_mask |= TSL2772_DIODE0;
else if (leds[i] == 1)
prox_diode_mask |= TSL2772_DIODE1;
else {
dev_err(dev, "Invalid value %d in amstaos,proximity-diodes.\n", leds[i]);
return -EINVAL;
}
}
chip->settings.prox_diode = prox_diode_mask;
return 0;
}
static void tsl2772_parse_dt(struct tsl2772_chip *chip)
{
tsl2772_read_prox_led_current(chip);
tsl2772_read_prox_diodes(chip);
}
/**
* tsl2772_defaults() - Populates the device nominal operating parameters
* with those provided by a 'platform' data struct or
* with prefined defaults.
*
* @chip: pointer to device structure.
*/
static void tsl2772_defaults(struct tsl2772_chip *chip)
{
/* If Operational settings defined elsewhere.. */
if (chip->pdata && chip->pdata->platform_default_settings)
memcpy(&chip->settings, chip->pdata->platform_default_settings,
sizeof(tsl2772_default_settings));
else
memcpy(&chip->settings, &tsl2772_default_settings,
sizeof(tsl2772_default_settings));
/* Load up the proper lux table. */
if (chip->pdata && chip->pdata->platform_lux_table[0].ch0 != 0)
memcpy(chip->tsl2772_device_lux,
chip->pdata->platform_lux_table,
sizeof(chip->pdata->platform_lux_table));
else
memcpy(chip->tsl2772_device_lux,
tsl2772_default_lux_table_group[chip->id],
TSL2772_DEFAULT_TABLE_BYTES);
tsl2772_parse_dt(chip);
}
/**
* tsl2772_als_calibrate() - Obtain single reading and calculate
* the als_gain_trim.
*
* @indio_dev: pointer to IIO device
*/
static int tsl2772_als_calibrate(struct iio_dev *indio_dev)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
int ret, lux_val;
ret = i2c_smbus_read_byte_data(chip->client,
TSL2772_CMD_REG | TSL2772_CNTRL);
if (ret < 0) {
dev_err(&chip->client->dev,
"%s: failed to read from the CNTRL register\n",
__func__);
return ret;
}
if ((ret & (TSL2772_CNTL_ADC_ENBL | TSL2772_CNTL_PWR_ON))
!= (TSL2772_CNTL_ADC_ENBL | TSL2772_CNTL_PWR_ON)) {
dev_err(&chip->client->dev,
"%s: Device is not powered on and/or ADC is not enabled\n",
__func__);
return -EINVAL;
} else if ((ret & TSL2772_STA_ADC_VALID) != TSL2772_STA_ADC_VALID) {
dev_err(&chip->client->dev,
"%s: The two ADC channels have not completed an integration cycle\n",
__func__);
return -ENODATA;
}
lux_val = tsl2772_get_lux(indio_dev);
if (lux_val < 0) {
dev_err(&chip->client->dev,
"%s: failed to get lux\n", __func__);
return lux_val;
}
if (lux_val == 0)
return -ERANGE;
ret = (chip->settings.als_cal_target * chip->settings.als_gain_trim) /
lux_val;
if (ret < TSL2772_ALS_GAIN_TRIM_MIN || ret > TSL2772_ALS_GAIN_TRIM_MAX)
return -ERANGE;
chip->settings.als_gain_trim = ret;
return ret;
}
static void tsl2772_disable_regulators_action(void *_data)
{
struct tsl2772_chip *chip = _data;
regulator_bulk_disable(ARRAY_SIZE(chip->supplies), chip->supplies);
}
static int tsl2772_chip_on(struct iio_dev *indio_dev)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
int ret, i, als_count, als_time_us;
u8 *dev_reg, reg_val;
/* Non calculated parameters */
chip->tsl2772_config[TSL2772_ALS_TIME] = chip->settings.als_time;
chip->tsl2772_config[TSL2772_PRX_TIME] = chip->settings.prox_time;
chip->tsl2772_config[TSL2772_WAIT_TIME] = chip->settings.wait_time;
chip->tsl2772_config[TSL2772_ALS_PRX_CONFIG] =
chip->settings.als_prox_config;
chip->tsl2772_config[TSL2772_ALS_MINTHRESHLO] =
(chip->settings.als_thresh_low) & 0xFF;
chip->tsl2772_config[TSL2772_ALS_MINTHRESHHI] =
(chip->settings.als_thresh_low >> 8) & 0xFF;
chip->tsl2772_config[TSL2772_ALS_MAXTHRESHLO] =
(chip->settings.als_thresh_high) & 0xFF;
chip->tsl2772_config[TSL2772_ALS_MAXTHRESHHI] =
(chip->settings.als_thresh_high >> 8) & 0xFF;
chip->tsl2772_config[TSL2772_PERSISTENCE] =
(chip->settings.prox_persistence & 0xFF) << 4 |
(chip->settings.als_persistence & 0xFF);
chip->tsl2772_config[TSL2772_PRX_COUNT] =
chip->settings.prox_pulse_count;
chip->tsl2772_config[TSL2772_PRX_MINTHRESHLO] =
(chip->settings.prox_thres_low) & 0xFF;
chip->tsl2772_config[TSL2772_PRX_MINTHRESHHI] =
(chip->settings.prox_thres_low >> 8) & 0xFF;
chip->tsl2772_config[TSL2772_PRX_MAXTHRESHLO] =
(chip->settings.prox_thres_high) & 0xFF;
chip->tsl2772_config[TSL2772_PRX_MAXTHRESHHI] =
(chip->settings.prox_thres_high >> 8) & 0xFF;
/* and make sure we're not already on */
if (chip->tsl2772_chip_status == TSL2772_CHIP_WORKING) {
/* if forcing a register update - turn off, then on */
dev_info(&chip->client->dev, "device is already enabled\n");
return -EINVAL;
}
/* Set the gain based on tsl2772_settings struct */
chip->tsl2772_config[TSL2772_GAIN] =
(chip->settings.als_gain & 0xFF) |
((chip->settings.prox_gain & 0xFF) << 2) |
(chip->settings.prox_diode << 4) |
(chip->settings.prox_power << 6);
/* set chip time scaling and saturation */
als_count = 256 - chip->settings.als_time;
als_time_us = als_count * tsl2772_int_time_avail[chip->id][3];
chip->als_saturation = als_count * 768; /* 75% of full scale */
chip->als_gain_time_scale = als_time_us *
tsl2772_als_gain[chip->settings.als_gain];
/*
* TSL2772 Specific power-on / adc enable sequence
* Power on the device 1st.
*/
ret = tsl2772_write_control_reg(chip, TSL2772_CNTL_PWR_ON);
if (ret < 0)
return ret;
/*
* Use the following shadow copy for our delay before enabling ADC.
* Write all the registers.
*/
for (i = 0, dev_reg = chip->tsl2772_config;
i < TSL2772_MAX_CONFIG_REG; i++) {
int reg = TSL2772_CMD_REG + i;
ret = i2c_smbus_write_byte_data(chip->client, reg,
*dev_reg++);
if (ret < 0) {
dev_err(&chip->client->dev,
"%s: failed to write to register %x: %d\n",
__func__, reg, ret);
return ret;
}
}
/* Power-on settling time */
usleep_range(3000, 3500);
reg_val = TSL2772_CNTL_PWR_ON | TSL2772_CNTL_ADC_ENBL |
TSL2772_CNTL_PROX_DET_ENBL;
if (chip->settings.als_interrupt_en)
reg_val |= TSL2772_CNTL_ALS_INT_ENBL;
if (chip->settings.prox_interrupt_en)
reg_val |= TSL2772_CNTL_PROX_INT_ENBL;
ret = tsl2772_write_control_reg(chip, reg_val);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte(chip->client,
TSL2772_CMD_REG | TSL2772_CMD_SPL_FN |
TSL2772_CMD_PROXALS_INT_CLR);
if (ret < 0) {
dev_err(&chip->client->dev,
"%s: failed to clear interrupt status: %d\n",
__func__, ret);
return ret;
}
chip->tsl2772_chip_status = TSL2772_CHIP_WORKING;
return ret;
}
static int tsl2772_chip_off(struct iio_dev *indio_dev)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
/* turn device off */
chip->tsl2772_chip_status = TSL2772_CHIP_SUSPENDED;
return tsl2772_write_control_reg(chip, 0x00);
}
static void tsl2772_chip_off_action(void *data)
{
struct iio_dev *indio_dev = data;
tsl2772_chip_off(indio_dev);
}
/**
* tsl2772_invoke_change - power cycle the device to implement the user
* parameters
* @indio_dev: pointer to IIO device
*
* Obtain and lock both ALS and PROX resources, determine and save device state
* (On/Off), cycle device to implement updated parameter, put device back into
* proper state, and unlock resource.
*/
static int tsl2772_invoke_change(struct iio_dev *indio_dev)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
int device_status = chip->tsl2772_chip_status;
int ret;
mutex_lock(&chip->als_mutex);
mutex_lock(&chip->prox_mutex);
if (device_status == TSL2772_CHIP_WORKING) {
ret = tsl2772_chip_off(indio_dev);
if (ret < 0)
goto unlock;
}
ret = tsl2772_chip_on(indio_dev);
unlock:
mutex_unlock(&chip->prox_mutex);
mutex_unlock(&chip->als_mutex);
return ret;
}
static int tsl2772_prox_cal(struct iio_dev *indio_dev)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
int prox_history[MAX_SAMPLES_CAL + 1];
int i, ret, mean, max, sample_sum;
if (chip->settings.prox_max_samples_cal < 1 ||
chip->settings.prox_max_samples_cal > MAX_SAMPLES_CAL)
return -EINVAL;
for (i = 0; i < chip->settings.prox_max_samples_cal; i++) {
usleep_range(15000, 17500);
ret = tsl2772_get_prox(indio_dev);
if (ret < 0)
return ret;
prox_history[i] = chip->prox_data;
}
sample_sum = 0;
max = INT_MIN;
for (i = 0; i < chip->settings.prox_max_samples_cal; i++) {
sample_sum += prox_history[i];
max = max(max, prox_history[i]);
}
mean = sample_sum / chip->settings.prox_max_samples_cal;
chip->settings.prox_thres_high = (max << 1) - mean;
return tsl2772_invoke_change(indio_dev);
}
static int tsl2772_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_CALIBSCALE:
if (chan->type == IIO_INTENSITY) {
*length = ARRAY_SIZE(tsl2772_int_calibscale_avail);
*vals = tsl2772_int_calibscale_avail;
} else {
*length = ARRAY_SIZE(tsl2772_prox_calibscale_avail);
*vals = tsl2772_prox_calibscale_avail;
}
*type = IIO_VAL_INT;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_INT_TIME:
*length = ARRAY_SIZE(tsl2772_int_time_avail[chip->id]);
*vals = tsl2772_int_time_avail[chip->id];
*type = IIO_VAL_INT_PLUS_MICRO;
return IIO_AVAIL_RANGE;
}
return -EINVAL;
}
static ssize_t in_illuminance0_target_input_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct tsl2772_chip *chip = iio_priv(dev_to_iio_dev(dev));
return scnprintf(buf, PAGE_SIZE, "%d\n", chip->settings.als_cal_target);
}
static ssize_t in_illuminance0_target_input_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct tsl2772_chip *chip = iio_priv(indio_dev);
u16 value;
int ret;
if (kstrtou16(buf, 0, &value))
return -EINVAL;
chip->settings.als_cal_target = value;
ret = tsl2772_invoke_change(indio_dev);
if (ret < 0)
return ret;
return len;
}
static ssize_t in_illuminance0_calibrate_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
bool value;
int ret;
if (kstrtobool(buf, &value) || !value)
return -EINVAL;
ret = tsl2772_als_calibrate(indio_dev);
if (ret < 0)
return ret;
ret = tsl2772_invoke_change(indio_dev);
if (ret < 0)
return ret;
return len;
}
static ssize_t in_illuminance0_lux_table_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct tsl2772_chip *chip = iio_priv(dev_to_iio_dev(dev));
int i = 0;
int offset = 0;
while (i < TSL2772_MAX_LUX_TABLE_SIZE) {
offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%u,%u,",
chip->tsl2772_device_lux[i].ch0,
chip->tsl2772_device_lux[i].ch1);
if (chip->tsl2772_device_lux[i].ch0 == 0) {
/*
* We just printed the first "0" entry.
* Now get rid of the extra "," and break.
*/
offset--;
break;
}
i++;
}
offset += scnprintf(buf + offset, PAGE_SIZE - offset, "\n");
return offset;
}
static ssize_t in_illuminance0_lux_table_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct tsl2772_chip *chip = iio_priv(indio_dev);
int value[ARRAY_SIZE(chip->tsl2772_device_lux) * 2 + 1];
int n, ret;
get_options(buf, ARRAY_SIZE(value), value);
/*
* We now have an array of ints starting at value[1], and
* enumerated by value[0].
* We expect each group of two ints to be one table entry,
* and the last table entry is all 0.
*/
n = value[0];
if ((n % 2) || n < 4 ||
n > ((ARRAY_SIZE(chip->tsl2772_device_lux) - 1) * 2))
return -EINVAL;
if ((value[(n - 1)] | value[n]) != 0)
return -EINVAL;
if (chip->tsl2772_chip_status == TSL2772_CHIP_WORKING) {
ret = tsl2772_chip_off(indio_dev);
if (ret < 0)
return ret;
}
/* Zero out the table */
memset(chip->tsl2772_device_lux, 0, sizeof(chip->tsl2772_device_lux));
memcpy(chip->tsl2772_device_lux, &value[1], (value[0] * 4));
ret = tsl2772_invoke_change(indio_dev);
if (ret < 0)
return ret;
return len;
}
static ssize_t in_proximity0_calibrate_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
bool value;
int ret;
if (kstrtobool(buf, &value) || !value)
return -EINVAL;
ret = tsl2772_prox_cal(indio_dev);
if (ret < 0)
return ret;
ret = tsl2772_invoke_change(indio_dev);
if (ret < 0)
return ret;
return len;
}
static int tsl2772_read_interrupt_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
if (chan->type == IIO_INTENSITY)
return chip->settings.als_interrupt_en;
else
return chip->settings.prox_interrupt_en;
}
static int tsl2772_write_interrupt_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int val)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
if (chan->type == IIO_INTENSITY)
chip->settings.als_interrupt_en = val ? true : false;
else
chip->settings.prox_interrupt_en = val ? true : false;
return tsl2772_invoke_change(indio_dev);
}
static int tsl2772_write_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
int ret = -EINVAL, count, persistence;
u8 time;
switch (info) {
case IIO_EV_INFO_VALUE:
if (chan->type == IIO_INTENSITY) {
switch (dir) {
case IIO_EV_DIR_RISING:
chip->settings.als_thresh_high = val;
ret = 0;
break;
case IIO_EV_DIR_FALLING:
chip->settings.als_thresh_low = val;
ret = 0;
break;
default:
break;
}
} else {
switch (dir) {
case IIO_EV_DIR_RISING:
chip->settings.prox_thres_high = val;
ret = 0;
break;
case IIO_EV_DIR_FALLING:
chip->settings.prox_thres_low = val;
ret = 0;
break;
default:
break;
}
}
break;
case IIO_EV_INFO_PERIOD:
if (chan->type == IIO_INTENSITY)
time = chip->settings.als_time;
else
time = chip->settings.prox_time;
count = 256 - time;
persistence = ((val * 1000000) + val2) /
(count * tsl2772_int_time_avail[chip->id][3]);
if (chan->type == IIO_INTENSITY) {
/* ALS filter values are 1, 2, 3, 5, 10, 15, ..., 60 */
if (persistence > 3)
persistence = (persistence / 5) + 3;
chip->settings.als_persistence = persistence;
} else {
chip->settings.prox_persistence = persistence;
}
ret = 0;
break;
default:
break;
}
if (ret < 0)
return ret;
return tsl2772_invoke_change(indio_dev);
}
static int tsl2772_read_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
int filter_delay, persistence;
u8 time;
switch (info) {
case IIO_EV_INFO_VALUE:
if (chan->type == IIO_INTENSITY) {
switch (dir) {
case IIO_EV_DIR_RISING:
*val = chip->settings.als_thresh_high;
return IIO_VAL_INT;
case IIO_EV_DIR_FALLING:
*val = chip->settings.als_thresh_low;
return IIO_VAL_INT;
default:
return -EINVAL;
}
} else {
switch (dir) {
case IIO_EV_DIR_RISING:
*val = chip->settings.prox_thres_high;
return IIO_VAL_INT;
case IIO_EV_DIR_FALLING:
*val = chip->settings.prox_thres_low;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
break;
case IIO_EV_INFO_PERIOD:
if (chan->type == IIO_INTENSITY) {
time = chip->settings.als_time;
persistence = chip->settings.als_persistence;
/* ALS filter values are 1, 2, 3, 5, 10, 15, ..., 60 */
if (persistence > 3)
persistence = (persistence - 3) * 5;
} else {
time = chip->settings.prox_time;
persistence = chip->settings.prox_persistence;
}
filter_delay = persistence * (256 - time) *
tsl2772_int_time_avail[chip->id][3];
*val = filter_delay / 1000000;
*val2 = filter_delay % 1000000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int tsl2772_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_LIGHT:
tsl2772_get_lux(indio_dev);
*val = chip->als_cur_info.lux;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_INTENSITY:
tsl2772_get_lux(indio_dev);
if (chan->channel == 0)
*val = chip->als_cur_info.als_ch0;
else
*val = chip->als_cur_info.als_ch1;
return IIO_VAL_INT;
case IIO_PROXIMITY:
tsl2772_get_prox(indio_dev);
*val = chip->prox_data;
return IIO_VAL_INT;
default:
return -EINVAL;
}
break;
case IIO_CHAN_INFO_CALIBSCALE:
if (chan->type == IIO_LIGHT)
*val = tsl2772_als_gain[chip->settings.als_gain];
else
*val = tsl2772_prox_gain[chip->settings.prox_gain];
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBBIAS:
*val = chip->settings.als_gain_trim;
return IIO_VAL_INT;
case IIO_CHAN_INFO_INT_TIME:
*val = 0;
*val2 = (256 - chip->settings.als_time) *
tsl2772_int_time_avail[chip->id][3];
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int tsl2772_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct tsl2772_chip *chip = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_CALIBSCALE:
if (chan->type == IIO_INTENSITY) {
switch (val) {
case 1:
chip->settings.als_gain = 0;
break;
case 8:
chip->settings.als_gain = 1;
break;
case 16:
chip->settings.als_gain = 2;
break;
case 120:
chip->settings.als_gain = 3;
break;
default:
return -EINVAL;
}
} else {
switch (val) {
case 1:
chip->settings.prox_gain = 0;
break;
case 2:
chip->settings.prox_gain = 1;
break;
case 4:
chip->settings.prox_gain = 2;
break;
case 8:
chip->settings.prox_gain = 3;
break;
default:
return -EINVAL;
}
}
break;
case IIO_CHAN_INFO_CALIBBIAS:
if (val < TSL2772_ALS_GAIN_TRIM_MIN ||
val > TSL2772_ALS_GAIN_TRIM_MAX)
return -EINVAL;
chip->settings.als_gain_trim = val;
break;
case IIO_CHAN_INFO_INT_TIME:
if (val != 0 || val2 < tsl2772_int_time_avail[chip->id][1] ||
val2 > tsl2772_int_time_avail[chip->id][5])
return -EINVAL;
chip->settings.als_time = 256 -
(val2 / tsl2772_int_time_avail[chip->id][3]);
break;
default:
return -EINVAL;
}
return tsl2772_invoke_change(indio_dev);
}
static DEVICE_ATTR_RW(in_illuminance0_target_input);
static DEVICE_ATTR_WO(in_illuminance0_calibrate);
static DEVICE_ATTR_WO(in_proximity0_calibrate);
static DEVICE_ATTR_RW(in_illuminance0_lux_table);
/* Use the default register values to identify the Taos device */
static int tsl2772_device_id_verif(int id, int target)
{
switch (target) {
case tsl2571:
case tsl2671:
case tsl2771:
return (id & 0xf0) == TRITON_ID;
case tmd2671:
case tmd2771:
return (id & 0xf0) == HALIBUT_ID;
case tsl2572:
case tsl2672:
case tmd2672:
case tsl2772:
case tmd2772:
case apds9930:
return (id & 0xf0) == SWORDFISH_ID;
}
return -EINVAL;
}
static irqreturn_t tsl2772_event_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct tsl2772_chip *chip = iio_priv(indio_dev);
s64 timestamp = iio_get_time_ns(indio_dev);
int ret;
ret = tsl2772_read_status(chip);
if (ret < 0)
return IRQ_HANDLED;
/* What type of interrupt do we need to process */
if (ret & TSL2772_STA_PRX_INTR) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY,
0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
timestamp);
}
if (ret & TSL2772_STA_ALS_INTR) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_LIGHT,
0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
timestamp);
}
ret = i2c_smbus_write_byte(chip->client,
TSL2772_CMD_REG | TSL2772_CMD_SPL_FN |
TSL2772_CMD_PROXALS_INT_CLR);
if (ret < 0)
dev_err(&chip->client->dev,
"%s: failed to clear interrupt status: %d\n",
__func__, ret);
return IRQ_HANDLED;
}
static struct attribute *tsl2772_ALS_device_attrs[] = {
&dev_attr_in_illuminance0_target_input.attr,
&dev_attr_in_illuminance0_calibrate.attr,
&dev_attr_in_illuminance0_lux_table.attr,
NULL
};
static struct attribute *tsl2772_PRX_device_attrs[] = {
&dev_attr_in_proximity0_calibrate.attr,
NULL
};
static struct attribute *tsl2772_ALSPRX_device_attrs[] = {
&dev_attr_in_illuminance0_target_input.attr,
&dev_attr_in_illuminance0_calibrate.attr,
&dev_attr_in_illuminance0_lux_table.attr,
NULL
};
static struct attribute *tsl2772_PRX2_device_attrs[] = {
&dev_attr_in_proximity0_calibrate.attr,
NULL
};
static struct attribute *tsl2772_ALSPRX2_device_attrs[] = {
&dev_attr_in_illuminance0_target_input.attr,
&dev_attr_in_illuminance0_calibrate.attr,
&dev_attr_in_illuminance0_lux_table.attr,
&dev_attr_in_proximity0_calibrate.attr,
NULL
};
static const struct attribute_group tsl2772_device_attr_group_tbl[] = {
[ALS] = {
.attrs = tsl2772_ALS_device_attrs,
},
[PRX] = {
.attrs = tsl2772_PRX_device_attrs,
},
[ALSPRX] = {
.attrs = tsl2772_ALSPRX_device_attrs,
},
[PRX2] = {
.attrs = tsl2772_PRX2_device_attrs,
},
[ALSPRX2] = {
.attrs = tsl2772_ALSPRX2_device_attrs,
},
};
#define TSL2772_DEVICE_INFO(type)[type] = \
{ \
.attrs = &tsl2772_device_attr_group_tbl[type], \
.read_raw = &tsl2772_read_raw, \
.read_avail = &tsl2772_read_avail, \
.write_raw = &tsl2772_write_raw, \
.read_event_value = &tsl2772_read_event_value, \
.write_event_value = &tsl2772_write_event_value, \
.read_event_config = &tsl2772_read_interrupt_config, \
.write_event_config = &tsl2772_write_interrupt_config, \
}
static const struct iio_info tsl2772_device_info[] = {
TSL2772_DEVICE_INFO(ALS),
TSL2772_DEVICE_INFO(PRX),
TSL2772_DEVICE_INFO(ALSPRX),
TSL2772_DEVICE_INFO(PRX2),
TSL2772_DEVICE_INFO(ALSPRX2),
};
static const struct iio_event_spec tsl2772_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_PERIOD) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct tsl2772_chip_info tsl2772_chip_info_tbl[] = {
[ALS] = {
.channel_with_events = {
{
.type = IIO_LIGHT,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
.event_spec = tsl2772_events,
.num_event_specs = ARRAY_SIZE(tsl2772_events),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 1,
},
},
.channel_without_events = {
{
.type = IIO_LIGHT,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 1,
},
},
.chan_table_elements = 3,
.info = &tsl2772_device_info[ALS],
},
[PRX] = {
.channel_with_events = {
{
.type = IIO_PROXIMITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.event_spec = tsl2772_events,
.num_event_specs = ARRAY_SIZE(tsl2772_events),
},
},
.channel_without_events = {
{
.type = IIO_PROXIMITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
},
},
.chan_table_elements = 1,
.info = &tsl2772_device_info[PRX],
},
[ALSPRX] = {
.channel_with_events = {
{
.type = IIO_LIGHT,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
.event_spec = tsl2772_events,
.num_event_specs = ARRAY_SIZE(tsl2772_events),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
}, {
.type = IIO_PROXIMITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.event_spec = tsl2772_events,
.num_event_specs = ARRAY_SIZE(tsl2772_events),
},
},
.channel_without_events = {
{
.type = IIO_LIGHT,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
}, {
.type = IIO_PROXIMITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
},
},
.chan_table_elements = 4,
.info = &tsl2772_device_info[ALSPRX],
},
[PRX2] = {
.channel_with_events = {
{
.type = IIO_PROXIMITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_CALIBSCALE),
.event_spec = tsl2772_events,
.num_event_specs = ARRAY_SIZE(tsl2772_events),
},
},
.channel_without_events = {
{
.type = IIO_PROXIMITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_CALIBSCALE),
},
},
.chan_table_elements = 1,
.info = &tsl2772_device_info[PRX2],
},
[ALSPRX2] = {
.channel_with_events = {
{
.type = IIO_LIGHT,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
.event_spec = tsl2772_events,
.num_event_specs = ARRAY_SIZE(tsl2772_events),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
}, {
.type = IIO_PROXIMITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_CALIBSCALE),
.event_spec = tsl2772_events,
.num_event_specs = ARRAY_SIZE(tsl2772_events),
},
},
.channel_without_events = {
{
.type = IIO_LIGHT,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_CALIBBIAS),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
}, {
.type = IIO_INTENSITY,
.indexed = 1,
.channel = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
}, {
.type = IIO_PROXIMITY,
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_CALIBSCALE),
},
},
.chan_table_elements = 4,
.info = &tsl2772_device_info[ALSPRX2],
},
};
static int tsl2772_probe(struct i2c_client *clientp)
{
const struct i2c_device_id *id = i2c_client_get_device_id(clientp);
struct iio_dev *indio_dev;
struct tsl2772_chip *chip;
int ret;
indio_dev = devm_iio_device_alloc(&clientp->dev, sizeof(*chip));
if (!indio_dev)
return -ENOMEM;
chip = iio_priv(indio_dev);
chip->client = clientp;
i2c_set_clientdata(clientp, indio_dev);
chip->supplies[TSL2772_SUPPLY_VDD].supply = "vdd";
chip->supplies[TSL2772_SUPPLY_VDDIO].supply = "vddio";
ret = devm_regulator_bulk_get(&clientp->dev,
ARRAY_SIZE(chip->supplies),
chip->supplies);
if (ret < 0)
return dev_err_probe(&clientp->dev, ret, "Failed to get regulators\n");
ret = regulator_bulk_enable(ARRAY_SIZE(chip->supplies), chip->supplies);
if (ret < 0) {
dev_err(&clientp->dev, "Failed to enable regulators: %d\n",
ret);
return ret;
}
ret = devm_add_action_or_reset(&clientp->dev,
tsl2772_disable_regulators_action,
chip);
if (ret < 0) {
dev_err(&clientp->dev, "Failed to setup regulator cleanup action %d\n",
ret);
return ret;
}
usleep_range(TSL2772_BOOT_MIN_SLEEP_TIME, TSL2772_BOOT_MAX_SLEEP_TIME);
ret = i2c_smbus_read_byte_data(chip->client,
TSL2772_CMD_REG | TSL2772_CHIPID);
if (ret < 0)
return ret;
if (tsl2772_device_id_verif(ret, id->driver_data) <= 0) {
dev_info(&chip->client->dev,
"%s: i2c device found does not match expected id\n",
__func__);
return -EINVAL;
}
ret = i2c_smbus_write_byte(clientp, TSL2772_CMD_REG | TSL2772_CNTRL);
if (ret < 0) {
dev_err(&clientp->dev,
"%s: Failed to write to CMD register: %d\n",
__func__, ret);
return ret;
}
mutex_init(&chip->als_mutex);
mutex_init(&chip->prox_mutex);
chip->tsl2772_chip_status = TSL2772_CHIP_UNKNOWN;
chip->pdata = dev_get_platdata(&clientp->dev);
chip->id = id->driver_data;
chip->chip_info =
&tsl2772_chip_info_tbl[device_channel_config[id->driver_data]];
indio_dev->info = chip->chip_info->info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->name = chip->client->name;
indio_dev->num_channels = chip->chip_info->chan_table_elements;
if (clientp->irq) {
indio_dev->channels = chip->chip_info->channel_with_events;
ret = devm_request_threaded_irq(&clientp->dev, clientp->irq,
NULL,
&tsl2772_event_handler,
IRQF_TRIGGER_FALLING |
IRQF_ONESHOT,
"TSL2772_event",
indio_dev);
if (ret) {
dev_err(&clientp->dev,
"%s: irq request failed\n", __func__);
return ret;
}
} else {
indio_dev->channels = chip->chip_info->channel_without_events;
}
tsl2772_defaults(chip);
ret = tsl2772_chip_on(indio_dev);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&clientp->dev,
tsl2772_chip_off_action,
indio_dev);
if (ret < 0)
return ret;
return devm_iio_device_register(&clientp->dev, indio_dev);
}
static int tsl2772_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct tsl2772_chip *chip = iio_priv(indio_dev);
int ret;
ret = tsl2772_chip_off(indio_dev);
regulator_bulk_disable(ARRAY_SIZE(chip->supplies), chip->supplies);
return ret;
}
static int tsl2772_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct tsl2772_chip *chip = iio_priv(indio_dev);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(chip->supplies), chip->supplies);
if (ret < 0)
return ret;
usleep_range(TSL2772_BOOT_MIN_SLEEP_TIME, TSL2772_BOOT_MAX_SLEEP_TIME);
return tsl2772_chip_on(indio_dev);
}
static const struct i2c_device_id tsl2772_idtable[] = {
{ "tsl2571", tsl2571 },
{ "tsl2671", tsl2671 },
{ "tmd2671", tmd2671 },
{ "tsl2771", tsl2771 },
{ "tmd2771", tmd2771 },
{ "tsl2572", tsl2572 },
{ "tsl2672", tsl2672 },
{ "tmd2672", tmd2672 },
{ "tsl2772", tsl2772 },
{ "tmd2772", tmd2772 },
{ "apds9930", apds9930 },
{}
};
MODULE_DEVICE_TABLE(i2c, tsl2772_idtable);
static const struct of_device_id tsl2772_of_match[] = {
{ .compatible = "amstaos,tsl2571" },
{ .compatible = "amstaos,tsl2671" },
{ .compatible = "amstaos,tmd2671" },
{ .compatible = "amstaos,tsl2771" },
{ .compatible = "amstaos,tmd2771" },
{ .compatible = "amstaos,tsl2572" },
{ .compatible = "amstaos,tsl2672" },
{ .compatible = "amstaos,tmd2672" },
{ .compatible = "amstaos,tsl2772" },
{ .compatible = "amstaos,tmd2772" },
{ .compatible = "avago,apds9930" },
{}
};
MODULE_DEVICE_TABLE(of, tsl2772_of_match);
static const struct dev_pm_ops tsl2772_pm_ops = {
.suspend = tsl2772_suspend,
.resume = tsl2772_resume,
};
static struct i2c_driver tsl2772_driver = {
.driver = {
.name = "tsl2772",
.of_match_table = tsl2772_of_match,
.pm = &tsl2772_pm_ops,
},
.id_table = tsl2772_idtable,
.probe = tsl2772_probe,
};
module_i2c_driver(tsl2772_driver);
MODULE_AUTHOR("J. August Brenner <[email protected]>");
MODULE_AUTHOR("Brian Masney <[email protected]>");
MODULE_DESCRIPTION("TAOS tsl2772 ambient and proximity light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/tsl2772.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2021 Joe Sandom <[email protected]>
*
* Datasheet: https://ams.com/tsl25911#tab/documents
*
* Device driver for the TAOS TSL2591. This is a very-high sensitivity
* light-to-digital converter that transforms light intensity into a digital
* signal.
*/
#include <linux/bitfield.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/pm_runtime.h>
#include <linux/sysfs.h>
#include <asm/unaligned.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
/* ADC integration time, field value to time in ms */
#define TSL2591_FVAL_TO_MSEC(x) (((x) + 1) * 100)
/* ADC integration time, field value to time in seconds */
#define TSL2591_FVAL_TO_SEC(x) ((x) + 1)
/* ADC integration time, time in seconds to field value */
#define TSL2591_SEC_TO_FVAL(x) ((x) - 1)
/* TSL2591 register set */
#define TSL2591_ENABLE 0x00
#define TSL2591_CONTROL 0x01
#define TSL2591_AILTL 0x04
#define TSL2591_AILTH 0x05
#define TSL2591_AIHTL 0x06
#define TSL2591_AIHTH 0x07
#define TSL2591_NP_AILTL 0x08
#define TSL2591_NP_AILTH 0x09
#define TSL2591_NP_AIHTL 0x0A
#define TSL2591_NP_AIHTH 0x0B
#define TSL2591_PERSIST 0x0C
#define TSL2591_PACKAGE_ID 0x11
#define TSL2591_DEVICE_ID 0x12
#define TSL2591_STATUS 0x13
#define TSL2591_C0_DATAL 0x14
#define TSL2591_C0_DATAH 0x15
#define TSL2591_C1_DATAL 0x16
#define TSL2591_C1_DATAH 0x17
/* TSL2591 command register definitions */
#define TSL2591_CMD_NOP 0xA0
#define TSL2591_CMD_SF_INTSET 0xE4
#define TSL2591_CMD_SF_CALS_I 0xE5
#define TSL2591_CMD_SF_CALS_NPI 0xE7
#define TSL2591_CMD_SF_CNP_ALSI 0xEA
/* TSL2591 enable register definitions */
#define TSL2591_PWR_ON 0x01
#define TSL2591_PWR_OFF 0x00
#define TSL2591_ENABLE_ALS 0x02
#define TSL2591_ENABLE_ALS_INT 0x10
#define TSL2591_ENABLE_SLEEP_INT 0x40
#define TSL2591_ENABLE_NP_INT 0x80
/* TSL2591 control register definitions */
#define TSL2591_CTRL_ALS_INTEGRATION_100MS 0x00
#define TSL2591_CTRL_ALS_INTEGRATION_200MS 0x01
#define TSL2591_CTRL_ALS_INTEGRATION_300MS 0x02
#define TSL2591_CTRL_ALS_INTEGRATION_400MS 0x03
#define TSL2591_CTRL_ALS_INTEGRATION_500MS 0x04
#define TSL2591_CTRL_ALS_INTEGRATION_600MS 0x05
#define TSL2591_CTRL_ALS_LOW_GAIN 0x00
#define TSL2591_CTRL_ALS_MED_GAIN 0x10
#define TSL2591_CTRL_ALS_HIGH_GAIN 0x20
#define TSL2591_CTRL_ALS_MAX_GAIN 0x30
#define TSL2591_CTRL_SYS_RESET 0x80
/* TSL2591 persist register definitions */
#define TSL2591_PRST_ALS_INT_CYCLE_0 0x00
#define TSL2591_PRST_ALS_INT_CYCLE_ANY 0x01
#define TSL2591_PRST_ALS_INT_CYCLE_2 0x02
#define TSL2591_PRST_ALS_INT_CYCLE_3 0x03
#define TSL2591_PRST_ALS_INT_CYCLE_5 0x04
#define TSL2591_PRST_ALS_INT_CYCLE_10 0x05
#define TSL2591_PRST_ALS_INT_CYCLE_15 0x06
#define TSL2591_PRST_ALS_INT_CYCLE_20 0x07
#define TSL2591_PRST_ALS_INT_CYCLE_25 0x08
#define TSL2591_PRST_ALS_INT_CYCLE_30 0x09
#define TSL2591_PRST_ALS_INT_CYCLE_35 0x0A
#define TSL2591_PRST_ALS_INT_CYCLE_40 0x0B
#define TSL2591_PRST_ALS_INT_CYCLE_45 0x0C
#define TSL2591_PRST_ALS_INT_CYCLE_50 0x0D
#define TSL2591_PRST_ALS_INT_CYCLE_55 0x0E
#define TSL2591_PRST_ALS_INT_CYCLE_60 0x0F
#define TSL2591_PRST_ALS_INT_CYCLE_MAX (BIT(4) - 1)
/* TSL2591 PID register mask */
#define TSL2591_PACKAGE_ID_MASK GENMASK(5, 4)
/* TSL2591 ID register mask */
#define TSL2591_DEVICE_ID_MASK GENMASK(7, 0)
/* TSL2591 status register masks */
#define TSL2591_STS_ALS_VALID_MASK BIT(0)
#define TSL2591_STS_ALS_INT_MASK BIT(4)
#define TSL2591_STS_NPERS_INT_MASK BIT(5)
#define TSL2591_STS_VAL_HIGH_MASK BIT(0)
/* TSL2591 constant values */
#define TSL2591_PACKAGE_ID_VAL 0x00
#define TSL2591_DEVICE_ID_VAL 0x50
/* Power off suspend delay time MS */
#define TSL2591_POWER_OFF_DELAY_MS 2000
/* TSL2591 default values */
#define TSL2591_DEFAULT_ALS_INT_TIME TSL2591_CTRL_ALS_INTEGRATION_300MS
#define TSL2591_DEFAULT_ALS_GAIN TSL2591_CTRL_ALS_MED_GAIN
#define TSL2591_DEFAULT_ALS_PERSIST TSL2591_PRST_ALS_INT_CYCLE_ANY
#define TSL2591_DEFAULT_ALS_LOWER_THRESH 100
#define TSL2591_DEFAULT_ALS_UPPER_THRESH 1500
/* TSL2591 number of data registers */
#define TSL2591_NUM_DATA_REGISTERS 4
/* TSL2591 number of valid status reads on ADC complete */
#define TSL2591_ALS_STS_VALID_COUNT 10
/* TSL2591 delay period between polls when checking for ALS valid flag */
#define TSL2591_DELAY_PERIOD_US 10000
/* TSL2591 maximum values */
#define TSL2591_MAX_ALS_INT_TIME_MS 600
#define TSL2591_ALS_MAX_VALUE (BIT(16) - 1)
/*
* LUX calculations;
* AGAIN values from Adafruit's TSL2591 Arduino library
* https://github.com/adafruit/Adafruit_TSL2591_Library
*/
#define TSL2591_CTRL_ALS_LOW_GAIN_MULTIPLIER 1
#define TSL2591_CTRL_ALS_MED_GAIN_MULTIPLIER 25
#define TSL2591_CTRL_ALS_HIGH_GAIN_MULTIPLIER 428
#define TSL2591_CTRL_ALS_MAX_GAIN_MULTIPLIER 9876
#define TSL2591_LUX_COEFFICIENT 408
struct tsl2591_als_settings {
u16 als_lower_thresh;
u16 als_upper_thresh;
u8 als_int_time;
u8 als_persist;
u8 als_gain;
};
struct tsl2591_chip {
struct tsl2591_als_settings als_settings;
struct i2c_client *client;
/*
* Keep als_settings in sync with hardware state
* and ensure multiple readers are serialized.
*/
struct mutex als_mutex;
bool events_enabled;
};
/*
* Period table is ALS persist cycle x integration time setting
* Integration times: 100ms, 200ms, 300ms, 400ms, 500ms, 600ms
* ALS cycles: 1, 2, 3, 5, 10, 20, 25, 30, 35, 40, 45, 50, 55, 60
*/
static const char * const tsl2591_als_period_list[] = {
"0.1 0.2 0.3 0.5 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0",
"0.2 0.4 0.6 1.0 2.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0",
"0.3 0.6 0.9 1.5 3.0 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5 18.0",
"0.4 0.8 1.2 2.0 4.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0",
"0.5 1.0 1.5 2.5 5.0 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0",
"0.6 1.2 1.8 3.0 6.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0 33.0 36.0",
};
static const int tsl2591_int_time_available[] = {
1, 2, 3, 4, 5, 6,
};
static const int tsl2591_calibscale_available[] = {
1, 25, 428, 9876,
};
static int tsl2591_set_als_lower_threshold(struct tsl2591_chip *chip,
u16 als_lower_threshold);
static int tsl2591_set_als_upper_threshold(struct tsl2591_chip *chip,
u16 als_upper_threshold);
static int tsl2591_gain_to_multiplier(const u8 als_gain)
{
switch (als_gain) {
case TSL2591_CTRL_ALS_LOW_GAIN:
return TSL2591_CTRL_ALS_LOW_GAIN_MULTIPLIER;
case TSL2591_CTRL_ALS_MED_GAIN:
return TSL2591_CTRL_ALS_MED_GAIN_MULTIPLIER;
case TSL2591_CTRL_ALS_HIGH_GAIN:
return TSL2591_CTRL_ALS_HIGH_GAIN_MULTIPLIER;
case TSL2591_CTRL_ALS_MAX_GAIN:
return TSL2591_CTRL_ALS_MAX_GAIN_MULTIPLIER;
default:
return -EINVAL;
}
}
static int tsl2591_multiplier_to_gain(const u32 multiplier)
{
switch (multiplier) {
case TSL2591_CTRL_ALS_LOW_GAIN_MULTIPLIER:
return TSL2591_CTRL_ALS_LOW_GAIN;
case TSL2591_CTRL_ALS_MED_GAIN_MULTIPLIER:
return TSL2591_CTRL_ALS_MED_GAIN;
case TSL2591_CTRL_ALS_HIGH_GAIN_MULTIPLIER:
return TSL2591_CTRL_ALS_HIGH_GAIN;
case TSL2591_CTRL_ALS_MAX_GAIN_MULTIPLIER:
return TSL2591_CTRL_ALS_MAX_GAIN;
default:
return -EINVAL;
}
}
static int tsl2591_persist_cycle_to_lit(const u8 als_persist)
{
switch (als_persist) {
case TSL2591_PRST_ALS_INT_CYCLE_ANY:
return 1;
case TSL2591_PRST_ALS_INT_CYCLE_2:
return 2;
case TSL2591_PRST_ALS_INT_CYCLE_3:
return 3;
case TSL2591_PRST_ALS_INT_CYCLE_5:
return 5;
case TSL2591_PRST_ALS_INT_CYCLE_10:
return 10;
case TSL2591_PRST_ALS_INT_CYCLE_15:
return 15;
case TSL2591_PRST_ALS_INT_CYCLE_20:
return 20;
case TSL2591_PRST_ALS_INT_CYCLE_25:
return 25;
case TSL2591_PRST_ALS_INT_CYCLE_30:
return 30;
case TSL2591_PRST_ALS_INT_CYCLE_35:
return 35;
case TSL2591_PRST_ALS_INT_CYCLE_40:
return 40;
case TSL2591_PRST_ALS_INT_CYCLE_45:
return 45;
case TSL2591_PRST_ALS_INT_CYCLE_50:
return 50;
case TSL2591_PRST_ALS_INT_CYCLE_55:
return 55;
case TSL2591_PRST_ALS_INT_CYCLE_60:
return 60;
default:
return -EINVAL;
}
}
static int tsl2591_persist_lit_to_cycle(const u8 als_persist)
{
switch (als_persist) {
case 1:
return TSL2591_PRST_ALS_INT_CYCLE_ANY;
case 2:
return TSL2591_PRST_ALS_INT_CYCLE_2;
case 3:
return TSL2591_PRST_ALS_INT_CYCLE_3;
case 5:
return TSL2591_PRST_ALS_INT_CYCLE_5;
case 10:
return TSL2591_PRST_ALS_INT_CYCLE_10;
case 15:
return TSL2591_PRST_ALS_INT_CYCLE_15;
case 20:
return TSL2591_PRST_ALS_INT_CYCLE_20;
case 25:
return TSL2591_PRST_ALS_INT_CYCLE_25;
case 30:
return TSL2591_PRST_ALS_INT_CYCLE_30;
case 35:
return TSL2591_PRST_ALS_INT_CYCLE_35;
case 40:
return TSL2591_PRST_ALS_INT_CYCLE_40;
case 45:
return TSL2591_PRST_ALS_INT_CYCLE_45;
case 50:
return TSL2591_PRST_ALS_INT_CYCLE_50;
case 55:
return TSL2591_PRST_ALS_INT_CYCLE_55;
case 60:
return TSL2591_PRST_ALS_INT_CYCLE_60;
default:
return -EINVAL;
}
}
static int tsl2591_compatible_int_time(struct tsl2591_chip *chip,
const u32 als_integration_time)
{
switch (als_integration_time) {
case TSL2591_CTRL_ALS_INTEGRATION_100MS:
case TSL2591_CTRL_ALS_INTEGRATION_200MS:
case TSL2591_CTRL_ALS_INTEGRATION_300MS:
case TSL2591_CTRL_ALS_INTEGRATION_400MS:
case TSL2591_CTRL_ALS_INTEGRATION_500MS:
case TSL2591_CTRL_ALS_INTEGRATION_600MS:
return 0;
default:
return -EINVAL;
}
}
static int tsl2591_als_time_to_fval(const u32 als_integration_time)
{
int i;
for (i = 0; i < ARRAY_SIZE(tsl2591_int_time_available); i++) {
if (als_integration_time == tsl2591_int_time_available[i])
return TSL2591_SEC_TO_FVAL(als_integration_time);
}
return -EINVAL;
}
static int tsl2591_compatible_gain(struct tsl2591_chip *chip, const u8 als_gain)
{
switch (als_gain) {
case TSL2591_CTRL_ALS_LOW_GAIN:
case TSL2591_CTRL_ALS_MED_GAIN:
case TSL2591_CTRL_ALS_HIGH_GAIN:
case TSL2591_CTRL_ALS_MAX_GAIN:
return 0;
default:
return -EINVAL;
}
}
static int tsl2591_compatible_als_persist_cycle(struct tsl2591_chip *chip,
const u32 als_persist)
{
switch (als_persist) {
case TSL2591_PRST_ALS_INT_CYCLE_ANY:
case TSL2591_PRST_ALS_INT_CYCLE_2:
case TSL2591_PRST_ALS_INT_CYCLE_3:
case TSL2591_PRST_ALS_INT_CYCLE_5:
case TSL2591_PRST_ALS_INT_CYCLE_10:
case TSL2591_PRST_ALS_INT_CYCLE_15:
case TSL2591_PRST_ALS_INT_CYCLE_20:
case TSL2591_PRST_ALS_INT_CYCLE_25:
case TSL2591_PRST_ALS_INT_CYCLE_30:
case TSL2591_PRST_ALS_INT_CYCLE_35:
case TSL2591_PRST_ALS_INT_CYCLE_40:
case TSL2591_PRST_ALS_INT_CYCLE_45:
case TSL2591_PRST_ALS_INT_CYCLE_50:
case TSL2591_PRST_ALS_INT_CYCLE_55:
case TSL2591_PRST_ALS_INT_CYCLE_60:
return 0;
default:
return -EINVAL;
}
}
static int tsl2591_check_als_valid(struct i2c_client *client)
{
int ret;
ret = i2c_smbus_read_byte_data(client, TSL2591_CMD_NOP | TSL2591_STATUS);
if (ret < 0) {
dev_err(&client->dev, "Failed to read register\n");
return -EINVAL;
}
return FIELD_GET(TSL2591_STS_ALS_VALID_MASK, ret);
}
static int tsl2591_wait_adc_complete(struct tsl2591_chip *chip)
{
struct tsl2591_als_settings settings = chip->als_settings;
struct i2c_client *client = chip->client;
int delay;
int val;
int ret;
delay = TSL2591_FVAL_TO_MSEC(settings.als_int_time);
if (!delay)
return -EINVAL;
/*
* Sleep for ALS integration time to allow enough time or an ADC read
* cycle to complete. Check status after delay for ALS valid.
*/
msleep(delay);
/* Check for status ALS valid flag for up to 100ms */
ret = readx_poll_timeout(tsl2591_check_als_valid, client,
val, val == TSL2591_STS_VAL_HIGH_MASK,
TSL2591_DELAY_PERIOD_US,
TSL2591_DELAY_PERIOD_US * TSL2591_ALS_STS_VALID_COUNT);
if (ret)
dev_err(&client->dev, "Timed out waiting for valid ALS data\n");
return ret;
}
/*
* tsl2591_read_channel_data - Reads raw channel data and calculates lux
*
* Formula for lux calculation;
* Derived from Adafruit's TSL2591 library
* Link: https://github.com/adafruit/Adafruit_TSL2591_Library
* Counts Per Lux (CPL) = (ATIME_ms * AGAIN) / LUX DF
* lux = ((C0DATA - C1DATA) * (1 - (C1DATA / C0DATA))) / CPL
*
* Scale values to get more representative value of lux i.e.
* lux = ((C0DATA - C1DATA) * (1000 - ((C1DATA * 1000) / C0DATA))) / CPL
*
* Channel 0 = IR + Visible
* Channel 1 = IR only
*/
static int tsl2591_read_channel_data(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2)
{
struct tsl2591_chip *chip = iio_priv(indio_dev);
struct tsl2591_als_settings *settings = &chip->als_settings;
struct i2c_client *client = chip->client;
u8 als_data[TSL2591_NUM_DATA_REGISTERS];
int counts_per_lux, int_time_fval, gain_multi, lux;
u16 als_ch0, als_ch1;
int ret;
ret = tsl2591_wait_adc_complete(chip);
if (ret < 0) {
dev_err(&client->dev, "No data available. Err: %d\n", ret);
return ret;
}
ret = i2c_smbus_read_i2c_block_data(client,
TSL2591_CMD_NOP | TSL2591_C0_DATAL,
sizeof(als_data), als_data);
if (ret < 0) {
dev_err(&client->dev, "Failed to read data bytes");
return ret;
}
als_ch0 = get_unaligned_le16(&als_data[0]);
als_ch1 = get_unaligned_le16(&als_data[2]);
switch (chan->type) {
case IIO_INTENSITY:
if (chan->channel2 == IIO_MOD_LIGHT_BOTH)
*val = als_ch0;
else if (chan->channel2 == IIO_MOD_LIGHT_IR)
*val = als_ch1;
else
return -EINVAL;
break;
case IIO_LIGHT:
gain_multi = tsl2591_gain_to_multiplier(settings->als_gain);
if (gain_multi < 0) {
dev_err(&client->dev, "Invalid multiplier");
return gain_multi;
}
int_time_fval = TSL2591_FVAL_TO_MSEC(settings->als_int_time);
/* Calculate counts per lux value */
counts_per_lux = (int_time_fval * gain_multi) / TSL2591_LUX_COEFFICIENT;
dev_dbg(&client->dev, "Counts Per Lux: %d\n", counts_per_lux);
/* Calculate lux value */
lux = ((als_ch0 - als_ch1) *
(1000 - ((als_ch1 * 1000) / als_ch0))) / counts_per_lux;
dev_dbg(&client->dev, "Raw lux calculation: %d\n", lux);
/* Divide by 1000 to get real lux value before scaling */
*val = lux / 1000;
/* Get the decimal part of lux reading */
*val2 = (lux - (*val * 1000)) * 1000;
break;
default:
return -EINVAL;
}
return 0;
}
static int tsl2591_set_als_gain_int_time(struct tsl2591_chip *chip)
{
struct tsl2591_als_settings als_settings = chip->als_settings;
struct i2c_client *client = chip->client;
int ret;
ret = i2c_smbus_write_byte_data(client,
TSL2591_CMD_NOP | TSL2591_CONTROL,
als_settings.als_int_time | als_settings.als_gain);
if (ret)
dev_err(&client->dev, "Failed to set als gain & int time\n");
return ret;
}
static int tsl2591_set_als_lower_threshold(struct tsl2591_chip *chip,
u16 als_lower_threshold)
{
struct tsl2591_als_settings als_settings = chip->als_settings;
struct i2c_client *client = chip->client;
u16 als_upper_threshold;
u8 als_lower_l;
u8 als_lower_h;
int ret;
chip->als_settings.als_lower_thresh = als_lower_threshold;
/*
* Lower threshold should not be greater or equal to upper.
* If this is the case, then assert upper threshold to new lower
* threshold + 1 to avoid ordering issues when setting thresholds.
*/
if (als_lower_threshold >= als_settings.als_upper_thresh) {
als_upper_threshold = als_lower_threshold + 1;
tsl2591_set_als_upper_threshold(chip, als_upper_threshold);
}
als_lower_l = als_lower_threshold;
als_lower_h = als_lower_threshold >> 8;
ret = i2c_smbus_write_byte_data(client,
TSL2591_CMD_NOP | TSL2591_AILTL,
als_lower_l);
if (ret) {
dev_err(&client->dev, "Failed to set als lower threshold\n");
return ret;
}
ret = i2c_smbus_write_byte_data(client,
TSL2591_CMD_NOP | TSL2591_AILTH,
als_lower_h);
if (ret) {
dev_err(&client->dev, "Failed to set als lower threshold\n");
return ret;
}
return 0;
}
static int tsl2591_set_als_upper_threshold(struct tsl2591_chip *chip,
u16 als_upper_threshold)
{
struct tsl2591_als_settings als_settings = chip->als_settings;
struct i2c_client *client = chip->client;
u16 als_lower_threshold;
u8 als_upper_l;
u8 als_upper_h;
int ret;
if (als_upper_threshold > TSL2591_ALS_MAX_VALUE)
return -EINVAL;
chip->als_settings.als_upper_thresh = als_upper_threshold;
/*
* Upper threshold should not be less than lower. If this
* is the case, then assert lower threshold to new upper
* threshold - 1 to avoid ordering issues when setting thresholds.
*/
if (als_upper_threshold < als_settings.als_lower_thresh) {
als_lower_threshold = als_upper_threshold - 1;
tsl2591_set_als_lower_threshold(chip, als_lower_threshold);
}
als_upper_l = als_upper_threshold;
als_upper_h = als_upper_threshold >> 8;
ret = i2c_smbus_write_byte_data(client,
TSL2591_CMD_NOP | TSL2591_AIHTL,
als_upper_l);
if (ret) {
dev_err(&client->dev, "Failed to set als upper threshold\n");
return ret;
}
ret = i2c_smbus_write_byte_data(client,
TSL2591_CMD_NOP | TSL2591_AIHTH,
als_upper_h);
if (ret) {
dev_err(&client->dev, "Failed to set als upper threshold\n");
return ret;
}
return 0;
}
static int tsl2591_set_als_persist_cycle(struct tsl2591_chip *chip,
u8 als_persist)
{
struct i2c_client *client = chip->client;
int ret;
ret = i2c_smbus_write_byte_data(client,
TSL2591_CMD_NOP | TSL2591_PERSIST,
als_persist);
if (ret)
dev_err(&client->dev, "Failed to set als persist cycle\n");
chip->als_settings.als_persist = als_persist;
return ret;
}
static int tsl2591_set_power_state(struct tsl2591_chip *chip, u8 state)
{
struct i2c_client *client = chip->client;
int ret;
ret = i2c_smbus_write_byte_data(client,
TSL2591_CMD_NOP | TSL2591_ENABLE,
state);
if (ret)
dev_err(&client->dev,
"Failed to set the power state to %#04x\n", state);
return ret;
}
static ssize_t tsl2591_in_illuminance_period_available_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct tsl2591_chip *chip = iio_priv(indio_dev);
return sysfs_emit(buf, "%s\n",
tsl2591_als_period_list[chip->als_settings.als_int_time]);
}
static IIO_DEVICE_ATTR_RO(tsl2591_in_illuminance_period_available, 0);
static struct attribute *tsl2591_event_attrs_ctrl[] = {
&iio_dev_attr_tsl2591_in_illuminance_period_available.dev_attr.attr,
NULL
};
static const struct attribute_group tsl2591_event_attribute_group = {
.attrs = tsl2591_event_attrs_ctrl,
};
static const struct iio_event_spec tsl2591_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_PERIOD) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec tsl2591_channels[] = {
{
.type = IIO_INTENSITY,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_IR,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE)
},
{
.type = IIO_INTENSITY,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_BOTH,
.event_spec = tsl2591_events,
.num_event_specs = ARRAY_SIZE(tsl2591_events),
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE)
},
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_CALIBSCALE)
},
};
static int tsl2591_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct tsl2591_chip *chip = iio_priv(indio_dev);
struct i2c_client *client = chip->client;
int ret;
pm_runtime_get_sync(&client->dev);
mutex_lock(&chip->als_mutex);
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (chan->type != IIO_INTENSITY) {
ret = -EINVAL;
goto err_unlock;
}
ret = tsl2591_read_channel_data(indio_dev, chan, val, val2);
if (ret < 0)
goto err_unlock;
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_PROCESSED:
if (chan->type != IIO_LIGHT) {
ret = -EINVAL;
goto err_unlock;
}
ret = tsl2591_read_channel_data(indio_dev, chan, val, val2);
if (ret < 0)
break;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
case IIO_CHAN_INFO_INT_TIME:
if (chan->type != IIO_INTENSITY) {
ret = -EINVAL;
goto err_unlock;
}
*val = TSL2591_FVAL_TO_SEC(chip->als_settings.als_int_time);
ret = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_CALIBSCALE:
if (chan->type != IIO_INTENSITY) {
ret = -EINVAL;
goto err_unlock;
}
*val = tsl2591_gain_to_multiplier(chip->als_settings.als_gain);
ret = IIO_VAL_INT;
break;
default:
ret = -EINVAL;
break;
}
err_unlock:
mutex_unlock(&chip->als_mutex);
pm_runtime_mark_last_busy(&client->dev);
pm_runtime_put_autosuspend(&client->dev);
return ret;
}
static int tsl2591_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct tsl2591_chip *chip = iio_priv(indio_dev);
int int_time;
int gain;
int ret;
mutex_lock(&chip->als_mutex);
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
int_time = tsl2591_als_time_to_fval(val);
if (int_time < 0) {
ret = int_time;
goto err_unlock;
}
ret = tsl2591_compatible_int_time(chip, int_time);
if (ret < 0)
goto err_unlock;
chip->als_settings.als_int_time = int_time;
break;
case IIO_CHAN_INFO_CALIBSCALE:
gain = tsl2591_multiplier_to_gain(val);
if (gain < 0) {
ret = gain;
goto err_unlock;
}
ret = tsl2591_compatible_gain(chip, gain);
if (ret < 0)
goto err_unlock;
chip->als_settings.als_gain = gain;
break;
default:
ret = -EINVAL;
goto err_unlock;
}
ret = tsl2591_set_als_gain_int_time(chip);
err_unlock:
mutex_unlock(&chip->als_mutex);
return ret;
}
static int tsl2591_read_available(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
*length = ARRAY_SIZE(tsl2591_int_time_available);
*vals = tsl2591_int_time_available;
*type = IIO_VAL_INT;
return IIO_AVAIL_LIST;
case IIO_CHAN_INFO_CALIBSCALE:
*length = ARRAY_SIZE(tsl2591_calibscale_available);
*vals = tsl2591_calibscale_available;
*type = IIO_VAL_INT;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static int tsl2591_read_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int *val,
int *val2)
{
struct tsl2591_chip *chip = iio_priv(indio_dev);
struct i2c_client *client = chip->client;
int als_persist, int_time, period;
int ret;
mutex_lock(&chip->als_mutex);
switch (info) {
case IIO_EV_INFO_VALUE:
switch (dir) {
case IIO_EV_DIR_RISING:
*val = chip->als_settings.als_upper_thresh;
break;
case IIO_EV_DIR_FALLING:
*val = chip->als_settings.als_lower_thresh;
break;
default:
ret = -EINVAL;
goto err_unlock;
}
ret = IIO_VAL_INT;
break;
case IIO_EV_INFO_PERIOD:
ret = i2c_smbus_read_byte_data(client,
TSL2591_CMD_NOP | TSL2591_PERSIST);
if (ret <= 0 || ret > TSL2591_PRST_ALS_INT_CYCLE_MAX)
goto err_unlock;
als_persist = tsl2591_persist_cycle_to_lit(ret);
int_time = TSL2591_FVAL_TO_MSEC(chip->als_settings.als_int_time);
period = als_persist * (int_time * MSEC_PER_SEC);
*val = period / USEC_PER_SEC;
*val2 = period % USEC_PER_SEC;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
ret = -EINVAL;
break;
}
err_unlock:
mutex_unlock(&chip->als_mutex);
return ret;
}
static int tsl2591_write_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int val,
int val2)
{
struct tsl2591_chip *chip = iio_priv(indio_dev);
int period, int_time, als_persist;
int ret;
if (val < 0 || val2 < 0)
return -EINVAL;
mutex_lock(&chip->als_mutex);
switch (info) {
case IIO_EV_INFO_VALUE:
if (val > TSL2591_ALS_MAX_VALUE) {
ret = -EINVAL;
goto err_unlock;
}
switch (dir) {
case IIO_EV_DIR_RISING:
ret = tsl2591_set_als_upper_threshold(chip, val);
if (ret < 0)
goto err_unlock;
break;
case IIO_EV_DIR_FALLING:
ret = tsl2591_set_als_lower_threshold(chip, val);
if (ret < 0)
goto err_unlock;
break;
default:
ret = -EINVAL;
goto err_unlock;
}
break;
case IIO_EV_INFO_PERIOD:
int_time = TSL2591_FVAL_TO_MSEC(chip->als_settings.als_int_time);
period = ((val * MSEC_PER_SEC) +
(val2 / MSEC_PER_SEC)) / int_time;
als_persist = tsl2591_persist_lit_to_cycle(period);
if (als_persist < 0) {
ret = -EINVAL;
goto err_unlock;
}
ret = tsl2591_compatible_als_persist_cycle(chip, als_persist);
if (ret < 0)
goto err_unlock;
ret = tsl2591_set_als_persist_cycle(chip, als_persist);
if (ret < 0)
goto err_unlock;
break;
default:
ret = -EINVAL;
break;
}
err_unlock:
mutex_unlock(&chip->als_mutex);
return ret;
}
static int tsl2591_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct tsl2591_chip *chip = iio_priv(indio_dev);
return chip->events_enabled;
}
static int tsl2591_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
struct tsl2591_chip *chip = iio_priv(indio_dev);
struct i2c_client *client = chip->client;
if (state && !chip->events_enabled) {
chip->events_enabled = true;
pm_runtime_get_sync(&client->dev);
} else if (!state && chip->events_enabled) {
chip->events_enabled = false;
pm_runtime_mark_last_busy(&client->dev);
pm_runtime_put_autosuspend(&client->dev);
}
return 0;
}
static const struct iio_info tsl2591_info = {
.event_attrs = &tsl2591_event_attribute_group,
.read_raw = tsl2591_read_raw,
.write_raw = tsl2591_write_raw,
.read_avail = tsl2591_read_available,
.read_event_value = tsl2591_read_event_value,
.write_event_value = tsl2591_write_event_value,
.read_event_config = tsl2591_read_event_config,
.write_event_config = tsl2591_write_event_config,
};
static const struct iio_info tsl2591_info_no_irq = {
.read_raw = tsl2591_read_raw,
.write_raw = tsl2591_write_raw,
.read_avail = tsl2591_read_available,
};
static int tsl2591_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct tsl2591_chip *chip = iio_priv(indio_dev);
int ret;
mutex_lock(&chip->als_mutex);
ret = tsl2591_set_power_state(chip, TSL2591_PWR_OFF);
mutex_unlock(&chip->als_mutex);
return ret;
}
static int tsl2591_resume(struct device *dev)
{
int power_state = TSL2591_PWR_ON | TSL2591_ENABLE_ALS;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct tsl2591_chip *chip = iio_priv(indio_dev);
int ret;
if (chip->events_enabled)
power_state |= TSL2591_ENABLE_ALS_INT;
mutex_lock(&chip->als_mutex);
ret = tsl2591_set_power_state(chip, power_state);
mutex_unlock(&chip->als_mutex);
return ret;
}
static DEFINE_RUNTIME_DEV_PM_OPS(tsl2591_pm_ops, tsl2591_suspend,
tsl2591_resume, NULL);
static irqreturn_t tsl2591_event_handler(int irq, void *private)
{
struct iio_dev *dev_info = private;
struct tsl2591_chip *chip = iio_priv(dev_info);
struct i2c_client *client = chip->client;
if (!chip->events_enabled)
return IRQ_NONE;
iio_push_event(dev_info,
IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(dev_info));
/* Clear ALS irq */
i2c_smbus_write_byte(client, TSL2591_CMD_SF_CALS_NPI);
return IRQ_HANDLED;
}
static int tsl2591_load_defaults(struct tsl2591_chip *chip)
{
int ret;
chip->als_settings.als_int_time = TSL2591_DEFAULT_ALS_INT_TIME;
chip->als_settings.als_gain = TSL2591_DEFAULT_ALS_GAIN;
chip->als_settings.als_lower_thresh = TSL2591_DEFAULT_ALS_LOWER_THRESH;
chip->als_settings.als_upper_thresh = TSL2591_DEFAULT_ALS_UPPER_THRESH;
ret = tsl2591_set_als_gain_int_time(chip);
if (ret < 0)
return ret;
ret = tsl2591_set_als_persist_cycle(chip, TSL2591_DEFAULT_ALS_PERSIST);
if (ret < 0)
return ret;
ret = tsl2591_set_als_lower_threshold(chip, TSL2591_DEFAULT_ALS_LOWER_THRESH);
if (ret < 0)
return ret;
ret = tsl2591_set_als_upper_threshold(chip, TSL2591_DEFAULT_ALS_UPPER_THRESH);
if (ret < 0)
return ret;
return 0;
}
static void tsl2591_chip_off(void *data)
{
struct iio_dev *indio_dev = data;
struct tsl2591_chip *chip = iio_priv(indio_dev);
struct i2c_client *client = chip->client;
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
pm_runtime_put_noidle(&client->dev);
tsl2591_set_power_state(chip, TSL2591_PWR_OFF);
}
static int tsl2591_probe(struct i2c_client *client)
{
struct tsl2591_chip *chip;
struct iio_dev *indio_dev;
int ret;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
dev_err(&client->dev,
"I2C smbus byte data functionality is not supported\n");
return -EOPNOTSUPP;
}
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
if (!indio_dev)
return -ENOMEM;
chip = iio_priv(indio_dev);
chip->client = client;
i2c_set_clientdata(client, indio_dev);
if (client->irq) {
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, tsl2591_event_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"tsl2591_irq", indio_dev);
if (ret) {
dev_err_probe(&client->dev, ret, "IRQ request error\n");
return -EINVAL;
}
indio_dev->info = &tsl2591_info;
} else {
indio_dev->info = &tsl2591_info_no_irq;
}
mutex_init(&chip->als_mutex);
ret = i2c_smbus_read_byte_data(client,
TSL2591_CMD_NOP | TSL2591_DEVICE_ID);
if (ret < 0) {
dev_err(&client->dev,
"Failed to read the device ID register\n");
return ret;
}
ret = FIELD_GET(TSL2591_DEVICE_ID_MASK, ret);
if (ret != TSL2591_DEVICE_ID_VAL) {
dev_err(&client->dev, "Device ID: %#04x unknown\n", ret);
return -EINVAL;
}
indio_dev->channels = tsl2591_channels;
indio_dev->num_channels = ARRAY_SIZE(tsl2591_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->name = chip->client->name;
chip->events_enabled = false;
pm_runtime_enable(&client->dev);
pm_runtime_set_autosuspend_delay(&client->dev,
TSL2591_POWER_OFF_DELAY_MS);
pm_runtime_use_autosuspend(&client->dev);
/*
* Add chip off to automatically managed path and disable runtime
* power management. This ensures that the chip power management
* is handled correctly on driver remove. tsl2591_chip_off() must be
* added to the managed path after pm runtime is enabled and before
* any error exit paths are met to ensure we're not left in a state
* of pm runtime not being disabled properly.
*/
ret = devm_add_action_or_reset(&client->dev, tsl2591_chip_off,
indio_dev);
if (ret < 0)
return -EINVAL;
ret = tsl2591_load_defaults(chip);
if (ret < 0) {
dev_err(&client->dev, "Failed to load sensor defaults\n");
return -EINVAL;
}
ret = i2c_smbus_write_byte(client, TSL2591_CMD_SF_CALS_NPI);
if (ret < 0) {
dev_err(&client->dev, "Failed to clear als irq\n");
return -EINVAL;
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct of_device_id tsl2591_of_match[] = {
{ .compatible = "amstaos,tsl2591"},
{}
};
MODULE_DEVICE_TABLE(of, tsl2591_of_match);
static struct i2c_driver tsl2591_driver = {
.driver = {
.name = "tsl2591",
.pm = pm_ptr(&tsl2591_pm_ops),
.of_match_table = tsl2591_of_match,
},
.probe = tsl2591_probe
};
module_i2c_driver(tsl2591_driver);
MODULE_AUTHOR("Joe Sandom <[email protected]>");
MODULE_DESCRIPTION("TAOS tsl2591 ambient light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/tsl2591.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for ON Semiconductor NOA1305 ambient light sensor
*
* Copyright (C) 2016 Emcraft Systems
* Copyright (C) 2019 Collabora Ltd.
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#define NOA1305_REG_POWER_CONTROL 0x0
#define NOA1305_POWER_CONTROL_DOWN 0x00
#define NOA1305_POWER_CONTROL_ON 0x08
#define NOA1305_REG_RESET 0x1
#define NOA1305_RESET_RESET 0x10
#define NOA1305_REG_INTEGRATION_TIME 0x2
#define NOA1305_INTEGR_TIME_800MS 0x00
#define NOA1305_INTEGR_TIME_400MS 0x01
#define NOA1305_INTEGR_TIME_200MS 0x02
#define NOA1305_INTEGR_TIME_100MS 0x03
#define NOA1305_INTEGR_TIME_50MS 0x04
#define NOA1305_INTEGR_TIME_25MS 0x05
#define NOA1305_INTEGR_TIME_12_5MS 0x06
#define NOA1305_INTEGR_TIME_6_25MS 0x07
#define NOA1305_REG_INT_SELECT 0x3
#define NOA1305_INT_SEL_ACTIVE_HIGH 0x01
#define NOA1305_INT_SEL_ACTIVE_LOW 0x02
#define NOA1305_INT_SEL_INACTIVE 0x03
#define NOA1305_REG_INT_THRESH_LSB 0x4
#define NOA1305_REG_INT_THRESH_MSB 0x5
#define NOA1305_REG_ALS_DATA_LSB 0x6
#define NOA1305_REG_ALS_DATA_MSB 0x7
#define NOA1305_REG_DEVICE_ID_LSB 0x8
#define NOA1305_REG_DEVICE_ID_MSB 0x9
#define NOA1305_DEVICE_ID 0x0519
#define NOA1305_DRIVER_NAME "noa1305"
struct noa1305_priv {
struct i2c_client *client;
struct regmap *regmap;
};
static int noa1305_measure(struct noa1305_priv *priv)
{
__le16 data;
int ret;
ret = regmap_bulk_read(priv->regmap, NOA1305_REG_ALS_DATA_LSB, &data,
2);
if (ret < 0)
return ret;
return le16_to_cpu(data);
}
static int noa1305_scale(struct noa1305_priv *priv, int *val, int *val2)
{
int data;
int ret;
ret = regmap_read(priv->regmap, NOA1305_REG_INTEGRATION_TIME, &data);
if (ret < 0)
return ret;
/*
* Lux = count / (<Integration Constant> * <Integration Time>)
*
* Integration Constant = 7.7
* Integration Time in Seconds
*/
switch (data) {
case NOA1305_INTEGR_TIME_800MS:
*val = 100;
*val2 = 77 * 8;
break;
case NOA1305_INTEGR_TIME_400MS:
*val = 100;
*val2 = 77 * 4;
break;
case NOA1305_INTEGR_TIME_200MS:
*val = 100;
*val2 = 77 * 2;
break;
case NOA1305_INTEGR_TIME_100MS:
*val = 100;
*val2 = 77;
break;
case NOA1305_INTEGR_TIME_50MS:
*val = 1000;
*val2 = 77 * 5;
break;
case NOA1305_INTEGR_TIME_25MS:
*val = 10000;
*val2 = 77 * 25;
break;
case NOA1305_INTEGR_TIME_12_5MS:
*val = 100000;
*val2 = 77 * 125;
break;
case NOA1305_INTEGR_TIME_6_25MS:
*val = 1000000;
*val2 = 77 * 625;
break;
default:
return -EINVAL;
}
return IIO_VAL_FRACTIONAL;
}
static const struct iio_chan_spec noa1305_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
}
};
static int noa1305_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
int ret = -EINVAL;
struct noa1305_priv *priv = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_LIGHT:
ret = noa1305_measure(priv);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
default:
break;
}
break;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_LIGHT:
return noa1305_scale(priv, val, val2);
default:
break;
}
break;
default:
break;
}
return ret;
}
static const struct iio_info noa1305_info = {
.read_raw = noa1305_read_raw,
};
static bool noa1305_writable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NOA1305_REG_POWER_CONTROL:
case NOA1305_REG_RESET:
case NOA1305_REG_INTEGRATION_TIME:
case NOA1305_REG_INT_SELECT:
case NOA1305_REG_INT_THRESH_LSB:
case NOA1305_REG_INT_THRESH_MSB:
return true;
default:
return false;
}
}
static const struct regmap_config noa1305_regmap_config = {
.name = NOA1305_DRIVER_NAME,
.reg_bits = 8,
.val_bits = 8,
.max_register = NOA1305_REG_DEVICE_ID_MSB,
.writeable_reg = noa1305_writable_reg,
};
static int noa1305_probe(struct i2c_client *client)
{
struct noa1305_priv *priv;
struct iio_dev *indio_dev;
struct regmap *regmap;
__le16 data;
unsigned int dev_id;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*priv));
if (!indio_dev)
return -ENOMEM;
regmap = devm_regmap_init_i2c(client, &noa1305_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "Regmap initialization failed.\n");
return PTR_ERR(regmap);
}
priv = iio_priv(indio_dev);
ret = devm_regulator_get_enable(&client->dev, "vin");
if (ret)
return dev_err_probe(&client->dev, ret,
"get regulator vin failed\n");
i2c_set_clientdata(client, indio_dev);
priv->client = client;
priv->regmap = regmap;
ret = regmap_bulk_read(regmap, NOA1305_REG_DEVICE_ID_LSB, &data, 2);
if (ret < 0) {
dev_err(&client->dev, "ID reading failed: %d\n", ret);
return ret;
}
dev_id = le16_to_cpu(data);
if (dev_id != NOA1305_DEVICE_ID) {
dev_err(&client->dev, "Unknown device ID: 0x%x\n", dev_id);
return -ENODEV;
}
ret = regmap_write(regmap, NOA1305_REG_POWER_CONTROL,
NOA1305_POWER_CONTROL_ON);
if (ret < 0) {
dev_err(&client->dev, "Enabling power control failed\n");
return ret;
}
ret = regmap_write(regmap, NOA1305_REG_RESET, NOA1305_RESET_RESET);
if (ret < 0) {
dev_err(&client->dev, "Device reset failed\n");
return ret;
}
ret = regmap_write(regmap, NOA1305_REG_INTEGRATION_TIME,
NOA1305_INTEGR_TIME_800MS);
if (ret < 0) {
dev_err(&client->dev, "Setting integration time failed\n");
return ret;
}
indio_dev->info = &noa1305_info;
indio_dev->channels = noa1305_channels;
indio_dev->num_channels = ARRAY_SIZE(noa1305_channels);
indio_dev->name = NOA1305_DRIVER_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = devm_iio_device_register(&client->dev, indio_dev);
if (ret)
dev_err(&client->dev, "registering device failed\n");
return ret;
}
static const struct of_device_id noa1305_of_match[] = {
{ .compatible = "onnn,noa1305" },
{ }
};
MODULE_DEVICE_TABLE(of, noa1305_of_match);
static const struct i2c_device_id noa1305_ids[] = {
{ "noa1305", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, noa1305_ids);
static struct i2c_driver noa1305_driver = {
.driver = {
.name = NOA1305_DRIVER_NAME,
.of_match_table = noa1305_of_match,
},
.probe = noa1305_probe,
.id_table = noa1305_ids,
};
module_i2c_driver(noa1305_driver);
MODULE_AUTHOR("Sergei Miroshnichenko <[email protected]>");
MODULE_AUTHOR("Martyn Welch <[email protected]");
MODULE_DESCRIPTION("ON Semiconductor NOA1305 ambient light sensor");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/noa1305.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tsl4531.c - Support for TAOS TSL4531 ambient light sensor
*
* Copyright 2013 Peter Meerwald <[email protected]>
*
* IIO driver for the TSL4531x family
* TSL45311/TSL45313: 7-bit I2C slave address 0x39
* TSL45315/TSL45317: 7-bit I2C slave address 0x29
*
* TODO: single cycle measurement
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define TSL4531_DRV_NAME "tsl4531"
#define TSL4531_COMMAND BIT(7)
#define TSL4531_CONTROL (TSL4531_COMMAND | 0x00)
#define TSL4531_CONFIG (TSL4531_COMMAND | 0x01)
#define TSL4531_DATA (TSL4531_COMMAND | 0x04)
#define TSL4531_ID (TSL4531_COMMAND | 0x0a)
/* operating modes in control register */
#define TSL4531_MODE_POWERDOWN 0x00
#define TSL4531_MODE_SINGLE_ADC 0x02
#define TSL4531_MODE_NORMAL 0x03
/* integration time control in config register */
#define TSL4531_TCNTRL_400MS 0x00
#define TSL4531_TCNTRL_200MS 0x01
#define TSL4531_TCNTRL_100MS 0x02
/* part number in id register */
#define TSL45311_ID 0x8
#define TSL45313_ID 0x9
#define TSL45315_ID 0xa
#define TSL45317_ID 0xb
#define TSL4531_ID_SHIFT 4
struct tsl4531_data {
struct i2c_client *client;
struct mutex lock;
int int_time;
};
static IIO_CONST_ATTR_INT_TIME_AVAIL("0.1 0.2 0.4");
static struct attribute *tsl4531_attributes[] = {
&iio_const_attr_integration_time_available.dev_attr.attr,
NULL
};
static const struct attribute_group tsl4531_attribute_group = {
.attrs = tsl4531_attributes,
};
static const struct iio_chan_spec tsl4531_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_INT_TIME)
}
};
static int tsl4531_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct tsl4531_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = i2c_smbus_read_word_data(data->client,
TSL4531_DATA);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/* 0.. 1x, 1 .. 2x, 2 .. 4x */
*val = 1 << data->int_time;
return IIO_VAL_INT;
case IIO_CHAN_INFO_INT_TIME:
if (data->int_time == 0)
*val2 = 400000;
else if (data->int_time == 1)
*val2 = 200000;
else if (data->int_time == 2)
*val2 = 100000;
else
return -EINVAL;
*val = 0;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
}
static int tsl4531_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct tsl4531_data *data = iio_priv(indio_dev);
int int_time, ret;
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
if (val != 0)
return -EINVAL;
if (val2 == 400000)
int_time = 0;
else if (val2 == 200000)
int_time = 1;
else if (val2 == 100000)
int_time = 2;
else
return -EINVAL;
mutex_lock(&data->lock);
ret = i2c_smbus_write_byte_data(data->client,
TSL4531_CONFIG, int_time);
if (ret >= 0)
data->int_time = int_time;
mutex_unlock(&data->lock);
return ret;
default:
return -EINVAL;
}
}
static const struct iio_info tsl4531_info = {
.read_raw = tsl4531_read_raw,
.write_raw = tsl4531_write_raw,
.attrs = &tsl4531_attribute_group,
};
static int tsl4531_check_id(struct i2c_client *client)
{
int ret = i2c_smbus_read_byte_data(client, TSL4531_ID);
if (ret < 0)
return ret;
switch (ret >> TSL4531_ID_SHIFT) {
case TSL45311_ID:
case TSL45313_ID:
case TSL45315_ID:
case TSL45317_ID:
return 0;
default:
return -ENODEV;
}
}
static int tsl4531_probe(struct i2c_client *client)
{
struct tsl4531_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
mutex_init(&data->lock);
ret = tsl4531_check_id(client);
if (ret) {
dev_err(&client->dev, "no TSL4531 sensor\n");
return ret;
}
ret = i2c_smbus_write_byte_data(data->client, TSL4531_CONTROL,
TSL4531_MODE_NORMAL);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client, TSL4531_CONFIG,
TSL4531_TCNTRL_400MS);
if (ret < 0)
return ret;
indio_dev->info = &tsl4531_info;
indio_dev->channels = tsl4531_channels;
indio_dev->num_channels = ARRAY_SIZE(tsl4531_channels);
indio_dev->name = TSL4531_DRV_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
return iio_device_register(indio_dev);
}
static int tsl4531_powerdown(struct i2c_client *client)
{
return i2c_smbus_write_byte_data(client, TSL4531_CONTROL,
TSL4531_MODE_POWERDOWN);
}
static void tsl4531_remove(struct i2c_client *client)
{
iio_device_unregister(i2c_get_clientdata(client));
tsl4531_powerdown(client);
}
static int tsl4531_suspend(struct device *dev)
{
return tsl4531_powerdown(to_i2c_client(dev));
}
static int tsl4531_resume(struct device *dev)
{
return i2c_smbus_write_byte_data(to_i2c_client(dev), TSL4531_CONTROL,
TSL4531_MODE_NORMAL);
}
static DEFINE_SIMPLE_DEV_PM_OPS(tsl4531_pm_ops, tsl4531_suspend,
tsl4531_resume);
static const struct i2c_device_id tsl4531_id[] = {
{ "tsl4531", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tsl4531_id);
static struct i2c_driver tsl4531_driver = {
.driver = {
.name = TSL4531_DRV_NAME,
.pm = pm_sleep_ptr(&tsl4531_pm_ops),
},
.probe = tsl4531_probe,
.remove = tsl4531_remove,
.id_table = tsl4531_id,
};
module_i2c_driver(tsl4531_driver);
MODULE_AUTHOR("Peter Meerwald <[email protected]>");
MODULE_DESCRIPTION("TAOS TSL4531 ambient light sensors driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/tsl4531.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Support for Lite-On LTR501 and similar ambient light and proximity sensors.
*
* Copyright 2014 Peter Meerwald <[email protected]>
*
* 7-bit I2C slave address 0x23
*
* TODO: IR LED characteristics
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/acpi.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/events.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#define LTR501_DRV_NAME "ltr501"
#define LTR501_ALS_CONTR 0x80 /* ALS operation mode, SW reset */
#define LTR501_PS_CONTR 0x81 /* PS operation mode */
#define LTR501_PS_MEAS_RATE 0x84 /* measurement rate*/
#define LTR501_ALS_MEAS_RATE 0x85 /* ALS integ time, measurement rate*/
#define LTR501_PART_ID 0x86
#define LTR501_MANUFAC_ID 0x87
#define LTR501_ALS_DATA1 0x88 /* 16-bit, little endian */
#define LTR501_ALS_DATA1_UPPER 0x89 /* upper 8 bits of LTR501_ALS_DATA1 */
#define LTR501_ALS_DATA0 0x8a /* 16-bit, little endian */
#define LTR501_ALS_DATA0_UPPER 0x8b /* upper 8 bits of LTR501_ALS_DATA0 */
#define LTR501_ALS_PS_STATUS 0x8c
#define LTR501_PS_DATA 0x8d /* 16-bit, little endian */
#define LTR501_PS_DATA_UPPER 0x8e /* upper 8 bits of LTR501_PS_DATA */
#define LTR501_INTR 0x8f /* output mode, polarity, mode */
#define LTR501_PS_THRESH_UP 0x90 /* 11 bit, ps upper threshold */
#define LTR501_PS_THRESH_LOW 0x92 /* 11 bit, ps lower threshold */
#define LTR501_ALS_THRESH_UP 0x97 /* 16 bit, ALS upper threshold */
#define LTR501_ALS_THRESH_LOW 0x99 /* 16 bit, ALS lower threshold */
#define LTR501_INTR_PRST 0x9e /* ps thresh, als thresh */
#define LTR501_MAX_REG 0x9f
#define LTR501_ALS_CONTR_SW_RESET BIT(2)
#define LTR501_CONTR_PS_GAIN_MASK (BIT(3) | BIT(2))
#define LTR501_CONTR_PS_GAIN_SHIFT 2
#define LTR501_CONTR_ALS_GAIN_MASK BIT(3)
#define LTR501_CONTR_ACTIVE BIT(1)
#define LTR501_STATUS_ALS_INTR BIT(3)
#define LTR501_STATUS_ALS_RDY BIT(2)
#define LTR501_STATUS_PS_INTR BIT(1)
#define LTR501_STATUS_PS_RDY BIT(0)
#define LTR501_PS_DATA_MASK 0x7ff
#define LTR501_PS_THRESH_MASK 0x7ff
#define LTR501_ALS_THRESH_MASK 0xffff
#define LTR501_ALS_DEF_PERIOD 500000
#define LTR501_PS_DEF_PERIOD 100000
#define LTR501_REGMAP_NAME "ltr501_regmap"
#define LTR501_LUX_CONV(vis_coeff, vis_data, ir_coeff, ir_data) \
((vis_coeff * vis_data) - (ir_coeff * ir_data))
static const int int_time_mapping[] = {100000, 50000, 200000, 400000};
static const struct reg_field reg_field_it =
REG_FIELD(LTR501_ALS_MEAS_RATE, 3, 4);
static const struct reg_field reg_field_als_intr =
REG_FIELD(LTR501_INTR, 1, 1);
static const struct reg_field reg_field_ps_intr =
REG_FIELD(LTR501_INTR, 0, 0);
static const struct reg_field reg_field_als_rate =
REG_FIELD(LTR501_ALS_MEAS_RATE, 0, 2);
static const struct reg_field reg_field_ps_rate =
REG_FIELD(LTR501_PS_MEAS_RATE, 0, 3);
static const struct reg_field reg_field_als_prst =
REG_FIELD(LTR501_INTR_PRST, 0, 3);
static const struct reg_field reg_field_ps_prst =
REG_FIELD(LTR501_INTR_PRST, 4, 7);
struct ltr501_samp_table {
int freq_val; /* repetition frequency in micro HZ*/
int time_val; /* repetition rate in micro seconds */
};
#define LTR501_RESERVED_GAIN -1
enum {
ltr501 = 0,
ltr559,
ltr301,
ltr303,
};
struct ltr501_gain {
int scale;
int uscale;
};
static const struct ltr501_gain ltr501_als_gain_tbl[] = {
{1, 0},
{0, 5000},
};
static const struct ltr501_gain ltr559_als_gain_tbl[] = {
{1, 0},
{0, 500000},
{0, 250000},
{0, 125000},
{LTR501_RESERVED_GAIN, LTR501_RESERVED_GAIN},
{LTR501_RESERVED_GAIN, LTR501_RESERVED_GAIN},
{0, 20000},
{0, 10000},
};
static const struct ltr501_gain ltr501_ps_gain_tbl[] = {
{1, 0},
{0, 250000},
{0, 125000},
{0, 62500},
};
static const struct ltr501_gain ltr559_ps_gain_tbl[] = {
{0, 62500}, /* x16 gain */
{0, 31250}, /* x32 gain */
{0, 15625}, /* bits X1 are for x64 gain */
{0, 15624},
};
struct ltr501_chip_info {
u8 partid;
const struct ltr501_gain *als_gain;
int als_gain_tbl_size;
const struct ltr501_gain *ps_gain;
int ps_gain_tbl_size;
u8 als_mode_active;
u8 als_gain_mask;
u8 als_gain_shift;
struct iio_chan_spec const *channels;
const int no_channels;
const struct iio_info *info;
const struct iio_info *info_no_irq;
};
struct ltr501_data {
struct i2c_client *client;
struct mutex lock_als, lock_ps;
const struct ltr501_chip_info *chip_info;
u8 als_contr, ps_contr;
int als_period, ps_period; /* period in micro seconds */
struct regmap *regmap;
struct regmap_field *reg_it;
struct regmap_field *reg_als_intr;
struct regmap_field *reg_ps_intr;
struct regmap_field *reg_als_rate;
struct regmap_field *reg_ps_rate;
struct regmap_field *reg_als_prst;
struct regmap_field *reg_ps_prst;
uint32_t near_level;
};
static const struct ltr501_samp_table ltr501_als_samp_table[] = {
{20000000, 50000}, {10000000, 100000},
{5000000, 200000}, {2000000, 500000},
{1000000, 1000000}, {500000, 2000000},
{500000, 2000000}, {500000, 2000000}
};
static const struct ltr501_samp_table ltr501_ps_samp_table[] = {
{20000000, 50000}, {14285714, 70000},
{10000000, 100000}, {5000000, 200000},
{2000000, 500000}, {1000000, 1000000},
{500000, 2000000}, {500000, 2000000},
{500000, 2000000}
};
static int ltr501_match_samp_freq(const struct ltr501_samp_table *tab,
int len, int val, int val2)
{
int i, freq;
freq = val * 1000000 + val2;
for (i = 0; i < len; i++) {
if (tab[i].freq_val == freq)
return i;
}
return -EINVAL;
}
static int ltr501_als_read_samp_freq(const struct ltr501_data *data,
int *val, int *val2)
{
int ret, i;
ret = regmap_field_read(data->reg_als_rate, &i);
if (ret < 0)
return ret;
if (i < 0 || i >= ARRAY_SIZE(ltr501_als_samp_table))
return -EINVAL;
*val = ltr501_als_samp_table[i].freq_val / 1000000;
*val2 = ltr501_als_samp_table[i].freq_val % 1000000;
return IIO_VAL_INT_PLUS_MICRO;
}
static int ltr501_ps_read_samp_freq(const struct ltr501_data *data,
int *val, int *val2)
{
int ret, i;
ret = regmap_field_read(data->reg_ps_rate, &i);
if (ret < 0)
return ret;
if (i < 0 || i >= ARRAY_SIZE(ltr501_ps_samp_table))
return -EINVAL;
*val = ltr501_ps_samp_table[i].freq_val / 1000000;
*val2 = ltr501_ps_samp_table[i].freq_val % 1000000;
return IIO_VAL_INT_PLUS_MICRO;
}
static int ltr501_als_write_samp_freq(struct ltr501_data *data,
int val, int val2)
{
int i, ret;
i = ltr501_match_samp_freq(ltr501_als_samp_table,
ARRAY_SIZE(ltr501_als_samp_table),
val, val2);
if (i < 0)
return i;
mutex_lock(&data->lock_als);
ret = regmap_field_write(data->reg_als_rate, i);
mutex_unlock(&data->lock_als);
return ret;
}
static int ltr501_ps_write_samp_freq(struct ltr501_data *data,
int val, int val2)
{
int i, ret;
i = ltr501_match_samp_freq(ltr501_ps_samp_table,
ARRAY_SIZE(ltr501_ps_samp_table),
val, val2);
if (i < 0)
return i;
mutex_lock(&data->lock_ps);
ret = regmap_field_write(data->reg_ps_rate, i);
mutex_unlock(&data->lock_ps);
return ret;
}
static int ltr501_als_read_samp_period(const struct ltr501_data *data, int *val)
{
int ret, i;
ret = regmap_field_read(data->reg_als_rate, &i);
if (ret < 0)
return ret;
if (i < 0 || i >= ARRAY_SIZE(ltr501_als_samp_table))
return -EINVAL;
*val = ltr501_als_samp_table[i].time_val;
return IIO_VAL_INT;
}
static int ltr501_ps_read_samp_period(const struct ltr501_data *data, int *val)
{
int ret, i;
ret = regmap_field_read(data->reg_ps_rate, &i);
if (ret < 0)
return ret;
if (i < 0 || i >= ARRAY_SIZE(ltr501_ps_samp_table))
return -EINVAL;
*val = ltr501_ps_samp_table[i].time_val;
return IIO_VAL_INT;
}
/* IR and visible spectrum coeff's are given in data sheet */
static unsigned long ltr501_calculate_lux(u16 vis_data, u16 ir_data)
{
unsigned long ratio, lux;
if (vis_data == 0)
return 0;
/* multiply numerator by 100 to avoid handling ratio < 1 */
ratio = DIV_ROUND_UP(ir_data * 100, ir_data + vis_data);
if (ratio < 45)
lux = LTR501_LUX_CONV(1774, vis_data, -1105, ir_data);
else if (ratio >= 45 && ratio < 64)
lux = LTR501_LUX_CONV(3772, vis_data, 1336, ir_data);
else if (ratio >= 64 && ratio < 85)
lux = LTR501_LUX_CONV(1690, vis_data, 169, ir_data);
else
lux = 0;
return lux / 1000;
}
static int ltr501_drdy(const struct ltr501_data *data, u8 drdy_mask)
{
int tries = 100;
int ret, status;
while (tries--) {
ret = regmap_read(data->regmap, LTR501_ALS_PS_STATUS, &status);
if (ret < 0)
return ret;
if ((status & drdy_mask) == drdy_mask)
return 0;
msleep(25);
}
dev_err(&data->client->dev, "ltr501_drdy() failed, data not ready\n");
return -EIO;
}
static int ltr501_set_it_time(struct ltr501_data *data, int it)
{
int ret, i, index = -1, status;
for (i = 0; i < ARRAY_SIZE(int_time_mapping); i++) {
if (int_time_mapping[i] == it) {
index = i;
break;
}
}
/* Make sure integ time index is valid */
if (index < 0)
return -EINVAL;
ret = regmap_read(data->regmap, LTR501_ALS_CONTR, &status);
if (ret < 0)
return ret;
if (status & LTR501_CONTR_ALS_GAIN_MASK) {
/*
* 200 ms and 400 ms integ time can only be
* used in dynamic range 1
*/
if (index > 1)
return -EINVAL;
} else
/* 50 ms integ time can only be used in dynamic range 2 */
if (index == 1)
return -EINVAL;
return regmap_field_write(data->reg_it, index);
}
/* read int time in micro seconds */
static int ltr501_read_it_time(const struct ltr501_data *data,
int *val, int *val2)
{
int ret, index;
ret = regmap_field_read(data->reg_it, &index);
if (ret < 0)
return ret;
/* Make sure integ time index is valid */
if (index < 0 || index >= ARRAY_SIZE(int_time_mapping))
return -EINVAL;
*val2 = int_time_mapping[index];
*val = 0;
return IIO_VAL_INT_PLUS_MICRO;
}
static int ltr501_read_als(const struct ltr501_data *data, __le16 buf[2])
{
int ret;
ret = ltr501_drdy(data, LTR501_STATUS_ALS_RDY);
if (ret < 0)
return ret;
/* always read both ALS channels in given order */
return regmap_bulk_read(data->regmap, LTR501_ALS_DATA1,
buf, 2 * sizeof(__le16));
}
static int ltr501_read_ps(const struct ltr501_data *data)
{
__le16 status;
int ret;
ret = ltr501_drdy(data, LTR501_STATUS_PS_RDY);
if (ret < 0)
return ret;
ret = regmap_bulk_read(data->regmap, LTR501_PS_DATA,
&status, sizeof(status));
if (ret < 0)
return ret;
return le16_to_cpu(status);
}
static int ltr501_read_intr_prst(const struct ltr501_data *data,
enum iio_chan_type type,
int *val2)
{
int ret, samp_period, prst;
switch (type) {
case IIO_INTENSITY:
ret = regmap_field_read(data->reg_als_prst, &prst);
if (ret < 0)
return ret;
ret = ltr501_als_read_samp_period(data, &samp_period);
if (ret < 0)
return ret;
*val2 = samp_period * prst;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_PROXIMITY:
ret = regmap_field_read(data->reg_ps_prst, &prst);
if (ret < 0)
return ret;
ret = ltr501_ps_read_samp_period(data, &samp_period);
if (ret < 0)
return ret;
*val2 = samp_period * prst;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
return -EINVAL;
}
static int ltr501_write_intr_prst(struct ltr501_data *data,
enum iio_chan_type type,
int val, int val2)
{
int ret, samp_period, new_val;
unsigned long period;
if (val < 0 || val2 < 0)
return -EINVAL;
/* period in microseconds */
period = ((val * 1000000) + val2);
switch (type) {
case IIO_INTENSITY:
ret = ltr501_als_read_samp_period(data, &samp_period);
if (ret < 0)
return ret;
/* period should be atleast equal to sampling period */
if (period < samp_period)
return -EINVAL;
new_val = DIV_ROUND_UP(period, samp_period);
if (new_val < 0 || new_val > 0x0f)
return -EINVAL;
mutex_lock(&data->lock_als);
ret = regmap_field_write(data->reg_als_prst, new_val);
mutex_unlock(&data->lock_als);
if (ret >= 0)
data->als_period = period;
return ret;
case IIO_PROXIMITY:
ret = ltr501_ps_read_samp_period(data, &samp_period);
if (ret < 0)
return ret;
/* period should be atleast equal to rate */
if (period < samp_period)
return -EINVAL;
new_val = DIV_ROUND_UP(period, samp_period);
if (new_val < 0 || new_val > 0x0f)
return -EINVAL;
mutex_lock(&data->lock_ps);
ret = regmap_field_write(data->reg_ps_prst, new_val);
mutex_unlock(&data->lock_ps);
if (ret >= 0)
data->ps_period = period;
return ret;
default:
return -EINVAL;
}
return -EINVAL;
}
static ssize_t ltr501_read_near_level(struct iio_dev *indio_dev,
uintptr_t priv,
const struct iio_chan_spec *chan,
char *buf)
{
struct ltr501_data *data = iio_priv(indio_dev);
return sprintf(buf, "%u\n", data->near_level);
}
static const struct iio_chan_spec_ext_info ltr501_ext_info[] = {
{
.name = "nearlevel",
.shared = IIO_SEPARATE,
.read = ltr501_read_near_level,
},
{ /* sentinel */ }
};
static const struct iio_event_spec ltr501_als_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
BIT(IIO_EV_INFO_PERIOD),
},
};
static const struct iio_event_spec ltr501_pxs_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
BIT(IIO_EV_INFO_PERIOD),
},
};
#define LTR501_INTENSITY_CHANNEL(_idx, _addr, _mod, _shared, \
_evspec, _evsize) { \
.type = IIO_INTENSITY, \
.modified = 1, \
.address = (_addr), \
.channel2 = (_mod), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = (_shared), \
.scan_index = (_idx), \
.scan_type = { \
.sign = 'u', \
.realbits = 16, \
.storagebits = 16, \
.endianness = IIO_CPU, \
}, \
.event_spec = _evspec,\
.num_event_specs = _evsize,\
}
#define LTR501_LIGHT_CHANNEL() { \
.type = IIO_LIGHT, \
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
.scan_index = -1, \
}
static const struct iio_chan_spec ltr501_channels[] = {
LTR501_LIGHT_CHANNEL(),
LTR501_INTENSITY_CHANNEL(0, LTR501_ALS_DATA0, IIO_MOD_LIGHT_BOTH, 0,
ltr501_als_event_spec,
ARRAY_SIZE(ltr501_als_event_spec)),
LTR501_INTENSITY_CHANNEL(1, LTR501_ALS_DATA1, IIO_MOD_LIGHT_IR,
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
NULL, 0),
{
.type = IIO_PROXIMITY,
.address = LTR501_PS_DATA,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.scan_index = 2,
.scan_type = {
.sign = 'u',
.realbits = 11,
.storagebits = 16,
.endianness = IIO_CPU,
},
.event_spec = ltr501_pxs_event_spec,
.num_event_specs = ARRAY_SIZE(ltr501_pxs_event_spec),
.ext_info = ltr501_ext_info,
},
IIO_CHAN_SOFT_TIMESTAMP(3),
};
static const struct iio_chan_spec ltr301_channels[] = {
LTR501_LIGHT_CHANNEL(),
LTR501_INTENSITY_CHANNEL(0, LTR501_ALS_DATA0, IIO_MOD_LIGHT_BOTH, 0,
ltr501_als_event_spec,
ARRAY_SIZE(ltr501_als_event_spec)),
LTR501_INTENSITY_CHANNEL(1, LTR501_ALS_DATA1, IIO_MOD_LIGHT_IR,
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_INT_TIME) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
NULL, 0),
IIO_CHAN_SOFT_TIMESTAMP(2),
};
static int ltr501_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct ltr501_data *data = iio_priv(indio_dev);
__le16 buf[2];
int ret, i;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_LIGHT:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
mutex_lock(&data->lock_als);
ret = ltr501_read_als(data, buf);
mutex_unlock(&data->lock_als);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = ltr501_calculate_lux(le16_to_cpu(buf[1]),
le16_to_cpu(buf[0]));
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_RAW:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
switch (chan->type) {
case IIO_INTENSITY:
mutex_lock(&data->lock_als);
ret = ltr501_read_als(data, buf);
mutex_unlock(&data->lock_als);
if (ret < 0)
break;
*val = le16_to_cpu(chan->address == LTR501_ALS_DATA1 ?
buf[0] : buf[1]);
ret = IIO_VAL_INT;
break;
case IIO_PROXIMITY:
mutex_lock(&data->lock_ps);
ret = ltr501_read_ps(data);
mutex_unlock(&data->lock_ps);
if (ret < 0)
break;
*val = ret & LTR501_PS_DATA_MASK;
ret = IIO_VAL_INT;
break;
default:
ret = -EINVAL;
break;
}
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_INTENSITY:
i = (data->als_contr & data->chip_info->als_gain_mask)
>> data->chip_info->als_gain_shift;
*val = data->chip_info->als_gain[i].scale;
*val2 = data->chip_info->als_gain[i].uscale;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_PROXIMITY:
i = (data->ps_contr & LTR501_CONTR_PS_GAIN_MASK) >>
LTR501_CONTR_PS_GAIN_SHIFT;
*val = data->chip_info->ps_gain[i].scale;
*val2 = data->chip_info->ps_gain[i].uscale;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_INT_TIME:
switch (chan->type) {
case IIO_INTENSITY:
return ltr501_read_it_time(data, val, val2);
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SAMP_FREQ:
switch (chan->type) {
case IIO_INTENSITY:
return ltr501_als_read_samp_freq(data, val, val2);
case IIO_PROXIMITY:
return ltr501_ps_read_samp_freq(data, val, val2);
default:
return -EINVAL;
}
}
return -EINVAL;
}
static int ltr501_get_gain_index(const struct ltr501_gain *gain, int size,
int val, int val2)
{
int i;
for (i = 0; i < size; i++)
if (val == gain[i].scale && val2 == gain[i].uscale)
return i;
return -1;
}
static int ltr501_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct ltr501_data *data = iio_priv(indio_dev);
int i, ret, freq_val, freq_val2;
const struct ltr501_chip_info *info = data->chip_info;
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_INTENSITY:
i = ltr501_get_gain_index(info->als_gain,
info->als_gain_tbl_size,
val, val2);
if (i < 0) {
ret = -EINVAL;
break;
}
data->als_contr &= ~info->als_gain_mask;
data->als_contr |= i << info->als_gain_shift;
ret = regmap_write(data->regmap, LTR501_ALS_CONTR,
data->als_contr);
break;
case IIO_PROXIMITY:
i = ltr501_get_gain_index(info->ps_gain,
info->ps_gain_tbl_size,
val, val2);
if (i < 0) {
ret = -EINVAL;
break;
}
data->ps_contr &= ~LTR501_CONTR_PS_GAIN_MASK;
data->ps_contr |= i << LTR501_CONTR_PS_GAIN_SHIFT;
ret = regmap_write(data->regmap, LTR501_PS_CONTR,
data->ps_contr);
break;
default:
ret = -EINVAL;
break;
}
break;
case IIO_CHAN_INFO_INT_TIME:
switch (chan->type) {
case IIO_INTENSITY:
if (val != 0) {
ret = -EINVAL;
break;
}
mutex_lock(&data->lock_als);
ret = ltr501_set_it_time(data, val2);
mutex_unlock(&data->lock_als);
break;
default:
ret = -EINVAL;
break;
}
break;
case IIO_CHAN_INFO_SAMP_FREQ:
switch (chan->type) {
case IIO_INTENSITY:
ret = ltr501_als_read_samp_freq(data, &freq_val,
&freq_val2);
if (ret < 0)
break;
ret = ltr501_als_write_samp_freq(data, val, val2);
if (ret < 0)
break;
/* update persistence count when changing frequency */
ret = ltr501_write_intr_prst(data, chan->type,
0, data->als_period);
if (ret < 0)
ret = ltr501_als_write_samp_freq(data, freq_val,
freq_val2);
break;
case IIO_PROXIMITY:
ret = ltr501_ps_read_samp_freq(data, &freq_val,
&freq_val2);
if (ret < 0)
break;
ret = ltr501_ps_write_samp_freq(data, val, val2);
if (ret < 0)
break;
/* update persistence count when changing frequency */
ret = ltr501_write_intr_prst(data, chan->type,
0, data->ps_period);
if (ret < 0)
ret = ltr501_ps_write_samp_freq(data, freq_val,
freq_val2);
break;
default:
ret = -EINVAL;
break;
}
break;
default:
ret = -EINVAL;
break;
}
iio_device_release_direct_mode(indio_dev);
return ret;
}
static int ltr501_read_thresh(const struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
const struct ltr501_data *data = iio_priv(indio_dev);
int ret, thresh_data;
switch (chan->type) {
case IIO_INTENSITY:
switch (dir) {
case IIO_EV_DIR_RISING:
ret = regmap_bulk_read(data->regmap,
LTR501_ALS_THRESH_UP,
&thresh_data, 2);
if (ret < 0)
return ret;
*val = thresh_data & LTR501_ALS_THRESH_MASK;
return IIO_VAL_INT;
case IIO_EV_DIR_FALLING:
ret = regmap_bulk_read(data->regmap,
LTR501_ALS_THRESH_LOW,
&thresh_data, 2);
if (ret < 0)
return ret;
*val = thresh_data & LTR501_ALS_THRESH_MASK;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_PROXIMITY:
switch (dir) {
case IIO_EV_DIR_RISING:
ret = regmap_bulk_read(data->regmap,
LTR501_PS_THRESH_UP,
&thresh_data, 2);
if (ret < 0)
return ret;
*val = thresh_data & LTR501_PS_THRESH_MASK;
return IIO_VAL_INT;
case IIO_EV_DIR_FALLING:
ret = regmap_bulk_read(data->regmap,
LTR501_PS_THRESH_LOW,
&thresh_data, 2);
if (ret < 0)
return ret;
*val = thresh_data & LTR501_PS_THRESH_MASK;
return IIO_VAL_INT;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
return -EINVAL;
}
static int ltr501_write_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
struct ltr501_data *data = iio_priv(indio_dev);
int ret;
if (val < 0)
return -EINVAL;
switch (chan->type) {
case IIO_INTENSITY:
if (val > LTR501_ALS_THRESH_MASK)
return -EINVAL;
switch (dir) {
case IIO_EV_DIR_RISING:
mutex_lock(&data->lock_als);
ret = regmap_bulk_write(data->regmap,
LTR501_ALS_THRESH_UP,
&val, 2);
mutex_unlock(&data->lock_als);
return ret;
case IIO_EV_DIR_FALLING:
mutex_lock(&data->lock_als);
ret = regmap_bulk_write(data->regmap,
LTR501_ALS_THRESH_LOW,
&val, 2);
mutex_unlock(&data->lock_als);
return ret;
default:
return -EINVAL;
}
case IIO_PROXIMITY:
if (val > LTR501_PS_THRESH_MASK)
return -EINVAL;
switch (dir) {
case IIO_EV_DIR_RISING:
mutex_lock(&data->lock_ps);
ret = regmap_bulk_write(data->regmap,
LTR501_PS_THRESH_UP,
&val, 2);
mutex_unlock(&data->lock_ps);
return ret;
case IIO_EV_DIR_FALLING:
mutex_lock(&data->lock_ps);
ret = regmap_bulk_write(data->regmap,
LTR501_PS_THRESH_LOW,
&val, 2);
mutex_unlock(&data->lock_ps);
return ret;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
return -EINVAL;
}
static int ltr501_read_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
int ret;
switch (info) {
case IIO_EV_INFO_VALUE:
return ltr501_read_thresh(indio_dev, chan, type, dir,
info, val, val2);
case IIO_EV_INFO_PERIOD:
ret = ltr501_read_intr_prst(iio_priv(indio_dev),
chan->type, val2);
*val = *val2 / 1000000;
*val2 = *val2 % 1000000;
return ret;
default:
return -EINVAL;
}
return -EINVAL;
}
static int ltr501_write_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
switch (info) {
case IIO_EV_INFO_VALUE:
if (val2 != 0)
return -EINVAL;
return ltr501_write_thresh(indio_dev, chan, type, dir,
info, val, val2);
case IIO_EV_INFO_PERIOD:
return ltr501_write_intr_prst(iio_priv(indio_dev), chan->type,
val, val2);
default:
return -EINVAL;
}
return -EINVAL;
}
static int ltr501_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct ltr501_data *data = iio_priv(indio_dev);
int ret, status;
switch (chan->type) {
case IIO_INTENSITY:
ret = regmap_field_read(data->reg_als_intr, &status);
if (ret < 0)
return ret;
return status;
case IIO_PROXIMITY:
ret = regmap_field_read(data->reg_ps_intr, &status);
if (ret < 0)
return ret;
return status;
default:
return -EINVAL;
}
return -EINVAL;
}
static int ltr501_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct ltr501_data *data = iio_priv(indio_dev);
int ret;
/* only 1 and 0 are valid inputs */
if (state != 1 && state != 0)
return -EINVAL;
switch (chan->type) {
case IIO_INTENSITY:
mutex_lock(&data->lock_als);
ret = regmap_field_write(data->reg_als_intr, state);
mutex_unlock(&data->lock_als);
return ret;
case IIO_PROXIMITY:
mutex_lock(&data->lock_ps);
ret = regmap_field_write(data->reg_ps_intr, state);
mutex_unlock(&data->lock_ps);
return ret;
default:
return -EINVAL;
}
return -EINVAL;
}
static ssize_t ltr501_show_proximity_scale_avail(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct ltr501_data *data = iio_priv(dev_to_iio_dev(dev));
const struct ltr501_chip_info *info = data->chip_info;
ssize_t len = 0;
int i;
for (i = 0; i < info->ps_gain_tbl_size; i++) {
if (info->ps_gain[i].scale == LTR501_RESERVED_GAIN)
continue;
len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
info->ps_gain[i].scale,
info->ps_gain[i].uscale);
}
buf[len - 1] = '\n';
return len;
}
static ssize_t ltr501_show_intensity_scale_avail(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct ltr501_data *data = iio_priv(dev_to_iio_dev(dev));
const struct ltr501_chip_info *info = data->chip_info;
ssize_t len = 0;
int i;
for (i = 0; i < info->als_gain_tbl_size; i++) {
if (info->als_gain[i].scale == LTR501_RESERVED_GAIN)
continue;
len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
info->als_gain[i].scale,
info->als_gain[i].uscale);
}
buf[len - 1] = '\n';
return len;
}
static IIO_CONST_ATTR_INT_TIME_AVAIL("0.05 0.1 0.2 0.4");
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("20 10 5 2 1 0.5");
static IIO_DEVICE_ATTR(in_proximity_scale_available, S_IRUGO,
ltr501_show_proximity_scale_avail, NULL, 0);
static IIO_DEVICE_ATTR(in_intensity_scale_available, S_IRUGO,
ltr501_show_intensity_scale_avail, NULL, 0);
static struct attribute *ltr501_attributes[] = {
&iio_dev_attr_in_proximity_scale_available.dev_attr.attr,
&iio_dev_attr_in_intensity_scale_available.dev_attr.attr,
&iio_const_attr_integration_time_available.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL
};
static struct attribute *ltr301_attributes[] = {
&iio_dev_attr_in_intensity_scale_available.dev_attr.attr,
&iio_const_attr_integration_time_available.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL
};
static const struct attribute_group ltr501_attribute_group = {
.attrs = ltr501_attributes,
};
static const struct attribute_group ltr301_attribute_group = {
.attrs = ltr301_attributes,
};
static const struct iio_info ltr501_info_no_irq = {
.read_raw = ltr501_read_raw,
.write_raw = ltr501_write_raw,
.attrs = <r501_attribute_group,
};
static const struct iio_info ltr501_info = {
.read_raw = ltr501_read_raw,
.write_raw = ltr501_write_raw,
.attrs = <r501_attribute_group,
.read_event_value = <r501_read_event,
.write_event_value = <r501_write_event,
.read_event_config = <r501_read_event_config,
.write_event_config = <r501_write_event_config,
};
static const struct iio_info ltr301_info_no_irq = {
.read_raw = ltr501_read_raw,
.write_raw = ltr501_write_raw,
.attrs = <r301_attribute_group,
};
static const struct iio_info ltr301_info = {
.read_raw = ltr501_read_raw,
.write_raw = ltr501_write_raw,
.attrs = <r301_attribute_group,
.read_event_value = <r501_read_event,
.write_event_value = <r501_write_event,
.read_event_config = <r501_read_event_config,
.write_event_config = <r501_write_event_config,
};
static const struct ltr501_chip_info ltr501_chip_info_tbl[] = {
[ltr501] = {
.partid = 0x08,
.als_gain = ltr501_als_gain_tbl,
.als_gain_tbl_size = ARRAY_SIZE(ltr501_als_gain_tbl),
.ps_gain = ltr501_ps_gain_tbl,
.ps_gain_tbl_size = ARRAY_SIZE(ltr501_ps_gain_tbl),
.als_mode_active = BIT(0) | BIT(1),
.als_gain_mask = BIT(3),
.als_gain_shift = 3,
.info = <r501_info,
.info_no_irq = <r501_info_no_irq,
.channels = ltr501_channels,
.no_channels = ARRAY_SIZE(ltr501_channels),
},
[ltr559] = {
.partid = 0x09,
.als_gain = ltr559_als_gain_tbl,
.als_gain_tbl_size = ARRAY_SIZE(ltr559_als_gain_tbl),
.ps_gain = ltr559_ps_gain_tbl,
.ps_gain_tbl_size = ARRAY_SIZE(ltr559_ps_gain_tbl),
.als_mode_active = BIT(0),
.als_gain_mask = BIT(2) | BIT(3) | BIT(4),
.als_gain_shift = 2,
.info = <r501_info,
.info_no_irq = <r501_info_no_irq,
.channels = ltr501_channels,
.no_channels = ARRAY_SIZE(ltr501_channels),
},
[ltr301] = {
.partid = 0x08,
.als_gain = ltr501_als_gain_tbl,
.als_gain_tbl_size = ARRAY_SIZE(ltr501_als_gain_tbl),
.als_mode_active = BIT(0) | BIT(1),
.als_gain_mask = BIT(3),
.als_gain_shift = 3,
.info = <r301_info,
.info_no_irq = <r301_info_no_irq,
.channels = ltr301_channels,
.no_channels = ARRAY_SIZE(ltr301_channels),
},
[ltr303] = {
.partid = 0x0A,
.als_gain = ltr559_als_gain_tbl,
.als_gain_tbl_size = ARRAY_SIZE(ltr559_als_gain_tbl),
.als_mode_active = BIT(0),
.als_gain_mask = BIT(2) | BIT(3) | BIT(4),
.als_gain_shift = 2,
.info = <r301_info,
.info_no_irq = <r301_info_no_irq,
.channels = ltr301_channels,
.no_channels = ARRAY_SIZE(ltr301_channels),
},
};
static int ltr501_write_contr(struct ltr501_data *data, u8 als_val, u8 ps_val)
{
int ret;
ret = regmap_write(data->regmap, LTR501_ALS_CONTR, als_val);
if (ret < 0)
return ret;
return regmap_write(data->regmap, LTR501_PS_CONTR, ps_val);
}
static irqreturn_t ltr501_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct ltr501_data *data = iio_priv(indio_dev);
struct {
u16 channels[3];
s64 ts __aligned(8);
} scan;
__le16 als_buf[2];
u8 mask = 0;
int j = 0;
int ret, psdata;
memset(&scan, 0, sizeof(scan));
/* figure out which data needs to be ready */
if (test_bit(0, indio_dev->active_scan_mask) ||
test_bit(1, indio_dev->active_scan_mask))
mask |= LTR501_STATUS_ALS_RDY;
if (test_bit(2, indio_dev->active_scan_mask))
mask |= LTR501_STATUS_PS_RDY;
ret = ltr501_drdy(data, mask);
if (ret < 0)
goto done;
if (mask & LTR501_STATUS_ALS_RDY) {
ret = regmap_bulk_read(data->regmap, LTR501_ALS_DATA1,
als_buf, sizeof(als_buf));
if (ret < 0)
goto done;
if (test_bit(0, indio_dev->active_scan_mask))
scan.channels[j++] = le16_to_cpu(als_buf[1]);
if (test_bit(1, indio_dev->active_scan_mask))
scan.channels[j++] = le16_to_cpu(als_buf[0]);
}
if (mask & LTR501_STATUS_PS_RDY) {
ret = regmap_bulk_read(data->regmap, LTR501_PS_DATA,
&psdata, 2);
if (ret < 0)
goto done;
scan.channels[j++] = psdata & LTR501_PS_DATA_MASK;
}
iio_push_to_buffers_with_timestamp(indio_dev, &scan,
iio_get_time_ns(indio_dev));
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static irqreturn_t ltr501_interrupt_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct ltr501_data *data = iio_priv(indio_dev);
int ret, status;
ret = regmap_read(data->regmap, LTR501_ALS_PS_STATUS, &status);
if (ret < 0) {
dev_err(&data->client->dev,
"irq read int reg failed\n");
return IRQ_HANDLED;
}
if (status & LTR501_STATUS_ALS_INTR)
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(indio_dev));
if (status & LTR501_STATUS_PS_INTR)
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(indio_dev));
return IRQ_HANDLED;
}
static int ltr501_init(struct ltr501_data *data)
{
int ret, status;
ret = regmap_read(data->regmap, LTR501_ALS_CONTR, &status);
if (ret < 0)
return ret;
data->als_contr = status | data->chip_info->als_mode_active;
ret = regmap_read(data->regmap, LTR501_PS_CONTR, &status);
if (ret < 0)
return ret;
data->ps_contr = status | LTR501_CONTR_ACTIVE;
ret = ltr501_read_intr_prst(data, IIO_INTENSITY, &data->als_period);
if (ret < 0)
return ret;
ret = ltr501_read_intr_prst(data, IIO_PROXIMITY, &data->ps_period);
if (ret < 0)
return ret;
return ltr501_write_contr(data, data->als_contr, data->ps_contr);
}
static bool ltr501_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case LTR501_ALS_DATA1:
case LTR501_ALS_DATA1_UPPER:
case LTR501_ALS_DATA0:
case LTR501_ALS_DATA0_UPPER:
case LTR501_ALS_PS_STATUS:
case LTR501_PS_DATA:
case LTR501_PS_DATA_UPPER:
return true;
default:
return false;
}
}
static const struct regmap_config ltr501_regmap_config = {
.name = LTR501_REGMAP_NAME,
.reg_bits = 8,
.val_bits = 8,
.max_register = LTR501_MAX_REG,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = ltr501_is_volatile_reg,
};
static int ltr501_powerdown(struct ltr501_data *data)
{
return ltr501_write_contr(data, data->als_contr &
~data->chip_info->als_mode_active,
data->ps_contr & ~LTR501_CONTR_ACTIVE);
}
static const char *ltr501_match_acpi_device(struct device *dev, int *chip_idx)
{
const struct acpi_device_id *id;
id = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!id)
return NULL;
*chip_idx = id->driver_data;
return dev_name(dev);
}
static int ltr501_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
static const char * const regulator_names[] = { "vdd", "vddio" };
struct ltr501_data *data;
struct iio_dev *indio_dev;
struct regmap *regmap;
int ret, partid, chip_idx = 0;
const char *name = NULL;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
regmap = devm_regmap_init_i2c(client, <r501_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "Regmap initialization failed.\n");
return PTR_ERR(regmap);
}
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->regmap = regmap;
mutex_init(&data->lock_als);
mutex_init(&data->lock_ps);
ret = devm_regulator_bulk_get_enable(&client->dev,
ARRAY_SIZE(regulator_names),
regulator_names);
if (ret)
return dev_err_probe(&client->dev, ret,
"Failed to get regulators\n");
data->reg_it = devm_regmap_field_alloc(&client->dev, regmap,
reg_field_it);
if (IS_ERR(data->reg_it)) {
dev_err(&client->dev, "Integ time reg field init failed.\n");
return PTR_ERR(data->reg_it);
}
data->reg_als_intr = devm_regmap_field_alloc(&client->dev, regmap,
reg_field_als_intr);
if (IS_ERR(data->reg_als_intr)) {
dev_err(&client->dev, "ALS intr mode reg field init failed\n");
return PTR_ERR(data->reg_als_intr);
}
data->reg_ps_intr = devm_regmap_field_alloc(&client->dev, regmap,
reg_field_ps_intr);
if (IS_ERR(data->reg_ps_intr)) {
dev_err(&client->dev, "PS intr mode reg field init failed.\n");
return PTR_ERR(data->reg_ps_intr);
}
data->reg_als_rate = devm_regmap_field_alloc(&client->dev, regmap,
reg_field_als_rate);
if (IS_ERR(data->reg_als_rate)) {
dev_err(&client->dev, "ALS samp rate field init failed.\n");
return PTR_ERR(data->reg_als_rate);
}
data->reg_ps_rate = devm_regmap_field_alloc(&client->dev, regmap,
reg_field_ps_rate);
if (IS_ERR(data->reg_ps_rate)) {
dev_err(&client->dev, "PS samp rate field init failed.\n");
return PTR_ERR(data->reg_ps_rate);
}
data->reg_als_prst = devm_regmap_field_alloc(&client->dev, regmap,
reg_field_als_prst);
if (IS_ERR(data->reg_als_prst)) {
dev_err(&client->dev, "ALS prst reg field init failed\n");
return PTR_ERR(data->reg_als_prst);
}
data->reg_ps_prst = devm_regmap_field_alloc(&client->dev, regmap,
reg_field_ps_prst);
if (IS_ERR(data->reg_ps_prst)) {
dev_err(&client->dev, "PS prst reg field init failed.\n");
return PTR_ERR(data->reg_ps_prst);
}
ret = regmap_read(data->regmap, LTR501_PART_ID, &partid);
if (ret < 0)
return ret;
if (id) {
name = id->name;
chip_idx = id->driver_data;
} else if (ACPI_HANDLE(&client->dev)) {
name = ltr501_match_acpi_device(&client->dev, &chip_idx);
} else {
return -ENODEV;
}
data->chip_info = <r501_chip_info_tbl[chip_idx];
if ((partid >> 4) != data->chip_info->partid)
return -ENODEV;
if (device_property_read_u32(&client->dev, "proximity-near-level",
&data->near_level))
data->near_level = 0;
indio_dev->info = data->chip_info->info;
indio_dev->channels = data->chip_info->channels;
indio_dev->num_channels = data->chip_info->no_channels;
indio_dev->name = name;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = ltr501_init(data);
if (ret < 0)
return ret;
if (client->irq > 0) {
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, ltr501_interrupt_handler,
IRQF_TRIGGER_FALLING |
IRQF_ONESHOT,
"ltr501_thresh_event",
indio_dev);
if (ret) {
dev_err(&client->dev, "request irq (%d) failed\n",
client->irq);
return ret;
}
} else {
indio_dev->info = data->chip_info->info_no_irq;
}
ret = iio_triggered_buffer_setup(indio_dev, NULL,
ltr501_trigger_handler, NULL);
if (ret)
goto powerdown_on_error;
ret = iio_device_register(indio_dev);
if (ret)
goto error_unreg_buffer;
return 0;
error_unreg_buffer:
iio_triggered_buffer_cleanup(indio_dev);
powerdown_on_error:
ltr501_powerdown(data);
return ret;
}
static void ltr501_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
iio_device_unregister(indio_dev);
iio_triggered_buffer_cleanup(indio_dev);
ltr501_powerdown(iio_priv(indio_dev));
}
static int ltr501_suspend(struct device *dev)
{
struct ltr501_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
return ltr501_powerdown(data);
}
static int ltr501_resume(struct device *dev)
{
struct ltr501_data *data = iio_priv(i2c_get_clientdata(
to_i2c_client(dev)));
return ltr501_write_contr(data, data->als_contr,
data->ps_contr);
}
static DEFINE_SIMPLE_DEV_PM_OPS(ltr501_pm_ops, ltr501_suspend, ltr501_resume);
static const struct acpi_device_id ltr_acpi_match[] = {
{ "LTER0501", ltr501 },
{ "LTER0559", ltr559 },
{ "LTER0301", ltr301 },
{ },
};
MODULE_DEVICE_TABLE(acpi, ltr_acpi_match);
static const struct i2c_device_id ltr501_id[] = {
{ "ltr501", ltr501 },
{ "ltr559", ltr559 },
{ "ltr301", ltr301 },
{ "ltr303", ltr303 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ltr501_id);
static const struct of_device_id ltr501_of_match[] = {
{ .compatible = "liteon,ltr501", },
{ .compatible = "liteon,ltr559", },
{ .compatible = "liteon,ltr301", },
{ .compatible = "liteon,ltr303", },
{}
};
MODULE_DEVICE_TABLE(of, ltr501_of_match);
static struct i2c_driver ltr501_driver = {
.driver = {
.name = LTR501_DRV_NAME,
.of_match_table = ltr501_of_match,
.pm = pm_sleep_ptr(<r501_pm_ops),
.acpi_match_table = ACPI_PTR(ltr_acpi_match),
},
.probe = ltr501_probe,
.remove = ltr501_remove,
.id_table = ltr501_id,
};
module_i2c_driver(ltr501_driver);
MODULE_AUTHOR("Peter Meerwald <[email protected]>");
MODULE_DESCRIPTION("Lite-On LTR501 ambient light and proximity sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/ltr501.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AL3010 - Dyna Image Ambient Light Sensor
*
* Copyright (c) 2014, Intel Corporation.
* Copyright (c) 2016, Dyna-Image Corp.
* Copyright (c) 2020, David Heidelberg, Michał Mirosław, Dmitry Osipenko
*
* IIO driver for AL3010 (7-bit I2C slave address 0x1C).
*
* TODO: interrupt support, thresholds
* When the driver will get support for interrupt handling, then interrupt
* will need to be disabled before turning sensor OFF in order to avoid
* potential races with the interrupt handling.
*/
#include <linux/bitfield.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define AL3010_DRV_NAME "al3010"
#define AL3010_REG_SYSTEM 0x00
#define AL3010_REG_DATA_LOW 0x0c
#define AL3010_REG_CONFIG 0x10
#define AL3010_CONFIG_DISABLE 0x00
#define AL3010_CONFIG_ENABLE 0x01
#define AL3010_GAIN_MASK GENMASK(6,4)
#define AL3010_SCALE_AVAILABLE "1.1872 0.2968 0.0742 0.018"
enum al3xxxx_range {
AL3XXX_RANGE_1, /* 77806 lx */
AL3XXX_RANGE_2, /* 19542 lx */
AL3XXX_RANGE_3, /* 4863 lx */
AL3XXX_RANGE_4 /* 1216 lx */
};
static const int al3010_scales[][2] = {
{0, 1187200}, {0, 296800}, {0, 74200}, {0, 18600}
};
struct al3010_data {
struct i2c_client *client;
};
static const struct iio_chan_spec al3010_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
}
};
static IIO_CONST_ATTR(in_illuminance_scale_available, AL3010_SCALE_AVAILABLE);
static struct attribute *al3010_attributes[] = {
&iio_const_attr_in_illuminance_scale_available.dev_attr.attr,
NULL,
};
static const struct attribute_group al3010_attribute_group = {
.attrs = al3010_attributes,
};
static int al3010_set_pwr(struct i2c_client *client, bool pwr)
{
u8 val = pwr ? AL3010_CONFIG_ENABLE : AL3010_CONFIG_DISABLE;
return i2c_smbus_write_byte_data(client, AL3010_REG_SYSTEM, val);
}
static void al3010_set_pwr_off(void *_data)
{
struct al3010_data *data = _data;
al3010_set_pwr(data->client, false);
}
static int al3010_init(struct al3010_data *data)
{
int ret;
ret = al3010_set_pwr(data->client, true);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client, AL3010_REG_CONFIG,
FIELD_PREP(AL3010_GAIN_MASK,
AL3XXX_RANGE_3));
if (ret < 0)
return ret;
return 0;
}
static int al3010_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct al3010_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
/*
* ALS ADC value is stored in two adjacent registers:
* - low byte of output is stored at AL3010_REG_DATA_LOW
* - high byte of output is stored at AL3010_REG_DATA_LOW + 1
*/
ret = i2c_smbus_read_word_data(data->client,
AL3010_REG_DATA_LOW);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = i2c_smbus_read_byte_data(data->client,
AL3010_REG_CONFIG);
if (ret < 0)
return ret;
ret = FIELD_GET(AL3010_GAIN_MASK, ret);
*val = al3010_scales[ret][0];
*val2 = al3010_scales[ret][1];
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
}
static int al3010_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct al3010_data *data = iio_priv(indio_dev);
int i;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
for (i = 0; i < ARRAY_SIZE(al3010_scales); i++) {
if (val != al3010_scales[i][0] ||
val2 != al3010_scales[i][1])
continue;
return i2c_smbus_write_byte_data(data->client,
AL3010_REG_CONFIG,
FIELD_PREP(AL3010_GAIN_MASK, i));
}
break;
}
return -EINVAL;
}
static const struct iio_info al3010_info = {
.read_raw = al3010_read_raw,
.write_raw = al3010_write_raw,
.attrs = &al3010_attribute_group,
};
static int al3010_probe(struct i2c_client *client)
{
struct al3010_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
indio_dev->info = &al3010_info;
indio_dev->name = AL3010_DRV_NAME;
indio_dev->channels = al3010_channels;
indio_dev->num_channels = ARRAY_SIZE(al3010_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = al3010_init(data);
if (ret < 0) {
dev_err(&client->dev, "al3010 chip init failed\n");
return ret;
}
ret = devm_add_action_or_reset(&client->dev,
al3010_set_pwr_off,
data);
if (ret < 0)
return ret;
return devm_iio_device_register(&client->dev, indio_dev);
}
static int al3010_suspend(struct device *dev)
{
return al3010_set_pwr(to_i2c_client(dev), false);
}
static int al3010_resume(struct device *dev)
{
return al3010_set_pwr(to_i2c_client(dev), true);
}
static DEFINE_SIMPLE_DEV_PM_OPS(al3010_pm_ops, al3010_suspend, al3010_resume);
static const struct i2c_device_id al3010_id[] = {
{"al3010", },
{}
};
MODULE_DEVICE_TABLE(i2c, al3010_id);
static const struct of_device_id al3010_of_match[] = {
{ .compatible = "dynaimage,al3010", },
{},
};
MODULE_DEVICE_TABLE(of, al3010_of_match);
static struct i2c_driver al3010_driver = {
.driver = {
.name = AL3010_DRV_NAME,
.of_match_table = al3010_of_match,
.pm = pm_sleep_ptr(&al3010_pm_ops),
},
.probe = al3010_probe,
.id_table = al3010_id,
};
module_i2c_driver(al3010_driver);
MODULE_AUTHOR("Daniel Baluta <[email protected]>");
MODULE_AUTHOR("David Heidelberg <[email protected]>");
MODULE_DESCRIPTION("AL3010 Ambient Light Sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/al3010.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/iio/light/tsl2563.c
*
* Copyright (C) 2008 Nokia Corporation
*
* Written by Timo O. Karjalainen <[email protected]>
* Contact: Amit Kucheria <[email protected]>
*
* Converted to IIO driver
* Amit Kucheria <[email protected]>
*/
#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/math.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/pm.h>
#include <linux/property.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
/* Use this many bits for fraction part. */
#define ADC_FRAC_BITS 14
/* Given number of 1/10000's in ADC_FRAC_BITS precision. */
#define FRAC10K(f) (((f) * BIT(ADC_FRAC_BITS)) / (10000))
/* Bits used for fraction in calibration coefficients.*/
#define CALIB_FRAC_BITS 10
/* Decimal 10^(digits in sysfs presentation) */
#define CALIB_BASE_SYSFS 1000
#define TSL2563_CMD BIT(7)
#define TSL2563_CLEARINT BIT(6)
#define TSL2563_REG_CTRL 0x00
#define TSL2563_REG_TIMING 0x01
#define TSL2563_REG_LOW 0x02 /* data0 low threshold, 2 bytes */
#define TSL2563_REG_HIGH 0x04 /* data0 high threshold, 2 bytes */
#define TSL2563_REG_INT 0x06
#define TSL2563_REG_ID 0x0a
#define TSL2563_REG_DATA0 0x0c /* broadband sensor value, 2 bytes */
#define TSL2563_REG_DATA1 0x0e /* infrared sensor value, 2 bytes */
#define TSL2563_CMD_POWER_ON 0x03
#define TSL2563_CMD_POWER_OFF 0x00
#define TSL2563_CTRL_POWER_MASK GENMASK(1, 0)
#define TSL2563_TIMING_13MS 0x00
#define TSL2563_TIMING_100MS 0x01
#define TSL2563_TIMING_400MS 0x02
#define TSL2563_TIMING_MASK GENMASK(1, 0)
#define TSL2563_TIMING_GAIN16 0x10
#define TSL2563_TIMING_GAIN1 0x00
#define TSL2563_INT_DISABLED 0x00
#define TSL2563_INT_LEVEL 0x10
#define TSL2563_INT_MASK GENMASK(5, 4)
#define TSL2563_INT_PERSIST(n) ((n) & GENMASK(3, 0))
struct tsl2563_gainlevel_coeff {
u8 gaintime;
u16 min;
u16 max;
};
static const struct tsl2563_gainlevel_coeff tsl2563_gainlevel_table[] = {
{
.gaintime = TSL2563_TIMING_400MS | TSL2563_TIMING_GAIN16,
.min = 0,
.max = 65534,
}, {
.gaintime = TSL2563_TIMING_400MS | TSL2563_TIMING_GAIN1,
.min = 2048,
.max = 65534,
}, {
.gaintime = TSL2563_TIMING_100MS | TSL2563_TIMING_GAIN1,
.min = 4095,
.max = 37177,
}, {
.gaintime = TSL2563_TIMING_13MS | TSL2563_TIMING_GAIN1,
.min = 3000,
.max = 65535,
},
};
struct tsl2563_chip {
struct mutex lock;
struct i2c_client *client;
struct delayed_work poweroff_work;
/* Remember state for suspend and resume functions */
bool suspended;
struct tsl2563_gainlevel_coeff const *gainlevel;
u16 low_thres;
u16 high_thres;
u8 intr;
bool int_enabled;
/* Calibration coefficients */
u32 calib0;
u32 calib1;
int cover_comp_gain;
/* Cache current values, to be returned while suspended */
u32 data0;
u32 data1;
};
static int tsl2563_set_power(struct tsl2563_chip *chip, int on)
{
struct i2c_client *client = chip->client;
u8 cmd;
cmd = on ? TSL2563_CMD_POWER_ON : TSL2563_CMD_POWER_OFF;
return i2c_smbus_write_byte_data(client,
TSL2563_CMD | TSL2563_REG_CTRL, cmd);
}
/*
* Return value is 0 for off, 1 for on, or a negative error
* code if reading failed.
*/
static int tsl2563_get_power(struct tsl2563_chip *chip)
{
struct i2c_client *client = chip->client;
int ret;
ret = i2c_smbus_read_byte_data(client, TSL2563_CMD | TSL2563_REG_CTRL);
if (ret < 0)
return ret;
return (ret & TSL2563_CTRL_POWER_MASK) == TSL2563_CMD_POWER_ON;
}
static int tsl2563_configure(struct tsl2563_chip *chip)
{
int ret;
ret = i2c_smbus_write_byte_data(chip->client,
TSL2563_CMD | TSL2563_REG_TIMING,
chip->gainlevel->gaintime);
if (ret)
goto error_ret;
ret = i2c_smbus_write_word_data(chip->client,
TSL2563_CMD | TSL2563_REG_HIGH,
chip->high_thres);
if (ret)
goto error_ret;
ret = i2c_smbus_write_word_data(chip->client,
TSL2563_CMD | TSL2563_REG_LOW,
chip->low_thres);
if (ret)
goto error_ret;
/*
* Interrupt register is automatically written anyway if it is relevant
* so is not here.
*/
error_ret:
return ret;
}
static void tsl2563_poweroff_work(struct work_struct *work)
{
struct tsl2563_chip *chip =
container_of(work, struct tsl2563_chip, poweroff_work.work);
tsl2563_set_power(chip, 0);
}
static int tsl2563_detect(struct tsl2563_chip *chip)
{
int ret;
ret = tsl2563_set_power(chip, 1);
if (ret)
return ret;
ret = tsl2563_get_power(chip);
if (ret < 0)
return ret;
return ret ? 0 : -ENODEV;
}
static int tsl2563_read_id(struct tsl2563_chip *chip, u8 *id)
{
struct i2c_client *client = chip->client;
int ret;
ret = i2c_smbus_read_byte_data(client, TSL2563_CMD | TSL2563_REG_ID);
if (ret < 0)
return ret;
*id = ret;
return 0;
}
static int tsl2563_configure_irq(struct tsl2563_chip *chip, bool enable)
{
int ret;
chip->intr &= ~TSL2563_INT_MASK;
if (enable)
chip->intr |= TSL2563_INT_LEVEL;
ret = i2c_smbus_write_byte_data(chip->client,
TSL2563_CMD | TSL2563_REG_INT,
chip->intr);
if (ret < 0)
return ret;
chip->int_enabled = enable;
return 0;
}
/*
* "Normalized" ADC value is one obtained with 400ms of integration time and
* 16x gain. This function returns the number of bits of shift needed to
* convert between normalized values and HW values obtained using given
* timing and gain settings.
*/
static int tsl2563_adc_shiftbits(u8 timing)
{
int shift = 0;
switch (timing & TSL2563_TIMING_MASK) {
case TSL2563_TIMING_13MS:
shift += 5;
break;
case TSL2563_TIMING_100MS:
shift += 2;
break;
case TSL2563_TIMING_400MS:
/* no-op */
break;
}
if (!(timing & TSL2563_TIMING_GAIN16))
shift += 4;
return shift;
}
/* Convert a HW ADC value to normalized scale. */
static u32 tsl2563_normalize_adc(u16 adc, u8 timing)
{
return adc << tsl2563_adc_shiftbits(timing);
}
static void tsl2563_wait_adc(struct tsl2563_chip *chip)
{
unsigned int delay;
switch (chip->gainlevel->gaintime & TSL2563_TIMING_MASK) {
case TSL2563_TIMING_13MS:
delay = 14;
break;
case TSL2563_TIMING_100MS:
delay = 101;
break;
default:
delay = 402;
}
/*
* TODO: Make sure that we wait at least required delay but why we
* have to extend it one tick more?
*/
schedule_timeout_interruptible(msecs_to_jiffies(delay) + 2);
}
static int tsl2563_adjust_gainlevel(struct tsl2563_chip *chip, u16 adc)
{
struct i2c_client *client = chip->client;
if (adc > chip->gainlevel->max || adc < chip->gainlevel->min) {
(adc > chip->gainlevel->max) ?
chip->gainlevel++ : chip->gainlevel--;
i2c_smbus_write_byte_data(client,
TSL2563_CMD | TSL2563_REG_TIMING,
chip->gainlevel->gaintime);
tsl2563_wait_adc(chip);
tsl2563_wait_adc(chip);
return 1;
} else
return 0;
}
static int tsl2563_get_adc(struct tsl2563_chip *chip)
{
struct i2c_client *client = chip->client;
u16 adc0, adc1;
int retry = 1;
int ret = 0;
if (chip->suspended)
goto out;
if (!chip->int_enabled) {
cancel_delayed_work_sync(&chip->poweroff_work);
if (!tsl2563_get_power(chip)) {
ret = tsl2563_set_power(chip, 1);
if (ret)
goto out;
ret = tsl2563_configure(chip);
if (ret)
goto out;
tsl2563_wait_adc(chip);
}
}
while (retry) {
ret = i2c_smbus_read_word_data(client,
TSL2563_CMD | TSL2563_REG_DATA0);
if (ret < 0)
goto out;
adc0 = ret;
ret = i2c_smbus_read_word_data(client,
TSL2563_CMD | TSL2563_REG_DATA1);
if (ret < 0)
goto out;
adc1 = ret;
retry = tsl2563_adjust_gainlevel(chip, adc0);
}
chip->data0 = tsl2563_normalize_adc(adc0, chip->gainlevel->gaintime);
chip->data1 = tsl2563_normalize_adc(adc1, chip->gainlevel->gaintime);
if (!chip->int_enabled)
schedule_delayed_work(&chip->poweroff_work, 5 * HZ);
ret = 0;
out:
return ret;
}
static inline int tsl2563_calib_to_sysfs(u32 calib)
{
return (int)DIV_ROUND_CLOSEST(calib * CALIB_BASE_SYSFS, BIT(CALIB_FRAC_BITS));
}
static inline u32 tsl2563_calib_from_sysfs(int value)
{
/* Make a fraction from a number n that was multiplied with b. */
return (((u32) value) << CALIB_FRAC_BITS) / CALIB_BASE_SYSFS;
}
/*
* Conversions between lux and ADC values.
*
* The basic formula is lux = c0 * adc0 - c1 * adc1, where c0 and c1 are
* appropriate constants. Different constants are needed for different
* kinds of light, determined by the ratio adc1/adc0 (basically the ratio
* of the intensities in infrared and visible wavelengths). lux_table below
* lists the upper threshold of the adc1/adc0 ratio and the corresponding
* constants.
*/
struct tsl2563_lux_coeff {
unsigned long ch_ratio;
unsigned long ch0_coeff;
unsigned long ch1_coeff;
};
static const struct tsl2563_lux_coeff lux_table[] = {
{
.ch_ratio = FRAC10K(1300),
.ch0_coeff = FRAC10K(315),
.ch1_coeff = FRAC10K(262),
}, {
.ch_ratio = FRAC10K(2600),
.ch0_coeff = FRAC10K(337),
.ch1_coeff = FRAC10K(430),
}, {
.ch_ratio = FRAC10K(3900),
.ch0_coeff = FRAC10K(363),
.ch1_coeff = FRAC10K(529),
}, {
.ch_ratio = FRAC10K(5200),
.ch0_coeff = FRAC10K(392),
.ch1_coeff = FRAC10K(605),
}, {
.ch_ratio = FRAC10K(6500),
.ch0_coeff = FRAC10K(229),
.ch1_coeff = FRAC10K(291),
}, {
.ch_ratio = FRAC10K(8000),
.ch0_coeff = FRAC10K(157),
.ch1_coeff = FRAC10K(180),
}, {
.ch_ratio = FRAC10K(13000),
.ch0_coeff = FRAC10K(34),
.ch1_coeff = FRAC10K(26),
}, {
.ch_ratio = ULONG_MAX,
.ch0_coeff = 0,
.ch1_coeff = 0,
},
};
/* Convert normalized, scaled ADC values to lux. */
static unsigned int tsl2563_adc_to_lux(u32 adc0, u32 adc1)
{
const struct tsl2563_lux_coeff *lp = lux_table;
unsigned long ratio, lux, ch0 = adc0, ch1 = adc1;
ratio = ch0 ? ((ch1 << ADC_FRAC_BITS) / ch0) : ULONG_MAX;
while (lp->ch_ratio < ratio)
lp++;
lux = ch0 * lp->ch0_coeff - ch1 * lp->ch1_coeff;
return (unsigned int) (lux >> ADC_FRAC_BITS);
}
/* Apply calibration coefficient to ADC count. */
static u32 tsl2563_calib_adc(u32 adc, u32 calib)
{
unsigned long scaled = adc;
scaled *= calib;
scaled >>= CALIB_FRAC_BITS;
return (u32) scaled;
}
static int tsl2563_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct tsl2563_chip *chip = iio_priv(indio_dev);
if (mask != IIO_CHAN_INFO_CALIBSCALE)
return -EINVAL;
if (chan->channel2 == IIO_MOD_LIGHT_BOTH)
chip->calib0 = tsl2563_calib_from_sysfs(val);
else if (chan->channel2 == IIO_MOD_LIGHT_IR)
chip->calib1 = tsl2563_calib_from_sysfs(val);
else
return -EINVAL;
return 0;
}
static int tsl2563_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
int ret = -EINVAL;
u32 calib0, calib1;
struct tsl2563_chip *chip = iio_priv(indio_dev);
mutex_lock(&chip->lock);
switch (mask) {
case IIO_CHAN_INFO_RAW:
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_LIGHT:
ret = tsl2563_get_adc(chip);
if (ret)
goto error_ret;
calib0 = tsl2563_calib_adc(chip->data0, chip->calib0) *
chip->cover_comp_gain;
calib1 = tsl2563_calib_adc(chip->data1, chip->calib1) *
chip->cover_comp_gain;
*val = tsl2563_adc_to_lux(calib0, calib1);
ret = IIO_VAL_INT;
break;
case IIO_INTENSITY:
ret = tsl2563_get_adc(chip);
if (ret)
goto error_ret;
if (chan->channel2 == IIO_MOD_LIGHT_BOTH)
*val = chip->data0;
else
*val = chip->data1;
ret = IIO_VAL_INT;
break;
default:
break;
}
break;
case IIO_CHAN_INFO_CALIBSCALE:
if (chan->channel2 == IIO_MOD_LIGHT_BOTH)
*val = tsl2563_calib_to_sysfs(chip->calib0);
else
*val = tsl2563_calib_to_sysfs(chip->calib1);
ret = IIO_VAL_INT;
break;
default:
ret = -EINVAL;
goto error_ret;
}
error_ret:
mutex_unlock(&chip->lock);
return ret;
}
static const struct iio_event_spec tsl2563_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec tsl2563_channels[] = {
{
.type = IIO_LIGHT,
.indexed = 1,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.channel = 0,
}, {
.type = IIO_INTENSITY,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_BOTH,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
.event_spec = tsl2563_events,
.num_event_specs = ARRAY_SIZE(tsl2563_events),
}, {
.type = IIO_INTENSITY,
.modified = 1,
.channel2 = IIO_MOD_LIGHT_IR,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_CALIBSCALE),
}
};
static int tsl2563_read_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info, int *val,
int *val2)
{
struct tsl2563_chip *chip = iio_priv(indio_dev);
switch (dir) {
case IIO_EV_DIR_RISING:
*val = chip->high_thres;
break;
case IIO_EV_DIR_FALLING:
*val = chip->low_thres;
break;
default:
return -EINVAL;
}
return IIO_VAL_INT;
}
static int tsl2563_write_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info, int val,
int val2)
{
struct tsl2563_chip *chip = iio_priv(indio_dev);
int ret;
mutex_lock(&chip->lock);
if (dir == IIO_EV_DIR_RISING)
ret = i2c_smbus_write_word_data(chip->client,
TSL2563_CMD | TSL2563_REG_HIGH, val);
else
ret = i2c_smbus_write_word_data(chip->client,
TSL2563_CMD | TSL2563_REG_LOW, val);
if (ret)
goto error_ret;
if (dir == IIO_EV_DIR_RISING)
chip->high_thres = val;
else
chip->low_thres = val;
error_ret:
mutex_unlock(&chip->lock);
return ret;
}
static irqreturn_t tsl2563_event_handler(int irq, void *private)
{
struct iio_dev *dev_info = private;
struct tsl2563_chip *chip = iio_priv(dev_info);
iio_push_event(dev_info,
IIO_UNMOD_EVENT_CODE(IIO_INTENSITY,
0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(dev_info));
/* clear the interrupt and push the event */
i2c_smbus_write_byte(chip->client, TSL2563_CMD | TSL2563_CLEARINT);
return IRQ_HANDLED;
}
static int tsl2563_write_interrupt_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct tsl2563_chip *chip = iio_priv(indio_dev);
int ret = 0;
mutex_lock(&chip->lock);
if (state && !(chip->intr & TSL2563_INT_MASK)) {
/* ensure the chip is actually on */
cancel_delayed_work_sync(&chip->poweroff_work);
if (!tsl2563_get_power(chip)) {
ret = tsl2563_set_power(chip, 1);
if (ret)
goto out;
ret = tsl2563_configure(chip);
if (ret)
goto out;
}
ret = tsl2563_configure_irq(chip, true);
}
if (!state && (chip->intr & TSL2563_INT_MASK)) {
ret = tsl2563_configure_irq(chip, false);
/* now the interrupt is not enabled, we can go to sleep */
schedule_delayed_work(&chip->poweroff_work, 5 * HZ);
}
out:
mutex_unlock(&chip->lock);
return ret;
}
static int tsl2563_read_interrupt_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir)
{
struct tsl2563_chip *chip = iio_priv(indio_dev);
int ret;
mutex_lock(&chip->lock);
ret = i2c_smbus_read_byte_data(chip->client,
TSL2563_CMD | TSL2563_REG_INT);
mutex_unlock(&chip->lock);
if (ret < 0)
return ret;
return !!(ret & TSL2563_INT_MASK);
}
static const struct iio_info tsl2563_info_no_irq = {
.read_raw = &tsl2563_read_raw,
.write_raw = &tsl2563_write_raw,
};
static const struct iio_info tsl2563_info = {
.read_raw = &tsl2563_read_raw,
.write_raw = &tsl2563_write_raw,
.read_event_value = &tsl2563_read_thresh,
.write_event_value = &tsl2563_write_thresh,
.read_event_config = &tsl2563_read_interrupt_config,
.write_event_config = &tsl2563_write_interrupt_config,
};
static int tsl2563_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct iio_dev *indio_dev;
struct tsl2563_chip *chip;
unsigned long irq_flags;
u8 id = 0;
int err;
indio_dev = devm_iio_device_alloc(dev, sizeof(*chip));
if (!indio_dev)
return -ENOMEM;
chip = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
chip->client = client;
err = tsl2563_detect(chip);
if (err)
return dev_err_probe(dev, err, "detect error\n");
err = tsl2563_read_id(chip, &id);
if (err)
return dev_err_probe(dev, err, "read id error\n");
mutex_init(&chip->lock);
/* Default values used until userspace says otherwise */
chip->low_thres = 0x0;
chip->high_thres = 0xffff;
chip->gainlevel = tsl2563_gainlevel_table;
chip->intr = TSL2563_INT_PERSIST(4);
chip->calib0 = tsl2563_calib_from_sysfs(CALIB_BASE_SYSFS);
chip->calib1 = tsl2563_calib_from_sysfs(CALIB_BASE_SYSFS);
chip->cover_comp_gain = 1;
device_property_read_u32(dev, "amstaos,cover-comp-gain", &chip->cover_comp_gain);
dev_info(dev, "model %d, rev. %d\n", id >> 4, id & 0x0f);
indio_dev->name = client->name;
indio_dev->channels = tsl2563_channels;
indio_dev->num_channels = ARRAY_SIZE(tsl2563_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
if (client->irq)
indio_dev->info = &tsl2563_info;
else
indio_dev->info = &tsl2563_info_no_irq;
if (client->irq) {
irq_flags = irq_get_trigger_type(client->irq);
if (irq_flags == IRQF_TRIGGER_NONE)
irq_flags = IRQF_TRIGGER_RISING;
irq_flags |= IRQF_ONESHOT;
err = devm_request_threaded_irq(dev, client->irq,
NULL,
&tsl2563_event_handler,
irq_flags,
"tsl2563_event",
indio_dev);
if (err)
return dev_err_probe(dev, err, "irq request error\n");
}
err = tsl2563_configure(chip);
if (err)
return dev_err_probe(dev, err, "configure error\n");
INIT_DELAYED_WORK(&chip->poweroff_work, tsl2563_poweroff_work);
/* The interrupt cannot yet be enabled so this is fine without lock */
schedule_delayed_work(&chip->poweroff_work, 5 * HZ);
err = iio_device_register(indio_dev);
if (err) {
dev_err_probe(dev, err, "iio registration error\n");
goto fail;
}
return 0;
fail:
cancel_delayed_work_sync(&chip->poweroff_work);
return err;
}
static void tsl2563_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct tsl2563_chip *chip = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
if (!chip->int_enabled)
cancel_delayed_work_sync(&chip->poweroff_work);
/* Ensure that interrupts are disabled - then flush any bottom halves */
tsl2563_configure_irq(chip, false);
tsl2563_set_power(chip, 0);
}
static int tsl2563_suspend(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct tsl2563_chip *chip = iio_priv(indio_dev);
int ret;
mutex_lock(&chip->lock);
ret = tsl2563_set_power(chip, 0);
if (ret)
goto out;
chip->suspended = true;
out:
mutex_unlock(&chip->lock);
return ret;
}
static int tsl2563_resume(struct device *dev)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct tsl2563_chip *chip = iio_priv(indio_dev);
int ret;
mutex_lock(&chip->lock);
ret = tsl2563_set_power(chip, 1);
if (ret)
goto out;
ret = tsl2563_configure(chip);
if (ret)
goto out;
chip->suspended = false;
out:
mutex_unlock(&chip->lock);
return ret;
}
static DEFINE_SIMPLE_DEV_PM_OPS(tsl2563_pm_ops, tsl2563_suspend,
tsl2563_resume);
static const struct i2c_device_id tsl2563_id[] = {
{ "tsl2560", 0 },
{ "tsl2561", 1 },
{ "tsl2562", 2 },
{ "tsl2563", 3 },
{}
};
MODULE_DEVICE_TABLE(i2c, tsl2563_id);
static const struct of_device_id tsl2563_of_match[] = {
{ .compatible = "amstaos,tsl2560" },
{ .compatible = "amstaos,tsl2561" },
{ .compatible = "amstaos,tsl2562" },
{ .compatible = "amstaos,tsl2563" },
{}
};
MODULE_DEVICE_TABLE(of, tsl2563_of_match);
static struct i2c_driver tsl2563_i2c_driver = {
.driver = {
.name = "tsl2563",
.of_match_table = tsl2563_of_match,
.pm = pm_sleep_ptr(&tsl2563_pm_ops),
},
.probe = tsl2563_probe,
.remove = tsl2563_remove,
.id_table = tsl2563_id,
};
module_i2c_driver(tsl2563_i2c_driver);
MODULE_AUTHOR("Nokia Corporation");
MODULE_DESCRIPTION("tsl2563 light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/tsl2563.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* si1145.c - Support for Silabs SI1132 and SI1141/2/3/5/6/7 combined ambient
* light, UV index and proximity sensors
*
* Copyright 2014-16 Peter Meerwald-Stadler <[email protected]>
* Copyright 2016 Crestez Dan Leonard <[email protected]>
*
* SI1132 (7-bit I2C slave address 0x60)
* SI1141/2/3 (7-bit I2C slave address 0x5a)
* SI1145/6/6 (7-bit I2C slave address 0x60)
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/buffer.h>
#include <linux/util_macros.h>
#define SI1145_REG_PART_ID 0x00
#define SI1145_REG_REV_ID 0x01
#define SI1145_REG_SEQ_ID 0x02
#define SI1145_REG_INT_CFG 0x03
#define SI1145_REG_IRQ_ENABLE 0x04
#define SI1145_REG_IRQ_MODE 0x05
#define SI1145_REG_HW_KEY 0x07
#define SI1145_REG_MEAS_RATE 0x08
#define SI1145_REG_PS_LED21 0x0f
#define SI1145_REG_PS_LED3 0x10
#define SI1145_REG_UCOEF1 0x13
#define SI1145_REG_UCOEF2 0x14
#define SI1145_REG_UCOEF3 0x15
#define SI1145_REG_UCOEF4 0x16
#define SI1145_REG_PARAM_WR 0x17
#define SI1145_REG_COMMAND 0x18
#define SI1145_REG_RESPONSE 0x20
#define SI1145_REG_IRQ_STATUS 0x21
#define SI1145_REG_ALSVIS_DATA 0x22
#define SI1145_REG_ALSIR_DATA 0x24
#define SI1145_REG_PS1_DATA 0x26
#define SI1145_REG_PS2_DATA 0x28
#define SI1145_REG_PS3_DATA 0x2a
#define SI1145_REG_AUX_DATA 0x2c
#define SI1145_REG_PARAM_RD 0x2e
#define SI1145_REG_CHIP_STAT 0x30
#define SI1145_UCOEF1_DEFAULT 0x7b
#define SI1145_UCOEF2_DEFAULT 0x6b
#define SI1145_UCOEF3_DEFAULT 0x01
#define SI1145_UCOEF4_DEFAULT 0x00
/* Helper to figure out PS_LED register / shift per channel */
#define SI1145_PS_LED_REG(ch) \
(((ch) == 2) ? SI1145_REG_PS_LED3 : SI1145_REG_PS_LED21)
#define SI1145_PS_LED_SHIFT(ch) \
(((ch) == 1) ? 4 : 0)
/* Parameter offsets */
#define SI1145_PARAM_CHLIST 0x01
#define SI1145_PARAM_PSLED12_SELECT 0x02
#define SI1145_PARAM_PSLED3_SELECT 0x03
#define SI1145_PARAM_PS_ENCODING 0x05
#define SI1145_PARAM_ALS_ENCODING 0x06
#define SI1145_PARAM_PS1_ADC_MUX 0x07
#define SI1145_PARAM_PS2_ADC_MUX 0x08
#define SI1145_PARAM_PS3_ADC_MUX 0x09
#define SI1145_PARAM_PS_ADC_COUNTER 0x0a
#define SI1145_PARAM_PS_ADC_GAIN 0x0b
#define SI1145_PARAM_PS_ADC_MISC 0x0c
#define SI1145_PARAM_ALS_ADC_MUX 0x0d
#define SI1145_PARAM_ALSIR_ADC_MUX 0x0e
#define SI1145_PARAM_AUX_ADC_MUX 0x0f
#define SI1145_PARAM_ALSVIS_ADC_COUNTER 0x10
#define SI1145_PARAM_ALSVIS_ADC_GAIN 0x11
#define SI1145_PARAM_ALSVIS_ADC_MISC 0x12
#define SI1145_PARAM_LED_RECOVERY 0x1c
#define SI1145_PARAM_ALSIR_ADC_COUNTER 0x1d
#define SI1145_PARAM_ALSIR_ADC_GAIN 0x1e
#define SI1145_PARAM_ALSIR_ADC_MISC 0x1f
#define SI1145_PARAM_ADC_OFFSET 0x1a
/* Channel enable masks for CHLIST parameter */
#define SI1145_CHLIST_EN_PS1 BIT(0)
#define SI1145_CHLIST_EN_PS2 BIT(1)
#define SI1145_CHLIST_EN_PS3 BIT(2)
#define SI1145_CHLIST_EN_ALSVIS BIT(4)
#define SI1145_CHLIST_EN_ALSIR BIT(5)
#define SI1145_CHLIST_EN_AUX BIT(6)
#define SI1145_CHLIST_EN_UV BIT(7)
/* Proximity measurement mode for ADC_MISC parameter */
#define SI1145_PS_ADC_MODE_NORMAL BIT(2)
/* Signal range mask for ADC_MISC parameter */
#define SI1145_ADC_MISC_RANGE BIT(5)
/* Commands for REG_COMMAND */
#define SI1145_CMD_NOP 0x00
#define SI1145_CMD_RESET 0x01
#define SI1145_CMD_PS_FORCE 0x05
#define SI1145_CMD_ALS_FORCE 0x06
#define SI1145_CMD_PSALS_FORCE 0x07
#define SI1145_CMD_PS_PAUSE 0x09
#define SI1145_CMD_ALS_PAUSE 0x0a
#define SI1145_CMD_PSALS_PAUSE 0x0b
#define SI1145_CMD_PS_AUTO 0x0d
#define SI1145_CMD_ALS_AUTO 0x0e
#define SI1145_CMD_PSALS_AUTO 0x0f
#define SI1145_CMD_PARAM_QUERY 0x80
#define SI1145_CMD_PARAM_SET 0xa0
#define SI1145_RSP_INVALID_SETTING 0x80
#define SI1145_RSP_COUNTER_MASK 0x0F
/* Minimum sleep after each command to ensure it's received */
#define SI1145_COMMAND_MINSLEEP_MS 5
/* Return -ETIMEDOUT after this long */
#define SI1145_COMMAND_TIMEOUT_MS 25
/* Interrupt configuration masks for INT_CFG register */
#define SI1145_INT_CFG_OE BIT(0) /* enable interrupt */
#define SI1145_INT_CFG_MODE BIT(1) /* auto reset interrupt pin */
/* Interrupt enable masks for IRQ_ENABLE register */
#define SI1145_MASK_ALL_IE (BIT(4) | BIT(3) | BIT(2) | BIT(0))
#define SI1145_MUX_TEMP 0x65
#define SI1145_MUX_VDD 0x75
/* Proximity LED current; see Table 2 in datasheet */
#define SI1145_LED_CURRENT_45mA 0x04
enum {
SI1132,
SI1141,
SI1142,
SI1143,
SI1145,
SI1146,
SI1147,
};
struct si1145_part_info {
u8 part;
const struct iio_info *iio_info;
const struct iio_chan_spec *channels;
unsigned int num_channels;
unsigned int num_leds;
bool uncompressed_meas_rate;
};
/**
* struct si1145_data - si1145 chip state data
* @client: I2C client
* @lock: mutex to protect shared state.
* @cmdlock: Low-level mutex to protect command execution only
* @rsp_seq: Next expected response number or -1 if counter reset required
* @scan_mask: Saved scan mask to avoid duplicate set_chlist
* @autonomous: If automatic measurements are active (for buffer support)
* @part_info: Part information
* @trig: Pointer to iio trigger
* @meas_rate: Value of MEAS_RATE register. Only set in HW in auto mode
* @buffer: Used to pack data read from sensor.
*/
struct si1145_data {
struct i2c_client *client;
struct mutex lock;
struct mutex cmdlock;
int rsp_seq;
const struct si1145_part_info *part_info;
unsigned long scan_mask;
bool autonomous;
struct iio_trigger *trig;
int meas_rate;
/*
* Ensure timestamp will be naturally aligned if present.
* Maximum buffer size (may be only partly used if not all
* channels are enabled):
* 6*2 bytes channels data + 4 bytes alignment +
* 8 bytes timestamp
*/
u8 buffer[24] __aligned(8);
};
/*
* __si1145_command_reset() - Send CMD_NOP and wait for response 0
*
* Does not modify data->rsp_seq
*
* Return: 0 on success and -errno on error.
*/
static int __si1145_command_reset(struct si1145_data *data)
{
struct device *dev = &data->client->dev;
unsigned long stop_jiffies;
int ret;
ret = i2c_smbus_write_byte_data(data->client, SI1145_REG_COMMAND,
SI1145_CMD_NOP);
if (ret < 0)
return ret;
msleep(SI1145_COMMAND_MINSLEEP_MS);
stop_jiffies = jiffies + SI1145_COMMAND_TIMEOUT_MS * HZ / 1000;
while (true) {
ret = i2c_smbus_read_byte_data(data->client,
SI1145_REG_RESPONSE);
if (ret <= 0)
return ret;
if (time_after(jiffies, stop_jiffies)) {
dev_warn(dev, "timeout on reset\n");
return -ETIMEDOUT;
}
msleep(SI1145_COMMAND_MINSLEEP_MS);
}
}
/*
* si1145_command() - Execute a command and poll the response register
*
* All conversion overflows are reported as -EOVERFLOW
* INVALID_SETTING is reported as -EINVAL
* Timeouts are reported as -ETIMEDOUT
*
* Return: 0 on success or -errno on failure
*/
static int si1145_command(struct si1145_data *data, u8 cmd)
{
struct device *dev = &data->client->dev;
unsigned long stop_jiffies;
int ret;
mutex_lock(&data->cmdlock);
if (data->rsp_seq < 0) {
ret = __si1145_command_reset(data);
if (ret < 0) {
dev_err(dev, "failed to reset command counter, ret=%d\n",
ret);
goto out;
}
data->rsp_seq = 0;
}
ret = i2c_smbus_write_byte_data(data->client, SI1145_REG_COMMAND, cmd);
if (ret) {
dev_warn(dev, "failed to write command, ret=%d\n", ret);
goto out;
}
/* Sleep a little to ensure the command is received */
msleep(SI1145_COMMAND_MINSLEEP_MS);
stop_jiffies = jiffies + SI1145_COMMAND_TIMEOUT_MS * HZ / 1000;
while (true) {
ret = i2c_smbus_read_byte_data(data->client,
SI1145_REG_RESPONSE);
if (ret < 0) {
dev_warn(dev, "failed to read response, ret=%d\n", ret);
break;
}
if ((ret & ~SI1145_RSP_COUNTER_MASK) == 0) {
if (ret == data->rsp_seq) {
if (time_after(jiffies, stop_jiffies)) {
dev_warn(dev, "timeout on command 0x%02x\n",
cmd);
ret = -ETIMEDOUT;
break;
}
msleep(SI1145_COMMAND_MINSLEEP_MS);
continue;
}
if (ret == ((data->rsp_seq + 1) &
SI1145_RSP_COUNTER_MASK)) {
data->rsp_seq = ret;
ret = 0;
break;
}
dev_warn(dev, "unexpected response counter %d instead of %d\n",
ret, (data->rsp_seq + 1) &
SI1145_RSP_COUNTER_MASK);
ret = -EIO;
} else {
if (ret == SI1145_RSP_INVALID_SETTING) {
dev_warn(dev, "INVALID_SETTING error on command 0x%02x\n",
cmd);
ret = -EINVAL;
} else {
/* All overflows are treated identically */
dev_dbg(dev, "overflow, ret=%d, cmd=0x%02x\n",
ret, cmd);
ret = -EOVERFLOW;
}
}
/* Force a counter reset next time */
data->rsp_seq = -1;
break;
}
out:
mutex_unlock(&data->cmdlock);
return ret;
}
static int si1145_param_update(struct si1145_data *data, u8 op, u8 param,
u8 value)
{
int ret;
ret = i2c_smbus_write_byte_data(data->client,
SI1145_REG_PARAM_WR, value);
if (ret < 0)
return ret;
return si1145_command(data, op | (param & 0x1F));
}
static int si1145_param_set(struct si1145_data *data, u8 param, u8 value)
{
return si1145_param_update(data, SI1145_CMD_PARAM_SET, param, value);
}
/* Set param. Returns negative errno or current value */
static int si1145_param_query(struct si1145_data *data, u8 param)
{
int ret;
ret = si1145_command(data, SI1145_CMD_PARAM_QUERY | (param & 0x1F));
if (ret < 0)
return ret;
return i2c_smbus_read_byte_data(data->client, SI1145_REG_PARAM_RD);
}
/* Expand 8 bit compressed value to 16 bit, see Silabs AN498 */
static u16 si1145_uncompress(u8 x)
{
u16 result = 0;
u8 exponent = 0;
if (x < 8)
return 0;
exponent = (x & 0xf0) >> 4;
result = 0x10 | (x & 0x0f);
if (exponent >= 4)
return result << (exponent - 4);
return result >> (4 - exponent);
}
/* Compress 16 bit value to 8 bit, see Silabs AN498 */
static u8 si1145_compress(u16 x)
{
u32 exponent = 0;
u32 significand = 0;
u32 tmp = x;
if (x == 0x0000)
return 0x00;
if (x == 0x0001)
return 0x08;
while (1) {
tmp >>= 1;
exponent += 1;
if (tmp == 1)
break;
}
if (exponent < 5) {
significand = x << (4 - exponent);
return (exponent << 4) | (significand & 0xF);
}
significand = x >> (exponent - 5);
if (significand & 1) {
significand += 2;
if (significand & 0x0040) {
exponent += 1;
significand >>= 1;
}
}
return (exponent << 4) | ((significand >> 1) & 0xF);
}
/* Write meas_rate in hardware */
static int si1145_set_meas_rate(struct si1145_data *data, int interval)
{
if (data->part_info->uncompressed_meas_rate)
return i2c_smbus_write_word_data(data->client,
SI1145_REG_MEAS_RATE, interval);
else
return i2c_smbus_write_byte_data(data->client,
SI1145_REG_MEAS_RATE, interval);
}
static int si1145_read_samp_freq(struct si1145_data *data, int *val, int *val2)
{
*val = 32000;
if (data->part_info->uncompressed_meas_rate)
*val2 = data->meas_rate;
else
*val2 = si1145_uncompress(data->meas_rate);
return IIO_VAL_FRACTIONAL;
}
/* Set the samp freq in driver private data */
static int si1145_store_samp_freq(struct si1145_data *data, int val)
{
int ret = 0;
int meas_rate;
if (val <= 0 || val > 32000)
return -ERANGE;
meas_rate = 32000 / val;
mutex_lock(&data->lock);
if (data->autonomous) {
ret = si1145_set_meas_rate(data, meas_rate);
if (ret)
goto out;
}
if (data->part_info->uncompressed_meas_rate)
data->meas_rate = meas_rate;
else
data->meas_rate = si1145_compress(meas_rate);
out:
mutex_unlock(&data->lock);
return ret;
}
static irqreturn_t si1145_trigger_handler(int irq, void *private)
{
struct iio_poll_func *pf = private;
struct iio_dev *indio_dev = pf->indio_dev;
struct si1145_data *data = iio_priv(indio_dev);
int i, j = 0;
int ret;
u8 irq_status = 0;
if (!data->autonomous) {
ret = si1145_command(data, SI1145_CMD_PSALS_FORCE);
if (ret < 0 && ret != -EOVERFLOW)
goto done;
} else {
irq_status = ret = i2c_smbus_read_byte_data(data->client,
SI1145_REG_IRQ_STATUS);
if (ret < 0)
goto done;
if (!(irq_status & SI1145_MASK_ALL_IE))
goto done;
}
for_each_set_bit(i, indio_dev->active_scan_mask,
indio_dev->masklength) {
int run = 1;
while (i + run < indio_dev->masklength) {
if (!test_bit(i + run, indio_dev->active_scan_mask))
break;
if (indio_dev->channels[i + run].address !=
indio_dev->channels[i].address + 2 * run)
break;
run++;
}
ret = i2c_smbus_read_i2c_block_data_or_emulated(
data->client, indio_dev->channels[i].address,
sizeof(u16) * run, &data->buffer[j]);
if (ret < 0)
goto done;
j += run * sizeof(u16);
i += run - 1;
}
if (data->autonomous) {
ret = i2c_smbus_write_byte_data(data->client,
SI1145_REG_IRQ_STATUS,
irq_status & SI1145_MASK_ALL_IE);
if (ret < 0)
goto done;
}
iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
iio_get_time_ns(indio_dev));
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int si1145_set_chlist(struct iio_dev *indio_dev, unsigned long scan_mask)
{
struct si1145_data *data = iio_priv(indio_dev);
u8 reg = 0, mux;
int ret;
int i;
/* channel list already set, no need to reprogram */
if (data->scan_mask == scan_mask)
return 0;
for_each_set_bit(i, &scan_mask, indio_dev->masklength) {
switch (indio_dev->channels[i].address) {
case SI1145_REG_ALSVIS_DATA:
reg |= SI1145_CHLIST_EN_ALSVIS;
break;
case SI1145_REG_ALSIR_DATA:
reg |= SI1145_CHLIST_EN_ALSIR;
break;
case SI1145_REG_PS1_DATA:
reg |= SI1145_CHLIST_EN_PS1;
break;
case SI1145_REG_PS2_DATA:
reg |= SI1145_CHLIST_EN_PS2;
break;
case SI1145_REG_PS3_DATA:
reg |= SI1145_CHLIST_EN_PS3;
break;
case SI1145_REG_AUX_DATA:
switch (indio_dev->channels[i].type) {
case IIO_UVINDEX:
reg |= SI1145_CHLIST_EN_UV;
break;
default:
reg |= SI1145_CHLIST_EN_AUX;
if (indio_dev->channels[i].type == IIO_TEMP)
mux = SI1145_MUX_TEMP;
else
mux = SI1145_MUX_VDD;
ret = si1145_param_set(data,
SI1145_PARAM_AUX_ADC_MUX, mux);
if (ret < 0)
return ret;
break;
}
}
}
data->scan_mask = scan_mask;
ret = si1145_param_set(data, SI1145_PARAM_CHLIST, reg);
return ret < 0 ? ret : 0;
}
static int si1145_measure(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan)
{
struct si1145_data *data = iio_priv(indio_dev);
u8 cmd;
int ret;
ret = si1145_set_chlist(indio_dev, BIT(chan->scan_index));
if (ret < 0)
return ret;
cmd = (chan->type == IIO_PROXIMITY) ? SI1145_CMD_PS_FORCE :
SI1145_CMD_ALS_FORCE;
ret = si1145_command(data, cmd);
if (ret < 0 && ret != -EOVERFLOW)
return ret;
return i2c_smbus_read_word_data(data->client, chan->address);
}
/*
* Conversion between iio scale and ADC_GAIN values
* These could be further adjusted but proximity/intensity are dimensionless
*/
static const int si1145_proximity_scale_available[] = {
128, 64, 32, 16, 8, 4};
static const int si1145_intensity_scale_available[] = {
128, 64, 32, 16, 8, 4, 2, 1};
static IIO_CONST_ATTR(in_proximity_scale_available,
"128 64 32 16 8 4");
static IIO_CONST_ATTR(in_intensity_scale_available,
"128 64 32 16 8 4 2 1");
static IIO_CONST_ATTR(in_intensity_ir_scale_available,
"128 64 32 16 8 4 2 1");
static int si1145_scale_from_adcgain(int regval)
{
return 128 >> regval;
}
static int si1145_proximity_adcgain_from_scale(int val, int val2)
{
val = find_closest_descending(val, si1145_proximity_scale_available,
ARRAY_SIZE(si1145_proximity_scale_available));
if (val < 0 || val > 5 || val2 != 0)
return -EINVAL;
return val;
}
static int si1145_intensity_adcgain_from_scale(int val, int val2)
{
val = find_closest_descending(val, si1145_intensity_scale_available,
ARRAY_SIZE(si1145_intensity_scale_available));
if (val < 0 || val > 7 || val2 != 0)
return -EINVAL;
return val;
}
static int si1145_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct si1145_data *data = iio_priv(indio_dev);
int ret;
u8 reg;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_INTENSITY:
case IIO_PROXIMITY:
case IIO_VOLTAGE:
case IIO_TEMP:
case IIO_UVINDEX:
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = si1145_measure(indio_dev, chan);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CURRENT:
ret = i2c_smbus_read_byte_data(data->client,
SI1145_PS_LED_REG(chan->channel));
if (ret < 0)
return ret;
*val = (ret >> SI1145_PS_LED_SHIFT(chan->channel))
& 0x0f;
return IIO_VAL_INT;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_PROXIMITY:
reg = SI1145_PARAM_PS_ADC_GAIN;
break;
case IIO_INTENSITY:
if (chan->channel2 == IIO_MOD_LIGHT_IR)
reg = SI1145_PARAM_ALSIR_ADC_GAIN;
else
reg = SI1145_PARAM_ALSVIS_ADC_GAIN;
break;
case IIO_TEMP:
*val = 28;
*val2 = 571429;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_UVINDEX:
*val = 0;
*val2 = 10000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
ret = si1145_param_query(data, reg);
if (ret < 0)
return ret;
*val = si1145_scale_from_adcgain(ret & 0x07);
return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET:
switch (chan->type) {
case IIO_TEMP:
/*
* -ADC offset - ADC counts @ 25°C -
* 35 * ADC counts / °C
*/
*val = -256 - 11136 + 25 * 35;
return IIO_VAL_INT;
default:
/*
* All ADC measurements have are by default offset
* by -256
* See AN498 5.6.3
*/
ret = si1145_param_query(data, SI1145_PARAM_ADC_OFFSET);
if (ret < 0)
return ret;
*val = -si1145_uncompress(ret);
return IIO_VAL_INT;
}
case IIO_CHAN_INFO_SAMP_FREQ:
return si1145_read_samp_freq(data, val, val2);
default:
return -EINVAL;
}
}
static int si1145_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct si1145_data *data = iio_priv(indio_dev);
u8 reg1, reg2, shift;
int ret;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_PROXIMITY:
val = si1145_proximity_adcgain_from_scale(val, val2);
if (val < 0)
return val;
reg1 = SI1145_PARAM_PS_ADC_GAIN;
reg2 = SI1145_PARAM_PS_ADC_COUNTER;
break;
case IIO_INTENSITY:
val = si1145_intensity_adcgain_from_scale(val, val2);
if (val < 0)
return val;
if (chan->channel2 == IIO_MOD_LIGHT_IR) {
reg1 = SI1145_PARAM_ALSIR_ADC_GAIN;
reg2 = SI1145_PARAM_ALSIR_ADC_COUNTER;
} else {
reg1 = SI1145_PARAM_ALSVIS_ADC_GAIN;
reg2 = SI1145_PARAM_ALSVIS_ADC_COUNTER;
}
break;
default:
return -EINVAL;
}
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = si1145_param_set(data, reg1, val);
if (ret < 0) {
iio_device_release_direct_mode(indio_dev);
return ret;
}
/* Set recovery period to one's complement of gain */
ret = si1145_param_set(data, reg2, (~val & 0x07) << 4);
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_RAW:
if (chan->type != IIO_CURRENT)
return -EINVAL;
if (val < 0 || val > 15 || val2 != 0)
return -EINVAL;
reg1 = SI1145_PS_LED_REG(chan->channel);
shift = SI1145_PS_LED_SHIFT(chan->channel);
ret = iio_device_claim_direct_mode(indio_dev);
if (ret)
return ret;
ret = i2c_smbus_read_byte_data(data->client, reg1);
if (ret < 0) {
iio_device_release_direct_mode(indio_dev);
return ret;
}
ret = i2c_smbus_write_byte_data(data->client, reg1,
(ret & ~(0x0f << shift)) |
((val & 0x0f) << shift));
iio_device_release_direct_mode(indio_dev);
return ret;
case IIO_CHAN_INFO_SAMP_FREQ:
return si1145_store_samp_freq(data, val);
default:
return -EINVAL;
}
}
#define SI1145_ST { \
.sign = 'u', \
.realbits = 16, \
.storagebits = 16, \
.endianness = IIO_LE, \
}
#define SI1145_INTENSITY_CHANNEL(_si) { \
.type = IIO_INTENSITY, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.scan_type = SI1145_ST, \
.scan_index = _si, \
.address = SI1145_REG_ALSVIS_DATA, \
}
#define SI1145_INTENSITY_IR_CHANNEL(_si) { \
.type = IIO_INTENSITY, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.modified = 1, \
.channel2 = IIO_MOD_LIGHT_IR, \
.scan_type = SI1145_ST, \
.scan_index = _si, \
.address = SI1145_REG_ALSIR_DATA, \
}
#define SI1145_TEMP_CHANNEL(_si) { \
.type = IIO_TEMP, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_OFFSET) | \
BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.scan_type = SI1145_ST, \
.scan_index = _si, \
.address = SI1145_REG_AUX_DATA, \
}
#define SI1145_UV_CHANNEL(_si) { \
.type = IIO_UVINDEX, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.scan_type = SI1145_ST, \
.scan_index = _si, \
.address = SI1145_REG_AUX_DATA, \
}
#define SI1145_PROXIMITY_CHANNEL(_si, _ch) { \
.type = IIO_PROXIMITY, \
.indexed = 1, \
.channel = _ch, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.scan_type = SI1145_ST, \
.scan_index = _si, \
.address = SI1145_REG_PS1_DATA + _ch * 2, \
}
#define SI1145_VOLTAGE_CHANNEL(_si) { \
.type = IIO_VOLTAGE, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.scan_type = SI1145_ST, \
.scan_index = _si, \
.address = SI1145_REG_AUX_DATA, \
}
#define SI1145_CURRENT_CHANNEL(_ch) { \
.type = IIO_CURRENT, \
.indexed = 1, \
.channel = _ch, \
.output = 1, \
.scan_index = -1, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
}
static const struct iio_chan_spec si1132_channels[] = {
SI1145_INTENSITY_CHANNEL(0),
SI1145_INTENSITY_IR_CHANNEL(1),
SI1145_TEMP_CHANNEL(2),
SI1145_VOLTAGE_CHANNEL(3),
SI1145_UV_CHANNEL(4),
IIO_CHAN_SOFT_TIMESTAMP(6),
};
static const struct iio_chan_spec si1141_channels[] = {
SI1145_INTENSITY_CHANNEL(0),
SI1145_INTENSITY_IR_CHANNEL(1),
SI1145_PROXIMITY_CHANNEL(2, 0),
SI1145_TEMP_CHANNEL(3),
SI1145_VOLTAGE_CHANNEL(4),
IIO_CHAN_SOFT_TIMESTAMP(5),
SI1145_CURRENT_CHANNEL(0),
};
static const struct iio_chan_spec si1142_channels[] = {
SI1145_INTENSITY_CHANNEL(0),
SI1145_INTENSITY_IR_CHANNEL(1),
SI1145_PROXIMITY_CHANNEL(2, 0),
SI1145_PROXIMITY_CHANNEL(3, 1),
SI1145_TEMP_CHANNEL(4),
SI1145_VOLTAGE_CHANNEL(5),
IIO_CHAN_SOFT_TIMESTAMP(6),
SI1145_CURRENT_CHANNEL(0),
SI1145_CURRENT_CHANNEL(1),
};
static const struct iio_chan_spec si1143_channels[] = {
SI1145_INTENSITY_CHANNEL(0),
SI1145_INTENSITY_IR_CHANNEL(1),
SI1145_PROXIMITY_CHANNEL(2, 0),
SI1145_PROXIMITY_CHANNEL(3, 1),
SI1145_PROXIMITY_CHANNEL(4, 2),
SI1145_TEMP_CHANNEL(5),
SI1145_VOLTAGE_CHANNEL(6),
IIO_CHAN_SOFT_TIMESTAMP(7),
SI1145_CURRENT_CHANNEL(0),
SI1145_CURRENT_CHANNEL(1),
SI1145_CURRENT_CHANNEL(2),
};
static const struct iio_chan_spec si1145_channels[] = {
SI1145_INTENSITY_CHANNEL(0),
SI1145_INTENSITY_IR_CHANNEL(1),
SI1145_PROXIMITY_CHANNEL(2, 0),
SI1145_TEMP_CHANNEL(3),
SI1145_VOLTAGE_CHANNEL(4),
SI1145_UV_CHANNEL(5),
IIO_CHAN_SOFT_TIMESTAMP(6),
SI1145_CURRENT_CHANNEL(0),
};
static const struct iio_chan_spec si1146_channels[] = {
SI1145_INTENSITY_CHANNEL(0),
SI1145_INTENSITY_IR_CHANNEL(1),
SI1145_TEMP_CHANNEL(2),
SI1145_VOLTAGE_CHANNEL(3),
SI1145_UV_CHANNEL(4),
SI1145_PROXIMITY_CHANNEL(5, 0),
SI1145_PROXIMITY_CHANNEL(6, 1),
IIO_CHAN_SOFT_TIMESTAMP(7),
SI1145_CURRENT_CHANNEL(0),
SI1145_CURRENT_CHANNEL(1),
};
static const struct iio_chan_spec si1147_channels[] = {
SI1145_INTENSITY_CHANNEL(0),
SI1145_INTENSITY_IR_CHANNEL(1),
SI1145_PROXIMITY_CHANNEL(2, 0),
SI1145_PROXIMITY_CHANNEL(3, 1),
SI1145_PROXIMITY_CHANNEL(4, 2),
SI1145_TEMP_CHANNEL(5),
SI1145_VOLTAGE_CHANNEL(6),
SI1145_UV_CHANNEL(7),
IIO_CHAN_SOFT_TIMESTAMP(8),
SI1145_CURRENT_CHANNEL(0),
SI1145_CURRENT_CHANNEL(1),
SI1145_CURRENT_CHANNEL(2),
};
static struct attribute *si1132_attributes[] = {
&iio_const_attr_in_intensity_scale_available.dev_attr.attr,
&iio_const_attr_in_intensity_ir_scale_available.dev_attr.attr,
NULL,
};
static struct attribute *si114x_attributes[] = {
&iio_const_attr_in_intensity_scale_available.dev_attr.attr,
&iio_const_attr_in_intensity_ir_scale_available.dev_attr.attr,
&iio_const_attr_in_proximity_scale_available.dev_attr.attr,
NULL,
};
static const struct attribute_group si1132_attribute_group = {
.attrs = si1132_attributes,
};
static const struct attribute_group si114x_attribute_group = {
.attrs = si114x_attributes,
};
static const struct iio_info si1132_info = {
.read_raw = si1145_read_raw,
.write_raw = si1145_write_raw,
.attrs = &si1132_attribute_group,
};
static const struct iio_info si114x_info = {
.read_raw = si1145_read_raw,
.write_raw = si1145_write_raw,
.attrs = &si114x_attribute_group,
};
#define SI1145_PART(id, iio_info, chans, leds, uncompressed_meas_rate) \
{id, iio_info, chans, ARRAY_SIZE(chans), leds, uncompressed_meas_rate}
static const struct si1145_part_info si1145_part_info[] = {
[SI1132] = SI1145_PART(0x32, &si1132_info, si1132_channels, 0, true),
[SI1141] = SI1145_PART(0x41, &si114x_info, si1141_channels, 1, false),
[SI1142] = SI1145_PART(0x42, &si114x_info, si1142_channels, 2, false),
[SI1143] = SI1145_PART(0x43, &si114x_info, si1143_channels, 3, false),
[SI1145] = SI1145_PART(0x45, &si114x_info, si1145_channels, 1, true),
[SI1146] = SI1145_PART(0x46, &si114x_info, si1146_channels, 2, true),
[SI1147] = SI1145_PART(0x47, &si114x_info, si1147_channels, 3, true),
};
static int si1145_initialize(struct si1145_data *data)
{
struct i2c_client *client = data->client;
int ret;
ret = i2c_smbus_write_byte_data(client, SI1145_REG_COMMAND,
SI1145_CMD_RESET);
if (ret < 0)
return ret;
msleep(SI1145_COMMAND_TIMEOUT_MS);
/* Hardware key, magic value */
ret = i2c_smbus_write_byte_data(client, SI1145_REG_HW_KEY, 0x17);
if (ret < 0)
return ret;
msleep(SI1145_COMMAND_TIMEOUT_MS);
/* Turn off autonomous mode */
ret = si1145_set_meas_rate(data, 0);
if (ret < 0)
return ret;
/* Initialize sampling freq to 10 Hz */
ret = si1145_store_samp_freq(data, 10);
if (ret < 0)
return ret;
/* Set LED currents to 45 mA; have 4 bits, see Table 2 in datasheet */
switch (data->part_info->num_leds) {
case 3:
ret = i2c_smbus_write_byte_data(client,
SI1145_REG_PS_LED3,
SI1145_LED_CURRENT_45mA);
if (ret < 0)
return ret;
fallthrough;
case 2:
ret = i2c_smbus_write_byte_data(client,
SI1145_REG_PS_LED21,
(SI1145_LED_CURRENT_45mA << 4) |
SI1145_LED_CURRENT_45mA);
break;
case 1:
ret = i2c_smbus_write_byte_data(client,
SI1145_REG_PS_LED21,
SI1145_LED_CURRENT_45mA);
break;
default:
ret = 0;
break;
}
if (ret < 0)
return ret;
/* Set normal proximity measurement mode */
ret = si1145_param_set(data, SI1145_PARAM_PS_ADC_MISC,
SI1145_PS_ADC_MODE_NORMAL);
if (ret < 0)
return ret;
ret = si1145_param_set(data, SI1145_PARAM_PS_ADC_GAIN, 0x01);
if (ret < 0)
return ret;
/* ADC_COUNTER should be one complement of ADC_GAIN */
ret = si1145_param_set(data, SI1145_PARAM_PS_ADC_COUNTER, 0x06 << 4);
if (ret < 0)
return ret;
/* Set ALS visible measurement mode */
ret = si1145_param_set(data, SI1145_PARAM_ALSVIS_ADC_MISC,
SI1145_ADC_MISC_RANGE);
if (ret < 0)
return ret;
ret = si1145_param_set(data, SI1145_PARAM_ALSVIS_ADC_GAIN, 0x03);
if (ret < 0)
return ret;
ret = si1145_param_set(data, SI1145_PARAM_ALSVIS_ADC_COUNTER,
0x04 << 4);
if (ret < 0)
return ret;
/* Set ALS IR measurement mode */
ret = si1145_param_set(data, SI1145_PARAM_ALSIR_ADC_MISC,
SI1145_ADC_MISC_RANGE);
if (ret < 0)
return ret;
ret = si1145_param_set(data, SI1145_PARAM_ALSIR_ADC_GAIN, 0x01);
if (ret < 0)
return ret;
ret = si1145_param_set(data, SI1145_PARAM_ALSIR_ADC_COUNTER,
0x06 << 4);
if (ret < 0)
return ret;
/*
* Initialize UCOEF to default values in datasheet
* These registers are normally zero on reset
*/
if (data->part_info == &si1145_part_info[SI1132] ||
data->part_info == &si1145_part_info[SI1145] ||
data->part_info == &si1145_part_info[SI1146] ||
data->part_info == &si1145_part_info[SI1147]) {
ret = i2c_smbus_write_byte_data(data->client,
SI1145_REG_UCOEF1,
SI1145_UCOEF1_DEFAULT);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client,
SI1145_REG_UCOEF2, SI1145_UCOEF2_DEFAULT);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client,
SI1145_REG_UCOEF3, SI1145_UCOEF3_DEFAULT);
if (ret < 0)
return ret;
ret = i2c_smbus_write_byte_data(data->client,
SI1145_REG_UCOEF4, SI1145_UCOEF4_DEFAULT);
if (ret < 0)
return ret;
}
return 0;
}
/*
* Program the channels we want to measure with CMD_PSALS_AUTO. No need for
* _postdisable as we stop with CMD_PSALS_PAUSE; single measurement (direct)
* mode reprograms the channels list anyway...
*/
static int si1145_buffer_preenable(struct iio_dev *indio_dev)
{
struct si1145_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->lock);
ret = si1145_set_chlist(indio_dev, *indio_dev->active_scan_mask);
mutex_unlock(&data->lock);
return ret;
}
static bool si1145_validate_scan_mask(struct iio_dev *indio_dev,
const unsigned long *scan_mask)
{
struct si1145_data *data = iio_priv(indio_dev);
unsigned int count = 0;
int i;
/* Check that at most one AUX channel is enabled */
for_each_set_bit(i, scan_mask, data->part_info->num_channels) {
if (indio_dev->channels[i].address == SI1145_REG_AUX_DATA)
count++;
}
return count <= 1;
}
static const struct iio_buffer_setup_ops si1145_buffer_setup_ops = {
.preenable = si1145_buffer_preenable,
.validate_scan_mask = si1145_validate_scan_mask,
};
/*
* si1145_trigger_set_state() - Set trigger state
*
* When not using triggers interrupts are disabled and measurement rate is
* set to zero in order to minimize power consumption.
*/
static int si1145_trigger_set_state(struct iio_trigger *trig, bool state)
{
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
struct si1145_data *data = iio_priv(indio_dev);
int err = 0, ret;
mutex_lock(&data->lock);
if (state) {
data->autonomous = true;
err = i2c_smbus_write_byte_data(data->client,
SI1145_REG_INT_CFG, SI1145_INT_CFG_OE);
if (err < 0)
goto disable;
err = i2c_smbus_write_byte_data(data->client,
SI1145_REG_IRQ_ENABLE, SI1145_MASK_ALL_IE);
if (err < 0)
goto disable;
err = si1145_set_meas_rate(data, data->meas_rate);
if (err < 0)
goto disable;
err = si1145_command(data, SI1145_CMD_PSALS_AUTO);
if (err < 0)
goto disable;
} else {
disable:
/* Disable as much as possible skipping errors */
ret = si1145_command(data, SI1145_CMD_PSALS_PAUSE);
if (ret < 0 && !err)
err = ret;
ret = si1145_set_meas_rate(data, 0);
if (ret < 0 && !err)
err = ret;
ret = i2c_smbus_write_byte_data(data->client,
SI1145_REG_IRQ_ENABLE, 0);
if (ret < 0 && !err)
err = ret;
ret = i2c_smbus_write_byte_data(data->client,
SI1145_REG_INT_CFG, 0);
if (ret < 0 && !err)
err = ret;
data->autonomous = false;
}
mutex_unlock(&data->lock);
return err;
}
static const struct iio_trigger_ops si1145_trigger_ops = {
.set_trigger_state = si1145_trigger_set_state,
};
static int si1145_probe_trigger(struct iio_dev *indio_dev)
{
struct si1145_data *data = iio_priv(indio_dev);
struct i2c_client *client = data->client;
struct iio_trigger *trig;
int ret;
trig = devm_iio_trigger_alloc(&client->dev,
"%s-dev%d", indio_dev->name, iio_device_id(indio_dev));
if (!trig)
return -ENOMEM;
trig->ops = &si1145_trigger_ops;
iio_trigger_set_drvdata(trig, indio_dev);
ret = devm_request_irq(&client->dev, client->irq,
iio_trigger_generic_data_rdy_poll,
IRQF_TRIGGER_FALLING,
"si1145_irq",
trig);
if (ret < 0) {
dev_err(&client->dev, "irq request failed\n");
return ret;
}
ret = devm_iio_trigger_register(&client->dev, trig);
if (ret)
return ret;
data->trig = trig;
indio_dev->trig = iio_trigger_get(data->trig);
return 0;
}
static int si1145_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct si1145_data *data;
struct iio_dev *indio_dev;
u8 part_id, rev_id, seq_id;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->part_info = &si1145_part_info[id->driver_data];
part_id = ret = i2c_smbus_read_byte_data(data->client,
SI1145_REG_PART_ID);
if (ret < 0)
return ret;
rev_id = ret = i2c_smbus_read_byte_data(data->client,
SI1145_REG_REV_ID);
if (ret < 0)
return ret;
seq_id = ret = i2c_smbus_read_byte_data(data->client,
SI1145_REG_SEQ_ID);
if (ret < 0)
return ret;
dev_info(&client->dev, "device ID part 0x%02x rev 0x%02x seq 0x%02x\n",
part_id, rev_id, seq_id);
if (part_id != data->part_info->part) {
dev_err(&client->dev, "part ID mismatch got 0x%02x, expected 0x%02x\n",
part_id, data->part_info->part);
return -ENODEV;
}
indio_dev->name = id->name;
indio_dev->channels = data->part_info->channels;
indio_dev->num_channels = data->part_info->num_channels;
indio_dev->info = data->part_info->iio_info;
indio_dev->modes = INDIO_DIRECT_MODE;
mutex_init(&data->lock);
mutex_init(&data->cmdlock);
ret = si1145_initialize(data);
if (ret < 0)
return ret;
ret = devm_iio_triggered_buffer_setup(&client->dev,
indio_dev, NULL,
si1145_trigger_handler, &si1145_buffer_setup_ops);
if (ret < 0)
return ret;
if (client->irq) {
ret = si1145_probe_trigger(indio_dev);
if (ret < 0)
return ret;
} else {
dev_info(&client->dev, "no irq, using polling\n");
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id si1145_ids[] = {
{ "si1132", SI1132 },
{ "si1141", SI1141 },
{ "si1142", SI1142 },
{ "si1143", SI1143 },
{ "si1145", SI1145 },
{ "si1146", SI1146 },
{ "si1147", SI1147 },
{ }
};
MODULE_DEVICE_TABLE(i2c, si1145_ids);
static struct i2c_driver si1145_driver = {
.driver = {
.name = "si1145",
},
.probe = si1145_probe,
.id_table = si1145_ids,
};
module_i2c_driver(si1145_driver);
MODULE_AUTHOR("Peter Meerwald-Stadler <[email protected]>");
MODULE_DESCRIPTION("Silabs SI1132 and SI1141/2/3/5/6/7 proximity, ambient light and UV index sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/si1145.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* adux1020.c - Support for Analog Devices ADUX1020 photometric sensor
*
* Copyright (C) 2019 Linaro Ltd.
* Author: Manivannan Sadhasivam <[email protected]>
*
* TODO: Triggered buffer support
*/
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
#define ADUX1020_REGMAP_NAME "adux1020_regmap"
#define ADUX1020_DRV_NAME "adux1020"
/* System registers */
#define ADUX1020_REG_CHIP_ID 0x08
#define ADUX1020_REG_SLAVE_ADDRESS 0x09
#define ADUX1020_REG_SW_RESET 0x0f
#define ADUX1020_REG_INT_ENABLE 0x1c
#define ADUX1020_REG_INT_POLARITY 0x1d
#define ADUX1020_REG_PROX_TH_ON1 0x2a
#define ADUX1020_REG_PROX_TH_OFF1 0x2b
#define ADUX1020_REG_PROX_TYPE 0x2f
#define ADUX1020_REG_TEST_MODES_3 0x32
#define ADUX1020_REG_FORCE_MODE 0x33
#define ADUX1020_REG_FREQUENCY 0x40
#define ADUX1020_REG_LED_CURRENT 0x41
#define ADUX1020_REG_OP_MODE 0x45
#define ADUX1020_REG_INT_MASK 0x48
#define ADUX1020_REG_INT_STATUS 0x49
#define ADUX1020_REG_DATA_BUFFER 0x60
/* Chip ID bits */
#define ADUX1020_CHIP_ID_MASK GENMASK(11, 0)
#define ADUX1020_CHIP_ID 0x03fc
#define ADUX1020_SW_RESET BIT(1)
#define ADUX1020_FIFO_FLUSH BIT(15)
#define ADUX1020_OP_MODE_MASK GENMASK(3, 0)
#define ADUX1020_DATA_OUT_MODE_MASK GENMASK(7, 4)
#define ADUX1020_DATA_OUT_PROX_I FIELD_PREP(ADUX1020_DATA_OUT_MODE_MASK, 1)
#define ADUX1020_MODE_INT_MASK GENMASK(7, 0)
#define ADUX1020_INT_ENABLE 0x2094
#define ADUX1020_INT_DISABLE 0x2090
#define ADUX1020_PROX_INT_ENABLE 0x00f0
#define ADUX1020_PROX_ON1_INT BIT(0)
#define ADUX1020_PROX_OFF1_INT BIT(1)
#define ADUX1020_FIFO_INT_ENABLE 0x7f
#define ADUX1020_MODE_INT_DISABLE 0xff
#define ADUX1020_MODE_INT_STATUS_MASK GENMASK(7, 0)
#define ADUX1020_FIFO_STATUS_MASK GENMASK(15, 8)
#define ADUX1020_INT_CLEAR 0xff
#define ADUX1020_PROX_TYPE BIT(15)
#define ADUX1020_INT_PROX_ON1 BIT(0)
#define ADUX1020_INT_PROX_OFF1 BIT(1)
#define ADUX1020_FORCE_CLOCK_ON 0x0f4f
#define ADUX1020_FORCE_CLOCK_RESET 0x0040
#define ADUX1020_ACTIVE_4_STATE 0x0008
#define ADUX1020_PROX_FREQ_MASK GENMASK(7, 4)
#define ADUX1020_PROX_FREQ(x) FIELD_PREP(ADUX1020_PROX_FREQ_MASK, x)
#define ADUX1020_LED_CURRENT_MASK GENMASK(3, 0)
#define ADUX1020_LED_PIREF_EN BIT(12)
/* Operating modes */
enum adux1020_op_modes {
ADUX1020_MODE_STANDBY,
ADUX1020_MODE_PROX_I,
ADUX1020_MODE_PROX_XY,
ADUX1020_MODE_GEST,
ADUX1020_MODE_SAMPLE,
ADUX1020_MODE_FORCE = 0x0e,
ADUX1020_MODE_IDLE = 0x0f,
};
struct adux1020_data {
struct i2c_client *client;
struct iio_dev *indio_dev;
struct mutex lock;
struct regmap *regmap;
};
struct adux1020_mode_data {
u8 bytes;
u8 buf_len;
u16 int_en;
};
static const struct adux1020_mode_data adux1020_modes[] = {
[ADUX1020_MODE_PROX_I] = {
.bytes = 2,
.buf_len = 1,
.int_en = ADUX1020_PROX_INT_ENABLE,
},
};
static const struct regmap_config adux1020_regmap_config = {
.name = ADUX1020_REGMAP_NAME,
.reg_bits = 8,
.val_bits = 16,
.max_register = 0x6F,
.cache_type = REGCACHE_NONE,
};
static const struct reg_sequence adux1020_def_conf[] = {
{ 0x000c, 0x000f },
{ 0x0010, 0x1010 },
{ 0x0011, 0x004c },
{ 0x0012, 0x5f0c },
{ 0x0013, 0xada5 },
{ 0x0014, 0x0080 },
{ 0x0015, 0x0000 },
{ 0x0016, 0x0600 },
{ 0x0017, 0x0000 },
{ 0x0018, 0x2693 },
{ 0x0019, 0x0004 },
{ 0x001a, 0x4280 },
{ 0x001b, 0x0060 },
{ 0x001c, 0x2094 },
{ 0x001d, 0x0020 },
{ 0x001e, 0x0001 },
{ 0x001f, 0x0100 },
{ 0x0020, 0x0320 },
{ 0x0021, 0x0A13 },
{ 0x0022, 0x0320 },
{ 0x0023, 0x0113 },
{ 0x0024, 0x0000 },
{ 0x0025, 0x2412 },
{ 0x0026, 0x2412 },
{ 0x0027, 0x0022 },
{ 0x0028, 0x0000 },
{ 0x0029, 0x0300 },
{ 0x002a, 0x0700 },
{ 0x002b, 0x0600 },
{ 0x002c, 0x6000 },
{ 0x002d, 0x4000 },
{ 0x002e, 0x0000 },
{ 0x002f, 0x0000 },
{ 0x0030, 0x0000 },
{ 0x0031, 0x0000 },
{ 0x0032, 0x0040 },
{ 0x0033, 0x0008 },
{ 0x0034, 0xE400 },
{ 0x0038, 0x8080 },
{ 0x0039, 0x8080 },
{ 0x003a, 0x2000 },
{ 0x003b, 0x1f00 },
{ 0x003c, 0x2000 },
{ 0x003d, 0x2000 },
{ 0x003e, 0x0000 },
{ 0x0040, 0x8069 },
{ 0x0041, 0x1f2f },
{ 0x0042, 0x4000 },
{ 0x0043, 0x0000 },
{ 0x0044, 0x0008 },
{ 0x0046, 0x0000 },
{ 0x0048, 0x00ef },
{ 0x0049, 0x0000 },
{ 0x0045, 0x0000 },
};
static const int adux1020_rates[][2] = {
{ 0, 100000 },
{ 0, 200000 },
{ 0, 500000 },
{ 1, 0 },
{ 2, 0 },
{ 5, 0 },
{ 10, 0 },
{ 20, 0 },
{ 50, 0 },
{ 100, 0 },
{ 190, 0 },
{ 450, 0 },
{ 820, 0 },
{ 1400, 0 },
};
static const int adux1020_led_currents[][2] = {
{ 0, 25000 },
{ 0, 40000 },
{ 0, 55000 },
{ 0, 70000 },
{ 0, 85000 },
{ 0, 100000 },
{ 0, 115000 },
{ 0, 130000 },
{ 0, 145000 },
{ 0, 160000 },
{ 0, 175000 },
{ 0, 190000 },
{ 0, 205000 },
{ 0, 220000 },
{ 0, 235000 },
{ 0, 250000 },
};
static int adux1020_flush_fifo(struct adux1020_data *data)
{
int ret;
/* Force Idle mode */
ret = regmap_write(data->regmap, ADUX1020_REG_FORCE_MODE,
ADUX1020_ACTIVE_4_STATE);
if (ret < 0)
return ret;
ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
ADUX1020_OP_MODE_MASK, ADUX1020_MODE_FORCE);
if (ret < 0)
return ret;
ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
ADUX1020_OP_MODE_MASK, ADUX1020_MODE_IDLE);
if (ret < 0)
return ret;
/* Flush FIFO */
ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
ADUX1020_FORCE_CLOCK_ON);
if (ret < 0)
return ret;
ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
ADUX1020_FIFO_FLUSH);
if (ret < 0)
return ret;
return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
ADUX1020_FORCE_CLOCK_RESET);
}
static int adux1020_read_fifo(struct adux1020_data *data, u16 *buf, u8 buf_len)
{
unsigned int regval;
int i, ret;
/* Enable 32MHz clock */
ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
ADUX1020_FORCE_CLOCK_ON);
if (ret < 0)
return ret;
for (i = 0; i < buf_len; i++) {
ret = regmap_read(data->regmap, ADUX1020_REG_DATA_BUFFER,
®val);
if (ret < 0)
return ret;
buf[i] = regval;
}
/* Set 32MHz clock to be controlled by internal state machine */
return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
ADUX1020_FORCE_CLOCK_RESET);
}
static int adux1020_set_mode(struct adux1020_data *data,
enum adux1020_op_modes mode)
{
int ret;
/* Switch to standby mode before changing the mode */
ret = regmap_write(data->regmap, ADUX1020_REG_OP_MODE,
ADUX1020_MODE_STANDBY);
if (ret < 0)
return ret;
/* Set data out and switch to the desired mode */
switch (mode) {
case ADUX1020_MODE_PROX_I:
ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
ADUX1020_DATA_OUT_MODE_MASK,
ADUX1020_DATA_OUT_PROX_I);
if (ret < 0)
return ret;
ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
ADUX1020_OP_MODE_MASK,
ADUX1020_MODE_PROX_I);
if (ret < 0)
return ret;
break;
default:
return -EINVAL;
}
return 0;
}
static int adux1020_measure(struct adux1020_data *data,
enum adux1020_op_modes mode,
u16 *val)
{
unsigned int status;
int ret, tries = 50;
/* Disable INT pin as polling is going to be used */
ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
ADUX1020_INT_DISABLE);
if (ret < 0)
return ret;
/* Enable mode interrupt */
ret = regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
ADUX1020_MODE_INT_MASK,
adux1020_modes[mode].int_en);
if (ret < 0)
return ret;
while (tries--) {
ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS,
&status);
if (ret < 0)
return ret;
status &= ADUX1020_FIFO_STATUS_MASK;
if (status >= adux1020_modes[mode].bytes)
break;
msleep(20);
}
if (tries < 0)
return -EIO;
ret = adux1020_read_fifo(data, val, adux1020_modes[mode].buf_len);
if (ret < 0)
return ret;
/* Clear mode interrupt */
ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
(~adux1020_modes[mode].int_en));
if (ret < 0)
return ret;
/* Disable mode interrupts */
return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
ADUX1020_MODE_INT_MASK,
ADUX1020_MODE_INT_DISABLE);
}
static int adux1020_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct adux1020_data *data = iio_priv(indio_dev);
u16 buf[3];
int ret = -EINVAL;
unsigned int regval;
mutex_lock(&data->lock);
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_PROXIMITY:
ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
if (ret < 0)
goto fail;
ret = adux1020_measure(data, ADUX1020_MODE_PROX_I, buf);
if (ret < 0)
goto fail;
*val = buf[0];
ret = IIO_VAL_INT;
break;
default:
break;
}
break;
case IIO_CHAN_INFO_PROCESSED:
switch (chan->type) {
case IIO_CURRENT:
ret = regmap_read(data->regmap,
ADUX1020_REG_LED_CURRENT, ®val);
if (ret < 0)
goto fail;
regval = regval & ADUX1020_LED_CURRENT_MASK;
*val = adux1020_led_currents[regval][0];
*val2 = adux1020_led_currents[regval][1];
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
break;
}
break;
case IIO_CHAN_INFO_SAMP_FREQ:
switch (chan->type) {
case IIO_PROXIMITY:
ret = regmap_read(data->regmap, ADUX1020_REG_FREQUENCY,
®val);
if (ret < 0)
goto fail;
regval = FIELD_GET(ADUX1020_PROX_FREQ_MASK, regval);
*val = adux1020_rates[regval][0];
*val2 = adux1020_rates[regval][1];
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
break;
}
break;
default:
break;
}
fail:
mutex_unlock(&data->lock);
return ret;
};
static inline int adux1020_find_index(const int array[][2], int count, int val,
int val2)
{
int i;
for (i = 0; i < count; i++)
if (val == array[i][0] && val2 == array[i][1])
return i;
return -EINVAL;
}
static int adux1020_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct adux1020_data *data = iio_priv(indio_dev);
int i, ret = -EINVAL;
mutex_lock(&data->lock);
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
if (chan->type == IIO_PROXIMITY) {
i = adux1020_find_index(adux1020_rates,
ARRAY_SIZE(adux1020_rates),
val, val2);
if (i < 0) {
ret = i;
goto fail;
}
ret = regmap_update_bits(data->regmap,
ADUX1020_REG_FREQUENCY,
ADUX1020_PROX_FREQ_MASK,
ADUX1020_PROX_FREQ(i));
}
break;
case IIO_CHAN_INFO_PROCESSED:
if (chan->type == IIO_CURRENT) {
i = adux1020_find_index(adux1020_led_currents,
ARRAY_SIZE(adux1020_led_currents),
val, val2);
if (i < 0) {
ret = i;
goto fail;
}
ret = regmap_update_bits(data->regmap,
ADUX1020_REG_LED_CURRENT,
ADUX1020_LED_CURRENT_MASK, i);
}
break;
default:
break;
}
fail:
mutex_unlock(&data->lock);
return ret;
}
static int adux1020_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct adux1020_data *data = iio_priv(indio_dev);
int ret, mask;
mutex_lock(&data->lock);
ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
ADUX1020_INT_ENABLE);
if (ret < 0)
goto fail;
ret = regmap_write(data->regmap, ADUX1020_REG_INT_POLARITY, 0);
if (ret < 0)
goto fail;
switch (chan->type) {
case IIO_PROXIMITY:
if (dir == IIO_EV_DIR_RISING)
mask = ADUX1020_PROX_ON1_INT;
else
mask = ADUX1020_PROX_OFF1_INT;
if (state)
state = 0;
else
state = mask;
ret = regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
mask, state);
if (ret < 0)
goto fail;
/*
* Trigger proximity interrupt when the intensity is above
* or below threshold
*/
ret = regmap_update_bits(data->regmap, ADUX1020_REG_PROX_TYPE,
ADUX1020_PROX_TYPE,
ADUX1020_PROX_TYPE);
if (ret < 0)
goto fail;
/* Set proximity mode */
ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
break;
default:
ret = -EINVAL;
break;
}
fail:
mutex_unlock(&data->lock);
return ret;
}
static int adux1020_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct adux1020_data *data = iio_priv(indio_dev);
int ret, mask;
unsigned int regval;
switch (chan->type) {
case IIO_PROXIMITY:
if (dir == IIO_EV_DIR_RISING)
mask = ADUX1020_PROX_ON1_INT;
else
mask = ADUX1020_PROX_OFF1_INT;
break;
default:
return -EINVAL;
}
ret = regmap_read(data->regmap, ADUX1020_REG_INT_MASK, ®val);
if (ret < 0)
return ret;
return !(regval & mask);
}
static int adux1020_read_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int *val, int *val2)
{
struct adux1020_data *data = iio_priv(indio_dev);
u8 reg;
int ret;
unsigned int regval;
switch (chan->type) {
case IIO_PROXIMITY:
if (dir == IIO_EV_DIR_RISING)
reg = ADUX1020_REG_PROX_TH_ON1;
else
reg = ADUX1020_REG_PROX_TH_OFF1;
break;
default:
return -EINVAL;
}
ret = regmap_read(data->regmap, reg, ®val);
if (ret < 0)
return ret;
*val = regval;
return IIO_VAL_INT;
}
static int adux1020_write_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info, int val, int val2)
{
struct adux1020_data *data = iio_priv(indio_dev);
u8 reg;
switch (chan->type) {
case IIO_PROXIMITY:
if (dir == IIO_EV_DIR_RISING)
reg = ADUX1020_REG_PROX_TH_ON1;
else
reg = ADUX1020_REG_PROX_TH_OFF1;
break;
default:
return -EINVAL;
}
/* Full scale threshold value is 0-65535 */
if (val < 0 || val > 65535)
return -EINVAL;
return regmap_write(data->regmap, reg, val);
}
static const struct iio_event_spec adux1020_proximity_event[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec adux1020_channels[] = {
{
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
.event_spec = adux1020_proximity_event,
.num_event_specs = ARRAY_SIZE(adux1020_proximity_event),
},
{
.type = IIO_CURRENT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
.extend_name = "led",
.output = 1,
},
};
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
"0.1 0.2 0.5 1 2 5 10 20 50 100 190 450 820 1400");
static struct attribute *adux1020_attributes[] = {
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL
};
static const struct attribute_group adux1020_attribute_group = {
.attrs = adux1020_attributes,
};
static const struct iio_info adux1020_info = {
.attrs = &adux1020_attribute_group,
.read_raw = adux1020_read_raw,
.write_raw = adux1020_write_raw,
.read_event_config = adux1020_read_event_config,
.write_event_config = adux1020_write_event_config,
.read_event_value = adux1020_read_thresh,
.write_event_value = adux1020_write_thresh,
};
static irqreturn_t adux1020_interrupt_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct adux1020_data *data = iio_priv(indio_dev);
int ret, status;
ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS, &status);
if (ret < 0)
return IRQ_HANDLED;
status &= ADUX1020_MODE_INT_STATUS_MASK;
if (status & ADUX1020_INT_PROX_ON1) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
iio_get_time_ns(indio_dev));
}
if (status & ADUX1020_INT_PROX_OFF1) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
iio_get_time_ns(indio_dev));
}
regmap_update_bits(data->regmap, ADUX1020_REG_INT_STATUS,
ADUX1020_MODE_INT_MASK, ADUX1020_INT_CLEAR);
return IRQ_HANDLED;
}
static int adux1020_chip_init(struct adux1020_data *data)
{
struct i2c_client *client = data->client;
int ret;
unsigned int val;
ret = regmap_read(data->regmap, ADUX1020_REG_CHIP_ID, &val);
if (ret < 0)
return ret;
if ((val & ADUX1020_CHIP_ID_MASK) != ADUX1020_CHIP_ID) {
dev_err(&client->dev, "invalid chip id 0x%04x\n", val);
return -ENODEV;
}
dev_dbg(&client->dev, "Detected ADUX1020 with chip id: 0x%04x\n", val);
ret = regmap_update_bits(data->regmap, ADUX1020_REG_SW_RESET,
ADUX1020_SW_RESET, ADUX1020_SW_RESET);
if (ret < 0)
return ret;
/* Load default configuration */
ret = regmap_multi_reg_write(data->regmap, adux1020_def_conf,
ARRAY_SIZE(adux1020_def_conf));
if (ret < 0)
return ret;
ret = adux1020_flush_fifo(data);
if (ret < 0)
return ret;
/* Use LED_IREF for proximity mode */
ret = regmap_update_bits(data->regmap, ADUX1020_REG_LED_CURRENT,
ADUX1020_LED_PIREF_EN, 0);
if (ret < 0)
return ret;
/* Mask all interrupts */
return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
ADUX1020_MODE_INT_MASK, ADUX1020_MODE_INT_DISABLE);
}
static int adux1020_probe(struct i2c_client *client)
{
struct adux1020_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
indio_dev->info = &adux1020_info;
indio_dev->name = ADUX1020_DRV_NAME;
indio_dev->channels = adux1020_channels;
indio_dev->num_channels = ARRAY_SIZE(adux1020_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
data = iio_priv(indio_dev);
data->regmap = devm_regmap_init_i2c(client, &adux1020_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(&client->dev, "regmap initialization failed.\n");
return PTR_ERR(data->regmap);
}
data->client = client;
data->indio_dev = indio_dev;
mutex_init(&data->lock);
ret = adux1020_chip_init(data);
if (ret)
return ret;
if (client->irq) {
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, adux1020_interrupt_handler,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
ADUX1020_DRV_NAME, indio_dev);
if (ret) {
dev_err(&client->dev, "irq request error %d\n", -ret);
return ret;
}
}
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id adux1020_id[] = {
{ "adux1020", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, adux1020_id);
static const struct of_device_id adux1020_of_match[] = {
{ .compatible = "adi,adux1020" },
{ }
};
MODULE_DEVICE_TABLE(of, adux1020_of_match);
static struct i2c_driver adux1020_driver = {
.driver = {
.name = ADUX1020_DRV_NAME,
.of_match_table = adux1020_of_match,
},
.probe = adux1020_probe,
.id_table = adux1020_id,
};
module_i2c_driver(adux1020_driver);
MODULE_AUTHOR("Manivannan Sadhasivam <[email protected]>");
MODULE_DESCRIPTION("ADUX1020 photometric sensor");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/adux1020.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* apds9300.c - IIO driver for Avago APDS9300 ambient light sensor
*
* Copyright 2013 Oleksandr Kravchenko <[email protected]>
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/interrupt.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/events.h>
#define APDS9300_DRV_NAME "apds9300"
#define APDS9300_IRQ_NAME "apds9300_event"
/* Command register bits */
#define APDS9300_CMD BIT(7) /* Select command register. Must write as 1 */
#define APDS9300_WORD BIT(5) /* I2C write/read: if 1 word, if 0 byte */
#define APDS9300_CLEAR BIT(6) /* Interrupt clear. Clears pending interrupt */
/* Register set */
#define APDS9300_CONTROL 0x00 /* Control of basic functions */
#define APDS9300_THRESHLOWLOW 0x02 /* Low byte of low interrupt threshold */
#define APDS9300_THRESHHIGHLOW 0x04 /* Low byte of high interrupt threshold */
#define APDS9300_INTERRUPT 0x06 /* Interrupt control */
#define APDS9300_DATA0LOW 0x0c /* Low byte of ADC channel 0 */
#define APDS9300_DATA1LOW 0x0e /* Low byte of ADC channel 1 */
/* Power on/off value for APDS9300_CONTROL register */
#define APDS9300_POWER_ON 0x03
#define APDS9300_POWER_OFF 0x00
/* Interrupts */
#define APDS9300_INTR_ENABLE 0x10
/* Interrupt Persist Function: Any value outside of threshold range */
#define APDS9300_THRESH_INTR 0x01
#define APDS9300_THRESH_MAX 0xffff /* Max threshold value */
struct apds9300_data {
struct i2c_client *client;
struct mutex mutex;
int power_state;
int thresh_low;
int thresh_hi;
int intr_en;
};
/* Lux calculation */
/* Calculated values 1000 * (CH1/CH0)^1.4 for CH1/CH0 from 0 to 0.52 */
static const u16 apds9300_lux_ratio[] = {
0, 2, 4, 7, 11, 15, 19, 24, 29, 34, 40, 45, 51, 57, 64, 70, 77, 84, 91,
98, 105, 112, 120, 128, 136, 144, 152, 160, 168, 177, 185, 194, 203,
212, 221, 230, 239, 249, 258, 268, 277, 287, 297, 307, 317, 327, 337,
347, 358, 368, 379, 390, 400,
};
static unsigned long apds9300_calculate_lux(u16 ch0, u16 ch1)
{
unsigned long lux, tmp;
/* avoid division by zero */
if (ch0 == 0)
return 0;
tmp = DIV_ROUND_UP(ch1 * 100, ch0);
if (tmp <= 52) {
lux = 3150 * ch0 - (unsigned long)DIV_ROUND_UP_ULL(ch0
* apds9300_lux_ratio[tmp] * 5930ull, 1000);
} else if (tmp <= 65) {
lux = 2290 * ch0 - 2910 * ch1;
} else if (tmp <= 80) {
lux = 1570 * ch0 - 1800 * ch1;
} else if (tmp <= 130) {
lux = 338 * ch0 - 260 * ch1;
} else {
lux = 0;
}
return lux / 100000;
}
static int apds9300_get_adc_val(struct apds9300_data *data, int adc_number)
{
int ret;
u8 flags = APDS9300_CMD | APDS9300_WORD;
if (!data->power_state)
return -EBUSY;
/* Select ADC0 or ADC1 data register */
flags |= adc_number ? APDS9300_DATA1LOW : APDS9300_DATA0LOW;
ret = i2c_smbus_read_word_data(data->client, flags);
if (ret < 0)
dev_err(&data->client->dev,
"failed to read ADC%d value\n", adc_number);
return ret;
}
static int apds9300_set_thresh_low(struct apds9300_data *data, int value)
{
int ret;
if (!data->power_state)
return -EBUSY;
if (value > APDS9300_THRESH_MAX)
return -EINVAL;
ret = i2c_smbus_write_word_data(data->client, APDS9300_THRESHLOWLOW
| APDS9300_CMD | APDS9300_WORD, value);
if (ret) {
dev_err(&data->client->dev, "failed to set thresh_low\n");
return ret;
}
data->thresh_low = value;
return 0;
}
static int apds9300_set_thresh_hi(struct apds9300_data *data, int value)
{
int ret;
if (!data->power_state)
return -EBUSY;
if (value > APDS9300_THRESH_MAX)
return -EINVAL;
ret = i2c_smbus_write_word_data(data->client, APDS9300_THRESHHIGHLOW
| APDS9300_CMD | APDS9300_WORD, value);
if (ret) {
dev_err(&data->client->dev, "failed to set thresh_hi\n");
return ret;
}
data->thresh_hi = value;
return 0;
}
static int apds9300_set_intr_state(struct apds9300_data *data, int state)
{
int ret;
u8 cmd;
if (!data->power_state)
return -EBUSY;
cmd = state ? APDS9300_INTR_ENABLE | APDS9300_THRESH_INTR : 0x00;
ret = i2c_smbus_write_byte_data(data->client,
APDS9300_INTERRUPT | APDS9300_CMD, cmd);
if (ret) {
dev_err(&data->client->dev,
"failed to set interrupt state %d\n", state);
return ret;
}
data->intr_en = state;
return 0;
}
static int apds9300_set_power_state(struct apds9300_data *data, int state)
{
int ret;
u8 cmd;
cmd = state ? APDS9300_POWER_ON : APDS9300_POWER_OFF;
ret = i2c_smbus_write_byte_data(data->client,
APDS9300_CONTROL | APDS9300_CMD, cmd);
if (ret) {
dev_err(&data->client->dev,
"failed to set power state %d\n", state);
return ret;
}
data->power_state = state;
return 0;
}
static void apds9300_clear_intr(struct apds9300_data *data)
{
int ret;
ret = i2c_smbus_write_byte(data->client, APDS9300_CLEAR | APDS9300_CMD);
if (ret < 0)
dev_err(&data->client->dev, "failed to clear interrupt\n");
}
static int apds9300_chip_init(struct apds9300_data *data)
{
int ret;
/* Need to set power off to ensure that the chip is off */
ret = apds9300_set_power_state(data, 0);
if (ret < 0)
goto err;
/*
* Probe the chip. To do so we try to power up the device and then to
* read back the 0x03 code
*/
ret = apds9300_set_power_state(data, 1);
if (ret < 0)
goto err;
ret = i2c_smbus_read_byte_data(data->client,
APDS9300_CONTROL | APDS9300_CMD);
if (ret != APDS9300_POWER_ON) {
ret = -ENODEV;
goto err;
}
/*
* Disable interrupt to ensure thai it is doesn't enable
* i.e. after device soft reset
*/
ret = apds9300_set_intr_state(data, 0);
if (ret < 0)
goto err;
return 0;
err:
dev_err(&data->client->dev, "failed to init the chip\n");
return ret;
}
static int apds9300_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2,
long mask)
{
int ch0, ch1, ret = -EINVAL;
struct apds9300_data *data = iio_priv(indio_dev);
mutex_lock(&data->mutex);
switch (chan->type) {
case IIO_LIGHT:
ch0 = apds9300_get_adc_val(data, 0);
if (ch0 < 0) {
ret = ch0;
break;
}
ch1 = apds9300_get_adc_val(data, 1);
if (ch1 < 0) {
ret = ch1;
break;
}
*val = apds9300_calculate_lux(ch0, ch1);
ret = IIO_VAL_INT;
break;
case IIO_INTENSITY:
ret = apds9300_get_adc_val(data, chan->channel);
if (ret < 0)
break;
*val = ret;
ret = IIO_VAL_INT;
break;
default:
break;
}
mutex_unlock(&data->mutex);
return ret;
}
static int apds9300_read_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info,
int *val, int *val2)
{
struct apds9300_data *data = iio_priv(indio_dev);
switch (dir) {
case IIO_EV_DIR_RISING:
*val = data->thresh_hi;
break;
case IIO_EV_DIR_FALLING:
*val = data->thresh_low;
break;
default:
return -EINVAL;
}
return IIO_VAL_INT;
}
static int apds9300_write_thresh(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info, int val,
int val2)
{
struct apds9300_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->mutex);
if (dir == IIO_EV_DIR_RISING)
ret = apds9300_set_thresh_hi(data, val);
else
ret = apds9300_set_thresh_low(data, val);
mutex_unlock(&data->mutex);
return ret;
}
static int apds9300_read_interrupt_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct apds9300_data *data = iio_priv(indio_dev);
return data->intr_en;
}
static int apds9300_write_interrupt_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct apds9300_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->mutex);
ret = apds9300_set_intr_state(data, state);
mutex_unlock(&data->mutex);
return ret;
}
static const struct iio_info apds9300_info_no_irq = {
.read_raw = apds9300_read_raw,
};
static const struct iio_info apds9300_info = {
.read_raw = apds9300_read_raw,
.read_event_value = apds9300_read_thresh,
.write_event_value = apds9300_write_thresh,
.read_event_config = apds9300_read_interrupt_config,
.write_event_config = apds9300_write_interrupt_config,
};
static const struct iio_event_spec apds9300_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec apds9300_channels[] = {
{
.type = IIO_LIGHT,
.channel = 0,
.indexed = true,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
}, {
.type = IIO_INTENSITY,
.channel = 0,
.channel2 = IIO_MOD_LIGHT_BOTH,
.indexed = true,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.event_spec = apds9300_event_spec,
.num_event_specs = ARRAY_SIZE(apds9300_event_spec),
}, {
.type = IIO_INTENSITY,
.channel = 1,
.channel2 = IIO_MOD_LIGHT_IR,
.indexed = true,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
},
};
static irqreturn_t apds9300_interrupt_handler(int irq, void *private)
{
struct iio_dev *dev_info = private;
struct apds9300_data *data = iio_priv(dev_info);
iio_push_event(dev_info,
IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(dev_info));
apds9300_clear_intr(data);
return IRQ_HANDLED;
}
static int apds9300_probe(struct i2c_client *client)
{
struct apds9300_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
ret = apds9300_chip_init(data);
if (ret < 0)
goto err;
mutex_init(&data->mutex);
indio_dev->channels = apds9300_channels;
indio_dev->num_channels = ARRAY_SIZE(apds9300_channels);
indio_dev->name = APDS9300_DRV_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
if (client->irq)
indio_dev->info = &apds9300_info;
else
indio_dev->info = &apds9300_info_no_irq;
if (client->irq) {
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, apds9300_interrupt_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
APDS9300_IRQ_NAME, indio_dev);
if (ret) {
dev_err(&client->dev, "irq request error %d\n", -ret);
goto err;
}
}
ret = iio_device_register(indio_dev);
if (ret < 0)
goto err;
return 0;
err:
/* Ensure that power off in case of error */
apds9300_set_power_state(data, 0);
return ret;
}
static void apds9300_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct apds9300_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
/* Ensure that power off and interrupts are disabled */
apds9300_set_intr_state(data, 0);
apds9300_set_power_state(data, 0);
}
static int apds9300_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct apds9300_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->mutex);
ret = apds9300_set_power_state(data, 0);
mutex_unlock(&data->mutex);
return ret;
}
static int apds9300_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct apds9300_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->mutex);
ret = apds9300_set_power_state(data, 1);
mutex_unlock(&data->mutex);
return ret;
}
static DEFINE_SIMPLE_DEV_PM_OPS(apds9300_pm_ops, apds9300_suspend,
apds9300_resume);
static const struct i2c_device_id apds9300_id[] = {
{ APDS9300_DRV_NAME, 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, apds9300_id);
static struct i2c_driver apds9300_driver = {
.driver = {
.name = APDS9300_DRV_NAME,
.pm = pm_sleep_ptr(&apds9300_pm_ops),
},
.probe = apds9300_probe,
.remove = apds9300_remove,
.id_table = apds9300_id,
};
module_i2c_driver(apds9300_driver);
MODULE_AUTHOR("Kravchenko Oleksandr <[email protected]>");
MODULE_AUTHOR("GlobalLogic inc.");
MODULE_DESCRIPTION("APDS9300 ambient light photo sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/apds9300.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015 Intel Corporation
*
* Driver for TXC PA12203001 Proximity and Ambient Light Sensor.
*
* To do: Interrupt support.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/mutex.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#define PA12203001_DRIVER_NAME "pa12203001"
#define PA12203001_REG_CFG0 0x00
#define PA12203001_REG_CFG1 0x01
#define PA12203001_REG_CFG2 0x02
#define PA12203001_REG_CFG3 0x03
#define PA12203001_REG_ADL 0x0b
#define PA12203001_REG_PDH 0x0e
#define PA12203001_REG_POFS 0x10
#define PA12203001_REG_PSET 0x11
#define PA12203001_ALS_EN_MASK BIT(0)
#define PA12203001_PX_EN_MASK BIT(1)
#define PA12203001_PX_NORMAL_MODE_MASK GENMASK(7, 6)
#define PA12203001_AFSR_MASK GENMASK(5, 4)
#define PA12203001_AFSR_SHIFT 4
#define PA12203001_PSCAN 0x03
/* als range 31000, ps, als disabled */
#define PA12203001_REG_CFG0_DEFAULT 0x30
/* led current: 100 mA */
#define PA12203001_REG_CFG1_DEFAULT 0x20
/* ps mode: normal, interrupts not active */
#define PA12203001_REG_CFG2_DEFAULT 0xcc
#define PA12203001_REG_CFG3_DEFAULT 0x00
#define PA12203001_SLEEP_DELAY_MS 3000
#define PA12203001_CHIP_ENABLE 0xff
#define PA12203001_CHIP_DISABLE 0x00
/* available scales: corresponding to [500, 4000, 7000, 31000] lux */
static const int pa12203001_scales[] = { 7629, 61036, 106813, 473029};
struct pa12203001_data {
struct i2c_client *client;
/* protect device states */
struct mutex lock;
bool als_enabled;
bool px_enabled;
bool als_needs_enable;
bool px_needs_enable;
struct regmap *map;
};
static const struct {
u8 reg;
u8 val;
} regvals[] = {
{PA12203001_REG_CFG0, PA12203001_REG_CFG0_DEFAULT},
{PA12203001_REG_CFG1, PA12203001_REG_CFG1_DEFAULT},
{PA12203001_REG_CFG2, PA12203001_REG_CFG2_DEFAULT},
{PA12203001_REG_CFG3, PA12203001_REG_CFG3_DEFAULT},
{PA12203001_REG_PSET, PA12203001_PSCAN},
};
static IIO_CONST_ATTR(in_illuminance_scale_available,
"0.007629 0.061036 0.106813 0.473029");
static struct attribute *pa12203001_attrs[] = {
&iio_const_attr_in_illuminance_scale_available.dev_attr.attr,
NULL
};
static const struct attribute_group pa12203001_attr_group = {
.attrs = pa12203001_attrs,
};
static const struct iio_chan_spec pa12203001_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
{
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
}
};
static const struct regmap_range pa12203001_volatile_regs_ranges[] = {
regmap_reg_range(PA12203001_REG_ADL, PA12203001_REG_ADL + 1),
regmap_reg_range(PA12203001_REG_PDH, PA12203001_REG_PDH),
};
static const struct regmap_access_table pa12203001_volatile_regs = {
.yes_ranges = pa12203001_volatile_regs_ranges,
.n_yes_ranges = ARRAY_SIZE(pa12203001_volatile_regs_ranges),
};
static const struct regmap_config pa12203001_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = PA12203001_REG_PSET,
.cache_type = REGCACHE_RBTREE,
.volatile_table = &pa12203001_volatile_regs,
};
static inline int pa12203001_als_enable(struct pa12203001_data *data, u8 enable)
{
int ret;
ret = regmap_update_bits(data->map, PA12203001_REG_CFG0,
PA12203001_ALS_EN_MASK, enable);
if (ret < 0)
return ret;
data->als_enabled = !!enable;
return 0;
}
static inline int pa12203001_px_enable(struct pa12203001_data *data, u8 enable)
{
int ret;
ret = regmap_update_bits(data->map, PA12203001_REG_CFG0,
PA12203001_PX_EN_MASK, enable);
if (ret < 0)
return ret;
data->px_enabled = !!enable;
return 0;
}
static int pa12203001_set_power_state(struct pa12203001_data *data, bool on,
u8 mask)
{
#ifdef CONFIG_PM
int ret;
if (on && (mask & PA12203001_ALS_EN_MASK)) {
mutex_lock(&data->lock);
if (data->px_enabled) {
ret = pa12203001_als_enable(data,
PA12203001_ALS_EN_MASK);
if (ret < 0)
goto err;
} else {
data->als_needs_enable = true;
}
mutex_unlock(&data->lock);
}
if (on && (mask & PA12203001_PX_EN_MASK)) {
mutex_lock(&data->lock);
if (data->als_enabled) {
ret = pa12203001_px_enable(data, PA12203001_PX_EN_MASK);
if (ret < 0)
goto err;
} else {
data->px_needs_enable = true;
}
mutex_unlock(&data->lock);
}
if (on) {
ret = pm_runtime_resume_and_get(&data->client->dev);
} else {
pm_runtime_mark_last_busy(&data->client->dev);
ret = pm_runtime_put_autosuspend(&data->client->dev);
}
return ret;
err:
mutex_unlock(&data->lock);
return ret;
#endif
return 0;
}
static int pa12203001_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct pa12203001_data *data = iio_priv(indio_dev);
int ret;
u8 dev_mask;
unsigned int reg_byte;
__le16 reg_word;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->type) {
case IIO_LIGHT:
dev_mask = PA12203001_ALS_EN_MASK;
ret = pa12203001_set_power_state(data, true, dev_mask);
if (ret < 0)
return ret;
/*
* ALS ADC value is stored in registers
* PA12203001_REG_ADL and in PA12203001_REG_ADL + 1.
*/
ret = regmap_bulk_read(data->map, PA12203001_REG_ADL,
®_word, 2);
if (ret < 0)
goto reg_err;
*val = le16_to_cpu(reg_word);
ret = pa12203001_set_power_state(data, false, dev_mask);
if (ret < 0)
return ret;
break;
case IIO_PROXIMITY:
dev_mask = PA12203001_PX_EN_MASK;
ret = pa12203001_set_power_state(data, true, dev_mask);
if (ret < 0)
return ret;
ret = regmap_read(data->map, PA12203001_REG_PDH,
®_byte);
if (ret < 0)
goto reg_err;
*val = reg_byte;
ret = pa12203001_set_power_state(data, false, dev_mask);
if (ret < 0)
return ret;
break;
default:
return -EINVAL;
}
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
ret = regmap_read(data->map, PA12203001_REG_CFG0, ®_byte);
if (ret < 0)
return ret;
*val = 0;
reg_byte = (reg_byte & PA12203001_AFSR_MASK);
*val2 = pa12203001_scales[reg_byte >> 4];
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
reg_err:
pa12203001_set_power_state(data, false, dev_mask);
return ret;
}
static int pa12203001_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct pa12203001_data *data = iio_priv(indio_dev);
int i, ret, new_val;
unsigned int reg_byte;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
ret = regmap_read(data->map, PA12203001_REG_CFG0, ®_byte);
if (val != 0 || ret < 0)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(pa12203001_scales); i++) {
if (val2 == pa12203001_scales[i]) {
new_val = i << PA12203001_AFSR_SHIFT;
return regmap_update_bits(data->map,
PA12203001_REG_CFG0,
PA12203001_AFSR_MASK,
new_val);
}
}
break;
default:
break;
}
return -EINVAL;
}
static const struct iio_info pa12203001_info = {
.read_raw = pa12203001_read_raw,
.write_raw = pa12203001_write_raw,
.attrs = &pa12203001_attr_group,
};
static int pa12203001_init(struct iio_dev *indio_dev)
{
struct pa12203001_data *data = iio_priv(indio_dev);
int i, ret;
for (i = 0; i < ARRAY_SIZE(regvals); i++) {
ret = regmap_write(data->map, regvals[i].reg, regvals[i].val);
if (ret < 0)
return ret;
}
return 0;
}
static int pa12203001_power_chip(struct iio_dev *indio_dev, u8 state)
{
struct pa12203001_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->lock);
ret = pa12203001_als_enable(data, state);
if (ret < 0)
goto out;
ret = pa12203001_px_enable(data, state);
out:
mutex_unlock(&data->lock);
return ret;
}
static int pa12203001_probe(struct i2c_client *client)
{
struct pa12203001_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev,
sizeof(struct pa12203001_data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->map = devm_regmap_init_i2c(client, &pa12203001_regmap_config);
if (IS_ERR(data->map))
return PTR_ERR(data->map);
mutex_init(&data->lock);
indio_dev->info = &pa12203001_info;
indio_dev->name = PA12203001_DRIVER_NAME;
indio_dev->channels = pa12203001_channels;
indio_dev->num_channels = ARRAY_SIZE(pa12203001_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = pa12203001_init(indio_dev);
if (ret < 0)
return ret;
ret = pa12203001_power_chip(indio_dev, PA12203001_CHIP_ENABLE);
if (ret < 0)
return ret;
ret = pm_runtime_set_active(&client->dev);
if (ret < 0)
goto out_err;
pm_runtime_enable(&client->dev);
pm_runtime_set_autosuspend_delay(&client->dev,
PA12203001_SLEEP_DELAY_MS);
pm_runtime_use_autosuspend(&client->dev);
ret = iio_device_register(indio_dev);
if (ret < 0)
goto out_err;
return 0;
out_err:
pa12203001_power_chip(indio_dev, PA12203001_CHIP_DISABLE);
return ret;
}
static void pa12203001_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
int ret;
iio_device_unregister(indio_dev);
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
ret = pa12203001_power_chip(indio_dev, PA12203001_CHIP_DISABLE);
if (ret)
dev_warn(&client->dev, "Failed to power down (%pe)\n",
ERR_PTR(ret));
}
#if defined(CONFIG_PM_SLEEP) || defined(CONFIG_PM)
static int pa12203001_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
return pa12203001_power_chip(indio_dev, PA12203001_CHIP_DISABLE);
}
#endif
#ifdef CONFIG_PM_SLEEP
static int pa12203001_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
return pa12203001_power_chip(indio_dev, PA12203001_CHIP_ENABLE);
}
#endif
#ifdef CONFIG_PM
static int pa12203001_runtime_resume(struct device *dev)
{
struct pa12203001_data *data;
data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
mutex_lock(&data->lock);
if (data->als_needs_enable) {
pa12203001_als_enable(data, PA12203001_ALS_EN_MASK);
data->als_needs_enable = false;
}
if (data->px_needs_enable) {
pa12203001_px_enable(data, PA12203001_PX_EN_MASK);
data->px_needs_enable = false;
}
mutex_unlock(&data->lock);
return 0;
}
#endif
static const struct dev_pm_ops pa12203001_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(pa12203001_suspend, pa12203001_resume)
SET_RUNTIME_PM_OPS(pa12203001_suspend, pa12203001_runtime_resume, NULL)
};
static const struct acpi_device_id pa12203001_acpi_match[] = {
{ "TXCPA122", 0 },
{}
};
MODULE_DEVICE_TABLE(acpi, pa12203001_acpi_match);
static const struct i2c_device_id pa12203001_id[] = {
{ "txcpa122", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, pa12203001_id);
static struct i2c_driver pa12203001_driver = {
.driver = {
.name = PA12203001_DRIVER_NAME,
.pm = &pa12203001_pm_ops,
.acpi_match_table = ACPI_PTR(pa12203001_acpi_match),
},
.probe = pa12203001_probe,
.remove = pa12203001_remove,
.id_table = pa12203001_id,
};
module_i2c_driver(pa12203001_driver);
MODULE_AUTHOR("Adriana Reus <[email protected]>");
MODULE_DESCRIPTION("Driver for TXC PA12203001 Proximity and Light Sensor");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/pa12203001.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* STMicroelectronics uvis25 spi driver
*
* Copyright 2017 STMicroelectronics Inc.
*
* Lorenzo Bianconi <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include "st_uvis25.h"
#define UVIS25_SENSORS_SPI_READ BIT(7)
#define UVIS25_SPI_AUTO_INCREMENT BIT(6)
static const struct regmap_config st_uvis25_spi_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.read_flag_mask = UVIS25_SENSORS_SPI_READ | UVIS25_SPI_AUTO_INCREMENT,
.write_flag_mask = UVIS25_SPI_AUTO_INCREMENT,
};
static int st_uvis25_spi_probe(struct spi_device *spi)
{
struct regmap *regmap;
regmap = devm_regmap_init_spi(spi, &st_uvis25_spi_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&spi->dev, "Failed to register spi regmap %ld\n",
PTR_ERR(regmap));
return PTR_ERR(regmap);
}
return st_uvis25_probe(&spi->dev, spi->irq, regmap);
}
static const struct of_device_id st_uvis25_spi_of_match[] = {
{ .compatible = "st,uvis25", },
{},
};
MODULE_DEVICE_TABLE(of, st_uvis25_spi_of_match);
static const struct spi_device_id st_uvis25_spi_id_table[] = {
{ ST_UVIS25_DEV_NAME },
{},
};
MODULE_DEVICE_TABLE(spi, st_uvis25_spi_id_table);
static struct spi_driver st_uvis25_driver = {
.driver = {
.name = "st_uvis25_spi",
.pm = pm_sleep_ptr(&st_uvis25_pm_ops),
.of_match_table = st_uvis25_spi_of_match,
},
.probe = st_uvis25_spi_probe,
.id_table = st_uvis25_spi_id_table,
};
module_spi_driver(st_uvis25_driver);
MODULE_AUTHOR("Lorenzo Bianconi <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics uvis25 spi driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(IIO_UVIS25);
| linux-master | drivers/iio/light/st_uvis25_spi.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* apds9960.c - Support for Avago APDS9960 gesture/RGB/ALS/proximity sensor
*
* Copyright (C) 2015, 2018
* Author: Matt Ranostay <[email protected]>
*
* TODO: gesture + proximity calib offsets
*/
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/i2c.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/events.h>
#include <linux/iio/kfifo_buf.h>
#include <linux/iio/sysfs.h>
#define APDS9960_REGMAP_NAME "apds9960_regmap"
#define APDS9960_DRV_NAME "apds9960"
#define APDS9960_REG_RAM_START 0x00
#define APDS9960_REG_RAM_END 0x7f
#define APDS9960_REG_ENABLE 0x80
#define APDS9960_REG_ATIME 0x81
#define APDS9960_REG_WTIME 0x83
#define APDS9960_REG_AILTL 0x84
#define APDS9960_REG_AILTH 0x85
#define APDS9960_REG_AIHTL 0x86
#define APDS9960_REG_AIHTH 0x87
#define APDS9960_REG_PILT 0x89
#define APDS9960_REG_PIHT 0x8b
#define APDS9960_REG_PERS 0x8c
#define APDS9960_REG_CONFIG_1 0x8d
#define APDS9960_REG_PPULSE 0x8e
#define APDS9960_REG_CONTROL 0x8f
#define APDS9960_REG_CONTROL_AGAIN_MASK 0x03
#define APDS9960_REG_CONTROL_PGAIN_MASK 0x0c
#define APDS9960_REG_CONTROL_AGAIN_MASK_SHIFT 0
#define APDS9960_REG_CONTROL_PGAIN_MASK_SHIFT 2
#define APDS9960_REG_CONFIG_2 0x90
#define APDS9960_REG_ID 0x92
#define APDS9960_REG_STATUS 0x93
#define APDS9960_REG_STATUS_PS_INT BIT(5)
#define APDS9960_REG_STATUS_ALS_INT BIT(4)
#define APDS9960_REG_STATUS_GINT BIT(2)
#define APDS9960_REG_PDATA 0x9c
#define APDS9960_REG_POFFSET_UR 0x9d
#define APDS9960_REG_POFFSET_DL 0x9e
#define APDS9960_REG_CONFIG_3 0x9f
#define APDS9960_REG_GPENTH 0xa0
#define APDS9960_REG_GEXTH 0xa1
#define APDS9960_REG_GCONF_1 0xa2
#define APDS9960_REG_GCONF_1_GFIFO_THRES_MASK 0xc0
#define APDS9960_REG_GCONF_1_GFIFO_THRES_MASK_SHIFT 6
#define APDS9960_REG_GCONF_2 0xa3
#define APDS9960_REG_GCONF_2_GGAIN_MASK 0x60
#define APDS9960_REG_GCONF_2_GGAIN_MASK_SHIFT 5
#define APDS9960_REG_GOFFSET_U 0xa4
#define APDS9960_REG_GOFFSET_D 0xa5
#define APDS9960_REG_GPULSE 0xa6
#define APDS9960_REG_GOFFSET_L 0xa7
#define APDS9960_REG_GOFFSET_R 0xa9
#define APDS9960_REG_GCONF_3 0xaa
#define APDS9960_REG_GCONF_4 0xab
#define APDS9960_REG_GFLVL 0xae
#define APDS9960_REG_GSTATUS 0xaf
#define APDS9960_REG_IFORCE 0xe4
#define APDS9960_REG_PICLEAR 0xe5
#define APDS9960_REG_CICLEAR 0xe6
#define APDS9960_REG_AICLEAR 0xe7
#define APDS9960_DEFAULT_PERS 0x33
#define APDS9960_DEFAULT_GPENTH 0x50
#define APDS9960_DEFAULT_GEXTH 0x40
#define APDS9960_MAX_PXS_THRES_VAL 255
#define APDS9960_MAX_ALS_THRES_VAL 0xffff
#define APDS9960_MAX_INT_TIME_IN_US 1000000
enum apds9960_als_channel_idx {
IDX_ALS_CLEAR, IDX_ALS_RED, IDX_ALS_GREEN, IDX_ALS_BLUE,
};
#define APDS9960_REG_ALS_BASE 0x94
#define APDS9960_REG_ALS_CHANNEL(_colour) \
(APDS9960_REG_ALS_BASE + (IDX_ALS_##_colour * 2))
enum apds9960_gesture_channel_idx {
IDX_DIR_UP, IDX_DIR_DOWN, IDX_DIR_LEFT, IDX_DIR_RIGHT,
};
#define APDS9960_REG_GFIFO_BASE 0xfc
#define APDS9960_REG_GFIFO_DIR(_dir) \
(APDS9960_REG_GFIFO_BASE + IDX_DIR_##_dir)
struct apds9960_data {
struct i2c_client *client;
struct iio_dev *indio_dev;
struct mutex lock;
/* regmap fields */
struct regmap *regmap;
struct regmap_field *reg_int_als;
struct regmap_field *reg_int_ges;
struct regmap_field *reg_int_pxs;
struct regmap_field *reg_enable_als;
struct regmap_field *reg_enable_ges;
struct regmap_field *reg_enable_pxs;
/* state */
int als_int;
int pxs_int;
int gesture_mode_running;
/* gain values */
int als_gain;
int pxs_gain;
/* integration time value in us */
int als_adc_int_us;
/* gesture buffer */
u8 buffer[4]; /* 4 8-bit channels */
};
static const struct reg_default apds9960_reg_defaults[] = {
/* Default ALS integration time = 2.48ms */
{ APDS9960_REG_ATIME, 0xff },
};
static const struct regmap_range apds9960_volatile_ranges[] = {
regmap_reg_range(APDS9960_REG_STATUS,
APDS9960_REG_PDATA),
regmap_reg_range(APDS9960_REG_GFLVL,
APDS9960_REG_GSTATUS),
regmap_reg_range(APDS9960_REG_GFIFO_DIR(UP),
APDS9960_REG_GFIFO_DIR(RIGHT)),
regmap_reg_range(APDS9960_REG_IFORCE,
APDS9960_REG_AICLEAR),
};
static const struct regmap_access_table apds9960_volatile_table = {
.yes_ranges = apds9960_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(apds9960_volatile_ranges),
};
static const struct regmap_range apds9960_precious_ranges[] = {
regmap_reg_range(APDS9960_REG_RAM_START, APDS9960_REG_RAM_END),
};
static const struct regmap_access_table apds9960_precious_table = {
.yes_ranges = apds9960_precious_ranges,
.n_yes_ranges = ARRAY_SIZE(apds9960_precious_ranges),
};
static const struct regmap_range apds9960_readable_ranges[] = {
regmap_reg_range(APDS9960_REG_ENABLE,
APDS9960_REG_GSTATUS),
regmap_reg_range(APDS9960_REG_GFIFO_DIR(UP),
APDS9960_REG_GFIFO_DIR(RIGHT)),
};
static const struct regmap_access_table apds9960_readable_table = {
.yes_ranges = apds9960_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(apds9960_readable_ranges),
};
static const struct regmap_range apds9960_writeable_ranges[] = {
regmap_reg_range(APDS9960_REG_ENABLE, APDS9960_REG_CONFIG_2),
regmap_reg_range(APDS9960_REG_POFFSET_UR, APDS9960_REG_GCONF_4),
regmap_reg_range(APDS9960_REG_IFORCE, APDS9960_REG_AICLEAR),
};
static const struct regmap_access_table apds9960_writeable_table = {
.yes_ranges = apds9960_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(apds9960_writeable_ranges),
};
static const struct regmap_config apds9960_regmap_config = {
.name = APDS9960_REGMAP_NAME,
.reg_bits = 8,
.val_bits = 8,
.use_single_read = true,
.use_single_write = true,
.volatile_table = &apds9960_volatile_table,
.precious_table = &apds9960_precious_table,
.rd_table = &apds9960_readable_table,
.wr_table = &apds9960_writeable_table,
.reg_defaults = apds9960_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(apds9960_reg_defaults),
.max_register = APDS9960_REG_GFIFO_DIR(RIGHT),
.cache_type = REGCACHE_RBTREE,
};
static const struct iio_event_spec apds9960_pxs_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
},
{
.type = IIO_EV_TYPE_THRESH,
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_event_spec apds9960_als_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
},
{
.type = IIO_EV_TYPE_THRESH,
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
},
};
#define APDS9960_GESTURE_CHANNEL(_dir, _si) { \
.type = IIO_PROXIMITY, \
.channel = _si + 1, \
.scan_index = _si, \
.indexed = 1, \
.scan_type = { \
.sign = 'u', \
.realbits = 8, \
.storagebits = 8, \
}, \
}
#define APDS9960_INTENSITY_CHANNEL(_colour) { \
.type = IIO_INTENSITY, \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_INT_TIME), \
.channel2 = IIO_MOD_LIGHT_##_colour, \
.address = APDS9960_REG_ALS_CHANNEL(_colour), \
.modified = 1, \
.scan_index = -1, \
}
static const unsigned long apds9960_scan_masks[] = {0xf, 0};
static const struct iio_chan_spec apds9960_channels[] = {
{
.type = IIO_PROXIMITY,
.address = APDS9960_REG_PDATA,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
.channel = 0,
.indexed = 0,
.scan_index = -1,
.event_spec = apds9960_pxs_event_spec,
.num_event_specs = ARRAY_SIZE(apds9960_pxs_event_spec),
},
/* Gesture Sensor */
APDS9960_GESTURE_CHANNEL(UP, 0),
APDS9960_GESTURE_CHANNEL(DOWN, 1),
APDS9960_GESTURE_CHANNEL(LEFT, 2),
APDS9960_GESTURE_CHANNEL(RIGHT, 3),
/* ALS */
{
.type = IIO_INTENSITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_INT_TIME),
.channel2 = IIO_MOD_LIGHT_CLEAR,
.address = APDS9960_REG_ALS_CHANNEL(CLEAR),
.modified = 1,
.scan_index = -1,
.event_spec = apds9960_als_event_spec,
.num_event_specs = ARRAY_SIZE(apds9960_als_event_spec),
},
/* RGB Sensor */
APDS9960_INTENSITY_CHANNEL(RED),
APDS9960_INTENSITY_CHANNEL(GREEN),
APDS9960_INTENSITY_CHANNEL(BLUE),
};
/* integration time in us */
static const int apds9960_int_time[][2] = {
{ 28000, 246},
{100000, 219},
{200000, 182},
{700000, 0}
};
/* gain mapping */
static const int apds9960_pxs_gain_map[] = {1, 2, 4, 8};
static const int apds9960_als_gain_map[] = {1, 4, 16, 64};
static IIO_CONST_ATTR(proximity_scale_available, "1 2 4 8");
static IIO_CONST_ATTR(intensity_scale_available, "1 4 16 64");
static IIO_CONST_ATTR_INT_TIME_AVAIL("0.028 0.1 0.2 0.7");
static struct attribute *apds9960_attributes[] = {
&iio_const_attr_proximity_scale_available.dev_attr.attr,
&iio_const_attr_intensity_scale_available.dev_attr.attr,
&iio_const_attr_integration_time_available.dev_attr.attr,
NULL,
};
static const struct attribute_group apds9960_attribute_group = {
.attrs = apds9960_attributes,
};
static const struct reg_field apds9960_reg_field_int_als =
REG_FIELD(APDS9960_REG_ENABLE, 4, 4);
static const struct reg_field apds9960_reg_field_int_ges =
REG_FIELD(APDS9960_REG_GCONF_4, 1, 1);
static const struct reg_field apds9960_reg_field_int_pxs =
REG_FIELD(APDS9960_REG_ENABLE, 5, 5);
static const struct reg_field apds9960_reg_field_enable_als =
REG_FIELD(APDS9960_REG_ENABLE, 1, 1);
static const struct reg_field apds9960_reg_field_enable_ges =
REG_FIELD(APDS9960_REG_ENABLE, 6, 6);
static const struct reg_field apds9960_reg_field_enable_pxs =
REG_FIELD(APDS9960_REG_ENABLE, 2, 2);
static int apds9960_set_it_time(struct apds9960_data *data, int val2)
{
int ret = -EINVAL;
int idx;
for (idx = 0; idx < ARRAY_SIZE(apds9960_int_time); idx++) {
if (apds9960_int_time[idx][0] == val2) {
mutex_lock(&data->lock);
ret = regmap_write(data->regmap, APDS9960_REG_ATIME,
apds9960_int_time[idx][1]);
if (!ret)
data->als_adc_int_us = val2;
mutex_unlock(&data->lock);
break;
}
}
return ret;
}
static int apds9960_set_pxs_gain(struct apds9960_data *data, int val)
{
int ret = -EINVAL;
int idx;
for (idx = 0; idx < ARRAY_SIZE(apds9960_pxs_gain_map); idx++) {
if (apds9960_pxs_gain_map[idx] == val) {
/* pxs + gesture gains are mirrored */
mutex_lock(&data->lock);
ret = regmap_update_bits(data->regmap,
APDS9960_REG_CONTROL,
APDS9960_REG_CONTROL_PGAIN_MASK,
idx << APDS9960_REG_CONTROL_PGAIN_MASK_SHIFT);
if (ret) {
mutex_unlock(&data->lock);
break;
}
ret = regmap_update_bits(data->regmap,
APDS9960_REG_GCONF_2,
APDS9960_REG_GCONF_2_GGAIN_MASK,
idx << APDS9960_REG_GCONF_2_GGAIN_MASK_SHIFT);
if (!ret)
data->pxs_gain = idx;
mutex_unlock(&data->lock);
break;
}
}
return ret;
}
static int apds9960_set_als_gain(struct apds9960_data *data, int val)
{
int ret = -EINVAL;
int idx;
for (idx = 0; idx < ARRAY_SIZE(apds9960_als_gain_map); idx++) {
if (apds9960_als_gain_map[idx] == val) {
mutex_lock(&data->lock);
ret = regmap_update_bits(data->regmap,
APDS9960_REG_CONTROL,
APDS9960_REG_CONTROL_AGAIN_MASK, idx);
if (!ret)
data->als_gain = idx;
mutex_unlock(&data->lock);
break;
}
}
return ret;
}
#ifdef CONFIG_PM
static int apds9960_set_power_state(struct apds9960_data *data, bool on)
{
struct device *dev = &data->client->dev;
int ret = 0;
mutex_lock(&data->lock);
if (on) {
int suspended;
suspended = pm_runtime_suspended(dev);
ret = pm_runtime_get_sync(dev);
/* Allow one integration cycle before allowing a reading */
if (suspended)
usleep_range(data->als_adc_int_us,
APDS9960_MAX_INT_TIME_IN_US);
} else {
pm_runtime_mark_last_busy(dev);
ret = pm_runtime_put_autosuspend(dev);
}
mutex_unlock(&data->lock);
return ret;
}
#else
static int apds9960_set_power_state(struct apds9960_data *data, bool on)
{
return 0;
}
#endif
static int apds9960_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct apds9960_data *data = iio_priv(indio_dev);
__le16 buf;
int ret = -EINVAL;
if (data->gesture_mode_running)
return -EBUSY;
switch (mask) {
case IIO_CHAN_INFO_RAW:
apds9960_set_power_state(data, true);
switch (chan->type) {
case IIO_PROXIMITY:
ret = regmap_read(data->regmap, chan->address, val);
if (!ret)
ret = IIO_VAL_INT;
break;
case IIO_INTENSITY:
ret = regmap_bulk_read(data->regmap, chan->address,
&buf, 2);
if (!ret) {
ret = IIO_VAL_INT;
*val = le16_to_cpu(buf);
}
break;
default:
ret = -EINVAL;
}
apds9960_set_power_state(data, false);
break;
case IIO_CHAN_INFO_INT_TIME:
/* RGB + ALS sensors only have integration time */
mutex_lock(&data->lock);
switch (chan->type) {
case IIO_INTENSITY:
*val = 0;
*val2 = data->als_adc_int_us;
ret = IIO_VAL_INT_PLUS_MICRO;
break;
default:
ret = -EINVAL;
}
mutex_unlock(&data->lock);
break;
case IIO_CHAN_INFO_SCALE:
mutex_lock(&data->lock);
switch (chan->type) {
case IIO_PROXIMITY:
*val = apds9960_pxs_gain_map[data->pxs_gain];
ret = IIO_VAL_INT;
break;
case IIO_INTENSITY:
*val = apds9960_als_gain_map[data->als_gain];
ret = IIO_VAL_INT;
break;
default:
ret = -EINVAL;
}
mutex_unlock(&data->lock);
break;
}
return ret;
};
static int apds9960_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct apds9960_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
/* RGB + ALS sensors only have int time */
switch (chan->type) {
case IIO_INTENSITY:
if (val != 0)
return -EINVAL;
return apds9960_set_it_time(data, val2);
default:
return -EINVAL;
}
case IIO_CHAN_INFO_SCALE:
if (val2 != 0)
return -EINVAL;
switch (chan->type) {
case IIO_PROXIMITY:
return apds9960_set_pxs_gain(data, val);
case IIO_INTENSITY:
return apds9960_set_als_gain(data, val);
default:
return -EINVAL;
}
default:
return -EINVAL;
}
return 0;
}
static inline int apds9960_get_thres_reg(const struct iio_chan_spec *chan,
enum iio_event_direction dir,
u8 *reg)
{
switch (dir) {
case IIO_EV_DIR_RISING:
switch (chan->type) {
case IIO_PROXIMITY:
*reg = APDS9960_REG_PIHT;
break;
case IIO_INTENSITY:
*reg = APDS9960_REG_AIHTL;
break;
default:
return -EINVAL;
}
break;
case IIO_EV_DIR_FALLING:
switch (chan->type) {
case IIO_PROXIMITY:
*reg = APDS9960_REG_PILT;
break;
case IIO_INTENSITY:
*reg = APDS9960_REG_AILTL;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
return 0;
}
static int apds9960_read_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
u8 reg;
__le16 buf;
int ret = 0;
struct apds9960_data *data = iio_priv(indio_dev);
if (info != IIO_EV_INFO_VALUE)
return -EINVAL;
ret = apds9960_get_thres_reg(chan, dir, ®);
if (ret < 0)
return ret;
if (chan->type == IIO_PROXIMITY) {
ret = regmap_read(data->regmap, reg, val);
if (ret < 0)
return ret;
} else if (chan->type == IIO_INTENSITY) {
ret = regmap_bulk_read(data->regmap, reg, &buf, 2);
if (ret < 0)
return ret;
*val = le16_to_cpu(buf);
} else
return -EINVAL;
*val2 = 0;
return IIO_VAL_INT;
}
static int apds9960_write_event(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
u8 reg;
__le16 buf;
int ret = 0;
struct apds9960_data *data = iio_priv(indio_dev);
if (info != IIO_EV_INFO_VALUE)
return -EINVAL;
ret = apds9960_get_thres_reg(chan, dir, ®);
if (ret < 0)
return ret;
if (chan->type == IIO_PROXIMITY) {
if (val < 0 || val > APDS9960_MAX_PXS_THRES_VAL)
return -EINVAL;
ret = regmap_write(data->regmap, reg, val);
if (ret < 0)
return ret;
} else if (chan->type == IIO_INTENSITY) {
if (val < 0 || val > APDS9960_MAX_ALS_THRES_VAL)
return -EINVAL;
buf = cpu_to_le16(val);
ret = regmap_bulk_write(data->regmap, reg, &buf, 2);
if (ret < 0)
return ret;
} else
return -EINVAL;
return 0;
}
static int apds9960_read_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct apds9960_data *data = iio_priv(indio_dev);
switch (chan->type) {
case IIO_PROXIMITY:
return data->pxs_int;
case IIO_INTENSITY:
return data->als_int;
default:
return -EINVAL;
}
return 0;
}
static int apds9960_write_event_config(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state)
{
struct apds9960_data *data = iio_priv(indio_dev);
int ret;
state = !!state;
switch (chan->type) {
case IIO_PROXIMITY:
if (data->pxs_int == state)
return -EINVAL;
ret = regmap_field_write(data->reg_int_pxs, state);
if (ret)
return ret;
data->pxs_int = state;
apds9960_set_power_state(data, state);
break;
case IIO_INTENSITY:
if (data->als_int == state)
return -EINVAL;
ret = regmap_field_write(data->reg_int_als, state);
if (ret)
return ret;
data->als_int = state;
apds9960_set_power_state(data, state);
break;
default:
return -EINVAL;
}
return 0;
}
static const struct iio_info apds9960_info = {
.attrs = &apds9960_attribute_group,
.read_raw = apds9960_read_raw,
.write_raw = apds9960_write_raw,
.read_event_value = apds9960_read_event,
.write_event_value = apds9960_write_event,
.read_event_config = apds9960_read_event_config,
.write_event_config = apds9960_write_event_config,
};
static inline int apds9660_fifo_is_empty(struct apds9960_data *data)
{
int cnt;
int ret;
ret = regmap_read(data->regmap, APDS9960_REG_GFLVL, &cnt);
if (ret)
return ret;
return cnt;
}
static void apds9960_read_gesture_fifo(struct apds9960_data *data)
{
int ret, cnt = 0;
mutex_lock(&data->lock);
data->gesture_mode_running = 1;
while (cnt || (cnt = apds9660_fifo_is_empty(data) > 0)) {
ret = regmap_bulk_read(data->regmap, APDS9960_REG_GFIFO_BASE,
&data->buffer, 4);
if (ret)
goto err_read;
iio_push_to_buffers(data->indio_dev, data->buffer);
cnt--;
}
err_read:
data->gesture_mode_running = 0;
mutex_unlock(&data->lock);
}
static irqreturn_t apds9960_interrupt_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct apds9960_data *data = iio_priv(indio_dev);
int ret, status;
ret = regmap_read(data->regmap, APDS9960_REG_STATUS, &status);
if (ret < 0) {
dev_err(&data->client->dev, "irq status reg read failed\n");
return IRQ_HANDLED;
}
if ((status & APDS9960_REG_STATUS_ALS_INT) && data->als_int) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(indio_dev));
regmap_write(data->regmap, APDS9960_REG_CICLEAR, 1);
}
if ((status & APDS9960_REG_STATUS_PS_INT) && data->pxs_int) {
iio_push_event(indio_dev,
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
iio_get_time_ns(indio_dev));
regmap_write(data->regmap, APDS9960_REG_PICLEAR, 1);
}
if (status & APDS9960_REG_STATUS_GINT)
apds9960_read_gesture_fifo(data);
return IRQ_HANDLED;
}
static int apds9960_set_powermode(struct apds9960_data *data, bool state)
{
return regmap_update_bits(data->regmap, APDS9960_REG_ENABLE, 1, state);
}
static int apds9960_buffer_postenable(struct iio_dev *indio_dev)
{
struct apds9960_data *data = iio_priv(indio_dev);
int ret;
ret = regmap_field_write(data->reg_int_ges, 1);
if (ret)
return ret;
ret = regmap_field_write(data->reg_enable_ges, 1);
if (ret)
return ret;
pm_runtime_get_sync(&data->client->dev);
return 0;
}
static int apds9960_buffer_predisable(struct iio_dev *indio_dev)
{
struct apds9960_data *data = iio_priv(indio_dev);
int ret;
ret = regmap_field_write(data->reg_enable_ges, 0);
if (ret)
return ret;
ret = regmap_field_write(data->reg_int_ges, 0);
if (ret)
return ret;
pm_runtime_put_autosuspend(&data->client->dev);
return 0;
}
static const struct iio_buffer_setup_ops apds9960_buffer_setup_ops = {
.postenable = apds9960_buffer_postenable,
.predisable = apds9960_buffer_predisable,
};
static int apds9960_regfield_init(struct apds9960_data *data)
{
struct device *dev = &data->client->dev;
struct regmap *regmap = data->regmap;
data->reg_int_als = devm_regmap_field_alloc(dev, regmap,
apds9960_reg_field_int_als);
if (IS_ERR(data->reg_int_als)) {
dev_err(dev, "INT ALS reg field init failed\n");
return PTR_ERR(data->reg_int_als);
}
data->reg_int_ges = devm_regmap_field_alloc(dev, regmap,
apds9960_reg_field_int_ges);
if (IS_ERR(data->reg_int_ges)) {
dev_err(dev, "INT gesture reg field init failed\n");
return PTR_ERR(data->reg_int_ges);
}
data->reg_int_pxs = devm_regmap_field_alloc(dev, regmap,
apds9960_reg_field_int_pxs);
if (IS_ERR(data->reg_int_pxs)) {
dev_err(dev, "INT pxs reg field init failed\n");
return PTR_ERR(data->reg_int_pxs);
}
data->reg_enable_als = devm_regmap_field_alloc(dev, regmap,
apds9960_reg_field_enable_als);
if (IS_ERR(data->reg_enable_als)) {
dev_err(dev, "Enable ALS reg field init failed\n");
return PTR_ERR(data->reg_enable_als);
}
data->reg_enable_ges = devm_regmap_field_alloc(dev, regmap,
apds9960_reg_field_enable_ges);
if (IS_ERR(data->reg_enable_ges)) {
dev_err(dev, "Enable gesture reg field init failed\n");
return PTR_ERR(data->reg_enable_ges);
}
data->reg_enable_pxs = devm_regmap_field_alloc(dev, regmap,
apds9960_reg_field_enable_pxs);
if (IS_ERR(data->reg_enable_pxs)) {
dev_err(dev, "Enable PXS reg field init failed\n");
return PTR_ERR(data->reg_enable_pxs);
}
return 0;
}
static int apds9960_chip_init(struct apds9960_data *data)
{
int ret;
/* Default IT for ALS of 28 ms */
ret = apds9960_set_it_time(data, 28000);
if (ret)
return ret;
/* Ensure gesture interrupt is OFF */
ret = regmap_field_write(data->reg_int_ges, 0);
if (ret)
return ret;
/* Disable gesture sensor, since polling is useless from user-space */
ret = regmap_field_write(data->reg_enable_ges, 0);
if (ret)
return ret;
/* Ensure proximity interrupt is OFF */
ret = regmap_field_write(data->reg_int_pxs, 0);
if (ret)
return ret;
/* Enable proximity sensor for polling */
ret = regmap_field_write(data->reg_enable_pxs, 1);
if (ret)
return ret;
/* Ensure ALS interrupt is OFF */
ret = regmap_field_write(data->reg_int_als, 0);
if (ret)
return ret;
/* Enable ALS sensor for polling */
ret = regmap_field_write(data->reg_enable_als, 1);
if (ret)
return ret;
/*
* When enabled trigger an interrupt after 3 readings
* outside threshold for ALS + PXS
*/
ret = regmap_write(data->regmap, APDS9960_REG_PERS,
APDS9960_DEFAULT_PERS);
if (ret)
return ret;
/*
* Wait for 4 event outside gesture threshold to prevent interrupt
* flooding.
*/
ret = regmap_update_bits(data->regmap, APDS9960_REG_GCONF_1,
APDS9960_REG_GCONF_1_GFIFO_THRES_MASK,
BIT(0) << APDS9960_REG_GCONF_1_GFIFO_THRES_MASK_SHIFT);
if (ret)
return ret;
/* Default ENTER and EXIT thresholds for the GESTURE engine. */
ret = regmap_write(data->regmap, APDS9960_REG_GPENTH,
APDS9960_DEFAULT_GPENTH);
if (ret)
return ret;
ret = regmap_write(data->regmap, APDS9960_REG_GEXTH,
APDS9960_DEFAULT_GEXTH);
if (ret)
return ret;
return apds9960_set_powermode(data, 1);
}
static int apds9960_probe(struct i2c_client *client)
{
struct apds9960_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
indio_dev->info = &apds9960_info;
indio_dev->name = APDS9960_DRV_NAME;
indio_dev->channels = apds9960_channels;
indio_dev->num_channels = ARRAY_SIZE(apds9960_channels);
indio_dev->available_scan_masks = apds9960_scan_masks;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = devm_iio_kfifo_buffer_setup(&client->dev, indio_dev,
&apds9960_buffer_setup_ops);
if (ret)
return ret;
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->regmap = devm_regmap_init_i2c(client, &apds9960_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(&client->dev, "regmap initialization failed.\n");
return PTR_ERR(data->regmap);
}
data->client = client;
data->indio_dev = indio_dev;
mutex_init(&data->lock);
ret = pm_runtime_set_active(&client->dev);
if (ret)
goto error_power_down;
pm_runtime_enable(&client->dev);
pm_runtime_set_autosuspend_delay(&client->dev, 5000);
pm_runtime_use_autosuspend(&client->dev);
apds9960_set_power_state(data, true);
ret = apds9960_regfield_init(data);
if (ret)
goto error_power_down;
ret = apds9960_chip_init(data);
if (ret)
goto error_power_down;
if (client->irq <= 0) {
dev_err(&client->dev, "no valid irq defined\n");
ret = -EINVAL;
goto error_power_down;
}
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, apds9960_interrupt_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"apds9960_event",
indio_dev);
if (ret) {
dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
goto error_power_down;
}
ret = iio_device_register(indio_dev);
if (ret)
goto error_power_down;
apds9960_set_power_state(data, false);
return 0;
error_power_down:
apds9960_set_power_state(data, false);
return ret;
}
static void apds9960_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct apds9960_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
apds9960_set_powermode(data, 0);
}
#ifdef CONFIG_PM
static int apds9960_runtime_suspend(struct device *dev)
{
struct apds9960_data *data =
iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
return apds9960_set_powermode(data, 0);
}
static int apds9960_runtime_resume(struct device *dev)
{
struct apds9960_data *data =
iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
return apds9960_set_powermode(data, 1);
}
#endif
static const struct dev_pm_ops apds9960_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(apds9960_runtime_suspend,
apds9960_runtime_resume, NULL)
};
static const struct i2c_device_id apds9960_id[] = {
{ "apds9960", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, apds9960_id);
static const struct acpi_device_id apds9960_acpi_match[] = {
{ "MSHW0184" },
{ }
};
MODULE_DEVICE_TABLE(acpi, apds9960_acpi_match);
static const struct of_device_id apds9960_of_match[] = {
{ .compatible = "avago,apds9960" },
{ }
};
MODULE_DEVICE_TABLE(of, apds9960_of_match);
static struct i2c_driver apds9960_driver = {
.driver = {
.name = APDS9960_DRV_NAME,
.of_match_table = apds9960_of_match,
.pm = &apds9960_pm_ops,
.acpi_match_table = apds9960_acpi_match,
},
.probe = apds9960_probe,
.remove = apds9960_remove,
.id_table = apds9960_id,
};
module_i2c_driver(apds9960_driver);
MODULE_AUTHOR("Matt Ranostay <[email protected]>");
MODULE_DESCRIPTION("APDS9960 Gesture/RGB/ALS/Proximity sensor");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/apds9960.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* adjd_s311.c - Support for ADJD-S311-CR999 digital color sensor
*
* Copyright (C) 2012 Peter Meerwald <[email protected]>
*
* driver for ADJD-S311-CR999 digital color sensor (10-bit channels for
* red, green, blue, clear); 7-bit I2C slave address 0x74
*
* limitations: no calibration, no offset mode, no sleep mode
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/bitmap.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#define ADJD_S311_DRV_NAME "adjd_s311"
#define ADJD_S311_CTRL 0x00
#define ADJD_S311_CONFIG 0x01
#define ADJD_S311_CAP_RED 0x06
#define ADJD_S311_CAP_GREEN 0x07
#define ADJD_S311_CAP_BLUE 0x08
#define ADJD_S311_CAP_CLEAR 0x09
#define ADJD_S311_INT_RED 0x0a
#define ADJD_S311_INT_GREEN 0x0c
#define ADJD_S311_INT_BLUE 0x0e
#define ADJD_S311_INT_CLEAR 0x10
#define ADJD_S311_DATA_RED 0x40
#define ADJD_S311_DATA_GREEN 0x42
#define ADJD_S311_DATA_BLUE 0x44
#define ADJD_S311_DATA_CLEAR 0x46
#define ADJD_S311_OFFSET_RED 0x48
#define ADJD_S311_OFFSET_GREEN 0x49
#define ADJD_S311_OFFSET_BLUE 0x4a
#define ADJD_S311_OFFSET_CLEAR 0x4b
#define ADJD_S311_CTRL_GOFS 0x02
#define ADJD_S311_CTRL_GSSR 0x01
#define ADJD_S311_CAP_MASK 0x0f
#define ADJD_S311_INT_MASK 0x0fff
#define ADJD_S311_DATA_MASK 0x03ff
struct adjd_s311_data {
struct i2c_client *client;
struct {
s16 chans[4];
s64 ts __aligned(8);
} scan;
};
enum adjd_s311_channel_idx {
IDX_RED, IDX_GREEN, IDX_BLUE, IDX_CLEAR
};
#define ADJD_S311_DATA_REG(chan) (ADJD_S311_DATA_RED + (chan) * 2)
#define ADJD_S311_INT_REG(chan) (ADJD_S311_INT_RED + (chan) * 2)
#define ADJD_S311_CAP_REG(chan) (ADJD_S311_CAP_RED + (chan))
static int adjd_s311_req_data(struct iio_dev *indio_dev)
{
struct adjd_s311_data *data = iio_priv(indio_dev);
int tries = 10;
int ret = i2c_smbus_write_byte_data(data->client, ADJD_S311_CTRL,
ADJD_S311_CTRL_GSSR);
if (ret < 0)
return ret;
while (tries--) {
ret = i2c_smbus_read_byte_data(data->client, ADJD_S311_CTRL);
if (ret < 0)
return ret;
if (!(ret & ADJD_S311_CTRL_GSSR))
break;
msleep(20);
}
if (tries < 0) {
dev_err(&data->client->dev,
"adjd_s311_req_data() failed, data not ready\n");
return -EIO;
}
return 0;
}
static int adjd_s311_read_data(struct iio_dev *indio_dev, u8 reg, int *val)
{
struct adjd_s311_data *data = iio_priv(indio_dev);
int ret = adjd_s311_req_data(indio_dev);
if (ret < 0)
return ret;
ret = i2c_smbus_read_word_data(data->client, reg);
if (ret < 0)
return ret;
*val = ret & ADJD_S311_DATA_MASK;
return 0;
}
static irqreturn_t adjd_s311_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct adjd_s311_data *data = iio_priv(indio_dev);
s64 time_ns = iio_get_time_ns(indio_dev);
int i, j = 0;
int ret = adjd_s311_req_data(indio_dev);
if (ret < 0)
goto done;
for_each_set_bit(i, indio_dev->active_scan_mask,
indio_dev->masklength) {
ret = i2c_smbus_read_word_data(data->client,
ADJD_S311_DATA_REG(i));
if (ret < 0)
goto done;
data->scan.chans[j++] = ret & ADJD_S311_DATA_MASK;
}
iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, time_ns);
done:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
#define ADJD_S311_CHANNEL(_color, _scan_idx) { \
.type = IIO_INTENSITY, \
.modified = 1, \
.address = (IDX_##_color), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_HARDWAREGAIN) | \
BIT(IIO_CHAN_INFO_INT_TIME), \
.channel2 = (IIO_MOD_LIGHT_##_color), \
.scan_index = (_scan_idx), \
.scan_type = { \
.sign = 'u', \
.realbits = 10, \
.storagebits = 16, \
.endianness = IIO_CPU, \
}, \
}
static const struct iio_chan_spec adjd_s311_channels[] = {
ADJD_S311_CHANNEL(RED, 0),
ADJD_S311_CHANNEL(GREEN, 1),
ADJD_S311_CHANNEL(BLUE, 2),
ADJD_S311_CHANNEL(CLEAR, 3),
IIO_CHAN_SOFT_TIMESTAMP(4),
};
static int adjd_s311_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct adjd_s311_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = adjd_s311_read_data(indio_dev,
ADJD_S311_DATA_REG(chan->address), val);
if (ret < 0)
return ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_HARDWAREGAIN:
ret = i2c_smbus_read_byte_data(data->client,
ADJD_S311_CAP_REG(chan->address));
if (ret < 0)
return ret;
*val = ret & ADJD_S311_CAP_MASK;
return IIO_VAL_INT;
case IIO_CHAN_INFO_INT_TIME:
ret = i2c_smbus_read_word_data(data->client,
ADJD_S311_INT_REG(chan->address));
if (ret < 0)
return ret;
*val = 0;
/*
* not documented, based on measurement:
* 4095 LSBs correspond to roughly 4 ms
*/
*val2 = ret & ADJD_S311_INT_MASK;
return IIO_VAL_INT_PLUS_MICRO;
}
return -EINVAL;
}
static int adjd_s311_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct adjd_s311_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_HARDWAREGAIN:
if (val < 0 || val > ADJD_S311_CAP_MASK)
return -EINVAL;
return i2c_smbus_write_byte_data(data->client,
ADJD_S311_CAP_REG(chan->address), val);
case IIO_CHAN_INFO_INT_TIME:
if (val != 0 || val2 < 0 || val2 > ADJD_S311_INT_MASK)
return -EINVAL;
return i2c_smbus_write_word_data(data->client,
ADJD_S311_INT_REG(chan->address), val2);
}
return -EINVAL;
}
static const struct iio_info adjd_s311_info = {
.read_raw = adjd_s311_read_raw,
.write_raw = adjd_s311_write_raw,
};
static int adjd_s311_probe(struct i2c_client *client)
{
struct adjd_s311_data *data;
struct iio_dev *indio_dev;
int err;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (indio_dev == NULL)
return -ENOMEM;
data = iio_priv(indio_dev);
data->client = client;
indio_dev->info = &adjd_s311_info;
indio_dev->name = ADJD_S311_DRV_NAME;
indio_dev->channels = adjd_s311_channels;
indio_dev->num_channels = ARRAY_SIZE(adjd_s311_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
err = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
adjd_s311_trigger_handler, NULL);
if (err < 0)
return err;
return devm_iio_device_register(&client->dev, indio_dev);
}
static const struct i2c_device_id adjd_s311_id[] = {
{ "adjd_s311", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adjd_s311_id);
static struct i2c_driver adjd_s311_driver = {
.driver = {
.name = ADJD_S311_DRV_NAME,
},
.probe = adjd_s311_probe,
.id_table = adjd_s311_id,
};
module_i2c_driver(adjd_s311_driver);
MODULE_AUTHOR("Peter Meerwald <[email protected]>");
MODULE_DESCRIPTION("ADJD-S311 color sensor");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/adjd_s311.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* CM3232 Ambient Light Sensor
*
* Copyright (C) 2014-2015 Capella Microsystems Inc.
* Author: Kevin Tsai <[email protected]>
*
* IIO driver for CM3232 (7-bit I2C slave address 0x10).
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/init.h>
/* Registers Address */
#define CM3232_REG_ADDR_CMD 0x00
#define CM3232_REG_ADDR_ALS 0x50
#define CM3232_REG_ADDR_ID 0x53
#define CM3232_CMD_ALS_DISABLE BIT(0)
#define CM3232_CMD_ALS_IT_SHIFT 2
#define CM3232_CMD_ALS_IT_MASK (BIT(2) | BIT(3) | BIT(4))
#define CM3232_CMD_ALS_IT_DEFAULT (0x01 << CM3232_CMD_ALS_IT_SHIFT)
#define CM3232_CMD_ALS_RESET BIT(6)
#define CM3232_CMD_DEFAULT CM3232_CMD_ALS_IT_DEFAULT
#define CM3232_HW_ID 0x32
#define CM3232_CALIBSCALE_DEFAULT 100000
#define CM3232_CALIBSCALE_RESOLUTION 100000
#define CM3232_MLUX_PER_LUX 1000
#define CM3232_MLUX_PER_BIT_DEFAULT 64
#define CM3232_MLUX_PER_BIT_BASE_IT 100000
static const struct {
int val;
int val2;
u8 it;
} cm3232_als_it_scales[] = {
{0, 100000, 0}, /* 0.100000 */
{0, 200000, 1}, /* 0.200000 */
{0, 400000, 2}, /* 0.400000 */
{0, 800000, 3}, /* 0.800000 */
{1, 600000, 4}, /* 1.600000 */
{3, 200000, 5}, /* 3.200000 */
};
struct cm3232_als_info {
u8 regs_cmd_default;
u8 hw_id;
int calibscale;
int mlux_per_bit;
int mlux_per_bit_base_it;
};
static struct cm3232_als_info cm3232_als_info_default = {
.regs_cmd_default = CM3232_CMD_DEFAULT,
.hw_id = CM3232_HW_ID,
.calibscale = CM3232_CALIBSCALE_DEFAULT,
.mlux_per_bit = CM3232_MLUX_PER_BIT_DEFAULT,
.mlux_per_bit_base_it = CM3232_MLUX_PER_BIT_BASE_IT,
};
struct cm3232_chip {
struct i2c_client *client;
struct cm3232_als_info *als_info;
u8 regs_cmd;
u16 regs_als;
};
/**
* cm3232_reg_init() - Initialize CM3232
* @chip: pointer of struct cm3232_chip.
*
* Check and initialize CM3232 ambient light sensor.
*
* Return: 0 for success; otherwise for error code.
*/
static int cm3232_reg_init(struct cm3232_chip *chip)
{
struct i2c_client *client = chip->client;
s32 ret;
chip->als_info = &cm3232_als_info_default;
/* Identify device */
ret = i2c_smbus_read_word_data(client, CM3232_REG_ADDR_ID);
if (ret < 0) {
dev_err(&chip->client->dev, "Error reading addr_id\n");
return ret;
}
if ((ret & 0xFF) != chip->als_info->hw_id)
return -ENODEV;
/* Disable and reset device */
chip->regs_cmd = CM3232_CMD_ALS_DISABLE | CM3232_CMD_ALS_RESET;
ret = i2c_smbus_write_byte_data(client, CM3232_REG_ADDR_CMD,
chip->regs_cmd);
if (ret < 0) {
dev_err(&chip->client->dev, "Error writing reg_cmd\n");
return ret;
}
/* Register default value */
chip->regs_cmd = chip->als_info->regs_cmd_default;
/* Configure register */
ret = i2c_smbus_write_byte_data(client, CM3232_REG_ADDR_CMD,
chip->regs_cmd);
if (ret < 0)
dev_err(&chip->client->dev, "Error writing reg_cmd\n");
return ret;
}
/**
* cm3232_read_als_it() - Get sensor integration time
* @chip: pointer of struct cm3232_chip
* @val: pointer of int to load the integration (sec).
* @val2: pointer of int to load the integration time (microsecond).
*
* Report the current integration time.
*
* Return: IIO_VAL_INT_PLUS_MICRO for success, otherwise -EINVAL.
*/
static int cm3232_read_als_it(struct cm3232_chip *chip, int *val, int *val2)
{
u16 als_it;
int i;
als_it = chip->regs_cmd;
als_it &= CM3232_CMD_ALS_IT_MASK;
als_it >>= CM3232_CMD_ALS_IT_SHIFT;
for (i = 0; i < ARRAY_SIZE(cm3232_als_it_scales); i++) {
if (als_it == cm3232_als_it_scales[i].it) {
*val = cm3232_als_it_scales[i].val;
*val2 = cm3232_als_it_scales[i].val2;
return IIO_VAL_INT_PLUS_MICRO;
}
}
return -EINVAL;
}
/**
* cm3232_write_als_it() - Write sensor integration time
* @chip: pointer of struct cm3232_chip.
* @val: integration time in second.
* @val2: integration time in microsecond.
*
* Convert integration time to sensor value.
*
* Return: i2c_smbus_write_byte_data command return value.
*/
static int cm3232_write_als_it(struct cm3232_chip *chip, int val, int val2)
{
struct i2c_client *client = chip->client;
u16 als_it, cmd;
int i;
s32 ret;
for (i = 0; i < ARRAY_SIZE(cm3232_als_it_scales); i++) {
if (val == cm3232_als_it_scales[i].val &&
val2 == cm3232_als_it_scales[i].val2) {
als_it = cm3232_als_it_scales[i].it;
als_it <<= CM3232_CMD_ALS_IT_SHIFT;
cmd = chip->regs_cmd & ~CM3232_CMD_ALS_IT_MASK;
cmd |= als_it;
ret = i2c_smbus_write_byte_data(client,
CM3232_REG_ADDR_CMD,
cmd);
if (ret < 0)
return ret;
chip->regs_cmd = cmd;
return 0;
}
}
return -EINVAL;
}
/**
* cm3232_get_lux() - report current lux value
* @chip: pointer of struct cm3232_chip.
*
* Convert sensor data to lux. It depends on integration
* time and calibscale variable.
*
* Return: Zero or positive value is lux, otherwise error code.
*/
static int cm3232_get_lux(struct cm3232_chip *chip)
{
struct i2c_client *client = chip->client;
struct cm3232_als_info *als_info = chip->als_info;
int ret;
int val, val2;
int als_it;
u64 lux;
/* Calculate mlux per bit based on als_it */
ret = cm3232_read_als_it(chip, &val, &val2);
if (ret < 0)
return -EINVAL;
als_it = val * 1000000 + val2;
lux = (__force u64)als_info->mlux_per_bit;
lux *= als_info->mlux_per_bit_base_it;
lux = div_u64(lux, als_it);
ret = i2c_smbus_read_word_data(client, CM3232_REG_ADDR_ALS);
if (ret < 0) {
dev_err(&client->dev, "Error reading reg_addr_als\n");
return ret;
}
chip->regs_als = (u16)ret;
lux *= chip->regs_als;
lux *= als_info->calibscale;
lux = div_u64(lux, CM3232_CALIBSCALE_RESOLUTION);
lux = div_u64(lux, CM3232_MLUX_PER_LUX);
if (lux > 0xFFFF)
lux = 0xFFFF;
return (int)lux;
}
static int cm3232_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct cm3232_chip *chip = iio_priv(indio_dev);
struct cm3232_als_info *als_info = chip->als_info;
int ret;
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
ret = cm3232_get_lux(chip);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBSCALE:
*val = als_info->calibscale;
return IIO_VAL_INT;
case IIO_CHAN_INFO_INT_TIME:
return cm3232_read_als_it(chip, val, val2);
}
return -EINVAL;
}
static int cm3232_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct cm3232_chip *chip = iio_priv(indio_dev);
struct cm3232_als_info *als_info = chip->als_info;
switch (mask) {
case IIO_CHAN_INFO_CALIBSCALE:
als_info->calibscale = val;
return 0;
case IIO_CHAN_INFO_INT_TIME:
return cm3232_write_als_it(chip, val, val2);
}
return -EINVAL;
}
/**
* cm3232_get_it_available() - Get available ALS IT value
* @dev: pointer of struct device.
* @attr: pointer of struct device_attribute.
* @buf: pointer of return string buffer.
*
* Display the available integration time in second.
*
* Return: string length.
*/
static ssize_t cm3232_get_it_available(struct device *dev,
struct device_attribute *attr, char *buf)
{
int i, len;
for (i = 0, len = 0; i < ARRAY_SIZE(cm3232_als_it_scales); i++)
len += scnprintf(buf + len, PAGE_SIZE - len, "%u.%06u ",
cm3232_als_it_scales[i].val,
cm3232_als_it_scales[i].val2);
return len + scnprintf(buf + len, PAGE_SIZE - len, "\n");
}
static const struct iio_chan_spec cm3232_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate =
BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
BIT(IIO_CHAN_INFO_INT_TIME),
}
};
static IIO_DEVICE_ATTR(in_illuminance_integration_time_available,
S_IRUGO, cm3232_get_it_available, NULL, 0);
static struct attribute *cm3232_attributes[] = {
&iio_dev_attr_in_illuminance_integration_time_available.dev_attr.attr,
NULL,
};
static const struct attribute_group cm3232_attribute_group = {
.attrs = cm3232_attributes
};
static const struct iio_info cm3232_info = {
.read_raw = &cm3232_read_raw,
.write_raw = &cm3232_write_raw,
.attrs = &cm3232_attribute_group,
};
static int cm3232_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct cm3232_chip *chip;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
if (!indio_dev)
return -ENOMEM;
chip = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
chip->client = client;
indio_dev->channels = cm3232_channels;
indio_dev->num_channels = ARRAY_SIZE(cm3232_channels);
indio_dev->info = &cm3232_info;
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = cm3232_reg_init(chip);
if (ret) {
dev_err(&client->dev,
"%s: register init failed\n",
__func__);
return ret;
}
return iio_device_register(indio_dev);
}
static void cm3232_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
i2c_smbus_write_byte_data(client, CM3232_REG_ADDR_CMD,
CM3232_CMD_ALS_DISABLE);
iio_device_unregister(indio_dev);
}
static const struct i2c_device_id cm3232_id[] = {
{"cm3232", 0},
{}
};
static int cm3232_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct cm3232_chip *chip = iio_priv(indio_dev);
struct i2c_client *client = chip->client;
int ret;
chip->regs_cmd |= CM3232_CMD_ALS_DISABLE;
ret = i2c_smbus_write_byte_data(client, CM3232_REG_ADDR_CMD,
chip->regs_cmd);
return ret;
}
static int cm3232_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct cm3232_chip *chip = iio_priv(indio_dev);
struct i2c_client *client = chip->client;
int ret;
chip->regs_cmd &= ~CM3232_CMD_ALS_DISABLE;
ret = i2c_smbus_write_byte_data(client, CM3232_REG_ADDR_CMD,
chip->regs_cmd | CM3232_CMD_ALS_RESET);
return ret;
}
static DEFINE_SIMPLE_DEV_PM_OPS(cm3232_pm_ops, cm3232_suspend, cm3232_resume);
MODULE_DEVICE_TABLE(i2c, cm3232_id);
static const struct of_device_id cm3232_of_match[] = {
{.compatible = "capella,cm3232"},
{}
};
MODULE_DEVICE_TABLE(of, cm3232_of_match);
static struct i2c_driver cm3232_driver = {
.driver = {
.name = "cm3232",
.of_match_table = cm3232_of_match,
.pm = pm_sleep_ptr(&cm3232_pm_ops),
},
.id_table = cm3232_id,
.probe = cm3232_probe,
.remove = cm3232_remove,
};
module_i2c_driver(cm3232_driver);
MODULE_AUTHOR("Kevin Tsai <[email protected]>");
MODULE_DESCRIPTION("CM3232 ambient light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/cm3232.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* opt3001.c - Texas Instruments OPT3001 Light Sensor
*
* Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Andreas Dannenberg <[email protected]>
* Based on previous work from: Felipe Balbi <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define OPT3001_RESULT 0x00
#define OPT3001_CONFIGURATION 0x01
#define OPT3001_LOW_LIMIT 0x02
#define OPT3001_HIGH_LIMIT 0x03
#define OPT3001_MANUFACTURER_ID 0x7e
#define OPT3001_DEVICE_ID 0x7f
#define OPT3001_CONFIGURATION_RN_MASK (0xf << 12)
#define OPT3001_CONFIGURATION_RN_AUTO (0xc << 12)
#define OPT3001_CONFIGURATION_CT BIT(11)
#define OPT3001_CONFIGURATION_M_MASK (3 << 9)
#define OPT3001_CONFIGURATION_M_SHUTDOWN (0 << 9)
#define OPT3001_CONFIGURATION_M_SINGLE (1 << 9)
#define OPT3001_CONFIGURATION_M_CONTINUOUS (2 << 9) /* also 3 << 9 */
#define OPT3001_CONFIGURATION_OVF BIT(8)
#define OPT3001_CONFIGURATION_CRF BIT(7)
#define OPT3001_CONFIGURATION_FH BIT(6)
#define OPT3001_CONFIGURATION_FL BIT(5)
#define OPT3001_CONFIGURATION_L BIT(4)
#define OPT3001_CONFIGURATION_POL BIT(3)
#define OPT3001_CONFIGURATION_ME BIT(2)
#define OPT3001_CONFIGURATION_FC_MASK (3 << 0)
/* The end-of-conversion enable is located in the low-limit register */
#define OPT3001_LOW_LIMIT_EOC_ENABLE 0xc000
#define OPT3001_REG_EXPONENT(n) ((n) >> 12)
#define OPT3001_REG_MANTISSA(n) ((n) & 0xfff)
#define OPT3001_INT_TIME_LONG 800000
#define OPT3001_INT_TIME_SHORT 100000
/*
* Time to wait for conversion result to be ready. The device datasheet
* sect. 6.5 states results are ready after total integration time plus 3ms.
* This results in worst-case max values of 113ms or 883ms, respectively.
* Add some slack to be on the safe side.
*/
#define OPT3001_RESULT_READY_SHORT 150
#define OPT3001_RESULT_READY_LONG 1000
struct opt3001 {
struct i2c_client *client;
struct device *dev;
struct mutex lock;
bool ok_to_ignore_lock;
bool result_ready;
wait_queue_head_t result_ready_queue;
u16 result;
u32 int_time;
u32 mode;
u16 high_thresh_mantissa;
u16 low_thresh_mantissa;
u8 high_thresh_exp;
u8 low_thresh_exp;
bool use_irq;
};
struct opt3001_scale {
int val;
int val2;
};
static const struct opt3001_scale opt3001_scales[] = {
{
.val = 40,
.val2 = 950000,
},
{
.val = 81,
.val2 = 900000,
},
{
.val = 163,
.val2 = 800000,
},
{
.val = 327,
.val2 = 600000,
},
{
.val = 655,
.val2 = 200000,
},
{
.val = 1310,
.val2 = 400000,
},
{
.val = 2620,
.val2 = 800000,
},
{
.val = 5241,
.val2 = 600000,
},
{
.val = 10483,
.val2 = 200000,
},
{
.val = 20966,
.val2 = 400000,
},
{
.val = 83865,
.val2 = 600000,
},
};
static int opt3001_find_scale(const struct opt3001 *opt, int val,
int val2, u8 *exponent)
{
int i;
for (i = 0; i < ARRAY_SIZE(opt3001_scales); i++) {
const struct opt3001_scale *scale = &opt3001_scales[i];
/*
* Combine the integer and micro parts for comparison
* purposes. Use milli lux precision to avoid 32-bit integer
* overflows.
*/
if ((val * 1000 + val2 / 1000) <=
(scale->val * 1000 + scale->val2 / 1000)) {
*exponent = i;
return 0;
}
}
return -EINVAL;
}
static void opt3001_to_iio_ret(struct opt3001 *opt, u8 exponent,
u16 mantissa, int *val, int *val2)
{
int lux;
lux = 10 * (mantissa << exponent);
*val = lux / 1000;
*val2 = (lux - (*val * 1000)) * 1000;
}
static void opt3001_set_mode(struct opt3001 *opt, u16 *reg, u16 mode)
{
*reg &= ~OPT3001_CONFIGURATION_M_MASK;
*reg |= mode;
opt->mode = mode;
}
static IIO_CONST_ATTR_INT_TIME_AVAIL("0.1 0.8");
static struct attribute *opt3001_attributes[] = {
&iio_const_attr_integration_time_available.dev_attr.attr,
NULL
};
static const struct attribute_group opt3001_attribute_group = {
.attrs = opt3001_attributes,
};
static const struct iio_event_spec opt3001_event_spec[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_ENABLE),
},
};
static const struct iio_chan_spec opt3001_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_INT_TIME),
.event_spec = opt3001_event_spec,
.num_event_specs = ARRAY_SIZE(opt3001_event_spec),
},
IIO_CHAN_SOFT_TIMESTAMP(1),
};
static int opt3001_get_lux(struct opt3001 *opt, int *val, int *val2)
{
int ret;
u16 mantissa;
u16 reg;
u8 exponent;
u16 value;
long timeout;
if (opt->use_irq) {
/*
* Enable the end-of-conversion interrupt mechanism. Note that
* doing so will overwrite the low-level limit value however we
* will restore this value later on.
*/
ret = i2c_smbus_write_word_swapped(opt->client,
OPT3001_LOW_LIMIT,
OPT3001_LOW_LIMIT_EOC_ENABLE);
if (ret < 0) {
dev_err(opt->dev, "failed to write register %02x\n",
OPT3001_LOW_LIMIT);
return ret;
}
/* Allow IRQ to access the device despite lock being set */
opt->ok_to_ignore_lock = true;
}
/* Reset data-ready indicator flag */
opt->result_ready = false;
/* Configure for single-conversion mode and start a new conversion */
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_CONFIGURATION);
goto err;
}
reg = ret;
opt3001_set_mode(opt, ®, OPT3001_CONFIGURATION_M_SINGLE);
ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
reg);
if (ret < 0) {
dev_err(opt->dev, "failed to write register %02x\n",
OPT3001_CONFIGURATION);
goto err;
}
if (opt->use_irq) {
/* Wait for the IRQ to indicate the conversion is complete */
ret = wait_event_timeout(opt->result_ready_queue,
opt->result_ready,
msecs_to_jiffies(OPT3001_RESULT_READY_LONG));
if (ret == 0)
return -ETIMEDOUT;
} else {
/* Sleep for result ready time */
timeout = (opt->int_time == OPT3001_INT_TIME_SHORT) ?
OPT3001_RESULT_READY_SHORT : OPT3001_RESULT_READY_LONG;
msleep(timeout);
/* Check result ready flag */
ret = i2c_smbus_read_word_swapped(opt->client,
OPT3001_CONFIGURATION);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_CONFIGURATION);
goto err;
}
if (!(ret & OPT3001_CONFIGURATION_CRF)) {
ret = -ETIMEDOUT;
goto err;
}
/* Obtain value */
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_RESULT);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_RESULT);
goto err;
}
opt->result = ret;
opt->result_ready = true;
}
err:
if (opt->use_irq)
/* Disallow IRQ to access the device while lock is active */
opt->ok_to_ignore_lock = false;
if (ret < 0)
return ret;
if (opt->use_irq) {
/*
* Disable the end-of-conversion interrupt mechanism by
* restoring the low-level limit value (clearing
* OPT3001_LOW_LIMIT_EOC_ENABLE). Note that selectively clearing
* those enable bits would affect the actual limit value due to
* bit-overlap and therefore can't be done.
*/
value = (opt->low_thresh_exp << 12) | opt->low_thresh_mantissa;
ret = i2c_smbus_write_word_swapped(opt->client,
OPT3001_LOW_LIMIT,
value);
if (ret < 0) {
dev_err(opt->dev, "failed to write register %02x\n",
OPT3001_LOW_LIMIT);
return ret;
}
}
exponent = OPT3001_REG_EXPONENT(opt->result);
mantissa = OPT3001_REG_MANTISSA(opt->result);
opt3001_to_iio_ret(opt, exponent, mantissa, val, val2);
return IIO_VAL_INT_PLUS_MICRO;
}
static int opt3001_get_int_time(struct opt3001 *opt, int *val, int *val2)
{
*val = 0;
*val2 = opt->int_time;
return IIO_VAL_INT_PLUS_MICRO;
}
static int opt3001_set_int_time(struct opt3001 *opt, int time)
{
int ret;
u16 reg;
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_CONFIGURATION);
return ret;
}
reg = ret;
switch (time) {
case OPT3001_INT_TIME_SHORT:
reg &= ~OPT3001_CONFIGURATION_CT;
opt->int_time = OPT3001_INT_TIME_SHORT;
break;
case OPT3001_INT_TIME_LONG:
reg |= OPT3001_CONFIGURATION_CT;
opt->int_time = OPT3001_INT_TIME_LONG;
break;
default:
return -EINVAL;
}
return i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
reg);
}
static int opt3001_read_raw(struct iio_dev *iio,
struct iio_chan_spec const *chan, int *val, int *val2,
long mask)
{
struct opt3001 *opt = iio_priv(iio);
int ret;
if (opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
return -EBUSY;
if (chan->type != IIO_LIGHT)
return -EINVAL;
mutex_lock(&opt->lock);
switch (mask) {
case IIO_CHAN_INFO_PROCESSED:
ret = opt3001_get_lux(opt, val, val2);
break;
case IIO_CHAN_INFO_INT_TIME:
ret = opt3001_get_int_time(opt, val, val2);
break;
default:
ret = -EINVAL;
}
mutex_unlock(&opt->lock);
return ret;
}
static int opt3001_write_raw(struct iio_dev *iio,
struct iio_chan_spec const *chan, int val, int val2,
long mask)
{
struct opt3001 *opt = iio_priv(iio);
int ret;
if (opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
return -EBUSY;
if (chan->type != IIO_LIGHT)
return -EINVAL;
if (mask != IIO_CHAN_INFO_INT_TIME)
return -EINVAL;
if (val != 0)
return -EINVAL;
mutex_lock(&opt->lock);
ret = opt3001_set_int_time(opt, val2);
mutex_unlock(&opt->lock);
return ret;
}
static int opt3001_read_event_value(struct iio_dev *iio,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info,
int *val, int *val2)
{
struct opt3001 *opt = iio_priv(iio);
int ret = IIO_VAL_INT_PLUS_MICRO;
mutex_lock(&opt->lock);
switch (dir) {
case IIO_EV_DIR_RISING:
opt3001_to_iio_ret(opt, opt->high_thresh_exp,
opt->high_thresh_mantissa, val, val2);
break;
case IIO_EV_DIR_FALLING:
opt3001_to_iio_ret(opt, opt->low_thresh_exp,
opt->low_thresh_mantissa, val, val2);
break;
default:
ret = -EINVAL;
}
mutex_unlock(&opt->lock);
return ret;
}
static int opt3001_write_event_value(struct iio_dev *iio,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, enum iio_event_info info,
int val, int val2)
{
struct opt3001 *opt = iio_priv(iio);
int ret;
u16 mantissa;
u16 value;
u16 reg;
u8 exponent;
if (val < 0)
return -EINVAL;
mutex_lock(&opt->lock);
ret = opt3001_find_scale(opt, val, val2, &exponent);
if (ret < 0) {
dev_err(opt->dev, "can't find scale for %d.%06u\n", val, val2);
goto err;
}
mantissa = (((val * 1000) + (val2 / 1000)) / 10) >> exponent;
value = (exponent << 12) | mantissa;
switch (dir) {
case IIO_EV_DIR_RISING:
reg = OPT3001_HIGH_LIMIT;
opt->high_thresh_mantissa = mantissa;
opt->high_thresh_exp = exponent;
break;
case IIO_EV_DIR_FALLING:
reg = OPT3001_LOW_LIMIT;
opt->low_thresh_mantissa = mantissa;
opt->low_thresh_exp = exponent;
break;
default:
ret = -EINVAL;
goto err;
}
ret = i2c_smbus_write_word_swapped(opt->client, reg, value);
if (ret < 0) {
dev_err(opt->dev, "failed to write register %02x\n", reg);
goto err;
}
err:
mutex_unlock(&opt->lock);
return ret;
}
static int opt3001_read_event_config(struct iio_dev *iio,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir)
{
struct opt3001 *opt = iio_priv(iio);
return opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS;
}
static int opt3001_write_event_config(struct iio_dev *iio,
const struct iio_chan_spec *chan, enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct opt3001 *opt = iio_priv(iio);
int ret;
u16 mode;
u16 reg;
if (state && opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
return 0;
if (!state && opt->mode == OPT3001_CONFIGURATION_M_SHUTDOWN)
return 0;
mutex_lock(&opt->lock);
mode = state ? OPT3001_CONFIGURATION_M_CONTINUOUS
: OPT3001_CONFIGURATION_M_SHUTDOWN;
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_CONFIGURATION);
goto err;
}
reg = ret;
opt3001_set_mode(opt, ®, mode);
ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
reg);
if (ret < 0) {
dev_err(opt->dev, "failed to write register %02x\n",
OPT3001_CONFIGURATION);
goto err;
}
err:
mutex_unlock(&opt->lock);
return ret;
}
static const struct iio_info opt3001_info = {
.attrs = &opt3001_attribute_group,
.read_raw = opt3001_read_raw,
.write_raw = opt3001_write_raw,
.read_event_value = opt3001_read_event_value,
.write_event_value = opt3001_write_event_value,
.read_event_config = opt3001_read_event_config,
.write_event_config = opt3001_write_event_config,
};
static int opt3001_read_id(struct opt3001 *opt)
{
char manufacturer[2];
u16 device_id;
int ret;
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_MANUFACTURER_ID);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_MANUFACTURER_ID);
return ret;
}
manufacturer[0] = ret >> 8;
manufacturer[1] = ret & 0xff;
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_DEVICE_ID);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_DEVICE_ID);
return ret;
}
device_id = ret;
dev_info(opt->dev, "Found %c%c OPT%04x\n", manufacturer[0],
manufacturer[1], device_id);
return 0;
}
static int opt3001_configure(struct opt3001 *opt)
{
int ret;
u16 reg;
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_CONFIGURATION);
return ret;
}
reg = ret;
/* Enable automatic full-scale setting mode */
reg &= ~OPT3001_CONFIGURATION_RN_MASK;
reg |= OPT3001_CONFIGURATION_RN_AUTO;
/* Reflect status of the device's integration time setting */
if (reg & OPT3001_CONFIGURATION_CT)
opt->int_time = OPT3001_INT_TIME_LONG;
else
opt->int_time = OPT3001_INT_TIME_SHORT;
/* Ensure device is in shutdown initially */
opt3001_set_mode(opt, ®, OPT3001_CONFIGURATION_M_SHUTDOWN);
/* Configure for latched window-style comparison operation */
reg |= OPT3001_CONFIGURATION_L;
reg &= ~OPT3001_CONFIGURATION_POL;
reg &= ~OPT3001_CONFIGURATION_ME;
reg &= ~OPT3001_CONFIGURATION_FC_MASK;
ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
reg);
if (ret < 0) {
dev_err(opt->dev, "failed to write register %02x\n",
OPT3001_CONFIGURATION);
return ret;
}
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_LOW_LIMIT);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_LOW_LIMIT);
return ret;
}
opt->low_thresh_mantissa = OPT3001_REG_MANTISSA(ret);
opt->low_thresh_exp = OPT3001_REG_EXPONENT(ret);
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_HIGH_LIMIT);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_HIGH_LIMIT);
return ret;
}
opt->high_thresh_mantissa = OPT3001_REG_MANTISSA(ret);
opt->high_thresh_exp = OPT3001_REG_EXPONENT(ret);
return 0;
}
static irqreturn_t opt3001_irq(int irq, void *_iio)
{
struct iio_dev *iio = _iio;
struct opt3001 *opt = iio_priv(iio);
int ret;
bool wake_result_ready_queue = false;
if (!opt->ok_to_ignore_lock)
mutex_lock(&opt->lock);
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_CONFIGURATION);
goto out;
}
if ((ret & OPT3001_CONFIGURATION_M_MASK) ==
OPT3001_CONFIGURATION_M_CONTINUOUS) {
if (ret & OPT3001_CONFIGURATION_FH)
iio_push_event(iio,
IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
iio_get_time_ns(iio));
if (ret & OPT3001_CONFIGURATION_FL)
iio_push_event(iio,
IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
iio_get_time_ns(iio));
} else if (ret & OPT3001_CONFIGURATION_CRF) {
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_RESULT);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_RESULT);
goto out;
}
opt->result = ret;
opt->result_ready = true;
wake_result_ready_queue = true;
}
out:
if (!opt->ok_to_ignore_lock)
mutex_unlock(&opt->lock);
if (wake_result_ready_queue)
wake_up(&opt->result_ready_queue);
return IRQ_HANDLED;
}
static int opt3001_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct iio_dev *iio;
struct opt3001 *opt;
int irq = client->irq;
int ret;
iio = devm_iio_device_alloc(dev, sizeof(*opt));
if (!iio)
return -ENOMEM;
opt = iio_priv(iio);
opt->client = client;
opt->dev = dev;
mutex_init(&opt->lock);
init_waitqueue_head(&opt->result_ready_queue);
i2c_set_clientdata(client, iio);
ret = opt3001_read_id(opt);
if (ret)
return ret;
ret = opt3001_configure(opt);
if (ret)
return ret;
iio->name = client->name;
iio->channels = opt3001_channels;
iio->num_channels = ARRAY_SIZE(opt3001_channels);
iio->modes = INDIO_DIRECT_MODE;
iio->info = &opt3001_info;
ret = devm_iio_device_register(dev, iio);
if (ret) {
dev_err(dev, "failed to register IIO device\n");
return ret;
}
/* Make use of INT pin only if valid IRQ no. is given */
if (irq > 0) {
ret = request_threaded_irq(irq, NULL, opt3001_irq,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"opt3001", iio);
if (ret) {
dev_err(dev, "failed to request IRQ #%d\n", irq);
return ret;
}
opt->use_irq = true;
} else {
dev_dbg(opt->dev, "enabling interrupt-less operation\n");
}
return 0;
}
static void opt3001_remove(struct i2c_client *client)
{
struct iio_dev *iio = i2c_get_clientdata(client);
struct opt3001 *opt = iio_priv(iio);
int ret;
u16 reg;
if (opt->use_irq)
free_irq(client->irq, iio);
ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
if (ret < 0) {
dev_err(opt->dev, "failed to read register %02x\n",
OPT3001_CONFIGURATION);
return;
}
reg = ret;
opt3001_set_mode(opt, ®, OPT3001_CONFIGURATION_M_SHUTDOWN);
ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
reg);
if (ret < 0) {
dev_err(opt->dev, "failed to write register %02x\n",
OPT3001_CONFIGURATION);
}
}
static const struct i2c_device_id opt3001_id[] = {
{ "opt3001", 0 },
{ } /* Terminating Entry */
};
MODULE_DEVICE_TABLE(i2c, opt3001_id);
static const struct of_device_id opt3001_of_match[] = {
{ .compatible = "ti,opt3001" },
{ }
};
MODULE_DEVICE_TABLE(of, opt3001_of_match);
static struct i2c_driver opt3001_driver = {
.probe = opt3001_probe,
.remove = opt3001_remove,
.id_table = opt3001_id,
.driver = {
.name = "opt3001",
.of_match_table = opt3001_of_match,
},
};
module_i2c_driver(opt3001_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Andreas Dannenberg <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments OPT3001 Light Sensor Driver");
| linux-master | drivers/iio/light/opt3001.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* LTRF216A Ambient Light Sensor
*
* Copyright (C) 2022 Collabora, Ltd.
* Author: Shreeya Patel <[email protected]>
*
* Copyright (C) 2021 Lite-On Technology Corp (Singapore)
* Author: Shi Zhigang <[email protected]>
*
* IIO driver for LTRF216A (7-bit I2C slave address 0x53).
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/iopoll.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include <asm/unaligned.h>
#define LTRF216A_ALS_RESET_MASK BIT(4)
#define LTRF216A_ALS_DATA_STATUS BIT(3)
#define LTRF216A_ALS_ENABLE_MASK BIT(1)
#define LTRF216A_MAIN_CTRL 0x00
#define LTRF216A_ALS_MEAS_RES 0x04
#define LTRF216A_ALS_GAIN 0x05
#define LTRF216A_PART_ID 0x06
#define LTRF216A_MAIN_STATUS 0x07
#define LTRF216A_ALS_CLEAR_DATA_0 0x0a
#define LTRF216A_ALS_CLEAR_DATA_1 0x0b
#define LTRF216A_ALS_CLEAR_DATA_2 0x0c
#define LTRF216A_ALS_DATA_0 0x0d
#define LTRF216A_ALS_DATA_1 0x0e
#define LTRF216A_ALS_DATA_2 0x0f
#define LTRF216A_INT_CFG 0x19
#define LTRF216A_INT_PST 0x1a
#define LTRF216A_ALS_THRES_UP_0 0x21
#define LTRF216A_ALS_THRES_UP_1 0x22
#define LTRF216A_ALS_THRES_UP_2 0x23
#define LTRF216A_ALS_THRES_LOW_0 0x24
#define LTRF216A_ALS_THRES_LOW_1 0x25
#define LTRF216A_ALS_THRES_LOW_2 0x26
#define LTRF216A_ALS_READ_DATA_DELAY_US 20000
static const int ltrf216a_int_time_available[][2] = {
{ 0, 400000 },
{ 0, 200000 },
{ 0, 100000 },
{ 0, 50000 },
{ 0, 25000 },
};
static const int ltrf216a_int_time_reg[][2] = {
{ 400, 0x03 },
{ 200, 0x13 },
{ 100, 0x22 },
{ 50, 0x31 },
{ 25, 0x40 },
};
/*
* Window Factor is needed when the device is under Window glass
* with coated tinted ink. This is to compensate for the light loss
* due to the lower transmission rate of the window glass and helps
* in calculating lux.
*/
#define LTRF216A_WIN_FAC 1
struct ltrf216a_data {
struct regmap *regmap;
struct i2c_client *client;
u32 int_time;
u16 int_time_fac;
u8 als_gain_fac;
/*
* Protects regmap accesses and makes sure integration time
* remains constant during the measurement of lux.
*/
struct mutex lock;
};
static const struct iio_chan_spec ltrf216a_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_INT_TIME),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_INT_TIME),
},
};
static void ltrf216a_reset(struct iio_dev *indio_dev)
{
struct ltrf216a_data *data = iio_priv(indio_dev);
/* reset sensor, chip fails to respond to this, so ignore any errors */
regmap_write(data->regmap, LTRF216A_MAIN_CTRL, LTRF216A_ALS_RESET_MASK);
/* reset time */
usleep_range(1000, 2000);
}
static int ltrf216a_enable(struct iio_dev *indio_dev)
{
struct ltrf216a_data *data = iio_priv(indio_dev);
struct device *dev = &data->client->dev;
int ret;
/* enable sensor */
ret = regmap_set_bits(data->regmap,
LTRF216A_MAIN_CTRL, LTRF216A_ALS_ENABLE_MASK);
if (ret) {
dev_err(dev, "failed to enable sensor: %d\n", ret);
return ret;
}
/* sleep for one integration cycle after enabling the device */
msleep(ltrf216a_int_time_reg[0][0]);
return 0;
}
static int ltrf216a_disable(struct iio_dev *indio_dev)
{
struct ltrf216a_data *data = iio_priv(indio_dev);
struct device *dev = &data->client->dev;
int ret;
ret = regmap_write(data->regmap, LTRF216A_MAIN_CTRL, 0);
if (ret)
dev_err(dev, "failed to disable sensor: %d\n", ret);
return ret;
}
static void ltrf216a_cleanup(void *data)
{
struct iio_dev *indio_dev = data;
ltrf216a_disable(indio_dev);
}
static int ltrf216a_set_int_time(struct ltrf216a_data *data, int itime)
{
struct device *dev = &data->client->dev;
unsigned int i;
u8 reg_val;
int ret;
for (i = 0; i < ARRAY_SIZE(ltrf216a_int_time_available); i++) {
if (ltrf216a_int_time_available[i][1] == itime)
break;
}
if (i == ARRAY_SIZE(ltrf216a_int_time_available))
return -EINVAL;
reg_val = ltrf216a_int_time_reg[i][1];
ret = regmap_write(data->regmap, LTRF216A_ALS_MEAS_RES, reg_val);
if (ret) {
dev_err(dev, "failed to set integration time: %d\n", ret);
return ret;
}
data->int_time_fac = ltrf216a_int_time_reg[i][0];
data->int_time = itime;
return 0;
}
static int ltrf216a_get_int_time(struct ltrf216a_data *data,
int *val, int *val2)
{
*val = 0;
*val2 = data->int_time;
return IIO_VAL_INT_PLUS_MICRO;
}
static int ltrf216a_set_power_state(struct ltrf216a_data *data, bool on)
{
struct device *dev = &data->client->dev;
int ret = 0;
if (on) {
ret = pm_runtime_resume_and_get(dev);
if (ret) {
dev_err(dev, "failed to resume runtime PM: %d\n", ret);
return ret;
}
} else {
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
}
return ret;
}
static int ltrf216a_read_data(struct ltrf216a_data *data, u8 addr)
{
struct device *dev = &data->client->dev;
int ret, val;
u8 buf[3];
ret = regmap_read_poll_timeout(data->regmap, LTRF216A_MAIN_STATUS,
val, val & LTRF216A_ALS_DATA_STATUS,
LTRF216A_ALS_READ_DATA_DELAY_US,
LTRF216A_ALS_READ_DATA_DELAY_US * 50);
if (ret) {
dev_err(dev, "failed to wait for measurement data: %d\n", ret);
return ret;
}
ret = regmap_bulk_read(data->regmap, addr, buf, sizeof(buf));
if (ret) {
dev_err(dev, "failed to read measurement data: %d\n", ret);
return ret;
}
return get_unaligned_le24(&buf[0]);
}
static int ltrf216a_get_lux(struct ltrf216a_data *data)
{
int ret, greendata;
u64 lux, div;
ret = ltrf216a_set_power_state(data, true);
if (ret)
return ret;
greendata = ltrf216a_read_data(data, LTRF216A_ALS_DATA_0);
if (greendata < 0)
return greendata;
ltrf216a_set_power_state(data, false);
lux = greendata * 45 * LTRF216A_WIN_FAC * 100;
div = data->als_gain_fac * data->int_time_fac * 100;
return div_u64(lux, div);
}
static int ltrf216a_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct ltrf216a_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = ltrf216a_set_power_state(data, true);
if (ret)
return ret;
mutex_lock(&data->lock);
ret = ltrf216a_read_data(data, LTRF216A_ALS_DATA_0);
mutex_unlock(&data->lock);
ltrf216a_set_power_state(data, false);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_PROCESSED:
mutex_lock(&data->lock);
ret = ltrf216a_get_lux(data);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
*val = ret;
return IIO_VAL_INT;
case IIO_CHAN_INFO_INT_TIME:
mutex_lock(&data->lock);
ret = ltrf216a_get_int_time(data, val, val2);
mutex_unlock(&data->lock);
return ret;
default:
return -EINVAL;
}
}
static int ltrf216a_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct ltrf216a_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
if (val != 0)
return -EINVAL;
mutex_lock(&data->lock);
ret = ltrf216a_set_int_time(data, val2);
mutex_unlock(&data->lock);
return ret;
default:
return -EINVAL;
}
}
static int ltrf216a_read_available(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
switch (mask) {
case IIO_CHAN_INFO_INT_TIME:
*length = ARRAY_SIZE(ltrf216a_int_time_available) * 2;
*vals = (const int *)ltrf216a_int_time_available;
*type = IIO_VAL_INT_PLUS_MICRO;
return IIO_AVAIL_LIST;
default:
return -EINVAL;
}
}
static const struct iio_info ltrf216a_info = {
.read_raw = ltrf216a_read_raw,
.write_raw = ltrf216a_write_raw,
.read_avail = ltrf216a_read_available,
};
static bool ltrf216a_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case LTRF216A_MAIN_CTRL:
case LTRF216A_ALS_MEAS_RES:
case LTRF216A_ALS_GAIN:
case LTRF216A_PART_ID:
case LTRF216A_MAIN_STATUS:
case LTRF216A_ALS_CLEAR_DATA_0:
case LTRF216A_ALS_CLEAR_DATA_1:
case LTRF216A_ALS_CLEAR_DATA_2:
case LTRF216A_ALS_DATA_0:
case LTRF216A_ALS_DATA_1:
case LTRF216A_ALS_DATA_2:
case LTRF216A_INT_CFG:
case LTRF216A_INT_PST:
case LTRF216A_ALS_THRES_UP_0:
case LTRF216A_ALS_THRES_UP_1:
case LTRF216A_ALS_THRES_UP_2:
case LTRF216A_ALS_THRES_LOW_0:
case LTRF216A_ALS_THRES_LOW_1:
case LTRF216A_ALS_THRES_LOW_2:
return true;
default:
return false;
}
}
static bool ltrf216a_writable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case LTRF216A_MAIN_CTRL:
case LTRF216A_ALS_MEAS_RES:
case LTRF216A_ALS_GAIN:
case LTRF216A_INT_CFG:
case LTRF216A_INT_PST:
case LTRF216A_ALS_THRES_UP_0:
case LTRF216A_ALS_THRES_UP_1:
case LTRF216A_ALS_THRES_UP_2:
case LTRF216A_ALS_THRES_LOW_0:
case LTRF216A_ALS_THRES_LOW_1:
case LTRF216A_ALS_THRES_LOW_2:
return true;
default:
return false;
}
}
static bool ltrf216a_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case LTRF216A_MAIN_STATUS:
case LTRF216A_ALS_CLEAR_DATA_0:
case LTRF216A_ALS_CLEAR_DATA_1:
case LTRF216A_ALS_CLEAR_DATA_2:
case LTRF216A_ALS_DATA_0:
case LTRF216A_ALS_DATA_1:
case LTRF216A_ALS_DATA_2:
return true;
default:
return false;
}
}
static bool ltrf216a_precious_reg(struct device *dev, unsigned int reg)
{
return reg == LTRF216A_MAIN_STATUS;
}
static const struct regmap_config ltrf216a_regmap_config = {
.name = "ltrf216a",
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.max_register = LTRF216A_ALS_THRES_LOW_2,
.readable_reg = ltrf216a_readable_reg,
.writeable_reg = ltrf216a_writable_reg,
.volatile_reg = ltrf216a_volatile_reg,
.precious_reg = ltrf216a_precious_reg,
.disable_locking = true,
};
static int ltrf216a_probe(struct i2c_client *client)
{
struct ltrf216a_data *data;
struct iio_dev *indio_dev;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
data = iio_priv(indio_dev);
data->regmap = devm_regmap_init_i2c(client, <rf216a_regmap_config);
if (IS_ERR(data->regmap))
return dev_err_probe(&client->dev, PTR_ERR(data->regmap),
"regmap initialization failed\n");
i2c_set_clientdata(client, indio_dev);
data->client = client;
mutex_init(&data->lock);
indio_dev->info = <rf216a_info;
indio_dev->name = "ltrf216a";
indio_dev->channels = ltrf216a_channels;
indio_dev->num_channels = ARRAY_SIZE(ltrf216a_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = pm_runtime_set_active(&client->dev);
if (ret)
return ret;
/* reset sensor, chip fails to respond to this, so ignore any errors */
ltrf216a_reset(indio_dev);
ret = regmap_reinit_cache(data->regmap, <rf216a_regmap_config);
if (ret)
return dev_err_probe(&client->dev, ret,
"failed to reinit regmap cache\n");
ret = ltrf216a_enable(indio_dev);
if (ret)
return ret;
ret = devm_add_action_or_reset(&client->dev, ltrf216a_cleanup,
indio_dev);
if (ret)
return ret;
ret = devm_pm_runtime_enable(&client->dev);
if (ret)
return dev_err_probe(&client->dev, ret,
"failed to enable runtime PM\n");
pm_runtime_set_autosuspend_delay(&client->dev, 1000);
pm_runtime_use_autosuspend(&client->dev);
data->int_time = 100000;
data->int_time_fac = 100;
data->als_gain_fac = 3;
return devm_iio_device_register(&client->dev, indio_dev);
}
static int ltrf216a_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct ltrf216a_data *data = iio_priv(indio_dev);
int ret;
ret = ltrf216a_disable(indio_dev);
if (ret)
return ret;
regcache_cache_only(data->regmap, true);
return 0;
}
static int ltrf216a_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct ltrf216a_data *data = iio_priv(indio_dev);
int ret;
regcache_cache_only(data->regmap, false);
regcache_mark_dirty(data->regmap);
ret = regcache_sync(data->regmap);
if (ret)
goto cache_only;
ret = ltrf216a_enable(indio_dev);
if (ret)
goto cache_only;
return 0;
cache_only:
regcache_cache_only(data->regmap, true);
return ret;
}
static DEFINE_RUNTIME_DEV_PM_OPS(ltrf216a_pm_ops, ltrf216a_runtime_suspend,
ltrf216a_runtime_resume, NULL);
static const struct i2c_device_id ltrf216a_id[] = {
{ "ltrf216a" },
{}
};
MODULE_DEVICE_TABLE(i2c, ltrf216a_id);
static const struct of_device_id ltrf216a_of_match[] = {
{ .compatible = "liteon,ltrf216a" },
{ .compatible = "ltr,ltrf216a" },
{}
};
MODULE_DEVICE_TABLE(of, ltrf216a_of_match);
static struct i2c_driver ltrf216a_driver = {
.driver = {
.name = "ltrf216a",
.pm = pm_ptr(<rf216a_pm_ops),
.of_match_table = ltrf216a_of_match,
},
.probe = ltrf216a_probe,
.id_table = ltrf216a_id,
};
module_i2c_driver(ltrf216a_driver);
MODULE_AUTHOR("Shreeya Patel <[email protected]>");
MODULE_AUTHOR("Shi Zhigang <[email protected]>");
MODULE_DESCRIPTION("LTRF216A ambient light sensor driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/iio/light/ltrf216a.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* JSA1212 Ambient Light & Proximity Sensor Driver
*
* Copyright (c) 2014, Intel Corporation.
*
* JSA1212 I2C slave address: 0x44(ADDR tied to GND), 0x45(ADDR tied to VDD)
*
* TODO: Interrupt support, thresholds, range support.
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/acpi.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
/* JSA1212 reg address */
#define JSA1212_CONF_REG 0x01
#define JSA1212_INT_REG 0x02
#define JSA1212_PXS_LT_REG 0x03
#define JSA1212_PXS_HT_REG 0x04
#define JSA1212_ALS_TH1_REG 0x05
#define JSA1212_ALS_TH2_REG 0x06
#define JSA1212_ALS_TH3_REG 0x07
#define JSA1212_PXS_DATA_REG 0x08
#define JSA1212_ALS_DT1_REG 0x09
#define JSA1212_ALS_DT2_REG 0x0A
#define JSA1212_ALS_RNG_REG 0x0B
#define JSA1212_MAX_REG 0x0C
/* JSA1212 reg masks */
#define JSA1212_CONF_MASK 0xFF
#define JSA1212_INT_MASK 0xFF
#define JSA1212_PXS_LT_MASK 0xFF
#define JSA1212_PXS_HT_MASK 0xFF
#define JSA1212_ALS_TH1_MASK 0xFF
#define JSA1212_ALS_TH2_LT_MASK 0x0F
#define JSA1212_ALS_TH2_HT_MASK 0xF0
#define JSA1212_ALS_TH3_MASK 0xFF
#define JSA1212_PXS_DATA_MASK 0xFF
#define JSA1212_ALS_DATA_MASK 0x0FFF
#define JSA1212_ALS_DT1_MASK 0xFF
#define JSA1212_ALS_DT2_MASK 0x0F
#define JSA1212_ALS_RNG_MASK 0x07
/* JSA1212 CONF REG bits */
#define JSA1212_CONF_PXS_MASK 0x80
#define JSA1212_CONF_PXS_ENABLE 0x80
#define JSA1212_CONF_PXS_DISABLE 0x00
#define JSA1212_CONF_ALS_MASK 0x04
#define JSA1212_CONF_ALS_ENABLE 0x04
#define JSA1212_CONF_ALS_DISABLE 0x00
#define JSA1212_CONF_IRDR_MASK 0x08
/* Proxmity sensing IRDR current sink settings */
#define JSA1212_CONF_IRDR_200MA 0x08
#define JSA1212_CONF_IRDR_100MA 0x00
#define JSA1212_CONF_PXS_SLP_MASK 0x70
#define JSA1212_CONF_PXS_SLP_0MS 0x70
#define JSA1212_CONF_PXS_SLP_12MS 0x60
#define JSA1212_CONF_PXS_SLP_50MS 0x50
#define JSA1212_CONF_PXS_SLP_75MS 0x40
#define JSA1212_CONF_PXS_SLP_100MS 0x30
#define JSA1212_CONF_PXS_SLP_200MS 0x20
#define JSA1212_CONF_PXS_SLP_400MS 0x10
#define JSA1212_CONF_PXS_SLP_800MS 0x00
/* JSA1212 INT REG bits */
#define JSA1212_INT_CTRL_MASK 0x01
#define JSA1212_INT_CTRL_EITHER 0x00
#define JSA1212_INT_CTRL_BOTH 0x01
#define JSA1212_INT_ALS_PRST_MASK 0x06
#define JSA1212_INT_ALS_PRST_1CONV 0x00
#define JSA1212_INT_ALS_PRST_4CONV 0x02
#define JSA1212_INT_ALS_PRST_8CONV 0x04
#define JSA1212_INT_ALS_PRST_16CONV 0x06
#define JSA1212_INT_ALS_FLAG_MASK 0x08
#define JSA1212_INT_ALS_FLAG_CLR 0x00
#define JSA1212_INT_PXS_PRST_MASK 0x60
#define JSA1212_INT_PXS_PRST_1CONV 0x00
#define JSA1212_INT_PXS_PRST_4CONV 0x20
#define JSA1212_INT_PXS_PRST_8CONV 0x40
#define JSA1212_INT_PXS_PRST_16CONV 0x60
#define JSA1212_INT_PXS_FLAG_MASK 0x80
#define JSA1212_INT_PXS_FLAG_CLR 0x00
/* JSA1212 ALS RNG REG bits */
#define JSA1212_ALS_RNG_0_2048 0x00
#define JSA1212_ALS_RNG_0_1024 0x01
#define JSA1212_ALS_RNG_0_512 0x02
#define JSA1212_ALS_RNG_0_256 0x03
#define JSA1212_ALS_RNG_0_128 0x04
/* JSA1212 INT threshold range */
#define JSA1212_ALS_TH_MIN 0x0000
#define JSA1212_ALS_TH_MAX 0x0FFF
#define JSA1212_PXS_TH_MIN 0x00
#define JSA1212_PXS_TH_MAX 0xFF
#define JSA1212_ALS_DELAY_MS 200
#define JSA1212_PXS_DELAY_MS 100
#define JSA1212_DRIVER_NAME "jsa1212"
#define JSA1212_REGMAP_NAME "jsa1212_regmap"
enum jsa1212_op_mode {
JSA1212_OPMODE_ALS_EN,
JSA1212_OPMODE_PXS_EN,
};
struct jsa1212_data {
struct i2c_client *client;
struct mutex lock;
u8 als_rng_idx;
bool als_en; /* ALS enable status */
bool pxs_en; /* proximity enable status */
struct regmap *regmap;
};
/* ALS range idx to val mapping */
static const int jsa1212_als_range_val[] = {2048, 1024, 512, 256, 128,
128, 128, 128};
/* Enables or disables ALS function based on status */
static int jsa1212_als_enable(struct jsa1212_data *data, u8 status)
{
int ret;
ret = regmap_update_bits(data->regmap, JSA1212_CONF_REG,
JSA1212_CONF_ALS_MASK,
status);
if (ret < 0)
return ret;
data->als_en = !!status;
return 0;
}
/* Enables or disables PXS function based on status */
static int jsa1212_pxs_enable(struct jsa1212_data *data, u8 status)
{
int ret;
ret = regmap_update_bits(data->regmap, JSA1212_CONF_REG,
JSA1212_CONF_PXS_MASK,
status);
if (ret < 0)
return ret;
data->pxs_en = !!status;
return 0;
}
static int jsa1212_read_als_data(struct jsa1212_data *data,
unsigned int *val)
{
int ret;
__le16 als_data;
ret = jsa1212_als_enable(data, JSA1212_CONF_ALS_ENABLE);
if (ret < 0)
return ret;
/* Delay for data output */
msleep(JSA1212_ALS_DELAY_MS);
/* Read 12 bit data */
ret = regmap_bulk_read(data->regmap, JSA1212_ALS_DT1_REG, &als_data, 2);
if (ret < 0) {
dev_err(&data->client->dev, "als data read err\n");
goto als_data_read_err;
}
*val = le16_to_cpu(als_data);
als_data_read_err:
return jsa1212_als_enable(data, JSA1212_CONF_ALS_DISABLE);
}
static int jsa1212_read_pxs_data(struct jsa1212_data *data,
unsigned int *val)
{
int ret;
unsigned int pxs_data;
ret = jsa1212_pxs_enable(data, JSA1212_CONF_PXS_ENABLE);
if (ret < 0)
return ret;
/* Delay for data output */
msleep(JSA1212_PXS_DELAY_MS);
/* Read out all data */
ret = regmap_read(data->regmap, JSA1212_PXS_DATA_REG, &pxs_data);
if (ret < 0) {
dev_err(&data->client->dev, "pxs data read err\n");
goto pxs_data_read_err;
}
*val = pxs_data & JSA1212_PXS_DATA_MASK;
pxs_data_read_err:
return jsa1212_pxs_enable(data, JSA1212_CONF_PXS_DISABLE);
}
static int jsa1212_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
int ret;
struct jsa1212_data *data = iio_priv(indio_dev);
switch (mask) {
case IIO_CHAN_INFO_RAW:
mutex_lock(&data->lock);
switch (chan->type) {
case IIO_LIGHT:
ret = jsa1212_read_als_data(data, val);
break;
case IIO_PROXIMITY:
ret = jsa1212_read_pxs_data(data, val);
break;
default:
ret = -EINVAL;
break;
}
mutex_unlock(&data->lock);
return ret < 0 ? ret : IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_LIGHT:
*val = jsa1212_als_range_val[data->als_rng_idx];
*val2 = BIT(12); /* Max 12 bit value */
return IIO_VAL_FRACTIONAL;
default:
break;
}
break;
default:
break;
}
return -EINVAL;
}
static const struct iio_chan_spec jsa1212_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
},
{
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
}
};
static const struct iio_info jsa1212_info = {
.read_raw = &jsa1212_read_raw,
};
static int jsa1212_chip_init(struct jsa1212_data *data)
{
int ret;
ret = regmap_write(data->regmap, JSA1212_CONF_REG,
(JSA1212_CONF_PXS_SLP_50MS |
JSA1212_CONF_IRDR_200MA));
if (ret < 0)
return ret;
ret = regmap_write(data->regmap, JSA1212_INT_REG,
JSA1212_INT_ALS_PRST_4CONV);
if (ret < 0)
return ret;
data->als_rng_idx = JSA1212_ALS_RNG_0_2048;
return 0;
}
static bool jsa1212_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case JSA1212_PXS_DATA_REG:
case JSA1212_ALS_DT1_REG:
case JSA1212_ALS_DT2_REG:
case JSA1212_INT_REG:
return true;
default:
return false;
}
}
static const struct regmap_config jsa1212_regmap_config = {
.name = JSA1212_REGMAP_NAME,
.reg_bits = 8,
.val_bits = 8,
.max_register = JSA1212_MAX_REG,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = jsa1212_is_volatile_reg,
};
static int jsa1212_probe(struct i2c_client *client)
{
struct jsa1212_data *data;
struct iio_dev *indio_dev;
struct regmap *regmap;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
regmap = devm_regmap_init_i2c(client, &jsa1212_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "Regmap initialization failed.\n");
return PTR_ERR(regmap);
}
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->regmap = regmap;
mutex_init(&data->lock);
ret = jsa1212_chip_init(data);
if (ret < 0)
return ret;
indio_dev->channels = jsa1212_channels;
indio_dev->num_channels = ARRAY_SIZE(jsa1212_channels);
indio_dev->name = JSA1212_DRIVER_NAME;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &jsa1212_info;
ret = iio_device_register(indio_dev);
if (ret < 0)
dev_err(&client->dev, "%s: register device failed\n", __func__);
return ret;
}
/* power off the device */
static int jsa1212_power_off(struct jsa1212_data *data)
{
int ret;
mutex_lock(&data->lock);
ret = regmap_update_bits(data->regmap, JSA1212_CONF_REG,
JSA1212_CONF_ALS_MASK |
JSA1212_CONF_PXS_MASK,
JSA1212_CONF_ALS_DISABLE |
JSA1212_CONF_PXS_DISABLE);
if (ret < 0)
dev_err(&data->client->dev, "power off cmd failed\n");
mutex_unlock(&data->lock);
return ret;
}
static void jsa1212_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
struct jsa1212_data *data = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
jsa1212_power_off(data);
}
static int jsa1212_suspend(struct device *dev)
{
struct jsa1212_data *data;
data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
return jsa1212_power_off(data);
}
static int jsa1212_resume(struct device *dev)
{
int ret = 0;
struct jsa1212_data *data;
data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
mutex_lock(&data->lock);
if (data->als_en) {
ret = jsa1212_als_enable(data, JSA1212_CONF_ALS_ENABLE);
if (ret < 0) {
dev_err(dev, "als resume failed\n");
goto unlock_and_ret;
}
}
if (data->pxs_en) {
ret = jsa1212_pxs_enable(data, JSA1212_CONF_PXS_ENABLE);
if (ret < 0)
dev_err(dev, "pxs resume failed\n");
}
unlock_and_ret:
mutex_unlock(&data->lock);
return ret;
}
static DEFINE_SIMPLE_DEV_PM_OPS(jsa1212_pm_ops, jsa1212_suspend,
jsa1212_resume);
static const struct acpi_device_id jsa1212_acpi_match[] = {
{"JSA1212", 0},
{ },
};
MODULE_DEVICE_TABLE(acpi, jsa1212_acpi_match);
static const struct i2c_device_id jsa1212_id[] = {
{ JSA1212_DRIVER_NAME, 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, jsa1212_id);
static struct i2c_driver jsa1212_driver = {
.driver = {
.name = JSA1212_DRIVER_NAME,
.pm = pm_sleep_ptr(&jsa1212_pm_ops),
.acpi_match_table = ACPI_PTR(jsa1212_acpi_match),
},
.probe = jsa1212_probe,
.remove = jsa1212_remove,
.id_table = jsa1212_id,
};
module_i2c_driver(jsa1212_driver);
MODULE_AUTHOR("Sathya Kuppuswamy <[email protected]>");
MODULE_DESCRIPTION("JSA1212 proximity/ambient light sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/jsa1212.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* RPR-0521 ROHM Ambient Light and Proximity Sensor
*
* Copyright (c) 2015, Intel Corporation.
*
* IIO driver for RPR-0521RS (7-bit I2C slave address 0x38).
*
* TODO: illuminance channel
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/delay.h>
#include <linux/acpi.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/sysfs.h>
#include <linux/pm_runtime.h>
#define RPR0521_REG_SYSTEM_CTRL 0x40
#define RPR0521_REG_MODE_CTRL 0x41
#define RPR0521_REG_ALS_CTRL 0x42
#define RPR0521_REG_PXS_CTRL 0x43
#define RPR0521_REG_PXS_DATA 0x44 /* 16-bit, little endian */
#define RPR0521_REG_ALS_DATA0 0x46 /* 16-bit, little endian */
#define RPR0521_REG_ALS_DATA1 0x48 /* 16-bit, little endian */
#define RPR0521_REG_INTERRUPT 0x4A
#define RPR0521_REG_PS_OFFSET_LSB 0x53
#define RPR0521_REG_ID 0x92
#define RPR0521_MODE_ALS_MASK BIT(7)
#define RPR0521_MODE_PXS_MASK BIT(6)
#define RPR0521_MODE_MEAS_TIME_MASK GENMASK(3, 0)
#define RPR0521_ALS_DATA0_GAIN_MASK GENMASK(5, 4)
#define RPR0521_ALS_DATA0_GAIN_SHIFT 4
#define RPR0521_ALS_DATA1_GAIN_MASK GENMASK(3, 2)
#define RPR0521_ALS_DATA1_GAIN_SHIFT 2
#define RPR0521_PXS_GAIN_MASK GENMASK(5, 4)
#define RPR0521_PXS_GAIN_SHIFT 4
#define RPR0521_PXS_PERSISTENCE_MASK GENMASK(3, 0)
#define RPR0521_INTERRUPT_INT_TRIG_PS_MASK BIT(0)
#define RPR0521_INTERRUPT_INT_TRIG_ALS_MASK BIT(1)
#define RPR0521_INTERRUPT_INT_REASSERT_MASK BIT(3)
#define RPR0521_INTERRUPT_ALS_INT_STATUS_MASK BIT(6)
#define RPR0521_INTERRUPT_PS_INT_STATUS_MASK BIT(7)
#define RPR0521_MODE_ALS_ENABLE BIT(7)
#define RPR0521_MODE_ALS_DISABLE 0x00
#define RPR0521_MODE_PXS_ENABLE BIT(6)
#define RPR0521_MODE_PXS_DISABLE 0x00
#define RPR0521_PXS_PERSISTENCE_DRDY 0x00
#define RPR0521_INTERRUPT_INT_TRIG_PS_ENABLE BIT(0)
#define RPR0521_INTERRUPT_INT_TRIG_PS_DISABLE 0x00
#define RPR0521_INTERRUPT_INT_TRIG_ALS_ENABLE BIT(1)
#define RPR0521_INTERRUPT_INT_TRIG_ALS_DISABLE 0x00
#define RPR0521_INTERRUPT_INT_REASSERT_ENABLE BIT(3)
#define RPR0521_INTERRUPT_INT_REASSERT_DISABLE 0x00
#define RPR0521_MANUFACT_ID 0xE0
#define RPR0521_DEFAULT_MEAS_TIME 0x06 /* ALS - 100ms, PXS - 100ms */
#define RPR0521_DRV_NAME "RPR0521"
#define RPR0521_IRQ_NAME "rpr0521_event"
#define RPR0521_REGMAP_NAME "rpr0521_regmap"
#define RPR0521_SLEEP_DELAY_MS 2000
#define RPR0521_ALS_SCALE_AVAIL "0.007812 0.015625 0.5 1"
#define RPR0521_PXS_SCALE_AVAIL "0.125 0.5 1"
struct rpr0521_gain {
int scale;
int uscale;
};
static const struct rpr0521_gain rpr0521_als_gain[4] = {
{1, 0}, /* x1 */
{0, 500000}, /* x2 */
{0, 15625}, /* x64 */
{0, 7812}, /* x128 */
};
static const struct rpr0521_gain rpr0521_pxs_gain[3] = {
{1, 0}, /* x1 */
{0, 500000}, /* x2 */
{0, 125000}, /* x4 */
};
enum rpr0521_channel {
RPR0521_CHAN_PXS,
RPR0521_CHAN_ALS_DATA0,
RPR0521_CHAN_ALS_DATA1,
};
struct rpr0521_reg_desc {
u8 address;
u8 device_mask;
};
static const struct rpr0521_reg_desc rpr0521_data_reg[] = {
[RPR0521_CHAN_PXS] = {
.address = RPR0521_REG_PXS_DATA,
.device_mask = RPR0521_MODE_PXS_MASK,
},
[RPR0521_CHAN_ALS_DATA0] = {
.address = RPR0521_REG_ALS_DATA0,
.device_mask = RPR0521_MODE_ALS_MASK,
},
[RPR0521_CHAN_ALS_DATA1] = {
.address = RPR0521_REG_ALS_DATA1,
.device_mask = RPR0521_MODE_ALS_MASK,
},
};
static const struct rpr0521_gain_info {
u8 reg;
u8 mask;
u8 shift;
const struct rpr0521_gain *gain;
int size;
} rpr0521_gain[] = {
[RPR0521_CHAN_PXS] = {
.reg = RPR0521_REG_PXS_CTRL,
.mask = RPR0521_PXS_GAIN_MASK,
.shift = RPR0521_PXS_GAIN_SHIFT,
.gain = rpr0521_pxs_gain,
.size = ARRAY_SIZE(rpr0521_pxs_gain),
},
[RPR0521_CHAN_ALS_DATA0] = {
.reg = RPR0521_REG_ALS_CTRL,
.mask = RPR0521_ALS_DATA0_GAIN_MASK,
.shift = RPR0521_ALS_DATA0_GAIN_SHIFT,
.gain = rpr0521_als_gain,
.size = ARRAY_SIZE(rpr0521_als_gain),
},
[RPR0521_CHAN_ALS_DATA1] = {
.reg = RPR0521_REG_ALS_CTRL,
.mask = RPR0521_ALS_DATA1_GAIN_MASK,
.shift = RPR0521_ALS_DATA1_GAIN_SHIFT,
.gain = rpr0521_als_gain,
.size = ARRAY_SIZE(rpr0521_als_gain),
},
};
struct rpr0521_samp_freq {
int als_hz;
int als_uhz;
int pxs_hz;
int pxs_uhz;
};
static const struct rpr0521_samp_freq rpr0521_samp_freq_i[13] = {
/* {ALS, PXS}, W==currently writable option */
{0, 0, 0, 0}, /* W0000, 0=standby */
{0, 0, 100, 0}, /* 0001 */
{0, 0, 25, 0}, /* 0010 */
{0, 0, 10, 0}, /* 0011 */
{0, 0, 2, 500000}, /* 0100 */
{10, 0, 20, 0}, /* 0101 */
{10, 0, 10, 0}, /* W0110 */
{10, 0, 2, 500000}, /* 0111 */
{2, 500000, 20, 0}, /* 1000, measurement 100ms, sleep 300ms */
{2, 500000, 10, 0}, /* 1001, measurement 100ms, sleep 300ms */
{2, 500000, 0, 0}, /* 1010, high sensitivity mode */
{2, 500000, 2, 500000}, /* W1011, high sensitivity mode */
{20, 0, 20, 0} /* 1100, ALS_data x 0.5, see specification P.18 */
};
struct rpr0521_data {
struct i2c_client *client;
/* protect device params updates (e.g state, gain) */
struct mutex lock;
/* device active status */
bool als_dev_en;
bool pxs_dev_en;
struct iio_trigger *drdy_trigger0;
s64 irq_timestamp;
/* optimize runtime pm ops - enable/disable device only if needed */
bool als_ps_need_en;
bool pxs_ps_need_en;
bool als_need_dis;
bool pxs_need_dis;
struct regmap *regmap;
/*
* Ensure correct naturally aligned timestamp.
* Note that the read will put garbage data into
* the padding but this should not be a problem
*/
struct {
__le16 channels[3];
u8 garbage;
s64 ts __aligned(8);
} scan;
};
static IIO_CONST_ATTR(in_intensity_scale_available, RPR0521_ALS_SCALE_AVAIL);
static IIO_CONST_ATTR(in_proximity_scale_available, RPR0521_PXS_SCALE_AVAIL);
/*
* Start with easy freq first, whole table of freq combinations is more
* complicated.
*/
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("2.5 10");
static struct attribute *rpr0521_attributes[] = {
&iio_const_attr_in_intensity_scale_available.dev_attr.attr,
&iio_const_attr_in_proximity_scale_available.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL,
};
static const struct attribute_group rpr0521_attribute_group = {
.attrs = rpr0521_attributes,
};
/* Order of the channel data in buffer */
enum rpr0521_scan_index_order {
RPR0521_CHAN_INDEX_PXS,
RPR0521_CHAN_INDEX_BOTH,
RPR0521_CHAN_INDEX_IR,
};
static const unsigned long rpr0521_available_scan_masks[] = {
BIT(RPR0521_CHAN_INDEX_PXS) | BIT(RPR0521_CHAN_INDEX_BOTH) |
BIT(RPR0521_CHAN_INDEX_IR),
0
};
static const struct iio_chan_spec rpr0521_channels[] = {
{
.type = IIO_PROXIMITY,
.address = RPR0521_CHAN_PXS,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.scan_index = RPR0521_CHAN_INDEX_PXS,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_LE,
},
},
{
.type = IIO_INTENSITY,
.modified = 1,
.address = RPR0521_CHAN_ALS_DATA0,
.channel2 = IIO_MOD_LIGHT_BOTH,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.scan_index = RPR0521_CHAN_INDEX_BOTH,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_LE,
},
},
{
.type = IIO_INTENSITY,
.modified = 1,
.address = RPR0521_CHAN_ALS_DATA1,
.channel2 = IIO_MOD_LIGHT_IR,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SCALE),
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
.scan_index = RPR0521_CHAN_INDEX_IR,
.scan_type = {
.sign = 'u',
.realbits = 16,
.storagebits = 16,
.endianness = IIO_LE,
},
},
};
static int rpr0521_als_enable(struct rpr0521_data *data, u8 status)
{
int ret;
ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
RPR0521_MODE_ALS_MASK,
status);
if (ret < 0)
return ret;
if (status & RPR0521_MODE_ALS_MASK)
data->als_dev_en = true;
else
data->als_dev_en = false;
return 0;
}
static int rpr0521_pxs_enable(struct rpr0521_data *data, u8 status)
{
int ret;
ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
RPR0521_MODE_PXS_MASK,
status);
if (ret < 0)
return ret;
if (status & RPR0521_MODE_PXS_MASK)
data->pxs_dev_en = true;
else
data->pxs_dev_en = false;
return 0;
}
/**
* rpr0521_set_power_state - handles runtime PM state and sensors enabled status
*
* @data: rpr0521 device private data
* @on: state to be set for devices in @device_mask
* @device_mask: bitmask specifying for which device we need to update @on state
*
* Calls for this function must be balanced so that each ON should have matching
* OFF. Otherwise pm usage_count gets out of sync.
*/
static int rpr0521_set_power_state(struct rpr0521_data *data, bool on,
u8 device_mask)
{
#ifdef CONFIG_PM
int ret;
if (device_mask & RPR0521_MODE_ALS_MASK) {
data->als_ps_need_en = on;
data->als_need_dis = !on;
}
if (device_mask & RPR0521_MODE_PXS_MASK) {
data->pxs_ps_need_en = on;
data->pxs_need_dis = !on;
}
/*
* On: _resume() is called only when we are suspended
* Off: _suspend() is called after delay if _resume() is not
* called before that.
* Note: If either measurement is re-enabled before _suspend(),
* both stay enabled until _suspend().
*/
if (on) {
ret = pm_runtime_resume_and_get(&data->client->dev);
} else {
pm_runtime_mark_last_busy(&data->client->dev);
ret = pm_runtime_put_autosuspend(&data->client->dev);
}
if (ret < 0) {
dev_err(&data->client->dev,
"Failed: rpr0521_set_power_state for %d, ret %d\n",
on, ret);
return ret;
}
if (on) {
/* If _resume() was not called, enable measurement now. */
if (data->als_ps_need_en) {
ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE);
if (ret)
return ret;
data->als_ps_need_en = false;
}
if (data->pxs_ps_need_en) {
ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE);
if (ret)
return ret;
data->pxs_ps_need_en = false;
}
}
#endif
return 0;
}
/* Interrupt register tells if this sensor caused the interrupt or not. */
static inline bool rpr0521_is_triggered(struct rpr0521_data *data)
{
int ret;
int reg;
ret = regmap_read(data->regmap, RPR0521_REG_INTERRUPT, ®);
if (ret < 0)
return false; /* Reg read failed. */
if (reg &
(RPR0521_INTERRUPT_ALS_INT_STATUS_MASK |
RPR0521_INTERRUPT_PS_INT_STATUS_MASK))
return true;
else
return false; /* Int not from this sensor. */
}
/* IRQ to trigger handler */
static irqreturn_t rpr0521_drdy_irq_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct rpr0521_data *data = iio_priv(indio_dev);
data->irq_timestamp = iio_get_time_ns(indio_dev);
/*
* We need to wake the thread to read the interrupt reg. It
* is not possible to do that here because regmap_read takes a
* mutex.
*/
return IRQ_WAKE_THREAD;
}
static irqreturn_t rpr0521_drdy_irq_thread(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct rpr0521_data *data = iio_priv(indio_dev);
if (rpr0521_is_triggered(data)) {
iio_trigger_poll_nested(data->drdy_trigger0);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static irqreturn_t rpr0521_trigger_consumer_store_time(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
/* Other trigger polls store time here. */
if (!iio_trigger_using_own(indio_dev))
pf->timestamp = iio_get_time_ns(indio_dev);
return IRQ_WAKE_THREAD;
}
static irqreturn_t rpr0521_trigger_consumer_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct rpr0521_data *data = iio_priv(indio_dev);
int err;
/* Use irq timestamp when reasonable. */
if (iio_trigger_using_own(indio_dev) && data->irq_timestamp) {
pf->timestamp = data->irq_timestamp;
data->irq_timestamp = 0;
}
/* Other chained trigger polls get timestamp only here. */
if (!pf->timestamp)
pf->timestamp = iio_get_time_ns(indio_dev);
err = regmap_bulk_read(data->regmap, RPR0521_REG_PXS_DATA,
data->scan.channels,
(3 * 2) + 1); /* 3 * 16-bit + (discarded) int clear reg. */
if (!err)
iio_push_to_buffers_with_timestamp(indio_dev,
&data->scan, pf->timestamp);
else
dev_err(&data->client->dev,
"Trigger consumer can't read from sensor.\n");
pf->timestamp = 0;
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int rpr0521_write_int_enable(struct rpr0521_data *data)
{
int err;
/* Interrupt after each measurement */
err = regmap_update_bits(data->regmap, RPR0521_REG_PXS_CTRL,
RPR0521_PXS_PERSISTENCE_MASK,
RPR0521_PXS_PERSISTENCE_DRDY);
if (err) {
dev_err(&data->client->dev, "PS control reg write fail.\n");
return -EBUSY;
}
/* Ignore latch and mode because of drdy */
err = regmap_write(data->regmap, RPR0521_REG_INTERRUPT,
RPR0521_INTERRUPT_INT_REASSERT_DISABLE |
RPR0521_INTERRUPT_INT_TRIG_ALS_DISABLE |
RPR0521_INTERRUPT_INT_TRIG_PS_ENABLE
);
if (err) {
dev_err(&data->client->dev, "Interrupt setup write fail.\n");
return -EBUSY;
}
return 0;
}
static int rpr0521_write_int_disable(struct rpr0521_data *data)
{
/* Don't care of clearing mode, assert and latch. */
return regmap_write(data->regmap, RPR0521_REG_INTERRUPT,
RPR0521_INTERRUPT_INT_TRIG_ALS_DISABLE |
RPR0521_INTERRUPT_INT_TRIG_PS_DISABLE
);
}
/*
* Trigger producer enable / disable. Note that there will be trigs only when
* measurement data is ready to be read.
*/
static int rpr0521_pxs_drdy_set_state(struct iio_trigger *trigger,
bool enable_drdy)
{
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trigger);
struct rpr0521_data *data = iio_priv(indio_dev);
int err;
if (enable_drdy)
err = rpr0521_write_int_enable(data);
else
err = rpr0521_write_int_disable(data);
if (err)
dev_err(&data->client->dev, "rpr0521_pxs_drdy_set_state failed\n");
return err;
}
static const struct iio_trigger_ops rpr0521_trigger_ops = {
.set_trigger_state = rpr0521_pxs_drdy_set_state,
};
static int rpr0521_buffer_preenable(struct iio_dev *indio_dev)
{
int err;
struct rpr0521_data *data = iio_priv(indio_dev);
mutex_lock(&data->lock);
err = rpr0521_set_power_state(data, true,
(RPR0521_MODE_PXS_MASK | RPR0521_MODE_ALS_MASK));
mutex_unlock(&data->lock);
if (err)
dev_err(&data->client->dev, "_buffer_preenable fail\n");
return err;
}
static int rpr0521_buffer_postdisable(struct iio_dev *indio_dev)
{
int err;
struct rpr0521_data *data = iio_priv(indio_dev);
mutex_lock(&data->lock);
err = rpr0521_set_power_state(data, false,
(RPR0521_MODE_PXS_MASK | RPR0521_MODE_ALS_MASK));
mutex_unlock(&data->lock);
if (err)
dev_err(&data->client->dev, "_buffer_postdisable fail\n");
return err;
}
static const struct iio_buffer_setup_ops rpr0521_buffer_setup_ops = {
.preenable = rpr0521_buffer_preenable,
.postdisable = rpr0521_buffer_postdisable,
};
static int rpr0521_get_gain(struct rpr0521_data *data, int chan,
int *val, int *val2)
{
int ret, reg, idx;
ret = regmap_read(data->regmap, rpr0521_gain[chan].reg, ®);
if (ret < 0)
return ret;
idx = (rpr0521_gain[chan].mask & reg) >> rpr0521_gain[chan].shift;
*val = rpr0521_gain[chan].gain[idx].scale;
*val2 = rpr0521_gain[chan].gain[idx].uscale;
return 0;
}
static int rpr0521_set_gain(struct rpr0521_data *data, int chan,
int val, int val2)
{
int i, idx = -EINVAL;
/* get gain index */
for (i = 0; i < rpr0521_gain[chan].size; i++)
if (val == rpr0521_gain[chan].gain[i].scale &&
val2 == rpr0521_gain[chan].gain[i].uscale) {
idx = i;
break;
}
if (idx < 0)
return idx;
return regmap_update_bits(data->regmap, rpr0521_gain[chan].reg,
rpr0521_gain[chan].mask,
idx << rpr0521_gain[chan].shift);
}
static int rpr0521_read_samp_freq(struct rpr0521_data *data,
enum iio_chan_type chan_type,
int *val, int *val2)
{
int reg, ret;
ret = regmap_read(data->regmap, RPR0521_REG_MODE_CTRL, ®);
if (ret < 0)
return ret;
reg &= RPR0521_MODE_MEAS_TIME_MASK;
if (reg >= ARRAY_SIZE(rpr0521_samp_freq_i))
return -EINVAL;
switch (chan_type) {
case IIO_INTENSITY:
*val = rpr0521_samp_freq_i[reg].als_hz;
*val2 = rpr0521_samp_freq_i[reg].als_uhz;
return 0;
case IIO_PROXIMITY:
*val = rpr0521_samp_freq_i[reg].pxs_hz;
*val2 = rpr0521_samp_freq_i[reg].pxs_uhz;
return 0;
default:
return -EINVAL;
}
}
static int rpr0521_write_samp_freq_common(struct rpr0521_data *data,
enum iio_chan_type chan_type,
int val, int val2)
{
int i;
/*
* Ignore channel
* both pxs and als are setup only to same freq because of simplicity
*/
switch (val) {
case 0:
i = 0;
break;
case 2:
if (val2 != 500000)
return -EINVAL;
i = 11;
break;
case 10:
i = 6;
break;
default:
return -EINVAL;
}
return regmap_update_bits(data->regmap,
RPR0521_REG_MODE_CTRL,
RPR0521_MODE_MEAS_TIME_MASK,
i);
}
static int rpr0521_read_ps_offset(struct rpr0521_data *data, int *offset)
{
int ret;
__le16 buffer;
ret = regmap_bulk_read(data->regmap,
RPR0521_REG_PS_OFFSET_LSB, &buffer, sizeof(buffer));
if (ret < 0) {
dev_err(&data->client->dev, "Failed to read PS OFFSET register\n");
return ret;
}
*offset = le16_to_cpu(buffer);
return ret;
}
static int rpr0521_write_ps_offset(struct rpr0521_data *data, int offset)
{
int ret;
__le16 buffer;
buffer = cpu_to_le16(offset & 0x3ff);
ret = regmap_raw_write(data->regmap,
RPR0521_REG_PS_OFFSET_LSB, &buffer, sizeof(buffer));
if (ret < 0) {
dev_err(&data->client->dev, "Failed to write PS OFFSET register\n");
return ret;
}
return ret;
}
static int rpr0521_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
struct rpr0521_data *data = iio_priv(indio_dev);
int ret;
int busy;
u8 device_mask;
__le16 raw_data;
switch (mask) {
case IIO_CHAN_INFO_RAW:
if (chan->type != IIO_INTENSITY && chan->type != IIO_PROXIMITY)
return -EINVAL;
busy = iio_device_claim_direct_mode(indio_dev);
if (busy)
return -EBUSY;
device_mask = rpr0521_data_reg[chan->address].device_mask;
mutex_lock(&data->lock);
ret = rpr0521_set_power_state(data, true, device_mask);
if (ret < 0)
goto rpr0521_read_raw_out;
ret = regmap_bulk_read(data->regmap,
rpr0521_data_reg[chan->address].address,
&raw_data, sizeof(raw_data));
if (ret < 0) {
rpr0521_set_power_state(data, false, device_mask);
goto rpr0521_read_raw_out;
}
ret = rpr0521_set_power_state(data, false, device_mask);
rpr0521_read_raw_out:
mutex_unlock(&data->lock);
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
*val = le16_to_cpu(raw_data);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
mutex_lock(&data->lock);
ret = rpr0521_get_gain(data, chan->address, val, val2);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_SAMP_FREQ:
mutex_lock(&data->lock);
ret = rpr0521_read_samp_freq(data, chan->type, val, val2);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_OFFSET:
mutex_lock(&data->lock);
ret = rpr0521_read_ps_offset(data, val);
mutex_unlock(&data->lock);
if (ret < 0)
return ret;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int rpr0521_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val,
int val2, long mask)
{
struct rpr0521_data *data = iio_priv(indio_dev);
int ret;
switch (mask) {
case IIO_CHAN_INFO_SCALE:
mutex_lock(&data->lock);
ret = rpr0521_set_gain(data, chan->address, val, val2);
mutex_unlock(&data->lock);
return ret;
case IIO_CHAN_INFO_SAMP_FREQ:
mutex_lock(&data->lock);
ret = rpr0521_write_samp_freq_common(data, chan->type,
val, val2);
mutex_unlock(&data->lock);
return ret;
case IIO_CHAN_INFO_OFFSET:
mutex_lock(&data->lock);
ret = rpr0521_write_ps_offset(data, val);
mutex_unlock(&data->lock);
return ret;
default:
return -EINVAL;
}
}
static const struct iio_info rpr0521_info = {
.read_raw = rpr0521_read_raw,
.write_raw = rpr0521_write_raw,
.attrs = &rpr0521_attribute_group,
};
static int rpr0521_init(struct rpr0521_data *data)
{
int ret;
int id;
ret = regmap_read(data->regmap, RPR0521_REG_ID, &id);
if (ret < 0) {
dev_err(&data->client->dev, "Failed to read REG_ID register\n");
return ret;
}
if (id != RPR0521_MANUFACT_ID) {
dev_err(&data->client->dev, "Wrong id, got %x, expected %x\n",
id, RPR0521_MANUFACT_ID);
return -ENODEV;
}
/* set default measurement time - 100 ms for both ALS and PS */
ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
RPR0521_MODE_MEAS_TIME_MASK,
RPR0521_DEFAULT_MEAS_TIME);
if (ret) {
pr_err("regmap_update_bits returned %d\n", ret);
return ret;
}
#ifndef CONFIG_PM
ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE);
if (ret < 0)
return ret;
ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE);
if (ret < 0)
return ret;
#endif
data->irq_timestamp = 0;
return 0;
}
static int rpr0521_poweroff(struct rpr0521_data *data)
{
int ret;
int tmp;
ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL,
RPR0521_MODE_ALS_MASK |
RPR0521_MODE_PXS_MASK,
RPR0521_MODE_ALS_DISABLE |
RPR0521_MODE_PXS_DISABLE);
if (ret < 0)
return ret;
data->als_dev_en = false;
data->pxs_dev_en = false;
/*
* Int pin keeps state after power off. Set pin to high impedance
* mode to prevent power drain.
*/
ret = regmap_read(data->regmap, RPR0521_REG_INTERRUPT, &tmp);
if (ret) {
dev_err(&data->client->dev, "Failed to reset int pin.\n");
return ret;
}
return 0;
}
static bool rpr0521_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case RPR0521_REG_MODE_CTRL:
case RPR0521_REG_ALS_CTRL:
case RPR0521_REG_PXS_CTRL:
return false;
default:
return true;
}
}
static const struct regmap_config rpr0521_regmap_config = {
.name = RPR0521_REGMAP_NAME,
.reg_bits = 8,
.val_bits = 8,
.max_register = RPR0521_REG_ID,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = rpr0521_is_volatile_reg,
};
static int rpr0521_probe(struct i2c_client *client)
{
struct rpr0521_data *data;
struct iio_dev *indio_dev;
struct regmap *regmap;
int ret;
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
if (!indio_dev)
return -ENOMEM;
regmap = devm_regmap_init_i2c(client, &rpr0521_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "regmap_init failed!\n");
return PTR_ERR(regmap);
}
data = iio_priv(indio_dev);
i2c_set_clientdata(client, indio_dev);
data->client = client;
data->regmap = regmap;
mutex_init(&data->lock);
indio_dev->info = &rpr0521_info;
indio_dev->name = RPR0521_DRV_NAME;
indio_dev->channels = rpr0521_channels;
indio_dev->num_channels = ARRAY_SIZE(rpr0521_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = rpr0521_init(data);
if (ret < 0) {
dev_err(&client->dev, "rpr0521 chip init failed\n");
return ret;
}
ret = pm_runtime_set_active(&client->dev);
if (ret < 0)
goto err_poweroff;
pm_runtime_enable(&client->dev);
pm_runtime_set_autosuspend_delay(&client->dev, RPR0521_SLEEP_DELAY_MS);
pm_runtime_use_autosuspend(&client->dev);
/*
* If sensor write/read is needed in _probe after _use_autosuspend,
* sensor needs to be _resumed first using rpr0521_set_power_state().
*/
/* IRQ to trigger setup */
if (client->irq) {
/* Trigger0 producer setup */
data->drdy_trigger0 = devm_iio_trigger_alloc(
indio_dev->dev.parent,
"%s-dev%d", indio_dev->name, iio_device_id(indio_dev));
if (!data->drdy_trigger0) {
ret = -ENOMEM;
goto err_pm_disable;
}
data->drdy_trigger0->ops = &rpr0521_trigger_ops;
indio_dev->available_scan_masks = rpr0521_available_scan_masks;
iio_trigger_set_drvdata(data->drdy_trigger0, indio_dev);
/* Ties irq to trigger producer handler. */
ret = devm_request_threaded_irq(&client->dev, client->irq,
rpr0521_drdy_irq_handler, rpr0521_drdy_irq_thread,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
RPR0521_IRQ_NAME, indio_dev);
if (ret < 0) {
dev_err(&client->dev, "request irq %d for trigger0 failed\n",
client->irq);
goto err_pm_disable;
}
ret = devm_iio_trigger_register(indio_dev->dev.parent,
data->drdy_trigger0);
if (ret) {
dev_err(&client->dev, "iio trigger register failed\n");
goto err_pm_disable;
}
/*
* Now whole pipe from physical interrupt (irq defined by
* devicetree to device) to trigger0 output is set up.
*/
/* Trigger consumer setup */
ret = devm_iio_triggered_buffer_setup(indio_dev->dev.parent,
indio_dev,
rpr0521_trigger_consumer_store_time,
rpr0521_trigger_consumer_handler,
&rpr0521_buffer_setup_ops);
if (ret < 0) {
dev_err(&client->dev, "iio triggered buffer setup failed\n");
goto err_pm_disable;
}
}
ret = iio_device_register(indio_dev);
if (ret)
goto err_pm_disable;
return 0;
err_pm_disable:
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
err_poweroff:
rpr0521_poweroff(data);
return ret;
}
static void rpr0521_remove(struct i2c_client *client)
{
struct iio_dev *indio_dev = i2c_get_clientdata(client);
iio_device_unregister(indio_dev);
pm_runtime_disable(&client->dev);
pm_runtime_set_suspended(&client->dev);
rpr0521_poweroff(iio_priv(indio_dev));
}
static int rpr0521_runtime_suspend(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct rpr0521_data *data = iio_priv(indio_dev);
int ret;
mutex_lock(&data->lock);
/* If measurements are enabled, enable them on resume */
if (!data->als_need_dis)
data->als_ps_need_en = data->als_dev_en;
if (!data->pxs_need_dis)
data->pxs_ps_need_en = data->pxs_dev_en;
/* disable channels and sets {als,pxs}_dev_en to false */
ret = rpr0521_poweroff(data);
regcache_mark_dirty(data->regmap);
mutex_unlock(&data->lock);
return ret;
}
static int rpr0521_runtime_resume(struct device *dev)
{
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
struct rpr0521_data *data = iio_priv(indio_dev);
int ret;
regcache_sync(data->regmap);
if (data->als_ps_need_en) {
ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE);
if (ret < 0)
return ret;
data->als_ps_need_en = false;
}
if (data->pxs_ps_need_en) {
ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE);
if (ret < 0)
return ret;
data->pxs_ps_need_en = false;
}
msleep(100); //wait for first measurement result
return 0;
}
static const struct dev_pm_ops rpr0521_pm_ops = {
RUNTIME_PM_OPS(rpr0521_runtime_suspend, rpr0521_runtime_resume, NULL)
};
static const struct acpi_device_id rpr0521_acpi_match[] = {
{"RPR0521", 0},
{ }
};
MODULE_DEVICE_TABLE(acpi, rpr0521_acpi_match);
static const struct i2c_device_id rpr0521_id[] = {
{"rpr0521", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, rpr0521_id);
static struct i2c_driver rpr0521_driver = {
.driver = {
.name = RPR0521_DRV_NAME,
.pm = pm_ptr(&rpr0521_pm_ops),
.acpi_match_table = ACPI_PTR(rpr0521_acpi_match),
},
.probe = rpr0521_probe,
.remove = rpr0521_remove,
.id_table = rpr0521_id,
};
module_i2c_driver(rpr0521_driver);
MODULE_AUTHOR("Daniel Baluta <[email protected]>");
MODULE_DESCRIPTION("RPR0521 ROHM Ambient Light and Proximity Sensor driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/iio/light/rpr0521.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* HID Sensors Driver
* Copyright (c) 2014, Intel Corporation.
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/slab.h>
#include <linux/hid-sensor-hub.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include "../common/hid-sensors/hid-sensor-trigger.h"
#define CHANNEL_SCAN_INDEX_PRESENCE 0
struct prox_state {
struct hid_sensor_hub_callbacks callbacks;
struct hid_sensor_common common_attributes;
struct hid_sensor_hub_attribute_info prox_attr;
u32 human_presence;
int scale_pre_decml;
int scale_post_decml;
int scale_precision;
};
static const u32 prox_sensitivity_addresses[] = {
HID_USAGE_SENSOR_HUMAN_PRESENCE,
HID_USAGE_SENSOR_DATA_PRESENCE,
};
/* Channel definitions */
static const struct iio_chan_spec prox_channels[] = {
{
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_SAMP_FREQ) |
BIT(IIO_CHAN_INFO_HYSTERESIS),
.scan_index = CHANNEL_SCAN_INDEX_PRESENCE,
}
};
/* Adjust channel real bits based on report descriptor */
static void prox_adjust_channel_bit_mask(struct iio_chan_spec *channels,
int channel, int size)
{
channels[channel].scan_type.sign = 's';
/* Real storage bits will change based on the report desc. */
channels[channel].scan_type.realbits = size * 8;
/* Maximum size of a sample to capture is u32 */
channels[channel].scan_type.storagebits = sizeof(u32) * 8;
}
/* Channel read_raw handler */
static int prox_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2,
long mask)
{
struct prox_state *prox_state = iio_priv(indio_dev);
struct hid_sensor_hub_device *hsdev;
int report_id = -1;
u32 address;
int ret_type;
s32 min;
*val = 0;
*val2 = 0;
switch (mask) {
case IIO_CHAN_INFO_RAW:
switch (chan->scan_index) {
case CHANNEL_SCAN_INDEX_PRESENCE:
report_id = prox_state->prox_attr.report_id;
min = prox_state->prox_attr.logical_minimum;
address = HID_USAGE_SENSOR_HUMAN_PRESENCE;
hsdev = prox_state->common_attributes.hsdev;
break;
default:
report_id = -1;
break;
}
if (report_id >= 0) {
hid_sensor_power_state(&prox_state->common_attributes,
true);
*val = sensor_hub_input_attr_get_raw_value(
hsdev, hsdev->usage, address, report_id,
SENSOR_HUB_SYNC, min < 0);
hid_sensor_power_state(&prox_state->common_attributes,
false);
} else {
*val = 0;
return -EINVAL;
}
ret_type = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SCALE:
*val = prox_state->scale_pre_decml;
*val2 = prox_state->scale_post_decml;
ret_type = prox_state->scale_precision;
break;
case IIO_CHAN_INFO_OFFSET:
*val = hid_sensor_convert_exponent(
prox_state->prox_attr.unit_expo);
ret_type = IIO_VAL_INT;
break;
case IIO_CHAN_INFO_SAMP_FREQ:
ret_type = hid_sensor_read_samp_freq_value(
&prox_state->common_attributes, val, val2);
break;
case IIO_CHAN_INFO_HYSTERESIS:
ret_type = hid_sensor_read_raw_hyst_value(
&prox_state->common_attributes, val, val2);
break;
default:
ret_type = -EINVAL;
break;
}
return ret_type;
}
/* Channel write_raw handler */
static int prox_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct prox_state *prox_state = iio_priv(indio_dev);
int ret = 0;
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
ret = hid_sensor_write_samp_freq_value(
&prox_state->common_attributes, val, val2);
break;
case IIO_CHAN_INFO_HYSTERESIS:
ret = hid_sensor_write_raw_hyst_value(
&prox_state->common_attributes, val, val2);
break;
default:
ret = -EINVAL;
}
return ret;
}
static const struct iio_info prox_info = {
.read_raw = &prox_read_raw,
.write_raw = &prox_write_raw,
};
/* Function to push data to buffer */
static void hid_sensor_push_data(struct iio_dev *indio_dev, const void *data,
int len)
{
dev_dbg(&indio_dev->dev, "hid_sensor_push_data\n");
iio_push_to_buffers(indio_dev, data);
}
/* Callback handler to send event after all samples are received and captured */
static int prox_proc_event(struct hid_sensor_hub_device *hsdev,
unsigned usage_id,
void *priv)
{
struct iio_dev *indio_dev = platform_get_drvdata(priv);
struct prox_state *prox_state = iio_priv(indio_dev);
dev_dbg(&indio_dev->dev, "prox_proc_event\n");
if (atomic_read(&prox_state->common_attributes.data_ready))
hid_sensor_push_data(indio_dev,
&prox_state->human_presence,
sizeof(prox_state->human_presence));
return 0;
}
/* Capture samples in local storage */
static int prox_capture_sample(struct hid_sensor_hub_device *hsdev,
unsigned usage_id,
size_t raw_len, char *raw_data,
void *priv)
{
struct iio_dev *indio_dev = platform_get_drvdata(priv);
struct prox_state *prox_state = iio_priv(indio_dev);
int ret = -EINVAL;
switch (usage_id) {
case HID_USAGE_SENSOR_HUMAN_PRESENCE:
switch (raw_len) {
case 1:
prox_state->human_presence = *(u8 *)raw_data;
return 0;
case 4:
prox_state->human_presence = *(u32 *)raw_data;
return 0;
default:
break;
}
break;
}
return ret;
}
/* Parse report which is specific to an usage id*/
static int prox_parse_report(struct platform_device *pdev,
struct hid_sensor_hub_device *hsdev,
struct iio_chan_spec *channels,
unsigned usage_id,
struct prox_state *st)
{
int ret;
ret = sensor_hub_input_get_attribute_info(hsdev, HID_INPUT_REPORT,
usage_id,
HID_USAGE_SENSOR_HUMAN_PRESENCE,
&st->prox_attr);
if (ret < 0)
return ret;
prox_adjust_channel_bit_mask(channels, CHANNEL_SCAN_INDEX_PRESENCE,
st->prox_attr.size);
dev_dbg(&pdev->dev, "prox %x:%x\n", st->prox_attr.index,
st->prox_attr.report_id);
return ret;
}
/* Function to initialize the processing for usage id */
static int hid_prox_probe(struct platform_device *pdev)
{
int ret = 0;
static const char *name = "prox";
struct iio_dev *indio_dev;
struct prox_state *prox_state;
struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data;
indio_dev = devm_iio_device_alloc(&pdev->dev,
sizeof(struct prox_state));
if (!indio_dev)
return -ENOMEM;
platform_set_drvdata(pdev, indio_dev);
prox_state = iio_priv(indio_dev);
prox_state->common_attributes.hsdev = hsdev;
prox_state->common_attributes.pdev = pdev;
ret = hid_sensor_parse_common_attributes(hsdev, hsdev->usage,
&prox_state->common_attributes,
prox_sensitivity_addresses,
ARRAY_SIZE(prox_sensitivity_addresses));
if (ret) {
dev_err(&pdev->dev, "failed to setup common attributes\n");
return ret;
}
indio_dev->channels = devm_kmemdup(&pdev->dev, prox_channels,
sizeof(prox_channels), GFP_KERNEL);
if (!indio_dev->channels) {
dev_err(&pdev->dev, "failed to duplicate channels\n");
return -ENOMEM;
}
ret = prox_parse_report(pdev, hsdev,
(struct iio_chan_spec *)indio_dev->channels,
hsdev->usage, prox_state);
if (ret) {
dev_err(&pdev->dev, "failed to setup attributes\n");
return ret;
}
indio_dev->num_channels = ARRAY_SIZE(prox_channels);
indio_dev->info = &prox_info;
indio_dev->name = name;
indio_dev->modes = INDIO_DIRECT_MODE;
atomic_set(&prox_state->common_attributes.data_ready, 0);
ret = hid_sensor_setup_trigger(indio_dev, name,
&prox_state->common_attributes);
if (ret) {
dev_err(&pdev->dev, "trigger setup failed\n");
return ret;
}
ret = iio_device_register(indio_dev);
if (ret) {
dev_err(&pdev->dev, "device register failed\n");
goto error_remove_trigger;
}
prox_state->callbacks.send_event = prox_proc_event;
prox_state->callbacks.capture_sample = prox_capture_sample;
prox_state->callbacks.pdev = pdev;
ret = sensor_hub_register_callback(hsdev, hsdev->usage,
&prox_state->callbacks);
if (ret < 0) {
dev_err(&pdev->dev, "callback reg failed\n");
goto error_iio_unreg;
}
return ret;
error_iio_unreg:
iio_device_unregister(indio_dev);
error_remove_trigger:
hid_sensor_remove_trigger(indio_dev, &prox_state->common_attributes);
return ret;
}
/* Function to deinitialize the processing for usage id */
static int hid_prox_remove(struct platform_device *pdev)
{
struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data;
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct prox_state *prox_state = iio_priv(indio_dev);
sensor_hub_remove_callback(hsdev, hsdev->usage);
iio_device_unregister(indio_dev);
hid_sensor_remove_trigger(indio_dev, &prox_state->common_attributes);
return 0;
}
static const struct platform_device_id hid_prox_ids[] = {
{
/* Format: HID-SENSOR-usage_id_in_hex_lowercase */
.name = "HID-SENSOR-200011",
},
{
/* Format: HID-SENSOR-tag-usage_id_in_hex_lowercase */
.name = "HID-SENSOR-LISS-0226",
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, hid_prox_ids);
static struct platform_driver hid_prox_platform_driver = {
.id_table = hid_prox_ids,
.driver = {
.name = KBUILD_MODNAME,
.pm = &hid_sensor_pm_ops,
},
.probe = hid_prox_probe,
.remove = hid_prox_remove,
};
module_platform_driver(hid_prox_platform_driver);
MODULE_DESCRIPTION("HID Sensor Proximity");
MODULE_AUTHOR("Archana Patni <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(IIO_HID);
| linux-master | drivers/iio/light/hid-sensor-prox.c |
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