python_code
stringlengths 0
1.8M
| repo_name
stringclasses 7
values | file_path
stringlengths 5
99
|
|---|---|---|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include <soc/tegra/fuse.h>
#include "fuse.h"
#define CPU_PROCESS_CORNERS 2
#define GPU_PROCESS_CORNERS 2
#define SOC_PROCESS_CORNERS 2
#define FUSE_CPU_SPEEDO_0 0x14
#define FUSE_CPU_SPEEDO_1 0x2c
#define FUSE_CPU_SPEEDO_2 0x30
#define FUSE_SOC_SPEEDO_0 0x34
#define FUSE_SOC_SPEEDO_1 0x38
#define FUSE_SOC_SPEEDO_2 0x3c
#define FUSE_CPU_IDDQ 0x18
#define FUSE_SOC_IDDQ 0x40
#define FUSE_GPU_IDDQ 0x128
#define FUSE_FT_REV 0x28
enum {
THRESHOLD_INDEX_0,
THRESHOLD_INDEX_1,
THRESHOLD_INDEX_COUNT,
};
static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
{2190, UINT_MAX},
{0, UINT_MAX},
};
static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = {
{1965, UINT_MAX},
{0, UINT_MAX},
};
static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
{2101, UINT_MAX},
{0, UINT_MAX},
};
static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
int *threshold)
{
int sku = sku_info->sku_id;
/* Assign to default */
sku_info->cpu_speedo_id = 0;
sku_info->soc_speedo_id = 0;
sku_info->gpu_speedo_id = 0;
*threshold = THRESHOLD_INDEX_0;
switch (sku) {
case 0x00: /* Eng sku */
case 0x0F:
case 0x23:
/* Using the default */
break;
case 0x83:
sku_info->cpu_speedo_id = 2;
break;
case 0x1F:
case 0x87:
case 0x27:
sku_info->cpu_speedo_id = 2;
sku_info->soc_speedo_id = 0;
sku_info->gpu_speedo_id = 1;
*threshold = THRESHOLD_INDEX_0;
break;
case 0x81:
case 0x21:
case 0x07:
sku_info->cpu_speedo_id = 1;
sku_info->soc_speedo_id = 1;
sku_info->gpu_speedo_id = 1;
*threshold = THRESHOLD_INDEX_1;
break;
case 0x49:
case 0x4A:
case 0x48:
sku_info->cpu_speedo_id = 4;
sku_info->soc_speedo_id = 2;
sku_info->gpu_speedo_id = 3;
*threshold = THRESHOLD_INDEX_1;
break;
default:
pr_err("Tegra Unknown SKU %d\n", sku);
/* Using the default for the error case */
break;
}
}
void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info)
{
int i, threshold, soc_speedo_0_value;
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
THRESHOLD_INDEX_COUNT);
BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
THRESHOLD_INDEX_COUNT);
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
THRESHOLD_INDEX_COUNT);
sku_info->cpu_speedo_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
if (sku_info->cpu_speedo_value == 0) {
pr_warn("Tegra Warning: Speedo value not fused.\n");
WARN_ON(1);
return;
}
/* GPU Speedo is stored in CPU_SPEEDO_2 */
sku_info->gpu_speedo_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
soc_speedo_0_value = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
rev_sku_to_speedo_ids(sku_info, &threshold);
sku_info->cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ);
for (i = 0; i < GPU_PROCESS_CORNERS; i++)
if (sku_info->gpu_speedo_value <
gpu_process_speedos[threshold][i])
break;
sku_info->gpu_process_id = i;
for (i = 0; i < CPU_PROCESS_CORNERS; i++)
if (sku_info->cpu_speedo_value <
cpu_process_speedos[threshold][i])
break;
sku_info->cpu_process_id = i;
for (i = 0; i < SOC_PROCESS_CORNERS; i++)
if (soc_speedo_0_value <
soc_process_speedos[threshold][i])
break;
sku_info->soc_process_id = i;
pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",
sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);
}
|
linux-master
|
drivers/soc/tegra/fuse/speedo-tegra124.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/bug.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <soc/tegra/fuse.h>
#include "fuse.h"
#define CPU_SPEEDO_LSBIT 20
#define CPU_SPEEDO_MSBIT 29
#define CPU_SPEEDO_REDUND_LSBIT 30
#define CPU_SPEEDO_REDUND_MSBIT 39
#define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
#define SOC_SPEEDO_LSBIT 40
#define SOC_SPEEDO_MSBIT 47
#define SOC_SPEEDO_REDUND_LSBIT 48
#define SOC_SPEEDO_REDUND_MSBIT 55
#define SOC_SPEEDO_REDUND_OFFS (SOC_SPEEDO_REDUND_MSBIT - SOC_SPEEDO_MSBIT)
#define SPEEDO_MULT 4
#define PROCESS_CORNERS_NUM 4
#define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2)
#define SPEEDO_ID_SELECT_1(sku) \
(((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
((sku) != 27) && ((sku) != 28))
enum {
SPEEDO_ID_0,
SPEEDO_ID_1,
SPEEDO_ID_2,
SPEEDO_ID_COUNT,
};
static const u32 __initconst cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
{315, 366, 420, UINT_MAX},
{303, 368, 419, UINT_MAX},
{316, 331, 383, UINT_MAX},
};
static const u32 __initconst soc_process_speedos[][PROCESS_CORNERS_NUM] = {
{165, 195, 224, UINT_MAX},
{165, 195, 224, UINT_MAX},
{165, 195, 224, UINT_MAX},
};
void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
{
u32 reg;
u32 val;
int i;
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) != SPEEDO_ID_COUNT);
if (SPEEDO_ID_SELECT_0(sku_info->revision))
sku_info->soc_speedo_id = SPEEDO_ID_0;
else if (SPEEDO_ID_SELECT_1(sku_info->sku_id))
sku_info->soc_speedo_id = SPEEDO_ID_1;
else
sku_info->soc_speedo_id = SPEEDO_ID_2;
val = 0;
for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
reg = tegra_fuse_read_spare(i) |
tegra_fuse_read_spare(i + CPU_SPEEDO_REDUND_OFFS);
val = (val << 1) | (reg & 0x1);
}
val = val * SPEEDO_MULT;
pr_debug("Tegra CPU speedo value %u\n", val);
for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
if (val <= cpu_process_speedos[sku_info->soc_speedo_id][i])
break;
}
sku_info->cpu_process_id = i;
val = 0;
for (i = SOC_SPEEDO_MSBIT; i >= SOC_SPEEDO_LSBIT; i--) {
reg = tegra_fuse_read_spare(i) |
tegra_fuse_read_spare(i + SOC_SPEEDO_REDUND_OFFS);
val = (val << 1) | (reg & 0x1);
}
val = val * SPEEDO_MULT;
pr_debug("Core speedo value %u\n", val);
for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
if (val <= soc_process_speedos[sku_info->soc_speedo_id][i])
break;
}
sku_info->soc_process_id = i;
}
|
linux-master
|
drivers/soc/tegra/fuse/speedo-tegra20.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
* Based on drivers/misc/eeprom/sunxi_sid.c
*/
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/kobject.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/random.h>
#include <soc/tegra/fuse.h>
#include "fuse.h"
#define FUSE_BEGIN 0x100
#define FUSE_UID_LOW 0x08
#define FUSE_UID_HIGH 0x0c
static u32 tegra20_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
{
return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
}
static void apb_dma_complete(void *args)
{
struct tegra_fuse *fuse = args;
complete(&fuse->apbdma.wait);
}
static u32 tegra20_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
{
unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
struct dma_async_tx_descriptor *dma_desc;
unsigned long time_left;
u32 value = 0;
int err;
err = pm_runtime_resume_and_get(fuse->dev);
if (err)
return err;
mutex_lock(&fuse->apbdma.lock);
fuse->apbdma.config.src_addr = fuse->phys + FUSE_BEGIN + offset;
err = dmaengine_slave_config(fuse->apbdma.chan, &fuse->apbdma.config);
if (err)
goto out;
dma_desc = dmaengine_prep_slave_single(fuse->apbdma.chan,
fuse->apbdma.phys,
sizeof(u32), DMA_DEV_TO_MEM,
flags);
if (!dma_desc)
goto out;
dma_desc->callback = apb_dma_complete;
dma_desc->callback_param = fuse;
reinit_completion(&fuse->apbdma.wait);
dmaengine_submit(dma_desc);
dma_async_issue_pending(fuse->apbdma.chan);
time_left = wait_for_completion_timeout(&fuse->apbdma.wait,
msecs_to_jiffies(50));
if (WARN(time_left == 0, "apb read dma timed out"))
dmaengine_terminate_all(fuse->apbdma.chan);
else
value = *fuse->apbdma.virt;
out:
mutex_unlock(&fuse->apbdma.lock);
pm_runtime_put(fuse->dev);
return value;
}
static bool dma_filter(struct dma_chan *chan, void *filter_param)
{
struct device_node *np = chan->device->dev->of_node;
return of_device_is_compatible(np, "nvidia,tegra20-apbdma");
}
static void tegra20_fuse_release_channel(void *data)
{
struct tegra_fuse *fuse = data;
dma_release_channel(fuse->apbdma.chan);
fuse->apbdma.chan = NULL;
}
static void tegra20_fuse_free_coherent(void *data)
{
struct tegra_fuse *fuse = data;
dma_free_coherent(fuse->dev, sizeof(u32), fuse->apbdma.virt,
fuse->apbdma.phys);
fuse->apbdma.virt = NULL;
fuse->apbdma.phys = 0x0;
}
static int tegra20_fuse_probe(struct tegra_fuse *fuse)
{
dma_cap_mask_t mask;
int err;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
fuse->apbdma.chan = dma_request_channel(mask, dma_filter, NULL);
if (!fuse->apbdma.chan)
return -EPROBE_DEFER;
err = devm_add_action_or_reset(fuse->dev, tegra20_fuse_release_channel,
fuse);
if (err)
return err;
fuse->apbdma.virt = dma_alloc_coherent(fuse->dev, sizeof(u32),
&fuse->apbdma.phys,
GFP_KERNEL);
if (!fuse->apbdma.virt)
return -ENOMEM;
err = devm_add_action_or_reset(fuse->dev, tegra20_fuse_free_coherent,
fuse);
if (err)
return err;
fuse->apbdma.config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
fuse->apbdma.config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
fuse->apbdma.config.src_maxburst = 1;
fuse->apbdma.config.dst_maxburst = 1;
fuse->apbdma.config.direction = DMA_DEV_TO_MEM;
fuse->apbdma.config.device_fc = false;
init_completion(&fuse->apbdma.wait);
mutex_init(&fuse->apbdma.lock);
fuse->read = tegra20_fuse_read;
return 0;
}
static const struct tegra_fuse_info tegra20_fuse_info = {
.read = tegra20_fuse_read,
.size = 0x1f8,
.spare = 0x100,
};
/* Early boot code. This code is called before the devices are created */
static void __init tegra20_fuse_add_randomness(void)
{
u32 randomness[7];
randomness[0] = tegra_sku_info.sku_id;
randomness[1] = tegra_read_straps();
randomness[2] = tegra_read_chipid();
randomness[3] = tegra_sku_info.cpu_process_id << 16;
randomness[3] |= tegra_sku_info.soc_process_id;
randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
randomness[4] |= tegra_sku_info.soc_speedo_id;
randomness[5] = tegra_fuse_read_early(FUSE_UID_LOW);
randomness[6] = tegra_fuse_read_early(FUSE_UID_HIGH);
add_device_randomness(randomness, sizeof(randomness));
}
static void __init tegra20_fuse_init(struct tegra_fuse *fuse)
{
fuse->read_early = tegra20_fuse_read_early;
tegra_init_revision();
fuse->soc->speedo_init(&tegra_sku_info);
tegra20_fuse_add_randomness();
}
const struct tegra_fuse_soc tegra20_fuse_soc = {
.init = tegra20_fuse_init,
.speedo_init = tegra20_init_speedo_data,
.probe = tegra20_fuse_probe,
.info = &tegra20_fuse_info,
.soc_attr_group = &tegra_soc_attr_group,
.clk_suspend_on = false,
};
|
linux-master
|
drivers/soc/tegra/fuse/fuse-tegra20.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/kobject.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/nvmem-consumer.h>
#include <linux/nvmem-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include <soc/tegra/common.h>
#include <soc/tegra/fuse.h>
#include "fuse.h"
struct tegra_sku_info tegra_sku_info;
EXPORT_SYMBOL(tegra_sku_info);
static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
[TEGRA_REVISION_UNKNOWN] = "unknown",
[TEGRA_REVISION_A01] = "A01",
[TEGRA_REVISION_A02] = "A02",
[TEGRA_REVISION_A03] = "A03",
[TEGRA_REVISION_A03p] = "A03 prime",
[TEGRA_REVISION_A04] = "A04",
};
static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {
[TEGRA_PLATFORM_SILICON] = "Silicon",
[TEGRA_PLATFORM_QT] = "QT",
[TEGRA_PLATFORM_SYSTEM_FPGA] = "System FPGA",
[TEGRA_PLATFORM_UNIT_FPGA] = "Unit FPGA",
[TEGRA_PLATFORM_ASIM_QT] = "Asim QT",
[TEGRA_PLATFORM_ASIM_LINSIM] = "Asim Linsim",
[TEGRA_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim",
[TEGRA_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation",
[TEGRA_PLATFORM_VDK] = "VDK",
[TEGRA_PLATFORM_VSP] = "VSP",
};
static const struct of_device_id car_match[] __initconst = {
{ .compatible = "nvidia,tegra20-car", },
{ .compatible = "nvidia,tegra30-car", },
{ .compatible = "nvidia,tegra114-car", },
{ .compatible = "nvidia,tegra124-car", },
{ .compatible = "nvidia,tegra132-car", },
{ .compatible = "nvidia,tegra210-car", },
{},
};
static struct tegra_fuse *fuse = &(struct tegra_fuse) {
.base = NULL,
.soc = NULL,
};
static const struct of_device_id tegra_fuse_match[] = {
#ifdef CONFIG_ARCH_TEGRA_234_SOC
{ .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_194_SOC
{ .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_186_SOC
{ .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_210_SOC
{ .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_132_SOC
{ .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_124_SOC
{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_114_SOC
{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
{ .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
#endif
{ /* sentinel */ }
};
static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
size_t bytes)
{
unsigned int count = bytes / 4, i;
struct tegra_fuse *fuse = priv;
u32 *buffer = value;
for (i = 0; i < count; i++)
buffer[i] = fuse->read(fuse, offset + i * 4);
return 0;
}
static void tegra_fuse_restore(void *base)
{
fuse->base = (void __iomem *)base;
fuse->clk = NULL;
}
static int tegra_fuse_probe(struct platform_device *pdev)
{
void __iomem *base = fuse->base;
struct nvmem_config nvmem;
struct resource *res;
int err;
err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base);
if (err)
return err;
/* take over the memory region from the early initialization */
fuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(fuse->base))
return PTR_ERR(fuse->base);
fuse->phys = res->start;
fuse->clk = devm_clk_get(&pdev->dev, "fuse");
if (IS_ERR(fuse->clk)) {
if (PTR_ERR(fuse->clk) != -EPROBE_DEFER)
dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
PTR_ERR(fuse->clk));
return PTR_ERR(fuse->clk);
}
platform_set_drvdata(pdev, fuse);
fuse->dev = &pdev->dev;
err = devm_pm_runtime_enable(&pdev->dev);
if (err)
return err;
if (fuse->soc->probe) {
err = fuse->soc->probe(fuse);
if (err < 0)
return err;
}
memset(&nvmem, 0, sizeof(nvmem));
nvmem.dev = &pdev->dev;
nvmem.name = "fuse";
nvmem.id = -1;
nvmem.owner = THIS_MODULE;
nvmem.cells = fuse->soc->cells;
nvmem.ncells = fuse->soc->num_cells;
nvmem.keepout = fuse->soc->keepouts;
nvmem.nkeepout = fuse->soc->num_keepouts;
nvmem.type = NVMEM_TYPE_OTP;
nvmem.read_only = true;
nvmem.root_only = false;
nvmem.reg_read = tegra_fuse_read;
nvmem.size = fuse->soc->info->size;
nvmem.word_size = 4;
nvmem.stride = 4;
nvmem.priv = fuse;
fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);
if (IS_ERR(fuse->nvmem)) {
err = PTR_ERR(fuse->nvmem);
dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",
err);
return err;
}
fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse");
if (IS_ERR(fuse->rst)) {
err = PTR_ERR(fuse->rst);
dev_err(&pdev->dev, "failed to get FUSE reset: %pe\n",
fuse->rst);
return err;
}
/*
* FUSE clock is enabled at a boot time, hence this resume/suspend
* disables the clock besides the h/w resetting.
*/
err = pm_runtime_resume_and_get(&pdev->dev);
if (err)
return err;
err = reset_control_reset(fuse->rst);
pm_runtime_put(&pdev->dev);
if (err < 0) {
dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err);
return err;
}
/* release the early I/O memory mapping */
iounmap(base);
return 0;
}
static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev)
{
int err;
err = clk_prepare_enable(fuse->clk);
if (err < 0) {
dev_err(dev, "failed to enable FUSE clock: %d\n", err);
return err;
}
return 0;
}
static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev)
{
clk_disable_unprepare(fuse->clk);
return 0;
}
static int __maybe_unused tegra_fuse_suspend(struct device *dev)
{
int ret;
/*
* Critical for RAM re-repair operation, which must occur on resume
* from LP1 system suspend and as part of CCPLEX cluster switching.
*/
if (fuse->soc->clk_suspend_on)
ret = pm_runtime_resume_and_get(dev);
else
ret = pm_runtime_force_suspend(dev);
return ret;
}
static int __maybe_unused tegra_fuse_resume(struct device *dev)
{
int ret = 0;
if (fuse->soc->clk_suspend_on)
pm_runtime_put(dev);
else
ret = pm_runtime_force_resume(dev);
return ret;
}
static const struct dev_pm_ops tegra_fuse_pm = {
SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume)
};
static struct platform_driver tegra_fuse_driver = {
.driver = {
.name = "tegra-fuse",
.of_match_table = tegra_fuse_match,
.pm = &tegra_fuse_pm,
.suppress_bind_attrs = true,
},
.probe = tegra_fuse_probe,
};
builtin_platform_driver(tegra_fuse_driver);
u32 __init tegra_fuse_read_spare(unsigned int spare)
{
unsigned int offset = fuse->soc->info->spare + spare * 4;
return fuse->read_early(fuse, offset) & 1;
}
u32 __init tegra_fuse_read_early(unsigned int offset)
{
return fuse->read_early(fuse, offset);
}
int tegra_fuse_readl(unsigned long offset, u32 *value)
{
if (!fuse->read || !fuse->clk)
return -EPROBE_DEFER;
if (IS_ERR(fuse->clk))
return PTR_ERR(fuse->clk);
*value = fuse->read(fuse, offset);
return 0;
}
EXPORT_SYMBOL(tegra_fuse_readl);
static void tegra_enable_fuse_clk(void __iomem *base)
{
u32 reg;
reg = readl_relaxed(base + 0x48);
reg |= 1 << 28;
writel(reg, base + 0x48);
/*
* Enable FUSE clock. This needs to be hardcoded because the clock
* subsystem is not active during early boot.
*/
reg = readl(base + 0x14);
reg |= 1 << 7;
writel(reg, base + 0x14);
}
static ssize_t major_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
return sprintf(buf, "%d\n", tegra_get_major_rev());
}
static DEVICE_ATTR_RO(major);
static ssize_t minor_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
return sprintf(buf, "%d\n", tegra_get_minor_rev());
}
static DEVICE_ATTR_RO(minor);
static struct attribute *tegra_soc_attr[] = {
&dev_attr_major.attr,
&dev_attr_minor.attr,
NULL,
};
const struct attribute_group tegra_soc_attr_group = {
.attrs = tegra_soc_attr,
};
#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
/*
* Displays the value in the 'pre_si_platform' field of the HIDREV
* register for Tegra194 devices. A value of 0 indicates that the
* platform type is silicon and all other non-zero values indicate
* the type of simulation platform is being used.
*/
return sprintf(buf, "%d\n", tegra_get_platform());
}
static DEVICE_ATTR_RO(platform);
static struct attribute *tegra194_soc_attr[] = {
&dev_attr_major.attr,
&dev_attr_minor.attr,
&dev_attr_platform.attr,
NULL,
};
const struct attribute_group tegra194_soc_attr_group = {
.attrs = tegra194_soc_attr,
};
#endif
struct device * __init tegra_soc_device_register(void)
{
struct soc_device_attribute *attr;
struct soc_device *dev;
attr = kzalloc(sizeof(*attr), GFP_KERNEL);
if (!attr)
return NULL;
attr->family = kasprintf(GFP_KERNEL, "Tegra");
if (tegra_is_silicon())
attr->revision = kasprintf(GFP_KERNEL, "%s %s",
tegra_platform_name[tegra_sku_info.platform],
tegra_revision_name[tegra_sku_info.revision]);
else
attr->revision = kasprintf(GFP_KERNEL, "%s",
tegra_platform_name[tegra_sku_info.platform]);
attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
attr->custom_attr_group = fuse->soc->soc_attr_group;
dev = soc_device_register(attr);
if (IS_ERR(dev)) {
kfree(attr->soc_id);
kfree(attr->revision);
kfree(attr->family);
kfree(attr);
return ERR_CAST(dev);
}
return soc_device_to_device(dev);
}
static int __init tegra_init_fuse(void)
{
const struct of_device_id *match;
struct device_node *np;
struct resource regs;
tegra_init_apbmisc();
np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
if (!np) {
/*
* Fall back to legacy initialization for 32-bit ARM only. All
* 64-bit ARM device tree files for Tegra are required to have
* a FUSE node.
*
* This is for backwards-compatibility with old device trees
* that didn't contain a FUSE node.
*/
if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
u8 chip = tegra_get_chip_id();
regs.start = 0x7000f800;
regs.end = 0x7000fbff;
regs.flags = IORESOURCE_MEM;
switch (chip) {
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
case TEGRA20:
fuse->soc = &tegra20_fuse_soc;
break;
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
case TEGRA30:
fuse->soc = &tegra30_fuse_soc;
break;
#endif
#ifdef CONFIG_ARCH_TEGRA_114_SOC
case TEGRA114:
fuse->soc = &tegra114_fuse_soc;
break;
#endif
#ifdef CONFIG_ARCH_TEGRA_124_SOC
case TEGRA124:
fuse->soc = &tegra124_fuse_soc;
break;
#endif
default:
pr_warn("Unsupported SoC: %02x\n", chip);
break;
}
} else {
/*
* At this point we're not running on Tegra, so play
* nice with multi-platform kernels.
*/
return 0;
}
} else {
/*
* Extract information from the device tree if we've found a
* matching node.
*/
if (of_address_to_resource(np, 0, ®s) < 0) {
pr_err("failed to get FUSE register\n");
return -ENXIO;
}
fuse->soc = match->data;
}
np = of_find_matching_node(NULL, car_match);
if (np) {
void __iomem *base = of_iomap(np, 0);
of_node_put(np);
if (base) {
tegra_enable_fuse_clk(base);
iounmap(base);
} else {
pr_err("failed to map clock registers\n");
return -ENXIO;
}
}
fuse->base = ioremap(regs.start, resource_size(®s));
if (!fuse->base) {
pr_err("failed to map FUSE registers\n");
return -ENXIO;
}
fuse->soc->init(fuse);
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
tegra_revision_name[tegra_sku_info.revision],
tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
tegra_sku_info.soc_process_id);
pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
if (fuse->soc->lookups) {
size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups;
fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL);
if (fuse->lookups)
nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups);
}
return 0;
}
early_initcall(tegra_init_fuse);
#ifdef CONFIG_ARM64
static int __init tegra_init_soc(void)
{
struct device_node *np;
struct device *soc;
/* make sure we're running on Tegra */
np = of_find_matching_node(NULL, tegra_fuse_match);
if (!np)
return 0;
of_node_put(np);
soc = tegra_soc_device_register();
if (IS_ERR(soc)) {
pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
return PTR_ERR(soc);
}
return 0;
}
device_initcall(tegra_init_soc);
#endif
|
linux-master
|
drivers/soc/tegra/fuse/fuse-tegra.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/nvmem-consumer.h>
#include <linux/nvmem-provider.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/random.h>
#include <soc/tegra/fuse.h>
#include "fuse.h"
#define FUSE_BEGIN 0x100
/* Tegra30 and later */
#define FUSE_VENDOR_CODE 0x100
#define FUSE_FAB_CODE 0x104
#define FUSE_LOT_CODE_0 0x108
#define FUSE_LOT_CODE_1 0x10c
#define FUSE_WAFER_ID 0x110
#define FUSE_X_COORDINATE 0x114
#define FUSE_Y_COORDINATE 0x118
#define FUSE_HAS_REVISION_INFO BIT(0)
#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
defined(CONFIG_ARCH_TEGRA_114_SOC) || \
defined(CONFIG_ARCH_TEGRA_124_SOC) || \
defined(CONFIG_ARCH_TEGRA_132_SOC) || \
defined(CONFIG_ARCH_TEGRA_210_SOC) || \
defined(CONFIG_ARCH_TEGRA_186_SOC) || \
defined(CONFIG_ARCH_TEGRA_194_SOC) || \
defined(CONFIG_ARCH_TEGRA_234_SOC)
static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
{
if (WARN_ON(!fuse->base))
return 0;
return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
}
static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
{
u32 value;
int err;
err = pm_runtime_resume_and_get(fuse->dev);
if (err)
return 0;
value = readl_relaxed(fuse->base + FUSE_BEGIN + offset);
pm_runtime_put(fuse->dev);
return value;
}
static void __init tegra30_fuse_add_randomness(void)
{
u32 randomness[12];
randomness[0] = tegra_sku_info.sku_id;
randomness[1] = tegra_read_straps();
randomness[2] = tegra_read_chipid();
randomness[3] = tegra_sku_info.cpu_process_id << 16;
randomness[3] |= tegra_sku_info.soc_process_id;
randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
randomness[4] |= tegra_sku_info.soc_speedo_id;
randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE);
randomness[6] = tegra_fuse_read_early(FUSE_FAB_CODE);
randomness[7] = tegra_fuse_read_early(FUSE_LOT_CODE_0);
randomness[8] = tegra_fuse_read_early(FUSE_LOT_CODE_1);
randomness[9] = tegra_fuse_read_early(FUSE_WAFER_ID);
randomness[10] = tegra_fuse_read_early(FUSE_X_COORDINATE);
randomness[11] = tegra_fuse_read_early(FUSE_Y_COORDINATE);
add_device_randomness(randomness, sizeof(randomness));
}
static void __init tegra30_fuse_init(struct tegra_fuse *fuse)
{
fuse->read_early = tegra30_fuse_read_early;
fuse->read = tegra30_fuse_read;
tegra_init_revision();
if (fuse->soc->speedo_init)
fuse->soc->speedo_init(&tegra_sku_info);
tegra30_fuse_add_randomness();
}
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
static const struct tegra_fuse_info tegra30_fuse_info = {
.read = tegra30_fuse_read,
.size = 0x2a4,
.spare = 0x144,
};
const struct tegra_fuse_soc tegra30_fuse_soc = {
.init = tegra30_fuse_init,
.speedo_init = tegra30_init_speedo_data,
.info = &tegra30_fuse_info,
.soc_attr_group = &tegra_soc_attr_group,
.clk_suspend_on = false,
};
#endif
#ifdef CONFIG_ARCH_TEGRA_114_SOC
static const struct tegra_fuse_info tegra114_fuse_info = {
.read = tegra30_fuse_read,
.size = 0x2a0,
.spare = 0x180,
};
const struct tegra_fuse_soc tegra114_fuse_soc = {
.init = tegra30_fuse_init,
.speedo_init = tegra114_init_speedo_data,
.info = &tegra114_fuse_info,
.soc_attr_group = &tegra_soc_attr_group,
.clk_suspend_on = false,
};
#endif
#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
static const struct nvmem_cell_info tegra124_fuse_cells[] = {
{
.name = "tsensor-cpu1",
.offset = 0x084,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu2",
.offset = 0x088,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu0",
.offset = 0x098,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration",
.offset = 0x0f0,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu3",
.offset = 0x12c,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "sata-calibration",
.offset = 0x124,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-gpu",
.offset = 0x154,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-mem0",
.offset = 0x158,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-mem1",
.offset = 0x15c,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-pllx",
.offset = 0x160,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-common",
.offset = 0x180,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-realignment",
.offset = 0x1fc,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};
static const struct nvmem_cell_lookup tegra124_fuse_lookups[] = {
{
.nvmem_name = "fuse",
.cell_name = "xusb-pad-calibration",
.dev_id = "7009f000.padctl",
.con_id = "calibration",
}, {
.nvmem_name = "fuse",
.cell_name = "sata-calibration",
.dev_id = "70020000.sata",
.con_id = "calibration",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-common",
.dev_id = "700e2000.thermal-sensor",
.con_id = "common",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-realignment",
.dev_id = "700e2000.thermal-sensor",
.con_id = "realignment",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-cpu0",
.dev_id = "700e2000.thermal-sensor",
.con_id = "cpu0",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-cpu1",
.dev_id = "700e2000.thermal-sensor",
.con_id = "cpu1",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-cpu2",
.dev_id = "700e2000.thermal-sensor",
.con_id = "cpu2",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-cpu3",
.dev_id = "700e2000.thermal-sensor",
.con_id = "cpu3",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-mem0",
.dev_id = "700e2000.thermal-sensor",
.con_id = "mem0",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-mem1",
.dev_id = "700e2000.thermal-sensor",
.con_id = "mem1",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-gpu",
.dev_id = "700e2000.thermal-sensor",
.con_id = "gpu",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-pllx",
.dev_id = "700e2000.thermal-sensor",
.con_id = "pllx",
},
};
static const struct tegra_fuse_info tegra124_fuse_info = {
.read = tegra30_fuse_read,
.size = 0x300,
.spare = 0x200,
};
const struct tegra_fuse_soc tegra124_fuse_soc = {
.init = tegra30_fuse_init,
.speedo_init = tegra124_init_speedo_data,
.info = &tegra124_fuse_info,
.lookups = tegra124_fuse_lookups,
.num_lookups = ARRAY_SIZE(tegra124_fuse_lookups),
.cells = tegra124_fuse_cells,
.num_cells = ARRAY_SIZE(tegra124_fuse_cells),
.soc_attr_group = &tegra_soc_attr_group,
.clk_suspend_on = true,
};
#endif
#if defined(CONFIG_ARCH_TEGRA_210_SOC)
static const struct nvmem_cell_info tegra210_fuse_cells[] = {
{
.name = "tsensor-cpu1",
.offset = 0x084,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu2",
.offset = 0x088,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu0",
.offset = 0x098,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration",
.offset = 0x0f0,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-cpu3",
.offset = 0x12c,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "sata-calibration",
.offset = 0x124,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-gpu",
.offset = 0x154,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-mem0",
.offset = 0x158,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-mem1",
.offset = 0x15c,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-pllx",
.offset = 0x160,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-common",
.offset = 0x180,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-calibration",
.offset = 0x204,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration-ext",
.offset = 0x250,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};
static const struct nvmem_cell_lookup tegra210_fuse_lookups[] = {
{
.nvmem_name = "fuse",
.cell_name = "tsensor-cpu1",
.dev_id = "700e2000.thermal-sensor",
.con_id = "cpu1",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-cpu2",
.dev_id = "700e2000.thermal-sensor",
.con_id = "cpu2",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-cpu0",
.dev_id = "700e2000.thermal-sensor",
.con_id = "cpu0",
}, {
.nvmem_name = "fuse",
.cell_name = "xusb-pad-calibration",
.dev_id = "7009f000.padctl",
.con_id = "calibration",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-cpu3",
.dev_id = "700e2000.thermal-sensor",
.con_id = "cpu3",
}, {
.nvmem_name = "fuse",
.cell_name = "sata-calibration",
.dev_id = "70020000.sata",
.con_id = "calibration",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-gpu",
.dev_id = "700e2000.thermal-sensor",
.con_id = "gpu",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-mem0",
.dev_id = "700e2000.thermal-sensor",
.con_id = "mem0",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-mem1",
.dev_id = "700e2000.thermal-sensor",
.con_id = "mem1",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-pllx",
.dev_id = "700e2000.thermal-sensor",
.con_id = "pllx",
}, {
.nvmem_name = "fuse",
.cell_name = "tsensor-common",
.dev_id = "700e2000.thermal-sensor",
.con_id = "common",
}, {
.nvmem_name = "fuse",
.cell_name = "gpu-calibration",
.dev_id = "57000000.gpu",
.con_id = "calibration",
}, {
.nvmem_name = "fuse",
.cell_name = "xusb-pad-calibration-ext",
.dev_id = "7009f000.padctl",
.con_id = "calibration-ext",
},
};
static const struct tegra_fuse_info tegra210_fuse_info = {
.read = tegra30_fuse_read,
.size = 0x300,
.spare = 0x280,
};
const struct tegra_fuse_soc tegra210_fuse_soc = {
.init = tegra30_fuse_init,
.speedo_init = tegra210_init_speedo_data,
.info = &tegra210_fuse_info,
.lookups = tegra210_fuse_lookups,
.cells = tegra210_fuse_cells,
.num_cells = ARRAY_SIZE(tegra210_fuse_cells),
.num_lookups = ARRAY_SIZE(tegra210_fuse_lookups),
.soc_attr_group = &tegra_soc_attr_group,
.clk_suspend_on = false,
};
#endif
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
static const struct nvmem_cell_info tegra186_fuse_cells[] = {
{
.name = "xusb-pad-calibration",
.offset = 0x0f0,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration-ext",
.offset = 0x250,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};
static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = {
{
.nvmem_name = "fuse",
.cell_name = "xusb-pad-calibration",
.dev_id = "3520000.padctl",
.con_id = "calibration",
}, {
.nvmem_name = "fuse",
.cell_name = "xusb-pad-calibration-ext",
.dev_id = "3520000.padctl",
.con_id = "calibration-ext",
},
};
static const struct nvmem_keepout tegra186_fuse_keepouts[] = {
{ .start = 0x01c, .end = 0x0f0 },
{ .start = 0x138, .end = 0x198 },
{ .start = 0x1d8, .end = 0x250 },
{ .start = 0x280, .end = 0x290 },
{ .start = 0x340, .end = 0x344 }
};
static const struct tegra_fuse_info tegra186_fuse_info = {
.read = tegra30_fuse_read,
.size = 0x478,
.spare = 0x280,
};
const struct tegra_fuse_soc tegra186_fuse_soc = {
.init = tegra30_fuse_init,
.info = &tegra186_fuse_info,
.lookups = tegra186_fuse_lookups,
.num_lookups = ARRAY_SIZE(tegra186_fuse_lookups),
.cells = tegra186_fuse_cells,
.num_cells = ARRAY_SIZE(tegra186_fuse_cells),
.keepouts = tegra186_fuse_keepouts,
.num_keepouts = ARRAY_SIZE(tegra186_fuse_keepouts),
.soc_attr_group = &tegra_soc_attr_group,
.clk_suspend_on = false,
};
#endif
#if defined(CONFIG_ARCH_TEGRA_194_SOC)
static const struct nvmem_cell_info tegra194_fuse_cells[] = {
{
.name = "xusb-pad-calibration",
.offset = 0x0f0,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-gcplex-config-fuse",
.offset = 0x1c8,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration-ext",
.offset = 0x250,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-pdi0",
.offset = 0x300,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gpu-pdi1",
.offset = 0x304,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};
static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = {
{
.nvmem_name = "fuse",
.cell_name = "xusb-pad-calibration",
.dev_id = "3520000.padctl",
.con_id = "calibration",
}, {
.nvmem_name = "fuse",
.cell_name = "xusb-pad-calibration-ext",
.dev_id = "3520000.padctl",
.con_id = "calibration-ext",
}, {
.nvmem_name = "fuse",
.cell_name = "gpu-gcplex-config-fuse",
.dev_id = "17000000.gpu",
.con_id = "gcplex-config-fuse",
}, {
.nvmem_name = "fuse",
.cell_name = "gpu-pdi0",
.dev_id = "17000000.gpu",
.con_id = "pdi0",
}, {
.nvmem_name = "fuse",
.cell_name = "gpu-pdi1",
.dev_id = "17000000.gpu",
.con_id = "pdi1",
},
};
static const struct nvmem_keepout tegra194_fuse_keepouts[] = {
{ .start = 0x01c, .end = 0x0b8 },
{ .start = 0x12c, .end = 0x198 },
{ .start = 0x1a0, .end = 0x1bc },
{ .start = 0x1d8, .end = 0x250 },
{ .start = 0x270, .end = 0x290 },
{ .start = 0x310, .end = 0x45c }
};
static const struct tegra_fuse_info tegra194_fuse_info = {
.read = tegra30_fuse_read,
.size = 0x650,
.spare = 0x280,
};
const struct tegra_fuse_soc tegra194_fuse_soc = {
.init = tegra30_fuse_init,
.info = &tegra194_fuse_info,
.lookups = tegra194_fuse_lookups,
.num_lookups = ARRAY_SIZE(tegra194_fuse_lookups),
.cells = tegra194_fuse_cells,
.num_cells = ARRAY_SIZE(tegra194_fuse_cells),
.keepouts = tegra194_fuse_keepouts,
.num_keepouts = ARRAY_SIZE(tegra194_fuse_keepouts),
.soc_attr_group = &tegra194_soc_attr_group,
.clk_suspend_on = false,
};
#endif
#if defined(CONFIG_ARCH_TEGRA_234_SOC)
static const struct nvmem_cell_info tegra234_fuse_cells[] = {
{
.name = "xusb-pad-calibration",
.offset = 0x0f0,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "xusb-pad-calibration-ext",
.offset = 0x250,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};
static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = {
{
.nvmem_name = "fuse",
.cell_name = "xusb-pad-calibration",
.dev_id = "3520000.padctl",
.con_id = "calibration",
}, {
.nvmem_name = "fuse",
.cell_name = "xusb-pad-calibration-ext",
.dev_id = "3520000.padctl",
.con_id = "calibration-ext",
},
};
static const struct nvmem_keepout tegra234_fuse_keepouts[] = {
{ .start = 0x01c, .end = 0x0c8 },
{ .start = 0x12c, .end = 0x184 },
{ .start = 0x190, .end = 0x198 },
{ .start = 0x1a0, .end = 0x204 },
{ .start = 0x21c, .end = 0x250 },
{ .start = 0x25c, .end = 0x2f0 },
{ .start = 0x310, .end = 0x3d8 },
{ .start = 0x400, .end = 0x4f0 },
{ .start = 0x4f8, .end = 0x7e8 },
{ .start = 0x8d0, .end = 0x8d8 },
{ .start = 0xacc, .end = 0xf00 }
};
static const struct tegra_fuse_info tegra234_fuse_info = {
.read = tegra30_fuse_read,
.size = 0xf90,
.spare = 0x280,
};
const struct tegra_fuse_soc tegra234_fuse_soc = {
.init = tegra30_fuse_init,
.info = &tegra234_fuse_info,
.lookups = tegra234_fuse_lookups,
.num_lookups = ARRAY_SIZE(tegra234_fuse_lookups),
.cells = tegra234_fuse_cells,
.num_cells = ARRAY_SIZE(tegra234_fuse_cells),
.keepouts = tegra234_fuse_keepouts,
.num_keepouts = ARRAY_SIZE(tegra234_fuse_keepouts),
.soc_attr_group = &tegra194_soc_attr_group,
.clk_suspend_on = false,
};
#endif
|
linux-master
|
drivers/soc/tegra/fuse/fuse-tegra30.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/export.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <soc/tegra/common.h>
#include <soc/tegra/fuse.h>
#include "fuse.h"
#define FUSE_SKU_INFO 0x10
#define ERD_ERR_CONFIG 0x120c
#define ERD_MASK_INBAND_ERR 0x1
#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
static void __iomem *apbmisc_base;
static bool long_ram_code;
static u32 strapping;
static u32 chipid;
u32 tegra_read_chipid(void)
{
WARN(!chipid, "Tegra APB MISC not yet available\n");
return chipid;
}
u8 tegra_get_chip_id(void)
{
return (tegra_read_chipid() >> 8) & 0xff;
}
u8 tegra_get_major_rev(void)
{
return (tegra_read_chipid() >> 4) & 0xf;
}
u8 tegra_get_minor_rev(void)
{
return (tegra_read_chipid() >> 16) & 0xf;
}
u8 tegra_get_platform(void)
{
return (tegra_read_chipid() >> 20) & 0xf;
}
bool tegra_is_silicon(void)
{
switch (tegra_get_chip_id()) {
case TEGRA194:
case TEGRA234:
case TEGRA264:
if (tegra_get_platform() == 0)
return true;
return false;
}
/*
* Chips prior to Tegra194 have a different way of determining whether
* they are silicon or not. Since we never supported simulation on the
* older Tegra chips, don't bother extracting the information and just
* report that we're running on silicon.
*/
return true;
}
u32 tegra_read_straps(void)
{
WARN(!chipid, "Tegra ABP MISC not yet available\n");
return strapping;
}
u32 tegra_read_ram_code(void)
{
u32 straps = tegra_read_straps();
if (long_ram_code)
straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
else
straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
}
EXPORT_SYMBOL_GPL(tegra_read_ram_code);
/*
* The function sets ERD(Error Response Disable) bit.
* This allows to mask inband errors and always send an
* OKAY response from CBB to the master which caused error.
*/
int tegra194_miscreg_mask_serror(void)
{
if (!apbmisc_base)
return -EPROBE_DEFER;
if (!of_machine_is_compatible("nvidia,tegra194")) {
WARN(1, "Only supported for Tegra194 devices!\n");
return -EOPNOTSUPP;
}
writel_relaxed(ERD_MASK_INBAND_ERR,
apbmisc_base + ERD_ERR_CONFIG);
return 0;
}
EXPORT_SYMBOL(tegra194_miscreg_mask_serror);
static const struct of_device_id apbmisc_match[] __initconst = {
{ .compatible = "nvidia,tegra20-apbmisc", },
{ .compatible = "nvidia,tegra186-misc", },
{ .compatible = "nvidia,tegra194-misc", },
{ .compatible = "nvidia,tegra234-misc", },
{},
};
void __init tegra_init_revision(void)
{
u8 chip_id, minor_rev;
chip_id = tegra_get_chip_id();
minor_rev = tegra_get_minor_rev();
switch (minor_rev) {
case 1:
tegra_sku_info.revision = TEGRA_REVISION_A01;
break;
case 2:
tegra_sku_info.revision = TEGRA_REVISION_A02;
break;
case 3:
if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
tegra_fuse_read_spare(19)))
tegra_sku_info.revision = TEGRA_REVISION_A03p;
else
tegra_sku_info.revision = TEGRA_REVISION_A03;
break;
case 4:
tegra_sku_info.revision = TEGRA_REVISION_A04;
break;
default:
tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN;
}
tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
tegra_sku_info.platform = tegra_get_platform();
}
void __init tegra_init_apbmisc(void)
{
void __iomem *strapping_base;
struct resource apbmisc, straps;
struct device_node *np;
np = of_find_matching_node(NULL, apbmisc_match);
if (!np) {
/*
* Fall back to legacy initialization for 32-bit ARM only. All
* 64-bit ARM device tree files for Tegra are required to have
* an APBMISC node.
*
* This is for backwards-compatibility with old device trees
* that didn't contain an APBMISC node.
*/
if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
/* APBMISC registers (chip revision, ...) */
apbmisc.start = 0x70000800;
apbmisc.end = 0x70000863;
apbmisc.flags = IORESOURCE_MEM;
/* strapping options */
if (of_machine_is_compatible("nvidia,tegra124")) {
straps.start = 0x7000e864;
straps.end = 0x7000e867;
} else {
straps.start = 0x70000008;
straps.end = 0x7000000b;
}
straps.flags = IORESOURCE_MEM;
pr_warn("Using APBMISC region %pR\n", &apbmisc);
pr_warn("Using strapping options registers %pR\n",
&straps);
} else {
/*
* At this point we're not running on Tegra, so play
* nice with multi-platform kernels.
*/
return;
}
} else {
/*
* Extract information from the device tree if we've found a
* matching node.
*/
if (of_address_to_resource(np, 0, &apbmisc) < 0) {
pr_err("failed to get APBMISC registers\n");
goto put;
}
if (of_address_to_resource(np, 1, &straps) < 0) {
pr_err("failed to get strapping options registers\n");
goto put;
}
}
apbmisc_base = ioremap(apbmisc.start, resource_size(&apbmisc));
if (!apbmisc_base) {
pr_err("failed to map APBMISC registers\n");
} else {
chipid = readl_relaxed(apbmisc_base + 4);
}
strapping_base = ioremap(straps.start, resource_size(&straps));
if (!strapping_base) {
pr_err("failed to map strapping options registers\n");
} else {
strapping = readl_relaxed(strapping_base);
iounmap(strapping_base);
}
long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
put:
of_node_put(np);
}
|
linux-master
|
drivers/soc/tegra/fuse/tegra-apbmisc.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include <soc/tegra/fuse.h>
#include "fuse.h"
#define CPU_PROCESS_CORNERS 2
#define GPU_PROCESS_CORNERS 2
#define SOC_PROCESS_CORNERS 3
#define FUSE_CPU_SPEEDO_0 0x014
#define FUSE_CPU_SPEEDO_1 0x02c
#define FUSE_CPU_SPEEDO_2 0x030
#define FUSE_SOC_SPEEDO_0 0x034
#define FUSE_SOC_SPEEDO_1 0x038
#define FUSE_SOC_SPEEDO_2 0x03c
#define FUSE_CPU_IDDQ 0x018
#define FUSE_SOC_IDDQ 0x040
#define FUSE_GPU_IDDQ 0x128
#define FUSE_FT_REV 0x028
enum {
THRESHOLD_INDEX_0,
THRESHOLD_INDEX_1,
THRESHOLD_INDEX_COUNT,
};
static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
{ 2119, UINT_MAX },
{ 2119, UINT_MAX },
};
static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = {
{ UINT_MAX, UINT_MAX },
{ UINT_MAX, UINT_MAX },
};
static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
{ 1950, 2100, UINT_MAX },
{ 1950, 2100, UINT_MAX },
};
static u8 __init get_speedo_revision(void)
{
return tegra_fuse_read_spare(4) << 2 |
tegra_fuse_read_spare(3) << 1 |
tegra_fuse_read_spare(2) << 0;
}
static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
u8 speedo_rev, int *threshold)
{
int sku = sku_info->sku_id;
/* Assign to default */
sku_info->cpu_speedo_id = 0;
sku_info->soc_speedo_id = 0;
sku_info->gpu_speedo_id = 0;
*threshold = THRESHOLD_INDEX_0;
switch (sku) {
case 0x00: /* Engineering SKU */
case 0x01: /* Engineering SKU */
case 0x07:
case 0x17:
case 0x27:
if (speedo_rev >= 2)
sku_info->gpu_speedo_id = 1;
break;
case 0x13:
if (speedo_rev >= 2)
sku_info->gpu_speedo_id = 1;
sku_info->cpu_speedo_id = 1;
break;
default:
pr_err("Tegra210: unknown SKU %#04x\n", sku);
/* Using the default for the error case */
break;
}
}
static int get_process_id(int value, const u32 *speedos, unsigned int num)
{
unsigned int i;
for (i = 0; i < num; i++)
if (value < speedos[i])
return i;
return -EINVAL;
}
void __init tegra210_init_speedo_data(struct tegra_sku_info *sku_info)
{
int cpu_speedo[3], soc_speedo[3];
unsigned int index;
u8 speedo_revision;
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
THRESHOLD_INDEX_COUNT);
BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
THRESHOLD_INDEX_COUNT);
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
THRESHOLD_INDEX_COUNT);
/* Read speedo/IDDQ fuses */
cpu_speedo[0] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
cpu_speedo[1] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_1);
cpu_speedo[2] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
soc_speedo[0] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
soc_speedo[1] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_1);
soc_speedo[2] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_2);
/*
* Determine CPU, GPU and SoC speedo values depending on speedo fusing
* revision. Note that GPU speedo value is fused in CPU_SPEEDO_2.
*/
speedo_revision = get_speedo_revision();
pr_info("Speedo Revision %u\n", speedo_revision);
if (speedo_revision >= 3) {
sku_info->cpu_speedo_value = cpu_speedo[0];
sku_info->gpu_speedo_value = cpu_speedo[2];
sku_info->soc_speedo_value = soc_speedo[0];
} else if (speedo_revision == 2) {
sku_info->cpu_speedo_value = (-1938 + (1095 * cpu_speedo[0] / 100)) / 10;
sku_info->gpu_speedo_value = (-1662 + (1082 * cpu_speedo[2] / 100)) / 10;
sku_info->soc_speedo_value = ( -705 + (1037 * soc_speedo[0] / 100)) / 10;
} else {
sku_info->cpu_speedo_value = 2100;
sku_info->gpu_speedo_value = cpu_speedo[2] - 75;
sku_info->soc_speedo_value = 1900;
}
if ((sku_info->cpu_speedo_value <= 0) ||
(sku_info->gpu_speedo_value <= 0) ||
(sku_info->soc_speedo_value <= 0)) {
WARN(1, "speedo value not fused\n");
return;
}
rev_sku_to_speedo_ids(sku_info, speedo_revision, &index);
sku_info->gpu_process_id = get_process_id(sku_info->gpu_speedo_value,
gpu_process_speedos[index],
GPU_PROCESS_CORNERS);
sku_info->cpu_process_id = get_process_id(sku_info->cpu_speedo_value,
cpu_process_speedos[index],
CPU_PROCESS_CORNERS);
sku_info->soc_process_id = get_process_id(sku_info->soc_speedo_value,
soc_process_speedos[index],
SOC_PROCESS_CORNERS);
pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",
sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);
}
|
linux-master
|
drivers/soc/tegra/fuse/speedo-tegra210.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/bug.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <soc/tegra/fuse.h>
#include "fuse.h"
#define SOC_PROCESS_CORNERS 2
#define CPU_PROCESS_CORNERS 2
enum {
THRESHOLD_INDEX_0,
THRESHOLD_INDEX_1,
THRESHOLD_INDEX_COUNT,
};
static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
{1123, UINT_MAX},
{0, UINT_MAX},
};
static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
{1695, UINT_MAX},
{0, UINT_MAX},
};
static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
int *threshold)
{
u32 tmp;
u32 sku = sku_info->sku_id;
enum tegra_revision rev = sku_info->revision;
switch (sku) {
case 0x00:
case 0x10:
case 0x05:
case 0x06:
sku_info->cpu_speedo_id = 1;
sku_info->soc_speedo_id = 0;
*threshold = THRESHOLD_INDEX_0;
break;
case 0x03:
case 0x04:
sku_info->cpu_speedo_id = 2;
sku_info->soc_speedo_id = 1;
*threshold = THRESHOLD_INDEX_1;
break;
default:
pr_err("Tegra Unknown SKU %d\n", sku);
sku_info->cpu_speedo_id = 0;
sku_info->soc_speedo_id = 0;
*threshold = THRESHOLD_INDEX_0;
break;
}
if (rev == TEGRA_REVISION_A01) {
tmp = tegra_fuse_read_early(0x270) << 1;
tmp |= tegra_fuse_read_early(0x26c);
if (!tmp)
sku_info->cpu_speedo_id = 0;
}
}
void __init tegra114_init_speedo_data(struct tegra_sku_info *sku_info)
{
u32 cpu_speedo_val;
u32 soc_speedo_val;
int threshold;
int i;
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
THRESHOLD_INDEX_COUNT);
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
THRESHOLD_INDEX_COUNT);
rev_sku_to_speedo_ids(sku_info, &threshold);
cpu_speedo_val = tegra_fuse_read_early(0x12c) + 1024;
soc_speedo_val = tegra_fuse_read_early(0x134);
for (i = 0; i < CPU_PROCESS_CORNERS; i++)
if (cpu_speedo_val < cpu_process_speedos[threshold][i])
break;
sku_info->cpu_process_id = i;
for (i = 0; i < SOC_PROCESS_CORNERS; i++)
if (soc_speedo_val < soc_process_speedos[threshold][i])
break;
sku_info->soc_process_id = i;
}
|
linux-master
|
drivers/soc/tegra/fuse/speedo-tegra114.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
*
* The driver handles Error's from Control Backbone(CBB) version 2.0.
* generated due to illegal accesses. The driver prints debug information
* about failed transaction on receiving interrupt from Error Notifier.
* Error types supported by CBB2.0 are:
* UNSUPPORTED_ERR, PWRDOWN_ERR, TIMEOUT_ERR, FIREWALL_ERR, DECODE_ERR,
* SLAVE_ERR
*/
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/cpufeature.h>
#include <linux/debugfs.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/tegra-cbb.h>
#define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
#define FABRIC_EN_CFG_STATUS_0_0 0x40
#define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
#define FABRIC_EN_CFG_ADDR_LOW_0 0x80
#define FABRIC_EN_CFG_ADDR_HI_0 0x84
#define FABRIC_MN_MASTER_ERR_EN_0 0x200
#define FABRIC_MN_MASTER_ERR_FORCE_0 0x204
#define FABRIC_MN_MASTER_ERR_STATUS_0 0x208
#define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c
#define FABRIC_MN_MASTER_LOG_ERR_STATUS_0 0x300
#define FABRIC_MN_MASTER_LOG_ADDR_LOW_0 0x304
#define FABRIC_MN_MASTER_LOG_ADDR_HIGH_0 0x308
#define FABRIC_MN_MASTER_LOG_ATTRIBUTES0_0 0x30c
#define FABRIC_MN_MASTER_LOG_ATTRIBUTES1_0 0x310
#define FABRIC_MN_MASTER_LOG_ATTRIBUTES2_0 0x314
#define FABRIC_MN_MASTER_LOG_USER_BITS0_0 0x318
#define AXI_SLV_TIMEOUT_STATUS_0_0 0x8
#define APB_BLOCK_TMO_STATUS_0 0xc00
#define APB_BLOCK_NUM_TMO_OFFSET 0x20
#define FAB_EM_EL_MSTRID GENMASK(29, 24)
#define FAB_EM_EL_VQC GENMASK(17, 16)
#define FAB_EM_EL_GRPSEC GENMASK(14, 8)
#define FAB_EM_EL_FALCONSEC GENMASK(1, 0)
#define FAB_EM_EL_FABID GENMASK(20, 16)
#define FAB_EM_EL_SLAVEID GENMASK(7, 0)
#define FAB_EM_EL_ACCESSID GENMASK(7, 0)
#define FAB_EM_EL_AXCACHE GENMASK(27, 24)
#define FAB_EM_EL_AXPROT GENMASK(22, 20)
#define FAB_EM_EL_BURSTLENGTH GENMASK(19, 12)
#define FAB_EM_EL_BURSTTYPE GENMASK(9, 8)
#define FAB_EM_EL_BEATSIZE GENMASK(6, 4)
#define FAB_EM_EL_ACCESSTYPE GENMASK(0, 0)
#define USRBITS_MSTR_ID GENMASK(29, 24)
#define REQ_SOCKET_ID GENMASK(27, 24)
#define CCPLEX_MSTRID 0x1
#define FIREWALL_APERTURE_SZ 0x10000
/* Write firewall check enable */
#define WEN 0x20000
enum tegra234_cbb_fabric_ids {
CBB_FAB_ID,
SCE_FAB_ID,
RCE_FAB_ID,
DCE_FAB_ID,
AON_FAB_ID,
PSC_FAB_ID,
BPMP_FAB_ID,
FSI_FAB_ID,
MAX_FAB_ID,
};
struct tegra234_slave_lookup {
const char *name;
unsigned int offset;
};
struct tegra234_cbb_fabric {
const char *name;
phys_addr_t off_mask_erd;
phys_addr_t firewall_base;
unsigned int firewall_ctl;
unsigned int firewall_wr_ctl;
const char * const *master_id;
unsigned int notifier_offset;
const struct tegra_cbb_error *errors;
const int max_errors;
const struct tegra234_slave_lookup *slave_map;
const int max_slaves;
};
struct tegra234_cbb {
struct tegra_cbb base;
const struct tegra234_cbb_fabric *fabric;
struct resource *res;
void __iomem *regs;
int num_intr;
int sec_irq;
/* record */
void __iomem *mon;
unsigned int type;
u32 mask;
u64 access;
u32 mn_attr0;
u32 mn_attr1;
u32 mn_attr2;
u32 mn_user_bits;
};
static inline struct tegra234_cbb *to_tegra234_cbb(struct tegra_cbb *cbb)
{
return container_of(cbb, struct tegra234_cbb, base);
}
static LIST_HEAD(cbb_list);
static DEFINE_SPINLOCK(cbb_lock);
static bool
tegra234_cbb_write_access_allowed(struct platform_device *pdev, struct tegra234_cbb *cbb)
{
u32 val;
if (!cbb->fabric->firewall_base ||
!cbb->fabric->firewall_ctl ||
!cbb->fabric->firewall_wr_ctl) {
dev_info(&pdev->dev, "SoC data missing for firewall\n");
return false;
}
if ((cbb->fabric->firewall_ctl > FIREWALL_APERTURE_SZ) ||
(cbb->fabric->firewall_wr_ctl > FIREWALL_APERTURE_SZ)) {
dev_err(&pdev->dev, "wrong firewall offset value\n");
return false;
}
val = readl(cbb->regs + cbb->fabric->firewall_base + cbb->fabric->firewall_ctl);
/*
* If the firewall check feature for allowing or blocking the
* write accesses through the firewall of a fabric is disabled
* then CCPLEX can write to the registers of that fabric.
*/
if (!(val & WEN))
return true;
/*
* If the firewall check is enabled then check whether CCPLEX
* has write access to the fabric's error notifier registers
*/
val = readl(cbb->regs + cbb->fabric->firewall_base + cbb->fabric->firewall_wr_ctl);
if (val & (BIT(CCPLEX_MSTRID)))
return true;
return false;
}
static void tegra234_cbb_fault_enable(struct tegra_cbb *cbb)
{
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
void __iomem *addr;
addr = priv->regs + priv->fabric->notifier_offset;
writel(0x1ff, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0);
dsb(sy);
}
static void tegra234_cbb_error_clear(struct tegra_cbb *cbb)
{
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
writel(0x3f, priv->mon + FABRIC_MN_MASTER_ERR_STATUS_0);
dsb(sy);
}
static u32 tegra234_cbb_get_status(struct tegra_cbb *cbb)
{
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
void __iomem *addr;
u32 value;
addr = priv->regs + priv->fabric->notifier_offset;
value = readl(addr + FABRIC_EN_CFG_STATUS_0_0);
dsb(sy);
return value;
}
static void tegra234_cbb_mask_serror(struct tegra234_cbb *cbb)
{
writel(0x1, cbb->regs + cbb->fabric->off_mask_erd);
dsb(sy);
}
static u32 tegra234_cbb_get_tmo_slv(void __iomem *addr)
{
u32 timeout;
timeout = readl(addr);
return timeout;
}
static void tegra234_cbb_tmo_slv(struct seq_file *file, const char *slave, void __iomem *addr,
u32 status)
{
tegra_cbb_print_err(file, "\t %s : %#x\n", slave, status);
}
static void tegra234_cbb_lookup_apbslv(struct seq_file *file, const char *slave,
void __iomem *base)
{
unsigned int block = 0;
void __iomem *addr;
char name[64];
u32 status;
status = tegra234_cbb_get_tmo_slv(base);
if (status)
tegra_cbb_print_err(file, "\t %s_BLOCK_TMO_STATUS : %#x\n", slave, status);
while (status) {
if (status & BIT(0)) {
u32 timeout, clients, client = 0;
addr = base + APB_BLOCK_NUM_TMO_OFFSET + (block * 4);
timeout = tegra234_cbb_get_tmo_slv(addr);
clients = timeout;
while (timeout) {
if (timeout & BIT(0)) {
if (clients != 0xffffffff)
clients &= BIT(client);
sprintf(name, "%s_BLOCK%d_TMO", slave, block);
tegra234_cbb_tmo_slv(file, name, addr, clients);
}
timeout >>= 1;
client++;
}
}
status >>= 1;
block++;
}
}
static void tegra234_lookup_slave_timeout(struct seq_file *file, struct tegra234_cbb *cbb,
u8 slave_id, u8 fab_id)
{
const struct tegra234_slave_lookup *map = cbb->fabric->slave_map;
void __iomem *addr;
/*
* 1) Get slave node name and address mapping using slave_id.
* 2) Check if the timed out slave node is APB or AXI.
* 3) If AXI, then print timeout register and reset axi slave
* using <FABRIC>_SN_<>_SLV_TIMEOUT_STATUS_0_0 register.
* 4) If APB, then perform an additional lookup to find the client
* which timed out.
* a) Get block number from the index of set bit in
* <FABRIC>_SN_AXI2APB_<>_BLOCK_TMO_STATUS_0 register.
* b) Get address of register repective to block number i.e.
* <FABRIC>_SN_AXI2APB_<>_BLOCK<index-set-bit>_TMO_0.
* c) Read the register in above step to get client_id which
* timed out as per the set bits.
* d) Reset the timedout client and print details.
* e) Goto step-a till all bits are set.
*/
addr = cbb->regs + map[slave_id].offset;
if (strstr(map[slave_id].name, "AXI2APB")) {
addr += APB_BLOCK_TMO_STATUS_0;
tegra234_cbb_lookup_apbslv(file, map[slave_id].name, addr);
} else {
char name[64];
u32 status;
addr += AXI_SLV_TIMEOUT_STATUS_0_0;
status = tegra234_cbb_get_tmo_slv(addr);
if (status) {
sprintf(name, "%s_SLV_TIMEOUT_STATUS", map[slave_id].name);
tegra234_cbb_tmo_slv(file, name, addr, status);
}
}
}
static void tegra234_cbb_print_error(struct seq_file *file, struct tegra234_cbb *cbb, u32 status,
u32 overflow)
{
unsigned int type = 0;
if (status & (status - 1))
tegra_cbb_print_err(file, "\t Multiple type of errors reported\n");
while (status) {
if (type >= cbb->fabric->max_errors) {
tegra_cbb_print_err(file, "\t Wrong type index:%u, status:%u\n",
type, status);
return;
}
if (status & 0x1)
tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
cbb->fabric->errors[type].code);
status >>= 1;
type++;
}
type = 0;
while (overflow) {
if (type >= cbb->fabric->max_errors) {
tegra_cbb_print_err(file, "\t Wrong type index:%u, overflow:%u\n",
type, overflow);
return;
}
if (overflow & 0x1)
tegra_cbb_print_err(file, "\t Overflow\t\t: Multiple %s\n",
cbb->fabric->errors[type].code);
overflow >>= 1;
type++;
}
}
static void print_errlog_err(struct seq_file *file, struct tegra234_cbb *cbb)
{
u8 cache_type, prot_type, burst_length, mstr_id, grpsec, vqc, falconsec, beat_size;
u8 access_type, access_id, requester_socket_id, local_socket_id, slave_id, fab_id;
char fabric_name[20];
bool is_numa = false;
u8 burst_type;
if (num_possible_nodes() > 1)
is_numa = true;
mstr_id = FIELD_GET(FAB_EM_EL_MSTRID, cbb->mn_user_bits);
vqc = FIELD_GET(FAB_EM_EL_VQC, cbb->mn_user_bits);
grpsec = FIELD_GET(FAB_EM_EL_GRPSEC, cbb->mn_user_bits);
falconsec = FIELD_GET(FAB_EM_EL_FALCONSEC, cbb->mn_user_bits);
/*
* For SOC with multiple NUMA nodes, print cross socket access
* errors only if initiator/master_id is CCPLEX, CPMU or GPU.
*/
if (is_numa) {
local_socket_id = numa_node_id();
requester_socket_id = FIELD_GET(REQ_SOCKET_ID, cbb->mn_attr2);
if (requester_socket_id != local_socket_id) {
if ((mstr_id != 0x1) && (mstr_id != 0x2) && (mstr_id != 0xB))
return;
}
}
fab_id = FIELD_GET(FAB_EM_EL_FABID, cbb->mn_attr2);
slave_id = FIELD_GET(FAB_EM_EL_SLAVEID, cbb->mn_attr2);
access_id = FIELD_GET(FAB_EM_EL_ACCESSID, cbb->mn_attr1);
cache_type = FIELD_GET(FAB_EM_EL_AXCACHE, cbb->mn_attr0);
prot_type = FIELD_GET(FAB_EM_EL_AXPROT, cbb->mn_attr0);
burst_length = FIELD_GET(FAB_EM_EL_BURSTLENGTH, cbb->mn_attr0);
burst_type = FIELD_GET(FAB_EM_EL_BURSTTYPE, cbb->mn_attr0);
beat_size = FIELD_GET(FAB_EM_EL_BEATSIZE, cbb->mn_attr0);
access_type = FIELD_GET(FAB_EM_EL_ACCESSTYPE, cbb->mn_attr0);
tegra_cbb_print_err(file, "\n");
if (cbb->type < cbb->fabric->max_errors)
tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
cbb->fabric->errors[cbb->type].code);
else
tegra_cbb_print_err(file, "\t Wrong type index:%u\n", cbb->type);
tegra_cbb_print_err(file, "\t MASTER_ID\t\t: %s\n", cbb->fabric->master_id[mstr_id]);
tegra_cbb_print_err(file, "\t Address\t\t: %#llx\n", cbb->access);
tegra_cbb_print_cache(file, cache_type);
tegra_cbb_print_prot(file, prot_type);
tegra_cbb_print_err(file, "\t Access_Type\t\t: %s", (access_type) ? "Write\n" : "Read\n");
tegra_cbb_print_err(file, "\t Access_ID\t\t: %#x", access_id);
if (fab_id == PSC_FAB_ID)
strcpy(fabric_name, "psc-fabric");
else if (fab_id == FSI_FAB_ID)
strcpy(fabric_name, "fsi-fabric");
else
strcpy(fabric_name, cbb->fabric->name);
if (is_numa) {
tegra_cbb_print_err(file, "\t Requester_Socket_Id\t: %#x\n",
requester_socket_id);
tegra_cbb_print_err(file, "\t Local_Socket_Id\t: %#x\n",
local_socket_id);
tegra_cbb_print_err(file, "\t No. of NUMA_NODES\t: %#x\n",
num_possible_nodes());
}
tegra_cbb_print_err(file, "\t Fabric\t\t: %s\n", fabric_name);
tegra_cbb_print_err(file, "\t Slave_Id\t\t: %#x\n", slave_id);
tegra_cbb_print_err(file, "\t Burst_length\t\t: %#x\n", burst_length);
tegra_cbb_print_err(file, "\t Burst_type\t\t: %#x\n", burst_type);
tegra_cbb_print_err(file, "\t Beat_size\t\t: %#x\n", beat_size);
tegra_cbb_print_err(file, "\t VQC\t\t\t: %#x\n", vqc);
tegra_cbb_print_err(file, "\t GRPSEC\t\t: %#x\n", grpsec);
tegra_cbb_print_err(file, "\t FALCONSEC\t\t: %#x\n", falconsec);
if ((fab_id == PSC_FAB_ID) || (fab_id == FSI_FAB_ID))
return;
if (slave_id >= cbb->fabric->max_slaves) {
tegra_cbb_print_err(file, "\t Invalid slave_id:%d\n", slave_id);
return;
}
if (!strcmp(cbb->fabric->errors[cbb->type].code, "TIMEOUT_ERR")) {
tegra234_lookup_slave_timeout(file, cbb, slave_id, fab_id);
return;
}
tegra_cbb_print_err(file, "\t Slave\t\t\t: %s\n", cbb->fabric->slave_map[slave_id].name);
}
static int print_errmonX_info(struct seq_file *file, struct tegra234_cbb *cbb)
{
u32 overflow, status, error;
status = readl(cbb->mon + FABRIC_MN_MASTER_ERR_STATUS_0);
if (!status) {
pr_err("Error Notifier received a spurious notification\n");
return -ENODATA;
}
if (status == 0xffffffff) {
pr_err("CBB registers returning all 1's which is invalid\n");
return -EINVAL;
}
overflow = readl(cbb->mon + FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0);
tegra234_cbb_print_error(file, cbb, status, overflow);
error = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ERR_STATUS_0);
if (!error) {
pr_info("Error Monitor doesn't have Error Logger\n");
return -EINVAL;
}
cbb->type = 0;
while (error) {
if (error & BIT(0)) {
u32 hi, lo;
hi = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ADDR_HIGH_0);
lo = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ADDR_LOW_0);
cbb->access = (u64)hi << 32 | lo;
cbb->mn_attr0 = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ATTRIBUTES0_0);
cbb->mn_attr1 = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ATTRIBUTES1_0);
cbb->mn_attr2 = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ATTRIBUTES2_0);
cbb->mn_user_bits = readl(cbb->mon + FABRIC_MN_MASTER_LOG_USER_BITS0_0);
print_errlog_err(file, cbb);
}
cbb->type++;
error >>= 1;
}
return 0;
}
static int print_err_notifier(struct seq_file *file, struct tegra234_cbb *cbb, u32 status)
{
unsigned int index = 0;
int err;
pr_crit("**************************************\n");
pr_crit("CPU:%d, Error:%s, Errmon:%d\n", smp_processor_id(),
cbb->fabric->name, status);
while (status) {
if (status & BIT(0)) {
unsigned int notifier = cbb->fabric->notifier_offset;
u32 hi, lo, mask = BIT(index);
phys_addr_t addr;
u64 offset;
writel(mask, cbb->regs + notifier + FABRIC_EN_CFG_ADDR_INDEX_0_0);
hi = readl(cbb->regs + notifier + FABRIC_EN_CFG_ADDR_HI_0);
lo = readl(cbb->regs + notifier + FABRIC_EN_CFG_ADDR_LOW_0);
addr = (u64)hi << 32 | lo;
offset = addr - cbb->res->start;
cbb->mon = cbb->regs + offset;
cbb->mask = BIT(index);
err = print_errmonX_info(file, cbb);
tegra234_cbb_error_clear(&cbb->base);
if (err)
return err;
}
status >>= 1;
index++;
}
tegra_cbb_print_err(file, "\t**************************************\n");
return 0;
}
#ifdef CONFIG_DEBUG_FS
static DEFINE_MUTEX(cbb_debugfs_mutex);
static int tegra234_cbb_debugfs_show(struct tegra_cbb *cbb, struct seq_file *file, void *data)
{
int err = 0;
mutex_lock(&cbb_debugfs_mutex);
list_for_each_entry(cbb, &cbb_list, node) {
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
u32 status;
status = tegra_cbb_get_status(&priv->base);
if (status) {
err = print_err_notifier(file, priv, status);
if (err)
break;
}
}
mutex_unlock(&cbb_debugfs_mutex);
return err;
}
#endif
/*
* Handler for CBB errors
*/
static irqreturn_t tegra234_cbb_isr(int irq, void *data)
{
bool is_inband_err = false;
struct tegra_cbb *cbb;
unsigned long flags;
u8 mstr_id;
int err;
spin_lock_irqsave(&cbb_lock, flags);
list_for_each_entry(cbb, &cbb_list, node) {
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
u32 status = tegra_cbb_get_status(cbb);
if (status && (irq == priv->sec_irq)) {
tegra_cbb_print_err(NULL, "CPU:%d, Error: %s@0x%llx, irq=%d\n",
smp_processor_id(), priv->fabric->name,
priv->res->start, irq);
err = print_err_notifier(NULL, priv, status);
if (err)
goto unlock;
/*
* If illegal request is from CCPLEX(id:0x1) master then call WARN()
*/
if (priv->fabric->off_mask_erd) {
mstr_id = FIELD_GET(USRBITS_MSTR_ID, priv->mn_user_bits);
if (mstr_id == CCPLEX_MSTRID)
is_inband_err = 1;
}
}
}
unlock:
spin_unlock_irqrestore(&cbb_lock, flags);
WARN_ON(is_inband_err);
return IRQ_HANDLED;
}
/*
* Register handler for CBB_SECURE interrupt for reporting errors
*/
static int tegra234_cbb_interrupt_enable(struct tegra_cbb *cbb)
{
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
if (priv->sec_irq) {
int err = devm_request_irq(cbb->dev, priv->sec_irq, tegra234_cbb_isr, 0,
dev_name(cbb->dev), priv);
if (err) {
dev_err(cbb->dev, "failed to register interrupt %u: %d\n", priv->sec_irq,
err);
return err;
}
}
return 0;
}
static void tegra234_cbb_error_enable(struct tegra_cbb *cbb)
{
tegra_cbb_fault_enable(cbb);
}
static const struct tegra_cbb_ops tegra234_cbb_ops = {
.get_status = tegra234_cbb_get_status,
.error_clear = tegra234_cbb_error_clear,
.fault_enable = tegra234_cbb_fault_enable,
.error_enable = tegra234_cbb_error_enable,
.interrupt_enable = tegra234_cbb_interrupt_enable,
#ifdef CONFIG_DEBUG_FS
.debugfs_show = tegra234_cbb_debugfs_show,
#endif
};
static const char * const tegra234_master_id[] = {
[0x00] = "TZ",
[0x01] = "CCPLEX",
[0x02] = "CCPMU",
[0x03] = "BPMP_FW",
[0x04] = "AON",
[0x05] = "SCE",
[0x06] = "GPCDMA_P",
[0x07] = "TSECA_NONSECURE",
[0x08] = "TSECA_LIGHTSECURE",
[0x09] = "TSECA_HEAVYSECURE",
[0x0a] = "CORESIGHT",
[0x0b] = "APE",
[0x0c] = "PEATRANS",
[0x0d] = "JTAGM_DFT",
[0x0e] = "RCE",
[0x0f] = "DCE",
[0x10] = "PSC_FW_USER",
[0x11] = "PSC_FW_SUPERVISOR",
[0x12] = "PSC_FW_MACHINE",
[0x13] = "PSC_BOOT",
[0x14] = "BPMP_BOOT",
[0x15] = "NVDEC_NONSECURE",
[0x16] = "NVDEC_LIGHTSECURE",
[0x17] = "NVDEC_HEAVYSECURE",
[0x18] = "CBB_INTERNAL",
[0x19] = "RSVD"
};
static const struct tegra_cbb_error tegra234_cbb_errors[] = {
{
.code = "SLAVE_ERR",
.desc = "Slave being accessed responded with an error"
}, {
.code = "DECODE_ERR",
.desc = "Attempt to access an address hole"
}, {
.code = "FIREWALL_ERR",
.desc = "Attempt to access a region which is firewall protected"
}, {
.code = "TIMEOUT_ERR",
.desc = "No response returned by slave"
}, {
.code = "PWRDOWN_ERR",
.desc = "Attempt to access a portion of fabric that is powered down"
}, {
.code = "UNSUPPORTED_ERR",
.desc = "Attempt to access a slave through an unsupported access"
}
};
static const struct tegra234_slave_lookup tegra234_aon_slave_map[] = {
{ "AXI2APB", 0x00000 },
{ "AST", 0x14000 },
{ "CBB", 0x15000 },
{ "CPU", 0x16000 },
};
static const struct tegra234_cbb_fabric tegra234_aon_fabric = {
.name = "aon-fabric",
.master_id = tegra234_master_id,
.slave_map = tegra234_aon_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_aon_slave_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x17000,
.firewall_base = 0x30000,
.firewall_ctl = 0x8d0,
.firewall_wr_ctl = 0x8c8,
};
static const struct tegra234_slave_lookup tegra234_bpmp_slave_map[] = {
{ "AXI2APB", 0x00000 },
{ "AST0", 0x15000 },
{ "AST1", 0x16000 },
{ "CBB", 0x17000 },
{ "CPU", 0x18000 },
};
static const struct tegra234_cbb_fabric tegra234_bpmp_fabric = {
.name = "bpmp-fabric",
.master_id = tegra234_master_id,
.slave_map = tegra234_bpmp_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_bpmp_slave_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x8f0,
.firewall_wr_ctl = 0x8e8,
};
static const struct tegra234_slave_lookup tegra234_cbb_slave_map[] = {
{ "AON", 0x40000 },
{ "BPMP", 0x41000 },
{ "CBB", 0x42000 },
{ "HOST1X", 0x43000 },
{ "STM", 0x44000 },
{ "FSI", 0x45000 },
{ "PSC", 0x46000 },
{ "PCIE_C1", 0x47000 },
{ "PCIE_C2", 0x48000 },
{ "PCIE_C3", 0x49000 },
{ "PCIE_C0", 0x4a000 },
{ "PCIE_C4", 0x4b000 },
{ "GPU", 0x4c000 },
{ "SMMU0", 0x4d000 },
{ "SMMU1", 0x4e000 },
{ "SMMU2", 0x4f000 },
{ "SMMU3", 0x50000 },
{ "SMMU4", 0x51000 },
{ "PCIE_C10", 0x52000 },
{ "PCIE_C7", 0x53000 },
{ "PCIE_C8", 0x54000 },
{ "PCIE_C9", 0x55000 },
{ "PCIE_C5", 0x56000 },
{ "PCIE_C6", 0x57000 },
{ "DCE", 0x58000 },
{ "RCE", 0x59000 },
{ "SCE", 0x5a000 },
{ "AXI2APB_1", 0x70000 },
{ "AXI2APB_10", 0x71000 },
{ "AXI2APB_11", 0x72000 },
{ "AXI2APB_12", 0x73000 },
{ "AXI2APB_13", 0x74000 },
{ "AXI2APB_14", 0x75000 },
{ "AXI2APB_15", 0x76000 },
{ "AXI2APB_16", 0x77000 },
{ "AXI2APB_17", 0x78000 },
{ "AXI2APB_18", 0x79000 },
{ "AXI2APB_19", 0x7a000 },
{ "AXI2APB_2", 0x7b000 },
{ "AXI2APB_20", 0x7c000 },
{ "AXI2APB_21", 0x7d000 },
{ "AXI2APB_22", 0x7e000 },
{ "AXI2APB_23", 0x7f000 },
{ "AXI2APB_25", 0x80000 },
{ "AXI2APB_26", 0x81000 },
{ "AXI2APB_27", 0x82000 },
{ "AXI2APB_28", 0x83000 },
{ "AXI2APB_29", 0x84000 },
{ "AXI2APB_30", 0x85000 },
{ "AXI2APB_31", 0x86000 },
{ "AXI2APB_32", 0x87000 },
{ "AXI2APB_33", 0x88000 },
{ "AXI2APB_34", 0x89000 },
{ "AXI2APB_35", 0x92000 },
{ "AXI2APB_4", 0x8b000 },
{ "AXI2APB_5", 0x8c000 },
{ "AXI2APB_6", 0x8d000 },
{ "AXI2APB_7", 0x8e000 },
{ "AXI2APB_8", 0x8f000 },
{ "AXI2APB_9", 0x90000 },
{ "AXI2APB_3", 0x91000 },
};
static const struct tegra234_cbb_fabric tegra234_cbb_fabric = {
.name = "cbb-fabric",
.master_id = tegra234_master_id,
.slave_map = tegra234_cbb_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_cbb_slave_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x60000,
.off_mask_erd = 0x3a004,
.firewall_base = 0x10000,
.firewall_ctl = 0x23f0,
.firewall_wr_ctl = 0x23e8,
};
static const struct tegra234_slave_lookup tegra234_common_slave_map[] = {
{ "AXI2APB", 0x00000 },
{ "AST0", 0x15000 },
{ "AST1", 0x16000 },
{ "CBB", 0x17000 },
{ "RSVD", 0x00000 },
{ "CPU", 0x18000 },
};
static const struct tegra234_cbb_fabric tegra234_dce_fabric = {
.name = "dce-fabric",
.master_id = tegra234_master_id,
.slave_map = tegra234_common_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_common_slave_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x290,
.firewall_wr_ctl = 0x288,
};
static const struct tegra234_cbb_fabric tegra234_rce_fabric = {
.name = "rce-fabric",
.master_id = tegra234_master_id,
.slave_map = tegra234_common_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_common_slave_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x290,
.firewall_wr_ctl = 0x288,
};
static const struct tegra234_cbb_fabric tegra234_sce_fabric = {
.name = "sce-fabric",
.master_id = tegra234_master_id,
.slave_map = tegra234_common_slave_map,
.max_slaves = ARRAY_SIZE(tegra234_common_slave_map),
.errors = tegra234_cbb_errors,
.max_errors = ARRAY_SIZE(tegra234_cbb_errors),
.notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x290,
.firewall_wr_ctl = 0x288,
};
static const char * const tegra241_master_id[] = {
[0x0] = "TZ",
[0x1] = "CCPLEX",
[0x2] = "CCPMU",
[0x3] = "BPMP_FW",
[0x4] = "PSC_FW_USER",
[0x5] = "PSC_FW_SUPERVISOR",
[0x6] = "PSC_FW_MACHINE",
[0x7] = "PSC_BOOT",
[0x8] = "BPMP_BOOT",
[0x9] = "JTAGM_DFT",
[0xa] = "CORESIGHT",
[0xb] = "GPU",
[0xc] = "PEATRANS",
[0xd ... 0x3f] = "RSVD"
};
/*
* Possible causes for Slave and Timeout errors.
* SLAVE_ERR:
* Slave being accessed responded with an error. Slave could return
* an error for various cases :
* Unsupported access, clamp setting when power gated, register
* level firewall(SCR), address hole within the slave, etc
*
* TIMEOUT_ERR:
* No response returned by slave. Can be due to slave being clock
* gated, under reset, powered down or slave inability to respond
* for an internal slave issue
*/
static const struct tegra_cbb_error tegra241_cbb_errors[] = {
{
.code = "SLAVE_ERR",
.desc = "Slave being accessed responded with an error."
}, {
.code = "DECODE_ERR",
.desc = "Attempt to access an address hole or Reserved region of memory."
}, {
.code = "FIREWALL_ERR",
.desc = "Attempt to access a region which is firewalled."
}, {
.code = "TIMEOUT_ERR",
.desc = "No response returned by slave."
}, {
.code = "PWRDOWN_ERR",
.desc = "Attempt to access a portion of the fabric that is powered down."
}, {
.code = "UNSUPPORTED_ERR",
.desc = "Attempt to access a slave through an unsupported access."
}, {
.code = "POISON_ERR",
.desc = "Slave responds with poison error to indicate error in data."
}, {
.code = "RSVD"
}, {
.code = "RSVD"
}, {
.code = "RSVD"
}, {
.code = "RSVD"
}, {
.code = "RSVD"
}, {
.code = "RSVD"
}, {
.code = "RSVD"
}, {
.code = "RSVD"
}, {
.code = "RSVD"
}, {
.code = "NO_SUCH_ADDRESS_ERR",
.desc = "The address belongs to the pri_target range but there is no register "
"implemented at the address."
}, {
.code = "TASK_ERR",
.desc = "Attempt to update a PRI task when the current task has still not "
"completed."
}, {
.code = "EXTERNAL_ERR",
.desc = "Indicates that an external PRI register access met with an error due to "
"any issue in the unit."
}, {
.code = "INDEX_ERR",
.desc = "Applicable to PRI index aperture pair, when the programmed index is "
"outside the range defined in the manual."
}, {
.code = "RESET_ERR",
.desc = "Target in Reset Error: Attempt to access a SubPri or external PRI "
"register but they are in reset."
}, {
.code = "REGISTER_RST_ERR",
.desc = "Attempt to access a PRI register but the register is partial or "
"completely in reset."
}, {
.code = "POWER_GATED_ERR",
.desc = "Returned by external PRI client when the external access goes to a power "
"gated domain."
}, {
.code = "SUBPRI_FS_ERR",
.desc = "Subpri is floorswept: Attempt to access a subpri through the main pri "
"target but subPri logic is floorswept."
}, {
.code = "SUBPRI_CLK_OFF_ERR",
.desc = "Subpri clock is off: Attempt to access a subpri through the main pri "
"target but subPris clock is gated/off."
},
};
static const struct tegra234_slave_lookup tegra241_cbb_slave_map[] = {
{ "RSVD", 0x00000 },
{ "PCIE_C8", 0x51000 },
{ "PCIE_C9", 0x52000 },
{ "RSVD", 0x00000 },
{ "RSVD", 0x00000 },
{ "RSVD", 0x00000 },
{ "RSVD", 0x00000 },
{ "RSVD", 0x00000 },
{ "RSVD", 0x00000 },
{ "RSVD", 0x00000 },
{ "RSVD", 0x00000 },
{ "AON", 0x5b000 },
{ "BPMP", 0x5c000 },
{ "RSVD", 0x00000 },
{ "RSVD", 0x00000 },
{ "PSC", 0x5d000 },
{ "STM", 0x5e000 },
{ "AXI2APB_1", 0x70000 },
{ "AXI2APB_10", 0x71000 },
{ "AXI2APB_11", 0x72000 },
{ "AXI2APB_12", 0x73000 },
{ "AXI2APB_13", 0x74000 },
{ "AXI2APB_14", 0x75000 },
{ "AXI2APB_15", 0x76000 },
{ "AXI2APB_16", 0x77000 },
{ "AXI2APB_17", 0x78000 },
{ "AXI2APB_18", 0x79000 },
{ "AXI2APB_19", 0x7a000 },
{ "AXI2APB_2", 0x7b000 },
{ "AXI2APB_20", 0x7c000 },
{ "AXI2APB_4", 0x87000 },
{ "AXI2APB_5", 0x88000 },
{ "AXI2APB_6", 0x89000 },
{ "AXI2APB_7", 0x8a000 },
{ "AXI2APB_8", 0x8b000 },
{ "AXI2APB_9", 0x8c000 },
{ "AXI2APB_3", 0x8d000 },
{ "AXI2APB_21", 0x7d000 },
{ "AXI2APB_22", 0x7e000 },
{ "AXI2APB_23", 0x7f000 },
{ "AXI2APB_24", 0x80000 },
{ "AXI2APB_25", 0x81000 },
{ "AXI2APB_26", 0x82000 },
{ "AXI2APB_27", 0x83000 },
{ "AXI2APB_28", 0x84000 },
{ "PCIE_C4", 0x53000 },
{ "PCIE_C5", 0x54000 },
{ "PCIE_C6", 0x55000 },
{ "PCIE_C7", 0x56000 },
{ "PCIE_C2", 0x57000 },
{ "PCIE_C3", 0x58000 },
{ "PCIE_C0", 0x59000 },
{ "PCIE_C1", 0x5a000 },
{ "CCPLEX", 0x50000 },
{ "AXI2APB_29", 0x85000 },
{ "AXI2APB_30", 0x86000 },
{ "CBB_CENTRAL", 0x00000 },
{ "AXI2APB_31", 0x8E000 },
{ "AXI2APB_32", 0x8F000 },
};
static const struct tegra234_cbb_fabric tegra241_cbb_fabric = {
.name = "cbb-fabric",
.master_id = tegra241_master_id,
.slave_map = tegra241_cbb_slave_map,
.max_slaves = ARRAY_SIZE(tegra241_cbb_slave_map),
.errors = tegra241_cbb_errors,
.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
.notifier_offset = 0x60000,
.off_mask_erd = 0x40004,
.firewall_base = 0x20000,
.firewall_ctl = 0x2370,
.firewall_wr_ctl = 0x2368,
};
static const struct tegra234_slave_lookup tegra241_bpmp_slave_map[] = {
{ "RSVD", 0x00000 },
{ "RSVD", 0x00000 },
{ "RSVD", 0x00000 },
{ "CBB", 0x15000 },
{ "CPU", 0x16000 },
{ "AXI2APB", 0x00000 },
{ "DBB0", 0x17000 },
{ "DBB1", 0x18000 },
};
static const struct tegra234_cbb_fabric tegra241_bpmp_fabric = {
.name = "bpmp-fabric",
.master_id = tegra241_master_id,
.slave_map = tegra241_bpmp_slave_map,
.max_slaves = ARRAY_SIZE(tegra241_bpmp_slave_map),
.errors = tegra241_cbb_errors,
.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
.notifier_offset = 0x19000,
.firewall_base = 0x30000,
.firewall_ctl = 0x8f0,
.firewall_wr_ctl = 0x8e8,
};
static const struct of_device_id tegra234_cbb_dt_ids[] = {
{ .compatible = "nvidia,tegra234-cbb-fabric", .data = &tegra234_cbb_fabric },
{ .compatible = "nvidia,tegra234-aon-fabric", .data = &tegra234_aon_fabric },
{ .compatible = "nvidia,tegra234-bpmp-fabric", .data = &tegra234_bpmp_fabric },
{ .compatible = "nvidia,tegra234-dce-fabric", .data = &tegra234_dce_fabric },
{ .compatible = "nvidia,tegra234-rce-fabric", .data = &tegra234_rce_fabric },
{ .compatible = "nvidia,tegra234-sce-fabric", .data = &tegra234_sce_fabric },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, tegra234_cbb_dt_ids);
struct tegra234_cbb_acpi_uid {
const char *hid;
const char *uid;
const struct tegra234_cbb_fabric *fabric;
};
static const struct tegra234_cbb_acpi_uid tegra234_cbb_acpi_uids[] = {
{ "NVDA1070", "1", &tegra241_cbb_fabric },
{ "NVDA1070", "2", &tegra241_bpmp_fabric },
{ },
};
static const struct
tegra234_cbb_fabric *tegra234_cbb_acpi_get_fabric(struct acpi_device *adev)
{
const struct tegra234_cbb_acpi_uid *entry;
for (entry = tegra234_cbb_acpi_uids; entry->hid; entry++) {
if (acpi_dev_hid_uid_match(adev, entry->hid, entry->uid))
return entry->fabric;
}
return NULL;
}
static const struct acpi_device_id tegra241_cbb_acpi_ids[] = {
{ "NVDA1070" },
{ },
};
MODULE_DEVICE_TABLE(acpi, tegra241_cbb_acpi_ids);
static int tegra234_cbb_probe(struct platform_device *pdev)
{
const struct tegra234_cbb_fabric *fabric;
struct tegra234_cbb *cbb;
unsigned long flags = 0;
int err;
if (pdev->dev.of_node) {
fabric = of_device_get_match_data(&pdev->dev);
} else {
struct acpi_device *device = ACPI_COMPANION(&pdev->dev);
if (!device)
return -ENODEV;
fabric = tegra234_cbb_acpi_get_fabric(device);
if (!fabric) {
dev_err(&pdev->dev, "no device match found\n");
return -ENODEV;
}
}
cbb = devm_kzalloc(&pdev->dev, sizeof(*cbb), GFP_KERNEL);
if (!cbb)
return -ENOMEM;
INIT_LIST_HEAD(&cbb->base.node);
cbb->base.ops = &tegra234_cbb_ops;
cbb->base.dev = &pdev->dev;
cbb->fabric = fabric;
cbb->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &cbb->res);
if (IS_ERR(cbb->regs))
return PTR_ERR(cbb->regs);
err = tegra_cbb_get_irq(pdev, NULL, &cbb->sec_irq);
if (err)
return err;
platform_set_drvdata(pdev, cbb);
/*
* Don't enable error reporting for a Fabric if write to it's registers
* is blocked by CBB firewall.
*/
if (!tegra234_cbb_write_access_allowed(pdev, cbb)) {
dev_info(&pdev->dev, "error reporting not enabled due to firewall\n");
return 0;
}
spin_lock_irqsave(&cbb_lock, flags);
list_add(&cbb->base.node, &cbb_list);
spin_unlock_irqrestore(&cbb_lock, flags);
/* set ERD bit to mask SError and generate interrupt to report error */
if (cbb->fabric->off_mask_erd)
tegra234_cbb_mask_serror(cbb);
return tegra_cbb_register(&cbb->base);
}
static int __maybe_unused tegra234_cbb_resume_noirq(struct device *dev)
{
struct tegra234_cbb *cbb = dev_get_drvdata(dev);
tegra234_cbb_error_enable(&cbb->base);
dev_dbg(dev, "%s resumed\n", cbb->fabric->name);
return 0;
}
static const struct dev_pm_ops tegra234_cbb_pm = {
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, tegra234_cbb_resume_noirq)
};
static struct platform_driver tegra234_cbb_driver = {
.probe = tegra234_cbb_probe,
.driver = {
.name = "tegra234-cbb",
.of_match_table = tegra234_cbb_dt_ids,
.acpi_match_table = tegra241_cbb_acpi_ids,
.pm = &tegra234_cbb_pm,
},
};
static int __init tegra234_cbb_init(void)
{
return platform_driver_register(&tegra234_cbb_driver);
}
pure_initcall(tegra234_cbb_init);
static void __exit tegra234_cbb_exit(void)
{
platform_driver_unregister(&tegra234_cbb_driver);
}
module_exit(tegra234_cbb_exit);
MODULE_DESCRIPTION("Control Backbone 2.0 error handling driver for Tegra234");
|
linux-master
|
drivers/soc/tegra/cbb/tegra234-cbb.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
*
* The driver handles Error's from Control Backbone(CBB) generated due to
* illegal accesses. When an error is reported from a NOC within CBB,
* the driver checks ErrVld status of all three Error Logger's of that NOC.
* It then prints debug information about failed transaction using ErrLog
* registers of error logger which has ErrVld set. Currently, SLV, DEC,
* TMO, SEC, UNS are the codes which are supported by CBB.
*/
#include <linux/clk.h>
#include <linux/cpufeature.h>
#include <linux/debugfs.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/tegra-cbb.h>
#define ERRLOGGER_0_ID_COREID_0 0x00000000
#define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
#define ERRLOGGER_0_FAULTEN_0 0x00000008
#define ERRLOGGER_0_ERRVLD_0 0x0000000c
#define ERRLOGGER_0_ERRCLR_0 0x00000010
#define ERRLOGGER_0_ERRLOG0_0 0x00000014
#define ERRLOGGER_0_ERRLOG1_0 0x00000018
#define ERRLOGGER_0_RSVD_00_0 0x0000001c
#define ERRLOGGER_0_ERRLOG3_0 0x00000020
#define ERRLOGGER_0_ERRLOG4_0 0x00000024
#define ERRLOGGER_0_ERRLOG5_0 0x00000028
#define ERRLOGGER_0_STALLEN_0 0x00000038
#define ERRLOGGER_1_ID_COREID_0 0x00000080
#define ERRLOGGER_1_ID_REVISIONID_0 0x00000084
#define ERRLOGGER_1_FAULTEN_0 0x00000088
#define ERRLOGGER_1_ERRVLD_0 0x0000008c
#define ERRLOGGER_1_ERRCLR_0 0x00000090
#define ERRLOGGER_1_ERRLOG0_0 0x00000094
#define ERRLOGGER_1_ERRLOG1_0 0x00000098
#define ERRLOGGER_1_RSVD_00_0 0x0000009c
#define ERRLOGGER_1_ERRLOG3_0 0x000000a0
#define ERRLOGGER_1_ERRLOG4_0 0x000000a4
#define ERRLOGGER_1_ERRLOG5_0 0x000000a8
#define ERRLOGGER_1_STALLEN_0 0x000000b8
#define ERRLOGGER_2_ID_COREID_0 0x00000100
#define ERRLOGGER_2_ID_REVISIONID_0 0x00000104
#define ERRLOGGER_2_FAULTEN_0 0x00000108
#define ERRLOGGER_2_ERRVLD_0 0x0000010c
#define ERRLOGGER_2_ERRCLR_0 0x00000110
#define ERRLOGGER_2_ERRLOG0_0 0x00000114
#define ERRLOGGER_2_ERRLOG1_0 0x00000118
#define ERRLOGGER_2_RSVD_00_0 0x0000011c
#define ERRLOGGER_2_ERRLOG3_0 0x00000120
#define ERRLOGGER_2_ERRLOG4_0 0x00000124
#define ERRLOGGER_2_ERRLOG5_0 0x00000128
#define ERRLOGGER_2_STALLEN_0 0x00000138
#define CBB_NOC_INITFLOW GENMASK(23, 20)
#define CBB_NOC_TARGFLOW GENMASK(19, 16)
#define CBB_NOC_TARG_SUBRANGE GENMASK(15, 9)
#define CBB_NOC_SEQID GENMASK(8, 0)
#define BPMP_NOC_INITFLOW GENMASK(20, 18)
#define BPMP_NOC_TARGFLOW GENMASK(17, 13)
#define BPMP_NOC_TARG_SUBRANGE GENMASK(12, 9)
#define BPMP_NOC_SEQID GENMASK(8, 0)
#define AON_NOC_INITFLOW GENMASK(22, 21)
#define AON_NOC_TARGFLOW GENMASK(20, 15)
#define AON_NOC_TARG_SUBRANGE GENMASK(14, 9)
#define AON_NOC_SEQID GENMASK(8, 0)
#define SCE_NOC_INITFLOW GENMASK(21, 19)
#define SCE_NOC_TARGFLOW GENMASK(18, 14)
#define SCE_NOC_TARG_SUBRANGE GENMASK(13, 9)
#define SCE_NOC_SEQID GENMASK(8, 0)
#define CBB_NOC_AXCACHE GENMASK(3, 0)
#define CBB_NOC_NON_MOD GENMASK(4, 4)
#define CBB_NOC_AXPROT GENMASK(7, 5)
#define CBB_NOC_FALCONSEC GENMASK(9, 8)
#define CBB_NOC_GRPSEC GENMASK(16, 10)
#define CBB_NOC_VQC GENMASK(18, 17)
#define CBB_NOC_MSTR_ID GENMASK(22, 19)
#define CBB_NOC_AXI_ID GENMASK(30, 23)
#define CLUSTER_NOC_AXCACHE GENMASK(3, 0)
#define CLUSTER_NOC_AXPROT GENMASK(6, 4)
#define CLUSTER_NOC_FALCONSEC GENMASK(8, 7)
#define CLUSTER_NOC_GRPSEC GENMASK(15, 9)
#define CLUSTER_NOC_VQC GENMASK(17, 16)
#define CLUSTER_NOC_MSTR_ID GENMASK(21, 18)
#define CBB_ERR_OPC GENMASK(4, 1)
#define CBB_ERR_ERRCODE GENMASK(10, 8)
#define CBB_ERR_LEN1 GENMASK(27, 16)
#define DMAAPB_X_RAW_INTERRUPT_STATUS 0x2ec
struct tegra194_cbb_packet_header {
bool lock; // [0]
u8 opc; // [4:1]
u8 errcode; // [10:8]= RD, RDW, RDL, RDX, WR, WRW, WRC, PRE, URG
u16 len1; // [27:16]
bool format; // [31] = 1 -> FlexNoC versions 2.7 & above
};
struct tegra194_cbb_aperture {
u8 initflow;
u8 targflow;
u8 targ_subrange;
u8 init_mapping;
u32 init_localaddress;
u8 targ_mapping;
u32 targ_localaddress;
u16 seqid;
};
struct tegra194_cbb_userbits {
u8 axcache;
u8 non_mod;
u8 axprot;
u8 falconsec;
u8 grpsec;
u8 vqc;
u8 mstr_id;
u8 axi_id;
};
struct tegra194_cbb_noc_data {
const char *name;
bool erd_mask_inband_err;
const char * const *master_id;
unsigned int max_aperture;
const struct tegra194_cbb_aperture *noc_aperture;
const char * const *routeid_initflow;
const char * const *routeid_targflow;
void (*parse_routeid)(struct tegra194_cbb_aperture *info, u64 routeid);
void (*parse_userbits)(struct tegra194_cbb_userbits *usrbits, u32 elog_5);
};
struct tegra194_axi2apb_bridge {
struct resource res;
void __iomem *base;
};
struct tegra194_cbb {
struct tegra_cbb base;
const struct tegra194_cbb_noc_data *noc;
struct resource *res;
void __iomem *regs;
unsigned int num_intr;
unsigned int sec_irq;
unsigned int nonsec_irq;
u32 errlog0;
u32 errlog1;
u32 errlog2;
u32 errlog3;
u32 errlog4;
u32 errlog5;
struct tegra194_axi2apb_bridge *bridges;
unsigned int num_bridges;
};
static inline struct tegra194_cbb *to_tegra194_cbb(struct tegra_cbb *cbb)
{
return container_of(cbb, struct tegra194_cbb, base);
}
static LIST_HEAD(cbb_list);
static DEFINE_SPINLOCK(cbb_lock);
static const char * const tegra194_cbb_trantype[] = {
"RD - Read, Incrementing",
"RDW - Read, Wrap", /* Not Supported */
"RDX - Exclusive Read", /* Not Supported */
"RDL - Linked Read", /* Not Supported */
"WR - Write, Incrementing",
"WRW - Write, Wrap", /* Not Supported */
"WRC - Exclusive Write", /* Not Supported */
"PRE - Preamble Sequence for Fixed Accesses"
};
static const char * const tegra194_axi2apb_error[] = {
"SFIFONE - Status FIFO Not Empty interrupt",
"SFIFOF - Status FIFO Full interrupt",
"TIM - Timer(Timeout) interrupt",
"SLV - SLVERR interrupt",
"NULL",
"ERBF - Early response buffer Full interrupt",
"NULL",
"RDFIFOF - Read Response FIFO Full interrupt",
"WRFIFOF - Write Response FIFO Full interrupt",
"CH0DFIFOF - Ch0 Data FIFO Full interrupt",
"CH1DFIFOF - Ch1 Data FIFO Full interrupt",
"CH2DFIFOF - Ch2 Data FIFO Full interrupt",
"UAT - Unsupported alignment type error",
"UBS - Unsupported burst size error",
"UBE - Unsupported Byte Enable error",
"UBT - Unsupported burst type error",
"BFS - Block Firewall security error",
"ARFS - Address Range Firewall security error",
"CH0RFIFOF - Ch0 Request FIFO Full interrupt",
"CH1RFIFOF - Ch1 Request FIFO Full interrupt",
"CH2RFIFOF - Ch2 Request FIFO Full interrupt"
};
static const char * const tegra194_master_id[] = {
[0x0] = "CCPLEX",
[0x1] = "CCPLEX_DPMU",
[0x2] = "BPMP",
[0x3] = "AON",
[0x4] = "SCE",
[0x5] = "GPCDMA_PERIPHERAL",
[0x6] = "TSECA",
[0x7] = "TSECB",
[0x8] = "JTAGM_DFT",
[0x9] = "CORESIGHT_AXIAP",
[0xa] = "APE",
[0xb] = "PEATR",
[0xc] = "NVDEC",
[0xd] = "RCE",
[0xe] = "NVDEC1"
};
static const struct tegra_cbb_error tegra194_cbb_errors[] = {
{
.code = "SLV",
.source = "Target",
.desc = "Target error detected by CBB slave"
}, {
.code = "DEC",
.source = "Initiator NIU",
.desc = "Address decode error"
}, {
.code = "UNS",
.source = "Target NIU",
.desc = "Unsupported request. Not a valid transaction"
}, {
.code = "DISC", /* Not Supported by CBB */
.source = "Power Disconnect",
.desc = "Disconnected target or domain"
}, {
.code = "SEC",
.source = "Initiator NIU or Firewall",
.desc = "Security violation. Firewall error"
}, {
.code = "HIDE", /* Not Supported by CBB */
.source = "Firewall",
.desc = "Hidden security violation, reported as OK to initiator"
}, {
.code = "TMO",
.source = "Target NIU",
.desc = "Target time-out error"
}, {
.code = "RSV",
.source = "None",
.desc = "Reserved"
}
};
/*
* CBB NOC aperture lookup table as per file "cbb_central_noc_Structure.info".
*/
static const char * const tegra194_cbbcentralnoc_routeid_initflow[] = {
[0x0] = "aon_p2ps/I/aon",
[0x1] = "ape_p2ps/I/ape_p2ps",
[0x2] = "bpmp_p2ps/I/bpmp_p2ps",
[0x3] = "ccroc_p2ps/I/ccroc_p2ps",
[0x4] = "csite_p2ps/I/0",
[0x5] = "gpcdma_mmio_p2ps/I/0",
[0x6] = "jtag_p2ps/I/0",
[0x7] = "nvdec1_p2ps/I/0",
[0x8] = "nvdec_p2ps/I/0",
[0x9] = "rce_p2ps/I/rce_p2ps",
[0xa] = "sce_p2ps/I/sce_p2ps",
[0xb] = "tseca_p2ps/I/0",
[0xc] = "tsecb_p2ps/I/0",
[0xd] = "RESERVED",
[0xe] = "RESERVED",
[0xf] = "RESERVED"
};
static const char * const tegra194_cbbcentralnoc_routeid_targflow[] = {
[0x0] = "SVC/T/intreg",
[0x1] = "axis_satellite_axi2apb_p2pm/T/axis_satellite_axi2apb_p2pm",
[0x2] = "axis_satellite_grout/T/axis_satellite_grout",
[0x3] = "cbb_firewall/T/cbb_firewall",
[0x4] = "gpu_p2pm/T/gpu_p2pm",
[0x5] = "host1x_p2pm/T/host1x_p2pm",
[0x6] = "sapb_3_p2pm/T/sapb_3_p2pm",
[0x7] = "smmu0_p2pm/T/smmu0_p2pm",
[0x8] = "smmu1_p2pm/T/smmu1_p2pm",
[0x9] = "smmu2_p2pm/T/smmu2_p2pm",
[0xa] = "stm_p2pm/T/stm_p2pm",
[0xb] = "RESERVED",
[0xc] = "RESERVED",
[0xd] = "RESERVED",
[0xe] = "RESERVED",
[0xf] = "RESERVED"
};
/*
* Fields of CBB NOC lookup table:
* Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
* Targ mapping, Targ localAddress
* ----------------------------------------------------------------------------
*/
static const struct tegra194_cbb_aperture tegra194_cbbcentralnoc_apert_lookup[] = {
{ 0x0, 0x0, 0x00, 0x0, 0x02300000, 0, 0x00000000 },
{ 0x0, 0x1, 0x00, 0x0, 0x02003000, 0, 0x02003000 },
{ 0x0, 0x1, 0x01, 0x0, 0x02006000, 2, 0x02006000 },
{ 0x0, 0x1, 0x02, 0x0, 0x02016000, 3, 0x02016000 },
{ 0x0, 0x1, 0x03, 0x0, 0x0201d000, 4, 0x0201d000 },
{ 0x0, 0x1, 0x04, 0x0, 0x0202b000, 6, 0x0202b000 },
{ 0x0, 0x1, 0x05, 0x0, 0x02434000, 20, 0x02434000 },
{ 0x0, 0x1, 0x06, 0x0, 0x02436000, 21, 0x02436000 },
{ 0x0, 0x1, 0x07, 0x0, 0x02438000, 22, 0x02438000 },
{ 0x0, 0x1, 0x08, 0x0, 0x02445000, 24, 0x02445000 },
{ 0x0, 0x1, 0x09, 0x0, 0x02446000, 25, 0x02446000 },
{ 0x0, 0x1, 0x0a, 0x0, 0x02004000, 1, 0x02004000 },
{ 0x0, 0x1, 0x0b, 0x0, 0x0201e000, 5, 0x0201e000 },
{ 0x0, 0x1, 0x0c, 0x0, 0x0202c000, 7, 0x0202c000 },
{ 0x0, 0x1, 0x0d, 0x0, 0x02204000, 8, 0x02204000 },
{ 0x0, 0x1, 0x0e, 0x0, 0x02214000, 9, 0x02214000 },
{ 0x0, 0x1, 0x0f, 0x0, 0x02224000, 10, 0x02224000 },
{ 0x0, 0x1, 0x10, 0x0, 0x02234000, 11, 0x02234000 },
{ 0x0, 0x1, 0x11, 0x0, 0x02244000, 12, 0x02244000 },
{ 0x0, 0x1, 0x12, 0x0, 0x02254000, 13, 0x02254000 },
{ 0x0, 0x1, 0x13, 0x0, 0x02264000, 14, 0x02264000 },
{ 0x0, 0x1, 0x14, 0x0, 0x02274000, 15, 0x02274000 },
{ 0x0, 0x1, 0x15, 0x0, 0x02284000, 16, 0x02284000 },
{ 0x0, 0x1, 0x16, 0x0, 0x0243a000, 23, 0x0243a000 },
{ 0x0, 0x1, 0x17, 0x0, 0x02370000, 17, 0x02370000 },
{ 0x0, 0x1, 0x18, 0x0, 0x023d0000, 18, 0x023d0000 },
{ 0x0, 0x1, 0x19, 0x0, 0x023e0000, 19, 0x023e0000 },
{ 0x0, 0x1, 0x1a, 0x0, 0x02450000, 26, 0x02450000 },
{ 0x0, 0x1, 0x1b, 0x0, 0x02460000, 27, 0x02460000 },
{ 0x0, 0x1, 0x1c, 0x0, 0x02490000, 28, 0x02490000 },
{ 0x0, 0x1, 0x1d, 0x0, 0x03130000, 31, 0x03130000 },
{ 0x0, 0x1, 0x1e, 0x0, 0x03160000, 32, 0x03160000 },
{ 0x0, 0x1, 0x1f, 0x0, 0x03270000, 33, 0x03270000 },
{ 0x0, 0x1, 0x20, 0x0, 0x032e0000, 35, 0x032e0000 },
{ 0x0, 0x1, 0x21, 0x0, 0x03300000, 36, 0x03300000 },
{ 0x0, 0x1, 0x22, 0x0, 0x13090000, 40, 0x13090000 },
{ 0x0, 0x1, 0x23, 0x0, 0x20120000, 43, 0x20120000 },
{ 0x0, 0x1, 0x24, 0x0, 0x20170000, 44, 0x20170000 },
{ 0x0, 0x1, 0x25, 0x0, 0x20190000, 45, 0x20190000 },
{ 0x0, 0x1, 0x26, 0x0, 0x201b0000, 46, 0x201b0000 },
{ 0x0, 0x1, 0x27, 0x0, 0x20250000, 47, 0x20250000 },
{ 0x0, 0x1, 0x28, 0x0, 0x20260000, 48, 0x20260000 },
{ 0x0, 0x1, 0x29, 0x0, 0x20420000, 49, 0x20420000 },
{ 0x0, 0x1, 0x2a, 0x0, 0x20460000, 50, 0x20460000 },
{ 0x0, 0x1, 0x2b, 0x0, 0x204f0000, 51, 0x204f0000 },
{ 0x0, 0x1, 0x2c, 0x0, 0x20520000, 52, 0x20520000 },
{ 0x0, 0x1, 0x2d, 0x0, 0x20580000, 53, 0x20580000 },
{ 0x0, 0x1, 0x2e, 0x0, 0x205a0000, 54, 0x205a0000 },
{ 0x0, 0x1, 0x2f, 0x0, 0x205c0000, 55, 0x205c0000 },
{ 0x0, 0x1, 0x30, 0x0, 0x20690000, 56, 0x20690000 },
{ 0x0, 0x1, 0x31, 0x0, 0x20770000, 57, 0x20770000 },
{ 0x0, 0x1, 0x32, 0x0, 0x20790000, 58, 0x20790000 },
{ 0x0, 0x1, 0x33, 0x0, 0x20880000, 59, 0x20880000 },
{ 0x0, 0x1, 0x34, 0x0, 0x20990000, 62, 0x20990000 },
{ 0x0, 0x1, 0x35, 0x0, 0x20e10000, 65, 0x20e10000 },
{ 0x0, 0x1, 0x36, 0x0, 0x20e70000, 66, 0x20e70000 },
{ 0x0, 0x1, 0x37, 0x0, 0x20e80000, 67, 0x20e80000 },
{ 0x0, 0x1, 0x38, 0x0, 0x20f30000, 68, 0x20f30000 },
{ 0x0, 0x1, 0x39, 0x0, 0x20f50000, 69, 0x20f50000 },
{ 0x0, 0x1, 0x3a, 0x0, 0x20fc0000, 70, 0x20fc0000 },
{ 0x0, 0x1, 0x3b, 0x0, 0x21110000, 72, 0x21110000 },
{ 0x0, 0x1, 0x3c, 0x0, 0x21270000, 73, 0x21270000 },
{ 0x0, 0x1, 0x3d, 0x0, 0x21290000, 74, 0x21290000 },
{ 0x0, 0x1, 0x3e, 0x0, 0x21840000, 75, 0x21840000 },
{ 0x0, 0x1, 0x3f, 0x0, 0x21880000, 76, 0x21880000 },
{ 0x0, 0x1, 0x40, 0x0, 0x218d0000, 77, 0x218d0000 },
{ 0x0, 0x1, 0x41, 0x0, 0x21950000, 78, 0x21950000 },
{ 0x0, 0x1, 0x42, 0x0, 0x21960000, 79, 0x21960000 },
{ 0x0, 0x1, 0x43, 0x0, 0x21a10000, 80, 0x21a10000 },
{ 0x0, 0x1, 0x44, 0x0, 0x024a0000, 29, 0x024a0000 },
{ 0x0, 0x1, 0x45, 0x0, 0x024c0000, 30, 0x024c0000 },
{ 0x0, 0x1, 0x46, 0x0, 0x032c0000, 34, 0x032c0000 },
{ 0x0, 0x1, 0x47, 0x0, 0x03400000, 37, 0x03400000 },
{ 0x0, 0x1, 0x48, 0x0, 0x130a0000, 41, 0x130a0000 },
{ 0x0, 0x1, 0x49, 0x0, 0x130c0000, 42, 0x130c0000 },
{ 0x0, 0x1, 0x4a, 0x0, 0x208a0000, 60, 0x208a0000 },
{ 0x0, 0x1, 0x4b, 0x0, 0x208c0000, 61, 0x208c0000 },
{ 0x0, 0x1, 0x4c, 0x0, 0x209a0000, 63, 0x209a0000 },
{ 0x0, 0x1, 0x4d, 0x0, 0x21a40000, 81, 0x21a40000 },
{ 0x0, 0x1, 0x4e, 0x0, 0x03440000, 38, 0x03440000 },
{ 0x0, 0x1, 0x4f, 0x0, 0x20d00000, 64, 0x20d00000 },
{ 0x0, 0x1, 0x50, 0x0, 0x21000000, 71, 0x21000000 },
{ 0x0, 0x1, 0x51, 0x0, 0x0b000000, 39, 0x0b000000 },
{ 0x0, 0x2, 0x00, 0x0, 0x00000000, 0, 0x00000000 },
{ 0x0, 0x3, 0x00, 0x0, 0x02340000, 0, 0x00000000 },
{ 0x0, 0x4, 0x00, 0x0, 0x17000000, 0, 0x17000000 },
{ 0x0, 0x4, 0x01, 0x0, 0x18000000, 1, 0x18000000 },
{ 0x0, 0x5, 0x00, 0x0, 0x13e80000, 1, 0x13e80000 },
{ 0x0, 0x5, 0x01, 0x0, 0x15810000, 12, 0x15810000 },
{ 0x0, 0x5, 0x02, 0x0, 0x15840000, 14, 0x15840000 },
{ 0x0, 0x5, 0x03, 0x0, 0x15a40000, 17, 0x15a40000 },
{ 0x0, 0x5, 0x04, 0x0, 0x13f00000, 3, 0x13f00000 },
{ 0x0, 0x5, 0x05, 0x0, 0x15820000, 13, 0x15820000 },
{ 0x0, 0x5, 0x06, 0x0, 0x13ec0000, 2, 0x13ec0000 },
{ 0x0, 0x5, 0x07, 0x0, 0x15200000, 6, 0x15200000 },
{ 0x0, 0x5, 0x08, 0x0, 0x15340000, 7, 0x15340000 },
{ 0x0, 0x5, 0x09, 0x0, 0x15380000, 8, 0x15380000 },
{ 0x0, 0x5, 0x0a, 0x0, 0x15500000, 10, 0x15500000 },
{ 0x0, 0x5, 0x0b, 0x0, 0x155c0000, 11, 0x155c0000 },
{ 0x0, 0x5, 0x0c, 0x0, 0x15a00000, 16, 0x15a00000 },
{ 0x0, 0x5, 0x0d, 0x0, 0x13e00000, 0, 0x13e00000 },
{ 0x0, 0x5, 0x0e, 0x0, 0x15100000, 5, 0x15100000 },
{ 0x0, 0x5, 0x0f, 0x0, 0x15480000, 9, 0x15480000 },
{ 0x0, 0x5, 0x10, 0x0, 0x15880000, 15, 0x15880000 },
{ 0x0, 0x5, 0x11, 0x0, 0x15a80000, 18, 0x15a80000 },
{ 0x0, 0x5, 0x12, 0x0, 0x15b00000, 19, 0x15b00000 },
{ 0x0, 0x5, 0x13, 0x0, 0x14800000, 4, 0x14800000 },
{ 0x0, 0x5, 0x14, 0x0, 0x15c00000, 20, 0x15c00000 },
{ 0x0, 0x5, 0x15, 0x0, 0x16000000, 21, 0x16000000 },
{ 0x0, 0x6, 0x00, 0x0, 0x02000000, 4, 0x02000000 },
{ 0x0, 0x6, 0x01, 0x0, 0x02007000, 5, 0x02007000 },
{ 0x0, 0x6, 0x02, 0x0, 0x02008000, 6, 0x02008000 },
{ 0x0, 0x6, 0x03, 0x0, 0x02013000, 7, 0x02013000 },
{ 0x0, 0x6, 0x04, 0x0, 0x0201c000, 8, 0x0201c000 },
{ 0x0, 0x6, 0x05, 0x0, 0x02020000, 9, 0x02020000 },
{ 0x0, 0x6, 0x06, 0x0, 0x0202a000, 10, 0x0202a000 },
{ 0x0, 0x6, 0x07, 0x0, 0x0202e000, 11, 0x0202e000 },
{ 0x0, 0x6, 0x08, 0x0, 0x06400000, 33, 0x06400000 },
{ 0x0, 0x6, 0x09, 0x0, 0x02038000, 12, 0x02038000 },
{ 0x0, 0x6, 0x0a, 0x0, 0x00100000, 0, 0x00100000 },
{ 0x0, 0x6, 0x0b, 0x0, 0x023b0000, 13, 0x023b0000 },
{ 0x0, 0x6, 0x0c, 0x0, 0x02800000, 16, 0x02800000 },
{ 0x0, 0x6, 0x0d, 0x0, 0x030e0000, 22, 0x030e0000 },
{ 0x0, 0x6, 0x0e, 0x0, 0x03800000, 23, 0x03800000 },
{ 0x0, 0x6, 0x0f, 0x0, 0x03980000, 25, 0x03980000 },
{ 0x0, 0x6, 0x10, 0x0, 0x03a60000, 26, 0x03a60000 },
{ 0x0, 0x6, 0x11, 0x0, 0x03d80000, 31, 0x03d80000 },
{ 0x0, 0x6, 0x12, 0x0, 0x20000000, 36, 0x20000000 },
{ 0x0, 0x6, 0x13, 0x0, 0x20050000, 38, 0x20050000 },
{ 0x0, 0x6, 0x14, 0x0, 0x201e0000, 40, 0x201e0000 },
{ 0x0, 0x6, 0x15, 0x0, 0x20280000, 42, 0x20280000 },
{ 0x0, 0x6, 0x16, 0x0, 0x202c0000, 43, 0x202c0000 },
{ 0x0, 0x6, 0x17, 0x0, 0x20390000, 44, 0x20390000 },
{ 0x0, 0x6, 0x18, 0x0, 0x20430000, 45, 0x20430000 },
{ 0x0, 0x6, 0x19, 0x0, 0x20440000, 46, 0x20440000 },
{ 0x0, 0x6, 0x1a, 0x0, 0x204e0000, 47, 0x204e0000 },
{ 0x0, 0x6, 0x1b, 0x0, 0x20550000, 48, 0x20550000 },
{ 0x0, 0x6, 0x1c, 0x0, 0x20570000, 49, 0x20570000 },
{ 0x0, 0x6, 0x1d, 0x0, 0x20590000, 50, 0x20590000 },
{ 0x0, 0x6, 0x1e, 0x0, 0x20730000, 52, 0x20730000 },
{ 0x0, 0x6, 0x1f, 0x0, 0x209f0000, 54, 0x209f0000 },
{ 0x0, 0x6, 0x20, 0x0, 0x20e20000, 55, 0x20e20000 },
{ 0x0, 0x6, 0x21, 0x0, 0x20ed0000, 56, 0x20ed0000 },
{ 0x0, 0x6, 0x22, 0x0, 0x20fd0000, 57, 0x20fd0000 },
{ 0x0, 0x6, 0x23, 0x0, 0x21120000, 59, 0x21120000 },
{ 0x0, 0x6, 0x24, 0x0, 0x211a0000, 60, 0x211a0000 },
{ 0x0, 0x6, 0x25, 0x0, 0x21850000, 61, 0x21850000 },
{ 0x0, 0x6, 0x26, 0x0, 0x21860000, 62, 0x21860000 },
{ 0x0, 0x6, 0x27, 0x0, 0x21890000, 63, 0x21890000 },
{ 0x0, 0x6, 0x28, 0x0, 0x21970000, 64, 0x21970000 },
{ 0x0, 0x6, 0x29, 0x0, 0x21990000, 65, 0x21990000 },
{ 0x0, 0x6, 0x2a, 0x0, 0x21a00000, 66, 0x21a00000 },
{ 0x0, 0x6, 0x2b, 0x0, 0x21a90000, 68, 0x21a90000 },
{ 0x0, 0x6, 0x2c, 0x0, 0x21ac0000, 70, 0x21ac0000 },
{ 0x0, 0x6, 0x2d, 0x0, 0x01f80000, 3, 0x01f80000 },
{ 0x0, 0x6, 0x2e, 0x0, 0x024e0000, 14, 0x024e0000 },
{ 0x0, 0x6, 0x2f, 0x0, 0x030c0000, 21, 0x030c0000 },
{ 0x0, 0x6, 0x30, 0x0, 0x03820000, 24, 0x03820000 },
{ 0x0, 0x6, 0x31, 0x0, 0x03aa0000, 27, 0x03aa0000 },
{ 0x0, 0x6, 0x32, 0x0, 0x03c80000, 29, 0x03c80000 },
{ 0x0, 0x6, 0x33, 0x0, 0x130e0000, 34, 0x130e0000 },
{ 0x0, 0x6, 0x34, 0x0, 0x20020000, 37, 0x20020000 },
{ 0x0, 0x6, 0x35, 0x0, 0x20060000, 39, 0x20060000 },
{ 0x0, 0x6, 0x36, 0x0, 0x20200000, 41, 0x20200000 },
{ 0x0, 0x6, 0x37, 0x0, 0x206a0000, 51, 0x206a0000 },
{ 0x0, 0x6, 0x38, 0x0, 0x20740000, 53, 0x20740000 },
{ 0x0, 0x6, 0x39, 0x0, 0x20fe0000, 58, 0x20fe0000 },
{ 0x0, 0x6, 0x3a, 0x0, 0x21a20000, 67, 0x21a20000 },
{ 0x0, 0x6, 0x3b, 0x0, 0x21aa0000, 69, 0x21aa0000 },
{ 0x0, 0x6, 0x3c, 0x0, 0x02b80000, 17, 0x02b80000 },
{ 0x0, 0x6, 0x3d, 0x0, 0x03080000, 20, 0x03080000 },
{ 0x0, 0x6, 0x3e, 0x0, 0x13100000, 35, 0x13100000 },
{ 0x0, 0x6, 0x3f, 0x0, 0x01f00000, 2, 0x01f00000 },
{ 0x0, 0x6, 0x40, 0x0, 0x03000000, 19, 0x03000000 },
{ 0x0, 0x6, 0x41, 0x0, 0x03c00000, 28, 0x03c00000 },
{ 0x0, 0x6, 0x42, 0x0, 0x03d00000, 30, 0x03d00000 },
{ 0x0, 0x6, 0x43, 0x0, 0x01700000, 1, 0x01700000 },
{ 0x0, 0x6, 0x44, 0x0, 0x02c00000, 18, 0x02c00000 },
{ 0x0, 0x6, 0x45, 0x0, 0x02600000, 15, 0x02600000 },
{ 0x0, 0x6, 0x46, 0x0, 0x06000000, 32, 0x06000000 },
{ 0x0, 0x6, 0x47, 0x0, 0x24000000, 71, 0x24000000 },
{ 0x0, 0x7, 0x00, 0x0, 0x12000000, 0, 0x12000000 },
{ 0x0, 0x8, 0x00, 0x0, 0x11000000, 0, 0x11000000 },
{ 0x0, 0x9, 0x00, 0x0, 0x10000000, 0, 0x10000000 },
{ 0x0, 0xa, 0x00, 0x0, 0x22000000, 0, 0x22000000 }
};
/*
* BPMP NOC aperture lookup table as per file "BPMP_NOC_Structure.info".
*/
static const char * const tegra194_bpmpnoc_routeid_initflow[] = {
[0x0] = "cbb_i/I/0",
[0x1] = "cpu_m_i/I/0",
[0x2] = "cpu_p_i/I/0",
[0x3] = "cvc_i/I/0",
[0x4] = "dma_m_i/I/0",
[0x5] = "dma_p_i/I/0",
[0x6] = "RESERVED",
[0x7] = "RESERVED"
};
static const char * const tegra194_bpmpnoc_routeid_targflow[] = {
[0x00] = "multiport0_t/T/actmon",
[0x01] = "multiport0_t/T/ast_0",
[0x02] = "multiport0_t/T/ast_1",
[0x03] = "multiport0_t/T/atcm_cfg",
[0x04] = "multiport0_t/T/car",
[0x05] = "multiport0_t/T/central_pwr_mgr",
[0x06] = "multiport0_t/T/central_vtg_ctlr",
[0x07] = "multiport0_t/T/cfg",
[0x08] = "multiport0_t/T/dma",
[0x09] = "multiport0_t/T/err_collator",
[0x0a] = "multiport0_t/T/err_collator_car",
[0x0b] = "multiport0_t/T/fpga_misc",
[0x0c] = "multiport0_t/T/fpga_uart",
[0x0d] = "multiport0_t/T/gte",
[0x0e] = "multiport0_t/T/hsp",
[0x0f] = "multiport0_t/T/misc",
[0x10] = "multiport0_t/T/pm",
[0x11] = "multiport0_t/T/simon0",
[0x12] = "multiport0_t/T/simon1",
[0x13] = "multiport0_t/T/simon2",
[0x14] = "multiport0_t/T/simon3",
[0x15] = "multiport0_t/T/simon4",
[0x16] = "multiport0_t/T/soc_therm",
[0x17] = "multiport0_t/T/tke",
[0x18] = "multiport0_t/T/vic_0",
[0x19] = "multiport0_t/T/vic_1",
[0x1a] = "ast0_t/T/0",
[0x1b] = "ast1_t/T/0",
[0x1c] = "bpmp_noc_firewall/T/0",
[0x1d] = "cbb_t/T/0",
[0x1e] = "cpu_t/T/0",
[0x1f] = "svc_t/T/0"
};
/*
* Fields of BPMP NOC lookup table:
* Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
* Targ mapping, Targ localAddress
* ----------------------------------------------------------------------------
*/
static const struct tegra194_cbb_aperture tegra194_bpmpnoc_apert_lookup[] = {
{ 0x0, 0x1c, 0x0, 0x0, 0x0d640000, 0, 0x00000000 },
{ 0x0, 0x1e, 0x0, 0x0, 0x0d400000, 0, 0x0d400000 },
{ 0x0, 0x00, 0x0, 0x0, 0x0d230000, 0, 0x00000000 },
{ 0x0, 0x01, 0x0, 0x0, 0x0d040000, 0, 0x00000000 },
{ 0x0, 0x02, 0x0, 0x0, 0x0d050000, 0, 0x00000000 },
{ 0x0, 0x03, 0x0, 0x0, 0x0d000000, 0, 0x00000000 },
{ 0x0, 0x04, 0x0, 0x0, 0x20ae0000, 3, 0x000e0000 },
{ 0x0, 0x04, 0x1, 0x0, 0x20ac0000, 2, 0x000c0000 },
{ 0x0, 0x04, 0x2, 0x0, 0x20a80000, 1, 0x00080000 },
{ 0x0, 0x04, 0x3, 0x0, 0x20a00000, 0, 0x00000000 },
{ 0x0, 0x05, 0x0, 0x0, 0x0d2a0000, 0, 0x00000000 },
{ 0x0, 0x06, 0x0, 0x0, 0x0d290000, 0, 0x00000000 },
{ 0x0, 0x07, 0x0, 0x0, 0x0d2c0000, 0, 0x00000000 },
{ 0x0, 0x08, 0x0, 0x0, 0x0d0e0000, 4, 0x00080000 },
{ 0x0, 0x08, 0x1, 0x0, 0x0d060000, 0, 0x00000000 },
{ 0x0, 0x08, 0x2, 0x0, 0x0d080000, 1, 0x00020000 },
{ 0x0, 0x08, 0x3, 0x0, 0x0d0a0000, 2, 0x00040000 },
{ 0x0, 0x08, 0x4, 0x0, 0x0d0c0000, 3, 0x00060000 },
{ 0x0, 0x09, 0x0, 0x0, 0x0d650000, 0, 0x00000000 },
{ 0x0, 0x0a, 0x0, 0x0, 0x20af0000, 0, 0x00000000 },
{ 0x0, 0x0b, 0x0, 0x0, 0x0d3e0000, 0, 0x00000000 },
{ 0x0, 0x0c, 0x0, 0x0, 0x0d3d0000, 0, 0x00000000 },
{ 0x0, 0x0d, 0x0, 0x0, 0x0d1e0000, 0, 0x00000000 },
{ 0x0, 0x0e, 0x0, 0x0, 0x0d150000, 0, 0x00000000 },
{ 0x0, 0x0e, 0x1, 0x0, 0x0d160000, 1, 0x00010000 },
{ 0x0, 0x0e, 0x2, 0x0, 0x0d170000, 2, 0x00020000 },
{ 0x0, 0x0e, 0x3, 0x0, 0x0d180000, 3, 0x00030000 },
{ 0x0, 0x0e, 0x4, 0x0, 0x0d190000, 4, 0x00040000 },
{ 0x0, 0x0e, 0x5, 0x0, 0x0d1a0000, 5, 0x00050000 },
{ 0x0, 0x0e, 0x6, 0x0, 0x0d1b0000, 6, 0x00060000 },
{ 0x0, 0x0e, 0x7, 0x0, 0x0d1c0000, 7, 0x00070000 },
{ 0x0, 0x0e, 0x8, 0x0, 0x0d1d0000, 8, 0x00080000 },
{ 0x0, 0x0f, 0x0, 0x0, 0x0d660000, 0, 0x00000000 },
{ 0x0, 0x10, 0x0, 0x0, 0x0d1f0000, 0, 0x00000000 },
{ 0x0, 0x10, 0x1, 0x0, 0x0d200000, 1, 0x00010000 },
{ 0x0, 0x10, 0x2, 0x0, 0x0d210000, 2, 0x00020000 },
{ 0x0, 0x10, 0x3, 0x0, 0x0d220000, 3, 0x00030000 },
{ 0x0, 0x11, 0x0, 0x0, 0x0d240000, 0, 0x00000000 },
{ 0x0, 0x12, 0x0, 0x0, 0x0d250000, 0, 0x00000000 },
{ 0x0, 0x13, 0x0, 0x0, 0x0d260000, 0, 0x00000000 },
{ 0x0, 0x14, 0x0, 0x0, 0x0d270000, 0, 0x00000000 },
{ 0x0, 0x15, 0x0, 0x0, 0x0d2b0000, 0, 0x00000000 },
{ 0x0, 0x16, 0x0, 0x0, 0x0d280000, 0, 0x00000000 },
{ 0x0, 0x17, 0x0, 0x0, 0x0d0f0000, 0, 0x00000000 },
{ 0x0, 0x17, 0x1, 0x0, 0x0d100000, 1, 0x00010000 },
{ 0x0, 0x17, 0x2, 0x0, 0x0d110000, 2, 0x00020000 },
{ 0x0, 0x17, 0x3, 0x0, 0x0d120000, 3, 0x00030000 },
{ 0x0, 0x17, 0x4, 0x0, 0x0d130000, 4, 0x00040000 },
{ 0x0, 0x17, 0x5, 0x0, 0x0d140000, 5, 0x00050000 },
{ 0x0, 0x18, 0x0, 0x0, 0x0d020000, 0, 0x00000000 },
{ 0x0, 0x19, 0x0, 0x0, 0x0d030000, 0, 0x00000000 },
{ 0x0, 0x1f, 0x0, 0x0, 0x0d600000, 0, 0x00000000 },
{ 0x0, 0x1f, 0x1, 0x0, 0x00000000, 0, 0x00000000 },
{ 0x1, 0x1a, 0x0, 0x0, 0x40000000, 0, 0x40000000 },
{ 0x1, 0x1a, 0x1, 0x1, 0x80000000, 1, 0x80000000 },
{ 0x1, 0x1a, 0x2, 0x0, 0x00000000, 0, 0x00000000 },
{ 0x2, 0x1c, 0x0, 0x0, 0x0d640000, 0, 0x00000000 },
{ 0x2, 0x1d, 0x0, 0x0, 0x20b00000, 8, 0x20b00000 },
{ 0x2, 0x1d, 0x1, 0x0, 0x20800000, 7, 0x20800000 },
{ 0x2, 0x1d, 0x2, 0x0, 0x20c00000, 9, 0x20c00000 },
{ 0x2, 0x1d, 0x3, 0x0, 0x0d800000, 3, 0x0d800000 },
{ 0x2, 0x1d, 0x4, 0x0, 0x20000000, 6, 0x20000000 },
{ 0x2, 0x1d, 0x5, 0x0, 0x0c000000, 2, 0x0c000000 },
{ 0x2, 0x1d, 0x6, 0x0, 0x21000000, 10, 0x21000000 },
{ 0x2, 0x1d, 0x7, 0x0, 0x0e000000, 4, 0x0e000000 },
{ 0x2, 0x1d, 0x8, 0x0, 0x22000000, 11, 0x22000000 },
{ 0x2, 0x1d, 0x9, 0x0, 0x08000000, 1, 0x08000000 },
{ 0x2, 0x1d, 0xa, 0x0, 0x24000000, 12, 0x24000000 },
{ 0x2, 0x1d, 0xb, 0x0, 0x00000000, 0, 0x00000000 },
{ 0x2, 0x1d, 0xc, 0x0, 0x28000000, 13, 0x28000000 },
{ 0x2, 0x1d, 0xd, 0x0, 0x10000000, 5, 0x10000000 },
{ 0x2, 0x1d, 0xe, 0x0, 0x30000000, 14, 0x30000000 },
{ 0x2, 0x00, 0x0, 0x0, 0x0d230000, 0, 0x00000000 },
{ 0x2, 0x01, 0x0, 0x0, 0x0d040000, 0, 0x00000000 },
{ 0x2, 0x02, 0x0, 0x0, 0x0d050000, 0, 0x00000000 },
{ 0x2, 0x03, 0x0, 0x0, 0x0d000000, 0, 0x00000000 },
{ 0x2, 0x04, 0x0, 0x0, 0x20ae0000, 3, 0x000e0000 },
{ 0x2, 0x04, 0x1, 0x0, 0x20ac0000, 2, 0x000c0000 },
{ 0x2, 0x04, 0x2, 0x0, 0x20a80000, 1, 0x00080000 },
{ 0x2, 0x04, 0x3, 0x0, 0x20a00000, 0, 0x00000000 },
{ 0x2, 0x05, 0x0, 0x0, 0x0d2a0000, 0, 0x00000000 },
{ 0x2, 0x06, 0x0, 0x0, 0x0d290000, 0, 0x00000000 },
{ 0x2, 0x07, 0x0, 0x0, 0x0d2c0000, 0, 0x00000000 },
{ 0x2, 0x08, 0x0, 0x0, 0x0d0e0000, 4, 0x00080000 },
{ 0x2, 0x08, 0x1, 0x0, 0x0d060000, 0, 0x00000000 },
{ 0x2, 0x08, 0x2, 0x0, 0x0d080000, 1, 0x00020000 },
{ 0x2, 0x08, 0x3, 0x0, 0x0d0a0000, 2, 0x00040000 },
{ 0x2, 0x08, 0x4, 0x0, 0x0d0c0000, 3, 0x00060000 },
{ 0x2, 0x09, 0x0, 0x0, 0x0d650000, 0, 0x00000000 },
{ 0x2, 0x0a, 0x0, 0x0, 0x20af0000, 0, 0x00000000 },
{ 0x2, 0x0b, 0x0, 0x0, 0x0d3e0000, 0, 0x00000000 },
{ 0x2, 0x0c, 0x0, 0x0, 0x0d3d0000, 0, 0x00000000 },
{ 0x2, 0x0d, 0x0, 0x0, 0x0d1e0000, 0, 0x00000000 },
{ 0x2, 0x0e, 0x0, 0x0, 0x0d150000, 0, 0x00000000 },
{ 0x2, 0x0e, 0x1, 0x0, 0x0d160000, 1, 0x00010000 },
{ 0x2, 0x0e, 0x2, 0x0, 0x0d170000, 2, 0x00020000 },
{ 0x2, 0x0e, 0x3, 0x0, 0x0d180000, 3, 0x00030000 },
{ 0x2, 0x0e, 0x4, 0x0, 0x0d190000, 4, 0x00040000 },
{ 0x2, 0x0e, 0x5, 0x0, 0x0d1a0000, 5, 0x00050000 },
{ 0x2, 0x0e, 0x6, 0x0, 0x0d1b0000, 6, 0x00060000 },
{ 0x2, 0x0e, 0x7, 0x0, 0x0d1c0000, 7, 0x00070000 },
{ 0x2, 0x0e, 0x8, 0x0, 0x0d1d0000, 8, 0x00080000 },
{ 0x2, 0x0f, 0x0, 0x0, 0x0d660000, 0, 0x00000000 },
{ 0x2, 0x10, 0x0, 0x0, 0x0d1f0000, 0, 0x00000000 },
{ 0x2, 0x10, 0x1, 0x0, 0x0d200000, 1, 0x00010000 },
{ 0x2, 0x10, 0x2, 0x0, 0x0d210000, 2, 0x00020000 },
{ 0x2, 0x10, 0x3, 0x0, 0x0d220000, 3, 0x00030000 },
{ 0x2, 0x11, 0x0, 0x0, 0x0d240000, 0, 0x00000000 },
{ 0x2, 0x12, 0x0, 0x0, 0x0d250000, 0, 0x00000000 },
{ 0x2, 0x13, 0x0, 0x0, 0x0d260000, 0, 0x00000000 },
{ 0x2, 0x14, 0x0, 0x0, 0x0d270000, 0, 0x00000000 },
{ 0x2, 0x15, 0x0, 0x0, 0x0d2b0000, 0, 0x00000000 },
{ 0x2, 0x16, 0x0, 0x0, 0x0d280000, 0, 0x00000000 },
{ 0x2, 0x17, 0x0, 0x0, 0x0d0f0000, 0, 0x00000000 },
{ 0x2, 0x17, 0x1, 0x0, 0x0d100000, 1, 0x00010000 },
{ 0x2, 0x17, 0x2, 0x0, 0x0d110000, 2, 0x00020000 },
{ 0x2, 0x17, 0x3, 0x0, 0x0d120000, 3, 0x00030000 },
{ 0x2, 0x17, 0x4, 0x0, 0x0d130000, 4, 0x00040000 },
{ 0x2, 0x17, 0x5, 0x0, 0x0d140000, 5, 0x00050000 },
{ 0x2, 0x18, 0x0, 0x0, 0x0d020000, 0, 0x00000000 },
{ 0x2, 0x19, 0x0, 0x0, 0x0d030000, 0, 0x00000000 },
{ 0x2, 0x1f, 0x0, 0x0, 0x0d600000, 0, 0x00000000 },
{ 0x2, 0x1f, 0x1, 0x0, 0x00000000, 0, 0x00000000 },
{ 0x3, 0x1b, 0x0, 0x0, 0x40000000, 0, 0x40000000 },
{ 0x3, 0x1b, 0x1, 0x1, 0x80000000, 1, 0x80000000 },
{ 0x3, 0x1c, 0x0, 0x2, 0x0d640000, 0, 0x00000000 },
{ 0x3, 0x1d, 0x0, 0x2, 0x20b00000, 8, 0x20b00000 },
{ 0x3, 0x1d, 0x1, 0x2, 0x20800000, 7, 0x20800000 },
{ 0x3, 0x1d, 0x2, 0x2, 0x20c00000, 9, 0x20c00000 },
{ 0x3, 0x1d, 0x3, 0x2, 0x0d800000, 3, 0x0d800000 },
{ 0x3, 0x1d, 0x4, 0x2, 0x20000000, 6, 0x20000000 },
{ 0x3, 0x1d, 0x5, 0x2, 0x0c000000, 2, 0x0c000000 },
{ 0x3, 0x1d, 0x6, 0x2, 0x21000000, 10, 0x21000000 },
{ 0x3, 0x1d, 0x7, 0x2, 0x0e000000, 4, 0x0e000000 },
{ 0x3, 0x1d, 0x8, 0x2, 0x22000000, 11, 0x22000000 },
{ 0x3, 0x1d, 0x9, 0x2, 0x08000000, 1, 0x08000000 },
{ 0x3, 0x1d, 0xa, 0x2, 0x24000000, 12, 0x24000000 },
{ 0x3, 0x1d, 0xb, 0x2, 0x00000000, 0, 0x00000000 },
{ 0x3, 0x1d, 0xc, 0x2, 0x28000000, 13, 0x28000000 },
{ 0x3, 0x1d, 0xd, 0x2, 0x10000000, 5, 0x10000000 },
{ 0x3, 0x1d, 0xe, 0x2, 0x30000000, 14, 0x30000000 },
{ 0x3, 0x1e, 0x0, 0x2, 0x0d400000, 0, 0x0d400000 },
{ 0x3, 0x00, 0x0, 0x2, 0x0d230000, 0, 0x00000000 },
{ 0x3, 0x01, 0x0, 0x2, 0x0d040000, 0, 0x00000000 },
{ 0x3, 0x02, 0x0, 0x2, 0x0d050000, 0, 0x00000000 },
{ 0x3, 0x03, 0x0, 0x2, 0x0d000000, 0, 0x00000000 },
{ 0x3, 0x04, 0x0, 0x2, 0x20ae0000, 3, 0x000e0000 },
{ 0x3, 0x04, 0x1, 0x2, 0x20ac0000, 2, 0x000c0000 },
{ 0x3, 0x04, 0x2, 0x2, 0x20a80000, 1, 0x00080000 },
{ 0x3, 0x04, 0x3, 0x2, 0x20a00000, 0, 0x00000000 },
{ 0x3, 0x05, 0x0, 0x2, 0x0d2a0000, 0, 0x00000000 },
{ 0x3, 0x06, 0x0, 0x2, 0x0d290000, 0, 0x00000000 },
{ 0x3, 0x07, 0x0, 0x2, 0x0d2c0000, 0, 0x00000000 },
{ 0x3, 0x08, 0x0, 0x2, 0x0d0e0000, 4, 0x00080000 },
{ 0x3, 0x08, 0x1, 0x2, 0x0d060000, 0, 0x00000000 },
{ 0x3, 0x08, 0x2, 0x2, 0x0d080000, 1, 0x00020000 },
{ 0x3, 0x08, 0x3, 0x2, 0x0d0a0000, 2, 0x00040000 },
{ 0x3, 0x08, 0x4, 0x2, 0x0d0c0000, 3, 0x00060000 },
{ 0x3, 0x09, 0x0, 0x2, 0x0d650000, 0, 0x00000000 },
{ 0x3, 0x0a, 0x0, 0x2, 0x20af0000, 0, 0x00000000 },
{ 0x3, 0x0b, 0x0, 0x2, 0x0d3e0000, 0, 0x00000000 },
{ 0x3, 0x0c, 0x0, 0x2, 0x0d3d0000, 0, 0x00000000 },
{ 0x3, 0x0d, 0x0, 0x2, 0x0d1e0000, 0, 0x00000000 },
{ 0x3, 0x0e, 0x0, 0x2, 0x0d150000, 0, 0x00000000 },
{ 0x3, 0x0e, 0x1, 0x2, 0x0d160000, 1, 0x00010000 },
{ 0x3, 0x0e, 0x2, 0x2, 0x0d170000, 2, 0x00020000 },
{ 0x3, 0x0e, 0x3, 0x2, 0x0d180000, 3, 0x00030000 },
{ 0x3, 0x0e, 0x4, 0x2, 0x0d190000, 4, 0x00040000 },
{ 0x3, 0x0e, 0x5, 0x2, 0x0d1a0000, 5, 0x00050000 },
{ 0x3, 0x0e, 0x6, 0x2, 0x0d1b0000, 6, 0x00060000 },
{ 0x3, 0x0e, 0x7, 0x2, 0x0d1c0000, 7, 0x00070000 },
{ 0x3, 0x0e, 0x8, 0x2, 0x0d1d0000, 8, 0x00080000 },
{ 0x3, 0x0f, 0x0, 0x2, 0x0d660000, 0, 0x00000000 },
{ 0x3, 0x10, 0x0, 0x2, 0x0d1f0000, 0, 0x00000000 },
{ 0x3, 0x10, 0x1, 0x2, 0x0d200000, 1, 0x00010000 },
{ 0x3, 0x10, 0x2, 0x2, 0x0d210000, 2, 0x00020000 },
{ 0x3, 0x10, 0x3, 0x2, 0x0d220000, 3, 0x00030000 },
{ 0x3, 0x11, 0x0, 0x2, 0x0d240000, 0, 0x00000000 },
{ 0x3, 0x12, 0x0, 0x2, 0x0d250000, 0, 0x00000000 },
{ 0x3, 0x13, 0x0, 0x2, 0x0d260000, 0, 0x00000000 },
{ 0x3, 0x14, 0x0, 0x2, 0x0d270000, 0, 0x00000000 },
{ 0x3, 0x15, 0x0, 0x2, 0x0d2b0000, 0, 0x00000000 },
{ 0x3, 0x16, 0x0, 0x2, 0x0d280000, 0, 0x00000000 },
{ 0x3, 0x17, 0x0, 0x2, 0x0d0f0000, 0, 0x00000000 },
{ 0x3, 0x17, 0x1, 0x2, 0x0d100000, 1, 0x00010000 },
{ 0x3, 0x17, 0x2, 0x2, 0x0d110000, 2, 0x00020000 },
{ 0x3, 0x17, 0x3, 0x2, 0x0d120000, 3, 0x00030000 },
{ 0x3, 0x17, 0x4, 0x2, 0x0d130000, 4, 0x00040000 },
{ 0x3, 0x17, 0x5, 0x2, 0x0d140000, 5, 0x00050000 },
{ 0x3, 0x18, 0x0, 0x2, 0x0d020000, 0, 0x00000000 },
{ 0x3, 0x19, 0x0, 0x2, 0x0d030000, 0, 0x00000000 },
{ 0x3, 0x1f, 0x0, 0x2, 0x0d600000, 0, 0x00000000 },
{ 0x3, 0x1f, 0x1, 0x0, 0x00000000, 0, 0x00000000 },
{ 0x4, 0x1b, 0x0, 0x0, 0x40000000, 0, 0x40000000 },
{ 0x4, 0x1b, 0x1, 0x1, 0x80000000, 1, 0x80000000 },
{ 0x4, 0x1e, 0x0, 0x2, 0x0d400000, 0, 0x0d400000 },
{ 0x4, 0x1e, 0x1, 0x0, 0x00000000, 0, 0x00000000 },
{ 0x5, 0x1c, 0x0, 0x0, 0x0d640000, 0, 0x00000000 },
{ 0x5, 0x1d, 0x0, 0x0, 0x20b00000, 8, 0x20b00000 },
{ 0x5, 0x1d, 0x1, 0x0, 0x20800000, 7, 0x20800000 },
{ 0x5, 0x1d, 0x2, 0x0, 0x20c00000, 9, 0x20c00000 },
{ 0x5, 0x1d, 0x3, 0x0, 0x0d800000, 3, 0x0d800000 },
{ 0x5, 0x1d, 0x4, 0x0, 0x20000000, 6, 0x20000000 },
{ 0x5, 0x1d, 0x5, 0x0, 0x0c000000, 2, 0x0c000000 },
{ 0x5, 0x1d, 0x6, 0x0, 0x21000000, 10, 0x21000000 },
{ 0x5, 0x1d, 0x7, 0x0, 0x0e000000, 4, 0x0e000000 },
{ 0x5, 0x1d, 0x8, 0x0, 0x22000000, 11, 0x22000000 },
{ 0x5, 0x1d, 0x9, 0x0, 0x08000000, 1, 0x08000000 },
{ 0x5, 0x1d, 0xa, 0x0, 0x24000000, 12, 0x24000000 },
{ 0x5, 0x1d, 0xb, 0x0, 0x00000000, 0, 0x00000000 },
{ 0x5, 0x1d, 0xc, 0x0, 0x28000000, 13, 0x28000000 },
{ 0x5, 0x1d, 0xd, 0x0, 0x10000000, 5, 0x10000000 },
{ 0x5, 0x1d, 0xe, 0x0, 0x30000000, 14, 0x30000000 },
{ 0x5, 0x00, 0x0, 0x0, 0x0d230000, 0, 0x00000000 },
{ 0x5, 0x01, 0x0, 0x0, 0x0d040000, 0, 0x00000000 },
{ 0x5, 0x02, 0x0, 0x0, 0x0d050000, 0, 0x00000000 },
{ 0x5, 0x03, 0x0, 0x0, 0x0d000000, 0, 0x00000000 },
{ 0x5, 0x04, 0x0, 0x0, 0x20ae0000, 3, 0x000e0000 },
{ 0x5, 0x04, 0x1, 0x0, 0x20ac0000, 2, 0x000c0000 },
{ 0x5, 0x04, 0x2, 0x0, 0x20a80000, 1, 0x00080000 },
{ 0x5, 0x04, 0x3, 0x0, 0x20a00000, 0, 0x00000000 },
{ 0x5, 0x05, 0x0, 0x0, 0x0d2a0000, 0, 0x00000000 },
{ 0x5, 0x06, 0x0, 0x0, 0x0d290000, 0, 0x00000000 },
{ 0x5, 0x07, 0x0, 0x0, 0x0d2c0000, 0, 0x00000000 },
{ 0x5, 0x08, 0x0, 0x0, 0x0d0e0000, 4, 0x00080000 },
{ 0x5, 0x08, 0x1, 0x0, 0x0d060000, 0, 0x00000000 },
{ 0x5, 0x08, 0x2, 0x0, 0x0d080000, 1, 0x00020000 },
{ 0x5, 0x08, 0x3, 0x0, 0x0d0a0000, 2, 0x00040000 },
{ 0x5, 0x08, 0x4, 0x0, 0x0d0c0000, 3, 0x00060000 },
{ 0x5, 0x09, 0x0, 0x0, 0x0d650000, 0, 0x00000000 },
{ 0x5, 0x0a, 0x0, 0x0, 0x20af0000, 0, 0x00000000 },
{ 0x5, 0x0b, 0x0, 0x0, 0x0d3e0000, 0, 0x00000000 },
{ 0x5, 0x0c, 0x0, 0x0, 0x0d3d0000, 0, 0x00000000 },
{ 0x5, 0x0d, 0x0, 0x0, 0x0d1e0000, 0, 0x00000000 },
{ 0x5, 0x0e, 0x0, 0x0, 0x0d150000, 0, 0x00000000 },
{ 0x5, 0x0e, 0x1, 0x0, 0x0d160000, 1, 0x00010000 },
{ 0x5, 0x0e, 0x2, 0x0, 0x0d170000, 2, 0x00020000 },
{ 0x5, 0x0e, 0x3, 0x0, 0x0d180000, 3, 0x00030000 },
{ 0x5, 0x0e, 0x4, 0x0, 0x0d190000, 4, 0x00040000 },
{ 0x5, 0x0e, 0x5, 0x0, 0x0d1a0000, 5, 0x00050000 },
{ 0x5, 0x0e, 0x6, 0x0, 0x0d1b0000, 6, 0x00060000 },
{ 0x5, 0x0e, 0x7, 0x0, 0x0d1c0000, 7, 0x00070000 },
{ 0x5, 0x0e, 0x8, 0x0, 0x0d1d0000, 8, 0x00080000 },
{ 0x5, 0x0f, 0x0, 0x0, 0x0d660000, 0, 0x00000000 },
{ 0x5, 0x10, 0x0, 0x0, 0x0d1f0000, 0, 0x00000000 },
{ 0x5, 0x10, 0x1, 0x0, 0x0d200000, 1, 0x00010000 },
{ 0x5, 0x10, 0x2, 0x0, 0x0d210000, 2, 0x00020000 },
{ 0x5, 0x10, 0x3, 0x0, 0x0d220000, 3, 0x00030000 },
{ 0x5, 0x11, 0x0, 0x0, 0x0d240000, 0, 0x00000000 },
{ 0x5, 0x12, 0x0, 0x0, 0x0d250000, 0, 0x00000000 },
{ 0x5, 0x13, 0x0, 0x0, 0x0d260000, 0, 0x00000000 },
{ 0x5, 0x14, 0x0, 0x0, 0x0d270000, 0, 0x00000000 },
{ 0x5, 0x15, 0x0, 0x0, 0x0d2b0000, 0, 0x00000000 },
{ 0x5, 0x16, 0x0, 0x0, 0x0d280000, 0, 0x00000000 },
{ 0x5, 0x17, 0x0, 0x0, 0x0d0f0000, 0, 0x00000000 },
{ 0x5, 0x17, 0x1, 0x0, 0x0d100000, 1, 0x00010000 },
{ 0x5, 0x17, 0x2, 0x0, 0x0d110000, 2, 0x00020000 },
{ 0x5, 0x17, 0x3, 0x0, 0x0d120000, 3, 0x00030000 },
{ 0x5, 0x17, 0x4, 0x0, 0x0d130000, 4, 0x00040000 },
{ 0x5, 0x17, 0x5, 0x0, 0x0d140000, 5, 0x00050000 },
{ 0x5, 0x18, 0x0, 0x0, 0x0d020000, 0, 0x00000000 },
{ 0x5, 0x19, 0x0, 0x0, 0x0d030000, 0, 0x00000000 },
{ 0x5, 0x1f, 0x0, 0x0, 0x0d600000, 0, 0x00000000 },
{ 0x5, 0x1f, 0x1, 0x0, 0x00000000, 0, 0x00000000 }
};
/*
* AON NOC aperture lookup table as per file "AON_NOC_Structure.info".
*/
static const char * const tegra194_aonnoc_routeid_initflow[] = {
[0x0] = "cbb_i/I/0",
[0x1] = "cpu_p_i/I/0",
[0x2] = "dma_m_i/I/0",
[0x3] = "dma_p_i/I/0"
};
static const char * const tegra194_aonnoc_routeid_targflow[] = {
[0x00] = "multiport1_t/T/aon_misc",
[0x01] = "multiport1_t/T/avic0",
[0x02] = "multiport1_t/T/avic1",
[0x03] = "multiport1_t/T/can1",
[0x04] = "multiport1_t/T/can2",
[0x05] = "multiport1_t/T/dma",
[0x06] = "multiport1_t/T/dmic",
[0x07] = "multiport1_t/T/err_collator",
[0x08] = "multiport1_t/T/fpga_misc",
[0x09] = "multiport1_t/T/gte",
[0x0a] = "multiport1_t/T/hsp",
[0x0b] = "multiport1_t/T/i2c2",
[0x0c] = "multiport1_t/T/i2c8",
[0x0d] = "multiport1_t/T/pwm",
[0x0e] = "multiport1_t/T/spi2",
[0x0f] = "multiport1_t/T/tke",
[0x10] = "multiport1_t/T/uartg",
[0x11] = "RESERVED",
[0x12] = "RESERVED",
[0x13] = "RESERVED",
[0x14] = "RESERVED",
[0x15] = "RESERVED",
[0x16] = "RESERVED",
[0x17] = "RESERVED",
[0x18] = "RESERVED",
[0x19] = "RESERVED",
[0x1a] = "RESERVED",
[0x1b] = "RESERVED",
[0x1c] = "RESERVED",
[0x1d] = "RESERVED",
[0x1e] = "RESERVED",
[0x1f] = "RESERVED",
[0x20] = "multiport0_t/T/aovc",
[0x21] = "multiport0_t/T/atcm",
[0x22] = "multiport0_t/T/cast",
[0x23] = "multiport0_t/T/dast",
[0x24] = "multiport0_t/T/err_collator_car",
[0x25] = "multiport0_t/T/gpio",
[0x26] = "multiport0_t/T/i2c10",
[0x27] = "multiport0_t/T/mss",
[0x28] = "multiport0_t/T/padctl_a12",
[0x29] = "multiport0_t/T/padctl_a14",
[0x2a] = "multiport0_t/T/padctl_a15",
[0x2b] = "multiport0_t/T/rtc",
[0x2c] = "multiport0_t/T/tsc",
[0x2d] = "RESERVED",
[0x2e] = "RESERVED",
[0x2f] = "RESERVED",
[0x30] = "multiport2_t/T/aon_vref_ro",
[0x31] = "multiport2_t/T/aopm",
[0x32] = "multiport2_t/T/car",
[0x33] = "multiport2_t/T/pmc",
[0x34] = "ast1_t/T/0",
[0x35] = "cbb_t/T/0",
[0x36] = "cpu_t/T/0",
[0x37] = "firewall_t/T/0",
[0x38] = "svc_t/T/0",
[0x39] = "uartc/T/uartc",
[0x3a] = "RESERVED",
[0x3b] = "RESERVED",
[0x3c] = "RESERVED",
[0x3d] = "RESERVED",
[0x3e] = "RESERVED",
[0x3f] = "RESERVED"
};
/*
* Fields of AON NOC lookup table:
* Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
* Targ mapping, Targ localAddress
* ----------------------------------------------------------------------------
*/
static const struct tegra194_cbb_aperture tegra194_aonnoc_aperture_lookup[] = {
{ 0x0, 0x37, 0x00, 0, 0x0c640000, 0, 0x00000000 },
{ 0x0, 0x20, 0x00, 0, 0x0c3b0000, 0, 0x00000000 },
{ 0x0, 0x21, 0x00, 0, 0x0c000000, 0, 0x00000000 },
{ 0x0, 0x22, 0x00, 0, 0x0c040000, 0, 0x00000000 },
{ 0x0, 0x23, 0x00, 0, 0x0c050000, 0, 0x00000000 },
{ 0x0, 0x24, 0x00, 0, 0x20cf0000, 0, 0x00000000 },
{ 0x0, 0x25, 0x00, 0, 0x0c2f0000, 0, 0x00000000 },
{ 0x0, 0x26, 0x00, 0, 0x0c230000, 0, 0x00000000 },
{ 0x0, 0x27, 0x00, 0, 0x0c350000, 0, 0x00000000 },
{ 0x0, 0x28, 0x00, 0, 0x0c301000, 0, 0x00000000 },
{ 0x0, 0x29, 0x00, 0, 0x0c302000, 0, 0x00000000 },
{ 0x0, 0x2a, 0x00, 0, 0x0c303000, 0, 0x00000000 },
{ 0x0, 0x2b, 0x00, 0, 0x0c2a0000, 0, 0x00000000 },
{ 0x0, 0x2c, 0x00, 0, 0x0c2b0000, 0, 0x00000000 },
{ 0x0, 0x2c, 0x01, 0, 0x0c2c0000, 1, 0x00010000 },
{ 0x0, 0x2c, 0x02, 0, 0x0c2d0000, 2, 0x00020000 },
{ 0x0, 0x2c, 0x03, 0, 0x0c2e0000, 3, 0x00030000 },
{ 0x0, 0x00, 0x00, 0, 0x0c660000, 0, 0x00000000 },
{ 0x0, 0x01, 0x00, 0, 0x0c020000, 0, 0x00000000 },
{ 0x0, 0x02, 0x00, 0, 0x0c030000, 0, 0x00000000 },
{ 0x0, 0x03, 0x00, 0, 0x0c310000, 0, 0x00000000 },
{ 0x0, 0x04, 0x00, 0, 0x0c320000, 0, 0x00000000 },
{ 0x0, 0x05, 0x00, 0, 0x0c0a0000, 2, 0x00040000 },
{ 0x0, 0x05, 0x01, 0, 0x0c0b0000, 3, 0x00050000 },
{ 0x0, 0x05, 0x02, 0, 0x0c0e0000, 5, 0x00080000 },
{ 0x0, 0x05, 0x03, 0, 0x0c060000, 0, 0x00000000 },
{ 0x0, 0x05, 0x04, 0, 0x0c080000, 1, 0x00020000 },
{ 0x0, 0x05, 0x05, 0, 0x0c0c0000, 4, 0x00060000 },
{ 0x0, 0x06, 0x00, 0, 0x0c330000, 0, 0x00000000 },
{ 0x0, 0x07, 0x00, 0, 0x0c650000, 0, 0x00000000 },
{ 0x0, 0x08, 0x00, 0, 0x0c3e0000, 0, 0x00000000 },
{ 0x0, 0x09, 0x00, 0, 0x0c1e0000, 0, 0x00000000 },
{ 0x0, 0x0a, 0x00, 0, 0x0c150000, 0, 0x00000000 },
{ 0x0, 0x0a, 0x01, 0, 0x0c160000, 1, 0x00010000 },
{ 0x0, 0x0a, 0x02, 0, 0x0c170000, 2, 0x00020000 },
{ 0x0, 0x0a, 0x03, 0, 0x0c180000, 3, 0x00030000 },
{ 0x0, 0x0a, 0x04, 0, 0x0c190000, 4, 0x00040000 },
{ 0x0, 0x0a, 0x05, 0, 0x0c1a0000, 5, 0x00050000 },
{ 0x0, 0x0a, 0x06, 0, 0x0c1b0000, 6, 0x00060000 },
{ 0x0, 0x0a, 0x07, 0, 0x0c1c0000, 7, 0x00070000 },
{ 0x0, 0x0a, 0x08, 0, 0x0c1d0000, 8, 0x00080000 },
{ 0x0, 0x0b, 0x00, 0, 0x0c240000, 0, 0x00000000 },
{ 0x0, 0x0c, 0x00, 0, 0x0c250000, 0, 0x00000000 },
{ 0x0, 0x0d, 0x00, 0, 0x0c340000, 0, 0x00000000 },
{ 0x0, 0x0e, 0x00, 0, 0x0c260000, 0, 0x00000000 },
{ 0x0, 0x0f, 0x00, 0, 0x0c0f0000, 0, 0x00000000 },
{ 0x0, 0x0f, 0x01, 0, 0x0c100000, 1, 0x00010000 },
{ 0x0, 0x0f, 0x02, 0, 0x0c110000, 2, 0x00020000 },
{ 0x0, 0x0f, 0x03, 0, 0x0c120000, 3, 0x00030000 },
{ 0x0, 0x0f, 0x04, 0, 0x0c130000, 4, 0x00040000 },
{ 0x0, 0x0f, 0x05, 0, 0x0c140000, 5, 0x00050000 },
{ 0x0, 0x10, 0x00, 0, 0x0c290000, 0, 0x00000000 },
{ 0x0, 0x30, 0x00, 0, 0x20ce0000, 0, 0x00000000 },
{ 0x0, 0x31, 0x00, 0, 0x0c1f0000, 0, 0x00000000 },
{ 0x0, 0x31, 0x01, 0, 0x0c200000, 1, 0x00010000 },
{ 0x0, 0x31, 0x02, 0, 0x0c210000, 2, 0x00020000 },
{ 0x0, 0x31, 0x03, 0, 0x0c220000, 3, 0x00030000 },
{ 0x0, 0x32, 0x00, 0, 0x20cc0000, 3, 0x001c0000 },
{ 0x0, 0x32, 0x01, 0, 0x20c80000, 2, 0x00180000 },
{ 0x0, 0x32, 0x02, 0, 0x20c00000, 1, 0x00100000 },
{ 0x0, 0x32, 0x03, 0, 0x20b00000, 0, 0x00000000 },
{ 0x0, 0x33, 0x00, 0, 0x0c360000, 0, 0x00000000 },
{ 0x0, 0x33, 0x01, 0, 0x0c370000, 1, 0x00010000 },
{ 0x0, 0x33, 0x02, 0, 0x0c3a0000, 3, 0x00040000 },
{ 0x0, 0x33, 0x03, 0, 0x0c380000, 2, 0x00020000 },
{ 0x0, 0x38, 0x00, 0, 0x0c600000, 0, 0x00000000 },
{ 0x0, 0x38, 0x01, 0, 0x00000000, 0, 0x00000000 },
{ 0x0, 0x39, 0x00, 0, 0x0c280000, 0, 0x00000000 },
{ 0x1, 0x35, 0x00, 0, 0x00000000, 0, 0x00000000 },
{ 0x1, 0x35, 0x01, 0, 0x00100000, 1, 0x00100000 },
{ 0x1, 0x35, 0x02, 0, 0x05a00000, 11, 0x05a00000 },
{ 0x1, 0x35, 0x03, 0, 0x05b00000, 32, 0x05b00000 },
{ 0x1, 0x35, 0x04, 0, 0x05c00000, 33, 0x05c00000 },
{ 0x1, 0x35, 0x05, 0, 0x05d00000, 12, 0x05d00000 },
{ 0x1, 0x35, 0x06, 0, 0x20000000, 19, 0x20000000 },
{ 0x1, 0x35, 0x07, 0, 0x20100000, 20, 0x20100000 },
{ 0x1, 0x35, 0x08, 0, 0x20a00000, 24, 0x20a00000 },
{ 0x1, 0x35, 0x09, 0, 0x20d00000, 25, 0x20d00000 },
{ 0x1, 0x35, 0x0a, 0, 0x00200000, 2, 0x00200000 },
{ 0x1, 0x35, 0x0b, 0, 0x05800000, 10, 0x05800000 },
{ 0x1, 0x35, 0x0c, 0, 0x05e00000, 13, 0x05e00000 },
{ 0x1, 0x35, 0x0d, 0, 0x20200000, 21, 0x20200000 },
{ 0x1, 0x35, 0x0e, 0, 0x20800000, 23, 0x20800000 },
{ 0x1, 0x35, 0x0f, 0, 0x20e00000, 26, 0x20e00000 },
{ 0x1, 0x35, 0x10, 0, 0x00400000, 3, 0x00400000 },
{ 0x1, 0x35, 0x11, 0, 0x20400000, 22, 0x20400000 },
{ 0x1, 0x35, 0x12, 0, 0x00800000, 4, 0x00800000 },
{ 0x1, 0x35, 0x13, 0, 0x05000000, 9, 0x05000000 },
{ 0x1, 0x35, 0x14, 0, 0x0c800000, 34, 0x0c800000 },
{ 0x1, 0x35, 0x15, 0, 0x01000000, 5, 0x01000000 },
{ 0x1, 0x35, 0x16, 0, 0x03000000, 7, 0x03000000 },
{ 0x1, 0x35, 0x17, 0, 0x04000000, 8, 0x04000000 },
{ 0x1, 0x35, 0x18, 0, 0x0d000000, 16, 0x0d000000 },
{ 0x1, 0x35, 0x19, 0, 0x21000000, 27, 0x21000000 },
{ 0x1, 0x35, 0x1a, 0, 0x02000000, 6, 0x02000000 },
{ 0x1, 0x35, 0x1b, 0, 0x06000000, 14, 0x06000000 },
{ 0x1, 0x35, 0x1c, 0, 0x0e000000, 17, 0x0e000000 },
{ 0x1, 0x35, 0x1d, 0, 0x22000000, 28, 0x22000000 },
{ 0x1, 0x35, 0x1e, 0, 0x08000000, 15, 0x08000000 },
{ 0x1, 0x35, 0x1f, 0, 0x24000000, 29, 0x24000000 },
{ 0x1, 0x35, 0x20, 0, 0x28000000, 30, 0x28000000 },
{ 0x1, 0x35, 0x21, 0, 0x10000000, 18, 0x10000000 },
{ 0x1, 0x35, 0x22, 0, 0x30000000, 31, 0x30000000 },
{ 0x1, 0x37, 0x00, 0, 0x0c640000, 0, 0x00000000 },
{ 0x1, 0x20, 0x00, 0, 0x0c3b0000, 0, 0x00000000 },
{ 0x1, 0x21, 0x00, 0, 0x0c000000, 0, 0x00000000 },
{ 0x1, 0x22, 0x00, 0, 0x0c040000, 0, 0x00000000 },
{ 0x1, 0x23, 0x00, 0, 0x0c050000, 0, 0x00000000 },
{ 0x1, 0x24, 0x00, 0, 0x20cf0000, 0, 0x00000000 },
{ 0x1, 0x25, 0x00, 0, 0x0c2f0000, 0, 0x00000000 },
{ 0x1, 0x26, 0x00, 0, 0x0c230000, 0, 0x00000000 },
{ 0x1, 0x27, 0x00, 0, 0x0c350000, 0, 0x00000000 },
{ 0x1, 0x28, 0x00, 0, 0x0c301000, 0, 0x00000000 },
{ 0x1, 0x29, 0x00, 0, 0x0c302000, 0, 0x00000000 },
{ 0x1, 0x2a, 0x00, 0, 0x0c303000, 0, 0x00000000 },
{ 0x1, 0x2b, 0x00, 0, 0x0c2a0000, 0, 0x00000000 },
{ 0x1, 0x2c, 0x00, 0, 0x0c2b0000, 0, 0x00000000 },
{ 0x1, 0x2c, 0x01, 0, 0x0c2c0000, 1, 0x00010000 },
{ 0x1, 0x2c, 0x02, 0, 0x0c2d0000, 2, 0x00020000 },
{ 0x1, 0x2c, 0x03, 0, 0x0c2e0000, 3, 0x00030000 },
{ 0x1, 0x00, 0x00, 0, 0x0c660000, 0, 0x00000000 },
{ 0x1, 0x01, 0x00, 0, 0x0c020000, 0, 0x00000000 },
{ 0x1, 0x02, 0x00, 0, 0x0c030000, 0, 0x00000000 },
{ 0x1, 0x03, 0x00, 0, 0x0c310000, 0, 0x00000000 },
{ 0x1, 0x04, 0x00, 0, 0x0c320000, 0, 0x00000000 },
{ 0x1, 0x05, 0x00, 0, 0x0c0a0000, 2, 0x00040000 },
{ 0x1, 0x05, 0x01, 0, 0x0c0b0000, 3, 0x00050000 },
{ 0x1, 0x05, 0x02, 0, 0x0c0e0000, 5, 0x00080000 },
{ 0x1, 0x05, 0x03, 0, 0x0c060000, 0, 0x00000000 },
{ 0x1, 0x05, 0x04, 0, 0x0c080000, 1, 0x00020000 },
{ 0x1, 0x05, 0x05, 0, 0x0c0c0000, 4, 0x00060000 },
{ 0x1, 0x06, 0x00, 0, 0x0c330000, 0, 0x00000000 },
{ 0x1, 0x07, 0x00, 0, 0x0c650000, 0, 0x00000000 },
{ 0x1, 0x08, 0x00, 0, 0x0c3e0000, 0, 0x00000000 },
{ 0x1, 0x09, 0x00, 0, 0x0c1e0000, 0, 0x00000000 },
{ 0x1, 0x0a, 0x00, 0, 0x0c150000, 0, 0x00000000 },
{ 0x1, 0x0a, 0x01, 0, 0x0c160000, 1, 0x00010000 },
{ 0x1, 0x0a, 0x02, 0, 0x0c170000, 2, 0x00020000 },
{ 0x1, 0x0a, 0x03, 0, 0x0c180000, 3, 0x00030000 },
{ 0x1, 0x0a, 0x04, 0, 0x0c190000, 4, 0x00040000 },
{ 0x1, 0x0a, 0x05, 0, 0x0c1a0000, 5, 0x00050000 },
{ 0x1, 0x0a, 0x06, 0, 0x0c1b0000, 6, 0x00060000 },
{ 0x1, 0x0a, 0x07, 0, 0x0c1c0000, 7, 0x00070000 },
{ 0x1, 0x0a, 0x08, 0, 0x0c1d0000, 8, 0x00080000 },
{ 0x1, 0x0b, 0x00, 0, 0x0c240000, 0, 0x00000000 },
{ 0x1, 0x0c, 0x00, 0, 0x0c250000, 0, 0x00000000 },
{ 0x1, 0x0d, 0x00, 0, 0x0c340000, 0, 0x00000000 },
{ 0x1, 0x0e, 0x00, 0, 0x0c260000, 0, 0x00000000 },
{ 0x1, 0x0f, 0x00, 0, 0x0c0f0000, 0, 0x00000000 },
{ 0x1, 0x0f, 0x01, 0, 0x0c100000, 1, 0x00010000 },
{ 0x1, 0x0f, 0x02, 0, 0x0c110000, 2, 0x00020000 },
{ 0x1, 0x0f, 0x03, 0, 0x0c120000, 3, 0x00030000 },
{ 0x1, 0x0f, 0x04, 0, 0x0c130000, 4, 0x00040000 },
{ 0x1, 0x0f, 0x05, 0, 0x0c140000, 5, 0x00050000 },
{ 0x1, 0x10, 0x00, 0, 0x0c290000, 0, 0x00000000 },
{ 0x1, 0x30, 0x00, 0, 0x20ce0000, 0, 0x00000000 },
{ 0x1, 0x31, 0x00, 0, 0x0c1f0000, 0, 0x00000000 },
{ 0x1, 0x31, 0x01, 0, 0x0c200000, 1, 0x00010000 },
{ 0x1, 0x31, 0x02, 0, 0x0c210000, 2, 0x00020000 },
{ 0x1, 0x31, 0x03, 0, 0x0c220000, 3, 0x00030000 },
{ 0x1, 0x32, 0x00, 0, 0x20cc0000, 3, 0x001c0000 },
{ 0x1, 0x32, 0x01, 0, 0x20c80000, 2, 0x00180000 },
{ 0x1, 0x32, 0x02, 0, 0x20c00000, 1, 0x00100000 },
{ 0x1, 0x32, 0x03, 0, 0x20b00000, 0, 0x00000000 },
{ 0x1, 0x33, 0x00, 0, 0x0c360000, 0, 0x00000000 },
{ 0x1, 0x33, 0x01, 0, 0x0c370000, 1, 0x00010000 },
{ 0x1, 0x33, 0x02, 0, 0x0c3a0000, 3, 0x00040000 },
{ 0x1, 0x33, 0x03, 0, 0x0c380000, 2, 0x00020000 },
{ 0x1, 0x38, 0x00, 0, 0x0c600000, 0, 0x00000000 },
{ 0x1, 0x38, 0x01, 0, 0x00000000, 0, 0x00000000 },
{ 0x1, 0x39, 0x00, 0, 0x0c280000, 0, 0x00000000 },
{ 0x2, 0x34, 0x00, 0, 0x40000000, 0, 0x40000000 },
{ 0x2, 0x34, 0x01, 0, 0x80000000, 1, 0x80000000 },
{ 0x2, 0x36, 0x00, 0, 0x0c400000, 0, 0x0c400000 },
{ 0x2, 0x36, 0x01, 0, 0x00000000, 0, 0x00000000 },
{ 0x3, 0x35, 0x00, 0, 0x00000000, 0, 0x00000000 },
{ 0x3, 0x35, 0x01, 0, 0x00100000, 1, 0x00100000 },
{ 0x3, 0x35, 0x02, 0, 0x05a00000, 11, 0x05a00000 },
{ 0x3, 0x35, 0x03, 0, 0x05b00000, 32, 0x05b00000 },
{ 0x3, 0x35, 0x04, 0, 0x05c00000, 33, 0x05c00000 },
{ 0x3, 0x35, 0x05, 0, 0x05d00000, 12, 0x05d00000 },
{ 0x3, 0x35, 0x06, 0, 0x20000000, 19, 0x20000000 },
{ 0x3, 0x35, 0x07, 0, 0x20100000, 20, 0x20100000 },
{ 0x3, 0x35, 0x08, 0, 0x20a00000, 24, 0x20a00000 },
{ 0x3, 0x35, 0x09, 0, 0x20d00000, 25, 0x20d00000 },
{ 0x3, 0x35, 0x0a, 0, 0x00200000, 2, 0x00200000 },
{ 0x3, 0x35, 0x0b, 0, 0x05800000, 10, 0x05800000 },
{ 0x3, 0x35, 0x0c, 0, 0x05e00000, 13, 0x05e00000 },
{ 0x3, 0x35, 0x0d, 0, 0x20200000, 21, 0x20200000 },
{ 0x3, 0x35, 0x0e, 0, 0x20800000, 23, 0x20800000 },
{ 0x3, 0x35, 0x0f, 0, 0x20e00000, 26, 0x20e00000 },
{ 0x3, 0x35, 0x10, 0, 0x00400000, 3, 0x00400000 },
{ 0x3, 0x35, 0x11, 0, 0x20400000, 22, 0x20400000 },
{ 0x3, 0x35, 0x12, 0, 0x00800000, 4, 0x00800000 },
{ 0x3, 0x35, 0x13, 0, 0x50000000, 9, 0x05000000 },
{ 0x3, 0x35, 0x14, 0, 0xc0800000, 34, 0x0c800000 },
{ 0x3, 0x35, 0x15, 0, 0x10000000, 5, 0x01000000 },
{ 0x3, 0x35, 0x16, 0, 0x30000000, 7, 0x03000000 },
{ 0x3, 0x35, 0x17, 0, 0x04000000, 8, 0x04000000 },
{ 0x3, 0x35, 0x18, 0, 0x0d000000, 16, 0x0d000000 },
{ 0x3, 0x35, 0x19, 0, 0x21000000, 27, 0x21000000 },
{ 0x3, 0x35, 0x1a, 0, 0x02000000, 6, 0x02000000 },
{ 0x3, 0x35, 0x1b, 0, 0x06000000, 14, 0x06000000 },
{ 0x3, 0x35, 0x1c, 0, 0x0e000000, 17, 0x0e000000 },
{ 0x3, 0x35, 0x1d, 0, 0x22000000, 28, 0x22000000 },
{ 0x3, 0x35, 0x1e, 0, 0x08000000, 15, 0x08000000 },
{ 0x3, 0x35, 0x1f, 0, 0x24000000, 29, 0x24000000 },
{ 0x3, 0x35, 0x20, 0, 0x28000000, 30, 0x28000000 },
{ 0x3, 0x35, 0x21, 0, 0x10000000, 18, 0x10000000 },
{ 0x3, 0x35, 0x22, 0, 0x30000000, 31, 0x30000000 },
{ 0x3, 0x37, 0x00, 0, 0x0c640000, 0, 0x00000000 },
{ 0x3, 0x20, 0x00, 0, 0x0c3b0000, 0, 0x00000000 },
{ 0x3, 0x21, 0x00, 0, 0x0c000000, 0, 0x00000000 },
{ 0x3, 0x22, 0x00, 0, 0x0c040000, 0, 0x00000000 },
{ 0x3, 0x23, 0x00, 0, 0x0c050000, 0, 0x00000000 },
{ 0x3, 0x24, 0x00, 0, 0x20cf0000, 0, 0x00000000 },
{ 0x3, 0x25, 0x00, 0, 0x0c2f0000, 0, 0x00000000 },
{ 0x3, 0x26, 0x00, 0, 0x0c230000, 0, 0x00000000 },
{ 0x3, 0x27, 0x00, 0, 0x0c350000, 0, 0x00000000 },
{ 0x3, 0x28, 0x00, 0, 0x0c301000, 0, 0x00000000 },
{ 0x3, 0x29, 0x00, 0, 0x0c302000, 0, 0x00000000 },
{ 0x3, 0x2a, 0x00, 0, 0x0c303000, 0, 0x00000000 },
{ 0x3, 0x2b, 0x00, 0, 0x0c2a0000, 0, 0x00000000 },
{ 0x3, 0x2c, 0x00, 0, 0x0c2b0000, 0, 0x00000000 },
{ 0x3, 0x2c, 0x01, 0, 0x0c2c0000, 1, 0x00010000 },
{ 0x3, 0x2c, 0x02, 0, 0x0c2d0000, 2, 0x00020000 },
{ 0x3, 0x2c, 0x03, 0, 0x0c2e0000, 3, 0x00030000 },
{ 0x3, 0x00, 0x00, 0, 0x0c660000, 0, 0x00000000 },
{ 0x3, 0x01, 0x00, 0, 0x0c020000, 0, 0x00000000 },
{ 0x3, 0x02, 0x00, 0, 0x0c030000, 0, 0x00000000 },
{ 0x3, 0x03, 0x00, 0, 0x0c310000, 0, 0x00000000 },
{ 0x3, 0x04, 0x00, 0, 0x0c320000, 0, 0x00000000 },
{ 0x3, 0x05, 0x00, 0, 0x0c0a0000, 2, 0x00040000 },
{ 0x3, 0x05, 0x01, 0, 0x0c0b0000, 3, 0x00050000 },
{ 0x3, 0x05, 0x02, 0, 0x0c0e0000, 5, 0x00080000 },
{ 0x3, 0x05, 0x03, 0, 0x0c060000, 0, 0x00000000 },
{ 0x3, 0x05, 0x04, 0, 0x0c080000, 1, 0x00020000 },
{ 0x3, 0x05, 0x05, 0, 0x0c0c0000, 4, 0x00060000 },
{ 0x3, 0x06, 0x00, 0, 0x0c330000, 0, 0x00000000 },
{ 0x3, 0x07, 0x00, 0, 0x0c650000, 0, 0x00000000 },
{ 0x3, 0x08, 0x00, 0, 0x0c3e0000, 0, 0x00000000 },
{ 0x3, 0x09, 0x00, 0, 0x0c1e0000, 0, 0x00000000 },
{ 0x3, 0x0a, 0x00, 0, 0x0c150000, 0, 0x00000000 },
{ 0x3, 0x0a, 0x01, 0, 0x0c160000, 1, 0x00010000 },
{ 0x3, 0x0a, 0x02, 0, 0x0c170000, 2, 0x00020000 },
{ 0x3, 0x0a, 0x03, 0, 0x0c180000, 3, 0x00030000 },
{ 0x3, 0x0a, 0x04, 0, 0x0c190000, 4, 0x00040000 },
{ 0x3, 0x0a, 0x05, 0, 0x0c1a0000, 5, 0x00050000 },
{ 0x3, 0x0a, 0x06, 0, 0x0c1b0000, 6, 0x00060000 },
{ 0x3, 0x0a, 0x07, 0, 0x0c1c0000, 7, 0x00070000 },
{ 0x3, 0x0a, 0x08, 0, 0x0c1d0000, 8, 0x00080000 },
{ 0x3, 0x0b, 0x00, 0, 0x0c240000, 0, 0x00000000 },
{ 0x3, 0x0c, 0x00, 0, 0x0c250000, 0, 0x00000000 },
{ 0x3, 0x0d, 0x00, 0, 0x0c340000, 0, 0x00000000 },
{ 0x3, 0x0e, 0x00, 0, 0x0c260000, 0, 0x00000000 },
{ 0x3, 0x0f, 0x00, 0, 0x0c0f0000, 0, 0x00000000 },
{ 0x3, 0x0f, 0x01, 0, 0x0c100000, 1, 0x00010000 },
{ 0x3, 0x0f, 0x02, 0, 0x0c110000, 2, 0x00020000 },
{ 0x3, 0x0f, 0x03, 0, 0x0c120000, 3, 0x00030000 },
{ 0x3, 0x0f, 0x04, 0, 0x0c130000, 4, 0x00040000 },
{ 0x3, 0x0f, 0x05, 0, 0x0c140000, 5, 0x00050000 },
{ 0x3, 0x10, 0x00, 0, 0x0c290000, 0, 0x00000000 },
{ 0x3, 0x30, 0x00, 0, 0x20ce0000, 0, 0x00000000 },
{ 0x3, 0x31, 0x00, 0, 0x0c1f0000, 0, 0x00000000 },
{ 0x3, 0x31, 0x01, 0, 0x0c200000, 1, 0x00010000 },
{ 0x3, 0x31, 0x02, 0, 0x0c210000, 2, 0x00020000 },
{ 0x3, 0x31, 0x03, 0, 0x0c220000, 3, 0x00030000 },
{ 0x3, 0x32, 0x00, 0, 0x20cc0000, 3, 0x001c0000 },
{ 0x3, 0x32, 0x01, 0, 0x20c80000, 2, 0x00180000 },
{ 0x3, 0x32, 0x02, 0, 0x20c00000, 1, 0x00100000 },
{ 0x3, 0x32, 0x03, 0, 0x20b00000, 0, 0x00000000 },
{ 0x3, 0x33, 0x00, 0, 0x0c360000, 0, 0x00000000 },
{ 0x3, 0x33, 0x01, 0, 0x0c370000, 1, 0x00010000 },
{ 0x3, 0x33, 0x02, 0, 0x0c3a0000, 3, 0x00040000 },
{ 0x3, 0x33, 0x03, 0, 0x0c380000, 2, 0x00020000 },
{ 0x3, 0x38, 0x00, 0, 0x0c600000, 0, 0x00000000 },
{ 0x3, 0x38, 0x01, 0, 0x00000000, 0, 0x00000000 },
{ 0x3, 0x39, 0x00, 0, 0x0c280000, 0, 0x00000000 }
};
/*
* SCE/RCE NOC aperture lookup table as per file "AON_NOC_Structure.info".
*/
static const char * const tegra194_scenoc_routeid_initflow[] = {
[0x0] = "cbb_i/I/0",
[0x1] = "cpu_m_i/I/0",
[0x2] = "cpu_p_i/I/0",
[0x3] = "dma_m_i/I/0",
[0x4] = "dma_p_i/I/0",
[0x5] = "RESERVED",
[0x6] = "RESERVED",
[0x7] = "RESERVED"
};
static const char * const tegra194_scenoc_routeid_targflow[] = {
[0x00] = "multiport0_t/T/atcm_cfg",
[0x01] = "multiport0_t/T/car",
[0x02] = "multiport0_t/T/cast",
[0x03] = "multiport0_t/T/cfg",
[0x04] = "multiport0_t/T/dast",
[0x05] = "multiport0_t/T/dma",
[0x06] = "multiport0_t/T/err_collator",
[0x07] = "multiport0_t/T/err_collator_car",
[0x08] = "multiport0_t/T/fpga_misc",
[0x09] = "multiport0_t/T/fpga_uart",
[0x0a] = "multiport0_t/T/gte",
[0x0b] = "multiport0_t/T/hsp",
[0x0c] = "multiport0_t/T/misc",
[0x0d] = "multiport0_t/T/pm",
[0x0e] = "multiport0_t/T/tke",
[0x0f] = "RESERVED",
[0x10] = "multiport1_t/T/hsm",
[0x11] = "multiport1_t/T/vic0",
[0x12] = "multiport1_t/T/vic1",
[0x13] = "ast0_t/T/0",
[0x14] = "ast1_t/T/0",
[0x15] = "cbb_t/T/0",
[0x16] = "cpu_t/T/0",
[0x17] = "sce_noc_firewall/T/0",
[0x18] = "svc_t/T/0",
[0x19] = "RESERVED",
[0x1a] = "RESERVED",
[0x1b] = "RESERVED",
[0x1c] = "RESERVED",
[0x1d] = "RESERVED",
[0x1e] = "RESERVED",
[0x1f] = "RESERVED"
};
/*
* Fields of SCE/RCE NOC lookup table:
* Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
* Targ mapping, Targ localAddress
* ----------------------------------------------------------------------------
*/
static const struct tegra194_cbb_aperture tegra194_scenoc_apert_lookup[] = {
{ 0x0, 0x16, 0x0, 0, 0x0b400000, 0, 0x0b400000 },
{ 0x0, 0x16, 0x1, 0, 0x0bc00000, 1, 0x0bc00000 },
{ 0x0, 0x0, 0x0, 0, 0x0b000000, 0, 0x00000000 },
{ 0x0, 0x0, 0x1, 0, 0x0b800000, 1, 0x00000000 },
{ 0x0, 0x1, 0x0, 0, 0x20de0000, 3, 0x000e0000 },
{ 0x0, 0x1, 0x1, 0, 0x210e0000, 7, 0x000e0000 },
{ 0x0, 0x1, 0x2, 0, 0x20dc0000, 2, 0x000c0000 },
{ 0x0, 0x1, 0x3, 0, 0x210c0000, 6, 0x000c0000 },
{ 0x0, 0x1, 0x4, 0, 0x20d80000, 1, 0x00080000 },
{ 0x0, 0x1, 0x5, 0, 0x21080000, 5, 0x00080000 },
{ 0x0, 0x1, 0x6, 0, 0x20d00000, 0, 0x00000000 },
{ 0x0, 0x1, 0x7, 0, 0x21000000, 4, 0x00000000 },
{ 0x0, 0x2, 0x0, 0, 0x0b040000, 0, 0x00000000 },
{ 0x0, 0x2, 0x1, 0, 0x0b840000, 1, 0x00000000 },
{ 0x0, 0x3, 0x0, 0, 0x0b230000, 0, 0x00000000 },
{ 0x0, 0x3, 0x1, 0, 0x0ba30000, 1, 0x00000000 },
{ 0x0, 0x4, 0x0, 0, 0x0b050000, 0, 0x00000000 },
{ 0x0, 0x4, 0x1, 0, 0x0b850000, 1, 0x00000000 },
{ 0x0, 0x5, 0x0, 0, 0x0b060000, 0, 0x00000000 },
{ 0x0, 0x5, 0x1, 0, 0x0b070000, 1, 0x00010000 },
{ 0x0, 0x5, 0x2, 0, 0x0b080000, 2, 0x00020000 },
{ 0x0, 0x5, 0x3, 0, 0x0b090000, 3, 0x00030000 },
{ 0x0, 0x5, 0x4, 0, 0x0b0a0000, 4, 0x00040000 },
{ 0x0, 0x5, 0x5, 0, 0x0b0b0000, 5, 0x00050000 },
{ 0x0, 0x5, 0x6, 0, 0x0b0c0000, 6, 0x00060000 },
{ 0x0, 0x5, 0x7, 0, 0x0b0d0000, 7, 0x00070000 },
{ 0x0, 0x5, 0x8, 0, 0x0b0e0000, 8, 0x00080000 },
{ 0x0, 0x5, 0x9, 0, 0x0b860000, 9, 0x00000000 },
{ 0x0, 0x5, 0xa, 0, 0x0b870000, 10, 0x00010000 },
{ 0x0, 0x5, 0xb, 0, 0x0b880000, 11, 0x00020000 },
{ 0x0, 0x5, 0xc, 0, 0x0b890000, 12, 0x00030000 },
{ 0x0, 0x5, 0xd, 0, 0x0b8a0000, 13, 0x00040000 },
{ 0x0, 0x5, 0xe, 0, 0x0b8b0000, 14, 0x00050000 },
{ 0x0, 0x5, 0xf, 0, 0x0b8c0000, 15, 0x00060000 },
{ 0x0, 0x5, 0x10, 0, 0x0b8d0000, 16, 0x00070000 },
{ 0x0, 0x5, 0x11, 0, 0x0b8e0000, 17, 0x00080000 },
{ 0x0, 0x6, 0x0, 0, 0x0b650000, 0, 0x00000000 },
{ 0x0, 0x6, 0x1, 0, 0x0be50000, 1, 0x00000000 },
{ 0x0, 0x7, 0x0, 0, 0x20df0000, 0, 0x00000000 },
{ 0x0, 0x7, 0x1, 0, 0x210f0000, 1, 0x00000000 },
{ 0x0, 0x8, 0x0, 0, 0x0b3e0000, 0, 0x00000000 },
{ 0x0, 0x8, 0x1, 0, 0x0bbe0000, 1, 0x00000000 },
{ 0x0, 0x9, 0x0, 0, 0x0b3d0000, 0, 0x00000000 },
{ 0x0, 0x9, 0x1, 0, 0x0bbd0000, 1, 0x00000000 },
{ 0x0, 0xa, 0x0, 0, 0x0b1e0000, 0, 0x00000000 },
{ 0x0, 0xa, 0x1, 0, 0x0b9e0000, 1, 0x00000000 },
{ 0x0, 0xb, 0x0, 0, 0x0b150000, 0, 0x00000000 },
{ 0x0, 0xb, 0x1, 0, 0x0b160000, 1, 0x00010000 },
{ 0x0, 0xb, 0x2, 0, 0x0b170000, 2, 0x00020000 },
{ 0x0, 0xb, 0x3, 0, 0x0b180000, 3, 0x00030000 },
{ 0x0, 0xb, 0x4, 0, 0x0b190000, 4, 0x00040000 },
{ 0x0, 0xb, 0x5, 0, 0x0b1a0000, 5, 0x00050000 },
{ 0x0, 0xb, 0x6, 0, 0x0b1b0000, 6, 0x00060000 },
{ 0x0, 0xb, 0x7, 0, 0x0b1c0000, 7, 0x00070000 },
{ 0x0, 0xb, 0x8, 0, 0x0b1d0000, 8, 0x00080000 },
{ 0x0, 0xb, 0x9, 0, 0x0b950000, 9, 0x00000000 },
{ 0x0, 0xb, 0xa, 0, 0x0b960000, 10, 0x00010000 },
{ 0x0, 0xb, 0xb, 0, 0x0b970000, 11, 0x00020000 },
{ 0x0, 0xb, 0xc, 0, 0x0b980000, 12, 0x00030000 },
{ 0x0, 0xb, 0xd, 0, 0x0b990000, 13, 0x00040000 },
{ 0x0, 0xb, 0xe, 0, 0x0b9a0000, 14, 0x00050000 },
{ 0x0, 0xb, 0xf, 0, 0x0b9b0000, 15, 0x00060000 },
{ 0x0, 0xb, 0x10, 0, 0x0b9c0000, 16, 0x00070000 },
{ 0x0, 0xb, 0x11, 0, 0x0b9d0000, 17, 0x00080000 },
{ 0x0, 0xc, 0x0, 0, 0x0b660000, 0, 0x00000000 },
{ 0x0, 0xc, 0x1, 0, 0x0be60000, 1, 0x00000000 },
{ 0x0, 0xd, 0x0, 0, 0x0b1f0000, 0, 0x00000000 },
{ 0x0, 0xd, 0x1, 0, 0x0b200000, 1, 0x00010000 },
{ 0x0, 0xd, 0x2, 0, 0x0b210000, 2, 0x00020000 },
{ 0x0, 0xd, 0x3, 0, 0x0b220000, 3, 0x00030000 },
{ 0x0, 0xd, 0x4, 0, 0x0b9f0000, 4, 0x00000000 },
{ 0x0, 0xd, 0x5, 0, 0x0ba00000, 5, 0x00010000 },
{ 0x0, 0xd, 0x6, 0, 0x0ba10000, 6, 0x00020000 },
{ 0x0, 0xd, 0x7, 0, 0x0ba20000, 7, 0x00030000 },
{ 0x0, 0xe, 0x0, 0, 0x0b0f0000, 0, 0x00000000 },
{ 0x0, 0xe, 0x1, 0, 0x0b100000, 1, 0x00010000 },
{ 0x0, 0xe, 0x2, 0, 0x0b110000, 2, 0x00020000 },
{ 0x0, 0xe, 0x3, 0, 0x0b120000, 3, 0x00030000 },
{ 0x0, 0xe, 0x4, 0, 0x0b130000, 4, 0x00040000 },
{ 0x0, 0xe, 0x5, 0, 0x0b140000, 5, 0x00050000 },
{ 0x0, 0xe, 0x6, 0, 0x0b8f0000, 6, 0x00000000 },
{ 0x0, 0xe, 0x7, 0, 0x0b900000, 7, 0x00010000 },
{ 0x0, 0xe, 0x8, 0, 0x0b910000, 8, 0x00020000 },
{ 0x0, 0xe, 0x9, 0, 0x0b920000, 9, 0x00030000 },
{ 0x0, 0xe, 0xa, 0, 0x0b930000, 10, 0x00040000 },
{ 0x0, 0xe, 0xb, 0, 0x0b940000, 11, 0x00050000 },
{ 0x0, 0x10, 0x0, 0, 0x0b240000, 0, 0x00000000 },
{ 0x0, 0x10, 0x1, 0, 0x0ba40000, 1, 0x00000000 },
{ 0x0, 0x11, 0x0, 0, 0x0b020000, 0, 0x00000000 },
{ 0x0, 0x11, 0x1, 0, 0x0b820000, 1, 0x00000000 },
{ 0x0, 0x12, 0x0, 0, 0x0b030000, 0, 0x00000000 },
{ 0x0, 0x12, 0x1, 0, 0x0b830000, 1, 0x00000000 },
{ 0x0, 0x17, 0x0, 0, 0x0b640000, 0, 0x00000000 },
{ 0x0, 0x17, 0x1, 0, 0x0be40000, 1, 0x00000000 },
{ 0x0, 0x18, 0x0, 0, 0x0b600000, 0, 0x00000000 },
{ 0x0, 0x18, 0x1, 0, 0x0be00000, 1, 0x00000000 },
{ 0x0, 0x18, 0x2, 0, 0x00000000, 0, 0x00000000 },
{ 0x0, 0x18, 0x3, 0, 0x00000000, 0, 0x00000000 },
{ 0x1, 0x13, 0x0, 0, 0x40000000, 0, 0x40000000 },
{ 0x1, 0x13, 0x1, 1, 0x80000000, 1, 0x80000000 },
{ 0x1, 0x13, 0x2, 0, 0x00000000, 0, 0x00000000 },
{ 0x2, 0x15, 0x0, 0, 0x20c00000, 8, 0x20c00000 },
{ 0x2, 0x15, 0x1, 0, 0x21100000, 22, 0x21100000 },
{ 0x2, 0x15, 0x2, 0, 0x20e00000, 9, 0x20e00000 },
{ 0x2, 0x15, 0x3, 0, 0x21200000, 23, 0x21200000 },
{ 0x2, 0x15, 0x4, 0, 0x20800000, 7, 0x20800000 },
{ 0x2, 0x15, 0x5, 0, 0x21400000, 24, 0x21400000 },
{ 0x2, 0x15, 0x6, 0, 0x0b000000, 18, 0x0b000000 },
{ 0x2, 0x15, 0x7, 0, 0x0b800000, 3, 0x0b800000 },
{ 0x2, 0x15, 0x8, 0, 0x20000000, 6, 0x20000000 },
{ 0x2, 0x15, 0x9, 0, 0x21800000, 25, 0x21800000 },
{ 0x2, 0x15, 0xa, 0, 0x0a000000, 2, 0x0a000000 },
{ 0x2, 0x15, 0xb, 0, 0x0a000000, 17, 0x0a000000 },
{ 0x2, 0x15, 0xc, 0, 0x20000000, 21, 0x20000000 },
{ 0x2, 0x15, 0xd, 0, 0x21000000, 10, 0x21000000 },
{ 0x2, 0x15, 0xe, 0, 0x08000000, 1, 0x08000000 },
{ 0x2, 0x15, 0xf, 0, 0x08000000, 16, 0x08000000 },
{ 0x2, 0x15, 0x10, 0, 0x22000000, 11, 0x22000000 },
{ 0x2, 0x15, 0x11, 0, 0x22000000, 26, 0x22000000 },
{ 0x2, 0x15, 0x12, 0, 0x0c000000, 4, 0x0c000000 },
{ 0x2, 0x15, 0x13, 0, 0x0c000000, 19, 0x0c000000 },
{ 0x2, 0x15, 0x14, 0, 0x24000000, 12, 0x24000000 },
{ 0x2, 0x15, 0x15, 0, 0x24000000, 27, 0x24000000 },
{ 0x2, 0x15, 0x16, 0, 0x00000000, 0, 0x00000000 },
{ 0x2, 0x15, 0x17, 0, 0x00000000, 15, 0x00000000 },
{ 0x2, 0x15, 0x18, 0, 0x28000000, 13, 0x28000000 },
{ 0x2, 0x15, 0x19, 0, 0x28000000, 28, 0x28000000 },
{ 0x2, 0x15, 0x1a, 0, 0x10000000, 5, 0x10000000 },
{ 0x2, 0x15, 0x1b, 0, 0x10000000, 20, 0x10000000 },
{ 0x2, 0x15, 0x1c, 0, 0x30000000, 14, 0x30000000 },
{ 0x2, 0x15, 0x1d, 0, 0x30000000, 29, 0x30000000 },
{ 0x2, 0x0, 0x0, 0, 0x0b000000, 0, 0x00000000 },
{ 0x2, 0x0, 0x1, 0, 0x0b800000, 1, 0x00000000 },
{ 0x2, 0x1, 0x0, 0, 0x20de0000, 3, 0x000e0000 },
{ 0x2, 0x1, 0x1, 0, 0x210e0000, 7, 0x000e0000 },
{ 0x2, 0x1, 0x2, 0, 0x20dc0000, 2, 0x000c0000 },
{ 0x2, 0x1, 0x3, 0, 0x210c0000, 6, 0x000c0000 },
{ 0x2, 0x1, 0x4, 0, 0x20d80000, 1, 0x00080000 },
{ 0x2, 0x1, 0x5, 0, 0x21080000, 5, 0x00080000 },
{ 0x2, 0x1, 0x6, 0, 0x20d00000, 0, 0x00000000 },
{ 0x2, 0x1, 0x7, 0, 0x21000000, 4, 0x00000000 },
{ 0x2, 0x2, 0x0, 0, 0x0b040000, 0, 0x00000000 },
{ 0x2, 0x2, 0x1, 0, 0x0b840000, 1, 0x00000000 },
{ 0x2, 0x3, 0x0, 0, 0x0b230000, 0, 0x00000000 },
{ 0x2, 0x3, 0x1, 0, 0x0ba30000, 1, 0x00000000 },
{ 0x2, 0x4, 0x0, 0, 0x0b050000, 0, 0x00000000 },
{ 0x2, 0x4, 0x1, 0, 0x0b850000, 1, 0x00000000 },
{ 0x2, 0x5, 0x0, 0, 0x0b060000, 0, 0x00000000 },
{ 0x2, 0x5, 0x1, 0, 0x0b070000, 1, 0x00010000 },
{ 0x2, 0x5, 0x2, 0, 0x0b080000, 2, 0x00020000 },
{ 0x2, 0x5, 0x3, 0, 0x0b090000, 3, 0x00030000 },
{ 0x2, 0x5, 0x4, 0, 0x0b0a0000, 4, 0x00040000 },
{ 0x2, 0x5, 0x5, 0, 0x0b0b0000, 5, 0x00050000 },
{ 0x2, 0x5, 0x6, 0, 0x0b0c0000, 6, 0x00060000 },
{ 0x2, 0x5, 0x7, 0, 0x0b0d0000, 7, 0x00070000 },
{ 0x2, 0x5, 0x8, 0, 0x0b0e0000, 8, 0x00080000 },
{ 0x2, 0x5, 0x9, 0, 0x0b860000, 9, 0x00000000 },
{ 0x2, 0x5, 0xa, 0, 0x0b870000, 10, 0x00010000 },
{ 0x2, 0x5, 0xb, 0, 0x0b880000, 11, 0x00020000 },
{ 0x2, 0x5, 0xc, 0, 0x0b890000, 12, 0x00030000 },
{ 0x2, 0x5, 0xd, 0, 0x0b8a0000, 13, 0x00040000 },
{ 0x2, 0x5, 0xe, 0, 0x0b8b0000, 14, 0x00050000 },
{ 0x2, 0x5, 0xf, 0, 0x0b8c0000, 15, 0x00060000 },
{ 0x2, 0x5, 0x10, 0, 0x0b8d0000, 16, 0x00070000 },
{ 0x2, 0x5, 0x11, 0, 0x0b8e0000, 17, 0x00080000 },
{ 0x2, 0x6, 0x0, 0, 0x0b650000, 0, 0x00000000 },
{ 0x2, 0x6, 0x1, 0, 0x0be50000, 1, 0x00000000 },
{ 0x2, 0x7, 0x0, 0, 0x20df0000, 0, 0x00000000 },
{ 0x2, 0x7, 0x1, 0, 0x210f0000, 1, 0x00000000 },
{ 0x2, 0x8, 0x0, 0, 0x0b3e0000, 0, 0x00000000 },
{ 0x2, 0x8, 0x1, 0, 0x0bbe0000, 1, 0x00000000 },
{ 0x2, 0x9, 0x0, 0, 0x0b3d0000, 0, 0x00000000 },
{ 0x2, 0x9, 0x1, 0, 0x0bbd0000, 1, 0x00000000 },
{ 0x2, 0xa, 0x0, 0, 0x0b1e0000, 0, 0x00000000 },
{ 0x2, 0xa, 0x1, 0, 0x0b9e0000, 1, 0x00000000 },
{ 0x2, 0xb, 0x0, 0, 0x0b150000, 0, 0x00000000 },
{ 0x2, 0xb, 0x1, 0, 0x0b160000, 1, 0x00010000 },
{ 0x2, 0xb, 0x2, 0, 0x0b170000, 2, 0x00020000 },
{ 0x2, 0xb, 0x3, 0, 0x0b180000, 3, 0x00030000 },
{ 0x2, 0xb, 0x4, 0, 0x0b190000, 4, 0x00040000 },
{ 0x2, 0xb, 0x5, 0, 0x0b1a0000, 5, 0x00050000 },
{ 0x2, 0xb, 0x6, 0, 0x0b1b0000, 6, 0x00060000 },
{ 0x2, 0xb, 0x7, 0, 0x0b1c0000, 7, 0x00070000 },
{ 0x2, 0xb, 0x8, 0, 0x0b1d0000, 8, 0x00080000 },
{ 0x2, 0xb, 0x9, 0, 0x0b950000, 9, 0x00000000 },
{ 0x2, 0xb, 0xa, 0, 0x0b960000, 10, 0x00010000 },
{ 0x2, 0xb, 0xb, 0, 0x0b970000, 11, 0x00020000 },
{ 0x2, 0xb, 0xc, 0, 0x0b980000, 12, 0x00030000 },
{ 0x2, 0xb, 0xd, 0, 0x0b990000, 13, 0x00040000 },
{ 0x2, 0xb, 0xe, 0, 0x0b9a0000, 14, 0x00050000 },
{ 0x2, 0xb, 0xf, 0, 0x0b9b0000, 15, 0x00060000 },
{ 0x2, 0xb, 0x10, 0, 0x0b9c0000, 16, 0x00070000 },
{ 0x2, 0xb, 0x11, 0, 0x0b9d0000, 17, 0x00080000 },
{ 0x2, 0xc, 0x0, 0, 0x0b660000, 0, 0x00000000 },
{ 0x2, 0xc, 0x1, 0, 0x0be60000, 1, 0x00000000 },
{ 0x2, 0xd, 0x0, 0, 0x0b1f0000, 0, 0x00000000 },
{ 0x2, 0xd, 0x1, 0, 0x0b200000, 1, 0x00010000 },
{ 0x2, 0xd, 0x2, 0, 0x0b210000, 2, 0x00020000 },
{ 0x2, 0xd, 0x3, 0, 0x0b220000, 3, 0x00030000 },
{ 0x2, 0xd, 0x4, 0, 0x0b9f0000, 4, 0x00000000 },
{ 0x2, 0xd, 0x5, 0, 0x0ba00000, 5, 0x00010000 },
{ 0x2, 0xd, 0x6, 0, 0x0ba10000, 6, 0x00020000 },
{ 0x2, 0xd, 0x7, 0, 0x0ba20000, 7, 0x00030000 },
{ 0x2, 0xe, 0x0, 0, 0x0b0f0000, 0, 0x00000000 },
{ 0x2, 0xe, 0x1, 0, 0x0b100000, 1, 0x00010000 },
{ 0x2, 0xe, 0x2, 0, 0x0b110000, 2, 0x00020000 },
{ 0x2, 0xe, 0x3, 0, 0x0b120000, 3, 0x00030000 },
{ 0x2, 0xe, 0x4, 0, 0x0b130000, 4, 0x00040000 },
{ 0x2, 0xe, 0x5, 0, 0x0b140000, 5, 0x00050000 },
{ 0x2, 0xe, 0x6, 0, 0x0b8f0000, 6, 0x00000000 },
{ 0x2, 0xe, 0x7, 0, 0x0b900000, 7, 0x00010000 },
{ 0x2, 0xe, 0x8, 0, 0x0b910000, 8, 0x00020000 },
{ 0x2, 0xe, 0x9, 0, 0x0b920000, 9, 0x00030000 },
{ 0x2, 0xe, 0xa, 0, 0x0b930000, 10, 0x00040000 },
{ 0x2, 0xe, 0xb, 0, 0x0b940000, 11, 0x00050000 },
{ 0x2, 0x10, 0x0, 0, 0x0b240000, 0, 0x00000000 },
{ 0x2, 0x10, 0x1, 0, 0x0ba40000, 1, 0x00000000 },
{ 0x2, 0x11, 0x0, 0, 0x0b020000, 0, 0x00000000 },
{ 0x2, 0x11, 0x1, 0, 0x0b820000, 1, 0x00000000 },
{ 0x2, 0x12, 0x0, 0, 0x0b030000, 0, 0x00000000 },
{ 0x2, 0x12, 0x1, 0, 0x0b830000, 1, 0x00000000 },
{ 0x2, 0x17, 0x0, 0, 0x0b640000, 0, 0x00000000 },
{ 0x2, 0x17, 0x1, 0, 0x0be40000, 1, 0x00000000 },
{ 0x2, 0x18, 0x0, 0, 0x0b600000, 0, 0x00000000 },
{ 0x2, 0x18, 0x1, 0, 0x0be00000, 1, 0x00000000 },
{ 0x2, 0x18, 0x2, 0, 0x00000000, 0, 0x00000000 },
{ 0x2, 0x18, 0x3, 0, 0x00000000, 0, 0x00000000 },
{ 0x3, 0x14, 0x0, 0, 0x40000000, 0, 0x40000000 },
{ 0x3, 0x14, 0x1, 1, 0x80000000, 1, 0x80000000 },
{ 0x3, 0x16, 0x0, 2, 0x0b400000, 0, 0x0b400000 },
{ 0x3, 0x16, 0x1, 2, 0x0bc00000, 1, 0x0bc00000 },
{ 0x3, 0x16, 0x2, 0, 0x00000000, 0, 0x00000000 },
{ 0x3, 0x16, 0x3, 0, 0x00000000, 0, 0x00000000 },
{ 0x4, 0x15, 0x0, 0, 0x20c00000, 8, 0x20c00000 },
{ 0x4, 0x15, 0x1, 0, 0x21100000, 22, 0x21100000 },
{ 0x4, 0x15, 0x2, 0, 0x20e00000, 9, 0x20e00000 },
{ 0x4, 0x15, 0x3, 0, 0x21200000, 23, 0x21200000 },
{ 0x4, 0x15, 0x4, 0, 0x20800000, 7, 0x20800000 },
{ 0x4, 0x15, 0x5, 0, 0x21400000, 24, 0x21400000 },
{ 0x4, 0x15, 0x6, 0, 0x0b000000, 18, 0x0b000000 },
{ 0x4, 0x15, 0x7, 0, 0x0b800000, 3, 0x0b800000 },
{ 0x4, 0x15, 0x8, 0, 0x20000000, 6, 0x20000000 },
{ 0x4, 0x15, 0x9, 0, 0x21800000, 25, 0x21800000 },
{ 0x4, 0x15, 0xa, 0, 0x0a000000, 2, 0x0a000000 },
{ 0x4, 0x15, 0xb, 0, 0x0a000000, 17, 0x0a000000 },
{ 0x4, 0x15, 0xc, 0, 0x20000000, 21, 0x20000000 },
{ 0x4, 0x15, 0xd, 0, 0x21000000, 10, 0x21000000 },
{ 0x4, 0x15, 0xe, 0, 0x08000000, 1, 0x08000000 },
{ 0x4, 0x15, 0xf, 0, 0x08000000, 16, 0x08000000 },
{ 0x4, 0x15, 0x10, 0, 0x22000000, 11, 0x22000000 },
{ 0x4, 0x15, 0x11, 0, 0x22000000, 26, 0x22000000 },
{ 0x4, 0x15, 0x12, 0, 0x0c000000, 4, 0x0c000000 },
{ 0x4, 0x15, 0x13, 0, 0x0c000000, 19, 0x0c000000 },
{ 0x4, 0x15, 0x14, 0, 0x24000000, 12, 0x24000000 },
{ 0x4, 0x15, 0x15, 0, 0x24000000, 27, 0x24000000 },
{ 0x4, 0x15, 0x16, 0, 0x00000000, 0, 0x00000000 },
{ 0x4, 0x15, 0x17, 0, 0x00000000, 15, 0x00000000 },
{ 0x4, 0x15, 0x18, 0, 0x28000000, 13, 0x28000000 },
{ 0x4, 0x15, 0x19, 0, 0x28000000, 28, 0x28000000 },
{ 0x4, 0x15, 0x1a, 0, 0x10000000, 5, 0x10000000 },
{ 0x4, 0x15, 0x1b, 0, 0x10000000, 20, 0x10000000 },
{ 0x4, 0x15, 0x1c, 0, 0x30000000, 14, 0x30000000 },
{ 0x4, 0x15, 0x1d, 0, 0x30000000, 29, 0x30000000 },
{ 0x4, 0x0, 0x0, 0, 0x0b000000, 0, 0x00000000 },
{ 0x4, 0x0, 0x1, 0, 0x0b800000, 1, 0x00000000 },
{ 0x4, 0x1, 0x0, 0, 0x20de0000, 3, 0x000e0000 },
{ 0x4, 0x1, 0x1, 0, 0x210e0000, 7, 0x000e0000 },
{ 0x4, 0x1, 0x2, 0, 0x20dc0000, 2, 0x000c0000 },
{ 0x4, 0x1, 0x3, 0, 0x210c0000, 6, 0x000c0000 },
{ 0x4, 0x1, 0x4, 0, 0x20d80000, 1, 0x00080000 },
{ 0x4, 0x1, 0x5, 0, 0x21080000, 5, 0x00080000 },
{ 0x4, 0x1, 0x6, 0, 0x20d00000, 0, 0x00000000 },
{ 0x4, 0x1, 0x7, 0, 0x21000000, 4, 0x00000000 },
{ 0x4, 0x2, 0x0, 0, 0x0b040000, 0, 0x00000000 },
{ 0x4, 0x2, 0x1, 0, 0x0b840000, 1, 0x00000000 },
{ 0x4, 0x3, 0x0, 0, 0x0b230000, 0, 0x00000000 },
{ 0x4, 0x3, 0x1, 0, 0x0ba30000, 1, 0x00000000 },
{ 0x4, 0x4, 0x0, 0, 0x0b050000, 0, 0x00000000 },
{ 0x4, 0x4, 0x1, 0, 0x0b850000, 1, 0x00000000 },
{ 0x4, 0x5, 0x0, 0, 0x0b060000, 0, 0x00000000 },
{ 0x4, 0x5, 0x1, 0, 0x0b070000, 1, 0x00010000 },
{ 0x4, 0x5, 0x2, 0, 0x0b080000, 2, 0x00020000 },
{ 0x4, 0x5, 0x3, 0, 0x0b090000, 3, 0x00030000 },
{ 0x4, 0x5, 0x4, 0, 0x0b0a0000, 4, 0x00040000 },
{ 0x4, 0x5, 0x5, 0, 0x0b0b0000, 5, 0x00050000 },
{ 0x4, 0x5, 0x6, 0, 0x0b0c0000, 6, 0x00060000 },
{ 0x4, 0x5, 0x7, 0, 0x0b0d0000, 7, 0x00070000 },
{ 0x4, 0x5, 0x8, 0, 0x0b0e0000, 8, 0x00080000 },
{ 0x4, 0x5, 0x9, 0, 0x0b860000, 9, 0x00000000 },
{ 0x4, 0x5, 0xa, 0, 0x0b870000, 10, 0x00010000 },
{ 0x4, 0x5, 0xb, 0, 0x0b880000, 11, 0x00020000 },
{ 0x4, 0x5, 0xc, 0, 0x0b890000, 12, 0x00030000 },
{ 0x4, 0x5, 0xd, 0, 0x0b8a0000, 13, 0x00040000 },
{ 0x4, 0x5, 0xe, 0, 0x0b8b0000, 14, 0x00050000 },
{ 0x4, 0x5, 0xf, 0, 0x0b8c0000, 15, 0x00060000 },
{ 0x4, 0x5, 0x10, 0, 0x0b8d0000, 16, 0x00070000 },
{ 0x4, 0x5, 0x11, 0, 0x0b8e0000, 17, 0x00080000 },
{ 0x4, 0x6, 0x0, 0, 0x0b650000, 0, 0x00000000 },
{ 0x4, 0x6, 0x1, 0, 0x0be50000, 1, 0x00000000 },
{ 0x4, 0x7, 0x0, 0, 0x20df0000, 0, 0x00000000 },
{ 0x4, 0x7, 0x1, 0, 0x210f0000, 1, 0x00000000 },
{ 0x4, 0x8, 0x0, 0, 0x0b3e0000, 0, 0x00000000 },
{ 0x4, 0x8, 0x1, 0, 0x0bbe0000, 1, 0x00000000 },
{ 0x4, 0x9, 0x0, 0, 0x0b3d0000, 0, 0x00000000 },
{ 0x4, 0x9, 0x1, 0, 0x0bbd0000, 1, 0x00000000 },
{ 0x4, 0xa, 0x0, 0, 0x0b1e0000, 0, 0x00000000 },
{ 0x4, 0xa, 0x1, 0, 0x0b9e0000, 1, 0x00000000 },
{ 0x4, 0xb, 0x0, 0, 0x0b150000, 0, 0x00000000 },
{ 0x4, 0xb, 0x1, 0, 0x0b160000, 1, 0x00010000 },
{ 0x4, 0xb, 0x2, 0, 0x0b170000, 2, 0x00020000 },
{ 0x4, 0xb, 0x3, 0, 0x0b180000, 3, 0x00030000 },
{ 0x4, 0xb, 0x4, 0, 0x0b190000, 4, 0x00040000 },
{ 0x4, 0xb, 0x5, 0, 0x0b1a0000, 5, 0x00050000 },
{ 0x4, 0xb, 0x6, 0, 0x0b1b0000, 6, 0x00060000 },
{ 0x4, 0xb, 0x7, 0, 0x0b1c0000, 7, 0x00070000 },
{ 0x4, 0xb, 0x8, 0, 0x0b1d0000, 8, 0x00080000 },
{ 0x4, 0xb, 0x9, 0, 0x0b950000, 9, 0x00000000 },
{ 0x4, 0xb, 0xa, 0, 0x0b960000, 10, 0x00010000 },
{ 0x4, 0xb, 0xb, 0, 0x0b970000, 11, 0x00020000 },
{ 0x4, 0xb, 0xc, 0, 0x0b980000, 12, 0x00030000 },
{ 0x4, 0xb, 0xd, 0, 0x0b990000, 13, 0x00040000 },
{ 0x4, 0xb, 0xe, 0, 0x0b9a0000, 14, 0x00050000 },
{ 0x4, 0xb, 0xf, 0, 0x0b9b0000, 15, 0x00060000 },
{ 0x4, 0xb, 0x10, 0, 0x0b9c0000, 16, 0x00070000 },
{ 0x4, 0xb, 0x11, 0, 0x0b9d0000, 17, 0x00080000 },
{ 0x4, 0xc, 0x0, 0, 0x0b660000, 0, 0x00000000 },
{ 0x4, 0xc, 0x1, 0, 0x0be60000, 1, 0x00000000 },
{ 0x4, 0xd, 0x0, 0, 0x0b1f0000, 0, 0x00000000 },
{ 0x4, 0xd, 0x1, 0, 0x0b200000, 1, 0x00010000 },
{ 0x4, 0xd, 0x2, 0, 0x0b210000, 2, 0x00020000 },
{ 0x4, 0xd, 0x3, 0, 0x0b220000, 3, 0x00030000 },
{ 0x4, 0xd, 0x4, 0, 0x0b9f0000, 4, 0x00000000 },
{ 0x4, 0xd, 0x5, 0, 0x0ba00000, 5, 0x00010000 },
{ 0x4, 0xd, 0x6, 0, 0x0ba10000, 6, 0x00020000 },
{ 0x4, 0xd, 0x7, 0, 0x0ba20000, 7, 0x00030000 },
{ 0x4, 0xe, 0x0, 0, 0x0b0f0000, 0, 0x00000000 },
{ 0x4, 0xe, 0x1, 0, 0x0b100000, 1, 0x00010000 },
{ 0x4, 0xe, 0x2, 0, 0x0b110000, 2, 0x00020000 },
{ 0x4, 0xe, 0x3, 0, 0x0b120000, 3, 0x00030000 },
{ 0x4, 0xe, 0x4, 0, 0x0b130000, 4, 0x00040000 },
{ 0x4, 0xe, 0x5, 0, 0x0b140000, 5, 0x00050000 },
{ 0x4, 0xe, 0x6, 0, 0x0b8f0000, 6, 0x00000000 },
{ 0x4, 0xe, 0x7, 0, 0x0b900000, 7, 0x00010000 },
{ 0x4, 0xe, 0x8, 0, 0x0b910000, 8, 0x00020000 },
{ 0x4, 0xe, 0x9, 0, 0x0b920000, 9, 0x00030000 },
{ 0x4, 0xe, 0xa, 0, 0x0b930000, 10, 0x00040000 },
{ 0x4, 0xe, 0xb, 0, 0x0b940000, 11, 0x00050000 },
{ 0x4, 0x10, 0x0, 0, 0x0b240000, 0, 0x00000000 },
{ 0x4, 0x10, 0x1, 0, 0x0ba40000, 1, 0x00000000 },
{ 0x4, 0x11, 0x0, 0, 0x0b020000, 0, 0x00000000 },
{ 0x4, 0x11, 0x1, 0, 0x0b820000, 1, 0x00000000 },
{ 0x4, 0x12, 0x0, 0, 0x0b030000, 0, 0x00000000 },
{ 0x4, 0x12, 0x1, 0, 0x0b830000, 1, 0x00000000 },
{ 0x4, 0x17, 0x0, 0, 0x0b640000, 0, 0x00000000 },
{ 0x4, 0x17, 0x1, 0, 0x0be40000, 1, 0x00000000 },
{ 0x4, 0x18, 0x0, 0, 0x0b600000, 0, 0x00000000 },
{ 0x4, 0x18, 0x1, 0, 0x0be00000, 1, 0x00000000 },
{ 0x4, 0x18, 0x2, 0, 0x00000000, 0, 0x00000000 },
{ 0x4, 0x18, 0x3, 0, 0x00000000, 0, 0x00000000 }
};
static void cbbcentralnoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
{
info->initflow = FIELD_GET(CBB_NOC_INITFLOW, routeid);
info->targflow = FIELD_GET(CBB_NOC_TARGFLOW, routeid);
info->targ_subrange = FIELD_GET(CBB_NOC_TARG_SUBRANGE, routeid);
info->seqid = FIELD_GET(CBB_NOC_SEQID, routeid);
}
static void bpmpnoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
{
info->initflow = FIELD_GET(BPMP_NOC_INITFLOW, routeid);
info->targflow = FIELD_GET(BPMP_NOC_TARGFLOW, routeid);
info->targ_subrange = FIELD_GET(BPMP_NOC_TARG_SUBRANGE, routeid);
info->seqid = FIELD_GET(BPMP_NOC_SEQID, routeid);
}
static void aonnoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
{
info->initflow = FIELD_GET(AON_NOC_INITFLOW, routeid);
info->targflow = FIELD_GET(AON_NOC_TARGFLOW, routeid);
info->targ_subrange = FIELD_GET(AON_NOC_TARG_SUBRANGE, routeid);
info->seqid = FIELD_GET(AON_NOC_SEQID, routeid);
}
static void scenoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
{
info->initflow = FIELD_GET(SCE_NOC_INITFLOW, routeid);
info->targflow = FIELD_GET(SCE_NOC_TARGFLOW, routeid);
info->targ_subrange = FIELD_GET(SCE_NOC_TARG_SUBRANGE, routeid);
info->seqid = FIELD_GET(SCE_NOC_SEQID, routeid);
}
static void cbbcentralnoc_parse_userbits(struct tegra194_cbb_userbits *usrbits, u32 elog_5)
{
usrbits->axcache = FIELD_GET(CBB_NOC_AXCACHE, elog_5);
usrbits->non_mod = FIELD_GET(CBB_NOC_NON_MOD, elog_5);
usrbits->axprot = FIELD_GET(CBB_NOC_AXPROT, elog_5);
usrbits->falconsec = FIELD_GET(CBB_NOC_FALCONSEC, elog_5);
usrbits->grpsec = FIELD_GET(CBB_NOC_GRPSEC, elog_5);
usrbits->vqc = FIELD_GET(CBB_NOC_VQC, elog_5);
usrbits->mstr_id = FIELD_GET(CBB_NOC_MSTR_ID, elog_5) - 1;
usrbits->axi_id = FIELD_GET(CBB_NOC_AXI_ID, elog_5);
}
static void clusternoc_parse_userbits(struct tegra194_cbb_userbits *usrbits, u32 elog_5)
{
usrbits->axcache = FIELD_GET(CLUSTER_NOC_AXCACHE, elog_5);
usrbits->axprot = FIELD_GET(CLUSTER_NOC_AXCACHE, elog_5);
usrbits->falconsec = FIELD_GET(CLUSTER_NOC_FALCONSEC, elog_5);
usrbits->grpsec = FIELD_GET(CLUSTER_NOC_GRPSEC, elog_5);
usrbits->vqc = FIELD_GET(CLUSTER_NOC_VQC, elog_5);
usrbits->mstr_id = FIELD_GET(CLUSTER_NOC_MSTR_ID, elog_5) - 1;
}
static void tegra194_cbb_fault_enable(struct tegra_cbb *cbb)
{
struct tegra194_cbb *priv = to_tegra194_cbb(cbb);
writel(1, priv->regs + ERRLOGGER_0_FAULTEN_0);
writel(1, priv->regs + ERRLOGGER_1_FAULTEN_0);
writel(1, priv->regs + ERRLOGGER_2_FAULTEN_0);
}
static void tegra194_cbb_stall_enable(struct tegra_cbb *cbb)
{
struct tegra194_cbb *priv = to_tegra194_cbb(cbb);
writel(1, priv->regs + ERRLOGGER_0_STALLEN_0);
writel(1, priv->regs + ERRLOGGER_1_STALLEN_0);
writel(1, priv->regs + ERRLOGGER_2_STALLEN_0);
}
static void tegra194_cbb_error_clear(struct tegra_cbb *cbb)
{
struct tegra194_cbb *priv = to_tegra194_cbb(cbb);
writel(1, priv->regs + ERRLOGGER_0_ERRCLR_0);
writel(1, priv->regs + ERRLOGGER_1_ERRCLR_0);
writel(1, priv->regs + ERRLOGGER_2_ERRCLR_0);
dsb(sy);
}
static u32 tegra194_cbb_get_status(struct tegra_cbb *cbb)
{
struct tegra194_cbb *priv = to_tegra194_cbb(cbb);
u32 value;
value = readl(priv->regs + ERRLOGGER_0_ERRVLD_0);
value |= (readl(priv->regs + ERRLOGGER_1_ERRVLD_0) << 1);
value |= (readl(priv->regs + ERRLOGGER_2_ERRVLD_0) << 2);
dsb(sy);
return value;
}
static u32 tegra194_axi2apb_status(void __iomem *addr)
{
u32 value;
value = readl(addr + DMAAPB_X_RAW_INTERRUPT_STATUS);
writel(0xffffffff, addr + DMAAPB_X_RAW_INTERRUPT_STATUS);
return value;
}
static bool tegra194_axi2apb_fatal(struct seq_file *file, unsigned int bridge, u32 status)
{
bool is_fatal = true;
size_t i;
for (i = 0; i < ARRAY_SIZE(tegra194_axi2apb_error); i++) {
if (status & BIT(i)) {
tegra_cbb_print_err(file, "\t AXI2APB_%d bridge error: %s\n",
bridge + 1, tegra194_axi2apb_error[i]);
if (strstr(tegra194_axi2apb_error[i], "Firewall"))
is_fatal = false;
}
}
return is_fatal;
}
/*
* Fetch InitlocalAddress from NOC Aperture lookup table
* using Targflow, Targsubrange
*/
static u32 get_init_localaddress(const struct tegra194_cbb_aperture *info,
const struct tegra194_cbb_aperture *aper, unsigned int max)
{
unsigned int t_f = 0, t_sr = 0;
u32 addr = 0;
for (t_f = 0; t_f < max; t_f++) {
if (aper[t_f].targflow == info->targflow) {
t_sr = t_f;
do {
if (aper[t_sr].targ_subrange == info->targ_subrange) {
addr = aper[t_sr].init_localaddress;
return addr;
}
if (t_sr >= max)
return 0;
t_sr++;
} while (aper[t_sr].targflow == aper[t_sr - 1].targflow);
t_f = t_sr;
}
}
return addr;
}
static void print_errlog5(struct seq_file *file, struct tegra194_cbb *cbb)
{
struct tegra194_cbb_userbits userbits;
cbb->noc->parse_userbits(&userbits, cbb->errlog5);
if (!strcmp(cbb->noc->name, "cbb-noc")) {
tegra_cbb_print_err(file, "\t Non-Modify\t\t: %#x\n", userbits.non_mod);
tegra_cbb_print_err(file, "\t AXI ID\t\t: %#x\n", userbits.axi_id);
}
tegra_cbb_print_err(file, "\t Master ID\t\t: %s\n",
cbb->noc->master_id[userbits.mstr_id]);
tegra_cbb_print_err(file, "\t Security Group(GRPSEC): %#x\n", userbits.grpsec);
tegra_cbb_print_cache(file, userbits.axcache);
tegra_cbb_print_prot(file, userbits.axprot);
tegra_cbb_print_err(file, "\t FALCONSEC\t\t: %#x\n", userbits.falconsec);
tegra_cbb_print_err(file, "\t Virtual Queuing Channel(VQC): %#x\n", userbits.vqc);
}
/*
* Fetch Base Address/InitlocalAddress from NOC aperture lookup table using TargFlow &
* Targ_subRange extracted from RouteId. Perform address reconstruction as below:
*
* Address = Base Address + (ErrLog3 + ErrLog4)
*/
static void
print_errlog3_4(struct seq_file *file, u32 errlog3, u32 errlog4,
const struct tegra194_cbb_aperture *info,
const struct tegra194_cbb_aperture *aperture, unsigned int max)
{
u64 addr = (u64)errlog4 << 32 | errlog3;
/*
* If errlog4[7] = "1", then it's a joker entry. Joker entries are a rare phenomenon and
* such addresses are not reliable. Debugging should be done using only the RouteId
* information.
*/
if (errlog4 & 0x80)
tegra_cbb_print_err(file, "\t debug using RouteId alone as below address is a "
"joker entry and not reliable");
addr += get_init_localaddress(info, aperture, max);
tegra_cbb_print_err(file, "\t Address accessed\t: %#llx\n", addr);
}
/*
* Get RouteId from ErrLog1+ErrLog2 registers and fetch values of
* InitFlow, TargFlow, Targ_subRange and SeqId values from RouteId
*/
static void
print_errlog1_2(struct seq_file *file, struct tegra194_cbb *cbb,
struct tegra194_cbb_aperture *info)
{
u64 routeid = (u64)cbb->errlog2 << 32 | cbb->errlog1;
u32 seqid = 0;
tegra_cbb_print_err(file, "\t RouteId\t\t: %#llx\n", routeid);
cbb->noc->parse_routeid(info, routeid);
tegra_cbb_print_err(file, "\t InitFlow\t\t: %s\n",
cbb->noc->routeid_initflow[info->initflow]);
tegra_cbb_print_err(file, "\t Targflow\t\t: %s\n",
cbb->noc->routeid_targflow[info->targflow]);
tegra_cbb_print_err(file, "\t TargSubRange\t\t: %d\n", info->targ_subrange);
tegra_cbb_print_err(file, "\t SeqId\t\t\t: %d\n", seqid);
}
/*
* Print transcation type, error code and description from ErrLog0 for all
* errors. For NOC slave errors, all relevant error info is printed using
* ErrLog0 only. But additional information is printed for errors from
* APB slaves because for them:
* - All errors are logged as SLV(slave) errors due to APB having only single
* bit pslverr to report all errors.
* - Exact cause is printed by reading DMAAPB_X_RAW_INTERRUPT_STATUS register.
* - The driver prints information showing AXI2APB bridge and exact error
* only if there is error in any AXI2APB slave.
* - There is still no way to disambiguate a DEC error from SLV error type.
*/
static bool print_errlog0(struct seq_file *file, struct tegra194_cbb *cbb)
{
struct tegra194_cbb_packet_header hdr;
bool is_fatal = true;
hdr.lock = cbb->errlog0 & 0x1;
hdr.opc = FIELD_GET(CBB_ERR_OPC, cbb->errlog0);
hdr.errcode = FIELD_GET(CBB_ERR_ERRCODE, cbb->errlog0);
hdr.len1 = FIELD_GET(CBB_ERR_LEN1, cbb->errlog0);
hdr.format = (cbb->errlog0 >> 31);
tegra_cbb_print_err(file, "\t Transaction Type\t: %s\n",
tegra194_cbb_trantype[hdr.opc]);
tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
tegra194_cbb_errors[hdr.errcode].code);
tegra_cbb_print_err(file, "\t Error Source\t\t: %s\n",
tegra194_cbb_errors[hdr.errcode].source);
tegra_cbb_print_err(file, "\t Error Description\t: %s\n",
tegra194_cbb_errors[hdr.errcode].desc);
/*
* Do not crash system for errors which are only notifications to indicate a transaction
* was not allowed to be attempted.
*/
if (!strcmp(tegra194_cbb_errors[hdr.errcode].code, "SEC") ||
!strcmp(tegra194_cbb_errors[hdr.errcode].code, "DEC") ||
!strcmp(tegra194_cbb_errors[hdr.errcode].code, "UNS") ||
!strcmp(tegra194_cbb_errors[hdr.errcode].code, "DISC")) {
is_fatal = false;
} else if (!strcmp(tegra194_cbb_errors[hdr.errcode].code, "SLV") &&
cbb->num_bridges > 0) {
unsigned int i;
u32 status;
/* For all SLV errors, read DMAAPB_X_RAW_INTERRUPT_STATUS
* register to get error status for all AXI2APB bridges.
* Print bridge details if a bit is set in a bridge's
* status register due to error in a APB slave connected
* to that bridge. For other NOC slaves, none of the status
* register will be set.
*/
for (i = 0; i < cbb->num_bridges; i++) {
status = tegra194_axi2apb_status(cbb->bridges[i].base);
if (status)
is_fatal = tegra194_axi2apb_fatal(file, i, status);
}
}
tegra_cbb_print_err(file, "\t Packet header Lock\t: %d\n", hdr.lock);
tegra_cbb_print_err(file, "\t Packet header Len1\t: %d\n", hdr.len1);
if (hdr.format)
tegra_cbb_print_err(file, "\t NOC protocol version\t: %s\n",
"version >= 2.7");
else
tegra_cbb_print_err(file, "\t NOC protocol version\t: %s\n",
"version < 2.7");
return is_fatal;
}
/*
* Print debug information about failed transaction using
* ErrLog registers of error loggger having ErrVld set
*/
static bool print_errloggerX_info(struct seq_file *file, struct tegra194_cbb *cbb,
int errloggerX)
{
struct tegra194_cbb_aperture info = { 0, };
bool is_fatal = true;
tegra_cbb_print_err(file, "\tError Logger\t\t: %d\n", errloggerX);
if (errloggerX == 0) {
cbb->errlog0 = readl(cbb->regs + ERRLOGGER_0_ERRLOG0_0);
cbb->errlog1 = readl(cbb->regs + ERRLOGGER_0_ERRLOG1_0);
cbb->errlog2 = readl(cbb->regs + ERRLOGGER_0_RSVD_00_0);
cbb->errlog3 = readl(cbb->regs + ERRLOGGER_0_ERRLOG3_0);
cbb->errlog4 = readl(cbb->regs + ERRLOGGER_0_ERRLOG4_0);
cbb->errlog5 = readl(cbb->regs + ERRLOGGER_0_ERRLOG5_0);
} else if (errloggerX == 1) {
cbb->errlog0 = readl(cbb->regs + ERRLOGGER_1_ERRLOG0_0);
cbb->errlog1 = readl(cbb->regs + ERRLOGGER_1_ERRLOG1_0);
cbb->errlog2 = readl(cbb->regs + ERRLOGGER_1_RSVD_00_0);
cbb->errlog3 = readl(cbb->regs + ERRLOGGER_1_ERRLOG3_0);
cbb->errlog4 = readl(cbb->regs + ERRLOGGER_1_ERRLOG4_0);
cbb->errlog5 = readl(cbb->regs + ERRLOGGER_1_ERRLOG5_0);
} else if (errloggerX == 2) {
cbb->errlog0 = readl(cbb->regs + ERRLOGGER_2_ERRLOG0_0);
cbb->errlog1 = readl(cbb->regs + ERRLOGGER_2_ERRLOG1_0);
cbb->errlog2 = readl(cbb->regs + ERRLOGGER_2_RSVD_00_0);
cbb->errlog3 = readl(cbb->regs + ERRLOGGER_2_ERRLOG3_0);
cbb->errlog4 = readl(cbb->regs + ERRLOGGER_2_ERRLOG4_0);
cbb->errlog5 = readl(cbb->regs + ERRLOGGER_2_ERRLOG5_0);
}
tegra_cbb_print_err(file, "\tErrLog0\t\t\t: %#x\n", cbb->errlog0);
is_fatal = print_errlog0(file, cbb);
tegra_cbb_print_err(file, "\tErrLog1\t\t\t: %#x\n", cbb->errlog1);
tegra_cbb_print_err(file, "\tErrLog2\t\t\t: %#x\n", cbb->errlog2);
print_errlog1_2(file, cbb, &info);
tegra_cbb_print_err(file, "\tErrLog3\t\t\t: %#x\n", cbb->errlog3);
tegra_cbb_print_err(file, "\tErrLog4\t\t\t: %#x\n", cbb->errlog4);
print_errlog3_4(file, cbb->errlog3, cbb->errlog4, &info, cbb->noc->noc_aperture,
cbb->noc->max_aperture);
tegra_cbb_print_err(file, "\tErrLog5\t\t\t: %#x\n", cbb->errlog5);
if (cbb->errlog5)
print_errlog5(file, cbb);
return is_fatal;
}
static bool print_errlog(struct seq_file *file, struct tegra194_cbb *cbb, u32 errvld)
{
bool is_fatal = true;
pr_crit("**************************************\n");
pr_crit("CPU:%d, Error:%s\n", smp_processor_id(), cbb->noc->name);
if (errvld & 0x1)
is_fatal = print_errloggerX_info(file, cbb, 0);
else if (errvld & 0x2)
is_fatal = print_errloggerX_info(file, cbb, 1);
else if (errvld & 0x4)
is_fatal = print_errloggerX_info(file, cbb, 2);
tegra_cbb_error_clear(&cbb->base);
tegra_cbb_print_err(file, "\t**************************************\n");
return is_fatal;
}
#ifdef CONFIG_DEBUG_FS
static DEFINE_MUTEX(cbb_err_mutex);
static int tegra194_cbb_debugfs_show(struct tegra_cbb *cbb, struct seq_file *file, void *data)
{
struct tegra_cbb *noc;
mutex_lock(&cbb_err_mutex);
list_for_each_entry(noc, &cbb_list, node) {
struct tegra194_cbb *priv = to_tegra194_cbb(noc);
u32 status;
status = tegra_cbb_get_status(noc);
if (status)
print_errlog(file, priv, status);
}
mutex_unlock(&cbb_err_mutex);
return 0;
}
#endif
/*
* Handler for CBB errors from different initiators
*/
static irqreturn_t tegra194_cbb_err_isr(int irq, void *data)
{
bool is_inband_err = false, is_fatal = false;
//struct tegra194_cbb *cbb = data;
struct tegra_cbb *noc;
unsigned long flags;
u8 mstr_id = 0;
spin_lock_irqsave(&cbb_lock, flags);
/* XXX only process interrupts for "cbb" instead of iterating over all NOCs? */
list_for_each_entry(noc, &cbb_list, node) {
struct tegra194_cbb *priv = to_tegra194_cbb(noc);
u32 status = 0;
status = tegra_cbb_get_status(noc);
if (status && ((irq == priv->sec_irq) || (irq == priv->nonsec_irq))) {
tegra_cbb_print_err(NULL, "CPU:%d, Error: %s@%llx, irq=%d\n",
smp_processor_id(), priv->noc->name, priv->res->start,
irq);
is_fatal = print_errlog(NULL, priv, status);
/*
* If illegal request is from CCPLEX(0x1) initiator
* and error is fatal then call BUG() to crash system.
*/
if (priv->noc->erd_mask_inband_err) {
mstr_id = FIELD_GET(CBB_NOC_MSTR_ID, priv->errlog5);
if (mstr_id == 0x1)
is_inband_err = 1;
}
}
}
spin_unlock_irqrestore(&cbb_lock, flags);
if (is_inband_err) {
if (is_fatal)
BUG();
else
WARN(true, "Warning due to CBB Error\n");
}
return IRQ_HANDLED;
}
/*
* Register handler for CBB_NONSECURE & CBB_SECURE interrupts
* for reporting CBB errors
*/
static int tegra194_cbb_interrupt_enable(struct tegra_cbb *cbb)
{
struct tegra194_cbb *priv = to_tegra194_cbb(cbb);
struct device *dev = cbb->dev;
int err;
if (priv->sec_irq) {
err = devm_request_irq(dev, priv->sec_irq, tegra194_cbb_err_isr, 0, dev_name(dev),
priv);
if (err) {
dev_err(dev, "failed to register interrupt %u: %d\n", priv->sec_irq, err);
return err;
}
}
if (priv->nonsec_irq) {
err = devm_request_irq(dev, priv->nonsec_irq, tegra194_cbb_err_isr, 0,
dev_name(dev), priv);
if (err) {
dev_err(dev, "failed to register interrupt %u: %d\n", priv->nonsec_irq,
err);
return err;
}
}
return 0;
}
static void tegra194_cbb_error_enable(struct tegra_cbb *cbb)
{
/*
* Set “StallEn=1” to enable queuing of error packets till
* first is served & cleared
*/
tegra_cbb_stall_enable(cbb);
/* set “FaultEn=1” to enable error reporting signal “Fault” */
tegra_cbb_fault_enable(cbb);
}
static const struct tegra_cbb_ops tegra194_cbb_ops = {
.get_status = tegra194_cbb_get_status,
.error_clear = tegra194_cbb_error_clear,
.fault_enable = tegra194_cbb_fault_enable,
.stall_enable = tegra194_cbb_stall_enable,
.error_enable = tegra194_cbb_error_enable,
.interrupt_enable = tegra194_cbb_interrupt_enable,
#ifdef CONFIG_DEBUG_FS
.debugfs_show = tegra194_cbb_debugfs_show,
#endif
};
static struct tegra194_cbb_noc_data tegra194_cbb_central_noc_data = {
.name = "cbb-noc",
.erd_mask_inband_err = true,
.master_id = tegra194_master_id,
.noc_aperture = tegra194_cbbcentralnoc_apert_lookup,
.max_aperture = ARRAY_SIZE(tegra194_cbbcentralnoc_apert_lookup),
.routeid_initflow = tegra194_cbbcentralnoc_routeid_initflow,
.routeid_targflow = tegra194_cbbcentralnoc_routeid_targflow,
.parse_routeid = cbbcentralnoc_parse_routeid,
.parse_userbits = cbbcentralnoc_parse_userbits
};
static struct tegra194_cbb_noc_data tegra194_aon_noc_data = {
.name = "aon-noc",
.erd_mask_inband_err = false,
.master_id = tegra194_master_id,
.noc_aperture = tegra194_aonnoc_aperture_lookup,
.max_aperture = ARRAY_SIZE(tegra194_aonnoc_aperture_lookup),
.routeid_initflow = tegra194_aonnoc_routeid_initflow,
.routeid_targflow = tegra194_aonnoc_routeid_targflow,
.parse_routeid = aonnoc_parse_routeid,
.parse_userbits = clusternoc_parse_userbits
};
static struct tegra194_cbb_noc_data tegra194_bpmp_noc_data = {
.name = "bpmp-noc",
.erd_mask_inband_err = false,
.master_id = tegra194_master_id,
.noc_aperture = tegra194_bpmpnoc_apert_lookup,
.max_aperture = ARRAY_SIZE(tegra194_bpmpnoc_apert_lookup),
.routeid_initflow = tegra194_bpmpnoc_routeid_initflow,
.routeid_targflow = tegra194_bpmpnoc_routeid_targflow,
.parse_routeid = bpmpnoc_parse_routeid,
.parse_userbits = clusternoc_parse_userbits
};
static struct tegra194_cbb_noc_data tegra194_rce_noc_data = {
.name = "rce-noc",
.erd_mask_inband_err = false,
.master_id = tegra194_master_id,
.noc_aperture = tegra194_scenoc_apert_lookup,
.max_aperture = ARRAY_SIZE(tegra194_scenoc_apert_lookup),
.routeid_initflow = tegra194_scenoc_routeid_initflow,
.routeid_targflow = tegra194_scenoc_routeid_targflow,
.parse_routeid = scenoc_parse_routeid,
.parse_userbits = clusternoc_parse_userbits
};
static struct tegra194_cbb_noc_data tegra194_sce_noc_data = {
.name = "sce-noc",
.erd_mask_inband_err = false,
.master_id = tegra194_master_id,
.noc_aperture = tegra194_scenoc_apert_lookup,
.max_aperture = ARRAY_SIZE(tegra194_scenoc_apert_lookup),
.routeid_initflow = tegra194_scenoc_routeid_initflow,
.routeid_targflow = tegra194_scenoc_routeid_targflow,
.parse_routeid = scenoc_parse_routeid,
.parse_userbits = clusternoc_parse_userbits
};
static const struct of_device_id tegra194_cbb_match[] = {
{ .compatible = "nvidia,tegra194-cbb-noc", .data = &tegra194_cbb_central_noc_data },
{ .compatible = "nvidia,tegra194-aon-noc", .data = &tegra194_aon_noc_data },
{ .compatible = "nvidia,tegra194-bpmp-noc", .data = &tegra194_bpmp_noc_data },
{ .compatible = "nvidia,tegra194-rce-noc", .data = &tegra194_rce_noc_data },
{ .compatible = "nvidia,tegra194-sce-noc", .data = &tegra194_sce_noc_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, tegra194_cbb_match);
static int tegra194_cbb_get_bridges(struct tegra194_cbb *cbb, struct device_node *np)
{
struct tegra_cbb *entry;
unsigned long flags;
unsigned int i;
int err;
spin_lock_irqsave(&cbb_lock, flags);
list_for_each_entry(entry, &cbb_list, node) {
struct tegra194_cbb *priv = to_tegra194_cbb(entry);
if (priv->bridges) {
cbb->num_bridges = priv->num_bridges;
cbb->bridges = priv->bridges;
break;
}
}
spin_unlock_irqrestore(&cbb_lock, flags);
if (!cbb->bridges) {
cbb->num_bridges = of_address_count(np);
cbb->bridges = devm_kcalloc(cbb->base.dev, cbb->num_bridges,
sizeof(*cbb->bridges), GFP_KERNEL);
if (!cbb->bridges)
return -ENOMEM;
for (i = 0; i < cbb->num_bridges; i++) {
err = of_address_to_resource(np, i, &cbb->bridges[i].res);
if (err < 0)
return err;
cbb->bridges[i].base = devm_ioremap_resource(cbb->base.dev,
&cbb->bridges[i].res);
if (IS_ERR(cbb->bridges[i].base))
return PTR_ERR(cbb->bridges[i].base);
}
}
if (cbb->num_bridges > 0) {
dev_dbg(cbb->base.dev, "AXI2APB bridge info present:\n");
for (i = 0; i < cbb->num_bridges; i++)
dev_dbg(cbb->base.dev, " %u: %pR\n", i, &cbb->bridges[i].res);
}
return 0;
}
static int tegra194_cbb_probe(struct platform_device *pdev)
{
const struct tegra194_cbb_noc_data *noc;
struct tegra194_cbb *cbb;
struct device_node *np;
unsigned long flags;
int err;
noc = of_device_get_match_data(&pdev->dev);
if (noc->erd_mask_inband_err) {
/*
* Set Error Response Disable(ERD) bit to mask SError/inband
* error and only trigger interrupts for illegal access from
* CCPLEX initiator.
*/
err = tegra194_miscreg_mask_serror();
if (err) {
dev_err(&pdev->dev, "couldn't mask inband errors\n");
return err;
}
}
cbb = devm_kzalloc(&pdev->dev, sizeof(*cbb), GFP_KERNEL);
if (!cbb)
return -ENOMEM;
INIT_LIST_HEAD(&cbb->base.node);
cbb->base.ops = &tegra194_cbb_ops;
cbb->base.dev = &pdev->dev;
cbb->noc = noc;
cbb->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &cbb->res);
if (IS_ERR(cbb->regs))
return PTR_ERR(cbb->regs);
err = tegra_cbb_get_irq(pdev, &cbb->nonsec_irq, &cbb->sec_irq);
if (err)
return err;
np = of_parse_phandle(pdev->dev.of_node, "nvidia,axi2apb", 0);
if (np) {
err = tegra194_cbb_get_bridges(cbb, np);
of_node_put(np);
if (err < 0)
return err;
}
platform_set_drvdata(pdev, cbb);
spin_lock_irqsave(&cbb_lock, flags);
list_add(&cbb->base.node, &cbb_list);
spin_unlock_irqrestore(&cbb_lock, flags);
return tegra_cbb_register(&cbb->base);
}
static int tegra194_cbb_remove(struct platform_device *pdev)
{
struct tegra194_cbb *cbb = platform_get_drvdata(pdev);
struct tegra_cbb *noc, *tmp;
unsigned long flags;
spin_lock_irqsave(&cbb_lock, flags);
list_for_each_entry_safe(noc, tmp, &cbb_list, node) {
struct tegra194_cbb *priv = to_tegra194_cbb(noc);
if (cbb->res->start == priv->res->start) {
list_del(&noc->node);
break;
}
}
spin_unlock_irqrestore(&cbb_lock, flags);
return 0;
}
static int __maybe_unused tegra194_cbb_resume_noirq(struct device *dev)
{
struct tegra194_cbb *cbb = dev_get_drvdata(dev);
tegra194_cbb_error_enable(&cbb->base);
dsb(sy);
dev_dbg(dev, "%s resumed\n", cbb->noc->name);
return 0;
}
static const struct dev_pm_ops tegra194_cbb_pm = {
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, tegra194_cbb_resume_noirq)
};
static struct platform_driver tegra194_cbb_driver = {
.probe = tegra194_cbb_probe,
.remove = tegra194_cbb_remove,
.driver = {
.name = "tegra194-cbb",
.of_match_table = of_match_ptr(tegra194_cbb_match),
.pm = &tegra194_cbb_pm,
},
};
static int __init tegra194_cbb_init(void)
{
return platform_driver_register(&tegra194_cbb_driver);
}
pure_initcall(tegra194_cbb_init);
static void __exit tegra194_cbb_exit(void)
{
platform_driver_unregister(&tegra194_cbb_driver);
}
module_exit(tegra194_cbb_exit);
MODULE_AUTHOR("Sumit Gupta <[email protected]>");
MODULE_DESCRIPTION("Control Backbone error handling driver for Tegra194");
|
linux-master
|
drivers/soc/tegra/cbb/tegra194-cbb.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
*/
#include <linux/clk.h>
#include <linux/cpufeature.h>
#include <linux/debugfs.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/tegra-cbb.h>
void tegra_cbb_print_err(struct seq_file *file, const char *fmt, ...)
{
struct va_format vaf;
va_list args;
va_start(args, fmt);
if (file) {
seq_vprintf(file, fmt, args);
} else {
vaf.fmt = fmt;
vaf.va = &args;
pr_crit("%pV", &vaf);
}
va_end(args);
}
void tegra_cbb_print_cache(struct seq_file *file, u32 cache)
{
const char *buff_str, *mod_str, *rd_str, *wr_str;
buff_str = (cache & BIT(0)) ? "Bufferable " : "";
mod_str = (cache & BIT(1)) ? "Modifiable " : "";
rd_str = (cache & BIT(2)) ? "Read-Allocate " : "";
wr_str = (cache & BIT(3)) ? "Write-Allocate" : "";
if (cache == 0x0)
buff_str = "Device Non-Bufferable";
tegra_cbb_print_err(file, "\t Cache\t\t\t: 0x%x -- %s%s%s%s\n",
cache, buff_str, mod_str, rd_str, wr_str);
}
void tegra_cbb_print_prot(struct seq_file *file, u32 prot)
{
const char *data_str, *secure_str, *priv_str;
data_str = (prot & 0x4) ? "Instruction" : "Data";
secure_str = (prot & 0x2) ? "Non-Secure" : "Secure";
priv_str = (prot & 0x1) ? "Privileged" : "Unprivileged";
tegra_cbb_print_err(file, "\t Protection\t\t: 0x%x -- %s, %s, %s Access\n",
prot, priv_str, secure_str, data_str);
}
static int tegra_cbb_err_show(struct seq_file *file, void *data)
{
struct tegra_cbb *cbb = file->private;
return cbb->ops->debugfs_show(cbb, file, data);
}
DEFINE_SHOW_ATTRIBUTE(tegra_cbb_err);
static int tegra_cbb_err_debugfs_init(struct tegra_cbb *cbb)
{
static struct dentry *root;
if (!root) {
root = debugfs_create_file("tegra_cbb_err", 0444, NULL, cbb, &tegra_cbb_err_fops);
if (IS_ERR_OR_NULL(root)) {
pr_err("%s(): could not create debugfs node\n", __func__);
return PTR_ERR(root);
}
}
return 0;
}
void tegra_cbb_stall_enable(struct tegra_cbb *cbb)
{
if (cbb->ops->stall_enable)
cbb->ops->stall_enable(cbb);
}
void tegra_cbb_fault_enable(struct tegra_cbb *cbb)
{
if (cbb->ops->fault_enable)
cbb->ops->fault_enable(cbb);
}
void tegra_cbb_error_clear(struct tegra_cbb *cbb)
{
if (cbb->ops->error_clear)
cbb->ops->error_clear(cbb);
}
u32 tegra_cbb_get_status(struct tegra_cbb *cbb)
{
if (cbb->ops->get_status)
return cbb->ops->get_status(cbb);
return 0;
}
int tegra_cbb_get_irq(struct platform_device *pdev, unsigned int *nonsec_irq,
unsigned int *sec_irq)
{
unsigned int index = 0;
int num_intr = 0, irq;
num_intr = platform_irq_count(pdev);
if (!num_intr)
return -EINVAL;
if (num_intr == 2) {
irq = platform_get_irq(pdev, index);
if (irq <= 0)
return -ENOENT;
*nonsec_irq = irq;
index++;
}
irq = platform_get_irq(pdev, index);
if (irq <= 0)
return -ENOENT;
*sec_irq = irq;
if (num_intr == 1)
dev_dbg(&pdev->dev, "secure IRQ: %u\n", *sec_irq);
if (num_intr == 2)
dev_dbg(&pdev->dev, "secure IRQ: %u, non-secure IRQ: %u\n", *sec_irq, *nonsec_irq);
return 0;
}
int tegra_cbb_register(struct tegra_cbb *cbb)
{
int ret;
if (IS_ENABLED(CONFIG_DEBUG_FS)) {
ret = tegra_cbb_err_debugfs_init(cbb);
if (ret) {
dev_err(cbb->dev, "failed to create debugfs\n");
return ret;
}
}
/* register interrupt handler for errors due to different initiators */
ret = cbb->ops->interrupt_enable(cbb);
if (ret < 0) {
dev_err(cbb->dev, "Failed to register CBB Interrupt ISR");
return ret;
}
cbb->ops->error_enable(cbb);
dsb(sy);
return 0;
}
|
linux-master
|
drivers/soc/tegra/cbb/tegra-cbb.c
|
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2020 Maxime Ripard <[email protected]> */
#include <linux/device.h>
#include <linux/dma-map-ops.h>
#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/of.h>
#include <linux/platform_device.h>
static const char * const sunxi_mbus_devices[] = {
/*
* The display engine virtual devices are not strictly speaking
* connected to the MBUS, but since DRM will perform all the
* memory allocations and DMA operations through that device, we
* need to have the quirk on those devices too.
*/
"allwinner,sun4i-a10-display-engine",
"allwinner,sun5i-a10s-display-engine",
"allwinner,sun5i-a13-display-engine",
"allwinner,sun6i-a31-display-engine",
"allwinner,sun6i-a31s-display-engine",
"allwinner,sun7i-a20-display-engine",
"allwinner,sun8i-a23-display-engine",
"allwinner,sun8i-a33-display-engine",
"allwinner,sun9i-a80-display-engine",
/*
* And now we have the regular devices connected to the MBUS
* (that we know of).
*/
"allwinner,sun4i-a10-csi1",
"allwinner,sun4i-a10-display-backend",
"allwinner,sun4i-a10-display-frontend",
"allwinner,sun4i-a10-video-engine",
"allwinner,sun5i-a13-display-backend",
"allwinner,sun5i-a13-video-engine",
"allwinner,sun6i-a31-csi",
"allwinner,sun6i-a31-display-backend",
"allwinner,sun7i-a20-csi0",
"allwinner,sun7i-a20-display-backend",
"allwinner,sun7i-a20-display-frontend",
"allwinner,sun7i-a20-video-engine",
"allwinner,sun8i-a23-display-backend",
"allwinner,sun8i-a23-display-frontend",
"allwinner,sun8i-a33-display-backend",
"allwinner,sun8i-a33-display-frontend",
"allwinner,sun8i-a33-video-engine",
"allwinner,sun8i-a83t-csi",
"allwinner,sun8i-h3-csi",
"allwinner,sun8i-h3-video-engine",
"allwinner,sun8i-v3s-csi",
"allwinner,sun9i-a80-display-backend",
"allwinner,sun50i-a64-csi",
"allwinner,sun50i-a64-video-engine",
"allwinner,sun50i-h5-video-engine",
NULL,
};
static int sunxi_mbus_notifier(struct notifier_block *nb,
unsigned long event, void *__dev)
{
struct device *dev = __dev;
int ret;
if (event != BUS_NOTIFY_ADD_DEVICE)
return NOTIFY_DONE;
/*
* Only the devices that need a large memory bandwidth do DMA
* directly over the memory bus (called MBUS), instead of going
* through the regular system bus.
*/
if (!of_device_compatible_match(dev->of_node, sunxi_mbus_devices))
return NOTIFY_DONE;
/*
* Devices with an interconnects property have the MBUS
* relationship described in their DT and dealt with by
* of_dma_configure, so we can just skip them.
*
* Older DTs or SoCs who are not clearly understood need to set
* that DMA offset though.
*/
if (of_property_present(dev->of_node, "interconnects"))
return NOTIFY_DONE;
ret = dma_direct_set_offset(dev, PHYS_OFFSET, 0, SZ_4G);
if (ret)
dev_err(dev, "Couldn't setup our DMA offset: %d\n", ret);
return NOTIFY_DONE;
}
static struct notifier_block sunxi_mbus_nb = {
.notifier_call = sunxi_mbus_notifier,
};
static const char * const sunxi_mbus_platforms[] __initconst = {
"allwinner,sun4i-a10",
"allwinner,sun5i-a10s",
"allwinner,sun5i-a13",
"allwinner,sun6i-a31",
"allwinner,sun7i-a20",
"allwinner,sun8i-a23",
"allwinner,sun8i-a33",
"allwinner,sun8i-a83t",
"allwinner,sun8i-h3",
"allwinner,sun8i-r40",
"allwinner,sun8i-v3",
"allwinner,sun8i-v3s",
"allwinner,sun9i-a80",
"allwinner,sun50i-a64",
"allwinner,sun50i-h5",
"nextthing,gr8",
NULL,
};
static int __init sunxi_mbus_init(void)
{
if (!of_device_compatible_match(of_root, sunxi_mbus_platforms))
return 0;
bus_register_notifier(&platform_bus_type, &sunxi_mbus_nb);
return 0;
}
arch_initcall(sunxi_mbus_init);
|
linux-master
|
drivers/soc/sunxi/sunxi_mbus.c
|
/*
* Allwinner SoCs SRAM Controller Driver
*
* Copyright (C) 2015 Maxime Ripard
*
* Author: Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/debugfs.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/soc/sunxi/sunxi_sram.h>
struct sunxi_sram_func {
char *func;
u8 val;
u32 reg_val;
};
struct sunxi_sram_data {
char *name;
u8 reg;
u8 offset;
u8 width;
struct sunxi_sram_func *func;
struct list_head list;
};
struct sunxi_sram_desc {
struct sunxi_sram_data data;
bool claimed;
};
#define SUNXI_SRAM_MAP(_reg_val, _val, _func) \
{ \
.func = _func, \
.val = _val, \
.reg_val = _reg_val, \
}
#define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \
{ \
.name = _name, \
.reg = _reg, \
.offset = _off, \
.width = _width, \
.func = (struct sunxi_sram_func[]){ \
__VA_ARGS__, { } }, \
}
static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = {
.data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
SUNXI_SRAM_MAP(0, 0, "cpu"),
SUNXI_SRAM_MAP(1, 1, "emac")),
};
static struct sunxi_sram_desc sun4i_a10_sram_c1 = {
.data = SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31,
SUNXI_SRAM_MAP(0, 0, "cpu"),
SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")),
};
static struct sunxi_sram_desc sun4i_a10_sram_d = {
.data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
SUNXI_SRAM_MAP(0, 0, "cpu"),
SUNXI_SRAM_MAP(1, 1, "usb-otg")),
};
static struct sunxi_sram_desc sun50i_a64_sram_c = {
.data = SUNXI_SRAM_DATA("C", 0x4, 24, 1,
SUNXI_SRAM_MAP(1, 0, "cpu"),
SUNXI_SRAM_MAP(0, 1, "de2")),
};
static const struct of_device_id sunxi_sram_dt_ids[] = {
{
.compatible = "allwinner,sun4i-a10-sram-a3-a4",
.data = &sun4i_a10_sram_a3_a4.data,
},
{
.compatible = "allwinner,sun4i-a10-sram-c1",
.data = &sun4i_a10_sram_c1.data,
},
{
.compatible = "allwinner,sun4i-a10-sram-d",
.data = &sun4i_a10_sram_d.data,
},
{
.compatible = "allwinner,sun50i-a64-sram-c",
.data = &sun50i_a64_sram_c.data,
},
{}
};
static struct device *sram_dev;
static LIST_HEAD(claimed_sram);
static DEFINE_SPINLOCK(sram_lock);
static void __iomem *base;
static int sunxi_sram_show(struct seq_file *s, void *data)
{
struct device_node *sram_node, *section_node;
const struct sunxi_sram_data *sram_data;
const struct of_device_id *match;
struct sunxi_sram_func *func;
const __be32 *sram_addr_p, *section_addr_p;
u32 val;
seq_puts(s, "Allwinner sunXi SRAM\n");
seq_puts(s, "--------------------\n\n");
for_each_child_of_node(sram_dev->of_node, sram_node) {
if (!of_device_is_compatible(sram_node, "mmio-sram"))
continue;
sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
seq_printf(s, "sram@%08x\n",
be32_to_cpu(*sram_addr_p));
for_each_child_of_node(sram_node, section_node) {
match = of_match_node(sunxi_sram_dt_ids, section_node);
if (!match)
continue;
sram_data = match->data;
section_addr_p = of_get_address(section_node, 0,
NULL, NULL);
seq_printf(s, "\tsection@%04x\t(%s)\n",
be32_to_cpu(*section_addr_p),
sram_data->name);
val = readl(base + sram_data->reg);
val >>= sram_data->offset;
val &= GENMASK(sram_data->width - 1, 0);
for (func = sram_data->func; func->func; func++) {
seq_printf(s, "\t\t%s%c\n", func->func,
func->reg_val == val ?
'*' : ' ');
}
}
seq_puts(s, "\n");
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(sunxi_sram);
static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data)
{
return container_of(data, struct sunxi_sram_desc, data);
}
static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node,
unsigned int *reg_value)
{
const struct of_device_id *match;
const struct sunxi_sram_data *data;
struct sunxi_sram_func *func;
struct of_phandle_args args;
u8 val;
int ret;
ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0,
&args);
if (ret)
return ERR_PTR(ret);
if (!of_device_is_available(args.np)) {
ret = -EBUSY;
goto err;
}
val = args.args[0];
match = of_match_node(sunxi_sram_dt_ids, args.np);
if (!match) {
ret = -EINVAL;
goto err;
}
data = match->data;
if (!data) {
ret = -EINVAL;
goto err;
}
for (func = data->func; func->func; func++) {
if (val == func->val) {
if (reg_value)
*reg_value = func->reg_val;
break;
}
}
if (!func->func) {
ret = -EINVAL;
goto err;
}
of_node_put(args.np);
return match->data;
err:
of_node_put(args.np);
return ERR_PTR(ret);
}
int sunxi_sram_claim(struct device *dev)
{
const struct sunxi_sram_data *sram_data;
struct sunxi_sram_desc *sram_desc;
unsigned int device;
u32 val, mask;
if (IS_ERR(base))
return PTR_ERR(base);
if (!base)
return -EPROBE_DEFER;
if (!dev || !dev->of_node)
return -EINVAL;
sram_data = sunxi_sram_of_parse(dev->of_node, &device);
if (IS_ERR(sram_data))
return PTR_ERR(sram_data);
sram_desc = to_sram_desc(sram_data);
spin_lock(&sram_lock);
if (sram_desc->claimed) {
spin_unlock(&sram_lock);
return -EBUSY;
}
mask = GENMASK(sram_data->offset + sram_data->width - 1,
sram_data->offset);
val = readl(base + sram_data->reg);
val &= ~mask;
writel(val | ((device << sram_data->offset) & mask),
base + sram_data->reg);
sram_desc->claimed = true;
spin_unlock(&sram_lock);
return 0;
}
EXPORT_SYMBOL(sunxi_sram_claim);
void sunxi_sram_release(struct device *dev)
{
const struct sunxi_sram_data *sram_data;
struct sunxi_sram_desc *sram_desc;
if (!dev || !dev->of_node)
return;
sram_data = sunxi_sram_of_parse(dev->of_node, NULL);
if (IS_ERR(sram_data))
return;
sram_desc = to_sram_desc(sram_data);
spin_lock(&sram_lock);
sram_desc->claimed = false;
spin_unlock(&sram_lock);
}
EXPORT_SYMBOL(sunxi_sram_release);
struct sunxi_sramc_variant {
int num_emac_clocks;
bool has_ldo_ctrl;
};
static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
/* Nothing special */
};
static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = {
.num_emac_clocks = 1,
};
static const struct sunxi_sramc_variant sun20i_d1_sramc_variant = {
.num_emac_clocks = 1,
.has_ldo_ctrl = true,
};
static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
.num_emac_clocks = 1,
};
static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
.num_emac_clocks = 2,
};
#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
#define SUNXI_SYS_LDO_CTRL_REG 0x150
static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
unsigned int reg)
{
const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
return true;
if (reg == SUNXI_SYS_LDO_CTRL_REG && variant->has_ldo_ctrl)
return true;
return false;
}
static struct regmap_config sunxi_sram_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
/* last defined register */
.max_register = SUNXI_SYS_LDO_CTRL_REG,
/* other devices have no business accessing other registers */
.readable_reg = sunxi_sram_regmap_accessible_reg,
.writeable_reg = sunxi_sram_regmap_accessible_reg,
};
static int __init sunxi_sram_probe(struct platform_device *pdev)
{
const struct sunxi_sramc_variant *variant;
struct device *dev = &pdev->dev;
struct regmap *regmap;
sram_dev = &pdev->dev;
variant = of_device_get_match_data(&pdev->dev);
if (!variant)
return -EINVAL;
dev_set_drvdata(dev, (struct sunxi_sramc_variant *)variant);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
if (variant->num_emac_clocks || variant->has_ldo_ctrl) {
regmap = devm_regmap_init_mmio(dev, base, &sunxi_sram_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
}
of_platform_populate(dev->of_node, NULL, NULL, dev);
debugfs_create_file("sram", 0444, NULL, NULL, &sunxi_sram_fops);
return 0;
}
static const struct of_device_id sunxi_sram_dt_match[] = {
{
.compatible = "allwinner,sun4i-a10-sram-controller",
.data = &sun4i_a10_sramc_variant,
},
{
.compatible = "allwinner,sun4i-a10-system-control",
.data = &sun4i_a10_sramc_variant,
},
{
.compatible = "allwinner,sun5i-a13-system-control",
.data = &sun4i_a10_sramc_variant,
},
{
.compatible = "allwinner,sun8i-a23-system-control",
.data = &sun4i_a10_sramc_variant,
},
{
.compatible = "allwinner,sun8i-h3-system-control",
.data = &sun8i_h3_sramc_variant,
},
{
.compatible = "allwinner,sun20i-d1-system-control",
.data = &sun20i_d1_sramc_variant,
},
{
.compatible = "allwinner,sun50i-a64-sram-controller",
.data = &sun50i_a64_sramc_variant,
},
{
.compatible = "allwinner,sun50i-a64-system-control",
.data = &sun50i_a64_sramc_variant,
},
{
.compatible = "allwinner,sun50i-h5-system-control",
.data = &sun50i_a64_sramc_variant,
},
{
.compatible = "allwinner,sun50i-h616-system-control",
.data = &sun50i_h616_sramc_variant,
},
{ },
};
MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
static struct platform_driver sunxi_sram_driver = {
.driver = {
.name = "sunxi-sram",
.of_match_table = sunxi_sram_dt_match,
},
};
builtin_platform_driver_probe(sunxi_sram_driver, sunxi_sram_probe);
MODULE_AUTHOR("Maxime Ripard <[email protected]>");
MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver");
|
linux-master
|
drivers/soc/sunxi/sunxi_sram.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Microchip PolarFire SoC (MPFS) system controller driver
*
* Copyright (c) 2020-2021 Microchip Corporation. All rights reserved.
*
* Author: Conor Dooley <[email protected]>
*
*/
#include <linux/slab.h>
#include <linux/kref.h>
#include <linux/module.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/mailbox_client.h>
#include <linux/platform_device.h>
#include <soc/microchip/mpfs.h>
/*
* This timeout must be long, as some services (example: image authentication)
* take significant time to complete
*/
#define MPFS_SYS_CTRL_TIMEOUT_MS 30000
static DEFINE_MUTEX(transaction_lock);
struct mpfs_sys_controller {
struct mbox_client client;
struct mbox_chan *chan;
struct completion c;
struct kref consumers;
};
int mpfs_blocking_transaction(struct mpfs_sys_controller *sys_controller, struct mpfs_mss_msg *msg)
{
unsigned long timeout = msecs_to_jiffies(MPFS_SYS_CTRL_TIMEOUT_MS);
int ret;
ret = mutex_lock_interruptible(&transaction_lock);
if (ret)
return ret;
reinit_completion(&sys_controller->c);
ret = mbox_send_message(sys_controller->chan, msg);
if (ret < 0) {
dev_warn(sys_controller->client.dev, "MPFS sys controller service timeout\n");
goto out;
}
/*
* Unfortunately, the system controller will only deliver an interrupt
* if a service succeeds. mbox_send_message() will block until the busy
* flag is gone. If the busy flag is gone but no interrupt has arrived
* to trigger the rx callback then the service can be deemed to have
* failed.
* The caller can then interrogate msg::response::resp_status to
* determine the cause of the failure.
* mbox_send_message() returns positive integers in the success path, so
* ret needs to be cleared if we do get an interrupt.
*/
if (!wait_for_completion_timeout(&sys_controller->c, timeout)) {
ret = -EBADMSG;
dev_warn(sys_controller->client.dev, "MPFS sys controller service failed\n");
} else {
ret = 0;
}
out:
mutex_unlock(&transaction_lock);
return ret;
}
EXPORT_SYMBOL(mpfs_blocking_transaction);
static void mpfs_sys_controller_rx_callback(struct mbox_client *client, void *msg)
{
struct mpfs_sys_controller *sys_controller =
container_of(client, struct mpfs_sys_controller, client);
complete(&sys_controller->c);
}
static void mpfs_sys_controller_delete(struct kref *kref)
{
struct mpfs_sys_controller *sys_controller =
container_of(kref, struct mpfs_sys_controller, consumers);
mbox_free_channel(sys_controller->chan);
kfree(sys_controller);
}
static void mpfs_sys_controller_put(void *data)
{
struct mpfs_sys_controller *sys_controller = data;
kref_put(&sys_controller->consumers, mpfs_sys_controller_delete);
}
static struct platform_device subdevs[] = {
{
.name = "mpfs-rng",
.id = -1,
},
{
.name = "mpfs-generic-service",
.id = -1,
}
};
static int mpfs_sys_controller_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mpfs_sys_controller *sys_controller;
int i, ret;
sys_controller = kzalloc(sizeof(*sys_controller), GFP_KERNEL);
if (!sys_controller)
return -ENOMEM;
sys_controller->client.dev = dev;
sys_controller->client.rx_callback = mpfs_sys_controller_rx_callback;
sys_controller->client.tx_block = 1U;
sys_controller->client.tx_tout = msecs_to_jiffies(MPFS_SYS_CTRL_TIMEOUT_MS);
sys_controller->chan = mbox_request_channel(&sys_controller->client, 0);
if (IS_ERR(sys_controller->chan)) {
ret = dev_err_probe(dev, PTR_ERR(sys_controller->chan),
"Failed to get mbox channel\n");
kfree(sys_controller);
return ret;
}
init_completion(&sys_controller->c);
kref_init(&sys_controller->consumers);
platform_set_drvdata(pdev, sys_controller);
dev_info(&pdev->dev, "Registered MPFS system controller\n");
for (i = 0; i < ARRAY_SIZE(subdevs); i++) {
subdevs[i].dev.parent = dev;
if (platform_device_register(&subdevs[i]))
dev_warn(dev, "Error registering sub device %s\n", subdevs[i].name);
}
return 0;
}
static int mpfs_sys_controller_remove(struct platform_device *pdev)
{
struct mpfs_sys_controller *sys_controller = platform_get_drvdata(pdev);
mpfs_sys_controller_put(sys_controller);
return 0;
}
static const struct of_device_id mpfs_sys_controller_of_match[] = {
{.compatible = "microchip,mpfs-sys-controller", },
{},
};
MODULE_DEVICE_TABLE(of, mpfs_sys_controller_of_match);
struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev)
{
const struct of_device_id *match;
struct mpfs_sys_controller *sys_controller;
int ret;
if (!dev->parent)
goto err_no_device;
match = of_match_node(mpfs_sys_controller_of_match, dev->parent->of_node);
of_node_put(dev->parent->of_node);
if (!match)
goto err_no_device;
sys_controller = dev_get_drvdata(dev->parent);
if (!sys_controller)
goto err_bad_device;
if (!kref_get_unless_zero(&sys_controller->consumers))
goto err_bad_device;
ret = devm_add_action_or_reset(dev, mpfs_sys_controller_put, sys_controller);
if (ret)
return ERR_PTR(ret);
return sys_controller;
err_no_device:
dev_dbg(dev, "Parent device was not an MPFS system controller\n");
return ERR_PTR(-ENODEV);
err_bad_device:
dev_dbg(dev, "MPFS system controller found but could not register as a sub device\n");
return ERR_PTR(-EPROBE_DEFER);
}
EXPORT_SYMBOL(mpfs_sys_controller_get);
static struct platform_driver mpfs_sys_controller_driver = {
.driver = {
.name = "mpfs-sys-controller",
.of_match_table = mpfs_sys_controller_of_match,
},
.probe = mpfs_sys_controller_probe,
.remove = mpfs_sys_controller_remove,
};
module_platform_driver(mpfs_sys_controller_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Conor Dooley <[email protected]>");
MODULE_DESCRIPTION("MPFS system controller driver");
|
linux-master
|
drivers/soc/microchip/mpfs-sys-controller.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Copyright (C) 2011-2015 John Crispin <[email protected]>
* Copyright (C) 2015 Martin Blumenstingl <[email protected]>
* Copyright (C) 2017 Hauke Mehrtens <[email protected]>
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <lantiq_soc.h>
#define XBAR_ALWAYS_LAST 0x430
#define XBAR_FPI_BURST_EN BIT(1)
#define XBAR_AHB_BURST_EN BIT(2)
#define RCU_VR9_BE_AHB1S 0x00000008
static int ltq_fpi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct regmap *rcu_regmap;
void __iomem *xbar_membase;
u32 rcu_ahb_endianness_reg_offset;
int ret;
xbar_membase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(xbar_membase))
return PTR_ERR(xbar_membase);
/* RCU configuration is optional */
rcu_regmap = syscon_regmap_lookup_by_phandle(np, "lantiq,rcu");
if (IS_ERR(rcu_regmap))
return PTR_ERR(rcu_regmap);
ret = device_property_read_u32(dev, "lantiq,offset-endianness",
&rcu_ahb_endianness_reg_offset);
if (ret) {
dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
return ret;
}
ret = regmap_update_bits(rcu_regmap, rcu_ahb_endianness_reg_offset,
RCU_VR9_BE_AHB1S, RCU_VR9_BE_AHB1S);
if (ret) {
dev_warn(&pdev->dev,
"Failed to configure RCU AHB endianness\n");
return ret;
}
/* disable fpi burst */
ltq_w32_mask(XBAR_FPI_BURST_EN, 0, xbar_membase + XBAR_ALWAYS_LAST);
return of_platform_populate(dev->of_node, NULL, NULL, dev);
}
static const struct of_device_id ltq_fpi_match[] = {
{ .compatible = "lantiq,xrx200-fpi" },
{},
};
MODULE_DEVICE_TABLE(of, ltq_fpi_match);
static struct platform_driver ltq_fpi_driver = {
.probe = ltq_fpi_probe,
.driver = {
.name = "fpi-xway",
.of_match_table = ltq_fpi_match,
},
};
module_platform_driver(ltq_fpi_driver);
MODULE_DESCRIPTION("Lantiq FPI bus driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/soc/lantiq/fpi-bus.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Marvell Dove PMU support
*/
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/reset.h>
#include <linux/reset-controller.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/soc/dove/pmu.h>
#include <linux/spinlock.h>
#define NR_PMU_IRQS 7
#define PMC_SW_RST 0x30
#define PMC_IRQ_CAUSE 0x50
#define PMC_IRQ_MASK 0x54
#define PMU_PWR 0x10
#define PMU_ISO 0x58
struct pmu_data {
spinlock_t lock;
struct device_node *of_node;
void __iomem *pmc_base;
void __iomem *pmu_base;
struct irq_chip_generic *irq_gc;
struct irq_domain *irq_domain;
#ifdef CONFIG_RESET_CONTROLLER
struct reset_controller_dev reset;
#endif
};
/*
* The PMU contains a register to reset various subsystems within the
* SoC. Export this as a reset controller.
*/
#ifdef CONFIG_RESET_CONTROLLER
#define rcdev_to_pmu(rcdev) container_of(rcdev, struct pmu_data, reset)
static int pmu_reset_reset(struct reset_controller_dev *rc, unsigned long id)
{
struct pmu_data *pmu = rcdev_to_pmu(rc);
unsigned long flags;
u32 val;
spin_lock_irqsave(&pmu->lock, flags);
val = readl_relaxed(pmu->pmc_base + PMC_SW_RST);
writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST);
writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST);
spin_unlock_irqrestore(&pmu->lock, flags);
return 0;
}
static int pmu_reset_assert(struct reset_controller_dev *rc, unsigned long id)
{
struct pmu_data *pmu = rcdev_to_pmu(rc);
unsigned long flags;
u32 val = ~BIT(id);
spin_lock_irqsave(&pmu->lock, flags);
val &= readl_relaxed(pmu->pmc_base + PMC_SW_RST);
writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
spin_unlock_irqrestore(&pmu->lock, flags);
return 0;
}
static int pmu_reset_deassert(struct reset_controller_dev *rc, unsigned long id)
{
struct pmu_data *pmu = rcdev_to_pmu(rc);
unsigned long flags;
u32 val = BIT(id);
spin_lock_irqsave(&pmu->lock, flags);
val |= readl_relaxed(pmu->pmc_base + PMC_SW_RST);
writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
spin_unlock_irqrestore(&pmu->lock, flags);
return 0;
}
static const struct reset_control_ops pmu_reset_ops = {
.reset = pmu_reset_reset,
.assert = pmu_reset_assert,
.deassert = pmu_reset_deassert,
};
static struct reset_controller_dev pmu_reset __initdata = {
.ops = &pmu_reset_ops,
.owner = THIS_MODULE,
.nr_resets = 32,
};
static void __init pmu_reset_init(struct pmu_data *pmu)
{
int ret;
pmu->reset = pmu_reset;
pmu->reset.of_node = pmu->of_node;
ret = reset_controller_register(&pmu->reset);
if (ret)
pr_err("pmu: %s failed: %d\n", "reset_controller_register", ret);
}
#else
static void __init pmu_reset_init(struct pmu_data *pmu)
{
}
#endif
struct pmu_domain {
struct pmu_data *pmu;
u32 pwr_mask;
u32 rst_mask;
u32 iso_mask;
struct generic_pm_domain base;
};
#define to_pmu_domain(dom) container_of(dom, struct pmu_domain, base)
/*
* This deals with the "old" Marvell sequence of bringing a power domain
* down/up, which is: apply power, release reset, disable isolators.
*
* Later devices apparantly use a different sequence: power up, disable
* isolators, assert repair signal, enable SRMA clock, enable AXI clock,
* enable module clock, deassert reset.
*
* Note: reading the assembly, it seems that the IO accessors have an
* unfortunate side-effect - they cause memory already read into registers
* for the if () to be re-read for the bit-set or bit-clear operation.
* The code is written to avoid this.
*/
static int pmu_domain_power_off(struct generic_pm_domain *domain)
{
struct pmu_domain *pmu_dom = to_pmu_domain(domain);
struct pmu_data *pmu = pmu_dom->pmu;
unsigned long flags;
unsigned int val;
void __iomem *pmu_base = pmu->pmu_base;
void __iomem *pmc_base = pmu->pmc_base;
spin_lock_irqsave(&pmu->lock, flags);
/* Enable isolators */
if (pmu_dom->iso_mask) {
val = ~pmu_dom->iso_mask;
val &= readl_relaxed(pmu_base + PMU_ISO);
writel_relaxed(val, pmu_base + PMU_ISO);
}
/* Reset unit */
if (pmu_dom->rst_mask) {
val = ~pmu_dom->rst_mask;
val &= readl_relaxed(pmc_base + PMC_SW_RST);
writel_relaxed(val, pmc_base + PMC_SW_RST);
}
/* Power down */
val = readl_relaxed(pmu_base + PMU_PWR) | pmu_dom->pwr_mask;
writel_relaxed(val, pmu_base + PMU_PWR);
spin_unlock_irqrestore(&pmu->lock, flags);
return 0;
}
static int pmu_domain_power_on(struct generic_pm_domain *domain)
{
struct pmu_domain *pmu_dom = to_pmu_domain(domain);
struct pmu_data *pmu = pmu_dom->pmu;
unsigned long flags;
unsigned int val;
void __iomem *pmu_base = pmu->pmu_base;
void __iomem *pmc_base = pmu->pmc_base;
spin_lock_irqsave(&pmu->lock, flags);
/* Power on */
val = ~pmu_dom->pwr_mask & readl_relaxed(pmu_base + PMU_PWR);
writel_relaxed(val, pmu_base + PMU_PWR);
/* Release reset */
if (pmu_dom->rst_mask) {
val = pmu_dom->rst_mask;
val |= readl_relaxed(pmc_base + PMC_SW_RST);
writel_relaxed(val, pmc_base + PMC_SW_RST);
}
/* Disable isolators */
if (pmu_dom->iso_mask) {
val = pmu_dom->iso_mask;
val |= readl_relaxed(pmu_base + PMU_ISO);
writel_relaxed(val, pmu_base + PMU_ISO);
}
spin_unlock_irqrestore(&pmu->lock, flags);
return 0;
}
static void __pmu_domain_register(struct pmu_domain *domain,
struct device_node *np)
{
unsigned int val = readl_relaxed(domain->pmu->pmu_base + PMU_PWR);
domain->base.power_off = pmu_domain_power_off;
domain->base.power_on = pmu_domain_power_on;
pm_genpd_init(&domain->base, NULL, !(val & domain->pwr_mask));
if (np)
of_genpd_add_provider_simple(np, &domain->base);
}
/* PMU IRQ controller */
static void pmu_irq_handler(struct irq_desc *desc)
{
struct pmu_data *pmu = irq_desc_get_handler_data(desc);
struct irq_chip_generic *gc = pmu->irq_gc;
struct irq_domain *domain = pmu->irq_domain;
void __iomem *base = gc->reg_base;
u32 stat = readl_relaxed(base + PMC_IRQ_CAUSE) & gc->mask_cache;
u32 done = ~0;
if (stat == 0) {
handle_bad_irq(desc);
return;
}
while (stat) {
u32 hwirq = fls(stat) - 1;
stat &= ~(1 << hwirq);
done &= ~(1 << hwirq);
generic_handle_irq(irq_find_mapping(domain, hwirq));
}
/*
* The PMU mask register is not RW0C: it is RW. This means that
* the bits take whatever value is written to them; if you write
* a '1', you will set the interrupt.
*
* Unfortunately this means there is NO race free way to clear
* these interrupts.
*
* So, let's structure the code so that the window is as small as
* possible.
*/
irq_gc_lock(gc);
done &= readl_relaxed(base + PMC_IRQ_CAUSE);
writel_relaxed(done, base + PMC_IRQ_CAUSE);
irq_gc_unlock(gc);
}
static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq)
{
const char *name = "pmu_irq";
struct irq_chip_generic *gc;
struct irq_domain *domain;
int ret;
/* mask and clear all interrupts */
writel(0, pmu->pmc_base + PMC_IRQ_MASK);
writel(0, pmu->pmc_base + PMC_IRQ_CAUSE);
domain = irq_domain_add_linear(pmu->of_node, NR_PMU_IRQS,
&irq_generic_chip_ops, NULL);
if (!domain) {
pr_err("%s: unable to add irq domain\n", name);
return -ENOMEM;
}
ret = irq_alloc_domain_generic_chips(domain, NR_PMU_IRQS, 1, name,
handle_level_irq,
IRQ_NOREQUEST | IRQ_NOPROBE, 0,
IRQ_GC_INIT_MASK_CACHE);
if (ret) {
pr_err("%s: unable to alloc irq domain gc: %d\n", name, ret);
irq_domain_remove(domain);
return ret;
}
gc = irq_get_domain_generic_chip(domain, 0);
gc->reg_base = pmu->pmc_base;
gc->chip_types[0].regs.mask = PMC_IRQ_MASK;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
pmu->irq_domain = domain;
pmu->irq_gc = gc;
irq_set_handler_data(irq, pmu);
irq_set_chained_handler(irq, pmu_irq_handler);
return 0;
}
int __init dove_init_pmu_legacy(const struct dove_pmu_initdata *initdata)
{
const struct dove_pmu_domain_initdata *domain_initdata;
struct pmu_data *pmu;
int ret;
pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
if (!pmu)
return -ENOMEM;
spin_lock_init(&pmu->lock);
pmu->pmc_base = initdata->pmc_base;
pmu->pmu_base = initdata->pmu_base;
pmu_reset_init(pmu);
for (domain_initdata = initdata->domains; domain_initdata->name;
domain_initdata++) {
struct pmu_domain *domain;
domain = kzalloc(sizeof(*domain), GFP_KERNEL);
if (domain) {
domain->pmu = pmu;
domain->pwr_mask = domain_initdata->pwr_mask;
domain->rst_mask = domain_initdata->rst_mask;
domain->iso_mask = domain_initdata->iso_mask;
domain->base.name = domain_initdata->name;
__pmu_domain_register(domain, NULL);
}
}
ret = dove_init_pmu_irq(pmu, initdata->irq);
if (ret)
pr_err("dove_init_pmu_irq() failed: %d\n", ret);
if (pmu->irq_domain)
irq_domain_associate_many(pmu->irq_domain,
initdata->irq_domain_start,
0, NR_PMU_IRQS);
return 0;
}
/*
* pmu: power-manager@d0000 {
* compatible = "marvell,dove-pmu";
* reg = <0xd0000 0x8000> <0xd8000 0x8000>;
* interrupts = <33>;
* interrupt-controller;
* #reset-cells = 1;
* vpu_domain: vpu-domain {
* #power-domain-cells = <0>;
* marvell,pmu_pwr_mask = <0x00000008>;
* marvell,pmu_iso_mask = <0x00000001>;
* resets = <&pmu 16>;
* };
* gpu_domain: gpu-domain {
* #power-domain-cells = <0>;
* marvell,pmu_pwr_mask = <0x00000004>;
* marvell,pmu_iso_mask = <0x00000002>;
* resets = <&pmu 18>;
* };
* };
*/
int __init dove_init_pmu(void)
{
struct device_node *np_pmu, *domains_node, *np;
struct pmu_data *pmu;
int ret, parent_irq;
/* Lookup the PMU node */
np_pmu = of_find_compatible_node(NULL, NULL, "marvell,dove-pmu");
if (!np_pmu)
return 0;
domains_node = of_get_child_by_name(np_pmu, "domains");
if (!domains_node) {
pr_err("%pOFn: failed to find domains sub-node\n", np_pmu);
return 0;
}
pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
if (!pmu)
return -ENOMEM;
spin_lock_init(&pmu->lock);
pmu->of_node = np_pmu;
pmu->pmc_base = of_iomap(pmu->of_node, 0);
pmu->pmu_base = of_iomap(pmu->of_node, 1);
if (!pmu->pmc_base || !pmu->pmu_base) {
pr_err("%pOFn: failed to map PMU\n", np_pmu);
iounmap(pmu->pmu_base);
iounmap(pmu->pmc_base);
kfree(pmu);
return -ENOMEM;
}
pmu_reset_init(pmu);
for_each_available_child_of_node(domains_node, np) {
struct of_phandle_args args;
struct pmu_domain *domain;
domain = kzalloc(sizeof(*domain), GFP_KERNEL);
if (!domain)
break;
domain->pmu = pmu;
domain->base.name = kasprintf(GFP_KERNEL, "%pOFn", np);
if (!domain->base.name) {
kfree(domain);
break;
}
of_property_read_u32(np, "marvell,pmu_pwr_mask",
&domain->pwr_mask);
of_property_read_u32(np, "marvell,pmu_iso_mask",
&domain->iso_mask);
/*
* We parse the reset controller property directly here
* to ensure that we can operate when the reset controller
* support is not configured into the kernel.
*/
ret = of_parse_phandle_with_args(np, "resets", "#reset-cells",
0, &args);
if (ret == 0) {
if (args.np == pmu->of_node)
domain->rst_mask = BIT(args.args[0]);
of_node_put(args.np);
}
__pmu_domain_register(domain, np);
}
/* Loss of the interrupt controller is not a fatal error. */
parent_irq = irq_of_parse_and_map(pmu->of_node, 0);
if (!parent_irq) {
pr_err("%pOFn: no interrupt specified\n", np_pmu);
} else {
ret = dove_init_pmu_irq(pmu, parent_irq);
if (ret)
pr_err("dove_init_pmu_irq() failed: %d\n", ret);
}
return 0;
}
|
linux-master
|
drivers/soc/dove/pmu.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Intel IXP4xx Network Processor Engine driver for Linux
*
* Copyright (C) 2007 Krzysztof Halasa <[email protected]>
*
* The code is based on publicly available information:
* - Intel IXP4xx Developer's Manual and other e-papers
* - Intel IXP400 Access Library Software (BSD license)
* - previous works by Christian Hohnstaedt <[email protected]>
* Thanks, Christian.
*/
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/firmware.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/soc/ixp4xx/npe.h>
#include <linux/soc/ixp4xx/cpu.h>
#define DEBUG_MSG 0
#define DEBUG_FW 0
#define NPE_COUNT 3
#define MAX_RETRIES 1000 /* microseconds */
#define NPE_42X_DATA_SIZE 0x800 /* in dwords */
#define NPE_46X_DATA_SIZE 0x1000
#define NPE_A_42X_INSTR_SIZE 0x1000
#define NPE_B_AND_C_42X_INSTR_SIZE 0x800
#define NPE_46X_INSTR_SIZE 0x1000
#define REGS_SIZE 0x1000
#define NPE_PHYS_REG 32
#define FW_MAGIC 0xFEEDF00D
#define FW_BLOCK_TYPE_INSTR 0x0
#define FW_BLOCK_TYPE_DATA 0x1
#define FW_BLOCK_TYPE_EOF 0xF
/* NPE exec status (read) and command (write) */
#define CMD_NPE_STEP 0x01
#define CMD_NPE_START 0x02
#define CMD_NPE_STOP 0x03
#define CMD_NPE_CLR_PIPE 0x04
#define CMD_CLR_PROFILE_CNT 0x0C
#define CMD_RD_INS_MEM 0x10 /* instruction memory */
#define CMD_WR_INS_MEM 0x11
#define CMD_RD_DATA_MEM 0x12 /* data memory */
#define CMD_WR_DATA_MEM 0x13
#define CMD_RD_ECS_REG 0x14 /* exec access register */
#define CMD_WR_ECS_REG 0x15
#define STAT_RUN 0x80000000
#define STAT_STOP 0x40000000
#define STAT_CLEAR 0x20000000
#define STAT_ECS_K 0x00800000 /* pipeline clean */
#define NPE_STEVT 0x1B
#define NPE_STARTPC 0x1C
#define NPE_REGMAP 0x1E
#define NPE_CINDEX 0x1F
#define INSTR_WR_REG_SHORT 0x0000C000
#define INSTR_WR_REG_BYTE 0x00004000
#define INSTR_RD_FIFO 0x0F888220
#define INSTR_RESET_MBOX 0x0FAC8210
#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */
#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */
#define ECS_BG_CTXT_REG_2 0x02
#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */
#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */
#define ECS_PRI_1_CTXT_REG_2 0x06
#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */
#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */
#define ECS_PRI_2_CTXT_REG_2 0x0A
#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */
#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */
#define ECS_DBG_CTXT_REG_2 0x0E
#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */
#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */
#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */
#define ECS_REG_0_LDUR_BITS 8
#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */
#define ECS_REG_1_CCTXT_BITS 16
#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */
#define ECS_REG_1_SELCTXT_BITS 0
#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */
#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */
#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */
/* NPE watchpoint_fifo register bit */
#define WFIFO_VALID 0x80000000
/* NPE messaging_status register bit definitions */
#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */
#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */
#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */
#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */
#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */
#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */
#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */
#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */
/* NPE messaging_control register bit definitions */
#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */
#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */
#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */
#define MSGCTL_IN_FIFO_WRITE 0x02000000
/* NPE mailbox_status value for reset */
#define RESET_MBOX_STAT 0x0000F0F0
#define NPE_A_FIRMWARE "NPE-A"
#define NPE_B_FIRMWARE "NPE-B"
#define NPE_C_FIRMWARE "NPE-C"
const char *npe_names[] = { NPE_A_FIRMWARE, NPE_B_FIRMWARE, NPE_C_FIRMWARE };
#define print_npe(pri, npe, fmt, ...) \
printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
#if DEBUG_MSG
#define debug_msg(npe, fmt, ...) \
print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
#else
#define debug_msg(npe, fmt, ...)
#endif
static struct {
u32 reg, val;
} ecs_reset[] = {
{ ECS_BG_CTXT_REG_0, 0xA0000000 },
{ ECS_BG_CTXT_REG_1, 0x01000000 },
{ ECS_BG_CTXT_REG_2, 0x00008000 },
{ ECS_PRI_1_CTXT_REG_0, 0x20000080 },
{ ECS_PRI_1_CTXT_REG_1, 0x01000000 },
{ ECS_PRI_1_CTXT_REG_2, 0x00008000 },
{ ECS_PRI_2_CTXT_REG_0, 0x20000080 },
{ ECS_PRI_2_CTXT_REG_1, 0x01000000 },
{ ECS_PRI_2_CTXT_REG_2, 0x00008000 },
{ ECS_DBG_CTXT_REG_0, 0x20000000 },
{ ECS_DBG_CTXT_REG_1, 0x00000000 },
{ ECS_DBG_CTXT_REG_2, 0x001E0000 },
{ ECS_INSTRUCT_REG, 0x1003C00F },
};
static struct npe npe_tab[NPE_COUNT] = {
{
.id = 0,
}, {
.id = 1,
}, {
.id = 2,
}
};
int npe_running(struct npe *npe)
{
return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
}
static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
{
__raw_writel(data, &npe->regs->exec_data);
__raw_writel(addr, &npe->regs->exec_addr);
__raw_writel(cmd, &npe->regs->exec_status_cmd);
}
static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
{
__raw_writel(addr, &npe->regs->exec_addr);
__raw_writel(cmd, &npe->regs->exec_status_cmd);
/* Iintroduce extra read cycles after issuing read command to NPE
so that we read the register after the NPE has updated it.
This is to overcome race condition between XScale and NPE */
__raw_readl(&npe->regs->exec_data);
__raw_readl(&npe->regs->exec_data);
return __raw_readl(&npe->regs->exec_data);
}
static void npe_clear_active(struct npe *npe, u32 reg)
{
u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
}
static void npe_start(struct npe *npe)
{
/* ensure only Background Context Stack Level is active */
npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
__raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
}
static void npe_stop(struct npe *npe)
{
__raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
}
static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
u32 ldur)
{
u32 wc;
int i;
/* set the Active bit, and the LDUR, in the debug level */
npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
/* set CCTXT at ECS DEBUG L3 to specify in which context to execute
the instruction, and set SELCTXT at ECS DEBUG Level to specify
which context store to access.
Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
*/
npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
(ctx << ECS_REG_1_CCTXT_BITS) |
(ctx << ECS_REG_1_SELCTXT_BITS));
/* clear the pipeline */
__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
/* load NPE instruction into the instruction register */
npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
/* we need this value later to wait for completion of NPE execution
step */
wc = __raw_readl(&npe->regs->watch_count);
/* issue a Step One command via the Execution Control register */
__raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
/* Watch Count register increments when NPE completes an instruction */
for (i = 0; i < MAX_RETRIES; i++) {
if (wc != __raw_readl(&npe->regs->watch_count))
return 0;
udelay(1);
}
print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
return -ETIMEDOUT;
}
static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
u8 val, u32 ctx)
{
/* here we build the NPE assembler instruction: mov8 d0, #0 */
u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
addr << 9 | /* base Operand */
(val & 0x1F) << 4 | /* lower 5 bits to immediate data */
(val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
}
static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
u16 val, u32 ctx)
{
/* here we build the NPE assembler instruction: mov16 d0, #0 */
u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
addr << 9 | /* base Operand */
(val & 0x1F) << 4 | /* lower 5 bits to immediate data */
(val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
}
static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
u32 val, u32 ctx)
{
/* write in 16 bit steps first the high and then the low value */
if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
return -ETIMEDOUT;
return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
}
static int npe_reset(struct npe *npe)
{
u32 reset_bit = (IXP4XX_FEATURE_RESET_NPEA << npe->id);
u32 val, ctl, exec_count, ctx_reg2;
int i;
ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
0x3F3FFFFF;
/* disable parity interrupt */
__raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
/* pre exec - debug instruction */
/* turn off the halt bit by clearing Execution Count register. */
exec_count = __raw_readl(&npe->regs->exec_count);
__raw_writel(0, &npe->regs->exec_count);
/* ensure that IF and IE are on (temporarily), so that we don't end up
stepping forever */
ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
/* clear the FIFOs */
while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
;
while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
/* read from the outFIFO until empty */
print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
__raw_readl(&npe->regs->in_out_fifo));
while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
/* step execution of the NPE intruction to read inFIFO using
the Debug Executing Context stack */
if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
return -ETIMEDOUT;
/* reset the mailbox reg from the XScale side */
__raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
/* from NPE side */
if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
return -ETIMEDOUT;
/* Reset the physical registers in the NPE register file */
for (val = 0; val < NPE_PHYS_REG; val++) {
if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
return -ETIMEDOUT;
/* address is either 0 or 4 */
if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
return -ETIMEDOUT;
}
/* Reset the context store = each context's Context Store registers */
/* Context 0 has no STARTPC. Instead, this value is used to set NextPC
for Background ECS, to set where NPE starts executing code */
val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
val &= ~ECS_REG_0_NEXTPC_MASK;
val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
for (i = 0; i < 16; i++) {
if (i) { /* Context 0 has no STEVT nor STARTPC */
/* STEVT = off, 0x80 */
if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
return -ETIMEDOUT;
if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
return -ETIMEDOUT;
}
/* REGMAP = d0->p0, d8->p2, d16->p4 */
if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
return -ETIMEDOUT;
if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
return -ETIMEDOUT;
}
/* post exec */
/* clear active bit in debug level */
npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
/* clear the pipeline */
__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
/* restore previous values */
__raw_writel(exec_count, &npe->regs->exec_count);
npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
/* write reset values to Execution Context Stack registers */
for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
ecs_reset[val].val);
/* clear the profile counter */
__raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
__raw_writel(0, &npe->regs->exec_count);
__raw_writel(0, &npe->regs->action_points[0]);
__raw_writel(0, &npe->regs->action_points[1]);
__raw_writel(0, &npe->regs->action_points[2]);
__raw_writel(0, &npe->regs->action_points[3]);
__raw_writel(0, &npe->regs->watch_count);
/*
* We need to work on cached values here because the register
* will read inverted but needs to be written non-inverted.
*/
val = cpu_ixp4xx_features(npe->rmap);
/* reset the NPE */
regmap_write(npe->rmap, IXP4XX_EXP_CNFG2, val & ~reset_bit);
/* deassert reset */
regmap_write(npe->rmap, IXP4XX_EXP_CNFG2, val | reset_bit);
for (i = 0; i < MAX_RETRIES; i++) {
val = cpu_ixp4xx_features(npe->rmap);
if (val & reset_bit)
break; /* NPE is back alive */
udelay(1);
}
if (i == MAX_RETRIES)
return -ETIMEDOUT;
npe_stop(npe);
/* restore NPE configuration bus Control Register - parity settings */
__raw_writel(ctl, &npe->regs->messaging_control);
return 0;
}
int npe_send_message(struct npe *npe, const void *msg, const char *what)
{
const u32 *send = msg;
int cycles = 0;
debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
what, send[0], send[1]);
if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
debug_msg(npe, "NPE input FIFO not empty\n");
return -EIO;
}
__raw_writel(send[0], &npe->regs->in_out_fifo);
if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
debug_msg(npe, "NPE input FIFO full\n");
return -EIO;
}
__raw_writel(send[1], &npe->regs->in_out_fifo);
while ((cycles < MAX_RETRIES) &&
(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
udelay(1);
cycles++;
}
if (cycles == MAX_RETRIES) {
debug_msg(npe, "Timeout sending message\n");
return -ETIMEDOUT;
}
#if DEBUG_MSG > 1
debug_msg(npe, "Sending a message took %i cycles\n", cycles);
#endif
return 0;
}
int npe_recv_message(struct npe *npe, void *msg, const char *what)
{
u32 *recv = msg;
int cycles = 0, cnt = 0;
debug_msg(npe, "Trying to receive message %s\n", what);
while (cycles < MAX_RETRIES) {
if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
if (cnt == 2)
break;
} else {
udelay(1);
cycles++;
}
}
switch(cnt) {
case 1:
debug_msg(npe, "Received [%08X]\n", recv[0]);
break;
case 2:
debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
break;
}
if (cycles == MAX_RETRIES) {
debug_msg(npe, "Timeout waiting for message\n");
return -ETIMEDOUT;
}
#if DEBUG_MSG > 1
debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
#endif
return 0;
}
int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
{
int result;
u32 *send = msg, recv[2];
if ((result = npe_send_message(npe, msg, what)) != 0)
return result;
if ((result = npe_recv_message(npe, recv, what)) != 0)
return result;
if ((recv[0] != send[0]) || (recv[1] != send[1])) {
debug_msg(npe, "Message %s: unexpected message received\n",
what);
return -EIO;
}
return 0;
}
int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
{
const struct firmware *fw_entry;
struct dl_block {
u32 type;
u32 offset;
} *blk;
struct dl_image {
u32 magic;
u32 id;
u32 size;
union {
DECLARE_FLEX_ARRAY(u32, data);
DECLARE_FLEX_ARRAY(struct dl_block, blocks);
};
} *image;
struct dl_codeblock {
u32 npe_addr;
u32 size;
u32 data[];
} *cb;
int i, j, err, data_size, instr_size, blocks, table_end;
u32 cmd;
if ((err = request_firmware(&fw_entry, name, dev)) != 0)
return err;
err = -EINVAL;
if (fw_entry->size < sizeof(struct dl_image)) {
print_npe(KERN_ERR, npe, "incomplete firmware file\n");
goto err;
}
image = (struct dl_image*)fw_entry->data;
#if DEBUG_FW
print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
image->magic, image->id, image->size, image->size * 4);
#endif
if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
image->id = swab32(image->id);
image->size = swab32(image->size);
} else if (image->magic != FW_MAGIC) {
print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
image->magic);
goto err;
}
if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
print_npe(KERN_ERR, npe,
"inconsistent size of firmware file\n");
goto err;
}
if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
goto err;
}
if (image->magic == swab32(FW_MAGIC))
for (i = 0; i < image->size; i++)
image->data[i] = swab32(image->data[i]);
if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) {
print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on "
"IXP42x\n");
goto err;
}
if (npe_running(npe)) {
print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
"already running\n");
err = -EBUSY;
goto err;
}
#if 0
npe_stop(npe);
npe_reset(npe);
#endif
print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
"revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
(image->id >> 8) & 0xFF, image->id & 0xFF);
if (cpu_is_ixp42x()) {
if (!npe->id)
instr_size = NPE_A_42X_INSTR_SIZE;
else
instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
data_size = NPE_42X_DATA_SIZE;
} else {
instr_size = NPE_46X_INSTR_SIZE;
data_size = NPE_46X_DATA_SIZE;
}
for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
blocks++)
if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
break;
if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
print_npe(KERN_INFO, npe, "firmware EOF block marker not "
"found\n");
goto err;
}
#if DEBUG_FW
print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
#endif
table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
|| blk->offset < table_end) {
print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
"firmware block #%i\n", blk->offset, i);
goto err;
}
cb = (struct dl_codeblock*)&image->data[blk->offset];
if (blk->type == FW_BLOCK_TYPE_INSTR) {
if (cb->npe_addr + cb->size > instr_size)
goto too_big;
cmd = CMD_WR_INS_MEM;
} else if (blk->type == FW_BLOCK_TYPE_DATA) {
if (cb->npe_addr + cb->size > data_size)
goto too_big;
cmd = CMD_WR_DATA_MEM;
} else {
print_npe(KERN_INFO, npe, "invalid firmware block #%i "
"type 0x%X\n", i, blk->type);
goto err;
}
if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
"fit in firmware image: type %c, start 0x%X,"
" length 0x%X\n", i,
blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
cb->npe_addr, cb->size);
goto err;
}
for (j = 0; j < cb->size; j++)
npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
}
npe_start(npe);
if (!npe_running(npe))
print_npe(KERN_ERR, npe, "unable to start\n");
release_firmware(fw_entry);
return 0;
too_big:
print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
"memory: type %c, start 0x%X, length 0x%X\n", i,
blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
cb->npe_addr, cb->size);
err:
release_firmware(fw_entry);
return err;
}
struct npe *npe_request(unsigned id)
{
if (id < NPE_COUNT)
if (npe_tab[id].valid)
if (try_module_get(THIS_MODULE))
return &npe_tab[id];
return NULL;
}
void npe_release(struct npe *npe)
{
module_put(THIS_MODULE);
}
static int ixp4xx_npe_probe(struct platform_device *pdev)
{
int i, found = 0;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct resource *res;
struct regmap *rmap;
u32 val;
/* This system has only one syscon, so fetch it */
rmap = syscon_regmap_lookup_by_compatible("syscon");
if (IS_ERR(rmap))
return dev_err_probe(dev, PTR_ERR(rmap),
"failed to look up syscon\n");
for (i = 0; i < NPE_COUNT; i++) {
struct npe *npe = &npe_tab[i];
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
if (!res)
return -ENODEV;
val = cpu_ixp4xx_features(rmap);
if (!(val & (IXP4XX_FEATURE_RESET_NPEA << i))) {
dev_info(dev, "NPE%d at %pR not available\n",
i, res);
continue; /* NPE already disabled or not present */
}
npe->regs = devm_ioremap_resource(dev, res);
if (IS_ERR(npe->regs))
return PTR_ERR(npe->regs);
npe->rmap = rmap;
if (npe_reset(npe)) {
dev_info(dev, "NPE%d at %pR does not reset\n",
i, res);
continue;
}
npe->valid = 1;
dev_info(dev, "NPE%d at %pR registered\n", i, res);
found++;
}
if (!found)
return -ENODEV;
/* Spawn crypto subdevice if using device tree */
if (IS_ENABLED(CONFIG_OF) && np)
devm_of_platform_populate(dev);
return 0;
}
static int ixp4xx_npe_remove(struct platform_device *pdev)
{
int i;
for (i = 0; i < NPE_COUNT; i++)
if (npe_tab[i].regs) {
npe_reset(&npe_tab[i]);
}
return 0;
}
static const struct of_device_id ixp4xx_npe_of_match[] = {
{
.compatible = "intel,ixp4xx-network-processing-engine",
},
{},
};
static struct platform_driver ixp4xx_npe_driver = {
.driver = {
.name = "ixp4xx-npe",
.of_match_table = ixp4xx_npe_of_match,
},
.probe = ixp4xx_npe_probe,
.remove = ixp4xx_npe_remove,
};
module_platform_driver(ixp4xx_npe_driver);
MODULE_AUTHOR("Krzysztof Halasa");
MODULE_LICENSE("GPL v2");
MODULE_FIRMWARE(NPE_A_FIRMWARE);
MODULE_FIRMWARE(NPE_B_FIRMWARE);
MODULE_FIRMWARE(NPE_C_FIRMWARE);
EXPORT_SYMBOL(npe_names);
EXPORT_SYMBOL(npe_running);
EXPORT_SYMBOL(npe_request);
EXPORT_SYMBOL(npe_release);
EXPORT_SYMBOL(npe_load_firmware);
EXPORT_SYMBOL(npe_send_message);
EXPORT_SYMBOL(npe_recv_message);
EXPORT_SYMBOL(npe_send_recv_message);
|
linux-master
|
drivers/soc/ixp4xx/ixp4xx-npe.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Intel IXP4xx Queue Manager driver for Linux
*
* Copyright (C) 2007 Krzysztof Halasa <[email protected]>
*/
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/soc/ixp4xx/qmgr.h>
#include <linux/soc/ixp4xx/cpu.h>
static struct qmgr_regs __iomem *qmgr_regs;
static int qmgr_irq_1;
static int qmgr_irq_2;
static spinlock_t qmgr_lock;
static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
static void (*irq_handlers[QUEUES])(void *pdev);
static void *irq_pdevs[QUEUES];
#if DEBUG_QMGR
char qmgr_queue_descs[QUEUES][32];
#endif
void qmgr_put_entry(unsigned int queue, u32 val)
{
#if DEBUG_QMGR
BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
printk(KERN_DEBUG "Queue %s(%i) put %X\n",
qmgr_queue_descs[queue], queue, val);
#endif
__raw_writel(val, &qmgr_regs->acc[queue][0]);
}
u32 qmgr_get_entry(unsigned int queue)
{
u32 val;
val = __raw_readl(&qmgr_regs->acc[queue][0]);
#if DEBUG_QMGR
BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
printk(KERN_DEBUG "Queue %s(%i) get %X\n",
qmgr_queue_descs[queue], queue, val);
#endif
return val;
}
static int __qmgr_get_stat1(unsigned int queue)
{
return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
>> ((queue & 7) << 2)) & 0xF;
}
static int __qmgr_get_stat2(unsigned int queue)
{
BUG_ON(queue >= HALF_QUEUES);
return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
>> ((queue & 0xF) << 1)) & 0x3;
}
/**
* qmgr_stat_empty() - checks if a hardware queue is empty
* @queue: queue number
*
* Returns non-zero value if the queue is empty.
*/
int qmgr_stat_empty(unsigned int queue)
{
BUG_ON(queue >= HALF_QUEUES);
return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
}
/**
* qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
* @queue: queue number
*
* Returns non-zero value if the queue is below low watermark.
*/
int qmgr_stat_below_low_watermark(unsigned int queue)
{
if (queue >= HALF_QUEUES)
return (__raw_readl(&qmgr_regs->statne_h) >>
(queue - HALF_QUEUES)) & 0x01;
return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
}
/**
* qmgr_stat_full() - checks if a hardware queue is full
* @queue: queue number
*
* Returns non-zero value if the queue is full.
*/
int qmgr_stat_full(unsigned int queue)
{
if (queue >= HALF_QUEUES)
return (__raw_readl(&qmgr_regs->statf_h) >>
(queue - HALF_QUEUES)) & 0x01;
return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
}
/**
* qmgr_stat_overflow() - checks if a hardware queue experienced overflow
* @queue: queue number
*
* Returns non-zero value if the queue experienced overflow.
*/
int qmgr_stat_overflow(unsigned int queue)
{
return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW;
}
void qmgr_set_irq(unsigned int queue, int src,
void (*handler)(void *pdev), void *pdev)
{
unsigned long flags;
spin_lock_irqsave(&qmgr_lock, flags);
if (queue < HALF_QUEUES) {
u32 __iomem *reg;
int bit;
BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL);
reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */
bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
__raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit),
reg);
} else
/* IRQ source for queues 32-63 is fixed */
BUG_ON(src != QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY);
irq_handlers[queue] = handler;
irq_pdevs[queue] = pdev;
spin_unlock_irqrestore(&qmgr_lock, flags);
}
static irqreturn_t qmgr_irq1_a0(int irq, void *pdev)
{
int i, ret = 0;
u32 en_bitmap, src, stat;
/* ACK - it may clear any bits so don't rely on it */
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]);
en_bitmap = __raw_readl(&qmgr_regs->irqen[0]);
while (en_bitmap) {
i = __fls(en_bitmap); /* number of the last "low" queue */
en_bitmap &= ~BIT(i);
src = __raw_readl(&qmgr_regs->irqsrc[i >> 3]);
stat = __raw_readl(&qmgr_regs->stat1[i >> 3]);
if (src & 4) /* the IRQ condition is inverted */
stat = ~stat;
if (stat & BIT(src & 3)) {
irq_handlers[i](irq_pdevs[i]);
ret = IRQ_HANDLED;
}
}
return ret;
}
static irqreturn_t qmgr_irq2_a0(int irq, void *pdev)
{
int i, ret = 0;
u32 req_bitmap;
/* ACK - it may clear any bits so don't rely on it */
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]);
req_bitmap = __raw_readl(&qmgr_regs->irqen[1]) &
__raw_readl(&qmgr_regs->statne_h);
while (req_bitmap) {
i = __fls(req_bitmap); /* number of the last "high" queue */
req_bitmap &= ~BIT(i);
irq_handlers[HALF_QUEUES + i](irq_pdevs[HALF_QUEUES + i]);
ret = IRQ_HANDLED;
}
return ret;
}
static irqreturn_t qmgr_irq(int irq, void *pdev)
{
int i, half = (irq == qmgr_irq_1 ? 0 : 1);
u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]);
if (!req_bitmap)
return 0;
__raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */
while (req_bitmap) {
i = __fls(req_bitmap); /* number of the last queue */
req_bitmap &= ~BIT(i);
i += half * HALF_QUEUES;
irq_handlers[i](irq_pdevs[i]);
}
return IRQ_HANDLED;
}
void qmgr_enable_irq(unsigned int queue)
{
unsigned long flags;
int half = queue / 32;
u32 mask = 1 << (queue & (HALF_QUEUES - 1));
spin_lock_irqsave(&qmgr_lock, flags);
__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask,
&qmgr_regs->irqen[half]);
spin_unlock_irqrestore(&qmgr_lock, flags);
}
void qmgr_disable_irq(unsigned int queue)
{
unsigned long flags;
int half = queue / 32;
u32 mask = 1 << (queue & (HALF_QUEUES - 1));
spin_lock_irqsave(&qmgr_lock, flags);
__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask,
&qmgr_regs->irqen[half]);
__raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */
spin_unlock_irqrestore(&qmgr_lock, flags);
}
static inline void shift_mask(u32 *mask)
{
mask[3] = mask[3] << 1 | mask[2] >> 31;
mask[2] = mask[2] << 1 | mask[1] >> 31;
mask[1] = mask[1] << 1 | mask[0] >> 31;
mask[0] <<= 1;
}
#if DEBUG_QMGR
int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
unsigned int nearly_empty_watermark,
unsigned int nearly_full_watermark,
const char *desc_format, const char* name)
#else
int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
unsigned int nearly_empty_watermark,
unsigned int nearly_full_watermark)
#endif
{
u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
int err;
BUG_ON(queue >= QUEUES);
if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
return -EINVAL;
switch (len) {
case 16:
cfg = 0 << 24;
mask[0] = 0x1;
break;
case 32:
cfg = 1 << 24;
mask[0] = 0x3;
break;
case 64:
cfg = 2 << 24;
mask[0] = 0xF;
break;
case 128:
cfg = 3 << 24;
mask[0] = 0xFF;
break;
default:
return -EINVAL;
}
cfg |= nearly_empty_watermark << 26;
cfg |= nearly_full_watermark << 29;
len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
mask[1] = mask[2] = mask[3] = 0;
if (!try_module_get(THIS_MODULE))
return -ENODEV;
spin_lock_irq(&qmgr_lock);
if (__raw_readl(&qmgr_regs->sram[queue])) {
err = -EBUSY;
goto err;
}
while (1) {
if (!(used_sram_bitmap[0] & mask[0]) &&
!(used_sram_bitmap[1] & mask[1]) &&
!(used_sram_bitmap[2] & mask[2]) &&
!(used_sram_bitmap[3] & mask[3]))
break; /* found free space */
addr++;
shift_mask(mask);
if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
printk(KERN_ERR "qmgr: no free SRAM space for"
" queue %i\n", queue);
err = -ENOMEM;
goto err;
}
}
used_sram_bitmap[0] |= mask[0];
used_sram_bitmap[1] |= mask[1];
used_sram_bitmap[2] |= mask[2];
used_sram_bitmap[3] |= mask[3];
__raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
#if DEBUG_QMGR
snprintf(qmgr_queue_descs[queue], sizeof(qmgr_queue_descs[0]),
desc_format, name);
printk(KERN_DEBUG "qmgr: requested queue %s(%i) addr = 0x%02X\n",
qmgr_queue_descs[queue], queue, addr);
#endif
spin_unlock_irq(&qmgr_lock);
return 0;
err:
spin_unlock_irq(&qmgr_lock);
module_put(THIS_MODULE);
return err;
}
void qmgr_release_queue(unsigned int queue)
{
u32 cfg, addr, mask[4];
BUG_ON(queue >= QUEUES); /* not in valid range */
spin_lock_irq(&qmgr_lock);
cfg = __raw_readl(&qmgr_regs->sram[queue]);
addr = (cfg >> 14) & 0xFF;
BUG_ON(!addr); /* not requested */
switch ((cfg >> 24) & 3) {
case 0: mask[0] = 0x1; break;
case 1: mask[0] = 0x3; break;
case 2: mask[0] = 0xF; break;
case 3: mask[0] = 0xFF; break;
}
mask[1] = mask[2] = mask[3] = 0;
while (addr--)
shift_mask(mask);
#if DEBUG_QMGR
printk(KERN_DEBUG "qmgr: releasing queue %s(%i)\n",
qmgr_queue_descs[queue], queue);
qmgr_queue_descs[queue][0] = '\x0';
#endif
while ((addr = qmgr_get_entry(queue)))
printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n",
queue, addr);
__raw_writel(0, &qmgr_regs->sram[queue]);
used_sram_bitmap[0] &= ~mask[0];
used_sram_bitmap[1] &= ~mask[1];
used_sram_bitmap[2] &= ~mask[2];
used_sram_bitmap[3] &= ~mask[3];
irq_handlers[queue] = NULL; /* catch IRQ bugs */
spin_unlock_irq(&qmgr_lock);
module_put(THIS_MODULE);
}
static int ixp4xx_qmgr_probe(struct platform_device *pdev)
{
int i, err;
irq_handler_t handler1, handler2;
struct device *dev = &pdev->dev;
struct resource *res;
int irq1, irq2;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
qmgr_regs = devm_ioremap_resource(dev, res);
if (IS_ERR(qmgr_regs))
return PTR_ERR(qmgr_regs);
irq1 = platform_get_irq(pdev, 0);
if (irq1 <= 0)
return irq1 ? irq1 : -EINVAL;
qmgr_irq_1 = irq1;
irq2 = platform_get_irq(pdev, 1);
if (irq2 <= 0)
return irq2 ? irq2 : -EINVAL;
qmgr_irq_2 = irq2;
/* reset qmgr registers */
for (i = 0; i < 4; i++) {
__raw_writel(0x33333333, &qmgr_regs->stat1[i]);
__raw_writel(0, &qmgr_regs->irqsrc[i]);
}
for (i = 0; i < 2; i++) {
__raw_writel(0, &qmgr_regs->stat2[i]);
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
__raw_writel(0, &qmgr_regs->irqen[i]);
}
__raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h);
__raw_writel(0, &qmgr_regs->statf_h);
for (i = 0; i < QUEUES; i++)
__raw_writel(0, &qmgr_regs->sram[i]);
if (cpu_is_ixp42x_rev_a0()) {
handler1 = qmgr_irq1_a0;
handler2 = qmgr_irq2_a0;
} else
handler1 = handler2 = qmgr_irq;
err = devm_request_irq(dev, irq1, handler1, 0, "IXP4xx Queue Manager",
NULL);
if (err) {
dev_err(dev, "failed to request IRQ%i (%i)\n",
irq1, err);
return err;
}
err = devm_request_irq(dev, irq2, handler2, 0, "IXP4xx Queue Manager",
NULL);
if (err) {
dev_err(dev, "failed to request IRQ%i (%i)\n",
irq2, err);
return err;
}
used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
spin_lock_init(&qmgr_lock);
dev_info(dev, "IXP4xx Queue Manager initialized.\n");
return 0;
}
static int ixp4xx_qmgr_remove(struct platform_device *pdev)
{
synchronize_irq(qmgr_irq_1);
synchronize_irq(qmgr_irq_2);
return 0;
}
static const struct of_device_id ixp4xx_qmgr_of_match[] = {
{
.compatible = "intel,ixp4xx-ahb-queue-manager",
},
{},
};
static struct platform_driver ixp4xx_qmgr_driver = {
.driver = {
.name = "ixp4xx-qmgr",
.of_match_table = ixp4xx_qmgr_of_match,
},
.probe = ixp4xx_qmgr_probe,
.remove = ixp4xx_qmgr_remove,
};
module_platform_driver(ixp4xx_qmgr_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Krzysztof Halasa");
EXPORT_SYMBOL(qmgr_put_entry);
EXPORT_SYMBOL(qmgr_get_entry);
EXPORT_SYMBOL(qmgr_stat_empty);
EXPORT_SYMBOL(qmgr_stat_below_low_watermark);
EXPORT_SYMBOL(qmgr_stat_full);
EXPORT_SYMBOL(qmgr_stat_overflow);
EXPORT_SYMBOL(qmgr_set_irq);
EXPORT_SYMBOL(qmgr_enable_irq);
EXPORT_SYMBOL(qmgr_disable_irq);
#if DEBUG_QMGR
EXPORT_SYMBOL(qmgr_queue_descs);
EXPORT_SYMBOL(qmgr_request_queue);
#else
EXPORT_SYMBOL(__qmgr_request_queue);
#endif
EXPORT_SYMBOL(qmgr_release_queue);
|
linux-master
|
drivers/soc/ixp4xx/ixp4xx-qmgr.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* The Huawei Cache Coherence System (HCCS) is a multi-chip interconnection
* bus protocol.
*
* Copyright (c) 2023 Hisilicon Limited.
* Author: Huisong Li <[email protected]>
*
* HCCS driver for Kunpeng SoC provides the following features:
* - Retrieve the following information about each port:
* - port type
* - lane mode
* - enable
* - current lane mode
* - link finite state machine
* - lane mask
* - CRC error count
*
* - Retrieve the following information about all the ports on the chip or
* the die:
* - if all enabled ports are in linked
* - if all linked ports are in full lane
* - CRC error count sum
*/
#include <linux/acpi.h>
#include <linux/iopoll.h>
#include <linux/platform_device.h>
#include <linux/sysfs.h>
#include <acpi/pcc.h>
#include "kunpeng_hccs.h"
/* PCC defines */
#define HCCS_PCC_SIGNATURE_MASK 0x50434300
#define HCCS_PCC_STATUS_CMD_COMPLETE BIT(0)
/*
* Arbitrary retries in case the remote processor is slow to respond
* to PCC commands
*/
#define HCCS_PCC_CMD_WAIT_RETRIES_NUM 500ULL
#define HCCS_POLL_STATUS_TIME_INTERVAL_US 3
static struct hccs_port_info *kobj_to_port_info(struct kobject *k)
{
return container_of(k, struct hccs_port_info, kobj);
}
static struct hccs_die_info *kobj_to_die_info(struct kobject *k)
{
return container_of(k, struct hccs_die_info, kobj);
}
static struct hccs_chip_info *kobj_to_chip_info(struct kobject *k)
{
return container_of(k, struct hccs_chip_info, kobj);
}
struct hccs_register_ctx {
struct device *dev;
u8 chan_id;
int err;
};
static acpi_status hccs_get_register_cb(struct acpi_resource *ares,
void *context)
{
struct acpi_resource_generic_register *reg;
struct hccs_register_ctx *ctx = context;
if (ares->type != ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
return AE_OK;
reg = &ares->data.generic_reg;
if (reg->space_id != ACPI_ADR_SPACE_PLATFORM_COMM) {
dev_err(ctx->dev, "Bad register resource.\n");
ctx->err = -EINVAL;
return AE_ERROR;
}
ctx->chan_id = reg->access_size;
return AE_OK;
}
static int hccs_get_pcc_chan_id(struct hccs_dev *hdev)
{
acpi_handle handle = ACPI_HANDLE(hdev->dev);
struct hccs_register_ctx ctx = {0};
acpi_status status;
if (!acpi_has_method(handle, METHOD_NAME__CRS))
return -ENODEV;
ctx.dev = hdev->dev;
status = acpi_walk_resources(handle, METHOD_NAME__CRS,
hccs_get_register_cb, &ctx);
if (ACPI_FAILURE(status))
return ctx.err;
hdev->chan_id = ctx.chan_id;
return 0;
}
static void hccs_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
{
if (ret < 0)
pr_debug("TX did not complete: CMD sent:0x%x, ret:%d\n",
*(u8 *)msg, ret);
else
pr_debug("TX completed. CMD sent:0x%x, ret:%d\n",
*(u8 *)msg, ret);
}
static void hccs_unregister_pcc_channel(struct hccs_dev *hdev)
{
struct hccs_mbox_client_info *cl_info = &hdev->cl_info;
if (cl_info->pcc_comm_addr)
iounmap(cl_info->pcc_comm_addr);
pcc_mbox_free_channel(hdev->cl_info.pcc_chan);
}
static int hccs_register_pcc_channel(struct hccs_dev *hdev)
{
struct hccs_mbox_client_info *cl_info = &hdev->cl_info;
struct mbox_client *cl = &cl_info->client;
struct pcc_mbox_chan *pcc_chan;
struct device *dev = hdev->dev;
int rc;
cl->dev = dev;
cl->tx_block = false;
cl->knows_txdone = true;
cl->tx_done = hccs_chan_tx_done;
pcc_chan = pcc_mbox_request_channel(cl, hdev->chan_id);
if (IS_ERR(pcc_chan)) {
dev_err(dev, "PPC channel request failed.\n");
rc = -ENODEV;
goto out;
}
cl_info->pcc_chan = pcc_chan;
cl_info->mbox_chan = pcc_chan->mchan;
/*
* pcc_chan->latency is just a nominal value. In reality the remote
* processor could be much slower to reply. So add an arbitrary amount
* of wait on top of nominal.
*/
cl_info->deadline_us =
HCCS_PCC_CMD_WAIT_RETRIES_NUM * pcc_chan->latency;
if (cl_info->mbox_chan->mbox->txdone_irq) {
dev_err(dev, "PCC IRQ in PCCT is enabled.\n");
rc = -EINVAL;
goto err_mbx_channel_free;
}
if (pcc_chan->shmem_base_addr) {
cl_info->pcc_comm_addr = ioremap(pcc_chan->shmem_base_addr,
pcc_chan->shmem_size);
if (!cl_info->pcc_comm_addr) {
dev_err(dev, "Failed to ioremap PCC communication region for channel-%d.\n",
hdev->chan_id);
rc = -ENOMEM;
goto err_mbx_channel_free;
}
}
return 0;
err_mbx_channel_free:
pcc_mbox_free_channel(cl_info->pcc_chan);
out:
return rc;
}
static int hccs_check_chan_cmd_complete(struct hccs_dev *hdev)
{
struct hccs_mbox_client_info *cl_info = &hdev->cl_info;
struct acpi_pcct_shared_memory __iomem *comm_base =
cl_info->pcc_comm_addr;
u16 status;
int ret;
/*
* Poll PCC status register every 3us(delay_us) for maximum of
* deadline_us(timeout_us) until PCC command complete bit is set(cond)
*/
ret = readw_poll_timeout(&comm_base->status, status,
status & HCCS_PCC_STATUS_CMD_COMPLETE,
HCCS_POLL_STATUS_TIME_INTERVAL_US,
cl_info->deadline_us);
if (unlikely(ret))
dev_err(hdev->dev, "poll PCC status failed, ret = %d.\n", ret);
return ret;
}
static int hccs_pcc_cmd_send(struct hccs_dev *hdev, u8 cmd,
struct hccs_desc *desc)
{
struct hccs_mbox_client_info *cl_info = &hdev->cl_info;
void __iomem *comm_space = cl_info->pcc_comm_addr +
sizeof(struct acpi_pcct_shared_memory);
struct hccs_fw_inner_head *fw_inner_head;
struct acpi_pcct_shared_memory tmp = {0};
u16 comm_space_size;
int ret;
/* Write signature for this subspace */
tmp.signature = HCCS_PCC_SIGNATURE_MASK | hdev->chan_id;
/* Write to the shared command region */
tmp.command = cmd;
/* Clear cmd complete bit */
tmp.status = 0;
memcpy_toio(cl_info->pcc_comm_addr, (void *)&tmp,
sizeof(struct acpi_pcct_shared_memory));
/* Copy the message to the PCC comm space */
comm_space_size = HCCS_PCC_SHARE_MEM_BYTES -
sizeof(struct acpi_pcct_shared_memory);
memcpy_toio(comm_space, (void *)desc, comm_space_size);
/* Ring doorbell */
ret = mbox_send_message(cl_info->mbox_chan, &cmd);
if (ret < 0) {
dev_err(hdev->dev, "Send PCC mbox message failed, ret = %d.\n",
ret);
goto end;
}
/* Wait for completion */
ret = hccs_check_chan_cmd_complete(hdev);
if (ret)
goto end;
/* Copy response data */
memcpy_fromio((void *)desc, comm_space, comm_space_size);
fw_inner_head = &desc->rsp.fw_inner_head;
if (fw_inner_head->retStatus) {
dev_err(hdev->dev, "Execute PCC command failed, error code = %u.\n",
fw_inner_head->retStatus);
ret = -EIO;
}
end:
mbox_client_txdone(cl_info->mbox_chan, ret);
return ret;
}
static void hccs_init_req_desc(struct hccs_desc *desc)
{
struct hccs_req_desc *req = &desc->req;
memset(desc, 0, sizeof(*desc));
req->req_head.module_code = HCCS_SERDES_MODULE_CODE;
}
static int hccs_get_dev_caps(struct hccs_dev *hdev)
{
struct hccs_desc desc;
int ret;
hccs_init_req_desc(&desc);
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DEV_CAP, &desc);
if (ret) {
dev_err(hdev->dev, "Get device capabilities failed, ret = %d.\n",
ret);
return ret;
}
memcpy(&hdev->caps, desc.rsp.data, sizeof(hdev->caps));
return 0;
}
static int hccs_query_chip_num_on_platform(struct hccs_dev *hdev)
{
struct hccs_desc desc;
int ret;
hccs_init_req_desc(&desc);
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_CHIP_NUM, &desc);
if (ret) {
dev_err(hdev->dev, "query system chip number failed, ret = %d.\n",
ret);
return ret;
}
hdev->chip_num = *((u8 *)&desc.rsp.data);
if (!hdev->chip_num) {
dev_err(hdev->dev, "chip num obtained from firmware is zero.\n");
return -EINVAL;
}
return 0;
}
static int hccs_get_chip_info(struct hccs_dev *hdev,
struct hccs_chip_info *chip)
{
struct hccs_die_num_req_param *req_param;
struct hccs_desc desc;
int ret;
hccs_init_req_desc(&desc);
req_param = (struct hccs_die_num_req_param *)desc.req.data;
req_param->chip_id = chip->chip_id;
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_NUM, &desc);
if (ret)
return ret;
chip->die_num = *((u8 *)&desc.rsp.data);
return 0;
}
static int hccs_query_chip_info_on_platform(struct hccs_dev *hdev)
{
struct hccs_chip_info *chip;
int ret;
u8 idx;
ret = hccs_query_chip_num_on_platform(hdev);
if (ret) {
dev_err(hdev->dev, "query chip number on platform failed, ret = %d.\n",
ret);
return ret;
}
hdev->chips = devm_kzalloc(hdev->dev,
hdev->chip_num * sizeof(struct hccs_chip_info),
GFP_KERNEL);
if (!hdev->chips) {
dev_err(hdev->dev, "allocate all chips memory failed.\n");
return -ENOMEM;
}
for (idx = 0; idx < hdev->chip_num; idx++) {
chip = &hdev->chips[idx];
chip->chip_id = idx;
ret = hccs_get_chip_info(hdev, chip);
if (ret) {
dev_err(hdev->dev, "get chip%u info failed, ret = %d.\n",
idx, ret);
return ret;
}
chip->hdev = hdev;
}
return 0;
}
static int hccs_query_die_info_on_chip(struct hccs_dev *hdev, u8 chip_id,
u8 die_idx, struct hccs_die_info *die)
{
struct hccs_die_info_req_param *req_param;
struct hccs_die_info_rsp_data *rsp_data;
struct hccs_desc desc;
int ret;
hccs_init_req_desc(&desc);
req_param = (struct hccs_die_info_req_param *)desc.req.data;
req_param->chip_id = chip_id;
req_param->die_idx = die_idx;
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_INFO, &desc);
if (ret)
return ret;
rsp_data = (struct hccs_die_info_rsp_data *)desc.rsp.data;
die->die_id = rsp_data->die_id;
die->port_num = rsp_data->port_num;
die->min_port_id = rsp_data->min_port_id;
die->max_port_id = rsp_data->max_port_id;
if (die->min_port_id > die->max_port_id) {
dev_err(hdev->dev, "min port id(%u) > max port id(%u) on die_idx(%u).\n",
die->min_port_id, die->max_port_id, die_idx);
return -EINVAL;
}
if (die->max_port_id > HCCS_DIE_MAX_PORT_ID) {
dev_err(hdev->dev, "max port id(%u) on die_idx(%u) is too big.\n",
die->max_port_id, die_idx);
return -EINVAL;
}
return 0;
}
static int hccs_query_all_die_info_on_platform(struct hccs_dev *hdev)
{
struct device *dev = hdev->dev;
struct hccs_chip_info *chip;
struct hccs_die_info *die;
u8 i, j;
int ret;
for (i = 0; i < hdev->chip_num; i++) {
chip = &hdev->chips[i];
if (!chip->die_num)
continue;
chip->dies = devm_kzalloc(hdev->dev,
chip->die_num * sizeof(struct hccs_die_info),
GFP_KERNEL);
if (!chip->dies) {
dev_err(dev, "allocate all dies memory on chip%u failed.\n",
i);
return -ENOMEM;
}
for (j = 0; j < chip->die_num; j++) {
die = &chip->dies[j];
ret = hccs_query_die_info_on_chip(hdev, i, j, die);
if (ret) {
dev_err(dev, "get die idx (%u) info on chip%u failed, ret = %d.\n",
j, i, ret);
return ret;
}
die->chip = chip;
}
}
return 0;
}
static int hccs_get_bd_info(struct hccs_dev *hdev, u8 opcode,
struct hccs_desc *desc,
void *buf, size_t buf_len,
struct hccs_rsp_head *rsp_head)
{
struct hccs_rsp_head *head;
struct hccs_rsp_desc *rsp;
int ret;
ret = hccs_pcc_cmd_send(hdev, opcode, desc);
if (ret)
return ret;
rsp = &desc->rsp;
head = &rsp->rsp_head;
if (head->data_len > buf_len) {
dev_err(hdev->dev,
"buffer overflow (buf_len = %zu, data_len = %u)!\n",
buf_len, head->data_len);
return -ENOMEM;
}
memcpy(buf, rsp->data, head->data_len);
*rsp_head = *head;
return 0;
}
static int hccs_get_all_port_attr(struct hccs_dev *hdev,
struct hccs_die_info *die,
struct hccs_port_attr *attrs, u16 size)
{
struct hccs_die_comm_req_param *req_param;
struct hccs_req_head *req_head;
struct hccs_rsp_head rsp_head;
struct hccs_desc desc;
size_t left_buf_len;
u32 data_len = 0;
u8 start_id;
u8 *buf;
int ret;
buf = (u8 *)attrs;
left_buf_len = sizeof(struct hccs_port_attr) * size;
start_id = die->min_port_id;
while (start_id <= die->max_port_id) {
hccs_init_req_desc(&desc);
req_head = &desc.req.req_head;
req_head->start_id = start_id;
req_param = (struct hccs_die_comm_req_param *)desc.req.data;
req_param->chip_id = die->chip->chip_id;
req_param->die_id = die->die_id;
ret = hccs_get_bd_info(hdev, HCCS_GET_DIE_PORT_INFO, &desc,
buf + data_len, left_buf_len, &rsp_head);
if (ret) {
dev_err(hdev->dev,
"get the information of port%u on die%u failed, ret = %d.\n",
start_id, die->die_id, ret);
return ret;
}
data_len += rsp_head.data_len;
left_buf_len -= rsp_head.data_len;
if (unlikely(rsp_head.next_id <= start_id)) {
dev_err(hdev->dev,
"next port id (%u) is not greater than last start id (%u) on die%u.\n",
rsp_head.next_id, start_id, die->die_id);
return -EINVAL;
}
start_id = rsp_head.next_id;
}
return 0;
}
static int hccs_get_all_port_info_on_die(struct hccs_dev *hdev,
struct hccs_die_info *die)
{
struct hccs_port_attr *attrs;
struct hccs_port_info *port;
int ret;
u8 i;
attrs = kcalloc(die->port_num, sizeof(struct hccs_port_attr),
GFP_KERNEL);
if (!attrs)
return -ENOMEM;
ret = hccs_get_all_port_attr(hdev, die, attrs, die->port_num);
if (ret)
goto out;
for (i = 0; i < die->port_num; i++) {
port = &die->ports[i];
port->port_id = attrs[i].port_id;
port->port_type = attrs[i].port_type;
port->lane_mode = attrs[i].lane_mode;
port->enable = attrs[i].enable;
port->die = die;
}
out:
kfree(attrs);
return ret;
}
static int hccs_query_all_port_info_on_platform(struct hccs_dev *hdev)
{
struct device *dev = hdev->dev;
struct hccs_chip_info *chip;
struct hccs_die_info *die;
u8 i, j;
int ret;
for (i = 0; i < hdev->chip_num; i++) {
chip = &hdev->chips[i];
for (j = 0; j < chip->die_num; j++) {
die = &chip->dies[j];
if (!die->port_num)
continue;
die->ports = devm_kzalloc(dev,
die->port_num * sizeof(struct hccs_port_info),
GFP_KERNEL);
if (!die->ports) {
dev_err(dev, "allocate ports memory on chip%u/die%u failed.\n",
i, die->die_id);
return -ENOMEM;
}
ret = hccs_get_all_port_info_on_die(hdev, die);
if (ret) {
dev_err(dev, "get all port info on chip%u/die%u failed, ret = %d.\n",
i, die->die_id, ret);
return ret;
}
}
}
return 0;
}
static int hccs_get_hw_info(struct hccs_dev *hdev)
{
int ret;
ret = hccs_query_chip_info_on_platform(hdev);
if (ret) {
dev_err(hdev->dev, "query chip info on platform failed, ret = %d.\n",
ret);
return ret;
}
ret = hccs_query_all_die_info_on_platform(hdev);
if (ret) {
dev_err(hdev->dev, "query all die info on platform failed, ret = %d.\n",
ret);
return ret;
}
ret = hccs_query_all_port_info_on_platform(hdev);
if (ret) {
dev_err(hdev->dev, "query all port info on platform failed, ret = %d.\n",
ret);
return ret;
}
return 0;
}
static int hccs_query_port_link_status(struct hccs_dev *hdev,
const struct hccs_port_info *port,
struct hccs_link_status *link_status)
{
const struct hccs_die_info *die = port->die;
const struct hccs_chip_info *chip = die->chip;
struct hccs_port_comm_req_param *req_param;
struct hccs_desc desc;
int ret;
hccs_init_req_desc(&desc);
req_param = (struct hccs_port_comm_req_param *)desc.req.data;
req_param->chip_id = chip->chip_id;
req_param->die_id = die->die_id;
req_param->port_id = port->port_id;
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_PORT_LINK_STATUS, &desc);
if (ret) {
dev_err(hdev->dev,
"get port link status info failed, ret = %d.\n", ret);
return ret;
}
*link_status = *((struct hccs_link_status *)desc.rsp.data);
return 0;
}
static int hccs_query_port_crc_err_cnt(struct hccs_dev *hdev,
const struct hccs_port_info *port,
u64 *crc_err_cnt)
{
const struct hccs_die_info *die = port->die;
const struct hccs_chip_info *chip = die->chip;
struct hccs_port_comm_req_param *req_param;
struct hccs_desc desc;
int ret;
hccs_init_req_desc(&desc);
req_param = (struct hccs_port_comm_req_param *)desc.req.data;
req_param->chip_id = chip->chip_id;
req_param->die_id = die->die_id;
req_param->port_id = port->port_id;
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_PORT_CRC_ERR_CNT, &desc);
if (ret) {
dev_err(hdev->dev,
"get port crc error count failed, ret = %d.\n", ret);
return ret;
}
memcpy(crc_err_cnt, &desc.rsp.data, sizeof(u64));
return 0;
}
static int hccs_get_die_all_link_status(struct hccs_dev *hdev,
const struct hccs_die_info *die,
u8 *all_linked)
{
struct hccs_die_comm_req_param *req_param;
struct hccs_desc desc;
int ret;
if (die->port_num == 0) {
*all_linked = 1;
return 0;
}
hccs_init_req_desc(&desc);
req_param = (struct hccs_die_comm_req_param *)desc.req.data;
req_param->chip_id = die->chip->chip_id;
req_param->die_id = die->die_id;
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_PORTS_LINK_STA, &desc);
if (ret) {
dev_err(hdev->dev,
"get link status of all ports failed on die%u, ret = %d.\n",
die->die_id, ret);
return ret;
}
*all_linked = *((u8 *)&desc.rsp.data);
return 0;
}
static int hccs_get_die_all_port_lane_status(struct hccs_dev *hdev,
const struct hccs_die_info *die,
u8 *full_lane)
{
struct hccs_die_comm_req_param *req_param;
struct hccs_desc desc;
int ret;
if (die->port_num == 0) {
*full_lane = 1;
return 0;
}
hccs_init_req_desc(&desc);
req_param = (struct hccs_die_comm_req_param *)desc.req.data;
req_param->chip_id = die->chip->chip_id;
req_param->die_id = die->die_id;
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_PORTS_LANE_STA, &desc);
if (ret) {
dev_err(hdev->dev, "get lane status of all ports failed on die%u, ret = %d.\n",
die->die_id, ret);
return ret;
}
*full_lane = *((u8 *)&desc.rsp.data);
return 0;
}
static int hccs_get_die_total_crc_err_cnt(struct hccs_dev *hdev,
const struct hccs_die_info *die,
u64 *total_crc_err_cnt)
{
struct hccs_die_comm_req_param *req_param;
struct hccs_desc desc;
int ret;
if (die->port_num == 0) {
*total_crc_err_cnt = 0;
return 0;
}
hccs_init_req_desc(&desc);
req_param = (struct hccs_die_comm_req_param *)desc.req.data;
req_param->chip_id = die->chip->chip_id;
req_param->die_id = die->die_id;
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_PORTS_CRC_ERR_CNT, &desc);
if (ret) {
dev_err(hdev->dev, "get crc error count sum failed on die%u, ret = %d.\n",
die->die_id, ret);
return ret;
}
memcpy(total_crc_err_cnt, &desc.rsp.data, sizeof(u64));
return 0;
}
static ssize_t hccs_show(struct kobject *k, struct attribute *attr, char *buf)
{
struct kobj_attribute *kobj_attr;
kobj_attr = container_of(attr, struct kobj_attribute, attr);
return kobj_attr->show(k, kobj_attr, buf);
}
static const struct sysfs_ops hccs_comm_ops = {
.show = hccs_show,
};
static ssize_t type_show(struct kobject *kobj, struct kobj_attribute *attr,
char *buf)
{
const struct hccs_port_info *port = kobj_to_port_info(kobj);
return sysfs_emit(buf, "HCCS-v%u\n", port->port_type);
}
static struct kobj_attribute hccs_type_attr = __ATTR_RO(type);
static ssize_t lane_mode_show(struct kobject *kobj, struct kobj_attribute *attr,
char *buf)
{
const struct hccs_port_info *port = kobj_to_port_info(kobj);
return sysfs_emit(buf, "x%u\n", port->lane_mode);
}
static struct kobj_attribute lane_mode_attr = __ATTR_RO(lane_mode);
static ssize_t enable_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
const struct hccs_port_info *port = kobj_to_port_info(kobj);
return sysfs_emit(buf, "%u\n", port->enable);
}
static struct kobj_attribute port_enable_attr = __ATTR_RO(enable);
static ssize_t cur_lane_num_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
const struct hccs_port_info *port = kobj_to_port_info(kobj);
struct hccs_dev *hdev = port->die->chip->hdev;
struct hccs_link_status link_status = {0};
int ret;
mutex_lock(&hdev->lock);
ret = hccs_query_port_link_status(hdev, port, &link_status);
mutex_unlock(&hdev->lock);
if (ret)
return ret;
return sysfs_emit(buf, "%u\n", link_status.lane_num);
}
static struct kobj_attribute cur_lane_num_attr = __ATTR_RO(cur_lane_num);
static ssize_t link_fsm_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
const struct hccs_port_info *port = kobj_to_port_info(kobj);
struct hccs_dev *hdev = port->die->chip->hdev;
struct hccs_link_status link_status = {0};
const struct {
u8 link_fsm;
char *str;
} link_fsm_map[] = {
{HCCS_PORT_RESET, "reset"},
{HCCS_PORT_SETUP, "setup"},
{HCCS_PORT_CONFIG, "config"},
{HCCS_PORT_READY, "link-up"},
};
const char *link_fsm_str = "unknown";
size_t i;
int ret;
mutex_lock(&hdev->lock);
ret = hccs_query_port_link_status(hdev, port, &link_status);
mutex_unlock(&hdev->lock);
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(link_fsm_map); i++) {
if (link_fsm_map[i].link_fsm == link_status.link_fsm) {
link_fsm_str = link_fsm_map[i].str;
break;
}
}
return sysfs_emit(buf, "%s\n", link_fsm_str);
}
static struct kobj_attribute link_fsm_attr = __ATTR_RO(link_fsm);
static ssize_t lane_mask_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
const struct hccs_port_info *port = kobj_to_port_info(kobj);
struct hccs_dev *hdev = port->die->chip->hdev;
struct hccs_link_status link_status = {0};
int ret;
mutex_lock(&hdev->lock);
ret = hccs_query_port_link_status(hdev, port, &link_status);
mutex_unlock(&hdev->lock);
if (ret)
return ret;
return sysfs_emit(buf, "0x%x\n", link_status.lane_mask);
}
static struct kobj_attribute lane_mask_attr = __ATTR_RO(lane_mask);
static ssize_t crc_err_cnt_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
const struct hccs_port_info *port = kobj_to_port_info(kobj);
struct hccs_dev *hdev = port->die->chip->hdev;
u64 crc_err_cnt;
int ret;
mutex_lock(&hdev->lock);
ret = hccs_query_port_crc_err_cnt(hdev, port, &crc_err_cnt);
mutex_unlock(&hdev->lock);
if (ret)
return ret;
return sysfs_emit(buf, "%llu\n", crc_err_cnt);
}
static struct kobj_attribute crc_err_cnt_attr = __ATTR_RO(crc_err_cnt);
static struct attribute *hccs_port_default_attrs[] = {
&hccs_type_attr.attr,
&lane_mode_attr.attr,
&port_enable_attr.attr,
&cur_lane_num_attr.attr,
&link_fsm_attr.attr,
&lane_mask_attr.attr,
&crc_err_cnt_attr.attr,
NULL,
};
ATTRIBUTE_GROUPS(hccs_port_default);
static const struct kobj_type hccs_port_type = {
.sysfs_ops = &hccs_comm_ops,
.default_groups = hccs_port_default_groups,
};
static ssize_t all_linked_on_die_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
const struct hccs_die_info *die = kobj_to_die_info(kobj);
struct hccs_dev *hdev = die->chip->hdev;
u8 all_linked;
int ret;
mutex_lock(&hdev->lock);
ret = hccs_get_die_all_link_status(hdev, die, &all_linked);
mutex_unlock(&hdev->lock);
if (ret)
return ret;
return sysfs_emit(buf, "%u\n", all_linked);
}
static struct kobj_attribute all_linked_on_die_attr =
__ATTR(all_linked, 0444, all_linked_on_die_show, NULL);
static ssize_t linked_full_lane_on_die_show(struct kobject *kobj,
struct kobj_attribute *attr,
char *buf)
{
const struct hccs_die_info *die = kobj_to_die_info(kobj);
struct hccs_dev *hdev = die->chip->hdev;
u8 full_lane;
int ret;
mutex_lock(&hdev->lock);
ret = hccs_get_die_all_port_lane_status(hdev, die, &full_lane);
mutex_unlock(&hdev->lock);
if (ret)
return ret;
return sysfs_emit(buf, "%u\n", full_lane);
}
static struct kobj_attribute linked_full_lane_on_die_attr =
__ATTR(linked_full_lane, 0444, linked_full_lane_on_die_show, NULL);
static ssize_t crc_err_cnt_sum_on_die_show(struct kobject *kobj,
struct kobj_attribute *attr,
char *buf)
{
const struct hccs_die_info *die = kobj_to_die_info(kobj);
struct hccs_dev *hdev = die->chip->hdev;
u64 total_crc_err_cnt;
int ret;
mutex_lock(&hdev->lock);
ret = hccs_get_die_total_crc_err_cnt(hdev, die, &total_crc_err_cnt);
mutex_unlock(&hdev->lock);
if (ret)
return ret;
return sysfs_emit(buf, "%llu\n", total_crc_err_cnt);
}
static struct kobj_attribute crc_err_cnt_sum_on_die_attr =
__ATTR(crc_err_cnt, 0444, crc_err_cnt_sum_on_die_show, NULL);
static struct attribute *hccs_die_default_attrs[] = {
&all_linked_on_die_attr.attr,
&linked_full_lane_on_die_attr.attr,
&crc_err_cnt_sum_on_die_attr.attr,
NULL,
};
ATTRIBUTE_GROUPS(hccs_die_default);
static const struct kobj_type hccs_die_type = {
.sysfs_ops = &hccs_comm_ops,
.default_groups = hccs_die_default_groups,
};
static ssize_t all_linked_on_chip_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
const struct hccs_chip_info *chip = kobj_to_chip_info(kobj);
struct hccs_dev *hdev = chip->hdev;
const struct hccs_die_info *die;
u8 all_linked = 1;
u8 i, tmp;
int ret;
mutex_lock(&hdev->lock);
for (i = 0; i < chip->die_num; i++) {
die = &chip->dies[i];
ret = hccs_get_die_all_link_status(hdev, die, &tmp);
if (ret) {
mutex_unlock(&hdev->lock);
return ret;
}
if (tmp != all_linked) {
all_linked = 0;
break;
}
}
mutex_unlock(&hdev->lock);
return sysfs_emit(buf, "%u\n", all_linked);
}
static struct kobj_attribute all_linked_on_chip_attr =
__ATTR(all_linked, 0444, all_linked_on_chip_show, NULL);
static ssize_t linked_full_lane_on_chip_show(struct kobject *kobj,
struct kobj_attribute *attr,
char *buf)
{
const struct hccs_chip_info *chip = kobj_to_chip_info(kobj);
struct hccs_dev *hdev = chip->hdev;
const struct hccs_die_info *die;
u8 full_lane = 1;
u8 i, tmp;
int ret;
mutex_lock(&hdev->lock);
for (i = 0; i < chip->die_num; i++) {
die = &chip->dies[i];
ret = hccs_get_die_all_port_lane_status(hdev, die, &tmp);
if (ret) {
mutex_unlock(&hdev->lock);
return ret;
}
if (tmp != full_lane) {
full_lane = 0;
break;
}
}
mutex_unlock(&hdev->lock);
return sysfs_emit(buf, "%u\n", full_lane);
}
static struct kobj_attribute linked_full_lane_on_chip_attr =
__ATTR(linked_full_lane, 0444, linked_full_lane_on_chip_show, NULL);
static ssize_t crc_err_cnt_sum_on_chip_show(struct kobject *kobj,
struct kobj_attribute *attr,
char *buf)
{
const struct hccs_chip_info *chip = kobj_to_chip_info(kobj);
u64 crc_err_cnt, total_crc_err_cnt = 0;
struct hccs_dev *hdev = chip->hdev;
const struct hccs_die_info *die;
int ret;
u16 i;
mutex_lock(&hdev->lock);
for (i = 0; i < chip->die_num; i++) {
die = &chip->dies[i];
ret = hccs_get_die_total_crc_err_cnt(hdev, die, &crc_err_cnt);
if (ret) {
mutex_unlock(&hdev->lock);
return ret;
}
total_crc_err_cnt += crc_err_cnt;
}
mutex_unlock(&hdev->lock);
return sysfs_emit(buf, "%llu\n", total_crc_err_cnt);
}
static struct kobj_attribute crc_err_cnt_sum_on_chip_attr =
__ATTR(crc_err_cnt, 0444, crc_err_cnt_sum_on_chip_show, NULL);
static struct attribute *hccs_chip_default_attrs[] = {
&all_linked_on_chip_attr.attr,
&linked_full_lane_on_chip_attr.attr,
&crc_err_cnt_sum_on_chip_attr.attr,
NULL,
};
ATTRIBUTE_GROUPS(hccs_chip_default);
static const struct kobj_type hccs_chip_type = {
.sysfs_ops = &hccs_comm_ops,
.default_groups = hccs_chip_default_groups,
};
static void hccs_remove_die_dir(struct hccs_die_info *die)
{
struct hccs_port_info *port;
u8 i;
for (i = 0; i < die->port_num; i++) {
port = &die->ports[i];
if (port->dir_created)
kobject_put(&port->kobj);
}
kobject_put(&die->kobj);
}
static void hccs_remove_chip_dir(struct hccs_chip_info *chip)
{
struct hccs_die_info *die;
u8 i;
for (i = 0; i < chip->die_num; i++) {
die = &chip->dies[i];
if (die->dir_created)
hccs_remove_die_dir(die);
}
kobject_put(&chip->kobj);
}
static void hccs_remove_topo_dirs(struct hccs_dev *hdev)
{
u8 i;
for (i = 0; i < hdev->chip_num; i++)
hccs_remove_chip_dir(&hdev->chips[i]);
}
static int hccs_create_hccs_dir(struct hccs_dev *hdev,
struct hccs_die_info *die,
struct hccs_port_info *port)
{
int ret;
ret = kobject_init_and_add(&port->kobj, &hccs_port_type,
&die->kobj, "hccs%d", port->port_id);
if (ret) {
kobject_put(&port->kobj);
return ret;
}
return 0;
}
static int hccs_create_die_dir(struct hccs_dev *hdev,
struct hccs_chip_info *chip,
struct hccs_die_info *die)
{
struct hccs_port_info *port;
int ret;
u16 i;
ret = kobject_init_and_add(&die->kobj, &hccs_die_type,
&chip->kobj, "die%d", die->die_id);
if (ret) {
kobject_put(&die->kobj);
return ret;
}
for (i = 0; i < die->port_num; i++) {
port = &die->ports[i];
ret = hccs_create_hccs_dir(hdev, die, port);
if (ret) {
dev_err(hdev->dev, "create hccs%d dir failed.\n",
port->port_id);
goto err;
}
port->dir_created = true;
}
return 0;
err:
hccs_remove_die_dir(die);
return ret;
}
static int hccs_create_chip_dir(struct hccs_dev *hdev,
struct hccs_chip_info *chip)
{
struct hccs_die_info *die;
int ret;
u16 id;
ret = kobject_init_and_add(&chip->kobj, &hccs_chip_type,
&hdev->dev->kobj, "chip%d", chip->chip_id);
if (ret) {
kobject_put(&chip->kobj);
return ret;
}
for (id = 0; id < chip->die_num; id++) {
die = &chip->dies[id];
ret = hccs_create_die_dir(hdev, chip, die);
if (ret)
goto err;
die->dir_created = true;
}
return 0;
err:
hccs_remove_chip_dir(chip);
return ret;
}
static int hccs_create_topo_dirs(struct hccs_dev *hdev)
{
struct hccs_chip_info *chip;
u8 id, k;
int ret;
for (id = 0; id < hdev->chip_num; id++) {
chip = &hdev->chips[id];
ret = hccs_create_chip_dir(hdev, chip);
if (ret) {
dev_err(hdev->dev, "init chip%d dir failed!\n", id);
goto err;
}
}
return 0;
err:
for (k = 0; k < id; k++)
hccs_remove_chip_dir(&hdev->chips[k]);
return ret;
}
static int hccs_probe(struct platform_device *pdev)
{
struct acpi_device *acpi_dev;
struct hccs_dev *hdev;
int rc;
if (acpi_disabled) {
dev_err(&pdev->dev, "acpi is disabled.\n");
return -ENODEV;
}
acpi_dev = ACPI_COMPANION(&pdev->dev);
if (!acpi_dev)
return -ENODEV;
hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
if (!hdev)
return -ENOMEM;
hdev->acpi_dev = acpi_dev;
hdev->dev = &pdev->dev;
platform_set_drvdata(pdev, hdev);
mutex_init(&hdev->lock);
rc = hccs_get_pcc_chan_id(hdev);
if (rc)
return rc;
rc = hccs_register_pcc_channel(hdev);
if (rc)
return rc;
rc = hccs_get_dev_caps(hdev);
if (rc)
goto unregister_pcc_chan;
rc = hccs_get_hw_info(hdev);
if (rc)
goto unregister_pcc_chan;
rc = hccs_create_topo_dirs(hdev);
if (rc)
goto unregister_pcc_chan;
return 0;
unregister_pcc_chan:
hccs_unregister_pcc_channel(hdev);
return rc;
}
static int hccs_remove(struct platform_device *pdev)
{
struct hccs_dev *hdev = platform_get_drvdata(pdev);
hccs_remove_topo_dirs(hdev);
hccs_unregister_pcc_channel(hdev);
return 0;
}
static const struct acpi_device_id hccs_acpi_match[] = {
{ "HISI04B1"},
{ ""},
};
MODULE_DEVICE_TABLE(acpi, hccs_acpi_match);
static struct platform_driver hccs_driver = {
.probe = hccs_probe,
.remove = hccs_remove,
.driver = {
.name = "kunpeng_hccs",
.acpi_match_table = hccs_acpi_match,
},
};
module_platform_driver(hccs_driver);
MODULE_DESCRIPTION("Kunpeng SoC HCCS driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Huisong Li <[email protected]>");
|
linux-master
|
drivers/soc/hisilicon/kunpeng_hccs.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Nuvoton WPCM450 SoC Identification
*
* Copyright (C) 2022 Jonathan Neuschäfer
*/
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#define GCR_PDID 0
#define PDID_CHIP(x) ((x) & 0x00ffffff)
#define CHIP_WPCM450 0x926450
#define PDID_REV(x) ((x) >> 24)
struct revision {
u8 number;
const char *name;
};
static const struct revision revisions[] __initconst = {
{ 0x00, "Z1" },
{ 0x03, "Z2" },
{ 0x04, "Z21" },
{ 0x08, "A1" },
{ 0x09, "A2" },
{ 0x0a, "A3" },
{}
};
static const char * __init get_revision(unsigned int rev)
{
int i;
for (i = 0; revisions[i].name; i++)
if (revisions[i].number == rev)
return revisions[i].name;
return NULL;
}
static struct soc_device_attribute *wpcm450_attr;
static struct soc_device *wpcm450_soc;
static int __init wpcm450_soc_init(void)
{
struct soc_device_attribute *attr;
struct soc_device *soc;
const char *revision;
struct regmap *gcr;
u32 pdid;
int ret;
if (!of_machine_is_compatible("nuvoton,wpcm450"))
return 0;
gcr = syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr");
if (IS_ERR(gcr))
return PTR_ERR(gcr);
ret = regmap_read(gcr, GCR_PDID, &pdid);
if (ret)
return ret;
if (PDID_CHIP(pdid) != CHIP_WPCM450) {
pr_warn("Unknown chip ID in GCR.PDID: 0x%06x\n", PDID_CHIP(pdid));
return -ENODEV;
}
revision = get_revision(PDID_REV(pdid));
if (!revision) {
pr_warn("Unknown chip revision in GCR.PDID: 0x%02x\n", PDID_REV(pdid));
return -ENODEV;
}
attr = kzalloc(sizeof(*attr), GFP_KERNEL);
if (!attr)
return -ENOMEM;
attr->family = "Nuvoton NPCM";
attr->soc_id = "WPCM450";
attr->revision = revision;
soc = soc_device_register(attr);
if (IS_ERR(soc)) {
kfree(attr);
pr_warn("Could not register SoC device\n");
return PTR_ERR(soc);
}
wpcm450_soc = soc;
wpcm450_attr = attr;
return 0;
}
module_init(wpcm450_soc_init);
static void __exit wpcm450_soc_exit(void)
{
if (wpcm450_soc) {
soc_device_unregister(wpcm450_soc);
wpcm450_soc = NULL;
kfree(wpcm450_attr);
}
}
module_exit(wpcm450_soc_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jonathan Neuschäfer");
MODULE_DESCRIPTION("Nuvoton WPCM450 SoC Identification driver");
|
linux-master
|
drivers/soc/nuvoton/wpcm450-soc.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright © 2014 NVIDIA Corporation
* Copyright © 2015 Broadcom Corporation
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/soc/brcmstb/brcmstb.h>
#include <linux/sys_soc.h>
static u32 family_id;
static u32 product_id;
u32 brcmstb_get_family_id(void)
{
return family_id;
}
EXPORT_SYMBOL(brcmstb_get_family_id);
u32 brcmstb_get_product_id(void)
{
return product_id;
}
EXPORT_SYMBOL(brcmstb_get_product_id);
static const struct of_device_id sun_top_ctrl_match[] = {
{ .compatible = "brcm,bcm7125-sun-top-ctrl", },
{ .compatible = "brcm,bcm7346-sun-top-ctrl", },
{ .compatible = "brcm,bcm7358-sun-top-ctrl", },
{ .compatible = "brcm,bcm7360-sun-top-ctrl", },
{ .compatible = "brcm,bcm7362-sun-top-ctrl", },
{ .compatible = "brcm,bcm7420-sun-top-ctrl", },
{ .compatible = "brcm,bcm7425-sun-top-ctrl", },
{ .compatible = "brcm,bcm7429-sun-top-ctrl", },
{ .compatible = "brcm,bcm7435-sun-top-ctrl", },
{ .compatible = "brcm,brcmstb-sun-top-ctrl", },
{ }
};
static int __init brcmstb_soc_device_early_init(void)
{
struct device_node *sun_top_ctrl;
void __iomem *sun_top_ctrl_base;
int ret = 0;
/* We could be on a multi-platform kernel, don't make this fatal but
* bail out early
*/
sun_top_ctrl = of_find_matching_node(NULL, sun_top_ctrl_match);
if (!sun_top_ctrl)
return ret;
sun_top_ctrl_base = of_iomap(sun_top_ctrl, 0);
if (!sun_top_ctrl_base) {
ret = -ENODEV;
goto out;
}
family_id = readl(sun_top_ctrl_base);
product_id = readl(sun_top_ctrl_base + 0x4);
iounmap(sun_top_ctrl_base);
out:
of_node_put(sun_top_ctrl);
return ret;
}
early_initcall(brcmstb_soc_device_early_init);
static int __init brcmstb_soc_device_init(void)
{
struct soc_device_attribute *soc_dev_attr;
struct device_node *sun_top_ctrl;
struct soc_device *soc_dev;
int ret = 0;
/* We could be on a multi-platform kernel, don't make this fatal but
* bail out early
*/
sun_top_ctrl = of_find_matching_node(NULL, sun_top_ctrl_match);
if (!sun_top_ctrl)
return ret;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr) {
ret = -ENOMEM;
goto out;
}
soc_dev_attr->family = kasprintf(GFP_KERNEL, "%x",
family_id >> 28 ?
family_id >> 16 : family_id >> 8);
soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%x",
product_id >> 28 ?
product_id >> 16 : product_id >> 8);
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c%d",
((product_id & 0xf0) >> 4) + 'A',
product_id & 0xf);
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr->family);
kfree(soc_dev_attr->soc_id);
kfree(soc_dev_attr->revision);
kfree(soc_dev_attr);
ret = -ENOMEM;
}
out:
of_node_put(sun_top_ctrl);
return ret;
}
arch_initcall(brcmstb_soc_device_init);
|
linux-master
|
drivers/soc/bcm/brcmstb/common.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Broadcom STB SoCs Bus Unit Interface controls
*
* Copyright (C) 2015, Broadcom Corporation
*/
#define pr_fmt(fmt) "brcmstb: " KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <linux/soc/brcmstb/brcmstb.h>
#define RACENPREF_MASK 0x3
#define RACPREFINST_SHIFT 0
#define RACENINST_SHIFT 2
#define RACPREFDATA_SHIFT 4
#define RACENDATA_SHIFT 6
#define RAC_CPU_SHIFT 8
#define RACCFG_MASK 0xff
#define DPREF_LINE_2_SHIFT 24
#define DPREF_LINE_2_MASK 0xff
/* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
#define RAC_DATA_INST_EN_MASK (1 << RACPREFINST_SHIFT | \
RACENPREF_MASK << RACENINST_SHIFT | \
1 << RACPREFDATA_SHIFT | \
RACENPREF_MASK << RACENDATA_SHIFT)
#define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
#define CPU_CREDIT_REG_MCPx_READ_CRED_MASK 0xf
#define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK 0xf
#define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x) ((x) * 8)
#define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) (((x) * 8) + 4)
#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x) ((x) * 8)
#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK 0xff
#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK 0xf
#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK 0xf
#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT 4
#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE BIT(8)
static void __iomem *cpubiuctrl_base;
static bool mcp_wr_pairing_en;
static const int *cpubiuctrl_regs;
enum cpubiuctrl_regs {
CPU_CREDIT_REG = 0,
CPU_MCP_FLOW_REG,
CPU_WRITEBACK_CTRL_REG,
RAC_CONFIG0_REG,
RAC_CONFIG1_REG,
NUM_CPU_BIUCTRL_REGS,
};
static inline u32 cbc_readl(int reg)
{
int offset = cpubiuctrl_regs[reg];
if (offset == -1 ||
(IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
return (u32)-1;
return readl_relaxed(cpubiuctrl_base + offset);
}
static inline void cbc_writel(u32 val, int reg)
{
int offset = cpubiuctrl_regs[reg];
if (offset == -1 ||
(IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
return;
writel(val, cpubiuctrl_base + offset);
}
static const int b15_cpubiuctrl_regs[] = {
[CPU_CREDIT_REG] = 0x184,
[CPU_MCP_FLOW_REG] = -1,
[CPU_WRITEBACK_CTRL_REG] = -1,
[RAC_CONFIG0_REG] = -1,
[RAC_CONFIG1_REG] = -1,
};
/* Odd cases, e.g: 7260A0 */
static const int b53_cpubiuctrl_no_wb_regs[] = {
[CPU_CREDIT_REG] = 0x0b0,
[CPU_MCP_FLOW_REG] = 0x0b4,
[CPU_WRITEBACK_CTRL_REG] = -1,
[RAC_CONFIG0_REG] = 0x78,
[RAC_CONFIG1_REG] = 0x7c,
};
static const int b53_cpubiuctrl_regs[] = {
[CPU_CREDIT_REG] = 0x0b0,
[CPU_MCP_FLOW_REG] = 0x0b4,
[CPU_WRITEBACK_CTRL_REG] = 0x22c,
[RAC_CONFIG0_REG] = 0x78,
[RAC_CONFIG1_REG] = 0x7c,
};
static const int a72_cpubiuctrl_regs[] = {
[CPU_CREDIT_REG] = 0x18,
[CPU_MCP_FLOW_REG] = 0x1c,
[CPU_WRITEBACK_CTRL_REG] = 0x20,
[RAC_CONFIG0_REG] = 0x08,
[RAC_CONFIG1_REG] = 0x0c,
};
static int __init mcp_write_pairing_set(void)
{
u32 creds = 0;
if (!cpubiuctrl_base)
return -1;
creds = cbc_readl(CPU_CREDIT_REG);
if (mcp_wr_pairing_en) {
pr_info("MCP: Enabling write pairing\n");
cbc_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
CPU_CREDIT_REG);
} else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
pr_info("MCP: Disabling write pairing\n");
cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
CPU_CREDIT_REG);
} else {
pr_info("MCP: Write pairing already disabled\n");
}
return 0;
}
static const u32 a72_b53_mach_compat[] = {
0x7211,
0x72113,
0x72116,
0x7216,
0x72164,
0x72165,
0x7255,
0x7260,
0x7268,
0x7271,
0x7278,
};
/* The read-ahead cache present in the Brahma-B53 CPU is a special piece of
* hardware after the integrated L2 cache of the B53 CPU complex whose purpose
* is to prefetch instruction and/or data with a line size of either 64 bytes
* or 256 bytes. The rationale is that the data-bus of the CPU interface is
* optimized for 256-byte transactions, and enabling the read-ahead cache
* provides a significant performance boost (typically twice the performance
* for a memcpy benchmark application).
*
* The read-ahead cache is transparent for Virtual Address cache maintenance
* operations: IC IVAU, DC IVAC, DC CVAC, DC CVAU and DC CIVAC. So no special
* handling is needed for the DMA API above and beyond what is included in the
* arm64 implementation.
*
* In addition, since the Point of Unification is typically between L1 and L2
* for the Brahma-B53 processor no special read-ahead cache handling is needed
* for the IC IALLU and IC IALLUIS cache maintenance operations.
*
* However, it is not possible to specify the cache level (L3) for the cache
* maintenance instructions operating by set/way to operate on the read-ahead
* cache. The read-ahead cache will maintain coherency when inner cache lines
* are cleaned by set/way, but if it is necessary to invalidate inner cache
* lines by set/way to maintain coherency with system masters operating on
* shared memory that does not have hardware support for coherency, then it
* will also be necessary to explicitly invalidate the read-ahead cache.
*/
static void __init a72_b53_rac_enable_all(struct device_node *np)
{
unsigned int cpu;
u32 enable = 0, pref_dist, shift;
if (IS_ENABLED(CONFIG_CACHE_B15_RAC))
return;
if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n"))
return;
pref_dist = cbc_readl(RAC_CONFIG1_REG);
for_each_possible_cpu(cpu) {
shift = cpu * RAC_CPU_SHIFT + RACPREFDATA_SHIFT;
enable |= RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT);
if (cpubiuctrl_regs == a72_cpubiuctrl_regs) {
enable &= ~(RACENPREF_MASK << shift);
enable |= 3 << shift;
pref_dist |= 1 << (cpu + DPREF_LINE_2_SHIFT);
}
}
cbc_writel(enable, RAC_CONFIG0_REG);
cbc_writel(pref_dist, RAC_CONFIG1_REG);
pr_info("%pOF: Broadcom %s read-ahead cache\n",
np, cpubiuctrl_regs == a72_cpubiuctrl_regs ?
"Cortex-A72" : "Brahma-B53");
}
static void __init mcp_a72_b53_set(void)
{
unsigned int i;
u32 reg;
reg = brcmstb_get_family_id();
for (i = 0; i < ARRAY_SIZE(a72_b53_mach_compat); i++) {
if (BRCM_ID(reg) == a72_b53_mach_compat[i])
break;
}
if (i == ARRAY_SIZE(a72_b53_mach_compat))
return;
/* Set all 3 MCP interfaces to 8 credits */
reg = cbc_readl(CPU_CREDIT_REG);
for (i = 0; i < 3; i++) {
reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK <<
CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i));
reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK <<
CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i));
reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i);
reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i);
}
cbc_writel(reg, CPU_CREDIT_REG);
/* Max out the number of in-flight Jwords reads on the MCP interface */
reg = cbc_readl(CPU_MCP_FLOW_REG);
for (i = 0; i < 3; i++)
reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK <<
CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i);
cbc_writel(reg, CPU_MCP_FLOW_REG);
/* Enable writeback throttling, set timeout to 128 cycles, 256 cycles
* threshold
*/
reg = cbc_readl(CPU_WRITEBACK_CTRL_REG);
reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE;
reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK;
reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK <<
CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT);
reg |= 8;
reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT;
cbc_writel(reg, CPU_WRITEBACK_CTRL_REG);
}
static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
{
struct device_node *cpu_dn;
u32 family_id;
int ret = 0;
cpubiuctrl_base = of_iomap(np, 0);
if (!cpubiuctrl_base) {
pr_err("failed to remap BIU control base\n");
ret = -ENOMEM;
goto out;
}
mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
cpu_dn = of_get_cpu_node(0, NULL);
if (!cpu_dn) {
pr_err("failed to obtain CPU device node\n");
ret = -ENODEV;
goto out;
}
if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
cpubiuctrl_regs = b15_cpubiuctrl_regs;
else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
cpubiuctrl_regs = b53_cpubiuctrl_regs;
else if (of_device_is_compatible(cpu_dn, "arm,cortex-a72"))
cpubiuctrl_regs = a72_cpubiuctrl_regs;
else {
pr_err("unsupported CPU\n");
ret = -EINVAL;
}
of_node_put(cpu_dn);
family_id = brcmstb_get_family_id();
if (BRCM_ID(family_id) == 0x7260 && BRCM_REV(family_id) == 0)
cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs;
out:
if (ret && cpubiuctrl_base) {
iounmap(cpubiuctrl_base);
cpubiuctrl_base = NULL;
}
return ret;
}
#ifdef CONFIG_PM_SLEEP
static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS];
static int brcmstb_cpu_credit_reg_suspend(void)
{
unsigned int i;
if (!cpubiuctrl_base)
return 0;
for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
cpubiuctrl_reg_save[i] = cbc_readl(i);
return 0;
}
static void brcmstb_cpu_credit_reg_resume(void)
{
unsigned int i;
if (!cpubiuctrl_base)
return;
for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
cbc_writel(cpubiuctrl_reg_save[i], i);
}
static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
.suspend = brcmstb_cpu_credit_reg_suspend,
.resume = brcmstb_cpu_credit_reg_resume,
};
#endif
static int __init brcmstb_biuctrl_init(void)
{
struct device_node *np;
int ret;
/* We might be running on a multi-platform kernel, don't make this a
* fatal error, just bail out early
*/
np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
if (!np)
return 0;
ret = setup_hifcpubiuctrl_regs(np);
if (ret)
goto out_put;
ret = mcp_write_pairing_set();
if (ret) {
pr_err("MCP: Unable to disable write pairing!\n");
goto out_put;
}
a72_b53_rac_enable_all(np);
mcp_a72_b53_set();
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
#endif
ret = 0;
out_put:
of_node_put(np);
return ret;
}
early_initcall(brcmstb_biuctrl_init);
|
linux-master
|
drivers/soc/bcm/brcmstb/biuctrl.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* MIPS-specific support for Broadcom STB S2/S3/S5 power management
*
* Copyright (C) 2016-2017 Broadcom
*/
#include <linux/kernel.h>
#include <linux/printk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/delay.h>
#include <linux/suspend.h>
#include <asm/bmips.h>
#include <asm/tlbflush.h>
#include "pm.h"
#define S2_NUM_PARAMS 6
#define MAX_NUM_MEMC 3
/* S3 constants */
#define MAX_GP_REGS 16
#define MAX_CP0_REGS 32
#define NUM_MEMC_CLIENTS 128
#define AON_CTRL_RAM_SIZE 128
#define BRCMSTB_S3_MAGIC 0x5AFEB007
#define CLEAR_RESET_MASK 0x01
/* Index each CP0 register that needs to be saved */
#define CONTEXT 0
#define USER_LOCAL 1
#define PGMK 2
#define HWRENA 3
#define COMPARE 4
#define STATUS 5
#define CONFIG 6
#define MODE 7
#define EDSP 8
#define BOOT_VEC 9
#define EBASE 10
struct brcmstb_memc {
void __iomem *ddr_phy_base;
void __iomem *arb_base;
};
struct brcmstb_pm_control {
void __iomem *aon_ctrl_base;
void __iomem *aon_sram_base;
void __iomem *timers_base;
struct brcmstb_memc memcs[MAX_NUM_MEMC];
int num_memc;
};
struct brcm_pm_s3_context {
u32 cp0_regs[MAX_CP0_REGS];
u32 memc0_rts[NUM_MEMC_CLIENTS];
u32 sc_boot_vec;
};
struct brcmstb_mem_transfer;
struct brcmstb_mem_transfer {
struct brcmstb_mem_transfer *next;
void *src;
void *dst;
dma_addr_t pa_src;
dma_addr_t pa_dst;
u32 len;
u8 key;
u8 mode;
u8 src_remapped;
u8 dst_remapped;
u8 src_dst_remapped;
};
#define AON_SAVE_SRAM(base, idx, val) \
__raw_writel(val, base + (idx << 2))
/* Used for saving registers in asm */
u32 gp_regs[MAX_GP_REGS];
#define BSP_CLOCK_STOP 0x00
#define PM_INITIATE 0x01
static struct brcmstb_pm_control ctrl;
static void brcm_pm_save_cp0_context(struct brcm_pm_s3_context *ctx)
{
/* Generic MIPS */
ctx->cp0_regs[CONTEXT] = read_c0_context();
ctx->cp0_regs[USER_LOCAL] = read_c0_userlocal();
ctx->cp0_regs[PGMK] = read_c0_pagemask();
ctx->cp0_regs[HWRENA] = read_c0_cache();
ctx->cp0_regs[COMPARE] = read_c0_compare();
ctx->cp0_regs[STATUS] = read_c0_status();
/* Broadcom specific */
ctx->cp0_regs[CONFIG] = read_c0_brcm_config();
ctx->cp0_regs[MODE] = read_c0_brcm_mode();
ctx->cp0_regs[EDSP] = read_c0_brcm_edsp();
ctx->cp0_regs[BOOT_VEC] = read_c0_brcm_bootvec();
ctx->cp0_regs[EBASE] = read_c0_ebase();
ctx->sc_boot_vec = bmips_read_zscm_reg(0xa0);
}
static void brcm_pm_restore_cp0_context(struct brcm_pm_s3_context *ctx)
{
/* Restore cp0 state */
bmips_write_zscm_reg(0xa0, ctx->sc_boot_vec);
/* Generic MIPS */
write_c0_context(ctx->cp0_regs[CONTEXT]);
write_c0_userlocal(ctx->cp0_regs[USER_LOCAL]);
write_c0_pagemask(ctx->cp0_regs[PGMK]);
write_c0_cache(ctx->cp0_regs[HWRENA]);
write_c0_compare(ctx->cp0_regs[COMPARE]);
write_c0_status(ctx->cp0_regs[STATUS]);
/* Broadcom specific */
write_c0_brcm_config(ctx->cp0_regs[CONFIG]);
write_c0_brcm_mode(ctx->cp0_regs[MODE]);
write_c0_brcm_edsp(ctx->cp0_regs[EDSP]);
write_c0_brcm_bootvec(ctx->cp0_regs[BOOT_VEC]);
write_c0_ebase(ctx->cp0_regs[EBASE]);
}
static void brcmstb_pm_handshake(void)
{
void __iomem *base = ctrl.aon_ctrl_base;
u32 tmp;
/* BSP power handshake, v1 */
tmp = __raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
tmp &= ~1UL;
__raw_writel(tmp, base + AON_CTRL_HOST_MISC_CMDS);
(void)__raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
__raw_writel(0, base + AON_CTRL_PM_INITIATE);
(void)__raw_readl(base + AON_CTRL_PM_INITIATE);
__raw_writel(BSP_CLOCK_STOP | PM_INITIATE,
base + AON_CTRL_PM_INITIATE);
/*
* HACK: BSP may have internal race on the CLOCK_STOP command.
* Avoid touching the BSP for a few milliseconds.
*/
mdelay(3);
}
static void brcmstb_pm_s5(void)
{
void __iomem *base = ctrl.aon_ctrl_base;
brcmstb_pm_handshake();
/* Clear magic s3 warm-boot value */
AON_SAVE_SRAM(ctrl.aon_sram_base, 0, 0);
/* Set the countdown */
__raw_writel(0x10, base + AON_CTRL_PM_CPU_WAIT_COUNT);
(void)__raw_readl(base + AON_CTRL_PM_CPU_WAIT_COUNT);
/* Prepare to S5 cold boot */
__raw_writel(PM_COLD_CONFIG, base + AON_CTRL_PM_CTRL);
(void)__raw_readl(base + AON_CTRL_PM_CTRL);
__raw_writel((PM_COLD_CONFIG | PM_PWR_DOWN), base +
AON_CTRL_PM_CTRL);
(void)__raw_readl(base + AON_CTRL_PM_CTRL);
__asm__ __volatile__(
" wait\n"
: : : "memory");
}
static int brcmstb_pm_s3(void)
{
struct brcm_pm_s3_context s3_context;
void __iomem *memc_arb_base;
unsigned long flags;
u32 tmp;
int i;
/* Prepare for s3 */
AON_SAVE_SRAM(ctrl.aon_sram_base, 0, BRCMSTB_S3_MAGIC);
AON_SAVE_SRAM(ctrl.aon_sram_base, 1, (u32)&s3_reentry);
AON_SAVE_SRAM(ctrl.aon_sram_base, 2, 0);
/* Clear RESET_HISTORY */
tmp = __raw_readl(ctrl.aon_ctrl_base + AON_CTRL_RESET_CTRL);
tmp &= ~CLEAR_RESET_MASK;
__raw_writel(tmp, ctrl.aon_ctrl_base + AON_CTRL_RESET_CTRL);
local_irq_save(flags);
/* Inhibit DDR_RSTb pulse for both MMCs*/
for (i = 0; i < ctrl.num_memc; i++) {
tmp = __raw_readl(ctrl.memcs[i].ddr_phy_base +
DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL);
tmp &= ~0x0f;
__raw_writel(tmp, ctrl.memcs[i].ddr_phy_base +
DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL);
tmp |= (0x05 | BIT(5));
__raw_writel(tmp, ctrl.memcs[i].ddr_phy_base +
DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL);
}
/* Save CP0 context */
brcm_pm_save_cp0_context(&s3_context);
/* Save RTS(skip debug register) */
memc_arb_base = ctrl.memcs[0].arb_base + 4;
for (i = 0; i < NUM_MEMC_CLIENTS; i++) {
s3_context.memc0_rts[i] = __raw_readl(memc_arb_base);
memc_arb_base += 4;
}
/* Save I/O context */
local_flush_tlb_all();
_dma_cache_wback_inv(0, ~0);
brcm_pm_do_s3(ctrl.aon_ctrl_base, current_cpu_data.dcache.linesz);
/* CPU reconfiguration */
local_flush_tlb_all();
bmips_cpu_setup();
cpumask_clear(&bmips_booted_mask);
/* Restore RTS (skip debug register) */
memc_arb_base = ctrl.memcs[0].arb_base + 4;
for (i = 0; i < NUM_MEMC_CLIENTS; i++) {
__raw_writel(s3_context.memc0_rts[i], memc_arb_base);
memc_arb_base += 4;
}
/* restore CP0 context */
brcm_pm_restore_cp0_context(&s3_context);
local_irq_restore(flags);
return 0;
}
static int brcmstb_pm_s2(void)
{
/*
* We need to pass 6 arguments to an assembly function. Lets avoid the
* stack and pass arguments in a explicit 4 byte array. The assembly
* code assumes all arguments are 4 bytes and arguments are ordered
* like so:
*
* 0: AON_CTRl base register
* 1: DDR_PHY base register
* 2: TIMERS base resgister
* 3: I-Cache line size
* 4: Restart vector address
* 5: Restart vector size
*/
u32 s2_params[6];
/* Prepare s2 parameters */
s2_params[0] = (u32)ctrl.aon_ctrl_base;
s2_params[1] = (u32)ctrl.memcs[0].ddr_phy_base;
s2_params[2] = (u32)ctrl.timers_base;
s2_params[3] = (u32)current_cpu_data.icache.linesz;
s2_params[4] = (u32)BMIPS_WARM_RESTART_VEC;
s2_params[5] = (u32)(bmips_smp_int_vec_end -
bmips_smp_int_vec);
/* Drop to standby */
brcm_pm_do_s2(s2_params);
return 0;
}
static int brcmstb_pm_standby(bool deep_standby)
{
brcmstb_pm_handshake();
/* Send IRQs to BMIPS_WARM_RESTART_VEC */
clear_c0_cause(CAUSEF_IV);
irq_disable_hazard();
set_c0_status(ST0_BEV);
irq_disable_hazard();
if (deep_standby)
brcmstb_pm_s3();
else
brcmstb_pm_s2();
/* Send IRQs to normal runtime vectors */
clear_c0_status(ST0_BEV);
irq_disable_hazard();
set_c0_cause(CAUSEF_IV);
irq_disable_hazard();
return 0;
}
static int brcmstb_pm_enter(suspend_state_t state)
{
int ret = -EINVAL;
switch (state) {
case PM_SUSPEND_STANDBY:
ret = brcmstb_pm_standby(false);
break;
case PM_SUSPEND_MEM:
ret = brcmstb_pm_standby(true);
break;
}
return ret;
}
static int brcmstb_pm_valid(suspend_state_t state)
{
switch (state) {
case PM_SUSPEND_STANDBY:
return true;
case PM_SUSPEND_MEM:
return true;
default:
return false;
}
}
static const struct platform_suspend_ops brcmstb_pm_ops = {
.enter = brcmstb_pm_enter,
.valid = brcmstb_pm_valid,
};
static const struct of_device_id aon_ctrl_dt_ids[] = {
{ .compatible = "brcm,brcmstb-aon-ctrl" },
{ /* sentinel */ }
};
static const struct of_device_id ddr_phy_dt_ids[] = {
{ .compatible = "brcm,brcmstb-ddr-phy" },
{ /* sentinel */ }
};
static const struct of_device_id arb_dt_ids[] = {
{ .compatible = "brcm,brcmstb-memc-arb" },
{ /* sentinel */ }
};
static const struct of_device_id timers_ids[] = {
{ .compatible = "brcm,brcmstb-timers" },
{ /* sentinel */ }
};
static inline void __iomem *brcmstb_ioremap_node(struct device_node *dn,
int index)
{
return of_io_request_and_map(dn, index, dn->full_name);
}
static void __iomem *brcmstb_ioremap_match(const struct of_device_id *matches,
int index, const void **ofdata)
{
struct device_node *dn;
const struct of_device_id *match;
dn = of_find_matching_node_and_match(NULL, matches, &match);
if (!dn)
return ERR_PTR(-EINVAL);
if (ofdata)
*ofdata = match->data;
return brcmstb_ioremap_node(dn, index);
}
static int brcmstb_pm_init(void)
{
struct device_node *dn;
void __iomem *base;
int i;
/* AON ctrl registers */
base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL);
if (IS_ERR(base)) {
pr_err("error mapping AON_CTRL\n");
goto aon_err;
}
ctrl.aon_ctrl_base = base;
/* AON SRAM registers */
base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 1, NULL);
if (IS_ERR(base)) {
pr_err("error mapping AON_SRAM\n");
goto sram_err;
}
ctrl.aon_sram_base = base;
ctrl.num_memc = 0;
/* Map MEMC DDR PHY registers */
for_each_matching_node(dn, ddr_phy_dt_ids) {
i = ctrl.num_memc;
if (i >= MAX_NUM_MEMC) {
pr_warn("Too many MEMCs (max %d)\n", MAX_NUM_MEMC);
of_node_put(dn);
break;
}
base = brcmstb_ioremap_node(dn, 0);
if (IS_ERR(base)) {
of_node_put(dn);
goto ddr_err;
}
ctrl.memcs[i].ddr_phy_base = base;
ctrl.num_memc++;
}
/* MEMC ARB registers */
base = brcmstb_ioremap_match(arb_dt_ids, 0, NULL);
if (IS_ERR(base)) {
pr_err("error mapping MEMC ARB\n");
goto ddr_err;
}
ctrl.memcs[0].arb_base = base;
/* Timer registers */
base = brcmstb_ioremap_match(timers_ids, 0, NULL);
if (IS_ERR(base)) {
pr_err("error mapping timers\n");
goto tmr_err;
}
ctrl.timers_base = base;
/* s3 cold boot aka s5 */
pm_power_off = brcmstb_pm_s5;
suspend_set_ops(&brcmstb_pm_ops);
return 0;
tmr_err:
iounmap(ctrl.memcs[0].arb_base);
ddr_err:
for (i = 0; i < ctrl.num_memc; i++)
iounmap(ctrl.memcs[i].ddr_phy_base);
iounmap(ctrl.aon_sram_base);
sram_err:
iounmap(ctrl.aon_ctrl_base);
aon_err:
return PTR_ERR(base);
}
arch_initcall(brcmstb_pm_init);
|
linux-master
|
drivers/soc/bcm/brcmstb/pm/pm-mips.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2017 IBM Corporation
*/
#include <linux/clk.h>
#include <linux/log2.h>
#include <linux/mfd/syscon.h>
#include <linux/miscdevice.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/poll.h>
#include <linux/regmap.h>
#include <linux/aspeed-lpc-ctrl.h>
#define DEVICE_NAME "aspeed-lpc-ctrl"
#define HICR5 0x80
#define HICR5_ENL2H BIT(8)
#define HICR5_ENFWH BIT(10)
#define HICR6 0x84
#define SW_FWH2AHB BIT(17)
#define HICR7 0x88
#define HICR8 0x8c
struct aspeed_lpc_ctrl {
struct miscdevice miscdev;
struct regmap *regmap;
struct clk *clk;
phys_addr_t mem_base;
resource_size_t mem_size;
u32 pnor_size;
u32 pnor_base;
bool fwh2ahb;
struct regmap *scu;
};
static struct aspeed_lpc_ctrl *file_aspeed_lpc_ctrl(struct file *file)
{
return container_of(file->private_data, struct aspeed_lpc_ctrl,
miscdev);
}
static int aspeed_lpc_ctrl_mmap(struct file *file, struct vm_area_struct *vma)
{
struct aspeed_lpc_ctrl *lpc_ctrl = file_aspeed_lpc_ctrl(file);
unsigned long vsize = vma->vm_end - vma->vm_start;
pgprot_t prot = vma->vm_page_prot;
if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT)
return -EINVAL;
/* ast2400/2500 AHB accesses are not cache coherent */
prot = pgprot_noncached(prot);
if (remap_pfn_range(vma, vma->vm_start,
(lpc_ctrl->mem_base >> PAGE_SHIFT) + vma->vm_pgoff,
vsize, prot))
return -EAGAIN;
return 0;
}
static long aspeed_lpc_ctrl_ioctl(struct file *file, unsigned int cmd,
unsigned long param)
{
struct aspeed_lpc_ctrl *lpc_ctrl = file_aspeed_lpc_ctrl(file);
struct device *dev = file->private_data;
void __user *p = (void __user *)param;
struct aspeed_lpc_ctrl_mapping map;
u32 addr;
u32 size;
long rc;
if (copy_from_user(&map, p, sizeof(map)))
return -EFAULT;
if (map.flags != 0)
return -EINVAL;
switch (cmd) {
case ASPEED_LPC_CTRL_IOCTL_GET_SIZE:
/* The flash windows don't report their size */
if (map.window_type != ASPEED_LPC_CTRL_WINDOW_MEMORY)
return -EINVAL;
/* Support more than one window id in the future */
if (map.window_id != 0)
return -EINVAL;
/* If memory-region is not described in device tree */
if (!lpc_ctrl->mem_size) {
dev_dbg(dev, "Didn't find reserved memory\n");
return -ENXIO;
}
map.size = lpc_ctrl->mem_size;
return copy_to_user(p, &map, sizeof(map)) ? -EFAULT : 0;
case ASPEED_LPC_CTRL_IOCTL_MAP:
/*
* The top half of HICR7 is the MSB of the BMC address of the
* mapping.
* The bottom half of HICR7 is the MSB of the HOST LPC
* firmware space address of the mapping.
*
* The 1 bits in the top of half of HICR8 represent the bits
* (in the requested address) that should be ignored and
* replaced with those from the top half of HICR7.
* The 1 bits in the bottom half of HICR8 represent the bits
* (in the requested address) that should be kept and pass
* into the BMC address space.
*/
/*
* It doesn't make sense to talk about a size or offset with
* low 16 bits set. Both HICR7 and HICR8 talk about the top 16
* bits of addresses and sizes.
*/
if ((map.size & 0x0000ffff) || (map.offset & 0x0000ffff))
return -EINVAL;
/*
* Because of the way the masks work in HICR8 offset has to
* be a multiple of size.
*/
if (map.offset & (map.size - 1))
return -EINVAL;
if (map.window_type == ASPEED_LPC_CTRL_WINDOW_FLASH) {
if (!lpc_ctrl->pnor_size) {
dev_dbg(dev, "Didn't find host pnor flash\n");
return -ENXIO;
}
addr = lpc_ctrl->pnor_base;
size = lpc_ctrl->pnor_size;
} else if (map.window_type == ASPEED_LPC_CTRL_WINDOW_MEMORY) {
/* If memory-region is not described in device tree */
if (!lpc_ctrl->mem_size) {
dev_dbg(dev, "Didn't find reserved memory\n");
return -ENXIO;
}
addr = lpc_ctrl->mem_base;
size = lpc_ctrl->mem_size;
} else {
return -EINVAL;
}
/* Check overflow first! */
if (map.offset + map.size < map.offset ||
map.offset + map.size > size)
return -EINVAL;
if (map.size == 0 || map.size > size)
return -EINVAL;
addr += map.offset;
/*
* addr (host lpc address) is safe regardless of values. This
* simply changes the address the host has to request on its
* side of the LPC bus. This cannot impact the hosts own
* memory space by surprise as LPC specific accessors are
* required. The only strange thing that could be done is
* setting the lower 16 bits but the shift takes care of that.
*/
rc = regmap_write(lpc_ctrl->regmap, HICR7,
(addr | (map.addr >> 16)));
if (rc)
return rc;
rc = regmap_write(lpc_ctrl->regmap, HICR8,
(~(map.size - 1)) | ((map.size >> 16) - 1));
if (rc)
return rc;
/*
* Switch to FWH2AHB mode, AST2600 only.
*/
if (lpc_ctrl->fwh2ahb) {
/*
* Enable FWH2AHB in SCU debug control register 2. This
* does not turn it on, but makes it available for it
* to be configured in HICR6.
*/
regmap_update_bits(lpc_ctrl->scu, 0x0D8, BIT(2), 0);
/*
* The other bits in this register are interrupt status bits
* that are cleared by writing 1. As we don't want to clear
* them, set only the bit of interest.
*/
regmap_write(lpc_ctrl->regmap, HICR6, SW_FWH2AHB);
}
/*
* Enable LPC FHW cycles. This is required for the host to
* access the regions specified.
*/
return regmap_update_bits(lpc_ctrl->regmap, HICR5,
HICR5_ENFWH | HICR5_ENL2H,
HICR5_ENFWH | HICR5_ENL2H);
}
return -EINVAL;
}
static const struct file_operations aspeed_lpc_ctrl_fops = {
.owner = THIS_MODULE,
.mmap = aspeed_lpc_ctrl_mmap,
.unlocked_ioctl = aspeed_lpc_ctrl_ioctl,
};
static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
{
struct aspeed_lpc_ctrl *lpc_ctrl;
struct device_node *node;
struct resource resm;
struct device *dev;
struct device_node *np;
int rc;
dev = &pdev->dev;
lpc_ctrl = devm_kzalloc(dev, sizeof(*lpc_ctrl), GFP_KERNEL);
if (!lpc_ctrl)
return -ENOMEM;
/* If flash is described in device tree then store */
node = of_parse_phandle(dev->of_node, "flash", 0);
if (!node) {
dev_dbg(dev, "Didn't find host pnor flash node\n");
} else {
rc = of_address_to_resource(node, 1, &resm);
of_node_put(node);
if (rc) {
dev_err(dev, "Couldn't address to resource for flash\n");
return rc;
}
lpc_ctrl->pnor_size = resource_size(&resm);
lpc_ctrl->pnor_base = resm.start;
}
dev_set_drvdata(&pdev->dev, lpc_ctrl);
/* If memory-region is described in device tree then store */
node = of_parse_phandle(dev->of_node, "memory-region", 0);
if (!node) {
dev_dbg(dev, "Didn't find reserved memory\n");
} else {
rc = of_address_to_resource(node, 0, &resm);
of_node_put(node);
if (rc) {
dev_err(dev, "Couldn't address to resource for reserved memory\n");
return -ENXIO;
}
lpc_ctrl->mem_size = resource_size(&resm);
lpc_ctrl->mem_base = resm.start;
if (!is_power_of_2(lpc_ctrl->mem_size)) {
dev_err(dev, "Reserved memory size must be a power of 2, got %u\n",
(unsigned int)lpc_ctrl->mem_size);
return -EINVAL;
}
if (!IS_ALIGNED(lpc_ctrl->mem_base, lpc_ctrl->mem_size)) {
dev_err(dev, "Reserved memory must be naturally aligned for size %u\n",
(unsigned int)lpc_ctrl->mem_size);
return -EINVAL;
}
}
np = pdev->dev.parent->of_node;
if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
!of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
!of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
dev_err(dev, "unsupported LPC device binding\n");
return -ENODEV;
}
lpc_ctrl->regmap = syscon_node_to_regmap(np);
if (IS_ERR(lpc_ctrl->regmap)) {
dev_err(dev, "Couldn't get regmap\n");
return -ENODEV;
}
if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-lpc-ctrl")) {
lpc_ctrl->fwh2ahb = true;
lpc_ctrl->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2600-scu");
if (IS_ERR(lpc_ctrl->scu)) {
dev_err(dev, "couldn't find scu\n");
return PTR_ERR(lpc_ctrl->scu);
}
}
lpc_ctrl->clk = devm_clk_get(dev, NULL);
if (IS_ERR(lpc_ctrl->clk))
return dev_err_probe(dev, PTR_ERR(lpc_ctrl->clk),
"couldn't get clock\n");
rc = clk_prepare_enable(lpc_ctrl->clk);
if (rc) {
dev_err(dev, "couldn't enable clock\n");
return rc;
}
lpc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR;
lpc_ctrl->miscdev.name = DEVICE_NAME;
lpc_ctrl->miscdev.fops = &aspeed_lpc_ctrl_fops;
lpc_ctrl->miscdev.parent = dev;
rc = misc_register(&lpc_ctrl->miscdev);
if (rc) {
dev_err(dev, "Unable to register device\n");
goto err;
}
return 0;
err:
clk_disable_unprepare(lpc_ctrl->clk);
return rc;
}
static int aspeed_lpc_ctrl_remove(struct platform_device *pdev)
{
struct aspeed_lpc_ctrl *lpc_ctrl = dev_get_drvdata(&pdev->dev);
misc_deregister(&lpc_ctrl->miscdev);
clk_disable_unprepare(lpc_ctrl->clk);
return 0;
}
static const struct of_device_id aspeed_lpc_ctrl_match[] = {
{ .compatible = "aspeed,ast2400-lpc-ctrl" },
{ .compatible = "aspeed,ast2500-lpc-ctrl" },
{ .compatible = "aspeed,ast2600-lpc-ctrl" },
{ },
};
static struct platform_driver aspeed_lpc_ctrl_driver = {
.driver = {
.name = DEVICE_NAME,
.of_match_table = aspeed_lpc_ctrl_match,
},
.probe = aspeed_lpc_ctrl_probe,
.remove = aspeed_lpc_ctrl_remove,
};
module_platform_driver(aspeed_lpc_ctrl_driver);
MODULE_DEVICE_TABLE(of, aspeed_lpc_ctrl_match);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Cyril Bur <[email protected]>");
MODULE_DESCRIPTION("Control for ASPEED LPC HOST to BMC mappings");
|
linux-master
|
drivers/soc/aspeed/aspeed-lpc-ctrl.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 Google Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Provides a simple driver to control the ASPEED P2A interface which allows
* the host to read and write to various regions of the BMC's memory.
*/
#include <linux/fs.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/miscdevice.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/aspeed-p2a-ctrl.h>
#define DEVICE_NAME "aspeed-p2a-ctrl"
/* SCU2C is a Misc. Control Register. */
#define SCU2C 0x2c
/* SCU180 is the PCIe Configuration Setting Control Register. */
#define SCU180 0x180
/* Bit 1 controls the P2A bridge, while bit 0 controls the entire VGA device
* on the PCI bus.
*/
#define SCU180_ENP2A BIT(1)
/* The ast2400/2500 both have six ranges. */
#define P2A_REGION_COUNT 6
struct region {
u64 min;
u64 max;
u32 bit;
};
struct aspeed_p2a_model_data {
/* min, max, bit */
struct region regions[P2A_REGION_COUNT];
};
struct aspeed_p2a_ctrl {
struct miscdevice miscdev;
struct regmap *regmap;
const struct aspeed_p2a_model_data *config;
/* Access to these needs to be locked, held via probe, mapping ioctl,
* and release, remove.
*/
struct mutex tracking;
u32 readers;
u32 readerwriters[P2A_REGION_COUNT];
phys_addr_t mem_base;
resource_size_t mem_size;
};
struct aspeed_p2a_user {
struct file *file;
struct aspeed_p2a_ctrl *parent;
/* The entire memory space is opened for reading once the bridge is
* enabled, therefore this needs only to be tracked once per user.
* If any user has it open for read, the bridge must stay enabled.
*/
u32 read;
/* Each entry of the array corresponds to a P2A Region. If the user
* opens for read or readwrite, the reference goes up here. On
* release, this array is walked and references adjusted accordingly.
*/
u32 readwrite[P2A_REGION_COUNT];
};
static void aspeed_p2a_enable_bridge(struct aspeed_p2a_ctrl *p2a_ctrl)
{
regmap_update_bits(p2a_ctrl->regmap,
SCU180, SCU180_ENP2A, SCU180_ENP2A);
}
static void aspeed_p2a_disable_bridge(struct aspeed_p2a_ctrl *p2a_ctrl)
{
regmap_update_bits(p2a_ctrl->regmap, SCU180, SCU180_ENP2A, 0);
}
static int aspeed_p2a_mmap(struct file *file, struct vm_area_struct *vma)
{
unsigned long vsize;
pgprot_t prot;
struct aspeed_p2a_user *priv = file->private_data;
struct aspeed_p2a_ctrl *ctrl = priv->parent;
if (ctrl->mem_base == 0 && ctrl->mem_size == 0)
return -EINVAL;
vsize = vma->vm_end - vma->vm_start;
prot = vma->vm_page_prot;
if (vma->vm_pgoff + vma_pages(vma) > ctrl->mem_size >> PAGE_SHIFT)
return -EINVAL;
/* ast2400/2500 AHB accesses are not cache coherent */
prot = pgprot_noncached(prot);
if (remap_pfn_range(vma, vma->vm_start,
(ctrl->mem_base >> PAGE_SHIFT) + vma->vm_pgoff,
vsize, prot))
return -EAGAIN;
return 0;
}
static bool aspeed_p2a_region_acquire(struct aspeed_p2a_user *priv,
struct aspeed_p2a_ctrl *ctrl,
struct aspeed_p2a_ctrl_mapping *map)
{
int i;
u64 base, end;
bool matched = false;
base = map->addr;
end = map->addr + (map->length - 1);
/* If the value is a legal u32, it will find a match. */
for (i = 0; i < P2A_REGION_COUNT; i++) {
const struct region *curr = &ctrl->config->regions[i];
/* If the top of this region is lower than your base, skip it.
*/
if (curr->max < base)
continue;
/* If the bottom of this region is higher than your end, bail.
*/
if (curr->min > end)
break;
/* Lock this and update it, therefore it someone else is
* closing their file out, this'll preserve the increment.
*/
mutex_lock(&ctrl->tracking);
ctrl->readerwriters[i] += 1;
mutex_unlock(&ctrl->tracking);
/* Track with the user, so when they close their file, we can
* decrement properly.
*/
priv->readwrite[i] += 1;
/* Enable the region as read-write. */
regmap_update_bits(ctrl->regmap, SCU2C, curr->bit, 0);
matched = true;
}
return matched;
}
static long aspeed_p2a_ioctl(struct file *file, unsigned int cmd,
unsigned long data)
{
struct aspeed_p2a_user *priv = file->private_data;
struct aspeed_p2a_ctrl *ctrl = priv->parent;
void __user *arg = (void __user *)data;
struct aspeed_p2a_ctrl_mapping map;
if (copy_from_user(&map, arg, sizeof(map)))
return -EFAULT;
switch (cmd) {
case ASPEED_P2A_CTRL_IOCTL_SET_WINDOW:
/* If they want a region to be read-only, since the entire
* region is read-only once enabled, we just need to track this
* user wants to read from the bridge, and if it's not enabled.
* Enable it.
*/
if (map.flags == ASPEED_P2A_CTRL_READ_ONLY) {
mutex_lock(&ctrl->tracking);
ctrl->readers += 1;
mutex_unlock(&ctrl->tracking);
/* Track with the user, so when they close their file,
* we can decrement properly.
*/
priv->read += 1;
} else if (map.flags == ASPEED_P2A_CTRL_READWRITE) {
/* If we don't acquire any region return error. */
if (!aspeed_p2a_region_acquire(priv, ctrl, &map)) {
return -EINVAL;
}
} else {
/* Invalid map flags. */
return -EINVAL;
}
aspeed_p2a_enable_bridge(ctrl);
return 0;
case ASPEED_P2A_CTRL_IOCTL_GET_MEMORY_CONFIG:
/* This is a request for the memory-region and corresponding
* length that is used by the driver for mmap.
*/
map.flags = 0;
map.addr = ctrl->mem_base;
map.length = ctrl->mem_size;
return copy_to_user(arg, &map, sizeof(map)) ? -EFAULT : 0;
}
return -EINVAL;
}
/*
* When a user opens this file, we create a structure to track their mappings.
*
* A user can map a region as read-only (bridge enabled), or read-write (bit
* flipped, and bridge enabled). Either way, this tracking is used, s.t. when
* they release the device references are handled.
*
* The bridge is not enabled until a user calls an ioctl to map a region,
* simply opening the device does not enable it.
*/
static int aspeed_p2a_open(struct inode *inode, struct file *file)
{
struct aspeed_p2a_user *priv;
priv = kmalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->file = file;
priv->read = 0;
memset(priv->readwrite, 0, sizeof(priv->readwrite));
/* The file's private_data is initialized to the p2a_ctrl. */
priv->parent = file->private_data;
/* Set the file's private_data to the user's data. */
file->private_data = priv;
return 0;
}
/*
* This will close the users mappings. It will go through what they had opened
* for readwrite, and decrement those counts. If at the end, this is the last
* user, it'll close the bridge.
*/
static int aspeed_p2a_release(struct inode *inode, struct file *file)
{
int i;
u32 bits = 0;
bool open_regions = false;
struct aspeed_p2a_user *priv = file->private_data;
/* Lock others from changing these values until everything is updated
* in one pass.
*/
mutex_lock(&priv->parent->tracking);
priv->parent->readers -= priv->read;
for (i = 0; i < P2A_REGION_COUNT; i++) {
priv->parent->readerwriters[i] -= priv->readwrite[i];
if (priv->parent->readerwriters[i] > 0)
open_regions = true;
else
bits |= priv->parent->config->regions[i].bit;
}
/* Setting a bit to 1 disables the region, so let's just OR with the
* above to disable any.
*/
/* Note, if another user is trying to ioctl, they can't grab tracking,
* and therefore can't grab either register mutex.
* If another user is trying to close, they can't grab tracking either.
*/
regmap_update_bits(priv->parent->regmap, SCU2C, bits, bits);
/* If parent->readers is zero and open windows is 0, disable the
* bridge.
*/
if (!open_regions && priv->parent->readers == 0)
aspeed_p2a_disable_bridge(priv->parent);
mutex_unlock(&priv->parent->tracking);
kfree(priv);
return 0;
}
static const struct file_operations aspeed_p2a_ctrl_fops = {
.owner = THIS_MODULE,
.mmap = aspeed_p2a_mmap,
.unlocked_ioctl = aspeed_p2a_ioctl,
.open = aspeed_p2a_open,
.release = aspeed_p2a_release,
};
/* The regions are controlled by SCU2C */
static void aspeed_p2a_disable_all(struct aspeed_p2a_ctrl *p2a_ctrl)
{
int i;
u32 value = 0;
for (i = 0; i < P2A_REGION_COUNT; i++)
value |= p2a_ctrl->config->regions[i].bit;
regmap_update_bits(p2a_ctrl->regmap, SCU2C, value, value);
/* Disable the bridge. */
aspeed_p2a_disable_bridge(p2a_ctrl);
}
static int aspeed_p2a_ctrl_probe(struct platform_device *pdev)
{
struct aspeed_p2a_ctrl *misc_ctrl;
struct device *dev;
struct resource resm;
struct device_node *node;
int rc = 0;
dev = &pdev->dev;
misc_ctrl = devm_kzalloc(dev, sizeof(*misc_ctrl), GFP_KERNEL);
if (!misc_ctrl)
return -ENOMEM;
mutex_init(&misc_ctrl->tracking);
/* optional. */
node = of_parse_phandle(dev->of_node, "memory-region", 0);
if (node) {
rc = of_address_to_resource(node, 0, &resm);
of_node_put(node);
if (rc) {
dev_err(dev, "Couldn't address to resource for reserved memory\n");
return -ENODEV;
}
misc_ctrl->mem_size = resource_size(&resm);
misc_ctrl->mem_base = resm.start;
}
misc_ctrl->regmap = syscon_node_to_regmap(pdev->dev.parent->of_node);
if (IS_ERR(misc_ctrl->regmap)) {
dev_err(dev, "Couldn't get regmap\n");
return -ENODEV;
}
misc_ctrl->config = of_device_get_match_data(dev);
dev_set_drvdata(&pdev->dev, misc_ctrl);
aspeed_p2a_disable_all(misc_ctrl);
misc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR;
misc_ctrl->miscdev.name = DEVICE_NAME;
misc_ctrl->miscdev.fops = &aspeed_p2a_ctrl_fops;
misc_ctrl->miscdev.parent = dev;
rc = misc_register(&misc_ctrl->miscdev);
if (rc)
dev_err(dev, "Unable to register device\n");
return rc;
}
static int aspeed_p2a_ctrl_remove(struct platform_device *pdev)
{
struct aspeed_p2a_ctrl *p2a_ctrl = dev_get_drvdata(&pdev->dev);
misc_deregister(&p2a_ctrl->miscdev);
return 0;
}
#define SCU2C_DRAM BIT(25)
#define SCU2C_SPI BIT(24)
#define SCU2C_SOC BIT(23)
#define SCU2C_FLASH BIT(22)
static const struct aspeed_p2a_model_data ast2400_model_data = {
.regions = {
{0x00000000, 0x17FFFFFF, SCU2C_FLASH},
{0x18000000, 0x1FFFFFFF, SCU2C_SOC},
{0x20000000, 0x2FFFFFFF, SCU2C_FLASH},
{0x30000000, 0x3FFFFFFF, SCU2C_SPI},
{0x40000000, 0x5FFFFFFF, SCU2C_DRAM},
{0x60000000, 0xFFFFFFFF, SCU2C_SOC},
}
};
static const struct aspeed_p2a_model_data ast2500_model_data = {
.regions = {
{0x00000000, 0x0FFFFFFF, SCU2C_FLASH},
{0x10000000, 0x1FFFFFFF, SCU2C_SOC},
{0x20000000, 0x3FFFFFFF, SCU2C_FLASH},
{0x40000000, 0x5FFFFFFF, SCU2C_SOC},
{0x60000000, 0x7FFFFFFF, SCU2C_SPI},
{0x80000000, 0xFFFFFFFF, SCU2C_DRAM},
}
};
static const struct of_device_id aspeed_p2a_ctrl_match[] = {
{ .compatible = "aspeed,ast2400-p2a-ctrl",
.data = &ast2400_model_data },
{ .compatible = "aspeed,ast2500-p2a-ctrl",
.data = &ast2500_model_data },
{ },
};
static struct platform_driver aspeed_p2a_ctrl_driver = {
.driver = {
.name = DEVICE_NAME,
.of_match_table = aspeed_p2a_ctrl_match,
},
.probe = aspeed_p2a_ctrl_probe,
.remove = aspeed_p2a_ctrl_remove,
};
module_platform_driver(aspeed_p2a_ctrl_driver);
MODULE_DEVICE_TABLE(of, aspeed_p2a_ctrl_match);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Patrick Venture <[email protected]>");
MODULE_DESCRIPTION("Control for aspeed 2400/2500 P2A VGA HOST to BMC mappings");
|
linux-master
|
drivers/soc/aspeed/aspeed-p2a-ctrl.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2017 Google Inc
*
* Provides a simple driver to control the ASPEED LPC snoop interface which
* allows the BMC to listen on and save the data written by
* the host to an arbitrary LPC I/O port.
*
* Typically used by the BMC to "watch" host boot progress via port
* 0x80 writes made by the BIOS during the boot process.
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/kfifo.h>
#include <linux/mfd/syscon.h>
#include <linux/miscdevice.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/poll.h>
#include <linux/regmap.h>
#define DEVICE_NAME "aspeed-lpc-snoop"
#define NUM_SNOOP_CHANNELS 2
#define SNOOP_FIFO_SIZE 2048
#define HICR5 0x80
#define HICR5_EN_SNP0W BIT(0)
#define HICR5_ENINT_SNP0W BIT(1)
#define HICR5_EN_SNP1W BIT(2)
#define HICR5_ENINT_SNP1W BIT(3)
#define HICR6 0x84
#define HICR6_STR_SNP0W BIT(0)
#define HICR6_STR_SNP1W BIT(1)
#define SNPWADR 0x90
#define SNPWADR_CH0_MASK GENMASK(15, 0)
#define SNPWADR_CH0_SHIFT 0
#define SNPWADR_CH1_MASK GENMASK(31, 16)
#define SNPWADR_CH1_SHIFT 16
#define SNPWDR 0x94
#define SNPWDR_CH0_MASK GENMASK(7, 0)
#define SNPWDR_CH0_SHIFT 0
#define SNPWDR_CH1_MASK GENMASK(15, 8)
#define SNPWDR_CH1_SHIFT 8
#define HICRB 0x100
#define HICRB_ENSNP0D BIT(14)
#define HICRB_ENSNP1D BIT(15)
struct aspeed_lpc_snoop_model_data {
/* The ast2400 has bits 14 and 15 as reserved, whereas the ast2500
* can use them.
*/
unsigned int has_hicrb_ensnp;
};
struct aspeed_lpc_snoop_channel {
struct kfifo fifo;
wait_queue_head_t wq;
struct miscdevice miscdev;
};
struct aspeed_lpc_snoop {
struct regmap *regmap;
int irq;
struct clk *clk;
struct aspeed_lpc_snoop_channel chan[NUM_SNOOP_CHANNELS];
};
static struct aspeed_lpc_snoop_channel *snoop_file_to_chan(struct file *file)
{
return container_of(file->private_data,
struct aspeed_lpc_snoop_channel,
miscdev);
}
static ssize_t snoop_file_read(struct file *file, char __user *buffer,
size_t count, loff_t *ppos)
{
struct aspeed_lpc_snoop_channel *chan = snoop_file_to_chan(file);
unsigned int copied;
int ret = 0;
if (kfifo_is_empty(&chan->fifo)) {
if (file->f_flags & O_NONBLOCK)
return -EAGAIN;
ret = wait_event_interruptible(chan->wq,
!kfifo_is_empty(&chan->fifo));
if (ret == -ERESTARTSYS)
return -EINTR;
}
ret = kfifo_to_user(&chan->fifo, buffer, count, &copied);
if (ret)
return ret;
return copied;
}
static __poll_t snoop_file_poll(struct file *file,
struct poll_table_struct *pt)
{
struct aspeed_lpc_snoop_channel *chan = snoop_file_to_chan(file);
poll_wait(file, &chan->wq, pt);
return !kfifo_is_empty(&chan->fifo) ? EPOLLIN : 0;
}
static const struct file_operations snoop_fops = {
.owner = THIS_MODULE,
.read = snoop_file_read,
.poll = snoop_file_poll,
.llseek = noop_llseek,
};
/* Save a byte to a FIFO and discard the oldest byte if FIFO is full */
static void put_fifo_with_discard(struct aspeed_lpc_snoop_channel *chan, u8 val)
{
if (!kfifo_initialized(&chan->fifo))
return;
if (kfifo_is_full(&chan->fifo))
kfifo_skip(&chan->fifo);
kfifo_put(&chan->fifo, val);
wake_up_interruptible(&chan->wq);
}
static irqreturn_t aspeed_lpc_snoop_irq(int irq, void *arg)
{
struct aspeed_lpc_snoop *lpc_snoop = arg;
u32 reg, data;
if (regmap_read(lpc_snoop->regmap, HICR6, ®))
return IRQ_NONE;
/* Check if one of the snoop channels is interrupting */
reg &= (HICR6_STR_SNP0W | HICR6_STR_SNP1W);
if (!reg)
return IRQ_NONE;
/* Ack pending IRQs */
regmap_write(lpc_snoop->regmap, HICR6, reg);
/* Read and save most recent snoop'ed data byte to FIFO */
regmap_read(lpc_snoop->regmap, SNPWDR, &data);
if (reg & HICR6_STR_SNP0W) {
u8 val = (data & SNPWDR_CH0_MASK) >> SNPWDR_CH0_SHIFT;
put_fifo_with_discard(&lpc_snoop->chan[0], val);
}
if (reg & HICR6_STR_SNP1W) {
u8 val = (data & SNPWDR_CH1_MASK) >> SNPWDR_CH1_SHIFT;
put_fifo_with_discard(&lpc_snoop->chan[1], val);
}
return IRQ_HANDLED;
}
static int aspeed_lpc_snoop_config_irq(struct aspeed_lpc_snoop *lpc_snoop,
struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int rc;
lpc_snoop->irq = platform_get_irq(pdev, 0);
if (!lpc_snoop->irq)
return -ENODEV;
rc = devm_request_irq(dev, lpc_snoop->irq,
aspeed_lpc_snoop_irq, IRQF_SHARED,
DEVICE_NAME, lpc_snoop);
if (rc < 0) {
dev_warn(dev, "Unable to request IRQ %d\n", lpc_snoop->irq);
lpc_snoop->irq = 0;
return rc;
}
return 0;
}
static int aspeed_lpc_enable_snoop(struct aspeed_lpc_snoop *lpc_snoop,
struct device *dev,
int channel, u16 lpc_port)
{
int rc = 0;
u32 hicr5_en, snpwadr_mask, snpwadr_shift, hicrb_en;
const struct aspeed_lpc_snoop_model_data *model_data =
of_device_get_match_data(dev);
init_waitqueue_head(&lpc_snoop->chan[channel].wq);
/* Create FIFO datastructure */
rc = kfifo_alloc(&lpc_snoop->chan[channel].fifo,
SNOOP_FIFO_SIZE, GFP_KERNEL);
if (rc)
return rc;
lpc_snoop->chan[channel].miscdev.minor = MISC_DYNAMIC_MINOR;
lpc_snoop->chan[channel].miscdev.name =
devm_kasprintf(dev, GFP_KERNEL, "%s%d", DEVICE_NAME, channel);
lpc_snoop->chan[channel].miscdev.fops = &snoop_fops;
lpc_snoop->chan[channel].miscdev.parent = dev;
rc = misc_register(&lpc_snoop->chan[channel].miscdev);
if (rc)
return rc;
/* Enable LPC snoop channel at requested port */
switch (channel) {
case 0:
hicr5_en = HICR5_EN_SNP0W | HICR5_ENINT_SNP0W;
snpwadr_mask = SNPWADR_CH0_MASK;
snpwadr_shift = SNPWADR_CH0_SHIFT;
hicrb_en = HICRB_ENSNP0D;
break;
case 1:
hicr5_en = HICR5_EN_SNP1W | HICR5_ENINT_SNP1W;
snpwadr_mask = SNPWADR_CH1_MASK;
snpwadr_shift = SNPWADR_CH1_SHIFT;
hicrb_en = HICRB_ENSNP1D;
break;
default:
return -EINVAL;
}
regmap_update_bits(lpc_snoop->regmap, HICR5, hicr5_en, hicr5_en);
regmap_update_bits(lpc_snoop->regmap, SNPWADR, snpwadr_mask,
lpc_port << snpwadr_shift);
if (model_data->has_hicrb_ensnp)
regmap_update_bits(lpc_snoop->regmap, HICRB,
hicrb_en, hicrb_en);
return rc;
}
static void aspeed_lpc_disable_snoop(struct aspeed_lpc_snoop *lpc_snoop,
int channel)
{
switch (channel) {
case 0:
regmap_update_bits(lpc_snoop->regmap, HICR5,
HICR5_EN_SNP0W | HICR5_ENINT_SNP0W,
0);
break;
case 1:
regmap_update_bits(lpc_snoop->regmap, HICR5,
HICR5_EN_SNP1W | HICR5_ENINT_SNP1W,
0);
break;
default:
return;
}
kfifo_free(&lpc_snoop->chan[channel].fifo);
misc_deregister(&lpc_snoop->chan[channel].miscdev);
}
static int aspeed_lpc_snoop_probe(struct platform_device *pdev)
{
struct aspeed_lpc_snoop *lpc_snoop;
struct device *dev;
struct device_node *np;
u32 port;
int rc;
dev = &pdev->dev;
lpc_snoop = devm_kzalloc(dev, sizeof(*lpc_snoop), GFP_KERNEL);
if (!lpc_snoop)
return -ENOMEM;
np = pdev->dev.parent->of_node;
if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
!of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
!of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
dev_err(dev, "unsupported LPC device binding\n");
return -ENODEV;
}
lpc_snoop->regmap = syscon_node_to_regmap(np);
if (IS_ERR(lpc_snoop->regmap)) {
dev_err(dev, "Couldn't get regmap\n");
return -ENODEV;
}
dev_set_drvdata(&pdev->dev, lpc_snoop);
rc = of_property_read_u32_index(dev->of_node, "snoop-ports", 0, &port);
if (rc) {
dev_err(dev, "no snoop ports configured\n");
return -ENODEV;
}
lpc_snoop->clk = devm_clk_get(dev, NULL);
if (IS_ERR(lpc_snoop->clk)) {
rc = PTR_ERR(lpc_snoop->clk);
if (rc != -EPROBE_DEFER)
dev_err(dev, "couldn't get clock\n");
return rc;
}
rc = clk_prepare_enable(lpc_snoop->clk);
if (rc) {
dev_err(dev, "couldn't enable clock\n");
return rc;
}
rc = aspeed_lpc_snoop_config_irq(lpc_snoop, pdev);
if (rc)
goto err;
rc = aspeed_lpc_enable_snoop(lpc_snoop, dev, 0, port);
if (rc)
goto err;
/* Configuration of 2nd snoop channel port is optional */
if (of_property_read_u32_index(dev->of_node, "snoop-ports",
1, &port) == 0) {
rc = aspeed_lpc_enable_snoop(lpc_snoop, dev, 1, port);
if (rc) {
aspeed_lpc_disable_snoop(lpc_snoop, 0);
goto err;
}
}
return 0;
err:
clk_disable_unprepare(lpc_snoop->clk);
return rc;
}
static int aspeed_lpc_snoop_remove(struct platform_device *pdev)
{
struct aspeed_lpc_snoop *lpc_snoop = dev_get_drvdata(&pdev->dev);
/* Disable both snoop channels */
aspeed_lpc_disable_snoop(lpc_snoop, 0);
aspeed_lpc_disable_snoop(lpc_snoop, 1);
clk_disable_unprepare(lpc_snoop->clk);
return 0;
}
static const struct aspeed_lpc_snoop_model_data ast2400_model_data = {
.has_hicrb_ensnp = 0,
};
static const struct aspeed_lpc_snoop_model_data ast2500_model_data = {
.has_hicrb_ensnp = 1,
};
static const struct of_device_id aspeed_lpc_snoop_match[] = {
{ .compatible = "aspeed,ast2400-lpc-snoop",
.data = &ast2400_model_data },
{ .compatible = "aspeed,ast2500-lpc-snoop",
.data = &ast2500_model_data },
{ .compatible = "aspeed,ast2600-lpc-snoop",
.data = &ast2500_model_data },
{ },
};
static struct platform_driver aspeed_lpc_snoop_driver = {
.driver = {
.name = DEVICE_NAME,
.of_match_table = aspeed_lpc_snoop_match,
},
.probe = aspeed_lpc_snoop_probe,
.remove = aspeed_lpc_snoop_remove,
};
module_platform_driver(aspeed_lpc_snoop_driver);
MODULE_DEVICE_TABLE(of, aspeed_lpc_snoop_match);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Robert Lippert <[email protected]>");
MODULE_DESCRIPTION("Linux driver to control Aspeed LPC snoop functionality");
|
linux-master
|
drivers/soc/aspeed/aspeed-lpc-snoop.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2018 Google LLC
* Copyright (c) 2021 Aspeed Technology Inc.
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
/* register offsets */
#define HICR9 0x98
#define HICRA 0x9c
/* attributes options */
#define UART_ROUTING_IO1 "io1"
#define UART_ROUTING_IO2 "io2"
#define UART_ROUTING_IO3 "io3"
#define UART_ROUTING_IO4 "io4"
#define UART_ROUTING_IO5 "io5"
#define UART_ROUTING_IO6 "io6"
#define UART_ROUTING_IO10 "io10"
#define UART_ROUTING_UART1 "uart1"
#define UART_ROUTING_UART2 "uart2"
#define UART_ROUTING_UART3 "uart3"
#define UART_ROUTING_UART4 "uart4"
#define UART_ROUTING_UART5 "uart5"
#define UART_ROUTING_UART6 "uart6"
#define UART_ROUTING_UART10 "uart10"
#define UART_ROUTING_RES "reserved"
struct aspeed_uart_routing {
struct regmap *map;
struct attribute_group const *attr_grp;
};
struct aspeed_uart_routing_selector {
struct device_attribute dev_attr;
uint8_t reg;
uint8_t mask;
uint8_t shift;
const char *const options[];
};
#define to_routing_selector(_dev_attr) \
container_of(_dev_attr, struct aspeed_uart_routing_selector, dev_attr)
static ssize_t aspeed_uart_routing_show(struct device *dev,
struct device_attribute *attr,
char *buf);
static ssize_t aspeed_uart_routing_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count);
#define ROUTING_ATTR(_name) { \
.attr = {.name = _name, \
.mode = VERIFY_OCTAL_PERMISSIONS(0644) }, \
.show = aspeed_uart_routing_show, \
.store = aspeed_uart_routing_store, \
}
/* routing selector for AST25xx */
static struct aspeed_uart_routing_selector ast2500_io6_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_IO6),
.reg = HICR9,
.shift = 8,
.mask = 0xf,
.options = {
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_UART5,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_IO5,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2500_uart5_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_UART5),
.reg = HICRA,
.shift = 28,
.mask = 0xf,
.options = {
UART_ROUTING_IO5,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_IO6,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2500_uart4_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_UART4),
.reg = HICRA,
.shift = 25,
.mask = 0x7,
.options = {
UART_ROUTING_IO4,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO3,
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_IO6,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2500_uart3_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_UART3),
.reg = HICRA,
.shift = 22,
.mask = 0x7,
.options = {
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_UART4,
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_IO6,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2500_uart2_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_UART2),
.reg = HICRA,
.shift = 19,
.mask = 0x7,
.options = {
UART_ROUTING_IO2,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_IO1,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_UART1,
UART_ROUTING_IO6,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2500_uart1_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_UART1),
.reg = HICRA,
.shift = 16,
.mask = 0x7,
.options = {
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_IO6,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2500_io5_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_IO5),
.reg = HICRA,
.shift = 12,
.mask = 0x7,
.options = {
UART_ROUTING_UART5,
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_IO1,
UART_ROUTING_IO3,
UART_ROUTING_IO6,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2500_io4_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_IO4),
.reg = HICRA,
.shift = 9,
.mask = 0x7,
.options = {
UART_ROUTING_UART4,
UART_ROUTING_UART5,
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO6,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2500_io3_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_IO3),
.reg = HICRA,
.shift = 6,
.mask = 0x7,
.options = {
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_UART5,
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO6,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2500_io2_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_IO2),
.reg = HICRA,
.shift = 3,
.mask = 0x7,
.options = {
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_UART5,
UART_ROUTING_UART1,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_IO6,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2500_io1_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_IO1),
.reg = HICRA,
.shift = 0,
.mask = 0x7,
.options = {
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_UART5,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_IO6,
NULL,
},
};
static struct attribute *ast2500_uart_routing_attrs[] = {
&ast2500_io6_sel.dev_attr.attr,
&ast2500_uart5_sel.dev_attr.attr,
&ast2500_uart4_sel.dev_attr.attr,
&ast2500_uart3_sel.dev_attr.attr,
&ast2500_uart2_sel.dev_attr.attr,
&ast2500_uart1_sel.dev_attr.attr,
&ast2500_io5_sel.dev_attr.attr,
&ast2500_io4_sel.dev_attr.attr,
&ast2500_io3_sel.dev_attr.attr,
&ast2500_io2_sel.dev_attr.attr,
&ast2500_io1_sel.dev_attr.attr,
NULL,
};
static const struct attribute_group ast2500_uart_routing_attr_group = {
.attrs = ast2500_uart_routing_attrs,
};
/* routing selector for AST26xx */
static struct aspeed_uart_routing_selector ast2600_uart10_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_UART10),
.reg = HICR9,
.shift = 12,
.mask = 0xf,
.options = {
UART_ROUTING_IO10,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_RES,
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2600_io10_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_IO10),
.reg = HICR9,
.shift = 8,
.mask = 0xf,
.options = {
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_RES,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_RES,
UART_ROUTING_UART10,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2600_uart4_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_UART4),
.reg = HICRA,
.shift = 25,
.mask = 0x7,
.options = {
UART_ROUTING_IO4,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO3,
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_IO10,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2600_uart3_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_UART3),
.reg = HICRA,
.shift = 22,
.mask = 0x7,
.options = {
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_UART4,
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_IO10,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2600_uart2_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_UART2),
.reg = HICRA,
.shift = 19,
.mask = 0x7,
.options = {
UART_ROUTING_IO2,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_IO1,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_UART1,
UART_ROUTING_IO10,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2600_uart1_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_UART1),
.reg = HICRA,
.shift = 16,
.mask = 0x7,
.options = {
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_IO10,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2600_io4_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_IO4),
.reg = HICRA,
.shift = 9,
.mask = 0x7,
.options = {
UART_ROUTING_UART4,
UART_ROUTING_UART10,
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO10,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2600_io3_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_IO3),
.reg = HICRA,
.shift = 6,
.mask = 0x7,
.options = {
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_UART10,
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_IO1,
UART_ROUTING_IO2,
UART_ROUTING_IO10,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2600_io2_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_IO2),
.reg = HICRA,
.shift = 3,
.mask = 0x7,
.options = {
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_UART10,
UART_ROUTING_UART1,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_IO10,
NULL,
},
};
static struct aspeed_uart_routing_selector ast2600_io1_sel = {
.dev_attr = ROUTING_ATTR(UART_ROUTING_IO1),
.reg = HICRA,
.shift = 0,
.mask = 0x7,
.options = {
UART_ROUTING_UART1,
UART_ROUTING_UART2,
UART_ROUTING_UART3,
UART_ROUTING_UART4,
UART_ROUTING_UART10,
UART_ROUTING_IO3,
UART_ROUTING_IO4,
UART_ROUTING_IO10,
NULL,
},
};
static struct attribute *ast2600_uart_routing_attrs[] = {
&ast2600_uart10_sel.dev_attr.attr,
&ast2600_io10_sel.dev_attr.attr,
&ast2600_uart4_sel.dev_attr.attr,
&ast2600_uart3_sel.dev_attr.attr,
&ast2600_uart2_sel.dev_attr.attr,
&ast2600_uart1_sel.dev_attr.attr,
&ast2600_io4_sel.dev_attr.attr,
&ast2600_io3_sel.dev_attr.attr,
&ast2600_io2_sel.dev_attr.attr,
&ast2600_io1_sel.dev_attr.attr,
NULL,
};
static const struct attribute_group ast2600_uart_routing_attr_group = {
.attrs = ast2600_uart_routing_attrs,
};
static ssize_t aspeed_uart_routing_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev);
struct aspeed_uart_routing_selector *sel = to_routing_selector(attr);
int val, pos, len;
regmap_read(uart_routing->map, sel->reg, &val);
val = (val >> sel->shift) & sel->mask;
len = 0;
for (pos = 0; sel->options[pos] != NULL; ++pos) {
if (pos == val)
len += sysfs_emit_at(buf, len, "[%s] ", sel->options[pos]);
else
len += sysfs_emit_at(buf, len, "%s ", sel->options[pos]);
}
if (val >= pos)
len += sysfs_emit_at(buf, len, "[unknown(%d)]", val);
len += sysfs_emit_at(buf, len, "\n");
return len;
}
static ssize_t aspeed_uart_routing_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev);
struct aspeed_uart_routing_selector *sel = to_routing_selector(attr);
int val;
val = __sysfs_match_string(sel->options, -1, buf);
if (val < 0) {
dev_err(dev, "invalid value \"%s\"\n", buf);
return -EINVAL;
}
regmap_update_bits(uart_routing->map, sel->reg,
(sel->mask << sel->shift),
(val & sel->mask) << sel->shift);
return count;
}
static int aspeed_uart_routing_probe(struct platform_device *pdev)
{
int rc;
struct device *dev = &pdev->dev;
struct aspeed_uart_routing *uart_routing;
uart_routing = devm_kzalloc(&pdev->dev, sizeof(*uart_routing), GFP_KERNEL);
if (!uart_routing)
return -ENOMEM;
uart_routing->map = syscon_node_to_regmap(dev->parent->of_node);
if (IS_ERR(uart_routing->map)) {
dev_err(dev, "cannot get regmap\n");
return PTR_ERR(uart_routing->map);
}
uart_routing->attr_grp = of_device_get_match_data(dev);
rc = sysfs_create_group(&dev->kobj, uart_routing->attr_grp);
if (rc < 0)
return rc;
dev_set_drvdata(dev, uart_routing);
dev_info(dev, "module loaded\n");
return 0;
}
static int aspeed_uart_routing_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct aspeed_uart_routing *uart_routing = platform_get_drvdata(pdev);
sysfs_remove_group(&dev->kobj, uart_routing->attr_grp);
return 0;
}
static const struct of_device_id aspeed_uart_routing_table[] = {
{ .compatible = "aspeed,ast2400-uart-routing",
.data = &ast2500_uart_routing_attr_group },
{ .compatible = "aspeed,ast2500-uart-routing",
.data = &ast2500_uart_routing_attr_group },
{ .compatible = "aspeed,ast2600-uart-routing",
.data = &ast2600_uart_routing_attr_group },
{ },
};
static struct platform_driver aspeed_uart_routing_driver = {
.driver = {
.name = "aspeed-uart-routing",
.of_match_table = aspeed_uart_routing_table,
},
.probe = aspeed_uart_routing_probe,
.remove = aspeed_uart_routing_remove,
};
module_platform_driver(aspeed_uart_routing_driver);
MODULE_AUTHOR("Oskar Senft <[email protected]>");
MODULE_AUTHOR("Chia-Wei Wang <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Driver to configure Aspeed UART routing");
|
linux-master
|
drivers/soc/aspeed/aspeed-uart-routing.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/* Copyright 2019 IBM Corp. */
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
static struct {
const char *name;
const u32 id;
} const rev_table[] = {
/* AST2400 */
{ "AST2400", 0x02000303 },
{ "AST1400", 0x02010103 },
{ "AST1250", 0x02010303 },
/* AST2500 */
{ "AST2500", 0x04000303 },
{ "AST2510", 0x04000103 },
{ "AST2520", 0x04000203 },
{ "AST2530", 0x04000403 },
/* AST2600 */
{ "AST2600", 0x05000303 },
{ "AST2620", 0x05010203 },
{ "AST2605", 0x05030103 },
{ "AST2625", 0x05030403 },
};
static const char *siliconid_to_name(u32 siliconid)
{
unsigned int id = siliconid & 0xff00ffff;
unsigned int i;
for (i = 0 ; i < ARRAY_SIZE(rev_table) ; ++i) {
if (rev_table[i].id == id)
return rev_table[i].name;
}
return "Unknown";
}
static const char *siliconid_to_rev(u32 siliconid)
{
unsigned int rev = (siliconid >> 16) & 0xff;
unsigned int gen = (siliconid >> 24) & 0xff;
if (gen < 0x5) {
/* AST2500 and below */
switch (rev) {
case 0:
return "A0";
case 1:
return "A1";
case 3:
return "A2";
}
} else {
/* AST2600 */
switch (rev) {
case 0:
return "A0";
case 1:
return "A1";
case 2:
return "A2";
case 3:
return "A3";
}
}
return "??";
}
static int __init aspeed_socinfo_init(void)
{
struct soc_device_attribute *attrs;
struct soc_device *soc_dev;
struct device_node *np;
void __iomem *reg;
bool has_chipid = false;
u32 siliconid;
u32 chipid[2];
const char *machine = NULL;
np = of_find_compatible_node(NULL, NULL, "aspeed,silicon-id");
if (!of_device_is_available(np)) {
of_node_put(np);
return -ENODEV;
}
reg = of_iomap(np, 0);
if (!reg) {
of_node_put(np);
return -ENODEV;
}
siliconid = readl(reg);
iounmap(reg);
/* This is optional, the ast2400 does not have it */
reg = of_iomap(np, 1);
if (reg) {
has_chipid = true;
chipid[0] = readl(reg);
chipid[1] = readl(reg + 4);
iounmap(reg);
}
of_node_put(np);
attrs = kzalloc(sizeof(*attrs), GFP_KERNEL);
if (!attrs)
return -ENODEV;
/*
* Machine: Romulus BMC
* Family: AST2500
* Revision: A1
* SoC ID: raw silicon revision id
* Serial Number: 64-bit chipid
*/
np = of_find_node_by_path("/");
of_property_read_string(np, "model", &machine);
if (machine)
attrs->machine = kstrdup(machine, GFP_KERNEL);
of_node_put(np);
attrs->family = siliconid_to_name(siliconid);
attrs->revision = siliconid_to_rev(siliconid);
attrs->soc_id = kasprintf(GFP_KERNEL, "%08x", siliconid);
if (has_chipid)
attrs->serial_number = kasprintf(GFP_KERNEL, "%08x%08x",
chipid[1], chipid[0]);
soc_dev = soc_device_register(attrs);
if (IS_ERR(soc_dev)) {
kfree(attrs->machine);
kfree(attrs->soc_id);
kfree(attrs->serial_number);
kfree(attrs);
return PTR_ERR(soc_dev);
}
pr_info("ASPEED %s rev %s (%s)\n",
attrs->family,
attrs->revision,
attrs->soc_id);
return 0;
}
early_initcall(aspeed_socinfo_init);
|
linux-master
|
drivers/soc/aspeed/aspeed-socinfo.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* LiteX SoC Controller Driver
*
* Copyright (C) 2020 Antmicro <www.antmicro.com>
*
*/
#include <linux/litex.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/printk.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/reboot.h>
/* reset register located at the base address */
#define RESET_REG_OFF 0x00
#define RESET_REG_VALUE 0x00000001
#define SCRATCH_REG_OFF 0x04
#define SCRATCH_REG_VALUE 0x12345678
#define SCRATCH_TEST_VALUE 0xdeadbeef
/*
* Check LiteX CSR read/write access
*
* This function reads and writes a scratch register in order to verify if CSR
* access works.
*
* In case any problems are detected, the driver should panic.
*
* Access to the LiteX CSR is, by design, done in CPU native endianness.
* The driver should not dynamically configure access functions when
* the endianness mismatch is detected. Such situation indicates problems in
* the soft SoC design and should be solved at the LiteX generator level,
* not in the software.
*/
static int litex_check_csr_access(void __iomem *reg_addr)
{
unsigned long reg;
reg = litex_read32(reg_addr + SCRATCH_REG_OFF);
if (reg != SCRATCH_REG_VALUE) {
panic("Scratch register read error - the system is probably broken! Expected: 0x%x but got: 0x%lx",
SCRATCH_REG_VALUE, reg);
return -EINVAL;
}
litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_TEST_VALUE);
reg = litex_read32(reg_addr + SCRATCH_REG_OFF);
if (reg != SCRATCH_TEST_VALUE) {
panic("Scratch register write error - the system is probably broken! Expected: 0x%x but got: 0x%lx",
SCRATCH_TEST_VALUE, reg);
return -EINVAL;
}
/* restore original value of the SCRATCH register */
litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_VALUE);
pr_info("LiteX SoC Controller driver initialized");
return 0;
}
struct litex_soc_ctrl_device {
void __iomem *base;
struct notifier_block reset_nb;
};
static int litex_reset_handler(struct notifier_block *this, unsigned long mode,
void *cmd)
{
struct litex_soc_ctrl_device *soc_ctrl_dev =
container_of(this, struct litex_soc_ctrl_device, reset_nb);
litex_write32(soc_ctrl_dev->base + RESET_REG_OFF, RESET_REG_VALUE);
return NOTIFY_DONE;
}
#ifdef CONFIG_OF
static const struct of_device_id litex_soc_ctrl_of_match[] = {
{.compatible = "litex,soc-controller"},
{},
};
MODULE_DEVICE_TABLE(of, litex_soc_ctrl_of_match);
#endif /* CONFIG_OF */
static int litex_soc_ctrl_probe(struct platform_device *pdev)
{
struct litex_soc_ctrl_device *soc_ctrl_dev;
int error;
soc_ctrl_dev = devm_kzalloc(&pdev->dev, sizeof(*soc_ctrl_dev), GFP_KERNEL);
if (!soc_ctrl_dev)
return -ENOMEM;
soc_ctrl_dev->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(soc_ctrl_dev->base))
return PTR_ERR(soc_ctrl_dev->base);
error = litex_check_csr_access(soc_ctrl_dev->base);
if (error)
return error;
platform_set_drvdata(pdev, soc_ctrl_dev);
soc_ctrl_dev->reset_nb.notifier_call = litex_reset_handler;
soc_ctrl_dev->reset_nb.priority = 128;
error = register_restart_handler(&soc_ctrl_dev->reset_nb);
if (error) {
dev_warn(&pdev->dev, "cannot register restart handler: %d\n",
error);
}
return 0;
}
static int litex_soc_ctrl_remove(struct platform_device *pdev)
{
struct litex_soc_ctrl_device *soc_ctrl_dev = platform_get_drvdata(pdev);
unregister_restart_handler(&soc_ctrl_dev->reset_nb);
return 0;
}
static struct platform_driver litex_soc_ctrl_driver = {
.driver = {
.name = "litex-soc-controller",
.of_match_table = of_match_ptr(litex_soc_ctrl_of_match)
},
.probe = litex_soc_ctrl_probe,
.remove = litex_soc_ctrl_remove,
};
module_platform_driver(litex_soc_ctrl_driver);
MODULE_DESCRIPTION("LiteX SoC Controller driver");
MODULE_AUTHOR("Antmicro <www.antmicro.com>");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/soc/litex/litex_soc_ctrl.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* R9A06G032 Second CA7 enabler.
*
* Copyright (C) 2018 Renesas Electronics Europe Limited
*
* Michel Pollet <[email protected]>, <[email protected]>
* Derived from actions,s500-smp
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/smp.h>
/*
* The second CPU is parked in ROM at boot time. It requires waking it after
* writing an address into the BOOTADDR register of sysctrl.
*
* So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
*
* *However* the BOOTADDR register is not available when the kernel
* starts in NONSEC mode.
*
* So for NONSEC mode, the bootloader re-parks the second CPU into a pen
* in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
* which is not restricted.
*/
static void __iomem *cpu_bootaddr;
static DEFINE_SPINLOCK(cpu_lock);
static int
r9a06g032_smp_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
if (!cpu_bootaddr)
return -ENODEV;
spin_lock(&cpu_lock);
writel(__pa_symbol(secondary_startup), cpu_bootaddr);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
spin_unlock(&cpu_lock);
return 0;
}
static void __init r9a06g032_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *dn;
int ret = -EINVAL, dns;
u32 bootaddr;
dn = of_get_cpu_node(1, NULL);
if (!dn) {
pr_err("CPU#1: missing device tree node\n");
return;
}
/*
* Determine the address from which the CPU is polling.
* The bootloader *does* change this property.
* Note: The property can be either 64 or 32 bits, so handle both cases
*/
if (of_find_property(dn, "cpu-release-addr", &dns)) {
if (dns == sizeof(u64)) {
u64 temp;
ret = of_property_read_u64(dn,
"cpu-release-addr", &temp);
bootaddr = temp;
} else {
ret = of_property_read_u32(dn,
"cpu-release-addr",
&bootaddr);
}
}
of_node_put(dn);
if (ret) {
pr_err("CPU#1: invalid cpu-release-addr property\n");
return;
}
pr_info("CPU#1: cpu-release-addr %08x\n", bootaddr);
cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr));
}
static const struct smp_operations r9a06g032_smp_ops __initconst = {
.smp_prepare_cpus = r9a06g032_smp_prepare_cpus,
.smp_boot_secondary = r9a06g032_smp_boot_secondary,
};
CPU_METHOD_OF_DECLARE(r9a06g032_smp,
"renesas,r9a06g032-smp", &r9a06g032_smp_ops);
|
linux-master
|
drivers/soc/renesas/r9a06g032-smp.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2023 Renesas Electronics Corporation
*/
#include <linux/delay.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#define PWC_PWCRST 0x00
#define PWC_PWCCKEN 0x04
#define PWC_PWCCTL 0x50
#define PWC_GPIO 0x80
#define PWC_PWCRST_RSTSOFTAX 0x1
#define PWC_PWCCKEN_ENGCKMAIN 0x1
#define PWC_PWCCTL_PWOFF 0x1
struct rzv2m_pwc_priv {
void __iomem *base;
struct device *dev;
struct gpio_chip gp;
DECLARE_BITMAP(ch_en_bits, 2);
};
static void rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct rzv2m_pwc_priv *priv = gpiochip_get_data(chip);
u32 reg;
/* BIT 16 enables write to BIT 0, and BIT 17 enables write to BIT 1 */
reg = BIT(offset + 16);
if (value)
reg |= BIT(offset);
writel(reg, priv->base + PWC_GPIO);
assign_bit(offset, priv->ch_en_bits, value);
}
static int rzv2m_pwc_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct rzv2m_pwc_priv *priv = gpiochip_get_data(chip);
return test_bit(offset, priv->ch_en_bits);
}
static int rzv2m_pwc_gpio_direction_output(struct gpio_chip *gc,
unsigned int nr, int value)
{
if (nr > 1)
return -EINVAL;
rzv2m_pwc_gpio_set(gc, nr, value);
return 0;
}
static const struct gpio_chip rzv2m_pwc_gc = {
.label = "gpio_rzv2m_pwc",
.owner = THIS_MODULE,
.get = rzv2m_pwc_gpio_get,
.set = rzv2m_pwc_gpio_set,
.direction_output = rzv2m_pwc_gpio_direction_output,
.can_sleep = false,
.ngpio = 2,
.base = -1,
};
static int rzv2m_pwc_poweroff(struct sys_off_data *data)
{
struct rzv2m_pwc_priv *priv = data->cb_data;
writel(PWC_PWCRST_RSTSOFTAX, priv->base + PWC_PWCRST);
writel(PWC_PWCCKEN_ENGCKMAIN, priv->base + PWC_PWCCKEN);
writel(PWC_PWCCTL_PWOFF, priv->base + PWC_PWCCTL);
mdelay(150);
dev_err(priv->dev, "Failed to power off the system");
return NOTIFY_DONE;
}
static int rzv2m_pwc_probe(struct platform_device *pdev)
{
struct rzv2m_pwc_priv *priv;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
/*
* The register used by this driver cannot be read, therefore set the
* outputs to their default values and initialize priv->ch_en_bits
* accordingly. BIT 16 enables write to BIT 0, BIT 17 enables write to
* BIT 1, and the default value of both BIT 0 and BIT 1 is 0.
*/
writel(BIT(17) | BIT(16), priv->base + PWC_GPIO);
bitmap_zero(priv->ch_en_bits, 2);
priv->gp = rzv2m_pwc_gc;
priv->gp.parent = pdev->dev.parent;
priv->gp.fwnode = dev_fwnode(&pdev->dev);
ret = devm_gpiochip_add_data(&pdev->dev, &priv->gp, priv);
if (ret)
return ret;
if (device_property_read_bool(&pdev->dev, "renesas,rzv2m-pwc-power"))
ret = devm_register_power_off_handler(&pdev->dev,
rzv2m_pwc_poweroff, priv);
return ret;
}
static const struct of_device_id rzv2m_pwc_of_match[] = {
{ .compatible = "renesas,rzv2m-pwc" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rzv2m_pwc_of_match);
static struct platform_driver rzv2m_pwc_driver = {
.probe = rzv2m_pwc_probe,
.driver = {
.name = "rzv2m_pwc",
.of_match_table = rzv2m_pwc_of_match,
},
};
module_platform_driver(rzv2m_pwc_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Fabrizio Castro <[email protected]>");
MODULE_DESCRIPTION("Renesas RZ/V2M PWC driver");
|
linux-master
|
drivers/soc/renesas/pwc-rzv2m.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas SoC Identification
*
* Copyright (C) 2014-2016 Glider bvba
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/sys_soc.h>
struct renesas_family {
const char name[16];
u32 reg; /* CCCR or PRR, if not in DT */
};
static const struct renesas_family fam_rcar_gen1 __initconst __maybe_unused = {
.name = "R-Car Gen1",
.reg = 0xff000044, /* PRR (Product Register) */
};
static const struct renesas_family fam_rcar_gen2 __initconst __maybe_unused = {
.name = "R-Car Gen2",
.reg = 0xff000044, /* PRR (Product Register) */
};
static const struct renesas_family fam_rcar_gen3 __initconst __maybe_unused = {
.name = "R-Car Gen3",
.reg = 0xfff00044, /* PRR (Product Register) */
};
static const struct renesas_family fam_rcar_gen4 __initconst __maybe_unused = {
.name = "R-Car Gen4",
};
static const struct renesas_family fam_rmobile __initconst __maybe_unused = {
.name = "R-Mobile",
.reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
};
static const struct renesas_family fam_rza1 __initconst __maybe_unused = {
.name = "RZ/A1",
};
static const struct renesas_family fam_rza2 __initconst __maybe_unused = {
.name = "RZ/A2",
};
static const struct renesas_family fam_rzfive __initconst __maybe_unused = {
.name = "RZ/Five",
};
static const struct renesas_family fam_rzg1 __initconst __maybe_unused = {
.name = "RZ/G1",
.reg = 0xff000044, /* PRR (Product Register) */
};
static const struct renesas_family fam_rzg2 __initconst __maybe_unused = {
.name = "RZ/G2",
.reg = 0xfff00044, /* PRR (Product Register) */
};
static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
.name = "RZ/G2L",
};
static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = {
.name = "RZ/G2UL",
};
static const struct renesas_family fam_rzv2l __initconst __maybe_unused = {
.name = "RZ/V2L",
};
static const struct renesas_family fam_rzv2m __initconst __maybe_unused = {
.name = "RZ/V2M",
};
static const struct renesas_family fam_shmobile __initconst __maybe_unused = {
.name = "SH-Mobile",
.reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
};
struct renesas_soc {
const struct renesas_family *family;
u32 id;
};
static const struct renesas_soc soc_rz_a1h __initconst __maybe_unused = {
.family = &fam_rza1,
};
static const struct renesas_soc soc_rz_a2m __initconst __maybe_unused = {
.family = &fam_rza2,
.id = 0x3b,
};
static const struct renesas_soc soc_rmobile_ape6 __initconst __maybe_unused = {
.family = &fam_rmobile,
.id = 0x3f,
};
static const struct renesas_soc soc_rmobile_a1 __initconst __maybe_unused = {
.family = &fam_rmobile,
.id = 0x40,
};
static const struct renesas_soc soc_rz_five __initconst __maybe_unused = {
.family = &fam_rzfive,
.id = 0x847c447,
};
static const struct renesas_soc soc_rz_g1h __initconst __maybe_unused = {
.family = &fam_rzg1,
.id = 0x45,
};
static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = {
.family = &fam_rzg1,
.id = 0x47,
};
static const struct renesas_soc soc_rz_g1n __initconst __maybe_unused = {
.family = &fam_rzg1,
.id = 0x4b,
};
static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
.family = &fam_rzg1,
.id = 0x4c,
};
static const struct renesas_soc soc_rz_g1c __initconst __maybe_unused = {
.family = &fam_rzg1,
.id = 0x53,
};
static const struct renesas_soc soc_rz_g2m __initconst __maybe_unused = {
.family = &fam_rzg2,
.id = 0x52,
};
static const struct renesas_soc soc_rz_g2n __initconst __maybe_unused = {
.family = &fam_rzg2,
.id = 0x55,
};
static const struct renesas_soc soc_rz_g2e __initconst __maybe_unused = {
.family = &fam_rzg2,
.id = 0x57,
};
static const struct renesas_soc soc_rz_g2h __initconst __maybe_unused = {
.family = &fam_rzg2,
.id = 0x4f,
};
static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = {
.family = &fam_rzg2l,
.id = 0x841c447,
};
static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = {
.family = &fam_rzg2ul,
.id = 0x8450447,
};
static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = {
.family = &fam_rzv2l,
.id = 0x8447447,
};
static const struct renesas_soc soc_rz_v2m __initconst __maybe_unused = {
.family = &fam_rzv2m,
};
static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
.family = &fam_rcar_gen1,
};
static const struct renesas_soc soc_rcar_h1 __initconst __maybe_unused = {
.family = &fam_rcar_gen1,
.id = 0x3b,
};
static const struct renesas_soc soc_rcar_h2 __initconst __maybe_unused = {
.family = &fam_rcar_gen2,
.id = 0x45,
};
static const struct renesas_soc soc_rcar_m2_w __initconst __maybe_unused = {
.family = &fam_rcar_gen2,
.id = 0x47,
};
static const struct renesas_soc soc_rcar_v2h __initconst __maybe_unused = {
.family = &fam_rcar_gen2,
.id = 0x4a,
};
static const struct renesas_soc soc_rcar_m2_n __initconst __maybe_unused = {
.family = &fam_rcar_gen2,
.id = 0x4b,
};
static const struct renesas_soc soc_rcar_e2 __initconst __maybe_unused = {
.family = &fam_rcar_gen2,
.id = 0x4c,
};
static const struct renesas_soc soc_rcar_h3 __initconst __maybe_unused = {
.family = &fam_rcar_gen3,
.id = 0x4f,
};
static const struct renesas_soc soc_rcar_m3_w __initconst __maybe_unused = {
.family = &fam_rcar_gen3,
.id = 0x52,
};
static const struct renesas_soc soc_rcar_m3_n __initconst __maybe_unused = {
.family = &fam_rcar_gen3,
.id = 0x55,
};
static const struct renesas_soc soc_rcar_v3m __initconst __maybe_unused = {
.family = &fam_rcar_gen3,
.id = 0x54,
};
static const struct renesas_soc soc_rcar_v3h __initconst __maybe_unused = {
.family = &fam_rcar_gen3,
.id = 0x56,
};
static const struct renesas_soc soc_rcar_e3 __initconst __maybe_unused = {
.family = &fam_rcar_gen3,
.id = 0x57,
};
static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
.family = &fam_rcar_gen3,
.id = 0x58,
};
static const struct renesas_soc soc_rcar_v3u __initconst __maybe_unused = {
.family = &fam_rcar_gen4,
.id = 0x59,
};
static const struct renesas_soc soc_rcar_s4 __initconst __maybe_unused = {
.family = &fam_rcar_gen4,
.id = 0x5a,
};
static const struct renesas_soc soc_rcar_v4h __initconst __maybe_unused = {
.family = &fam_rcar_gen4,
.id = 0x5c,
};
static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
.family = &fam_shmobile,
.id = 0x37,
};
static const struct of_device_id renesas_socs[] __initconst __maybe_unused = {
#ifdef CONFIG_ARCH_R7S72100
{ .compatible = "renesas,r7s72100", .data = &soc_rz_a1h },
#endif
#ifdef CONFIG_ARCH_R7S9210
{ .compatible = "renesas,r7s9210", .data = &soc_rz_a2m },
#endif
#ifdef CONFIG_ARCH_R8A73A4
{ .compatible = "renesas,r8a73a4", .data = &soc_rmobile_ape6 },
#endif
#ifdef CONFIG_ARCH_R8A7740
{ .compatible = "renesas,r8a7740", .data = &soc_rmobile_a1 },
#endif
#ifdef CONFIG_ARCH_R8A7742
{ .compatible = "renesas,r8a7742", .data = &soc_rz_g1h },
#endif
#ifdef CONFIG_ARCH_R8A7743
{ .compatible = "renesas,r8a7743", .data = &soc_rz_g1m },
#endif
#ifdef CONFIG_ARCH_R8A7744
{ .compatible = "renesas,r8a7744", .data = &soc_rz_g1n },
#endif
#ifdef CONFIG_ARCH_R8A7745
{ .compatible = "renesas,r8a7745", .data = &soc_rz_g1e },
#endif
#ifdef CONFIG_ARCH_R8A77470
{ .compatible = "renesas,r8a77470", .data = &soc_rz_g1c },
#endif
#ifdef CONFIG_ARCH_R8A774A1
{ .compatible = "renesas,r8a774a1", .data = &soc_rz_g2m },
#endif
#ifdef CONFIG_ARCH_R8A774B1
{ .compatible = "renesas,r8a774b1", .data = &soc_rz_g2n },
#endif
#ifdef CONFIG_ARCH_R8A774C0
{ .compatible = "renesas,r8a774c0", .data = &soc_rz_g2e },
#endif
#ifdef CONFIG_ARCH_R8A774E1
{ .compatible = "renesas,r8a774e1", .data = &soc_rz_g2h },
#endif
#ifdef CONFIG_ARCH_R8A7778
{ .compatible = "renesas,r8a7778", .data = &soc_rcar_m1a },
#endif
#ifdef CONFIG_ARCH_R8A7779
{ .compatible = "renesas,r8a7779", .data = &soc_rcar_h1 },
#endif
#ifdef CONFIG_ARCH_R8A7790
{ .compatible = "renesas,r8a7790", .data = &soc_rcar_h2 },
#endif
#ifdef CONFIG_ARCH_R8A7791
{ .compatible = "renesas,r8a7791", .data = &soc_rcar_m2_w },
#endif
#ifdef CONFIG_ARCH_R8A7792
{ .compatible = "renesas,r8a7792", .data = &soc_rcar_v2h },
#endif
#ifdef CONFIG_ARCH_R8A7793
{ .compatible = "renesas,r8a7793", .data = &soc_rcar_m2_n },
#endif
#ifdef CONFIG_ARCH_R8A7794
{ .compatible = "renesas,r8a7794", .data = &soc_rcar_e2 },
#endif
#ifdef CONFIG_ARCH_R8A77951
{ .compatible = "renesas,r8a7795", .data = &soc_rcar_h3 },
{ .compatible = "renesas,r8a779m0", .data = &soc_rcar_h3 },
{ .compatible = "renesas,r8a779m1", .data = &soc_rcar_h3 },
{ .compatible = "renesas,r8a779m8", .data = &soc_rcar_h3 },
{ .compatible = "renesas,r8a779mb", .data = &soc_rcar_h3 },
#endif
#ifdef CONFIG_ARCH_R8A77960
{ .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w },
#endif
#ifdef CONFIG_ARCH_R8A77961
{ .compatible = "renesas,r8a77961", .data = &soc_rcar_m3_w },
{ .compatible = "renesas,r8a779m2", .data = &soc_rcar_m3_w },
{ .compatible = "renesas,r8a779m3", .data = &soc_rcar_m3_w },
#endif
#ifdef CONFIG_ARCH_R8A77965
{ .compatible = "renesas,r8a77965", .data = &soc_rcar_m3_n },
{ .compatible = "renesas,r8a779m4", .data = &soc_rcar_m3_n },
{ .compatible = "renesas,r8a779m5", .data = &soc_rcar_m3_n },
#endif
#ifdef CONFIG_ARCH_R8A77970
{ .compatible = "renesas,r8a77970", .data = &soc_rcar_v3m },
#endif
#ifdef CONFIG_ARCH_R8A77980
{ .compatible = "renesas,r8a77980", .data = &soc_rcar_v3h },
#endif
#ifdef CONFIG_ARCH_R8A77990
{ .compatible = "renesas,r8a77990", .data = &soc_rcar_e3 },
{ .compatible = "renesas,r8a779m6", .data = &soc_rcar_e3 },
#endif
#ifdef CONFIG_ARCH_R8A77995
{ .compatible = "renesas,r8a77995", .data = &soc_rcar_d3 },
{ .compatible = "renesas,r8a779m7", .data = &soc_rcar_d3 },
#endif
#ifdef CONFIG_ARCH_R8A779A0
{ .compatible = "renesas,r8a779a0", .data = &soc_rcar_v3u },
#endif
#ifdef CONFIG_ARCH_R8A779F0
{ .compatible = "renesas,r8a779f0", .data = &soc_rcar_s4 },
#endif
#ifdef CONFIG_ARCH_R8A779G0
{ .compatible = "renesas,r8a779g0", .data = &soc_rcar_v4h },
#endif
#ifdef CONFIG_ARCH_R9A07G043
#ifdef CONFIG_RISCV
{ .compatible = "renesas,r9a07g043", .data = &soc_rz_five },
#else
{ .compatible = "renesas,r9a07g043", .data = &soc_rz_g2ul },
#endif
#endif
#ifdef CONFIG_ARCH_R9A07G044
{ .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l },
#endif
#ifdef CONFIG_ARCH_R9A07G054
{ .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l },
#endif
#ifdef CONFIG_ARCH_R9A09G011
{ .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m },
#endif
#ifdef CONFIG_ARCH_SH73A0
{ .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
#endif
{ /* sentinel */ }
};
struct renesas_id {
unsigned int offset;
u32 mask;
};
static const struct renesas_id id_bsid __initconst = {
.offset = 0,
.mask = 0xff0000,
/*
* TODO: Upper 4 bits of BSID are for chip version, but the format is
* not known at this time so we don't know how to specify eshi and eslo
*/
};
static const struct renesas_id id_rzg2l __initconst = {
.offset = 0xa04,
.mask = 0xfffffff,
};
static const struct renesas_id id_rzv2m __initconst = {
.offset = 0x104,
.mask = 0xff,
};
static const struct renesas_id id_prr __initconst = {
.offset = 0,
.mask = 0xff00,
};
static const struct of_device_id renesas_ids[] __initconst = {
{ .compatible = "renesas,bsid", .data = &id_bsid },
{ .compatible = "renesas,r9a07g043-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a09g011-sys", .data = &id_rzv2m },
{ .compatible = "renesas,prr", .data = &id_prr },
{ /* sentinel */ }
};
static int __init renesas_soc_init(void)
{
struct soc_device_attribute *soc_dev_attr;
unsigned int product, eshi = 0, eslo;
const struct renesas_family *family;
const struct of_device_id *match;
const struct renesas_soc *soc;
const struct renesas_id *id;
void __iomem *chipid = NULL;
const char *rev_prefix = "";
struct soc_device *soc_dev;
struct device_node *np;
const char *soc_id;
int ret;
match = of_match_node(renesas_socs, of_root);
if (!match)
return -ENODEV;
soc_id = strchr(match->compatible, ',') + 1;
soc = match->data;
family = soc->family;
np = of_find_matching_node_and_match(NULL, renesas_ids, &match);
if (np) {
id = match->data;
chipid = of_iomap(np, 0);
of_node_put(np);
} else if (soc->id && family->reg) {
/* Try hardcoded CCCR/PRR fallback */
id = &id_prr;
chipid = ioremap(family->reg, 4);
}
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr) {
if (chipid)
iounmap(chipid);
return -ENOMEM;
}
np = of_find_node_by_path("/");
of_property_read_string(np, "model", &soc_dev_attr->machine);
of_node_put(np);
soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL);
soc_dev_attr->soc_id = kstrdup_const(soc_id, GFP_KERNEL);
if (chipid) {
product = readl(chipid + id->offset);
iounmap(chipid);
if (id == &id_prr) {
/* R-Car M3-W ES1.1 incorrectly identifies as ES2.0 */
if ((product & 0x7fff) == 0x5210)
product ^= 0x11;
/* R-Car M3-W ES1.3 incorrectly identifies as ES2.1 */
if ((product & 0x7fff) == 0x5211)
product ^= 0x12;
eshi = ((product >> 4) & 0x0f) + 1;
eslo = product & 0xf;
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u",
eshi, eslo);
} else if (id == &id_rzg2l) {
eshi = ((product >> 28) & 0x0f);
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u",
eshi);
rev_prefix = "Rev ";
} else if (id == &id_rzv2m) {
eshi = ((product >> 4) & 0x0f);
eslo = product & 0xf;
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u.%u",
eshi, eslo);
}
if (soc->id &&
((product & id->mask) >> __ffs(id->mask)) != soc->id) {
pr_warn("SoC mismatch (product = 0x%x)\n", product);
ret = -ENODEV;
goto free_soc_dev_attr;
}
}
pr_info("Detected Renesas %s %s %s%s\n", soc_dev_attr->family,
soc_dev_attr->soc_id, rev_prefix, soc_dev_attr->revision ?: "");
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
ret = PTR_ERR(soc_dev);
goto free_soc_dev_attr;
}
return 0;
free_soc_dev_attr:
kfree(soc_dev_attr->revision);
kfree_const(soc_dev_attr->soc_id);
kfree_const(soc_dev_attr->family);
kfree(soc_dev_attr);
return ret;
}
early_initcall(renesas_soc_init);
|
linux-master
|
drivers/soc/renesas/renesas-soc.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
*
* Copyright (C) 2016 Glider bvba
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/soc/renesas/rcar-rst.h>
#define WDTRSTCR_RESET 0xA55A0002
#define WDTRSTCR 0x0054
#define GEN4_WDTRSTCR 0x0010
#define CR7BAR 0x0070
#define CR7BAREN BIT(4)
#define CR7BAR_MASK 0xFFFC0000
static void __iomem *rcar_rst_base;
static u32 saved_mode __initdata;
static int (*rcar_rst_set_rproc_boot_addr_func)(u64 boot_addr);
static int rcar_rst_enable_wdt_reset(void __iomem *base)
{
iowrite32(WDTRSTCR_RESET, base + WDTRSTCR);
return 0;
}
static int rcar_rst_v3u_enable_wdt_reset(void __iomem *base)
{
iowrite32(WDTRSTCR_RESET, base + GEN4_WDTRSTCR);
return 0;
}
/*
* Most of the R-Car Gen3 SoCs have an ARM Realtime Core.
* Firmware boot address has to be set in CR7BAR before
* starting the realtime core.
* Boot address must be aligned on a 256k boundary.
*/
static int rcar_rst_set_gen3_rproc_boot_addr(u64 boot_addr)
{
if (boot_addr & ~(u64)CR7BAR_MASK) {
pr_err("Invalid boot address got %llx\n", boot_addr);
return -EINVAL;
}
iowrite32(boot_addr, rcar_rst_base + CR7BAR);
iowrite32(boot_addr | CR7BAREN, rcar_rst_base + CR7BAR);
return 0;
}
struct rst_config {
unsigned int modemr; /* Mode Monitoring Register Offset */
int (*configure)(void __iomem *base); /* Platform specific config */
int (*set_rproc_boot_addr)(u64 boot_addr);
};
static const struct rst_config rcar_rst_gen1 __initconst = {
.modemr = 0x20,
};
static const struct rst_config rcar_rst_gen2 __initconst = {
.modemr = 0x60,
.configure = rcar_rst_enable_wdt_reset,
};
static const struct rst_config rcar_rst_gen3 __initconst = {
.modemr = 0x60,
.set_rproc_boot_addr = rcar_rst_set_gen3_rproc_boot_addr,
};
/* V3U firmware doesn't enable WDT reset and there won't be updates anymore */
static const struct rst_config rcar_rst_v3u __initconst = {
.modemr = 0x00, /* MODEMR0 and it has CPG related bits */
.configure = rcar_rst_v3u_enable_wdt_reset,
};
static const struct rst_config rcar_rst_gen4 __initconst = {
.modemr = 0x00, /* MODEMR0 and it has CPG related bits */
};
static const struct of_device_id rcar_rst_matches[] __initconst = {
/* RZ/G1 is handled like R-Car Gen2 */
{ .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
/* RZ/G2 is handled like R-Car Gen3 */
{ .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a774b1-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a774e1-rst", .data = &rcar_rst_gen3 },
/* R-Car Gen1 */
{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
/* R-Car Gen2 */
{ .compatible = "renesas,r8a7790-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7791-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7792-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7793-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7794-rst", .data = &rcar_rst_gen2 },
/* R-Car Gen3 */
{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77961-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
/* R-Car Gen4 */
{ .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_v3u },
{ .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 },
{ .compatible = "renesas,r8a779g0-rst", .data = &rcar_rst_gen4 },
{ /* sentinel */ }
};
static int __init rcar_rst_init(void)
{
const struct of_device_id *match;
const struct rst_config *cfg;
struct device_node *np;
void __iomem *base;
int error = 0;
np = of_find_matching_node_and_match(NULL, rcar_rst_matches, &match);
if (!np)
return -ENODEV;
base = of_iomap(np, 0);
if (!base) {
pr_warn("%pOF: Cannot map regs\n", np);
error = -ENOMEM;
goto out_put;
}
rcar_rst_base = base;
cfg = match->data;
rcar_rst_set_rproc_boot_addr_func = cfg->set_rproc_boot_addr;
saved_mode = ioread32(base + cfg->modemr);
if (cfg->configure) {
error = cfg->configure(base);
if (error) {
pr_warn("%pOF: Cannot run SoC specific configuration\n",
np);
goto out_put;
}
}
pr_debug("%pOF: MODE = 0x%08x\n", np, saved_mode);
out_put:
of_node_put(np);
return error;
}
int __init rcar_rst_read_mode_pins(u32 *mode)
{
int error;
if (!rcar_rst_base) {
error = rcar_rst_init();
if (error)
return error;
}
*mode = saved_mode;
return 0;
}
int rcar_rst_set_rproc_boot_addr(u64 boot_addr)
{
if (!rcar_rst_set_rproc_boot_addr_func)
return -EIO;
return rcar_rst_set_rproc_boot_addr_func(boot_addr);
}
EXPORT_SYMBOL_GPL(rcar_rst_set_rproc_boot_addr);
|
linux-master
|
drivers/soc/renesas/rcar-rst.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Keystone accumulator queue manager
*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
* Author: Sandeep Nair <[email protected]>
* Cyril Chemparathy <[email protected]>
* Santosh Shilimkar <[email protected]>
*/
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/soc/ti/knav_qmss.h>
#include "knav_qmss.h"
#define knav_range_offset_to_inst(kdev, range, q) \
(range->queue_base_inst + (q << kdev->inst_shift))
static void __knav_acc_notify(struct knav_range_info *range,
struct knav_acc_channel *acc)
{
struct knav_device *kdev = range->kdev;
struct knav_queue_inst *inst;
int range_base, queue;
range_base = kdev->base_id + range->queue_base;
if (range->flags & RANGE_MULTI_QUEUE) {
for (queue = 0; queue < range->num_queues; queue++) {
inst = knav_range_offset_to_inst(kdev, range,
queue);
if (inst->notify_needed) {
inst->notify_needed = 0;
dev_dbg(kdev->dev, "acc-irq: notifying %d\n",
range_base + queue);
knav_queue_notify(inst);
}
}
} else {
queue = acc->channel - range->acc_info.start_channel;
inst = knav_range_offset_to_inst(kdev, range, queue);
dev_dbg(kdev->dev, "acc-irq: notifying %d\n",
range_base + queue);
knav_queue_notify(inst);
}
}
static int knav_acc_set_notify(struct knav_range_info *range,
struct knav_queue_inst *kq,
bool enabled)
{
struct knav_pdsp_info *pdsp = range->acc_info.pdsp;
struct knav_device *kdev = range->kdev;
u32 mask, offset;
/*
* when enabling, we need to re-trigger an interrupt if we
* have descriptors pending
*/
if (!enabled || atomic_read(&kq->desc_count) <= 0)
return 0;
kq->notify_needed = 1;
atomic_inc(&kq->acc->retrigger_count);
mask = BIT(kq->acc->channel % 32);
offset = ACC_INTD_OFFSET_STATUS(kq->acc->channel);
dev_dbg(kdev->dev, "setup-notify: re-triggering irq for %s\n",
kq->acc->name);
writel_relaxed(mask, pdsp->intd + offset);
return 0;
}
static irqreturn_t knav_acc_int_handler(int irq, void *_instdata)
{
struct knav_acc_channel *acc;
struct knav_queue_inst *kq = NULL;
struct knav_range_info *range;
struct knav_pdsp_info *pdsp;
struct knav_acc_info *info;
struct knav_device *kdev;
u32 *list, *list_cpu, val, idx, notifies;
int range_base, channel, queue = 0;
dma_addr_t list_dma;
range = _instdata;
info = &range->acc_info;
kdev = range->kdev;
pdsp = range->acc_info.pdsp;
acc = range->acc;
range_base = kdev->base_id + range->queue_base;
if ((range->flags & RANGE_MULTI_QUEUE) == 0) {
for (queue = 0; queue < range->num_irqs; queue++)
if (range->irqs[queue].irq == irq)
break;
kq = knav_range_offset_to_inst(kdev, range, queue);
acc += queue;
}
channel = acc->channel;
list_dma = acc->list_dma[acc->list_index];
list_cpu = acc->list_cpu[acc->list_index];
dev_dbg(kdev->dev, "acc-irq: channel %d, list %d, virt %p, dma %pad\n",
channel, acc->list_index, list_cpu, &list_dma);
if (atomic_read(&acc->retrigger_count)) {
atomic_dec(&acc->retrigger_count);
__knav_acc_notify(range, acc);
writel_relaxed(1, pdsp->intd + ACC_INTD_OFFSET_COUNT(channel));
/* ack the interrupt */
writel_relaxed(ACC_CHANNEL_INT_BASE + channel,
pdsp->intd + ACC_INTD_OFFSET_EOI);
return IRQ_HANDLED;
}
notifies = readl_relaxed(pdsp->intd + ACC_INTD_OFFSET_COUNT(channel));
WARN_ON(!notifies);
dma_sync_single_for_cpu(kdev->dev, list_dma, info->list_size,
DMA_FROM_DEVICE);
for (list = list_cpu; list < list_cpu + (info->list_size / sizeof(u32));
list += ACC_LIST_ENTRY_WORDS) {
if (ACC_LIST_ENTRY_WORDS == 1) {
dev_dbg(kdev->dev,
"acc-irq: list %d, entry @%p, %08x\n",
acc->list_index, list, list[0]);
} else if (ACC_LIST_ENTRY_WORDS == 2) {
dev_dbg(kdev->dev,
"acc-irq: list %d, entry @%p, %08x %08x\n",
acc->list_index, list, list[0], list[1]);
} else if (ACC_LIST_ENTRY_WORDS == 4) {
dev_dbg(kdev->dev,
"acc-irq: list %d, entry @%p, %08x %08x %08x %08x\n",
acc->list_index, list, list[0], list[1],
list[2], list[3]);
}
val = list[ACC_LIST_ENTRY_DESC_IDX];
if (!val)
break;
if (range->flags & RANGE_MULTI_QUEUE) {
queue = list[ACC_LIST_ENTRY_QUEUE_IDX] >> 16;
if (queue < range_base ||
queue >= range_base + range->num_queues) {
dev_err(kdev->dev,
"bad queue %d, expecting %d-%d\n",
queue, range_base,
range_base + range->num_queues);
break;
}
queue -= range_base;
kq = knav_range_offset_to_inst(kdev, range,
queue);
}
if (atomic_inc_return(&kq->desc_count) >= ACC_DESCS_MAX) {
atomic_dec(&kq->desc_count);
dev_err(kdev->dev,
"acc-irq: queue %d full, entry dropped\n",
queue + range_base);
continue;
}
idx = atomic_inc_return(&kq->desc_tail) & ACC_DESCS_MASK;
kq->descs[idx] = val;
kq->notify_needed = 1;
dev_dbg(kdev->dev, "acc-irq: enqueue %08x at %d, queue %d\n",
val, idx, queue + range_base);
}
__knav_acc_notify(range, acc);
memset(list_cpu, 0, info->list_size);
dma_sync_single_for_device(kdev->dev, list_dma, info->list_size,
DMA_TO_DEVICE);
/* flip to the other list */
acc->list_index ^= 1;
/* reset the interrupt counter */
writel_relaxed(1, pdsp->intd + ACC_INTD_OFFSET_COUNT(channel));
/* ack the interrupt */
writel_relaxed(ACC_CHANNEL_INT_BASE + channel,
pdsp->intd + ACC_INTD_OFFSET_EOI);
return IRQ_HANDLED;
}
static int knav_range_setup_acc_irq(struct knav_range_info *range,
int queue, bool enabled)
{
struct knav_device *kdev = range->kdev;
struct knav_acc_channel *acc;
struct cpumask *cpu_mask;
int ret = 0, irq;
u32 old, new;
if (range->flags & RANGE_MULTI_QUEUE) {
acc = range->acc;
irq = range->irqs[0].irq;
cpu_mask = range->irqs[0].cpu_mask;
} else {
acc = range->acc + queue;
irq = range->irqs[queue].irq;
cpu_mask = range->irqs[queue].cpu_mask;
}
old = acc->open_mask;
if (enabled)
new = old | BIT(queue);
else
new = old & ~BIT(queue);
acc->open_mask = new;
dev_dbg(kdev->dev,
"setup-acc-irq: open mask old %08x, new %08x, channel %s\n",
old, new, acc->name);
if (likely(new == old))
return 0;
if (new && !old) {
dev_dbg(kdev->dev,
"setup-acc-irq: requesting %s for channel %s\n",
acc->name, acc->name);
ret = request_irq(irq, knav_acc_int_handler, 0, acc->name,
range);
if (!ret && cpu_mask) {
ret = irq_set_affinity_hint(irq, cpu_mask);
if (ret) {
dev_warn(range->kdev->dev,
"Failed to set IRQ affinity\n");
return ret;
}
}
}
if (old && !new) {
dev_dbg(kdev->dev, "setup-acc-irq: freeing %s for channel %s\n",
acc->name, acc->name);
ret = irq_set_affinity_hint(irq, NULL);
if (ret)
dev_warn(range->kdev->dev,
"Failed to set IRQ affinity\n");
free_irq(irq, range);
}
return ret;
}
static const char *knav_acc_result_str(enum knav_acc_result result)
{
static const char * const result_str[] = {
[ACC_RET_IDLE] = "idle",
[ACC_RET_SUCCESS] = "success",
[ACC_RET_INVALID_COMMAND] = "invalid command",
[ACC_RET_INVALID_CHANNEL] = "invalid channel",
[ACC_RET_INACTIVE_CHANNEL] = "inactive channel",
[ACC_RET_ACTIVE_CHANNEL] = "active channel",
[ACC_RET_INVALID_QUEUE] = "invalid queue",
[ACC_RET_INVALID_RET] = "invalid return code",
};
if (result >= ARRAY_SIZE(result_str))
return result_str[ACC_RET_INVALID_RET];
else
return result_str[result];
}
static enum knav_acc_result
knav_acc_write(struct knav_device *kdev, struct knav_pdsp_info *pdsp,
struct knav_reg_acc_command *cmd)
{
u32 result;
dev_dbg(kdev->dev, "acc command %08x %08x %08x %08x %08x\n",
cmd->command, cmd->queue_mask, cmd->list_dma,
cmd->queue_num, cmd->timer_config);
writel_relaxed(cmd->timer_config, &pdsp->acc_command->timer_config);
writel_relaxed(cmd->queue_num, &pdsp->acc_command->queue_num);
writel_relaxed(cmd->list_dma, &pdsp->acc_command->list_dma);
writel_relaxed(cmd->queue_mask, &pdsp->acc_command->queue_mask);
writel_relaxed(cmd->command, &pdsp->acc_command->command);
/* wait for the command to clear */
do {
result = readl_relaxed(&pdsp->acc_command->command);
} while ((result >> 8) & 0xff);
return (result >> 24) & 0xff;
}
static void knav_acc_setup_cmd(struct knav_device *kdev,
struct knav_range_info *range,
struct knav_reg_acc_command *cmd,
int queue)
{
struct knav_acc_info *info = &range->acc_info;
struct knav_acc_channel *acc;
int queue_base;
u32 queue_mask;
if (range->flags & RANGE_MULTI_QUEUE) {
acc = range->acc;
queue_base = range->queue_base;
queue_mask = BIT(range->num_queues) - 1;
} else {
acc = range->acc + queue;
queue_base = range->queue_base + queue;
queue_mask = 0;
}
memset(cmd, 0, sizeof(*cmd));
cmd->command = acc->channel;
cmd->queue_mask = queue_mask;
cmd->list_dma = (u32)acc->list_dma[0];
cmd->queue_num = info->list_entries << 16;
cmd->queue_num |= queue_base;
cmd->timer_config = ACC_LIST_ENTRY_TYPE << 18;
if (range->flags & RANGE_MULTI_QUEUE)
cmd->timer_config |= ACC_CFG_MULTI_QUEUE;
cmd->timer_config |= info->pacing_mode << 16;
cmd->timer_config |= info->timer_count;
}
static void knav_acc_stop(struct knav_device *kdev,
struct knav_range_info *range,
int queue)
{
struct knav_reg_acc_command cmd;
struct knav_acc_channel *acc;
enum knav_acc_result result;
acc = range->acc + queue;
knav_acc_setup_cmd(kdev, range, &cmd, queue);
cmd.command |= ACC_CMD_DISABLE_CHANNEL << 8;
result = knav_acc_write(kdev, range->acc_info.pdsp, &cmd);
dev_dbg(kdev->dev, "stopped acc channel %s, result %s\n",
acc->name, knav_acc_result_str(result));
}
static enum knav_acc_result knav_acc_start(struct knav_device *kdev,
struct knav_range_info *range,
int queue)
{
struct knav_reg_acc_command cmd;
struct knav_acc_channel *acc;
enum knav_acc_result result;
acc = range->acc + queue;
knav_acc_setup_cmd(kdev, range, &cmd, queue);
cmd.command |= ACC_CMD_ENABLE_CHANNEL << 8;
result = knav_acc_write(kdev, range->acc_info.pdsp, &cmd);
dev_dbg(kdev->dev, "started acc channel %s, result %s\n",
acc->name, knav_acc_result_str(result));
return result;
}
static int knav_acc_init_range(struct knav_range_info *range)
{
struct knav_device *kdev = range->kdev;
struct knav_acc_channel *acc;
enum knav_acc_result result;
int queue;
for (queue = 0; queue < range->num_queues; queue++) {
acc = range->acc + queue;
knav_acc_stop(kdev, range, queue);
acc->list_index = 0;
result = knav_acc_start(kdev, range, queue);
if (result != ACC_RET_SUCCESS)
return -EIO;
if (range->flags & RANGE_MULTI_QUEUE)
return 0;
}
return 0;
}
static int knav_acc_init_queue(struct knav_range_info *range,
struct knav_queue_inst *kq)
{
unsigned id = kq->id - range->queue_base;
kq->descs = devm_kcalloc(range->kdev->dev,
ACC_DESCS_MAX, sizeof(u32), GFP_KERNEL);
if (!kq->descs)
return -ENOMEM;
kq->acc = range->acc;
if ((range->flags & RANGE_MULTI_QUEUE) == 0)
kq->acc += id;
return 0;
}
static int knav_acc_open_queue(struct knav_range_info *range,
struct knav_queue_inst *inst, unsigned flags)
{
unsigned id = inst->id - range->queue_base;
return knav_range_setup_acc_irq(range, id, true);
}
static int knav_acc_close_queue(struct knav_range_info *range,
struct knav_queue_inst *inst)
{
unsigned id = inst->id - range->queue_base;
return knav_range_setup_acc_irq(range, id, false);
}
static int knav_acc_free_range(struct knav_range_info *range)
{
struct knav_device *kdev = range->kdev;
struct knav_acc_channel *acc;
struct knav_acc_info *info;
int channel, channels;
info = &range->acc_info;
if (range->flags & RANGE_MULTI_QUEUE)
channels = 1;
else
channels = range->num_queues;
for (channel = 0; channel < channels; channel++) {
acc = range->acc + channel;
if (!acc->list_cpu[0])
continue;
dma_unmap_single(kdev->dev, acc->list_dma[0],
info->mem_size, DMA_BIDIRECTIONAL);
free_pages_exact(acc->list_cpu[0], info->mem_size);
}
devm_kfree(range->kdev->dev, range->acc);
return 0;
}
static struct knav_range_ops knav_acc_range_ops = {
.set_notify = knav_acc_set_notify,
.init_queue = knav_acc_init_queue,
.open_queue = knav_acc_open_queue,
.close_queue = knav_acc_close_queue,
.init_range = knav_acc_init_range,
.free_range = knav_acc_free_range,
};
/**
* knav_init_acc_range: Initialise accumulator ranges
*
* @kdev: qmss device
* @node: device node
* @range: qmms range information
*
* Return 0 on success or error
*/
int knav_init_acc_range(struct knav_device *kdev,
struct device_node *node,
struct knav_range_info *range)
{
struct knav_acc_channel *acc;
struct knav_pdsp_info *pdsp;
struct knav_acc_info *info;
int ret, channel, channels;
int list_size, mem_size;
dma_addr_t list_dma;
void *list_mem;
u32 config[5];
range->flags |= RANGE_HAS_ACCUMULATOR;
info = &range->acc_info;
ret = of_property_read_u32_array(node, "accumulator", config, 5);
if (ret)
return ret;
info->pdsp_id = config[0];
info->start_channel = config[1];
info->list_entries = config[2];
info->pacing_mode = config[3];
info->timer_count = config[4] / ACC_DEFAULT_PERIOD;
if (info->start_channel > ACC_MAX_CHANNEL) {
dev_err(kdev->dev, "channel %d invalid for range %s\n",
info->start_channel, range->name);
return -EINVAL;
}
if (info->pacing_mode > 3) {
dev_err(kdev->dev, "pacing mode %d invalid for range %s\n",
info->pacing_mode, range->name);
return -EINVAL;
}
pdsp = knav_find_pdsp(kdev, info->pdsp_id);
if (!pdsp) {
dev_err(kdev->dev, "pdsp id %d not found for range %s\n",
info->pdsp_id, range->name);
return -EINVAL;
}
if (!pdsp->started) {
dev_err(kdev->dev, "pdsp id %d not started for range %s\n",
info->pdsp_id, range->name);
return -ENODEV;
}
info->pdsp = pdsp;
channels = range->num_queues;
if (of_property_read_bool(node, "multi-queue")) {
range->flags |= RANGE_MULTI_QUEUE;
channels = 1;
if (range->queue_base & (32 - 1)) {
dev_err(kdev->dev,
"misaligned multi-queue accumulator range %s\n",
range->name);
return -EINVAL;
}
if (range->num_queues > 32) {
dev_err(kdev->dev,
"too many queues in accumulator range %s\n",
range->name);
return -EINVAL;
}
}
/* figure out list size */
list_size = info->list_entries;
list_size *= ACC_LIST_ENTRY_WORDS * sizeof(u32);
info->list_size = list_size;
mem_size = PAGE_ALIGN(list_size * 2);
info->mem_size = mem_size;
range->acc = devm_kcalloc(kdev->dev, channels, sizeof(*range->acc),
GFP_KERNEL);
if (!range->acc)
return -ENOMEM;
for (channel = 0; channel < channels; channel++) {
acc = range->acc + channel;
acc->channel = info->start_channel + channel;
/* allocate memory for the two lists */
list_mem = alloc_pages_exact(mem_size, GFP_KERNEL | GFP_DMA);
if (!list_mem)
return -ENOMEM;
list_dma = dma_map_single(kdev->dev, list_mem, mem_size,
DMA_BIDIRECTIONAL);
if (dma_mapping_error(kdev->dev, list_dma)) {
free_pages_exact(list_mem, mem_size);
return -ENOMEM;
}
memset(list_mem, 0, mem_size);
dma_sync_single_for_device(kdev->dev, list_dma, mem_size,
DMA_TO_DEVICE);
scnprintf(acc->name, sizeof(acc->name), "hwqueue-acc-%d",
acc->channel);
acc->list_cpu[0] = list_mem;
acc->list_cpu[1] = list_mem + list_size;
acc->list_dma[0] = list_dma;
acc->list_dma[1] = list_dma + list_size;
dev_dbg(kdev->dev, "%s: channel %d, dma %pad, virt %8p\n",
acc->name, acc->channel, &list_dma, list_mem);
}
range->ops = &knav_acc_range_ops;
return 0;
}
EXPORT_SYMBOL_GPL(knav_init_acc_range);
|
linux-master
|
drivers/soc/ti/knav_qmss_acc.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* PRU-ICSS platform driver for various TI SoCs
*
* Copyright (C) 2014-2020 Texas Instruments Incorporated - http://www.ti.com/
* Author(s):
* Suman Anna <[email protected]>
* Andrew F. Davis <[email protected]>
* Tero Kristo <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/pruss_driver.h>
#include <linux/regmap.h>
#include <linux/remoteproc.h>
#include <linux/slab.h>
#include "pruss.h"
/**
* struct pruss_private_data - PRUSS driver private data
* @has_no_sharedram: flag to indicate the absence of PRUSS Shared Data RAM
* @has_core_mux_clock: flag to indicate the presence of PRUSS core clock
*/
struct pruss_private_data {
bool has_no_sharedram;
bool has_core_mux_clock;
};
/**
* pruss_get() - get the pruss for a given PRU remoteproc
* @rproc: remoteproc handle of a PRU instance
*
* Finds the parent pruss device for a PRU given the @rproc handle of the
* PRU remote processor. This function increments the pruss device's refcount,
* so always use pruss_put() to decrement it back once pruss isn't needed
* anymore.
*
* This API doesn't check if @rproc is valid or not. It is expected the caller
* will have done a pru_rproc_get() on @rproc, before calling this API to make
* sure that @rproc is valid.
*
* Return: pruss handle on success, and an ERR_PTR on failure using one
* of the following error values
* -EINVAL if invalid parameter
* -ENODEV if PRU device or PRUSS device is not found
*/
struct pruss *pruss_get(struct rproc *rproc)
{
struct pruss *pruss;
struct device *dev;
struct platform_device *ppdev;
if (IS_ERR_OR_NULL(rproc))
return ERR_PTR(-EINVAL);
dev = &rproc->dev;
/* make sure it is PRU rproc */
if (!dev->parent || !is_pru_rproc(dev->parent))
return ERR_PTR(-ENODEV);
ppdev = to_platform_device(dev->parent->parent);
pruss = platform_get_drvdata(ppdev);
if (!pruss)
return ERR_PTR(-ENODEV);
get_device(pruss->dev);
return pruss;
}
EXPORT_SYMBOL_GPL(pruss_get);
/**
* pruss_put() - decrement pruss device's usecount
* @pruss: pruss handle
*
* Complimentary function for pruss_get(). Needs to be called
* after the PRUSS is used, and only if the pruss_get() succeeds.
*/
void pruss_put(struct pruss *pruss)
{
if (IS_ERR_OR_NULL(pruss))
return;
put_device(pruss->dev);
}
EXPORT_SYMBOL_GPL(pruss_put);
/**
* pruss_request_mem_region() - request a memory resource
* @pruss: the pruss instance
* @mem_id: the memory resource id
* @region: pointer to memory region structure to be filled in
*
* This function allows a client driver to request a memory resource,
* and if successful, will let the client driver own the particular
* memory region until released using the pruss_release_mem_region()
* API.
*
* Return: 0 if requested memory region is available (in such case pointer to
* memory region is returned via @region), an error otherwise
*/
int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id,
struct pruss_mem_region *region)
{
if (!pruss || !region || mem_id >= PRUSS_MEM_MAX)
return -EINVAL;
mutex_lock(&pruss->lock);
if (pruss->mem_in_use[mem_id]) {
mutex_unlock(&pruss->lock);
return -EBUSY;
}
*region = pruss->mem_regions[mem_id];
pruss->mem_in_use[mem_id] = region;
mutex_unlock(&pruss->lock);
return 0;
}
EXPORT_SYMBOL_GPL(pruss_request_mem_region);
/**
* pruss_release_mem_region() - release a memory resource
* @pruss: the pruss instance
* @region: the memory region to release
*
* This function is the complimentary function to
* pruss_request_mem_region(), and allows the client drivers to
* release back a memory resource.
*
* Return: 0 on success, an error code otherwise
*/
int pruss_release_mem_region(struct pruss *pruss,
struct pruss_mem_region *region)
{
int id;
if (!pruss || !region)
return -EINVAL;
mutex_lock(&pruss->lock);
/* find out the memory region being released */
for (id = 0; id < PRUSS_MEM_MAX; id++) {
if (pruss->mem_in_use[id] == region)
break;
}
if (id == PRUSS_MEM_MAX) {
mutex_unlock(&pruss->lock);
return -EINVAL;
}
pruss->mem_in_use[id] = NULL;
mutex_unlock(&pruss->lock);
return 0;
}
EXPORT_SYMBOL_GPL(pruss_release_mem_region);
/**
* pruss_cfg_get_gpmux() - get the current GPMUX value for a PRU device
* @pruss: pruss instance
* @pru_id: PRU identifier (0-1)
* @mux: pointer to store the current mux value into
*
* Return: 0 on success, or an error code otherwise
*/
int pruss_cfg_get_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 *mux)
{
int ret;
u32 val;
if (pru_id >= PRUSS_NUM_PRUS || !mux)
return -EINVAL;
ret = pruss_cfg_read(pruss, PRUSS_CFG_GPCFG(pru_id), &val);
if (!ret)
*mux = (u8)((val & PRUSS_GPCFG_PRU_MUX_SEL_MASK) >>
PRUSS_GPCFG_PRU_MUX_SEL_SHIFT);
return ret;
}
EXPORT_SYMBOL_GPL(pruss_cfg_get_gpmux);
/**
* pruss_cfg_set_gpmux() - set the GPMUX value for a PRU device
* @pruss: pruss instance
* @pru_id: PRU identifier (0-1)
* @mux: new mux value for PRU
*
* Return: 0 on success, or an error code otherwise
*/
int pruss_cfg_set_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 mux)
{
if (mux >= PRUSS_GP_MUX_SEL_MAX ||
pru_id >= PRUSS_NUM_PRUS)
return -EINVAL;
return pruss_cfg_update(pruss, PRUSS_CFG_GPCFG(pru_id),
PRUSS_GPCFG_PRU_MUX_SEL_MASK,
(u32)mux << PRUSS_GPCFG_PRU_MUX_SEL_SHIFT);
}
EXPORT_SYMBOL_GPL(pruss_cfg_set_gpmux);
/**
* pruss_cfg_gpimode() - set the GPI mode of the PRU
* @pruss: the pruss instance handle
* @pru_id: id of the PRU core within the PRUSS
* @mode: GPI mode to set
*
* Sets the GPI mode for a given PRU by programming the
* corresponding PRUSS_CFG_GPCFGx register
*
* Return: 0 on success, or an error code otherwise
*/
int pruss_cfg_gpimode(struct pruss *pruss, enum pruss_pru_id pru_id,
enum pruss_gpi_mode mode)
{
if (pru_id >= PRUSS_NUM_PRUS || mode >= PRUSS_GPI_MODE_MAX)
return -EINVAL;
return pruss_cfg_update(pruss, PRUSS_CFG_GPCFG(pru_id),
PRUSS_GPCFG_PRU_GPI_MODE_MASK,
mode << PRUSS_GPCFG_PRU_GPI_MODE_SHIFT);
}
EXPORT_SYMBOL_GPL(pruss_cfg_gpimode);
/**
* pruss_cfg_miirt_enable() - Enable/disable MII RT Events
* @pruss: the pruss instance
* @enable: enable/disable
*
* Enable/disable the MII RT Events for the PRUSS.
*
* Return: 0 on success, or an error code otherwise
*/
int pruss_cfg_miirt_enable(struct pruss *pruss, bool enable)
{
u32 set = enable ? PRUSS_MII_RT_EVENT_EN : 0;
return pruss_cfg_update(pruss, PRUSS_CFG_MII_RT,
PRUSS_MII_RT_EVENT_EN, set);
}
EXPORT_SYMBOL_GPL(pruss_cfg_miirt_enable);
/**
* pruss_cfg_xfr_enable() - Enable/disable XIN XOUT shift functionality
* @pruss: the pruss instance
* @pru_type: PRU core type identifier
* @enable: enable/disable
*
* Return: 0 on success, or an error code otherwise
*/
int pruss_cfg_xfr_enable(struct pruss *pruss, enum pru_type pru_type,
bool enable)
{
u32 mask, set;
switch (pru_type) {
case PRU_TYPE_PRU:
mask = PRUSS_SPP_XFER_SHIFT_EN;
break;
case PRU_TYPE_RTU:
mask = PRUSS_SPP_RTU_XFR_SHIFT_EN;
break;
default:
return -EINVAL;
}
set = enable ? mask : 0;
return pruss_cfg_update(pruss, PRUSS_CFG_SPP, mask, set);
}
EXPORT_SYMBOL_GPL(pruss_cfg_xfr_enable);
static void pruss_of_free_clk_provider(void *data)
{
struct device_node *clk_mux_np = data;
of_clk_del_provider(clk_mux_np);
of_node_put(clk_mux_np);
}
static void pruss_clk_unregister_mux(void *data)
{
clk_unregister_mux(data);
}
static int pruss_clk_mux_setup(struct pruss *pruss, struct clk *clk_mux,
char *mux_name, struct device_node *clks_np)
{
struct device_node *clk_mux_np;
struct device *dev = pruss->dev;
char *clk_mux_name;
unsigned int num_parents;
const char **parent_names;
void __iomem *reg;
u32 reg_offset;
int ret;
clk_mux_np = of_get_child_by_name(clks_np, mux_name);
if (!clk_mux_np) {
dev_err(dev, "%pOF is missing its '%s' node\n", clks_np,
mux_name);
return -ENODEV;
}
num_parents = of_clk_get_parent_count(clk_mux_np);
if (num_parents < 1) {
dev_err(dev, "mux-clock %pOF must have parents\n", clk_mux_np);
ret = -EINVAL;
goto put_clk_mux_np;
}
parent_names = devm_kcalloc(dev, sizeof(*parent_names), num_parents,
GFP_KERNEL);
if (!parent_names) {
ret = -ENOMEM;
goto put_clk_mux_np;
}
of_clk_parent_fill(clk_mux_np, parent_names, num_parents);
clk_mux_name = devm_kasprintf(dev, GFP_KERNEL, "%s.%pOFn",
dev_name(dev), clk_mux_np);
if (!clk_mux_name) {
ret = -ENOMEM;
goto put_clk_mux_np;
}
ret = of_property_read_u32(clk_mux_np, "reg", ®_offset);
if (ret)
goto put_clk_mux_np;
reg = pruss->cfg_base + reg_offset;
clk_mux = clk_register_mux(NULL, clk_mux_name, parent_names,
num_parents, 0, reg, 0, 1, 0, NULL);
if (IS_ERR(clk_mux)) {
ret = PTR_ERR(clk_mux);
goto put_clk_mux_np;
}
ret = devm_add_action_or_reset(dev, pruss_clk_unregister_mux, clk_mux);
if (ret) {
dev_err(dev, "failed to add clkmux unregister action %d", ret);
goto put_clk_mux_np;
}
ret = of_clk_add_provider(clk_mux_np, of_clk_src_simple_get, clk_mux);
if (ret)
goto put_clk_mux_np;
ret = devm_add_action_or_reset(dev, pruss_of_free_clk_provider,
clk_mux_np);
if (ret) {
dev_err(dev, "failed to add clkmux free action %d", ret);
goto put_clk_mux_np;
}
return 0;
put_clk_mux_np:
of_node_put(clk_mux_np);
return ret;
}
static int pruss_clk_init(struct pruss *pruss, struct device_node *cfg_node)
{
const struct pruss_private_data *data;
struct device_node *clks_np;
struct device *dev = pruss->dev;
int ret = 0;
data = of_device_get_match_data(dev);
clks_np = of_get_child_by_name(cfg_node, "clocks");
if (!clks_np) {
dev_err(dev, "%pOF is missing its 'clocks' node\n", cfg_node);
return -ENODEV;
}
if (data && data->has_core_mux_clock) {
ret = pruss_clk_mux_setup(pruss, pruss->core_clk_mux,
"coreclk-mux", clks_np);
if (ret) {
dev_err(dev, "failed to setup coreclk-mux\n");
goto put_clks_node;
}
}
ret = pruss_clk_mux_setup(pruss, pruss->iep_clk_mux, "iepclk-mux",
clks_np);
if (ret) {
dev_err(dev, "failed to setup iepclk-mux\n");
goto put_clks_node;
}
put_clks_node:
of_node_put(clks_np);
return ret;
}
static struct regmap_config regmap_conf = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static int pruss_cfg_of_init(struct device *dev, struct pruss *pruss)
{
struct device_node *np = dev_of_node(dev);
struct device_node *child;
struct resource res;
int ret;
child = of_get_child_by_name(np, "cfg");
if (!child) {
dev_err(dev, "%pOF is missing its 'cfg' node\n", child);
return -ENODEV;
}
if (of_address_to_resource(child, 0, &res)) {
ret = -ENOMEM;
goto node_put;
}
pruss->cfg_base = devm_ioremap(dev, res.start, resource_size(&res));
if (!pruss->cfg_base) {
ret = -ENOMEM;
goto node_put;
}
regmap_conf.name = kasprintf(GFP_KERNEL, "%pOFn@%llx", child,
(u64)res.start);
regmap_conf.max_register = resource_size(&res) - 4;
pruss->cfg_regmap = devm_regmap_init_mmio(dev, pruss->cfg_base,
®map_conf);
kfree(regmap_conf.name);
if (IS_ERR(pruss->cfg_regmap)) {
dev_err(dev, "regmap_init_mmio failed for cfg, ret = %ld\n",
PTR_ERR(pruss->cfg_regmap));
ret = PTR_ERR(pruss->cfg_regmap);
goto node_put;
}
ret = pruss_clk_init(pruss, child);
if (ret)
dev_err(dev, "pruss_clk_init failed, ret = %d\n", ret);
node_put:
of_node_put(child);
return ret;
}
static int pruss_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev_of_node(dev);
struct device_node *child;
struct pruss *pruss;
struct resource res;
int ret, i, index;
const struct pruss_private_data *data;
const char *mem_names[PRUSS_MEM_MAX] = { "dram0", "dram1", "shrdram2" };
data = of_device_get_match_data(&pdev->dev);
ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
if (ret) {
dev_err(dev, "failed to set the DMA coherent mask");
return ret;
}
pruss = devm_kzalloc(dev, sizeof(*pruss), GFP_KERNEL);
if (!pruss)
return -ENOMEM;
pruss->dev = dev;
mutex_init(&pruss->lock);
child = of_get_child_by_name(np, "memories");
if (!child) {
dev_err(dev, "%pOF is missing its 'memories' node\n", child);
return -ENODEV;
}
for (i = 0; i < PRUSS_MEM_MAX; i++) {
/*
* On AM437x one of two PRUSS units don't contain Shared RAM,
* skip it
*/
if (data && data->has_no_sharedram && i == PRUSS_MEM_SHRD_RAM2)
continue;
index = of_property_match_string(child, "reg-names",
mem_names[i]);
if (index < 0) {
of_node_put(child);
return index;
}
if (of_address_to_resource(child, index, &res)) {
of_node_put(child);
return -EINVAL;
}
pruss->mem_regions[i].va = devm_ioremap(dev, res.start,
resource_size(&res));
if (!pruss->mem_regions[i].va) {
dev_err(dev, "failed to parse and map memory resource %d %s\n",
i, mem_names[i]);
of_node_put(child);
return -ENOMEM;
}
pruss->mem_regions[i].pa = res.start;
pruss->mem_regions[i].size = resource_size(&res);
dev_dbg(dev, "memory %8s: pa %pa size 0x%zx va %pK\n",
mem_names[i], &pruss->mem_regions[i].pa,
pruss->mem_regions[i].size, pruss->mem_regions[i].va);
}
of_node_put(child);
platform_set_drvdata(pdev, pruss);
pm_runtime_enable(dev);
ret = pm_runtime_resume_and_get(dev);
if (ret < 0) {
dev_err(dev, "couldn't enable module\n");
goto rpm_disable;
}
ret = pruss_cfg_of_init(dev, pruss);
if (ret < 0)
goto rpm_put;
ret = devm_of_platform_populate(dev);
if (ret) {
dev_err(dev, "failed to register child devices\n");
goto rpm_put;
}
return 0;
rpm_put:
pm_runtime_put_sync(dev);
rpm_disable:
pm_runtime_disable(dev);
return ret;
}
static int pruss_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
devm_of_platform_depopulate(dev);
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
return 0;
}
/* instance-specific driver private data */
static const struct pruss_private_data am437x_pruss1_data = {
.has_no_sharedram = false,
};
static const struct pruss_private_data am437x_pruss0_data = {
.has_no_sharedram = true,
};
static const struct pruss_private_data am65x_j721e_pruss_data = {
.has_core_mux_clock = true,
};
static const struct of_device_id pruss_of_match[] = {
{ .compatible = "ti,am3356-pruss" },
{ .compatible = "ti,am4376-pruss0", .data = &am437x_pruss0_data, },
{ .compatible = "ti,am4376-pruss1", .data = &am437x_pruss1_data, },
{ .compatible = "ti,am5728-pruss" },
{ .compatible = "ti,k2g-pruss" },
{ .compatible = "ti,am654-icssg", .data = &am65x_j721e_pruss_data, },
{ .compatible = "ti,j721e-icssg", .data = &am65x_j721e_pruss_data, },
{ .compatible = "ti,am642-icssg", .data = &am65x_j721e_pruss_data, },
{ .compatible = "ti,am625-pruss", .data = &am65x_j721e_pruss_data, },
{},
};
MODULE_DEVICE_TABLE(of, pruss_of_match);
static struct platform_driver pruss_driver = {
.driver = {
.name = "pruss",
.of_match_table = pruss_of_match,
},
.probe = pruss_probe,
.remove = pruss_remove,
};
module_platform_driver(pruss_driver);
MODULE_AUTHOR("Suman Anna <[email protected]>");
MODULE_DESCRIPTION("PRU-ICSS Subsystem Driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/soc/ti/pruss.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* TI K3 SoC info driver
*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
*/
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/sys_soc.h>
#define CTRLMMR_WKUP_JTAGID_REG 0
/*
* Bits:
* 31-28 VARIANT Device variant
* 27-12 PARTNO Part number
* 11-1 MFG Indicates TI as manufacturer (0x17)
* 1 Always 1
*/
#define CTRLMMR_WKUP_JTAGID_VARIANT_SHIFT (28)
#define CTRLMMR_WKUP_JTAGID_VARIANT_MASK GENMASK(31, 28)
#define CTRLMMR_WKUP_JTAGID_PARTNO_SHIFT (12)
#define CTRLMMR_WKUP_JTAGID_PARTNO_MASK GENMASK(27, 12)
#define CTRLMMR_WKUP_JTAGID_MFG_SHIFT (1)
#define CTRLMMR_WKUP_JTAGID_MFG_MASK GENMASK(11, 1)
#define CTRLMMR_WKUP_JTAGID_MFG_TI 0x17
static const struct k3_soc_id {
unsigned int id;
const char *family_name;
} k3_soc_ids[] = {
{ 0xBB5A, "AM65X" },
{ 0xBB64, "J721E" },
{ 0xBB6D, "J7200" },
{ 0xBB38, "AM64X" },
{ 0xBB75, "J721S2"},
{ 0xBB7E, "AM62X" },
{ 0xBB80, "J784S4" },
{ 0xBB8D, "AM62AX" },
{ 0xBB9D, "AM62PX" },
};
static int
k3_chipinfo_partno_to_names(unsigned int partno,
struct soc_device_attribute *soc_dev_attr)
{
int i;
for (i = 0; i < ARRAY_SIZE(k3_soc_ids); i++)
if (partno == k3_soc_ids[i].id) {
soc_dev_attr->family = k3_soc_ids[i].family_name;
return 0;
}
return -EINVAL;
}
static int k3_chipinfo_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct soc_device_attribute *soc_dev_attr;
struct device *dev = &pdev->dev;
struct soc_device *soc_dev;
struct regmap *regmap;
u32 partno_id;
u32 variant;
u32 jtag_id;
u32 mfg;
int ret;
regmap = device_node_to_regmap(node);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = regmap_read(regmap, CTRLMMR_WKUP_JTAGID_REG, &jtag_id);
if (ret < 0)
return ret;
mfg = (jtag_id & CTRLMMR_WKUP_JTAGID_MFG_MASK) >>
CTRLMMR_WKUP_JTAGID_MFG_SHIFT;
if (mfg != CTRLMMR_WKUP_JTAGID_MFG_TI) {
dev_err(dev, "Invalid MFG SoC\n");
return -ENODEV;
}
variant = (jtag_id & CTRLMMR_WKUP_JTAGID_VARIANT_MASK) >>
CTRLMMR_WKUP_JTAGID_VARIANT_SHIFT;
variant++;
partno_id = (jtag_id & CTRLMMR_WKUP_JTAGID_PARTNO_MASK) >>
CTRLMMR_WKUP_JTAGID_PARTNO_SHIFT;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return -ENOMEM;
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%x.0", variant);
if (!soc_dev_attr->revision) {
ret = -ENOMEM;
goto err;
}
ret = k3_chipinfo_partno_to_names(partno_id, soc_dev_attr);
if (ret) {
dev_err(dev, "Unknown SoC JTAGID[0x%08X]\n", jtag_id);
ret = -ENODEV;
goto err_free_rev;
}
node = of_find_node_by_path("/");
of_property_read_string(node, "model", &soc_dev_attr->machine);
of_node_put(node);
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
ret = PTR_ERR(soc_dev);
goto err_free_rev;
}
dev_info(dev, "Family:%s rev:%s JTAGID[0x%08x] Detected\n",
soc_dev_attr->family,
soc_dev_attr->revision, jtag_id);
return 0;
err_free_rev:
kfree(soc_dev_attr->revision);
err:
kfree(soc_dev_attr);
return ret;
}
static const struct of_device_id k3_chipinfo_of_match[] = {
{ .compatible = "ti,am654-chipid", },
{ /* sentinel */ },
};
static struct platform_driver k3_chipinfo_driver = {
.driver = {
.name = "k3-chipinfo",
.of_match_table = k3_chipinfo_of_match,
},
.probe = k3_chipinfo_probe,
};
static int __init k3_chipinfo_init(void)
{
return platform_driver_register(&k3_chipinfo_driver);
}
subsys_initcall(k3_chipinfo_init);
|
linux-master
|
drivers/soc/ti/k3-socinfo.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* AMx3 Wkup M3 IPC driver
*
* Copyright (C) 2015 Texas Instruments, Inc.
*
* Dave Gerlach <[email protected]>
*/
#include <linux/debugfs.h>
#include <linux/err.h>
#include <linux/firmware.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/omap-mailbox.h>
#include <linux/platform_device.h>
#include <linux/remoteproc.h>
#include <linux/suspend.h>
#include <linux/wkup_m3_ipc.h>
#define AM33XX_CTRL_IPC_REG_COUNT 0x8
#define AM33XX_CTRL_IPC_REG_OFFSET(m) (0x4 + 4 * (m))
/* AM33XX M3_TXEV_EOI register */
#define AM33XX_CONTROL_M3_TXEV_EOI 0x00
#define AM33XX_M3_TXEV_ACK (0x1 << 0)
#define AM33XX_M3_TXEV_ENABLE (0x0 << 0)
#define IPC_CMD_DS0 0x4
#define IPC_CMD_STANDBY 0xc
#define IPC_CMD_IDLE 0x10
#define IPC_CMD_RESET 0xe
#define DS_IPC_DEFAULT 0xffffffff
#define M3_VERSION_UNKNOWN 0x0000ffff
#define M3_BASELINE_VERSION 0x191
#define M3_STATUS_RESP_MASK (0xffff << 16)
#define M3_FW_VERSION_MASK 0xffff
#define M3_WAKE_SRC_MASK 0xff
#define IPC_MEM_TYPE_SHIFT (0x0)
#define IPC_MEM_TYPE_MASK (0x7 << 0)
#define IPC_VTT_STAT_SHIFT (0x3)
#define IPC_VTT_STAT_MASK (0x1 << 3)
#define IPC_VTT_GPIO_PIN_SHIFT (0x4)
#define IPC_VTT_GPIO_PIN_MASK (0x3f << 4)
#define IPC_IO_ISOLATION_STAT_SHIFT (10)
#define IPC_IO_ISOLATION_STAT_MASK (0x1 << 10)
#define IPC_DBG_HALT_SHIFT (11)
#define IPC_DBG_HALT_MASK (0x1 << 11)
#define M3_STATE_UNKNOWN 0
#define M3_STATE_RESET 1
#define M3_STATE_INITED 2
#define M3_STATE_MSG_FOR_LP 3
#define M3_STATE_MSG_FOR_RESET 4
#define WKUP_M3_SD_FW_MAGIC 0x570C
#define WKUP_M3_DMEM_START 0x80000
#define WKUP_M3_AUXDATA_OFFSET 0x1000
#define WKUP_M3_AUXDATA_SIZE 0xFF
static struct wkup_m3_ipc *m3_ipc_state;
static const struct wkup_m3_wakeup_src wakeups[] = {
{.irq_nr = 16, .src = "PRCM"},
{.irq_nr = 35, .src = "USB0_PHY"},
{.irq_nr = 36, .src = "USB1_PHY"},
{.irq_nr = 40, .src = "I2C0"},
{.irq_nr = 41, .src = "RTC Timer"},
{.irq_nr = 42, .src = "RTC Alarm"},
{.irq_nr = 43, .src = "Timer0"},
{.irq_nr = 44, .src = "Timer1"},
{.irq_nr = 45, .src = "UART"},
{.irq_nr = 46, .src = "GPIO0"},
{.irq_nr = 48, .src = "MPU_WAKE"},
{.irq_nr = 49, .src = "WDT0"},
{.irq_nr = 50, .src = "WDT1"},
{.irq_nr = 51, .src = "ADC_TSC"},
{.irq_nr = 0, .src = "Unknown"},
};
/**
* wkup_m3_copy_aux_data - Copy auxiliary data to special region of m3 dmem
* @data - pointer to data
* @sz - size of data to copy (limit 256 bytes)
*
* Copies any additional blob of data to the wkup_m3 dmem to be used by the
* firmware
*/
static unsigned long wkup_m3_copy_aux_data(struct wkup_m3_ipc *m3_ipc,
const void *data, int sz)
{
unsigned long aux_data_dev_addr;
void *aux_data_addr;
aux_data_dev_addr = WKUP_M3_DMEM_START + WKUP_M3_AUXDATA_OFFSET;
aux_data_addr = rproc_da_to_va(m3_ipc->rproc,
aux_data_dev_addr,
WKUP_M3_AUXDATA_SIZE,
NULL);
memcpy(aux_data_addr, data, sz);
return WKUP_M3_AUXDATA_OFFSET;
}
static void wkup_m3_scale_data_fw_cb(const struct firmware *fw, void *context)
{
unsigned long val, aux_base;
struct wkup_m3_scale_data_header hdr;
struct wkup_m3_ipc *m3_ipc = context;
struct device *dev = m3_ipc->dev;
if (!fw) {
dev_err(dev, "Voltage scale fw name given but file missing.\n");
return;
}
memcpy(&hdr, fw->data, sizeof(hdr));
if (hdr.magic != WKUP_M3_SD_FW_MAGIC) {
dev_err(dev, "PM: Voltage Scale Data binary does not appear valid.\n");
goto release_sd_fw;
}
aux_base = wkup_m3_copy_aux_data(m3_ipc, fw->data + sizeof(hdr),
fw->size - sizeof(hdr));
val = (aux_base + hdr.sleep_offset);
val |= ((aux_base + hdr.wake_offset) << 16);
m3_ipc->volt_scale_offsets = val;
release_sd_fw:
release_firmware(fw);
};
static int wkup_m3_init_scale_data(struct wkup_m3_ipc *m3_ipc,
struct device *dev)
{
int ret = 0;
/*
* If no name is provided, user has already been warned, pm will
* still work so return 0
*/
if (!m3_ipc->sd_fw_name)
return ret;
ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
m3_ipc->sd_fw_name, dev, GFP_ATOMIC,
m3_ipc, wkup_m3_scale_data_fw_cb);
return ret;
}
#ifdef CONFIG_DEBUG_FS
static void wkup_m3_set_halt_late(bool enabled)
{
if (enabled)
m3_ipc_state->halt = (1 << IPC_DBG_HALT_SHIFT);
else
m3_ipc_state->halt = 0;
}
static int option_get(void *data, u64 *val)
{
u32 *option = data;
*val = *option;
return 0;
}
static int option_set(void *data, u64 val)
{
u32 *option = data;
*option = val;
if (option == &m3_ipc_state->halt) {
if (val)
wkup_m3_set_halt_late(true);
else
wkup_m3_set_halt_late(false);
}
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(wkup_m3_ipc_option_fops, option_get, option_set,
"%llu\n");
static int wkup_m3_ipc_dbg_init(struct wkup_m3_ipc *m3_ipc)
{
m3_ipc->dbg_path = debugfs_create_dir("wkup_m3_ipc", NULL);
if (IS_ERR(m3_ipc->dbg_path))
return -EINVAL;
(void)debugfs_create_file("enable_late_halt", 0644,
m3_ipc->dbg_path,
&m3_ipc->halt,
&wkup_m3_ipc_option_fops);
return 0;
}
static inline void wkup_m3_ipc_dbg_destroy(struct wkup_m3_ipc *m3_ipc)
{
debugfs_remove_recursive(m3_ipc->dbg_path);
}
#else
static inline int wkup_m3_ipc_dbg_init(struct wkup_m3_ipc *m3_ipc)
{
return 0;
}
static inline void wkup_m3_ipc_dbg_destroy(struct wkup_m3_ipc *m3_ipc)
{
}
#endif /* CONFIG_DEBUG_FS */
static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc)
{
writel(AM33XX_M3_TXEV_ACK,
m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
}
static void am33xx_txev_enable(struct wkup_m3_ipc *m3_ipc)
{
writel(AM33XX_M3_TXEV_ENABLE,
m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
}
static void wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc *m3_ipc,
u32 val, int ipc_reg_num)
{
if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
"ipc register operation out of range"))
return;
writel(val, m3_ipc->ipc_mem_base +
AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
}
static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc *m3_ipc,
int ipc_reg_num)
{
if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
"ipc register operation out of range"))
return 0;
return readl(m3_ipc->ipc_mem_base +
AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
}
static int wkup_m3_fw_version_read(struct wkup_m3_ipc *m3_ipc)
{
int val;
val = wkup_m3_ctrl_ipc_read(m3_ipc, 2);
return val & M3_FW_VERSION_MASK;
}
static irqreturn_t wkup_m3_txev_handler(int irq, void *ipc_data)
{
struct wkup_m3_ipc *m3_ipc = ipc_data;
struct device *dev = m3_ipc->dev;
int ver = 0;
am33xx_txev_eoi(m3_ipc);
switch (m3_ipc->state) {
case M3_STATE_RESET:
ver = wkup_m3_fw_version_read(m3_ipc);
if (ver == M3_VERSION_UNKNOWN ||
ver < M3_BASELINE_VERSION) {
dev_warn(dev, "CM3 Firmware Version %x not supported\n",
ver);
} else {
dev_info(dev, "CM3 Firmware Version = 0x%x\n", ver);
}
m3_ipc->state = M3_STATE_INITED;
wkup_m3_init_scale_data(m3_ipc, dev);
complete(&m3_ipc->sync_complete);
break;
case M3_STATE_MSG_FOR_RESET:
m3_ipc->state = M3_STATE_INITED;
complete(&m3_ipc->sync_complete);
break;
case M3_STATE_MSG_FOR_LP:
complete(&m3_ipc->sync_complete);
break;
case M3_STATE_UNKNOWN:
dev_warn(dev, "Unknown CM3 State\n");
}
am33xx_txev_enable(m3_ipc);
return IRQ_HANDLED;
}
static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc)
{
struct device *dev = m3_ipc->dev;
mbox_msg_t dummy_msg = 0;
int ret;
if (!m3_ipc->mbox) {
dev_err(dev,
"No IPC channel to communicate with wkup_m3!\n");
return -EIO;
}
/*
* Write a dummy message to the mailbox in order to trigger the RX
* interrupt to alert the M3 that data is available in the IPC
* registers. We must enable the IRQ here and disable it after in
* the RX callback to avoid multiple interrupts being received
* by the CM3.
*/
ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
if (ret < 0) {
dev_err(dev, "%s: mbox_send_message() failed: %d\n",
__func__, ret);
return ret;
}
ret = wait_for_completion_timeout(&m3_ipc->sync_complete,
msecs_to_jiffies(500));
if (!ret) {
dev_err(dev, "MPU<->CM3 sync failure\n");
m3_ipc->state = M3_STATE_UNKNOWN;
return -EIO;
}
mbox_client_txdone(m3_ipc->mbox, 0);
return 0;
}
static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc)
{
struct device *dev = m3_ipc->dev;
mbox_msg_t dummy_msg = 0;
int ret;
if (!m3_ipc->mbox) {
dev_err(dev,
"No IPC channel to communicate with wkup_m3!\n");
return -EIO;
}
ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
if (ret < 0) {
dev_err(dev, "%s: mbox_send_message() failed: %d\n",
__func__, ret);
return ret;
}
mbox_client_txdone(m3_ipc->mbox, 0);
return 0;
}
static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc)
{
return ((m3_ipc->state != M3_STATE_RESET) &&
(m3_ipc->state != M3_STATE_UNKNOWN));
}
static void wkup_m3_set_vtt_gpio(struct wkup_m3_ipc *m3_ipc, int gpio)
{
m3_ipc->vtt_conf = (1 << IPC_VTT_STAT_SHIFT) |
(gpio << IPC_VTT_GPIO_PIN_SHIFT);
}
static void wkup_m3_set_io_isolation(struct wkup_m3_ipc *m3_ipc)
{
m3_ipc->isolation_conf = (1 << IPC_IO_ISOLATION_STAT_SHIFT);
}
/* Public functions */
/**
* wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use
* @m3_ipc: Pointer to wkup_m3_ipc context
* @mem_type: memory type value read directly from emif
*
* wkup_m3 must know what memory type is in use to properly suspend
* and resume.
*/
static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type)
{
m3_ipc->mem_type = mem_type;
}
/**
* wkup_m3_set_resume_address - Pass wkup_m3 resume address
* @m3_ipc: Pointer to wkup_m3_ipc context
* @addr: Physical address from which resume code should execute
*/
static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr)
{
m3_ipc->resume_addr = (unsigned long)addr;
}
/**
* wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend
* @m3_ipc: Pointer to wkup_m3_ipc context
*
* Returns code representing the status of a low power mode transition.
* 0 - Successful transition
* 1 - Failure to transition to low power state
*/
static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc)
{
unsigned int i;
int val;
val = wkup_m3_ctrl_ipc_read(m3_ipc, 1);
i = M3_STATUS_RESP_MASK & val;
i >>= __ffs(M3_STATUS_RESP_MASK);
return i;
}
/**
* wkup_m3_prepare_low_power - Request preparation for transition to
* low power state
* @m3_ipc: Pointer to wkup_m3_ipc context
* @state: A kernel suspend state to enter, either MEM or STANDBY
*
* Returns 0 if preparation was successful, otherwise returns error code
*/
static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state)
{
struct device *dev = m3_ipc->dev;
int m3_power_state;
int ret = 0;
if (!wkup_m3_is_available(m3_ipc))
return -ENODEV;
switch (state) {
case WKUP_M3_DEEPSLEEP:
m3_power_state = IPC_CMD_DS0;
wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->volt_scale_offsets, 5);
break;
case WKUP_M3_STANDBY:
m3_power_state = IPC_CMD_STANDBY;
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
break;
case WKUP_M3_IDLE:
m3_power_state = IPC_CMD_IDLE;
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
break;
default:
return 1;
}
/* Program each required IPC register then write defaults to others */
wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0);
wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1);
wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type |
m3_ipc->vtt_conf |
m3_ipc->isolation_conf |
m3_ipc->halt, 4);
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3);
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 6);
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 7);
m3_ipc->state = M3_STATE_MSG_FOR_LP;
if (state == WKUP_M3_IDLE)
ret = wkup_m3_ping_noirq(m3_ipc);
else
ret = wkup_m3_ping(m3_ipc);
if (ret) {
dev_err(dev, "Unable to ping CM3\n");
return ret;
}
return 0;
}
/**
* wkup_m3_finish_low_power - Return m3 to reset state
* @m3_ipc: Pointer to wkup_m3_ipc context
*
* Returns 0 if reset was successful, otherwise returns error code
*/
static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc)
{
struct device *dev = m3_ipc->dev;
int ret = 0;
if (!wkup_m3_is_available(m3_ipc))
return -ENODEV;
wkup_m3_ctrl_ipc_write(m3_ipc, IPC_CMD_RESET, 1);
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
m3_ipc->state = M3_STATE_MSG_FOR_RESET;
ret = wkup_m3_ping(m3_ipc);
if (ret) {
dev_err(dev, "Unable to ping CM3\n");
return ret;
}
return 0;
}
/**
* wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3
* @m3_ipc: Pointer to wkup_m3_ipc context
*/
static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc)
{
unsigned int wakeup_src_idx;
int j, val;
val = wkup_m3_ctrl_ipc_read(m3_ipc, 6);
wakeup_src_idx = val & M3_WAKE_SRC_MASK;
for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) {
if (wakeups[j].irq_nr == wakeup_src_idx)
return wakeups[j].src;
}
return wakeups[j].src;
}
/**
* wkup_m3_set_rtc_only - Set the rtc_only flag
* @m3_ipc: Pointer to wkup_m3_ipc context
*/
static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc)
{
if (m3_ipc_state)
m3_ipc_state->is_rtc_only = true;
}
static struct wkup_m3_ipc_ops ipc_ops = {
.set_mem_type = wkup_m3_set_mem_type,
.set_resume_address = wkup_m3_set_resume_address,
.prepare_low_power = wkup_m3_prepare_low_power,
.finish_low_power = wkup_m3_finish_low_power,
.request_pm_status = wkup_m3_request_pm_status,
.request_wake_src = wkup_m3_request_wake_src,
.set_rtc_only = wkup_m3_set_rtc_only,
};
/**
* wkup_m3_ipc_get - Return handle to wkup_m3_ipc
*
* Returns NULL if the wkup_m3 is not yet available, otherwise returns
* pointer to wkup_m3_ipc struct.
*/
struct wkup_m3_ipc *wkup_m3_ipc_get(void)
{
if (m3_ipc_state)
get_device(m3_ipc_state->dev);
else
return NULL;
return m3_ipc_state;
}
EXPORT_SYMBOL_GPL(wkup_m3_ipc_get);
/**
* wkup_m3_ipc_put - Free handle to wkup_m3_ipc returned from wkup_m3_ipc_get
* @m3_ipc: A pointer to wkup_m3_ipc struct returned by wkup_m3_ipc_get
*/
void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc)
{
if (m3_ipc_state)
put_device(m3_ipc_state->dev);
}
EXPORT_SYMBOL_GPL(wkup_m3_ipc_put);
static int wkup_m3_rproc_boot_thread(void *arg)
{
struct wkup_m3_ipc *m3_ipc = arg;
struct device *dev = m3_ipc->dev;
int ret;
init_completion(&m3_ipc->sync_complete);
ret = rproc_boot(m3_ipc->rproc);
if (ret)
dev_err(dev, "rproc_boot failed\n");
else
m3_ipc_state = m3_ipc;
return 0;
}
static int wkup_m3_ipc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int irq, ret, temp;
phandle rproc_phandle;
struct rproc *m3_rproc;
struct task_struct *task;
struct wkup_m3_ipc *m3_ipc;
struct device_node *np = dev->of_node;
m3_ipc = devm_kzalloc(dev, sizeof(*m3_ipc), GFP_KERNEL);
if (!m3_ipc)
return -ENOMEM;
m3_ipc->ipc_mem_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(m3_ipc->ipc_mem_base))
return PTR_ERR(m3_ipc->ipc_mem_base);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(dev, irq, wkup_m3_txev_handler,
0, "wkup_m3_txev", m3_ipc);
if (ret) {
dev_err(dev, "request_irq failed\n");
return ret;
}
m3_ipc->mbox_client.dev = dev;
m3_ipc->mbox_client.tx_done = NULL;
m3_ipc->mbox_client.tx_prepare = NULL;
m3_ipc->mbox_client.rx_callback = NULL;
m3_ipc->mbox_client.tx_block = false;
m3_ipc->mbox_client.knows_txdone = false;
m3_ipc->mbox = mbox_request_channel(&m3_ipc->mbox_client, 0);
if (IS_ERR(m3_ipc->mbox)) {
dev_err(dev, "IPC Request for A8->M3 Channel failed! %ld\n",
PTR_ERR(m3_ipc->mbox));
return PTR_ERR(m3_ipc->mbox);
}
if (of_property_read_u32(dev->of_node, "ti,rproc", &rproc_phandle)) {
dev_err(&pdev->dev, "could not get rproc phandle\n");
ret = -ENODEV;
goto err_free_mbox;
}
m3_rproc = rproc_get_by_phandle(rproc_phandle);
if (!m3_rproc) {
dev_err(&pdev->dev, "could not get rproc handle\n");
ret = -EPROBE_DEFER;
goto err_free_mbox;
}
m3_ipc->rproc = m3_rproc;
m3_ipc->dev = dev;
m3_ipc->state = M3_STATE_RESET;
m3_ipc->ops = &ipc_ops;
if (!of_property_read_u32(np, "ti,vtt-gpio-pin", &temp)) {
if (temp >= 0 && temp <= 31)
wkup_m3_set_vtt_gpio(m3_ipc, temp);
else
dev_warn(dev, "Invalid VTT GPIO(%d) pin\n", temp);
}
if (of_property_read_bool(np, "ti,set-io-isolation"))
wkup_m3_set_io_isolation(m3_ipc);
ret = of_property_read_string(np, "firmware-name",
&m3_ipc->sd_fw_name);
if (ret) {
dev_dbg(dev, "Voltage scaling data blob not provided from DT.\n");
}
/*
* Wait for firmware loading completion in a thread so we
* can boot the wkup_m3 as soon as it's ready without holding
* up kernel boot
*/
task = kthread_run(wkup_m3_rproc_boot_thread, m3_ipc,
"wkup_m3_rproc_loader");
if (IS_ERR(task)) {
dev_err(dev, "can't create rproc_boot thread\n");
ret = PTR_ERR(task);
goto err_put_rproc;
}
wkup_m3_ipc_dbg_init(m3_ipc);
return 0;
err_put_rproc:
rproc_put(m3_rproc);
err_free_mbox:
mbox_free_channel(m3_ipc->mbox);
return ret;
}
static int wkup_m3_ipc_remove(struct platform_device *pdev)
{
wkup_m3_ipc_dbg_destroy(m3_ipc_state);
mbox_free_channel(m3_ipc_state->mbox);
rproc_shutdown(m3_ipc_state->rproc);
rproc_put(m3_ipc_state->rproc);
m3_ipc_state = NULL;
return 0;
}
static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev)
{
/*
* Nothing needs to be done on suspend even with rtc_only flag set
*/
return 0;
}
static int __maybe_unused wkup_m3_ipc_resume(struct device *dev)
{
if (m3_ipc_state->is_rtc_only) {
rproc_shutdown(m3_ipc_state->rproc);
rproc_boot(m3_ipc_state->rproc);
}
m3_ipc_state->is_rtc_only = false;
return 0;
}
static const struct dev_pm_ops wkup_m3_ipc_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume)
};
static const struct of_device_id wkup_m3_ipc_of_match[] = {
{ .compatible = "ti,am3352-wkup-m3-ipc", },
{ .compatible = "ti,am4372-wkup-m3-ipc", },
{},
};
MODULE_DEVICE_TABLE(of, wkup_m3_ipc_of_match);
static struct platform_driver wkup_m3_ipc_driver = {
.probe = wkup_m3_ipc_probe,
.remove = wkup_m3_ipc_remove,
.driver = {
.name = "wkup_m3_ipc",
.of_match_table = wkup_m3_ipc_of_match,
.pm = &wkup_m3_ipc_pm_ops,
},
};
module_platform_driver(wkup_m3_ipc_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("wkup m3 remote processor ipc driver");
MODULE_AUTHOR("Dave Gerlach <[email protected]>");
|
linux-master
|
drivers/soc/ti/wkup_m3_ipc.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Texas Instruments Incorporated
* Authors: Santosh Shilimkar <[email protected]>
* Sandeep Nair <[email protected]>
* Cyril Chemparathy <[email protected]>
*/
#include <linux/io.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/dma-direction.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/of_dma.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/soc/ti/knav_dma.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#define REG_MASK 0xffffffff
#define DMA_LOOPBACK BIT(31)
#define DMA_ENABLE BIT(31)
#define DMA_TEARDOWN BIT(30)
#define DMA_TX_FILT_PSWORDS BIT(29)
#define DMA_TX_FILT_EINFO BIT(30)
#define DMA_TX_PRIO_SHIFT 0
#define DMA_RX_PRIO_SHIFT 16
#define DMA_PRIO_MASK GENMASK(3, 0)
#define DMA_PRIO_DEFAULT 0
#define DMA_RX_TIMEOUT_DEFAULT 17500 /* cycles */
#define DMA_RX_TIMEOUT_MASK GENMASK(16, 0)
#define DMA_RX_TIMEOUT_SHIFT 0
#define CHAN_HAS_EPIB BIT(30)
#define CHAN_HAS_PSINFO BIT(29)
#define CHAN_ERR_RETRY BIT(28)
#define CHAN_PSINFO_AT_SOP BIT(25)
#define CHAN_SOP_OFF_SHIFT 16
#define CHAN_SOP_OFF_MASK GENMASK(9, 0)
#define DESC_TYPE_SHIFT 26
#define DESC_TYPE_MASK GENMASK(2, 0)
/*
* QMGR & QNUM together make up 14 bits with QMGR as the 2 MSb's in the logical
* navigator cloud mapping scheme.
* using the 14bit physical queue numbers directly maps into this scheme.
*/
#define CHAN_QNUM_MASK GENMASK(14, 0)
#define DMA_MAX_QMS 4
#define DMA_TIMEOUT 1 /* msecs */
#define DMA_INVALID_ID 0xffff
struct reg_global {
u32 revision;
u32 perf_control;
u32 emulation_control;
u32 priority_control;
u32 qm_base_address[DMA_MAX_QMS];
};
struct reg_chan {
u32 control;
u32 mode;
u32 __rsvd[6];
};
struct reg_tx_sched {
u32 prio;
};
struct reg_rx_flow {
u32 control;
u32 tags;
u32 tag_sel;
u32 fdq_sel[2];
u32 thresh[3];
};
struct knav_dma_pool_device {
struct device *dev;
struct list_head list;
};
struct knav_dma_device {
bool loopback, enable_all;
unsigned tx_priority, rx_priority, rx_timeout;
unsigned logical_queue_managers;
unsigned qm_base_address[DMA_MAX_QMS];
struct reg_global __iomem *reg_global;
struct reg_chan __iomem *reg_tx_chan;
struct reg_rx_flow __iomem *reg_rx_flow;
struct reg_chan __iomem *reg_rx_chan;
struct reg_tx_sched __iomem *reg_tx_sched;
unsigned max_rx_chan, max_tx_chan;
unsigned max_rx_flow;
char name[32];
atomic_t ref_count;
struct list_head list;
struct list_head chan_list;
spinlock_t lock;
};
struct knav_dma_chan {
enum dma_transfer_direction direction;
struct knav_dma_device *dma;
atomic_t ref_count;
/* registers */
struct reg_chan __iomem *reg_chan;
struct reg_tx_sched __iomem *reg_tx_sched;
struct reg_rx_flow __iomem *reg_rx_flow;
/* configuration stuff */
unsigned channel, flow;
struct knav_dma_cfg cfg;
struct list_head list;
spinlock_t lock;
};
#define chan_number(ch) ((ch->direction == DMA_MEM_TO_DEV) ? \
ch->channel : ch->flow)
static struct knav_dma_pool_device *kdev;
static bool device_ready;
bool knav_dma_device_ready(void)
{
return device_ready;
}
EXPORT_SYMBOL_GPL(knav_dma_device_ready);
static bool check_config(struct knav_dma_chan *chan, struct knav_dma_cfg *cfg)
{
if (!memcmp(&chan->cfg, cfg, sizeof(*cfg)))
return true;
else
return false;
}
static int chan_start(struct knav_dma_chan *chan,
struct knav_dma_cfg *cfg)
{
u32 v = 0;
spin_lock(&chan->lock);
if ((chan->direction == DMA_MEM_TO_DEV) && chan->reg_chan) {
if (cfg->u.tx.filt_pswords)
v |= DMA_TX_FILT_PSWORDS;
if (cfg->u.tx.filt_einfo)
v |= DMA_TX_FILT_EINFO;
writel_relaxed(v, &chan->reg_chan->mode);
writel_relaxed(DMA_ENABLE, &chan->reg_chan->control);
}
if (chan->reg_tx_sched)
writel_relaxed(cfg->u.tx.priority, &chan->reg_tx_sched->prio);
if (chan->reg_rx_flow) {
v = 0;
if (cfg->u.rx.einfo_present)
v |= CHAN_HAS_EPIB;
if (cfg->u.rx.psinfo_present)
v |= CHAN_HAS_PSINFO;
if (cfg->u.rx.err_mode == DMA_RETRY)
v |= CHAN_ERR_RETRY;
v |= (cfg->u.rx.desc_type & DESC_TYPE_MASK) << DESC_TYPE_SHIFT;
if (cfg->u.rx.psinfo_at_sop)
v |= CHAN_PSINFO_AT_SOP;
v |= (cfg->u.rx.sop_offset & CHAN_SOP_OFF_MASK)
<< CHAN_SOP_OFF_SHIFT;
v |= cfg->u.rx.dst_q & CHAN_QNUM_MASK;
writel_relaxed(v, &chan->reg_rx_flow->control);
writel_relaxed(0, &chan->reg_rx_flow->tags);
writel_relaxed(0, &chan->reg_rx_flow->tag_sel);
v = cfg->u.rx.fdq[0] << 16;
v |= cfg->u.rx.fdq[1] & CHAN_QNUM_MASK;
writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[0]);
v = cfg->u.rx.fdq[2] << 16;
v |= cfg->u.rx.fdq[3] & CHAN_QNUM_MASK;
writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[1]);
writel_relaxed(0, &chan->reg_rx_flow->thresh[0]);
writel_relaxed(0, &chan->reg_rx_flow->thresh[1]);
writel_relaxed(0, &chan->reg_rx_flow->thresh[2]);
}
/* Keep a copy of the cfg */
memcpy(&chan->cfg, cfg, sizeof(*cfg));
spin_unlock(&chan->lock);
return 0;
}
static int chan_teardown(struct knav_dma_chan *chan)
{
unsigned long end, value;
if (!chan->reg_chan)
return 0;
/* indicate teardown */
writel_relaxed(DMA_TEARDOWN, &chan->reg_chan->control);
/* wait for the dma to shut itself down */
end = jiffies + msecs_to_jiffies(DMA_TIMEOUT);
do {
value = readl_relaxed(&chan->reg_chan->control);
if ((value & DMA_ENABLE) == 0)
break;
} while (time_after(end, jiffies));
if (readl_relaxed(&chan->reg_chan->control) & DMA_ENABLE) {
dev_err(kdev->dev, "timeout waiting for teardown\n");
return -ETIMEDOUT;
}
return 0;
}
static void chan_stop(struct knav_dma_chan *chan)
{
spin_lock(&chan->lock);
if (chan->reg_rx_flow) {
/* first detach fdqs, starve out the flow */
writel_relaxed(0, &chan->reg_rx_flow->fdq_sel[0]);
writel_relaxed(0, &chan->reg_rx_flow->fdq_sel[1]);
writel_relaxed(0, &chan->reg_rx_flow->thresh[0]);
writel_relaxed(0, &chan->reg_rx_flow->thresh[1]);
writel_relaxed(0, &chan->reg_rx_flow->thresh[2]);
}
/* teardown the dma channel */
chan_teardown(chan);
/* then disconnect the completion side */
if (chan->reg_rx_flow) {
writel_relaxed(0, &chan->reg_rx_flow->control);
writel_relaxed(0, &chan->reg_rx_flow->tags);
writel_relaxed(0, &chan->reg_rx_flow->tag_sel);
}
memset(&chan->cfg, 0, sizeof(struct knav_dma_cfg));
spin_unlock(&chan->lock);
dev_dbg(kdev->dev, "channel stopped\n");
}
static void dma_hw_enable_all(struct knav_dma_device *dma)
{
int i;
for (i = 0; i < dma->max_tx_chan; i++) {
writel_relaxed(0, &dma->reg_tx_chan[i].mode);
writel_relaxed(DMA_ENABLE, &dma->reg_tx_chan[i].control);
}
}
static void knav_dma_hw_init(struct knav_dma_device *dma)
{
unsigned v;
int i;
spin_lock(&dma->lock);
v = dma->loopback ? DMA_LOOPBACK : 0;
writel_relaxed(v, &dma->reg_global->emulation_control);
v = readl_relaxed(&dma->reg_global->perf_control);
v |= ((dma->rx_timeout & DMA_RX_TIMEOUT_MASK) << DMA_RX_TIMEOUT_SHIFT);
writel_relaxed(v, &dma->reg_global->perf_control);
v = ((dma->tx_priority << DMA_TX_PRIO_SHIFT) |
(dma->rx_priority << DMA_RX_PRIO_SHIFT));
writel_relaxed(v, &dma->reg_global->priority_control);
/* Always enable all Rx channels. Rx paths are managed using flows */
for (i = 0; i < dma->max_rx_chan; i++)
writel_relaxed(DMA_ENABLE, &dma->reg_rx_chan[i].control);
for (i = 0; i < dma->logical_queue_managers; i++)
writel_relaxed(dma->qm_base_address[i],
&dma->reg_global->qm_base_address[i]);
spin_unlock(&dma->lock);
}
static void knav_dma_hw_destroy(struct knav_dma_device *dma)
{
int i;
unsigned v;
spin_lock(&dma->lock);
v = ~DMA_ENABLE & REG_MASK;
for (i = 0; i < dma->max_rx_chan; i++)
writel_relaxed(v, &dma->reg_rx_chan[i].control);
for (i = 0; i < dma->max_tx_chan; i++)
writel_relaxed(v, &dma->reg_tx_chan[i].control);
spin_unlock(&dma->lock);
}
static void dma_debug_show_channels(struct seq_file *s,
struct knav_dma_chan *chan)
{
int i;
seq_printf(s, "\t%s %d:\t",
((chan->direction == DMA_MEM_TO_DEV) ? "tx chan" : "rx flow"),
chan_number(chan));
if (chan->direction == DMA_MEM_TO_DEV) {
seq_printf(s, "einfo - %d, pswords - %d, priority - %d\n",
chan->cfg.u.tx.filt_einfo,
chan->cfg.u.tx.filt_pswords,
chan->cfg.u.tx.priority);
} else {
seq_printf(s, "einfo - %d, psinfo - %d, desc_type - %d\n",
chan->cfg.u.rx.einfo_present,
chan->cfg.u.rx.psinfo_present,
chan->cfg.u.rx.desc_type);
seq_printf(s, "\t\t\tdst_q: [%d], thresh: %d fdq: ",
chan->cfg.u.rx.dst_q,
chan->cfg.u.rx.thresh);
for (i = 0; i < KNAV_DMA_FDQ_PER_CHAN; i++)
seq_printf(s, "[%d]", chan->cfg.u.rx.fdq[i]);
seq_printf(s, "\n");
}
}
static void dma_debug_show_devices(struct seq_file *s,
struct knav_dma_device *dma)
{
struct knav_dma_chan *chan;
list_for_each_entry(chan, &dma->chan_list, list) {
if (atomic_read(&chan->ref_count))
dma_debug_show_channels(s, chan);
}
}
static int knav_dma_debug_show(struct seq_file *s, void *v)
{
struct knav_dma_device *dma;
list_for_each_entry(dma, &kdev->list, list) {
if (atomic_read(&dma->ref_count)) {
seq_printf(s, "%s : max_tx_chan: (%d), max_rx_flows: (%d)\n",
dma->name, dma->max_tx_chan, dma->max_rx_flow);
dma_debug_show_devices(s, dma);
}
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(knav_dma_debug);
static int of_channel_match_helper(struct device_node *np, const char *name,
const char **dma_instance)
{
struct of_phandle_args args;
struct device_node *dma_node;
int index;
dma_node = of_parse_phandle(np, "ti,navigator-dmas", 0);
if (!dma_node)
return -ENODEV;
*dma_instance = dma_node->name;
index = of_property_match_string(np, "ti,navigator-dma-names", name);
if (index < 0) {
dev_err(kdev->dev, "No 'ti,navigator-dma-names' property\n");
return -ENODEV;
}
if (of_parse_phandle_with_fixed_args(np, "ti,navigator-dmas",
1, index, &args)) {
dev_err(kdev->dev, "Missing the phandle args name %s\n", name);
return -ENODEV;
}
if (args.args[0] < 0) {
dev_err(kdev->dev, "Missing args for %s\n", name);
return -ENODEV;
}
return args.args[0];
}
/**
* knav_dma_open_channel() - try to setup an exclusive slave channel
* @dev: pointer to client device structure
* @name: slave channel name
* @config: dma configuration parameters
*
* Returns pointer to appropriate DMA channel on success or error.
*/
void *knav_dma_open_channel(struct device *dev, const char *name,
struct knav_dma_cfg *config)
{
struct knav_dma_device *dma = NULL, *iter1;
struct knav_dma_chan *chan = NULL, *iter2;
int chan_num = -1;
const char *instance;
if (!kdev) {
pr_err("keystone-navigator-dma driver not registered\n");
return (void *)-EINVAL;
}
chan_num = of_channel_match_helper(dev->of_node, name, &instance);
if (chan_num < 0) {
dev_err(kdev->dev, "No DMA instance with name %s\n", name);
return (void *)-EINVAL;
}
dev_dbg(kdev->dev, "initializing %s channel %d from DMA %s\n",
config->direction == DMA_MEM_TO_DEV ? "transmit" :
config->direction == DMA_DEV_TO_MEM ? "receive" :
"unknown", chan_num, instance);
if (config->direction != DMA_MEM_TO_DEV &&
config->direction != DMA_DEV_TO_MEM) {
dev_err(kdev->dev, "bad direction\n");
return (void *)-EINVAL;
}
/* Look for correct dma instance */
list_for_each_entry(iter1, &kdev->list, list) {
if (!strcmp(iter1->name, instance)) {
dma = iter1;
break;
}
}
if (!dma) {
dev_err(kdev->dev, "No DMA instance with name %s\n", instance);
return (void *)-EINVAL;
}
/* Look for correct dma channel from dma instance */
list_for_each_entry(iter2, &dma->chan_list, list) {
if (config->direction == DMA_MEM_TO_DEV) {
if (iter2->channel == chan_num) {
chan = iter2;
break;
}
} else {
if (iter2->flow == chan_num) {
chan = iter2;
break;
}
}
}
if (!chan) {
dev_err(kdev->dev, "channel %d is not in DMA %s\n",
chan_num, instance);
return (void *)-EINVAL;
}
if (atomic_read(&chan->ref_count) >= 1) {
if (!check_config(chan, config)) {
dev_err(kdev->dev, "channel %d config miss-match\n",
chan_num);
return (void *)-EINVAL;
}
}
if (atomic_inc_return(&chan->dma->ref_count) <= 1)
knav_dma_hw_init(chan->dma);
if (atomic_inc_return(&chan->ref_count) <= 1)
chan_start(chan, config);
dev_dbg(kdev->dev, "channel %d opened from DMA %s\n",
chan_num, instance);
return chan;
}
EXPORT_SYMBOL_GPL(knav_dma_open_channel);
/**
* knav_dma_close_channel() - Destroy a dma channel
*
* @channel: dma channel handle
*
*/
void knav_dma_close_channel(void *channel)
{
struct knav_dma_chan *chan = channel;
if (!kdev) {
pr_err("keystone-navigator-dma driver not registered\n");
return;
}
if (atomic_dec_return(&chan->ref_count) <= 0)
chan_stop(chan);
if (atomic_dec_return(&chan->dma->ref_count) <= 0)
knav_dma_hw_destroy(chan->dma);
dev_dbg(kdev->dev, "channel %d or flow %d closed from DMA %s\n",
chan->channel, chan->flow, chan->dma->name);
}
EXPORT_SYMBOL_GPL(knav_dma_close_channel);
static void __iomem *pktdma_get_regs(struct knav_dma_device *dma,
struct device_node *node,
unsigned index, resource_size_t *_size)
{
struct device *dev = kdev->dev;
struct resource res;
void __iomem *regs;
int ret;
ret = of_address_to_resource(node, index, &res);
if (ret) {
dev_err(dev, "Can't translate of node(%pOFn) address for index(%d)\n",
node, index);
return ERR_PTR(ret);
}
regs = devm_ioremap_resource(kdev->dev, &res);
if (IS_ERR(regs))
dev_err(dev, "Failed to map register base for index(%d) node(%pOFn)\n",
index, node);
if (_size)
*_size = resource_size(&res);
return regs;
}
static int pktdma_init_rx_chan(struct knav_dma_chan *chan, u32 flow)
{
struct knav_dma_device *dma = chan->dma;
chan->flow = flow;
chan->reg_rx_flow = dma->reg_rx_flow + flow;
chan->channel = DMA_INVALID_ID;
dev_dbg(kdev->dev, "rx flow(%d) (%p)\n", chan->flow, chan->reg_rx_flow);
return 0;
}
static int pktdma_init_tx_chan(struct knav_dma_chan *chan, u32 channel)
{
struct knav_dma_device *dma = chan->dma;
chan->channel = channel;
chan->reg_chan = dma->reg_tx_chan + channel;
chan->reg_tx_sched = dma->reg_tx_sched + channel;
chan->flow = DMA_INVALID_ID;
dev_dbg(kdev->dev, "tx channel(%d) (%p)\n", chan->channel, chan->reg_chan);
return 0;
}
static int pktdma_init_chan(struct knav_dma_device *dma,
enum dma_transfer_direction dir,
unsigned chan_num)
{
struct device *dev = kdev->dev;
struct knav_dma_chan *chan;
int ret = -EINVAL;
chan = devm_kzalloc(dev, sizeof(*chan), GFP_KERNEL);
if (!chan)
return -ENOMEM;
INIT_LIST_HEAD(&chan->list);
chan->dma = dma;
chan->direction = DMA_TRANS_NONE;
atomic_set(&chan->ref_count, 0);
spin_lock_init(&chan->lock);
if (dir == DMA_MEM_TO_DEV) {
chan->direction = dir;
ret = pktdma_init_tx_chan(chan, chan_num);
} else if (dir == DMA_DEV_TO_MEM) {
chan->direction = dir;
ret = pktdma_init_rx_chan(chan, chan_num);
} else {
dev_err(dev, "channel(%d) direction unknown\n", chan_num);
}
list_add_tail(&chan->list, &dma->chan_list);
return ret;
}
static int dma_init(struct device_node *cloud, struct device_node *dma_node)
{
unsigned max_tx_chan, max_rx_chan, max_rx_flow, max_tx_sched;
struct device_node *node = dma_node;
struct knav_dma_device *dma;
int ret, len, num_chan = 0;
resource_size_t size;
u32 timeout;
u32 i;
dma = devm_kzalloc(kdev->dev, sizeof(*dma), GFP_KERNEL);
if (!dma) {
dev_err(kdev->dev, "could not allocate driver mem\n");
return -ENOMEM;
}
INIT_LIST_HEAD(&dma->list);
INIT_LIST_HEAD(&dma->chan_list);
if (!of_find_property(cloud, "ti,navigator-cloud-address", &len)) {
dev_err(kdev->dev, "unspecified navigator cloud addresses\n");
return -ENODEV;
}
dma->logical_queue_managers = len / sizeof(u32);
if (dma->logical_queue_managers > DMA_MAX_QMS) {
dev_warn(kdev->dev, "too many queue mgrs(>%d) rest ignored\n",
dma->logical_queue_managers);
dma->logical_queue_managers = DMA_MAX_QMS;
}
ret = of_property_read_u32_array(cloud, "ti,navigator-cloud-address",
dma->qm_base_address,
dma->logical_queue_managers);
if (ret) {
dev_err(kdev->dev, "invalid navigator cloud addresses\n");
return -ENODEV;
}
dma->reg_global = pktdma_get_regs(dma, node, 0, &size);
if (IS_ERR(dma->reg_global))
return PTR_ERR(dma->reg_global);
if (size < sizeof(struct reg_global)) {
dev_err(kdev->dev, "bad size %pa for global regs\n", &size);
return -ENODEV;
}
dma->reg_tx_chan = pktdma_get_regs(dma, node, 1, &size);
if (IS_ERR(dma->reg_tx_chan))
return PTR_ERR(dma->reg_tx_chan);
max_tx_chan = size / sizeof(struct reg_chan);
dma->reg_rx_chan = pktdma_get_regs(dma, node, 2, &size);
if (IS_ERR(dma->reg_rx_chan))
return PTR_ERR(dma->reg_rx_chan);
max_rx_chan = size / sizeof(struct reg_chan);
dma->reg_tx_sched = pktdma_get_regs(dma, node, 3, &size);
if (IS_ERR(dma->reg_tx_sched))
return PTR_ERR(dma->reg_tx_sched);
max_tx_sched = size / sizeof(struct reg_tx_sched);
dma->reg_rx_flow = pktdma_get_regs(dma, node, 4, &size);
if (IS_ERR(dma->reg_rx_flow))
return PTR_ERR(dma->reg_rx_flow);
max_rx_flow = size / sizeof(struct reg_rx_flow);
dma->rx_priority = DMA_PRIO_DEFAULT;
dma->tx_priority = DMA_PRIO_DEFAULT;
dma->enable_all = of_property_read_bool(node, "ti,enable-all");
dma->loopback = of_property_read_bool(node, "ti,loop-back");
ret = of_property_read_u32(node, "ti,rx-retry-timeout", &timeout);
if (ret < 0) {
dev_dbg(kdev->dev, "unspecified rx timeout using value %d\n",
DMA_RX_TIMEOUT_DEFAULT);
timeout = DMA_RX_TIMEOUT_DEFAULT;
}
dma->rx_timeout = timeout;
dma->max_rx_chan = max_rx_chan;
dma->max_rx_flow = max_rx_flow;
dma->max_tx_chan = min(max_tx_chan, max_tx_sched);
atomic_set(&dma->ref_count, 0);
strcpy(dma->name, node->name);
spin_lock_init(&dma->lock);
for (i = 0; i < dma->max_tx_chan; i++) {
if (pktdma_init_chan(dma, DMA_MEM_TO_DEV, i) >= 0)
num_chan++;
}
for (i = 0; i < dma->max_rx_flow; i++) {
if (pktdma_init_chan(dma, DMA_DEV_TO_MEM, i) >= 0)
num_chan++;
}
list_add_tail(&dma->list, &kdev->list);
/*
* For DSP software usecases or userpace transport software, setup all
* the DMA hardware resources.
*/
if (dma->enable_all) {
atomic_inc(&dma->ref_count);
knav_dma_hw_init(dma);
dma_hw_enable_all(dma);
}
dev_info(kdev->dev, "DMA %s registered %d logical channels, flows %d, tx chans: %d, rx chans: %d%s\n",
dma->name, num_chan, dma->max_rx_flow,
dma->max_tx_chan, dma->max_rx_chan,
dma->loopback ? ", loopback" : "");
return 0;
}
static int knav_dma_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = pdev->dev.of_node;
struct device_node *child;
int ret = 0;
if (!node) {
dev_err(&pdev->dev, "could not find device info\n");
return -EINVAL;
}
kdev = devm_kzalloc(dev,
sizeof(struct knav_dma_pool_device), GFP_KERNEL);
if (!kdev) {
dev_err(dev, "could not allocate driver mem\n");
return -ENOMEM;
}
kdev->dev = dev;
INIT_LIST_HEAD(&kdev->list);
pm_runtime_enable(kdev->dev);
ret = pm_runtime_resume_and_get(kdev->dev);
if (ret < 0) {
dev_err(kdev->dev, "unable to enable pktdma, err %d\n", ret);
goto err_pm_disable;
}
/* Initialise all packet dmas */
for_each_child_of_node(node, child) {
ret = dma_init(node, child);
if (ret) {
of_node_put(child);
dev_err(&pdev->dev, "init failed with %d\n", ret);
break;
}
}
if (list_empty(&kdev->list)) {
dev_err(dev, "no valid dma instance\n");
ret = -ENODEV;
goto err_put_sync;
}
debugfs_create_file("knav_dma", S_IFREG | S_IRUGO, NULL, NULL,
&knav_dma_debug_fops);
device_ready = true;
return ret;
err_put_sync:
pm_runtime_put_sync(kdev->dev);
err_pm_disable:
pm_runtime_disable(kdev->dev);
return ret;
}
static int knav_dma_remove(struct platform_device *pdev)
{
struct knav_dma_device *dma;
list_for_each_entry(dma, &kdev->list, list) {
if (atomic_dec_return(&dma->ref_count) == 0)
knav_dma_hw_destroy(dma);
}
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return 0;
}
static struct of_device_id of_match[] = {
{ .compatible = "ti,keystone-navigator-dma", },
{},
};
MODULE_DEVICE_TABLE(of, of_match);
static struct platform_driver knav_dma_driver = {
.probe = knav_dma_probe,
.remove = knav_dma_remove,
.driver = {
.name = "keystone-navigator-dma",
.of_match_table = of_match,
},
};
module_platform_driver(knav_dma_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("TI Keystone Navigator Packet DMA driver");
MODULE_AUTHOR("Sandeep Nair <[email protected]>");
MODULE_AUTHOR("Santosh Shilimkar <[email protected]>");
|
linux-master
|
drivers/soc/ti/knav_dma.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Texas Instruments' K3 Interrupt Aggregator MSI bus
*
* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
* Lokesh Vutla <[email protected]>
*/
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/msi.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/soc/ti/ti_sci_inta_msi.h>
#include <linux/soc/ti/ti_sci_protocol.h>
static void ti_sci_inta_msi_write_msg(struct irq_data *data,
struct msi_msg *msg)
{
/* Nothing to do */
}
static void ti_sci_inta_msi_compose_msi_msg(struct irq_data *data,
struct msi_msg *msg)
{
/* Nothing to do */
}
static void ti_sci_inta_msi_update_chip_ops(struct msi_domain_info *info)
{
struct irq_chip *chip = info->chip;
if (WARN_ON(!chip))
return;
chip->irq_request_resources = irq_chip_request_resources_parent;
chip->irq_release_resources = irq_chip_release_resources_parent;
chip->irq_compose_msi_msg = ti_sci_inta_msi_compose_msi_msg;
chip->irq_write_msi_msg = ti_sci_inta_msi_write_msg;
chip->irq_set_type = irq_chip_set_type_parent;
chip->irq_unmask = irq_chip_unmask_parent;
chip->irq_mask = irq_chip_mask_parent;
chip->irq_ack = irq_chip_ack_parent;
}
struct irq_domain *ti_sci_inta_msi_create_irq_domain(struct fwnode_handle *fwnode,
struct msi_domain_info *info,
struct irq_domain *parent)
{
struct irq_domain *domain;
ti_sci_inta_msi_update_chip_ops(info);
info->flags |= MSI_FLAG_FREE_MSI_DESCS;
domain = msi_create_irq_domain(fwnode, info, parent);
if (domain)
irq_domain_update_bus_token(domain, DOMAIN_BUS_TI_SCI_INTA_MSI);
return domain;
}
EXPORT_SYMBOL_GPL(ti_sci_inta_msi_create_irq_domain);
static int ti_sci_inta_msi_alloc_descs(struct device *dev,
struct ti_sci_resource *res)
{
struct msi_desc msi_desc;
int set, i, count = 0;
memset(&msi_desc, 0, sizeof(msi_desc));
msi_desc.nvec_used = 1;
for (set = 0; set < res->sets; set++) {
for (i = 0; i < res->desc[set].num; i++, count++) {
msi_desc.msi_index = res->desc[set].start + i;
if (msi_insert_msi_desc(dev, &msi_desc))
goto fail;
}
for (i = 0; i < res->desc[set].num_sec; i++, count++) {
msi_desc.msi_index = res->desc[set].start_sec + i;
if (msi_insert_msi_desc(dev, &msi_desc))
goto fail;
}
}
return count;
fail:
msi_free_msi_descs(dev);
return -ENOMEM;
}
int ti_sci_inta_msi_domain_alloc_irqs(struct device *dev,
struct ti_sci_resource *res)
{
struct platform_device *pdev = to_platform_device(dev);
int ret, nvec;
if (pdev->id < 0)
return -ENODEV;
ret = msi_setup_device_data(dev);
if (ret)
return ret;
msi_lock_descs(dev);
nvec = ti_sci_inta_msi_alloc_descs(dev, res);
if (nvec <= 0) {
ret = nvec;
goto unlock;
}
/* Use alloc ALL as it's unclear whether there are gaps in the indices */
ret = msi_domain_alloc_irqs_all_locked(dev, MSI_DEFAULT_DOMAIN, nvec);
if (ret)
dev_err(dev, "Failed to allocate IRQs %d\n", ret);
unlock:
msi_unlock_descs(dev);
return ret;
}
EXPORT_SYMBOL_GPL(ti_sci_inta_msi_domain_alloc_irqs);
|
linux-master
|
drivers/soc/ti/ti_sci_inta_msi.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Keystone Queue Manager subsystem driver
*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
* Authors: Sandeep Nair <[email protected]>
* Cyril Chemparathy <[email protected]>
* Santosh Shilimkar <[email protected]>
*/
#include <linux/debugfs.h>
#include <linux/dma-mapping.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/soc/ti/knav_qmss.h>
#include "knav_qmss.h"
static struct knav_device *kdev;
static DEFINE_MUTEX(knav_dev_lock);
#define knav_dev_lock_held() \
lockdep_is_held(&knav_dev_lock)
/* Queue manager register indices in DTS */
#define KNAV_QUEUE_PEEK_REG_INDEX 0
#define KNAV_QUEUE_STATUS_REG_INDEX 1
#define KNAV_QUEUE_CONFIG_REG_INDEX 2
#define KNAV_QUEUE_REGION_REG_INDEX 3
#define KNAV_QUEUE_PUSH_REG_INDEX 4
#define KNAV_QUEUE_POP_REG_INDEX 5
/* Queue manager register indices in DTS for QMSS in K2G NAVSS.
* There are no status and vbusm push registers on this version
* of QMSS. Push registers are same as pop, So all indices above 1
* are to be re-defined
*/
#define KNAV_L_QUEUE_CONFIG_REG_INDEX 1
#define KNAV_L_QUEUE_REGION_REG_INDEX 2
#define KNAV_L_QUEUE_PUSH_REG_INDEX 3
/* PDSP register indices in DTS */
#define KNAV_QUEUE_PDSP_IRAM_REG_INDEX 0
#define KNAV_QUEUE_PDSP_REGS_REG_INDEX 1
#define KNAV_QUEUE_PDSP_INTD_REG_INDEX 2
#define KNAV_QUEUE_PDSP_CMD_REG_INDEX 3
#define knav_queue_idx_to_inst(kdev, idx) \
(kdev->instances + (idx << kdev->inst_shift))
#define for_each_handle_rcu(qh, inst) \
list_for_each_entry_rcu(qh, &inst->handles, list, \
knav_dev_lock_held())
#define for_each_instance(idx, inst, kdev) \
for (idx = 0, inst = kdev->instances; \
idx < (kdev)->num_queues_in_use; \
idx++, inst = knav_queue_idx_to_inst(kdev, idx))
/* All firmware file names end up here. List the firmware file names below.
* Newest followed by older ones. Search is done from start of the array
* until a firmware file is found.
*/
static const char * const knav_acc_firmwares[] = {"ks2_qmss_pdsp_acc48.bin"};
static bool device_ready;
bool knav_qmss_device_ready(void)
{
return device_ready;
}
EXPORT_SYMBOL_GPL(knav_qmss_device_ready);
/**
* knav_queue_notify: qmss queue notfier call
*
* @inst: - qmss queue instance like accumulator
*/
void knav_queue_notify(struct knav_queue_inst *inst)
{
struct knav_queue *qh;
if (!inst)
return;
rcu_read_lock();
for_each_handle_rcu(qh, inst) {
if (atomic_read(&qh->notifier_enabled) <= 0)
continue;
if (WARN_ON(!qh->notifier_fn))
continue;
this_cpu_inc(qh->stats->notifies);
qh->notifier_fn(qh->notifier_fn_arg);
}
rcu_read_unlock();
}
EXPORT_SYMBOL_GPL(knav_queue_notify);
static irqreturn_t knav_queue_int_handler(int irq, void *_instdata)
{
struct knav_queue_inst *inst = _instdata;
knav_queue_notify(inst);
return IRQ_HANDLED;
}
static int knav_queue_setup_irq(struct knav_range_info *range,
struct knav_queue_inst *inst)
{
unsigned queue = inst->id - range->queue_base;
int ret = 0, irq;
if (range->flags & RANGE_HAS_IRQ) {
irq = range->irqs[queue].irq;
ret = request_irq(irq, knav_queue_int_handler, 0,
inst->irq_name, inst);
if (ret)
return ret;
disable_irq(irq);
if (range->irqs[queue].cpu_mask) {
ret = irq_set_affinity_hint(irq, range->irqs[queue].cpu_mask);
if (ret) {
dev_warn(range->kdev->dev,
"Failed to set IRQ affinity\n");
return ret;
}
}
}
return ret;
}
static void knav_queue_free_irq(struct knav_queue_inst *inst)
{
struct knav_range_info *range = inst->range;
unsigned queue = inst->id - inst->range->queue_base;
int irq;
if (range->flags & RANGE_HAS_IRQ) {
irq = range->irqs[queue].irq;
irq_set_affinity_hint(irq, NULL);
free_irq(irq, inst);
}
}
static inline bool knav_queue_is_busy(struct knav_queue_inst *inst)
{
return !list_empty(&inst->handles);
}
static inline bool knav_queue_is_reserved(struct knav_queue_inst *inst)
{
return inst->range->flags & RANGE_RESERVED;
}
static inline bool knav_queue_is_shared(struct knav_queue_inst *inst)
{
struct knav_queue *tmp;
rcu_read_lock();
for_each_handle_rcu(tmp, inst) {
if (tmp->flags & KNAV_QUEUE_SHARED) {
rcu_read_unlock();
return true;
}
}
rcu_read_unlock();
return false;
}
static inline bool knav_queue_match_type(struct knav_queue_inst *inst,
unsigned type)
{
if ((type == KNAV_QUEUE_QPEND) &&
(inst->range->flags & RANGE_HAS_IRQ)) {
return true;
} else if ((type == KNAV_QUEUE_ACC) &&
(inst->range->flags & RANGE_HAS_ACCUMULATOR)) {
return true;
} else if ((type == KNAV_QUEUE_GP) &&
!(inst->range->flags &
(RANGE_HAS_ACCUMULATOR | RANGE_HAS_IRQ))) {
return true;
}
return false;
}
static inline struct knav_queue_inst *
knav_queue_match_id_to_inst(struct knav_device *kdev, unsigned id)
{
struct knav_queue_inst *inst;
int idx;
for_each_instance(idx, inst, kdev) {
if (inst->id == id)
return inst;
}
return NULL;
}
static inline struct knav_queue_inst *knav_queue_find_by_id(int id)
{
if (kdev->base_id <= id &&
kdev->base_id + kdev->num_queues > id) {
id -= kdev->base_id;
return knav_queue_match_id_to_inst(kdev, id);
}
return NULL;
}
static struct knav_queue *__knav_queue_open(struct knav_queue_inst *inst,
const char *name, unsigned flags)
{
struct knav_queue *qh;
unsigned id;
int ret = 0;
qh = devm_kzalloc(inst->kdev->dev, sizeof(*qh), GFP_KERNEL);
if (!qh)
return ERR_PTR(-ENOMEM);
qh->stats = alloc_percpu(struct knav_queue_stats);
if (!qh->stats) {
ret = -ENOMEM;
goto err;
}
qh->flags = flags;
qh->inst = inst;
id = inst->id - inst->qmgr->start_queue;
qh->reg_push = &inst->qmgr->reg_push[id];
qh->reg_pop = &inst->qmgr->reg_pop[id];
qh->reg_peek = &inst->qmgr->reg_peek[id];
/* first opener? */
if (!knav_queue_is_busy(inst)) {
struct knav_range_info *range = inst->range;
inst->name = kstrndup(name, KNAV_NAME_SIZE - 1, GFP_KERNEL);
if (range->ops && range->ops->open_queue)
ret = range->ops->open_queue(range, inst, flags);
if (ret)
goto err;
}
list_add_tail_rcu(&qh->list, &inst->handles);
return qh;
err:
if (qh->stats)
free_percpu(qh->stats);
devm_kfree(inst->kdev->dev, qh);
return ERR_PTR(ret);
}
static struct knav_queue *
knav_queue_open_by_id(const char *name, unsigned id, unsigned flags)
{
struct knav_queue_inst *inst;
struct knav_queue *qh;
mutex_lock(&knav_dev_lock);
qh = ERR_PTR(-ENODEV);
inst = knav_queue_find_by_id(id);
if (!inst)
goto unlock_ret;
qh = ERR_PTR(-EEXIST);
if (!(flags & KNAV_QUEUE_SHARED) && knav_queue_is_busy(inst))
goto unlock_ret;
qh = ERR_PTR(-EBUSY);
if ((flags & KNAV_QUEUE_SHARED) &&
(knav_queue_is_busy(inst) && !knav_queue_is_shared(inst)))
goto unlock_ret;
qh = __knav_queue_open(inst, name, flags);
unlock_ret:
mutex_unlock(&knav_dev_lock);
return qh;
}
static struct knav_queue *knav_queue_open_by_type(const char *name,
unsigned type, unsigned flags)
{
struct knav_queue_inst *inst;
struct knav_queue *qh = ERR_PTR(-EINVAL);
int idx;
mutex_lock(&knav_dev_lock);
for_each_instance(idx, inst, kdev) {
if (knav_queue_is_reserved(inst))
continue;
if (!knav_queue_match_type(inst, type))
continue;
if (knav_queue_is_busy(inst))
continue;
qh = __knav_queue_open(inst, name, flags);
goto unlock_ret;
}
unlock_ret:
mutex_unlock(&knav_dev_lock);
return qh;
}
static void knav_queue_set_notify(struct knav_queue_inst *inst, bool enabled)
{
struct knav_range_info *range = inst->range;
if (range->ops && range->ops->set_notify)
range->ops->set_notify(range, inst, enabled);
}
static int knav_queue_enable_notifier(struct knav_queue *qh)
{
struct knav_queue_inst *inst = qh->inst;
bool first;
if (WARN_ON(!qh->notifier_fn))
return -EINVAL;
/* Adjust the per handle notifier count */
first = (atomic_inc_return(&qh->notifier_enabled) == 1);
if (!first)
return 0; /* nothing to do */
/* Now adjust the per instance notifier count */
first = (atomic_inc_return(&inst->num_notifiers) == 1);
if (first)
knav_queue_set_notify(inst, true);
return 0;
}
static int knav_queue_disable_notifier(struct knav_queue *qh)
{
struct knav_queue_inst *inst = qh->inst;
bool last;
last = (atomic_dec_return(&qh->notifier_enabled) == 0);
if (!last)
return 0; /* nothing to do */
last = (atomic_dec_return(&inst->num_notifiers) == 0);
if (last)
knav_queue_set_notify(inst, false);
return 0;
}
static int knav_queue_set_notifier(struct knav_queue *qh,
struct knav_queue_notify_config *cfg)
{
knav_queue_notify_fn old_fn = qh->notifier_fn;
if (!cfg)
return -EINVAL;
if (!(qh->inst->range->flags & (RANGE_HAS_ACCUMULATOR | RANGE_HAS_IRQ)))
return -ENOTSUPP;
if (!cfg->fn && old_fn)
knav_queue_disable_notifier(qh);
qh->notifier_fn = cfg->fn;
qh->notifier_fn_arg = cfg->fn_arg;
if (cfg->fn && !old_fn)
knav_queue_enable_notifier(qh);
return 0;
}
static int knav_gp_set_notify(struct knav_range_info *range,
struct knav_queue_inst *inst,
bool enabled)
{
unsigned queue;
if (range->flags & RANGE_HAS_IRQ) {
queue = inst->id - range->queue_base;
if (enabled)
enable_irq(range->irqs[queue].irq);
else
disable_irq_nosync(range->irqs[queue].irq);
}
return 0;
}
static int knav_gp_open_queue(struct knav_range_info *range,
struct knav_queue_inst *inst, unsigned flags)
{
return knav_queue_setup_irq(range, inst);
}
static int knav_gp_close_queue(struct knav_range_info *range,
struct knav_queue_inst *inst)
{
knav_queue_free_irq(inst);
return 0;
}
static struct knav_range_ops knav_gp_range_ops = {
.set_notify = knav_gp_set_notify,
.open_queue = knav_gp_open_queue,
.close_queue = knav_gp_close_queue,
};
static int knav_queue_get_count(void *qhandle)
{
struct knav_queue *qh = qhandle;
struct knav_queue_inst *inst = qh->inst;
return readl_relaxed(&qh->reg_peek[0].entry_count) +
atomic_read(&inst->desc_count);
}
static void knav_queue_debug_show_instance(struct seq_file *s,
struct knav_queue_inst *inst)
{
struct knav_device *kdev = inst->kdev;
struct knav_queue *qh;
int cpu = 0;
int pushes = 0;
int pops = 0;
int push_errors = 0;
int pop_errors = 0;
int notifies = 0;
if (!knav_queue_is_busy(inst))
return;
seq_printf(s, "\tqueue id %d (%s)\n",
kdev->base_id + inst->id, inst->name);
for_each_handle_rcu(qh, inst) {
for_each_possible_cpu(cpu) {
pushes += per_cpu_ptr(qh->stats, cpu)->pushes;
pops += per_cpu_ptr(qh->stats, cpu)->pops;
push_errors += per_cpu_ptr(qh->stats, cpu)->push_errors;
pop_errors += per_cpu_ptr(qh->stats, cpu)->pop_errors;
notifies += per_cpu_ptr(qh->stats, cpu)->notifies;
}
seq_printf(s, "\t\thandle %p: pushes %8d, pops %8d, count %8d, notifies %8d, push errors %8d, pop errors %8d\n",
qh,
pushes,
pops,
knav_queue_get_count(qh),
notifies,
push_errors,
pop_errors);
}
}
static int knav_queue_debug_show(struct seq_file *s, void *v)
{
struct knav_queue_inst *inst;
int idx;
mutex_lock(&knav_dev_lock);
seq_printf(s, "%s: %u-%u\n",
dev_name(kdev->dev), kdev->base_id,
kdev->base_id + kdev->num_queues - 1);
for_each_instance(idx, inst, kdev)
knav_queue_debug_show_instance(s, inst);
mutex_unlock(&knav_dev_lock);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(knav_queue_debug);
static inline int knav_queue_pdsp_wait(u32 * __iomem addr, unsigned timeout,
u32 flags)
{
unsigned long end;
u32 val = 0;
end = jiffies + msecs_to_jiffies(timeout);
while (time_after(end, jiffies)) {
val = readl_relaxed(addr);
if (flags)
val &= flags;
if (!val)
break;
cpu_relax();
}
return val ? -ETIMEDOUT : 0;
}
static int knav_queue_flush(struct knav_queue *qh)
{
struct knav_queue_inst *inst = qh->inst;
unsigned id = inst->id - inst->qmgr->start_queue;
atomic_set(&inst->desc_count, 0);
writel_relaxed(0, &inst->qmgr->reg_push[id].ptr_size_thresh);
return 0;
}
/**
* knav_queue_open() - open a hardware queue
* @name: - name to give the queue handle
* @id: - desired queue number if any or specifes the type
* of queue
* @flags: - the following flags are applicable to queues:
* KNAV_QUEUE_SHARED - allow the queue to be shared. Queues are
* exclusive by default.
* Subsequent attempts to open a shared queue should
* also have this flag.
*
* Returns a handle to the open hardware queue if successful. Use IS_ERR()
* to check the returned value for error codes.
*/
void *knav_queue_open(const char *name, unsigned id,
unsigned flags)
{
struct knav_queue *qh = ERR_PTR(-EINVAL);
switch (id) {
case KNAV_QUEUE_QPEND:
case KNAV_QUEUE_ACC:
case KNAV_QUEUE_GP:
qh = knav_queue_open_by_type(name, id, flags);
break;
default:
qh = knav_queue_open_by_id(name, id, flags);
break;
}
return qh;
}
EXPORT_SYMBOL_GPL(knav_queue_open);
/**
* knav_queue_close() - close a hardware queue handle
* @qhandle: - handle to close
*/
void knav_queue_close(void *qhandle)
{
struct knav_queue *qh = qhandle;
struct knav_queue_inst *inst = qh->inst;
while (atomic_read(&qh->notifier_enabled) > 0)
knav_queue_disable_notifier(qh);
mutex_lock(&knav_dev_lock);
list_del_rcu(&qh->list);
mutex_unlock(&knav_dev_lock);
synchronize_rcu();
if (!knav_queue_is_busy(inst)) {
struct knav_range_info *range = inst->range;
if (range->ops && range->ops->close_queue)
range->ops->close_queue(range, inst);
}
free_percpu(qh->stats);
devm_kfree(inst->kdev->dev, qh);
}
EXPORT_SYMBOL_GPL(knav_queue_close);
/**
* knav_queue_device_control() - Perform control operations on a queue
* @qhandle: - queue handle
* @cmd: - control commands
* @arg: - command argument
*
* Returns 0 on success, errno otherwise.
*/
int knav_queue_device_control(void *qhandle, enum knav_queue_ctrl_cmd cmd,
unsigned long arg)
{
struct knav_queue *qh = qhandle;
struct knav_queue_notify_config *cfg;
int ret;
switch ((int)cmd) {
case KNAV_QUEUE_GET_ID:
ret = qh->inst->kdev->base_id + qh->inst->id;
break;
case KNAV_QUEUE_FLUSH:
ret = knav_queue_flush(qh);
break;
case KNAV_QUEUE_SET_NOTIFIER:
cfg = (void *)arg;
ret = knav_queue_set_notifier(qh, cfg);
break;
case KNAV_QUEUE_ENABLE_NOTIFY:
ret = knav_queue_enable_notifier(qh);
break;
case KNAV_QUEUE_DISABLE_NOTIFY:
ret = knav_queue_disable_notifier(qh);
break;
case KNAV_QUEUE_GET_COUNT:
ret = knav_queue_get_count(qh);
break;
default:
ret = -ENOTSUPP;
break;
}
return ret;
}
EXPORT_SYMBOL_GPL(knav_queue_device_control);
/**
* knav_queue_push() - push data (or descriptor) to the tail of a queue
* @qhandle: - hardware queue handle
* @dma: - DMA data to push
* @size: - size of data to push
* @flags: - can be used to pass additional information
*
* Returns 0 on success, errno otherwise.
*/
int knav_queue_push(void *qhandle, dma_addr_t dma,
unsigned size, unsigned flags)
{
struct knav_queue *qh = qhandle;
u32 val;
val = (u32)dma | ((size / 16) - 1);
writel_relaxed(val, &qh->reg_push[0].ptr_size_thresh);
this_cpu_inc(qh->stats->pushes);
return 0;
}
EXPORT_SYMBOL_GPL(knav_queue_push);
/**
* knav_queue_pop() - pop data (or descriptor) from the head of a queue
* @qhandle: - hardware queue handle
* @size: - (optional) size of the data pop'ed.
*
* Returns a DMA address on success, 0 on failure.
*/
dma_addr_t knav_queue_pop(void *qhandle, unsigned *size)
{
struct knav_queue *qh = qhandle;
struct knav_queue_inst *inst = qh->inst;
dma_addr_t dma;
u32 val, idx;
/* are we accumulated? */
if (inst->descs) {
if (unlikely(atomic_dec_return(&inst->desc_count) < 0)) {
atomic_inc(&inst->desc_count);
return 0;
}
idx = atomic_inc_return(&inst->desc_head);
idx &= ACC_DESCS_MASK;
val = inst->descs[idx];
} else {
val = readl_relaxed(&qh->reg_pop[0].ptr_size_thresh);
if (unlikely(!val))
return 0;
}
dma = val & DESC_PTR_MASK;
if (size)
*size = ((val & DESC_SIZE_MASK) + 1) * 16;
this_cpu_inc(qh->stats->pops);
return dma;
}
EXPORT_SYMBOL_GPL(knav_queue_pop);
/* carve out descriptors and push into queue */
static void kdesc_fill_pool(struct knav_pool *pool)
{
struct knav_region *region;
int i;
region = pool->region;
pool->desc_size = region->desc_size;
for (i = 0; i < pool->num_desc; i++) {
int index = pool->region_offset + i;
dma_addr_t dma_addr;
unsigned dma_size;
dma_addr = region->dma_start + (region->desc_size * index);
dma_size = ALIGN(pool->desc_size, SMP_CACHE_BYTES);
dma_sync_single_for_device(pool->dev, dma_addr, dma_size,
DMA_TO_DEVICE);
knav_queue_push(pool->queue, dma_addr, dma_size, 0);
}
}
/* pop out descriptors and close the queue */
static void kdesc_empty_pool(struct knav_pool *pool)
{
dma_addr_t dma;
unsigned size;
void *desc;
int i;
if (!pool->queue)
return;
for (i = 0;; i++) {
dma = knav_queue_pop(pool->queue, &size);
if (!dma)
break;
desc = knav_pool_desc_dma_to_virt(pool, dma);
if (!desc) {
dev_dbg(pool->kdev->dev,
"couldn't unmap desc, continuing\n");
continue;
}
}
WARN_ON(i != pool->num_desc);
knav_queue_close(pool->queue);
}
/* Get the DMA address of a descriptor */
dma_addr_t knav_pool_desc_virt_to_dma(void *ph, void *virt)
{
struct knav_pool *pool = ph;
return pool->region->dma_start + (virt - pool->region->virt_start);
}
EXPORT_SYMBOL_GPL(knav_pool_desc_virt_to_dma);
void *knav_pool_desc_dma_to_virt(void *ph, dma_addr_t dma)
{
struct knav_pool *pool = ph;
return pool->region->virt_start + (dma - pool->region->dma_start);
}
EXPORT_SYMBOL_GPL(knav_pool_desc_dma_to_virt);
/**
* knav_pool_create() - Create a pool of descriptors
* @name: - name to give the pool handle
* @num_desc: - numbers of descriptors in the pool
* @region_id: - QMSS region id from which the descriptors are to be
* allocated.
*
* Returns a pool handle on success.
* Use IS_ERR_OR_NULL() to identify error values on return.
*/
void *knav_pool_create(const char *name,
int num_desc, int region_id)
{
struct knav_region *reg_itr, *region = NULL;
struct knav_pool *pool, *pi = NULL, *iter;
struct list_head *node;
unsigned last_offset;
int ret;
if (!kdev)
return ERR_PTR(-EPROBE_DEFER);
if (!kdev->dev)
return ERR_PTR(-ENODEV);
pool = devm_kzalloc(kdev->dev, sizeof(*pool), GFP_KERNEL);
if (!pool) {
dev_err(kdev->dev, "out of memory allocating pool\n");
return ERR_PTR(-ENOMEM);
}
for_each_region(kdev, reg_itr) {
if (reg_itr->id != region_id)
continue;
region = reg_itr;
break;
}
if (!region) {
dev_err(kdev->dev, "region-id(%d) not found\n", region_id);
ret = -EINVAL;
goto err;
}
pool->queue = knav_queue_open(name, KNAV_QUEUE_GP, 0);
if (IS_ERR(pool->queue)) {
dev_err(kdev->dev,
"failed to open queue for pool(%s), error %ld\n",
name, PTR_ERR(pool->queue));
ret = PTR_ERR(pool->queue);
goto err;
}
pool->name = kstrndup(name, KNAV_NAME_SIZE - 1, GFP_KERNEL);
pool->kdev = kdev;
pool->dev = kdev->dev;
mutex_lock(&knav_dev_lock);
if (num_desc > (region->num_desc - region->used_desc)) {
dev_err(kdev->dev, "out of descs in region(%d) for pool(%s)\n",
region_id, name);
ret = -ENOMEM;
goto err_unlock;
}
/* Region maintains a sorted (by region offset) list of pools
* use the first free slot which is large enough to accomodate
* the request
*/
last_offset = 0;
node = ®ion->pools;
list_for_each_entry(iter, ®ion->pools, region_inst) {
if ((iter->region_offset - last_offset) >= num_desc) {
pi = iter;
break;
}
last_offset = iter->region_offset + iter->num_desc;
}
if (pi) {
node = &pi->region_inst;
pool->region = region;
pool->num_desc = num_desc;
pool->region_offset = last_offset;
region->used_desc += num_desc;
list_add_tail(&pool->list, &kdev->pools);
list_add_tail(&pool->region_inst, node);
} else {
dev_err(kdev->dev, "pool(%s) create failed: fragmented desc pool in region(%d)\n",
name, region_id);
ret = -ENOMEM;
goto err_unlock;
}
mutex_unlock(&knav_dev_lock);
kdesc_fill_pool(pool);
return pool;
err_unlock:
mutex_unlock(&knav_dev_lock);
err:
kfree(pool->name);
devm_kfree(kdev->dev, pool);
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(knav_pool_create);
/**
* knav_pool_destroy() - Free a pool of descriptors
* @ph: - pool handle
*/
void knav_pool_destroy(void *ph)
{
struct knav_pool *pool = ph;
if (!pool)
return;
if (!pool->region)
return;
kdesc_empty_pool(pool);
mutex_lock(&knav_dev_lock);
pool->region->used_desc -= pool->num_desc;
list_del(&pool->region_inst);
list_del(&pool->list);
mutex_unlock(&knav_dev_lock);
kfree(pool->name);
devm_kfree(kdev->dev, pool);
}
EXPORT_SYMBOL_GPL(knav_pool_destroy);
/**
* knav_pool_desc_get() - Get a descriptor from the pool
* @ph: - pool handle
*
* Returns descriptor from the pool.
*/
void *knav_pool_desc_get(void *ph)
{
struct knav_pool *pool = ph;
dma_addr_t dma;
unsigned size;
void *data;
dma = knav_queue_pop(pool->queue, &size);
if (unlikely(!dma))
return ERR_PTR(-ENOMEM);
data = knav_pool_desc_dma_to_virt(pool, dma);
return data;
}
EXPORT_SYMBOL_GPL(knav_pool_desc_get);
/**
* knav_pool_desc_put() - return a descriptor to the pool
* @ph: - pool handle
* @desc: - virtual address
*/
void knav_pool_desc_put(void *ph, void *desc)
{
struct knav_pool *pool = ph;
dma_addr_t dma;
dma = knav_pool_desc_virt_to_dma(pool, desc);
knav_queue_push(pool->queue, dma, pool->region->desc_size, 0);
}
EXPORT_SYMBOL_GPL(knav_pool_desc_put);
/**
* knav_pool_desc_map() - Map descriptor for DMA transfer
* @ph: - pool handle
* @desc: - address of descriptor to map
* @size: - size of descriptor to map
* @dma: - DMA address return pointer
* @dma_sz: - adjusted return pointer
*
* Returns 0 on success, errno otherwise.
*/
int knav_pool_desc_map(void *ph, void *desc, unsigned size,
dma_addr_t *dma, unsigned *dma_sz)
{
struct knav_pool *pool = ph;
*dma = knav_pool_desc_virt_to_dma(pool, desc);
size = min(size, pool->region->desc_size);
size = ALIGN(size, SMP_CACHE_BYTES);
*dma_sz = size;
dma_sync_single_for_device(pool->dev, *dma, size, DMA_TO_DEVICE);
/* Ensure the descriptor reaches to the memory */
__iowmb();
return 0;
}
EXPORT_SYMBOL_GPL(knav_pool_desc_map);
/**
* knav_pool_desc_unmap() - Unmap descriptor after DMA transfer
* @ph: - pool handle
* @dma: - DMA address of descriptor to unmap
* @dma_sz: - size of descriptor to unmap
*
* Returns descriptor address on success, Use IS_ERR_OR_NULL() to identify
* error values on return.
*/
void *knav_pool_desc_unmap(void *ph, dma_addr_t dma, unsigned dma_sz)
{
struct knav_pool *pool = ph;
unsigned desc_sz;
void *desc;
desc_sz = min(dma_sz, pool->region->desc_size);
desc = knav_pool_desc_dma_to_virt(pool, dma);
dma_sync_single_for_cpu(pool->dev, dma, desc_sz, DMA_FROM_DEVICE);
prefetch(desc);
return desc;
}
EXPORT_SYMBOL_GPL(knav_pool_desc_unmap);
/**
* knav_pool_count() - Get the number of descriptors in pool.
* @ph: - pool handle
* Returns number of elements in the pool.
*/
int knav_pool_count(void *ph)
{
struct knav_pool *pool = ph;
return knav_queue_get_count(pool->queue);
}
EXPORT_SYMBOL_GPL(knav_pool_count);
static void knav_queue_setup_region(struct knav_device *kdev,
struct knav_region *region)
{
unsigned hw_num_desc, hw_desc_size, size;
struct knav_reg_region __iomem *regs;
struct knav_qmgr_info *qmgr;
struct knav_pool *pool;
int id = region->id;
struct page *page;
/* unused region? */
if (!region->num_desc) {
dev_warn(kdev->dev, "unused region %s\n", region->name);
return;
}
/* get hardware descriptor value */
hw_num_desc = ilog2(region->num_desc - 1) + 1;
/* did we force fit ourselves into nothingness? */
if (region->num_desc < 32) {
region->num_desc = 0;
dev_warn(kdev->dev, "too few descriptors in region %s\n",
region->name);
return;
}
size = region->num_desc * region->desc_size;
region->virt_start = alloc_pages_exact(size, GFP_KERNEL | GFP_DMA |
GFP_DMA32);
if (!region->virt_start) {
region->num_desc = 0;
dev_err(kdev->dev, "memory alloc failed for region %s\n",
region->name);
return;
}
region->virt_end = region->virt_start + size;
page = virt_to_page(region->virt_start);
region->dma_start = dma_map_page(kdev->dev, page, 0, size,
DMA_BIDIRECTIONAL);
if (dma_mapping_error(kdev->dev, region->dma_start)) {
dev_err(kdev->dev, "dma map failed for region %s\n",
region->name);
goto fail;
}
region->dma_end = region->dma_start + size;
pool = devm_kzalloc(kdev->dev, sizeof(*pool), GFP_KERNEL);
if (!pool) {
dev_err(kdev->dev, "out of memory allocating dummy pool\n");
goto fail;
}
pool->num_desc = 0;
pool->region_offset = region->num_desc;
list_add(&pool->region_inst, ®ion->pools);
dev_dbg(kdev->dev,
"region %s (%d): size:%d, link:%d@%d, dma:%pad-%pad, virt:%p-%p\n",
region->name, id, region->desc_size, region->num_desc,
region->link_index, ®ion->dma_start, ®ion->dma_end,
region->virt_start, region->virt_end);
hw_desc_size = (region->desc_size / 16) - 1;
hw_num_desc -= 5;
for_each_qmgr(kdev, qmgr) {
regs = qmgr->reg_region + id;
writel_relaxed((u32)region->dma_start, ®s->base);
writel_relaxed(region->link_index, ®s->start_index);
writel_relaxed(hw_desc_size << 16 | hw_num_desc,
®s->size_count);
}
return;
fail:
if (region->dma_start)
dma_unmap_page(kdev->dev, region->dma_start, size,
DMA_BIDIRECTIONAL);
if (region->virt_start)
free_pages_exact(region->virt_start, size);
region->num_desc = 0;
return;
}
static const char *knav_queue_find_name(struct device_node *node)
{
const char *name;
if (of_property_read_string(node, "label", &name) < 0)
name = node->name;
if (!name)
name = "unknown";
return name;
}
static int knav_queue_setup_regions(struct knav_device *kdev,
struct device_node *regions)
{
struct device *dev = kdev->dev;
struct knav_region *region;
struct device_node *child;
u32 temp[2];
int ret;
for_each_child_of_node(regions, child) {
region = devm_kzalloc(dev, sizeof(*region), GFP_KERNEL);
if (!region) {
of_node_put(child);
dev_err(dev, "out of memory allocating region\n");
return -ENOMEM;
}
region->name = knav_queue_find_name(child);
of_property_read_u32(child, "id", ®ion->id);
ret = of_property_read_u32_array(child, "region-spec", temp, 2);
if (!ret) {
region->num_desc = temp[0];
region->desc_size = temp[1];
} else {
dev_err(dev, "invalid region info %s\n", region->name);
devm_kfree(dev, region);
continue;
}
if (!of_get_property(child, "link-index", NULL)) {
dev_err(dev, "No link info for %s\n", region->name);
devm_kfree(dev, region);
continue;
}
ret = of_property_read_u32(child, "link-index",
®ion->link_index);
if (ret) {
dev_err(dev, "link index not found for %s\n",
region->name);
devm_kfree(dev, region);
continue;
}
INIT_LIST_HEAD(®ion->pools);
list_add_tail(®ion->list, &kdev->regions);
}
if (list_empty(&kdev->regions)) {
dev_err(dev, "no valid region information found\n");
return -ENODEV;
}
/* Next, we run through the regions and set things up */
for_each_region(kdev, region)
knav_queue_setup_region(kdev, region);
return 0;
}
static int knav_get_link_ram(struct knav_device *kdev,
const char *name,
struct knav_link_ram_block *block)
{
struct platform_device *pdev = to_platform_device(kdev->dev);
struct device_node *node = pdev->dev.of_node;
u32 temp[2];
/*
* Note: link ram resources are specified in "entry" sized units. In
* reality, although entries are ~40bits in hardware, we treat them as
* 64-bit entities here.
*
* For example, to specify the internal link ram for Keystone-I class
* devices, we would set the linkram0 resource to 0x80000-0x83fff.
*
* This gets a bit weird when other link rams are used. For example,
* if the range specified is 0x0c000000-0x0c003fff (i.e., 16K entries
* in MSMC SRAM), the actual memory used is 0x0c000000-0x0c020000,
* which accounts for 64-bits per entry, for 16K entries.
*/
if (!of_property_read_u32_array(node, name , temp, 2)) {
if (temp[0]) {
/*
* queue_base specified => using internal or onchip
* link ram WARNING - we do not "reserve" this block
*/
block->dma = (dma_addr_t)temp[0];
block->virt = NULL;
block->size = temp[1];
} else {
block->size = temp[1];
/* queue_base not specific => allocate requested size */
block->virt = dmam_alloc_coherent(kdev->dev,
8 * block->size, &block->dma,
GFP_KERNEL);
if (!block->virt) {
dev_err(kdev->dev, "failed to alloc linkram\n");
return -ENOMEM;
}
}
} else {
return -ENODEV;
}
return 0;
}
static int knav_queue_setup_link_ram(struct knav_device *kdev)
{
struct knav_link_ram_block *block;
struct knav_qmgr_info *qmgr;
for_each_qmgr(kdev, qmgr) {
block = &kdev->link_rams[0];
dev_dbg(kdev->dev, "linkram0: dma:%pad, virt:%p, size:%x\n",
&block->dma, block->virt, block->size);
writel_relaxed((u32)block->dma, &qmgr->reg_config->link_ram_base0);
if (kdev->version == QMSS_66AK2G)
writel_relaxed(block->size,
&qmgr->reg_config->link_ram_size0);
else
writel_relaxed(block->size - 1,
&qmgr->reg_config->link_ram_size0);
block++;
if (!block->size)
continue;
dev_dbg(kdev->dev, "linkram1: dma:%pad, virt:%p, size:%x\n",
&block->dma, block->virt, block->size);
writel_relaxed(block->dma, &qmgr->reg_config->link_ram_base1);
}
return 0;
}
static int knav_setup_queue_range(struct knav_device *kdev,
struct device_node *node)
{
struct device *dev = kdev->dev;
struct knav_range_info *range;
struct knav_qmgr_info *qmgr;
u32 temp[2], start, end, id, index;
int ret, i;
range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL);
if (!range) {
dev_err(dev, "out of memory allocating range\n");
return -ENOMEM;
}
range->kdev = kdev;
range->name = knav_queue_find_name(node);
ret = of_property_read_u32_array(node, "qrange", temp, 2);
if (!ret) {
range->queue_base = temp[0] - kdev->base_id;
range->num_queues = temp[1];
} else {
dev_err(dev, "invalid queue range %s\n", range->name);
devm_kfree(dev, range);
return -EINVAL;
}
for (i = 0; i < RANGE_MAX_IRQS; i++) {
struct of_phandle_args oirq;
if (of_irq_parse_one(node, i, &oirq))
break;
range->irqs[i].irq = irq_create_of_mapping(&oirq);
if (range->irqs[i].irq == IRQ_NONE)
break;
range->num_irqs++;
if (IS_ENABLED(CONFIG_SMP) && oirq.args_count == 3) {
unsigned long mask;
int bit;
range->irqs[i].cpu_mask = devm_kzalloc(dev,
cpumask_size(), GFP_KERNEL);
if (!range->irqs[i].cpu_mask)
return -ENOMEM;
mask = (oirq.args[2] & 0x0000ff00) >> 8;
for_each_set_bit(bit, &mask, BITS_PER_LONG)
cpumask_set_cpu(bit, range->irqs[i].cpu_mask);
}
}
range->num_irqs = min(range->num_irqs, range->num_queues);
if (range->num_irqs)
range->flags |= RANGE_HAS_IRQ;
if (of_property_read_bool(node, "qalloc-by-id"))
range->flags |= RANGE_RESERVED;
if (of_property_present(node, "accumulator")) {
ret = knav_init_acc_range(kdev, node, range);
if (ret < 0) {
devm_kfree(dev, range);
return ret;
}
} else {
range->ops = &knav_gp_range_ops;
}
/* set threshold to 1, and flush out the queues */
for_each_qmgr(kdev, qmgr) {
start = max(qmgr->start_queue, range->queue_base);
end = min(qmgr->start_queue + qmgr->num_queues,
range->queue_base + range->num_queues);
for (id = start; id < end; id++) {
index = id - qmgr->start_queue;
writel_relaxed(THRESH_GTE | 1,
&qmgr->reg_peek[index].ptr_size_thresh);
writel_relaxed(0,
&qmgr->reg_push[index].ptr_size_thresh);
}
}
list_add_tail(&range->list, &kdev->queue_ranges);
dev_dbg(dev, "added range %s: %d-%d, %d irqs%s%s%s\n",
range->name, range->queue_base,
range->queue_base + range->num_queues - 1,
range->num_irqs,
(range->flags & RANGE_HAS_IRQ) ? ", has irq" : "",
(range->flags & RANGE_RESERVED) ? ", reserved" : "",
(range->flags & RANGE_HAS_ACCUMULATOR) ? ", acc" : "");
kdev->num_queues_in_use += range->num_queues;
return 0;
}
static int knav_setup_queue_pools(struct knav_device *kdev,
struct device_node *queue_pools)
{
struct device_node *type, *range;
for_each_child_of_node(queue_pools, type) {
for_each_child_of_node(type, range) {
/* return value ignored, we init the rest... */
knav_setup_queue_range(kdev, range);
}
}
/* ... and barf if they all failed! */
if (list_empty(&kdev->queue_ranges)) {
dev_err(kdev->dev, "no valid queue range found\n");
return -ENODEV;
}
return 0;
}
static void knav_free_queue_range(struct knav_device *kdev,
struct knav_range_info *range)
{
if (range->ops && range->ops->free_range)
range->ops->free_range(range);
list_del(&range->list);
devm_kfree(kdev->dev, range);
}
static void knav_free_queue_ranges(struct knav_device *kdev)
{
struct knav_range_info *range;
for (;;) {
range = first_queue_range(kdev);
if (!range)
break;
knav_free_queue_range(kdev, range);
}
}
static void knav_queue_free_regions(struct knav_device *kdev)
{
struct knav_region *region;
struct knav_pool *pool, *tmp;
unsigned size;
for (;;) {
region = first_region(kdev);
if (!region)
break;
list_for_each_entry_safe(pool, tmp, ®ion->pools, region_inst)
knav_pool_destroy(pool);
size = region->virt_end - region->virt_start;
if (size)
free_pages_exact(region->virt_start, size);
list_del(®ion->list);
devm_kfree(kdev->dev, region);
}
}
static void __iomem *knav_queue_map_reg(struct knav_device *kdev,
struct device_node *node, int index)
{
struct resource res;
void __iomem *regs;
int ret;
ret = of_address_to_resource(node, index, &res);
if (ret) {
dev_err(kdev->dev, "Can't translate of node(%pOFn) address for index(%d)\n",
node, index);
return ERR_PTR(ret);
}
regs = devm_ioremap_resource(kdev->dev, &res);
if (IS_ERR(regs))
dev_err(kdev->dev, "Failed to map register base for index(%d) node(%pOFn)\n",
index, node);
return regs;
}
static int knav_queue_init_qmgrs(struct knav_device *kdev,
struct device_node *qmgrs)
{
struct device *dev = kdev->dev;
struct knav_qmgr_info *qmgr;
struct device_node *child;
u32 temp[2];
int ret;
for_each_child_of_node(qmgrs, child) {
qmgr = devm_kzalloc(dev, sizeof(*qmgr), GFP_KERNEL);
if (!qmgr) {
of_node_put(child);
dev_err(dev, "out of memory allocating qmgr\n");
return -ENOMEM;
}
ret = of_property_read_u32_array(child, "managed-queues",
temp, 2);
if (!ret) {
qmgr->start_queue = temp[0];
qmgr->num_queues = temp[1];
} else {
dev_err(dev, "invalid qmgr queue range\n");
devm_kfree(dev, qmgr);
continue;
}
dev_info(dev, "qmgr start queue %d, number of queues %d\n",
qmgr->start_queue, qmgr->num_queues);
qmgr->reg_peek =
knav_queue_map_reg(kdev, child,
KNAV_QUEUE_PEEK_REG_INDEX);
if (kdev->version == QMSS) {
qmgr->reg_status =
knav_queue_map_reg(kdev, child,
KNAV_QUEUE_STATUS_REG_INDEX);
}
qmgr->reg_config =
knav_queue_map_reg(kdev, child,
(kdev->version == QMSS_66AK2G) ?
KNAV_L_QUEUE_CONFIG_REG_INDEX :
KNAV_QUEUE_CONFIG_REG_INDEX);
qmgr->reg_region =
knav_queue_map_reg(kdev, child,
(kdev->version == QMSS_66AK2G) ?
KNAV_L_QUEUE_REGION_REG_INDEX :
KNAV_QUEUE_REGION_REG_INDEX);
qmgr->reg_push =
knav_queue_map_reg(kdev, child,
(kdev->version == QMSS_66AK2G) ?
KNAV_L_QUEUE_PUSH_REG_INDEX :
KNAV_QUEUE_PUSH_REG_INDEX);
if (kdev->version == QMSS) {
qmgr->reg_pop =
knav_queue_map_reg(kdev, child,
KNAV_QUEUE_POP_REG_INDEX);
}
if (IS_ERR(qmgr->reg_peek) ||
((kdev->version == QMSS) &&
(IS_ERR(qmgr->reg_status) || IS_ERR(qmgr->reg_pop))) ||
IS_ERR(qmgr->reg_config) || IS_ERR(qmgr->reg_region) ||
IS_ERR(qmgr->reg_push)) {
dev_err(dev, "failed to map qmgr regs\n");
if (kdev->version == QMSS) {
if (!IS_ERR(qmgr->reg_status))
devm_iounmap(dev, qmgr->reg_status);
if (!IS_ERR(qmgr->reg_pop))
devm_iounmap(dev, qmgr->reg_pop);
}
if (!IS_ERR(qmgr->reg_peek))
devm_iounmap(dev, qmgr->reg_peek);
if (!IS_ERR(qmgr->reg_config))
devm_iounmap(dev, qmgr->reg_config);
if (!IS_ERR(qmgr->reg_region))
devm_iounmap(dev, qmgr->reg_region);
if (!IS_ERR(qmgr->reg_push))
devm_iounmap(dev, qmgr->reg_push);
devm_kfree(dev, qmgr);
continue;
}
/* Use same push register for pop as well */
if (kdev->version == QMSS_66AK2G)
qmgr->reg_pop = qmgr->reg_push;
list_add_tail(&qmgr->list, &kdev->qmgrs);
dev_info(dev, "added qmgr start queue %d, num of queues %d, reg_peek %p, reg_status %p, reg_config %p, reg_region %p, reg_push %p, reg_pop %p\n",
qmgr->start_queue, qmgr->num_queues,
qmgr->reg_peek, qmgr->reg_status,
qmgr->reg_config, qmgr->reg_region,
qmgr->reg_push, qmgr->reg_pop);
}
return 0;
}
static int knav_queue_init_pdsps(struct knav_device *kdev,
struct device_node *pdsps)
{
struct device *dev = kdev->dev;
struct knav_pdsp_info *pdsp;
struct device_node *child;
for_each_child_of_node(pdsps, child) {
pdsp = devm_kzalloc(dev, sizeof(*pdsp), GFP_KERNEL);
if (!pdsp) {
of_node_put(child);
dev_err(dev, "out of memory allocating pdsp\n");
return -ENOMEM;
}
pdsp->name = knav_queue_find_name(child);
pdsp->iram =
knav_queue_map_reg(kdev, child,
KNAV_QUEUE_PDSP_IRAM_REG_INDEX);
pdsp->regs =
knav_queue_map_reg(kdev, child,
KNAV_QUEUE_PDSP_REGS_REG_INDEX);
pdsp->intd =
knav_queue_map_reg(kdev, child,
KNAV_QUEUE_PDSP_INTD_REG_INDEX);
pdsp->command =
knav_queue_map_reg(kdev, child,
KNAV_QUEUE_PDSP_CMD_REG_INDEX);
if (IS_ERR(pdsp->command) || IS_ERR(pdsp->iram) ||
IS_ERR(pdsp->regs) || IS_ERR(pdsp->intd)) {
dev_err(dev, "failed to map pdsp %s regs\n",
pdsp->name);
if (!IS_ERR(pdsp->command))
devm_iounmap(dev, pdsp->command);
if (!IS_ERR(pdsp->iram))
devm_iounmap(dev, pdsp->iram);
if (!IS_ERR(pdsp->regs))
devm_iounmap(dev, pdsp->regs);
if (!IS_ERR(pdsp->intd))
devm_iounmap(dev, pdsp->intd);
devm_kfree(dev, pdsp);
continue;
}
of_property_read_u32(child, "id", &pdsp->id);
list_add_tail(&pdsp->list, &kdev->pdsps);
dev_dbg(dev, "added pdsp %s: command %p, iram %p, regs %p, intd %p\n",
pdsp->name, pdsp->command, pdsp->iram, pdsp->regs,
pdsp->intd);
}
return 0;
}
static int knav_queue_stop_pdsp(struct knav_device *kdev,
struct knav_pdsp_info *pdsp)
{
u32 val, timeout = 1000;
int ret;
val = readl_relaxed(&pdsp->regs->control) & ~PDSP_CTRL_ENABLE;
writel_relaxed(val, &pdsp->regs->control);
ret = knav_queue_pdsp_wait(&pdsp->regs->control, timeout,
PDSP_CTRL_RUNNING);
if (ret < 0) {
dev_err(kdev->dev, "timed out on pdsp %s stop\n", pdsp->name);
return ret;
}
pdsp->loaded = false;
pdsp->started = false;
return 0;
}
static int knav_queue_load_pdsp(struct knav_device *kdev,
struct knav_pdsp_info *pdsp)
{
int i, ret, fwlen;
const struct firmware *fw;
bool found = false;
u32 *fwdata;
for (i = 0; i < ARRAY_SIZE(knav_acc_firmwares); i++) {
if (knav_acc_firmwares[i]) {
ret = request_firmware_direct(&fw,
knav_acc_firmwares[i],
kdev->dev);
if (!ret) {
found = true;
break;
}
}
}
if (!found) {
dev_err(kdev->dev, "failed to get firmware for pdsp\n");
return -ENODEV;
}
dev_info(kdev->dev, "firmware file %s downloaded for PDSP\n",
knav_acc_firmwares[i]);
writel_relaxed(pdsp->id + 1, pdsp->command + 0x18);
/* download the firmware */
fwdata = (u32 *)fw->data;
fwlen = (fw->size + sizeof(u32) - 1) / sizeof(u32);
for (i = 0; i < fwlen; i++)
writel_relaxed(be32_to_cpu(fwdata[i]), pdsp->iram + i);
release_firmware(fw);
return 0;
}
static int knav_queue_start_pdsp(struct knav_device *kdev,
struct knav_pdsp_info *pdsp)
{
u32 val, timeout = 1000;
int ret;
/* write a command for sync */
writel_relaxed(0xffffffff, pdsp->command);
while (readl_relaxed(pdsp->command) != 0xffffffff)
cpu_relax();
/* soft reset the PDSP */
val = readl_relaxed(&pdsp->regs->control);
val &= ~(PDSP_CTRL_PC_MASK | PDSP_CTRL_SOFT_RESET);
writel_relaxed(val, &pdsp->regs->control);
/* enable pdsp */
val = readl_relaxed(&pdsp->regs->control) | PDSP_CTRL_ENABLE;
writel_relaxed(val, &pdsp->regs->control);
/* wait for command register to clear */
ret = knav_queue_pdsp_wait(pdsp->command, timeout, 0);
if (ret < 0) {
dev_err(kdev->dev,
"timed out on pdsp %s command register wait\n",
pdsp->name);
return ret;
}
return 0;
}
static void knav_queue_stop_pdsps(struct knav_device *kdev)
{
struct knav_pdsp_info *pdsp;
/* disable all pdsps */
for_each_pdsp(kdev, pdsp)
knav_queue_stop_pdsp(kdev, pdsp);
}
static int knav_queue_start_pdsps(struct knav_device *kdev)
{
struct knav_pdsp_info *pdsp;
int ret;
knav_queue_stop_pdsps(kdev);
/* now load them all. We return success even if pdsp
* is not loaded as acc channels are optional on having
* firmware availability in the system. We set the loaded
* and stated flag and when initialize the acc range, check
* it and init the range only if pdsp is started.
*/
for_each_pdsp(kdev, pdsp) {
ret = knav_queue_load_pdsp(kdev, pdsp);
if (!ret)
pdsp->loaded = true;
}
for_each_pdsp(kdev, pdsp) {
if (pdsp->loaded) {
ret = knav_queue_start_pdsp(kdev, pdsp);
if (!ret)
pdsp->started = true;
}
}
return 0;
}
static inline struct knav_qmgr_info *knav_find_qmgr(unsigned id)
{
struct knav_qmgr_info *qmgr;
for_each_qmgr(kdev, qmgr) {
if ((id >= qmgr->start_queue) &&
(id < qmgr->start_queue + qmgr->num_queues))
return qmgr;
}
return NULL;
}
static int knav_queue_init_queue(struct knav_device *kdev,
struct knav_range_info *range,
struct knav_queue_inst *inst,
unsigned id)
{
char irq_name[KNAV_NAME_SIZE];
inst->qmgr = knav_find_qmgr(id);
if (!inst->qmgr)
return -1;
INIT_LIST_HEAD(&inst->handles);
inst->kdev = kdev;
inst->range = range;
inst->irq_num = -1;
inst->id = id;
scnprintf(irq_name, sizeof(irq_name), "hwqueue-%d", id);
inst->irq_name = kstrndup(irq_name, sizeof(irq_name), GFP_KERNEL);
if (range->ops && range->ops->init_queue)
return range->ops->init_queue(range, inst);
else
return 0;
}
static int knav_queue_init_queues(struct knav_device *kdev)
{
struct knav_range_info *range;
int size, id, base_idx;
int idx = 0, ret = 0;
/* how much do we need for instance data? */
size = sizeof(struct knav_queue_inst);
/* round this up to a power of 2, keep the index to instance
* arithmetic fast.
* */
kdev->inst_shift = order_base_2(size);
size = (1 << kdev->inst_shift) * kdev->num_queues_in_use;
kdev->instances = devm_kzalloc(kdev->dev, size, GFP_KERNEL);
if (!kdev->instances)
return -ENOMEM;
for_each_queue_range(kdev, range) {
if (range->ops && range->ops->init_range)
range->ops->init_range(range);
base_idx = idx;
for (id = range->queue_base;
id < range->queue_base + range->num_queues; id++, idx++) {
ret = knav_queue_init_queue(kdev, range,
knav_queue_idx_to_inst(kdev, idx), id);
if (ret < 0)
return ret;
}
range->queue_base_inst =
knav_queue_idx_to_inst(kdev, base_idx);
}
return 0;
}
/* Match table for of_platform binding */
static const struct of_device_id keystone_qmss_of_match[] = {
{
.compatible = "ti,keystone-navigator-qmss",
},
{
.compatible = "ti,66ak2g-navss-qm",
.data = (void *)QMSS_66AK2G,
},
{},
};
MODULE_DEVICE_TABLE(of, keystone_qmss_of_match);
static int knav_queue_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct device_node *qmgrs, *queue_pools, *regions, *pdsps;
const struct of_device_id *match;
struct device *dev = &pdev->dev;
u32 temp[2];
int ret;
if (!node) {
dev_err(dev, "device tree info unavailable\n");
return -ENODEV;
}
kdev = devm_kzalloc(dev, sizeof(struct knav_device), GFP_KERNEL);
if (!kdev) {
dev_err(dev, "memory allocation failed\n");
return -ENOMEM;
}
match = of_match_device(of_match_ptr(keystone_qmss_of_match), dev);
if (match && match->data)
kdev->version = QMSS_66AK2G;
platform_set_drvdata(pdev, kdev);
kdev->dev = dev;
INIT_LIST_HEAD(&kdev->queue_ranges);
INIT_LIST_HEAD(&kdev->qmgrs);
INIT_LIST_HEAD(&kdev->pools);
INIT_LIST_HEAD(&kdev->regions);
INIT_LIST_HEAD(&kdev->pdsps);
pm_runtime_enable(&pdev->dev);
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0) {
pm_runtime_disable(&pdev->dev);
dev_err(dev, "Failed to enable QMSS\n");
return ret;
}
if (of_property_read_u32_array(node, "queue-range", temp, 2)) {
dev_err(dev, "queue-range not specified\n");
ret = -ENODEV;
goto err;
}
kdev->base_id = temp[0];
kdev->num_queues = temp[1];
/* Initialize queue managers using device tree configuration */
qmgrs = of_get_child_by_name(node, "qmgrs");
if (!qmgrs) {
dev_err(dev, "queue manager info not specified\n");
ret = -ENODEV;
goto err;
}
ret = knav_queue_init_qmgrs(kdev, qmgrs);
of_node_put(qmgrs);
if (ret)
goto err;
/* get pdsp configuration values from device tree */
pdsps = of_get_child_by_name(node, "pdsps");
if (pdsps) {
ret = knav_queue_init_pdsps(kdev, pdsps);
if (ret)
goto err;
ret = knav_queue_start_pdsps(kdev);
if (ret)
goto err;
}
of_node_put(pdsps);
/* get usable queue range values from device tree */
queue_pools = of_get_child_by_name(node, "queue-pools");
if (!queue_pools) {
dev_err(dev, "queue-pools not specified\n");
ret = -ENODEV;
goto err;
}
ret = knav_setup_queue_pools(kdev, queue_pools);
of_node_put(queue_pools);
if (ret)
goto err;
ret = knav_get_link_ram(kdev, "linkram0", &kdev->link_rams[0]);
if (ret) {
dev_err(kdev->dev, "could not setup linking ram\n");
goto err;
}
ret = knav_get_link_ram(kdev, "linkram1", &kdev->link_rams[1]);
if (ret) {
/*
* nothing really, we have one linking ram already, so we just
* live within our means
*/
}
ret = knav_queue_setup_link_ram(kdev);
if (ret)
goto err;
regions = of_get_child_by_name(node, "descriptor-regions");
if (!regions) {
dev_err(dev, "descriptor-regions not specified\n");
ret = -ENODEV;
goto err;
}
ret = knav_queue_setup_regions(kdev, regions);
of_node_put(regions);
if (ret)
goto err;
ret = knav_queue_init_queues(kdev);
if (ret < 0) {
dev_err(dev, "hwqueue initialization failed\n");
goto err;
}
debugfs_create_file("qmss", S_IFREG | S_IRUGO, NULL, NULL,
&knav_queue_debug_fops);
device_ready = true;
return 0;
err:
knav_queue_stop_pdsps(kdev);
knav_queue_free_regions(kdev);
knav_free_queue_ranges(kdev);
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return ret;
}
static int knav_queue_remove(struct platform_device *pdev)
{
/* TODO: Free resources */
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return 0;
}
static struct platform_driver keystone_qmss_driver = {
.probe = knav_queue_probe,
.remove = knav_queue_remove,
.driver = {
.name = "keystone-navigator-qmss",
.of_match_table = keystone_qmss_of_match,
},
};
module_platform_driver(keystone_qmss_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("TI QMSS driver for Keystone SOCs");
MODULE_AUTHOR("Sandeep Nair <[email protected]>");
MODULE_AUTHOR("Santosh Shilimkar <[email protected]>");
|
linux-master
|
drivers/soc/ti/knav_qmss_queue.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* TI K3 NAVSS Ring Accelerator subsystem driver
*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
*/
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/sys_soc.h>
#include <linux/dma/ti-cppi5.h>
#include <linux/soc/ti/k3-ringacc.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <linux/soc/ti/ti_sci_inta_msi.h>
#include <linux/of_irq.h>
#include <linux/irqdomain.h>
static LIST_HEAD(k3_ringacc_list);
static DEFINE_MUTEX(k3_ringacc_list_lock);
#define K3_RINGACC_CFG_RING_SIZE_ELCNT_MASK GENMASK(19, 0)
#define K3_DMARING_CFG_RING_SIZE_ELCNT_MASK GENMASK(15, 0)
/**
* struct k3_ring_rt_regs - The RA realtime Control/Status Registers region
*
* @resv_16: Reserved
* @db: Ring Doorbell Register
* @resv_4: Reserved
* @occ: Ring Occupancy Register
* @indx: Ring Current Index Register
* @hwocc: Ring Hardware Occupancy Register
* @hwindx: Ring Hardware Current Index Register
*/
struct k3_ring_rt_regs {
u32 resv_16[4];
u32 db;
u32 resv_4[1];
u32 occ;
u32 indx;
u32 hwocc;
u32 hwindx;
};
#define K3_RINGACC_RT_REGS_STEP 0x1000
#define K3_DMARING_RT_REGS_STEP 0x2000
#define K3_DMARING_RT_REGS_REVERSE_OFS 0x1000
#define K3_RINGACC_RT_OCC_MASK GENMASK(20, 0)
#define K3_DMARING_RT_OCC_TDOWN_COMPLETE BIT(31)
#define K3_DMARING_RT_DB_ENTRY_MASK GENMASK(7, 0)
#define K3_DMARING_RT_DB_TDOWN_ACK BIT(31)
/**
* struct k3_ring_fifo_regs - The Ring Accelerator Queues Registers region
*
* @head_data: Ring Head Entry Data Registers
* @tail_data: Ring Tail Entry Data Registers
* @peek_head_data: Ring Peek Head Entry Data Regs
* @peek_tail_data: Ring Peek Tail Entry Data Regs
*/
struct k3_ring_fifo_regs {
u32 head_data[128];
u32 tail_data[128];
u32 peek_head_data[128];
u32 peek_tail_data[128];
};
/**
* struct k3_ringacc_proxy_gcfg_regs - RA Proxy Global Config MMIO Region
*
* @revision: Revision Register
* @config: Config Register
*/
struct k3_ringacc_proxy_gcfg_regs {
u32 revision;
u32 config;
};
#define K3_RINGACC_PROXY_CFG_THREADS_MASK GENMASK(15, 0)
/**
* struct k3_ringacc_proxy_target_regs - Proxy Datapath MMIO Region
*
* @control: Proxy Control Register
* @status: Proxy Status Register
* @resv_512: Reserved
* @data: Proxy Data Register
*/
struct k3_ringacc_proxy_target_regs {
u32 control;
u32 status;
u8 resv_512[504];
u32 data[128];
};
#define K3_RINGACC_PROXY_TARGET_STEP 0x1000
#define K3_RINGACC_PROXY_NOT_USED (-1)
enum k3_ringacc_proxy_access_mode {
PROXY_ACCESS_MODE_HEAD = 0,
PROXY_ACCESS_MODE_TAIL = 1,
PROXY_ACCESS_MODE_PEEK_HEAD = 2,
PROXY_ACCESS_MODE_PEEK_TAIL = 3,
};
#define K3_RINGACC_FIFO_WINDOW_SIZE_BYTES (512U)
#define K3_RINGACC_FIFO_REGS_STEP 0x1000
#define K3_RINGACC_MAX_DB_RING_CNT (127U)
struct k3_ring_ops {
int (*push_tail)(struct k3_ring *ring, void *elm);
int (*push_head)(struct k3_ring *ring, void *elm);
int (*pop_tail)(struct k3_ring *ring, void *elm);
int (*pop_head)(struct k3_ring *ring, void *elm);
};
/**
* struct k3_ring_state - Internal state tracking structure
*
* @free: Number of free entries
* @occ: Occupancy
* @windex: Write index
* @rindex: Read index
* @tdown_complete: Tear down complete state
*/
struct k3_ring_state {
u32 free;
u32 occ;
u32 windex;
u32 rindex;
u32 tdown_complete:1;
};
/**
* struct k3_ring - RA Ring descriptor
*
* @rt: Ring control/status registers
* @fifos: Ring queues registers
* @proxy: Ring Proxy Datapath registers
* @ring_mem_dma: Ring buffer dma address
* @ring_mem_virt: Ring buffer virt address
* @ops: Ring operations
* @size: Ring size in elements
* @elm_size: Size of the ring element
* @mode: Ring mode
* @flags: flags
* @state: Ring state
* @ring_id: Ring Id
* @parent: Pointer on struct @k3_ringacc
* @use_count: Use count for shared rings
* @proxy_id: RA Ring Proxy Id (only if @K3_RINGACC_RING_USE_PROXY)
* @dma_dev: device to be used for DMA API (allocation, mapping)
* @asel: Address Space Select value for physical addresses
*/
struct k3_ring {
struct k3_ring_rt_regs __iomem *rt;
struct k3_ring_fifo_regs __iomem *fifos;
struct k3_ringacc_proxy_target_regs __iomem *proxy;
dma_addr_t ring_mem_dma;
void *ring_mem_virt;
struct k3_ring_ops *ops;
u32 size;
enum k3_ring_size elm_size;
enum k3_ring_mode mode;
u32 flags;
#define K3_RING_FLAG_BUSY BIT(1)
#define K3_RING_FLAG_SHARED BIT(2)
#define K3_RING_FLAG_REVERSE BIT(3)
struct k3_ring_state state;
u32 ring_id;
struct k3_ringacc *parent;
u32 use_count;
int proxy_id;
struct device *dma_dev;
u32 asel;
#define K3_ADDRESS_ASEL_SHIFT 48
};
struct k3_ringacc_ops {
int (*init)(struct platform_device *pdev, struct k3_ringacc *ringacc);
};
/**
* struct k3_ringacc - Rings accelerator descriptor
*
* @dev: pointer on RA device
* @proxy_gcfg: RA proxy global config registers
* @proxy_target_base: RA proxy datapath region
* @num_rings: number of ring in RA
* @rings_inuse: bitfield for ring usage tracking
* @rm_gp_range: general purpose rings range from tisci
* @dma_ring_reset_quirk: DMA reset workaround enable
* @num_proxies: number of RA proxies
* @proxy_inuse: bitfield for proxy usage tracking
* @rings: array of rings descriptors (struct @k3_ring)
* @list: list of RAs in the system
* @req_lock: protect rings allocation
* @tisci: pointer ti-sci handle
* @tisci_ring_ops: ti-sci rings ops
* @tisci_dev_id: ti-sci device id
* @ops: SoC specific ringacc operation
* @dma_rings: indicate DMA ring (dual ring within BCDMA/PKTDMA)
*/
struct k3_ringacc {
struct device *dev;
struct k3_ringacc_proxy_gcfg_regs __iomem *proxy_gcfg;
void __iomem *proxy_target_base;
u32 num_rings; /* number of rings in Ringacc module */
unsigned long *rings_inuse;
struct ti_sci_resource *rm_gp_range;
bool dma_ring_reset_quirk;
u32 num_proxies;
unsigned long *proxy_inuse;
struct k3_ring *rings;
struct list_head list;
struct mutex req_lock; /* protect rings allocation */
const struct ti_sci_handle *tisci;
const struct ti_sci_rm_ringacc_ops *tisci_ring_ops;
u32 tisci_dev_id;
const struct k3_ringacc_ops *ops;
bool dma_rings;
};
/**
* struct k3_ringacc_soc_data - Rings accelerator SoC data
*
* @dma_ring_reset_quirk: DMA reset workaround enable
*/
struct k3_ringacc_soc_data {
unsigned dma_ring_reset_quirk:1;
};
static int k3_ringacc_ring_read_occ(struct k3_ring *ring)
{
return readl(&ring->rt->occ) & K3_RINGACC_RT_OCC_MASK;
}
static void k3_ringacc_ring_update_occ(struct k3_ring *ring)
{
u32 val;
val = readl(&ring->rt->occ);
ring->state.occ = val & K3_RINGACC_RT_OCC_MASK;
ring->state.tdown_complete = !!(val & K3_DMARING_RT_OCC_TDOWN_COMPLETE);
}
static long k3_ringacc_ring_get_fifo_pos(struct k3_ring *ring)
{
return K3_RINGACC_FIFO_WINDOW_SIZE_BYTES -
(4 << ring->elm_size);
}
static void *k3_ringacc_get_elm_addr(struct k3_ring *ring, u32 idx)
{
return (ring->ring_mem_virt + idx * (4 << ring->elm_size));
}
static int k3_ringacc_ring_push_mem(struct k3_ring *ring, void *elem);
static int k3_ringacc_ring_pop_mem(struct k3_ring *ring, void *elem);
static int k3_dmaring_fwd_pop(struct k3_ring *ring, void *elem);
static int k3_dmaring_reverse_pop(struct k3_ring *ring, void *elem);
static struct k3_ring_ops k3_ring_mode_ring_ops = {
.push_tail = k3_ringacc_ring_push_mem,
.pop_head = k3_ringacc_ring_pop_mem,
};
static struct k3_ring_ops k3_dmaring_fwd_ops = {
.push_tail = k3_ringacc_ring_push_mem,
.pop_head = k3_dmaring_fwd_pop,
};
static struct k3_ring_ops k3_dmaring_reverse_ops = {
/* Reverse side of the DMA ring can only be popped by SW */
.pop_head = k3_dmaring_reverse_pop,
};
static int k3_ringacc_ring_push_io(struct k3_ring *ring, void *elem);
static int k3_ringacc_ring_pop_io(struct k3_ring *ring, void *elem);
static int k3_ringacc_ring_push_head_io(struct k3_ring *ring, void *elem);
static int k3_ringacc_ring_pop_tail_io(struct k3_ring *ring, void *elem);
static struct k3_ring_ops k3_ring_mode_msg_ops = {
.push_tail = k3_ringacc_ring_push_io,
.push_head = k3_ringacc_ring_push_head_io,
.pop_tail = k3_ringacc_ring_pop_tail_io,
.pop_head = k3_ringacc_ring_pop_io,
};
static int k3_ringacc_ring_push_head_proxy(struct k3_ring *ring, void *elem);
static int k3_ringacc_ring_push_tail_proxy(struct k3_ring *ring, void *elem);
static int k3_ringacc_ring_pop_head_proxy(struct k3_ring *ring, void *elem);
static int k3_ringacc_ring_pop_tail_proxy(struct k3_ring *ring, void *elem);
static struct k3_ring_ops k3_ring_mode_proxy_ops = {
.push_tail = k3_ringacc_ring_push_tail_proxy,
.push_head = k3_ringacc_ring_push_head_proxy,
.pop_tail = k3_ringacc_ring_pop_tail_proxy,
.pop_head = k3_ringacc_ring_pop_head_proxy,
};
static void k3_ringacc_ring_dump(struct k3_ring *ring)
{
struct device *dev = ring->parent->dev;
dev_dbg(dev, "dump ring: %d\n", ring->ring_id);
dev_dbg(dev, "dump mem virt %p, dma %pad\n", ring->ring_mem_virt,
&ring->ring_mem_dma);
dev_dbg(dev, "dump elmsize %d, size %d, mode %d, proxy_id %d\n",
ring->elm_size, ring->size, ring->mode, ring->proxy_id);
dev_dbg(dev, "dump flags %08X\n", ring->flags);
dev_dbg(dev, "dump ring_rt_regs: db%08x\n", readl(&ring->rt->db));
dev_dbg(dev, "dump occ%08x\n", readl(&ring->rt->occ));
dev_dbg(dev, "dump indx%08x\n", readl(&ring->rt->indx));
dev_dbg(dev, "dump hwocc%08x\n", readl(&ring->rt->hwocc));
dev_dbg(dev, "dump hwindx%08x\n", readl(&ring->rt->hwindx));
if (ring->ring_mem_virt)
print_hex_dump_debug("dump ring_mem_virt ", DUMP_PREFIX_NONE,
16, 1, ring->ring_mem_virt, 16 * 8, false);
}
struct k3_ring *k3_ringacc_request_ring(struct k3_ringacc *ringacc,
int id, u32 flags)
{
int proxy_id = K3_RINGACC_PROXY_NOT_USED;
mutex_lock(&ringacc->req_lock);
if (!try_module_get(ringacc->dev->driver->owner))
goto err_module_get;
if (id == K3_RINGACC_RING_ID_ANY) {
/* Request for any general purpose ring */
struct ti_sci_resource_desc *gp_rings =
&ringacc->rm_gp_range->desc[0];
unsigned long size;
size = gp_rings->start + gp_rings->num;
id = find_next_zero_bit(ringacc->rings_inuse, size,
gp_rings->start);
if (id == size)
goto error;
} else if (id < 0) {
goto error;
}
if (test_bit(id, ringacc->rings_inuse) &&
!(ringacc->rings[id].flags & K3_RING_FLAG_SHARED))
goto error;
else if (ringacc->rings[id].flags & K3_RING_FLAG_SHARED)
goto out;
if (flags & K3_RINGACC_RING_USE_PROXY) {
proxy_id = find_first_zero_bit(ringacc->proxy_inuse,
ringacc->num_proxies);
if (proxy_id == ringacc->num_proxies)
goto error;
}
if (proxy_id != K3_RINGACC_PROXY_NOT_USED) {
set_bit(proxy_id, ringacc->proxy_inuse);
ringacc->rings[id].proxy_id = proxy_id;
dev_dbg(ringacc->dev, "Giving ring#%d proxy#%d\n", id,
proxy_id);
} else {
dev_dbg(ringacc->dev, "Giving ring#%d\n", id);
}
set_bit(id, ringacc->rings_inuse);
out:
ringacc->rings[id].use_count++;
mutex_unlock(&ringacc->req_lock);
return &ringacc->rings[id];
error:
module_put(ringacc->dev->driver->owner);
err_module_get:
mutex_unlock(&ringacc->req_lock);
return NULL;
}
EXPORT_SYMBOL_GPL(k3_ringacc_request_ring);
static int k3_dmaring_request_dual_ring(struct k3_ringacc *ringacc, int fwd_id,
struct k3_ring **fwd_ring,
struct k3_ring **compl_ring)
{
int ret = 0;
/*
* DMA rings must be requested by ID, completion ring is the reverse
* side of the forward ring
*/
if (fwd_id < 0)
return -EINVAL;
mutex_lock(&ringacc->req_lock);
if (!try_module_get(ringacc->dev->driver->owner)) {
ret = -EINVAL;
goto err_module_get;
}
if (test_bit(fwd_id, ringacc->rings_inuse)) {
ret = -EBUSY;
goto error;
}
*fwd_ring = &ringacc->rings[fwd_id];
*compl_ring = &ringacc->rings[fwd_id + ringacc->num_rings];
set_bit(fwd_id, ringacc->rings_inuse);
ringacc->rings[fwd_id].use_count++;
dev_dbg(ringacc->dev, "Giving ring#%d\n", fwd_id);
mutex_unlock(&ringacc->req_lock);
return 0;
error:
module_put(ringacc->dev->driver->owner);
err_module_get:
mutex_unlock(&ringacc->req_lock);
return ret;
}
int k3_ringacc_request_rings_pair(struct k3_ringacc *ringacc,
int fwd_id, int compl_id,
struct k3_ring **fwd_ring,
struct k3_ring **compl_ring)
{
int ret = 0;
if (!fwd_ring || !compl_ring)
return -EINVAL;
if (ringacc->dma_rings)
return k3_dmaring_request_dual_ring(ringacc, fwd_id,
fwd_ring, compl_ring);
*fwd_ring = k3_ringacc_request_ring(ringacc, fwd_id, 0);
if (!(*fwd_ring))
return -ENODEV;
*compl_ring = k3_ringacc_request_ring(ringacc, compl_id, 0);
if (!(*compl_ring)) {
k3_ringacc_ring_free(*fwd_ring);
ret = -ENODEV;
}
return ret;
}
EXPORT_SYMBOL_GPL(k3_ringacc_request_rings_pair);
static void k3_ringacc_ring_reset_sci(struct k3_ring *ring)
{
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
int ret;
ring_cfg.nav_id = ringacc->tisci_dev_id;
ring_cfg.index = ring->ring_id;
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
ring_cfg.count = ring->size;
ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
if (ret)
dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
ret, ring->ring_id);
}
void k3_ringacc_ring_reset(struct k3_ring *ring)
{
if (!ring || !(ring->flags & K3_RING_FLAG_BUSY))
return;
memset(&ring->state, 0, sizeof(ring->state));
k3_ringacc_ring_reset_sci(ring);
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_reset);
static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_ring *ring,
enum k3_ring_mode mode)
{
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
int ret;
ring_cfg.nav_id = ringacc->tisci_dev_id;
ring_cfg.index = ring->ring_id;
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_MODE_VALID;
ring_cfg.mode = mode;
ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
if (ret)
dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
ret, ring->ring_id);
}
void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ)
{
if (!ring || !(ring->flags & K3_RING_FLAG_BUSY))
return;
if (!ring->parent->dma_ring_reset_quirk)
goto reset;
if (!occ)
occ = k3_ringacc_ring_read_occ(ring);
if (occ) {
u32 db_ring_cnt, db_ring_cnt_cur;
dev_dbg(ring->parent->dev, "%s %u occ: %u\n", __func__,
ring->ring_id, occ);
/* TI-SCI ring reset */
k3_ringacc_ring_reset_sci(ring);
/*
* Setup the ring in ring/doorbell mode (if not already in this
* mode)
*/
if (ring->mode != K3_RINGACC_RING_MODE_RING)
k3_ringacc_ring_reconfig_qmode_sci(
ring, K3_RINGACC_RING_MODE_RING);
/*
* Ring the doorbell 2**22 – ringOcc times.
* This will wrap the internal UDMAP ring state occupancy
* counter (which is 21-bits wide) to 0.
*/
db_ring_cnt = (1U << 22) - occ;
while (db_ring_cnt != 0) {
/*
* Ring the doorbell with the maximum count each
* iteration if possible to minimize the total
* of writes
*/
if (db_ring_cnt > K3_RINGACC_MAX_DB_RING_CNT)
db_ring_cnt_cur = K3_RINGACC_MAX_DB_RING_CNT;
else
db_ring_cnt_cur = db_ring_cnt;
writel(db_ring_cnt_cur, &ring->rt->db);
db_ring_cnt -= db_ring_cnt_cur;
}
/* Restore the original ring mode (if not ring mode) */
if (ring->mode != K3_RINGACC_RING_MODE_RING)
k3_ringacc_ring_reconfig_qmode_sci(ring, ring->mode);
}
reset:
/* Reset the ring */
k3_ringacc_ring_reset(ring);
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_reset_dma);
static void k3_ringacc_ring_free_sci(struct k3_ring *ring)
{
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
int ret;
ring_cfg.nav_id = ringacc->tisci_dev_id;
ring_cfg.index = ring->ring_id;
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
if (ret)
dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
ret, ring->ring_id);
}
int k3_ringacc_ring_free(struct k3_ring *ring)
{
struct k3_ringacc *ringacc;
if (!ring)
return -EINVAL;
ringacc = ring->parent;
/*
* DMA rings: rings shared memory and configuration, only forward ring
* is configured and reverse ring considered as slave.
*/
if (ringacc->dma_rings && (ring->flags & K3_RING_FLAG_REVERSE))
return 0;
dev_dbg(ring->parent->dev, "flags: 0x%08x\n", ring->flags);
if (!test_bit(ring->ring_id, ringacc->rings_inuse))
return -EINVAL;
mutex_lock(&ringacc->req_lock);
if (--ring->use_count)
goto out;
if (!(ring->flags & K3_RING_FLAG_BUSY))
goto no_init;
k3_ringacc_ring_free_sci(ring);
dma_free_coherent(ring->dma_dev,
ring->size * (4 << ring->elm_size),
ring->ring_mem_virt, ring->ring_mem_dma);
ring->flags = 0;
ring->ops = NULL;
ring->dma_dev = NULL;
ring->asel = 0;
if (ring->proxy_id != K3_RINGACC_PROXY_NOT_USED) {
clear_bit(ring->proxy_id, ringacc->proxy_inuse);
ring->proxy = NULL;
ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
}
no_init:
clear_bit(ring->ring_id, ringacc->rings_inuse);
module_put(ringacc->dev->driver->owner);
out:
mutex_unlock(&ringacc->req_lock);
return 0;
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_free);
u32 k3_ringacc_get_ring_id(struct k3_ring *ring)
{
if (!ring)
return -EINVAL;
return ring->ring_id;
}
EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_id);
u32 k3_ringacc_get_tisci_dev_id(struct k3_ring *ring)
{
if (!ring)
return -EINVAL;
return ring->parent->tisci_dev_id;
}
EXPORT_SYMBOL_GPL(k3_ringacc_get_tisci_dev_id);
int k3_ringacc_get_ring_irq_num(struct k3_ring *ring)
{
int irq_num;
if (!ring)
return -EINVAL;
irq_num = msi_get_virq(ring->parent->dev, ring->ring_id);
if (irq_num <= 0)
irq_num = -EINVAL;
return irq_num;
}
EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_irq_num);
static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring)
{
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
int ret;
if (!ringacc->tisci)
return -EINVAL;
ring_cfg.nav_id = ringacc->tisci_dev_id;
ring_cfg.index = ring->ring_id;
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
ring_cfg.addr_lo = lower_32_bits(ring->ring_mem_dma);
ring_cfg.addr_hi = upper_32_bits(ring->ring_mem_dma);
ring_cfg.count = ring->size;
ring_cfg.mode = ring->mode;
ring_cfg.size = ring->elm_size;
ring_cfg.asel = ring->asel;
ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
if (ret)
dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n",
ret, ring->ring_id);
return ret;
}
static int k3_dmaring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg)
{
struct k3_ringacc *ringacc;
struct k3_ring *reverse_ring;
int ret = 0;
if (cfg->elm_size != K3_RINGACC_RING_ELSIZE_8 ||
cfg->mode != K3_RINGACC_RING_MODE_RING ||
cfg->size & ~K3_DMARING_CFG_RING_SIZE_ELCNT_MASK)
return -EINVAL;
ringacc = ring->parent;
/*
* DMA rings: rings shared memory and configuration, only forward ring
* is configured and reverse ring considered as slave.
*/
if (ringacc->dma_rings && (ring->flags & K3_RING_FLAG_REVERSE))
return 0;
if (!test_bit(ring->ring_id, ringacc->rings_inuse))
return -EINVAL;
ring->size = cfg->size;
ring->elm_size = cfg->elm_size;
ring->mode = cfg->mode;
ring->asel = cfg->asel;
ring->dma_dev = cfg->dma_dev;
if (!ring->dma_dev) {
dev_warn(ringacc->dev, "dma_dev is not provided for ring%d\n",
ring->ring_id);
ring->dma_dev = ringacc->dev;
}
memset(&ring->state, 0, sizeof(ring->state));
ring->ops = &k3_dmaring_fwd_ops;
ring->ring_mem_virt = dma_alloc_coherent(ring->dma_dev,
ring->size * (4 << ring->elm_size),
&ring->ring_mem_dma, GFP_KERNEL);
if (!ring->ring_mem_virt) {
dev_err(ringacc->dev, "Failed to alloc ring mem\n");
ret = -ENOMEM;
goto err_free_ops;
}
ret = k3_ringacc_ring_cfg_sci(ring);
if (ret)
goto err_free_mem;
ring->flags |= K3_RING_FLAG_BUSY;
k3_ringacc_ring_dump(ring);
/* DMA rings: configure reverse ring */
reverse_ring = &ringacc->rings[ring->ring_id + ringacc->num_rings];
reverse_ring->size = cfg->size;
reverse_ring->elm_size = cfg->elm_size;
reverse_ring->mode = cfg->mode;
reverse_ring->asel = cfg->asel;
memset(&reverse_ring->state, 0, sizeof(reverse_ring->state));
reverse_ring->ops = &k3_dmaring_reverse_ops;
reverse_ring->ring_mem_virt = ring->ring_mem_virt;
reverse_ring->ring_mem_dma = ring->ring_mem_dma;
reverse_ring->flags |= K3_RING_FLAG_BUSY;
k3_ringacc_ring_dump(reverse_ring);
return 0;
err_free_mem:
dma_free_coherent(ring->dma_dev,
ring->size * (4 << ring->elm_size),
ring->ring_mem_virt,
ring->ring_mem_dma);
err_free_ops:
ring->ops = NULL;
ring->proxy = NULL;
ring->dma_dev = NULL;
ring->asel = 0;
return ret;
}
int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg)
{
struct k3_ringacc *ringacc;
int ret = 0;
if (!ring || !cfg)
return -EINVAL;
ringacc = ring->parent;
if (ringacc->dma_rings)
return k3_dmaring_cfg(ring, cfg);
if (cfg->elm_size > K3_RINGACC_RING_ELSIZE_256 ||
cfg->mode >= K3_RINGACC_RING_MODE_INVALID ||
cfg->size & ~K3_RINGACC_CFG_RING_SIZE_ELCNT_MASK ||
!test_bit(ring->ring_id, ringacc->rings_inuse))
return -EINVAL;
if (cfg->mode == K3_RINGACC_RING_MODE_MESSAGE &&
ring->proxy_id == K3_RINGACC_PROXY_NOT_USED &&
cfg->elm_size > K3_RINGACC_RING_ELSIZE_8) {
dev_err(ringacc->dev,
"Message mode must use proxy for %u element size\n",
4 << ring->elm_size);
return -EINVAL;
}
/*
* In case of shared ring only the first user (master user) can
* configure the ring. The sequence should be by the client:
* ring = k3_ringacc_request_ring(ringacc, ring_id, 0); # master user
* k3_ringacc_ring_cfg(ring, cfg); # master configuration
* k3_ringacc_request_ring(ringacc, ring_id, K3_RING_FLAG_SHARED);
* k3_ringacc_request_ring(ringacc, ring_id, K3_RING_FLAG_SHARED);
*/
if (ring->use_count != 1)
return 0;
ring->size = cfg->size;
ring->elm_size = cfg->elm_size;
ring->mode = cfg->mode;
memset(&ring->state, 0, sizeof(ring->state));
if (ring->proxy_id != K3_RINGACC_PROXY_NOT_USED)
ring->proxy = ringacc->proxy_target_base +
ring->proxy_id * K3_RINGACC_PROXY_TARGET_STEP;
switch (ring->mode) {
case K3_RINGACC_RING_MODE_RING:
ring->ops = &k3_ring_mode_ring_ops;
ring->dma_dev = cfg->dma_dev;
if (!ring->dma_dev)
ring->dma_dev = ringacc->dev;
break;
case K3_RINGACC_RING_MODE_MESSAGE:
ring->dma_dev = ringacc->dev;
if (ring->proxy)
ring->ops = &k3_ring_mode_proxy_ops;
else
ring->ops = &k3_ring_mode_msg_ops;
break;
default:
ring->ops = NULL;
ret = -EINVAL;
goto err_free_proxy;
}
ring->ring_mem_virt = dma_alloc_coherent(ring->dma_dev,
ring->size * (4 << ring->elm_size),
&ring->ring_mem_dma, GFP_KERNEL);
if (!ring->ring_mem_virt) {
dev_err(ringacc->dev, "Failed to alloc ring mem\n");
ret = -ENOMEM;
goto err_free_ops;
}
ret = k3_ringacc_ring_cfg_sci(ring);
if (ret)
goto err_free_mem;
ring->flags |= K3_RING_FLAG_BUSY;
ring->flags |= (cfg->flags & K3_RINGACC_RING_SHARED) ?
K3_RING_FLAG_SHARED : 0;
k3_ringacc_ring_dump(ring);
return 0;
err_free_mem:
dma_free_coherent(ring->dma_dev,
ring->size * (4 << ring->elm_size),
ring->ring_mem_virt,
ring->ring_mem_dma);
err_free_ops:
ring->ops = NULL;
ring->dma_dev = NULL;
err_free_proxy:
ring->proxy = NULL;
return ret;
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_cfg);
u32 k3_ringacc_ring_get_size(struct k3_ring *ring)
{
if (!ring || !(ring->flags & K3_RING_FLAG_BUSY))
return -EINVAL;
return ring->size;
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_size);
u32 k3_ringacc_ring_get_free(struct k3_ring *ring)
{
if (!ring || !(ring->flags & K3_RING_FLAG_BUSY))
return -EINVAL;
if (!ring->state.free)
ring->state.free = ring->size - k3_ringacc_ring_read_occ(ring);
return ring->state.free;
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_free);
u32 k3_ringacc_ring_get_occ(struct k3_ring *ring)
{
if (!ring || !(ring->flags & K3_RING_FLAG_BUSY))
return -EINVAL;
return k3_ringacc_ring_read_occ(ring);
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_occ);
u32 k3_ringacc_ring_is_full(struct k3_ring *ring)
{
return !k3_ringacc_ring_get_free(ring);
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_is_full);
enum k3_ringacc_access_mode {
K3_RINGACC_ACCESS_MODE_PUSH_HEAD,
K3_RINGACC_ACCESS_MODE_POP_HEAD,
K3_RINGACC_ACCESS_MODE_PUSH_TAIL,
K3_RINGACC_ACCESS_MODE_POP_TAIL,
K3_RINGACC_ACCESS_MODE_PEEK_HEAD,
K3_RINGACC_ACCESS_MODE_PEEK_TAIL,
};
#define K3_RINGACC_PROXY_MODE(x) (((x) & 0x3) << 16)
#define K3_RINGACC_PROXY_ELSIZE(x) (((x) & 0x7) << 24)
static int k3_ringacc_ring_cfg_proxy(struct k3_ring *ring,
enum k3_ringacc_proxy_access_mode mode)
{
u32 val;
val = ring->ring_id;
val |= K3_RINGACC_PROXY_MODE(mode);
val |= K3_RINGACC_PROXY_ELSIZE(ring->elm_size);
writel(val, &ring->proxy->control);
return 0;
}
static int k3_ringacc_ring_access_proxy(struct k3_ring *ring, void *elem,
enum k3_ringacc_access_mode access_mode)
{
void __iomem *ptr;
ptr = (void __iomem *)&ring->proxy->data;
switch (access_mode) {
case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
case K3_RINGACC_ACCESS_MODE_POP_HEAD:
k3_ringacc_ring_cfg_proxy(ring, PROXY_ACCESS_MODE_HEAD);
break;
case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
case K3_RINGACC_ACCESS_MODE_POP_TAIL:
k3_ringacc_ring_cfg_proxy(ring, PROXY_ACCESS_MODE_TAIL);
break;
default:
return -EINVAL;
}
ptr += k3_ringacc_ring_get_fifo_pos(ring);
switch (access_mode) {
case K3_RINGACC_ACCESS_MODE_POP_HEAD:
case K3_RINGACC_ACCESS_MODE_POP_TAIL:
dev_dbg(ring->parent->dev,
"proxy:memcpy_fromio(x): --> ptr(%p), mode:%d\n", ptr,
access_mode);
memcpy_fromio(elem, ptr, (4 << ring->elm_size));
ring->state.occ--;
break;
case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
dev_dbg(ring->parent->dev,
"proxy:memcpy_toio(x): --> ptr(%p), mode:%d\n", ptr,
access_mode);
memcpy_toio(ptr, elem, (4 << ring->elm_size));
ring->state.free--;
break;
default:
return -EINVAL;
}
dev_dbg(ring->parent->dev, "proxy: free%d occ%d\n", ring->state.free,
ring->state.occ);
return 0;
}
static int k3_ringacc_ring_push_head_proxy(struct k3_ring *ring, void *elem)
{
return k3_ringacc_ring_access_proxy(ring, elem,
K3_RINGACC_ACCESS_MODE_PUSH_HEAD);
}
static int k3_ringacc_ring_push_tail_proxy(struct k3_ring *ring, void *elem)
{
return k3_ringacc_ring_access_proxy(ring, elem,
K3_RINGACC_ACCESS_MODE_PUSH_TAIL);
}
static int k3_ringacc_ring_pop_head_proxy(struct k3_ring *ring, void *elem)
{
return k3_ringacc_ring_access_proxy(ring, elem,
K3_RINGACC_ACCESS_MODE_POP_HEAD);
}
static int k3_ringacc_ring_pop_tail_proxy(struct k3_ring *ring, void *elem)
{
return k3_ringacc_ring_access_proxy(ring, elem,
K3_RINGACC_ACCESS_MODE_POP_HEAD);
}
static int k3_ringacc_ring_access_io(struct k3_ring *ring, void *elem,
enum k3_ringacc_access_mode access_mode)
{
void __iomem *ptr;
switch (access_mode) {
case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
case K3_RINGACC_ACCESS_MODE_POP_HEAD:
ptr = (void __iomem *)&ring->fifos->head_data;
break;
case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
case K3_RINGACC_ACCESS_MODE_POP_TAIL:
ptr = (void __iomem *)&ring->fifos->tail_data;
break;
default:
return -EINVAL;
}
ptr += k3_ringacc_ring_get_fifo_pos(ring);
switch (access_mode) {
case K3_RINGACC_ACCESS_MODE_POP_HEAD:
case K3_RINGACC_ACCESS_MODE_POP_TAIL:
dev_dbg(ring->parent->dev,
"memcpy_fromio(x): --> ptr(%p), mode:%d\n", ptr,
access_mode);
memcpy_fromio(elem, ptr, (4 << ring->elm_size));
ring->state.occ--;
break;
case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
dev_dbg(ring->parent->dev,
"memcpy_toio(x): --> ptr(%p), mode:%d\n", ptr,
access_mode);
memcpy_toio(ptr, elem, (4 << ring->elm_size));
ring->state.free--;
break;
default:
return -EINVAL;
}
dev_dbg(ring->parent->dev, "free%d index%d occ%d index%d\n",
ring->state.free, ring->state.windex, ring->state.occ,
ring->state.rindex);
return 0;
}
static int k3_ringacc_ring_push_head_io(struct k3_ring *ring, void *elem)
{
return k3_ringacc_ring_access_io(ring, elem,
K3_RINGACC_ACCESS_MODE_PUSH_HEAD);
}
static int k3_ringacc_ring_push_io(struct k3_ring *ring, void *elem)
{
return k3_ringacc_ring_access_io(ring, elem,
K3_RINGACC_ACCESS_MODE_PUSH_TAIL);
}
static int k3_ringacc_ring_pop_io(struct k3_ring *ring, void *elem)
{
return k3_ringacc_ring_access_io(ring, elem,
K3_RINGACC_ACCESS_MODE_POP_HEAD);
}
static int k3_ringacc_ring_pop_tail_io(struct k3_ring *ring, void *elem)
{
return k3_ringacc_ring_access_io(ring, elem,
K3_RINGACC_ACCESS_MODE_POP_HEAD);
}
/*
* The element is 48 bits of address + ASEL bits in the ring.
* ASEL is used by the DMAs and should be removed for the kernel as it is not
* part of the physical memory address.
*/
static void k3_dmaring_remove_asel_from_elem(u64 *elem)
{
*elem &= GENMASK_ULL(K3_ADDRESS_ASEL_SHIFT - 1, 0);
}
static int k3_dmaring_fwd_pop(struct k3_ring *ring, void *elem)
{
void *elem_ptr;
u32 elem_idx;
/*
* DMA rings: forward ring is always tied DMA channel and HW does not
* maintain any state data required for POP operation and its unknown
* how much elements were consumed by HW. So, to actually
* do POP, the read pointer has to be recalculated every time.
*/
ring->state.occ = k3_ringacc_ring_read_occ(ring);
if (ring->state.windex >= ring->state.occ)
elem_idx = ring->state.windex - ring->state.occ;
else
elem_idx = ring->size - (ring->state.occ - ring->state.windex);
elem_ptr = k3_ringacc_get_elm_addr(ring, elem_idx);
memcpy(elem, elem_ptr, (4 << ring->elm_size));
k3_dmaring_remove_asel_from_elem(elem);
ring->state.occ--;
writel(-1, &ring->rt->db);
dev_dbg(ring->parent->dev, "%s: occ%d Windex%d Rindex%d pos_ptr%px\n",
__func__, ring->state.occ, ring->state.windex, elem_idx,
elem_ptr);
return 0;
}
static int k3_dmaring_reverse_pop(struct k3_ring *ring, void *elem)
{
void *elem_ptr;
elem_ptr = k3_ringacc_get_elm_addr(ring, ring->state.rindex);
if (ring->state.occ) {
memcpy(elem, elem_ptr, (4 << ring->elm_size));
k3_dmaring_remove_asel_from_elem(elem);
ring->state.rindex = (ring->state.rindex + 1) % ring->size;
ring->state.occ--;
writel(-1 & K3_DMARING_RT_DB_ENTRY_MASK, &ring->rt->db);
} else if (ring->state.tdown_complete) {
dma_addr_t *value = elem;
*value = CPPI5_TDCM_MARKER;
writel(K3_DMARING_RT_DB_TDOWN_ACK, &ring->rt->db);
ring->state.tdown_complete = false;
}
dev_dbg(ring->parent->dev, "%s: occ%d index%d pos_ptr%px\n",
__func__, ring->state.occ, ring->state.rindex, elem_ptr);
return 0;
}
static int k3_ringacc_ring_push_mem(struct k3_ring *ring, void *elem)
{
void *elem_ptr;
elem_ptr = k3_ringacc_get_elm_addr(ring, ring->state.windex);
memcpy(elem_ptr, elem, (4 << ring->elm_size));
if (ring->parent->dma_rings) {
u64 *addr = elem_ptr;
*addr |= ((u64)ring->asel << K3_ADDRESS_ASEL_SHIFT);
}
ring->state.windex = (ring->state.windex + 1) % ring->size;
ring->state.free--;
writel(1, &ring->rt->db);
dev_dbg(ring->parent->dev, "ring_push_mem: free%d index%d\n",
ring->state.free, ring->state.windex);
return 0;
}
static int k3_ringacc_ring_pop_mem(struct k3_ring *ring, void *elem)
{
void *elem_ptr;
elem_ptr = k3_ringacc_get_elm_addr(ring, ring->state.rindex);
memcpy(elem, elem_ptr, (4 << ring->elm_size));
ring->state.rindex = (ring->state.rindex + 1) % ring->size;
ring->state.occ--;
writel(-1, &ring->rt->db);
dev_dbg(ring->parent->dev, "ring_pop_mem: occ%d index%d pos_ptr%p\n",
ring->state.occ, ring->state.rindex, elem_ptr);
return 0;
}
int k3_ringacc_ring_push(struct k3_ring *ring, void *elem)
{
int ret = -EOPNOTSUPP;
if (!ring || !(ring->flags & K3_RING_FLAG_BUSY))
return -EINVAL;
dev_dbg(ring->parent->dev, "ring_push: free%d index%d\n",
ring->state.free, ring->state.windex);
if (k3_ringacc_ring_is_full(ring))
return -ENOMEM;
if (ring->ops && ring->ops->push_tail)
ret = ring->ops->push_tail(ring, elem);
return ret;
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_push);
int k3_ringacc_ring_push_head(struct k3_ring *ring, void *elem)
{
int ret = -EOPNOTSUPP;
if (!ring || !(ring->flags & K3_RING_FLAG_BUSY))
return -EINVAL;
dev_dbg(ring->parent->dev, "ring_push_head: free%d index%d\n",
ring->state.free, ring->state.windex);
if (k3_ringacc_ring_is_full(ring))
return -ENOMEM;
if (ring->ops && ring->ops->push_head)
ret = ring->ops->push_head(ring, elem);
return ret;
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_push_head);
int k3_ringacc_ring_pop(struct k3_ring *ring, void *elem)
{
int ret = -EOPNOTSUPP;
if (!ring || !(ring->flags & K3_RING_FLAG_BUSY))
return -EINVAL;
if (!ring->state.occ)
k3_ringacc_ring_update_occ(ring);
dev_dbg(ring->parent->dev, "ring_pop: occ%d index%d\n", ring->state.occ,
ring->state.rindex);
if (!ring->state.occ && !ring->state.tdown_complete)
return -ENODATA;
if (ring->ops && ring->ops->pop_head)
ret = ring->ops->pop_head(ring, elem);
return ret;
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_pop);
int k3_ringacc_ring_pop_tail(struct k3_ring *ring, void *elem)
{
int ret = -EOPNOTSUPP;
if (!ring || !(ring->flags & K3_RING_FLAG_BUSY))
return -EINVAL;
if (!ring->state.occ)
k3_ringacc_ring_update_occ(ring);
dev_dbg(ring->parent->dev, "ring_pop_tail: occ%d index%d\n",
ring->state.occ, ring->state.rindex);
if (!ring->state.occ)
return -ENODATA;
if (ring->ops && ring->ops->pop_tail)
ret = ring->ops->pop_tail(ring, elem);
return ret;
}
EXPORT_SYMBOL_GPL(k3_ringacc_ring_pop_tail);
struct k3_ringacc *of_k3_ringacc_get_by_phandle(struct device_node *np,
const char *property)
{
struct device_node *ringacc_np;
struct k3_ringacc *ringacc = ERR_PTR(-EPROBE_DEFER);
struct k3_ringacc *entry;
ringacc_np = of_parse_phandle(np, property, 0);
if (!ringacc_np)
return ERR_PTR(-ENODEV);
mutex_lock(&k3_ringacc_list_lock);
list_for_each_entry(entry, &k3_ringacc_list, list)
if (entry->dev->of_node == ringacc_np) {
ringacc = entry;
break;
}
mutex_unlock(&k3_ringacc_list_lock);
of_node_put(ringacc_np);
return ringacc;
}
EXPORT_SYMBOL_GPL(of_k3_ringacc_get_by_phandle);
static int k3_ringacc_probe_dt(struct k3_ringacc *ringacc)
{
struct device_node *node = ringacc->dev->of_node;
struct device *dev = ringacc->dev;
struct platform_device *pdev = to_platform_device(dev);
int ret;
if (!node) {
dev_err(dev, "device tree info unavailable\n");
return -ENODEV;
}
ret = of_property_read_u32(node, "ti,num-rings", &ringacc->num_rings);
if (ret) {
dev_err(dev, "ti,num-rings read failure %d\n", ret);
return ret;
}
ringacc->tisci = ti_sci_get_by_phandle(node, "ti,sci");
if (IS_ERR(ringacc->tisci)) {
ret = PTR_ERR(ringacc->tisci);
if (ret != -EPROBE_DEFER)
dev_err(dev, "ti,sci read fail %d\n", ret);
ringacc->tisci = NULL;
return ret;
}
ret = of_property_read_u32(node, "ti,sci-dev-id",
&ringacc->tisci_dev_id);
if (ret) {
dev_err(dev, "ti,sci-dev-id read fail %d\n", ret);
return ret;
}
pdev->id = ringacc->tisci_dev_id;
ringacc->rm_gp_range = devm_ti_sci_get_of_resource(ringacc->tisci, dev,
ringacc->tisci_dev_id,
"ti,sci-rm-range-gp-rings");
if (IS_ERR(ringacc->rm_gp_range)) {
dev_err(dev, "Failed to allocate MSI interrupts\n");
return PTR_ERR(ringacc->rm_gp_range);
}
return ti_sci_inta_msi_domain_alloc_irqs(ringacc->dev,
ringacc->rm_gp_range);
}
static const struct k3_ringacc_soc_data k3_ringacc_soc_data_sr1 = {
.dma_ring_reset_quirk = 1,
};
static const struct soc_device_attribute k3_ringacc_socinfo[] = {
{ .family = "AM65X",
.revision = "SR1.0",
.data = &k3_ringacc_soc_data_sr1
},
{/* sentinel */}
};
static int k3_ringacc_init(struct platform_device *pdev,
struct k3_ringacc *ringacc)
{
const struct soc_device_attribute *soc;
void __iomem *base_fifo, *base_rt;
struct device *dev = &pdev->dev;
int ret, i;
dev->msi.domain = of_msi_get_domain(dev, dev->of_node,
DOMAIN_BUS_TI_SCI_INTA_MSI);
if (!dev->msi.domain)
return -EPROBE_DEFER;
ret = k3_ringacc_probe_dt(ringacc);
if (ret)
return ret;
soc = soc_device_match(k3_ringacc_socinfo);
if (soc && soc->data) {
const struct k3_ringacc_soc_data *soc_data = soc->data;
ringacc->dma_ring_reset_quirk = soc_data->dma_ring_reset_quirk;
}
base_rt = devm_platform_ioremap_resource_byname(pdev, "rt");
if (IS_ERR(base_rt))
return PTR_ERR(base_rt);
base_fifo = devm_platform_ioremap_resource_byname(pdev, "fifos");
if (IS_ERR(base_fifo))
return PTR_ERR(base_fifo);
ringacc->proxy_gcfg = devm_platform_ioremap_resource_byname(pdev, "proxy_gcfg");
if (IS_ERR(ringacc->proxy_gcfg))
return PTR_ERR(ringacc->proxy_gcfg);
ringacc->proxy_target_base = devm_platform_ioremap_resource_byname(pdev,
"proxy_target");
if (IS_ERR(ringacc->proxy_target_base))
return PTR_ERR(ringacc->proxy_target_base);
ringacc->num_proxies = readl(&ringacc->proxy_gcfg->config) &
K3_RINGACC_PROXY_CFG_THREADS_MASK;
ringacc->rings = devm_kzalloc(dev,
sizeof(*ringacc->rings) *
ringacc->num_rings,
GFP_KERNEL);
ringacc->rings_inuse = devm_bitmap_zalloc(dev, ringacc->num_rings,
GFP_KERNEL);
ringacc->proxy_inuse = devm_bitmap_zalloc(dev, ringacc->num_proxies,
GFP_KERNEL);
if (!ringacc->rings || !ringacc->rings_inuse || !ringacc->proxy_inuse)
return -ENOMEM;
for (i = 0; i < ringacc->num_rings; i++) {
ringacc->rings[i].rt = base_rt +
K3_RINGACC_RT_REGS_STEP * i;
ringacc->rings[i].fifos = base_fifo +
K3_RINGACC_FIFO_REGS_STEP * i;
ringacc->rings[i].parent = ringacc;
ringacc->rings[i].ring_id = i;
ringacc->rings[i].proxy_id = K3_RINGACC_PROXY_NOT_USED;
}
ringacc->tisci_ring_ops = &ringacc->tisci->ops.rm_ring_ops;
dev_info(dev, "Ring Accelerator probed rings:%u, gp-rings[%u,%u] sci-dev-id:%u\n",
ringacc->num_rings,
ringacc->rm_gp_range->desc[0].start,
ringacc->rm_gp_range->desc[0].num,
ringacc->tisci_dev_id);
dev_info(dev, "dma-ring-reset-quirk: %s\n",
ringacc->dma_ring_reset_quirk ? "enabled" : "disabled");
dev_info(dev, "RA Proxy rev. %08x, num_proxies:%u\n",
readl(&ringacc->proxy_gcfg->revision), ringacc->num_proxies);
return 0;
}
struct ringacc_match_data {
struct k3_ringacc_ops ops;
};
static struct ringacc_match_data k3_ringacc_data = {
.ops = {
.init = k3_ringacc_init,
},
};
/* Match table for of_platform binding */
static const struct of_device_id k3_ringacc_of_match[] = {
{ .compatible = "ti,am654-navss-ringacc", .data = &k3_ringacc_data, },
{},
};
MODULE_DEVICE_TABLE(of, k3_ringacc_of_match);
struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
struct k3_ringacc_init_data *data)
{
struct device *dev = &pdev->dev;
struct k3_ringacc *ringacc;
void __iomem *base_rt;
int i;
ringacc = devm_kzalloc(dev, sizeof(*ringacc), GFP_KERNEL);
if (!ringacc)
return ERR_PTR(-ENOMEM);
ringacc->dev = dev;
ringacc->dma_rings = true;
ringacc->num_rings = data->num_rings;
ringacc->tisci = data->tisci;
ringacc->tisci_dev_id = data->tisci_dev_id;
mutex_init(&ringacc->req_lock);
base_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt");
if (IS_ERR(base_rt))
return ERR_CAST(base_rt);
ringacc->rings = devm_kzalloc(dev,
sizeof(*ringacc->rings) *
ringacc->num_rings * 2,
GFP_KERNEL);
ringacc->rings_inuse = devm_bitmap_zalloc(dev, ringacc->num_rings,
GFP_KERNEL);
if (!ringacc->rings || !ringacc->rings_inuse)
return ERR_PTR(-ENOMEM);
for (i = 0; i < ringacc->num_rings; i++) {
struct k3_ring *ring = &ringacc->rings[i];
ring->rt = base_rt + K3_DMARING_RT_REGS_STEP * i;
ring->parent = ringacc;
ring->ring_id = i;
ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
ring = &ringacc->rings[ringacc->num_rings + i];
ring->rt = base_rt + K3_DMARING_RT_REGS_STEP * i +
K3_DMARING_RT_REGS_REVERSE_OFS;
ring->parent = ringacc;
ring->ring_id = i;
ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
ring->flags = K3_RING_FLAG_REVERSE;
}
ringacc->tisci_ring_ops = &ringacc->tisci->ops.rm_ring_ops;
dev_info(dev, "Number of rings: %u\n", ringacc->num_rings);
return ringacc;
}
EXPORT_SYMBOL_GPL(k3_ringacc_dmarings_init);
static int k3_ringacc_probe(struct platform_device *pdev)
{
const struct ringacc_match_data *match_data;
struct device *dev = &pdev->dev;
struct k3_ringacc *ringacc;
int ret;
match_data = of_device_get_match_data(&pdev->dev);
if (!match_data)
return -ENODEV;
ringacc = devm_kzalloc(dev, sizeof(*ringacc), GFP_KERNEL);
if (!ringacc)
return -ENOMEM;
ringacc->dev = dev;
mutex_init(&ringacc->req_lock);
ringacc->ops = &match_data->ops;
ret = ringacc->ops->init(pdev, ringacc);
if (ret)
return ret;
dev_set_drvdata(dev, ringacc);
mutex_lock(&k3_ringacc_list_lock);
list_add_tail(&ringacc->list, &k3_ringacc_list);
mutex_unlock(&k3_ringacc_list_lock);
return 0;
}
static int k3_ringacc_remove(struct platform_device *pdev)
{
struct k3_ringacc *ringacc = dev_get_drvdata(&pdev->dev);
mutex_lock(&k3_ringacc_list_lock);
list_del(&ringacc->list);
mutex_unlock(&k3_ringacc_list_lock);
return 0;
}
static struct platform_driver k3_ringacc_driver = {
.probe = k3_ringacc_probe,
.remove = k3_ringacc_remove,
.driver = {
.name = "k3-ringacc",
.of_match_table = k3_ringacc_of_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(k3_ringacc_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("TI Ringacc driver for K3 SOCs");
MODULE_AUTHOR("Grygorii Strashko <[email protected]>");
|
linux-master
|
drivers/soc/ti/k3-ringacc.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* AM33XX Power Management Routines
*
* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
* Vaibhav Bedia, Dave Gerlach
*/
#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/err.h>
#include <linux/genalloc.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_data/pm33xx.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/rtc.h>
#include <linux/rtc/rtc-omap.h>
#include <linux/sizes.h>
#include <linux/sram.h>
#include <linux/suspend.h>
#include <linux/ti-emif-sram.h>
#include <linux/wkup_m3_ipc.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include <asm/system_misc.h>
#define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
(unsigned long)pm_sram->do_wfi)
#define RTC_SCRATCH_RESUME_REG 0
#define RTC_SCRATCH_MAGIC_REG 1
#define RTC_REG_BOOT_MAGIC 0x8cd0 /* RTC */
#define GIC_INT_SET_PENDING_BASE 0x200
#define AM43XX_GIC_DIST_BASE 0x48241000
static void __iomem *rtc_base_virt;
static struct clk *rtc_fck;
static u32 rtc_magic_val;
static int (*am33xx_do_wfi_sram)(unsigned long unused);
static phys_addr_t am33xx_do_wfi_sram_phys;
static struct gen_pool *sram_pool, *sram_pool_data;
static unsigned long ocmcram_location, ocmcram_location_data;
static struct rtc_device *omap_rtc;
static void __iomem *gic_dist_base;
static struct am33xx_pm_platform_data *pm_ops;
static struct am33xx_pm_sram_addr *pm_sram;
static struct device *pm33xx_dev;
static struct wkup_m3_ipc *m3_ipc;
#ifdef CONFIG_SUSPEND
static int rtc_only_idle;
static int retrigger_irq;
static unsigned long suspend_wfi_flags;
static struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0,
.src = "Unknown",
};
static struct wkup_m3_wakeup_src rtc_alarm_wakeup = {
.irq_nr = 108, .src = "RTC Alarm",
};
static struct wkup_m3_wakeup_src rtc_ext_wakeup = {
.irq_nr = 0, .src = "Ext wakeup",
};
#endif
static u32 sram_suspend_address(unsigned long addr)
{
return ((unsigned long)am33xx_do_wfi_sram +
AMX3_PM_SRAM_SYMBOL_OFFSET(addr));
}
static int am33xx_push_sram_idle(void)
{
struct am33xx_pm_ro_sram_data ro_sram_data;
int ret;
u32 table_addr, ro_data_addr;
void *copy_addr;
ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
ro_sram_data.amx3_pm_sram_data_phys =
gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
ro_sram_data.rtc_base_virt = rtc_base_virt;
/* Save physical address to calculate resume offset during pm init */
am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
ocmcram_location);
am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location,
pm_sram->do_wfi,
*pm_sram->do_wfi_sz);
if (!am33xx_do_wfi_sram) {
dev_err(pm33xx_dev,
"PM: %s: am33xx_do_wfi copy to sram failed\n",
__func__);
return -ENODEV;
}
table_addr =
sram_suspend_address((unsigned long)pm_sram->emif_sram_table);
ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr);
if (ret) {
dev_dbg(pm33xx_dev,
"PM: %s: EMIF function copy failed\n", __func__);
return -EPROBE_DEFER;
}
ro_data_addr =
sram_suspend_address((unsigned long)pm_sram->ro_sram_data);
copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr,
&ro_sram_data,
sizeof(ro_sram_data));
if (!copy_addr) {
dev_err(pm33xx_dev,
"PM: %s: ro_sram_data copy to sram failed\n",
__func__);
return -ENODEV;
}
return 0;
}
static int am33xx_do_sram_idle(u32 wfi_flags)
{
if (!m3_ipc || !pm_ops)
return 0;
if (wfi_flags & WFI_FLAG_WAKE_M3)
m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE);
return pm_ops->cpu_suspend(am33xx_do_wfi_sram, wfi_flags);
}
static int __init am43xx_map_gic(void)
{
gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K);
if (!gic_dist_base)
return -ENOMEM;
return 0;
}
#ifdef CONFIG_SUSPEND
static struct wkup_m3_wakeup_src rtc_wake_src(void)
{
u32 i;
i = __raw_readl(rtc_base_virt + 0x44) & 0x40;
if (i) {
retrigger_irq = rtc_alarm_wakeup.irq_nr;
return rtc_alarm_wakeup;
}
retrigger_irq = rtc_ext_wakeup.irq_nr;
return rtc_ext_wakeup;
}
static int am33xx_rtc_only_idle(unsigned long wfi_flags)
{
omap_rtc_power_off_program(&omap_rtc->dev);
am33xx_do_wfi_sram(wfi_flags);
return 0;
}
/*
* Note that the RTC module clock must be re-enabled only for rtc+ddr suspend.
* And looks like the module can stay in SYSC_IDLE_SMART_WKUP mode configured
* by the interconnect code just fine for both rtc+ddr suspend and retention
* suspend.
*/
static int am33xx_pm_suspend(suspend_state_t suspend_state)
{
int i, ret = 0;
if (suspend_state == PM_SUSPEND_MEM &&
pm_ops->check_off_mode_enable()) {
ret = clk_prepare_enable(rtc_fck);
if (ret) {
dev_err(pm33xx_dev, "Failed to enable clock: %i\n", ret);
return ret;
}
pm_ops->save_context();
suspend_wfi_flags |= WFI_FLAG_RTC_ONLY;
clk_save_context();
ret = pm_ops->soc_suspend(suspend_state, am33xx_rtc_only_idle,
suspend_wfi_flags);
suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY;
dev_info(pm33xx_dev, "Entering RTC Only mode with DDR in self-refresh\n");
if (!ret) {
clk_restore_context();
pm_ops->restore_context();
m3_ipc->ops->set_rtc_only(m3_ipc);
am33xx_push_sram_idle();
}
} else {
ret = pm_ops->soc_suspend(suspend_state, am33xx_do_wfi_sram,
suspend_wfi_flags);
}
if (ret) {
dev_err(pm33xx_dev, "PM: Kernel suspend failure\n");
} else {
i = m3_ipc->ops->request_pm_status(m3_ipc);
switch (i) {
case 0:
dev_info(pm33xx_dev,
"PM: Successfully put all powerdomains to target state\n");
break;
case 1:
dev_err(pm33xx_dev,
"PM: Could not transition all powerdomains to target state\n");
ret = -1;
break;
default:
dev_err(pm33xx_dev,
"PM: CM3 returned unknown result = %d\n", i);
ret = -1;
}
/* print the wakeup reason */
if (rtc_only_idle) {
wakeup_src = rtc_wake_src();
pr_info("PM: Wakeup source %s\n", wakeup_src.src);
} else {
pr_info("PM: Wakeup source %s\n",
m3_ipc->ops->request_wake_src(m3_ipc));
}
}
if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable())
clk_disable_unprepare(rtc_fck);
return ret;
}
static int am33xx_pm_enter(suspend_state_t suspend_state)
{
int ret = 0;
switch (suspend_state) {
case PM_SUSPEND_MEM:
case PM_SUSPEND_STANDBY:
ret = am33xx_pm_suspend(suspend_state);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int am33xx_pm_begin(suspend_state_t state)
{
int ret = -EINVAL;
struct nvmem_device *nvmem;
if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) {
nvmem = devm_nvmem_device_get(&omap_rtc->dev,
"omap_rtc_scratch0");
if (!IS_ERR(nvmem))
nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
(void *)&rtc_magic_val);
rtc_only_idle = 1;
} else {
rtc_only_idle = 0;
}
pm_ops->begin_suspend();
switch (state) {
case PM_SUSPEND_MEM:
ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_DEEPSLEEP);
break;
case PM_SUSPEND_STANDBY:
ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_STANDBY);
break;
}
return ret;
}
static void am33xx_pm_end(void)
{
u32 val = 0;
struct nvmem_device *nvmem;
nvmem = devm_nvmem_device_get(&omap_rtc->dev, "omap_rtc_scratch0");
if (IS_ERR(nvmem))
return;
m3_ipc->ops->finish_low_power(m3_ipc);
if (rtc_only_idle) {
if (retrigger_irq) {
/*
* 32 bits of Interrupt Set-Pending correspond to 32
* 32 interrupts. Compute the bit offset of the
* Interrupt and set that particular bit
* Compute the register offset by dividing interrupt
* number by 32 and mutiplying by 4
*/
writel_relaxed(1 << (retrigger_irq & 31),
gic_dist_base + GIC_INT_SET_PENDING_BASE
+ retrigger_irq / 32 * 4);
}
nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
(void *)&val);
}
rtc_only_idle = 0;
pm_ops->finish_suspend();
}
static int am33xx_pm_valid(suspend_state_t state)
{
switch (state) {
case PM_SUSPEND_STANDBY:
case PM_SUSPEND_MEM:
return 1;
default:
return 0;
}
}
static const struct platform_suspend_ops am33xx_pm_ops = {
.begin = am33xx_pm_begin,
.end = am33xx_pm_end,
.enter = am33xx_pm_enter,
.valid = am33xx_pm_valid,
};
#endif /* CONFIG_SUSPEND */
static void am33xx_pm_set_ipc_ops(void)
{
u32 resume_address;
int temp;
temp = ti_emif_get_mem_type();
if (temp < 0) {
dev_err(pm33xx_dev, "PM: Cannot determine memory type, no PM available\n");
return;
}
m3_ipc->ops->set_mem_type(m3_ipc, temp);
/* Physical resume address to be used by ROM code */
resume_address = am33xx_do_wfi_sram_phys +
*pm_sram->resume_offset + 0x4;
m3_ipc->ops->set_resume_address(m3_ipc, (void *)resume_address);
}
static void am33xx_pm_free_sram(void)
{
gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
gen_pool_free(sram_pool_data, ocmcram_location_data,
sizeof(struct am33xx_pm_ro_sram_data));
}
/*
* Push the minimal suspend-resume code to SRAM
*/
static int am33xx_pm_alloc_sram(void)
{
struct device_node *np;
int ret = 0;
np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu");
if (!np) {
np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
if (!np) {
dev_err(pm33xx_dev, "PM: %s: Unable to find device node for mpu\n",
__func__);
return -ENODEV;
}
}
sram_pool = of_gen_pool_get(np, "pm-sram", 0);
if (!sram_pool) {
dev_err(pm33xx_dev, "PM: %s: Unable to get sram pool for ocmcram\n",
__func__);
ret = -ENODEV;
goto mpu_put_node;
}
sram_pool_data = of_gen_pool_get(np, "pm-sram", 1);
if (!sram_pool_data) {
dev_err(pm33xx_dev, "PM: %s: Unable to get sram data pool for ocmcram\n",
__func__);
ret = -ENODEV;
goto mpu_put_node;
}
ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz);
if (!ocmcram_location) {
dev_err(pm33xx_dev, "PM: %s: Unable to allocate memory from ocmcram\n",
__func__);
ret = -ENOMEM;
goto mpu_put_node;
}
ocmcram_location_data = gen_pool_alloc(sram_pool_data,
sizeof(struct emif_regs_amx3));
if (!ocmcram_location_data) {
dev_err(pm33xx_dev, "PM: Unable to allocate memory from ocmcram\n");
gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
ret = -ENOMEM;
}
mpu_put_node:
of_node_put(np);
return ret;
}
static int am33xx_pm_rtc_setup(void)
{
struct device_node *np;
unsigned long val = 0;
struct nvmem_device *nvmem;
int error;
np = of_find_node_by_name(NULL, "rtc");
if (of_device_is_available(np)) {
/* RTC interconnect target module clock */
rtc_fck = of_clk_get_by_name(np->parent, "fck");
if (IS_ERR(rtc_fck))
return PTR_ERR(rtc_fck);
rtc_base_virt = of_iomap(np, 0);
if (!rtc_base_virt) {
pr_warn("PM: could not iomap rtc");
error = -ENODEV;
goto err_clk_put;
}
omap_rtc = rtc_class_open("rtc0");
if (!omap_rtc) {
pr_warn("PM: rtc0 not available");
error = -EPROBE_DEFER;
goto err_iounmap;
}
nvmem = devm_nvmem_device_get(&omap_rtc->dev,
"omap_rtc_scratch0");
if (!IS_ERR(nvmem)) {
nvmem_device_read(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
4, (void *)&rtc_magic_val);
if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC)
pr_warn("PM: bootloader does not support rtc-only!\n");
nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
4, (void *)&val);
val = pm_sram->resume_address;
nvmem_device_write(nvmem, RTC_SCRATCH_RESUME_REG * 4,
4, (void *)&val);
}
} else {
pr_warn("PM: no-rtc available, rtc-only mode disabled.\n");
}
return 0;
err_iounmap:
iounmap(rtc_base_virt);
err_clk_put:
clk_put(rtc_fck);
return error;
}
static int am33xx_pm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret;
if (!of_machine_is_compatible("ti,am33xx") &&
!of_machine_is_compatible("ti,am43"))
return -ENODEV;
pm_ops = dev->platform_data;
if (!pm_ops) {
dev_err(dev, "PM: Cannot get core PM ops!\n");
return -ENODEV;
}
ret = am43xx_map_gic();
if (ret) {
pr_err("PM: Could not ioremap GIC base\n");
return ret;
}
pm_sram = pm_ops->get_sram_addrs();
if (!pm_sram) {
dev_err(dev, "PM: Cannot get PM asm function addresses!!\n");
return -ENODEV;
}
m3_ipc = wkup_m3_ipc_get();
if (!m3_ipc) {
pr_err("PM: Cannot get wkup_m3_ipc handle\n");
return -EPROBE_DEFER;
}
pm33xx_dev = dev;
ret = am33xx_pm_alloc_sram();
if (ret)
goto err_wkup_m3_ipc_put;
ret = am33xx_pm_rtc_setup();
if (ret)
goto err_free_sram;
ret = am33xx_push_sram_idle();
if (ret)
goto err_unsetup_rtc;
am33xx_pm_set_ipc_ops();
#ifdef CONFIG_SUSPEND
suspend_set_ops(&am33xx_pm_ops);
/*
* For a system suspend we must flush the caches, we want
* the DDR in self-refresh, we want to save the context
* of the EMIF, and we want the wkup_m3 to handle low-power
* transition.
*/
suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE;
suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH;
suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF;
suspend_wfi_flags |= WFI_FLAG_WAKE_M3;
#endif /* CONFIG_SUSPEND */
pm_runtime_enable(dev);
ret = pm_runtime_resume_and_get(dev);
if (ret < 0)
goto err_pm_runtime_disable;
ret = pm_ops->init(am33xx_do_sram_idle);
if (ret) {
dev_err(dev, "Unable to call core pm init!\n");
ret = -ENODEV;
goto err_pm_runtime_put;
}
return 0;
err_pm_runtime_put:
pm_runtime_put_sync(dev);
err_pm_runtime_disable:
pm_runtime_disable(dev);
err_unsetup_rtc:
iounmap(rtc_base_virt);
clk_put(rtc_fck);
err_free_sram:
am33xx_pm_free_sram();
pm33xx_dev = NULL;
err_wkup_m3_ipc_put:
wkup_m3_ipc_put(m3_ipc);
return ret;
}
static int am33xx_pm_remove(struct platform_device *pdev)
{
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
if (pm_ops->deinit)
pm_ops->deinit();
suspend_set_ops(NULL);
wkup_m3_ipc_put(m3_ipc);
am33xx_pm_free_sram();
iounmap(rtc_base_virt);
clk_put(rtc_fck);
return 0;
}
static struct platform_driver am33xx_pm_driver = {
.driver = {
.name = "pm33xx",
},
.probe = am33xx_pm_probe,
.remove = am33xx_pm_remove,
};
module_platform_driver(am33xx_pm_driver);
MODULE_ALIAS("platform:pm33xx");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("am33xx power management driver");
|
linux-master
|
drivers/soc/ti/pm33xx.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* OMAP SmartReflex Voltage Control
*
* Author: Thara Gopinath <[email protected]>
*
* Copyright (C) 2012 Texas Instruments, Inc.
* Thara Gopinath <[email protected]>
*
* Copyright (C) 2008 Nokia Corporation
* Kalle Jokiniemi
*
* Copyright (C) 2007 Texas Instruments, Inc.
* Lesly A M <[email protected]>
*/
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/power/smartreflex.h>
#define DRIVER_NAME "smartreflex"
#define SMARTREFLEX_NAME_LEN 32
#define NVALUE_NAME_LEN 40
#define SR_DISABLE_TIMEOUT 200
/* sr_list contains all the instances of smartreflex module */
static LIST_HEAD(sr_list);
static struct omap_sr_class_data *sr_class;
static struct dentry *sr_dbg_dir;
static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
{
__raw_writel(value, (sr->base + offset));
}
static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
u32 value)
{
u32 reg_val;
/*
* Smartreflex error config register is special as it contains
* certain status bits which if written a 1 into means a clear
* of those bits. So in order to make sure no accidental write of
* 1 happens to those status bits, do a clear of them in the read
* value. This mean this API doesn't rewrite values in these bits
* if they are currently set, but does allow the caller to write
* those bits.
*/
if (sr->ip_type == SR_TYPE_V1 && offset == ERRCONFIG_V1)
mask |= ERRCONFIG_STATUS_V1_MASK;
else if (sr->ip_type == SR_TYPE_V2 && offset == ERRCONFIG_V2)
mask |= ERRCONFIG_VPBOUNDINTST_V2;
reg_val = __raw_readl(sr->base + offset);
reg_val &= ~mask;
value &= mask;
reg_val |= value;
__raw_writel(reg_val, (sr->base + offset));
}
static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
{
return __raw_readl(sr->base + offset);
}
static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
{
struct omap_sr *sr_info;
if (!voltdm) {
pr_err("%s: Null voltage domain passed!\n", __func__);
return ERR_PTR(-EINVAL);
}
list_for_each_entry(sr_info, &sr_list, node) {
if (voltdm == sr_info->voltdm)
return sr_info;
}
return ERR_PTR(-ENODATA);
}
static irqreturn_t sr_interrupt(int irq, void *data)
{
struct omap_sr *sr_info = data;
u32 status = 0;
switch (sr_info->ip_type) {
case SR_TYPE_V1:
/* Read the status bits */
status = sr_read_reg(sr_info, ERRCONFIG_V1);
/* Clear them by writing back */
sr_write_reg(sr_info, ERRCONFIG_V1, status);
break;
case SR_TYPE_V2:
/* Read the status bits */
status = sr_read_reg(sr_info, IRQSTATUS);
/* Clear them by writing back */
sr_write_reg(sr_info, IRQSTATUS, status);
break;
default:
dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n",
sr_info->ip_type);
return IRQ_NONE;
}
if (sr_class->notify)
sr_class->notify(sr_info, status);
return IRQ_HANDLED;
}
static void sr_set_clk_length(struct omap_sr *sr)
{
u32 fclk_speed;
/* Try interconnect target module fck first if it already exists */
if (IS_ERR(sr->fck))
return;
fclk_speed = clk_get_rate(sr->fck);
switch (fclk_speed) {
case 12000000:
sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
break;
case 13000000:
sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
break;
case 19200000:
sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
break;
case 26000000:
sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
break;
case 38400000:
sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
break;
default:
dev_err(&sr->pdev->dev, "%s: Invalid fclk rate: %d\n",
__func__, fclk_speed);
break;
}
}
static void sr_start_vddautocomp(struct omap_sr *sr)
{
if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
dev_warn(&sr->pdev->dev,
"%s: smartreflex class driver not registered\n",
__func__);
return;
}
if (!sr_class->enable(sr))
sr->autocomp_active = true;
}
static void sr_stop_vddautocomp(struct omap_sr *sr)
{
if (!sr_class || !(sr_class->disable)) {
dev_warn(&sr->pdev->dev,
"%s: smartreflex class driver not registered\n",
__func__);
return;
}
if (sr->autocomp_active) {
sr_class->disable(sr, 1);
sr->autocomp_active = false;
}
}
/*
* This function handles the initializations which have to be done
* only when both sr device and class driver regiter has
* completed. This will be attempted to be called from both sr class
* driver register and sr device intializtion API's. Only one call
* will ultimately succeed.
*
* Currently this function registers interrupt handler for a particular SR
* if smartreflex class driver is already registered and has
* requested for interrupts and the SR interrupt line in present.
*/
static int sr_late_init(struct omap_sr *sr_info)
{
int ret = 0;
if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
ret = devm_request_irq(&sr_info->pdev->dev, sr_info->irq,
sr_interrupt, 0, sr_info->name, sr_info);
if (ret)
goto error;
disable_irq(sr_info->irq);
}
return ret;
error:
list_del(&sr_info->node);
dev_err(&sr_info->pdev->dev, "%s: ERROR in registering interrupt handler. Smartreflex will not function as desired\n",
__func__);
return ret;
}
static void sr_v1_disable(struct omap_sr *sr)
{
int timeout = 0;
int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
ERRCONFIG_MCUBOUNDINTST;
/* Enable MCUDisableAcknowledge interrupt */
sr_modify_reg(sr, ERRCONFIG_V1,
ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
/* SRCONFIG - disable SR */
sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
/* Disable all other SR interrupts and clear the status as needed */
if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1)
errconf_val |= ERRCONFIG_VPBOUNDINTST_V1;
sr_modify_reg(sr, ERRCONFIG_V1,
(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
errconf_val);
/*
* Wait for SR to be disabled.
* wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
*/
sr_test_cond_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
timeout);
if (timeout >= SR_DISABLE_TIMEOUT)
dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
__func__);
/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
ERRCONFIG_MCUDISACKINTST);
}
static void sr_v2_disable(struct omap_sr *sr)
{
int timeout = 0;
/* Enable MCUDisableAcknowledge interrupt */
sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
/* SRCONFIG - disable SR */
sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
/*
* Disable all other SR interrupts and clear the status
* write to status register ONLY on need basis - only if status
* is set.
*/
if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2)
sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
ERRCONFIG_VPBOUNDINTST_V2);
else
sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
0x0);
sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
IRQENABLE_MCUVALIDINT |
IRQENABLE_MCUBOUNDSINT));
sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
IRQSTATUS_MCVALIDINT |
IRQSTATUS_MCBOUNDSINT));
/*
* Wait for SR to be disabled.
* wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
*/
sr_test_cond_timeout((sr_read_reg(sr, IRQSTATUS) &
IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
timeout);
if (timeout >= SR_DISABLE_TIMEOUT)
dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
__func__);
/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
}
static struct omap_sr_nvalue_table *sr_retrieve_nvalue_row(
struct omap_sr *sr, u32 efuse_offs)
{
int i;
if (!sr->nvalue_table) {
dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
__func__);
return NULL;
}
for (i = 0; i < sr->nvalue_count; i++) {
if (sr->nvalue_table[i].efuse_offs == efuse_offs)
return &sr->nvalue_table[i];
}
return NULL;
}
/* Public Functions */
/**
* sr_configure_errgen() - Configures the SmartReflex to perform AVS using the
* error generator module.
* @sr: SR module to be configured.
*
* This API is to be called from the smartreflex class driver to
* configure the error generator module inside the smartreflex module.
* SR settings if using the ERROR module inside Smartreflex.
* SR CLASS 3 by default uses only the ERROR module where as
* SR CLASS 2 can choose between ERROR module and MINMAXAVG
* module. Returns 0 on success and error value in case of failure.
*/
int sr_configure_errgen(struct omap_sr *sr)
{
u32 sr_config, sr_errconfig, errconfig_offs;
u32 vpboundint_en, vpboundint_st;
u32 senp_en = 0, senn_en = 0;
u8 senp_shift, senn_shift;
if (!sr) {
pr_warn("%s: NULL omap_sr from %pS\n",
__func__, (void *)_RET_IP_);
return -EINVAL;
}
if (!sr->clk_length)
sr_set_clk_length(sr);
senp_en = sr->senp_mod;
senn_en = sr->senn_mod;
sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
switch (sr->ip_type) {
case SR_TYPE_V1:
sr_config |= SRCONFIG_DELAYCTRL;
senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
errconfig_offs = ERRCONFIG_V1;
vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
break;
case SR_TYPE_V2:
senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
errconfig_offs = ERRCONFIG_V2;
vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
break;
default:
dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
__func__);
return -EINVAL;
}
sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
sr_write_reg(sr, SRCONFIG, sr_config);
sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
(sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
(sr->err_minlimit << ERRCONFIG_ERRMINLIMIT_SHIFT);
sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
sr_errconfig);
/* Enabling the interrupts if the ERROR module is used */
sr_modify_reg(sr, errconfig_offs, (vpboundint_en | vpboundint_st),
vpboundint_en);
return 0;
}
/**
* sr_disable_errgen() - Disables SmartReflex AVS module's errgen component
* @sr: SR module to be configured.
*
* This API is to be called from the smartreflex class driver to
* disable the error generator module inside the smartreflex module.
*
* Returns 0 on success and error value in case of failure.
*/
int sr_disable_errgen(struct omap_sr *sr)
{
u32 errconfig_offs;
u32 vpboundint_en, vpboundint_st;
if (!sr) {
pr_warn("%s: NULL omap_sr from %pS\n",
__func__, (void *)_RET_IP_);
return -EINVAL;
}
switch (sr->ip_type) {
case SR_TYPE_V1:
errconfig_offs = ERRCONFIG_V1;
vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
break;
case SR_TYPE_V2:
errconfig_offs = ERRCONFIG_V2;
vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
break;
default:
dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
__func__);
return -EINVAL;
}
/* Disable the Sensor and errorgen */
sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0);
/*
* Disable the interrupts of ERROR module
* NOTE: modify is a read, modify,write - an implicit OCP barrier
* which is required is present here - sequencing is critical
* at this point (after errgen is disabled, vpboundint disable)
*/
sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
return 0;
}
/**
* sr_configure_minmax() - Configures the SmartReflex to perform AVS using the
* minmaxavg module.
* @sr: SR module to be configured.
*
* This API is to be called from the smartreflex class driver to
* configure the minmaxavg module inside the smartreflex module.
* SR settings if using the ERROR module inside Smartreflex.
* SR CLASS 3 by default uses only the ERROR module where as
* SR CLASS 2 can choose between ERROR module and MINMAXAVG
* module. Returns 0 on success and error value in case of failure.
*/
int sr_configure_minmax(struct omap_sr *sr)
{
u32 sr_config, sr_avgwt;
u32 senp_en = 0, senn_en = 0;
u8 senp_shift, senn_shift;
if (!sr) {
pr_warn("%s: NULL omap_sr from %pS\n",
__func__, (void *)_RET_IP_);
return -EINVAL;
}
if (!sr->clk_length)
sr_set_clk_length(sr);
senp_en = sr->senp_mod;
senn_en = sr->senn_mod;
sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
SRCONFIG_SENENABLE |
(sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
switch (sr->ip_type) {
case SR_TYPE_V1:
sr_config |= SRCONFIG_DELAYCTRL;
senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
break;
case SR_TYPE_V2:
senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
break;
default:
dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
__func__);
return -EINVAL;
}
sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
sr_write_reg(sr, SRCONFIG, sr_config);
sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
(sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
/*
* Enabling the interrupts if MINMAXAVG module is used.
* TODO: check if all the interrupts are mandatory
*/
switch (sr->ip_type) {
case SR_TYPE_V1:
sr_modify_reg(sr, ERRCONFIG_V1,
(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
ERRCONFIG_MCUBOUNDINTEN),
(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
break;
case SR_TYPE_V2:
sr_write_reg(sr, IRQSTATUS,
IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
sr_write_reg(sr, IRQENABLE_SET,
IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
break;
default:
dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex module without specifying the ip\n",
__func__);
return -EINVAL;
}
return 0;
}
/**
* sr_enable() - Enables the smartreflex module.
* @sr: pointer to which the SR module to be configured belongs to.
* @volt: The voltage at which the Voltage domain associated with
* the smartreflex module is operating at.
* This is required only to program the correct Ntarget value.
*
* This API is to be called from the smartreflex class driver to
* enable a smartreflex module. Returns 0 on success. Returns error
* value if the voltage passed is wrong or if ntarget value is wrong.
*/
int sr_enable(struct omap_sr *sr, unsigned long volt)
{
struct omap_volt_data *volt_data;
struct omap_sr_nvalue_table *nvalue_row;
int ret;
if (!sr) {
pr_warn("%s: NULL omap_sr from %pS\n",
__func__, (void *)_RET_IP_);
return -EINVAL;
}
volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
if (IS_ERR(volt_data)) {
dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table for nominal voltage %ld\n",
__func__, volt);
return PTR_ERR(volt_data);
}
nvalue_row = sr_retrieve_nvalue_row(sr, volt_data->sr_efuse_offs);
if (!nvalue_row) {
dev_warn(&sr->pdev->dev, "%s: failure getting SR data for this voltage %ld\n",
__func__, volt);
return -ENODATA;
}
/* errminlimit is opp dependent and hence linked to voltage */
sr->err_minlimit = nvalue_row->errminlimit;
clk_enable(sr->fck);
/* Check if SR is already enabled. If yes do nothing */
if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
goto out_enabled;
/* Configure SR */
ret = sr_class->configure(sr);
if (ret)
goto out_enabled;
sr_write_reg(sr, NVALUERECIPROCAL, nvalue_row->nvalue);
/* SRCONFIG - enable SR */
sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
out_enabled:
sr->enabled = 1;
return 0;
}
/**
* sr_disable() - Disables the smartreflex module.
* @sr: pointer to which the SR module to be configured belongs to.
*
* This API is to be called from the smartreflex class driver to
* disable a smartreflex module.
*/
void sr_disable(struct omap_sr *sr)
{
if (!sr) {
pr_warn("%s: NULL omap_sr from %pS\n",
__func__, (void *)_RET_IP_);
return;
}
/* Check if SR clocks are already disabled. If yes do nothing */
if (!sr->enabled)
return;
/*
* Disable SR if only it is indeed enabled. Else just
* disable the clocks.
*/
if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
switch (sr->ip_type) {
case SR_TYPE_V1:
sr_v1_disable(sr);
break;
case SR_TYPE_V2:
sr_v2_disable(sr);
break;
default:
dev_err(&sr->pdev->dev, "UNKNOWN IP type %d\n",
sr->ip_type);
}
}
clk_disable(sr->fck);
sr->enabled = 0;
}
/**
* sr_register_class() - API to register a smartreflex class parameters.
* @class_data: The structure containing various sr class specific data.
*
* This API is to be called by the smartreflex class driver to register itself
* with the smartreflex driver during init. Returns 0 on success else the
* error value.
*/
int sr_register_class(struct omap_sr_class_data *class_data)
{
struct omap_sr *sr_info;
if (!class_data) {
pr_warn("%s:, Smartreflex class data passed is NULL\n",
__func__);
return -EINVAL;
}
if (sr_class) {
pr_warn("%s: Smartreflex class driver already registered\n",
__func__);
return -EBUSY;
}
sr_class = class_data;
/*
* Call into late init to do initializations that require
* both sr driver and sr class driver to be initiallized.
*/
list_for_each_entry(sr_info, &sr_list, node)
sr_late_init(sr_info);
return 0;
}
/**
* omap_sr_enable() - API to enable SR clocks and to call into the
* registered smartreflex class enable API.
* @voltdm: VDD pointer to which the SR module to be configured belongs to.
*
* This API is to be called from the kernel in order to enable
* a particular smartreflex module. This API will do the initial
* configurations to turn on the smartreflex module and in turn call
* into the registered smartreflex class enable API.
*/
void omap_sr_enable(struct voltagedomain *voltdm)
{
struct omap_sr *sr = _sr_lookup(voltdm);
if (IS_ERR(sr)) {
pr_warn("%s: omap_sr struct for voltdm not found\n", __func__);
return;
}
if (!sr->autocomp_active)
return;
if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not registered\n",
__func__);
return;
}
sr_class->enable(sr);
}
/**
* omap_sr_disable() - API to disable SR without resetting the voltage
* processor voltage
* @voltdm: VDD pointer to which the SR module to be configured belongs to.
*
* This API is to be called from the kernel in order to disable
* a particular smartreflex module. This API will in turn call
* into the registered smartreflex class disable API. This API will tell
* the smartreflex class disable not to reset the VP voltage after
* disabling smartreflex.
*/
void omap_sr_disable(struct voltagedomain *voltdm)
{
struct omap_sr *sr = _sr_lookup(voltdm);
if (IS_ERR(sr)) {
pr_warn("%s: omap_sr struct for voltdm not found\n", __func__);
return;
}
if (!sr->autocomp_active)
return;
if (!sr_class || !(sr_class->disable)) {
dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not registered\n",
__func__);
return;
}
sr_class->disable(sr, 0);
}
/**
* omap_sr_disable_reset_volt() - API to disable SR and reset the
* voltage processor voltage
* @voltdm: VDD pointer to which the SR module to be configured belongs to.
*
* This API is to be called from the kernel in order to disable
* a particular smartreflex module. This API will in turn call
* into the registered smartreflex class disable API. This API will tell
* the smartreflex class disable to reset the VP voltage after
* disabling smartreflex.
*/
void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
{
struct omap_sr *sr = _sr_lookup(voltdm);
if (IS_ERR(sr)) {
pr_warn("%s: omap_sr struct for voltdm not found\n", __func__);
return;
}
if (!sr->autocomp_active)
return;
if (!sr_class || !(sr_class->disable)) {
dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not registered\n",
__func__);
return;
}
sr_class->disable(sr, 1);
}
/* PM Debug FS entries to enable and disable smartreflex. */
static int omap_sr_autocomp_show(void *data, u64 *val)
{
struct omap_sr *sr_info = data;
if (!sr_info) {
pr_warn("%s: omap_sr struct not found\n", __func__);
return -EINVAL;
}
*val = sr_info->autocomp_active;
return 0;
}
static int omap_sr_autocomp_store(void *data, u64 val)
{
struct omap_sr *sr_info = data;
if (!sr_info) {
pr_warn("%s: omap_sr struct not found\n", __func__);
return -EINVAL;
}
/* Sanity check */
if (val > 1) {
pr_warn("%s: Invalid argument %lld\n", __func__, val);
return -EINVAL;
}
/* control enable/disable only if there is a delta in value */
if (sr_info->autocomp_active != val) {
if (!val)
sr_stop_vddautocomp(sr_info);
else
sr_start_vddautocomp(sr_info);
}
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
omap_sr_autocomp_store, "%llu\n");
static int omap_sr_probe(struct platform_device *pdev)
{
struct omap_sr *sr_info;
struct omap_sr_data *pdata = pdev->dev.platform_data;
struct dentry *nvalue_dir;
int i, ret = 0;
sr_info = devm_kzalloc(&pdev->dev, sizeof(struct omap_sr), GFP_KERNEL);
if (!sr_info)
return -ENOMEM;
sr_info->name = devm_kzalloc(&pdev->dev,
SMARTREFLEX_NAME_LEN, GFP_KERNEL);
if (!sr_info->name)
return -ENOMEM;
platform_set_drvdata(pdev, sr_info);
if (!pdata) {
dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
return -EINVAL;
}
sr_info->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sr_info->base))
return PTR_ERR(sr_info->base);
ret = platform_get_irq_optional(pdev, 0);
if (ret < 0 && ret != -ENXIO)
return dev_err_probe(&pdev->dev, ret, "failed to get IRQ resource\n");
if (ret > 0)
sr_info->irq = ret;
sr_info->fck = devm_clk_get(pdev->dev.parent, "fck");
if (IS_ERR(sr_info->fck))
return PTR_ERR(sr_info->fck);
clk_prepare(sr_info->fck);
pm_runtime_enable(&pdev->dev);
snprintf(sr_info->name, SMARTREFLEX_NAME_LEN, "%s", pdata->name);
sr_info->pdev = pdev;
sr_info->srid = pdev->id;
sr_info->voltdm = pdata->voltdm;
sr_info->nvalue_table = pdata->nvalue_table;
sr_info->nvalue_count = pdata->nvalue_count;
sr_info->senn_mod = pdata->senn_mod;
sr_info->senp_mod = pdata->senp_mod;
sr_info->err_weight = pdata->err_weight;
sr_info->err_maxlimit = pdata->err_maxlimit;
sr_info->accum_data = pdata->accum_data;
sr_info->senn_avgweight = pdata->senn_avgweight;
sr_info->senp_avgweight = pdata->senp_avgweight;
sr_info->autocomp_active = false;
sr_info->ip_type = pdata->ip_type;
sr_set_clk_length(sr_info);
list_add(&sr_info->node, &sr_list);
/*
* Call into late init to do initializations that require
* both sr driver and sr class driver to be initiallized.
*/
if (sr_class) {
ret = sr_late_init(sr_info);
if (ret) {
pr_warn("%s: Error in SR late init\n", __func__);
goto err_list_del;
}
}
dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
if (!sr_dbg_dir)
sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
sr_info->dbg_dir = debugfs_create_dir(sr_info->name, sr_dbg_dir);
debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, sr_info->dbg_dir,
sr_info, &pm_sr_fops);
debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
&sr_info->err_weight);
debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
&sr_info->err_maxlimit);
nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
if (sr_info->nvalue_count == 0 || !sr_info->nvalue_table) {
dev_warn(&pdev->dev, "%s: %s: No Voltage table for the corresponding vdd. Cannot create debugfs entries for n-values\n",
__func__, sr_info->name);
ret = -ENODATA;
goto err_debugfs;
}
for (i = 0; i < sr_info->nvalue_count; i++) {
char name[NVALUE_NAME_LEN + 1];
snprintf(name, sizeof(name), "volt_%lu",
sr_info->nvalue_table[i].volt_nominal);
debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
&(sr_info->nvalue_table[i].nvalue));
snprintf(name, sizeof(name), "errminlimit_%lu",
sr_info->nvalue_table[i].volt_nominal);
debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
&(sr_info->nvalue_table[i].errminlimit));
}
return 0;
err_debugfs:
debugfs_remove_recursive(sr_info->dbg_dir);
err_list_del:
pm_runtime_disable(&pdev->dev);
list_del(&sr_info->node);
clk_unprepare(sr_info->fck);
return ret;
}
static int omap_sr_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct omap_sr *sr_info = platform_get_drvdata(pdev);
if (sr_info->autocomp_active)
sr_stop_vddautocomp(sr_info);
debugfs_remove_recursive(sr_info->dbg_dir);
pm_runtime_disable(dev);
clk_unprepare(sr_info->fck);
list_del(&sr_info->node);
return 0;
}
static void omap_sr_shutdown(struct platform_device *pdev)
{
struct omap_sr *sr_info = platform_get_drvdata(pdev);
if (sr_info->autocomp_active)
sr_stop_vddautocomp(sr_info);
return;
}
static const struct of_device_id omap_sr_match[] = {
{ .compatible = "ti,omap3-smartreflex-core", },
{ .compatible = "ti,omap3-smartreflex-mpu-iva", },
{ .compatible = "ti,omap4-smartreflex-core", },
{ .compatible = "ti,omap4-smartreflex-mpu", },
{ .compatible = "ti,omap4-smartreflex-iva", },
{ },
};
MODULE_DEVICE_TABLE(of, omap_sr_match);
static struct platform_driver smartreflex_driver = {
.probe = omap_sr_probe,
.remove = omap_sr_remove,
.shutdown = omap_sr_shutdown,
.driver = {
.name = DRIVER_NAME,
.of_match_table = omap_sr_match,
},
};
static int __init sr_init(void)
{
int ret = 0;
ret = platform_driver_register(&smartreflex_driver);
if (ret) {
pr_err("%s: platform driver register failed for SR\n",
__func__);
return ret;
}
return 0;
}
late_initcall(sr_init);
static void __exit sr_exit(void)
{
platform_driver_unregister(&smartreflex_driver);
}
module_exit(sr_exit);
MODULE_DESCRIPTION("OMAP Smartreflex Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_AUTHOR("Texas Instruments Inc");
|
linux-master
|
drivers/soc/ti/smartreflex.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* sfr.c - driver for special function registers
*
* Copyright (C) 2019 Bootlin.
*
*/
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/random.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define SFR_SN0 0x4c
#define SFR_SN_SIZE 8
struct atmel_sfr_priv {
struct regmap *regmap;
};
static int atmel_sfr_read(void *context, unsigned int offset,
void *buf, size_t bytes)
{
struct atmel_sfr_priv *priv = context;
return regmap_bulk_read(priv->regmap, SFR_SN0 + offset,
buf, bytes / 4);
}
static struct nvmem_config atmel_sfr_nvmem_config = {
.name = "atmel-sfr",
.read_only = true,
.word_size = 4,
.stride = 4,
.size = SFR_SN_SIZE,
.reg_read = atmel_sfr_read,
};
static int atmel_sfr_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct nvmem_device *nvmem;
struct atmel_sfr_priv *priv;
u8 sn[SFR_SN_SIZE];
int ret;
priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->regmap = syscon_node_to_regmap(np);
if (IS_ERR(priv->regmap)) {
dev_err(dev, "cannot get parent's regmap\n");
return PTR_ERR(priv->regmap);
}
atmel_sfr_nvmem_config.dev = dev;
atmel_sfr_nvmem_config.priv = priv;
nvmem = devm_nvmem_register(dev, &atmel_sfr_nvmem_config);
if (IS_ERR(nvmem)) {
dev_err(dev, "error registering nvmem config\n");
return PTR_ERR(nvmem);
}
ret = atmel_sfr_read(priv, 0, sn, SFR_SN_SIZE);
if (ret == 0)
add_device_randomness(sn, SFR_SN_SIZE);
return ret;
}
static const struct of_device_id atmel_sfr_dt_ids[] = {
{
.compatible = "atmel,sama5d2-sfr",
}, {
.compatible = "atmel,sama5d4-sfr",
}, {
/* sentinel */
},
};
MODULE_DEVICE_TABLE(of, atmel_sfr_dt_ids);
static struct platform_driver atmel_sfr_driver = {
.probe = atmel_sfr_probe,
.driver = {
.name = "atmel-sfr",
.of_match_table = atmel_sfr_dt_ids,
},
};
module_platform_driver(atmel_sfr_driver);
MODULE_AUTHOR("Kamel Bouhara <[email protected]>");
MODULE_DESCRIPTION("Atmel SFR SN driver for SAMA5D2/4 SoC family");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/soc/atmel/sfr.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Atmel
*
* Alexandre Belloni <[email protected]
* Boris Brezillon <[email protected]
*/
#define pr_fmt(fmt) "AT91: " fmt
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include "soc.h"
#define AT91_DBGU_CIDR 0x40
#define AT91_DBGU_EXID 0x44
#define AT91_CHIPID_CIDR 0x00
#define AT91_CHIPID_EXID 0x04
#define AT91_CIDR_VERSION(x, m) ((x) & (m))
#define AT91_CIDR_VERSION_MASK GENMASK(4, 0)
#define AT91_CIDR_VERSION_MASK_SAMA7G5 GENMASK(3, 0)
#define AT91_CIDR_EXT BIT(31)
#define AT91_CIDR_MATCH_MASK GENMASK(30, 5)
#define AT91_CIDR_MASK_SAMA7G5 GENMASK(27, 5)
static const struct at91_soc socs[] __initconst = {
#ifdef CONFIG_SOC_AT91RM9200
AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"),
#endif
#ifdef CONFIG_SOC_AT91SAM9
AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL),
AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL),
AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL),
AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL),
AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL),
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH,
"at91sam9m11", "at91sam9g45"),
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH,
"at91sam9m10", "at91sam9g45"),
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH,
"at91sam9g46", "at91sam9g45"),
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH,
"at91sam9g45", "at91sam9g45"),
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH,
"at91sam9g15", "at91sam9x5"),
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH,
"at91sam9g35", "at91sam9x5"),
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH,
"at91sam9x35", "at91sam9x5"),
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH,
"at91sam9g25", "at91sam9x5"),
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH,
"at91sam9x25", "at91sam9x5"),
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH,
"at91sam9cn12", "at91sam9n12"),
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH,
"at91sam9n12", "at91sam9n12"),
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH,
"at91sam9cn11", "at91sam9n12"),
AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"),
AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"),
AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"),
#endif
#ifdef CONFIG_SOC_SAM9X60
AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
"sam9x60", "sam9x60"),
AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_D5M_EXID_MATCH,
"sam9x60 64MiB DDR2 SiP", "sam9x60"),
AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_D1G_EXID_MATCH,
"sam9x60 128MiB DDR2 SiP", "sam9x60"),
AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
"sam9x60 8MiB SDRAM SiP", "sam9x60"),
#endif
#ifdef CONFIG_SOC_SAMA5
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
"sama5d21", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH,
"sama5d22", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH,
"sama5d225c 16MiB SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH,
"sama5d23", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH,
"sama5d24", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH,
"sama5d24", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH,
"sama5d26", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH,
"sama5d27", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH,
"sama5d27", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH,
"sama5d27c 128MiB SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH,
"sama5d27c 64MiB SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH,
"sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH,
"sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH,
"sama5d28", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH,
"sama5d28", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH,
"sama5d28c 128MiB SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH,
"sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH,
"sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D29CN_EXID_MATCH,
"sama5d29", "sama5d2"),
AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH,
"sama5d31", "sama5d3"),
AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH,
"sama5d33", "sama5d3"),
AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH,
"sama5d34", "sama5d3"),
AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH,
"sama5d35", "sama5d3"),
AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH,
"sama5d36", "sama5d3"),
AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH,
"sama5d41", "sama5d4"),
AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH,
"sama5d42", "sama5d4"),
AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH,
"sama5d43", "sama5d4"),
AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH,
"sama5d44", "sama5d4"),
#endif
#ifdef CONFIG_SOC_SAMV7
AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH,
"same70q21", "same7"),
AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,
"same70q20", "same7"),
AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,
"same70q19", "same7"),
AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH,
"sams70q21", "sams7"),
AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH,
"sams70q20", "sams7"),
AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH,
"sams70q19", "sams7"),
AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH,
"samv71q21", "samv7"),
AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH,
"samv71q20", "samv7"),
AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH,
"samv71q19", "samv7"),
AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH,
"samv70q20", "samv7"),
AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
"samv70q19", "samv7"),
#endif
#ifdef CONFIG_SOC_SAMA7
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH,
"sama7g51", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH,
"sama7g52", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH,
"sama7g53", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,
"sama7g54", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D1G_EXID_MATCH,
"SAMA7G54 1Gb DDR3L SiP", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D2G_EXID_MATCH,
"SAMA7G54 2Gb DDR3L SiP", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D4G_EXID_MATCH,
"SAMA7G54 4Gb DDR3L SiP", "sama7g5"),
#endif
{ /* sentinel */ },
};
static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid)
{
struct device_node *np;
void __iomem *regs;
np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
if (!np)
np = of_find_compatible_node(NULL, NULL,
"atmel,at91sam9260-dbgu");
if (!np)
return -ENODEV;
regs = of_iomap(np, 0);
of_node_put(np);
if (!regs) {
pr_warn("Could not map DBGU iomem range");
return -ENXIO;
}
*cidr = readl(regs + AT91_DBGU_CIDR);
*exid = readl(regs + AT91_DBGU_EXID);
iounmap(regs);
return 0;
}
static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
{
struct device_node *np;
void __iomem *regs;
static const struct of_device_id chipids[] = {
{ .compatible = "atmel,sama5d2-chipid" },
{ .compatible = "microchip,sama7g5-chipid" },
{ },
};
np = of_find_matching_node(NULL, chipids);
if (!np)
return -ENODEV;
regs = of_iomap(np, 0);
of_node_put(np);
if (!regs) {
pr_warn("Could not map DBGU iomem range");
return -ENXIO;
}
*cidr = readl(regs + AT91_CHIPID_CIDR);
*exid = readl(regs + AT91_CHIPID_EXID);
iounmap(regs);
return 0;
}
struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
{
struct soc_device_attribute *soc_dev_attr;
const struct at91_soc *soc;
struct soc_device *soc_dev;
u32 cidr, exid;
int ret;
/*
* With SAMA5D2 and later SoCs, CIDR and EXID registers are no more
* in the dbgu device but in the chipid device whose purpose is only
* to expose these two registers.
*/
ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid);
if (ret)
ret = at91_get_cidr_exid_from_chipid(&cidr, &exid);
if (ret) {
if (ret == -ENODEV)
pr_warn("Could not find identification node");
return NULL;
}
for (soc = socs; soc->name; soc++) {
if (soc->cidr_match != (cidr & soc->cidr_mask))
continue;
if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
break;
}
if (!soc->name) {
pr_warn("Could not find matching SoC description\n");
return NULL;
}
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return NULL;
soc_dev_attr->family = soc->family;
soc_dev_attr->soc_id = soc->name;
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
AT91_CIDR_VERSION(cidr, soc->version_mask));
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr->revision);
kfree(soc_dev_attr);
pr_warn("Could not register SoC device\n");
return NULL;
}
if (soc->family)
pr_info("Detected SoC family: %s\n", soc->family);
pr_info("Detected SoC: %s, revision %X\n", soc->name,
AT91_CIDR_VERSION(cidr, soc->version_mask));
return soc_dev;
}
static const struct of_device_id at91_soc_allowed_list[] __initconst = {
{ .compatible = "atmel,at91rm9200", },
{ .compatible = "atmel,at91sam9", },
{ .compatible = "atmel,sama5", },
{ .compatible = "atmel,samv7", },
{ .compatible = "microchip,sama7g5", },
{ }
};
static int __init atmel_soc_device_init(void)
{
struct device_node *np = of_find_node_by_path("/");
if (!of_match_node(at91_soc_allowed_list, np))
return 0;
at91_soc_init(socs);
return 0;
}
subsys_initcall(atmel_soc_device_init);
|
linux-master
|
drivers/soc/atmel/soc.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices LTC2947 high precision power and energy monitor over SPI
*
* Copyright 2019 Analog Devices Inc.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include "ltc2947.h"
static const struct regmap_config ltc2947_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.read_flag_mask = BIT(0),
};
static int ltc2947_probe(struct spi_device *spi)
{
struct regmap *map;
map = devm_regmap_init_spi(spi, <c2947_regmap_config);
if (IS_ERR(map))
return PTR_ERR(map);
return ltc2947_core_probe(map, spi_get_device_id(spi)->name);
}
static const struct spi_device_id ltc2947_id[] = {
{"ltc2947", 0},
{}
};
MODULE_DEVICE_TABLE(spi, ltc2947_id);
static struct spi_driver ltc2947_driver = {
.driver = {
.name = "ltc2947",
.of_match_table = ltc2947_of_match,
.pm = pm_sleep_ptr(<c2947_pm_ops),
},
.probe = ltc2947_probe,
.id_table = ltc2947_id,
};
module_spi_driver(ltc2947_driver);
MODULE_AUTHOR("Nuno Sa <[email protected]>");
MODULE_DESCRIPTION("LTC2947 SPI power and energy monitor driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/ltc2947-spi.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* lm92 - Hardware monitoring driver
* Copyright (C) 2005-2008 Jean Delvare <[email protected]>
*
* Based on the lm90 driver, with some ideas taken from the lm_sensors
* lm92 driver as well.
*
* The LM92 is a sensor chip made by National Semiconductor. It reports
* its own temperature with a 0.0625 deg resolution and a 0.33 deg
* accuracy. Complete datasheet can be obtained from National's website
* at:
* http://www.national.com/pf/LM/LM92.html
*
* This driver also supports the MAX6635 sensor chip made by Maxim.
* This chip is compatible with the LM92, but has a lesser accuracy
* (1.0 deg). Complete datasheet can be obtained from Maxim's website
* at:
* http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3074
*
* Since the LM92 was the first chipset supported by this driver, most
* comments will refer to this chipset, but are actually general and
* concern all supported chipsets, unless mentioned otherwise.
*
* Support could easily be added for the National Semiconductor LM76
* and Maxim MAX6633 and MAX6634 chips, which are mostly compatible
* with the LM92.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/jiffies.h>
/*
* The LM92 and MAX6635 have 2 two-state pins for address selection,
* resulting in 4 possible addresses.
*/
static const unsigned short normal_i2c[] = { 0x48, 0x49, 0x4a, 0x4b,
I2C_CLIENT_END };
enum chips { lm92, max6635 };
/* The LM92 registers */
#define LM92_REG_CONFIG 0x01 /* 8-bit, RW */
#define LM92_REG_TEMP 0x00 /* 16-bit, RO */
#define LM92_REG_TEMP_HYST 0x02 /* 16-bit, RW */
#define LM92_REG_TEMP_CRIT 0x03 /* 16-bit, RW */
#define LM92_REG_TEMP_LOW 0x04 /* 16-bit, RW */
#define LM92_REG_TEMP_HIGH 0x05 /* 16-bit, RW */
#define LM92_REG_MAN_ID 0x07 /* 16-bit, RO, LM92 only */
/*
* The LM92 uses signed 13-bit values with LSB = 0.0625 degree Celsius,
* left-justified in 16-bit registers. No rounding is done, with such
* a resolution it's just not worth it. Note that the MAX6635 doesn't
* make use of the 4 lower bits for limits (i.e. effective resolution
* for limits is 1 degree Celsius).
*/
static inline int TEMP_FROM_REG(s16 reg)
{
return reg / 8 * 625 / 10;
}
static inline s16 TEMP_TO_REG(long val)
{
val = clamp_val(val, -60000, 160000);
return val * 10 / 625 * 8;
}
/* Alarm flags are stored in the 3 LSB of the temperature register */
static inline u8 ALARMS_FROM_REG(s16 reg)
{
return reg & 0x0007;
}
enum temp_index {
t_input,
t_crit,
t_min,
t_max,
t_hyst,
t_num_regs
};
static const u8 regs[t_num_regs] = {
[t_input] = LM92_REG_TEMP,
[t_crit] = LM92_REG_TEMP_CRIT,
[t_min] = LM92_REG_TEMP_LOW,
[t_max] = LM92_REG_TEMP_HIGH,
[t_hyst] = LM92_REG_TEMP_HYST,
};
/* Client data (each client gets its own) */
struct lm92_data {
struct i2c_client *client;
struct mutex update_lock;
bool valid; /* false until following fields are valid */
unsigned long last_updated; /* in jiffies */
/* registers values */
s16 temp[t_num_regs]; /* index with enum temp_index */
};
/*
* Sysfs attributes and callback functions
*/
static struct lm92_data *lm92_update_device(struct device *dev)
{
struct lm92_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int i;
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ) ||
!data->valid) {
dev_dbg(&client->dev, "Updating lm92 data\n");
for (i = 0; i < t_num_regs; i++) {
data->temp[i] =
i2c_smbus_read_word_swapped(client, regs[i]);
}
data->last_updated = jiffies;
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
static ssize_t temp_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct lm92_data *data = lm92_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[attr->index]));
}
static ssize_t temp_store(struct device *dev,
struct device_attribute *devattr, const char *buf,
size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct lm92_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr = attr->index;
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->temp[nr] = TEMP_TO_REG(val);
i2c_smbus_write_word_swapped(client, regs[nr], data->temp[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t temp_hyst_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct lm92_data *data = lm92_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[attr->index])
- TEMP_FROM_REG(data->temp[t_hyst]));
}
static ssize_t temp1_min_hyst_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct lm92_data *data = lm92_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[t_min])
+ TEMP_FROM_REG(data->temp[t_hyst]));
}
static ssize_t temp_hyst_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct lm92_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
val = clamp_val(val, -120000, 220000);
mutex_lock(&data->update_lock);
data->temp[t_hyst] =
TEMP_TO_REG(TEMP_FROM_REG(data->temp[attr->index]) - val);
i2c_smbus_write_word_swapped(client, LM92_REG_TEMP_HYST,
data->temp[t_hyst]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t alarms_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct lm92_data *data = lm92_update_device(dev);
return sprintf(buf, "%d\n", ALARMS_FROM_REG(data->temp[t_input]));
}
static ssize_t alarm_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int bitnr = to_sensor_dev_attr(attr)->index;
struct lm92_data *data = lm92_update_device(dev);
return sprintf(buf, "%d\n", (data->temp[t_input] >> bitnr) & 1);
}
static SENSOR_DEVICE_ATTR_RO(temp1_input, temp, t_input);
static SENSOR_DEVICE_ATTR_RW(temp1_crit, temp, t_crit);
static SENSOR_DEVICE_ATTR_RW(temp1_crit_hyst, temp_hyst, t_crit);
static SENSOR_DEVICE_ATTR_RW(temp1_min, temp, t_min);
static DEVICE_ATTR_RO(temp1_min_hyst);
static SENSOR_DEVICE_ATTR_RW(temp1_max, temp, t_max);
static SENSOR_DEVICE_ATTR_RO(temp1_max_hyst, temp_hyst, t_max);
static DEVICE_ATTR_RO(alarms);
static SENSOR_DEVICE_ATTR_RO(temp1_crit_alarm, alarm, 2);
static SENSOR_DEVICE_ATTR_RO(temp1_min_alarm, alarm, 0);
static SENSOR_DEVICE_ATTR_RO(temp1_max_alarm, alarm, 1);
/*
* Detection and registration
*/
static void lm92_init_client(struct i2c_client *client)
{
u8 config;
/* Start the conversions if needed */
config = i2c_smbus_read_byte_data(client, LM92_REG_CONFIG);
if (config & 0x01)
i2c_smbus_write_byte_data(client, LM92_REG_CONFIG,
config & 0xFE);
}
static struct attribute *lm92_attrs[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_crit.dev_attr.attr,
&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
&sensor_dev_attr_temp1_min.dev_attr.attr,
&dev_attr_temp1_min_hyst.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp1_max_hyst.dev_attr.attr,
&dev_attr_alarms.attr,
&sensor_dev_attr_temp1_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
NULL
};
ATTRIBUTE_GROUPS(lm92);
/* Return 0 if detection is successful, -ENODEV otherwise */
static int lm92_detect(struct i2c_client *new_client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = new_client->adapter;
u8 config;
u16 man_id;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA
| I2C_FUNC_SMBUS_WORD_DATA))
return -ENODEV;
config = i2c_smbus_read_byte_data(new_client, LM92_REG_CONFIG);
man_id = i2c_smbus_read_word_data(new_client, LM92_REG_MAN_ID);
if ((config & 0xe0) == 0x00 && man_id == 0x0180)
pr_info("lm92: Found National Semiconductor LM92 chip\n");
else
return -ENODEV;
strscpy(info->type, "lm92", I2C_NAME_SIZE);
return 0;
}
static int lm92_probe(struct i2c_client *new_client)
{
struct device *hwmon_dev;
struct lm92_data *data;
data = devm_kzalloc(&new_client->dev, sizeof(struct lm92_data),
GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = new_client;
mutex_init(&data->update_lock);
/* Initialize the chipset */
lm92_init_client(new_client);
hwmon_dev = devm_hwmon_device_register_with_groups(&new_client->dev,
new_client->name,
data, lm92_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
/*
* Module and driver stuff
*/
static const struct i2c_device_id lm92_id[] = {
{ "lm92", lm92 },
{ "max6635", max6635 },
{ }
};
MODULE_DEVICE_TABLE(i2c, lm92_id);
static struct i2c_driver lm92_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "lm92",
},
.probe = lm92_probe,
.id_table = lm92_id,
.detect = lm92_detect,
.address_list = normal_i2c,
};
module_i2c_driver(lm92_driver);
MODULE_AUTHOR("Jean Delvare <[email protected]>");
MODULE_DESCRIPTION("LM92/MAX6635 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/lm92.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* w83627ehf - Driver for the hardware monitoring functionality of
* the Winbond W83627EHF Super-I/O chip
* Copyright (C) 2005-2012 Jean Delvare <[email protected]>
* Copyright (C) 2006 Yuan Mu (Winbond),
* Rudolf Marek <[email protected]>
* David Hubbard <[email protected]>
* Daniel J Blueman <[email protected]>
* Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
*
* Shamelessly ripped from the w83627hf driver
* Copyright (C) 2003 Mark Studebaker
*
* Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
* in testing and debugging this driver.
*
* This driver also supports the W83627EHG, which is the lead-free
* version of the W83627EHF.
*
* Supports the following chips:
*
* Chip #vin #fan #pwm #temp chip IDs man ID
* w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
* 0x8860 0xa1
* w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
* w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
* w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
* w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
* w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/platform_device.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/hwmon-vid.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/acpi.h>
#include <linux/io.h>
#include "lm75.h"
enum kinds {
w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
w83667hg, w83667hg_b,
};
/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
static const char * const w83627ehf_device_names[] = {
"w83627ehf",
"w83627dhg",
"w83627dhg",
"w83627uhg",
"w83667hg",
"w83667hg",
};
static unsigned short force_id;
module_param(force_id, ushort, 0);
MODULE_PARM_DESC(force_id, "Override the detected device ID");
#define DRVNAME "w83627ehf"
/*
* Super-I/O constants and functions
*/
#define W83627EHF_LD_HWM 0x0b
#define W83667HG_LD_VID 0x0d
#define SIO_REG_LDSEL 0x07 /* Logical device select */
#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
#define SIO_REG_ENABLE 0x30 /* Logical device enable */
#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
#define SIO_REG_VID_CTRL 0xF0 /* VID control */
#define SIO_REG_VID_DATA 0xF1 /* VID data */
#define SIO_W83627EHF_ID 0x8850
#define SIO_W83627EHG_ID 0x8860
#define SIO_W83627DHG_ID 0xa020
#define SIO_W83627DHG_P_ID 0xb070
#define SIO_W83627UHG_ID 0xa230
#define SIO_W83667HG_ID 0xa510
#define SIO_W83667HG_B_ID 0xb350
#define SIO_ID_MASK 0xFFF0
static inline void
superio_outb(int ioreg, int reg, int val)
{
outb(reg, ioreg);
outb(val, ioreg + 1);
}
static inline int
superio_inb(int ioreg, int reg)
{
outb(reg, ioreg);
return inb(ioreg + 1);
}
static inline void
superio_select(int ioreg, int ld)
{
outb(SIO_REG_LDSEL, ioreg);
outb(ld, ioreg + 1);
}
static inline int
superio_enter(int ioreg)
{
if (!request_muxed_region(ioreg, 2, DRVNAME))
return -EBUSY;
outb(0x87, ioreg);
outb(0x87, ioreg);
return 0;
}
static inline void
superio_exit(int ioreg)
{
outb(0xaa, ioreg);
outb(0x02, ioreg);
outb(0x02, ioreg + 1);
release_region(ioreg, 2);
}
/*
* ISA constants
*/
#define IOREGION_ALIGNMENT (~7)
#define IOREGION_OFFSET 5
#define IOREGION_LENGTH 2
#define ADDR_REG_OFFSET 0
#define DATA_REG_OFFSET 1
#define W83627EHF_REG_BANK 0x4E
#define W83627EHF_REG_CONFIG 0x40
/*
* Not currently used:
* REG_MAN_ID has the value 0x5ca3 for all supported chips.
* REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
* REG_MAN_ID is at port 0x4f
* REG_CHIP_ID is at port 0x58
*/
static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
(0x554 + (((nr) - 7) * 2)))
#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
(0x555 + (((nr) - 7) * 2)))
#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
(0x550 + (nr) - 7))
static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
/* Fan clock dividers are spread over the following five registers */
#define W83627EHF_REG_FANDIV1 0x47
#define W83627EHF_REG_FANDIV2 0x4B
#define W83627EHF_REG_VBAT 0x5D
#define W83627EHF_REG_DIODE 0x59
#define W83627EHF_REG_SMI_OVT 0x4C
#define W83627EHF_REG_ALARM1 0x459
#define W83627EHF_REG_ALARM2 0x45A
#define W83627EHF_REG_ALARM3 0x45B
#define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
#define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
/* SmartFan registers */
#define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
#define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
/* DC or PWM output fan configuration */
static const u8 W83627EHF_REG_PWM_ENABLE[] = {
0x04, /* SYS FAN0 output mode and PWM mode */
0x04, /* CPU FAN0 output mode and PWM mode */
0x12, /* AUX FAN mode */
0x62, /* CPU FAN1 mode */
};
static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
/* FAN Duty Cycle, be used to control */
static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
/* Advanced Fan control, some values are common for all fans */
static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
= { 0xff, 0x67, 0xff, 0x69 };
static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
= { 0xff, 0x68, 0xff, 0x6a };
static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
= { 0x68, 0x6a, 0x6c };
static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
static const char *const w83667hg_b_temp_label[] = {
"SYSTIN",
"CPUTIN",
"AUXTIN",
"AMDTSI",
"PECI Agent 1",
"PECI Agent 2",
"PECI Agent 3",
"PECI Agent 4"
};
#define NUM_REG_TEMP ARRAY_SIZE(W83627EHF_REG_TEMP)
static int is_word_sized(u16 reg)
{
return ((((reg & 0xff00) == 0x100
|| (reg & 0xff00) == 0x200)
&& ((reg & 0x00ff) == 0x50
|| (reg & 0x00ff) == 0x53
|| (reg & 0x00ff) == 0x55))
|| (reg & 0xfff0) == 0x630
|| reg == 0x640 || reg == 0x642
|| ((reg & 0xfff0) == 0x650
&& (reg & 0x000f) >= 0x06)
|| reg == 0x73 || reg == 0x75 || reg == 0x77
);
}
/*
* Conversions
*/
/* 1 is PWM mode, output in ms */
static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
{
return mode ? 100 * reg : 400 * reg;
}
static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
{
return clamp_val((mode ? (msec + 50) / 100 : (msec + 200) / 400),
1, 255);
}
static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
{
if (reg == 0 || reg == 255)
return 0;
return 1350000U / (reg << divreg);
}
static inline unsigned int
div_from_reg(u8 reg)
{
return 1 << reg;
}
/*
* Some of the voltage inputs have internal scaling, the tables below
* contain 8 (the ADC LSB in mV) * scaling factor * 100
*/
static const u16 scale_in_common[10] = {
800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
};
static const u16 scale_in_w83627uhg[9] = {
800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
};
static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
{
return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
}
static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
{
return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
}
/*
* Data structures and manipulation thereof
*/
struct w83627ehf_data {
int addr; /* IO base of hw monitor block */
const char *name;
struct mutex lock;
u16 reg_temp[NUM_REG_TEMP];
u16 reg_temp_over[NUM_REG_TEMP];
u16 reg_temp_hyst[NUM_REG_TEMP];
u16 reg_temp_config[NUM_REG_TEMP];
u8 temp_src[NUM_REG_TEMP];
const char * const *temp_label;
const u16 *REG_FAN_MAX_OUTPUT;
const u16 *REG_FAN_STEP_OUTPUT;
const u16 *scale_in;
struct mutex update_lock;
bool valid; /* true if following fields are valid */
unsigned long last_updated; /* In jiffies */
/* Register values */
u8 bank; /* current register bank */
u8 in_num; /* number of in inputs we have */
u8 in[10]; /* Register value */
u8 in_max[10]; /* Register value */
u8 in_min[10]; /* Register value */
unsigned int rpm[5];
u16 fan_min[5];
u8 fan_div[5];
u8 has_fan; /* some fan inputs can be disabled */
u8 has_fan_min; /* some fans don't have min register */
u8 temp_type[3];
s8 temp_offset[3];
s16 temp[9];
s16 temp_max[9];
s16 temp_max_hyst[9];
u32 alarms;
u8 caseopen;
u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
u8 pwm_enable[4]; /* 1->manual
* 2->thermal cruise mode (also called SmartFan I)
* 3->fan speed cruise mode
* 4->variable thermal cruise (also called
* SmartFan III)
* 5->enhanced variable thermal cruise (also called
* SmartFan IV)
*/
u8 pwm_enable_orig[4]; /* original value of pwm_enable */
u8 pwm_num; /* number of pwm */
u8 pwm[4];
u8 target_temp[4];
u8 tolerance[4];
u8 fan_start_output[4]; /* minimum fan speed when spinning up */
u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
u8 fan_stop_time[4]; /* time at minimum before disabling fan */
u8 fan_max_output[4]; /* maximum fan speed */
u8 fan_step_output[4]; /* rate of change output value */
u8 vid;
u8 vrm;
u16 have_temp;
u16 have_temp_offset;
u8 in6_skip:1;
u8 temp3_val_only:1;
u8 have_vid:1;
/* Remember extra register values over suspend/resume */
u8 vbat;
u8 fandiv1;
u8 fandiv2;
};
struct w83627ehf_sio_data {
int sioreg;
enum kinds kind;
};
/*
* On older chips, only registers 0x50-0x5f are banked.
* On more recent chips, all registers are banked.
* Assume that is the case and set the bank number for each access.
* Cache the bank number so it only needs to be set if it changes.
*/
static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
{
u8 bank = reg >> 8;
if (data->bank != bank) {
outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
outb_p(bank, data->addr + DATA_REG_OFFSET);
data->bank = bank;
}
}
static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
{
int res, word_sized = is_word_sized(reg);
mutex_lock(&data->lock);
w83627ehf_set_bank(data, reg);
outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
res = inb_p(data->addr + DATA_REG_OFFSET);
if (word_sized) {
outb_p((reg & 0xff) + 1,
data->addr + ADDR_REG_OFFSET);
res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
}
mutex_unlock(&data->lock);
return res;
}
static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
u16 value)
{
int word_sized = is_word_sized(reg);
mutex_lock(&data->lock);
w83627ehf_set_bank(data, reg);
outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
if (word_sized) {
outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
outb_p((reg & 0xff) + 1,
data->addr + ADDR_REG_OFFSET);
}
outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
mutex_unlock(&data->lock);
return 0;
}
/* We left-align 8-bit temperature values to make the code simpler */
static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
{
u16 res;
res = w83627ehf_read_value(data, reg);
if (!is_word_sized(reg))
res <<= 8;
return res;
}
static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
u16 value)
{
if (!is_word_sized(reg))
value >>= 8;
return w83627ehf_write_value(data, reg, value);
}
/* This function assumes that the caller holds data->update_lock */
static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
{
u8 reg;
switch (nr) {
case 0:
reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
| ((data->fan_div[0] & 0x03) << 4);
/* fan5 input control bit is write only, compute the value */
reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
| ((data->fan_div[0] & 0x04) << 3);
w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
break;
case 1:
reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
| ((data->fan_div[1] & 0x03) << 6);
/* fan5 input control bit is write only, compute the value */
reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
| ((data->fan_div[1] & 0x04) << 4);
w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
break;
case 2:
reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
| ((data->fan_div[2] & 0x03) << 6);
w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
| ((data->fan_div[2] & 0x04) << 5);
w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
break;
case 3:
reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
| (data->fan_div[3] & 0x03);
w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
| ((data->fan_div[3] & 0x04) << 5);
w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
break;
case 4:
reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
| ((data->fan_div[4] & 0x03) << 2)
| ((data->fan_div[4] & 0x04) << 5);
w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
break;
}
}
static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
{
int i;
i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
data->fan_div[0] = (i >> 4) & 0x03;
data->fan_div[1] = (i >> 6) & 0x03;
i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
data->fan_div[2] = (i >> 6) & 0x03;
i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
data->fan_div[0] |= (i >> 3) & 0x04;
data->fan_div[1] |= (i >> 4) & 0x04;
data->fan_div[2] |= (i >> 5) & 0x04;
if (data->has_fan & ((1 << 3) | (1 << 4))) {
i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
data->fan_div[3] = i & 0x03;
data->fan_div[4] = ((i >> 2) & 0x03)
| ((i >> 5) & 0x04);
}
if (data->has_fan & (1 << 3)) {
i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
data->fan_div[3] |= (i >> 5) & 0x04;
}
}
static void w83627ehf_update_pwm(struct w83627ehf_data *data)
{
int i;
int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
for (i = 0; i < data->pwm_num; i++) {
if (!(data->has_fan & (1 << i)))
continue;
/* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
if (i != 1) {
pwmcfg = w83627ehf_read_value(data,
W83627EHF_REG_PWM_ENABLE[i]);
tolerance = w83627ehf_read_value(data,
W83627EHF_REG_TOLERANCE[i]);
}
data->pwm_mode[i] =
((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
& 3) + 1;
data->pwm[i] = w83627ehf_read_value(data, W83627EHF_REG_PWM[i]);
data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
}
}
static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
{
struct w83627ehf_data *data = dev_get_drvdata(dev);
int i;
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ + HZ/2)
|| !data->valid) {
/* Fan clock dividers */
w83627ehf_update_fan_div(data);
/* Measured voltages and limits */
for (i = 0; i < data->in_num; i++) {
if ((i == 6) && data->in6_skip)
continue;
data->in[i] = w83627ehf_read_value(data,
W83627EHF_REG_IN(i));
data->in_min[i] = w83627ehf_read_value(data,
W83627EHF_REG_IN_MIN(i));
data->in_max[i] = w83627ehf_read_value(data,
W83627EHF_REG_IN_MAX(i));
}
/* Measured fan speeds and limits */
for (i = 0; i < 5; i++) {
u16 reg;
if (!(data->has_fan & (1 << i)))
continue;
reg = w83627ehf_read_value(data, W83627EHF_REG_FAN[i]);
data->rpm[i] = fan_from_reg8(reg, data->fan_div[i]);
if (data->has_fan_min & (1 << i))
data->fan_min[i] = w83627ehf_read_value(data,
W83627EHF_REG_FAN_MIN[i]);
/*
* If we failed to measure the fan speed and clock
* divider can be increased, let's try that for next
* time
*/
if (reg >= 0xff && data->fan_div[i] < 0x07) {
dev_dbg(dev,
"Increasing fan%d clock divider from %u to %u\n",
i + 1, div_from_reg(data->fan_div[i]),
div_from_reg(data->fan_div[i] + 1));
data->fan_div[i]++;
w83627ehf_write_fan_div(data, i);
/* Preserve min limit if possible */
if ((data->has_fan_min & (1 << i))
&& data->fan_min[i] >= 2
&& data->fan_min[i] != 255)
w83627ehf_write_value(data,
W83627EHF_REG_FAN_MIN[i],
(data->fan_min[i] /= 2));
}
}
w83627ehf_update_pwm(data);
for (i = 0; i < data->pwm_num; i++) {
if (!(data->has_fan & (1 << i)))
continue;
data->fan_start_output[i] =
w83627ehf_read_value(data,
W83627EHF_REG_FAN_START_OUTPUT[i]);
data->fan_stop_output[i] =
w83627ehf_read_value(data,
W83627EHF_REG_FAN_STOP_OUTPUT[i]);
data->fan_stop_time[i] =
w83627ehf_read_value(data,
W83627EHF_REG_FAN_STOP_TIME[i]);
if (data->REG_FAN_MAX_OUTPUT &&
data->REG_FAN_MAX_OUTPUT[i] != 0xff)
data->fan_max_output[i] =
w83627ehf_read_value(data,
data->REG_FAN_MAX_OUTPUT[i]);
if (data->REG_FAN_STEP_OUTPUT &&
data->REG_FAN_STEP_OUTPUT[i] != 0xff)
data->fan_step_output[i] =
w83627ehf_read_value(data,
data->REG_FAN_STEP_OUTPUT[i]);
data->target_temp[i] =
w83627ehf_read_value(data,
W83627EHF_REG_TARGET[i]) &
(data->pwm_mode[i] == 1 ? 0x7f : 0xff);
}
/* Measured temperatures and limits */
for (i = 0; i < NUM_REG_TEMP; i++) {
if (!(data->have_temp & (1 << i)))
continue;
data->temp[i] = w83627ehf_read_temp(data,
data->reg_temp[i]);
if (data->reg_temp_over[i])
data->temp_max[i]
= w83627ehf_read_temp(data,
data->reg_temp_over[i]);
if (data->reg_temp_hyst[i])
data->temp_max_hyst[i]
= w83627ehf_read_temp(data,
data->reg_temp_hyst[i]);
if (i > 2)
continue;
if (data->have_temp_offset & (1 << i))
data->temp_offset[i]
= w83627ehf_read_value(data,
W83627EHF_REG_TEMP_OFFSET[i]);
}
data->alarms = w83627ehf_read_value(data,
W83627EHF_REG_ALARM1) |
(w83627ehf_read_value(data,
W83627EHF_REG_ALARM2) << 8) |
(w83627ehf_read_value(data,
W83627EHF_REG_ALARM3) << 16);
data->caseopen = w83627ehf_read_value(data,
W83627EHF_REG_CASEOPEN_DET);
data->last_updated = jiffies;
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
#define store_in_reg(REG, reg) \
static int \
store_in_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
long val) \
{ \
if (val < 0) \
return -EINVAL; \
mutex_lock(&data->update_lock); \
data->in_##reg[channel] = in_to_reg(val, channel, data->scale_in); \
w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(channel), \
data->in_##reg[channel]); \
mutex_unlock(&data->update_lock); \
return 0; \
}
store_in_reg(MIN, min)
store_in_reg(MAX, max)
static int
store_fan_min(struct device *dev, struct w83627ehf_data *data, int channel,
long val)
{
unsigned int reg;
u8 new_div;
if (val < 0)
return -EINVAL;
mutex_lock(&data->update_lock);
if (!val) {
/* No min limit, alarm disabled */
data->fan_min[channel] = 255;
new_div = data->fan_div[channel]; /* No change */
dev_info(dev, "fan%u low limit and alarm disabled\n",
channel + 1);
} else if ((reg = 1350000U / val) >= 128 * 255) {
/*
* Speed below this value cannot possibly be represented,
* even with the highest divider (128)
*/
data->fan_min[channel] = 254;
new_div = 7; /* 128 == (1 << 7) */
dev_warn(dev,
"fan%u low limit %lu below minimum %u, set to minimum\n",
channel + 1, val, fan_from_reg8(254, 7));
} else if (!reg) {
/*
* Speed above this value cannot possibly be represented,
* even with the lowest divider (1)
*/
data->fan_min[channel] = 1;
new_div = 0; /* 1 == (1 << 0) */
dev_warn(dev,
"fan%u low limit %lu above maximum %u, set to maximum\n",
channel + 1, val, fan_from_reg8(1, 0));
} else {
/*
* Automatically pick the best divider, i.e. the one such
* that the min limit will correspond to a register value
* in the 96..192 range
*/
new_div = 0;
while (reg > 192 && new_div < 7) {
reg >>= 1;
new_div++;
}
data->fan_min[channel] = reg;
}
/*
* Write both the fan clock divider (if it changed) and the new
* fan min (unconditionally)
*/
if (new_div != data->fan_div[channel]) {
dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
channel + 1, div_from_reg(data->fan_div[channel]),
div_from_reg(new_div));
data->fan_div[channel] = new_div;
w83627ehf_write_fan_div(data, channel);
/* Give the chip time to sample a new speed value */
data->last_updated = jiffies;
}
w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[channel],
data->fan_min[channel]);
mutex_unlock(&data->update_lock);
return 0;
}
#define store_temp_reg(addr, reg) \
static int \
store_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
long val) \
{ \
mutex_lock(&data->update_lock); \
data->reg[channel] = LM75_TEMP_TO_REG(val); \
w83627ehf_write_temp(data, data->addr[channel], data->reg[channel]); \
mutex_unlock(&data->update_lock); \
return 0; \
}
store_temp_reg(reg_temp_over, temp_max);
store_temp_reg(reg_temp_hyst, temp_max_hyst);
static int
store_temp_offset(struct device *dev, struct w83627ehf_data *data, int channel,
long val)
{
val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
mutex_lock(&data->update_lock);
data->temp_offset[channel] = val;
w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[channel], val);
mutex_unlock(&data->update_lock);
return 0;
}
static int
store_pwm_mode(struct device *dev, struct w83627ehf_data *data, int channel,
long val)
{
u16 reg;
if (val < 0 || val > 1)
return -EINVAL;
mutex_lock(&data->update_lock);
reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[channel]);
data->pwm_mode[channel] = val;
reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[channel]);
if (!val)
reg |= 1 << W83627EHF_PWM_MODE_SHIFT[channel];
w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel], reg);
mutex_unlock(&data->update_lock);
return 0;
}
static int
store_pwm(struct device *dev, struct w83627ehf_data *data, int channel,
long val)
{
val = clamp_val(val, 0, 255);
mutex_lock(&data->update_lock);
data->pwm[channel] = val;
w83627ehf_write_value(data, W83627EHF_REG_PWM[channel], val);
mutex_unlock(&data->update_lock);
return 0;
}
static int
store_pwm_enable(struct device *dev, struct w83627ehf_data *data, int channel,
long val)
{
u16 reg;
if (!val || val < 0 ||
(val > 4 && val != data->pwm_enable_orig[channel]))
return -EINVAL;
mutex_lock(&data->update_lock);
data->pwm_enable[channel] = val;
reg = w83627ehf_read_value(data,
W83627EHF_REG_PWM_ENABLE[channel]);
reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[channel]);
reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[channel];
w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel],
reg);
mutex_unlock(&data->update_lock);
return 0;
}
#define show_tol_temp(reg) \
static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
char *buf) \
{ \
struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
struct sensor_device_attribute *sensor_attr = \
to_sensor_dev_attr(attr); \
int nr = sensor_attr->index; \
return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
}
show_tol_temp(tolerance)
show_tol_temp(target_temp)
static ssize_t
store_target_temp(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct w83627ehf_data *data = dev_get_drvdata(dev);
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err < 0)
return err;
val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
mutex_lock(&data->update_lock);
data->target_temp[nr] = val;
w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t
store_tolerance(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct w83627ehf_data *data = dev_get_drvdata(dev);
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
u16 reg;
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err < 0)
return err;
/* Limit the temp to 0C - 15C */
val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
mutex_lock(&data->update_lock);
reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
if (nr == 1)
reg = (reg & 0x0f) | (val << 4);
else
reg = (reg & 0xf0) | val;
w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
data->tolerance[nr] = val;
mutex_unlock(&data->update_lock);
return count;
}
static SENSOR_DEVICE_ATTR(pwm1_target, 0644, show_target_temp,
store_target_temp, 0);
static SENSOR_DEVICE_ATTR(pwm2_target, 0644, show_target_temp,
store_target_temp, 1);
static SENSOR_DEVICE_ATTR(pwm3_target, 0644, show_target_temp,
store_target_temp, 2);
static SENSOR_DEVICE_ATTR(pwm4_target, 0644, show_target_temp,
store_target_temp, 3);
static SENSOR_DEVICE_ATTR(pwm1_tolerance, 0644, show_tolerance,
store_tolerance, 0);
static SENSOR_DEVICE_ATTR(pwm2_tolerance, 0644, show_tolerance,
store_tolerance, 1);
static SENSOR_DEVICE_ATTR(pwm3_tolerance, 0644, show_tolerance,
store_tolerance, 2);
static SENSOR_DEVICE_ATTR(pwm4_tolerance, 0644, show_tolerance,
store_tolerance, 3);
/* Smart Fan registers */
#define fan_functions(reg, REG) \
static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
char *buf) \
{ \
struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
struct sensor_device_attribute *sensor_attr = \
to_sensor_dev_attr(attr); \
int nr = sensor_attr->index; \
return sprintf(buf, "%d\n", data->reg[nr]); \
} \
static ssize_t \
store_##reg(struct device *dev, struct device_attribute *attr, \
const char *buf, size_t count) \
{ \
struct w83627ehf_data *data = dev_get_drvdata(dev); \
struct sensor_device_attribute *sensor_attr = \
to_sensor_dev_attr(attr); \
int nr = sensor_attr->index; \
unsigned long val; \
int err; \
err = kstrtoul(buf, 10, &val); \
if (err < 0) \
return err; \
val = clamp_val(val, 1, 255); \
mutex_lock(&data->update_lock); \
data->reg[nr] = val; \
w83627ehf_write_value(data, REG[nr], val); \
mutex_unlock(&data->update_lock); \
return count; \
}
fan_functions(fan_start_output, W83627EHF_REG_FAN_START_OUTPUT)
fan_functions(fan_stop_output, W83627EHF_REG_FAN_STOP_OUTPUT)
fan_functions(fan_max_output, data->REG_FAN_MAX_OUTPUT)
fan_functions(fan_step_output, data->REG_FAN_STEP_OUTPUT)
#define fan_time_functions(reg, REG) \
static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
char *buf) \
{ \
struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
struct sensor_device_attribute *sensor_attr = \
to_sensor_dev_attr(attr); \
int nr = sensor_attr->index; \
return sprintf(buf, "%d\n", \
step_time_from_reg(data->reg[nr], \
data->pwm_mode[nr])); \
} \
\
static ssize_t \
store_##reg(struct device *dev, struct device_attribute *attr, \
const char *buf, size_t count) \
{ \
struct w83627ehf_data *data = dev_get_drvdata(dev); \
struct sensor_device_attribute *sensor_attr = \
to_sensor_dev_attr(attr); \
int nr = sensor_attr->index; \
unsigned long val; \
int err; \
err = kstrtoul(buf, 10, &val); \
if (err < 0) \
return err; \
val = step_time_to_reg(val, data->pwm_mode[nr]); \
mutex_lock(&data->update_lock); \
data->reg[nr] = val; \
w83627ehf_write_value(data, REG[nr], val); \
mutex_unlock(&data->update_lock); \
return count; \
} \
fan_time_functions(fan_stop_time, W83627EHF_REG_FAN_STOP_TIME)
static SENSOR_DEVICE_ATTR(pwm4_stop_time, 0644, show_fan_stop_time,
store_fan_stop_time, 3);
static SENSOR_DEVICE_ATTR(pwm4_start_output, 0644, show_fan_start_output,
store_fan_start_output, 3);
static SENSOR_DEVICE_ATTR(pwm4_stop_output, 0644, show_fan_stop_output,
store_fan_stop_output, 3);
static SENSOR_DEVICE_ATTR(pwm4_max_output, 0644, show_fan_max_output,
store_fan_max_output, 3);
static SENSOR_DEVICE_ATTR(pwm4_step_output, 0644, show_fan_step_output,
store_fan_step_output, 3);
static SENSOR_DEVICE_ATTR(pwm3_stop_time, 0644, show_fan_stop_time,
store_fan_stop_time, 2);
static SENSOR_DEVICE_ATTR(pwm3_start_output, 0644, show_fan_start_output,
store_fan_start_output, 2);
static SENSOR_DEVICE_ATTR(pwm3_stop_output, 0644, show_fan_stop_output,
store_fan_stop_output, 2);
static SENSOR_DEVICE_ATTR(pwm1_stop_time, 0644, show_fan_stop_time,
store_fan_stop_time, 0);
static SENSOR_DEVICE_ATTR(pwm2_stop_time, 0644, show_fan_stop_time,
store_fan_stop_time, 1);
static SENSOR_DEVICE_ATTR(pwm1_start_output, 0644, show_fan_start_output,
store_fan_start_output, 0);
static SENSOR_DEVICE_ATTR(pwm2_start_output, 0644, show_fan_start_output,
store_fan_start_output, 1);
static SENSOR_DEVICE_ATTR(pwm1_stop_output, 0644, show_fan_stop_output,
store_fan_stop_output, 0);
static SENSOR_DEVICE_ATTR(pwm2_stop_output, 0644, show_fan_stop_output,
store_fan_stop_output, 1);
/*
* pwm1 and pwm3 don't support max and step settings on all chips.
* Need to check support while generating/removing attribute files.
*/
static SENSOR_DEVICE_ATTR(pwm1_max_output, 0644, show_fan_max_output,
store_fan_max_output, 0);
static SENSOR_DEVICE_ATTR(pwm1_step_output, 0644, show_fan_step_output,
store_fan_step_output, 0);
static SENSOR_DEVICE_ATTR(pwm2_max_output, 0644, show_fan_max_output,
store_fan_max_output, 1);
static SENSOR_DEVICE_ATTR(pwm2_step_output, 0644, show_fan_step_output,
store_fan_step_output, 1);
static SENSOR_DEVICE_ATTR(pwm3_max_output, 0644, show_fan_max_output,
store_fan_max_output, 2);
static SENSOR_DEVICE_ATTR(pwm3_step_output, 0644, show_fan_step_output,
store_fan_step_output, 2);
static ssize_t
cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct w83627ehf_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
}
static DEVICE_ATTR_RO(cpu0_vid);
/* Case open detection */
static int
clear_caseopen(struct device *dev, struct w83627ehf_data *data, int channel,
long val)
{
const u16 mask = 0x80;
u16 reg;
if (val != 0 || channel != 0)
return -EINVAL;
mutex_lock(&data->update_lock);
reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
data->valid = false; /* Force cache refresh */
mutex_unlock(&data->update_lock);
return 0;
}
static umode_t w83627ehf_attrs_visible(struct kobject *kobj,
struct attribute *a, int n)
{
struct device *dev = kobj_to_dev(kobj);
struct w83627ehf_data *data = dev_get_drvdata(dev);
struct device_attribute *devattr;
struct sensor_device_attribute *sda;
devattr = container_of(a, struct device_attribute, attr);
/* Not sensor */
if (devattr->show == cpu0_vid_show && data->have_vid)
return a->mode;
sda = (struct sensor_device_attribute *)devattr;
if (sda->index < 2 &&
(devattr->show == show_fan_stop_time ||
devattr->show == show_fan_start_output ||
devattr->show == show_fan_stop_output))
return a->mode;
if (sda->index < 3 &&
(devattr->show == show_fan_max_output ||
devattr->show == show_fan_step_output) &&
data->REG_FAN_STEP_OUTPUT &&
data->REG_FAN_STEP_OUTPUT[sda->index] != 0xff)
return a->mode;
/* if fan3 and fan4 are enabled create the files for them */
if (sda->index == 2 &&
(data->has_fan & (1 << 2)) && data->pwm_num >= 3 &&
(devattr->show == show_fan_stop_time ||
devattr->show == show_fan_start_output ||
devattr->show == show_fan_stop_output))
return a->mode;
if (sda->index == 3 &&
(data->has_fan & (1 << 3)) && data->pwm_num >= 4 &&
(devattr->show == show_fan_stop_time ||
devattr->show == show_fan_start_output ||
devattr->show == show_fan_stop_output ||
devattr->show == show_fan_max_output ||
devattr->show == show_fan_step_output))
return a->mode;
if ((devattr->show == show_target_temp ||
devattr->show == show_tolerance) &&
(data->has_fan & (1 << sda->index)) &&
sda->index < data->pwm_num)
return a->mode;
return 0;
}
/* These groups handle non-standard attributes used in this device */
static struct attribute *w83627ehf_attrs[] = {
&sensor_dev_attr_pwm1_stop_time.dev_attr.attr,
&sensor_dev_attr_pwm1_start_output.dev_attr.attr,
&sensor_dev_attr_pwm1_stop_output.dev_attr.attr,
&sensor_dev_attr_pwm1_max_output.dev_attr.attr,
&sensor_dev_attr_pwm1_step_output.dev_attr.attr,
&sensor_dev_attr_pwm1_target.dev_attr.attr,
&sensor_dev_attr_pwm1_tolerance.dev_attr.attr,
&sensor_dev_attr_pwm2_stop_time.dev_attr.attr,
&sensor_dev_attr_pwm2_start_output.dev_attr.attr,
&sensor_dev_attr_pwm2_stop_output.dev_attr.attr,
&sensor_dev_attr_pwm2_max_output.dev_attr.attr,
&sensor_dev_attr_pwm2_step_output.dev_attr.attr,
&sensor_dev_attr_pwm2_target.dev_attr.attr,
&sensor_dev_attr_pwm2_tolerance.dev_attr.attr,
&sensor_dev_attr_pwm3_stop_time.dev_attr.attr,
&sensor_dev_attr_pwm3_start_output.dev_attr.attr,
&sensor_dev_attr_pwm3_stop_output.dev_attr.attr,
&sensor_dev_attr_pwm3_max_output.dev_attr.attr,
&sensor_dev_attr_pwm3_step_output.dev_attr.attr,
&sensor_dev_attr_pwm3_target.dev_attr.attr,
&sensor_dev_attr_pwm3_tolerance.dev_attr.attr,
&sensor_dev_attr_pwm4_stop_time.dev_attr.attr,
&sensor_dev_attr_pwm4_start_output.dev_attr.attr,
&sensor_dev_attr_pwm4_stop_output.dev_attr.attr,
&sensor_dev_attr_pwm4_max_output.dev_attr.attr,
&sensor_dev_attr_pwm4_step_output.dev_attr.attr,
&sensor_dev_attr_pwm4_target.dev_attr.attr,
&sensor_dev_attr_pwm4_tolerance.dev_attr.attr,
&dev_attr_cpu0_vid.attr,
NULL
};
static const struct attribute_group w83627ehf_group = {
.attrs = w83627ehf_attrs,
.is_visible = w83627ehf_attrs_visible,
};
static const struct attribute_group *w83627ehf_groups[] = {
&w83627ehf_group,
NULL
};
/*
* Driver and device management
*/
/* Get the monitoring functions started */
static inline void w83627ehf_init_device(struct w83627ehf_data *data,
enum kinds kind)
{
int i;
u8 tmp, diode;
/* Start monitoring is needed */
tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
if (!(tmp & 0x01))
w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
tmp | 0x01);
/* Enable temperature sensors if needed */
for (i = 0; i < NUM_REG_TEMP; i++) {
if (!(data->have_temp & (1 << i)))
continue;
if (!data->reg_temp_config[i])
continue;
tmp = w83627ehf_read_value(data,
data->reg_temp_config[i]);
if (tmp & 0x01)
w83627ehf_write_value(data,
data->reg_temp_config[i],
tmp & 0xfe);
}
/* Enable VBAT monitoring if needed */
tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
if (!(tmp & 0x01))
w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
/* Get thermal sensor types */
switch (kind) {
case w83627ehf:
diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
break;
case w83627uhg:
diode = 0x00;
break;
default:
diode = 0x70;
}
for (i = 0; i < 3; i++) {
const char *label = NULL;
if (data->temp_label)
label = data->temp_label[data->temp_src[i]];
/* Digital source overrides analog type */
if (label && strncmp(label, "PECI", 4) == 0)
data->temp_type[i] = 6;
else if (label && strncmp(label, "AMD", 3) == 0)
data->temp_type[i] = 5;
else if ((tmp & (0x02 << i)))
data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
else
data->temp_type[i] = 4; /* thermistor */
}
}
static void
w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
{
int i;
for (i = 0; i < n_temp; i++) {
data->reg_temp[i] = W83627EHF_REG_TEMP[i];
data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
}
}
static void
w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
struct w83627ehf_data *data)
{
int fan3pin, fan4pin, fan5pin, regval;
/* The W83627UHG is simple, only two fan inputs, no config */
if (sio_data->kind == w83627uhg) {
data->has_fan = 0x03; /* fan1 and fan2 */
data->has_fan_min = 0x03;
return;
}
/* fan4 and fan5 share some pins with the GPIO and serial flash */
if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
fan3pin = 1;
fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
} else {
fan3pin = 1;
fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
}
data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
data->has_fan |= (fan3pin << 2);
data->has_fan_min |= (fan3pin << 2);
/*
* It looks like fan4 and fan5 pins can be alternatively used
* as fan on/off switches, but fan5 control is write only :/
* We assume that if the serial interface is disabled, designers
* connected fan5 as input unless they are emitting log 1, which
* is not the default.
*/
regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
if ((regval & (1 << 2)) && fan4pin) {
data->has_fan |= (1 << 3);
data->has_fan_min |= (1 << 3);
}
if (!(regval & (1 << 1)) && fan5pin) {
data->has_fan |= (1 << 4);
data->has_fan_min |= (1 << 4);
}
}
static umode_t
w83627ehf_is_visible(const void *drvdata, enum hwmon_sensor_types type,
u32 attr, int channel)
{
const struct w83627ehf_data *data = drvdata;
switch (type) {
case hwmon_temp:
/* channel 0.., name 1.. */
if (!(data->have_temp & (1 << channel)))
return 0;
if (attr == hwmon_temp_input)
return 0444;
if (attr == hwmon_temp_label) {
if (data->temp_label)
return 0444;
return 0;
}
if (channel == 2 && data->temp3_val_only)
return 0;
if (attr == hwmon_temp_max) {
if (data->reg_temp_over[channel])
return 0644;
else
return 0;
}
if (attr == hwmon_temp_max_hyst) {
if (data->reg_temp_hyst[channel])
return 0644;
else
return 0;
}
if (channel > 2)
return 0;
if (attr == hwmon_temp_alarm || attr == hwmon_temp_type)
return 0444;
if (attr == hwmon_temp_offset) {
if (data->have_temp_offset & (1 << channel))
return 0644;
else
return 0;
}
break;
case hwmon_fan:
/* channel 0.., name 1.. */
if (!(data->has_fan & (1 << channel)))
return 0;
if (attr == hwmon_fan_input || attr == hwmon_fan_alarm)
return 0444;
if (attr == hwmon_fan_div) {
return 0444;
}
if (attr == hwmon_fan_min) {
if (data->has_fan_min & (1 << channel))
return 0644;
else
return 0;
}
break;
case hwmon_in:
/* channel 0.., name 0.. */
if (channel >= data->in_num)
return 0;
if (channel == 6 && data->in6_skip)
return 0;
if (attr == hwmon_in_alarm || attr == hwmon_in_input)
return 0444;
if (attr == hwmon_in_min || attr == hwmon_in_max)
return 0644;
break;
case hwmon_pwm:
/* channel 0.., name 1.. */
if (!(data->has_fan & (1 << channel)) ||
channel >= data->pwm_num)
return 0;
if (attr == hwmon_pwm_mode || attr == hwmon_pwm_enable ||
attr == hwmon_pwm_input)
return 0644;
break;
case hwmon_intrusion:
return 0644;
default: /* Shouldn't happen */
return 0;
}
return 0; /* Shouldn't happen */
}
static int
w83627ehf_do_read_temp(struct w83627ehf_data *data, u32 attr,
int channel, long *val)
{
switch (attr) {
case hwmon_temp_input:
*val = LM75_TEMP_FROM_REG(data->temp[channel]);
return 0;
case hwmon_temp_max:
*val = LM75_TEMP_FROM_REG(data->temp_max[channel]);
return 0;
case hwmon_temp_max_hyst:
*val = LM75_TEMP_FROM_REG(data->temp_max_hyst[channel]);
return 0;
case hwmon_temp_offset:
*val = data->temp_offset[channel] * 1000;
return 0;
case hwmon_temp_type:
*val = (int)data->temp_type[channel];
return 0;
case hwmon_temp_alarm:
if (channel < 3) {
int bit[] = { 4, 5, 13 };
*val = (data->alarms >> bit[channel]) & 1;
return 0;
}
break;
default:
break;
}
return -EOPNOTSUPP;
}
static int
w83627ehf_do_read_in(struct w83627ehf_data *data, u32 attr,
int channel, long *val)
{
switch (attr) {
case hwmon_in_input:
*val = in_from_reg(data->in[channel], channel, data->scale_in);
return 0;
case hwmon_in_min:
*val = in_from_reg(data->in_min[channel], channel,
data->scale_in);
return 0;
case hwmon_in_max:
*val = in_from_reg(data->in_max[channel], channel,
data->scale_in);
return 0;
case hwmon_in_alarm:
if (channel < 10) {
int bit[] = { 0, 1, 2, 3, 8, 21, 20, 16, 17, 19 };
*val = (data->alarms >> bit[channel]) & 1;
return 0;
}
break;
default:
break;
}
return -EOPNOTSUPP;
}
static int
w83627ehf_do_read_fan(struct w83627ehf_data *data, u32 attr,
int channel, long *val)
{
switch (attr) {
case hwmon_fan_input:
*val = data->rpm[channel];
return 0;
case hwmon_fan_min:
*val = fan_from_reg8(data->fan_min[channel],
data->fan_div[channel]);
return 0;
case hwmon_fan_div:
*val = div_from_reg(data->fan_div[channel]);
return 0;
case hwmon_fan_alarm:
if (channel < 5) {
int bit[] = { 6, 7, 11, 10, 23 };
*val = (data->alarms >> bit[channel]) & 1;
return 0;
}
break;
default:
break;
}
return -EOPNOTSUPP;
}
static int
w83627ehf_do_read_pwm(struct w83627ehf_data *data, u32 attr,
int channel, long *val)
{
switch (attr) {
case hwmon_pwm_input:
*val = data->pwm[channel];
return 0;
case hwmon_pwm_enable:
*val = data->pwm_enable[channel];
return 0;
case hwmon_pwm_mode:
*val = data->pwm_enable[channel];
return 0;
default:
break;
}
return -EOPNOTSUPP;
}
static int
w83627ehf_do_read_intrusion(struct w83627ehf_data *data, u32 attr,
int channel, long *val)
{
if (attr != hwmon_intrusion_alarm || channel != 0)
return -EOPNOTSUPP; /* shouldn't happen */
*val = !!(data->caseopen & 0x10);
return 0;
}
static int
w83627ehf_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct w83627ehf_data *data = w83627ehf_update_device(dev->parent);
switch (type) {
case hwmon_fan:
return w83627ehf_do_read_fan(data, attr, channel, val);
case hwmon_in:
return w83627ehf_do_read_in(data, attr, channel, val);
case hwmon_pwm:
return w83627ehf_do_read_pwm(data, attr, channel, val);
case hwmon_temp:
return w83627ehf_do_read_temp(data, attr, channel, val);
case hwmon_intrusion:
return w83627ehf_do_read_intrusion(data, attr, channel, val);
default:
break;
}
return -EOPNOTSUPP;
}
static int
w83627ehf_read_string(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, const char **str)
{
struct w83627ehf_data *data = dev_get_drvdata(dev);
switch (type) {
case hwmon_temp:
if (attr == hwmon_temp_label) {
*str = data->temp_label[data->temp_src[channel]];
return 0;
}
break;
default:
break;
}
/* Nothing else should be read as a string */
return -EOPNOTSUPP;
}
static int
w83627ehf_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
struct w83627ehf_data *data = dev_get_drvdata(dev);
if (type == hwmon_in && attr == hwmon_in_min)
return store_in_min(dev, data, channel, val);
if (type == hwmon_in && attr == hwmon_in_max)
return store_in_max(dev, data, channel, val);
if (type == hwmon_fan && attr == hwmon_fan_min)
return store_fan_min(dev, data, channel, val);
if (type == hwmon_temp && attr == hwmon_temp_max)
return store_temp_max(dev, data, channel, val);
if (type == hwmon_temp && attr == hwmon_temp_max_hyst)
return store_temp_max_hyst(dev, data, channel, val);
if (type == hwmon_temp && attr == hwmon_temp_offset)
return store_temp_offset(dev, data, channel, val);
if (type == hwmon_pwm && attr == hwmon_pwm_mode)
return store_pwm_mode(dev, data, channel, val);
if (type == hwmon_pwm && attr == hwmon_pwm_enable)
return store_pwm_enable(dev, data, channel, val);
if (type == hwmon_pwm && attr == hwmon_pwm_input)
return store_pwm(dev, data, channel, val);
if (type == hwmon_intrusion && attr == hwmon_intrusion_alarm)
return clear_caseopen(dev, data, channel, val);
return -EOPNOTSUPP;
}
static const struct hwmon_ops w83627ehf_ops = {
.is_visible = w83627ehf_is_visible,
.read = w83627ehf_read,
.read_string = w83627ehf_read_string,
.write = w83627ehf_write,
};
static const struct hwmon_channel_info * const w83627ehf_info[] = {
HWMON_CHANNEL_INFO(fan,
HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN),
HWMON_CHANNEL_INFO(in,
HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN),
HWMON_CHANNEL_INFO(pwm,
HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE),
HWMON_CHANNEL_INFO(temp,
HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE),
HWMON_CHANNEL_INFO(intrusion,
HWMON_INTRUSION_ALARM),
NULL
};
static const struct hwmon_chip_info w83627ehf_chip_info = {
.ops = &w83627ehf_ops,
.info = w83627ehf_info,
};
static int __init w83627ehf_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
struct w83627ehf_data *data;
struct resource *res;
u8 en_vrm10;
int i, err = 0;
struct device *hwmon_dev;
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!devm_request_region(dev, res->start, IOREGION_LENGTH, DRVNAME))
return -EBUSY;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->addr = res->start;
mutex_init(&data->lock);
mutex_init(&data->update_lock);
data->name = w83627ehf_device_names[sio_data->kind];
data->bank = 0xff; /* Force initial bank selection */
platform_set_drvdata(pdev, data);
/* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
/* 667HG has 3 pwms, and 627UHG has only 2 */
switch (sio_data->kind) {
default:
data->pwm_num = 4;
break;
case w83667hg:
case w83667hg_b:
data->pwm_num = 3;
break;
case w83627uhg:
data->pwm_num = 2;
break;
}
/* Default to 3 temperature inputs, code below will adjust as needed */
data->have_temp = 0x07;
/* Deal with temperature register setup first. */
if (sio_data->kind == w83667hg_b) {
u8 reg;
w83627ehf_set_temp_reg_ehf(data, 4);
/*
* Temperature sources are selected with bank 0, registers 0x49
* and 0x4a.
*/
reg = w83627ehf_read_value(data, 0x4a);
data->temp_src[0] = reg >> 5;
reg = w83627ehf_read_value(data, 0x49);
data->temp_src[1] = reg & 0x07;
data->temp_src[2] = (reg >> 4) & 0x07;
/*
* W83667HG-B has another temperature register at 0x7e.
* The temperature source is selected with register 0x7d.
* Support it if the source differs from already reported
* sources.
*/
reg = w83627ehf_read_value(data, 0x7d);
reg &= 0x07;
if (reg != data->temp_src[0] && reg != data->temp_src[1]
&& reg != data->temp_src[2]) {
data->temp_src[3] = reg;
data->have_temp |= 1 << 3;
}
/*
* Chip supports either AUXTIN or VIN3. Try to find out which
* one.
*/
reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
if (data->temp_src[2] == 2 && (reg & 0x01))
data->have_temp &= ~(1 << 2);
if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
|| (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
data->in6_skip = 1;
data->temp_label = w83667hg_b_temp_label;
data->have_temp_offset = data->have_temp & 0x07;
for (i = 0; i < 3; i++) {
if (data->temp_src[i] > 2)
data->have_temp_offset &= ~(1 << i);
}
} else if (sio_data->kind == w83627uhg) {
u8 reg;
w83627ehf_set_temp_reg_ehf(data, 3);
/*
* Temperature sources for temp2 and temp3 are selected with
* bank 0, registers 0x49 and 0x4a.
*/
data->temp_src[0] = 0; /* SYSTIN */
reg = w83627ehf_read_value(data, 0x49) & 0x07;
/* Adjust to have the same mapping as other source registers */
if (reg == 0)
data->temp_src[1] = 1;
else if (reg >= 2 && reg <= 5)
data->temp_src[1] = reg + 2;
else /* should never happen */
data->have_temp &= ~(1 << 1);
reg = w83627ehf_read_value(data, 0x4a);
data->temp_src[2] = reg >> 5;
/*
* Skip temp3 if source is invalid or the same as temp1
* or temp2.
*/
if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
data->temp_src[2] == data->temp_src[0] ||
((data->have_temp & (1 << 1)) &&
data->temp_src[2] == data->temp_src[1]))
data->have_temp &= ~(1 << 2);
else
data->temp3_val_only = 1; /* No limit regs */
data->in6_skip = 1; /* No VIN3 */
data->temp_label = w83667hg_b_temp_label;
data->have_temp_offset = data->have_temp & 0x03;
for (i = 0; i < 3; i++) {
if (data->temp_src[i] > 1)
data->have_temp_offset &= ~(1 << i);
}
} else {
w83627ehf_set_temp_reg_ehf(data, 3);
/* Temperature sources are fixed */
if (sio_data->kind == w83667hg) {
u8 reg;
/*
* Chip supports either AUXTIN or VIN3. Try to find
* out which one.
*/
reg = w83627ehf_read_value(data,
W83627EHF_REG_TEMP_CONFIG[2]);
if (reg & 0x01)
data->have_temp &= ~(1 << 2);
else
data->in6_skip = 1;
}
data->have_temp_offset = data->have_temp & 0x07;
}
if (sio_data->kind == w83667hg_b) {
data->REG_FAN_MAX_OUTPUT =
W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
data->REG_FAN_STEP_OUTPUT =
W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
} else {
data->REG_FAN_MAX_OUTPUT =
W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
data->REG_FAN_STEP_OUTPUT =
W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
}
/* Setup input voltage scaling factors */
if (sio_data->kind == w83627uhg)
data->scale_in = scale_in_w83627uhg;
else
data->scale_in = scale_in_common;
/* Initialize the chip */
w83627ehf_init_device(data, sio_data->kind);
data->vrm = vid_which_vrm();
err = superio_enter(sio_data->sioreg);
if (err)
return err;
/* Read VID value */
if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
/*
* W83667HG has different pins for VID input and output, so
* we can get the VID input values directly at logical device D
* 0xe3.
*/
superio_select(sio_data->sioreg, W83667HG_LD_VID);
data->vid = superio_inb(sio_data->sioreg, 0xe3);
data->have_vid = true;
} else if (sio_data->kind != w83627uhg) {
superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
/*
* Set VID input sensibility if needed. In theory the
* BIOS should have set it, but in practice it's not
* always the case. We only do it for the W83627EHF/EHG
* because the W83627DHG is more complex in this
* respect.
*/
if (sio_data->kind == w83627ehf) {
en_vrm10 = superio_inb(sio_data->sioreg,
SIO_REG_EN_VRM10);
if ((en_vrm10 & 0x08) && data->vrm == 90) {
dev_warn(dev,
"Setting VID input voltage to TTL\n");
superio_outb(sio_data->sioreg,
SIO_REG_EN_VRM10,
en_vrm10 & ~0x08);
} else if (!(en_vrm10 & 0x08)
&& data->vrm == 100) {
dev_warn(dev,
"Setting VID input voltage to VRM10\n");
superio_outb(sio_data->sioreg,
SIO_REG_EN_VRM10,
en_vrm10 | 0x08);
}
}
data->vid = superio_inb(sio_data->sioreg,
SIO_REG_VID_DATA);
if (sio_data->kind == w83627ehf) /* 6 VID pins only */
data->vid &= 0x3f;
data->have_vid = true;
} else {
dev_info(dev,
"VID pins in output mode, CPU VID not available\n");
}
}
w83627ehf_check_fan_inputs(sio_data, data);
superio_exit(sio_data->sioreg);
/* Read fan clock dividers immediately */
w83627ehf_update_fan_div(data);
/* Read pwm data to save original values */
w83627ehf_update_pwm(data);
for (i = 0; i < data->pwm_num; i++)
data->pwm_enable_orig[i] = data->pwm_enable[i];
hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
data->name,
data,
&w83627ehf_chip_info,
w83627ehf_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static int w83627ehf_suspend(struct device *dev)
{
struct w83627ehf_data *data = w83627ehf_update_device(dev);
mutex_lock(&data->update_lock);
data->vbat = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
mutex_unlock(&data->update_lock);
return 0;
}
static int w83627ehf_resume(struct device *dev)
{
struct w83627ehf_data *data = dev_get_drvdata(dev);
int i;
mutex_lock(&data->update_lock);
data->bank = 0xff; /* Force initial bank selection */
/* Restore limits */
for (i = 0; i < data->in_num; i++) {
if ((i == 6) && data->in6_skip)
continue;
w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
data->in_min[i]);
w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
data->in_max[i]);
}
for (i = 0; i < 5; i++) {
if (!(data->has_fan_min & (1 << i)))
continue;
w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[i],
data->fan_min[i]);
}
for (i = 0; i < NUM_REG_TEMP; i++) {
if (!(data->have_temp & (1 << i)))
continue;
if (data->reg_temp_over[i])
w83627ehf_write_temp(data, data->reg_temp_over[i],
data->temp_max[i]);
if (data->reg_temp_hyst[i])
w83627ehf_write_temp(data, data->reg_temp_hyst[i],
data->temp_max_hyst[i]);
if (i > 2)
continue;
if (data->have_temp_offset & (1 << i))
w83627ehf_write_value(data,
W83627EHF_REG_TEMP_OFFSET[i],
data->temp_offset[i]);
}
/* Restore other settings */
w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);
/* Force re-reading all values */
data->valid = false;
mutex_unlock(&data->update_lock);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(w83627ehf_dev_pm_ops, w83627ehf_suspend, w83627ehf_resume);
static struct platform_driver w83627ehf_driver = {
.driver = {
.name = DRVNAME,
.pm = pm_sleep_ptr(&w83627ehf_dev_pm_ops),
},
};
/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
struct w83627ehf_sio_data *sio_data)
{
static const char sio_name_W83627EHF[] __initconst = "W83627EHF";
static const char sio_name_W83627EHG[] __initconst = "W83627EHG";
static const char sio_name_W83627DHG[] __initconst = "W83627DHG";
static const char sio_name_W83627DHG_P[] __initconst = "W83627DHG-P";
static const char sio_name_W83627UHG[] __initconst = "W83627UHG";
static const char sio_name_W83667HG[] __initconst = "W83667HG";
static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B";
u16 val;
const char *sio_name;
int err;
err = superio_enter(sioaddr);
if (err)
return err;
if (force_id)
val = force_id;
else
val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
| superio_inb(sioaddr, SIO_REG_DEVID + 1);
switch (val & SIO_ID_MASK) {
case SIO_W83627EHF_ID:
sio_data->kind = w83627ehf;
sio_name = sio_name_W83627EHF;
break;
case SIO_W83627EHG_ID:
sio_data->kind = w83627ehf;
sio_name = sio_name_W83627EHG;
break;
case SIO_W83627DHG_ID:
sio_data->kind = w83627dhg;
sio_name = sio_name_W83627DHG;
break;
case SIO_W83627DHG_P_ID:
sio_data->kind = w83627dhg_p;
sio_name = sio_name_W83627DHG_P;
break;
case SIO_W83627UHG_ID:
sio_data->kind = w83627uhg;
sio_name = sio_name_W83627UHG;
break;
case SIO_W83667HG_ID:
sio_data->kind = w83667hg;
sio_name = sio_name_W83667HG;
break;
case SIO_W83667HG_B_ID:
sio_data->kind = w83667hg_b;
sio_name = sio_name_W83667HG_B;
break;
default:
if (val != 0xffff)
pr_debug("unsupported chip ID: 0x%04x\n", val);
superio_exit(sioaddr);
return -ENODEV;
}
/* We have a known chip, find the HWM I/O address */
superio_select(sioaddr, W83627EHF_LD_HWM);
val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
| superio_inb(sioaddr, SIO_REG_ADDR + 1);
*addr = val & IOREGION_ALIGNMENT;
if (*addr == 0) {
pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
superio_exit(sioaddr);
return -ENODEV;
}
/* Activate logical device if needed */
val = superio_inb(sioaddr, SIO_REG_ENABLE);
if (!(val & 0x01)) {
pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
}
superio_exit(sioaddr);
pr_info("Found %s chip at %#x\n", sio_name, *addr);
sio_data->sioreg = sioaddr;
return 0;
}
/*
* when Super-I/O functions move to a separate file, the Super-I/O
* bus will manage the lifetime of the device and this module will only keep
* track of the w83627ehf driver.
*/
static struct platform_device *pdev;
static int __init sensors_w83627ehf_init(void)
{
int err;
unsigned short address;
struct resource res = {
.name = DRVNAME,
.flags = IORESOURCE_IO,
};
struct w83627ehf_sio_data sio_data;
/*
* initialize sio_data->kind and sio_data->sioreg.
*
* when Super-I/O functions move to a separate file, the Super-I/O
* driver will probe 0x2e and 0x4e and auto-detect the presence of a
* w83627ehf hardware monitor, and call probe()
*/
if (w83627ehf_find(0x2e, &address, &sio_data) &&
w83627ehf_find(0x4e, &address, &sio_data))
return -ENODEV;
res.start = address + IOREGION_OFFSET;
res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
err = acpi_check_resource_conflict(&res);
if (err)
return err;
pdev = platform_create_bundle(&w83627ehf_driver, w83627ehf_probe, &res, 1, &sio_data,
sizeof(struct w83627ehf_sio_data));
return PTR_ERR_OR_ZERO(pdev);
}
static void __exit sensors_w83627ehf_exit(void)
{
platform_device_unregister(pdev);
platform_driver_unregister(&w83627ehf_driver);
}
MODULE_AUTHOR("Jean Delvare <[email protected]>");
MODULE_DESCRIPTION("W83627EHF driver");
MODULE_LICENSE("GPL");
module_init(sensors_w83627ehf_init);
module_exit(sensors_w83627ehf_exit);
|
linux-master
|
drivers/hwmon/w83627ehf.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* lm75.c - Part of lm_sensors, Linux kernel modules for hardware
* monitoring
* Copyright (c) 1998, 1999 Frodo Looijaard <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/util_macros.h>
#include <linux/regulator/consumer.h>
#include "lm75.h"
/*
* This driver handles the LM75 and compatible digital temperature sensors.
*/
enum lm75_type { /* keep sorted in alphabetical order */
adt75,
at30ts74,
ds1775,
ds75,
ds7505,
g751,
lm75,
lm75a,
lm75b,
max6625,
max6626,
max31725,
mcp980x,
pct2075,
stds75,
stlm75,
tcn75,
tmp100,
tmp101,
tmp105,
tmp112,
tmp175,
tmp275,
tmp75,
tmp75b,
tmp75c,
tmp1075,
};
/**
* struct lm75_params - lm75 configuration parameters.
* @set_mask: Bits to set in configuration register when configuring
* the chip.
* @clr_mask: Bits to clear in configuration register when configuring
* the chip.
* @default_resolution: Default number of bits to represent the temperature
* value.
* @resolution_limits: Limit register resolution. Optional. Should be set if
* the resolution of limit registers does not match the
* resolution of the temperature register.
* @resolutions: List of resolutions associated with sample times.
* Optional. Should be set if num_sample_times is larger
* than 1, and if the resolution changes with sample times.
* If set, number of entries must match num_sample_times.
* @default_sample_time:Sample time to be set by default.
* @num_sample_times: Number of possible sample times to be set. Optional.
* Should be set if the number of sample times is larger
* than one.
* @sample_times: All the possible sample times to be set. Mandatory if
* num_sample_times is larger than 1. If set, number of
* entries must match num_sample_times.
*/
struct lm75_params {
u8 set_mask;
u8 clr_mask;
u8 default_resolution;
u8 resolution_limits;
const u8 *resolutions;
unsigned int default_sample_time;
u8 num_sample_times;
const unsigned int *sample_times;
};
/* Addresses scanned */
static const unsigned short normal_i2c[] = { 0x48, 0x49, 0x4a, 0x4b, 0x4c,
0x4d, 0x4e, 0x4f, I2C_CLIENT_END };
/* The LM75 registers */
#define LM75_REG_TEMP 0x00
#define LM75_REG_CONF 0x01
#define LM75_REG_HYST 0x02
#define LM75_REG_MAX 0x03
#define PCT2075_REG_IDLE 0x04
/* Each client has this additional data */
struct lm75_data {
struct i2c_client *client;
struct regmap *regmap;
struct regulator *vs;
u8 orig_conf;
u8 current_conf;
u8 resolution; /* In bits, 9 to 16 */
unsigned int sample_time; /* In ms */
enum lm75_type kind;
const struct lm75_params *params;
};
/*-----------------------------------------------------------------------*/
static const u8 lm75_sample_set_masks[] = { 0 << 5, 1 << 5, 2 << 5, 3 << 5 };
#define LM75_SAMPLE_CLEAR_MASK (3 << 5)
/* The structure below stores the configuration values of the supported devices.
* In case of being supported multiple configurations, the default one must
* always be the first element of the array
*/
static const struct lm75_params device_params[] = {
[adt75] = {
.clr_mask = 1 << 5, /* not one-shot mode */
.default_resolution = 12,
.default_sample_time = MSEC_PER_SEC / 10,
},
[at30ts74] = {
.set_mask = 3 << 5, /* 12-bit mode*/
.default_resolution = 12,
.default_sample_time = 200,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 25, 50, 100, 200 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[ds1775] = {
.clr_mask = 3 << 5,
.set_mask = 2 << 5, /* 11-bit mode */
.default_resolution = 11,
.default_sample_time = 500,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 125, 250, 500, 1000 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[ds75] = {
.clr_mask = 3 << 5,
.set_mask = 2 << 5, /* 11-bit mode */
.default_resolution = 11,
.default_sample_time = 600,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 150, 300, 600, 1200 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[stds75] = {
.clr_mask = 3 << 5,
.set_mask = 2 << 5, /* 11-bit mode */
.default_resolution = 11,
.default_sample_time = 600,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 150, 300, 600, 1200 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[stlm75] = {
.default_resolution = 9,
.default_sample_time = MSEC_PER_SEC / 6,
},
[ds7505] = {
.set_mask = 3 << 5, /* 12-bit mode*/
.default_resolution = 12,
.default_sample_time = 200,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 25, 50, 100, 200 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[g751] = {
.default_resolution = 9,
.default_sample_time = MSEC_PER_SEC / 10,
},
[lm75] = {
.default_resolution = 9,
.default_sample_time = MSEC_PER_SEC / 10,
},
[lm75a] = {
.default_resolution = 9,
.default_sample_time = MSEC_PER_SEC / 10,
},
[lm75b] = {
.default_resolution = 11,
.default_sample_time = MSEC_PER_SEC / 10,
},
[max6625] = {
.default_resolution = 9,
.default_sample_time = MSEC_PER_SEC / 7,
},
[max6626] = {
.default_resolution = 12,
.default_sample_time = MSEC_PER_SEC / 7,
.resolution_limits = 9,
},
[max31725] = {
.default_resolution = 16,
.default_sample_time = MSEC_PER_SEC / 20,
},
[tcn75] = {
.default_resolution = 9,
.default_sample_time = MSEC_PER_SEC / 18,
},
[pct2075] = {
.default_resolution = 11,
.default_sample_time = MSEC_PER_SEC / 10,
.num_sample_times = 31,
.sample_times = (unsigned int []){ 100, 200, 300, 400, 500, 600,
700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700,
1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700,
2800, 2900, 3000, 3100 },
},
[mcp980x] = {
.set_mask = 3 << 5, /* 12-bit mode */
.clr_mask = 1 << 7, /* not one-shot mode */
.default_resolution = 12,
.resolution_limits = 9,
.default_sample_time = 240,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 30, 60, 120, 240 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[tmp100] = {
.set_mask = 3 << 5, /* 12-bit mode */
.clr_mask = 1 << 7, /* not one-shot mode */
.default_resolution = 12,
.default_sample_time = 320,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 40, 80, 160, 320 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[tmp101] = {
.set_mask = 3 << 5, /* 12-bit mode */
.clr_mask = 1 << 7, /* not one-shot mode */
.default_resolution = 12,
.default_sample_time = 320,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 40, 80, 160, 320 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[tmp105] = {
.set_mask = 3 << 5, /* 12-bit mode */
.clr_mask = 1 << 7, /* not one-shot mode*/
.default_resolution = 12,
.default_sample_time = 220,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 28, 55, 110, 220 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[tmp112] = {
.set_mask = 3 << 5, /* 8 samples / second */
.clr_mask = 1 << 7, /* no one-shot mode*/
.default_resolution = 12,
.default_sample_time = 125,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 125, 250, 1000, 4000 },
},
[tmp175] = {
.set_mask = 3 << 5, /* 12-bit mode */
.clr_mask = 1 << 7, /* not one-shot mode*/
.default_resolution = 12,
.default_sample_time = 220,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 28, 55, 110, 220 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[tmp275] = {
.set_mask = 3 << 5, /* 12-bit mode */
.clr_mask = 1 << 7, /* not one-shot mode*/
.default_resolution = 12,
.default_sample_time = 220,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 28, 55, 110, 220 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[tmp75] = {
.set_mask = 3 << 5, /* 12-bit mode */
.clr_mask = 1 << 7, /* not one-shot mode*/
.default_resolution = 12,
.default_sample_time = 220,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 28, 55, 110, 220 },
.resolutions = (u8 []) {9, 10, 11, 12 },
},
[tmp75b] = { /* not one-shot mode, Conversion rate 37Hz */
.clr_mask = 1 << 7 | 3 << 5,
.default_resolution = 12,
.default_sample_time = MSEC_PER_SEC / 37,
.sample_times = (unsigned int []){ MSEC_PER_SEC / 37,
MSEC_PER_SEC / 18,
MSEC_PER_SEC / 9, MSEC_PER_SEC / 4 },
.num_sample_times = 4,
},
[tmp75c] = {
.clr_mask = 1 << 5, /*not one-shot mode*/
.default_resolution = 12,
.default_sample_time = MSEC_PER_SEC / 12,
},
[tmp1075] = { /* not one-shot mode, 27.5 ms sample rate */
.clr_mask = 1 << 5 | 1 << 6 | 1 << 7,
.default_resolution = 12,
.default_sample_time = 28,
.num_sample_times = 4,
.sample_times = (unsigned int []){ 28, 55, 110, 220 },
}
};
static inline long lm75_reg_to_mc(s16 temp, u8 resolution)
{
return ((temp >> (16 - resolution)) * 1000) >> (resolution - 8);
}
static int lm75_write_config(struct lm75_data *data, u8 set_mask,
u8 clr_mask)
{
u8 value;
clr_mask |= LM75_SHUTDOWN;
value = data->current_conf & ~clr_mask;
value |= set_mask;
if (data->current_conf != value) {
s32 err;
err = i2c_smbus_write_byte_data(data->client, LM75_REG_CONF,
value);
if (err)
return err;
data->current_conf = value;
}
return 0;
}
static int lm75_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct lm75_data *data = dev_get_drvdata(dev);
unsigned int regval;
int err, reg;
switch (type) {
case hwmon_chip:
switch (attr) {
case hwmon_chip_update_interval:
*val = data->sample_time;
break;
default:
return -EINVAL;
}
break;
case hwmon_temp:
switch (attr) {
case hwmon_temp_input:
reg = LM75_REG_TEMP;
break;
case hwmon_temp_max:
reg = LM75_REG_MAX;
break;
case hwmon_temp_max_hyst:
reg = LM75_REG_HYST;
break;
default:
return -EINVAL;
}
err = regmap_read(data->regmap, reg, ®val);
if (err < 0)
return err;
*val = lm75_reg_to_mc(regval, data->resolution);
break;
default:
return -EINVAL;
}
return 0;
}
static int lm75_write_temp(struct device *dev, u32 attr, long temp)
{
struct lm75_data *data = dev_get_drvdata(dev);
u8 resolution;
int reg;
switch (attr) {
case hwmon_temp_max:
reg = LM75_REG_MAX;
break;
case hwmon_temp_max_hyst:
reg = LM75_REG_HYST;
break;
default:
return -EINVAL;
}
/*
* Resolution of limit registers is assumed to be the same as the
* temperature input register resolution unless given explicitly.
*/
if (data->params->resolution_limits)
resolution = data->params->resolution_limits;
else
resolution = data->resolution;
temp = clamp_val(temp, LM75_TEMP_MIN, LM75_TEMP_MAX);
temp = DIV_ROUND_CLOSEST(temp << (resolution - 8),
1000) << (16 - resolution);
return regmap_write(data->regmap, reg, (u16)temp);
}
static int lm75_update_interval(struct device *dev, long val)
{
struct lm75_data *data = dev_get_drvdata(dev);
unsigned int reg;
u8 index;
s32 err;
index = find_closest(val, data->params->sample_times,
(int)data->params->num_sample_times);
switch (data->kind) {
default:
err = lm75_write_config(data, lm75_sample_set_masks[index],
LM75_SAMPLE_CLEAR_MASK);
if (err)
return err;
data->sample_time = data->params->sample_times[index];
if (data->params->resolutions)
data->resolution = data->params->resolutions[index];
break;
case tmp112:
err = regmap_read(data->regmap, LM75_REG_CONF, ®);
if (err < 0)
return err;
reg &= ~0x00c0;
reg |= (3 - index) << 6;
err = regmap_write(data->regmap, LM75_REG_CONF, reg);
if (err < 0)
return err;
data->sample_time = data->params->sample_times[index];
break;
case pct2075:
err = i2c_smbus_write_byte_data(data->client, PCT2075_REG_IDLE,
index + 1);
if (err)
return err;
data->sample_time = data->params->sample_times[index];
break;
}
return 0;
}
static int lm75_write_chip(struct device *dev, u32 attr, long val)
{
switch (attr) {
case hwmon_chip_update_interval:
return lm75_update_interval(dev, val);
default:
return -EINVAL;
}
return 0;
}
static int lm75_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
switch (type) {
case hwmon_chip:
return lm75_write_chip(dev, attr, val);
case hwmon_temp:
return lm75_write_temp(dev, attr, val);
default:
return -EINVAL;
}
return 0;
}
static umode_t lm75_is_visible(const void *data, enum hwmon_sensor_types type,
u32 attr, int channel)
{
const struct lm75_data *config_data = data;
switch (type) {
case hwmon_chip:
switch (attr) {
case hwmon_chip_update_interval:
if (config_data->params->num_sample_times > 1)
return 0644;
return 0444;
}
break;
case hwmon_temp:
switch (attr) {
case hwmon_temp_input:
return 0444;
case hwmon_temp_max:
case hwmon_temp_max_hyst:
return 0644;
}
break;
default:
break;
}
return 0;
}
static const struct hwmon_channel_info * const lm75_info[] = {
HWMON_CHANNEL_INFO(chip,
HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST),
NULL
};
static const struct hwmon_ops lm75_hwmon_ops = {
.is_visible = lm75_is_visible,
.read = lm75_read,
.write = lm75_write,
};
static const struct hwmon_chip_info lm75_chip_info = {
.ops = &lm75_hwmon_ops,
.info = lm75_info,
};
static bool lm75_is_writeable_reg(struct device *dev, unsigned int reg)
{
return reg != LM75_REG_TEMP;
}
static bool lm75_is_volatile_reg(struct device *dev, unsigned int reg)
{
return reg == LM75_REG_TEMP || reg == LM75_REG_CONF;
}
static const struct regmap_config lm75_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.max_register = PCT2075_REG_IDLE,
.writeable_reg = lm75_is_writeable_reg,
.volatile_reg = lm75_is_volatile_reg,
.val_format_endian = REGMAP_ENDIAN_BIG,
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static void lm75_disable_regulator(void *data)
{
struct lm75_data *lm75 = data;
regulator_disable(lm75->vs);
}
static void lm75_remove(void *data)
{
struct lm75_data *lm75 = data;
struct i2c_client *client = lm75->client;
i2c_smbus_write_byte_data(client, LM75_REG_CONF, lm75->orig_conf);
}
static const struct i2c_device_id lm75_ids[];
static int lm75_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct device *hwmon_dev;
struct lm75_data *data;
int status, err;
enum lm75_type kind;
if (client->dev.of_node)
kind = (uintptr_t)of_device_get_match_data(&client->dev);
else
kind = i2c_match_id(lm75_ids, client)->driver_data;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA))
return -EIO;
data = devm_kzalloc(dev, sizeof(struct lm75_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
data->kind = kind;
data->vs = devm_regulator_get(dev, "vs");
if (IS_ERR(data->vs))
return PTR_ERR(data->vs);
data->regmap = devm_regmap_init_i2c(client, &lm75_regmap_config);
if (IS_ERR(data->regmap))
return PTR_ERR(data->regmap);
/* Set to LM75 resolution (9 bits, 1/2 degree C) and range.
* Then tweak to be more precise when appropriate.
*/
data->params = &device_params[data->kind];
/* Save default sample time and resolution*/
data->sample_time = data->params->default_sample_time;
data->resolution = data->params->default_resolution;
/* Enable the power */
err = regulator_enable(data->vs);
if (err) {
dev_err(dev, "failed to enable regulator: %d\n", err);
return err;
}
err = devm_add_action_or_reset(dev, lm75_disable_regulator, data);
if (err)
return err;
/* Cache original configuration */
status = i2c_smbus_read_byte_data(client, LM75_REG_CONF);
if (status < 0) {
dev_dbg(dev, "Can't read config? %d\n", status);
return status;
}
data->orig_conf = status;
data->current_conf = status;
err = lm75_write_config(data, data->params->set_mask,
data->params->clr_mask);
if (err)
return err;
err = devm_add_action_or_reset(dev, lm75_remove, data);
if (err)
return err;
hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
data, &lm75_chip_info,
NULL);
if (IS_ERR(hwmon_dev))
return PTR_ERR(hwmon_dev);
dev_info(dev, "%s: sensor '%s'\n", dev_name(hwmon_dev), client->name);
return 0;
}
static const struct i2c_device_id lm75_ids[] = {
{ "adt75", adt75, },
{ "at30ts74", at30ts74, },
{ "ds1775", ds1775, },
{ "ds75", ds75, },
{ "ds7505", ds7505, },
{ "g751", g751, },
{ "lm75", lm75, },
{ "lm75a", lm75a, },
{ "lm75b", lm75b, },
{ "max6625", max6625, },
{ "max6626", max6626, },
{ "max31725", max31725, },
{ "max31726", max31725, },
{ "mcp980x", mcp980x, },
{ "pct2075", pct2075, },
{ "stds75", stds75, },
{ "stlm75", stlm75, },
{ "tcn75", tcn75, },
{ "tmp100", tmp100, },
{ "tmp101", tmp101, },
{ "tmp105", tmp105, },
{ "tmp112", tmp112, },
{ "tmp175", tmp175, },
{ "tmp275", tmp275, },
{ "tmp75", tmp75, },
{ "tmp75b", tmp75b, },
{ "tmp75c", tmp75c, },
{ "tmp1075", tmp1075, },
{ /* LIST END */ }
};
MODULE_DEVICE_TABLE(i2c, lm75_ids);
static const struct of_device_id __maybe_unused lm75_of_match[] = {
{
.compatible = "adi,adt75",
.data = (void *)adt75
},
{
.compatible = "atmel,at30ts74",
.data = (void *)at30ts74
},
{
.compatible = "dallas,ds1775",
.data = (void *)ds1775
},
{
.compatible = "dallas,ds75",
.data = (void *)ds75
},
{
.compatible = "dallas,ds7505",
.data = (void *)ds7505
},
{
.compatible = "gmt,g751",
.data = (void *)g751
},
{
.compatible = "national,lm75",
.data = (void *)lm75
},
{
.compatible = "national,lm75a",
.data = (void *)lm75a
},
{
.compatible = "national,lm75b",
.data = (void *)lm75b
},
{
.compatible = "maxim,max6625",
.data = (void *)max6625
},
{
.compatible = "maxim,max6626",
.data = (void *)max6626
},
{
.compatible = "maxim,max31725",
.data = (void *)max31725
},
{
.compatible = "maxim,max31726",
.data = (void *)max31725
},
{
.compatible = "maxim,mcp980x",
.data = (void *)mcp980x
},
{
.compatible = "nxp,pct2075",
.data = (void *)pct2075
},
{
.compatible = "st,stds75",
.data = (void *)stds75
},
{
.compatible = "st,stlm75",
.data = (void *)stlm75
},
{
.compatible = "microchip,tcn75",
.data = (void *)tcn75
},
{
.compatible = "ti,tmp100",
.data = (void *)tmp100
},
{
.compatible = "ti,tmp101",
.data = (void *)tmp101
},
{
.compatible = "ti,tmp105",
.data = (void *)tmp105
},
{
.compatible = "ti,tmp112",
.data = (void *)tmp112
},
{
.compatible = "ti,tmp175",
.data = (void *)tmp175
},
{
.compatible = "ti,tmp275",
.data = (void *)tmp275
},
{
.compatible = "ti,tmp75",
.data = (void *)tmp75
},
{
.compatible = "ti,tmp75b",
.data = (void *)tmp75b
},
{
.compatible = "ti,tmp75c",
.data = (void *)tmp75c
},
{
.compatible = "ti,tmp1075",
.data = (void *)tmp1075
},
{ },
};
MODULE_DEVICE_TABLE(of, lm75_of_match);
#define LM75A_ID 0xA1
/* Return 0 if detection is successful, -ENODEV otherwise */
static int lm75_detect(struct i2c_client *new_client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = new_client->adapter;
int i;
int conf, hyst, os;
bool is_lm75a = 0;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_WORD_DATA))
return -ENODEV;
/*
* Now, we do the remaining detection. There is no identification-
* dedicated register so we have to rely on several tricks:
* unused bits, registers cycling over 8-address boundaries,
* addresses 0x04-0x07 returning the last read value.
* The cycling+unused addresses combination is not tested,
* since it would significantly slow the detection down and would
* hardly add any value.
*
* The National Semiconductor LM75A is different than earlier
* LM75s. It has an ID byte of 0xaX (where X is the chip
* revision, with 1 being the only revision in existence) in
* register 7, and unused registers return 0xff rather than the
* last read value.
*
* Note that this function only detects the original National
* Semiconductor LM75 and the LM75A. Clones from other vendors
* aren't detected, on purpose, because they are typically never
* found on PC hardware. They are found on embedded designs where
* they can be instantiated explicitly so detection is not needed.
* The absence of identification registers on all these clones
* would make their exhaustive detection very difficult and weak,
* and odds are that the driver would bind to unsupported devices.
*/
/* Unused bits */
conf = i2c_smbus_read_byte_data(new_client, 1);
if (conf & 0xe0)
return -ENODEV;
/* First check for LM75A */
if (i2c_smbus_read_byte_data(new_client, 7) == LM75A_ID) {
/*
* LM75A returns 0xff on unused registers so
* just to be sure we check for that too.
*/
if (i2c_smbus_read_byte_data(new_client, 4) != 0xff
|| i2c_smbus_read_byte_data(new_client, 5) != 0xff
|| i2c_smbus_read_byte_data(new_client, 6) != 0xff)
return -ENODEV;
is_lm75a = 1;
hyst = i2c_smbus_read_byte_data(new_client, 2);
os = i2c_smbus_read_byte_data(new_client, 3);
} else { /* Traditional style LM75 detection */
/* Unused addresses */
hyst = i2c_smbus_read_byte_data(new_client, 2);
if (i2c_smbus_read_byte_data(new_client, 4) != hyst
|| i2c_smbus_read_byte_data(new_client, 5) != hyst
|| i2c_smbus_read_byte_data(new_client, 6) != hyst
|| i2c_smbus_read_byte_data(new_client, 7) != hyst)
return -ENODEV;
os = i2c_smbus_read_byte_data(new_client, 3);
if (i2c_smbus_read_byte_data(new_client, 4) != os
|| i2c_smbus_read_byte_data(new_client, 5) != os
|| i2c_smbus_read_byte_data(new_client, 6) != os
|| i2c_smbus_read_byte_data(new_client, 7) != os)
return -ENODEV;
}
/*
* It is very unlikely that this is a LM75 if both
* hysteresis and temperature limit registers are 0.
*/
if (hyst == 0 && os == 0)
return -ENODEV;
/* Addresses cycling */
for (i = 8; i <= 248; i += 40) {
if (i2c_smbus_read_byte_data(new_client, i + 1) != conf
|| i2c_smbus_read_byte_data(new_client, i + 2) != hyst
|| i2c_smbus_read_byte_data(new_client, i + 3) != os)
return -ENODEV;
if (is_lm75a && i2c_smbus_read_byte_data(new_client, i + 7)
!= LM75A_ID)
return -ENODEV;
}
strscpy(info->type, is_lm75a ? "lm75a" : "lm75", I2C_NAME_SIZE);
return 0;
}
#ifdef CONFIG_PM
static int lm75_suspend(struct device *dev)
{
int status;
struct i2c_client *client = to_i2c_client(dev);
status = i2c_smbus_read_byte_data(client, LM75_REG_CONF);
if (status < 0) {
dev_dbg(&client->dev, "Can't read config? %d\n", status);
return status;
}
status = status | LM75_SHUTDOWN;
i2c_smbus_write_byte_data(client, LM75_REG_CONF, status);
return 0;
}
static int lm75_resume(struct device *dev)
{
int status;
struct i2c_client *client = to_i2c_client(dev);
status = i2c_smbus_read_byte_data(client, LM75_REG_CONF);
if (status < 0) {
dev_dbg(&client->dev, "Can't read config? %d\n", status);
return status;
}
status = status & ~LM75_SHUTDOWN;
i2c_smbus_write_byte_data(client, LM75_REG_CONF, status);
return 0;
}
static const struct dev_pm_ops lm75_dev_pm_ops = {
.suspend = lm75_suspend,
.resume = lm75_resume,
};
#define LM75_DEV_PM_OPS (&lm75_dev_pm_ops)
#else
#define LM75_DEV_PM_OPS NULL
#endif /* CONFIG_PM */
static struct i2c_driver lm75_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "lm75",
.of_match_table = of_match_ptr(lm75_of_match),
.pm = LM75_DEV_PM_OPS,
},
.probe = lm75_probe,
.id_table = lm75_ids,
.detect = lm75_detect,
.address_list = normal_i2c,
};
module_i2c_driver(lm75_driver);
MODULE_AUTHOR("Frodo Looijaard <[email protected]>");
MODULE_DESCRIPTION("LM75 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/lm75.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for Texas Instruments INA238 power monitor chip
* Datasheet: https://www.ti.com/product/ina238
*
* Copyright (C) 2021 Nathan Rossi <[email protected]>
*/
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/platform_data/ina2xx.h>
/* INA238 register definitions */
#define INA238_CONFIG 0x0
#define INA238_ADC_CONFIG 0x1
#define INA238_SHUNT_CALIBRATION 0x2
#define INA238_SHUNT_VOLTAGE 0x4
#define INA238_BUS_VOLTAGE 0x5
#define INA238_DIE_TEMP 0x6
#define INA238_CURRENT 0x7
#define INA238_POWER 0x8
#define INA238_DIAG_ALERT 0xb
#define INA238_SHUNT_OVER_VOLTAGE 0xc
#define INA238_SHUNT_UNDER_VOLTAGE 0xd
#define INA238_BUS_OVER_VOLTAGE 0xe
#define INA238_BUS_UNDER_VOLTAGE 0xf
#define INA238_TEMP_LIMIT 0x10
#define INA238_POWER_LIMIT 0x11
#define INA238_DEVICE_ID 0x3f
#define INA238_CONFIG_ADCRANGE BIT(4)
#define INA238_DIAG_ALERT_TMPOL BIT(7)
#define INA238_DIAG_ALERT_SHNTOL BIT(6)
#define INA238_DIAG_ALERT_SHNTUL BIT(5)
#define INA238_DIAG_ALERT_BUSOL BIT(4)
#define INA238_DIAG_ALERT_BUSUL BIT(3)
#define INA238_DIAG_ALERT_POL BIT(2)
#define INA238_REGISTERS 0x11
#define INA238_RSHUNT_DEFAULT 10000 /* uOhm */
/* Default configuration of device on reset. */
#define INA238_CONFIG_DEFAULT 0
/* 16 sample averaging, 1052us conversion time, continuous mode */
#define INA238_ADC_CONFIG_DEFAULT 0xfb6a
/* Configure alerts to be based on averaged value (SLOWALERT) */
#define INA238_DIAG_ALERT_DEFAULT 0x2000
/*
* This driver uses a fixed calibration value in order to scale current/power
* based on a fixed shunt resistor value. This allows for conversion within the
* device to avoid integer limits whilst current/power accuracy is scaled
* relative to the shunt resistor value within the driver. This is similar to
* how the ina2xx driver handles current/power scaling.
*
* The end result of this is that increasing shunt values (from a fixed 20 mOhm
* shunt) increase the effective current/power accuracy whilst limiting the
* range and decreasing shunt values decrease the effective accuracy but
* increase the range.
*
* The value of the Current register is calculated given the following:
* Current (A) = (shunt voltage register * 5) * calibration / 81920
*
* The maximum shunt voltage is 163.835 mV (0x7fff, ADC_RANGE = 0, gain = 4).
* With the maximum current value of 0x7fff and a fixed shunt value results in
* a calibration value of 16384 (0x4000).
*
* 0x7fff = (0x7fff * 5) * calibration / 81920
* calibration = 0x4000
*
* Equivalent calibration is applied for the Power register (maximum value for
* bus voltage is 102396.875 mV, 0x7fff), where the maximum power that can
* occur is ~16776192 uW (register value 0x147a8):
*
* This scaling means the resulting values for Current and Power registers need
* to be scaled by the difference between the fixed shunt resistor and the
* actual shunt resistor:
*
* shunt = 0x4000 / (819.2 * 10^6) / 0.001 = 20000 uOhms (with 1mA/lsb)
*
* Current (mA) = register value * 20000 / rshunt / 4 * gain
* Power (W) = 0.2 * register value * 20000 / rshunt / 4 * gain
*/
#define INA238_CALIBRATION_VALUE 16384
#define INA238_FIXED_SHUNT 20000
#define INA238_SHUNT_VOLTAGE_LSB 5 /* 5 uV/lsb */
#define INA238_BUS_VOLTAGE_LSB 3125 /* 3.125 mV/lsb */
#define INA238_DIE_TEMP_LSB 125 /* 125 mC/lsb */
static struct regmap_config ina238_regmap_config = {
.max_register = INA238_REGISTERS,
.reg_bits = 8,
.val_bits = 16,
};
struct ina238_data {
struct i2c_client *client;
struct mutex config_lock;
struct regmap *regmap;
u32 rshunt;
int gain;
};
static int ina238_read_reg24(const struct i2c_client *client, u8 reg, u32 *val)
{
u8 data[3];
int err;
/* 24-bit register read */
err = i2c_smbus_read_i2c_block_data(client, reg, 3, data);
if (err < 0)
return err;
if (err != 3)
return -EIO;
*val = (data[0] << 16) | (data[1] << 8) | data[2];
return 0;
}
static int ina238_read_in(struct device *dev, u32 attr, int channel,
long *val)
{
struct ina238_data *data = dev_get_drvdata(dev);
int reg, mask;
int regval;
int err;
switch (channel) {
case 0:
switch (attr) {
case hwmon_in_input:
reg = INA238_SHUNT_VOLTAGE;
break;
case hwmon_in_max:
reg = INA238_SHUNT_OVER_VOLTAGE;
break;
case hwmon_in_min:
reg = INA238_SHUNT_UNDER_VOLTAGE;
break;
case hwmon_in_max_alarm:
reg = INA238_DIAG_ALERT;
mask = INA238_DIAG_ALERT_SHNTOL;
break;
case hwmon_in_min_alarm:
reg = INA238_DIAG_ALERT;
mask = INA238_DIAG_ALERT_SHNTUL;
break;
default:
return -EOPNOTSUPP;
}
break;
case 1:
switch (attr) {
case hwmon_in_input:
reg = INA238_BUS_VOLTAGE;
break;
case hwmon_in_max:
reg = INA238_BUS_OVER_VOLTAGE;
break;
case hwmon_in_min:
reg = INA238_BUS_UNDER_VOLTAGE;
break;
case hwmon_in_max_alarm:
reg = INA238_DIAG_ALERT;
mask = INA238_DIAG_ALERT_BUSOL;
break;
case hwmon_in_min_alarm:
reg = INA238_DIAG_ALERT;
mask = INA238_DIAG_ALERT_BUSUL;
break;
default:
return -EOPNOTSUPP;
}
break;
default:
return -EOPNOTSUPP;
}
err = regmap_read(data->regmap, reg, ®val);
if (err < 0)
return err;
switch (attr) {
case hwmon_in_input:
case hwmon_in_max:
case hwmon_in_min:
/* signed register, value in mV */
regval = (s16)regval;
if (channel == 0)
/* gain of 1 -> LSB / 4 */
*val = (regval * INA238_SHUNT_VOLTAGE_LSB) /
(1000 * (4 - data->gain + 1));
else
*val = (regval * INA238_BUS_VOLTAGE_LSB) / 1000;
break;
case hwmon_in_max_alarm:
case hwmon_in_min_alarm:
*val = !!(regval & mask);
break;
}
return 0;
}
static int ina238_write_in(struct device *dev, u32 attr, int channel,
long val)
{
struct ina238_data *data = dev_get_drvdata(dev);
int regval;
if (attr != hwmon_in_max && attr != hwmon_in_min)
return -EOPNOTSUPP;
/* convert decimal to register value */
switch (channel) {
case 0:
/* signed value, clamp to max range +/-163 mV */
regval = clamp_val(val, -163, 163);
regval = (regval * 1000 * (4 - data->gain + 1)) /
INA238_SHUNT_VOLTAGE_LSB;
regval = clamp_val(regval, S16_MIN, S16_MAX);
switch (attr) {
case hwmon_in_max:
return regmap_write(data->regmap,
INA238_SHUNT_OVER_VOLTAGE, regval);
case hwmon_in_min:
return regmap_write(data->regmap,
INA238_SHUNT_UNDER_VOLTAGE, regval);
default:
return -EOPNOTSUPP;
}
case 1:
/* signed value, positive values only. Clamp to max 102.396 V */
regval = clamp_val(val, 0, 102396);
regval = (regval * 1000) / INA238_BUS_VOLTAGE_LSB;
regval = clamp_val(regval, 0, S16_MAX);
switch (attr) {
case hwmon_in_max:
return regmap_write(data->regmap,
INA238_BUS_OVER_VOLTAGE, regval);
case hwmon_in_min:
return regmap_write(data->regmap,
INA238_BUS_UNDER_VOLTAGE, regval);
default:
return -EOPNOTSUPP;
}
default:
return -EOPNOTSUPP;
}
}
static int ina238_read_current(struct device *dev, u32 attr, long *val)
{
struct ina238_data *data = dev_get_drvdata(dev);
int regval;
int err;
switch (attr) {
case hwmon_curr_input:
err = regmap_read(data->regmap, INA238_CURRENT, ®val);
if (err < 0)
return err;
/* Signed register, fixed 1mA current lsb. result in mA */
*val = div_s64((s16)regval * INA238_FIXED_SHUNT * data->gain,
data->rshunt * 4);
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static int ina238_read_power(struct device *dev, u32 attr, long *val)
{
struct ina238_data *data = dev_get_drvdata(dev);
long long power;
int regval;
int err;
switch (attr) {
case hwmon_power_input:
err = ina238_read_reg24(data->client, INA238_POWER, ®val);
if (err)
return err;
/* Fixed 1mA lsb, scaled by 1000000 to have result in uW */
power = div_u64(regval * 1000ULL * INA238_FIXED_SHUNT *
data->gain, 20 * data->rshunt);
/* Clamp value to maximum value of long */
*val = clamp_val(power, 0, LONG_MAX);
break;
case hwmon_power_max:
err = regmap_read(data->regmap, INA238_POWER_LIMIT, ®val);
if (err)
return err;
/*
* Truncated 24-bit compare register, lower 8-bits are
* truncated. Same conversion to/from uW as POWER register.
*/
power = div_u64((regval << 8) * 1000ULL * INA238_FIXED_SHUNT *
data->gain, 20 * data->rshunt);
/* Clamp value to maximum value of long */
*val = clamp_val(power, 0, LONG_MAX);
break;
case hwmon_power_max_alarm:
err = regmap_read(data->regmap, INA238_DIAG_ALERT, ®val);
if (err)
return err;
*val = !!(regval & INA238_DIAG_ALERT_POL);
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static int ina238_write_power(struct device *dev, u32 attr, long val)
{
struct ina238_data *data = dev_get_drvdata(dev);
long regval;
if (attr != hwmon_power_max)
return -EOPNOTSUPP;
/*
* Unsigned postive values. Compared against the 24-bit power register,
* lower 8-bits are truncated. Same conversion to/from uW as POWER
* register.
*/
regval = clamp_val(val, 0, LONG_MAX);
regval = div_u64(val * 20ULL * data->rshunt,
1000ULL * INA238_FIXED_SHUNT * data->gain);
regval = clamp_val(regval >> 8, 0, U16_MAX);
return regmap_write(data->regmap, INA238_POWER_LIMIT, regval);
}
static int ina238_read_temp(struct device *dev, u32 attr, long *val)
{
struct ina238_data *data = dev_get_drvdata(dev);
int regval;
int err;
switch (attr) {
case hwmon_temp_input:
err = regmap_read(data->regmap, INA238_DIE_TEMP, ®val);
if (err)
return err;
/* Signed, bits 15-4 of register, result in mC */
*val = ((s16)regval >> 4) * INA238_DIE_TEMP_LSB;
break;
case hwmon_temp_max:
err = regmap_read(data->regmap, INA238_TEMP_LIMIT, ®val);
if (err)
return err;
/* Signed, bits 15-4 of register, result in mC */
*val = ((s16)regval >> 4) * INA238_DIE_TEMP_LSB;
break;
case hwmon_temp_max_alarm:
err = regmap_read(data->regmap, INA238_DIAG_ALERT, ®val);
if (err)
return err;
*val = !!(regval & INA238_DIAG_ALERT_TMPOL);
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static int ina238_write_temp(struct device *dev, u32 attr, long val)
{
struct ina238_data *data = dev_get_drvdata(dev);
int regval;
if (attr != hwmon_temp_max)
return -EOPNOTSUPP;
/* Signed, bits 15-4 of register */
regval = (val / INA238_DIE_TEMP_LSB) << 4;
regval = clamp_val(regval, S16_MIN, S16_MAX) & 0xfff0;
return regmap_write(data->regmap, INA238_TEMP_LIMIT, regval);
}
static int ina238_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
switch (type) {
case hwmon_in:
return ina238_read_in(dev, attr, channel, val);
case hwmon_curr:
return ina238_read_current(dev, attr, val);
case hwmon_power:
return ina238_read_power(dev, attr, val);
case hwmon_temp:
return ina238_read_temp(dev, attr, val);
default:
return -EOPNOTSUPP;
}
return 0;
}
static int ina238_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
struct ina238_data *data = dev_get_drvdata(dev);
int err;
mutex_lock(&data->config_lock);
switch (type) {
case hwmon_in:
err = ina238_write_in(dev, attr, channel, val);
break;
case hwmon_power:
err = ina238_write_power(dev, attr, val);
break;
case hwmon_temp:
err = ina238_write_temp(dev, attr, val);
break;
default:
err = -EOPNOTSUPP;
break;
}
mutex_unlock(&data->config_lock);
return err;
}
static umode_t ina238_is_visible(const void *drvdata,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
switch (type) {
case hwmon_in:
switch (attr) {
case hwmon_in_input:
case hwmon_in_max_alarm:
case hwmon_in_min_alarm:
return 0444;
case hwmon_in_max:
case hwmon_in_min:
return 0644;
default:
return 0;
}
case hwmon_curr:
switch (attr) {
case hwmon_curr_input:
return 0444;
default:
return 0;
}
case hwmon_power:
switch (attr) {
case hwmon_power_input:
case hwmon_power_max_alarm:
return 0444;
case hwmon_power_max:
return 0644;
default:
return 0;
}
case hwmon_temp:
switch (attr) {
case hwmon_temp_input:
case hwmon_temp_max_alarm:
return 0444;
case hwmon_temp_max:
return 0644;
default:
return 0;
}
default:
return 0;
}
}
#define INA238_HWMON_IN_CONFIG (HWMON_I_INPUT | \
HWMON_I_MAX | HWMON_I_MAX_ALARM | \
HWMON_I_MIN | HWMON_I_MIN_ALARM)
static const struct hwmon_channel_info * const ina238_info[] = {
HWMON_CHANNEL_INFO(in,
/* 0: shunt voltage */
INA238_HWMON_IN_CONFIG,
/* 1: bus voltage */
INA238_HWMON_IN_CONFIG),
HWMON_CHANNEL_INFO(curr,
/* 0: current through shunt */
HWMON_C_INPUT),
HWMON_CHANNEL_INFO(power,
/* 0: power */
HWMON_P_INPUT | HWMON_P_MAX | HWMON_P_MAX_ALARM),
HWMON_CHANNEL_INFO(temp,
/* 0: die temperature */
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_ALARM),
NULL
};
static const struct hwmon_ops ina238_hwmon_ops = {
.is_visible = ina238_is_visible,
.read = ina238_read,
.write = ina238_write,
};
static const struct hwmon_chip_info ina238_chip_info = {
.ops = &ina238_hwmon_ops,
.info = ina238_info,
};
static int ina238_probe(struct i2c_client *client)
{
struct ina2xx_platform_data *pdata = dev_get_platdata(&client->dev);
struct device *dev = &client->dev;
struct device *hwmon_dev;
struct ina238_data *data;
int config;
int ret;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
mutex_init(&data->config_lock);
data->regmap = devm_regmap_init_i2c(client, &ina238_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(dev, "failed to allocate register map\n");
return PTR_ERR(data->regmap);
}
/* load shunt value */
data->rshunt = INA238_RSHUNT_DEFAULT;
if (device_property_read_u32(dev, "shunt-resistor", &data->rshunt) < 0 && pdata)
data->rshunt = pdata->shunt_uohms;
if (data->rshunt == 0) {
dev_err(dev, "invalid shunt resister value %u\n", data->rshunt);
return -EINVAL;
}
/* load shunt gain value */
if (device_property_read_u32(dev, "ti,shunt-gain", &data->gain) < 0)
data->gain = 4; /* Default of ADCRANGE = 0 */
if (data->gain != 1 && data->gain != 4) {
dev_err(dev, "invalid shunt gain value %u\n", data->gain);
return -EINVAL;
}
/* Setup CONFIG register */
config = INA238_CONFIG_DEFAULT;
if (data->gain == 1)
config |= INA238_CONFIG_ADCRANGE; /* ADCRANGE = 1 is /1 */
ret = regmap_write(data->regmap, INA238_CONFIG, config);
if (ret < 0) {
dev_err(dev, "error configuring the device: %d\n", ret);
return -ENODEV;
}
/* Setup ADC_CONFIG register */
ret = regmap_write(data->regmap, INA238_ADC_CONFIG,
INA238_ADC_CONFIG_DEFAULT);
if (ret < 0) {
dev_err(dev, "error configuring the device: %d\n", ret);
return -ENODEV;
}
/* Setup SHUNT_CALIBRATION register with fixed value */
ret = regmap_write(data->regmap, INA238_SHUNT_CALIBRATION,
INA238_CALIBRATION_VALUE);
if (ret < 0) {
dev_err(dev, "error configuring the device: %d\n", ret);
return -ENODEV;
}
/* Setup alert/alarm configuration */
ret = regmap_write(data->regmap, INA238_DIAG_ALERT,
INA238_DIAG_ALERT_DEFAULT);
if (ret < 0) {
dev_err(dev, "error configuring the device: %d\n", ret);
return -ENODEV;
}
hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, data,
&ina238_chip_info,
NULL);
if (IS_ERR(hwmon_dev))
return PTR_ERR(hwmon_dev);
dev_info(dev, "power monitor %s (Rshunt = %u uOhm, gain = %u)\n",
client->name, data->rshunt, data->gain);
return 0;
}
static const struct i2c_device_id ina238_id[] = {
{ "ina238", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ina238_id);
static const struct of_device_id __maybe_unused ina238_of_match[] = {
{ .compatible = "ti,ina238" },
{ },
};
MODULE_DEVICE_TABLE(of, ina238_of_match);
static struct i2c_driver ina238_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "ina238",
.of_match_table = of_match_ptr(ina238_of_match),
},
.probe = ina238_probe,
.id_table = ina238_id,
};
module_i2c_driver(ina238_driver);
MODULE_AUTHOR("Nathan Rossi <[email protected]>");
MODULE_DESCRIPTION("ina238 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/ina238.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* pc87427.c - hardware monitoring driver for the
* National Semiconductor PC87427 Super-I/O chip
* Copyright (C) 2006, 2008, 2010 Jean Delvare <[email protected]>
*
* Supports the following chips:
*
* Chip #vin #fan #pwm #temp devid
* PC87427 - 8 4 6 0xF2
*
* This driver assumes that no more than one chip is present.
* Only fans are fully supported so far. Temperatures are in read-only
* mode, and voltages aren't supported at all.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/platform_device.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/sysfs.h>
#include <linux/ioport.h>
#include <linux/acpi.h>
#include <linux/io.h>
static unsigned short force_id;
module_param(force_id, ushort, 0);
MODULE_PARM_DESC(force_id, "Override the detected device ID");
static struct platform_device *pdev;
#define DRVNAME "pc87427"
/*
* The lock mutex protects both the I/O accesses (needed because the
* device is using banked registers) and the register cache (needed to keep
* the data in the registers and the cache in sync at any time).
*/
struct pc87427_data {
struct device *hwmon_dev;
struct mutex lock;
int address[2];
const char *name;
unsigned long last_updated; /* in jiffies */
u8 fan_enabled; /* bit vector */
u16 fan[8]; /* register values */
u16 fan_min[8]; /* register values */
u8 fan_status[8]; /* register values */
u8 pwm_enabled; /* bit vector */
u8 pwm_auto_ok; /* bit vector */
u8 pwm_enable[4]; /* register values */
u8 pwm[4]; /* register values */
u8 temp_enabled; /* bit vector */
s16 temp[6]; /* register values */
s8 temp_min[6]; /* register values */
s8 temp_max[6]; /* register values */
s8 temp_crit[6]; /* register values */
u8 temp_status[6]; /* register values */
u8 temp_type[6]; /* register values */
};
struct pc87427_sio_data {
unsigned short address[2];
u8 has_fanin;
u8 has_fanout;
};
/*
* Super-I/O registers and operations
*/
#define SIOREG_LDSEL 0x07 /* Logical device select */
#define SIOREG_DEVID 0x20 /* Device ID */
#define SIOREG_CF2 0x22 /* Configuration 2 */
#define SIOREG_CF3 0x23 /* Configuration 3 */
#define SIOREG_CF4 0x24 /* Configuration 4 */
#define SIOREG_CF5 0x25 /* Configuration 5 */
#define SIOREG_CFB 0x2B /* Configuration B */
#define SIOREG_CFC 0x2C /* Configuration C */
#define SIOREG_CFD 0x2D /* Configuration D */
#define SIOREG_ACT 0x30 /* Device activation */
#define SIOREG_MAP 0x50 /* I/O or memory mapping */
#define SIOREG_IOBASE 0x60 /* I/O base address */
static const u8 logdev[2] = { 0x09, 0x14 };
static const char *logdev_str[2] = { DRVNAME " FMC", DRVNAME " HMC" };
#define LD_FAN 0
#define LD_IN 1
#define LD_TEMP 1
static inline int superio_enter(int sioaddr)
{
if (!request_muxed_region(sioaddr, 2, DRVNAME))
return -EBUSY;
return 0;
}
static inline void superio_outb(int sioaddr, int reg, int val)
{
outb(reg, sioaddr);
outb(val, sioaddr + 1);
}
static inline int superio_inb(int sioaddr, int reg)
{
outb(reg, sioaddr);
return inb(sioaddr + 1);
}
static inline void superio_exit(int sioaddr)
{
outb(0x02, sioaddr);
outb(0x02, sioaddr + 1);
release_region(sioaddr, 2);
}
/*
* Logical devices
*/
#define REGION_LENGTH 32
#define PC87427_REG_BANK 0x0f
#define BANK_FM(nr) (nr)
#define BANK_FT(nr) (0x08 + (nr))
#define BANK_FC(nr) (0x10 + (nr) * 2)
#define BANK_TM(nr) (nr)
#define BANK_VM(nr) (0x08 + (nr))
/*
* I/O access functions
*/
/* ldi is the logical device index */
static inline int pc87427_read8(struct pc87427_data *data, u8 ldi, u8 reg)
{
return inb(data->address[ldi] + reg);
}
/* Must be called with data->lock held, except during init */
static inline int pc87427_read8_bank(struct pc87427_data *data, u8 ldi,
u8 bank, u8 reg)
{
outb(bank, data->address[ldi] + PC87427_REG_BANK);
return inb(data->address[ldi] + reg);
}
/* Must be called with data->lock held, except during init */
static inline void pc87427_write8_bank(struct pc87427_data *data, u8 ldi,
u8 bank, u8 reg, u8 value)
{
outb(bank, data->address[ldi] + PC87427_REG_BANK);
outb(value, data->address[ldi] + reg);
}
/*
* Fan registers and conversions
*/
/* fan data registers are 16-bit wide */
#define PC87427_REG_FAN 0x12
#define PC87427_REG_FAN_MIN 0x14
#define PC87427_REG_FAN_STATUS 0x10
#define FAN_STATUS_STALL (1 << 3)
#define FAN_STATUS_LOSPD (1 << 1)
#define FAN_STATUS_MONEN (1 << 0)
/*
* Dedicated function to read all registers related to a given fan input.
* This saves us quite a few locks and bank selections.
* Must be called with data->lock held.
* nr is from 0 to 7
*/
static void pc87427_readall_fan(struct pc87427_data *data, u8 nr)
{
int iobase = data->address[LD_FAN];
outb(BANK_FM(nr), iobase + PC87427_REG_BANK);
data->fan[nr] = inw(iobase + PC87427_REG_FAN);
data->fan_min[nr] = inw(iobase + PC87427_REG_FAN_MIN);
data->fan_status[nr] = inb(iobase + PC87427_REG_FAN_STATUS);
/* Clear fan alarm bits */
outb(data->fan_status[nr], iobase + PC87427_REG_FAN_STATUS);
}
/*
* The 2 LSB of fan speed registers are used for something different.
* The actual 2 LSB of the measurements are not available.
*/
static inline unsigned long fan_from_reg(u16 reg)
{
reg &= 0xfffc;
if (reg == 0x0000 || reg == 0xfffc)
return 0;
return 5400000UL / reg;
}
/* The 2 LSB of the fan speed limit registers are not significant. */
static inline u16 fan_to_reg(unsigned long val)
{
if (val < 83UL)
return 0xffff;
if (val >= 1350000UL)
return 0x0004;
return ((1350000UL + val / 2) / val) << 2;
}
/*
* PWM registers and conversions
*/
#define PC87427_REG_PWM_ENABLE 0x10
#define PC87427_REG_PWM_DUTY 0x12
#define PWM_ENABLE_MODE_MASK (7 << 4)
#define PWM_ENABLE_CTLEN (1 << 0)
#define PWM_MODE_MANUAL (0 << 4)
#define PWM_MODE_AUTO (1 << 4)
#define PWM_MODE_OFF (2 << 4)
#define PWM_MODE_ON (7 << 4)
/*
* Dedicated function to read all registers related to a given PWM output.
* This saves us quite a few locks and bank selections.
* Must be called with data->lock held.
* nr is from 0 to 3
*/
static void pc87427_readall_pwm(struct pc87427_data *data, u8 nr)
{
int iobase = data->address[LD_FAN];
outb(BANK_FC(nr), iobase + PC87427_REG_BANK);
data->pwm_enable[nr] = inb(iobase + PC87427_REG_PWM_ENABLE);
data->pwm[nr] = inb(iobase + PC87427_REG_PWM_DUTY);
}
static inline int pwm_enable_from_reg(u8 reg)
{
switch (reg & PWM_ENABLE_MODE_MASK) {
case PWM_MODE_ON:
return 0;
case PWM_MODE_MANUAL:
case PWM_MODE_OFF:
return 1;
case PWM_MODE_AUTO:
return 2;
default:
return -EPROTO;
}
}
static inline u8 pwm_enable_to_reg(unsigned long val, u8 pwmval)
{
switch (val) {
default:
return PWM_MODE_ON;
case 1:
return pwmval ? PWM_MODE_MANUAL : PWM_MODE_OFF;
case 2:
return PWM_MODE_AUTO;
}
}
/*
* Temperature registers and conversions
*/
#define PC87427_REG_TEMP_STATUS 0x10
#define PC87427_REG_TEMP 0x14
#define PC87427_REG_TEMP_MAX 0x18
#define PC87427_REG_TEMP_MIN 0x19
#define PC87427_REG_TEMP_CRIT 0x1a
#define PC87427_REG_TEMP_TYPE 0x1d
#define TEMP_STATUS_CHANEN (1 << 0)
#define TEMP_STATUS_LOWFLG (1 << 1)
#define TEMP_STATUS_HIGHFLG (1 << 2)
#define TEMP_STATUS_CRITFLG (1 << 3)
#define TEMP_STATUS_SENSERR (1 << 5)
#define TEMP_TYPE_MASK (3 << 5)
#define TEMP_TYPE_THERMISTOR (1 << 5)
#define TEMP_TYPE_REMOTE_DIODE (2 << 5)
#define TEMP_TYPE_LOCAL_DIODE (3 << 5)
/*
* Dedicated function to read all registers related to a given temperature
* input. This saves us quite a few locks and bank selections.
* Must be called with data->lock held.
* nr is from 0 to 5
*/
static void pc87427_readall_temp(struct pc87427_data *data, u8 nr)
{
int iobase = data->address[LD_TEMP];
outb(BANK_TM(nr), iobase + PC87427_REG_BANK);
data->temp[nr] = le16_to_cpu(inw(iobase + PC87427_REG_TEMP));
data->temp_max[nr] = inb(iobase + PC87427_REG_TEMP_MAX);
data->temp_min[nr] = inb(iobase + PC87427_REG_TEMP_MIN);
data->temp_crit[nr] = inb(iobase + PC87427_REG_TEMP_CRIT);
data->temp_type[nr] = inb(iobase + PC87427_REG_TEMP_TYPE);
data->temp_status[nr] = inb(iobase + PC87427_REG_TEMP_STATUS);
/* Clear fan alarm bits */
outb(data->temp_status[nr], iobase + PC87427_REG_TEMP_STATUS);
}
static inline unsigned int temp_type_from_reg(u8 reg)
{
switch (reg & TEMP_TYPE_MASK) {
case TEMP_TYPE_THERMISTOR:
return 4;
case TEMP_TYPE_REMOTE_DIODE:
case TEMP_TYPE_LOCAL_DIODE:
return 3;
default:
return 0;
}
}
/*
* We assume 8-bit thermal sensors; 9-bit thermal sensors are possible
* too, but I have no idea how to figure out when they are used.
*/
static inline long temp_from_reg(s16 reg)
{
return reg * 1000 / 256;
}
static inline long temp_from_reg8(s8 reg)
{
return reg * 1000;
}
/*
* Data interface
*/
static struct pc87427_data *pc87427_update_device(struct device *dev)
{
struct pc87427_data *data = dev_get_drvdata(dev);
int i;
mutex_lock(&data->lock);
if (!time_after(jiffies, data->last_updated + HZ)
&& data->last_updated)
goto done;
/* Fans */
for (i = 0; i < 8; i++) {
if (!(data->fan_enabled & (1 << i)))
continue;
pc87427_readall_fan(data, i);
}
/* PWM outputs */
for (i = 0; i < 4; i++) {
if (!(data->pwm_enabled & (1 << i)))
continue;
pc87427_readall_pwm(data, i);
}
/* Temperature channels */
for (i = 0; i < 6; i++) {
if (!(data->temp_enabled & (1 << i)))
continue;
pc87427_readall_temp(data, i);
}
data->last_updated = jiffies;
done:
mutex_unlock(&data->lock);
return data;
}
static ssize_t fan_input_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%lu\n", fan_from_reg(data->fan[nr]));
}
static ssize_t fan_min_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%lu\n", fan_from_reg(data->fan_min[nr]));
}
static ssize_t fan_alarm_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%d\n", !!(data->fan_status[nr]
& FAN_STATUS_LOSPD));
}
static ssize_t fan_fault_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%d\n", !!(data->fan_status[nr]
& FAN_STATUS_STALL));
}
static ssize_t fan_min_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct pc87427_data *data = dev_get_drvdata(dev);
int nr = to_sensor_dev_attr(devattr)->index;
unsigned long val;
int iobase = data->address[LD_FAN];
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
mutex_lock(&data->lock);
outb(BANK_FM(nr), iobase + PC87427_REG_BANK);
/*
* The low speed limit registers are read-only while monitoring
* is enabled, so we have to disable monitoring, then change the
* limit, and finally enable monitoring again.
*/
outb(0, iobase + PC87427_REG_FAN_STATUS);
data->fan_min[nr] = fan_to_reg(val);
outw(data->fan_min[nr], iobase + PC87427_REG_FAN_MIN);
outb(FAN_STATUS_MONEN, iobase + PC87427_REG_FAN_STATUS);
mutex_unlock(&data->lock);
return count;
}
static SENSOR_DEVICE_ATTR_RO(fan1_input, fan_input, 0);
static SENSOR_DEVICE_ATTR_RO(fan2_input, fan_input, 1);
static SENSOR_DEVICE_ATTR_RO(fan3_input, fan_input, 2);
static SENSOR_DEVICE_ATTR_RO(fan4_input, fan_input, 3);
static SENSOR_DEVICE_ATTR_RO(fan5_input, fan_input, 4);
static SENSOR_DEVICE_ATTR_RO(fan6_input, fan_input, 5);
static SENSOR_DEVICE_ATTR_RO(fan7_input, fan_input, 6);
static SENSOR_DEVICE_ATTR_RO(fan8_input, fan_input, 7);
static SENSOR_DEVICE_ATTR_RW(fan1_min, fan_min, 0);
static SENSOR_DEVICE_ATTR_RW(fan2_min, fan_min, 1);
static SENSOR_DEVICE_ATTR_RW(fan3_min, fan_min, 2);
static SENSOR_DEVICE_ATTR_RW(fan4_min, fan_min, 3);
static SENSOR_DEVICE_ATTR_RW(fan5_min, fan_min, 4);
static SENSOR_DEVICE_ATTR_RW(fan6_min, fan_min, 5);
static SENSOR_DEVICE_ATTR_RW(fan7_min, fan_min, 6);
static SENSOR_DEVICE_ATTR_RW(fan8_min, fan_min, 7);
static SENSOR_DEVICE_ATTR_RO(fan1_alarm, fan_alarm, 0);
static SENSOR_DEVICE_ATTR_RO(fan2_alarm, fan_alarm, 1);
static SENSOR_DEVICE_ATTR_RO(fan3_alarm, fan_alarm, 2);
static SENSOR_DEVICE_ATTR_RO(fan4_alarm, fan_alarm, 3);
static SENSOR_DEVICE_ATTR_RO(fan5_alarm, fan_alarm, 4);
static SENSOR_DEVICE_ATTR_RO(fan6_alarm, fan_alarm, 5);
static SENSOR_DEVICE_ATTR_RO(fan7_alarm, fan_alarm, 6);
static SENSOR_DEVICE_ATTR_RO(fan8_alarm, fan_alarm, 7);
static SENSOR_DEVICE_ATTR_RO(fan1_fault, fan_fault, 0);
static SENSOR_DEVICE_ATTR_RO(fan2_fault, fan_fault, 1);
static SENSOR_DEVICE_ATTR_RO(fan3_fault, fan_fault, 2);
static SENSOR_DEVICE_ATTR_RO(fan4_fault, fan_fault, 3);
static SENSOR_DEVICE_ATTR_RO(fan5_fault, fan_fault, 4);
static SENSOR_DEVICE_ATTR_RO(fan6_fault, fan_fault, 5);
static SENSOR_DEVICE_ATTR_RO(fan7_fault, fan_fault, 6);
static SENSOR_DEVICE_ATTR_RO(fan8_fault, fan_fault, 7);
static struct attribute *pc87427_attributes_fan[8][5] = {
{
&sensor_dev_attr_fan1_input.dev_attr.attr,
&sensor_dev_attr_fan1_min.dev_attr.attr,
&sensor_dev_attr_fan1_alarm.dev_attr.attr,
&sensor_dev_attr_fan1_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_fan2_input.dev_attr.attr,
&sensor_dev_attr_fan2_min.dev_attr.attr,
&sensor_dev_attr_fan2_alarm.dev_attr.attr,
&sensor_dev_attr_fan2_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_fan3_input.dev_attr.attr,
&sensor_dev_attr_fan3_min.dev_attr.attr,
&sensor_dev_attr_fan3_alarm.dev_attr.attr,
&sensor_dev_attr_fan3_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_fan4_input.dev_attr.attr,
&sensor_dev_attr_fan4_min.dev_attr.attr,
&sensor_dev_attr_fan4_alarm.dev_attr.attr,
&sensor_dev_attr_fan4_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_fan5_input.dev_attr.attr,
&sensor_dev_attr_fan5_min.dev_attr.attr,
&sensor_dev_attr_fan5_alarm.dev_attr.attr,
&sensor_dev_attr_fan5_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_fan6_input.dev_attr.attr,
&sensor_dev_attr_fan6_min.dev_attr.attr,
&sensor_dev_attr_fan6_alarm.dev_attr.attr,
&sensor_dev_attr_fan6_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_fan7_input.dev_attr.attr,
&sensor_dev_attr_fan7_min.dev_attr.attr,
&sensor_dev_attr_fan7_alarm.dev_attr.attr,
&sensor_dev_attr_fan7_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_fan8_input.dev_attr.attr,
&sensor_dev_attr_fan8_min.dev_attr.attr,
&sensor_dev_attr_fan8_alarm.dev_attr.attr,
&sensor_dev_attr_fan8_fault.dev_attr.attr,
NULL
}
};
static const struct attribute_group pc87427_group_fan[8] = {
{ .attrs = pc87427_attributes_fan[0] },
{ .attrs = pc87427_attributes_fan[1] },
{ .attrs = pc87427_attributes_fan[2] },
{ .attrs = pc87427_attributes_fan[3] },
{ .attrs = pc87427_attributes_fan[4] },
{ .attrs = pc87427_attributes_fan[5] },
{ .attrs = pc87427_attributes_fan[6] },
{ .attrs = pc87427_attributes_fan[7] },
};
/*
* Must be called with data->lock held and pc87427_readall_pwm() freshly
* called
*/
static void update_pwm_enable(struct pc87427_data *data, int nr, u8 mode)
{
int iobase = data->address[LD_FAN];
data->pwm_enable[nr] &= ~PWM_ENABLE_MODE_MASK;
data->pwm_enable[nr] |= mode;
outb(data->pwm_enable[nr], iobase + PC87427_REG_PWM_ENABLE);
}
static ssize_t pwm_enable_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
int pwm_enable;
pwm_enable = pwm_enable_from_reg(data->pwm_enable[nr]);
if (pwm_enable < 0)
return pwm_enable;
return sprintf(buf, "%d\n", pwm_enable);
}
static ssize_t pwm_enable_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct pc87427_data *data = dev_get_drvdata(dev);
int nr = to_sensor_dev_attr(devattr)->index;
unsigned long val;
if (kstrtoul(buf, 10, &val) < 0 || val > 2)
return -EINVAL;
/* Can't go to automatic mode if it isn't configured */
if (val == 2 && !(data->pwm_auto_ok & (1 << nr)))
return -EINVAL;
mutex_lock(&data->lock);
pc87427_readall_pwm(data, nr);
update_pwm_enable(data, nr, pwm_enable_to_reg(val, data->pwm[nr]));
mutex_unlock(&data->lock);
return count;
}
static ssize_t pwm_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%d\n", (int)data->pwm[nr]);
}
static ssize_t pwm_store(struct device *dev, struct device_attribute *devattr,
const char *buf, size_t count)
{
struct pc87427_data *data = dev_get_drvdata(dev);
int nr = to_sensor_dev_attr(devattr)->index;
unsigned long val;
int iobase = data->address[LD_FAN];
u8 mode;
if (kstrtoul(buf, 10, &val) < 0 || val > 0xff)
return -EINVAL;
mutex_lock(&data->lock);
pc87427_readall_pwm(data, nr);
mode = data->pwm_enable[nr] & PWM_ENABLE_MODE_MASK;
if (mode != PWM_MODE_MANUAL && mode != PWM_MODE_OFF) {
dev_notice(dev,
"Can't set PWM%d duty cycle while not in manual mode\n",
nr + 1);
mutex_unlock(&data->lock);
return -EPERM;
}
/* We may have to change the mode */
if (mode == PWM_MODE_MANUAL && val == 0) {
/* Transition from Manual to Off */
update_pwm_enable(data, nr, PWM_MODE_OFF);
mode = PWM_MODE_OFF;
dev_dbg(dev, "Switching PWM%d from %s to %s\n", nr + 1,
"manual", "off");
} else if (mode == PWM_MODE_OFF && val != 0) {
/* Transition from Off to Manual */
update_pwm_enable(data, nr, PWM_MODE_MANUAL);
mode = PWM_MODE_MANUAL;
dev_dbg(dev, "Switching PWM%d from %s to %s\n", nr + 1,
"off", "manual");
}
data->pwm[nr] = val;
if (mode == PWM_MODE_MANUAL)
outb(val, iobase + PC87427_REG_PWM_DUTY);
mutex_unlock(&data->lock);
return count;
}
static SENSOR_DEVICE_ATTR_RW(pwm1_enable, pwm_enable, 0);
static SENSOR_DEVICE_ATTR_RW(pwm2_enable, pwm_enable, 1);
static SENSOR_DEVICE_ATTR_RW(pwm3_enable, pwm_enable, 2);
static SENSOR_DEVICE_ATTR_RW(pwm4_enable, pwm_enable, 3);
static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1);
static SENSOR_DEVICE_ATTR_RW(pwm3, pwm, 2);
static SENSOR_DEVICE_ATTR_RW(pwm4, pwm, 3);
static struct attribute *pc87427_attributes_pwm[4][3] = {
{
&sensor_dev_attr_pwm1_enable.dev_attr.attr,
&sensor_dev_attr_pwm1.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_pwm2_enable.dev_attr.attr,
&sensor_dev_attr_pwm2.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_pwm3_enable.dev_attr.attr,
&sensor_dev_attr_pwm3.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_pwm4_enable.dev_attr.attr,
&sensor_dev_attr_pwm4.dev_attr.attr,
NULL
}
};
static const struct attribute_group pc87427_group_pwm[4] = {
{ .attrs = pc87427_attributes_pwm[0] },
{ .attrs = pc87427_attributes_pwm[1] },
{ .attrs = pc87427_attributes_pwm[2] },
{ .attrs = pc87427_attributes_pwm[3] },
};
static ssize_t temp_input_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%ld\n", temp_from_reg(data->temp[nr]));
}
static ssize_t temp_min_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%ld\n", temp_from_reg8(data->temp_min[nr]));
}
static ssize_t temp_max_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%ld\n", temp_from_reg8(data->temp_max[nr]));
}
static ssize_t temp_crit_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%ld\n", temp_from_reg8(data->temp_crit[nr]));
}
static ssize_t temp_type_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%u\n", temp_type_from_reg(data->temp_type[nr]));
}
static ssize_t temp_min_alarm_show(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%d\n", !!(data->temp_status[nr]
& TEMP_STATUS_LOWFLG));
}
static ssize_t temp_max_alarm_show(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%d\n", !!(data->temp_status[nr]
& TEMP_STATUS_HIGHFLG));
}
static ssize_t temp_crit_alarm_show(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%d\n", !!(data->temp_status[nr]
& TEMP_STATUS_CRITFLG));
}
static ssize_t temp_fault_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct pc87427_data *data = pc87427_update_device(dev);
int nr = to_sensor_dev_attr(devattr)->index;
return sprintf(buf, "%d\n", !!(data->temp_status[nr]
& TEMP_STATUS_SENSERR));
}
static SENSOR_DEVICE_ATTR_RO(temp1_input, temp_input, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_input, temp_input, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_input, temp_input, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_input, temp_input, 3);
static SENSOR_DEVICE_ATTR_RO(temp5_input, temp_input, 4);
static SENSOR_DEVICE_ATTR_RO(temp6_input, temp_input, 5);
static SENSOR_DEVICE_ATTR_RO(temp1_min, temp_min, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_min, temp_min, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_min, temp_min, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_min, temp_min, 3);
static SENSOR_DEVICE_ATTR_RO(temp5_min, temp_min, 4);
static SENSOR_DEVICE_ATTR_RO(temp6_min, temp_min, 5);
static SENSOR_DEVICE_ATTR_RO(temp1_max, temp_max, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_max, temp_max, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_max, temp_max, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_max, temp_max, 3);
static SENSOR_DEVICE_ATTR_RO(temp5_max, temp_max, 4);
static SENSOR_DEVICE_ATTR_RO(temp6_max, temp_max, 5);
static SENSOR_DEVICE_ATTR_RO(temp1_crit, temp_crit, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_crit, temp_crit, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_crit, temp_crit, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_crit, temp_crit, 3);
static SENSOR_DEVICE_ATTR_RO(temp5_crit, temp_crit, 4);
static SENSOR_DEVICE_ATTR_RO(temp6_crit, temp_crit, 5);
static SENSOR_DEVICE_ATTR_RO(temp1_type, temp_type, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_type, temp_type, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_type, temp_type, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_type, temp_type, 3);
static SENSOR_DEVICE_ATTR_RO(temp5_type, temp_type, 4);
static SENSOR_DEVICE_ATTR_RO(temp6_type, temp_type, 5);
static SENSOR_DEVICE_ATTR_RO(temp1_min_alarm, temp_min_alarm, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_min_alarm, temp_min_alarm, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_min_alarm, temp_min_alarm, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_min_alarm, temp_min_alarm, 3);
static SENSOR_DEVICE_ATTR_RO(temp5_min_alarm, temp_min_alarm, 4);
static SENSOR_DEVICE_ATTR_RO(temp6_min_alarm, temp_min_alarm, 5);
static SENSOR_DEVICE_ATTR_RO(temp1_max_alarm, temp_max_alarm, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_max_alarm, temp_max_alarm, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_max_alarm, temp_max_alarm, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_max_alarm, temp_max_alarm, 3);
static SENSOR_DEVICE_ATTR_RO(temp5_max_alarm, temp_max_alarm, 4);
static SENSOR_DEVICE_ATTR_RO(temp6_max_alarm, temp_max_alarm, 5);
static SENSOR_DEVICE_ATTR_RO(temp1_crit_alarm, temp_crit_alarm, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_crit_alarm, temp_crit_alarm, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_crit_alarm, temp_crit_alarm, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_crit_alarm, temp_crit_alarm, 3);
static SENSOR_DEVICE_ATTR_RO(temp5_crit_alarm, temp_crit_alarm, 4);
static SENSOR_DEVICE_ATTR_RO(temp6_crit_alarm, temp_crit_alarm, 5);
static SENSOR_DEVICE_ATTR_RO(temp1_fault, temp_fault, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_fault, temp_fault, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_fault, temp_fault, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_fault, temp_fault, 3);
static SENSOR_DEVICE_ATTR_RO(temp5_fault, temp_fault, 4);
static SENSOR_DEVICE_ATTR_RO(temp6_fault, temp_fault, 5);
static struct attribute *pc87427_attributes_temp[6][10] = {
{
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_min.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp1_crit.dev_attr.attr,
&sensor_dev_attr_temp1_type.dev_attr.attr,
&sensor_dev_attr_temp1_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp2_min.dev_attr.attr,
&sensor_dev_attr_temp2_max.dev_attr.attr,
&sensor_dev_attr_temp2_crit.dev_attr.attr,
&sensor_dev_attr_temp2_type.dev_attr.attr,
&sensor_dev_attr_temp2_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_temp3_input.dev_attr.attr,
&sensor_dev_attr_temp3_min.dev_attr.attr,
&sensor_dev_attr_temp3_max.dev_attr.attr,
&sensor_dev_attr_temp3_crit.dev_attr.attr,
&sensor_dev_attr_temp3_type.dev_attr.attr,
&sensor_dev_attr_temp3_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp3_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp3_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp3_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_temp4_input.dev_attr.attr,
&sensor_dev_attr_temp4_min.dev_attr.attr,
&sensor_dev_attr_temp4_max.dev_attr.attr,
&sensor_dev_attr_temp4_crit.dev_attr.attr,
&sensor_dev_attr_temp4_type.dev_attr.attr,
&sensor_dev_attr_temp4_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp4_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp4_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp4_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_temp5_input.dev_attr.attr,
&sensor_dev_attr_temp5_min.dev_attr.attr,
&sensor_dev_attr_temp5_max.dev_attr.attr,
&sensor_dev_attr_temp5_crit.dev_attr.attr,
&sensor_dev_attr_temp5_type.dev_attr.attr,
&sensor_dev_attr_temp5_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp5_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp5_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp5_fault.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_temp6_input.dev_attr.attr,
&sensor_dev_attr_temp6_min.dev_attr.attr,
&sensor_dev_attr_temp6_max.dev_attr.attr,
&sensor_dev_attr_temp6_crit.dev_attr.attr,
&sensor_dev_attr_temp6_type.dev_attr.attr,
&sensor_dev_attr_temp6_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp6_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp6_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp6_fault.dev_attr.attr,
NULL
}
};
static const struct attribute_group pc87427_group_temp[6] = {
{ .attrs = pc87427_attributes_temp[0] },
{ .attrs = pc87427_attributes_temp[1] },
{ .attrs = pc87427_attributes_temp[2] },
{ .attrs = pc87427_attributes_temp[3] },
{ .attrs = pc87427_attributes_temp[4] },
{ .attrs = pc87427_attributes_temp[5] },
};
static ssize_t name_show(struct device *dev, struct device_attribute
*devattr, char *buf)
{
struct pc87427_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%s\n", data->name);
}
static DEVICE_ATTR_RO(name);
/*
* Device detection, attach and detach
*/
static int pc87427_request_regions(struct platform_device *pdev,
int count)
{
struct resource *res;
int i;
for (i = 0; i < count; i++) {
res = platform_get_resource(pdev, IORESOURCE_IO, i);
if (!res) {
dev_err(&pdev->dev, "Missing resource #%d\n", i);
return -ENOENT;
}
if (!devm_request_region(&pdev->dev, res->start,
resource_size(res), DRVNAME)) {
dev_err(&pdev->dev,
"Failed to request region 0x%lx-0x%lx\n",
(unsigned long)res->start,
(unsigned long)res->end);
return -EBUSY;
}
}
return 0;
}
static void pc87427_init_device(struct device *dev)
{
struct pc87427_sio_data *sio_data = dev_get_platdata(dev);
struct pc87427_data *data = dev_get_drvdata(dev);
int i;
u8 reg;
/* The FMC module should be ready */
reg = pc87427_read8(data, LD_FAN, PC87427_REG_BANK);
if (!(reg & 0x80))
dev_warn(dev, "%s module not ready!\n", "FMC");
/* Check which fans are enabled */
for (i = 0; i < 8; i++) {
if (!(sio_data->has_fanin & (1 << i))) /* Not wired */
continue;
reg = pc87427_read8_bank(data, LD_FAN, BANK_FM(i),
PC87427_REG_FAN_STATUS);
if (reg & FAN_STATUS_MONEN)
data->fan_enabled |= (1 << i);
}
if (!data->fan_enabled) {
dev_dbg(dev, "Enabling monitoring of all fans\n");
for (i = 0; i < 8; i++) {
if (!(sio_data->has_fanin & (1 << i))) /* Not wired */
continue;
pc87427_write8_bank(data, LD_FAN, BANK_FM(i),
PC87427_REG_FAN_STATUS,
FAN_STATUS_MONEN);
}
data->fan_enabled = sio_data->has_fanin;
}
/* Check which PWM outputs are enabled */
for (i = 0; i < 4; i++) {
if (!(sio_data->has_fanout & (1 << i))) /* Not wired */
continue;
reg = pc87427_read8_bank(data, LD_FAN, BANK_FC(i),
PC87427_REG_PWM_ENABLE);
if (reg & PWM_ENABLE_CTLEN)
data->pwm_enabled |= (1 << i);
/*
* We don't expose an interface to reconfigure the automatic
* fan control mode, so only allow to return to this mode if
* it was originally set.
*/
if ((reg & PWM_ENABLE_MODE_MASK) == PWM_MODE_AUTO) {
dev_dbg(dev, "PWM%d is in automatic control mode\n",
i + 1);
data->pwm_auto_ok |= (1 << i);
}
}
/* The HMC module should be ready */
reg = pc87427_read8(data, LD_TEMP, PC87427_REG_BANK);
if (!(reg & 0x80))
dev_warn(dev, "%s module not ready!\n", "HMC");
/* Check which temperature channels are enabled */
for (i = 0; i < 6; i++) {
reg = pc87427_read8_bank(data, LD_TEMP, BANK_TM(i),
PC87427_REG_TEMP_STATUS);
if (reg & TEMP_STATUS_CHANEN)
data->temp_enabled |= (1 << i);
}
}
static void pc87427_remove_files(struct device *dev)
{
struct pc87427_data *data = dev_get_drvdata(dev);
int i;
device_remove_file(dev, &dev_attr_name);
for (i = 0; i < 8; i++) {
if (!(data->fan_enabled & (1 << i)))
continue;
sysfs_remove_group(&dev->kobj, &pc87427_group_fan[i]);
}
for (i = 0; i < 4; i++) {
if (!(data->pwm_enabled & (1 << i)))
continue;
sysfs_remove_group(&dev->kobj, &pc87427_group_pwm[i]);
}
for (i = 0; i < 6; i++) {
if (!(data->temp_enabled & (1 << i)))
continue;
sysfs_remove_group(&dev->kobj, &pc87427_group_temp[i]);
}
}
static int pc87427_probe(struct platform_device *pdev)
{
struct pc87427_sio_data *sio_data = dev_get_platdata(&pdev->dev);
struct pc87427_data *data;
int i, err, res_count;
data = devm_kzalloc(&pdev->dev, sizeof(struct pc87427_data),
GFP_KERNEL);
if (!data)
return -ENOMEM;
data->address[0] = sio_data->address[0];
data->address[1] = sio_data->address[1];
res_count = (data->address[0] != 0) + (data->address[1] != 0);
err = pc87427_request_regions(pdev, res_count);
if (err)
return err;
mutex_init(&data->lock);
data->name = "pc87427";
platform_set_drvdata(pdev, data);
pc87427_init_device(&pdev->dev);
/* Register sysfs hooks */
err = device_create_file(&pdev->dev, &dev_attr_name);
if (err)
return err;
for (i = 0; i < 8; i++) {
if (!(data->fan_enabled & (1 << i)))
continue;
err = sysfs_create_group(&pdev->dev.kobj,
&pc87427_group_fan[i]);
if (err)
goto exit_remove_files;
}
for (i = 0; i < 4; i++) {
if (!(data->pwm_enabled & (1 << i)))
continue;
err = sysfs_create_group(&pdev->dev.kobj,
&pc87427_group_pwm[i]);
if (err)
goto exit_remove_files;
}
for (i = 0; i < 6; i++) {
if (!(data->temp_enabled & (1 << i)))
continue;
err = sysfs_create_group(&pdev->dev.kobj,
&pc87427_group_temp[i]);
if (err)
goto exit_remove_files;
}
data->hwmon_dev = hwmon_device_register(&pdev->dev);
if (IS_ERR(data->hwmon_dev)) {
err = PTR_ERR(data->hwmon_dev);
dev_err(&pdev->dev, "Class registration failed (%d)\n", err);
goto exit_remove_files;
}
return 0;
exit_remove_files:
pc87427_remove_files(&pdev->dev);
return err;
}
static int pc87427_remove(struct platform_device *pdev)
{
struct pc87427_data *data = platform_get_drvdata(pdev);
hwmon_device_unregister(data->hwmon_dev);
pc87427_remove_files(&pdev->dev);
return 0;
}
static struct platform_driver pc87427_driver = {
.driver = {
.name = DRVNAME,
},
.probe = pc87427_probe,
.remove = pc87427_remove,
};
static int __init pc87427_device_add(const struct pc87427_sio_data *sio_data)
{
struct resource res[2] = {
{ .flags = IORESOURCE_IO },
{ .flags = IORESOURCE_IO },
};
int err, i, res_count;
res_count = 0;
for (i = 0; i < 2; i++) {
if (!sio_data->address[i])
continue;
res[res_count].start = sio_data->address[i];
res[res_count].end = sio_data->address[i] + REGION_LENGTH - 1;
res[res_count].name = logdev_str[i];
err = acpi_check_resource_conflict(&res[res_count]);
if (err)
goto exit;
res_count++;
}
pdev = platform_device_alloc(DRVNAME, res[0].start);
if (!pdev) {
err = -ENOMEM;
pr_err("Device allocation failed\n");
goto exit;
}
err = platform_device_add_resources(pdev, res, res_count);
if (err) {
pr_err("Device resource addition failed (%d)\n", err);
goto exit_device_put;
}
err = platform_device_add_data(pdev, sio_data,
sizeof(struct pc87427_sio_data));
if (err) {
pr_err("Platform data allocation failed\n");
goto exit_device_put;
}
err = platform_device_add(pdev);
if (err) {
pr_err("Device addition failed (%d)\n", err);
goto exit_device_put;
}
return 0;
exit_device_put:
platform_device_put(pdev);
exit:
return err;
}
static int __init pc87427_find(int sioaddr, struct pc87427_sio_data *sio_data)
{
u16 val;
u8 cfg, cfg_b;
int i, err;
err = superio_enter(sioaddr);
if (err)
return err;
/* Identify device */
val = force_id ? force_id : superio_inb(sioaddr, SIOREG_DEVID);
if (val != 0xf2) { /* PC87427 */
err = -ENODEV;
goto exit;
}
for (i = 0; i < 2; i++) {
sio_data->address[i] = 0;
/* Select logical device */
superio_outb(sioaddr, SIOREG_LDSEL, logdev[i]);
val = superio_inb(sioaddr, SIOREG_ACT);
if (!(val & 0x01)) {
pr_info("Logical device 0x%02x not activated\n",
logdev[i]);
continue;
}
val = superio_inb(sioaddr, SIOREG_MAP);
if (val & 0x01) {
pr_warn("Logical device 0x%02x is memory-mapped, can't use\n",
logdev[i]);
continue;
}
val = (superio_inb(sioaddr, SIOREG_IOBASE) << 8)
| superio_inb(sioaddr, SIOREG_IOBASE + 1);
if (!val) {
pr_info("I/O base address not set for logical device 0x%02x\n",
logdev[i]);
continue;
}
sio_data->address[i] = val;
}
/* No point in loading the driver if everything is disabled */
if (!sio_data->address[0] && !sio_data->address[1]) {
err = -ENODEV;
goto exit;
}
/* Check which fan inputs are wired */
sio_data->has_fanin = (1 << 2) | (1 << 3); /* FANIN2, FANIN3 */
cfg = superio_inb(sioaddr, SIOREG_CF2);
if (!(cfg & (1 << 3)))
sio_data->has_fanin |= (1 << 0); /* FANIN0 */
if (!(cfg & (1 << 2)))
sio_data->has_fanin |= (1 << 4); /* FANIN4 */
cfg = superio_inb(sioaddr, SIOREG_CFD);
if (!(cfg & (1 << 0)))
sio_data->has_fanin |= (1 << 1); /* FANIN1 */
cfg = superio_inb(sioaddr, SIOREG_CF4);
if (!(cfg & (1 << 0)))
sio_data->has_fanin |= (1 << 7); /* FANIN7 */
cfg_b = superio_inb(sioaddr, SIOREG_CFB);
if (!(cfg & (1 << 1)) && (cfg_b & (1 << 3)))
sio_data->has_fanin |= (1 << 5); /* FANIN5 */
cfg = superio_inb(sioaddr, SIOREG_CF3);
if ((cfg & (1 << 3)) && !(cfg_b & (1 << 5)))
sio_data->has_fanin |= (1 << 6); /* FANIN6 */
/* Check which fan outputs are wired */
sio_data->has_fanout = (1 << 0); /* FANOUT0 */
if (cfg_b & (1 << 0))
sio_data->has_fanout |= (1 << 3); /* FANOUT3 */
cfg = superio_inb(sioaddr, SIOREG_CFC);
if (!(cfg & (1 << 4))) {
if (cfg_b & (1 << 1))
sio_data->has_fanout |= (1 << 1); /* FANOUT1 */
if (cfg_b & (1 << 2))
sio_data->has_fanout |= (1 << 2); /* FANOUT2 */
}
/* FANOUT1 and FANOUT2 can each be routed to 2 different pins */
cfg = superio_inb(sioaddr, SIOREG_CF5);
if (cfg & (1 << 6))
sio_data->has_fanout |= (1 << 1); /* FANOUT1 */
if (cfg & (1 << 5))
sio_data->has_fanout |= (1 << 2); /* FANOUT2 */
exit:
superio_exit(sioaddr);
return err;
}
static int __init pc87427_init(void)
{
int err;
struct pc87427_sio_data sio_data;
if (pc87427_find(0x2e, &sio_data)
&& pc87427_find(0x4e, &sio_data))
return -ENODEV;
err = platform_driver_register(&pc87427_driver);
if (err)
goto exit;
/* Sets global pdev as a side effect */
err = pc87427_device_add(&sio_data);
if (err)
goto exit_driver;
return 0;
exit_driver:
platform_driver_unregister(&pc87427_driver);
exit:
return err;
}
static void __exit pc87427_exit(void)
{
platform_device_unregister(pdev);
platform_driver_unregister(&pc87427_driver);
}
MODULE_AUTHOR("Jean Delvare <[email protected]>");
MODULE_DESCRIPTION("PC87427 hardware monitoring driver");
MODULE_LICENSE("GPL");
module_init(pc87427_init);
module_exit(pc87427_exit);
|
linux-master
|
drivers/hwmon/pc87427.c
|
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2014-2018 Nuvoton Technology corporation.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/sysfs.h>
#include <linux/thermal.h>
/* NPCM7XX PWM registers */
#define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L))
#define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00)
#define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04)
#define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08)
#define NPCM7XX_PWM_REG_CNRx(base, n, ch) \
(NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch)))
#define NPCM7XX_PWM_REG_CMRx(base, n, ch) \
(NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch)))
#define NPCM7XX_PWM_REG_PDRx(base, n, ch) \
(NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch)))
#define NPCM7XX_PWM_REG_PIER(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C)
#define NPCM7XX_PWM_REG_PIIR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x40)
#define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3)
#define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11)
#define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15)
#define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19)
#define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2)
#define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10)
#define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14)
#define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18)
#define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0)
#define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8)
#define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12)
#define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16)
/* Define the maximum PWM channel number */
#define NPCM7XX_PWM_MAX_CHN_NUM 8
#define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 4
#define NPCM7XX_PWM_MAX_MODULES 2
/* Define the Counter Register, value = 100 for match 100% */
#define NPCM7XX_PWM_COUNTER_DEFAULT_NUM 255
#define NPCM7XX_PWM_CMR_DEFAULT_NUM 255
#define NPCM7XX_PWM_CMR_MAX 255
/* default all PWM channels PRESCALE2 = 1 */
#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 0x4
#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 0x40
#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 0x400
#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3 0x4000
#define PWM_OUTPUT_FREQ_25KHZ 25000
#define PWN_CNT_DEFAULT 256
#define MIN_PRESCALE1 2
#define NPCM7XX_PWM_PRESCALE_SHIFT_CH01 8
#define NPCM7XX_PWM_PRESCALE2_DEFAULT (NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 | \
NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 | \
NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 | \
NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3)
#define NPCM7XX_PWM_CTRL_MODE_DEFAULT (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \
NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \
NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \
NPCM7XX_PWM_CTRL_CH3_MODE_BIT)
/* NPCM7XX FAN Tacho registers */
#define NPCM7XX_FAN_REG_BASE(base, n) ((base) + ((n) * 0x1000L))
#define NPCM7XX_FAN_REG_TCNT1(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x00)
#define NPCM7XX_FAN_REG_TCRA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x02)
#define NPCM7XX_FAN_REG_TCRB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x04)
#define NPCM7XX_FAN_REG_TCNT2(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x06)
#define NPCM7XX_FAN_REG_TPRSC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x08)
#define NPCM7XX_FAN_REG_TCKC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A)
#define NPCM7XX_FAN_REG_TMCTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C)
#define NPCM7XX_FAN_REG_TICTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E)
#define NPCM7XX_FAN_REG_TICLR(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x10)
#define NPCM7XX_FAN_REG_TIEN(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x12)
#define NPCM7XX_FAN_REG_TCPA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x14)
#define NPCM7XX_FAN_REG_TCPB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x16)
#define NPCM7XX_FAN_REG_TCPCFG(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x18)
#define NPCM7XX_FAN_REG_TINASEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A)
#define NPCM7XX_FAN_REG_TINBSEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C)
#define NPCM7XX_FAN_TCKC_CLKX_NONE 0
#define NPCM7XX_FAN_TCKC_CLK1_APB BIT(0)
#define NPCM7XX_FAN_TCKC_CLK2_APB BIT(3)
#define NPCM7XX_FAN_TMCTRL_TBEN BIT(6)
#define NPCM7XX_FAN_TMCTRL_TAEN BIT(5)
#define NPCM7XX_FAN_TMCTRL_TBEDG BIT(4)
#define NPCM7XX_FAN_TMCTRL_TAEDG BIT(3)
#define NPCM7XX_FAN_TMCTRL_MODE_5 BIT(2)
#define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0)
#define NPCM7XX_FAN_TICLR_TFCLR BIT(5)
#define NPCM7XX_FAN_TICLR_TECLR BIT(4)
#define NPCM7XX_FAN_TICLR_TDCLR BIT(3)
#define NPCM7XX_FAN_TICLR_TCCLR BIT(2)
#define NPCM7XX_FAN_TICLR_TBCLR BIT(1)
#define NPCM7XX_FAN_TICLR_TACLR BIT(0)
#define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0)
#define NPCM7XX_FAN_TIEN_TFIEN BIT(5)
#define NPCM7XX_FAN_TIEN_TEIEN BIT(4)
#define NPCM7XX_FAN_TIEN_TDIEN BIT(3)
#define NPCM7XX_FAN_TIEN_TCIEN BIT(2)
#define NPCM7XX_FAN_TIEN_TBIEN BIT(1)
#define NPCM7XX_FAN_TIEN_TAIEN BIT(0)
#define NPCM7XX_FAN_TICTRL_TFPND BIT(5)
#define NPCM7XX_FAN_TICTRL_TEPND BIT(4)
#define NPCM7XX_FAN_TICTRL_TDPND BIT(3)
#define NPCM7XX_FAN_TICTRL_TCPND BIT(2)
#define NPCM7XX_FAN_TICTRL_TBPND BIT(1)
#define NPCM7XX_FAN_TICTRL_TAPND BIT(0)
#define NPCM7XX_FAN_TCPCFG_HIBEN BIT(7)
#define NPCM7XX_FAN_TCPCFG_EQBEN BIT(6)
#define NPCM7XX_FAN_TCPCFG_LOBEN BIT(5)
#define NPCM7XX_FAN_TCPCFG_CPBSEL BIT(4)
#define NPCM7XX_FAN_TCPCFG_HIAEN BIT(3)
#define NPCM7XX_FAN_TCPCFG_EQAEN BIT(2)
#define NPCM7XX_FAN_TCPCFG_LOAEN BIT(1)
#define NPCM7XX_FAN_TCPCFG_CPASEL BIT(0)
/* FAN General Definition */
/* Define the maximum FAN channel number */
#define NPCM7XX_FAN_MAX_MODULE 8
#define NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE 2
#define NPCM7XX_FAN_MAX_CHN_NUM 16
/*
* Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us)
* Timeout 94ms ~= 0x5000
* (The minimum FAN speed could to support ~640RPM/pulse 1,
* 320RPM/pulse 2, ...-- 10.6Hz)
*/
#define NPCM7XX_FAN_TIMEOUT 0x5000
#define NPCM7XX_FAN_TCNT 0xFFFF
#define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
#define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
#define NPCM7XX_FAN_POLL_TIMER_200MS 200
#define NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION 2
#define NPCM7XX_FAN_TINASEL_FANIN_DEFAULT 0
#define NPCM7XX_FAN_CLK_PRESCALE 255
#define NPCM7XX_FAN_CMPA 0
#define NPCM7XX_FAN_CMPB 1
/* Obtain the fan number */
#define NPCM7XX_FAN_INPUT(fan, cmp) (((fan) << 1) + (cmp))
/* fan sample status */
#define FAN_DISABLE 0xFF
#define FAN_INIT 0x00
#define FAN_PREPARE_TO_GET_FIRST_CAPTURE 0x01
#define FAN_ENOUGH_SAMPLE 0x02
struct npcm7xx_fan_dev {
u8 fan_st_flg;
u8 fan_pls_per_rev;
u16 fan_cnt;
u32 fan_cnt_tmp;
};
struct npcm7xx_cooling_device {
char name[THERMAL_NAME_LENGTH];
struct npcm7xx_pwm_fan_data *data;
struct thermal_cooling_device *tcdev;
int pwm_port;
u8 *cooling_levels;
u8 max_state;
u8 cur_state;
};
struct npcm7xx_pwm_fan_data {
void __iomem *pwm_base;
void __iomem *fan_base;
unsigned long pwm_clk_freq;
unsigned long fan_clk_freq;
struct clk *pwm_clk;
struct clk *fan_clk;
struct mutex pwm_lock[NPCM7XX_PWM_MAX_MODULES];
spinlock_t fan_lock[NPCM7XX_FAN_MAX_MODULE];
int fan_irq[NPCM7XX_FAN_MAX_MODULE];
bool pwm_present[NPCM7XX_PWM_MAX_CHN_NUM];
bool fan_present[NPCM7XX_FAN_MAX_CHN_NUM];
u32 input_clk_freq;
struct timer_list fan_timer;
struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM];
struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM];
u8 fan_select;
};
static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data,
int channel, u16 val)
{
u32 pwm_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
u32 tmp_buf, ctrl_en_bit, env_bit;
/*
* Config PWM Comparator register for setting duty cycle
*/
mutex_lock(&data->pwm_lock[module]);
/* write new CMR value */
iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch));
tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module));
switch (pwm_ch) {
case 0:
ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT;
env_bit = NPCM7XX_PWM_CTRL_CH0_INV_BIT;
break;
case 1:
ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT;
env_bit = NPCM7XX_PWM_CTRL_CH1_INV_BIT;
break;
case 2:
ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT;
env_bit = NPCM7XX_PWM_CTRL_CH2_INV_BIT;
break;
case 3:
ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT;
env_bit = NPCM7XX_PWM_CTRL_CH3_INV_BIT;
break;
default:
mutex_unlock(&data->pwm_lock[module]);
return -ENODEV;
}
if (val == 0) {
/* Disable PWM */
tmp_buf &= ~ctrl_en_bit;
tmp_buf |= env_bit;
} else {
/* Enable PWM */
tmp_buf |= ctrl_en_bit;
tmp_buf &= ~env_bit;
}
iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module));
mutex_unlock(&data->pwm_lock[module]);
return 0;
}
static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data,
u8 fan, u8 cmp)
{
u8 fan_id;
u8 reg_mode;
u8 reg_int;
unsigned long flags;
fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
/* to check whether any fan tach is enable */
if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) {
/* reset status */
spin_lock_irqsave(&data->fan_lock[fan], flags);
data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
/*
* the interrupt enable bits do not need to be cleared before
* it sets, the interrupt enable bits are cleared only on reset.
* the clock unit control register is behaving in the same
* manner that the interrupt enable register behave.
*/
if (cmp == NPCM7XX_FAN_CMPA) {
/* enable interrupt */
iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TAIEN |
NPCM7XX_FAN_TIEN_TEIEN),
NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB
| ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
fan));
/* start to Capture */
iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base,
fan));
} else {
/* enable interrupt */
iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TBIEN |
NPCM7XX_FAN_TIEN_TFIEN),
NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
reg_mode =
NPCM7XX_FAN_TCKC_CLK2_APB
| ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
fan));
/* start to Capture */
iowrite8(reg_mode,
NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
}
spin_unlock_irqrestore(&data->fan_lock[fan], flags);
}
}
/*
* Enable a background timer to poll fan tach value, (200ms * 4)
* to polling all fan
*/
static void npcm7xx_fan_polling(struct timer_list *t)
{
struct npcm7xx_pwm_fan_data *data;
int i;
data = from_timer(data, t, fan_timer);
/*
* Polling two module per one round,
* FAN01 & FAN89 / FAN23 & FAN1011 / FAN45 & FAN1213 / FAN67 & FAN1415
*/
for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE;
i = i + 4) {
/* clear the flag and reset the counter (TCNT) */
iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
NPCM7XX_FAN_REG_TICLR(data->fan_base, i));
if (data->fan_present[i * 2]) {
iowrite16(NPCM7XX_FAN_TCNT,
NPCM7XX_FAN_REG_TCNT1(data->fan_base, i));
npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA);
}
if (data->fan_present[(i * 2) + 1]) {
iowrite16(NPCM7XX_FAN_TCNT,
NPCM7XX_FAN_REG_TCNT2(data->fan_base, i));
npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB);
}
}
data->fan_select++;
data->fan_select &= 0x3;
/* reset the timer interval */
data->fan_timer.expires = jiffies +
msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
add_timer(&data->fan_timer);
}
static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data,
u8 fan, u8 cmp, u8 fan_id, u8 flag_int,
u8 flag_mode, u8 flag_clear)
{
u8 reg_int;
u8 reg_mode;
u16 fan_cap;
if (cmp == NPCM7XX_FAN_CMPA)
fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan));
else
fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan));
/* clear capature flag, H/W will auto reset the NPCM7XX_FAN_TCNTx */
iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) {
/* First capture, drop it */
data->fan_dev[fan_id].fan_st_flg =
FAN_PREPARE_TO_GET_FIRST_CAPTURE;
/* reset counter */
data->fan_dev[fan_id].fan_cnt_tmp = 0;
} else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) {
/*
* collect the enough sample,
* (ex: 2 pulse fan need to get 2 sample)
*/
data->fan_dev[fan_id].fan_cnt_tmp +=
(NPCM7XX_FAN_TCNT - fan_cap);
data->fan_dev[fan_id].fan_st_flg++;
} else {
/* get enough sample or fan disable */
if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) {
data->fan_dev[fan_id].fan_cnt_tmp +=
(NPCM7XX_FAN_TCNT - fan_cap);
/* compute finial average cnt per pulse */
data->fan_dev[fan_id].fan_cnt =
data->fan_dev[fan_id].fan_cnt_tmp /
FAN_ENOUGH_SAMPLE;
data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
}
reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
/* disable interrupt */
iowrite8((reg_int & ~flag_int),
NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
/* stop capturing */
iowrite8((reg_mode & ~flag_mode),
NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
}
}
static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data,
u8 fan, u8 cmp, u8 flag)
{
u8 reg_int;
u8 reg_mode;
u8 flag_timeout;
u8 flag_cap;
u8 flag_clear;
u8 flag_int;
u8 flag_mode;
u8 fan_id;
fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
if (cmp == NPCM7XX_FAN_CMPA) {
flag_cap = NPCM7XX_FAN_TICTRL_TAPND;
flag_timeout = NPCM7XX_FAN_TICTRL_TEPND;
flag_int = NPCM7XX_FAN_TIEN_TAIEN | NPCM7XX_FAN_TIEN_TEIEN;
flag_mode = NPCM7XX_FAN_TCKC_CLK1_APB;
flag_clear = NPCM7XX_FAN_TICLR_TACLR | NPCM7XX_FAN_TICLR_TECLR;
} else {
flag_cap = NPCM7XX_FAN_TICTRL_TBPND;
flag_timeout = NPCM7XX_FAN_TICTRL_TFPND;
flag_int = NPCM7XX_FAN_TIEN_TBIEN | NPCM7XX_FAN_TIEN_TFIEN;
flag_mode = NPCM7XX_FAN_TCKC_CLK2_APB;
flag_clear = NPCM7XX_FAN_TICLR_TBCLR | NPCM7XX_FAN_TICLR_TFCLR;
}
if (flag & flag_timeout) {
reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
/* disable interrupt */
iowrite8((reg_int & ~flag_int),
NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
/* clear interrupt flag */
iowrite8(flag_clear,
NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
/* stop capturing */
iowrite8((reg_mode & ~flag_mode),
NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
/*
* If timeout occurs (NPCM7XX_FAN_TIMEOUT), the fan doesn't
* connect or speed is lower than 10.6Hz (320RPM/pulse2).
* In these situation, the RPM output should be zero.
*/
data->fan_dev[fan_id].fan_cnt = 0;
} else {
/* input capture is occurred */
if (flag & flag_cap)
npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int,
flag_mode, flag_clear);
}
}
static irqreturn_t npcm7xx_fan_isr(int irq, void *dev_id)
{
struct npcm7xx_pwm_fan_data *data = dev_id;
unsigned long flags;
int module;
u8 flag;
module = irq - data->fan_irq[0];
spin_lock_irqsave(&data->fan_lock[module], flags);
flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module));
if (flag > 0) {
npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag);
npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag);
spin_unlock_irqrestore(&data->fan_lock[module], flags);
return IRQ_HANDLED;
}
spin_unlock_irqrestore(&data->fan_lock[module], flags);
return IRQ_NONE;
}
static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel,
long *val)
{
struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
u32 pmw_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
switch (attr) {
case hwmon_pwm_input:
*val = ioread32
(NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch));
return 0;
default:
return -EOPNOTSUPP;
}
}
static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel,
long val)
{
struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
int err;
switch (attr) {
case hwmon_pwm_input:
if (val < 0 || val > NPCM7XX_PWM_CMR_MAX)
return -EINVAL;
err = npcm7xx_pwm_config_set(data, channel, (u16)val);
break;
default:
err = -EOPNOTSUPP;
break;
}
return err;
}
static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel)
{
const struct npcm7xx_pwm_fan_data *data = _data;
if (!data->pwm_present[channel])
return 0;
switch (attr) {
case hwmon_pwm_input:
return 0644;
default:
return 0;
}
}
static int npcm7xx_read_fan(struct device *dev, u32 attr, int channel,
long *val)
{
struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
switch (attr) {
case hwmon_fan_input:
*val = 0;
if (data->fan_dev[channel].fan_cnt <= 0)
return data->fan_dev[channel].fan_cnt;
/* Convert the raw reading to RPM */
if (data->fan_dev[channel].fan_cnt > 0 &&
data->fan_dev[channel].fan_pls_per_rev > 0)
*val = ((data->input_clk_freq * 60) /
(data->fan_dev[channel].fan_cnt *
data->fan_dev[channel].fan_pls_per_rev));
return 0;
default:
return -EOPNOTSUPP;
}
}
static umode_t npcm7xx_fan_is_visible(const void *_data, u32 attr, int channel)
{
const struct npcm7xx_pwm_fan_data *data = _data;
if (!data->fan_present[channel])
return 0;
switch (attr) {
case hwmon_fan_input:
return 0444;
default:
return 0;
}
}
static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
switch (type) {
case hwmon_pwm:
return npcm7xx_read_pwm(dev, attr, channel, val);
case hwmon_fan:
return npcm7xx_read_fan(dev, attr, channel, val);
default:
return -EOPNOTSUPP;
}
}
static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
switch (type) {
case hwmon_pwm:
return npcm7xx_write_pwm(dev, attr, channel, val);
default:
return -EOPNOTSUPP;
}
}
static umode_t npcm7xx_is_visible(const void *data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
switch (type) {
case hwmon_pwm:
return npcm7xx_pwm_is_visible(data, attr, channel);
case hwmon_fan:
return npcm7xx_fan_is_visible(data, attr, channel);
default:
return 0;
}
}
static const struct hwmon_channel_info * const npcm7xx_info[] = {
HWMON_CHANNEL_INFO(pwm,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT),
HWMON_CHANNEL_INFO(fan,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT,
HWMON_F_INPUT),
NULL
};
static const struct hwmon_ops npcm7xx_hwmon_ops = {
.is_visible = npcm7xx_is_visible,
.read = npcm7xx_read,
.write = npcm7xx_write,
};
static const struct hwmon_chip_info npcm7xx_chip_info = {
.ops = &npcm7xx_hwmon_ops,
.info = npcm7xx_info,
};
static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data)
{
int m, ch;
u32 prescale_val, output_freq;
data->pwm_clk_freq = clk_get_rate(data->pwm_clk);
/* Adjust NPCM7xx PWMs output frequency to ~25Khz */
output_freq = data->pwm_clk_freq / PWN_CNT_DEFAULT;
prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ);
/* If prescale_val = 0, then the prescale output clock is stopped */
if (prescale_val < MIN_PRESCALE1)
prescale_val = MIN_PRESCALE1;
/*
* prescale_val need to decrement in one because in the PWM Prescale
* register the Prescale value increment by one
*/
prescale_val--;
/* Setting PWM Prescale Register value register to both modules */
prescale_val |= (prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01);
for (m = 0; m < NPCM7XX_PWM_MAX_MODULES ; m++) {
iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m));
iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT,
NPCM7XX_PWM_REG_CSR(data->pwm_base, m));
iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFAULT,
NPCM7XX_PWM_REG_CR(data->pwm_base, m));
for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch++) {
iowrite32(NPCM7XX_PWM_COUNTER_DEFAULT_NUM,
NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch));
}
}
return output_freq / ((prescale_val & 0xf) + 1);
}
static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data)
{
int md;
int ch;
int i;
u32 apb_clk_freq;
for (md = 0; md < NPCM7XX_FAN_MAX_MODULE; md++) {
/* stop FAN0~7 clock */
iowrite8(NPCM7XX_FAN_TCKC_CLKX_NONE,
NPCM7XX_FAN_REG_TCKC(data->fan_base, md));
/* disable all interrupt */
iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md));
/* clear all interrupt */
iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
NPCM7XX_FAN_REG_TICLR(data->fan_base, md));
/* set FAN0~7 clock prescaler */
iowrite8(NPCM7XX_FAN_CLK_PRESCALE,
NPCM7XX_FAN_REG_TPRSC(data->fan_base, md));
/* set FAN0~7 mode (high-to-low transition) */
iowrite8((NPCM7XX_FAN_TMCTRL_MODE_5 | NPCM7XX_FAN_TMCTRL_TBEN |
NPCM7XX_FAN_TMCTRL_TAEN),
NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md));
/* set FAN0~7 Initial Count/Cap */
iowrite16(NPCM7XX_FAN_TCNT,
NPCM7XX_FAN_REG_TCNT1(data->fan_base, md));
iowrite16(NPCM7XX_FAN_TCNT,
NPCM7XX_FAN_REG_TCNT2(data->fan_base, md));
/* set FAN0~7 compare (equal to count) */
iowrite8((NPCM7XX_FAN_TCPCFG_EQAEN | NPCM7XX_FAN_TCPCFG_EQBEN),
NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md));
/* set FAN0~7 compare value */
iowrite16(NPCM7XX_FAN_TCPA,
NPCM7XX_FAN_REG_TCPA(data->fan_base, md));
iowrite16(NPCM7XX_FAN_TCPB,
NPCM7XX_FAN_REG_TCPB(data->fan_base, md));
/* set FAN0~7 fan input FANIN 0~15 */
iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
NPCM7XX_FAN_REG_TINASEL(data->fan_base, md));
iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md));
for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE; i++) {
ch = md * NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE + i;
data->fan_dev[ch].fan_st_flg = FAN_DISABLE;
data->fan_dev[ch].fan_pls_per_rev =
NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION;
data->fan_dev[ch].fan_cnt = 0;
}
}
apb_clk_freq = clk_get_rate(data->fan_clk);
/* Fan tach input clock = APB clock / prescalar, default is 255. */
data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1);
}
static int
npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
unsigned long *state)
{
struct npcm7xx_cooling_device *cdev = tcdev->devdata;
*state = cdev->max_state;
return 0;
}
static int
npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
unsigned long *state)
{
struct npcm7xx_cooling_device *cdev = tcdev->devdata;
*state = cdev->cur_state;
return 0;
}
static int
npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
unsigned long state)
{
struct npcm7xx_cooling_device *cdev = tcdev->devdata;
int ret;
if (state > cdev->max_state)
return -EINVAL;
cdev->cur_state = state;
ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port,
cdev->cooling_levels[cdev->cur_state]);
return ret;
}
static const struct thermal_cooling_device_ops npcm7xx_pwm_cool_ops = {
.get_max_state = npcm7xx_pwm_cz_get_max_state,
.get_cur_state = npcm7xx_pwm_cz_get_cur_state,
.set_cur_state = npcm7xx_pwm_cz_set_cur_state,
};
static int npcm7xx_create_pwm_cooling(struct device *dev,
struct device_node *child,
struct npcm7xx_pwm_fan_data *data,
u32 pwm_port, u8 num_levels)
{
int ret;
struct npcm7xx_cooling_device *cdev;
cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
if (!cdev)
return -ENOMEM;
cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
if (!cdev->cooling_levels)
return -ENOMEM;
cdev->max_state = num_levels - 1;
ret = of_property_read_u8_array(child, "cooling-levels",
cdev->cooling_levels,
num_levels);
if (ret) {
dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
return ret;
}
snprintf(cdev->name, THERMAL_NAME_LENGTH, "%pOFn%d", child,
pwm_port);
cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,
cdev->name, cdev, &npcm7xx_pwm_cool_ops);
if (IS_ERR(cdev->tcdev))
return PTR_ERR(cdev->tcdev);
cdev->data = data;
cdev->pwm_port = pwm_port;
data->cdev[pwm_port] = cdev;
return 0;
}
static int npcm7xx_en_pwm_fan(struct device *dev,
struct device_node *child,
struct npcm7xx_pwm_fan_data *data)
{
u8 *fan_ch;
u32 pwm_port;
int ret, fan_cnt;
u8 index, ch;
ret = of_property_read_u32(child, "reg", &pwm_port);
if (ret)
return ret;
data->pwm_present[pwm_port] = true;
ret = npcm7xx_pwm_config_set(data, pwm_port,
NPCM7XX_PWM_CMR_DEFAULT_NUM);
ret = of_property_count_u8_elems(child, "cooling-levels");
if (ret > 0) {
ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port,
ret);
if (ret)
return ret;
}
fan_cnt = of_property_count_u8_elems(child, "fan-tach-ch");
if (fan_cnt < 1)
return -EINVAL;
fan_ch = devm_kcalloc(dev, fan_cnt, sizeof(*fan_ch), GFP_KERNEL);
if (!fan_ch)
return -ENOMEM;
ret = of_property_read_u8_array(child, "fan-tach-ch", fan_ch, fan_cnt);
if (ret)
return ret;
for (ch = 0; ch < fan_cnt; ch++) {
index = fan_ch[ch];
data->fan_present[index] = true;
data->fan_dev[index].fan_st_flg = FAN_INIT;
}
return 0;
}
static int npcm7xx_pwm_fan_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np, *child;
struct npcm7xx_pwm_fan_data *data;
struct resource *res;
struct device *hwmon;
char name[20];
int ret, cnt;
u32 output_freq;
u32 i;
np = dev->of_node;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");
if (!res) {
dev_err(dev, "pwm resource not found\n");
return -ENODEV;
}
data->pwm_base = devm_ioremap_resource(dev, res);
dev_dbg(dev, "pwm base resource is %pR\n", res);
if (IS_ERR(data->pwm_base))
return PTR_ERR(data->pwm_base);
data->pwm_clk = devm_clk_get(dev, "pwm");
if (IS_ERR(data->pwm_clk)) {
dev_err(dev, "couldn't get pwm clock\n");
return PTR_ERR(data->pwm_clk);
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fan");
if (!res) {
dev_err(dev, "fan resource not found\n");
return -ENODEV;
}
data->fan_base = devm_ioremap_resource(dev, res);
dev_dbg(dev, "fan base resource is %pR\n", res);
if (IS_ERR(data->fan_base))
return PTR_ERR(data->fan_base);
data->fan_clk = devm_clk_get(dev, "fan");
if (IS_ERR(data->fan_clk)) {
dev_err(dev, "couldn't get fan clock\n");
return PTR_ERR(data->fan_clk);
}
output_freq = npcm7xx_pwm_init(data);
npcm7xx_fan_init(data);
for (cnt = 0; cnt < NPCM7XX_PWM_MAX_MODULES ; cnt++)
mutex_init(&data->pwm_lock[cnt]);
for (i = 0; i < NPCM7XX_FAN_MAX_MODULE; i++) {
spin_lock_init(&data->fan_lock[i]);
data->fan_irq[i] = platform_get_irq(pdev, i);
if (data->fan_irq[i] < 0)
return data->fan_irq[i];
sprintf(name, "NPCM7XX-FAN-MD%d", i);
ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr,
0, name, (void *)data);
if (ret) {
dev_err(dev, "register IRQ fan%d failed\n", i);
return ret;
}
}
for_each_child_of_node(np, child) {
ret = npcm7xx_en_pwm_fan(dev, child, data);
if (ret) {
dev_err(dev, "enable pwm and fan failed\n");
of_node_put(child);
return ret;
}
}
hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm_fan",
data, &npcm7xx_chip_info,
NULL);
if (IS_ERR(hwmon)) {
dev_err(dev, "unable to register hwmon device\n");
return PTR_ERR(hwmon);
}
for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM; i++) {
if (data->fan_present[i]) {
/* fan timer initialization */
data->fan_timer.expires = jiffies +
msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
timer_setup(&data->fan_timer,
npcm7xx_fan_polling, 0);
add_timer(&data->fan_timer);
break;
}
}
pr_info("NPCM7XX PWM-FAN Driver probed, output Freq %dHz[PWM], input Freq %dHz[FAN]\n",
output_freq, data->input_clk_freq);
return 0;
}
static const struct of_device_id of_pwm_fan_match_table[] = {
{ .compatible = "nuvoton,npcm750-pwm-fan", },
{},
};
MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table);
static struct platform_driver npcm7xx_pwm_fan_driver = {
.probe = npcm7xx_pwm_fan_probe,
.driver = {
.name = "npcm7xx_pwm_fan",
.of_match_table = of_pwm_fan_match_table,
},
};
module_platform_driver(npcm7xx_pwm_fan_driver);
MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM and Fan Tacho driver");
MODULE_AUTHOR("Tomer Maimon <[email protected]>");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/hwmon/npcm750-pwm-fan.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* A hwmon driver for the IBM System Director Active Energy Manager (AEM)
* temperature/power/energy sensors and capping functionality.
* Copyright (C) 2008 IBM
*
* Author: Darrick J. Wong <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/ipmi.h>
#include <linux/module.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/jiffies.h>
#include <linux/mutex.h>
#include <linux/kdev_t.h>
#include <linux/spinlock.h>
#include <linux/idr.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/platform_device.h>
#include <linux/math64.h>
#include <linux/time.h>
#include <linux/err.h>
#define REFRESH_INTERVAL (HZ)
#define IPMI_TIMEOUT (30 * HZ)
#define DRVNAME "aem"
#define AEM_NETFN 0x2E
#define AEM_FIND_FW_CMD 0x80
#define AEM_ELEMENT_CMD 0x81
#define AEM_FW_INSTANCE_CMD 0x82
#define AEM_READ_ELEMENT_CFG 0x80
#define AEM_READ_BUFFER 0x81
#define AEM_READ_REGISTER 0x82
#define AEM_WRITE_REGISTER 0x83
#define AEM_SET_REG_MASK 0x84
#define AEM_CLEAR_REG_MASK 0x85
#define AEM_READ_ELEMENT_CFG2 0x86
#define AEM_CONTROL_ELEMENT 0
#define AEM_ENERGY_ELEMENT 1
#define AEM_CLOCK_ELEMENT 4
#define AEM_POWER_CAP_ELEMENT 7
#define AEM_EXHAUST_ELEMENT 9
#define AEM_POWER_ELEMENT 10
#define AEM_MODULE_TYPE_ID 0x0001
#define AEM2_NUM_ENERGY_REGS 2
#define AEM2_NUM_PCAP_REGS 6
#define AEM2_NUM_TEMP_REGS 2
#define AEM2_NUM_SENSORS 14
#define AEM1_NUM_ENERGY_REGS 1
#define AEM1_NUM_SENSORS 3
/* AEM 2.x has more energy registers */
#define AEM_NUM_ENERGY_REGS AEM2_NUM_ENERGY_REGS
/* AEM 2.x needs more sensor files */
#define AEM_NUM_SENSORS AEM2_NUM_SENSORS
#define POWER_CAP 0
#define POWER_CAP_MAX_HOTPLUG 1
#define POWER_CAP_MAX 2
#define POWER_CAP_MIN_WARNING 3
#define POWER_CAP_MIN 4
#define POWER_AUX 5
#define AEM_DEFAULT_POWER_INTERVAL 1000
#define AEM_MIN_POWER_INTERVAL 200
#define UJ_PER_MJ 1000L
static DEFINE_IDA(aem_ida);
static struct platform_driver aem_driver = {
.driver = {
.name = DRVNAME,
.bus = &platform_bus_type,
}
};
struct aem_ipmi_data {
struct completion read_complete;
struct ipmi_addr address;
struct ipmi_user *user;
int interface;
struct kernel_ipmi_msg tx_message;
long tx_msgid;
void *rx_msg_data;
unsigned short rx_msg_len;
unsigned char rx_result;
int rx_recv_type;
struct device *bmc_device;
};
struct aem_ro_sensor_template {
char *label;
ssize_t (*show)(struct device *dev,
struct device_attribute *devattr,
char *buf);
int index;
};
struct aem_rw_sensor_template {
char *label;
ssize_t (*show)(struct device *dev,
struct device_attribute *devattr,
char *buf);
ssize_t (*set)(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count);
int index;
};
struct aem_data {
struct list_head list;
struct device *hwmon_dev;
struct platform_device *pdev;
struct mutex lock;
bool valid;
unsigned long last_updated; /* In jiffies */
u8 ver_major;
u8 ver_minor;
u8 module_handle;
int id;
struct aem_ipmi_data ipmi;
/* Function and buffer to update sensors */
void (*update)(struct aem_data *data);
struct aem_read_sensor_resp *rs_resp;
/*
* AEM 1.x sensors:
* Available sensors:
* Energy meter
* Power meter
*
* AEM 2.x sensors:
* Two energy meters
* Two power meters
* Two temperature sensors
* Six power cap registers
*/
/* sysfs attrs */
struct sensor_device_attribute sensors[AEM_NUM_SENSORS];
/* energy use in mJ */
u64 energy[AEM_NUM_ENERGY_REGS];
/* power sampling interval in ms */
unsigned long power_period[AEM_NUM_ENERGY_REGS];
/* Everything past here is for AEM2 only */
/* power caps in dW */
u16 pcap[AEM2_NUM_PCAP_REGS];
/* exhaust temperature in C */
u8 temp[AEM2_NUM_TEMP_REGS];
};
/* Data structures returned by the AEM firmware */
struct aem_iana_id {
u8 bytes[3];
};
static struct aem_iana_id system_x_id = {
.bytes = {0x4D, 0x4F, 0x00}
};
/* These are used to find AEM1 instances */
struct aem_find_firmware_req {
struct aem_iana_id id;
u8 rsvd;
__be16 index;
__be16 module_type_id;
} __packed;
struct aem_find_firmware_resp {
struct aem_iana_id id;
u8 num_instances;
} __packed;
/* These are used to find AEM2 instances */
struct aem_find_instance_req {
struct aem_iana_id id;
u8 instance_number;
__be16 module_type_id;
} __packed;
struct aem_find_instance_resp {
struct aem_iana_id id;
u8 num_instances;
u8 major;
u8 minor;
u8 module_handle;
u16 record_id;
} __packed;
/* These are used to query sensors */
struct aem_read_sensor_req {
struct aem_iana_id id;
u8 module_handle;
u8 element;
u8 subcommand;
u8 reg;
u8 rx_buf_size;
} __packed;
struct aem_read_sensor_resp {
struct aem_iana_id id;
u8 bytes[];
} __packed;
/* Data structures to talk to the IPMI layer */
struct aem_driver_data {
struct list_head aem_devices;
struct ipmi_smi_watcher bmc_events;
struct ipmi_user_hndl ipmi_hndlrs;
};
static void aem_register_bmc(int iface, struct device *dev);
static void aem_bmc_gone(int iface);
static void aem_msg_handler(struct ipmi_recv_msg *msg, void *user_msg_data);
static void aem_remove_sensors(struct aem_data *data);
static int aem1_find_sensors(struct aem_data *data);
static int aem2_find_sensors(struct aem_data *data);
static void update_aem1_sensors(struct aem_data *data);
static void update_aem2_sensors(struct aem_data *data);
static struct aem_driver_data driver_data = {
.aem_devices = LIST_HEAD_INIT(driver_data.aem_devices),
.bmc_events = {
.owner = THIS_MODULE,
.new_smi = aem_register_bmc,
.smi_gone = aem_bmc_gone,
},
.ipmi_hndlrs = {
.ipmi_recv_hndl = aem_msg_handler,
},
};
/* Functions to talk to the IPMI layer */
/* Initialize IPMI address, message buffers and user data */
static int aem_init_ipmi_data(struct aem_ipmi_data *data, int iface,
struct device *bmc)
{
int err;
init_completion(&data->read_complete);
data->bmc_device = bmc;
/* Initialize IPMI address */
data->address.addr_type = IPMI_SYSTEM_INTERFACE_ADDR_TYPE;
data->address.channel = IPMI_BMC_CHANNEL;
data->address.data[0] = 0;
data->interface = iface;
/* Initialize message buffers */
data->tx_msgid = 0;
data->tx_message.netfn = AEM_NETFN;
/* Create IPMI messaging interface user */
err = ipmi_create_user(data->interface, &driver_data.ipmi_hndlrs,
data, &data->user);
if (err < 0) {
dev_err(bmc,
"Unable to register user with IPMI interface %d\n",
data->interface);
return err;
}
return 0;
}
/* Send an IPMI command */
static int aem_send_message(struct aem_ipmi_data *data)
{
int err;
err = ipmi_validate_addr(&data->address, sizeof(data->address));
if (err)
goto out;
data->tx_msgid++;
err = ipmi_request_settime(data->user, &data->address, data->tx_msgid,
&data->tx_message, data, 0, 0, 0);
if (err)
goto out1;
return 0;
out1:
dev_err(data->bmc_device, "request_settime=%x\n", err);
return err;
out:
dev_err(data->bmc_device, "validate_addr=%x\n", err);
return err;
}
/* Dispatch IPMI messages to callers */
static void aem_msg_handler(struct ipmi_recv_msg *msg, void *user_msg_data)
{
unsigned short rx_len;
struct aem_ipmi_data *data = user_msg_data;
if (msg->msgid != data->tx_msgid) {
dev_err(data->bmc_device,
"Mismatch between received msgid (%02x) and transmitted msgid (%02x)!\n",
(int)msg->msgid,
(int)data->tx_msgid);
ipmi_free_recv_msg(msg);
return;
}
data->rx_recv_type = msg->recv_type;
if (msg->msg.data_len > 0)
data->rx_result = msg->msg.data[0];
else
data->rx_result = IPMI_UNKNOWN_ERR_COMPLETION_CODE;
if (msg->msg.data_len > 1) {
rx_len = msg->msg.data_len - 1;
if (data->rx_msg_len < rx_len)
rx_len = data->rx_msg_len;
data->rx_msg_len = rx_len;
memcpy(data->rx_msg_data, msg->msg.data + 1, data->rx_msg_len);
} else
data->rx_msg_len = 0;
ipmi_free_recv_msg(msg);
complete(&data->read_complete);
}
/* Sensor support functions */
/* Read a sensor value; must be called with data->lock held */
static int aem_read_sensor(struct aem_data *data, u8 elt, u8 reg,
void *buf, size_t size)
{
int rs_size, res;
struct aem_read_sensor_req rs_req;
/* Use preallocated rx buffer */
struct aem_read_sensor_resp *rs_resp = data->rs_resp;
struct aem_ipmi_data *ipmi = &data->ipmi;
/* AEM registers are 1, 2, 4 or 8 bytes */
switch (size) {
case 1:
case 2:
case 4:
case 8:
break;
default:
return -EINVAL;
}
rs_req.id = system_x_id;
rs_req.module_handle = data->module_handle;
rs_req.element = elt;
rs_req.subcommand = AEM_READ_REGISTER;
rs_req.reg = reg;
rs_req.rx_buf_size = size;
ipmi->tx_message.cmd = AEM_ELEMENT_CMD;
ipmi->tx_message.data = (char *)&rs_req;
ipmi->tx_message.data_len = sizeof(rs_req);
rs_size = sizeof(*rs_resp) + size;
ipmi->rx_msg_data = rs_resp;
ipmi->rx_msg_len = rs_size;
aem_send_message(ipmi);
res = wait_for_completion_timeout(&ipmi->read_complete, IPMI_TIMEOUT);
if (!res) {
res = -ETIMEDOUT;
goto out;
}
if (ipmi->rx_result || ipmi->rx_msg_len != rs_size ||
memcmp(&rs_resp->id, &system_x_id, sizeof(system_x_id))) {
res = -ENOENT;
goto out;
}
switch (size) {
case 1: {
u8 *x = buf;
*x = rs_resp->bytes[0];
break;
}
case 2: {
u16 *x = buf;
*x = be16_to_cpup((__be16 *)rs_resp->bytes);
break;
}
case 4: {
u32 *x = buf;
*x = be32_to_cpup((__be32 *)rs_resp->bytes);
break;
}
case 8: {
u64 *x = buf;
*x = be64_to_cpup((__be64 *)rs_resp->bytes);
break;
}
}
res = 0;
out:
return res;
}
/* Update AEM energy registers */
static void update_aem_energy_one(struct aem_data *data, int which)
{
aem_read_sensor(data, AEM_ENERGY_ELEMENT, which,
&data->energy[which], 8);
}
static void update_aem_energy(struct aem_data *data)
{
update_aem_energy_one(data, 0);
if (data->ver_major < 2)
return;
update_aem_energy_one(data, 1);
}
/* Update all AEM1 sensors */
static void update_aem1_sensors(struct aem_data *data)
{
mutex_lock(&data->lock);
if (time_before(jiffies, data->last_updated + REFRESH_INTERVAL) &&
data->valid)
goto out;
update_aem_energy(data);
out:
mutex_unlock(&data->lock);
}
/* Update all AEM2 sensors */
static void update_aem2_sensors(struct aem_data *data)
{
int i;
mutex_lock(&data->lock);
if (time_before(jiffies, data->last_updated + REFRESH_INTERVAL) &&
data->valid)
goto out;
update_aem_energy(data);
aem_read_sensor(data, AEM_EXHAUST_ELEMENT, 0, &data->temp[0], 1);
aem_read_sensor(data, AEM_EXHAUST_ELEMENT, 1, &data->temp[1], 1);
for (i = POWER_CAP; i <= POWER_AUX; i++)
aem_read_sensor(data, AEM_POWER_CAP_ELEMENT, i,
&data->pcap[i], 2);
out:
mutex_unlock(&data->lock);
}
/* Delete an AEM instance */
static void aem_delete(struct aem_data *data)
{
list_del(&data->list);
aem_remove_sensors(data);
kfree(data->rs_resp);
hwmon_device_unregister(data->hwmon_dev);
ipmi_destroy_user(data->ipmi.user);
platform_set_drvdata(data->pdev, NULL);
platform_device_unregister(data->pdev);
ida_free(&aem_ida, data->id);
kfree(data);
}
/* Probe functions for AEM1 devices */
/* Retrieve version and module handle for an AEM1 instance */
static int aem_find_aem1_count(struct aem_ipmi_data *data)
{
int res;
struct aem_find_firmware_req ff_req;
struct aem_find_firmware_resp ff_resp;
ff_req.id = system_x_id;
ff_req.index = 0;
ff_req.module_type_id = cpu_to_be16(AEM_MODULE_TYPE_ID);
data->tx_message.cmd = AEM_FIND_FW_CMD;
data->tx_message.data = (char *)&ff_req;
data->tx_message.data_len = sizeof(ff_req);
data->rx_msg_data = &ff_resp;
data->rx_msg_len = sizeof(ff_resp);
aem_send_message(data);
res = wait_for_completion_timeout(&data->read_complete, IPMI_TIMEOUT);
if (!res)
return -ETIMEDOUT;
if (data->rx_result || data->rx_msg_len != sizeof(ff_resp) ||
memcmp(&ff_resp.id, &system_x_id, sizeof(system_x_id)))
return -ENOENT;
return ff_resp.num_instances;
}
/* Find and initialize one AEM1 instance */
static int aem_init_aem1_inst(struct aem_ipmi_data *probe, u8 module_handle)
{
struct aem_data *data;
int i;
int res = -ENOMEM;
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return res;
mutex_init(&data->lock);
/* Copy instance data */
data->ver_major = 1;
data->ver_minor = 0;
data->module_handle = module_handle;
for (i = 0; i < AEM1_NUM_ENERGY_REGS; i++)
data->power_period[i] = AEM_DEFAULT_POWER_INTERVAL;
/* Create sub-device for this fw instance */
data->id = ida_alloc(&aem_ida, GFP_KERNEL);
if (data->id < 0)
goto id_err;
data->pdev = platform_device_alloc(DRVNAME, data->id);
if (!data->pdev)
goto dev_err;
data->pdev->dev.driver = &aem_driver.driver;
res = platform_device_add(data->pdev);
if (res)
goto dev_add_err;
platform_set_drvdata(data->pdev, data);
/* Set up IPMI interface */
res = aem_init_ipmi_data(&data->ipmi, probe->interface,
probe->bmc_device);
if (res)
goto ipmi_err;
/* Register with hwmon */
data->hwmon_dev = hwmon_device_register(&data->pdev->dev);
if (IS_ERR(data->hwmon_dev)) {
dev_err(&data->pdev->dev,
"Unable to register hwmon device for IPMI interface %d\n",
probe->interface);
res = PTR_ERR(data->hwmon_dev);
goto hwmon_reg_err;
}
data->update = update_aem1_sensors;
data->rs_resp = kzalloc(sizeof(*(data->rs_resp)) + 8, GFP_KERNEL);
if (!data->rs_resp) {
res = -ENOMEM;
goto alloc_resp_err;
}
/* Find sensors */
res = aem1_find_sensors(data);
if (res)
goto sensor_err;
/* Add to our list of AEM devices */
list_add_tail(&data->list, &driver_data.aem_devices);
dev_info(data->ipmi.bmc_device, "Found AEM v%d.%d at 0x%X\n",
data->ver_major, data->ver_minor,
data->module_handle);
return 0;
sensor_err:
kfree(data->rs_resp);
alloc_resp_err:
hwmon_device_unregister(data->hwmon_dev);
hwmon_reg_err:
ipmi_destroy_user(data->ipmi.user);
ipmi_err:
platform_set_drvdata(data->pdev, NULL);
platform_device_del(data->pdev);
dev_add_err:
platform_device_put(data->pdev);
dev_err:
ida_free(&aem_ida, data->id);
id_err:
kfree(data);
return res;
}
/* Find and initialize all AEM1 instances */
static void aem_init_aem1(struct aem_ipmi_data *probe)
{
int num, i, err;
num = aem_find_aem1_count(probe);
for (i = 0; i < num; i++) {
err = aem_init_aem1_inst(probe, i);
if (err) {
dev_err(probe->bmc_device,
"Error %d initializing AEM1 0x%X\n",
err, i);
}
}
}
/* Probe functions for AEM2 devices */
/* Retrieve version and module handle for an AEM2 instance */
static int aem_find_aem2(struct aem_ipmi_data *data,
struct aem_find_instance_resp *fi_resp,
int instance_num)
{
int res;
struct aem_find_instance_req fi_req;
fi_req.id = system_x_id;
fi_req.instance_number = instance_num;
fi_req.module_type_id = cpu_to_be16(AEM_MODULE_TYPE_ID);
data->tx_message.cmd = AEM_FW_INSTANCE_CMD;
data->tx_message.data = (char *)&fi_req;
data->tx_message.data_len = sizeof(fi_req);
data->rx_msg_data = fi_resp;
data->rx_msg_len = sizeof(*fi_resp);
aem_send_message(data);
res = wait_for_completion_timeout(&data->read_complete, IPMI_TIMEOUT);
if (!res)
return -ETIMEDOUT;
if (data->rx_result || data->rx_msg_len != sizeof(*fi_resp) ||
memcmp(&fi_resp->id, &system_x_id, sizeof(system_x_id)) ||
fi_resp->num_instances <= instance_num)
return -ENOENT;
return 0;
}
/* Find and initialize one AEM2 instance */
static int aem_init_aem2_inst(struct aem_ipmi_data *probe,
struct aem_find_instance_resp *fi_resp)
{
struct aem_data *data;
int i;
int res = -ENOMEM;
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return res;
mutex_init(&data->lock);
/* Copy instance data */
data->ver_major = fi_resp->major;
data->ver_minor = fi_resp->minor;
data->module_handle = fi_resp->module_handle;
for (i = 0; i < AEM2_NUM_ENERGY_REGS; i++)
data->power_period[i] = AEM_DEFAULT_POWER_INTERVAL;
/* Create sub-device for this fw instance */
data->id = ida_alloc(&aem_ida, GFP_KERNEL);
if (data->id < 0)
goto id_err;
data->pdev = platform_device_alloc(DRVNAME, data->id);
if (!data->pdev)
goto dev_err;
data->pdev->dev.driver = &aem_driver.driver;
res = platform_device_add(data->pdev);
if (res)
goto dev_add_err;
platform_set_drvdata(data->pdev, data);
/* Set up IPMI interface */
res = aem_init_ipmi_data(&data->ipmi, probe->interface,
probe->bmc_device);
if (res)
goto ipmi_err;
/* Register with hwmon */
data->hwmon_dev = hwmon_device_register(&data->pdev->dev);
if (IS_ERR(data->hwmon_dev)) {
dev_err(&data->pdev->dev,
"Unable to register hwmon device for IPMI interface %d\n",
probe->interface);
res = PTR_ERR(data->hwmon_dev);
goto hwmon_reg_err;
}
data->update = update_aem2_sensors;
data->rs_resp = kzalloc(sizeof(*(data->rs_resp)) + 8, GFP_KERNEL);
if (!data->rs_resp) {
res = -ENOMEM;
goto alloc_resp_err;
}
/* Find sensors */
res = aem2_find_sensors(data);
if (res)
goto sensor_err;
/* Add to our list of AEM devices */
list_add_tail(&data->list, &driver_data.aem_devices);
dev_info(data->ipmi.bmc_device, "Found AEM v%d.%d at 0x%X\n",
data->ver_major, data->ver_minor,
data->module_handle);
return 0;
sensor_err:
kfree(data->rs_resp);
alloc_resp_err:
hwmon_device_unregister(data->hwmon_dev);
hwmon_reg_err:
ipmi_destroy_user(data->ipmi.user);
ipmi_err:
platform_set_drvdata(data->pdev, NULL);
platform_device_del(data->pdev);
dev_add_err:
platform_device_put(data->pdev);
dev_err:
ida_free(&aem_ida, data->id);
id_err:
kfree(data);
return res;
}
/* Find and initialize all AEM2 instances */
static void aem_init_aem2(struct aem_ipmi_data *probe)
{
struct aem_find_instance_resp fi_resp;
int err;
int i = 0;
while (!aem_find_aem2(probe, &fi_resp, i)) {
if (fi_resp.major != 2) {
dev_err(probe->bmc_device,
"Unknown AEM v%d; please report this to the maintainer.\n",
fi_resp.major);
i++;
continue;
}
err = aem_init_aem2_inst(probe, &fi_resp);
if (err) {
dev_err(probe->bmc_device,
"Error %d initializing AEM2 0x%X\n",
err, fi_resp.module_handle);
}
i++;
}
}
/* Probe a BMC for AEM firmware instances */
static void aem_register_bmc(int iface, struct device *dev)
{
struct aem_ipmi_data probe;
if (aem_init_ipmi_data(&probe, iface, dev))
return;
/* Ignore probe errors; they won't cause problems */
aem_init_aem1(&probe);
aem_init_aem2(&probe);
ipmi_destroy_user(probe.user);
}
/* Handle BMC deletion */
static void aem_bmc_gone(int iface)
{
struct aem_data *p1, *next1;
list_for_each_entry_safe(p1, next1, &driver_data.aem_devices, list)
if (p1->ipmi.interface == iface)
aem_delete(p1);
}
/* sysfs support functions */
/* AEM device name */
static ssize_t name_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct aem_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%s%d\n", DRVNAME, data->ver_major);
}
static SENSOR_DEVICE_ATTR_RO(name, name, 0);
/* AEM device version */
static ssize_t version_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct aem_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%d.%d\n", data->ver_major, data->ver_minor);
}
static SENSOR_DEVICE_ATTR_RO(version, version, 0);
/* Display power use */
static ssize_t aem_show_power(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct aem_data *data = dev_get_drvdata(dev);
u64 before, after, delta, time;
signed long leftover;
mutex_lock(&data->lock);
update_aem_energy_one(data, attr->index);
time = ktime_get_ns();
before = data->energy[attr->index];
leftover = schedule_timeout_interruptible(
msecs_to_jiffies(data->power_period[attr->index])
);
if (leftover) {
mutex_unlock(&data->lock);
return 0;
}
update_aem_energy_one(data, attr->index);
time = ktime_get_ns() - time;
after = data->energy[attr->index];
mutex_unlock(&data->lock);
delta = (after - before) * UJ_PER_MJ;
return sprintf(buf, "%llu\n",
(unsigned long long)div64_u64(delta * NSEC_PER_SEC, time));
}
/* Display energy use */
static ssize_t aem_show_energy(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct aem_data *a = dev_get_drvdata(dev);
mutex_lock(&a->lock);
update_aem_energy_one(a, attr->index);
mutex_unlock(&a->lock);
return sprintf(buf, "%llu\n",
(unsigned long long)a->energy[attr->index] * 1000);
}
/* Display power interval registers */
static ssize_t aem_show_power_period(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct aem_data *a = dev_get_drvdata(dev);
a->update(a);
return sprintf(buf, "%lu\n", a->power_period[attr->index]);
}
/* Set power interval registers */
static ssize_t aem_set_power_period(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct aem_data *a = dev_get_drvdata(dev);
unsigned long temp;
int res;
res = kstrtoul(buf, 10, &temp);
if (res)
return res;
if (temp < AEM_MIN_POWER_INTERVAL)
return -EINVAL;
mutex_lock(&a->lock);
a->power_period[attr->index] = temp;
mutex_unlock(&a->lock);
return count;
}
/* Discover sensors on an AEM device */
static int aem_register_sensors(struct aem_data *data,
const struct aem_ro_sensor_template *ro,
const struct aem_rw_sensor_template *rw)
{
struct device *dev = &data->pdev->dev;
struct sensor_device_attribute *sensors = data->sensors;
int err;
/* Set up read-only sensors */
while (ro->label) {
sysfs_attr_init(&sensors->dev_attr.attr);
sensors->dev_attr.attr.name = ro->label;
sensors->dev_attr.attr.mode = 0444;
sensors->dev_attr.show = ro->show;
sensors->index = ro->index;
err = device_create_file(dev, &sensors->dev_attr);
if (err) {
sensors->dev_attr.attr.name = NULL;
goto error;
}
sensors++;
ro++;
}
/* Set up read-write sensors */
while (rw->label) {
sysfs_attr_init(&sensors->dev_attr.attr);
sensors->dev_attr.attr.name = rw->label;
sensors->dev_attr.attr.mode = 0644;
sensors->dev_attr.show = rw->show;
sensors->dev_attr.store = rw->set;
sensors->index = rw->index;
err = device_create_file(dev, &sensors->dev_attr);
if (err) {
sensors->dev_attr.attr.name = NULL;
goto error;
}
sensors++;
rw++;
}
err = device_create_file(dev, &sensor_dev_attr_name.dev_attr);
if (err)
goto error;
err = device_create_file(dev, &sensor_dev_attr_version.dev_attr);
return err;
error:
aem_remove_sensors(data);
return err;
}
/* sysfs support functions for AEM2 sensors */
/* Display temperature use */
static ssize_t aem2_show_temp(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct aem_data *a = dev_get_drvdata(dev);
a->update(a);
return sprintf(buf, "%u\n", a->temp[attr->index] * 1000);
}
/* Display power-capping registers */
static ssize_t aem2_show_pcap_value(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct aem_data *a = dev_get_drvdata(dev);
a->update(a);
return sprintf(buf, "%u\n", a->pcap[attr->index] * 100000);
}
/* Remove sensors attached to an AEM device */
static void aem_remove_sensors(struct aem_data *data)
{
int i;
for (i = 0; i < AEM_NUM_SENSORS; i++) {
if (!data->sensors[i].dev_attr.attr.name)
continue;
device_remove_file(&data->pdev->dev,
&data->sensors[i].dev_attr);
}
device_remove_file(&data->pdev->dev,
&sensor_dev_attr_name.dev_attr);
device_remove_file(&data->pdev->dev,
&sensor_dev_attr_version.dev_attr);
}
/* Sensor probe functions */
/* Description of AEM1 sensors */
static const struct aem_ro_sensor_template aem1_ro_sensors[] = {
{"energy1_input", aem_show_energy, 0},
{"power1_average", aem_show_power, 0},
{NULL, NULL, 0},
};
static const struct aem_rw_sensor_template aem1_rw_sensors[] = {
{"power1_average_interval", aem_show_power_period, aem_set_power_period, 0},
{NULL, NULL, NULL, 0},
};
/* Description of AEM2 sensors */
static const struct aem_ro_sensor_template aem2_ro_sensors[] = {
{"energy1_input", aem_show_energy, 0},
{"energy2_input", aem_show_energy, 1},
{"power1_average", aem_show_power, 0},
{"power2_average", aem_show_power, 1},
{"temp1_input", aem2_show_temp, 0},
{"temp2_input", aem2_show_temp, 1},
{"power4_average", aem2_show_pcap_value, POWER_CAP_MAX_HOTPLUG},
{"power5_average", aem2_show_pcap_value, POWER_CAP_MAX},
{"power6_average", aem2_show_pcap_value, POWER_CAP_MIN_WARNING},
{"power7_average", aem2_show_pcap_value, POWER_CAP_MIN},
{"power3_average", aem2_show_pcap_value, POWER_AUX},
{"power_cap", aem2_show_pcap_value, POWER_CAP},
{NULL, NULL, 0},
};
static const struct aem_rw_sensor_template aem2_rw_sensors[] = {
{"power1_average_interval", aem_show_power_period, aem_set_power_period, 0},
{"power2_average_interval", aem_show_power_period, aem_set_power_period, 1},
{NULL, NULL, NULL, 0},
};
/* Set up AEM1 sensor attrs */
static int aem1_find_sensors(struct aem_data *data)
{
return aem_register_sensors(data, aem1_ro_sensors, aem1_rw_sensors);
}
/* Set up AEM2 sensor attrs */
static int aem2_find_sensors(struct aem_data *data)
{
return aem_register_sensors(data, aem2_ro_sensors, aem2_rw_sensors);
}
/* Module init/exit routines */
static int __init aem_init(void)
{
int res;
res = driver_register(&aem_driver.driver);
if (res) {
pr_err("Can't register aem driver\n");
return res;
}
res = ipmi_smi_watcher_register(&driver_data.bmc_events);
if (res)
goto ipmi_reg_err;
return 0;
ipmi_reg_err:
driver_unregister(&aem_driver.driver);
return res;
}
static void __exit aem_exit(void)
{
struct aem_data *p1, *next1;
ipmi_smi_watcher_unregister(&driver_data.bmc_events);
driver_unregister(&aem_driver.driver);
list_for_each_entry_safe(p1, next1, &driver_data.aem_devices, list)
aem_delete(p1);
}
MODULE_AUTHOR("Darrick J. Wong <[email protected]>");
MODULE_DESCRIPTION("IBM AEM power/temp/energy sensor driver");
MODULE_LICENSE("GPL");
module_init(aem_init);
module_exit(aem_exit);
MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3350-*");
MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3550-*");
MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3650-*");
MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3655-*");
MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3755-*");
MODULE_ALIAS("dmi:bvnIBM:*:pnIBM3850M2/x3950M2-*");
MODULE_ALIAS("dmi:bvnIBM:*:pnIBMBladeHC10-*");
|
linux-master
|
drivers/hwmon/ibmaem.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* A hwmon driver for the Analog Devices ADT7462
* Copyright (C) 2008 IBM
*
* Author: Darrick J. Wong <[email protected]>
*/
#include <linux/module.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/log2.h>
#include <linux/slab.h>
/* Addresses to scan */
static const unsigned short normal_i2c[] = { 0x58, 0x5C, I2C_CLIENT_END };
/* ADT7462 registers */
#define ADT7462_REG_DEVICE 0x3D
#define ADT7462_REG_VENDOR 0x3E
#define ADT7462_REG_REVISION 0x3F
#define ADT7462_REG_MIN_TEMP_BASE_ADDR 0x44
#define ADT7462_REG_MIN_TEMP_MAX_ADDR 0x47
#define ADT7462_REG_MAX_TEMP_BASE_ADDR 0x48
#define ADT7462_REG_MAX_TEMP_MAX_ADDR 0x4B
#define ADT7462_REG_TEMP_BASE_ADDR 0x88
#define ADT7462_REG_TEMP_MAX_ADDR 0x8F
#define ADT7462_REG_FAN_BASE_ADDR 0x98
#define ADT7462_REG_FAN_MAX_ADDR 0x9F
#define ADT7462_REG_FAN2_BASE_ADDR 0xA2
#define ADT7462_REG_FAN2_MAX_ADDR 0xA9
#define ADT7462_REG_FAN_ENABLE 0x07
#define ADT7462_REG_FAN_MIN_BASE_ADDR 0x78
#define ADT7462_REG_FAN_MIN_MAX_ADDR 0x7F
#define ADT7462_REG_CFG2 0x02
#define ADT7462_FSPD_MASK 0x20
#define ADT7462_REG_PWM_BASE_ADDR 0xAA
#define ADT7462_REG_PWM_MAX_ADDR 0xAD
#define ADT7462_REG_PWM_MIN_BASE_ADDR 0x28
#define ADT7462_REG_PWM_MIN_MAX_ADDR 0x2B
#define ADT7462_REG_PWM_MAX 0x2C
#define ADT7462_REG_PWM_TEMP_MIN_BASE_ADDR 0x5C
#define ADT7462_REG_PWM_TEMP_MIN_MAX_ADDR 0x5F
#define ADT7462_REG_PWM_TEMP_RANGE_BASE_ADDR 0x60
#define ADT7462_REG_PWM_TEMP_RANGE_MAX_ADDR 0x63
#define ADT7462_PWM_HYST_MASK 0x0F
#define ADT7462_PWM_RANGE_MASK 0xF0
#define ADT7462_PWM_RANGE_SHIFT 4
#define ADT7462_REG_PWM_CFG_BASE_ADDR 0x21
#define ADT7462_REG_PWM_CFG_MAX_ADDR 0x24
#define ADT7462_PWM_CHANNEL_MASK 0xE0
#define ADT7462_PWM_CHANNEL_SHIFT 5
#define ADT7462_REG_PIN_CFG_BASE_ADDR 0x10
#define ADT7462_REG_PIN_CFG_MAX_ADDR 0x13
#define ADT7462_PIN7_INPUT 0x01 /* cfg0 */
#define ADT7462_DIODE3_INPUT 0x20
#define ADT7462_DIODE1_INPUT 0x40
#define ADT7462_VID_INPUT 0x80
#define ADT7462_PIN22_INPUT 0x04 /* cfg1 */
#define ADT7462_PIN21_INPUT 0x08
#define ADT7462_PIN19_INPUT 0x10
#define ADT7462_PIN15_INPUT 0x20
#define ADT7462_PIN13_INPUT 0x40
#define ADT7462_PIN8_INPUT 0x80
#define ADT7462_PIN23_MASK 0x03
#define ADT7462_PIN23_SHIFT 0
#define ADT7462_PIN26_MASK 0x0C /* cfg2 */
#define ADT7462_PIN26_SHIFT 2
#define ADT7462_PIN25_MASK 0x30
#define ADT7462_PIN25_SHIFT 4
#define ADT7462_PIN24_MASK 0xC0
#define ADT7462_PIN24_SHIFT 6
#define ADT7462_PIN26_VOLT_INPUT 0x08
#define ADT7462_PIN25_VOLT_INPUT 0x20
#define ADT7462_PIN28_SHIFT 4 /* cfg3 */
#define ADT7462_PIN28_VOLT 0x5
#define ADT7462_REG_ALARM1 0xB8
#define ADT7462_LT_ALARM 0x02
#define ADT7462_R1T_ALARM 0x04
#define ADT7462_R2T_ALARM 0x08
#define ADT7462_R3T_ALARM 0x10
#define ADT7462_REG_ALARM2 0xBB
#define ADT7462_V0_ALARM 0x01
#define ADT7462_V1_ALARM 0x02
#define ADT7462_V2_ALARM 0x04
#define ADT7462_V3_ALARM 0x08
#define ADT7462_V4_ALARM 0x10
#define ADT7462_V5_ALARM 0x20
#define ADT7462_V6_ALARM 0x40
#define ADT7462_V7_ALARM 0x80
#define ADT7462_REG_ALARM3 0xBC
#define ADT7462_V8_ALARM 0x08
#define ADT7462_V9_ALARM 0x10
#define ADT7462_V10_ALARM 0x20
#define ADT7462_V11_ALARM 0x40
#define ADT7462_V12_ALARM 0x80
#define ADT7462_REG_ALARM4 0xBD
#define ADT7462_F0_ALARM 0x01
#define ADT7462_F1_ALARM 0x02
#define ADT7462_F2_ALARM 0x04
#define ADT7462_F3_ALARM 0x08
#define ADT7462_F4_ALARM 0x10
#define ADT7462_F5_ALARM 0x20
#define ADT7462_F6_ALARM 0x40
#define ADT7462_F7_ALARM 0x80
#define ADT7462_ALARM1 0x0000
#define ADT7462_ALARM2 0x0100
#define ADT7462_ALARM3 0x0200
#define ADT7462_ALARM4 0x0300
#define ADT7462_ALARM_REG_SHIFT 8
#define ADT7462_ALARM_FLAG_MASK 0x0F
#define ADT7462_TEMP_COUNT 4
#define ADT7462_TEMP_REG(x) (ADT7462_REG_TEMP_BASE_ADDR + ((x) * 2))
#define ADT7462_TEMP_MIN_REG(x) (ADT7462_REG_MIN_TEMP_BASE_ADDR + (x))
#define ADT7462_TEMP_MAX_REG(x) (ADT7462_REG_MAX_TEMP_BASE_ADDR + (x))
#define TEMP_FRAC_OFFSET 6
#define ADT7462_FAN_COUNT 8
#define ADT7462_REG_FAN_MIN(x) (ADT7462_REG_FAN_MIN_BASE_ADDR + (x))
#define ADT7462_PWM_COUNT 4
#define ADT7462_REG_PWM(x) (ADT7462_REG_PWM_BASE_ADDR + (x))
#define ADT7462_REG_PWM_MIN(x) (ADT7462_REG_PWM_MIN_BASE_ADDR + (x))
#define ADT7462_REG_PWM_TMIN(x) \
(ADT7462_REG_PWM_TEMP_MIN_BASE_ADDR + (x))
#define ADT7462_REG_PWM_TRANGE(x) \
(ADT7462_REG_PWM_TEMP_RANGE_BASE_ADDR + (x))
#define ADT7462_PIN_CFG_REG_COUNT 4
#define ADT7462_REG_PIN_CFG(x) (ADT7462_REG_PIN_CFG_BASE_ADDR + (x))
#define ADT7462_REG_PWM_CFG(x) (ADT7462_REG_PWM_CFG_BASE_ADDR + (x))
#define ADT7462_ALARM_REG_COUNT 4
/*
* The chip can measure 13 different voltage sources:
*
* 1. +12V1 (pin 7)
* 2. Vccp1/+2.5V/+1.8V/+1.5V (pin 23)
* 3. +12V3 (pin 22)
* 4. +5V (pin 21)
* 5. +1.25V/+0.9V (pin 19)
* 6. +2.5V/+1.8V (pin 15)
* 7. +3.3v (pin 13)
* 8. +12V2 (pin 8)
* 9. Vbatt/FSB_Vtt (pin 26)
* A. +3.3V/+1.2V1 (pin 25)
* B. Vccp2/+2.5V/+1.8V/+1.5V (pin 24)
* C. +1.5V ICH (only if BOTH pin 28/29 are set to +1.5V)
* D. +1.5V 3GPIO (only if BOTH pin 28/29 are set to +1.5V)
*
* Each of these 13 has a factor to convert raw to voltage. Even better,
* the pins can be connected to other sensors (tach/gpio/hot/etc), which
* makes the bookkeeping tricky.
*
* Some, but not all, of these voltages have low/high limits.
*/
#define ADT7462_VOLT_COUNT 13
#define ADT7462_VENDOR 0x41
#define ADT7462_DEVICE 0x62
/* datasheet only mentions a revision 4 */
#define ADT7462_REVISION 0x04
/* How often do we reread sensors values? (In jiffies) */
#define SENSOR_REFRESH_INTERVAL (2 * HZ)
/* How often do we reread sensor limit values? (In jiffies) */
#define LIMIT_REFRESH_INTERVAL (60 * HZ)
/* datasheet says to divide this number by the fan reading to get fan rpm */
#define FAN_PERIOD_TO_RPM(x) ((90000 * 60) / (x))
#define FAN_RPM_TO_PERIOD FAN_PERIOD_TO_RPM
#define FAN_PERIOD_INVALID 65535
#define FAN_DATA_VALID(x) ((x) && (x) != FAN_PERIOD_INVALID)
#define MASK_AND_SHIFT(value, prefix) \
(((value) & prefix##_MASK) >> prefix##_SHIFT)
struct adt7462_data {
struct i2c_client *client;
struct mutex lock;
char sensors_valid;
char limits_valid;
unsigned long sensors_last_updated; /* In jiffies */
unsigned long limits_last_updated; /* In jiffies */
u8 temp[ADT7462_TEMP_COUNT];
/* bits 6-7 are quarter pieces of temp */
u8 temp_frac[ADT7462_TEMP_COUNT];
u8 temp_min[ADT7462_TEMP_COUNT];
u8 temp_max[ADT7462_TEMP_COUNT];
u16 fan[ADT7462_FAN_COUNT];
u8 fan_enabled;
u8 fan_min[ADT7462_FAN_COUNT];
u8 cfg2;
u8 pwm[ADT7462_PWM_COUNT];
u8 pin_cfg[ADT7462_PIN_CFG_REG_COUNT];
u8 voltages[ADT7462_VOLT_COUNT];
u8 volt_max[ADT7462_VOLT_COUNT];
u8 volt_min[ADT7462_VOLT_COUNT];
u8 pwm_min[ADT7462_PWM_COUNT];
u8 pwm_tmin[ADT7462_PWM_COUNT];
u8 pwm_trange[ADT7462_PWM_COUNT];
u8 pwm_max; /* only one per chip */
u8 pwm_cfg[ADT7462_PWM_COUNT];
u8 alarms[ADT7462_ALARM_REG_COUNT];
};
/*
* 16-bit registers on the ADT7462 are low-byte first. The data sheet says
* that the low byte must be read before the high byte.
*/
static inline int adt7462_read_word_data(struct i2c_client *client, u8 reg)
{
u16 foo;
foo = i2c_smbus_read_byte_data(client, reg);
foo |= ((u16)i2c_smbus_read_byte_data(client, reg + 1) << 8);
return foo;
}
/* For some reason these registers are not contiguous. */
static int ADT7462_REG_FAN(int fan)
{
if (fan < 4)
return ADT7462_REG_FAN_BASE_ADDR + (2 * fan);
return ADT7462_REG_FAN2_BASE_ADDR + (2 * (fan - 4));
}
/* Voltage registers are scattered everywhere */
static int ADT7462_REG_VOLT_MAX(struct adt7462_data *data, int which)
{
switch (which) {
case 0:
if (!(data->pin_cfg[0] & ADT7462_PIN7_INPUT))
return 0x7C;
break;
case 1:
return 0x69;
case 2:
if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT))
return 0x7F;
break;
case 3:
if (!(data->pin_cfg[1] & ADT7462_PIN21_INPUT))
return 0x7E;
break;
case 4:
if (!(data->pin_cfg[0] & ADT7462_DIODE3_INPUT))
return 0x4B;
break;
case 5:
if (!(data->pin_cfg[0] & ADT7462_DIODE1_INPUT))
return 0x49;
break;
case 6:
if (!(data->pin_cfg[1] & ADT7462_PIN13_INPUT))
return 0x68;
break;
case 7:
if (!(data->pin_cfg[1] & ADT7462_PIN8_INPUT))
return 0x7D;
break;
case 8:
if (!(data->pin_cfg[2] & ADT7462_PIN26_VOLT_INPUT))
return 0x6C;
break;
case 9:
if (!(data->pin_cfg[2] & ADT7462_PIN25_VOLT_INPUT))
return 0x6B;
break;
case 10:
return 0x6A;
case 11:
if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==
ADT7462_PIN28_VOLT &&
!(data->pin_cfg[0] & ADT7462_VID_INPUT))
return 0x50;
break;
case 12:
if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==
ADT7462_PIN28_VOLT &&
!(data->pin_cfg[0] & ADT7462_VID_INPUT))
return 0x4C;
break;
}
return 0;
}
static int ADT7462_REG_VOLT_MIN(struct adt7462_data *data, int which)
{
switch (which) {
case 0:
if (!(data->pin_cfg[0] & ADT7462_PIN7_INPUT))
return 0x6D;
break;
case 1:
return 0x72;
case 2:
if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT))
return 0x6F;
break;
case 3:
if (!(data->pin_cfg[1] & ADT7462_PIN21_INPUT))
return 0x71;
break;
case 4:
if (!(data->pin_cfg[0] & ADT7462_DIODE3_INPUT))
return 0x47;
break;
case 5:
if (!(data->pin_cfg[0] & ADT7462_DIODE1_INPUT))
return 0x45;
break;
case 6:
if (!(data->pin_cfg[1] & ADT7462_PIN13_INPUT))
return 0x70;
break;
case 7:
if (!(data->pin_cfg[1] & ADT7462_PIN8_INPUT))
return 0x6E;
break;
case 8:
if (!(data->pin_cfg[2] & ADT7462_PIN26_VOLT_INPUT))
return 0x75;
break;
case 9:
if (!(data->pin_cfg[2] & ADT7462_PIN25_VOLT_INPUT))
return 0x74;
break;
case 10:
return 0x73;
case 11:
if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==
ADT7462_PIN28_VOLT &&
!(data->pin_cfg[0] & ADT7462_VID_INPUT))
return 0x76;
break;
case 12:
if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==
ADT7462_PIN28_VOLT &&
!(data->pin_cfg[0] & ADT7462_VID_INPUT))
return 0x77;
break;
}
return 0;
}
static int ADT7462_REG_VOLT(struct adt7462_data *data, int which)
{
switch (which) {
case 0:
if (!(data->pin_cfg[0] & ADT7462_PIN7_INPUT))
return 0xA3;
break;
case 1:
return 0x90;
case 2:
if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT))
return 0xA9;
break;
case 3:
if (!(data->pin_cfg[1] & ADT7462_PIN21_INPUT))
return 0xA7;
break;
case 4:
if (!(data->pin_cfg[0] & ADT7462_DIODE3_INPUT))
return 0x8F;
break;
case 5:
if (!(data->pin_cfg[0] & ADT7462_DIODE1_INPUT))
return 0x8B;
break;
case 6:
if (!(data->pin_cfg[1] & ADT7462_PIN13_INPUT))
return 0x96;
break;
case 7:
if (!(data->pin_cfg[1] & ADT7462_PIN8_INPUT))
return 0xA5;
break;
case 8:
if (!(data->pin_cfg[2] & ADT7462_PIN26_VOLT_INPUT))
return 0x93;
break;
case 9:
if (!(data->pin_cfg[2] & ADT7462_PIN25_VOLT_INPUT))
return 0x92;
break;
case 10:
return 0x91;
case 11:
if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==
ADT7462_PIN28_VOLT &&
!(data->pin_cfg[0] & ADT7462_VID_INPUT))
return 0x94;
break;
case 12:
if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==
ADT7462_PIN28_VOLT &&
!(data->pin_cfg[0] & ADT7462_VID_INPUT))
return 0x95;
break;
}
return 0;
}
/* Provide labels for sysfs */
static const char *voltage_label(struct adt7462_data *data, int which)
{
switch (which) {
case 0:
if (!(data->pin_cfg[0] & ADT7462_PIN7_INPUT))
return "+12V1";
break;
case 1:
switch (MASK_AND_SHIFT(data->pin_cfg[1], ADT7462_PIN23)) {
case 0:
return "Vccp1";
case 1:
return "+2.5V";
case 2:
return "+1.8V";
case 3:
return "+1.5V";
}
fallthrough;
case 2:
if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT))
return "+12V3";
break;
case 3:
if (!(data->pin_cfg[1] & ADT7462_PIN21_INPUT))
return "+5V";
break;
case 4:
if (!(data->pin_cfg[0] & ADT7462_DIODE3_INPUT)) {
if (data->pin_cfg[1] & ADT7462_PIN19_INPUT)
return "+0.9V";
return "+1.25V";
}
break;
case 5:
if (!(data->pin_cfg[0] & ADT7462_DIODE1_INPUT)) {
if (data->pin_cfg[1] & ADT7462_PIN19_INPUT)
return "+1.8V";
return "+2.5V";
}
break;
case 6:
if (!(data->pin_cfg[1] & ADT7462_PIN13_INPUT))
return "+3.3V";
break;
case 7:
if (!(data->pin_cfg[1] & ADT7462_PIN8_INPUT))
return "+12V2";
break;
case 8:
switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN26)) {
case 0:
return "Vbatt";
case 1:
return "FSB_Vtt";
}
break;
case 9:
switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN25)) {
case 0:
return "+3.3V";
case 1:
return "+1.2V1";
}
break;
case 10:
switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN24)) {
case 0:
return "Vccp2";
case 1:
return "+2.5V";
case 2:
return "+1.8V";
case 3:
return "+1.5";
}
fallthrough;
case 11:
if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==
ADT7462_PIN28_VOLT &&
!(data->pin_cfg[0] & ADT7462_VID_INPUT))
return "+1.5V ICH";
break;
case 12:
if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==
ADT7462_PIN28_VOLT &&
!(data->pin_cfg[0] & ADT7462_VID_INPUT))
return "+1.5V 3GPIO";
break;
}
return "N/A";
}
/* Multipliers are actually in uV, not mV. */
static int voltage_multiplier(struct adt7462_data *data, int which)
{
switch (which) {
case 0:
if (!(data->pin_cfg[0] & ADT7462_PIN7_INPUT))
return 62500;
break;
case 1:
switch (MASK_AND_SHIFT(data->pin_cfg[1], ADT7462_PIN23)) {
case 0:
if (data->pin_cfg[0] & ADT7462_VID_INPUT)
return 12500;
return 6250;
case 1:
return 13000;
case 2:
return 9400;
case 3:
return 7800;
}
fallthrough;
case 2:
if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT))
return 62500;
break;
case 3:
if (!(data->pin_cfg[1] & ADT7462_PIN21_INPUT))
return 26000;
break;
case 4:
if (!(data->pin_cfg[0] & ADT7462_DIODE3_INPUT)) {
if (data->pin_cfg[1] & ADT7462_PIN19_INPUT)
return 4690;
return 6500;
}
break;
case 5:
if (!(data->pin_cfg[0] & ADT7462_DIODE1_INPUT)) {
if (data->pin_cfg[1] & ADT7462_PIN15_INPUT)
return 9400;
return 13000;
}
break;
case 6:
if (!(data->pin_cfg[1] & ADT7462_PIN13_INPUT))
return 17200;
break;
case 7:
if (!(data->pin_cfg[1] & ADT7462_PIN8_INPUT))
return 62500;
break;
case 8:
switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN26)) {
case 0:
return 15600;
case 1:
return 6250;
}
break;
case 9:
switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN25)) {
case 0:
return 17200;
case 1:
return 6250;
}
break;
case 10:
switch (MASK_AND_SHIFT(data->pin_cfg[2], ADT7462_PIN24)) {
case 0:
return 6250;
case 1:
return 13000;
case 2:
return 9400;
case 3:
return 7800;
}
fallthrough;
case 11:
case 12:
if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==
ADT7462_PIN28_VOLT &&
!(data->pin_cfg[0] & ADT7462_VID_INPUT))
return 7800;
}
return 0;
}
static int temp_enabled(struct adt7462_data *data, int which)
{
switch (which) {
case 0:
case 2:
return 1;
case 1:
if (data->pin_cfg[0] & ADT7462_DIODE1_INPUT)
return 1;
break;
case 3:
if (data->pin_cfg[0] & ADT7462_DIODE3_INPUT)
return 1;
break;
}
return 0;
}
static const char *temp_label(struct adt7462_data *data, int which)
{
switch (which) {
case 0:
return "local";
case 1:
if (data->pin_cfg[0] & ADT7462_DIODE1_INPUT)
return "remote1";
break;
case 2:
return "remote2";
case 3:
if (data->pin_cfg[0] & ADT7462_DIODE3_INPUT)
return "remote3";
break;
}
return "N/A";
}
/* Map Trange register values to mC */
#define NUM_TRANGE_VALUES 16
static const int trange_values[NUM_TRANGE_VALUES] = {
2000,
2500,
3300,
4000,
5000,
6700,
8000,
10000,
13300,
16000,
20000,
26700,
32000,
40000,
53300,
80000
};
static int find_trange_value(int trange)
{
int i;
for (i = 0; i < NUM_TRANGE_VALUES; i++)
if (trange_values[i] == trange)
return i;
return -EINVAL;
}
static struct adt7462_data *adt7462_update_device(struct device *dev)
{
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
unsigned long local_jiffies = jiffies;
int i;
mutex_lock(&data->lock);
if (time_before(local_jiffies, data->sensors_last_updated +
SENSOR_REFRESH_INTERVAL)
&& data->sensors_valid)
goto no_sensor_update;
for (i = 0; i < ADT7462_TEMP_COUNT; i++) {
/*
* Reading the fractional register locks the integral
* register until both have been read.
*/
data->temp_frac[i] = i2c_smbus_read_byte_data(client,
ADT7462_TEMP_REG(i));
data->temp[i] = i2c_smbus_read_byte_data(client,
ADT7462_TEMP_REG(i) + 1);
}
for (i = 0; i < ADT7462_FAN_COUNT; i++)
data->fan[i] = adt7462_read_word_data(client,
ADT7462_REG_FAN(i));
data->fan_enabled = i2c_smbus_read_byte_data(client,
ADT7462_REG_FAN_ENABLE);
for (i = 0; i < ADT7462_PWM_COUNT; i++)
data->pwm[i] = i2c_smbus_read_byte_data(client,
ADT7462_REG_PWM(i));
for (i = 0; i < ADT7462_PIN_CFG_REG_COUNT; i++)
data->pin_cfg[i] = i2c_smbus_read_byte_data(client,
ADT7462_REG_PIN_CFG(i));
for (i = 0; i < ADT7462_VOLT_COUNT; i++) {
int reg = ADT7462_REG_VOLT(data, i);
if (!reg)
data->voltages[i] = 0;
else
data->voltages[i] = i2c_smbus_read_byte_data(client,
reg);
}
data->alarms[0] = i2c_smbus_read_byte_data(client, ADT7462_REG_ALARM1);
data->alarms[1] = i2c_smbus_read_byte_data(client, ADT7462_REG_ALARM2);
data->alarms[2] = i2c_smbus_read_byte_data(client, ADT7462_REG_ALARM3);
data->alarms[3] = i2c_smbus_read_byte_data(client, ADT7462_REG_ALARM4);
data->sensors_last_updated = local_jiffies;
data->sensors_valid = 1;
no_sensor_update:
if (time_before(local_jiffies, data->limits_last_updated +
LIMIT_REFRESH_INTERVAL)
&& data->limits_valid)
goto out;
for (i = 0; i < ADT7462_TEMP_COUNT; i++) {
data->temp_min[i] = i2c_smbus_read_byte_data(client,
ADT7462_TEMP_MIN_REG(i));
data->temp_max[i] = i2c_smbus_read_byte_data(client,
ADT7462_TEMP_MAX_REG(i));
}
for (i = 0; i < ADT7462_FAN_COUNT; i++)
data->fan_min[i] = i2c_smbus_read_byte_data(client,
ADT7462_REG_FAN_MIN(i));
for (i = 0; i < ADT7462_VOLT_COUNT; i++) {
int reg = ADT7462_REG_VOLT_MAX(data, i);
data->volt_max[i] =
(reg ? i2c_smbus_read_byte_data(client, reg) : 0);
reg = ADT7462_REG_VOLT_MIN(data, i);
data->volt_min[i] =
(reg ? i2c_smbus_read_byte_data(client, reg) : 0);
}
for (i = 0; i < ADT7462_PWM_COUNT; i++) {
data->pwm_min[i] = i2c_smbus_read_byte_data(client,
ADT7462_REG_PWM_MIN(i));
data->pwm_tmin[i] = i2c_smbus_read_byte_data(client,
ADT7462_REG_PWM_TMIN(i));
data->pwm_trange[i] = i2c_smbus_read_byte_data(client,
ADT7462_REG_PWM_TRANGE(i));
data->pwm_cfg[i] = i2c_smbus_read_byte_data(client,
ADT7462_REG_PWM_CFG(i));
}
data->pwm_max = i2c_smbus_read_byte_data(client, ADT7462_REG_PWM_MAX);
data->cfg2 = i2c_smbus_read_byte_data(client, ADT7462_REG_CFG2);
data->limits_last_updated = local_jiffies;
data->limits_valid = 1;
out:
mutex_unlock(&data->lock);
return data;
}
static ssize_t temp_min_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
if (!temp_enabled(data, attr->index))
return sprintf(buf, "0\n");
return sprintf(buf, "%d\n", 1000 * (data->temp_min[attr->index] - 64));
}
static ssize_t temp_min_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
if (kstrtol(buf, 10, &temp) || !temp_enabled(data, attr->index))
return -EINVAL;
temp = clamp_val(temp, -64000, 191000);
temp = DIV_ROUND_CLOSEST(temp, 1000) + 64;
mutex_lock(&data->lock);
data->temp_min[attr->index] = temp;
i2c_smbus_write_byte_data(client, ADT7462_TEMP_MIN_REG(attr->index),
temp);
mutex_unlock(&data->lock);
return count;
}
static ssize_t temp_max_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
if (!temp_enabled(data, attr->index))
return sprintf(buf, "0\n");
return sprintf(buf, "%d\n", 1000 * (data->temp_max[attr->index] - 64));
}
static ssize_t temp_max_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
if (kstrtol(buf, 10, &temp) || !temp_enabled(data, attr->index))
return -EINVAL;
temp = clamp_val(temp, -64000, 191000);
temp = DIV_ROUND_CLOSEST(temp, 1000) + 64;
mutex_lock(&data->lock);
data->temp_max[attr->index] = temp;
i2c_smbus_write_byte_data(client, ADT7462_TEMP_MAX_REG(attr->index),
temp);
mutex_unlock(&data->lock);
return count;
}
static ssize_t temp_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
u8 frac = data->temp_frac[attr->index] >> TEMP_FRAC_OFFSET;
if (!temp_enabled(data, attr->index))
return sprintf(buf, "0\n");
return sprintf(buf, "%d\n", 1000 * (data->temp[attr->index] - 64) +
250 * frac);
}
static ssize_t temp_label_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
return sprintf(buf, "%s\n", temp_label(data, attr->index));
}
static ssize_t volt_max_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
int x = voltage_multiplier(data, attr->index);
x *= data->volt_max[attr->index];
x /= 1000; /* convert from uV to mV */
return sprintf(buf, "%d\n", x);
}
static ssize_t volt_max_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int x = voltage_multiplier(data, attr->index);
long temp;
if (kstrtol(buf, 10, &temp) || !x)
return -EINVAL;
temp = clamp_val(temp, 0, 255 * x / 1000);
temp *= 1000; /* convert mV to uV */
temp = DIV_ROUND_CLOSEST(temp, x);
mutex_lock(&data->lock);
data->volt_max[attr->index] = temp;
i2c_smbus_write_byte_data(client,
ADT7462_REG_VOLT_MAX(data, attr->index),
temp);
mutex_unlock(&data->lock);
return count;
}
static ssize_t volt_min_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
int x = voltage_multiplier(data, attr->index);
x *= data->volt_min[attr->index];
x /= 1000; /* convert from uV to mV */
return sprintf(buf, "%d\n", x);
}
static ssize_t volt_min_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int x = voltage_multiplier(data, attr->index);
long temp;
if (kstrtol(buf, 10, &temp) || !x)
return -EINVAL;
temp = clamp_val(temp, 0, 255 * x / 1000);
temp *= 1000; /* convert mV to uV */
temp = DIV_ROUND_CLOSEST(temp, x);
mutex_lock(&data->lock);
data->volt_min[attr->index] = temp;
i2c_smbus_write_byte_data(client,
ADT7462_REG_VOLT_MIN(data, attr->index),
temp);
mutex_unlock(&data->lock);
return count;
}
static ssize_t voltage_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
int x = voltage_multiplier(data, attr->index);
x *= data->voltages[attr->index];
x /= 1000; /* convert from uV to mV */
return sprintf(buf, "%d\n", x);
}
static ssize_t voltage_label_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
return sprintf(buf, "%s\n", voltage_label(data, attr->index));
}
static ssize_t alarm_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
int reg = attr->index >> ADT7462_ALARM_REG_SHIFT;
int mask = attr->index & ADT7462_ALARM_FLAG_MASK;
if (data->alarms[reg] & mask)
return sprintf(buf, "1\n");
else
return sprintf(buf, "0\n");
}
static int fan_enabled(struct adt7462_data *data, int fan)
{
return data->fan_enabled & (1 << fan);
}
static ssize_t fan_min_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
u16 temp;
/* Only the MSB of the min fan period is stored... */
temp = data->fan_min[attr->index];
temp <<= 8;
if (!fan_enabled(data, attr->index) ||
!FAN_DATA_VALID(temp))
return sprintf(buf, "0\n");
return sprintf(buf, "%d\n", FAN_PERIOD_TO_RPM(temp));
}
static ssize_t fan_min_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
if (kstrtol(buf, 10, &temp) || !temp ||
!fan_enabled(data, attr->index))
return -EINVAL;
temp = FAN_RPM_TO_PERIOD(temp);
temp >>= 8;
temp = clamp_val(temp, 1, 255);
mutex_lock(&data->lock);
data->fan_min[attr->index] = temp;
i2c_smbus_write_byte_data(client, ADT7462_REG_FAN_MIN(attr->index),
temp);
mutex_unlock(&data->lock);
return count;
}
static ssize_t fan_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
if (!fan_enabled(data, attr->index) ||
!FAN_DATA_VALID(data->fan[attr->index]))
return sprintf(buf, "0\n");
return sprintf(buf, "%d\n",
FAN_PERIOD_TO_RPM(data->fan[attr->index]));
}
static ssize_t force_pwm_max_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct adt7462_data *data = adt7462_update_device(dev);
return sprintf(buf, "%d\n", (data->cfg2 & ADT7462_FSPD_MASK ? 1 : 0));
}
static ssize_t force_pwm_max_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
u8 reg;
if (kstrtol(buf, 10, &temp))
return -EINVAL;
mutex_lock(&data->lock);
reg = i2c_smbus_read_byte_data(client, ADT7462_REG_CFG2);
if (temp)
reg |= ADT7462_FSPD_MASK;
else
reg &= ~ADT7462_FSPD_MASK;
data->cfg2 = reg;
i2c_smbus_write_byte_data(client, ADT7462_REG_CFG2, reg);
mutex_unlock(&data->lock);
return count;
}
static ssize_t pwm_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
return sprintf(buf, "%d\n", data->pwm[attr->index]);
}
static ssize_t pwm_store(struct device *dev, struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
if (kstrtol(buf, 10, &temp))
return -EINVAL;
temp = clamp_val(temp, 0, 255);
mutex_lock(&data->lock);
data->pwm[attr->index] = temp;
i2c_smbus_write_byte_data(client, ADT7462_REG_PWM(attr->index), temp);
mutex_unlock(&data->lock);
return count;
}
static ssize_t pwm_max_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct adt7462_data *data = adt7462_update_device(dev);
return sprintf(buf, "%d\n", data->pwm_max);
}
static ssize_t pwm_max_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
if (kstrtol(buf, 10, &temp))
return -EINVAL;
temp = clamp_val(temp, 0, 255);
mutex_lock(&data->lock);
data->pwm_max = temp;
i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_MAX, temp);
mutex_unlock(&data->lock);
return count;
}
static ssize_t pwm_min_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
return sprintf(buf, "%d\n", data->pwm_min[attr->index]);
}
static ssize_t pwm_min_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
if (kstrtol(buf, 10, &temp))
return -EINVAL;
temp = clamp_val(temp, 0, 255);
mutex_lock(&data->lock);
data->pwm_min[attr->index] = temp;
i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_MIN(attr->index),
temp);
mutex_unlock(&data->lock);
return count;
}
static ssize_t pwm_hyst_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
return sprintf(buf, "%d\n", 1000 *
(data->pwm_trange[attr->index] & ADT7462_PWM_HYST_MASK));
}
static ssize_t pwm_hyst_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
if (kstrtol(buf, 10, &temp))
return -EINVAL;
temp = clamp_val(temp, 0, 15000);
temp = DIV_ROUND_CLOSEST(temp, 1000);
/* package things up */
temp &= ADT7462_PWM_HYST_MASK;
temp |= data->pwm_trange[attr->index] & ADT7462_PWM_RANGE_MASK;
mutex_lock(&data->lock);
data->pwm_trange[attr->index] = temp;
i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_TRANGE(attr->index),
temp);
mutex_unlock(&data->lock);
return count;
}
static ssize_t pwm_tmax_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
/* tmax = tmin + trange */
int trange = trange_values[data->pwm_trange[attr->index] >>
ADT7462_PWM_RANGE_SHIFT];
int tmin = (data->pwm_tmin[attr->index] - 64) * 1000;
return sprintf(buf, "%d\n", tmin + trange);
}
static ssize_t pwm_tmax_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
int temp;
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int tmin, trange_value;
long trange;
if (kstrtol(buf, 10, &trange))
return -EINVAL;
/* trange = tmax - tmin */
tmin = (data->pwm_tmin[attr->index] - 64) * 1000;
trange_value = find_trange_value(trange - tmin);
if (trange_value < 0)
return trange_value;
temp = trange_value << ADT7462_PWM_RANGE_SHIFT;
temp |= data->pwm_trange[attr->index] & ADT7462_PWM_HYST_MASK;
mutex_lock(&data->lock);
data->pwm_trange[attr->index] = temp;
i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_TRANGE(attr->index),
temp);
mutex_unlock(&data->lock);
return count;
}
static ssize_t pwm_tmin_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
return sprintf(buf, "%d\n", 1000 * (data->pwm_tmin[attr->index] - 64));
}
static ssize_t pwm_tmin_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
if (kstrtol(buf, 10, &temp))
return -EINVAL;
temp = clamp_val(temp, -64000, 191000);
temp = DIV_ROUND_CLOSEST(temp, 1000) + 64;
mutex_lock(&data->lock);
data->pwm_tmin[attr->index] = temp;
i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_TMIN(attr->index),
temp);
mutex_unlock(&data->lock);
return count;
}
static ssize_t pwm_auto_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
int cfg = data->pwm_cfg[attr->index] >> ADT7462_PWM_CHANNEL_SHIFT;
switch (cfg) {
case 4: /* off */
return sprintf(buf, "0\n");
case 7: /* manual */
return sprintf(buf, "1\n");
default: /* automatic */
return sprintf(buf, "2\n");
}
}
static void set_pwm_channel(struct i2c_client *client,
struct adt7462_data *data,
int which,
int value)
{
int temp = data->pwm_cfg[which] & ~ADT7462_PWM_CHANNEL_MASK;
temp |= value << ADT7462_PWM_CHANNEL_SHIFT;
mutex_lock(&data->lock);
data->pwm_cfg[which] = temp;
i2c_smbus_write_byte_data(client, ADT7462_REG_PWM_CFG(which), temp);
mutex_unlock(&data->lock);
}
static ssize_t pwm_auto_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
if (kstrtol(buf, 10, &temp))
return -EINVAL;
switch (temp) {
case 0: /* off */
set_pwm_channel(client, data, attr->index, 4);
return count;
case 1: /* manual */
set_pwm_channel(client, data, attr->index, 7);
return count;
default:
return -EINVAL;
}
}
static ssize_t pwm_auto_temp_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = adt7462_update_device(dev);
int channel = data->pwm_cfg[attr->index] >> ADT7462_PWM_CHANNEL_SHIFT;
switch (channel) {
case 0: /* temp[1234] only */
case 1:
case 2:
case 3:
return sprintf(buf, "%d\n", (1 << channel));
case 5: /* temp1 & temp4 */
return sprintf(buf, "9\n");
case 6:
return sprintf(buf, "15\n");
default:
return sprintf(buf, "0\n");
}
}
static int cvt_auto_temp(int input)
{
if (input == 0xF)
return 6;
if (input == 0x9)
return 5;
if (input < 1 || !is_power_of_2(input))
return -EINVAL;
return ilog2(input);
}
static ssize_t pwm_auto_temp_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adt7462_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
if (kstrtol(buf, 10, &temp))
return -EINVAL;
temp = cvt_auto_temp(temp);
if (temp < 0)
return temp;
set_pwm_channel(client, data, attr->index, temp);
return count;
}
static SENSOR_DEVICE_ATTR_RW(temp1_max, temp_max, 0);
static SENSOR_DEVICE_ATTR_RW(temp2_max, temp_max, 1);
static SENSOR_DEVICE_ATTR_RW(temp3_max, temp_max, 2);
static SENSOR_DEVICE_ATTR_RW(temp4_max, temp_max, 3);
static SENSOR_DEVICE_ATTR_RW(temp1_min, temp_min, 0);
static SENSOR_DEVICE_ATTR_RW(temp2_min, temp_min, 1);
static SENSOR_DEVICE_ATTR_RW(temp3_min, temp_min, 2);
static SENSOR_DEVICE_ATTR_RW(temp4_min, temp_min, 3);
static SENSOR_DEVICE_ATTR_RO(temp1_input, temp, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_input, temp, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_input, temp, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_input, temp, 3);
static SENSOR_DEVICE_ATTR_RO(temp1_label, temp_label, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_label, temp_label, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_label, temp_label, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_label, temp_label, 3);
static SENSOR_DEVICE_ATTR_RO(temp1_alarm, alarm,
ADT7462_ALARM1 | ADT7462_LT_ALARM);
static SENSOR_DEVICE_ATTR_RO(temp2_alarm, alarm,
ADT7462_ALARM1 | ADT7462_R1T_ALARM);
static SENSOR_DEVICE_ATTR_RO(temp3_alarm, alarm,
ADT7462_ALARM1 | ADT7462_R2T_ALARM);
static SENSOR_DEVICE_ATTR_RO(temp4_alarm, alarm,
ADT7462_ALARM1 | ADT7462_R3T_ALARM);
static SENSOR_DEVICE_ATTR_RW(in1_max, volt_max, 0);
static SENSOR_DEVICE_ATTR_RW(in2_max, volt_max, 1);
static SENSOR_DEVICE_ATTR_RW(in3_max, volt_max, 2);
static SENSOR_DEVICE_ATTR_RW(in4_max, volt_max, 3);
static SENSOR_DEVICE_ATTR_RW(in5_max, volt_max, 4);
static SENSOR_DEVICE_ATTR_RW(in6_max, volt_max, 5);
static SENSOR_DEVICE_ATTR_RW(in7_max, volt_max, 6);
static SENSOR_DEVICE_ATTR_RW(in8_max, volt_max, 7);
static SENSOR_DEVICE_ATTR_RW(in9_max, volt_max, 8);
static SENSOR_DEVICE_ATTR_RW(in10_max, volt_max, 9);
static SENSOR_DEVICE_ATTR_RW(in11_max, volt_max, 10);
static SENSOR_DEVICE_ATTR_RW(in12_max, volt_max, 11);
static SENSOR_DEVICE_ATTR_RW(in13_max, volt_max, 12);
static SENSOR_DEVICE_ATTR_RW(in1_min, volt_min, 0);
static SENSOR_DEVICE_ATTR_RW(in2_min, volt_min, 1);
static SENSOR_DEVICE_ATTR_RW(in3_min, volt_min, 2);
static SENSOR_DEVICE_ATTR_RW(in4_min, volt_min, 3);
static SENSOR_DEVICE_ATTR_RW(in5_min, volt_min, 4);
static SENSOR_DEVICE_ATTR_RW(in6_min, volt_min, 5);
static SENSOR_DEVICE_ATTR_RW(in7_min, volt_min, 6);
static SENSOR_DEVICE_ATTR_RW(in8_min, volt_min, 7);
static SENSOR_DEVICE_ATTR_RW(in9_min, volt_min, 8);
static SENSOR_DEVICE_ATTR_RW(in10_min, volt_min, 9);
static SENSOR_DEVICE_ATTR_RW(in11_min, volt_min, 10);
static SENSOR_DEVICE_ATTR_RW(in12_min, volt_min, 11);
static SENSOR_DEVICE_ATTR_RW(in13_min, volt_min, 12);
static SENSOR_DEVICE_ATTR_RO(in1_input, voltage, 0);
static SENSOR_DEVICE_ATTR_RO(in2_input, voltage, 1);
static SENSOR_DEVICE_ATTR_RO(in3_input, voltage, 2);
static SENSOR_DEVICE_ATTR_RO(in4_input, voltage, 3);
static SENSOR_DEVICE_ATTR_RO(in5_input, voltage, 4);
static SENSOR_DEVICE_ATTR_RO(in6_input, voltage, 5);
static SENSOR_DEVICE_ATTR_RO(in7_input, voltage, 6);
static SENSOR_DEVICE_ATTR_RO(in8_input, voltage, 7);
static SENSOR_DEVICE_ATTR_RO(in9_input, voltage, 8);
static SENSOR_DEVICE_ATTR_RO(in10_input, voltage, 9);
static SENSOR_DEVICE_ATTR_RO(in11_input, voltage, 10);
static SENSOR_DEVICE_ATTR_RO(in12_input, voltage, 11);
static SENSOR_DEVICE_ATTR_RO(in13_input, voltage, 12);
static SENSOR_DEVICE_ATTR_RO(in1_label, voltage_label, 0);
static SENSOR_DEVICE_ATTR_RO(in2_label, voltage_label, 1);
static SENSOR_DEVICE_ATTR_RO(in3_label, voltage_label, 2);
static SENSOR_DEVICE_ATTR_RO(in4_label, voltage_label, 3);
static SENSOR_DEVICE_ATTR_RO(in5_label, voltage_label, 4);
static SENSOR_DEVICE_ATTR_RO(in6_label, voltage_label, 5);
static SENSOR_DEVICE_ATTR_RO(in7_label, voltage_label, 6);
static SENSOR_DEVICE_ATTR_RO(in8_label, voltage_label, 7);
static SENSOR_DEVICE_ATTR_RO(in9_label, voltage_label, 8);
static SENSOR_DEVICE_ATTR_RO(in10_label, voltage_label, 9);
static SENSOR_DEVICE_ATTR_RO(in11_label, voltage_label, 10);
static SENSOR_DEVICE_ATTR_RO(in12_label, voltage_label, 11);
static SENSOR_DEVICE_ATTR_RO(in13_label, voltage_label, 12);
static SENSOR_DEVICE_ATTR_RO(in1_alarm, alarm,
ADT7462_ALARM2 | ADT7462_V0_ALARM);
static SENSOR_DEVICE_ATTR_RO(in2_alarm, alarm,
ADT7462_ALARM2 | ADT7462_V7_ALARM);
static SENSOR_DEVICE_ATTR_RO(in3_alarm, alarm,
ADT7462_ALARM2 | ADT7462_V2_ALARM);
static SENSOR_DEVICE_ATTR_RO(in4_alarm, alarm,
ADT7462_ALARM2 | ADT7462_V6_ALARM);
static SENSOR_DEVICE_ATTR_RO(in5_alarm, alarm,
ADT7462_ALARM2 | ADT7462_V5_ALARM);
static SENSOR_DEVICE_ATTR_RO(in6_alarm, alarm,
ADT7462_ALARM2 | ADT7462_V4_ALARM);
static SENSOR_DEVICE_ATTR_RO(in7_alarm, alarm,
ADT7462_ALARM2 | ADT7462_V3_ALARM);
static SENSOR_DEVICE_ATTR_RO(in8_alarm, alarm,
ADT7462_ALARM2 | ADT7462_V1_ALARM);
static SENSOR_DEVICE_ATTR_RO(in9_alarm, alarm,
ADT7462_ALARM3 | ADT7462_V10_ALARM);
static SENSOR_DEVICE_ATTR_RO(in10_alarm, alarm,
ADT7462_ALARM3 | ADT7462_V9_ALARM);
static SENSOR_DEVICE_ATTR_RO(in11_alarm, alarm,
ADT7462_ALARM3 | ADT7462_V8_ALARM);
static SENSOR_DEVICE_ATTR_RO(in12_alarm, alarm,
ADT7462_ALARM3 | ADT7462_V11_ALARM);
static SENSOR_DEVICE_ATTR_RO(in13_alarm, alarm,
ADT7462_ALARM3 | ADT7462_V12_ALARM);
static SENSOR_DEVICE_ATTR_RW(fan1_min, fan_min, 0);
static SENSOR_DEVICE_ATTR_RW(fan2_min, fan_min, 1);
static SENSOR_DEVICE_ATTR_RW(fan3_min, fan_min, 2);
static SENSOR_DEVICE_ATTR_RW(fan4_min, fan_min, 3);
static SENSOR_DEVICE_ATTR_RW(fan5_min, fan_min, 4);
static SENSOR_DEVICE_ATTR_RW(fan6_min, fan_min, 5);
static SENSOR_DEVICE_ATTR_RW(fan7_min, fan_min, 6);
static SENSOR_DEVICE_ATTR_RW(fan8_min, fan_min, 7);
static SENSOR_DEVICE_ATTR_RO(fan1_input, fan, 0);
static SENSOR_DEVICE_ATTR_RO(fan2_input, fan, 1);
static SENSOR_DEVICE_ATTR_RO(fan3_input, fan, 2);
static SENSOR_DEVICE_ATTR_RO(fan4_input, fan, 3);
static SENSOR_DEVICE_ATTR_RO(fan5_input, fan, 4);
static SENSOR_DEVICE_ATTR_RO(fan6_input, fan, 5);
static SENSOR_DEVICE_ATTR_RO(fan7_input, fan, 6);
static SENSOR_DEVICE_ATTR_RO(fan8_input, fan, 7);
static SENSOR_DEVICE_ATTR_RO(fan1_alarm, alarm,
ADT7462_ALARM4 | ADT7462_F0_ALARM);
static SENSOR_DEVICE_ATTR_RO(fan2_alarm, alarm,
ADT7462_ALARM4 | ADT7462_F1_ALARM);
static SENSOR_DEVICE_ATTR_RO(fan3_alarm, alarm,
ADT7462_ALARM4 | ADT7462_F2_ALARM);
static SENSOR_DEVICE_ATTR_RO(fan4_alarm, alarm,
ADT7462_ALARM4 | ADT7462_F3_ALARM);
static SENSOR_DEVICE_ATTR_RO(fan5_alarm, alarm,
ADT7462_ALARM4 | ADT7462_F4_ALARM);
static SENSOR_DEVICE_ATTR_RO(fan6_alarm, alarm,
ADT7462_ALARM4 | ADT7462_F5_ALARM);
static SENSOR_DEVICE_ATTR_RO(fan7_alarm, alarm,
ADT7462_ALARM4 | ADT7462_F6_ALARM);
static SENSOR_DEVICE_ATTR_RO(fan8_alarm, alarm,
ADT7462_ALARM4 | ADT7462_F7_ALARM);
static SENSOR_DEVICE_ATTR_RW(force_pwm_max, force_pwm_max, 0);
static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1);
static SENSOR_DEVICE_ATTR_RW(pwm3, pwm, 2);
static SENSOR_DEVICE_ATTR_RW(pwm4, pwm, 3);
static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point1_pwm, pwm_min, 0);
static SENSOR_DEVICE_ATTR_RW(pwm2_auto_point1_pwm, pwm_min, 1);
static SENSOR_DEVICE_ATTR_RW(pwm3_auto_point1_pwm, pwm_min, 2);
static SENSOR_DEVICE_ATTR_RW(pwm4_auto_point1_pwm, pwm_min, 3);
static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point2_pwm, pwm_max, 0);
static SENSOR_DEVICE_ATTR_RW(pwm2_auto_point2_pwm, pwm_max, 1);
static SENSOR_DEVICE_ATTR_RW(pwm3_auto_point2_pwm, pwm_max, 2);
static SENSOR_DEVICE_ATTR_RW(pwm4_auto_point2_pwm, pwm_max, 3);
static SENSOR_DEVICE_ATTR_RW(temp1_auto_point1_hyst, pwm_hyst, 0);
static SENSOR_DEVICE_ATTR_RW(temp2_auto_point1_hyst, pwm_hyst, 1);
static SENSOR_DEVICE_ATTR_RW(temp3_auto_point1_hyst, pwm_hyst, 2);
static SENSOR_DEVICE_ATTR_RW(temp4_auto_point1_hyst, pwm_hyst, 3);
static SENSOR_DEVICE_ATTR_RW(temp1_auto_point2_hyst, pwm_hyst, 0);
static SENSOR_DEVICE_ATTR_RW(temp2_auto_point2_hyst, pwm_hyst, 1);
static SENSOR_DEVICE_ATTR_RW(temp3_auto_point2_hyst, pwm_hyst, 2);
static SENSOR_DEVICE_ATTR_RW(temp4_auto_point2_hyst, pwm_hyst, 3);
static SENSOR_DEVICE_ATTR_RW(temp1_auto_point1_temp, pwm_tmin, 0);
static SENSOR_DEVICE_ATTR_RW(temp2_auto_point1_temp, pwm_tmin, 1);
static SENSOR_DEVICE_ATTR_RW(temp3_auto_point1_temp, pwm_tmin, 2);
static SENSOR_DEVICE_ATTR_RW(temp4_auto_point1_temp, pwm_tmin, 3);
static SENSOR_DEVICE_ATTR_RW(temp1_auto_point2_temp, pwm_tmax, 0);
static SENSOR_DEVICE_ATTR_RW(temp2_auto_point2_temp, pwm_tmax, 1);
static SENSOR_DEVICE_ATTR_RW(temp3_auto_point2_temp, pwm_tmax, 2);
static SENSOR_DEVICE_ATTR_RW(temp4_auto_point2_temp, pwm_tmax, 3);
static SENSOR_DEVICE_ATTR_RW(pwm1_enable, pwm_auto, 0);
static SENSOR_DEVICE_ATTR_RW(pwm2_enable, pwm_auto, 1);
static SENSOR_DEVICE_ATTR_RW(pwm3_enable, pwm_auto, 2);
static SENSOR_DEVICE_ATTR_RW(pwm4_enable, pwm_auto, 3);
static SENSOR_DEVICE_ATTR_RW(pwm1_auto_channels_temp, pwm_auto_temp, 0);
static SENSOR_DEVICE_ATTR_RW(pwm2_auto_channels_temp, pwm_auto_temp, 1);
static SENSOR_DEVICE_ATTR_RW(pwm3_auto_channels_temp, pwm_auto_temp, 2);
static SENSOR_DEVICE_ATTR_RW(pwm4_auto_channels_temp, pwm_auto_temp, 3);
static struct attribute *adt7462_attrs[] = {
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp2_max.dev_attr.attr,
&sensor_dev_attr_temp3_max.dev_attr.attr,
&sensor_dev_attr_temp4_max.dev_attr.attr,
&sensor_dev_attr_temp1_min.dev_attr.attr,
&sensor_dev_attr_temp2_min.dev_attr.attr,
&sensor_dev_attr_temp3_min.dev_attr.attr,
&sensor_dev_attr_temp4_min.dev_attr.attr,
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp3_input.dev_attr.attr,
&sensor_dev_attr_temp4_input.dev_attr.attr,
&sensor_dev_attr_temp1_label.dev_attr.attr,
&sensor_dev_attr_temp2_label.dev_attr.attr,
&sensor_dev_attr_temp3_label.dev_attr.attr,
&sensor_dev_attr_temp4_label.dev_attr.attr,
&sensor_dev_attr_temp1_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_alarm.dev_attr.attr,
&sensor_dev_attr_temp3_alarm.dev_attr.attr,
&sensor_dev_attr_temp4_alarm.dev_attr.attr,
&sensor_dev_attr_in1_max.dev_attr.attr,
&sensor_dev_attr_in2_max.dev_attr.attr,
&sensor_dev_attr_in3_max.dev_attr.attr,
&sensor_dev_attr_in4_max.dev_attr.attr,
&sensor_dev_attr_in5_max.dev_attr.attr,
&sensor_dev_attr_in6_max.dev_attr.attr,
&sensor_dev_attr_in7_max.dev_attr.attr,
&sensor_dev_attr_in8_max.dev_attr.attr,
&sensor_dev_attr_in9_max.dev_attr.attr,
&sensor_dev_attr_in10_max.dev_attr.attr,
&sensor_dev_attr_in11_max.dev_attr.attr,
&sensor_dev_attr_in12_max.dev_attr.attr,
&sensor_dev_attr_in13_max.dev_attr.attr,
&sensor_dev_attr_in1_min.dev_attr.attr,
&sensor_dev_attr_in2_min.dev_attr.attr,
&sensor_dev_attr_in3_min.dev_attr.attr,
&sensor_dev_attr_in4_min.dev_attr.attr,
&sensor_dev_attr_in5_min.dev_attr.attr,
&sensor_dev_attr_in6_min.dev_attr.attr,
&sensor_dev_attr_in7_min.dev_attr.attr,
&sensor_dev_attr_in8_min.dev_attr.attr,
&sensor_dev_attr_in9_min.dev_attr.attr,
&sensor_dev_attr_in10_min.dev_attr.attr,
&sensor_dev_attr_in11_min.dev_attr.attr,
&sensor_dev_attr_in12_min.dev_attr.attr,
&sensor_dev_attr_in13_min.dev_attr.attr,
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in2_input.dev_attr.attr,
&sensor_dev_attr_in3_input.dev_attr.attr,
&sensor_dev_attr_in4_input.dev_attr.attr,
&sensor_dev_attr_in5_input.dev_attr.attr,
&sensor_dev_attr_in6_input.dev_attr.attr,
&sensor_dev_attr_in7_input.dev_attr.attr,
&sensor_dev_attr_in8_input.dev_attr.attr,
&sensor_dev_attr_in9_input.dev_attr.attr,
&sensor_dev_attr_in10_input.dev_attr.attr,
&sensor_dev_attr_in11_input.dev_attr.attr,
&sensor_dev_attr_in12_input.dev_attr.attr,
&sensor_dev_attr_in13_input.dev_attr.attr,
&sensor_dev_attr_in1_label.dev_attr.attr,
&sensor_dev_attr_in2_label.dev_attr.attr,
&sensor_dev_attr_in3_label.dev_attr.attr,
&sensor_dev_attr_in4_label.dev_attr.attr,
&sensor_dev_attr_in5_label.dev_attr.attr,
&sensor_dev_attr_in6_label.dev_attr.attr,
&sensor_dev_attr_in7_label.dev_attr.attr,
&sensor_dev_attr_in8_label.dev_attr.attr,
&sensor_dev_attr_in9_label.dev_attr.attr,
&sensor_dev_attr_in10_label.dev_attr.attr,
&sensor_dev_attr_in11_label.dev_attr.attr,
&sensor_dev_attr_in12_label.dev_attr.attr,
&sensor_dev_attr_in13_label.dev_attr.attr,
&sensor_dev_attr_in1_alarm.dev_attr.attr,
&sensor_dev_attr_in2_alarm.dev_attr.attr,
&sensor_dev_attr_in3_alarm.dev_attr.attr,
&sensor_dev_attr_in4_alarm.dev_attr.attr,
&sensor_dev_attr_in5_alarm.dev_attr.attr,
&sensor_dev_attr_in6_alarm.dev_attr.attr,
&sensor_dev_attr_in7_alarm.dev_attr.attr,
&sensor_dev_attr_in8_alarm.dev_attr.attr,
&sensor_dev_attr_in9_alarm.dev_attr.attr,
&sensor_dev_attr_in10_alarm.dev_attr.attr,
&sensor_dev_attr_in11_alarm.dev_attr.attr,
&sensor_dev_attr_in12_alarm.dev_attr.attr,
&sensor_dev_attr_in13_alarm.dev_attr.attr,
&sensor_dev_attr_fan1_min.dev_attr.attr,
&sensor_dev_attr_fan2_min.dev_attr.attr,
&sensor_dev_attr_fan3_min.dev_attr.attr,
&sensor_dev_attr_fan4_min.dev_attr.attr,
&sensor_dev_attr_fan5_min.dev_attr.attr,
&sensor_dev_attr_fan6_min.dev_attr.attr,
&sensor_dev_attr_fan7_min.dev_attr.attr,
&sensor_dev_attr_fan8_min.dev_attr.attr,
&sensor_dev_attr_fan1_input.dev_attr.attr,
&sensor_dev_attr_fan2_input.dev_attr.attr,
&sensor_dev_attr_fan3_input.dev_attr.attr,
&sensor_dev_attr_fan4_input.dev_attr.attr,
&sensor_dev_attr_fan5_input.dev_attr.attr,
&sensor_dev_attr_fan6_input.dev_attr.attr,
&sensor_dev_attr_fan7_input.dev_attr.attr,
&sensor_dev_attr_fan8_input.dev_attr.attr,
&sensor_dev_attr_fan1_alarm.dev_attr.attr,
&sensor_dev_attr_fan2_alarm.dev_attr.attr,
&sensor_dev_attr_fan3_alarm.dev_attr.attr,
&sensor_dev_attr_fan4_alarm.dev_attr.attr,
&sensor_dev_attr_fan5_alarm.dev_attr.attr,
&sensor_dev_attr_fan6_alarm.dev_attr.attr,
&sensor_dev_attr_fan7_alarm.dev_attr.attr,
&sensor_dev_attr_fan8_alarm.dev_attr.attr,
&sensor_dev_attr_force_pwm_max.dev_attr.attr,
&sensor_dev_attr_pwm1.dev_attr.attr,
&sensor_dev_attr_pwm2.dev_attr.attr,
&sensor_dev_attr_pwm3.dev_attr.attr,
&sensor_dev_attr_pwm4.dev_attr.attr,
&sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
&sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
&sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
&sensor_dev_attr_pwm4_auto_point1_pwm.dev_attr.attr,
&sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
&sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
&sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
&sensor_dev_attr_pwm4_auto_point2_pwm.dev_attr.attr,
&sensor_dev_attr_temp1_auto_point1_hyst.dev_attr.attr,
&sensor_dev_attr_temp2_auto_point1_hyst.dev_attr.attr,
&sensor_dev_attr_temp3_auto_point1_hyst.dev_attr.attr,
&sensor_dev_attr_temp4_auto_point1_hyst.dev_attr.attr,
&sensor_dev_attr_temp1_auto_point2_hyst.dev_attr.attr,
&sensor_dev_attr_temp2_auto_point2_hyst.dev_attr.attr,
&sensor_dev_attr_temp3_auto_point2_hyst.dev_attr.attr,
&sensor_dev_attr_temp4_auto_point2_hyst.dev_attr.attr,
&sensor_dev_attr_temp1_auto_point1_temp.dev_attr.attr,
&sensor_dev_attr_temp2_auto_point1_temp.dev_attr.attr,
&sensor_dev_attr_temp3_auto_point1_temp.dev_attr.attr,
&sensor_dev_attr_temp4_auto_point1_temp.dev_attr.attr,
&sensor_dev_attr_temp1_auto_point2_temp.dev_attr.attr,
&sensor_dev_attr_temp2_auto_point2_temp.dev_attr.attr,
&sensor_dev_attr_temp3_auto_point2_temp.dev_attr.attr,
&sensor_dev_attr_temp4_auto_point2_temp.dev_attr.attr,
&sensor_dev_attr_pwm1_enable.dev_attr.attr,
&sensor_dev_attr_pwm2_enable.dev_attr.attr,
&sensor_dev_attr_pwm3_enable.dev_attr.attr,
&sensor_dev_attr_pwm4_enable.dev_attr.attr,
&sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
&sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
&sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
&sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
NULL
};
ATTRIBUTE_GROUPS(adt7462);
/* Return 0 if detection is successful, -ENODEV otherwise */
static int adt7462_detect(struct i2c_client *client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
int vendor, device, revision;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
vendor = i2c_smbus_read_byte_data(client, ADT7462_REG_VENDOR);
if (vendor != ADT7462_VENDOR)
return -ENODEV;
device = i2c_smbus_read_byte_data(client, ADT7462_REG_DEVICE);
if (device != ADT7462_DEVICE)
return -ENODEV;
revision = i2c_smbus_read_byte_data(client, ADT7462_REG_REVISION);
if (revision != ADT7462_REVISION)
return -ENODEV;
strscpy(info->type, "adt7462", I2C_NAME_SIZE);
return 0;
}
static int adt7462_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct adt7462_data *data;
struct device *hwmon_dev;
data = devm_kzalloc(dev, sizeof(struct adt7462_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
mutex_init(&data->lock);
dev_info(&client->dev, "%s chip found\n", client->name);
hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
data,
adt7462_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id adt7462_id[] = {
{ "adt7462", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adt7462_id);
static struct i2c_driver adt7462_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "adt7462",
},
.probe = adt7462_probe,
.id_table = adt7462_id,
.detect = adt7462_detect,
.address_list = normal_i2c,
};
module_i2c_driver(adt7462_driver);
MODULE_AUTHOR("Darrick J. Wong <[email protected]>");
MODULE_DESCRIPTION("ADT7462 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/adt7462.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* An hwmon driver for the Microchip TC74
*
* Copyright 2015 Maciej Szmigiero <[email protected]>
*
* Based on ad7414.c:
* Copyright 2006 Stefan Roese, DENX Software Engineering
* Copyright 2008 Sean MacLennan, PIKA Technologies
* Copyright 2008 Frank Edelhaeuser, Spansion Inc.
*/
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/i2c.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
/* TC74 registers */
#define TC74_REG_TEMP 0x00
#define TC74_REG_CONFIG 0x01
struct tc74_data {
struct i2c_client *client;
struct mutex lock; /* atomic read data updates */
bool valid; /* validity of fields below */
unsigned long next_update; /* In jiffies */
s8 temp_input; /* Temp value in dC */
};
static int tc74_update_device(struct device *dev)
{
struct tc74_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int ret;
ret = mutex_lock_interruptible(&data->lock);
if (ret)
return ret;
if (time_after(jiffies, data->next_update) || !data->valid) {
s32 value;
value = i2c_smbus_read_byte_data(client, TC74_REG_CONFIG);
if (value < 0) {
dev_dbg(&client->dev, "TC74_REG_CONFIG read err %d\n",
(int)value);
ret = value;
goto ret_unlock;
}
if (!(value & BIT(6))) {
/* not ready yet */
ret = -EAGAIN;
goto ret_unlock;
}
value = i2c_smbus_read_byte_data(client, TC74_REG_TEMP);
if (value < 0) {
dev_dbg(&client->dev, "TC74_REG_TEMP read err %d\n",
(int)value);
ret = value;
goto ret_unlock;
}
data->temp_input = value;
data->next_update = jiffies + HZ / 4;
data->valid = true;
}
ret_unlock:
mutex_unlock(&data->lock);
return ret;
}
static ssize_t temp_input_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct tc74_data *data = dev_get_drvdata(dev);
int ret;
ret = tc74_update_device(dev);
if (ret)
return ret;
return sprintf(buf, "%d\n", data->temp_input * 1000);
}
static SENSOR_DEVICE_ATTR_RO(temp1_input, temp_input, 0);
static struct attribute *tc74_attrs[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
NULL
};
ATTRIBUTE_GROUPS(tc74);
static int tc74_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct tc74_data *data;
struct device *hwmon_dev;
s32 conf;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -EOPNOTSUPP;
data = devm_kzalloc(dev, sizeof(struct tc74_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
mutex_init(&data->lock);
/* Make sure the chip is powered up. */
conf = i2c_smbus_read_byte_data(client, TC74_REG_CONFIG);
if (conf < 0) {
dev_err(dev, "unable to read config register\n");
return conf;
}
if (conf & 0x3f) {
dev_err(dev, "invalid config register value\n");
return -ENODEV;
}
if (conf & BIT(7)) {
s32 ret;
conf &= ~BIT(7);
ret = i2c_smbus_write_byte_data(client, TC74_REG_CONFIG, conf);
if (ret)
dev_warn(dev, "unable to disable STANDBY\n");
}
hwmon_dev = devm_hwmon_device_register_with_groups(dev,
client->name,
data, tc74_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id tc74_id[] = {
{ "tc74", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, tc74_id);
static struct i2c_driver tc74_driver = {
.driver = {
.name = "tc74",
},
.probe = tc74_probe,
.id_table = tc74_id,
};
module_i2c_driver(tc74_driver);
MODULE_AUTHOR("Maciej Szmigiero <[email protected]>");
MODULE_DESCRIPTION("TC74 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/tc74.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* jc42.c - driver for Jedec JC42.4 compliant temperature sensors
*
* Copyright (c) 2010 Ericsson AB.
*
* Derived from lm77.c by Andras BALI <[email protected]>.
*
* JC42.4 compliant temperature sensors are typically used on memory modules.
*/
#include <linux/bitops.h>
#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/regmap.h>
/* Addresses to scan */
static const unsigned short normal_i2c[] = {
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
/* JC42 registers. All registers are 16 bit. */
#define JC42_REG_CAP 0x00
#define JC42_REG_CONFIG 0x01
#define JC42_REG_TEMP_UPPER 0x02
#define JC42_REG_TEMP_LOWER 0x03
#define JC42_REG_TEMP_CRITICAL 0x04
#define JC42_REG_TEMP 0x05
#define JC42_REG_MANID 0x06
#define JC42_REG_DEVICEID 0x07
#define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
/* Status bits in temperature register */
#define JC42_ALARM_CRIT BIT(15)
#define JC42_ALARM_MAX BIT(14)
#define JC42_ALARM_MIN BIT(13)
/* Configuration register defines */
#define JC42_CFG_CRIT_ONLY BIT(2)
#define JC42_CFG_TCRIT_LOCK BIT(6)
#define JC42_CFG_EVENT_LOCK BIT(7)
#define JC42_CFG_SHUTDOWN BIT(8)
#define JC42_CFG_HYST_MASK GENMASK(10, 9)
/* Capabilities */
#define JC42_CAP_RANGE BIT(2)
/* Manufacturer IDs */
#define ADT_MANID 0x11d4 /* Analog Devices */
#define ATMEL_MANID 0x001f /* Atmel */
#define ATMEL_MANID2 0x1114 /* Atmel */
#define MAX_MANID 0x004d /* Maxim */
#define IDT_MANID 0x00b3 /* IDT */
#define MCP_MANID 0x0054 /* Microchip */
#define NXP_MANID 0x1131 /* NXP Semiconductors */
#define ONS_MANID 0x1b09 /* ON Semiconductor */
#define STM_MANID 0x104a /* ST Microelectronics */
#define GT_MANID 0x1c68 /* Giantec */
#define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */
#define SI_MANID 0x1c85 /* Seiko Instruments */
/* SMBUS register */
#define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */
/* Supported chips */
/* Analog Devices */
#define ADT7408_DEVID 0x0801
#define ADT7408_DEVID_MASK 0xffff
/* Atmel */
#define AT30TS00_DEVID 0x8201
#define AT30TS00_DEVID_MASK 0xffff
#define AT30TSE004_DEVID 0x2200
#define AT30TSE004_DEVID_MASK 0xffff
/* Giantec */
#define GT30TS00_DEVID 0x2200
#define GT30TS00_DEVID_MASK 0xff00
#define GT34TS02_DEVID 0x3300
#define GT34TS02_DEVID_MASK 0xff00
/* IDT */
#define TSE2004_DEVID 0x2200
#define TSE2004_DEVID_MASK 0xff00
#define TS3000_DEVID 0x2900 /* Also matches TSE2002 */
#define TS3000_DEVID_MASK 0xff00
#define TS3001_DEVID 0x3000
#define TS3001_DEVID_MASK 0xff00
/* Maxim */
#define MAX6604_DEVID 0x3e00
#define MAX6604_DEVID_MASK 0xffff
/* Microchip */
#define MCP9804_DEVID 0x0200
#define MCP9804_DEVID_MASK 0xfffc
#define MCP9808_DEVID 0x0400
#define MCP9808_DEVID_MASK 0xfffc
#define MCP98242_DEVID 0x2000
#define MCP98242_DEVID_MASK 0xfffc
#define MCP98243_DEVID 0x2100
#define MCP98243_DEVID_MASK 0xfffc
#define MCP98244_DEVID 0x2200
#define MCP98244_DEVID_MASK 0xfffc
#define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */
#define MCP9843_DEVID_MASK 0xfffe
/* NXP */
#define SE97_DEVID 0xa200
#define SE97_DEVID_MASK 0xfffc
#define SE98_DEVID 0xa100
#define SE98_DEVID_MASK 0xfffc
/* ON Semiconductor */
#define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */
#define CAT6095_DEVID_MASK 0xffe0
#define CAT34TS02C_DEVID 0x0a00
#define CAT34TS02C_DEVID_MASK 0xfff0
#define CAT34TS04_DEVID 0x2200
#define CAT34TS04_DEVID_MASK 0xfff0
#define N34TS04_DEVID 0x2230
#define N34TS04_DEVID_MASK 0xfff0
/* ST Microelectronics */
#define STTS424_DEVID 0x0101
#define STTS424_DEVID_MASK 0xffff
#define STTS424E_DEVID 0x0000
#define STTS424E_DEVID_MASK 0xfffe
#define STTS2002_DEVID 0x0300
#define STTS2002_DEVID_MASK 0xffff
#define STTS2004_DEVID 0x2201
#define STTS2004_DEVID_MASK 0xffff
#define STTS3000_DEVID 0x0200
#define STTS3000_DEVID_MASK 0xffff
/* Seiko Instruments */
#define S34TS04A_DEVID 0x2221
#define S34TS04A_DEVID_MASK 0xffff
static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
struct jc42_chips {
u16 manid;
u16 devid;
u16 devid_mask;
};
static struct jc42_chips jc42_chips[] = {
{ ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
{ ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
{ ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
{ GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK },
{ GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
{ IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
{ IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
{ IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
{ MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
{ MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
{ MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
{ MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
{ MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
{ MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
{ MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
{ NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
{ ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
{ ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
{ ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
{ ONS_MANID, N34TS04_DEVID, N34TS04_DEVID_MASK },
{ NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
{ SI_MANID, S34TS04A_DEVID, S34TS04A_DEVID_MASK },
{ STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
{ STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
{ STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
{ STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
{ STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
};
/* Each client has this additional data */
struct jc42_data {
struct mutex update_lock; /* protect register access */
struct regmap *regmap;
bool extended; /* true if extended range supported */
bool valid;
u16 orig_config; /* original configuration */
u16 config; /* current configuration */
};
#define JC42_TEMP_MIN_EXTENDED (-40000)
#define JC42_TEMP_MIN 0
#define JC42_TEMP_MAX 125000
static u16 jc42_temp_to_reg(long temp, bool extended)
{
int ntemp = clamp_val(temp,
extended ? JC42_TEMP_MIN_EXTENDED :
JC42_TEMP_MIN, JC42_TEMP_MAX);
/* convert from 0.001 to 0.0625 resolution */
return (ntemp * 2 / 125) & 0x1fff;
}
static int jc42_temp_from_reg(s16 reg)
{
reg = sign_extend32(reg, 12);
/* convert from 0.0625 to 0.001 resolution */
return reg * 125 / 2;
}
static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct jc42_data *data = dev_get_drvdata(dev);
unsigned int regval;
int ret, temp, hyst;
mutex_lock(&data->update_lock);
switch (attr) {
case hwmon_temp_input:
ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
if (ret)
break;
*val = jc42_temp_from_reg(regval);
break;
case hwmon_temp_min:
ret = regmap_read(data->regmap, JC42_REG_TEMP_LOWER, ®val);
if (ret)
break;
*val = jc42_temp_from_reg(regval);
break;
case hwmon_temp_max:
ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, ®val);
if (ret)
break;
*val = jc42_temp_from_reg(regval);
break;
case hwmon_temp_crit:
ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
®val);
if (ret)
break;
*val = jc42_temp_from_reg(regval);
break;
case hwmon_temp_max_hyst:
ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, ®val);
if (ret)
break;
temp = jc42_temp_from_reg(regval);
hyst = jc42_hysteresis[FIELD_GET(JC42_CFG_HYST_MASK,
data->config)];
*val = temp - hyst;
break;
case hwmon_temp_crit_hyst:
ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
®val);
if (ret)
break;
temp = jc42_temp_from_reg(regval);
hyst = jc42_hysteresis[FIELD_GET(JC42_CFG_HYST_MASK,
data->config)];
*val = temp - hyst;
break;
case hwmon_temp_min_alarm:
ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
if (ret)
break;
*val = FIELD_GET(JC42_ALARM_MIN, regval);
break;
case hwmon_temp_max_alarm:
ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
if (ret)
break;
*val = FIELD_GET(JC42_ALARM_MAX, regval);
break;
case hwmon_temp_crit_alarm:
ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val);
if (ret)
break;
*val = FIELD_GET(JC42_ALARM_CRIT, regval);
break;
default:
ret = -EOPNOTSUPP;
break;
}
mutex_unlock(&data->update_lock);
return ret;
}
static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
struct jc42_data *data = dev_get_drvdata(dev);
unsigned int regval;
int diff, hyst;
int ret;
mutex_lock(&data->update_lock);
switch (attr) {
case hwmon_temp_min:
ret = regmap_write(data->regmap, JC42_REG_TEMP_LOWER,
jc42_temp_to_reg(val, data->extended));
break;
case hwmon_temp_max:
ret = regmap_write(data->regmap, JC42_REG_TEMP_UPPER,
jc42_temp_to_reg(val, data->extended));
break;
case hwmon_temp_crit:
ret = regmap_write(data->regmap, JC42_REG_TEMP_CRITICAL,
jc42_temp_to_reg(val, data->extended));
break;
case hwmon_temp_crit_hyst:
ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
®val);
if (ret)
break;
/*
* JC42.4 compliant chips only support four hysteresis values.
* Pick best choice and go from there.
*/
val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
: JC42_TEMP_MIN) - 6000,
JC42_TEMP_MAX);
diff = jc42_temp_from_reg(regval) - val;
hyst = 0;
if (diff > 0) {
if (diff < 2250)
hyst = 1; /* 1.5 degrees C */
else if (diff < 4500)
hyst = 2; /* 3.0 degrees C */
else
hyst = 3; /* 6.0 degrees C */
}
data->config = (data->config & ~JC42_CFG_HYST_MASK) |
FIELD_PREP(JC42_CFG_HYST_MASK, hyst);
ret = regmap_write(data->regmap, JC42_REG_CONFIG,
data->config);
break;
default:
ret = -EOPNOTSUPP;
break;
}
mutex_unlock(&data->update_lock);
return ret;
}
static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
u32 attr, int channel)
{
const struct jc42_data *data = _data;
unsigned int config = data->config;
umode_t mode = 0444;
switch (attr) {
case hwmon_temp_min:
case hwmon_temp_max:
if (!(config & JC42_CFG_EVENT_LOCK))
mode |= 0200;
break;
case hwmon_temp_crit:
if (!(config & JC42_CFG_TCRIT_LOCK))
mode |= 0200;
break;
case hwmon_temp_crit_hyst:
if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK)))
mode |= 0200;
break;
case hwmon_temp_input:
case hwmon_temp_max_hyst:
case hwmon_temp_min_alarm:
case hwmon_temp_max_alarm:
case hwmon_temp_crit_alarm:
break;
default:
mode = 0;
break;
}
return mode;
}
/* Return 0 if detection is successful, -ENODEV otherwise */
static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
int i, config, cap, manid, devid;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_WORD_DATA))
return -ENODEV;
cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
if (cap < 0 || config < 0 || manid < 0 || devid < 0)
return -ENODEV;
if ((cap & 0xff00) || (config & 0xf800))
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
struct jc42_chips *chip = &jc42_chips[i];
if (manid == chip->manid &&
(devid & chip->devid_mask) == chip->devid) {
strscpy(info->type, "jc42", I2C_NAME_SIZE);
return 0;
}
}
return -ENODEV;
}
static const struct hwmon_channel_info * const jc42_info[] = {
HWMON_CHANNEL_INFO(chip,
HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
HWMON_T_CRIT | HWMON_T_MAX_HYST |
HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM),
NULL
};
static const struct hwmon_ops jc42_hwmon_ops = {
.is_visible = jc42_is_visible,
.read = jc42_read,
.write = jc42_write,
};
static const struct hwmon_chip_info jc42_chip_info = {
.ops = &jc42_hwmon_ops,
.info = jc42_info,
};
static bool jc42_readable_reg(struct device *dev, unsigned int reg)
{
return (reg >= JC42_REG_CAP && reg <= JC42_REG_DEVICEID) ||
reg == JC42_REG_SMBUS;
}
static bool jc42_writable_reg(struct device *dev, unsigned int reg)
{
return (reg >= JC42_REG_CONFIG && reg <= JC42_REG_TEMP_CRITICAL) ||
reg == JC42_REG_SMBUS;
}
static bool jc42_volatile_reg(struct device *dev, unsigned int reg)
{
return reg == JC42_REG_CONFIG || reg == JC42_REG_TEMP;
}
static const struct regmap_config jc42_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = JC42_REG_SMBUS,
.writeable_reg = jc42_writable_reg,
.readable_reg = jc42_readable_reg,
.volatile_reg = jc42_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static int jc42_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct device *hwmon_dev;
unsigned int config, cap;
struct jc42_data *data;
int ret;
data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->regmap = devm_regmap_init_i2c(client, &jc42_regmap_config);
if (IS_ERR(data->regmap))
return PTR_ERR(data->regmap);
i2c_set_clientdata(client, data);
mutex_init(&data->update_lock);
ret = regmap_read(data->regmap, JC42_REG_CAP, &cap);
if (ret)
return ret;
data->extended = !!(cap & JC42_CAP_RANGE);
if (device_property_read_bool(dev, "smbus-timeout-disable")) {
/*
* Not all chips support this register, but from a
* quick read of various datasheets no chip appears
* incompatible with the below attempt to disable
* the timeout. And the whole thing is opt-in...
*/
ret = regmap_set_bits(data->regmap, JC42_REG_SMBUS,
SMBUS_STMOUT);
if (ret)
return ret;
}
ret = regmap_read(data->regmap, JC42_REG_CONFIG, &config);
if (ret)
return ret;
data->orig_config = config;
if (config & JC42_CFG_SHUTDOWN) {
config &= ~JC42_CFG_SHUTDOWN;
regmap_write(data->regmap, JC42_REG_CONFIG, config);
}
data->config = config;
hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42",
data, &jc42_chip_info,
NULL);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static void jc42_remove(struct i2c_client *client)
{
struct jc42_data *data = i2c_get_clientdata(client);
/* Restore original configuration except hysteresis */
if ((data->config & ~JC42_CFG_HYST_MASK) !=
(data->orig_config & ~JC42_CFG_HYST_MASK)) {
int config;
config = (data->orig_config & ~JC42_CFG_HYST_MASK)
| (data->config & JC42_CFG_HYST_MASK);
regmap_write(data->regmap, JC42_REG_CONFIG, config);
}
}
#ifdef CONFIG_PM
static int jc42_suspend(struct device *dev)
{
struct jc42_data *data = dev_get_drvdata(dev);
data->config |= JC42_CFG_SHUTDOWN;
regmap_write(data->regmap, JC42_REG_CONFIG, data->config);
regcache_cache_only(data->regmap, true);
regcache_mark_dirty(data->regmap);
return 0;
}
static int jc42_resume(struct device *dev)
{
struct jc42_data *data = dev_get_drvdata(dev);
regcache_cache_only(data->regmap, false);
data->config &= ~JC42_CFG_SHUTDOWN;
regmap_write(data->regmap, JC42_REG_CONFIG, data->config);
/* Restore cached register values to hardware */
return regcache_sync(data->regmap);
}
static const struct dev_pm_ops jc42_dev_pm_ops = {
.suspend = jc42_suspend,
.resume = jc42_resume,
};
#define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
#else
#define JC42_DEV_PM_OPS NULL
#endif /* CONFIG_PM */
static const struct i2c_device_id jc42_id[] = {
{ "jc42", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, jc42_id);
#ifdef CONFIG_OF
static const struct of_device_id jc42_of_ids[] = {
{ .compatible = "jedec,jc-42.4-temp", },
{ }
};
MODULE_DEVICE_TABLE(of, jc42_of_ids);
#endif
static struct i2c_driver jc42_driver = {
.class = I2C_CLASS_SPD | I2C_CLASS_HWMON,
.driver = {
.name = "jc42",
.pm = JC42_DEV_PM_OPS,
.of_match_table = of_match_ptr(jc42_of_ids),
},
.probe = jc42_probe,
.remove = jc42_remove,
.id_table = jc42_id,
.detect = jc42_detect,
.address_list = normal_i2c,
};
module_i2c_driver(jc42_driver);
MODULE_AUTHOR("Guenter Roeck <[email protected]>");
MODULE_DESCRIPTION("JC42 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/jc42.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
* processor hardware monitoring
*
* Copyright (c) 2009 Clemens Ladisch <[email protected]>
* Copyright (c) 2020 Guenter Roeck <[email protected]>
*
* Implementation notes:
* - CCD register address information as well as the calculation to
* convert raw register values is from https://github.com/ocerman/zenpower.
* The information is not confirmed from chip datasheets, but experiments
* suggest that it provides reasonable temperature values.
*/
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <asm/amd_nb.h>
#include <asm/processor.h>
MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
MODULE_AUTHOR("Clemens Ladisch <[email protected]>");
MODULE_LICENSE("GPL");
static bool force;
module_param(force, bool, 0444);
MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
/* Provide lock for writing to NB_SMU_IND_ADDR */
static DEFINE_MUTEX(nb_smu_ind_mutex);
#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
#endif
/* CPUID function 0x80000001, ebx */
#define CPUID_PKGTYPE_MASK GENMASK(31, 28)
#define CPUID_PKGTYPE_F 0x00000000
#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
/* DRAM controller (PCI function 2) */
#define REG_DCT0_CONFIG_HIGH 0x094
#define DDR3_MODE BIT(8)
/* miscellaneous (PCI function 3) */
#define REG_HARDWARE_THERMAL_CONTROL 0x64
#define HTC_ENABLE BIT(0)
#define REG_REPORTED_TEMPERATURE 0xa4
#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
#define NB_CAP_HTC BIT(10)
/*
* For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
* and REG_REPORTED_TEMPERATURE have been moved to
* D0F0xBC_xD820_0C64 [Hardware Temperature Control]
* D0F0xBC_xD820_0CA4 [Reported Temperature Control]
*/
#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
/* Common for Zen CPU families (Family 17h and 18h and 19h and 1Ah) */
#define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800
#define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \
(offset) + ((x) * 4))
#define ZEN_CCD_TEMP_VALID BIT(11)
#define ZEN_CCD_TEMP_MASK GENMASK(10, 0)
#define ZEN_CUR_TEMP_SHIFT 21
#define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19)
#define ZEN_CUR_TEMP_TJ_SEL_MASK GENMASK(17, 16)
/*
* AMD's Industrial processor 3255 supports temperature from -40 deg to 105 deg Celsius.
* Use the model name to identify 3255 CPUs and set a flag to display negative temperature.
* Do not round off to zero for negative Tctl or Tdie values if the flag is set
*/
#define AMD_I3255_STR "3255"
struct k10temp_data {
struct pci_dev *pdev;
void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
int temp_offset;
u32 temp_adjust_mask;
u32 show_temp;
bool is_zen;
u32 ccd_offset;
bool disp_negative;
};
#define TCTL_BIT 0
#define TDIE_BIT 1
#define TCCD_BIT(x) ((x) + 2)
#define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
#define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT)
struct tctl_offset {
u8 model;
char const *id;
int offset;
};
static const struct tctl_offset tctl_offset_table[] = {
{ 0x17, "AMD Ryzen 5 1600X", 20000 },
{ 0x17, "AMD Ryzen 7 1700X", 20000 },
{ 0x17, "AMD Ryzen 7 1800X", 20000 },
{ 0x17, "AMD Ryzen 7 2700X", 10000 },
{ 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
{ 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
};
static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
{
pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
}
static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
{
pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
}
static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
unsigned int base, int offset, u32 *val)
{
mutex_lock(&nb_smu_ind_mutex);
pci_bus_write_config_dword(pdev->bus, devfn,
base, offset);
pci_bus_read_config_dword(pdev->bus, devfn,
base + 4, val);
mutex_unlock(&nb_smu_ind_mutex);
}
static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
}
static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
}
static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
{
amd_smn_read(amd_pci_dev_to_node_id(pdev),
ZEN_REPORTED_TEMP_CTRL_BASE, regval);
}
static long get_raw_temp(struct k10temp_data *data)
{
u32 regval;
long temp;
data->read_tempreg(data->pdev, ®val);
temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
if ((regval & data->temp_adjust_mask) ||
(regval & ZEN_CUR_TEMP_TJ_SEL_MASK) == ZEN_CUR_TEMP_TJ_SEL_MASK)
temp -= 49000;
return temp;
}
static const char *k10temp_temp_label[] = {
"Tctl",
"Tdie",
"Tccd1",
"Tccd2",
"Tccd3",
"Tccd4",
"Tccd5",
"Tccd6",
"Tccd7",
"Tccd8",
"Tccd9",
"Tccd10",
"Tccd11",
"Tccd12",
};
static int k10temp_read_labels(struct device *dev,
enum hwmon_sensor_types type,
u32 attr, int channel, const char **str)
{
switch (type) {
case hwmon_temp:
*str = k10temp_temp_label[channel];
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
long *val)
{
struct k10temp_data *data = dev_get_drvdata(dev);
u32 regval;
switch (attr) {
case hwmon_temp_input:
switch (channel) {
case 0: /* Tctl */
*val = get_raw_temp(data);
if (*val < 0 && !data->disp_negative)
*val = 0;
break;
case 1: /* Tdie */
*val = get_raw_temp(data) - data->temp_offset;
if (*val < 0 && !data->disp_negative)
*val = 0;
break;
case 2 ... 13: /* Tccd{1-12} */
amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
®val);
*val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
break;
default:
return -EOPNOTSUPP;
}
break;
case hwmon_temp_max:
*val = 70 * 1000;
break;
case hwmon_temp_crit:
data->read_htcreg(data->pdev, ®val);
*val = ((regval >> 16) & 0x7f) * 500 + 52000;
break;
case hwmon_temp_crit_hyst:
data->read_htcreg(data->pdev, ®val);
*val = (((regval >> 16) & 0x7f)
- ((regval >> 24) & 0xf)) * 500 + 52000;
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
switch (type) {
case hwmon_temp:
return k10temp_read_temp(dev, attr, channel, val);
default:
return -EOPNOTSUPP;
}
}
static umode_t k10temp_is_visible(const void *_data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
const struct k10temp_data *data = _data;
struct pci_dev *pdev = data->pdev;
u32 reg;
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_input:
if (!HAVE_TEMP(data, channel))
return 0;
break;
case hwmon_temp_max:
if (channel || data->is_zen)
return 0;
break;
case hwmon_temp_crit:
case hwmon_temp_crit_hyst:
if (channel || !data->read_htcreg)
return 0;
pci_read_config_dword(pdev,
REG_NORTHBRIDGE_CAPABILITIES,
®);
if (!(reg & NB_CAP_HTC))
return 0;
data->read_htcreg(data->pdev, ®);
if (!(reg & HTC_ENABLE))
return 0;
break;
case hwmon_temp_label:
/* Show temperature labels only on Zen CPUs */
if (!data->is_zen || !HAVE_TEMP(data, channel))
return 0;
break;
default:
return 0;
}
break;
default:
return 0;
}
return 0444;
}
static bool has_erratum_319(struct pci_dev *pdev)
{
u32 pkg_type, reg_dram_cfg;
if (boot_cpu_data.x86 != 0x10)
return false;
/*
* Erratum 319: The thermal sensor of Socket F/AM2+ processors
* may be unreliable.
*/
pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
if (pkg_type == CPUID_PKGTYPE_F)
return true;
if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
return false;
/* DDR3 memory implies socket AM3, which is good */
pci_bus_read_config_dword(pdev->bus,
PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
if (reg_dram_cfg & DDR3_MODE)
return false;
/*
* Unfortunately it is possible to run a socket AM3 CPU with DDR2
* memory. We blacklist all the cores which do exist in socket AM2+
* format. It still isn't perfect, as RB-C2 cores exist in both AM2+
* and AM3 formats, but that's the best we can do.
*/
return boot_cpu_data.x86_model < 4 ||
(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
}
static const struct hwmon_channel_info * const k10temp_info[] = {
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT | HWMON_T_MAX |
HWMON_T_CRIT | HWMON_T_CRIT_HYST |
HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL),
NULL
};
static const struct hwmon_ops k10temp_hwmon_ops = {
.is_visible = k10temp_is_visible,
.read = k10temp_read,
.read_string = k10temp_read_labels,
};
static const struct hwmon_chip_info k10temp_chip_info = {
.ops = &k10temp_hwmon_ops,
.info = k10temp_info,
};
static void k10temp_get_ccd_support(struct pci_dev *pdev,
struct k10temp_data *data, int limit)
{
u32 regval;
int i;
for (i = 0; i < limit; i++) {
amd_smn_read(amd_pci_dev_to_node_id(pdev),
ZEN_CCD_TEMP(data->ccd_offset, i), ®val);
if (regval & ZEN_CCD_TEMP_VALID)
data->show_temp |= BIT(TCCD_BIT(i));
}
}
static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
int unreliable = has_erratum_319(pdev);
struct device *dev = &pdev->dev;
struct k10temp_data *data;
struct device *hwmon_dev;
int i;
if (unreliable) {
if (!force) {
dev_err(dev,
"unreliable CPU thermal sensor; monitoring disabled\n");
return -ENODEV;
}
dev_warn(dev,
"unreliable CPU thermal sensor; check erratum 319\n");
}
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->pdev = pdev;
data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */
if (boot_cpu_data.x86 == 0x17 &&
strstr(boot_cpu_data.x86_model_id, AMD_I3255_STR)) {
data->disp_negative = true;
}
if (boot_cpu_data.x86 == 0x15 &&
((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
(boot_cpu_data.x86_model & 0xf0) == 0x70)) {
data->read_htcreg = read_htcreg_nb_f15;
data->read_tempreg = read_tempreg_nb_f15;
} else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
data->read_tempreg = read_tempreg_nb_zen;
data->is_zen = true;
switch (boot_cpu_data.x86_model) {
case 0x1: /* Zen */
case 0x8: /* Zen+ */
case 0x11: /* Zen APU */
case 0x18: /* Zen+ APU */
data->ccd_offset = 0x154;
k10temp_get_ccd_support(pdev, data, 4);
break;
case 0x31: /* Zen2 Threadripper */
case 0x60: /* Renoir */
case 0x68: /* Lucienne */
case 0x71: /* Zen2 */
data->ccd_offset = 0x154;
k10temp_get_ccd_support(pdev, data, 8);
break;
case 0xa0 ... 0xaf:
data->ccd_offset = 0x300;
k10temp_get_ccd_support(pdev, data, 8);
break;
}
} else if (boot_cpu_data.x86 == 0x19) {
data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
data->read_tempreg = read_tempreg_nb_zen;
data->is_zen = true;
switch (boot_cpu_data.x86_model) {
case 0x0 ... 0x1: /* Zen3 SP3/TR */
case 0x21: /* Zen3 Ryzen Desktop */
case 0x50 ... 0x5f: /* Green Sardine */
data->ccd_offset = 0x154;
k10temp_get_ccd_support(pdev, data, 8);
break;
case 0x40 ... 0x4f: /* Yellow Carp */
data->ccd_offset = 0x300;
k10temp_get_ccd_support(pdev, data, 8);
break;
case 0x60 ... 0x6f:
case 0x70 ... 0x7f:
data->ccd_offset = 0x308;
k10temp_get_ccd_support(pdev, data, 8);
break;
case 0x10 ... 0x1f:
case 0xa0 ... 0xaf:
data->ccd_offset = 0x300;
k10temp_get_ccd_support(pdev, data, 12);
break;
}
} else if (boot_cpu_data.x86 == 0x1a) {
data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
data->read_tempreg = read_tempreg_nb_zen;
data->is_zen = true;
} else {
data->read_htcreg = read_htcreg_pci;
data->read_tempreg = read_tempreg_pci;
}
for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
const struct tctl_offset *entry = &tctl_offset_table[i];
if (boot_cpu_data.x86 == entry->model &&
strstr(boot_cpu_data.x86_model_id, entry->id)) {
data->show_temp |= BIT(TDIE_BIT); /* show Tdie */
data->temp_offset = entry->offset;
break;
}
}
hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
&k10temp_chip_info,
NULL);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct pci_device_id k10temp_id_table[] = {
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) },
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
{}
};
MODULE_DEVICE_TABLE(pci, k10temp_id_table);
static struct pci_driver k10temp_driver = {
.name = "k10temp",
.id_table = k10temp_id_table,
.probe = k10temp_probe,
};
module_pci_driver(k10temp_driver);
|
linux-master
|
drivers/hwmon/k10temp.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* atxp1.c - kernel module for setting CPU VID and general purpose
* I/Os using the Attansic ATXP1 chip.
*
* The ATXP1 can reside on I2C addresses 0x37 or 0x4e. The chip is
* not auto-detected by the driver and must be instantiated explicitly.
* See Documentation/i2c/instantiating-devices.rst for more information.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-vid.h>
#include <linux/err.h>
#include <linux/kstrtox.h>
#include <linux/mutex.h>
#include <linux/sysfs.h>
#include <linux/slab.h>
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("System voltages control via Attansic ATXP1");
MODULE_VERSION("0.6.3");
MODULE_AUTHOR("Sebastian Witt <[email protected]>");
#define ATXP1_VID 0x00
#define ATXP1_CVID 0x01
#define ATXP1_GPIO1 0x06
#define ATXP1_GPIO2 0x0a
#define ATXP1_VIDENA 0x20
#define ATXP1_VIDMASK 0x1f
#define ATXP1_GPIO1MASK 0x0f
struct atxp1_data {
struct i2c_client *client;
struct mutex update_lock;
unsigned long last_updated;
bool valid;
struct {
u8 vid; /* VID output register */
u8 cpu_vid; /* VID input from CPU */
u8 gpio1; /* General purpose I/O register 1 */
u8 gpio2; /* General purpose I/O register 2 */
} reg;
u8 vrm; /* Detected CPU VRM */
};
static struct atxp1_data *atxp1_update_device(struct device *dev)
{
struct atxp1_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
/* Update local register data */
data->reg.vid = i2c_smbus_read_byte_data(client, ATXP1_VID);
data->reg.cpu_vid = i2c_smbus_read_byte_data(client,
ATXP1_CVID);
data->reg.gpio1 = i2c_smbus_read_byte_data(client, ATXP1_GPIO1);
data->reg.gpio2 = i2c_smbus_read_byte_data(client, ATXP1_GPIO2);
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
/* sys file functions for cpu0_vid */
static ssize_t cpu0_vid_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int size;
struct atxp1_data *data;
data = atxp1_update_device(dev);
size = sprintf(buf, "%d\n", vid_from_reg(data->reg.vid & ATXP1_VIDMASK,
data->vrm));
return size;
}
static ssize_t cpu0_vid_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct atxp1_data *data = atxp1_update_device(dev);
struct i2c_client *client = data->client;
int vid, cvid;
unsigned long vcore;
int err;
err = kstrtoul(buf, 10, &vcore);
if (err)
return err;
vcore /= 25;
vcore *= 25;
/* Calculate VID */
vid = vid_to_reg(vcore, data->vrm);
if (vid < 0) {
dev_err(dev, "VID calculation failed.\n");
return vid;
}
/*
* If output enabled, use control register value.
* Otherwise original CPU VID
*/
if (data->reg.vid & ATXP1_VIDENA)
cvid = data->reg.vid & ATXP1_VIDMASK;
else
cvid = data->reg.cpu_vid;
/* Nothing changed, aborting */
if (vid == cvid)
return count;
dev_dbg(dev, "Setting VCore to %d mV (0x%02x)\n", (int)vcore, vid);
/* Write every 25 mV step to increase stability */
if (cvid > vid) {
for (; cvid >= vid; cvid--)
i2c_smbus_write_byte_data(client,
ATXP1_VID, cvid | ATXP1_VIDENA);
} else {
for (; cvid <= vid; cvid++)
i2c_smbus_write_byte_data(client,
ATXP1_VID, cvid | ATXP1_VIDENA);
}
data->valid = false;
return count;
}
/*
* CPU core reference voltage
* unit: millivolt
*/
static DEVICE_ATTR_RW(cpu0_vid);
/* sys file functions for GPIO1 */
static ssize_t gpio1_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int size;
struct atxp1_data *data;
data = atxp1_update_device(dev);
size = sprintf(buf, "0x%02x\n", data->reg.gpio1 & ATXP1_GPIO1MASK);
return size;
}
static ssize_t gpio1_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct atxp1_data *data = atxp1_update_device(dev);
struct i2c_client *client = data->client;
unsigned long value;
int err;
err = kstrtoul(buf, 16, &value);
if (err)
return err;
value &= ATXP1_GPIO1MASK;
if (value != (data->reg.gpio1 & ATXP1_GPIO1MASK)) {
dev_info(dev, "Writing 0x%x to GPIO1.\n", (unsigned int)value);
i2c_smbus_write_byte_data(client, ATXP1_GPIO1, value);
data->valid = false;
}
return count;
}
/*
* GPIO1 data register
* unit: Four bit as hex (e.g. 0x0f)
*/
static DEVICE_ATTR_RW(gpio1);
/* sys file functions for GPIO2 */
static ssize_t gpio2_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int size;
struct atxp1_data *data;
data = atxp1_update_device(dev);
size = sprintf(buf, "0x%02x\n", data->reg.gpio2);
return size;
}
static ssize_t gpio2_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct atxp1_data *data = atxp1_update_device(dev);
struct i2c_client *client = data->client;
unsigned long value;
int err;
err = kstrtoul(buf, 16, &value);
if (err)
return err;
value &= 0xff;
if (value != data->reg.gpio2) {
dev_info(dev, "Writing 0x%x to GPIO1.\n", (unsigned int)value);
i2c_smbus_write_byte_data(client, ATXP1_GPIO2, value);
data->valid = false;
}
return count;
}
/*
* GPIO2 data register
* unit: Eight bit as hex (e.g. 0xff)
*/
static DEVICE_ATTR_RW(gpio2);
static struct attribute *atxp1_attrs[] = {
&dev_attr_gpio1.attr,
&dev_attr_gpio2.attr,
&dev_attr_cpu0_vid.attr,
NULL
};
ATTRIBUTE_GROUPS(atxp1);
static int atxp1_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct atxp1_data *data;
struct device *hwmon_dev;
data = devm_kzalloc(dev, sizeof(struct atxp1_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
/* Get VRM */
data->vrm = vid_which_vrm();
if (data->vrm != 90 && data->vrm != 91) {
dev_err(dev, "atxp1: Not supporting VRM %d.%d\n",
data->vrm / 10, data->vrm % 10);
return -ENODEV;
}
data->client = client;
mutex_init(&data->update_lock);
hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
data,
atxp1_groups);
if (IS_ERR(hwmon_dev))
return PTR_ERR(hwmon_dev);
dev_info(dev, "Using VRM: %d.%d\n", data->vrm / 10, data->vrm % 10);
return 0;
};
static const struct i2c_device_id atxp1_id[] = {
{ "atxp1", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, atxp1_id);
static struct i2c_driver atxp1_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "atxp1",
},
.probe = atxp1_probe,
.id_table = atxp1_id,
};
module_i2c_driver(atxp1_driver);
|
linux-master
|
drivers/hwmon/atxp1.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* STTS751 sensor driver
*
* Copyright (C) 2016-2017 Istituto Italiano di Tecnologia - RBCS - EDL
* Robotics, Brain and Cognitive Sciences department
* Electronic Design Laboratory
*
* Written by Andrea Merello <[email protected]>
*
* Based on LM95241 driver and LM90 driver
*/
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/util_macros.h>
#define DEVNAME "stts751"
static const unsigned short normal_i2c[] = {
0x48, 0x49, 0x38, 0x39, /* STTS751-0 */
0x4A, 0x4B, 0x3A, 0x3B, /* STTS751-1 */
I2C_CLIENT_END };
#define STTS751_REG_TEMP_H 0x00
#define STTS751_REG_STATUS 0x01
#define STTS751_STATUS_TRIPT BIT(0)
#define STTS751_STATUS_TRIPL BIT(5)
#define STTS751_STATUS_TRIPH BIT(6)
#define STTS751_REG_TEMP_L 0x02
#define STTS751_REG_CONF 0x03
#define STTS751_CONF_RES_MASK 0x0C
#define STTS751_CONF_RES_SHIFT 2
#define STTS751_CONF_EVENT_DIS BIT(7)
#define STTS751_CONF_STOP BIT(6)
#define STTS751_REG_RATE 0x04
#define STTS751_REG_HLIM_H 0x05
#define STTS751_REG_HLIM_L 0x06
#define STTS751_REG_LLIM_H 0x07
#define STTS751_REG_LLIM_L 0x08
#define STTS751_REG_TLIM 0x20
#define STTS751_REG_HYST 0x21
#define STTS751_REG_SMBUS_TO 0x22
#define STTS751_REG_PROD_ID 0xFD
#define STTS751_REG_MAN_ID 0xFE
#define STTS751_REG_REV_ID 0xFF
#define STTS751_0_PROD_ID 0x00
#define STTS751_1_PROD_ID 0x01
#define ST_MAN_ID 0x53
/*
* Possible update intervals are (in mS):
* 16000, 8000, 4000, 2000, 1000, 500, 250, 125, 62.5, 31.25
* However we are not going to complicate things too much and we stick to the
* approx value in mS.
*/
static const int stts751_intervals[] = {
16000, 8000, 4000, 2000, 1000, 500, 250, 125, 63, 31
};
static const struct i2c_device_id stts751_id[] = {
{ "stts751", 0 },
{ }
};
static const struct of_device_id __maybe_unused stts751_of_match[] = {
{ .compatible = "stts751" },
{ },
};
MODULE_DEVICE_TABLE(of, stts751_of_match);
struct stts751_priv {
struct device *dev;
struct i2c_client *client;
struct mutex access_lock;
u8 interval;
int res;
int event_max, event_min;
int therm;
int hyst;
bool smbus_timeout;
int temp;
unsigned long last_update, last_alert_update;
u8 config;
bool min_alert, max_alert, therm_trip;
bool data_valid, alert_valid;
bool notify_max, notify_min;
};
/*
* These functions converts temperature from HW format to integer format and
* vice-vers. They are (mostly) taken from lm90 driver. Unit is in mC.
*/
static int stts751_to_deg(s16 hw_val)
{
return hw_val * 125 / 32;
}
static s32 stts751_to_hw(int val)
{
return DIV_ROUND_CLOSEST(val, 125) * 32;
}
static int stts751_adjust_resolution(struct stts751_priv *priv)
{
u8 res;
switch (priv->interval) {
case 9:
/* 10 bits */
res = 0;
break;
case 8:
/* 11 bits */
res = 1;
break;
default:
/* 12 bits */
res = 3;
break;
}
if (priv->res == res)
return 0;
priv->config &= ~STTS751_CONF_RES_MASK;
priv->config |= res << STTS751_CONF_RES_SHIFT;
dev_dbg(&priv->client->dev, "setting res %d. config %x",
res, priv->config);
priv->res = res;
return i2c_smbus_write_byte_data(priv->client,
STTS751_REG_CONF, priv->config);
}
static int stts751_update_temp(struct stts751_priv *priv)
{
s32 integer1, integer2, frac;
/*
* There is a trick here, like in the lm90 driver. We have to read two
* registers to get the sensor temperature, but we have to beware a
* conversion could occur between the readings. We could use the
* one-shot conversion register, but we don't want to do this (disables
* hardware monitoring). So the solution used here is to read the high
* byte once, then the low byte, then the high byte again. If the new
* high byte matches the old one, then we have a valid reading. Else we
* have to read the low byte again, and now we believe we have a correct
* reading.
*/
integer1 = i2c_smbus_read_byte_data(priv->client, STTS751_REG_TEMP_H);
if (integer1 < 0) {
dev_dbg(&priv->client->dev,
"I2C read failed (temp H). ret: %x\n", integer1);
return integer1;
}
frac = i2c_smbus_read_byte_data(priv->client, STTS751_REG_TEMP_L);
if (frac < 0) {
dev_dbg(&priv->client->dev,
"I2C read failed (temp L). ret: %x\n", frac);
return frac;
}
integer2 = i2c_smbus_read_byte_data(priv->client, STTS751_REG_TEMP_H);
if (integer2 < 0) {
dev_dbg(&priv->client->dev,
"I2C 2nd read failed (temp H). ret: %x\n", integer2);
return integer2;
}
if (integer1 != integer2) {
frac = i2c_smbus_read_byte_data(priv->client,
STTS751_REG_TEMP_L);
if (frac < 0) {
dev_dbg(&priv->client->dev,
"I2C 2nd read failed (temp L). ret: %x\n",
frac);
return frac;
}
}
priv->temp = stts751_to_deg((integer1 << 8) | frac);
return 0;
}
static int stts751_set_temp_reg16(struct stts751_priv *priv, int temp,
u8 hreg, u8 lreg)
{
s32 hwval;
int ret;
hwval = stts751_to_hw(temp);
ret = i2c_smbus_write_byte_data(priv->client, hreg, hwval >> 8);
if (ret)
return ret;
return i2c_smbus_write_byte_data(priv->client, lreg, hwval & 0xff);
}
static int stts751_set_temp_reg8(struct stts751_priv *priv, int temp, u8 reg)
{
s32 hwval;
hwval = stts751_to_hw(temp);
return i2c_smbus_write_byte_data(priv->client, reg, hwval >> 8);
}
static int stts751_read_reg16(struct stts751_priv *priv, int *temp,
u8 hreg, u8 lreg)
{
int integer, frac;
integer = i2c_smbus_read_byte_data(priv->client, hreg);
if (integer < 0)
return integer;
frac = i2c_smbus_read_byte_data(priv->client, lreg);
if (frac < 0)
return frac;
*temp = stts751_to_deg((integer << 8) | frac);
return 0;
}
static int stts751_read_reg8(struct stts751_priv *priv, int *temp, u8 reg)
{
int integer;
integer = i2c_smbus_read_byte_data(priv->client, reg);
if (integer < 0)
return integer;
*temp = stts751_to_deg(integer << 8);
return 0;
}
/*
* Update alert flags without waiting for cache to expire. We detects alerts
* immediately for the sake of the alert handler; we still need to deal with
* caching to workaround the fact that alarm flags int the status register,
* despite what the datasheet claims, gets always cleared on read.
*/
static int stts751_update_alert(struct stts751_priv *priv)
{
int ret;
bool conv_done;
int cache_time = msecs_to_jiffies(stts751_intervals[priv->interval]);
/*
* Add another 10% because if we run faster than the HW conversion
* rate we will end up in reporting incorrectly alarms.
*/
cache_time += cache_time / 10;
ret = i2c_smbus_read_byte_data(priv->client, STTS751_REG_STATUS);
if (ret < 0)
return ret;
dev_dbg(&priv->client->dev, "status reg %x\n", ret);
conv_done = ret & (STTS751_STATUS_TRIPH | STTS751_STATUS_TRIPL);
/*
* Reset the cache if the cache time expired, or if we are sure
* we have valid data from a device conversion, or if we know
* our cache has been never written.
*
* Note that when the cache has been never written the point is
* to correctly initialize the timestamp, rather than clearing
* the cache values.
*
* Note that updating the cache timestamp when we get an alarm flag
* is required, otherwise we could incorrectly report alarms to be zero.
*/
if (time_after(jiffies, priv->last_alert_update + cache_time) ||
conv_done || !priv->alert_valid) {
priv->max_alert = false;
priv->min_alert = false;
priv->alert_valid = true;
priv->last_alert_update = jiffies;
dev_dbg(&priv->client->dev, "invalidating alert cache\n");
}
priv->max_alert |= !!(ret & STTS751_STATUS_TRIPH);
priv->min_alert |= !!(ret & STTS751_STATUS_TRIPL);
priv->therm_trip = !!(ret & STTS751_STATUS_TRIPT);
dev_dbg(&priv->client->dev, "max_alert: %d, min_alert: %d, therm_trip: %d\n",
priv->max_alert, priv->min_alert, priv->therm_trip);
return 0;
}
static void stts751_alert(struct i2c_client *client,
enum i2c_alert_protocol type, unsigned int data)
{
int ret;
struct stts751_priv *priv = i2c_get_clientdata(client);
if (type != I2C_PROTOCOL_SMBUS_ALERT)
return;
dev_dbg(&client->dev, "alert!");
mutex_lock(&priv->access_lock);
ret = stts751_update_alert(priv);
if (ret < 0) {
/* default to worst case */
priv->max_alert = true;
priv->min_alert = true;
dev_warn(priv->dev,
"Alert received, but can't communicate to the device. Triggering all alarms!");
}
if (priv->max_alert) {
if (priv->notify_max)
dev_notice(priv->dev, "got alert for HIGH temperature");
priv->notify_max = false;
/* unblock alert poll */
sysfs_notify(&priv->dev->kobj, NULL, "temp1_max_alarm");
}
if (priv->min_alert) {
if (priv->notify_min)
dev_notice(priv->dev, "got alert for LOW temperature");
priv->notify_min = false;
/* unblock alert poll */
sysfs_notify(&priv->dev->kobj, NULL, "temp1_min_alarm");
}
if (priv->min_alert || priv->max_alert)
kobject_uevent(&priv->dev->kobj, KOBJ_CHANGE);
mutex_unlock(&priv->access_lock);
}
static int stts751_update(struct stts751_priv *priv)
{
int ret;
int cache_time = msecs_to_jiffies(stts751_intervals[priv->interval]);
if (time_after(jiffies, priv->last_update + cache_time) ||
!priv->data_valid) {
ret = stts751_update_temp(priv);
if (ret)
return ret;
ret = stts751_update_alert(priv);
if (ret)
return ret;
priv->data_valid = true;
priv->last_update = jiffies;
}
return 0;
}
static ssize_t max_alarm_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int ret;
struct stts751_priv *priv = dev_get_drvdata(dev);
mutex_lock(&priv->access_lock);
ret = stts751_update(priv);
if (!ret)
priv->notify_max = true;
mutex_unlock(&priv->access_lock);
if (ret < 0)
return ret;
return sysfs_emit(buf, "%d\n", priv->max_alert);
}
static ssize_t min_alarm_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int ret;
struct stts751_priv *priv = dev_get_drvdata(dev);
mutex_lock(&priv->access_lock);
ret = stts751_update(priv);
if (!ret)
priv->notify_min = true;
mutex_unlock(&priv->access_lock);
if (ret < 0)
return ret;
return sysfs_emit(buf, "%d\n", priv->min_alert);
}
static ssize_t input_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int ret;
struct stts751_priv *priv = dev_get_drvdata(dev);
mutex_lock(&priv->access_lock);
ret = stts751_update(priv);
mutex_unlock(&priv->access_lock);
if (ret < 0)
return ret;
return sysfs_emit(buf, "%d\n", priv->temp);
}
static ssize_t therm_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct stts751_priv *priv = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d\n", priv->therm);
}
static ssize_t therm_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int ret;
long temp;
struct stts751_priv *priv = dev_get_drvdata(dev);
if (kstrtol(buf, 10, &temp) < 0)
return -EINVAL;
/* HW works in range -64C to +127.937C */
temp = clamp_val(temp, -64000, 127937);
mutex_lock(&priv->access_lock);
ret = stts751_set_temp_reg8(priv, temp, STTS751_REG_TLIM);
if (ret)
goto exit;
dev_dbg(&priv->client->dev, "setting therm %ld", temp);
/*
* hysteresis reg is relative to therm, so the HW does not need to be
* adjusted, we need to update our local copy only.
*/
priv->hyst = temp - (priv->therm - priv->hyst);
priv->therm = temp;
exit:
mutex_unlock(&priv->access_lock);
if (ret)
return ret;
return count;
}
static ssize_t hyst_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct stts751_priv *priv = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d\n", priv->hyst);
}
static ssize_t hyst_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int ret;
long temp;
struct stts751_priv *priv = dev_get_drvdata(dev);
if (kstrtol(buf, 10, &temp) < 0)
return -EINVAL;
mutex_lock(&priv->access_lock);
/* HW works in range -64C to +127.937C */
temp = clamp_val(temp, -64000, priv->therm);
priv->hyst = temp;
dev_dbg(&priv->client->dev, "setting hyst %ld", temp);
temp = priv->therm - temp;
ret = stts751_set_temp_reg8(priv, temp, STTS751_REG_HYST);
mutex_unlock(&priv->access_lock);
if (ret)
return ret;
return count;
}
static ssize_t therm_trip_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int ret;
struct stts751_priv *priv = dev_get_drvdata(dev);
mutex_lock(&priv->access_lock);
ret = stts751_update(priv);
mutex_unlock(&priv->access_lock);
if (ret < 0)
return ret;
return sysfs_emit(buf, "%d\n", priv->therm_trip);
}
static ssize_t max_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct stts751_priv *priv = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d\n", priv->event_max);
}
static ssize_t max_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int ret;
long temp;
struct stts751_priv *priv = dev_get_drvdata(dev);
if (kstrtol(buf, 10, &temp) < 0)
return -EINVAL;
mutex_lock(&priv->access_lock);
/* HW works in range -64C to +127.937C */
temp = clamp_val(temp, priv->event_min, 127937);
ret = stts751_set_temp_reg16(priv, temp,
STTS751_REG_HLIM_H, STTS751_REG_HLIM_L);
if (ret)
goto exit;
dev_dbg(&priv->client->dev, "setting event max %ld", temp);
priv->event_max = temp;
ret = count;
exit:
mutex_unlock(&priv->access_lock);
return ret;
}
static ssize_t min_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct stts751_priv *priv = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d\n", priv->event_min);
}
static ssize_t min_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int ret;
long temp;
struct stts751_priv *priv = dev_get_drvdata(dev);
if (kstrtol(buf, 10, &temp) < 0)
return -EINVAL;
mutex_lock(&priv->access_lock);
/* HW works in range -64C to +127.937C */
temp = clamp_val(temp, -64000, priv->event_max);
ret = stts751_set_temp_reg16(priv, temp,
STTS751_REG_LLIM_H, STTS751_REG_LLIM_L);
if (ret)
goto exit;
dev_dbg(&priv->client->dev, "setting event min %ld", temp);
priv->event_min = temp;
ret = count;
exit:
mutex_unlock(&priv->access_lock);
return ret;
}
static ssize_t interval_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct stts751_priv *priv = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d\n",
stts751_intervals[priv->interval]);
}
static ssize_t interval_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
unsigned long val;
int idx;
int ret = count;
struct stts751_priv *priv = dev_get_drvdata(dev);
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
idx = find_closest_descending(val, stts751_intervals,
ARRAY_SIZE(stts751_intervals));
dev_dbg(&priv->client->dev, "setting interval. req:%lu, idx: %d, val: %d",
val, idx, stts751_intervals[idx]);
mutex_lock(&priv->access_lock);
if (priv->interval == idx)
goto exit;
/*
* In early development stages I've become suspicious about the chip
* starting to misbehave if I ever set, even briefly, an invalid
* configuration. While I'm not sure this is really needed, be
* conservative and set rate/resolution in such an order that avoids
* passing through an invalid configuration.
*/
/* speed up: lower the resolution, then modify convrate */
if (priv->interval < idx) {
dev_dbg(&priv->client->dev, "lower resolution, then modify convrate");
priv->interval = idx;
ret = stts751_adjust_resolution(priv);
if (ret)
goto exit;
}
ret = i2c_smbus_write_byte_data(priv->client, STTS751_REG_RATE, idx);
if (ret)
goto exit;
/* slow down: modify convrate, then raise resolution */
if (priv->interval != idx) {
dev_dbg(&priv->client->dev, "modify convrate, then raise resolution");
priv->interval = idx;
ret = stts751_adjust_resolution(priv);
if (ret)
goto exit;
}
ret = count;
exit:
mutex_unlock(&priv->access_lock);
return ret;
}
static int stts751_detect(struct i2c_client *new_client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = new_client->adapter;
const char *name;
int tmp;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
tmp = i2c_smbus_read_byte_data(new_client, STTS751_REG_MAN_ID);
if (tmp != ST_MAN_ID)
return -ENODEV;
/* lower temperaure registers always have bits 0-3 set to zero */
tmp = i2c_smbus_read_byte_data(new_client, STTS751_REG_TEMP_L);
if (tmp & 0xf)
return -ENODEV;
tmp = i2c_smbus_read_byte_data(new_client, STTS751_REG_HLIM_L);
if (tmp & 0xf)
return -ENODEV;
tmp = i2c_smbus_read_byte_data(new_client, STTS751_REG_LLIM_L);
if (tmp & 0xf)
return -ENODEV;
/* smbus timeout register always have bits 0-7 set to zero */
tmp = i2c_smbus_read_byte_data(new_client, STTS751_REG_SMBUS_TO);
if (tmp & 0x7f)
return -ENODEV;
tmp = i2c_smbus_read_byte_data(new_client, STTS751_REG_PROD_ID);
switch (tmp) {
case STTS751_0_PROD_ID:
name = "STTS751-0";
break;
case STTS751_1_PROD_ID:
name = "STTS751-1";
break;
default:
return -ENODEV;
}
dev_dbg(&new_client->dev, "Chip %s detected", name);
strscpy(info->type, stts751_id[0].name, I2C_NAME_SIZE);
return 0;
}
static int stts751_read_chip_config(struct stts751_priv *priv)
{
int ret;
int tmp;
ret = i2c_smbus_read_byte_data(priv->client, STTS751_REG_CONF);
if (ret < 0)
return ret;
priv->config = ret;
priv->res = (ret & STTS751_CONF_RES_MASK) >> STTS751_CONF_RES_SHIFT;
ret = i2c_smbus_read_byte_data(priv->client, STTS751_REG_RATE);
if (ret < 0)
return ret;
if (ret >= ARRAY_SIZE(stts751_intervals)) {
dev_err(priv->dev, "Unrecognized conversion rate 0x%x\n", ret);
return -ENODEV;
}
priv->interval = ret;
ret = stts751_read_reg16(priv, &priv->event_max,
STTS751_REG_HLIM_H, STTS751_REG_HLIM_L);
if (ret)
return ret;
ret = stts751_read_reg16(priv, &priv->event_min,
STTS751_REG_LLIM_H, STTS751_REG_LLIM_L);
if (ret)
return ret;
ret = stts751_read_reg8(priv, &priv->therm, STTS751_REG_TLIM);
if (ret)
return ret;
ret = stts751_read_reg8(priv, &tmp, STTS751_REG_HYST);
if (ret)
return ret;
priv->hyst = priv->therm - tmp;
return 0;
}
static SENSOR_DEVICE_ATTR_RO(temp1_input, input, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_min, min, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_max, max, 0);
static SENSOR_DEVICE_ATTR_RO(temp1_min_alarm, min_alarm, 0);
static SENSOR_DEVICE_ATTR_RO(temp1_max_alarm, max_alarm, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_crit, therm, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_crit_hyst, hyst, 0);
static SENSOR_DEVICE_ATTR_RO(temp1_crit_alarm, therm_trip, 0);
static SENSOR_DEVICE_ATTR_RW(update_interval, interval, 0);
static struct attribute *stts751_attrs[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_min.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp1_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_crit.dev_attr.attr,
&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
&sensor_dev_attr_temp1_crit_alarm.dev_attr.attr,
&sensor_dev_attr_update_interval.dev_attr.attr,
NULL
};
ATTRIBUTE_GROUPS(stts751);
static int stts751_probe(struct i2c_client *client)
{
struct stts751_priv *priv;
int ret;
bool smbus_nto;
int rev_id;
priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->client = client;
priv->notify_max = true;
priv->notify_min = true;
i2c_set_clientdata(client, priv);
mutex_init(&priv->access_lock);
if (device_property_present(&client->dev,
"smbus-timeout-disable")) {
smbus_nto = device_property_read_bool(&client->dev,
"smbus-timeout-disable");
ret = i2c_smbus_write_byte_data(client, STTS751_REG_SMBUS_TO,
smbus_nto ? 0 : 0x80);
if (ret)
return ret;
}
rev_id = i2c_smbus_read_byte_data(client, STTS751_REG_REV_ID);
if (rev_id < 0)
return -ENODEV;
if (rev_id != 0x1) {
dev_dbg(&client->dev, "Chip revision 0x%x is untested\n",
rev_id);
}
ret = stts751_read_chip_config(priv);
if (ret)
return ret;
priv->config &= ~(STTS751_CONF_STOP | STTS751_CONF_EVENT_DIS);
ret = i2c_smbus_write_byte_data(client, STTS751_REG_CONF, priv->config);
if (ret)
return ret;
priv->dev = devm_hwmon_device_register_with_groups(&client->dev,
client->name, priv,
stts751_groups);
return PTR_ERR_OR_ZERO(priv->dev);
}
MODULE_DEVICE_TABLE(i2c, stts751_id);
static struct i2c_driver stts751_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = DEVNAME,
.of_match_table = of_match_ptr(stts751_of_match),
},
.probe = stts751_probe,
.id_table = stts751_id,
.detect = stts751_detect,
.alert = stts751_alert,
.address_list = normal_i2c,
};
module_i2c_driver(stts751_driver);
MODULE_AUTHOR("Andrea Merello <[email protected]>");
MODULE_DESCRIPTION("STTS751 sensor driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/stts751.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ntc_thermistor.c - NTC Thermistors
*
* Copyright (C) 2010 Samsung Electronics
* MyungJoo Ham <[email protected]>
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/math64.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/err.h>
#include <linux/fixp-arith.h>
#include <linux/iio/consumer.h>
#include <linux/hwmon.h>
enum ntc_thermistor_type {
TYPE_B57330V2103,
TYPE_B57891S0103,
TYPE_NCPXXWB473,
TYPE_NCPXXWF104,
TYPE_NCPXXWL333,
TYPE_NCPXXXH103,
};
struct ntc_compensation {
int temp_c;
unsigned int ohm;
};
/*
* Used as index in a zero-terminated array, holes not allowed so
* that NTC_LAST is the first empty array entry.
*/
enum {
NTC_B57330V2103,
NTC_B57891S0103,
NTC_NCP03WB473,
NTC_NCP03WF104,
NTC_NCP15WB473,
NTC_NCP15WL333,
NTC_NCP15XH103,
NTC_NCP18WB473,
NTC_NCP21WB473,
NTC_SSG1404001221,
NTC_LAST,
};
static const struct platform_device_id ntc_thermistor_id[] = {
[NTC_B57330V2103] = { "b57330v2103", TYPE_B57330V2103 },
[NTC_B57891S0103] = { "b57891s0103", TYPE_B57891S0103 },
[NTC_NCP03WB473] = { "ncp03wb473", TYPE_NCPXXWB473 },
[NTC_NCP03WF104] = { "ncp03wf104", TYPE_NCPXXWF104 },
[NTC_NCP15WB473] = { "ncp15wb473", TYPE_NCPXXWB473 },
[NTC_NCP15WL333] = { "ncp15wl333", TYPE_NCPXXWL333 },
[NTC_NCP15XH103] = { "ncp15xh103", TYPE_NCPXXXH103 },
[NTC_NCP18WB473] = { "ncp18wb473", TYPE_NCPXXWB473 },
[NTC_NCP21WB473] = { "ncp21wb473", TYPE_NCPXXWB473 },
[NTC_SSG1404001221] = { "ssg1404_001221", TYPE_NCPXXWB473 },
[NTC_LAST] = { },
};
/*
* A compensation table should be sorted by the values of .ohm
* in descending order.
* The following compensation tables are from the specification of Murata NTC
* Thermistors Datasheet
*/
static const struct ntc_compensation ncpXXwb473[] = {
{ .temp_c = -40, .ohm = 1747920 },
{ .temp_c = -35, .ohm = 1245428 },
{ .temp_c = -30, .ohm = 898485 },
{ .temp_c = -25, .ohm = 655802 },
{ .temp_c = -20, .ohm = 483954 },
{ .temp_c = -15, .ohm = 360850 },
{ .temp_c = -10, .ohm = 271697 },
{ .temp_c = -5, .ohm = 206463 },
{ .temp_c = 0, .ohm = 158214 },
{ .temp_c = 5, .ohm = 122259 },
{ .temp_c = 10, .ohm = 95227 },
{ .temp_c = 15, .ohm = 74730 },
{ .temp_c = 20, .ohm = 59065 },
{ .temp_c = 25, .ohm = 47000 },
{ .temp_c = 30, .ohm = 37643 },
{ .temp_c = 35, .ohm = 30334 },
{ .temp_c = 40, .ohm = 24591 },
{ .temp_c = 45, .ohm = 20048 },
{ .temp_c = 50, .ohm = 16433 },
{ .temp_c = 55, .ohm = 13539 },
{ .temp_c = 60, .ohm = 11209 },
{ .temp_c = 65, .ohm = 9328 },
{ .temp_c = 70, .ohm = 7798 },
{ .temp_c = 75, .ohm = 6544 },
{ .temp_c = 80, .ohm = 5518 },
{ .temp_c = 85, .ohm = 4674 },
{ .temp_c = 90, .ohm = 3972 },
{ .temp_c = 95, .ohm = 3388 },
{ .temp_c = 100, .ohm = 2902 },
{ .temp_c = 105, .ohm = 2494 },
{ .temp_c = 110, .ohm = 2150 },
{ .temp_c = 115, .ohm = 1860 },
{ .temp_c = 120, .ohm = 1615 },
{ .temp_c = 125, .ohm = 1406 },
};
static const struct ntc_compensation ncpXXwl333[] = {
{ .temp_c = -40, .ohm = 1610154 },
{ .temp_c = -35, .ohm = 1130850 },
{ .temp_c = -30, .ohm = 802609 },
{ .temp_c = -25, .ohm = 575385 },
{ .temp_c = -20, .ohm = 416464 },
{ .temp_c = -15, .ohm = 304219 },
{ .temp_c = -10, .ohm = 224193 },
{ .temp_c = -5, .ohm = 166623 },
{ .temp_c = 0, .ohm = 124850 },
{ .temp_c = 5, .ohm = 94287 },
{ .temp_c = 10, .ohm = 71747 },
{ .temp_c = 15, .ohm = 54996 },
{ .temp_c = 20, .ohm = 42455 },
{ .temp_c = 25, .ohm = 33000 },
{ .temp_c = 30, .ohm = 25822 },
{ .temp_c = 35, .ohm = 20335 },
{ .temp_c = 40, .ohm = 16115 },
{ .temp_c = 45, .ohm = 12849 },
{ .temp_c = 50, .ohm = 10306 },
{ .temp_c = 55, .ohm = 8314 },
{ .temp_c = 60, .ohm = 6746 },
{ .temp_c = 65, .ohm = 5503 },
{ .temp_c = 70, .ohm = 4513 },
{ .temp_c = 75, .ohm = 3721 },
{ .temp_c = 80, .ohm = 3084 },
{ .temp_c = 85, .ohm = 2569 },
{ .temp_c = 90, .ohm = 2151 },
{ .temp_c = 95, .ohm = 1809 },
{ .temp_c = 100, .ohm = 1529 },
{ .temp_c = 105, .ohm = 1299 },
{ .temp_c = 110, .ohm = 1108 },
{ .temp_c = 115, .ohm = 949 },
{ .temp_c = 120, .ohm = 817 },
{ .temp_c = 125, .ohm = 707 },
};
static const struct ntc_compensation ncpXXwf104[] = {
{ .temp_c = -40, .ohm = 4397119 },
{ .temp_c = -35, .ohm = 3088599 },
{ .temp_c = -30, .ohm = 2197225 },
{ .temp_c = -25, .ohm = 1581881 },
{ .temp_c = -20, .ohm = 1151037 },
{ .temp_c = -15, .ohm = 846579 },
{ .temp_c = -10, .ohm = 628988 },
{ .temp_c = -5, .ohm = 471632 },
{ .temp_c = 0, .ohm = 357012 },
{ .temp_c = 5, .ohm = 272500 },
{ .temp_c = 10, .ohm = 209710 },
{ .temp_c = 15, .ohm = 162651 },
{ .temp_c = 20, .ohm = 127080 },
{ .temp_c = 25, .ohm = 100000 },
{ .temp_c = 30, .ohm = 79222 },
{ .temp_c = 35, .ohm = 63167 },
{ .temp_c = 40, .ohm = 50677 },
{ .temp_c = 45, .ohm = 40904 },
{ .temp_c = 50, .ohm = 33195 },
{ .temp_c = 55, .ohm = 27091 },
{ .temp_c = 60, .ohm = 22224 },
{ .temp_c = 65, .ohm = 18323 },
{ .temp_c = 70, .ohm = 15184 },
{ .temp_c = 75, .ohm = 12635 },
{ .temp_c = 80, .ohm = 10566 },
{ .temp_c = 85, .ohm = 8873 },
{ .temp_c = 90, .ohm = 7481 },
{ .temp_c = 95, .ohm = 6337 },
{ .temp_c = 100, .ohm = 5384 },
{ .temp_c = 105, .ohm = 4594 },
{ .temp_c = 110, .ohm = 3934 },
{ .temp_c = 115, .ohm = 3380 },
{ .temp_c = 120, .ohm = 2916 },
{ .temp_c = 125, .ohm = 2522 },
};
static const struct ntc_compensation ncpXXxh103[] = {
{ .temp_c = -40, .ohm = 247565 },
{ .temp_c = -35, .ohm = 181742 },
{ .temp_c = -30, .ohm = 135128 },
{ .temp_c = -25, .ohm = 101678 },
{ .temp_c = -20, .ohm = 77373 },
{ .temp_c = -15, .ohm = 59504 },
{ .temp_c = -10, .ohm = 46222 },
{ .temp_c = -5, .ohm = 36244 },
{ .temp_c = 0, .ohm = 28674 },
{ .temp_c = 5, .ohm = 22878 },
{ .temp_c = 10, .ohm = 18399 },
{ .temp_c = 15, .ohm = 14910 },
{ .temp_c = 20, .ohm = 12169 },
{ .temp_c = 25, .ohm = 10000 },
{ .temp_c = 30, .ohm = 8271 },
{ .temp_c = 35, .ohm = 6883 },
{ .temp_c = 40, .ohm = 5762 },
{ .temp_c = 45, .ohm = 4851 },
{ .temp_c = 50, .ohm = 4105 },
{ .temp_c = 55, .ohm = 3492 },
{ .temp_c = 60, .ohm = 2985 },
{ .temp_c = 65, .ohm = 2563 },
{ .temp_c = 70, .ohm = 2211 },
{ .temp_c = 75, .ohm = 1915 },
{ .temp_c = 80, .ohm = 1666 },
{ .temp_c = 85, .ohm = 1454 },
{ .temp_c = 90, .ohm = 1275 },
{ .temp_c = 95, .ohm = 1121 },
{ .temp_c = 100, .ohm = 990 },
{ .temp_c = 105, .ohm = 876 },
{ .temp_c = 110, .ohm = 779 },
{ .temp_c = 115, .ohm = 694 },
{ .temp_c = 120, .ohm = 620 },
{ .temp_c = 125, .ohm = 556 },
};
/*
* The following compensation tables are from the specifications in EPCOS NTC
* Thermistors Datasheets
*/
static const struct ntc_compensation b57330v2103[] = {
{ .temp_c = -40, .ohm = 190030 },
{ .temp_c = -35, .ohm = 145360 },
{ .temp_c = -30, .ohm = 112060 },
{ .temp_c = -25, .ohm = 87041 },
{ .temp_c = -20, .ohm = 68104 },
{ .temp_c = -15, .ohm = 53665 },
{ .temp_c = -10, .ohm = 42576 },
{ .temp_c = -5, .ohm = 34001 },
{ .temp_c = 0, .ohm = 27326 },
{ .temp_c = 5, .ohm = 22096 },
{ .temp_c = 10, .ohm = 17973 },
{ .temp_c = 15, .ohm = 14703 },
{ .temp_c = 20, .ohm = 12090 },
{ .temp_c = 25, .ohm = 10000 },
{ .temp_c = 30, .ohm = 8311 },
{ .temp_c = 35, .ohm = 6941 },
{ .temp_c = 40, .ohm = 5825 },
{ .temp_c = 45, .ohm = 4911 },
{ .temp_c = 50, .ohm = 4158 },
{ .temp_c = 55, .ohm = 3536 },
{ .temp_c = 60, .ohm = 3019 },
{ .temp_c = 65, .ohm = 2588 },
{ .temp_c = 70, .ohm = 2227 },
{ .temp_c = 75, .ohm = 1924 },
{ .temp_c = 80, .ohm = 1668 },
{ .temp_c = 85, .ohm = 1451 },
{ .temp_c = 90, .ohm = 1266 },
{ .temp_c = 95, .ohm = 1108 },
{ .temp_c = 100, .ohm = 973 },
{ .temp_c = 105, .ohm = 857 },
{ .temp_c = 110, .ohm = 757 },
{ .temp_c = 115, .ohm = 671 },
{ .temp_c = 120, .ohm = 596 },
{ .temp_c = 125, .ohm = 531 },
};
static const struct ntc_compensation b57891s0103[] = {
{ .temp_c = -55.0, .ohm = 878900 },
{ .temp_c = -50.0, .ohm = 617590 },
{ .temp_c = -45.0, .ohm = 439340 },
{ .temp_c = -40.0, .ohm = 316180 },
{ .temp_c = -35.0, .ohm = 230060 },
{ .temp_c = -30.0, .ohm = 169150 },
{ .temp_c = -25.0, .ohm = 125550 },
{ .temp_c = -20.0, .ohm = 94143 },
{ .temp_c = -15.0, .ohm = 71172 },
{ .temp_c = -10.0, .ohm = 54308 },
{ .temp_c = -5.0, .ohm = 41505 },
{ .temp_c = 0.0, .ohm = 32014 },
{ .temp_c = 5.0, .ohm = 25011 },
{ .temp_c = 10.0, .ohm = 19691 },
{ .temp_c = 15.0, .ohm = 15618 },
{ .temp_c = 20.0, .ohm = 12474 },
{ .temp_c = 25.0, .ohm = 10000 },
{ .temp_c = 30.0, .ohm = 8080 },
{ .temp_c = 35.0, .ohm = 6569 },
{ .temp_c = 40.0, .ohm = 5372 },
{ .temp_c = 45.0, .ohm = 4424 },
{ .temp_c = 50.0, .ohm = 3661 },
{ .temp_c = 55.0, .ohm = 3039 },
{ .temp_c = 60.0, .ohm = 2536 },
{ .temp_c = 65.0, .ohm = 2128 },
{ .temp_c = 70.0, .ohm = 1794 },
{ .temp_c = 75.0, .ohm = 1518 },
{ .temp_c = 80.0, .ohm = 1290 },
{ .temp_c = 85.0, .ohm = 1100 },
{ .temp_c = 90.0, .ohm = 942 },
{ .temp_c = 95.0, .ohm = 809 },
{ .temp_c = 100.0, .ohm = 697 },
{ .temp_c = 105.0, .ohm = 604 },
{ .temp_c = 110.0, .ohm = 525 },
{ .temp_c = 115.0, .ohm = 457 },
{ .temp_c = 120.0, .ohm = 400 },
{ .temp_c = 125.0, .ohm = 351 },
{ .temp_c = 130.0, .ohm = 308 },
{ .temp_c = 135.0, .ohm = 272 },
{ .temp_c = 140.0, .ohm = 240 },
{ .temp_c = 145.0, .ohm = 213 },
{ .temp_c = 150.0, .ohm = 189 },
{ .temp_c = 155.0, .ohm = 168 },
};
struct ntc_type {
const struct ntc_compensation *comp;
int n_comp;
};
#define NTC_TYPE(ntc, compensation) \
[(ntc)] = { .comp = (compensation), .n_comp = ARRAY_SIZE(compensation) }
static const struct ntc_type ntc_type[] = {
NTC_TYPE(TYPE_B57330V2103, b57330v2103),
NTC_TYPE(TYPE_B57891S0103, b57891s0103),
NTC_TYPE(TYPE_NCPXXWB473, ncpXXwb473),
NTC_TYPE(TYPE_NCPXXWF104, ncpXXwf104),
NTC_TYPE(TYPE_NCPXXWL333, ncpXXwl333),
NTC_TYPE(TYPE_NCPXXXH103, ncpXXxh103),
};
/*
* pullup_uV, pullup_ohm, pulldown_ohm, and connect are required.
*
* How to setup pullup_ohm, pulldown_ohm, and connect is
* described at Documentation/hwmon/ntc_thermistor.rst
*
* pullup/down_ohm: 0 for infinite / not-connected
*
* chan: iio_channel pointer to communicate with the ADC which the
* thermistor is using for conversion of the analog values.
*/
struct ntc_data {
const struct ntc_compensation *comp;
int n_comp;
unsigned int pullup_uv;
unsigned int pullup_ohm;
unsigned int pulldown_ohm;
enum { NTC_CONNECTED_POSITIVE, NTC_CONNECTED_GROUND } connect;
struct iio_channel *chan;
};
static int ntc_adc_iio_read(struct ntc_data *data)
{
struct iio_channel *channel = data->chan;
int uv, ret;
ret = iio_read_channel_processed_scale(channel, &uv, 1000);
if (ret < 0) {
int raw;
/*
* This fallback uses a raw read and then
* assumes the ADC is 12 bits, scaling with
* a factor 1000 to get to microvolts.
*/
ret = iio_read_channel_raw(channel, &raw);
if (ret < 0) {
pr_err("read channel() error: %d\n", ret);
return ret;
}
ret = iio_convert_raw_to_processed(channel, raw, &uv, 1000);
if (ret < 0) {
/* Assume 12 bit ADC with vref at pullup_uv */
uv = (data->pullup_uv * (s64)raw) >> 12;
}
}
return uv;
}
static inline u64 div64_u64_safe(u64 dividend, u64 divisor)
{
if (divisor == 0 && dividend == 0)
return 0;
if (divisor == 0)
return UINT_MAX;
return div64_u64(dividend, divisor);
}
static int get_ohm_of_thermistor(struct ntc_data *data, unsigned int uv)
{
u32 puv = data->pullup_uv;
u64 n, puo, pdo;
puo = data->pullup_ohm;
pdo = data->pulldown_ohm;
if (uv == 0)
return (data->connect == NTC_CONNECTED_POSITIVE) ?
INT_MAX : 0;
if (uv >= puv)
return (data->connect == NTC_CONNECTED_POSITIVE) ?
0 : INT_MAX;
if (data->connect == NTC_CONNECTED_POSITIVE && puo == 0)
n = div_u64(pdo * (puv - uv), uv);
else if (data->connect == NTC_CONNECTED_GROUND && pdo == 0)
n = div_u64(puo * uv, puv - uv);
else if (data->connect == NTC_CONNECTED_POSITIVE)
n = div64_u64_safe(pdo * puo * (puv - uv),
puo * uv - pdo * (puv - uv));
else
n = div64_u64_safe(pdo * puo * uv, pdo * (puv - uv) - puo * uv);
if (n > INT_MAX)
n = INT_MAX;
return n;
}
static void lookup_comp(struct ntc_data *data, unsigned int ohm,
int *i_low, int *i_high)
{
int start, end, mid;
/*
* Handle special cases: Resistance is higher than or equal to
* resistance in first table entry, or resistance is lower or equal
* to resistance in last table entry.
* In these cases, return i_low == i_high, either pointing to the
* beginning or to the end of the table depending on the condition.
*/
if (ohm >= data->comp[0].ohm) {
*i_low = 0;
*i_high = 0;
return;
}
if (ohm <= data->comp[data->n_comp - 1].ohm) {
*i_low = data->n_comp - 1;
*i_high = data->n_comp - 1;
return;
}
/* Do a binary search on compensation table */
start = 0;
end = data->n_comp;
while (start < end) {
mid = start + (end - start) / 2;
/*
* start <= mid < end
* data->comp[start].ohm > ohm >= data->comp[end].ohm
*
* We could check for "ohm == data->comp[mid].ohm" here, but
* that is a quite unlikely condition, and we would have to
* check again after updating start. Check it at the end instead
* for simplicity.
*/
if (ohm >= data->comp[mid].ohm) {
end = mid;
} else {
start = mid + 1;
/*
* ohm >= data->comp[start].ohm might be true here,
* since we set start to mid + 1. In that case, we are
* done. We could keep going, but the condition is quite
* likely to occur, so it is worth checking for it.
*/
if (ohm >= data->comp[start].ohm)
end = start;
}
/*
* start <= end
* data->comp[start].ohm >= ohm >= data->comp[end].ohm
*/
}
/*
* start == end
* ohm >= data->comp[end].ohm
*/
*i_low = end;
if (ohm == data->comp[end].ohm)
*i_high = end;
else
*i_high = end - 1;
}
static int get_temp_mc(struct ntc_data *data, unsigned int ohm)
{
int low, high;
int temp;
lookup_comp(data, ohm, &low, &high);
/*
* First multiplying the table temperatures with 1000 to get to
* millicentigrades (which is what we want) and then interpolating
* will give the best precision.
*/
temp = fixp_linear_interpolate(data->comp[low].ohm,
data->comp[low].temp_c * 1000,
data->comp[high].ohm,
data->comp[high].temp_c * 1000,
ohm);
return temp;
}
static int ntc_thermistor_get_ohm(struct ntc_data *data)
{
int read_uv;
read_uv = ntc_adc_iio_read(data);
if (read_uv < 0)
return read_uv;
return get_ohm_of_thermistor(data, read_uv);
}
static int ntc_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct ntc_data *data = dev_get_drvdata(dev);
int ohm;
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_input:
ohm = ntc_thermistor_get_ohm(data);
if (ohm < 0)
return ohm;
*val = get_temp_mc(data, ohm);
return 0;
case hwmon_temp_type:
*val = 4;
return 0;
default:
break;
}
break;
default:
break;
}
return -EINVAL;
}
static umode_t ntc_is_visible(const void *data, enum hwmon_sensor_types type,
u32 attr, int channel)
{
if (type == hwmon_temp) {
switch (attr) {
case hwmon_temp_input:
case hwmon_temp_type:
return 0444;
default:
break;
}
}
return 0;
}
static const struct hwmon_channel_info * const ntc_info[] = {
HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_TYPE),
NULL
};
static const struct hwmon_ops ntc_hwmon_ops = {
.is_visible = ntc_is_visible,
.read = ntc_read,
};
static const struct hwmon_chip_info ntc_chip_info = {
.ops = &ntc_hwmon_ops,
.info = ntc_info,
};
static int ntc_thermistor_parse_props(struct device *dev,
struct ntc_data *data)
{
struct iio_channel *chan;
enum iio_chan_type type;
int ret;
chan = devm_iio_channel_get(dev, NULL);
if (IS_ERR(chan))
return PTR_ERR(chan);
ret = iio_get_channel_type(chan, &type);
if (ret < 0)
return ret;
if (type != IIO_VOLTAGE)
return -EINVAL;
ret = device_property_read_u32(dev, "pullup-uv", &data->pullup_uv);
if (ret)
return dev_err_probe(dev, ret, "pullup-uv not specified\n");
ret = device_property_read_u32(dev, "pullup-ohm", &data->pullup_ohm);
if (ret)
return dev_err_probe(dev, ret, "pullup-ohm not specified\n");
ret = device_property_read_u32(dev, "pulldown-ohm", &data->pulldown_ohm);
if (ret)
return dev_err_probe(dev, ret, "pulldown-ohm not specified\n");
if (device_property_read_bool(dev, "connected-positive"))
data->connect = NTC_CONNECTED_POSITIVE;
else /* status change should be possible if not always on. */
data->connect = NTC_CONNECTED_GROUND;
data->chan = chan;
return 0;
}
static int ntc_thermistor_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct platform_device_id *pdev_id;
struct device *hwmon_dev;
struct ntc_data *data;
int ret;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
ret = ntc_thermistor_parse_props(dev, data);
if (ret)
return ret;
if (data->pullup_uv == 0 ||
(data->pullup_ohm == 0 && data->connect ==
NTC_CONNECTED_GROUND) ||
(data->pulldown_ohm == 0 && data->connect ==
NTC_CONNECTED_POSITIVE) ||
(data->connect != NTC_CONNECTED_POSITIVE &&
data->connect != NTC_CONNECTED_GROUND)) {
dev_err(dev, "Required data to use NTC driver not supplied.\n");
return -EINVAL;
}
pdev_id = device_get_match_data(dev);
if (pdev_id->driver_data >= ARRAY_SIZE(ntc_type)) {
dev_err(dev, "Unknown device type: %lu(%s)\n",
pdev_id->driver_data, pdev_id->name);
return -EINVAL;
}
data->comp = ntc_type[pdev_id->driver_data].comp;
data->n_comp = ntc_type[pdev_id->driver_data].n_comp;
hwmon_dev = devm_hwmon_device_register_with_info(dev, pdev_id->name,
data, &ntc_chip_info,
NULL);
if (IS_ERR(hwmon_dev)) {
dev_err(dev, "unable to register as hwmon device.\n");
return PTR_ERR(hwmon_dev);
}
dev_info(dev, "Thermistor type: %s successfully probed.\n",
pdev_id->name);
return 0;
}
static const struct of_device_id ntc_match[] = {
{ .compatible = "epcos,b57330v2103",
.data = &ntc_thermistor_id[NTC_B57330V2103]},
{ .compatible = "epcos,b57891s0103",
.data = &ntc_thermistor_id[NTC_B57891S0103] },
{ .compatible = "murata,ncp03wb473",
.data = &ntc_thermistor_id[NTC_NCP03WB473] },
{ .compatible = "murata,ncp03wf104",
.data = &ntc_thermistor_id[NTC_NCP03WF104] },
{ .compatible = "murata,ncp15wb473",
.data = &ntc_thermistor_id[NTC_NCP15WB473] },
{ .compatible = "murata,ncp15wl333",
.data = &ntc_thermistor_id[NTC_NCP15WL333] },
{ .compatible = "murata,ncp15xh103",
.data = &ntc_thermistor_id[NTC_NCP15XH103] },
{ .compatible = "murata,ncp18wb473",
.data = &ntc_thermistor_id[NTC_NCP18WB473] },
{ .compatible = "murata,ncp21wb473",
.data = &ntc_thermistor_id[NTC_NCP21WB473] },
{ .compatible = "samsung,1404-001221",
.data = &ntc_thermistor_id[NTC_SSG1404001221] },
/* Usage of vendor name "ntc" is deprecated */
{ .compatible = "ntc,ncp03wb473",
.data = &ntc_thermistor_id[NTC_NCP03WB473] },
{ .compatible = "ntc,ncp15wb473",
.data = &ntc_thermistor_id[NTC_NCP15WB473] },
{ .compatible = "ntc,ncp15wl333",
.data = &ntc_thermistor_id[NTC_NCP15WL333] },
{ .compatible = "ntc,ncp18wb473",
.data = &ntc_thermistor_id[NTC_NCP18WB473] },
{ .compatible = "ntc,ncp21wb473",
.data = &ntc_thermistor_id[NTC_NCP21WB473] },
{ },
};
MODULE_DEVICE_TABLE(of, ntc_match);
static struct platform_driver ntc_thermistor_driver = {
.driver = {
.name = "ntc-thermistor",
.of_match_table = ntc_match,
},
.probe = ntc_thermistor_probe,
.id_table = ntc_thermistor_id,
};
module_platform_driver(ntc_thermistor_driver);
MODULE_DESCRIPTION("NTC Thermistor Driver");
MODULE_AUTHOR("MyungJoo Ham <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ntc-thermistor");
|
linux-master
|
drivers/hwmon/ntc_thermistor.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/* Lantiq cpu temperature sensor driver
*
* Copyright (C) 2017 Florian Eckert <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <lantiq_soc.h>
/* gphy1 configuration register contains cpu temperature */
#define CGU_GPHY1_CR 0x0040
#define CGU_TEMP_PD BIT(19)
static void ltq_cputemp_enable(void)
{
ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR);
}
static void ltq_cputemp_disable(void *data)
{
ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR);
}
static int ltq_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *temp)
{
int value;
switch (attr) {
case hwmon_temp_input:
/* get the temperature including one decimal place */
value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF;
value = value * 5;
/* range -38 to +154 °C, register value zero is -38.0 °C */
value -= 380;
/* scale temp to millidegree */
value = value * 100;
break;
default:
return -EOPNOTSUPP;
}
*temp = value;
return 0;
}
static umode_t ltq_is_visible(const void *_data, enum hwmon_sensor_types type,
u32 attr, int channel)
{
if (type != hwmon_temp)
return 0;
switch (attr) {
case hwmon_temp_input:
return 0444;
default:
return 0;
}
}
static const struct hwmon_channel_info * const ltq_info[] = {
HWMON_CHANNEL_INFO(chip,
HWMON_C_REGISTER_TZ),
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT),
NULL
};
static const struct hwmon_ops ltq_hwmon_ops = {
.is_visible = ltq_is_visible,
.read = ltq_read,
};
static const struct hwmon_chip_info ltq_chip_info = {
.ops = <q_hwmon_ops,
.info = ltq_info,
};
static int ltq_cputemp_probe(struct platform_device *pdev)
{
struct device *hwmon_dev;
int err = 0;
/* available on vr9 v1.2 SoCs only */
if (ltq_soc_type() != SOC_TYPE_VR9_2)
return -ENODEV;
err = devm_add_action(&pdev->dev, ltq_cputemp_disable, NULL);
if (err)
return err;
ltq_cputemp_enable();
hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
"ltq_cputemp",
NULL,
<q_chip_info,
NULL);
if (IS_ERR(hwmon_dev)) {
dev_err(&pdev->dev, "Failed to register as hwmon device");
return PTR_ERR(hwmon_dev);
}
return 0;
}
const struct of_device_id ltq_cputemp_match[] = {
{ .compatible = "lantiq,cputemp" },
{},
};
MODULE_DEVICE_TABLE(of, ltq_cputemp_match);
static struct platform_driver ltq_cputemp_driver = {
.probe = ltq_cputemp_probe,
.driver = {
.name = "ltq-cputemp",
.of_match_table = ltq_cputemp_match,
},
};
module_platform_driver(ltq_cputemp_driver);
MODULE_AUTHOR("Florian Eckert <[email protected]>");
MODULE_DESCRIPTION("Lantiq cpu temperature sensor driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/ltq-cputemp.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for +/-1 degree C, SMBus-Compatible Remote/Local Temperature Sensor
* with Overtemperature Alarm
*
* Copyright (C) 2011 AppearTV AS
*
* Derived from:
*
* Based on the max1619 driver.
* Copyright (C) 2003-2004 Oleksij Rempel <[email protected]>
* Jean Delvare <[email protected]>
*
* The MAX6642 is a sensor chip made by Maxim.
* It reports up to two temperatures (its own plus up to
* one external one). Complete datasheet can be
* obtained from Maxim's website at:
* http://datasheets.maxim-ic.com/en/ds/MAX6642.pdf
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/sysfs.h>
static const unsigned short normal_i2c[] = {
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, I2C_CLIENT_END };
/*
* The MAX6642 registers
*/
#define MAX6642_REG_R_MAN_ID 0xFE
#define MAX6642_REG_R_CONFIG 0x03
#define MAX6642_REG_W_CONFIG 0x09
#define MAX6642_REG_R_STATUS 0x02
#define MAX6642_REG_R_LOCAL_TEMP 0x00
#define MAX6642_REG_R_LOCAL_TEMPL 0x11
#define MAX6642_REG_R_LOCAL_HIGH 0x05
#define MAX6642_REG_W_LOCAL_HIGH 0x0B
#define MAX6642_REG_R_REMOTE_TEMP 0x01
#define MAX6642_REG_R_REMOTE_TEMPL 0x10
#define MAX6642_REG_R_REMOTE_HIGH 0x07
#define MAX6642_REG_W_REMOTE_HIGH 0x0D
/*
* Conversions
*/
static int temp_from_reg10(int val)
{
return val * 250;
}
static int temp_from_reg(int val)
{
return val * 1000;
}
static int temp_to_reg(int val)
{
return val / 1000;
}
/*
* Client data (each client gets its own)
*/
struct max6642_data {
struct i2c_client *client;
struct mutex update_lock;
bool valid; /* zero until following fields are valid */
unsigned long last_updated; /* in jiffies */
/* registers values */
u16 temp_input[2]; /* local/remote */
u16 temp_high[2]; /* local/remote */
u8 alarms;
};
/*
* Real code
*/
static void max6642_init_client(struct max6642_data *data,
struct i2c_client *client)
{
u8 config;
/*
* Start the conversions.
*/
config = i2c_smbus_read_byte_data(client, MAX6642_REG_R_CONFIG);
if (config & 0x40)
i2c_smbus_write_byte_data(client, MAX6642_REG_W_CONFIG,
config & 0xBF); /* run */
data->temp_high[0] = i2c_smbus_read_byte_data(client,
MAX6642_REG_R_LOCAL_HIGH);
data->temp_high[1] = i2c_smbus_read_byte_data(client,
MAX6642_REG_R_REMOTE_HIGH);
}
/* Return 0 if detection is successful, -ENODEV otherwise */
static int max6642_detect(struct i2c_client *client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
u8 reg_config, reg_status, man_id;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
/* identification */
man_id = i2c_smbus_read_byte_data(client, MAX6642_REG_R_MAN_ID);
if (man_id != 0x4D)
return -ENODEV;
/* sanity check */
if (i2c_smbus_read_byte_data(client, 0x04) != 0x4D
|| i2c_smbus_read_byte_data(client, 0x06) != 0x4D
|| i2c_smbus_read_byte_data(client, 0xff) != 0x4D)
return -ENODEV;
/*
* We read the config and status register, the 4 lower bits in the
* config register should be zero and bit 5, 3, 1 and 0 should be
* zero in the status register.
*/
reg_config = i2c_smbus_read_byte_data(client, MAX6642_REG_R_CONFIG);
if ((reg_config & 0x0f) != 0x00)
return -ENODEV;
/* in between, another round of sanity checks */
if (i2c_smbus_read_byte_data(client, 0x04) != reg_config
|| i2c_smbus_read_byte_data(client, 0x06) != reg_config
|| i2c_smbus_read_byte_data(client, 0xff) != reg_config)
return -ENODEV;
reg_status = i2c_smbus_read_byte_data(client, MAX6642_REG_R_STATUS);
if ((reg_status & 0x2b) != 0x00)
return -ENODEV;
strscpy(info->type, "max6642", I2C_NAME_SIZE);
return 0;
}
static struct max6642_data *max6642_update_device(struct device *dev)
{
struct max6642_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
u16 val, tmp;
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
dev_dbg(dev, "Updating max6642 data.\n");
val = i2c_smbus_read_byte_data(client,
MAX6642_REG_R_LOCAL_TEMPL);
tmp = (val >> 6) & 3;
val = i2c_smbus_read_byte_data(client,
MAX6642_REG_R_LOCAL_TEMP);
val = (val << 2) | tmp;
data->temp_input[0] = val;
val = i2c_smbus_read_byte_data(client,
MAX6642_REG_R_REMOTE_TEMPL);
tmp = (val >> 6) & 3;
val = i2c_smbus_read_byte_data(client,
MAX6642_REG_R_REMOTE_TEMP);
val = (val << 2) | tmp;
data->temp_input[1] = val;
data->alarms = i2c_smbus_read_byte_data(client,
MAX6642_REG_R_STATUS);
data->last_updated = jiffies;
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
/*
* Sysfs stuff
*/
static ssize_t temp_max10_show(struct device *dev,
struct device_attribute *dev_attr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
struct max6642_data *data = max6642_update_device(dev);
return sprintf(buf, "%d\n",
temp_from_reg10(data->temp_input[attr->index]));
}
static ssize_t temp_max_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct sensor_device_attribute_2 *attr2 = to_sensor_dev_attr_2(attr);
struct max6642_data *data = max6642_update_device(dev);
return sprintf(buf, "%d\n", temp_from_reg(data->temp_high[attr2->nr]));
}
static ssize_t temp_max_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct sensor_device_attribute_2 *attr2 = to_sensor_dev_attr_2(attr);
struct max6642_data *data = dev_get_drvdata(dev);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err < 0)
return err;
mutex_lock(&data->update_lock);
data->temp_high[attr2->nr] = clamp_val(temp_to_reg(val), 0, 255);
i2c_smbus_write_byte_data(data->client, attr2->index,
data->temp_high[attr2->nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t alarm_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int bitnr = to_sensor_dev_attr(attr)->index;
struct max6642_data *data = max6642_update_device(dev);
return sprintf(buf, "%d\n", (data->alarms >> bitnr) & 1);
}
static SENSOR_DEVICE_ATTR_RO(temp1_input, temp_max10, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_input, temp_max10, 1);
static SENSOR_DEVICE_ATTR_2_RW(temp1_max, temp_max, 0,
MAX6642_REG_W_LOCAL_HIGH);
static SENSOR_DEVICE_ATTR_2_RW(temp2_max, temp_max, 1,
MAX6642_REG_W_REMOTE_HIGH);
static SENSOR_DEVICE_ATTR_RO(temp2_fault, alarm, 2);
static SENSOR_DEVICE_ATTR_RO(temp1_max_alarm, alarm, 6);
static SENSOR_DEVICE_ATTR_RO(temp2_max_alarm, alarm, 4);
static struct attribute *max6642_attrs[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp2_max.dev_attr.attr,
&sensor_dev_attr_temp2_fault.dev_attr.attr,
&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_max_alarm.dev_attr.attr,
NULL
};
ATTRIBUTE_GROUPS(max6642);
static int max6642_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct max6642_data *data;
struct device *hwmon_dev;
data = devm_kzalloc(dev, sizeof(struct max6642_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
mutex_init(&data->update_lock);
/* Initialize the MAX6642 chip */
max6642_init_client(data, client);
hwmon_dev = devm_hwmon_device_register_with_groups(&client->dev,
client->name, data,
max6642_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
/*
* Driver data (common to all clients)
*/
static const struct i2c_device_id max6642_id[] = {
{ "max6642", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max6642_id);
static struct i2c_driver max6642_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "max6642",
},
.probe = max6642_probe,
.id_table = max6642_id,
.detect = max6642_detect,
.address_list = normal_i2c,
};
module_i2c_driver(max6642_driver);
MODULE_AUTHOR("Per Dalen <[email protected]>");
MODULE_DESCRIPTION("MAX6642 sensor driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/max6642.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Texas Instruments TMP103 SMBus temperature sensor driver
* Copyright (C) 2014 Heiko Schocher <[email protected]>
*
* Based on:
* Texas Instruments TMP102 SMBus temperature sensor driver
*
* Copyright (C) 2010 Steven King <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/regmap.h>
#define TMP103_TEMP_REG 0x00
#define TMP103_CONF_REG 0x01
#define TMP103_TLOW_REG 0x02
#define TMP103_THIGH_REG 0x03
#define TMP103_CONF_M0 0x01
#define TMP103_CONF_M1 0x02
#define TMP103_CONF_LC 0x04
#define TMP103_CONF_FL 0x08
#define TMP103_CONF_FH 0x10
#define TMP103_CONF_CR0 0x20
#define TMP103_CONF_CR1 0x40
#define TMP103_CONF_ID 0x80
#define TMP103_CONF_SD (TMP103_CONF_M1)
#define TMP103_CONF_SD_MASK (TMP103_CONF_M0 | TMP103_CONF_M1)
#define TMP103_CONFIG (TMP103_CONF_CR1 | TMP103_CONF_M1)
#define TMP103_CONFIG_MASK (TMP103_CONF_CR0 | TMP103_CONF_CR1 | \
TMP103_CONF_M0 | TMP103_CONF_M1)
static inline int tmp103_reg_to_mc(s8 val)
{
return val * 1000;
}
static inline u8 tmp103_mc_to_reg(int val)
{
return DIV_ROUND_CLOSEST(val, 1000);
}
static int tmp103_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *temp)
{
struct regmap *regmap = dev_get_drvdata(dev);
unsigned int regval;
int err, reg;
switch (attr) {
case hwmon_temp_input:
reg = TMP103_TEMP_REG;
break;
case hwmon_temp_min:
reg = TMP103_TLOW_REG;
break;
case hwmon_temp_max:
reg = TMP103_THIGH_REG;
break;
default:
return -EOPNOTSUPP;
}
err = regmap_read(regmap, reg, ®val);
if (err < 0)
return err;
*temp = tmp103_reg_to_mc(regval);
return 0;
}
static int tmp103_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long temp)
{
struct regmap *regmap = dev_get_drvdata(dev);
int reg;
switch (attr) {
case hwmon_temp_min:
reg = TMP103_TLOW_REG;
break;
case hwmon_temp_max:
reg = TMP103_THIGH_REG;
break;
default:
return -EOPNOTSUPP;
}
temp = clamp_val(temp, -55000, 127000);
return regmap_write(regmap, reg, tmp103_mc_to_reg(temp));
}
static umode_t tmp103_is_visible(const void *data, enum hwmon_sensor_types type,
u32 attr, int channel)
{
if (type != hwmon_temp)
return 0;
switch (attr) {
case hwmon_temp_input:
return 0444;
case hwmon_temp_min:
case hwmon_temp_max:
return 0644;
default:
return 0;
}
}
static const struct hwmon_channel_info * const tmp103_info[] = {
HWMON_CHANNEL_INFO(chip,
HWMON_C_REGISTER_TZ),
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN),
NULL
};
static const struct hwmon_ops tmp103_hwmon_ops = {
.is_visible = tmp103_is_visible,
.read = tmp103_read,
.write = tmp103_write,
};
static const struct hwmon_chip_info tmp103_chip_info = {
.ops = &tmp103_hwmon_ops,
.info = tmp103_info,
};
static bool tmp103_regmap_is_volatile(struct device *dev, unsigned int reg)
{
return reg == TMP103_TEMP_REG;
}
static const struct regmap_config tmp103_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TMP103_THIGH_REG,
.volatile_reg = tmp103_regmap_is_volatile,
};
static int tmp103_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct device *hwmon_dev;
struct regmap *regmap;
int ret;
regmap = devm_regmap_init_i2c(client, &tmp103_regmap_config);
if (IS_ERR(regmap)) {
dev_err(dev, "failed to allocate register map\n");
return PTR_ERR(regmap);
}
ret = regmap_update_bits(regmap, TMP103_CONF_REG, TMP103_CONFIG_MASK,
TMP103_CONFIG);
if (ret < 0) {
dev_err(&client->dev, "error writing config register\n");
return ret;
}
i2c_set_clientdata(client, regmap);
hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
regmap,
&tmp103_chip_info,
NULL);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static int tmp103_suspend(struct device *dev)
{
struct regmap *regmap = dev_get_drvdata(dev);
return regmap_update_bits(regmap, TMP103_CONF_REG,
TMP103_CONF_SD_MASK, 0);
}
static int tmp103_resume(struct device *dev)
{
struct regmap *regmap = dev_get_drvdata(dev);
return regmap_update_bits(regmap, TMP103_CONF_REG,
TMP103_CONF_SD_MASK, TMP103_CONF_SD);
}
static DEFINE_SIMPLE_DEV_PM_OPS(tmp103_dev_pm_ops, tmp103_suspend, tmp103_resume);
static const struct i2c_device_id tmp103_id[] = {
{ "tmp103", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tmp103_id);
static const struct of_device_id __maybe_unused tmp103_of_match[] = {
{ .compatible = "ti,tmp103" },
{ },
};
MODULE_DEVICE_TABLE(of, tmp103_of_match);
static struct i2c_driver tmp103_driver = {
.driver = {
.name = "tmp103",
.of_match_table = of_match_ptr(tmp103_of_match),
.pm = pm_sleep_ptr(&tmp103_dev_pm_ops),
},
.probe = tmp103_probe,
.id_table = tmp103_id,
};
module_i2c_driver(tmp103_driver);
MODULE_AUTHOR("Heiko Schocher <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments TMP103 temperature sensor driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/tmp103.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for Linear Technology LTC4245 I2C Multiple Supply Hot Swap Controller
*
* Copyright (C) 2008 Ira W. Snyder <[email protected]>
*
* This driver is based on the ds1621 and ina209 drivers.
*
* Datasheet:
* http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1003,C1006,C1140,P19392,D13517
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/jiffies.h>
#include <linux/platform_data/ltc4245.h>
/* Here are names of the chip's registers (a.k.a. commands) */
enum ltc4245_cmd {
LTC4245_STATUS = 0x00, /* readonly */
LTC4245_ALERT = 0x01,
LTC4245_CONTROL = 0x02,
LTC4245_ON = 0x03,
LTC4245_FAULT1 = 0x04,
LTC4245_FAULT2 = 0x05,
LTC4245_GPIO = 0x06,
LTC4245_ADCADR = 0x07,
LTC4245_12VIN = 0x10,
LTC4245_12VSENSE = 0x11,
LTC4245_12VOUT = 0x12,
LTC4245_5VIN = 0x13,
LTC4245_5VSENSE = 0x14,
LTC4245_5VOUT = 0x15,
LTC4245_3VIN = 0x16,
LTC4245_3VSENSE = 0x17,
LTC4245_3VOUT = 0x18,
LTC4245_VEEIN = 0x19,
LTC4245_VEESENSE = 0x1a,
LTC4245_VEEOUT = 0x1b,
LTC4245_GPIOADC = 0x1c,
};
struct ltc4245_data {
struct i2c_client *client;
struct mutex update_lock;
bool valid;
unsigned long last_updated; /* in jiffies */
/* Control registers */
u8 cregs[0x08];
/* Voltage registers */
u8 vregs[0x0d];
/* GPIO ADC registers */
bool use_extra_gpios;
int gpios[3];
};
/*
* Update the readings from the GPIO pins. If the driver has been configured to
* sample all GPIO's as analog voltages, a round-robin sampling method is used.
* Otherwise, only the configured GPIO pin is sampled.
*
* LOCKING: must hold data->update_lock
*/
static void ltc4245_update_gpios(struct device *dev)
{
struct ltc4245_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
u8 gpio_curr, gpio_next, gpio_reg;
int i;
/* no extra gpio support, we're basically done */
if (!data->use_extra_gpios) {
data->gpios[0] = data->vregs[LTC4245_GPIOADC - 0x10];
return;
}
/*
* If the last reading was too long ago, then we mark all old GPIO
* readings as stale by setting them to -EAGAIN
*/
if (time_after(jiffies, data->last_updated + 5 * HZ)) {
for (i = 0; i < ARRAY_SIZE(data->gpios); i++)
data->gpios[i] = -EAGAIN;
}
/*
* Get the current GPIO pin
*
* The datasheet calls these GPIO[1-3], but we'll calculate the zero
* based array index instead, and call them GPIO[0-2]. This is much
* easier to think about.
*/
gpio_curr = (data->cregs[LTC4245_GPIO] & 0xc0) >> 6;
if (gpio_curr > 0)
gpio_curr -= 1;
/* Read the GPIO voltage from the GPIOADC register */
data->gpios[gpio_curr] = data->vregs[LTC4245_GPIOADC - 0x10];
/* Find the next GPIO pin to read */
gpio_next = (gpio_curr + 1) % ARRAY_SIZE(data->gpios);
/*
* Calculate the correct setting for the GPIO register so it will
* sample the next GPIO pin
*/
gpio_reg = (data->cregs[LTC4245_GPIO] & 0x3f) | ((gpio_next + 1) << 6);
/* Update the GPIO register */
i2c_smbus_write_byte_data(client, LTC4245_GPIO, gpio_reg);
/* Update saved data */
data->cregs[LTC4245_GPIO] = gpio_reg;
}
static struct ltc4245_data *ltc4245_update_device(struct device *dev)
{
struct ltc4245_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
s32 val;
int i;
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
/* Read control registers -- 0x00 to 0x07 */
for (i = 0; i < ARRAY_SIZE(data->cregs); i++) {
val = i2c_smbus_read_byte_data(client, i);
if (unlikely(val < 0))
data->cregs[i] = 0;
else
data->cregs[i] = val;
}
/* Read voltage registers -- 0x10 to 0x1c */
for (i = 0; i < ARRAY_SIZE(data->vregs); i++) {
val = i2c_smbus_read_byte_data(client, i+0x10);
if (unlikely(val < 0))
data->vregs[i] = 0;
else
data->vregs[i] = val;
}
/* Update GPIO readings */
ltc4245_update_gpios(dev);
data->last_updated = jiffies;
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
/* Return the voltage from the given register in millivolts */
static int ltc4245_get_voltage(struct device *dev, u8 reg)
{
struct ltc4245_data *data = ltc4245_update_device(dev);
const u8 regval = data->vregs[reg - 0x10];
u32 voltage = 0;
switch (reg) {
case LTC4245_12VIN:
case LTC4245_12VOUT:
voltage = regval * 55;
break;
case LTC4245_5VIN:
case LTC4245_5VOUT:
voltage = regval * 22;
break;
case LTC4245_3VIN:
case LTC4245_3VOUT:
voltage = regval * 15;
break;
case LTC4245_VEEIN:
case LTC4245_VEEOUT:
voltage = regval * -55;
break;
case LTC4245_GPIOADC:
voltage = regval * 10;
break;
default:
/* If we get here, the developer messed up */
WARN_ON_ONCE(1);
break;
}
return voltage;
}
/* Return the current in the given sense register in milliAmperes */
static unsigned int ltc4245_get_current(struct device *dev, u8 reg)
{
struct ltc4245_data *data = ltc4245_update_device(dev);
const u8 regval = data->vregs[reg - 0x10];
unsigned int voltage;
unsigned int curr;
/*
* The strange looking conversions that follow are fixed-point
* math, since we cannot do floating point in the kernel.
*
* Step 1: convert sense register to microVolts
* Step 2: convert voltage to milliAmperes
*
* If you play around with the V=IR equation, you come up with
* the following: X uV / Y mOhm == Z mA
*
* With the resistors that are fractions of a milliOhm, we multiply
* the voltage and resistance by 10, to shift the decimal point.
* Now we can use the normal division operator again.
*/
switch (reg) {
case LTC4245_12VSENSE:
voltage = regval * 250; /* voltage in uV */
curr = voltage / 50; /* sense resistor 50 mOhm */
break;
case LTC4245_5VSENSE:
voltage = regval * 125; /* voltage in uV */
curr = (voltage * 10) / 35; /* sense resistor 3.5 mOhm */
break;
case LTC4245_3VSENSE:
voltage = regval * 125; /* voltage in uV */
curr = (voltage * 10) / 25; /* sense resistor 2.5 mOhm */
break;
case LTC4245_VEESENSE:
voltage = regval * 250; /* voltage in uV */
curr = voltage / 100; /* sense resistor 100 mOhm */
break;
default:
/* If we get here, the developer messed up */
WARN_ON_ONCE(1);
curr = 0;
break;
}
return curr;
}
/* Map from voltage channel index to voltage register */
static const s8 ltc4245_in_regs[] = {
LTC4245_12VIN, LTC4245_5VIN, LTC4245_3VIN, LTC4245_VEEIN,
LTC4245_12VOUT, LTC4245_5VOUT, LTC4245_3VOUT, LTC4245_VEEOUT,
};
/* Map from current channel index to current register */
static const s8 ltc4245_curr_regs[] = {
LTC4245_12VSENSE, LTC4245_5VSENSE, LTC4245_3VSENSE, LTC4245_VEESENSE,
};
static int ltc4245_read_curr(struct device *dev, u32 attr, int channel,
long *val)
{
struct ltc4245_data *data = ltc4245_update_device(dev);
switch (attr) {
case hwmon_curr_input:
*val = ltc4245_get_current(dev, ltc4245_curr_regs[channel]);
return 0;
case hwmon_curr_max_alarm:
*val = !!(data->cregs[LTC4245_FAULT1] & BIT(channel + 4));
return 0;
default:
return -EOPNOTSUPP;
}
}
static int ltc4245_read_in(struct device *dev, u32 attr, int channel, long *val)
{
struct ltc4245_data *data = ltc4245_update_device(dev);
switch (attr) {
case hwmon_in_input:
if (channel < 8) {
*val = ltc4245_get_voltage(dev,
ltc4245_in_regs[channel]);
} else {
int regval = data->gpios[channel - 8];
if (regval < 0)
return regval;
*val = regval * 10;
}
return 0;
case hwmon_in_min_alarm:
if (channel < 4)
*val = !!(data->cregs[LTC4245_FAULT1] & BIT(channel));
else
*val = !!(data->cregs[LTC4245_FAULT2] &
BIT(channel - 4));
return 0;
default:
return -EOPNOTSUPP;
}
}
static int ltc4245_read_power(struct device *dev, u32 attr, int channel,
long *val)
{
unsigned long curr;
long voltage;
switch (attr) {
case hwmon_power_input:
(void)ltc4245_update_device(dev);
curr = ltc4245_get_current(dev, ltc4245_curr_regs[channel]);
voltage = ltc4245_get_voltage(dev, ltc4245_in_regs[channel]);
*val = abs(curr * voltage);
return 0;
default:
return -EOPNOTSUPP;
}
}
static int ltc4245_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
switch (type) {
case hwmon_curr:
return ltc4245_read_curr(dev, attr, channel, val);
case hwmon_power:
return ltc4245_read_power(dev, attr, channel, val);
case hwmon_in:
return ltc4245_read_in(dev, attr, channel - 1, val);
default:
return -EOPNOTSUPP;
}
}
static umode_t ltc4245_is_visible(const void *_data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
const struct ltc4245_data *data = _data;
switch (type) {
case hwmon_in:
if (channel == 0)
return 0;
switch (attr) {
case hwmon_in_input:
if (channel > 9 && !data->use_extra_gpios)
return 0;
return 0444;
case hwmon_in_min_alarm:
if (channel > 8)
return 0;
return 0444;
default:
return 0;
}
case hwmon_curr:
switch (attr) {
case hwmon_curr_input:
case hwmon_curr_max_alarm:
return 0444;
default:
return 0;
}
case hwmon_power:
switch (attr) {
case hwmon_power_input:
return 0444;
default:
return 0;
}
default:
return 0;
}
}
static const struct hwmon_channel_info * const ltc4245_info[] = {
HWMON_CHANNEL_INFO(in,
HWMON_I_INPUT,
HWMON_I_INPUT | HWMON_I_MIN_ALARM,
HWMON_I_INPUT | HWMON_I_MIN_ALARM,
HWMON_I_INPUT | HWMON_I_MIN_ALARM,
HWMON_I_INPUT | HWMON_I_MIN_ALARM,
HWMON_I_INPUT | HWMON_I_MIN_ALARM,
HWMON_I_INPUT | HWMON_I_MIN_ALARM,
HWMON_I_INPUT | HWMON_I_MIN_ALARM,
HWMON_I_INPUT | HWMON_I_MIN_ALARM,
HWMON_I_INPUT,
HWMON_I_INPUT,
HWMON_I_INPUT),
HWMON_CHANNEL_INFO(curr,
HWMON_C_INPUT | HWMON_C_MAX_ALARM,
HWMON_C_INPUT | HWMON_C_MAX_ALARM,
HWMON_C_INPUT | HWMON_C_MAX_ALARM,
HWMON_C_INPUT | HWMON_C_MAX_ALARM),
HWMON_CHANNEL_INFO(power,
HWMON_P_INPUT,
HWMON_P_INPUT,
HWMON_P_INPUT,
HWMON_P_INPUT),
NULL
};
static const struct hwmon_ops ltc4245_hwmon_ops = {
.is_visible = ltc4245_is_visible,
.read = ltc4245_read,
};
static const struct hwmon_chip_info ltc4245_chip_info = {
.ops = <c4245_hwmon_ops,
.info = ltc4245_info,
};
static bool ltc4245_use_extra_gpios(struct i2c_client *client)
{
struct ltc4245_platform_data *pdata = dev_get_platdata(&client->dev);
struct device_node *np = client->dev.of_node;
/* prefer platform data */
if (pdata)
return pdata->use_extra_gpios;
/* fallback on OF */
if (of_property_read_bool(np, "ltc4245,use-extra-gpios"))
return true;
return false;
}
static int ltc4245_probe(struct i2c_client *client)
{
struct i2c_adapter *adapter = client->adapter;
struct ltc4245_data *data;
struct device *hwmon_dev;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
mutex_init(&data->update_lock);
data->use_extra_gpios = ltc4245_use_extra_gpios(client);
/* Initialize the LTC4245 chip */
i2c_smbus_write_byte_data(client, LTC4245_FAULT1, 0x00);
i2c_smbus_write_byte_data(client, LTC4245_FAULT2, 0x00);
hwmon_dev = devm_hwmon_device_register_with_info(&client->dev,
client->name, data,
<c4245_chip_info,
NULL);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id ltc4245_id[] = {
{ "ltc4245", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ltc4245_id);
/* This is the driver that will be inserted */
static struct i2c_driver ltc4245_driver = {
.driver = {
.name = "ltc4245",
},
.probe = ltc4245_probe,
.id_table = ltc4245_id,
};
module_i2c_driver(ltc4245_driver);
MODULE_AUTHOR("Ira W. Snyder <[email protected]>");
MODULE_DESCRIPTION("LTC4245 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/ltc4245.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* adcxx.c
*
* The adcxx4s is an AD converter family from National Semiconductor (NS).
*
* Copyright (c) 2008 Marc Pignat <[email protected]>
*
* The adcxx4s communicates with a host processor via an SPI/Microwire Bus
* interface. This driver supports the whole family of devices with name
* ADC<bb><c>S<sss>, where
* * bb is the resolution in number of bits (8, 10, 12)
* * c is the number of channels (1, 2, 4, 8)
* * sss is the maximum conversion speed (021 for 200 kSPS, 051 for 500 kSPS
* and 101 for 1 MSPS)
*
* Complete datasheets are available at National's website here:
* http://www.national.com/ds/DC/ADC<bb><c>S<sss>.pdf
*
* Handling of 8, 10 and 12 bits converters are the same, the
* unavailable bits are 0 :)
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/sysfs.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/mutex.h>
#include <linux/mod_devicetable.h>
#include <linux/spi/spi.h>
#define DRVNAME "adcxx"
struct adcxx {
struct device *hwmon_dev;
struct mutex lock;
u32 channels;
u32 reference; /* in millivolts */
};
/* sysfs hook function */
static ssize_t adcxx_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct spi_device *spi = to_spi_device(dev);
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct adcxx *adc = spi_get_drvdata(spi);
u8 tx_buf[2];
u8 rx_buf[2];
int status;
u32 value;
if (mutex_lock_interruptible(&adc->lock))
return -ERESTARTSYS;
if (adc->channels == 1) {
status = spi_read(spi, rx_buf, sizeof(rx_buf));
} else {
tx_buf[0] = attr->index << 3; /* other bits are don't care */
status = spi_write_then_read(spi, tx_buf, sizeof(tx_buf),
rx_buf, sizeof(rx_buf));
}
if (status < 0) {
dev_warn(dev, "SPI synch. transfer failed with status %d\n",
status);
goto out;
}
value = (rx_buf[0] << 8) + rx_buf[1];
dev_dbg(dev, "raw value = 0x%x\n", value);
value = value * adc->reference >> 12;
status = sprintf(buf, "%d\n", value);
out:
mutex_unlock(&adc->lock);
return status;
}
static ssize_t adcxx_min_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
/* The minimum reference is 0 for this chip family */
return sprintf(buf, "0\n");
}
static ssize_t adcxx_max_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct spi_device *spi = to_spi_device(dev);
struct adcxx *adc = spi_get_drvdata(spi);
u32 reference;
if (mutex_lock_interruptible(&adc->lock))
return -ERESTARTSYS;
reference = adc->reference;
mutex_unlock(&adc->lock);
return sprintf(buf, "%d\n", reference);
}
static ssize_t adcxx_max_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct spi_device *spi = to_spi_device(dev);
struct adcxx *adc = spi_get_drvdata(spi);
unsigned long value;
if (kstrtoul(buf, 10, &value))
return -EINVAL;
if (mutex_lock_interruptible(&adc->lock))
return -ERESTARTSYS;
adc->reference = value;
mutex_unlock(&adc->lock);
return count;
}
static ssize_t adcxx_name_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
return sprintf(buf, "%s\n", to_spi_device(dev)->modalias);
}
static struct sensor_device_attribute ad_input[] = {
SENSOR_ATTR_RO(name, adcxx_name, 0),
SENSOR_ATTR_RO(in_min, adcxx_min, 0),
SENSOR_ATTR_RW(in_max, adcxx_max, 0),
SENSOR_ATTR_RO(in0_input, adcxx, 0),
SENSOR_ATTR_RO(in1_input, adcxx, 1),
SENSOR_ATTR_RO(in2_input, adcxx, 2),
SENSOR_ATTR_RO(in3_input, adcxx, 3),
SENSOR_ATTR_RO(in4_input, adcxx, 4),
SENSOR_ATTR_RO(in5_input, adcxx, 5),
SENSOR_ATTR_RO(in6_input, adcxx, 6),
SENSOR_ATTR_RO(in7_input, adcxx, 7),
};
/*----------------------------------------------------------------------*/
static int adcxx_probe(struct spi_device *spi)
{
int channels = spi_get_device_id(spi)->driver_data;
struct adcxx *adc;
int status;
int i;
adc = devm_kzalloc(&spi->dev, sizeof(*adc), GFP_KERNEL);
if (!adc)
return -ENOMEM;
/* set a default value for the reference */
adc->reference = 3300;
adc->channels = channels;
mutex_init(&adc->lock);
mutex_lock(&adc->lock);
spi_set_drvdata(spi, adc);
for (i = 0; i < 3 + adc->channels; i++) {
status = device_create_file(&spi->dev, &ad_input[i].dev_attr);
if (status) {
dev_err(&spi->dev, "device_create_file failed.\n");
goto out_err;
}
}
adc->hwmon_dev = hwmon_device_register(&spi->dev);
if (IS_ERR(adc->hwmon_dev)) {
dev_err(&spi->dev, "hwmon_device_register failed.\n");
status = PTR_ERR(adc->hwmon_dev);
goto out_err;
}
mutex_unlock(&adc->lock);
return 0;
out_err:
for (i--; i >= 0; i--)
device_remove_file(&spi->dev, &ad_input[i].dev_attr);
mutex_unlock(&adc->lock);
return status;
}
static void adcxx_remove(struct spi_device *spi)
{
struct adcxx *adc = spi_get_drvdata(spi);
int i;
mutex_lock(&adc->lock);
hwmon_device_unregister(adc->hwmon_dev);
for (i = 0; i < 3 + adc->channels; i++)
device_remove_file(&spi->dev, &ad_input[i].dev_attr);
mutex_unlock(&adc->lock);
}
static const struct spi_device_id adcxx_ids[] = {
{ "adcxx1s", 1 },
{ "adcxx2s", 2 },
{ "adcxx4s", 4 },
{ "adcxx8s", 8 },
{ },
};
MODULE_DEVICE_TABLE(spi, adcxx_ids);
static struct spi_driver adcxx_driver = {
.driver = {
.name = "adcxx",
},
.id_table = adcxx_ids,
.probe = adcxx_probe,
.remove = adcxx_remove,
};
module_spi_driver(adcxx_driver);
MODULE_AUTHOR("Marc Pignat");
MODULE_DESCRIPTION("National Semiconductor adcxx8sxxx Linux driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/adcxx.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* abituguru.c Copyright (c) 2005-2006 Hans de Goede <[email protected]>
*/
/*
* This driver supports the sensor part of the first and second revision of
* the custom Abit uGuru chip found on Abit uGuru motherboards. Note: because
* of lack of specs the CPU/RAM voltage & frequency control is not supported!
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/dmi.h>
#include <linux/io.h>
/* Banks */
#define ABIT_UGURU_ALARM_BANK 0x20 /* 1x 3 bytes */
#define ABIT_UGURU_SENSOR_BANK1 0x21 /* 16x volt and temp */
#define ABIT_UGURU_FAN_PWM 0x24 /* 3x 5 bytes */
#define ABIT_UGURU_SENSOR_BANK2 0x26 /* fans */
/* max nr of sensors in bank1, a bank1 sensor can be in, temp or nc */
#define ABIT_UGURU_MAX_BANK1_SENSORS 16
/*
* Warning if you increase one of the 2 MAX defines below to 10 or higher you
* should adjust the belonging _NAMES_LENGTH macro for the 2 digit number!
*/
/* max nr of sensors in bank2, currently mb's with max 6 fans are known */
#define ABIT_UGURU_MAX_BANK2_SENSORS 6
/* max nr of pwm outputs, currently mb's with max 5 pwm outputs are known */
#define ABIT_UGURU_MAX_PWMS 5
/* uGuru sensor bank 1 flags */ /* Alarm if: */
#define ABIT_UGURU_TEMP_HIGH_ALARM_ENABLE 0x01 /* temp over warn */
#define ABIT_UGURU_VOLT_HIGH_ALARM_ENABLE 0x02 /* volt over max */
#define ABIT_UGURU_VOLT_LOW_ALARM_ENABLE 0x04 /* volt under min */
#define ABIT_UGURU_TEMP_HIGH_ALARM_FLAG 0x10 /* temp is over warn */
#define ABIT_UGURU_VOLT_HIGH_ALARM_FLAG 0x20 /* volt is over max */
#define ABIT_UGURU_VOLT_LOW_ALARM_FLAG 0x40 /* volt is under min */
/* uGuru sensor bank 2 flags */ /* Alarm if: */
#define ABIT_UGURU_FAN_LOW_ALARM_ENABLE 0x01 /* fan under min */
/* uGuru sensor bank common flags */
#define ABIT_UGURU_BEEP_ENABLE 0x08 /* beep if alarm */
#define ABIT_UGURU_SHUTDOWN_ENABLE 0x80 /* shutdown if alarm */
/* uGuru fan PWM (speed control) flags */
#define ABIT_UGURU_FAN_PWM_ENABLE 0x80 /* enable speed control */
/* Values used for conversion */
#define ABIT_UGURU_FAN_MAX 15300 /* RPM */
/* Bank1 sensor types */
#define ABIT_UGURU_IN_SENSOR 0
#define ABIT_UGURU_TEMP_SENSOR 1
#define ABIT_UGURU_NC 2
/*
* In many cases we need to wait for the uGuru to reach a certain status, most
* of the time it will reach this status within 30 - 90 ISA reads, and thus we
* can best busy wait. This define gives the total amount of reads to try.
*/
#define ABIT_UGURU_WAIT_TIMEOUT 125
/*
* However sometimes older versions of the uGuru seem to be distracted and they
* do not respond for a long time. To handle this we sleep before each of the
* last ABIT_UGURU_WAIT_TIMEOUT_SLEEP tries.
*/
#define ABIT_UGURU_WAIT_TIMEOUT_SLEEP 5
/*
* Normally all expected status in abituguru_ready, are reported after the
* first read, but sometimes not and we need to poll.
*/
#define ABIT_UGURU_READY_TIMEOUT 5
/* Maximum 3 retries on timedout reads/writes, delay 200 ms before retrying */
#define ABIT_UGURU_MAX_RETRIES 3
#define ABIT_UGURU_RETRY_DELAY (HZ/5)
/* Maximum 2 timeouts in abituguru_update_device, iow 3 in a row is an error */
#define ABIT_UGURU_MAX_TIMEOUTS 2
/* utility macros */
#define ABIT_UGURU_NAME "abituguru"
#define ABIT_UGURU_DEBUG(level, format, arg...) \
do { \
if (level <= verbose) \
pr_debug(format , ## arg); \
} while (0)
/* Macros to help calculate the sysfs_names array length */
/*
* sum of strlen of: in??_input\0, in??_{min,max}\0, in??_{min,max}_alarm\0,
* in??_{min,max}_alarm_enable\0, in??_beep\0, in??_shutdown\0
*/
#define ABITUGURU_IN_NAMES_LENGTH (11 + 2 * 9 + 2 * 15 + 2 * 22 + 10 + 14)
/*
* sum of strlen of: temp??_input\0, temp??_max\0, temp??_crit\0,
* temp??_alarm\0, temp??_alarm_enable\0, temp??_beep\0, temp??_shutdown\0
*/
#define ABITUGURU_TEMP_NAMES_LENGTH (13 + 11 + 12 + 13 + 20 + 12 + 16)
/*
* sum of strlen of: fan?_input\0, fan?_min\0, fan?_alarm\0,
* fan?_alarm_enable\0, fan?_beep\0, fan?_shutdown\0
*/
#define ABITUGURU_FAN_NAMES_LENGTH (11 + 9 + 11 + 18 + 10 + 14)
/*
* sum of strlen of: pwm?_enable\0, pwm?_auto_channels_temp\0,
* pwm?_auto_point{1,2}_pwm\0, pwm?_auto_point{1,2}_temp\0
*/
#define ABITUGURU_PWM_NAMES_LENGTH (12 + 24 + 2 * 21 + 2 * 22)
/* IN_NAMES_LENGTH > TEMP_NAMES_LENGTH so assume all bank1 sensors are in */
#define ABITUGURU_SYSFS_NAMES_LENGTH ( \
ABIT_UGURU_MAX_BANK1_SENSORS * ABITUGURU_IN_NAMES_LENGTH + \
ABIT_UGURU_MAX_BANK2_SENSORS * ABITUGURU_FAN_NAMES_LENGTH + \
ABIT_UGURU_MAX_PWMS * ABITUGURU_PWM_NAMES_LENGTH)
/*
* All the macros below are named identical to the oguru and oguru2 programs
* reverse engineered by Olle Sandberg, hence the names might not be 100%
* logical. I could come up with better names, but I prefer keeping the names
* identical so that this driver can be compared with his work more easily.
*/
/* Two i/o-ports are used by uGuru */
#define ABIT_UGURU_BASE 0x00E0
/* Used to tell uGuru what to read and to read the actual data */
#define ABIT_UGURU_CMD 0x00
/* Mostly used to check if uGuru is busy */
#define ABIT_UGURU_DATA 0x04
#define ABIT_UGURU_REGION_LENGTH 5
/* uGuru status' */
#define ABIT_UGURU_STATUS_WRITE 0x00 /* Ready to be written */
#define ABIT_UGURU_STATUS_READ 0x01 /* Ready to be read */
#define ABIT_UGURU_STATUS_INPUT 0x08 /* More input */
#define ABIT_UGURU_STATUS_READY 0x09 /* Ready to be written */
/* Constants */
/* in (Volt) sensors go up to 3494 mV, temp to 255000 millidegrees Celsius */
static const int abituguru_bank1_max_value[2] = { 3494, 255000 };
/*
* Min / Max allowed values for sensor2 (fan) alarm threshold, these values
* correspond to 300-3000 RPM
*/
static const u8 abituguru_bank2_min_threshold = 5;
static const u8 abituguru_bank2_max_threshold = 50;
/*
* Register 0 is a bitfield, 1 and 2 are pwm settings (255 = 100%), 3 and 4
* are temperature trip points.
*/
static const int abituguru_pwm_settings_multiplier[5] = { 0, 1, 1, 1000, 1000 };
/*
* Min / Max allowed values for pwm_settings. Note: pwm1 (CPU fan) is a
* special case the minimum allowed pwm% setting for this is 30% (77) on
* some MB's this special case is handled in the code!
*/
static const u8 abituguru_pwm_min[5] = { 0, 170, 170, 25, 25 };
static const u8 abituguru_pwm_max[5] = { 0, 255, 255, 75, 75 };
/* Insmod parameters */
static bool force;
module_param(force, bool, 0);
MODULE_PARM_DESC(force, "Set to one to force detection.");
static int bank1_types[ABIT_UGURU_MAX_BANK1_SENSORS] = { -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 };
module_param_array(bank1_types, int, NULL, 0);
MODULE_PARM_DESC(bank1_types, "Bank1 sensortype autodetection override:\n"
" -1 autodetect\n"
" 0 volt sensor\n"
" 1 temp sensor\n"
" 2 not connected");
static int fan_sensors;
module_param(fan_sensors, int, 0);
MODULE_PARM_DESC(fan_sensors, "Number of fan sensors on the uGuru "
"(0 = autodetect)");
static int pwms;
module_param(pwms, int, 0);
MODULE_PARM_DESC(pwms, "Number of PWMs on the uGuru "
"(0 = autodetect)");
/* Default verbose is 2, since this driver is still in the testing phase */
static int verbose = 2;
module_param(verbose, int, 0644);
MODULE_PARM_DESC(verbose, "How verbose should the driver be? (0-3):\n"
" 0 normal output\n"
" 1 + verbose error reporting\n"
" 2 + sensors type probing info\n"
" 3 + retryable error reporting");
/*
* For the Abit uGuru, we need to keep some data in memory.
* The structure is dynamically allocated, at the same time when a new
* abituguru device is allocated.
*/
struct abituguru_data {
struct device *hwmon_dev; /* hwmon registered device */
struct mutex update_lock; /* protect access to data and uGuru */
unsigned long last_updated; /* In jiffies */
unsigned short addr; /* uguru base address */
char uguru_ready; /* is the uguru in ready state? */
unsigned char update_timeouts; /*
* number of update timeouts since last
* successful update
*/
/*
* The sysfs attr and their names are generated automatically, for bank1
* we cannot use a predefined array because we don't know beforehand
* of a sensor is a volt or a temp sensor, for bank2 and the pwms its
* easier todo things the same way. For in sensors we have 9 (temp 7)
* sysfs entries per sensor, for bank2 and pwms 6.
*/
struct sensor_device_attribute_2 sysfs_attr[
ABIT_UGURU_MAX_BANK1_SENSORS * 9 +
ABIT_UGURU_MAX_BANK2_SENSORS * 6 + ABIT_UGURU_MAX_PWMS * 6];
/* Buffer to store the dynamically generated sysfs names */
char sysfs_names[ABITUGURU_SYSFS_NAMES_LENGTH];
/* Bank 1 data */
/* number of and addresses of [0] in, [1] temp sensors */
u8 bank1_sensors[2];
u8 bank1_address[2][ABIT_UGURU_MAX_BANK1_SENSORS];
u8 bank1_value[ABIT_UGURU_MAX_BANK1_SENSORS];
/*
* This array holds 3 entries per sensor for the bank 1 sensor settings
* (flags, min, max for voltage / flags, warn, shutdown for temp).
*/
u8 bank1_settings[ABIT_UGURU_MAX_BANK1_SENSORS][3];
/*
* Maximum value for each sensor used for scaling in mV/millidegrees
* Celsius.
*/
int bank1_max_value[ABIT_UGURU_MAX_BANK1_SENSORS];
/* Bank 2 data, ABIT_UGURU_MAX_BANK2_SENSORS entries for bank2 */
u8 bank2_sensors; /* actual number of bank2 sensors found */
u8 bank2_value[ABIT_UGURU_MAX_BANK2_SENSORS];
u8 bank2_settings[ABIT_UGURU_MAX_BANK2_SENSORS][2]; /* flags, min */
/* Alarms 2 bytes for bank1, 1 byte for bank2 */
u8 alarms[3];
/* Fan PWM (speed control) 5 bytes per PWM */
u8 pwms; /* actual number of pwms found */
u8 pwm_settings[ABIT_UGURU_MAX_PWMS][5];
};
static const char *never_happen = "This should never happen.";
static const char *report_this =
"Please report this to the abituguru maintainer (see MAINTAINERS)";
/* wait till the uguru is in the specified state */
static int abituguru_wait(struct abituguru_data *data, u8 state)
{
int timeout = ABIT_UGURU_WAIT_TIMEOUT;
while (inb_p(data->addr + ABIT_UGURU_DATA) != state) {
timeout--;
if (timeout == 0)
return -EBUSY;
/*
* sleep a bit before our last few tries, see the comment on
* this where ABIT_UGURU_WAIT_TIMEOUT_SLEEP is defined.
*/
if (timeout <= ABIT_UGURU_WAIT_TIMEOUT_SLEEP)
msleep(0);
}
return 0;
}
/* Put the uguru in ready for input state */
static int abituguru_ready(struct abituguru_data *data)
{
int timeout = ABIT_UGURU_READY_TIMEOUT;
if (data->uguru_ready)
return 0;
/* Reset? / Prepare for next read/write cycle */
outb(0x00, data->addr + ABIT_UGURU_DATA);
/* Wait till the uguru is ready */
if (abituguru_wait(data, ABIT_UGURU_STATUS_READY)) {
ABIT_UGURU_DEBUG(1,
"timeout exceeded waiting for ready state\n");
return -EIO;
}
/* Cmd port MUST be read now and should contain 0xAC */
while (inb_p(data->addr + ABIT_UGURU_CMD) != 0xAC) {
timeout--;
if (timeout == 0) {
ABIT_UGURU_DEBUG(1,
"CMD reg does not hold 0xAC after ready command\n");
return -EIO;
}
msleep(0);
}
/*
* After this the ABIT_UGURU_DATA port should contain
* ABIT_UGURU_STATUS_INPUT
*/
timeout = ABIT_UGURU_READY_TIMEOUT;
while (inb_p(data->addr + ABIT_UGURU_DATA) != ABIT_UGURU_STATUS_INPUT) {
timeout--;
if (timeout == 0) {
ABIT_UGURU_DEBUG(1,
"state != more input after ready command\n");
return -EIO;
}
msleep(0);
}
data->uguru_ready = 1;
return 0;
}
/*
* Send the bank and then sensor address to the uGuru for the next read/write
* cycle. This function gets called as the first part of a read/write by
* abituguru_read and abituguru_write. This function should never be
* called by any other function.
*/
static int abituguru_send_address(struct abituguru_data *data,
u8 bank_addr, u8 sensor_addr, int retries)
{
/*
* assume the caller does error handling itself if it has not requested
* any retries, and thus be quiet.
*/
int report_errors = retries;
for (;;) {
/*
* Make sure the uguru is ready and then send the bank address,
* after this the uguru is no longer "ready".
*/
if (abituguru_ready(data) != 0)
return -EIO;
outb(bank_addr, data->addr + ABIT_UGURU_DATA);
data->uguru_ready = 0;
/*
* Wait till the uguru is ABIT_UGURU_STATUS_INPUT state again
* and send the sensor addr
*/
if (abituguru_wait(data, ABIT_UGURU_STATUS_INPUT)) {
if (retries) {
ABIT_UGURU_DEBUG(3, "timeout exceeded "
"waiting for more input state, %d "
"tries remaining\n", retries);
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(ABIT_UGURU_RETRY_DELAY);
retries--;
continue;
}
if (report_errors)
ABIT_UGURU_DEBUG(1, "timeout exceeded "
"waiting for more input state "
"(bank: %d)\n", (int)bank_addr);
return -EBUSY;
}
outb(sensor_addr, data->addr + ABIT_UGURU_CMD);
return 0;
}
}
/*
* Read count bytes from sensor sensor_addr in bank bank_addr and store the
* result in buf, retry the send address part of the read retries times.
*/
static int abituguru_read(struct abituguru_data *data,
u8 bank_addr, u8 sensor_addr, u8 *buf, int count, int retries)
{
int i;
/* Send the address */
i = abituguru_send_address(data, bank_addr, sensor_addr, retries);
if (i)
return i;
/* And read the data */
for (i = 0; i < count; i++) {
if (abituguru_wait(data, ABIT_UGURU_STATUS_READ)) {
ABIT_UGURU_DEBUG(retries ? 1 : 3,
"timeout exceeded waiting for "
"read state (bank: %d, sensor: %d)\n",
(int)bank_addr, (int)sensor_addr);
break;
}
buf[i] = inb(data->addr + ABIT_UGURU_CMD);
}
/* Last put the chip back in ready state */
abituguru_ready(data);
return i;
}
/*
* Write count bytes from buf to sensor sensor_addr in bank bank_addr, the send
* address part of the write is always retried ABIT_UGURU_MAX_RETRIES times.
*/
static int abituguru_write(struct abituguru_data *data,
u8 bank_addr, u8 sensor_addr, u8 *buf, int count)
{
/*
* We use the ready timeout as we have to wait for 0xAC just like the
* ready function
*/
int i, timeout = ABIT_UGURU_READY_TIMEOUT;
/* Send the address */
i = abituguru_send_address(data, bank_addr, sensor_addr,
ABIT_UGURU_MAX_RETRIES);
if (i)
return i;
/* And write the data */
for (i = 0; i < count; i++) {
if (abituguru_wait(data, ABIT_UGURU_STATUS_WRITE)) {
ABIT_UGURU_DEBUG(1, "timeout exceeded waiting for "
"write state (bank: %d, sensor: %d)\n",
(int)bank_addr, (int)sensor_addr);
break;
}
outb(buf[i], data->addr + ABIT_UGURU_CMD);
}
/*
* Now we need to wait till the chip is ready to be read again,
* so that we can read 0xAC as confirmation that our write has
* succeeded.
*/
if (abituguru_wait(data, ABIT_UGURU_STATUS_READ)) {
ABIT_UGURU_DEBUG(1, "timeout exceeded waiting for read state "
"after write (bank: %d, sensor: %d)\n", (int)bank_addr,
(int)sensor_addr);
return -EIO;
}
/* Cmd port MUST be read now and should contain 0xAC */
while (inb_p(data->addr + ABIT_UGURU_CMD) != 0xAC) {
timeout--;
if (timeout == 0) {
ABIT_UGURU_DEBUG(1, "CMD reg does not hold 0xAC after "
"write (bank: %d, sensor: %d)\n",
(int)bank_addr, (int)sensor_addr);
return -EIO;
}
msleep(0);
}
/* Last put the chip back in ready state */
abituguru_ready(data);
return i;
}
/*
* Detect sensor type. Temp and Volt sensors are enabled with
* different masks and will ignore enable masks not meant for them.
* This enables us to test what kind of sensor we're dealing with.
* By setting the alarm thresholds so that we will always get an
* alarm for sensor type X and then enabling the sensor as sensor type
* X, if we then get an alarm it is a sensor of type X.
*/
static int
abituguru_detect_bank1_sensor_type(struct abituguru_data *data,
u8 sensor_addr)
{
u8 val, test_flag, buf[3];
int i, ret = -ENODEV; /* error is the most common used retval :| */
/* If overriden by the user return the user selected type */
if (bank1_types[sensor_addr] >= ABIT_UGURU_IN_SENSOR &&
bank1_types[sensor_addr] <= ABIT_UGURU_NC) {
ABIT_UGURU_DEBUG(2, "assuming sensor type %d for bank1 sensor "
"%d because of \"bank1_types\" module param\n",
bank1_types[sensor_addr], (int)sensor_addr);
return bank1_types[sensor_addr];
}
/* First read the sensor and the current settings */
if (abituguru_read(data, ABIT_UGURU_SENSOR_BANK1, sensor_addr, &val,
1, ABIT_UGURU_MAX_RETRIES) != 1)
return -ENODEV;
/* Test val is sane / usable for sensor type detection. */
if ((val < 10u) || (val > 250u)) {
pr_warn("bank1-sensor: %d reading (%d) too close to limits, "
"unable to determine sensor type, skipping sensor\n",
(int)sensor_addr, (int)val);
/*
* assume no sensor is there for sensors for which we can't
* determine the sensor type because their reading is too close
* to their limits, this usually means no sensor is there.
*/
return ABIT_UGURU_NC;
}
ABIT_UGURU_DEBUG(2, "testing bank1 sensor %d\n", (int)sensor_addr);
/*
* Volt sensor test, enable volt low alarm, set min value ridiculously
* high, or vica versa if the reading is very high. If its a volt
* sensor this should always give us an alarm.
*/
if (val <= 240u) {
buf[0] = ABIT_UGURU_VOLT_LOW_ALARM_ENABLE;
buf[1] = 245;
buf[2] = 250;
test_flag = ABIT_UGURU_VOLT_LOW_ALARM_FLAG;
} else {
buf[0] = ABIT_UGURU_VOLT_HIGH_ALARM_ENABLE;
buf[1] = 5;
buf[2] = 10;
test_flag = ABIT_UGURU_VOLT_HIGH_ALARM_FLAG;
}
if (abituguru_write(data, ABIT_UGURU_SENSOR_BANK1 + 2, sensor_addr,
buf, 3) != 3)
goto abituguru_detect_bank1_sensor_type_exit;
/*
* Now we need 20 ms to give the uguru time to read the sensors
* and raise a voltage alarm
*/
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ/50);
/* Check for alarm and check the alarm is a volt low alarm. */
if (abituguru_read(data, ABIT_UGURU_ALARM_BANK, 0, buf, 3,
ABIT_UGURU_MAX_RETRIES) != 3)
goto abituguru_detect_bank1_sensor_type_exit;
if (buf[sensor_addr/8] & (0x01 << (sensor_addr % 8))) {
if (abituguru_read(data, ABIT_UGURU_SENSOR_BANK1 + 1,
sensor_addr, buf, 3,
ABIT_UGURU_MAX_RETRIES) != 3)
goto abituguru_detect_bank1_sensor_type_exit;
if (buf[0] & test_flag) {
ABIT_UGURU_DEBUG(2, " found volt sensor\n");
ret = ABIT_UGURU_IN_SENSOR;
goto abituguru_detect_bank1_sensor_type_exit;
} else
ABIT_UGURU_DEBUG(2, " alarm raised during volt "
"sensor test, but volt range flag not set\n");
} else
ABIT_UGURU_DEBUG(2, " alarm not raised during volt sensor "
"test\n");
/*
* Temp sensor test, enable sensor as a temp sensor, set beep value
* ridiculously low (but not too low, otherwise uguru ignores it).
* If its a temp sensor this should always give us an alarm.
*/
buf[0] = ABIT_UGURU_TEMP_HIGH_ALARM_ENABLE;
buf[1] = 5;
buf[2] = 10;
if (abituguru_write(data, ABIT_UGURU_SENSOR_BANK1 + 2, sensor_addr,
buf, 3) != 3)
goto abituguru_detect_bank1_sensor_type_exit;
/*
* Now we need 50 ms to give the uguru time to read the sensors
* and raise a temp alarm
*/
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ/20);
/* Check for alarm and check the alarm is a temp high alarm. */
if (abituguru_read(data, ABIT_UGURU_ALARM_BANK, 0, buf, 3,
ABIT_UGURU_MAX_RETRIES) != 3)
goto abituguru_detect_bank1_sensor_type_exit;
if (buf[sensor_addr/8] & (0x01 << (sensor_addr % 8))) {
if (abituguru_read(data, ABIT_UGURU_SENSOR_BANK1 + 1,
sensor_addr, buf, 3,
ABIT_UGURU_MAX_RETRIES) != 3)
goto abituguru_detect_bank1_sensor_type_exit;
if (buf[0] & ABIT_UGURU_TEMP_HIGH_ALARM_FLAG) {
ABIT_UGURU_DEBUG(2, " found temp sensor\n");
ret = ABIT_UGURU_TEMP_SENSOR;
goto abituguru_detect_bank1_sensor_type_exit;
} else
ABIT_UGURU_DEBUG(2, " alarm raised during temp "
"sensor test, but temp high flag not set\n");
} else
ABIT_UGURU_DEBUG(2, " alarm not raised during temp sensor "
"test\n");
ret = ABIT_UGURU_NC;
abituguru_detect_bank1_sensor_type_exit:
/*
* Restore original settings, failing here is really BAD, it has been
* reported that some BIOS-es hang when entering the uGuru menu with
* invalid settings present in the uGuru, so we try this 3 times.
*/
for (i = 0; i < 3; i++)
if (abituguru_write(data, ABIT_UGURU_SENSOR_BANK1 + 2,
sensor_addr, data->bank1_settings[sensor_addr],
3) == 3)
break;
if (i == 3) {
pr_err("Fatal error could not restore original settings. %s %s\n",
never_happen, report_this);
return -ENODEV;
}
return ret;
}
/*
* These functions try to find out how many sensors there are in bank2 and how
* many pwms there are. The purpose of this is to make sure that we don't give
* the user the possibility to change settings for non-existent sensors / pwm.
* The uGuru will happily read / write whatever memory happens to be after the
* memory storing the PWM settings when reading/writing to a PWM which is not
* there. Notice even if we detect a PWM which doesn't exist we normally won't
* write to it, unless the user tries to change the settings.
*
* Although the uGuru allows reading (settings) from non existing bank2
* sensors, my version of the uGuru does seem to stop writing to them, the
* write function above aborts in this case with:
* "CMD reg does not hold 0xAC after write"
*
* Notice these 2 tests are non destructive iow read-only tests, otherwise
* they would defeat their purpose. Although for the bank2_sensors detection a
* read/write test would be feasible because of the reaction above, I've
* however opted to stay on the safe side.
*/
static void
abituguru_detect_no_bank2_sensors(struct abituguru_data *data)
{
int i;
if (fan_sensors > 0 && fan_sensors <= ABIT_UGURU_MAX_BANK2_SENSORS) {
data->bank2_sensors = fan_sensors;
ABIT_UGURU_DEBUG(2, "assuming %d fan sensors because of "
"\"fan_sensors\" module param\n",
(int)data->bank2_sensors);
return;
}
ABIT_UGURU_DEBUG(2, "detecting number of fan sensors\n");
for (i = 0; i < ABIT_UGURU_MAX_BANK2_SENSORS; i++) {
/*
* 0x89 are the known used bits:
* -0x80 enable shutdown
* -0x08 enable beep
* -0x01 enable alarm
* All other bits should be 0, but on some motherboards
* 0x40 (bit 6) is also high for some of the fans??
*/
if (data->bank2_settings[i][0] & ~0xC9) {
ABIT_UGURU_DEBUG(2, " bank2 sensor %d does not seem "
"to be a fan sensor: settings[0] = %02X\n",
i, (unsigned int)data->bank2_settings[i][0]);
break;
}
/* check if the threshold is within the allowed range */
if (data->bank2_settings[i][1] <
abituguru_bank2_min_threshold) {
ABIT_UGURU_DEBUG(2, " bank2 sensor %d does not seem "
"to be a fan sensor: the threshold (%d) is "
"below the minimum (%d)\n", i,
(int)data->bank2_settings[i][1],
(int)abituguru_bank2_min_threshold);
break;
}
if (data->bank2_settings[i][1] >
abituguru_bank2_max_threshold) {
ABIT_UGURU_DEBUG(2, " bank2 sensor %d does not seem "
"to be a fan sensor: the threshold (%d) is "
"above the maximum (%d)\n", i,
(int)data->bank2_settings[i][1],
(int)abituguru_bank2_max_threshold);
break;
}
}
data->bank2_sensors = i;
ABIT_UGURU_DEBUG(2, " found: %d fan sensors\n",
(int)data->bank2_sensors);
}
static void
abituguru_detect_no_pwms(struct abituguru_data *data)
{
int i, j;
if (pwms > 0 && pwms <= ABIT_UGURU_MAX_PWMS) {
data->pwms = pwms;
ABIT_UGURU_DEBUG(2, "assuming %d PWM outputs because of "
"\"pwms\" module param\n", (int)data->pwms);
return;
}
ABIT_UGURU_DEBUG(2, "detecting number of PWM outputs\n");
for (i = 0; i < ABIT_UGURU_MAX_PWMS; i++) {
/*
* 0x80 is the enable bit and the low
* nibble is which temp sensor to use,
* the other bits should be 0
*/
if (data->pwm_settings[i][0] & ~0x8F) {
ABIT_UGURU_DEBUG(2, " pwm channel %d does not seem "
"to be a pwm channel: settings[0] = %02X\n",
i, (unsigned int)data->pwm_settings[i][0]);
break;
}
/*
* the low nibble must correspond to one of the temp sensors
* we've found
*/
for (j = 0; j < data->bank1_sensors[ABIT_UGURU_TEMP_SENSOR];
j++) {
if (data->bank1_address[ABIT_UGURU_TEMP_SENSOR][j] ==
(data->pwm_settings[i][0] & 0x0F))
break;
}
if (j == data->bank1_sensors[ABIT_UGURU_TEMP_SENSOR]) {
ABIT_UGURU_DEBUG(2, " pwm channel %d does not seem "
"to be a pwm channel: %d is not a valid temp "
"sensor address\n", i,
data->pwm_settings[i][0] & 0x0F);
break;
}
/* check if all other settings are within the allowed range */
for (j = 1; j < 5; j++) {
u8 min;
/* special case pwm1 min pwm% */
if ((i == 0) && ((j == 1) || (j == 2)))
min = 77;
else
min = abituguru_pwm_min[j];
if (data->pwm_settings[i][j] < min) {
ABIT_UGURU_DEBUG(2, " pwm channel %d does "
"not seem to be a pwm channel: "
"setting %d (%d) is below the minimum "
"value (%d)\n", i, j,
(int)data->pwm_settings[i][j],
(int)min);
goto abituguru_detect_no_pwms_exit;
}
if (data->pwm_settings[i][j] > abituguru_pwm_max[j]) {
ABIT_UGURU_DEBUG(2, " pwm channel %d does "
"not seem to be a pwm channel: "
"setting %d (%d) is above the maximum "
"value (%d)\n", i, j,
(int)data->pwm_settings[i][j],
(int)abituguru_pwm_max[j]);
goto abituguru_detect_no_pwms_exit;
}
}
/* check that min temp < max temp and min pwm < max pwm */
if (data->pwm_settings[i][1] >= data->pwm_settings[i][2]) {
ABIT_UGURU_DEBUG(2, " pwm channel %d does not seem "
"to be a pwm channel: min pwm (%d) >= "
"max pwm (%d)\n", i,
(int)data->pwm_settings[i][1],
(int)data->pwm_settings[i][2]);
break;
}
if (data->pwm_settings[i][3] >= data->pwm_settings[i][4]) {
ABIT_UGURU_DEBUG(2, " pwm channel %d does not seem "
"to be a pwm channel: min temp (%d) >= "
"max temp (%d)\n", i,
(int)data->pwm_settings[i][3],
(int)data->pwm_settings[i][4]);
break;
}
}
abituguru_detect_no_pwms_exit:
data->pwms = i;
ABIT_UGURU_DEBUG(2, " found: %d PWM outputs\n", (int)data->pwms);
}
/*
* Following are the sysfs callback functions. These functions expect:
* sensor_device_attribute_2->index: sensor address/offset in the bank
* sensor_device_attribute_2->nr: register offset, bitmask or NA.
*/
static struct abituguru_data *abituguru_update_device(struct device *dev);
static ssize_t show_bank1_value(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = abituguru_update_device(dev);
if (!data)
return -EIO;
return sprintf(buf, "%d\n", (data->bank1_value[attr->index] *
data->bank1_max_value[attr->index] + 128) / 255);
}
static ssize_t show_bank1_setting(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%d\n",
(data->bank1_settings[attr->index][attr->nr] *
data->bank1_max_value[attr->index] + 128) / 255);
}
static ssize_t show_bank2_value(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = abituguru_update_device(dev);
if (!data)
return -EIO;
return sprintf(buf, "%d\n", (data->bank2_value[attr->index] *
ABIT_UGURU_FAN_MAX + 128) / 255);
}
static ssize_t show_bank2_setting(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%d\n",
(data->bank2_settings[attr->index][attr->nr] *
ABIT_UGURU_FAN_MAX + 128) / 255);
}
static ssize_t store_bank1_setting(struct device *dev, struct device_attribute
*devattr, const char *buf, size_t count)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
unsigned long val;
ssize_t ret;
ret = kstrtoul(buf, 10, &val);
if (ret)
return ret;
ret = count;
val = (val * 255 + data->bank1_max_value[attr->index] / 2) /
data->bank1_max_value[attr->index];
if (val > 255)
return -EINVAL;
mutex_lock(&data->update_lock);
if (data->bank1_settings[attr->index][attr->nr] != val) {
u8 orig_val = data->bank1_settings[attr->index][attr->nr];
data->bank1_settings[attr->index][attr->nr] = val;
if (abituguru_write(data, ABIT_UGURU_SENSOR_BANK1 + 2,
attr->index, data->bank1_settings[attr->index],
3) <= attr->nr) {
data->bank1_settings[attr->index][attr->nr] = orig_val;
ret = -EIO;
}
}
mutex_unlock(&data->update_lock);
return ret;
}
static ssize_t store_bank2_setting(struct device *dev, struct device_attribute
*devattr, const char *buf, size_t count)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
unsigned long val;
ssize_t ret;
ret = kstrtoul(buf, 10, &val);
if (ret)
return ret;
ret = count;
val = (val * 255 + ABIT_UGURU_FAN_MAX / 2) / ABIT_UGURU_FAN_MAX;
/* this check can be done before taking the lock */
if (val < abituguru_bank2_min_threshold ||
val > abituguru_bank2_max_threshold)
return -EINVAL;
mutex_lock(&data->update_lock);
if (data->bank2_settings[attr->index][attr->nr] != val) {
u8 orig_val = data->bank2_settings[attr->index][attr->nr];
data->bank2_settings[attr->index][attr->nr] = val;
if (abituguru_write(data, ABIT_UGURU_SENSOR_BANK2 + 2,
attr->index, data->bank2_settings[attr->index],
2) <= attr->nr) {
data->bank2_settings[attr->index][attr->nr] = orig_val;
ret = -EIO;
}
}
mutex_unlock(&data->update_lock);
return ret;
}
static ssize_t show_bank1_alarm(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = abituguru_update_device(dev);
if (!data)
return -EIO;
/*
* See if the alarm bit for this sensor is set, and if the
* alarm matches the type of alarm we're looking for (for volt
* it can be either low or high). The type is stored in a few
* readonly bits in the settings part of the relevant sensor.
* The bitmask of the type is passed to us in attr->nr.
*/
if ((data->alarms[attr->index / 8] & (0x01 << (attr->index % 8))) &&
(data->bank1_settings[attr->index][0] & attr->nr))
return sprintf(buf, "1\n");
else
return sprintf(buf, "0\n");
}
static ssize_t show_bank2_alarm(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = abituguru_update_device(dev);
if (!data)
return -EIO;
if (data->alarms[2] & (0x01 << attr->index))
return sprintf(buf, "1\n");
else
return sprintf(buf, "0\n");
}
static ssize_t show_bank1_mask(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
if (data->bank1_settings[attr->index][0] & attr->nr)
return sprintf(buf, "1\n");
else
return sprintf(buf, "0\n");
}
static ssize_t show_bank2_mask(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
if (data->bank2_settings[attr->index][0] & attr->nr)
return sprintf(buf, "1\n");
else
return sprintf(buf, "0\n");
}
static ssize_t store_bank1_mask(struct device *dev,
struct device_attribute *devattr, const char *buf, size_t count)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
ssize_t ret;
u8 orig_val;
unsigned long mask;
ret = kstrtoul(buf, 10, &mask);
if (ret)
return ret;
ret = count;
mutex_lock(&data->update_lock);
orig_val = data->bank1_settings[attr->index][0];
if (mask)
data->bank1_settings[attr->index][0] |= attr->nr;
else
data->bank1_settings[attr->index][0] &= ~attr->nr;
if ((data->bank1_settings[attr->index][0] != orig_val) &&
(abituguru_write(data,
ABIT_UGURU_SENSOR_BANK1 + 2, attr->index,
data->bank1_settings[attr->index], 3) < 1)) {
data->bank1_settings[attr->index][0] = orig_val;
ret = -EIO;
}
mutex_unlock(&data->update_lock);
return ret;
}
static ssize_t store_bank2_mask(struct device *dev,
struct device_attribute *devattr, const char *buf, size_t count)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
ssize_t ret;
u8 orig_val;
unsigned long mask;
ret = kstrtoul(buf, 10, &mask);
if (ret)
return ret;
ret = count;
mutex_lock(&data->update_lock);
orig_val = data->bank2_settings[attr->index][0];
if (mask)
data->bank2_settings[attr->index][0] |= attr->nr;
else
data->bank2_settings[attr->index][0] &= ~attr->nr;
if ((data->bank2_settings[attr->index][0] != orig_val) &&
(abituguru_write(data,
ABIT_UGURU_SENSOR_BANK2 + 2, attr->index,
data->bank2_settings[attr->index], 2) < 1)) {
data->bank2_settings[attr->index][0] = orig_val;
ret = -EIO;
}
mutex_unlock(&data->update_lock);
return ret;
}
/* Fan PWM (speed control) */
static ssize_t show_pwm_setting(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", data->pwm_settings[attr->index][attr->nr] *
abituguru_pwm_settings_multiplier[attr->nr]);
}
static ssize_t store_pwm_setting(struct device *dev, struct device_attribute
*devattr, const char *buf, size_t count)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
u8 min;
unsigned long val;
ssize_t ret;
ret = kstrtoul(buf, 10, &val);
if (ret)
return ret;
ret = count;
val = (val + abituguru_pwm_settings_multiplier[attr->nr] / 2) /
abituguru_pwm_settings_multiplier[attr->nr];
/* special case pwm1 min pwm% */
if ((attr->index == 0) && ((attr->nr == 1) || (attr->nr == 2)))
min = 77;
else
min = abituguru_pwm_min[attr->nr];
/* this check can be done before taking the lock */
if (val < min || val > abituguru_pwm_max[attr->nr])
return -EINVAL;
mutex_lock(&data->update_lock);
/* this check needs to be done after taking the lock */
if ((attr->nr & 1) &&
(val >= data->pwm_settings[attr->index][attr->nr + 1]))
ret = -EINVAL;
else if (!(attr->nr & 1) &&
(val <= data->pwm_settings[attr->index][attr->nr - 1]))
ret = -EINVAL;
else if (data->pwm_settings[attr->index][attr->nr] != val) {
u8 orig_val = data->pwm_settings[attr->index][attr->nr];
data->pwm_settings[attr->index][attr->nr] = val;
if (abituguru_write(data, ABIT_UGURU_FAN_PWM + 1,
attr->index, data->pwm_settings[attr->index],
5) <= attr->nr) {
data->pwm_settings[attr->index][attr->nr] =
orig_val;
ret = -EIO;
}
}
mutex_unlock(&data->update_lock);
return ret;
}
static ssize_t show_pwm_sensor(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
int i;
/*
* We need to walk to the temp sensor addresses to find what
* the userspace id of the configured temp sensor is.
*/
for (i = 0; i < data->bank1_sensors[ABIT_UGURU_TEMP_SENSOR]; i++)
if (data->bank1_address[ABIT_UGURU_TEMP_SENSOR][i] ==
(data->pwm_settings[attr->index][0] & 0x0F))
return sprintf(buf, "%d\n", i+1);
return -ENXIO;
}
static ssize_t store_pwm_sensor(struct device *dev, struct device_attribute
*devattr, const char *buf, size_t count)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
ssize_t ret;
unsigned long val;
u8 orig_val;
u8 address;
ret = kstrtoul(buf, 10, &val);
if (ret)
return ret;
if (val == 0 || val > data->bank1_sensors[ABIT_UGURU_TEMP_SENSOR])
return -EINVAL;
val -= 1;
ret = count;
mutex_lock(&data->update_lock);
orig_val = data->pwm_settings[attr->index][0];
address = data->bank1_address[ABIT_UGURU_TEMP_SENSOR][val];
data->pwm_settings[attr->index][0] &= 0xF0;
data->pwm_settings[attr->index][0] |= address;
if (data->pwm_settings[attr->index][0] != orig_val) {
if (abituguru_write(data, ABIT_UGURU_FAN_PWM + 1, attr->index,
data->pwm_settings[attr->index], 5) < 1) {
data->pwm_settings[attr->index][0] = orig_val;
ret = -EIO;
}
}
mutex_unlock(&data->update_lock);
return ret;
}
static ssize_t show_pwm_enable(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
int res = 0;
if (data->pwm_settings[attr->index][0] & ABIT_UGURU_FAN_PWM_ENABLE)
res = 2;
return sprintf(buf, "%d\n", res);
}
static ssize_t store_pwm_enable(struct device *dev, struct device_attribute
*devattr, const char *buf, size_t count)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru_data *data = dev_get_drvdata(dev);
u8 orig_val;
ssize_t ret;
unsigned long user_val;
ret = kstrtoul(buf, 10, &user_val);
if (ret)
return ret;
ret = count;
mutex_lock(&data->update_lock);
orig_val = data->pwm_settings[attr->index][0];
switch (user_val) {
case 0:
data->pwm_settings[attr->index][0] &=
~ABIT_UGURU_FAN_PWM_ENABLE;
break;
case 2:
data->pwm_settings[attr->index][0] |= ABIT_UGURU_FAN_PWM_ENABLE;
break;
default:
ret = -EINVAL;
}
if ((data->pwm_settings[attr->index][0] != orig_val) &&
(abituguru_write(data, ABIT_UGURU_FAN_PWM + 1,
attr->index, data->pwm_settings[attr->index],
5) < 1)) {
data->pwm_settings[attr->index][0] = orig_val;
ret = -EIO;
}
mutex_unlock(&data->update_lock);
return ret;
}
static ssize_t show_name(struct device *dev,
struct device_attribute *devattr, char *buf)
{
return sprintf(buf, "%s\n", ABIT_UGURU_NAME);
}
/* Sysfs attr templates, the real entries are generated automatically. */
static const
struct sensor_device_attribute_2 abituguru_sysfs_bank1_templ[2][9] = {
{
SENSOR_ATTR_2(in%d_input, 0444, show_bank1_value, NULL, 0, 0),
SENSOR_ATTR_2(in%d_min, 0644, show_bank1_setting,
store_bank1_setting, 1, 0),
SENSOR_ATTR_2(in%d_min_alarm, 0444, show_bank1_alarm, NULL,
ABIT_UGURU_VOLT_LOW_ALARM_FLAG, 0),
SENSOR_ATTR_2(in%d_max, 0644, show_bank1_setting,
store_bank1_setting, 2, 0),
SENSOR_ATTR_2(in%d_max_alarm, 0444, show_bank1_alarm, NULL,
ABIT_UGURU_VOLT_HIGH_ALARM_FLAG, 0),
SENSOR_ATTR_2(in%d_beep, 0644, show_bank1_mask,
store_bank1_mask, ABIT_UGURU_BEEP_ENABLE, 0),
SENSOR_ATTR_2(in%d_shutdown, 0644, show_bank1_mask,
store_bank1_mask, ABIT_UGURU_SHUTDOWN_ENABLE, 0),
SENSOR_ATTR_2(in%d_min_alarm_enable, 0644, show_bank1_mask,
store_bank1_mask, ABIT_UGURU_VOLT_LOW_ALARM_ENABLE, 0),
SENSOR_ATTR_2(in%d_max_alarm_enable, 0644, show_bank1_mask,
store_bank1_mask, ABIT_UGURU_VOLT_HIGH_ALARM_ENABLE, 0),
}, {
SENSOR_ATTR_2(temp%d_input, 0444, show_bank1_value, NULL, 0, 0),
SENSOR_ATTR_2(temp%d_alarm, 0444, show_bank1_alarm, NULL,
ABIT_UGURU_TEMP_HIGH_ALARM_FLAG, 0),
SENSOR_ATTR_2(temp%d_max, 0644, show_bank1_setting,
store_bank1_setting, 1, 0),
SENSOR_ATTR_2(temp%d_crit, 0644, show_bank1_setting,
store_bank1_setting, 2, 0),
SENSOR_ATTR_2(temp%d_beep, 0644, show_bank1_mask,
store_bank1_mask, ABIT_UGURU_BEEP_ENABLE, 0),
SENSOR_ATTR_2(temp%d_shutdown, 0644, show_bank1_mask,
store_bank1_mask, ABIT_UGURU_SHUTDOWN_ENABLE, 0),
SENSOR_ATTR_2(temp%d_alarm_enable, 0644, show_bank1_mask,
store_bank1_mask, ABIT_UGURU_TEMP_HIGH_ALARM_ENABLE, 0),
}
};
static const struct sensor_device_attribute_2 abituguru_sysfs_fan_templ[6] = {
SENSOR_ATTR_2(fan%d_input, 0444, show_bank2_value, NULL, 0, 0),
SENSOR_ATTR_2(fan%d_alarm, 0444, show_bank2_alarm, NULL, 0, 0),
SENSOR_ATTR_2(fan%d_min, 0644, show_bank2_setting,
store_bank2_setting, 1, 0),
SENSOR_ATTR_2(fan%d_beep, 0644, show_bank2_mask,
store_bank2_mask, ABIT_UGURU_BEEP_ENABLE, 0),
SENSOR_ATTR_2(fan%d_shutdown, 0644, show_bank2_mask,
store_bank2_mask, ABIT_UGURU_SHUTDOWN_ENABLE, 0),
SENSOR_ATTR_2(fan%d_alarm_enable, 0644, show_bank2_mask,
store_bank2_mask, ABIT_UGURU_FAN_LOW_ALARM_ENABLE, 0),
};
static const struct sensor_device_attribute_2 abituguru_sysfs_pwm_templ[6] = {
SENSOR_ATTR_2(pwm%d_enable, 0644, show_pwm_enable,
store_pwm_enable, 0, 0),
SENSOR_ATTR_2(pwm%d_auto_channels_temp, 0644, show_pwm_sensor,
store_pwm_sensor, 0, 0),
SENSOR_ATTR_2(pwm%d_auto_point1_pwm, 0644, show_pwm_setting,
store_pwm_setting, 1, 0),
SENSOR_ATTR_2(pwm%d_auto_point2_pwm, 0644, show_pwm_setting,
store_pwm_setting, 2, 0),
SENSOR_ATTR_2(pwm%d_auto_point1_temp, 0644, show_pwm_setting,
store_pwm_setting, 3, 0),
SENSOR_ATTR_2(pwm%d_auto_point2_temp, 0644, show_pwm_setting,
store_pwm_setting, 4, 0),
};
static struct sensor_device_attribute_2 abituguru_sysfs_attr[] = {
SENSOR_ATTR_2(name, 0444, show_name, NULL, 0, 0),
};
static int abituguru_probe(struct platform_device *pdev)
{
struct abituguru_data *data;
int i, j, used, sysfs_names_free, sysfs_attr_i, res = -ENODEV;
char *sysfs_filename;
/*
* El weirdo probe order, to keep the sysfs order identical to the
* BIOS and window-appliction listing order.
*/
static const u8 probe_order[ABIT_UGURU_MAX_BANK1_SENSORS] = {
0x00, 0x01, 0x03, 0x04, 0x0A, 0x08, 0x0E, 0x02,
0x09, 0x06, 0x05, 0x0B, 0x0F, 0x0D, 0x07, 0x0C };
data = devm_kzalloc(&pdev->dev, sizeof(struct abituguru_data),
GFP_KERNEL);
if (!data)
return -ENOMEM;
data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start;
mutex_init(&data->update_lock);
platform_set_drvdata(pdev, data);
/* See if the uGuru is ready */
if (inb_p(data->addr + ABIT_UGURU_DATA) == ABIT_UGURU_STATUS_INPUT)
data->uguru_ready = 1;
/*
* Completely read the uGuru this has 2 purposes:
* - testread / see if one really is there.
* - make an in memory copy of all the uguru settings for future use.
*/
if (abituguru_read(data, ABIT_UGURU_ALARM_BANK, 0,
data->alarms, 3, ABIT_UGURU_MAX_RETRIES) != 3)
goto abituguru_probe_error;
for (i = 0; i < ABIT_UGURU_MAX_BANK1_SENSORS; i++) {
if (abituguru_read(data, ABIT_UGURU_SENSOR_BANK1, i,
&data->bank1_value[i], 1,
ABIT_UGURU_MAX_RETRIES) != 1)
goto abituguru_probe_error;
if (abituguru_read(data, ABIT_UGURU_SENSOR_BANK1+1, i,
data->bank1_settings[i], 3,
ABIT_UGURU_MAX_RETRIES) != 3)
goto abituguru_probe_error;
}
/*
* Note: We don't know how many bank2 sensors / pwms there really are,
* but in order to "detect" this we need to read the maximum amount
* anyways. If we read sensors/pwms not there we'll just read crap
* this can't hurt. We need the detection because we don't want
* unwanted writes, which will hurt!
*/
for (i = 0; i < ABIT_UGURU_MAX_BANK2_SENSORS; i++) {
if (abituguru_read(data, ABIT_UGURU_SENSOR_BANK2, i,
&data->bank2_value[i], 1,
ABIT_UGURU_MAX_RETRIES) != 1)
goto abituguru_probe_error;
if (abituguru_read(data, ABIT_UGURU_SENSOR_BANK2+1, i,
data->bank2_settings[i], 2,
ABIT_UGURU_MAX_RETRIES) != 2)
goto abituguru_probe_error;
}
for (i = 0; i < ABIT_UGURU_MAX_PWMS; i++) {
if (abituguru_read(data, ABIT_UGURU_FAN_PWM, i,
data->pwm_settings[i], 5,
ABIT_UGURU_MAX_RETRIES) != 5)
goto abituguru_probe_error;
}
data->last_updated = jiffies;
/* Detect sensor types and fill the sysfs attr for bank1 */
sysfs_attr_i = 0;
sysfs_filename = data->sysfs_names;
sysfs_names_free = ABITUGURU_SYSFS_NAMES_LENGTH;
for (i = 0; i < ABIT_UGURU_MAX_BANK1_SENSORS; i++) {
res = abituguru_detect_bank1_sensor_type(data, probe_order[i]);
if (res < 0)
goto abituguru_probe_error;
if (res == ABIT_UGURU_NC)
continue;
/* res 1 (temp) sensors have 7 sysfs entries, 0 (in) 9 */
for (j = 0; j < (res ? 7 : 9); j++) {
used = snprintf(sysfs_filename, sysfs_names_free,
abituguru_sysfs_bank1_templ[res][j].dev_attr.
attr.name, data->bank1_sensors[res] + res)
+ 1;
data->sysfs_attr[sysfs_attr_i] =
abituguru_sysfs_bank1_templ[res][j];
data->sysfs_attr[sysfs_attr_i].dev_attr.attr.name =
sysfs_filename;
data->sysfs_attr[sysfs_attr_i].index = probe_order[i];
sysfs_filename += used;
sysfs_names_free -= used;
sysfs_attr_i++;
}
data->bank1_max_value[probe_order[i]] =
abituguru_bank1_max_value[res];
data->bank1_address[res][data->bank1_sensors[res]] =
probe_order[i];
data->bank1_sensors[res]++;
}
/* Detect number of sensors and fill the sysfs attr for bank2 (fans) */
abituguru_detect_no_bank2_sensors(data);
for (i = 0; i < data->bank2_sensors; i++) {
for (j = 0; j < ARRAY_SIZE(abituguru_sysfs_fan_templ); j++) {
used = snprintf(sysfs_filename, sysfs_names_free,
abituguru_sysfs_fan_templ[j].dev_attr.attr.name,
i + 1) + 1;
data->sysfs_attr[sysfs_attr_i] =
abituguru_sysfs_fan_templ[j];
data->sysfs_attr[sysfs_attr_i].dev_attr.attr.name =
sysfs_filename;
data->sysfs_attr[sysfs_attr_i].index = i;
sysfs_filename += used;
sysfs_names_free -= used;
sysfs_attr_i++;
}
}
/* Detect number of sensors and fill the sysfs attr for pwms */
abituguru_detect_no_pwms(data);
for (i = 0; i < data->pwms; i++) {
for (j = 0; j < ARRAY_SIZE(abituguru_sysfs_pwm_templ); j++) {
used = snprintf(sysfs_filename, sysfs_names_free,
abituguru_sysfs_pwm_templ[j].dev_attr.attr.name,
i + 1) + 1;
data->sysfs_attr[sysfs_attr_i] =
abituguru_sysfs_pwm_templ[j];
data->sysfs_attr[sysfs_attr_i].dev_attr.attr.name =
sysfs_filename;
data->sysfs_attr[sysfs_attr_i].index = i;
sysfs_filename += used;
sysfs_names_free -= used;
sysfs_attr_i++;
}
}
/* Fail safe check, this should never happen! */
if (sysfs_names_free < 0) {
pr_err("Fatal error ran out of space for sysfs attr names. %s %s",
never_happen, report_this);
res = -ENAMETOOLONG;
goto abituguru_probe_error;
}
pr_info("found Abit uGuru\n");
/* Register sysfs hooks */
for (i = 0; i < sysfs_attr_i; i++) {
res = device_create_file(&pdev->dev,
&data->sysfs_attr[i].dev_attr);
if (res)
goto abituguru_probe_error;
}
for (i = 0; i < ARRAY_SIZE(abituguru_sysfs_attr); i++) {
res = device_create_file(&pdev->dev,
&abituguru_sysfs_attr[i].dev_attr);
if (res)
goto abituguru_probe_error;
}
data->hwmon_dev = hwmon_device_register(&pdev->dev);
if (!IS_ERR(data->hwmon_dev))
return 0; /* success */
res = PTR_ERR(data->hwmon_dev);
abituguru_probe_error:
for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++)
device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr);
for (i = 0; i < ARRAY_SIZE(abituguru_sysfs_attr); i++)
device_remove_file(&pdev->dev,
&abituguru_sysfs_attr[i].dev_attr);
return res;
}
static int abituguru_remove(struct platform_device *pdev)
{
int i;
struct abituguru_data *data = platform_get_drvdata(pdev);
hwmon_device_unregister(data->hwmon_dev);
for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++)
device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr);
for (i = 0; i < ARRAY_SIZE(abituguru_sysfs_attr); i++)
device_remove_file(&pdev->dev,
&abituguru_sysfs_attr[i].dev_attr);
return 0;
}
static struct abituguru_data *abituguru_update_device(struct device *dev)
{
int i, err;
struct abituguru_data *data = dev_get_drvdata(dev);
/* fake a complete successful read if no update necessary. */
char success = 1;
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ)) {
success = 0;
err = abituguru_read(data, ABIT_UGURU_ALARM_BANK, 0,
data->alarms, 3, 0);
if (err != 3)
goto LEAVE_UPDATE;
for (i = 0; i < ABIT_UGURU_MAX_BANK1_SENSORS; i++) {
err = abituguru_read(data, ABIT_UGURU_SENSOR_BANK1,
i, &data->bank1_value[i], 1, 0);
if (err != 1)
goto LEAVE_UPDATE;
err = abituguru_read(data, ABIT_UGURU_SENSOR_BANK1 + 1,
i, data->bank1_settings[i], 3, 0);
if (err != 3)
goto LEAVE_UPDATE;
}
for (i = 0; i < data->bank2_sensors; i++) {
err = abituguru_read(data, ABIT_UGURU_SENSOR_BANK2, i,
&data->bank2_value[i], 1, 0);
if (err != 1)
goto LEAVE_UPDATE;
}
/* success! */
success = 1;
data->update_timeouts = 0;
LEAVE_UPDATE:
/* handle timeout condition */
if (!success && (err == -EBUSY || err >= 0)) {
/* No overflow please */
if (data->update_timeouts < 255u)
data->update_timeouts++;
if (data->update_timeouts <= ABIT_UGURU_MAX_TIMEOUTS) {
ABIT_UGURU_DEBUG(3, "timeout exceeded, will "
"try again next update\n");
/* Just a timeout, fake a successful read */
success = 1;
} else
ABIT_UGURU_DEBUG(1, "timeout exceeded %d "
"times waiting for more input state\n",
(int)data->update_timeouts);
}
/* On success set last_updated */
if (success)
data->last_updated = jiffies;
}
mutex_unlock(&data->update_lock);
if (success)
return data;
else
return NULL;
}
static int abituguru_suspend(struct device *dev)
{
struct abituguru_data *data = dev_get_drvdata(dev);
/*
* make sure all communications with the uguru are done and no new
* ones are started
*/
mutex_lock(&data->update_lock);
return 0;
}
static int abituguru_resume(struct device *dev)
{
struct abituguru_data *data = dev_get_drvdata(dev);
/* See if the uGuru is still ready */
if (inb_p(data->addr + ABIT_UGURU_DATA) != ABIT_UGURU_STATUS_INPUT)
data->uguru_ready = 0;
mutex_unlock(&data->update_lock);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(abituguru_pm, abituguru_suspend, abituguru_resume);
static struct platform_driver abituguru_driver = {
.driver = {
.name = ABIT_UGURU_NAME,
.pm = pm_sleep_ptr(&abituguru_pm),
},
.probe = abituguru_probe,
.remove = abituguru_remove,
};
static int __init abituguru_detect(void)
{
/*
* See if there is an uguru there. After a reboot uGuru will hold 0x00
* at DATA and 0xAC, when this driver has already been loaded once
* DATA will hold 0x08. For most uGuru's CMD will hold 0xAC in either
* scenario but some will hold 0x00.
* Some uGuru's initially hold 0x09 at DATA and will only hold 0x08
* after reading CMD first, so CMD must be read first!
*/
u8 cmd_val = inb_p(ABIT_UGURU_BASE + ABIT_UGURU_CMD);
u8 data_val = inb_p(ABIT_UGURU_BASE + ABIT_UGURU_DATA);
if (((data_val == 0x00) || (data_val == 0x08)) &&
((cmd_val == 0x00) || (cmd_val == 0xAC)))
return ABIT_UGURU_BASE;
ABIT_UGURU_DEBUG(2, "no Abit uGuru found, data = 0x%02X, cmd = "
"0x%02X\n", (unsigned int)data_val, (unsigned int)cmd_val);
if (force) {
pr_info("Assuming Abit uGuru is present because of \"force\" parameter\n");
return ABIT_UGURU_BASE;
}
/* No uGuru found */
return -ENODEV;
}
static struct platform_device *abituguru_pdev;
static int __init abituguru_init(void)
{
int address, err;
struct resource res = { .flags = IORESOURCE_IO };
const char *board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
/* safety check, refuse to load on non Abit motherboards */
if (!force && (!board_vendor ||
strcmp(board_vendor, "http://www.abit.com.tw/")))
return -ENODEV;
address = abituguru_detect();
if (address < 0)
return address;
err = platform_driver_register(&abituguru_driver);
if (err)
goto exit;
abituguru_pdev = platform_device_alloc(ABIT_UGURU_NAME, address);
if (!abituguru_pdev) {
pr_err("Device allocation failed\n");
err = -ENOMEM;
goto exit_driver_unregister;
}
res.start = address;
res.end = address + ABIT_UGURU_REGION_LENGTH - 1;
res.name = ABIT_UGURU_NAME;
err = platform_device_add_resources(abituguru_pdev, &res, 1);
if (err) {
pr_err("Device resource addition failed (%d)\n", err);
goto exit_device_put;
}
err = platform_device_add(abituguru_pdev);
if (err) {
pr_err("Device addition failed (%d)\n", err);
goto exit_device_put;
}
return 0;
exit_device_put:
platform_device_put(abituguru_pdev);
exit_driver_unregister:
platform_driver_unregister(&abituguru_driver);
exit:
return err;
}
static void __exit abituguru_exit(void)
{
platform_device_unregister(abituguru_pdev);
platform_driver_unregister(&abituguru_driver);
}
MODULE_AUTHOR("Hans de Goede <[email protected]>");
MODULE_DESCRIPTION("Abit uGuru Sensor device");
MODULE_LICENSE("GPL");
module_init(abituguru_init);
module_exit(abituguru_exit);
|
linux-master
|
drivers/hwmon/abituguru.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* vt8231.c - Part of lm_sensors, Linux kernel modules
* for hardware monitoring
*
* Copyright (c) 2005 Roger Lucas <[email protected]>
* Copyright (c) 2002 Mark D. Studebaker <[email protected]>
* Aaron M. Marsh <[email protected]>
*/
/*
* Supports VIA VT8231 South Bridge embedded sensors
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/jiffies.h>
#include <linux/platform_device.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/acpi.h>
#include <linux/io.h>
static int force_addr;
module_param(force_addr, int, 0);
MODULE_PARM_DESC(force_addr, "Initialize the base address of the sensors");
static struct platform_device *pdev;
#define VT8231_EXTENT 0x80
#define VT8231_BASE_REG 0x70
#define VT8231_ENABLE_REG 0x74
#define DRIVER_NAME "vt8231"
/*
* The VT8231 registers
*
* The reset value for the input channel configuration is used (Reg 0x4A=0x07)
* which sets the selected inputs marked with '*' below if multiple options are
* possible:
*
* Voltage Mode Temperature Mode
* Sensor Linux Id Linux Id VIA Id
* -------- -------- -------- ------
* CPU Diode N/A temp1 0
* UIC1 in0 temp2 * 1
* UIC2 in1 * temp3 2
* UIC3 in2 * temp4 3
* UIC4 in3 * temp5 4
* UIC5 in4 * temp6 5
* 3.3V in5 N/A
*
* Note that the BIOS may set the configuration register to a different value
* to match the motherboard configuration.
*/
/* fans numbered 0-1 */
#define VT8231_REG_FAN_MIN(nr) (0x3b + (nr))
#define VT8231_REG_FAN(nr) (0x29 + (nr))
/* Voltage inputs numbered 0-5 */
static const u8 regvolt[] = { 0x21, 0x22, 0x23, 0x24, 0x25, 0x26 };
static const u8 regvoltmax[] = { 0x3d, 0x2b, 0x2d, 0x2f, 0x31, 0x33 };
static const u8 regvoltmin[] = { 0x3e, 0x2c, 0x2e, 0x30, 0x32, 0x34 };
/*
* Temperatures are numbered 1-6 according to the Linux kernel specification.
*
* In the VIA datasheet, however, the temperatures are numbered from zero.
* Since it is important that this driver can easily be compared to the VIA
* datasheet, we will use the VIA numbering within this driver and map the
* kernel sysfs device name to the VIA number in the sysfs callback.
*/
#define VT8231_REG_TEMP_LOW01 0x49
#define VT8231_REG_TEMP_LOW25 0x4d
static const u8 regtemp[] = { 0x1f, 0x21, 0x22, 0x23, 0x24, 0x25 };
static const u8 regtempmax[] = { 0x39, 0x3d, 0x2b, 0x2d, 0x2f, 0x31 };
static const u8 regtempmin[] = { 0x3a, 0x3e, 0x2c, 0x2e, 0x30, 0x32 };
#define TEMP_FROM_REG(reg) (((253 * 4 - (reg)) * 550 + 105) / 210)
#define TEMP_MAXMIN_FROM_REG(reg) (((253 - (reg)) * 2200 + 105) / 210)
#define TEMP_MAXMIN_TO_REG(val) (253 - ((val) * 210 + 1100) / 2200)
#define VT8231_REG_CONFIG 0x40
#define VT8231_REG_ALARM1 0x41
#define VT8231_REG_ALARM2 0x42
#define VT8231_REG_FANDIV 0x47
#define VT8231_REG_UCH_CONFIG 0x4a
#define VT8231_REG_TEMP1_CONFIG 0x4b
#define VT8231_REG_TEMP2_CONFIG 0x4c
/*
* temps 0-5 as numbered in VIA datasheet - see later for mapping to Linux
* numbering
*/
#define ISTEMP(i, ch_config) ((i) == 0 ? 1 : \
((ch_config) >> ((i)+1)) & 0x01)
/* voltages 0-5 */
#define ISVOLT(i, ch_config) ((i) == 5 ? 1 : \
!(((ch_config) >> ((i)+2)) & 0x01))
#define DIV_FROM_REG(val) (1 << (val))
/*
* NB The values returned here are NOT temperatures. The calibration curves
* for the thermistor curves are board-specific and must go in the
* sensors.conf file. Temperature sensors are actually ten bits, but the
* VIA datasheet only considers the 8 MSBs obtained from the regtemp[]
* register. The temperature value returned should have a magnitude of 3,
* so we use the VIA scaling as the "true" scaling and use the remaining 2
* LSBs as fractional precision.
*
* All the on-chip hardware temperature comparisons for the alarms are only
* 8-bits wide, and compare against the 8 MSBs of the temperature. The bits
* in the registers VT8231_REG_TEMP_LOW01 and VT8231_REG_TEMP_LOW25 are
* ignored.
*/
/*
****** FAN RPM CONVERSIONS ********
* This chip saturates back at 0, not at 255 like many the other chips.
* So, 0 means 0 RPM
*/
static inline u8 FAN_TO_REG(long rpm, int div)
{
if (rpm <= 0 || rpm > 1310720)
return 0;
return clamp_val(1310720 / (rpm * div), 1, 255);
}
#define FAN_FROM_REG(val, div) ((val) == 0 ? 0 : 1310720 / ((val) * (div)))
struct vt8231_data {
unsigned short addr;
const char *name;
struct mutex update_lock;
struct device *hwmon_dev;
bool valid; /* true if following fields are valid */
unsigned long last_updated; /* In jiffies */
u8 in[6]; /* Register value */
u8 in_max[6]; /* Register value */
u8 in_min[6]; /* Register value */
u16 temp[6]; /* Register value 10 bit, right aligned */
u8 temp_max[6]; /* Register value */
u8 temp_min[6]; /* Register value */
u8 fan[2]; /* Register value */
u8 fan_min[2]; /* Register value */
u8 fan_div[2]; /* Register encoding, shifted right */
u16 alarms; /* Register encoding */
u8 uch_config;
};
static struct pci_dev *s_bridge;
static inline int vt8231_read_value(struct vt8231_data *data, u8 reg)
{
return inb_p(data->addr + reg);
}
static inline void vt8231_write_value(struct vt8231_data *data, u8 reg,
u8 value)
{
outb_p(value, data->addr + reg);
}
static struct vt8231_data *vt8231_update_device(struct device *dev)
{
struct vt8231_data *data = dev_get_drvdata(dev);
int i;
u16 low;
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
|| !data->valid) {
for (i = 0; i < 6; i++) {
if (ISVOLT(i, data->uch_config)) {
data->in[i] = vt8231_read_value(data,
regvolt[i]);
data->in_min[i] = vt8231_read_value(data,
regvoltmin[i]);
data->in_max[i] = vt8231_read_value(data,
regvoltmax[i]);
}
}
for (i = 0; i < 2; i++) {
data->fan[i] = vt8231_read_value(data,
VT8231_REG_FAN(i));
data->fan_min[i] = vt8231_read_value(data,
VT8231_REG_FAN_MIN(i));
}
low = vt8231_read_value(data, VT8231_REG_TEMP_LOW01);
low = (low >> 6) | ((low & 0x30) >> 2)
| (vt8231_read_value(data, VT8231_REG_TEMP_LOW25) << 4);
for (i = 0; i < 6; i++) {
if (ISTEMP(i, data->uch_config)) {
data->temp[i] = (vt8231_read_value(data,
regtemp[i]) << 2)
| ((low >> (2 * i)) & 0x03);
data->temp_max[i] = vt8231_read_value(data,
regtempmax[i]);
data->temp_min[i] = vt8231_read_value(data,
regtempmin[i]);
}
}
i = vt8231_read_value(data, VT8231_REG_FANDIV);
data->fan_div[0] = (i >> 4) & 0x03;
data->fan_div[1] = i >> 6;
data->alarms = vt8231_read_value(data, VT8231_REG_ALARM1) |
(vt8231_read_value(data, VT8231_REG_ALARM2) << 8);
/* Set alarm flags correctly */
if (!data->fan[0] && data->fan_min[0])
data->alarms |= 0x40;
else if (data->fan[0] && !data->fan_min[0])
data->alarms &= ~0x40;
if (!data->fan[1] && data->fan_min[1])
data->alarms |= 0x80;
else if (data->fan[1] && !data->fan_min[1])
data->alarms &= ~0x80;
data->last_updated = jiffies;
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
/* following are the sysfs callback functions */
static ssize_t in_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", ((data->in[nr] - 3) * 10000) / 958);
}
static ssize_t in_min_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", ((data->in_min[nr] - 3) * 10000) / 958);
}
static ssize_t in_max_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", (((data->in_max[nr] - 3) * 10000) / 958));
}
static ssize_t in_min_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = dev_get_drvdata(dev);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->in_min[nr] = clamp_val(((val * 958) / 10000) + 3, 0, 255);
vt8231_write_value(data, regvoltmin[nr], data->in_min[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t in_max_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = dev_get_drvdata(dev);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->in_max[nr] = clamp_val(((val * 958) / 10000) + 3, 0, 255);
vt8231_write_value(data, regvoltmax[nr], data->in_max[nr]);
mutex_unlock(&data->update_lock);
return count;
}
/* Special case for input 5 as this has 3.3V scaling built into the chip */
static ssize_t in5_input_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n",
(((data->in[5] - 3) * 10000 * 54) / (958 * 34)));
}
static ssize_t in5_min_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n",
(((data->in_min[5] - 3) * 10000 * 54) / (958 * 34)));
}
static ssize_t in5_max_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n",
(((data->in_max[5] - 3) * 10000 * 54) / (958 * 34)));
}
static ssize_t in5_min_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct vt8231_data *data = dev_get_drvdata(dev);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->in_min[5] = clamp_val(((val * 958 * 34) / (10000 * 54)) + 3,
0, 255);
vt8231_write_value(data, regvoltmin[5], data->in_min[5]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t in5_max_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct vt8231_data *data = dev_get_drvdata(dev);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->in_max[5] = clamp_val(((val * 958 * 34) / (10000 * 54)) + 3,
0, 255);
vt8231_write_value(data, regvoltmax[5], data->in_max[5]);
mutex_unlock(&data->update_lock);
return count;
}
static SENSOR_DEVICE_ATTR_RO(in0_input, in, 0);
static SENSOR_DEVICE_ATTR_RW(in0_min, in_min, 0);
static SENSOR_DEVICE_ATTR_RW(in0_max, in_max, 0);
static SENSOR_DEVICE_ATTR_RO(in1_input, in, 1);
static SENSOR_DEVICE_ATTR_RW(in1_min, in_min, 1);
static SENSOR_DEVICE_ATTR_RW(in1_max, in_max, 1);
static SENSOR_DEVICE_ATTR_RO(in2_input, in, 2);
static SENSOR_DEVICE_ATTR_RW(in2_min, in_min, 2);
static SENSOR_DEVICE_ATTR_RW(in2_max, in_max, 2);
static SENSOR_DEVICE_ATTR_RO(in3_input, in, 3);
static SENSOR_DEVICE_ATTR_RW(in3_min, in_min, 3);
static SENSOR_DEVICE_ATTR_RW(in3_max, in_max, 3);
static SENSOR_DEVICE_ATTR_RO(in4_input, in, 4);
static SENSOR_DEVICE_ATTR_RW(in4_min, in_min, 4);
static SENSOR_DEVICE_ATTR_RW(in4_max, in_max, 4);
static DEVICE_ATTR_RO(in5_input);
static DEVICE_ATTR_RW(in5_min);
static DEVICE_ATTR_RW(in5_max);
/* Temperatures */
static ssize_t temp1_input_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", data->temp[0] * 250);
}
static ssize_t temp1_max_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", data->temp_max[0] * 1000);
}
static ssize_t temp1_max_hyst_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", data->temp_min[0] * 1000);
}
static ssize_t temp1_max_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct vt8231_data *data = dev_get_drvdata(dev);
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->temp_max[0] = clamp_val((val + 500) / 1000, 0, 255);
vt8231_write_value(data, regtempmax[0], data->temp_max[0]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t temp1_max_hyst_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct vt8231_data *data = dev_get_drvdata(dev);
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->temp_min[0] = clamp_val((val + 500) / 1000, 0, 255);
vt8231_write_value(data, regtempmin[0], data->temp_min[0]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t temp_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr]));
}
static ssize_t temp_max_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", TEMP_MAXMIN_FROM_REG(data->temp_max[nr]));
}
static ssize_t temp_min_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", TEMP_MAXMIN_FROM_REG(data->temp_min[nr]));
}
static ssize_t temp_max_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = dev_get_drvdata(dev);
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->temp_max[nr] = clamp_val(TEMP_MAXMIN_TO_REG(val), 0, 255);
vt8231_write_value(data, regtempmax[nr], data->temp_max[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t temp_min_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = dev_get_drvdata(dev);
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->temp_min[nr] = clamp_val(TEMP_MAXMIN_TO_REG(val), 0, 255);
vt8231_write_value(data, regtempmin[nr], data->temp_min[nr]);
mutex_unlock(&data->update_lock);
return count;
}
/*
* Note that these map the Linux temperature sensor numbering (1-6) to the VIA
* temperature sensor numbering (0-5)
*/
static DEVICE_ATTR_RO(temp1_input);
static DEVICE_ATTR_RW(temp1_max);
static DEVICE_ATTR_RW(temp1_max_hyst);
static SENSOR_DEVICE_ATTR_RO(temp2_input, temp, 1);
static SENSOR_DEVICE_ATTR_RW(temp2_max, temp_max, 1);
static SENSOR_DEVICE_ATTR_RW(temp2_max_hyst, temp_min, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_input, temp, 2);
static SENSOR_DEVICE_ATTR_RW(temp3_max, temp_max, 2);
static SENSOR_DEVICE_ATTR_RW(temp3_max_hyst, temp_min, 2);
static SENSOR_DEVICE_ATTR_RO(temp4_input, temp, 3);
static SENSOR_DEVICE_ATTR_RW(temp4_max, temp_max, 3);
static SENSOR_DEVICE_ATTR_RW(temp4_max_hyst, temp_min, 3);
static SENSOR_DEVICE_ATTR_RO(temp5_input, temp, 4);
static SENSOR_DEVICE_ATTR_RW(temp5_max, temp_max, 4);
static SENSOR_DEVICE_ATTR_RW(temp5_max_hyst, temp_min, 4);
static SENSOR_DEVICE_ATTR_RO(temp6_input, temp, 5);
static SENSOR_DEVICE_ATTR_RW(temp6_max, temp_max, 5);
static SENSOR_DEVICE_ATTR_RW(temp6_max_hyst, temp_min, 5);
/* Fans */
static ssize_t fan_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", FAN_FROM_REG(data->fan[nr],
DIV_FROM_REG(data->fan_div[nr])));
}
static ssize_t fan_min_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", FAN_FROM_REG(data->fan_min[nr],
DIV_FROM_REG(data->fan_div[nr])));
}
static ssize_t fan_div_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", DIV_FROM_REG(data->fan_div[nr]));
}
static ssize_t fan_min_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
struct vt8231_data *data = dev_get_drvdata(dev);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
vt8231_write_value(data, VT8231_REG_FAN_MIN(nr), data->fan_min[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t fan_div_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct vt8231_data *data = dev_get_drvdata(dev);
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
unsigned long val;
int nr = sensor_attr->index;
int old = vt8231_read_value(data, VT8231_REG_FANDIV);
long min = FAN_FROM_REG(data->fan_min[nr],
DIV_FROM_REG(data->fan_div[nr]));
int err;
err = kstrtoul(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
switch (val) {
case 1:
data->fan_div[nr] = 0;
break;
case 2:
data->fan_div[nr] = 1;
break;
case 4:
data->fan_div[nr] = 2;
break;
case 8:
data->fan_div[nr] = 3;
break;
default:
dev_err(dev,
"fan_div value %ld not supported. Choose one of 1, 2, 4 or 8!\n",
val);
mutex_unlock(&data->update_lock);
return -EINVAL;
}
/* Correct the fan minimum speed */
data->fan_min[nr] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
vt8231_write_value(data, VT8231_REG_FAN_MIN(nr), data->fan_min[nr]);
old = (old & 0x0f) | (data->fan_div[1] << 6) | (data->fan_div[0] << 4);
vt8231_write_value(data, VT8231_REG_FANDIV, old);
mutex_unlock(&data->update_lock);
return count;
}
static SENSOR_DEVICE_ATTR_RO(fan1_input, fan, 0);
static SENSOR_DEVICE_ATTR_RW(fan1_min, fan_min, 0);
static SENSOR_DEVICE_ATTR_RW(fan1_div, fan_div, 0);
static SENSOR_DEVICE_ATTR_RO(fan2_input, fan, 1);
static SENSOR_DEVICE_ATTR_RW(fan2_min, fan_min, 1);
static SENSOR_DEVICE_ATTR_RW(fan2_div, fan_div, 1);
/* Alarms */
static ssize_t alarms_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%d\n", data->alarms);
}
static DEVICE_ATTR_RO(alarms);
static ssize_t alarm_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int bitnr = to_sensor_dev_attr(attr)->index;
struct vt8231_data *data = vt8231_update_device(dev);
return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
}
static SENSOR_DEVICE_ATTR_RO(temp1_alarm, alarm, 4);
static SENSOR_DEVICE_ATTR_RO(temp2_alarm, alarm, 11);
static SENSOR_DEVICE_ATTR_RO(temp3_alarm, alarm, 0);
static SENSOR_DEVICE_ATTR_RO(temp4_alarm, alarm, 1);
static SENSOR_DEVICE_ATTR_RO(temp5_alarm, alarm, 3);
static SENSOR_DEVICE_ATTR_RO(temp6_alarm, alarm, 8);
static SENSOR_DEVICE_ATTR_RO(in0_alarm, alarm, 11);
static SENSOR_DEVICE_ATTR_RO(in1_alarm, alarm, 0);
static SENSOR_DEVICE_ATTR_RO(in2_alarm, alarm, 1);
static SENSOR_DEVICE_ATTR_RO(in3_alarm, alarm, 3);
static SENSOR_DEVICE_ATTR_RO(in4_alarm, alarm, 8);
static SENSOR_DEVICE_ATTR_RO(in5_alarm, alarm, 2);
static SENSOR_DEVICE_ATTR_RO(fan1_alarm, alarm, 6);
static SENSOR_DEVICE_ATTR_RO(fan2_alarm, alarm, 7);
static ssize_t name_show(struct device *dev, struct device_attribute
*devattr, char *buf)
{
struct vt8231_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%s\n", data->name);
}
static DEVICE_ATTR_RO(name);
static struct attribute *vt8231_attributes_temps[6][5] = {
{
&dev_attr_temp1_input.attr,
&dev_attr_temp1_max_hyst.attr,
&dev_attr_temp1_max.attr,
&sensor_dev_attr_temp1_alarm.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp2_max_hyst.dev_attr.attr,
&sensor_dev_attr_temp2_max.dev_attr.attr,
&sensor_dev_attr_temp2_alarm.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_temp3_input.dev_attr.attr,
&sensor_dev_attr_temp3_max_hyst.dev_attr.attr,
&sensor_dev_attr_temp3_max.dev_attr.attr,
&sensor_dev_attr_temp3_alarm.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_temp4_input.dev_attr.attr,
&sensor_dev_attr_temp4_max_hyst.dev_attr.attr,
&sensor_dev_attr_temp4_max.dev_attr.attr,
&sensor_dev_attr_temp4_alarm.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_temp5_input.dev_attr.attr,
&sensor_dev_attr_temp5_max_hyst.dev_attr.attr,
&sensor_dev_attr_temp5_max.dev_attr.attr,
&sensor_dev_attr_temp5_alarm.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_temp6_input.dev_attr.attr,
&sensor_dev_attr_temp6_max_hyst.dev_attr.attr,
&sensor_dev_attr_temp6_max.dev_attr.attr,
&sensor_dev_attr_temp6_alarm.dev_attr.attr,
NULL
}
};
static const struct attribute_group vt8231_group_temps[6] = {
{ .attrs = vt8231_attributes_temps[0] },
{ .attrs = vt8231_attributes_temps[1] },
{ .attrs = vt8231_attributes_temps[2] },
{ .attrs = vt8231_attributes_temps[3] },
{ .attrs = vt8231_attributes_temps[4] },
{ .attrs = vt8231_attributes_temps[5] },
};
static struct attribute *vt8231_attributes_volts[6][5] = {
{
&sensor_dev_attr_in0_input.dev_attr.attr,
&sensor_dev_attr_in0_min.dev_attr.attr,
&sensor_dev_attr_in0_max.dev_attr.attr,
&sensor_dev_attr_in0_alarm.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in1_min.dev_attr.attr,
&sensor_dev_attr_in1_max.dev_attr.attr,
&sensor_dev_attr_in1_alarm.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_in2_input.dev_attr.attr,
&sensor_dev_attr_in2_min.dev_attr.attr,
&sensor_dev_attr_in2_max.dev_attr.attr,
&sensor_dev_attr_in2_alarm.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_in3_input.dev_attr.attr,
&sensor_dev_attr_in3_min.dev_attr.attr,
&sensor_dev_attr_in3_max.dev_attr.attr,
&sensor_dev_attr_in3_alarm.dev_attr.attr,
NULL
}, {
&sensor_dev_attr_in4_input.dev_attr.attr,
&sensor_dev_attr_in4_min.dev_attr.attr,
&sensor_dev_attr_in4_max.dev_attr.attr,
&sensor_dev_attr_in4_alarm.dev_attr.attr,
NULL
}, {
&dev_attr_in5_input.attr,
&dev_attr_in5_min.attr,
&dev_attr_in5_max.attr,
&sensor_dev_attr_in5_alarm.dev_attr.attr,
NULL
}
};
static const struct attribute_group vt8231_group_volts[6] = {
{ .attrs = vt8231_attributes_volts[0] },
{ .attrs = vt8231_attributes_volts[1] },
{ .attrs = vt8231_attributes_volts[2] },
{ .attrs = vt8231_attributes_volts[3] },
{ .attrs = vt8231_attributes_volts[4] },
{ .attrs = vt8231_attributes_volts[5] },
};
static struct attribute *vt8231_attributes[] = {
&sensor_dev_attr_fan1_input.dev_attr.attr,
&sensor_dev_attr_fan2_input.dev_attr.attr,
&sensor_dev_attr_fan1_min.dev_attr.attr,
&sensor_dev_attr_fan2_min.dev_attr.attr,
&sensor_dev_attr_fan1_div.dev_attr.attr,
&sensor_dev_attr_fan2_div.dev_attr.attr,
&sensor_dev_attr_fan1_alarm.dev_attr.attr,
&sensor_dev_attr_fan2_alarm.dev_attr.attr,
&dev_attr_alarms.attr,
&dev_attr_name.attr,
NULL
};
static const struct attribute_group vt8231_group = {
.attrs = vt8231_attributes,
};
static void vt8231_init_device(struct vt8231_data *data)
{
vt8231_write_value(data, VT8231_REG_TEMP1_CONFIG, 0);
vt8231_write_value(data, VT8231_REG_TEMP2_CONFIG, 0);
}
static int vt8231_probe(struct platform_device *pdev)
{
struct resource *res;
struct vt8231_data *data;
int err = 0, i;
/* Reserve the ISA region */
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!devm_request_region(&pdev->dev, res->start, VT8231_EXTENT,
DRIVER_NAME)) {
dev_err(&pdev->dev, "Region 0x%lx-0x%lx already in use!\n",
(unsigned long)res->start, (unsigned long)res->end);
return -ENODEV;
}
data = devm_kzalloc(&pdev->dev, sizeof(struct vt8231_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
platform_set_drvdata(pdev, data);
data->addr = res->start;
data->name = DRIVER_NAME;
mutex_init(&data->update_lock);
vt8231_init_device(data);
/* Register sysfs hooks */
err = sysfs_create_group(&pdev->dev.kobj, &vt8231_group);
if (err)
return err;
/* Must update device information to find out the config field */
data->uch_config = vt8231_read_value(data, VT8231_REG_UCH_CONFIG);
for (i = 0; i < ARRAY_SIZE(vt8231_group_temps); i++) {
if (ISTEMP(i, data->uch_config)) {
err = sysfs_create_group(&pdev->dev.kobj,
&vt8231_group_temps[i]);
if (err)
goto exit_remove_files;
}
}
for (i = 0; i < ARRAY_SIZE(vt8231_group_volts); i++) {
if (ISVOLT(i, data->uch_config)) {
err = sysfs_create_group(&pdev->dev.kobj,
&vt8231_group_volts[i]);
if (err)
goto exit_remove_files;
}
}
data->hwmon_dev = hwmon_device_register(&pdev->dev);
if (IS_ERR(data->hwmon_dev)) {
err = PTR_ERR(data->hwmon_dev);
goto exit_remove_files;
}
return 0;
exit_remove_files:
for (i = 0; i < ARRAY_SIZE(vt8231_group_volts); i++)
sysfs_remove_group(&pdev->dev.kobj, &vt8231_group_volts[i]);
for (i = 0; i < ARRAY_SIZE(vt8231_group_temps); i++)
sysfs_remove_group(&pdev->dev.kobj, &vt8231_group_temps[i]);
sysfs_remove_group(&pdev->dev.kobj, &vt8231_group);
return err;
}
static int vt8231_remove(struct platform_device *pdev)
{
struct vt8231_data *data = platform_get_drvdata(pdev);
int i;
hwmon_device_unregister(data->hwmon_dev);
for (i = 0; i < ARRAY_SIZE(vt8231_group_volts); i++)
sysfs_remove_group(&pdev->dev.kobj, &vt8231_group_volts[i]);
for (i = 0; i < ARRAY_SIZE(vt8231_group_temps); i++)
sysfs_remove_group(&pdev->dev.kobj, &vt8231_group_temps[i]);
sysfs_remove_group(&pdev->dev.kobj, &vt8231_group);
return 0;
}
static struct platform_driver vt8231_driver = {
.driver = {
.name = DRIVER_NAME,
},
.probe = vt8231_probe,
.remove = vt8231_remove,
};
static const struct pci_device_id vt8231_pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, vt8231_pci_ids);
static int vt8231_device_add(unsigned short address)
{
struct resource res = {
.start = address,
.end = address + VT8231_EXTENT - 1,
.name = DRIVER_NAME,
.flags = IORESOURCE_IO,
};
int err;
err = acpi_check_resource_conflict(&res);
if (err)
goto exit;
pdev = platform_device_alloc(DRIVER_NAME, address);
if (!pdev) {
err = -ENOMEM;
pr_err("Device allocation failed\n");
goto exit;
}
err = platform_device_add_resources(pdev, &res, 1);
if (err) {
pr_err("Device resource addition failed (%d)\n", err);
goto exit_device_put;
}
err = platform_device_add(pdev);
if (err) {
pr_err("Device addition failed (%d)\n", err);
goto exit_device_put;
}
return 0;
exit_device_put:
platform_device_put(pdev);
exit:
return err;
}
static int vt8231_pci_probe(struct pci_dev *dev,
const struct pci_device_id *id)
{
u16 address, val;
int ret;
if (force_addr) {
address = force_addr & 0xff00;
dev_warn(&dev->dev, "Forcing ISA address 0x%x\n",
address);
ret = pci_write_config_word(dev, VT8231_BASE_REG, address | 1);
if (ret != PCIBIOS_SUCCESSFUL)
return -ENODEV;
}
pci_read_config_word(dev, VT8231_BASE_REG, &val);
if (val == (u16)~0)
return -ENODEV;
address = val & ~(VT8231_EXTENT - 1);
if (address == 0) {
dev_err(&dev->dev, "base address not set - upgrade BIOS or use force_addr=0xaddr\n");
return -ENODEV;
}
pci_read_config_word(dev, VT8231_ENABLE_REG, &val);
if (val == (u16)~0)
return -ENODEV;
if (!(val & 0x0001)) {
dev_warn(&dev->dev, "enabling sensors\n");
ret = pci_write_config_word(dev, VT8231_ENABLE_REG, val | 0x1);
if (ret != PCIBIOS_SUCCESSFUL)
return -ENODEV;
}
if (platform_driver_register(&vt8231_driver))
goto exit;
/* Sets global pdev as a side effect */
if (vt8231_device_add(address))
goto exit_unregister;
/*
* Always return failure here. This is to allow other drivers to bind
* to this pci device. We don't really want to have control over the
* pci device, we only wanted to read as few register values from it.
*/
/*
* We do, however, mark ourselves as using the PCI device to stop it
* getting unloaded.
*/
s_bridge = pci_dev_get(dev);
return -ENODEV;
exit_unregister:
platform_driver_unregister(&vt8231_driver);
exit:
return -ENODEV;
}
static struct pci_driver vt8231_pci_driver = {
.name = DRIVER_NAME,
.id_table = vt8231_pci_ids,
.probe = vt8231_pci_probe,
};
static int __init sm_vt8231_init(void)
{
return pci_register_driver(&vt8231_pci_driver);
}
static void __exit sm_vt8231_exit(void)
{
pci_unregister_driver(&vt8231_pci_driver);
if (s_bridge != NULL) {
platform_device_unregister(pdev);
platform_driver_unregister(&vt8231_driver);
pci_dev_put(s_bridge);
s_bridge = NULL;
}
}
MODULE_AUTHOR("Roger Lucas <[email protected]>");
MODULE_DESCRIPTION("VT8231 sensors");
MODULE_LICENSE("GPL");
module_init(sm_vt8231_init);
module_exit(sm_vt8231_exit);
|
linux-master
|
drivers/hwmon/vt8231.c
|
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/util_macros.h>
#define REG_CR1 0x00
#define CR1_HYST BIT(5)
#define CR1_DRV GENMASK(4, 3)
#define CR1_TEMP_SRC GENMASK(1, 0)
#define REG_CR2 0x01
#define CR2_STBY BIT(7)
#define CR2_ALERTS BIT(6)
#define CR2_DFC BIT(0)
#define REG_CR3 0x02
#define REG_PWMR 0x50
#define REG_PWMV 0x51
#define REG_STATUS 0x5A
#define STATUS_ALARM_CRIT(ch) BIT(2 + 2 * (ch))
#define STATUS_ALARM_MAX(ch) BIT(3 + 2 * (ch))
#define STATUS_RDFA BIT(6)
#define REG_TACH(ch) (0x52 + (ch) * 2)
#define REG_TEMP_INPUT(ch) (0x56 + (ch) * 2)
#define REG_TEMP_MAX(ch) (0x06 + (ch) * 2)
#define REG_TEMP_CRIT(ch) (0x0A + (ch) * 2)
#define TEMP11_FROM_REG(reg) ((reg) / 32 * 125)
#define TEMP11_TO_REG(val) (DIV_ROUND_CLOSEST(clamp_val((val), -128000, \
127875), 125) * 32)
#define LUT_SIZE 48
#define REG_LUT(index) (0x20 + (index))
struct max31760_state {
struct regmap *regmap;
struct lut_attribute {
char name[24];
struct sensor_device_attribute sda;
} lut[LUT_SIZE];
struct attribute *attrs[LUT_SIZE + 2];
struct attribute_group group;
const struct attribute_group *groups[2];
};
static bool max31760_volatile_reg(struct device *dev, unsigned int reg)
{
return reg > 0x50;
}
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x5B,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = max31760_volatile_reg,
};
static const int max31760_pwm_freq[] = {33, 150, 1500, 25000};
static int tach_to_rpm(u16 tach)
{
if (tach == 0)
tach = 1;
return 60 * 100000 / tach / 2;
}
static int max31760_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct max31760_state *state = dev_get_drvdata(dev);
unsigned int regval;
unsigned int reg_temp;
s16 temp;
u8 reg[2];
int ret;
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_fault:
ret = regmap_read(state->regmap, REG_STATUS, ®val);
if (ret)
return ret;
*val = FIELD_GET(STATUS_RDFA, regval);
return 0;
case hwmon_temp_max_alarm:
ret = regmap_read(state->regmap, REG_STATUS, ®val);
if (ret)
return ret;
if (channel)
*val = FIELD_GET(STATUS_ALARM_MAX(1), regval);
else
*val = FIELD_GET(STATUS_ALARM_MAX(0), regval);
return 0;
case hwmon_temp_crit_alarm:
ret = regmap_read(state->regmap, REG_STATUS, ®val);
if (ret)
return ret;
if (channel)
*val = FIELD_GET(STATUS_ALARM_CRIT(1), regval);
else
*val = FIELD_GET(STATUS_ALARM_CRIT(0), regval);
return 0;
case hwmon_temp_input:
reg_temp = REG_TEMP_INPUT(channel);
break;
case hwmon_temp_max:
reg_temp = REG_TEMP_MAX(channel);
break;
case hwmon_temp_crit:
reg_temp = REG_TEMP_CRIT(channel);
break;
default:
return -EOPNOTSUPP;
}
ret = regmap_bulk_read(state->regmap, reg_temp, reg, 2);
if (ret)
return ret;
temp = (reg[0] << 8) | reg[1];
*val = TEMP11_FROM_REG(temp);
return 0;
case hwmon_fan:
switch (attr) {
case hwmon_fan_input:
ret = regmap_bulk_read(state->regmap, REG_TACH(channel), reg, 2);
if (ret)
return ret;
*val = tach_to_rpm(reg[0] * 256 + reg[1]);
return 0;
case hwmon_fan_fault:
ret = regmap_read(state->regmap, REG_STATUS, ®val);
if (ret)
return ret;
if (channel)
*val = FIELD_GET(BIT(1), regval);
else
*val = FIELD_GET(BIT(0), regval);
return 0;
case hwmon_fan_enable:
ret = regmap_read(state->regmap, REG_CR3, ®val);
if (ret)
return ret;
if (channel)
*val = FIELD_GET(BIT(1), regval);
else
*val = FIELD_GET(BIT(0), regval);
return 0;
default:
return -EOPNOTSUPP;
}
case hwmon_pwm:
switch (attr) {
case hwmon_pwm_input:
ret = regmap_read(state->regmap, REG_PWMV, ®val);
if (ret)
return ret;
*val = regval;
return 0;
case hwmon_pwm_freq:
ret = regmap_read(state->regmap, REG_CR1, ®val);
if (ret)
return ret;
regval = FIELD_GET(CR1_DRV, regval);
if (regval >= ARRAY_SIZE(max31760_pwm_freq))
return -EINVAL;
*val = max31760_pwm_freq[regval];
return 0;
case hwmon_pwm_enable:
ret = regmap_read(state->regmap, REG_CR2, ®val);
if (ret)
return ret;
*val = 2 - FIELD_GET(CR2_DFC, regval);
return 0;
case hwmon_pwm_auto_channels_temp:
ret = regmap_read(state->regmap, REG_CR1, ®val);
if (ret)
return ret;
switch (FIELD_GET(CR1_TEMP_SRC, regval)) {
case 0:
*val = 2;
break;
case 1:
*val = 1;
break;
case 2:
case 3:
*val = 3;
break;
default:
return -EINVAL;
}
return 0;
default:
return -EOPNOTSUPP;
}
default:
return -EOPNOTSUPP;
}
}
static int max31760_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
struct max31760_state *state = dev_get_drvdata(dev);
unsigned int pwm_index;
unsigned int reg_temp;
int temp;
u8 reg_val[2];
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_max:
reg_temp = REG_TEMP_MAX(channel);
break;
case hwmon_temp_crit:
reg_temp = REG_TEMP_CRIT(channel);
break;
default:
return -EOPNOTSUPP;
}
temp = TEMP11_TO_REG(val);
reg_val[0] = temp >> 8;
reg_val[1] = temp & 0xFF;
return regmap_bulk_write(state->regmap, reg_temp, reg_val, 2);
case hwmon_fan:
switch (attr) {
case hwmon_fan_enable:
if (val == 0)
return regmap_clear_bits(state->regmap, REG_CR3, BIT(channel));
if (val == 1)
return regmap_set_bits(state->regmap, REG_CR3, BIT(channel));
return -EINVAL;
default:
return -EOPNOTSUPP;
}
case hwmon_pwm:
switch (attr) {
case hwmon_pwm_input:
if (val < 0 || val > 255)
return -EINVAL;
return regmap_write(state->regmap, REG_PWMR, val);
case hwmon_pwm_enable:
if (val == 1)
return regmap_set_bits(state->regmap, REG_CR2, CR2_DFC);
if (val == 2)
return regmap_clear_bits(state->regmap, REG_CR2, CR2_DFC);
return -EINVAL;
case hwmon_pwm_freq:
pwm_index = find_closest(val, max31760_pwm_freq,
ARRAY_SIZE(max31760_pwm_freq));
return regmap_update_bits(state->regmap,
REG_CR1, CR1_DRV,
FIELD_PREP(CR1_DRV, pwm_index));
case hwmon_pwm_auto_channels_temp:
switch (val) {
case 1:
break;
case 2:
val = 0;
break;
case 3:
val = 2;
break;
default:
return -EINVAL;
}
return regmap_update_bits(state->regmap, REG_CR1, CR1_TEMP_SRC, val);
default:
return -EOPNOTSUPP;
}
default:
return -EOPNOTSUPP;
}
}
static const struct hwmon_channel_info * const max31760_info[] = {
HWMON_CHANNEL_INFO(chip,
HWMON_C_REGISTER_TZ),
HWMON_CHANNEL_INFO(fan,
HWMON_F_INPUT | HWMON_F_FAULT | HWMON_F_ENABLE,
HWMON_F_INPUT | HWMON_F_FAULT | HWMON_F_ENABLE),
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_FAULT |
HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_LABEL),
HWMON_CHANNEL_INFO(pwm,
HWMON_PWM_ENABLE | HWMON_PWM_FREQ | HWMON_PWM_INPUT |
HWMON_PWM_AUTO_CHANNELS_TEMP),
NULL
};
static umode_t max31760_is_visible(const void *data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_input:
case hwmon_temp_max_alarm:
case hwmon_temp_crit_alarm:
case hwmon_temp_fault:
case hwmon_temp_label:
return 0444;
case hwmon_temp_max:
case hwmon_temp_crit:
return 0644;
default:
return 0;
}
case hwmon_fan:
switch (attr) {
case hwmon_fan_input:
case hwmon_fan_fault:
return 0444;
case hwmon_fan_enable:
return 0644;
default:
return 0;
}
case hwmon_pwm:
switch (attr) {
case hwmon_pwm_enable:
case hwmon_pwm_input:
case hwmon_pwm_freq:
case hwmon_pwm_auto_channels_temp:
return 0644;
default:
return 0;
}
default:
return 0;
}
}
static int max31760_read_string(struct device *dev,
enum hwmon_sensor_types type,
u32 attr, int channel, const char **str)
{
switch (type) {
case hwmon_temp:
if (attr != hwmon_temp_label)
return -EOPNOTSUPP;
*str = channel ? "local" : "remote";
return 0;
default:
return -EOPNOTSUPP;
}
}
static const struct hwmon_ops max31760_hwmon_ops = {
.is_visible = max31760_is_visible,
.read = max31760_read,
.write = max31760_write,
.read_string = max31760_read_string
};
static const struct hwmon_chip_info max31760_chip_info = {
.ops = &max31760_hwmon_ops,
.info = max31760_info,
};
static ssize_t lut_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *sda = to_sensor_dev_attr(devattr);
struct max31760_state *state = dev_get_drvdata(dev);
int ret;
unsigned int regval;
ret = regmap_read(state->regmap, REG_LUT(sda->index), ®val);
if (ret)
return ret;
return sysfs_emit(buf, "%d\n", regval);
}
static ssize_t lut_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *sda = to_sensor_dev_attr(devattr);
struct max31760_state *state = dev_get_drvdata(dev);
int ret;
u8 pwm;
ret = kstrtou8(buf, 10, &pwm);
if (ret)
return ret;
ret = regmap_write(state->regmap, REG_LUT(sda->index), pwm);
if (ret)
return ret;
return count;
}
static ssize_t pwm1_auto_point_temp_hyst_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct max31760_state *state = dev_get_drvdata(dev);
unsigned int regval;
int ret;
ret = regmap_read(state->regmap, REG_CR1, ®val);
if (ret)
return ret;
return sysfs_emit(buf, "%d\n", (1 + (int)FIELD_GET(CR1_HYST, regval)) * 2000);
}
static ssize_t pwm1_auto_point_temp_hyst_store(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t count)
{
struct max31760_state *state = dev_get_drvdata(dev);
unsigned int hyst;
int ret;
ret = kstrtou32(buf, 10, &hyst);
if (ret)
return ret;
if (hyst < 3000)
ret = regmap_clear_bits(state->regmap, REG_CR1, CR1_HYST);
else
ret = regmap_set_bits(state->regmap, REG_CR1, CR1_HYST);
if (ret)
return ret;
return count;
}
static DEVICE_ATTR_RW(pwm1_auto_point_temp_hyst);
static void max31760_create_lut_nodes(struct max31760_state *state)
{
int i;
struct sensor_device_attribute *sda;
struct lut_attribute *lut;
for (i = 0; i < LUT_SIZE; ++i) {
lut = &state->lut[i];
sda = &lut->sda;
snprintf(lut->name, sizeof(lut->name),
"pwm1_auto_point%d_pwm", i + 1);
sda->dev_attr.attr.mode = 0644;
sda->index = i;
sda->dev_attr.show = lut_show;
sda->dev_attr.store = lut_store;
sda->dev_attr.attr.name = lut->name;
sysfs_attr_init(&sda->dev_attr.attr);
state->attrs[i] = &sda->dev_attr.attr;
}
state->attrs[i] = &dev_attr_pwm1_auto_point_temp_hyst.attr;
state->group.attrs = state->attrs;
state->groups[0] = &state->group;
}
static int max31760_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct max31760_state *state;
struct device *hwmon_dev;
int ret;
state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
if (!state)
return -ENOMEM;
state->regmap = devm_regmap_init_i2c(client, ®map_config);
if (IS_ERR(state->regmap))
return dev_err_probe(dev,
PTR_ERR(state->regmap),
"regmap initialization failed\n");
dev_set_drvdata(dev, state);
/* Set alert output to comparator mode */
ret = regmap_set_bits(state->regmap, REG_CR2, CR2_ALERTS);
if (ret)
return dev_err_probe(dev, ret, "cannot write register\n");
max31760_create_lut_nodes(state);
hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
state,
&max31760_chip_info,
state->groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct of_device_id max31760_of_match[] = {
{.compatible = "adi,max31760"},
{ }
};
MODULE_DEVICE_TABLE(of, max31760_of_match);
static const struct i2c_device_id max31760_id[] = {
{"max31760"},
{ }
};
MODULE_DEVICE_TABLE(i2c, max31760_id);
static int max31760_suspend(struct device *dev)
{
struct max31760_state *state = dev_get_drvdata(dev);
return regmap_set_bits(state->regmap, REG_CR2, CR2_STBY);
}
static int max31760_resume(struct device *dev)
{
struct max31760_state *state = dev_get_drvdata(dev);
return regmap_clear_bits(state->regmap, REG_CR2, CR2_STBY);
}
static DEFINE_SIMPLE_DEV_PM_OPS(max31760_pm_ops, max31760_suspend,
max31760_resume);
static struct i2c_driver max31760_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "max31760",
.of_match_table = max31760_of_match,
.pm = pm_ptr(&max31760_pm_ops)
},
.probe = max31760_probe,
.id_table = max31760_id
};
module_i2c_driver(max31760_driver);
MODULE_AUTHOR("Ibrahim Tilki <[email protected]>");
MODULE_DESCRIPTION("Analog Devices MAX31760 Fan Speed Controller");
MODULE_SOFTDEP("pre: regmap_i2c");
MODULE_VERSION("1.0");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/max31760.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* asc7621.c - Part of lm_sensors, Linux kernel modules for hardware monitoring
* Copyright (c) 2007, 2010 George Joseph <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
/* Addresses to scan */
static const unsigned short normal_i2c[] = {
0x2c, 0x2d, 0x2e, I2C_CLIENT_END
};
enum asc7621_type {
asc7621,
asc7621a
};
#define INTERVAL_HIGH (HZ + HZ / 2)
#define INTERVAL_LOW (1 * 60 * HZ)
#define PRI_NONE 0
#define PRI_LOW 1
#define PRI_HIGH 2
#define FIRST_CHIP asc7621
#define LAST_CHIP asc7621a
struct asc7621_chip {
char *name;
enum asc7621_type chip_type;
u8 company_reg;
u8 company_id;
u8 verstep_reg;
u8 verstep_id;
const unsigned short *addresses;
};
static struct asc7621_chip asc7621_chips[] = {
{
.name = "asc7621",
.chip_type = asc7621,
.company_reg = 0x3e,
.company_id = 0x61,
.verstep_reg = 0x3f,
.verstep_id = 0x6c,
.addresses = normal_i2c,
},
{
.name = "asc7621a",
.chip_type = asc7621a,
.company_reg = 0x3e,
.company_id = 0x61,
.verstep_reg = 0x3f,
.verstep_id = 0x6d,
.addresses = normal_i2c,
},
};
/*
* Defines the highest register to be used, not the count.
* The actual count will probably be smaller because of gaps
* in the implementation (unused register locations).
* This define will safely set the array size of both the parameter
* and data arrays.
* This comes from the data sheet register description table.
*/
#define LAST_REGISTER 0xff
struct asc7621_data {
struct i2c_client client;
struct device *class_dev;
struct mutex update_lock;
bool valid; /* true if following fields are valid */
unsigned long last_high_reading; /* In jiffies */
unsigned long last_low_reading; /* In jiffies */
/*
* Registers we care about occupy the corresponding index
* in the array. Registers we don't care about are left
* at 0.
*/
u8 reg[LAST_REGISTER + 1];
};
/*
* Macro to get the parent asc7621_param structure
* from a sensor_device_attribute passed into the
* show/store functions.
*/
#define to_asc7621_param(_sda) \
container_of(_sda, struct asc7621_param, sda)
/*
* Each parameter to be retrieved needs an asc7621_param structure
* allocated. It contains the sensor_device_attribute structure
* and the control info needed to retrieve the value from the register map.
*/
struct asc7621_param {
struct sensor_device_attribute sda;
u8 priority;
u8 msb[3];
u8 lsb[3];
u8 mask[3];
u8 shift[3];
};
/*
* This is the map that ultimately indicates whether we'll be
* retrieving a register value or not, and at what frequency.
*/
static u8 asc7621_register_priorities[255];
static struct asc7621_data *asc7621_update_device(struct device *dev);
static inline u8 read_byte(struct i2c_client *client, u8 reg)
{
int res = i2c_smbus_read_byte_data(client, reg);
if (res < 0) {
dev_err(&client->dev,
"Unable to read from register 0x%02x.\n", reg);
return 0;
}
return res & 0xff;
}
static inline int write_byte(struct i2c_client *client, u8 reg, u8 data)
{
int res = i2c_smbus_write_byte_data(client, reg, data);
if (res < 0) {
dev_err(&client->dev,
"Unable to write value 0x%02x to register 0x%02x.\n",
data, reg);
}
return res;
}
/*
* Data Handlers
* Each function handles the formatting, storage
* and retrieval of like parameters.
*/
#define SETUP_SHOW_DATA_PARAM(d, a) \
struct sensor_device_attribute *sda = to_sensor_dev_attr(a); \
struct asc7621_data *data = asc7621_update_device(d); \
struct asc7621_param *param = to_asc7621_param(sda)
#define SETUP_STORE_DATA_PARAM(d, a) \
struct sensor_device_attribute *sda = to_sensor_dev_attr(a); \
struct i2c_client *client = to_i2c_client(d); \
struct asc7621_data *data = i2c_get_clientdata(client); \
struct asc7621_param *param = to_asc7621_param(sda)
/*
* u8 is just what it sounds like...an unsigned byte with no
* special formatting.
*/
static ssize_t show_u8(struct device *dev, struct device_attribute *attr,
char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
return sprintf(buf, "%u\n", data->reg[param->msb[0]]);
}
static ssize_t store_u8(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
long reqval;
if (kstrtol(buf, 10, &reqval))
return -EINVAL;
reqval = clamp_val(reqval, 0, 255);
mutex_lock(&data->update_lock);
data->reg[param->msb[0]] = reqval;
write_byte(client, param->msb[0], reqval);
mutex_unlock(&data->update_lock);
return count;
}
/*
* Many of the config values occupy only a few bits of a register.
*/
static ssize_t show_bitmask(struct device *dev,
struct device_attribute *attr, char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
return sprintf(buf, "%u\n",
(data->reg[param->msb[0]] >> param->
shift[0]) & param->mask[0]);
}
static ssize_t store_bitmask(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
long reqval;
u8 currval;
if (kstrtol(buf, 10, &reqval))
return -EINVAL;
reqval = clamp_val(reqval, 0, param->mask[0]);
reqval = (reqval & param->mask[0]) << param->shift[0];
mutex_lock(&data->update_lock);
currval = read_byte(client, param->msb[0]);
reqval |= (currval & ~(param->mask[0] << param->shift[0]));
data->reg[param->msb[0]] = reqval;
write_byte(client, param->msb[0], reqval);
mutex_unlock(&data->update_lock);
return count;
}
/*
* 16 bit fan rpm values
* reported by the device as the number of 11.111us periods (90khz)
* between full fan rotations. Therefore...
* RPM = (90000 * 60) / register value
*/
static ssize_t show_fan16(struct device *dev,
struct device_attribute *attr, char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
u16 regval;
mutex_lock(&data->update_lock);
regval = (data->reg[param->msb[0]] << 8) | data->reg[param->lsb[0]];
mutex_unlock(&data->update_lock);
return sprintf(buf, "%u\n",
(regval == 0 ? -1 : (regval) ==
0xffff ? 0 : 5400000 / regval));
}
static ssize_t store_fan16(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
long reqval;
if (kstrtol(buf, 10, &reqval))
return -EINVAL;
/*
* If a minimum RPM of zero is requested, then we set the register to
* 0xffff. This value allows the fan to be stopped completely without
* generating an alarm.
*/
reqval =
(reqval <= 0 ? 0xffff : clamp_val(5400000 / reqval, 0, 0xfffe));
mutex_lock(&data->update_lock);
data->reg[param->msb[0]] = (reqval >> 8) & 0xff;
data->reg[param->lsb[0]] = reqval & 0xff;
write_byte(client, param->msb[0], data->reg[param->msb[0]]);
write_byte(client, param->lsb[0], data->reg[param->lsb[0]]);
mutex_unlock(&data->update_lock);
return count;
}
/*
* Voltages are scaled in the device so that the nominal voltage
* is 3/4ths of the 0-255 range (i.e. 192).
* If all voltages are 'normal' then all voltage registers will
* read 0xC0.
*
* The data sheet provides us with the 3/4 scale value for each voltage
* which is stored in in_scaling. The sda->index parameter value provides
* the index into in_scaling.
*
* NOTE: The chip expects the first 2 inputs be 2.5 and 2.25 volts
* respectively. That doesn't mean that's what the motherboard provides. :)
*/
static const int asc7621_in_scaling[] = {
2500, 2250, 3300, 5000, 12000
};
static ssize_t show_in10(struct device *dev, struct device_attribute *attr,
char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
u16 regval;
u8 nr = sda->index;
mutex_lock(&data->update_lock);
regval = (data->reg[param->msb[0]] << 8) | (data->reg[param->lsb[0]]);
mutex_unlock(&data->update_lock);
/* The LSB value is a 2-bit scaling of the MSB's LSbit value. */
regval = (regval >> 6) * asc7621_in_scaling[nr] / (0xc0 << 2);
return sprintf(buf, "%u\n", regval);
}
/* 8 bit voltage values (the mins and maxs) */
static ssize_t show_in8(struct device *dev, struct device_attribute *attr,
char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
u8 nr = sda->index;
return sprintf(buf, "%u\n",
((data->reg[param->msb[0]] *
asc7621_in_scaling[nr]) / 0xc0));
}
static ssize_t store_in8(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
long reqval;
u8 nr = sda->index;
if (kstrtol(buf, 10, &reqval))
return -EINVAL;
reqval = clamp_val(reqval, 0, 0xffff);
reqval = reqval * 0xc0 / asc7621_in_scaling[nr];
reqval = clamp_val(reqval, 0, 0xff);
mutex_lock(&data->update_lock);
data->reg[param->msb[0]] = reqval;
write_byte(client, param->msb[0], reqval);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t show_temp8(struct device *dev,
struct device_attribute *attr, char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
return sprintf(buf, "%d\n", ((s8) data->reg[param->msb[0]]) * 1000);
}
static ssize_t store_temp8(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
long reqval;
s8 temp;
if (kstrtol(buf, 10, &reqval))
return -EINVAL;
reqval = clamp_val(reqval, -127000, 127000);
temp = reqval / 1000;
mutex_lock(&data->update_lock);
data->reg[param->msb[0]] = temp;
write_byte(client, param->msb[0], temp);
mutex_unlock(&data->update_lock);
return count;
}
/*
* Temperatures that occupy 2 bytes always have the whole
* number of degrees in the MSB with some part of the LSB
* indicating fractional degrees.
*/
/* mmmmmmmm.llxxxxxx */
static ssize_t show_temp10(struct device *dev,
struct device_attribute *attr, char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
u8 msb, lsb;
int temp;
mutex_lock(&data->update_lock);
msb = data->reg[param->msb[0]];
lsb = (data->reg[param->lsb[0]] >> 6) & 0x03;
temp = (((s8) msb) * 1000) + (lsb * 250);
mutex_unlock(&data->update_lock);
return sprintf(buf, "%d\n", temp);
}
/* mmmmmm.ll */
static ssize_t show_temp62(struct device *dev,
struct device_attribute *attr, char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
u8 regval = data->reg[param->msb[0]];
int temp = ((s8) (regval & 0xfc) * 1000) + ((regval & 0x03) * 250);
return sprintf(buf, "%d\n", temp);
}
static ssize_t store_temp62(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
long reqval, i, f;
s8 temp;
if (kstrtol(buf, 10, &reqval))
return -EINVAL;
reqval = clamp_val(reqval, -32000, 31750);
i = reqval / 1000;
f = reqval - (i * 1000);
temp = i << 2;
temp |= f / 250;
mutex_lock(&data->update_lock);
data->reg[param->msb[0]] = temp;
write_byte(client, param->msb[0], temp);
mutex_unlock(&data->update_lock);
return count;
}
/*
* The aSC7621 doesn't provide an "auto_point2". Instead, you
* specify the auto_point1 and a range. To keep with the sysfs
* hwmon specs, we synthesize the auto_point_2 from them.
*/
static const u32 asc7621_range_map[] = {
2000, 2500, 3330, 4000, 5000, 6670, 8000, 10000,
13330, 16000, 20000, 26670, 32000, 40000, 53330, 80000,
};
static ssize_t show_ap2_temp(struct device *dev,
struct device_attribute *attr, char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
long auto_point1;
u8 regval;
int temp;
mutex_lock(&data->update_lock);
auto_point1 = ((s8) data->reg[param->msb[1]]) * 1000;
regval =
((data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]);
temp = auto_point1 + asc7621_range_map[clamp_val(regval, 0, 15)];
mutex_unlock(&data->update_lock);
return sprintf(buf, "%d\n", temp);
}
static ssize_t store_ap2_temp(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
long reqval, auto_point1;
int i;
u8 currval, newval = 0;
if (kstrtol(buf, 10, &reqval))
return -EINVAL;
mutex_lock(&data->update_lock);
auto_point1 = data->reg[param->msb[1]] * 1000;
reqval = clamp_val(reqval, auto_point1 + 2000, auto_point1 + 80000);
for (i = ARRAY_SIZE(asc7621_range_map) - 1; i >= 0; i--) {
if (reqval >= auto_point1 + asc7621_range_map[i]) {
newval = i;
break;
}
}
newval = (newval & param->mask[0]) << param->shift[0];
currval = read_byte(client, param->msb[0]);
newval |= (currval & ~(param->mask[0] << param->shift[0]));
data->reg[param->msb[0]] = newval;
write_byte(client, param->msb[0], newval);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t show_pwm_ac(struct device *dev,
struct device_attribute *attr, char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
u8 config, altbit, regval;
static const u8 map[] = {
0x01, 0x02, 0x04, 0x1f, 0x00, 0x06, 0x07, 0x10,
0x08, 0x0f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f
};
mutex_lock(&data->update_lock);
config = (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0];
altbit = (data->reg[param->msb[1]] >> param->shift[1]) & param->mask[1];
regval = config | (altbit << 3);
mutex_unlock(&data->update_lock);
return sprintf(buf, "%u\n", map[clamp_val(regval, 0, 15)]);
}
static ssize_t store_pwm_ac(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
unsigned long reqval;
u8 currval, config, altbit, newval;
static const u16 map[] = {
0x04, 0x00, 0x01, 0xff, 0x02, 0xff, 0x05, 0x06,
0x08, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f,
0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x03,
};
if (kstrtoul(buf, 10, &reqval))
return -EINVAL;
if (reqval > 31)
return -EINVAL;
reqval = map[reqval];
if (reqval == 0xff)
return -EINVAL;
config = reqval & 0x07;
altbit = (reqval >> 3) & 0x01;
config = (config & param->mask[0]) << param->shift[0];
altbit = (altbit & param->mask[1]) << param->shift[1];
mutex_lock(&data->update_lock);
currval = read_byte(client, param->msb[0]);
newval = config | (currval & ~(param->mask[0] << param->shift[0]));
newval = altbit | (newval & ~(param->mask[1] << param->shift[1]));
data->reg[param->msb[0]] = newval;
write_byte(client, param->msb[0], newval);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t show_pwm_enable(struct device *dev,
struct device_attribute *attr, char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
u8 config, altbit, minoff, val, newval;
mutex_lock(&data->update_lock);
config = (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0];
altbit = (data->reg[param->msb[1]] >> param->shift[1]) & param->mask[1];
minoff = (data->reg[param->msb[2]] >> param->shift[2]) & param->mask[2];
mutex_unlock(&data->update_lock);
val = config | (altbit << 3);
if (val == 3 || val >= 10)
newval = 255;
else if (val == 4)
newval = 0;
else if (val == 7)
newval = 1;
else if (minoff == 1)
newval = 2;
else
newval = 3;
return sprintf(buf, "%u\n", newval);
}
static ssize_t store_pwm_enable(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
long reqval;
u8 currval, config, altbit, newval, minoff = 255;
if (kstrtol(buf, 10, &reqval))
return -EINVAL;
switch (reqval) {
case 0:
newval = 0x04;
break;
case 1:
newval = 0x07;
break;
case 2:
newval = 0x00;
minoff = 1;
break;
case 3:
newval = 0x00;
minoff = 0;
break;
case 255:
newval = 0x03;
break;
default:
return -EINVAL;
}
config = newval & 0x07;
altbit = (newval >> 3) & 0x01;
mutex_lock(&data->update_lock);
config = (config & param->mask[0]) << param->shift[0];
altbit = (altbit & param->mask[1]) << param->shift[1];
currval = read_byte(client, param->msb[0]);
newval = config | (currval & ~(param->mask[0] << param->shift[0]));
newval = altbit | (newval & ~(param->mask[1] << param->shift[1]));
data->reg[param->msb[0]] = newval;
write_byte(client, param->msb[0], newval);
if (minoff < 255) {
minoff = (minoff & param->mask[2]) << param->shift[2];
currval = read_byte(client, param->msb[2]);
newval =
minoff | (currval & ~(param->mask[2] << param->shift[2]));
data->reg[param->msb[2]] = newval;
write_byte(client, param->msb[2], newval);
}
mutex_unlock(&data->update_lock);
return count;
}
static const u32 asc7621_pwm_freq_map[] = {
10, 15, 23, 30, 38, 47, 62, 94,
23000, 24000, 25000, 26000, 27000, 28000, 29000, 30000
};
static ssize_t show_pwm_freq(struct device *dev,
struct device_attribute *attr, char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
u8 regval =
(data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0];
regval = clamp_val(regval, 0, 15);
return sprintf(buf, "%u\n", asc7621_pwm_freq_map[regval]);
}
static ssize_t store_pwm_freq(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
unsigned long reqval;
u8 currval, newval = 255;
int i;
if (kstrtoul(buf, 10, &reqval))
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(asc7621_pwm_freq_map); i++) {
if (reqval == asc7621_pwm_freq_map[i]) {
newval = i;
break;
}
}
if (newval == 255)
return -EINVAL;
newval = (newval & param->mask[0]) << param->shift[0];
mutex_lock(&data->update_lock);
currval = read_byte(client, param->msb[0]);
newval |= (currval & ~(param->mask[0] << param->shift[0]));
data->reg[param->msb[0]] = newval;
write_byte(client, param->msb[0], newval);
mutex_unlock(&data->update_lock);
return count;
}
static const u32 asc7621_pwm_auto_spinup_map[] = {
0, 100, 250, 400, 700, 1000, 2000, 4000
};
static ssize_t show_pwm_ast(struct device *dev,
struct device_attribute *attr, char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
u8 regval =
(data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0];
regval = clamp_val(regval, 0, 7);
return sprintf(buf, "%u\n", asc7621_pwm_auto_spinup_map[regval]);
}
static ssize_t store_pwm_ast(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
long reqval;
u8 currval, newval = 255;
u32 i;
if (kstrtol(buf, 10, &reqval))
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(asc7621_pwm_auto_spinup_map); i++) {
if (reqval == asc7621_pwm_auto_spinup_map[i]) {
newval = i;
break;
}
}
if (newval == 255)
return -EINVAL;
newval = (newval & param->mask[0]) << param->shift[0];
mutex_lock(&data->update_lock);
currval = read_byte(client, param->msb[0]);
newval |= (currval & ~(param->mask[0] << param->shift[0]));
data->reg[param->msb[0]] = newval;
write_byte(client, param->msb[0], newval);
mutex_unlock(&data->update_lock);
return count;
}
static const u32 asc7621_temp_smoothing_time_map[] = {
35000, 17600, 11800, 7000, 4400, 3000, 1600, 800
};
static ssize_t show_temp_st(struct device *dev,
struct device_attribute *attr, char *buf)
{
SETUP_SHOW_DATA_PARAM(dev, attr);
u8 regval =
(data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0];
regval = clamp_val(regval, 0, 7);
return sprintf(buf, "%u\n", asc7621_temp_smoothing_time_map[regval]);
}
static ssize_t store_temp_st(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
SETUP_STORE_DATA_PARAM(dev, attr);
long reqval;
u8 currval, newval = 255;
u32 i;
if (kstrtol(buf, 10, &reqval))
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(asc7621_temp_smoothing_time_map); i++) {
if (reqval == asc7621_temp_smoothing_time_map[i]) {
newval = i;
break;
}
}
if (newval == 255)
return -EINVAL;
newval = (newval & param->mask[0]) << param->shift[0];
mutex_lock(&data->update_lock);
currval = read_byte(client, param->msb[0]);
newval |= (currval & ~(param->mask[0] << param->shift[0]));
data->reg[param->msb[0]] = newval;
write_byte(client, param->msb[0], newval);
mutex_unlock(&data->update_lock);
return count;
}
/*
* End of data handlers
*
* These defines do nothing more than make the table easier
* to read when wrapped at column 80.
*/
/*
* Creates a variable length array inititalizer.
* VAA(1,3,5,7) would produce {1,3,5,7}
*/
#define VAA(args...) {args}
#define PREAD(name, n, pri, rm, rl, m, s, r) \
{.sda = SENSOR_ATTR(name, S_IRUGO, show_##r, NULL, n), \
.priority = pri, .msb[0] = rm, .lsb[0] = rl, .mask[0] = m, \
.shift[0] = s,}
#define PWRITE(name, n, pri, rm, rl, m, s, r) \
{.sda = SENSOR_ATTR(name, S_IRUGO | S_IWUSR, show_##r, store_##r, n), \
.priority = pri, .msb[0] = rm, .lsb[0] = rl, .mask[0] = m, \
.shift[0] = s,}
/*
* PWRITEM assumes that the initializers for the .msb, .lsb, .mask and .shift
* were created using the VAA macro.
*/
#define PWRITEM(name, n, pri, rm, rl, m, s, r) \
{.sda = SENSOR_ATTR(name, S_IRUGO | S_IWUSR, show_##r, store_##r, n), \
.priority = pri, .msb = rm, .lsb = rl, .mask = m, .shift = s,}
static struct asc7621_param asc7621_params[] = {
PREAD(in0_input, 0, PRI_HIGH, 0x20, 0x13, 0, 0, in10),
PREAD(in1_input, 1, PRI_HIGH, 0x21, 0x18, 0, 0, in10),
PREAD(in2_input, 2, PRI_HIGH, 0x22, 0x11, 0, 0, in10),
PREAD(in3_input, 3, PRI_HIGH, 0x23, 0x12, 0, 0, in10),
PREAD(in4_input, 4, PRI_HIGH, 0x24, 0x14, 0, 0, in10),
PWRITE(in0_min, 0, PRI_LOW, 0x44, 0, 0, 0, in8),
PWRITE(in1_min, 1, PRI_LOW, 0x46, 0, 0, 0, in8),
PWRITE(in2_min, 2, PRI_LOW, 0x48, 0, 0, 0, in8),
PWRITE(in3_min, 3, PRI_LOW, 0x4a, 0, 0, 0, in8),
PWRITE(in4_min, 4, PRI_LOW, 0x4c, 0, 0, 0, in8),
PWRITE(in0_max, 0, PRI_LOW, 0x45, 0, 0, 0, in8),
PWRITE(in1_max, 1, PRI_LOW, 0x47, 0, 0, 0, in8),
PWRITE(in2_max, 2, PRI_LOW, 0x49, 0, 0, 0, in8),
PWRITE(in3_max, 3, PRI_LOW, 0x4b, 0, 0, 0, in8),
PWRITE(in4_max, 4, PRI_LOW, 0x4d, 0, 0, 0, in8),
PREAD(in0_alarm, 0, PRI_HIGH, 0x41, 0, 0x01, 0, bitmask),
PREAD(in1_alarm, 1, PRI_HIGH, 0x41, 0, 0x01, 1, bitmask),
PREAD(in2_alarm, 2, PRI_HIGH, 0x41, 0, 0x01, 2, bitmask),
PREAD(in3_alarm, 3, PRI_HIGH, 0x41, 0, 0x01, 3, bitmask),
PREAD(in4_alarm, 4, PRI_HIGH, 0x42, 0, 0x01, 0, bitmask),
PREAD(fan1_input, 0, PRI_HIGH, 0x29, 0x28, 0, 0, fan16),
PREAD(fan2_input, 1, PRI_HIGH, 0x2b, 0x2a, 0, 0, fan16),
PREAD(fan3_input, 2, PRI_HIGH, 0x2d, 0x2c, 0, 0, fan16),
PREAD(fan4_input, 3, PRI_HIGH, 0x2f, 0x2e, 0, 0, fan16),
PWRITE(fan1_min, 0, PRI_LOW, 0x55, 0x54, 0, 0, fan16),
PWRITE(fan2_min, 1, PRI_LOW, 0x57, 0x56, 0, 0, fan16),
PWRITE(fan3_min, 2, PRI_LOW, 0x59, 0x58, 0, 0, fan16),
PWRITE(fan4_min, 3, PRI_LOW, 0x5b, 0x5a, 0, 0, fan16),
PREAD(fan1_alarm, 0, PRI_HIGH, 0x42, 0, 0x01, 2, bitmask),
PREAD(fan2_alarm, 1, PRI_HIGH, 0x42, 0, 0x01, 3, bitmask),
PREAD(fan3_alarm, 2, PRI_HIGH, 0x42, 0, 0x01, 4, bitmask),
PREAD(fan4_alarm, 3, PRI_HIGH, 0x42, 0, 0x01, 5, bitmask),
PREAD(temp1_input, 0, PRI_HIGH, 0x25, 0x10, 0, 0, temp10),
PREAD(temp2_input, 1, PRI_HIGH, 0x26, 0x15, 0, 0, temp10),
PREAD(temp3_input, 2, PRI_HIGH, 0x27, 0x16, 0, 0, temp10),
PREAD(temp4_input, 3, PRI_HIGH, 0x33, 0x17, 0, 0, temp10),
PREAD(temp5_input, 4, PRI_HIGH, 0xf7, 0xf6, 0, 0, temp10),
PREAD(temp6_input, 5, PRI_HIGH, 0xf9, 0xf8, 0, 0, temp10),
PREAD(temp7_input, 6, PRI_HIGH, 0xfb, 0xfa, 0, 0, temp10),
PREAD(temp8_input, 7, PRI_HIGH, 0xfd, 0xfc, 0, 0, temp10),
PWRITE(temp1_min, 0, PRI_LOW, 0x4e, 0, 0, 0, temp8),
PWRITE(temp2_min, 1, PRI_LOW, 0x50, 0, 0, 0, temp8),
PWRITE(temp3_min, 2, PRI_LOW, 0x52, 0, 0, 0, temp8),
PWRITE(temp4_min, 3, PRI_LOW, 0x34, 0, 0, 0, temp8),
PWRITE(temp1_max, 0, PRI_LOW, 0x4f, 0, 0, 0, temp8),
PWRITE(temp2_max, 1, PRI_LOW, 0x51, 0, 0, 0, temp8),
PWRITE(temp3_max, 2, PRI_LOW, 0x53, 0, 0, 0, temp8),
PWRITE(temp4_max, 3, PRI_LOW, 0x35, 0, 0, 0, temp8),
PREAD(temp1_alarm, 0, PRI_HIGH, 0x41, 0, 0x01, 4, bitmask),
PREAD(temp2_alarm, 1, PRI_HIGH, 0x41, 0, 0x01, 5, bitmask),
PREAD(temp3_alarm, 2, PRI_HIGH, 0x41, 0, 0x01, 6, bitmask),
PREAD(temp4_alarm, 3, PRI_HIGH, 0x43, 0, 0x01, 0, bitmask),
PWRITE(temp1_source, 0, PRI_LOW, 0x02, 0, 0x07, 4, bitmask),
PWRITE(temp2_source, 1, PRI_LOW, 0x02, 0, 0x07, 0, bitmask),
PWRITE(temp3_source, 2, PRI_LOW, 0x03, 0, 0x07, 4, bitmask),
PWRITE(temp4_source, 3, PRI_LOW, 0x03, 0, 0x07, 0, bitmask),
PWRITE(temp1_smoothing_enable, 0, PRI_LOW, 0x62, 0, 0x01, 3, bitmask),
PWRITE(temp2_smoothing_enable, 1, PRI_LOW, 0x63, 0, 0x01, 7, bitmask),
PWRITE(temp3_smoothing_enable, 2, PRI_LOW, 0x63, 0, 0x01, 3, bitmask),
PWRITE(temp4_smoothing_enable, 3, PRI_LOW, 0x3c, 0, 0x01, 3, bitmask),
PWRITE(temp1_smoothing_time, 0, PRI_LOW, 0x62, 0, 0x07, 0, temp_st),
PWRITE(temp2_smoothing_time, 1, PRI_LOW, 0x63, 0, 0x07, 4, temp_st),
PWRITE(temp3_smoothing_time, 2, PRI_LOW, 0x63, 0, 0x07, 0, temp_st),
PWRITE(temp4_smoothing_time, 3, PRI_LOW, 0x3c, 0, 0x07, 0, temp_st),
PWRITE(temp1_auto_point1_temp_hyst, 0, PRI_LOW, 0x6d, 0, 0x0f, 4,
bitmask),
PWRITE(temp2_auto_point1_temp_hyst, 1, PRI_LOW, 0x6d, 0, 0x0f, 0,
bitmask),
PWRITE(temp3_auto_point1_temp_hyst, 2, PRI_LOW, 0x6e, 0, 0x0f, 4,
bitmask),
PWRITE(temp4_auto_point1_temp_hyst, 3, PRI_LOW, 0x6e, 0, 0x0f, 0,
bitmask),
PREAD(temp1_auto_point2_temp_hyst, 0, PRI_LOW, 0x6d, 0, 0x0f, 4,
bitmask),
PREAD(temp2_auto_point2_temp_hyst, 1, PRI_LOW, 0x6d, 0, 0x0f, 0,
bitmask),
PREAD(temp3_auto_point2_temp_hyst, 2, PRI_LOW, 0x6e, 0, 0x0f, 4,
bitmask),
PREAD(temp4_auto_point2_temp_hyst, 3, PRI_LOW, 0x6e, 0, 0x0f, 0,
bitmask),
PWRITE(temp1_auto_point1_temp, 0, PRI_LOW, 0x67, 0, 0, 0, temp8),
PWRITE(temp2_auto_point1_temp, 1, PRI_LOW, 0x68, 0, 0, 0, temp8),
PWRITE(temp3_auto_point1_temp, 2, PRI_LOW, 0x69, 0, 0, 0, temp8),
PWRITE(temp4_auto_point1_temp, 3, PRI_LOW, 0x3b, 0, 0, 0, temp8),
PWRITEM(temp1_auto_point2_temp, 0, PRI_LOW, VAA(0x5f, 0x67), VAA(0),
VAA(0x0f), VAA(4), ap2_temp),
PWRITEM(temp2_auto_point2_temp, 1, PRI_LOW, VAA(0x60, 0x68), VAA(0),
VAA(0x0f), VAA(4), ap2_temp),
PWRITEM(temp3_auto_point2_temp, 2, PRI_LOW, VAA(0x61, 0x69), VAA(0),
VAA(0x0f), VAA(4), ap2_temp),
PWRITEM(temp4_auto_point2_temp, 3, PRI_LOW, VAA(0x3c, 0x3b), VAA(0),
VAA(0x0f), VAA(4), ap2_temp),
PWRITE(temp1_crit, 0, PRI_LOW, 0x6a, 0, 0, 0, temp8),
PWRITE(temp2_crit, 1, PRI_LOW, 0x6b, 0, 0, 0, temp8),
PWRITE(temp3_crit, 2, PRI_LOW, 0x6c, 0, 0, 0, temp8),
PWRITE(temp4_crit, 3, PRI_LOW, 0x3d, 0, 0, 0, temp8),
PWRITE(temp5_enable, 4, PRI_LOW, 0x0e, 0, 0x01, 0, bitmask),
PWRITE(temp6_enable, 5, PRI_LOW, 0x0e, 0, 0x01, 1, bitmask),
PWRITE(temp7_enable, 6, PRI_LOW, 0x0e, 0, 0x01, 2, bitmask),
PWRITE(temp8_enable, 7, PRI_LOW, 0x0e, 0, 0x01, 3, bitmask),
PWRITE(remote1_offset, 0, PRI_LOW, 0x1c, 0, 0, 0, temp62),
PWRITE(remote2_offset, 1, PRI_LOW, 0x1d, 0, 0, 0, temp62),
PWRITE(pwm1, 0, PRI_HIGH, 0x30, 0, 0, 0, u8),
PWRITE(pwm2, 1, PRI_HIGH, 0x31, 0, 0, 0, u8),
PWRITE(pwm3, 2, PRI_HIGH, 0x32, 0, 0, 0, u8),
PWRITE(pwm1_invert, 0, PRI_LOW, 0x5c, 0, 0x01, 4, bitmask),
PWRITE(pwm2_invert, 1, PRI_LOW, 0x5d, 0, 0x01, 4, bitmask),
PWRITE(pwm3_invert, 2, PRI_LOW, 0x5e, 0, 0x01, 4, bitmask),
PWRITEM(pwm1_enable, 0, PRI_LOW, VAA(0x5c, 0x5c, 0x62), VAA(0, 0, 0),
VAA(0x07, 0x01, 0x01), VAA(5, 3, 5), pwm_enable),
PWRITEM(pwm2_enable, 1, PRI_LOW, VAA(0x5d, 0x5d, 0x62), VAA(0, 0, 0),
VAA(0x07, 0x01, 0x01), VAA(5, 3, 6), pwm_enable),
PWRITEM(pwm3_enable, 2, PRI_LOW, VAA(0x5e, 0x5e, 0x62), VAA(0, 0, 0),
VAA(0x07, 0x01, 0x01), VAA(5, 3, 7), pwm_enable),
PWRITEM(pwm1_auto_channels, 0, PRI_LOW, VAA(0x5c, 0x5c), VAA(0, 0),
VAA(0x07, 0x01), VAA(5, 3), pwm_ac),
PWRITEM(pwm2_auto_channels, 1, PRI_LOW, VAA(0x5d, 0x5d), VAA(0, 0),
VAA(0x07, 0x01), VAA(5, 3), pwm_ac),
PWRITEM(pwm3_auto_channels, 2, PRI_LOW, VAA(0x5e, 0x5e), VAA(0, 0),
VAA(0x07, 0x01), VAA(5, 3), pwm_ac),
PWRITE(pwm1_auto_point1_pwm, 0, PRI_LOW, 0x64, 0, 0, 0, u8),
PWRITE(pwm2_auto_point1_pwm, 1, PRI_LOW, 0x65, 0, 0, 0, u8),
PWRITE(pwm3_auto_point1_pwm, 2, PRI_LOW, 0x66, 0, 0, 0, u8),
PWRITE(pwm1_auto_point2_pwm, 0, PRI_LOW, 0x38, 0, 0, 0, u8),
PWRITE(pwm2_auto_point2_pwm, 1, PRI_LOW, 0x39, 0, 0, 0, u8),
PWRITE(pwm3_auto_point2_pwm, 2, PRI_LOW, 0x3a, 0, 0, 0, u8),
PWRITE(pwm1_freq, 0, PRI_LOW, 0x5f, 0, 0x0f, 0, pwm_freq),
PWRITE(pwm2_freq, 1, PRI_LOW, 0x60, 0, 0x0f, 0, pwm_freq),
PWRITE(pwm3_freq, 2, PRI_LOW, 0x61, 0, 0x0f, 0, pwm_freq),
PREAD(pwm1_auto_zone_assigned, 0, PRI_LOW, 0, 0, 0x03, 2, bitmask),
PREAD(pwm2_auto_zone_assigned, 1, PRI_LOW, 0, 0, 0x03, 4, bitmask),
PREAD(pwm3_auto_zone_assigned, 2, PRI_LOW, 0, 0, 0x03, 6, bitmask),
PWRITE(pwm1_auto_spinup_time, 0, PRI_LOW, 0x5c, 0, 0x07, 0, pwm_ast),
PWRITE(pwm2_auto_spinup_time, 1, PRI_LOW, 0x5d, 0, 0x07, 0, pwm_ast),
PWRITE(pwm3_auto_spinup_time, 2, PRI_LOW, 0x5e, 0, 0x07, 0, pwm_ast),
PWRITE(peci_enable, 0, PRI_LOW, 0x40, 0, 0x01, 4, bitmask),
PWRITE(peci_avg, 0, PRI_LOW, 0x36, 0, 0x07, 0, bitmask),
PWRITE(peci_domain, 0, PRI_LOW, 0x36, 0, 0x01, 3, bitmask),
PWRITE(peci_legacy, 0, PRI_LOW, 0x36, 0, 0x01, 4, bitmask),
PWRITE(peci_diode, 0, PRI_LOW, 0x0e, 0, 0x07, 4, bitmask),
PWRITE(peci_4domain, 0, PRI_LOW, 0x0e, 0, 0x01, 4, bitmask),
};
static struct asc7621_data *asc7621_update_device(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct asc7621_data *data = i2c_get_clientdata(client);
int i;
/*
* The asc7621 chips guarantee consistent reads of multi-byte values
* regardless of the order of the reads. No special logic is needed
* so we can just read the registers in whatever order they appear
* in the asc7621_params array.
*/
mutex_lock(&data->update_lock);
/* Read all the high priority registers */
if (!data->valid ||
time_after(jiffies, data->last_high_reading + INTERVAL_HIGH)) {
for (i = 0; i < ARRAY_SIZE(asc7621_register_priorities); i++) {
if (asc7621_register_priorities[i] == PRI_HIGH) {
data->reg[i] =
i2c_smbus_read_byte_data(client, i) & 0xff;
}
}
data->last_high_reading = jiffies;
} /* last_reading */
/* Read all the low priority registers. */
if (!data->valid ||
time_after(jiffies, data->last_low_reading + INTERVAL_LOW)) {
for (i = 0; i < ARRAY_SIZE(asc7621_params); i++) {
if (asc7621_register_priorities[i] == PRI_LOW) {
data->reg[i] =
i2c_smbus_read_byte_data(client, i) & 0xff;
}
}
data->last_low_reading = jiffies;
} /* last_reading */
data->valid = true;
mutex_unlock(&data->update_lock);
return data;
}
/*
* Standard detection and initialization below
*
* Helper function that checks if an address is valid
* for a particular chip.
*/
static inline int valid_address_for_chip(int chip_type, int address)
{
int i;
for (i = 0; asc7621_chips[chip_type].addresses[i] != I2C_CLIENT_END;
i++) {
if (asc7621_chips[chip_type].addresses[i] == address)
return 1;
}
return 0;
}
static void asc7621_init_client(struct i2c_client *client)
{
int value;
/* Warn if part was not "READY" */
value = read_byte(client, 0x40);
if (value & 0x02) {
dev_err(&client->dev,
"Client (%d,0x%02x) config is locked.\n",
i2c_adapter_id(client->adapter), client->addr);
}
if (!(value & 0x04)) {
dev_err(&client->dev, "Client (%d,0x%02x) is not ready.\n",
i2c_adapter_id(client->adapter), client->addr);
}
/*
* Start monitoring
*
* Try to clear LOCK, Set START, save everything else
*/
value = (value & ~0x02) | 0x01;
write_byte(client, 0x40, value & 0xff);
}
static int
asc7621_probe(struct i2c_client *client)
{
struct asc7621_data *data;
int i, err;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -EIO;
data = devm_kzalloc(&client->dev, sizeof(struct asc7621_data),
GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
i2c_set_clientdata(client, data);
mutex_init(&data->update_lock);
/* Initialize the asc7621 chip */
asc7621_init_client(client);
/* Create the sysfs entries */
for (i = 0; i < ARRAY_SIZE(asc7621_params); i++) {
err =
device_create_file(&client->dev,
&(asc7621_params[i].sda.dev_attr));
if (err)
goto exit_remove;
}
data->class_dev = hwmon_device_register(&client->dev);
if (IS_ERR(data->class_dev)) {
err = PTR_ERR(data->class_dev);
goto exit_remove;
}
return 0;
exit_remove:
for (i = 0; i < ARRAY_SIZE(asc7621_params); i++) {
device_remove_file(&client->dev,
&(asc7621_params[i].sda.dev_attr));
}
return err;
}
static int asc7621_detect(struct i2c_client *client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
int company, verstep, chip_index;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
for (chip_index = FIRST_CHIP; chip_index <= LAST_CHIP; chip_index++) {
if (!valid_address_for_chip(chip_index, client->addr))
continue;
company = read_byte(client,
asc7621_chips[chip_index].company_reg);
verstep = read_byte(client,
asc7621_chips[chip_index].verstep_reg);
if (company == asc7621_chips[chip_index].company_id &&
verstep == asc7621_chips[chip_index].verstep_id) {
strscpy(info->type, asc7621_chips[chip_index].name,
I2C_NAME_SIZE);
dev_info(&adapter->dev, "Matched %s at 0x%02x\n",
asc7621_chips[chip_index].name, client->addr);
return 0;
}
}
return -ENODEV;
}
static void asc7621_remove(struct i2c_client *client)
{
struct asc7621_data *data = i2c_get_clientdata(client);
int i;
hwmon_device_unregister(data->class_dev);
for (i = 0; i < ARRAY_SIZE(asc7621_params); i++) {
device_remove_file(&client->dev,
&(asc7621_params[i].sda.dev_attr));
}
}
static const struct i2c_device_id asc7621_id[] = {
{"asc7621", asc7621},
{"asc7621a", asc7621a},
{},
};
MODULE_DEVICE_TABLE(i2c, asc7621_id);
static struct i2c_driver asc7621_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "asc7621",
},
.probe = asc7621_probe,
.remove = asc7621_remove,
.id_table = asc7621_id,
.detect = asc7621_detect,
.address_list = normal_i2c,
};
static int __init sm_asc7621_init(void)
{
int i, j;
/*
* Collect all the registers needed into a single array.
* This way, if a register isn't actually used for anything,
* we don't retrieve it.
*/
for (i = 0; i < ARRAY_SIZE(asc7621_params); i++) {
for (j = 0; j < ARRAY_SIZE(asc7621_params[i].msb); j++)
asc7621_register_priorities[asc7621_params[i].msb[j]] =
asc7621_params[i].priority;
for (j = 0; j < ARRAY_SIZE(asc7621_params[i].lsb); j++)
asc7621_register_priorities[asc7621_params[i].lsb[j]] =
asc7621_params[i].priority;
}
return i2c_add_driver(&asc7621_driver);
}
static void __exit sm_asc7621_exit(void)
{
i2c_del_driver(&asc7621_driver);
}
MODULE_LICENSE("GPL");
MODULE_AUTHOR("George Joseph");
MODULE_DESCRIPTION("Andigilog aSC7621 and aSC7621a driver");
module_init(sm_asc7621_init);
module_exit(sm_asc7621_exit);
|
linux-master
|
drivers/hwmon/asc7621.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* k8temp.c - Linux kernel module for hardware monitoring
*
* Copyright (C) 2006 Rudolf Marek <[email protected]>
*
* Inspired from the w83785 and amd756 drivers.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/hwmon.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <asm/processor.h>
#define TEMP_FROM_REG(val) (((((val) >> 16) & 0xff) - 49) * 1000)
#define REG_TEMP 0xe4
#define SEL_PLACE 0x40
#define SEL_CORE 0x04
struct k8temp_data {
struct mutex update_lock;
/* registers values */
u8 sensorsp; /* sensor presence bits - SEL_CORE, SEL_PLACE */
u8 swap_core_select; /* meaning of SEL_CORE is inverted */
u32 temp_offset;
};
static const struct pci_device_id k8temp_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
{ 0 },
};
MODULE_DEVICE_TABLE(pci, k8temp_ids);
static int is_rev_g_desktop(u8 model)
{
u32 brandidx;
if (model < 0x69)
return 0;
if (model == 0xc1 || model == 0x6c || model == 0x7c)
return 0;
/*
* Differentiate between AM2 and ASB1.
* See "Constructing the processor Name String" in "Revision
* Guide for AMD NPT Family 0Fh Processors" (33610).
*/
brandidx = cpuid_ebx(0x80000001);
brandidx = (brandidx >> 9) & 0x1f;
/* Single core */
if ((model == 0x6f || model == 0x7f) &&
(brandidx == 0x7 || brandidx == 0x9 || brandidx == 0xc))
return 0;
/* Dual core */
if (model == 0x6b &&
(brandidx == 0xb || brandidx == 0xc))
return 0;
return 1;
}
static umode_t
k8temp_is_visible(const void *drvdata, enum hwmon_sensor_types type,
u32 attr, int channel)
{
const struct k8temp_data *data = drvdata;
if ((channel & 1) && !(data->sensorsp & SEL_PLACE))
return 0;
if ((channel & 2) && !(data->sensorsp & SEL_CORE))
return 0;
return 0444;
}
static int
k8temp_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct k8temp_data *data = dev_get_drvdata(dev);
struct pci_dev *pdev = to_pci_dev(dev->parent);
int core, place;
u32 temp;
u8 tmp;
core = (channel >> 1) & 1;
place = channel & 1;
core ^= data->swap_core_select;
mutex_lock(&data->update_lock);
pci_read_config_byte(pdev, REG_TEMP, &tmp);
tmp &= ~(SEL_PLACE | SEL_CORE);
if (core)
tmp |= SEL_CORE;
if (place)
tmp |= SEL_PLACE;
pci_write_config_byte(pdev, REG_TEMP, tmp);
pci_read_config_dword(pdev, REG_TEMP, &temp);
mutex_unlock(&data->update_lock);
*val = TEMP_FROM_REG(temp) + data->temp_offset;
return 0;
}
static const struct hwmon_ops k8temp_ops = {
.is_visible = k8temp_is_visible,
.read = k8temp_read,
};
static const struct hwmon_channel_info * const k8temp_info[] = {
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT, HWMON_T_INPUT, HWMON_T_INPUT, HWMON_T_INPUT),
NULL
};
static const struct hwmon_chip_info k8temp_chip_info = {
.ops = &k8temp_ops,
.info = k8temp_info,
};
static int k8temp_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
u8 scfg;
u32 temp;
u8 model, stepping;
struct k8temp_data *data;
struct device *hwmon_dev;
data = devm_kzalloc(&pdev->dev, sizeof(struct k8temp_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
model = boot_cpu_data.x86_model;
stepping = boot_cpu_data.x86_stepping;
/* feature available since SH-C0, exclude older revisions */
if ((model == 4 && stepping == 0) ||
(model == 5 && stepping <= 1))
return -ENODEV;
/*
* AMD NPT family 0fh, i.e. RevF and RevG:
* meaning of SEL_CORE bit is inverted
*/
if (model >= 0x40) {
data->swap_core_select = 1;
dev_warn(&pdev->dev,
"Temperature readouts might be wrong - check erratum #141\n");
}
/*
* RevG desktop CPUs (i.e. no socket S1G1 or ASB1 parts) need
* additional offset, otherwise reported temperature is below
* ambient temperature
*/
if (is_rev_g_desktop(model))
data->temp_offset = 21000;
pci_read_config_byte(pdev, REG_TEMP, &scfg);
scfg &= ~(SEL_PLACE | SEL_CORE); /* Select sensor 0, core0 */
pci_write_config_byte(pdev, REG_TEMP, scfg);
pci_read_config_byte(pdev, REG_TEMP, &scfg);
if (scfg & (SEL_PLACE | SEL_CORE)) {
dev_err(&pdev->dev, "Configuration bit(s) stuck at 1!\n");
return -ENODEV;
}
scfg |= (SEL_PLACE | SEL_CORE);
pci_write_config_byte(pdev, REG_TEMP, scfg);
/* now we know if we can change core and/or sensor */
pci_read_config_byte(pdev, REG_TEMP, &data->sensorsp);
if (data->sensorsp & SEL_PLACE) {
scfg &= ~SEL_CORE; /* Select sensor 1, core0 */
pci_write_config_byte(pdev, REG_TEMP, scfg);
pci_read_config_dword(pdev, REG_TEMP, &temp);
scfg |= SEL_CORE; /* prepare for next selection */
if (!((temp >> 16) & 0xff)) /* if temp is 0 -49C is unlikely */
data->sensorsp &= ~SEL_PLACE;
}
if (data->sensorsp & SEL_CORE) {
scfg &= ~SEL_PLACE; /* Select sensor 0, core1 */
pci_write_config_byte(pdev, REG_TEMP, scfg);
pci_read_config_dword(pdev, REG_TEMP, &temp);
if (!((temp >> 16) & 0xff)) /* if temp is 0 -49C is unlikely */
data->sensorsp &= ~SEL_CORE;
}
mutex_init(&data->update_lock);
hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
"k8temp",
data,
&k8temp_chip_info,
NULL);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static struct pci_driver k8temp_driver = {
.name = "k8temp",
.id_table = k8temp_ids,
.probe = k8temp_probe,
};
module_pci_driver(k8temp_driver);
MODULE_AUTHOR("Rudolf Marek <[email protected]>");
MODULE_DESCRIPTION("AMD K8 core temperature monitor");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/k8temp.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Ampere Computing SoC's SMPro Hardware Monitoring Driver
*
* Copyright (c) 2022, Ampere Computing LLC
*/
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
/* Logical Power Sensor Registers */
#define SOC_TEMP 0x10
#define SOC_VRD_TEMP 0x11
#define DIMM_VRD_TEMP 0x12
#define CORE_VRD_TEMP 0x13
#define CH0_DIMM_TEMP 0x14
#define CH1_DIMM_TEMP 0x15
#define CH2_DIMM_TEMP 0x16
#define CH3_DIMM_TEMP 0x17
#define CH4_DIMM_TEMP 0x18
#define CH5_DIMM_TEMP 0x19
#define CH6_DIMM_TEMP 0x1A
#define CH7_DIMM_TEMP 0x1B
#define RCA_VRD_TEMP 0x1C
#define CORE_VRD_PWR 0x20
#define SOC_PWR 0x21
#define DIMM_VRD1_PWR 0x22
#define DIMM_VRD2_PWR 0x23
#define CORE_VRD_PWR_MW 0x26
#define SOC_PWR_MW 0x27
#define DIMM_VRD1_PWR_MW 0x28
#define DIMM_VRD2_PWR_MW 0x29
#define RCA_VRD_PWR 0x2A
#define RCA_VRD_PWR_MW 0x2B
#define MEM_HOT_THRESHOLD 0x32
#define SOC_VR_HOT_THRESHOLD 0x33
#define CORE_VRD_VOLT 0x34
#define SOC_VRD_VOLT 0x35
#define DIMM_VRD1_VOLT 0x36
#define DIMM_VRD2_VOLT 0x37
#define RCA_VRD_VOLT 0x38
#define CORE_VRD_CURR 0x39
#define SOC_VRD_CURR 0x3A
#define DIMM_VRD1_CURR 0x3B
#define DIMM_VRD2_CURR 0x3C
#define RCA_VRD_CURR 0x3D
struct smpro_hwmon {
struct regmap *regmap;
};
struct smpro_sensor {
const u8 reg;
const u8 reg_ext;
const char *label;
};
static const struct smpro_sensor temperature[] = {
{
.reg = SOC_TEMP,
.label = "temp1 SoC"
},
{
.reg = SOC_VRD_TEMP,
.reg_ext = SOC_VR_HOT_THRESHOLD,
.label = "temp2 SoC VRD"
},
{
.reg = DIMM_VRD_TEMP,
.label = "temp3 DIMM VRD"
},
{
.reg = CORE_VRD_TEMP,
.label = "temp4 CORE VRD"
},
{
.reg = CH0_DIMM_TEMP,
.reg_ext = MEM_HOT_THRESHOLD,
.label = "temp5 CH0 DIMM"
},
{
.reg = CH1_DIMM_TEMP,
.reg_ext = MEM_HOT_THRESHOLD,
.label = "temp6 CH1 DIMM"
},
{
.reg = CH2_DIMM_TEMP,
.reg_ext = MEM_HOT_THRESHOLD,
.label = "temp7 CH2 DIMM"
},
{
.reg = CH3_DIMM_TEMP,
.reg_ext = MEM_HOT_THRESHOLD,
.label = "temp8 CH3 DIMM"
},
{
.reg = CH4_DIMM_TEMP,
.reg_ext = MEM_HOT_THRESHOLD,
.label = "temp9 CH4 DIMM"
},
{
.reg = CH5_DIMM_TEMP,
.reg_ext = MEM_HOT_THRESHOLD,
.label = "temp10 CH5 DIMM"
},
{
.reg = CH6_DIMM_TEMP,
.reg_ext = MEM_HOT_THRESHOLD,
.label = "temp11 CH6 DIMM"
},
{
.reg = CH7_DIMM_TEMP,
.reg_ext = MEM_HOT_THRESHOLD,
.label = "temp12 CH7 DIMM"
},
{
.reg = RCA_VRD_TEMP,
.label = "temp13 RCA VRD"
},
};
static const struct smpro_sensor voltage[] = {
{
.reg = CORE_VRD_VOLT,
.label = "vout0 CORE VRD"
},
{
.reg = SOC_VRD_VOLT,
.label = "vout1 SoC VRD"
},
{
.reg = DIMM_VRD1_VOLT,
.label = "vout2 DIMM VRD1"
},
{
.reg = DIMM_VRD2_VOLT,
.label = "vout3 DIMM VRD2"
},
{
.reg = RCA_VRD_VOLT,
.label = "vout4 RCA VRD"
},
};
static const struct smpro_sensor curr_sensor[] = {
{
.reg = CORE_VRD_CURR,
.label = "iout1 CORE VRD"
},
{
.reg = SOC_VRD_CURR,
.label = "iout2 SoC VRD"
},
{
.reg = DIMM_VRD1_CURR,
.label = "iout3 DIMM VRD1"
},
{
.reg = DIMM_VRD2_CURR,
.label = "iout4 DIMM VRD2"
},
{
.reg = RCA_VRD_CURR,
.label = "iout5 RCA VRD"
},
};
static const struct smpro_sensor power[] = {
{
.reg = CORE_VRD_PWR,
.reg_ext = CORE_VRD_PWR_MW,
.label = "power1 CORE VRD"
},
{
.reg = SOC_PWR,
.reg_ext = SOC_PWR_MW,
.label = "power2 SoC"
},
{
.reg = DIMM_VRD1_PWR,
.reg_ext = DIMM_VRD1_PWR_MW,
.label = "power3 DIMM VRD1"
},
{
.reg = DIMM_VRD2_PWR,
.reg_ext = DIMM_VRD2_PWR_MW,
.label = "power4 DIMM VRD2"
},
{
.reg = RCA_VRD_PWR,
.reg_ext = RCA_VRD_PWR_MW,
.label = "power5 RCA VRD"
},
};
static int smpro_read_temp(struct device *dev, u32 attr, int channel, long *val)
{
struct smpro_hwmon *hwmon = dev_get_drvdata(dev);
unsigned int value;
int ret;
switch (attr) {
case hwmon_temp_input:
ret = regmap_read(hwmon->regmap, temperature[channel].reg, &value);
if (ret)
return ret;
break;
case hwmon_temp_crit:
ret = regmap_read(hwmon->regmap, temperature[channel].reg_ext, &value);
if (ret)
return ret;
break;
default:
return -EOPNOTSUPP;
}
*val = sign_extend32(value, 8) * 1000;
return 0;
}
static int smpro_read_in(struct device *dev, u32 attr, int channel, long *val)
{
struct smpro_hwmon *hwmon = dev_get_drvdata(dev);
unsigned int value;
int ret;
switch (attr) {
case hwmon_in_input:
ret = regmap_read(hwmon->regmap, voltage[channel].reg, &value);
if (ret < 0)
return ret;
/* 15-bit value in 1mV */
*val = value & 0x7fff;
return 0;
default:
return -EOPNOTSUPP;
}
}
static int smpro_read_curr(struct device *dev, u32 attr, int channel, long *val)
{
struct smpro_hwmon *hwmon = dev_get_drvdata(dev);
unsigned int value;
int ret;
switch (attr) {
case hwmon_curr_input:
ret = regmap_read(hwmon->regmap, curr_sensor[channel].reg, &value);
if (ret < 0)
return ret;
/* Scale reported by the hardware is 1mA */
*val = value & 0x7fff;
return 0;
default:
return -EOPNOTSUPP;
}
}
static int smpro_read_power(struct device *dev, u32 attr, int channel, long *val_pwr)
{
struct smpro_hwmon *hwmon = dev_get_drvdata(dev);
unsigned int val = 0, val_mw = 0;
int ret;
switch (attr) {
case hwmon_power_input:
ret = regmap_read(hwmon->regmap, power[channel].reg, &val);
if (ret)
return ret;
ret = regmap_read(hwmon->regmap, power[channel].reg_ext, &val_mw);
if (ret)
return ret;
/* 10-bit value */
*val_pwr = (val & 0x3ff) * 1000000 + (val_mw & 0x3ff) * 1000;
return 0;
default:
return -EOPNOTSUPP;
}
}
static int smpro_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
switch (type) {
case hwmon_temp:
return smpro_read_temp(dev, attr, channel, val);
case hwmon_in:
return smpro_read_in(dev, attr, channel, val);
case hwmon_power:
return smpro_read_power(dev, attr, channel, val);
case hwmon_curr:
return smpro_read_curr(dev, attr, channel, val);
default:
return -EOPNOTSUPP;
}
}
static int smpro_read_string(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, const char **str)
{
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_label:
*str = temperature[channel].label;
return 0;
default:
break;
}
break;
case hwmon_in:
switch (attr) {
case hwmon_in_label:
*str = voltage[channel].label;
return 0;
default:
break;
}
break;
case hwmon_curr:
switch (attr) {
case hwmon_curr_label:
*str = curr_sensor[channel].label;
return 0;
default:
break;
}
break;
case hwmon_power:
switch (attr) {
case hwmon_power_label:
*str = power[channel].label;
return 0;
default:
break;
}
break;
default:
break;
}
return -EOPNOTSUPP;
}
static umode_t smpro_is_visible(const void *data, enum hwmon_sensor_types type,
u32 attr, int channel)
{
const struct smpro_hwmon *hwmon = data;
unsigned int value;
int ret;
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_input:
case hwmon_temp_label:
case hwmon_temp_crit:
ret = regmap_read(hwmon->regmap, temperature[channel].reg, &value);
if (ret || value == 0xFFFF)
return 0;
break;
default:
break;
}
break;
default:
break;
}
return 0444;
}
static const struct hwmon_channel_info * const smpro_info[] = {
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_CRIT,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL,
HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_CRIT,
HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_CRIT,
HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_CRIT,
HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_CRIT,
HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_CRIT,
HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_CRIT,
HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_CRIT,
HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_CRIT,
HWMON_T_INPUT | HWMON_T_LABEL),
HWMON_CHANNEL_INFO(in,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL),
HWMON_CHANNEL_INFO(power,
HWMON_P_INPUT | HWMON_P_LABEL,
HWMON_P_INPUT | HWMON_P_LABEL,
HWMON_P_INPUT | HWMON_P_LABEL,
HWMON_P_INPUT | HWMON_P_LABEL,
HWMON_P_INPUT | HWMON_P_LABEL),
HWMON_CHANNEL_INFO(curr,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL,
HWMON_C_INPUT | HWMON_C_LABEL),
NULL
};
static const struct hwmon_ops smpro_hwmon_ops = {
.is_visible = smpro_is_visible,
.read = smpro_read,
.read_string = smpro_read_string,
};
static const struct hwmon_chip_info smpro_chip_info = {
.ops = &smpro_hwmon_ops,
.info = smpro_info,
};
static int smpro_hwmon_probe(struct platform_device *pdev)
{
struct smpro_hwmon *hwmon;
struct device *hwmon_dev;
hwmon = devm_kzalloc(&pdev->dev, sizeof(struct smpro_hwmon), GFP_KERNEL);
if (!hwmon)
return -ENOMEM;
hwmon->regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!hwmon->regmap)
return -ENODEV;
hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, "smpro_hwmon",
hwmon, &smpro_chip_info, NULL);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static struct platform_driver smpro_hwmon_driver = {
.probe = smpro_hwmon_probe,
.driver = {
.name = "smpro-hwmon",
},
};
module_platform_driver(smpro_hwmon_driver);
MODULE_AUTHOR("Thu Nguyen <[email protected]>");
MODULE_AUTHOR("Quan Nguyen <[email protected]>");
MODULE_DESCRIPTION("Ampere Altra SMPro hwmon driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/smpro-hwmon.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* adm1031.c - Part of lm_sensors, Linux kernel modules for hardware
* monitoring
* Based on lm75.c and lm85.c
* Supports adm1030 / adm1031
* Copyright (C) 2004 Alexandre d'Alton <[email protected]>
* Reworked by Jean Delvare <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
/* Following macros takes channel parameter starting from 0 to 2 */
#define ADM1031_REG_FAN_SPEED(nr) (0x08 + (nr))
#define ADM1031_REG_FAN_DIV(nr) (0x20 + (nr))
#define ADM1031_REG_PWM (0x22)
#define ADM1031_REG_FAN_MIN(nr) (0x10 + (nr))
#define ADM1031_REG_FAN_FILTER (0x23)
#define ADM1031_REG_TEMP_OFFSET(nr) (0x0d + (nr))
#define ADM1031_REG_TEMP_MAX(nr) (0x14 + 4 * (nr))
#define ADM1031_REG_TEMP_MIN(nr) (0x15 + 4 * (nr))
#define ADM1031_REG_TEMP_CRIT(nr) (0x16 + 4 * (nr))
#define ADM1031_REG_TEMP(nr) (0x0a + (nr))
#define ADM1031_REG_AUTO_TEMP(nr) (0x24 + (nr))
#define ADM1031_REG_STATUS(nr) (0x2 + (nr))
#define ADM1031_REG_CONF1 0x00
#define ADM1031_REG_CONF2 0x01
#define ADM1031_REG_EXT_TEMP 0x06
#define ADM1031_CONF1_MONITOR_ENABLE 0x01 /* Monitoring enable */
#define ADM1031_CONF1_PWM_INVERT 0x08 /* PWM Invert */
#define ADM1031_CONF1_AUTO_MODE 0x80 /* Auto FAN */
#define ADM1031_CONF2_PWM1_ENABLE 0x01
#define ADM1031_CONF2_PWM2_ENABLE 0x02
#define ADM1031_CONF2_TACH1_ENABLE 0x04
#define ADM1031_CONF2_TACH2_ENABLE 0x08
#define ADM1031_CONF2_TEMP_ENABLE(chan) (0x10 << (chan))
#define ADM1031_UPDATE_RATE_MASK 0x1c
#define ADM1031_UPDATE_RATE_SHIFT 2
/* Addresses to scan */
static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, I2C_CLIENT_END };
enum chips { adm1030, adm1031 };
typedef u8 auto_chan_table_t[8][2];
/* Each client has this additional data */
struct adm1031_data {
struct i2c_client *client;
const struct attribute_group *groups[3];
struct mutex update_lock;
int chip_type;
bool valid; /* true if following fields are valid */
unsigned long last_updated; /* In jiffies */
unsigned int update_interval; /* In milliseconds */
/*
* The chan_select_table contains the possible configurations for
* auto fan control.
*/
const auto_chan_table_t *chan_select_table;
u16 alarm;
u8 conf1;
u8 conf2;
u8 fan[2];
u8 fan_div[2];
u8 fan_min[2];
u8 pwm[2];
u8 old_pwm[2];
s8 temp[3];
u8 ext_temp[3];
u8 auto_temp[3];
u8 auto_temp_min[3];
u8 auto_temp_off[3];
u8 auto_temp_max[3];
s8 temp_offset[3];
s8 temp_min[3];
s8 temp_max[3];
s8 temp_crit[3];
};
static inline u8 adm1031_read_value(struct i2c_client *client, u8 reg)
{
return i2c_smbus_read_byte_data(client, reg);
}
static inline int
adm1031_write_value(struct i2c_client *client, u8 reg, unsigned int value)
{
return i2c_smbus_write_byte_data(client, reg, value);
}
static struct adm1031_data *adm1031_update_device(struct device *dev)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
unsigned long next_update;
int chan;
mutex_lock(&data->update_lock);
next_update = data->last_updated
+ msecs_to_jiffies(data->update_interval);
if (time_after(jiffies, next_update) || !data->valid) {
dev_dbg(&client->dev, "Starting adm1031 update\n");
for (chan = 0;
chan < ((data->chip_type == adm1031) ? 3 : 2); chan++) {
u8 oldh, newh;
oldh =
adm1031_read_value(client, ADM1031_REG_TEMP(chan));
data->ext_temp[chan] =
adm1031_read_value(client, ADM1031_REG_EXT_TEMP);
newh =
adm1031_read_value(client, ADM1031_REG_TEMP(chan));
if (newh != oldh) {
data->ext_temp[chan] =
adm1031_read_value(client,
ADM1031_REG_EXT_TEMP);
#ifdef DEBUG
oldh =
adm1031_read_value(client,
ADM1031_REG_TEMP(chan));
/* oldh is actually newer */
if (newh != oldh)
dev_warn(&client->dev,
"Remote temperature may be wrong.\n");
#endif
}
data->temp[chan] = newh;
data->temp_offset[chan] =
adm1031_read_value(client,
ADM1031_REG_TEMP_OFFSET(chan));
data->temp_min[chan] =
adm1031_read_value(client,
ADM1031_REG_TEMP_MIN(chan));
data->temp_max[chan] =
adm1031_read_value(client,
ADM1031_REG_TEMP_MAX(chan));
data->temp_crit[chan] =
adm1031_read_value(client,
ADM1031_REG_TEMP_CRIT(chan));
data->auto_temp[chan] =
adm1031_read_value(client,
ADM1031_REG_AUTO_TEMP(chan));
}
data->conf1 = adm1031_read_value(client, ADM1031_REG_CONF1);
data->conf2 = adm1031_read_value(client, ADM1031_REG_CONF2);
data->alarm = adm1031_read_value(client, ADM1031_REG_STATUS(0))
| (adm1031_read_value(client, ADM1031_REG_STATUS(1)) << 8);
if (data->chip_type == adm1030)
data->alarm &= 0xc0ff;
for (chan = 0; chan < (data->chip_type == adm1030 ? 1 : 2);
chan++) {
data->fan_div[chan] =
adm1031_read_value(client,
ADM1031_REG_FAN_DIV(chan));
data->fan_min[chan] =
adm1031_read_value(client,
ADM1031_REG_FAN_MIN(chan));
data->fan[chan] =
adm1031_read_value(client,
ADM1031_REG_FAN_SPEED(chan));
data->pwm[chan] =
(adm1031_read_value(client,
ADM1031_REG_PWM) >> (4 * chan)) & 0x0f;
}
data->last_updated = jiffies;
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
#define TEMP_TO_REG(val) (((val) < 0 ? ((val - 500) / 1000) : \
((val + 500) / 1000)))
#define TEMP_FROM_REG(val) ((val) * 1000)
#define TEMP_FROM_REG_EXT(val, ext) (TEMP_FROM_REG(val) + (ext) * 125)
#define TEMP_OFFSET_TO_REG(val) (TEMP_TO_REG(val) & 0x8f)
#define TEMP_OFFSET_FROM_REG(val) TEMP_FROM_REG((val) < 0 ? \
(val) | 0x70 : (val))
#define FAN_FROM_REG(reg, div) ((reg) ? \
(11250 * 60) / ((reg) * (div)) : 0)
static int FAN_TO_REG(int reg, int div)
{
int tmp;
tmp = FAN_FROM_REG(clamp_val(reg, 0, 65535), div);
return tmp > 255 ? 255 : tmp;
}
#define FAN_DIV_FROM_REG(reg) (1<<(((reg)&0xc0)>>6))
#define PWM_TO_REG(val) (clamp_val((val), 0, 255) >> 4)
#define PWM_FROM_REG(val) ((val) << 4)
#define FAN_CHAN_FROM_REG(reg) (((reg) >> 5) & 7)
#define FAN_CHAN_TO_REG(val, reg) \
(((reg) & 0x1F) | (((val) << 5) & 0xe0))
#define AUTO_TEMP_MIN_TO_REG(val, reg) \
((((val) / 500) & 0xf8) | ((reg) & 0x7))
#define AUTO_TEMP_RANGE_FROM_REG(reg) (5000 * (1 << ((reg) & 0x7)))
#define AUTO_TEMP_MIN_FROM_REG(reg) (1000 * ((((reg) >> 3) & 0x1f) << 2))
#define AUTO_TEMP_MIN_FROM_REG_DEG(reg) ((((reg) >> 3) & 0x1f) << 2)
#define AUTO_TEMP_OFF_FROM_REG(reg) \
(AUTO_TEMP_MIN_FROM_REG(reg) - 5000)
#define AUTO_TEMP_MAX_FROM_REG(reg) \
(AUTO_TEMP_RANGE_FROM_REG(reg) + \
AUTO_TEMP_MIN_FROM_REG(reg))
static int AUTO_TEMP_MAX_TO_REG(int val, int reg, int pwm)
{
int ret;
int range = ((val - AUTO_TEMP_MIN_FROM_REG(reg)) * 10) / (16 - pwm);
ret = ((reg & 0xf8) |
(range < 10000 ? 0 :
range < 20000 ? 1 :
range < 40000 ? 2 : range < 80000 ? 3 : 4));
return ret;
}
/* FAN auto control */
#define GET_FAN_AUTO_BITFIELD(data, idx) \
(*(data)->chan_select_table)[FAN_CHAN_FROM_REG((data)->conf1)][idx % 2]
/*
* The tables below contains the possible values for the auto fan
* control bitfields. the index in the table is the register value.
* MSb is the auto fan control enable bit, so the four first entries
* in the table disables auto fan control when both bitfields are zero.
*/
static const auto_chan_table_t auto_channel_select_table_adm1031 = {
{ 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 },
{ 2 /* 0b010 */ , 4 /* 0b100 */ },
{ 2 /* 0b010 */ , 2 /* 0b010 */ },
{ 4 /* 0b100 */ , 4 /* 0b100 */ },
{ 7 /* 0b111 */ , 7 /* 0b111 */ },
};
static const auto_chan_table_t auto_channel_select_table_adm1030 = {
{ 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 },
{ 2 /* 0b10 */ , 0 },
{ 0xff /* invalid */ , 0 },
{ 0xff /* invalid */ , 0 },
{ 3 /* 0b11 */ , 0 },
};
/*
* That function checks if a bitfield is valid and returns the other bitfield
* nearest match if no exact match where found.
*/
static int
get_fan_auto_nearest(struct adm1031_data *data, int chan, u8 val, u8 reg)
{
int i;
int first_match = -1, exact_match = -1;
u8 other_reg_val =
(*data->chan_select_table)[FAN_CHAN_FROM_REG(reg)][chan ? 0 : 1];
if (val == 0)
return 0;
for (i = 0; i < 8; i++) {
if ((val == (*data->chan_select_table)[i][chan]) &&
((*data->chan_select_table)[i][chan ? 0 : 1] ==
other_reg_val)) {
/* We found an exact match */
exact_match = i;
break;
} else if (val == (*data->chan_select_table)[i][chan] &&
first_match == -1) {
/*
* Save the first match in case of an exact match has
* not been found
*/
first_match = i;
}
}
if (exact_match >= 0)
return exact_match;
else if (first_match >= 0)
return first_match;
return -EINVAL;
}
static ssize_t fan_auto_channel_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n", GET_FAN_AUTO_BITFIELD(data, nr));
}
static ssize_t
fan_auto_channel_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr = to_sensor_dev_attr(attr)->index;
long val;
u8 reg;
int ret;
u8 old_fan_mode;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
old_fan_mode = data->conf1;
mutex_lock(&data->update_lock);
ret = get_fan_auto_nearest(data, nr, val, data->conf1);
if (ret < 0) {
mutex_unlock(&data->update_lock);
return ret;
}
reg = ret;
data->conf1 = FAN_CHAN_TO_REG(reg, data->conf1);
if ((data->conf1 & ADM1031_CONF1_AUTO_MODE) ^
(old_fan_mode & ADM1031_CONF1_AUTO_MODE)) {
if (data->conf1 & ADM1031_CONF1_AUTO_MODE) {
/*
* Switch to Auto Fan Mode
* Save PWM registers
* Set PWM registers to 33% Both
*/
data->old_pwm[0] = data->pwm[0];
data->old_pwm[1] = data->pwm[1];
adm1031_write_value(client, ADM1031_REG_PWM, 0x55);
} else {
/* Switch to Manual Mode */
data->pwm[0] = data->old_pwm[0];
data->pwm[1] = data->old_pwm[1];
/* Restore PWM registers */
adm1031_write_value(client, ADM1031_REG_PWM,
data->pwm[0] | (data->pwm[1] << 4));
}
}
data->conf1 = FAN_CHAN_TO_REG(reg, data->conf1);
adm1031_write_value(client, ADM1031_REG_CONF1, data->conf1);
mutex_unlock(&data->update_lock);
return count;
}
static SENSOR_DEVICE_ATTR_RW(auto_fan1_channel, fan_auto_channel, 0);
static SENSOR_DEVICE_ATTR_RW(auto_fan2_channel, fan_auto_channel, 1);
/* Auto Temps */
static ssize_t auto_temp_off_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n",
AUTO_TEMP_OFF_FROM_REG(data->auto_temp[nr]));
}
static ssize_t auto_temp_min_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n",
AUTO_TEMP_MIN_FROM_REG(data->auto_temp[nr]));
}
static ssize_t
auto_temp_min_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr = to_sensor_dev_attr(attr)->index;
long val;
int ret;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
val = clamp_val(val, 0, 127000);
mutex_lock(&data->update_lock);
data->auto_temp[nr] = AUTO_TEMP_MIN_TO_REG(val, data->auto_temp[nr]);
adm1031_write_value(client, ADM1031_REG_AUTO_TEMP(nr),
data->auto_temp[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t auto_temp_max_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n",
AUTO_TEMP_MAX_FROM_REG(data->auto_temp[nr]));
}
static ssize_t
auto_temp_max_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr = to_sensor_dev_attr(attr)->index;
long val;
int ret;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
val = clamp_val(val, 0, 127000);
mutex_lock(&data->update_lock);
data->temp_max[nr] = AUTO_TEMP_MAX_TO_REG(val, data->auto_temp[nr],
data->pwm[nr]);
adm1031_write_value(client, ADM1031_REG_AUTO_TEMP(nr),
data->temp_max[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static SENSOR_DEVICE_ATTR_RO(auto_temp1_off, auto_temp_off, 0);
static SENSOR_DEVICE_ATTR_RW(auto_temp1_min, auto_temp_min, 0);
static SENSOR_DEVICE_ATTR_RW(auto_temp1_max, auto_temp_max, 0);
static SENSOR_DEVICE_ATTR_RO(auto_temp2_off, auto_temp_off, 1);
static SENSOR_DEVICE_ATTR_RW(auto_temp2_min, auto_temp_min, 1);
static SENSOR_DEVICE_ATTR_RW(auto_temp2_max, auto_temp_max, 1);
static SENSOR_DEVICE_ATTR_RO(auto_temp3_off, auto_temp_off, 2);
static SENSOR_DEVICE_ATTR_RW(auto_temp3_min, auto_temp_min, 2);
static SENSOR_DEVICE_ATTR_RW(auto_temp3_max, auto_temp_max, 2);
/* pwm */
static ssize_t pwm_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n", PWM_FROM_REG(data->pwm[nr]));
}
static ssize_t pwm_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr = to_sensor_dev_attr(attr)->index;
long val;
int ret, reg;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
mutex_lock(&data->update_lock);
if ((data->conf1 & ADM1031_CONF1_AUTO_MODE) &&
(((val>>4) & 0xf) != 5)) {
/* In automatic mode, the only PWM accepted is 33% */
mutex_unlock(&data->update_lock);
return -EINVAL;
}
data->pwm[nr] = PWM_TO_REG(val);
reg = adm1031_read_value(client, ADM1031_REG_PWM);
adm1031_write_value(client, ADM1031_REG_PWM,
nr ? ((data->pwm[nr] << 4) & 0xf0) | (reg & 0xf)
: (data->pwm[nr] & 0xf) | (reg & 0xf0));
mutex_unlock(&data->update_lock);
return count;
}
static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1);
static SENSOR_DEVICE_ATTR_RW(auto_fan1_min_pwm, pwm, 0);
static SENSOR_DEVICE_ATTR_RW(auto_fan2_min_pwm, pwm, 1);
/* Fans */
/*
* That function checks the cases where the fan reading is not
* relevant. It is used to provide 0 as fan reading when the fan is
* not supposed to run
*/
static int trust_fan_readings(struct adm1031_data *data, int chan)
{
int res = 0;
if (data->conf1 & ADM1031_CONF1_AUTO_MODE) {
switch (data->conf1 & 0x60) {
case 0x00:
/*
* remote temp1 controls fan1,
* remote temp2 controls fan2
*/
res = data->temp[chan+1] >=
AUTO_TEMP_MIN_FROM_REG_DEG(data->auto_temp[chan+1]);
break;
case 0x20: /* remote temp1 controls both fans */
res =
data->temp[1] >=
AUTO_TEMP_MIN_FROM_REG_DEG(data->auto_temp[1]);
break;
case 0x40: /* remote temp2 controls both fans */
res =
data->temp[2] >=
AUTO_TEMP_MIN_FROM_REG_DEG(data->auto_temp[2]);
break;
case 0x60: /* max controls both fans */
res =
data->temp[0] >=
AUTO_TEMP_MIN_FROM_REG_DEG(data->auto_temp[0])
|| data->temp[1] >=
AUTO_TEMP_MIN_FROM_REG_DEG(data->auto_temp[1])
|| (data->chip_type == adm1031
&& data->temp[2] >=
AUTO_TEMP_MIN_FROM_REG_DEG(data->auto_temp[2]));
break;
}
} else {
res = data->pwm[chan] > 0;
}
return res;
}
static ssize_t fan_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
int value;
value = trust_fan_readings(data, nr) ? FAN_FROM_REG(data->fan[nr],
FAN_DIV_FROM_REG(data->fan_div[nr])) : 0;
return sprintf(buf, "%d\n", value);
}
static ssize_t fan_div_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n", FAN_DIV_FROM_REG(data->fan_div[nr]));
}
static ssize_t fan_min_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n",
FAN_FROM_REG(data->fan_min[nr],
FAN_DIV_FROM_REG(data->fan_div[nr])));
}
static ssize_t fan_min_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr = to_sensor_dev_attr(attr)->index;
long val;
int ret;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
mutex_lock(&data->update_lock);
if (val) {
data->fan_min[nr] =
FAN_TO_REG(val, FAN_DIV_FROM_REG(data->fan_div[nr]));
} else {
data->fan_min[nr] = 0xff;
}
adm1031_write_value(client, ADM1031_REG_FAN_MIN(nr), data->fan_min[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t fan_div_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr = to_sensor_dev_attr(attr)->index;
long val;
u8 tmp;
int old_div;
int new_min;
int ret;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
tmp = val == 8 ? 0xc0 :
val == 4 ? 0x80 :
val == 2 ? 0x40 :
val == 1 ? 0x00 :
0xff;
if (tmp == 0xff)
return -EINVAL;
mutex_lock(&data->update_lock);
/* Get fresh readings */
data->fan_div[nr] = adm1031_read_value(client,
ADM1031_REG_FAN_DIV(nr));
data->fan_min[nr] = adm1031_read_value(client,
ADM1031_REG_FAN_MIN(nr));
/* Write the new clock divider and fan min */
old_div = FAN_DIV_FROM_REG(data->fan_div[nr]);
data->fan_div[nr] = tmp | (0x3f & data->fan_div[nr]);
new_min = data->fan_min[nr] * old_div / val;
data->fan_min[nr] = new_min > 0xff ? 0xff : new_min;
adm1031_write_value(client, ADM1031_REG_FAN_DIV(nr),
data->fan_div[nr]);
adm1031_write_value(client, ADM1031_REG_FAN_MIN(nr),
data->fan_min[nr]);
/* Invalidate the cache: fan speed is no longer valid */
data->valid = false;
mutex_unlock(&data->update_lock);
return count;
}
static SENSOR_DEVICE_ATTR_RO(fan1_input, fan, 0);
static SENSOR_DEVICE_ATTR_RW(fan1_min, fan_min, 0);
static SENSOR_DEVICE_ATTR_RW(fan1_div, fan_div, 0);
static SENSOR_DEVICE_ATTR_RO(fan2_input, fan, 1);
static SENSOR_DEVICE_ATTR_RW(fan2_min, fan_min, 1);
static SENSOR_DEVICE_ATTR_RW(fan2_div, fan_div, 1);
/* Temps */
static ssize_t temp_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
int ext;
ext = nr == 0 ?
((data->ext_temp[nr] >> 6) & 0x3) * 2 :
(((data->ext_temp[nr] >> ((nr - 1) * 3)) & 7));
return sprintf(buf, "%d\n", TEMP_FROM_REG_EXT(data->temp[nr], ext));
}
static ssize_t temp_offset_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n",
TEMP_OFFSET_FROM_REG(data->temp_offset[nr]));
}
static ssize_t temp_min_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp_min[nr]));
}
static ssize_t temp_max_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp_max[nr]));
}
static ssize_t temp_crit_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp_crit[nr]));
}
static ssize_t temp_offset_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr = to_sensor_dev_attr(attr)->index;
long val;
int ret;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
val = clamp_val(val, -15000, 15000);
mutex_lock(&data->update_lock);
data->temp_offset[nr] = TEMP_OFFSET_TO_REG(val);
adm1031_write_value(client, ADM1031_REG_TEMP_OFFSET(nr),
data->temp_offset[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t temp_min_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr = to_sensor_dev_attr(attr)->index;
long val;
int ret;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
val = clamp_val(val, -55000, 127000);
mutex_lock(&data->update_lock);
data->temp_min[nr] = TEMP_TO_REG(val);
adm1031_write_value(client, ADM1031_REG_TEMP_MIN(nr),
data->temp_min[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t temp_max_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr = to_sensor_dev_attr(attr)->index;
long val;
int ret;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
val = clamp_val(val, -55000, 127000);
mutex_lock(&data->update_lock);
data->temp_max[nr] = TEMP_TO_REG(val);
adm1031_write_value(client, ADM1031_REG_TEMP_MAX(nr),
data->temp_max[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t temp_crit_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr = to_sensor_dev_attr(attr)->index;
long val;
int ret;
ret = kstrtol(buf, 10, &val);
if (ret)
return ret;
val = clamp_val(val, -55000, 127000);
mutex_lock(&data->update_lock);
data->temp_crit[nr] = TEMP_TO_REG(val);
adm1031_write_value(client, ADM1031_REG_TEMP_CRIT(nr),
data->temp_crit[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static SENSOR_DEVICE_ATTR_RO(temp1_input, temp, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_offset, temp_offset, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_min, temp_min, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_max, temp_max, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_crit, temp_crit, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_input, temp, 1);
static SENSOR_DEVICE_ATTR_RW(temp2_offset, temp_offset, 1);
static SENSOR_DEVICE_ATTR_RW(temp2_min, temp_min, 1);
static SENSOR_DEVICE_ATTR_RW(temp2_max, temp_max, 1);
static SENSOR_DEVICE_ATTR_RW(temp2_crit, temp_crit, 1);
static SENSOR_DEVICE_ATTR_RO(temp3_input, temp, 2);
static SENSOR_DEVICE_ATTR_RW(temp3_offset, temp_offset, 2);
static SENSOR_DEVICE_ATTR_RW(temp3_min, temp_min, 2);
static SENSOR_DEVICE_ATTR_RW(temp3_max, temp_max, 2);
static SENSOR_DEVICE_ATTR_RW(temp3_crit, temp_crit, 2);
/* Alarms */
static ssize_t alarms_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n", data->alarm);
}
static DEVICE_ATTR_RO(alarms);
static ssize_t alarm_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int bitnr = to_sensor_dev_attr(attr)->index;
struct adm1031_data *data = adm1031_update_device(dev);
return sprintf(buf, "%d\n", (data->alarm >> bitnr) & 1);
}
static SENSOR_DEVICE_ATTR_RO(fan1_alarm, alarm, 0);
static SENSOR_DEVICE_ATTR_RO(fan1_fault, alarm, 1);
static SENSOR_DEVICE_ATTR_RO(temp2_max_alarm, alarm, 2);
static SENSOR_DEVICE_ATTR_RO(temp2_min_alarm, alarm, 3);
static SENSOR_DEVICE_ATTR_RO(temp2_crit_alarm, alarm, 4);
static SENSOR_DEVICE_ATTR_RO(temp2_fault, alarm, 5);
static SENSOR_DEVICE_ATTR_RO(temp1_max_alarm, alarm, 6);
static SENSOR_DEVICE_ATTR_RO(temp1_min_alarm, alarm, 7);
static SENSOR_DEVICE_ATTR_RO(fan2_alarm, alarm, 8);
static SENSOR_DEVICE_ATTR_RO(fan2_fault, alarm, 9);
static SENSOR_DEVICE_ATTR_RO(temp3_max_alarm, alarm, 10);
static SENSOR_DEVICE_ATTR_RO(temp3_min_alarm, alarm, 11);
static SENSOR_DEVICE_ATTR_RO(temp3_crit_alarm, alarm, 12);
static SENSOR_DEVICE_ATTR_RO(temp3_fault, alarm, 13);
static SENSOR_DEVICE_ATTR_RO(temp1_crit_alarm, alarm, 14);
/* Update Interval */
static const unsigned int update_intervals[] = {
16000, 8000, 4000, 2000, 1000, 500, 250, 125,
};
static ssize_t update_interval_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct adm1031_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%u\n", data->update_interval);
}
static ssize_t update_interval_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct adm1031_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
unsigned long val;
int i, err;
u8 reg;
err = kstrtoul(buf, 10, &val);
if (err)
return err;
/*
* Find the nearest update interval from the table.
* Use it to determine the matching update rate.
*/
for (i = 0; i < ARRAY_SIZE(update_intervals) - 1; i++) {
if (val >= update_intervals[i])
break;
}
/* if not found, we point to the last entry (lowest update interval) */
/* set the new update rate while preserving other settings */
reg = adm1031_read_value(client, ADM1031_REG_FAN_FILTER);
reg &= ~ADM1031_UPDATE_RATE_MASK;
reg |= i << ADM1031_UPDATE_RATE_SHIFT;
adm1031_write_value(client, ADM1031_REG_FAN_FILTER, reg);
mutex_lock(&data->update_lock);
data->update_interval = update_intervals[i];
mutex_unlock(&data->update_lock);
return count;
}
static DEVICE_ATTR_RW(update_interval);
static struct attribute *adm1031_attributes[] = {
&sensor_dev_attr_fan1_input.dev_attr.attr,
&sensor_dev_attr_fan1_div.dev_attr.attr,
&sensor_dev_attr_fan1_min.dev_attr.attr,
&sensor_dev_attr_fan1_alarm.dev_attr.attr,
&sensor_dev_attr_fan1_fault.dev_attr.attr,
&sensor_dev_attr_pwm1.dev_attr.attr,
&sensor_dev_attr_auto_fan1_channel.dev_attr.attr,
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_offset.dev_attr.attr,
&sensor_dev_attr_temp1_min.dev_attr.attr,
&sensor_dev_attr_temp1_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_crit.dev_attr.attr,
&sensor_dev_attr_temp1_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp2_offset.dev_attr.attr,
&sensor_dev_attr_temp2_min.dev_attr.attr,
&sensor_dev_attr_temp2_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_max.dev_attr.attr,
&sensor_dev_attr_temp2_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_crit.dev_attr.attr,
&sensor_dev_attr_temp2_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_fault.dev_attr.attr,
&sensor_dev_attr_auto_temp1_off.dev_attr.attr,
&sensor_dev_attr_auto_temp1_min.dev_attr.attr,
&sensor_dev_attr_auto_temp1_max.dev_attr.attr,
&sensor_dev_attr_auto_temp2_off.dev_attr.attr,
&sensor_dev_attr_auto_temp2_min.dev_attr.attr,
&sensor_dev_attr_auto_temp2_max.dev_attr.attr,
&sensor_dev_attr_auto_fan1_min_pwm.dev_attr.attr,
&dev_attr_update_interval.attr,
&dev_attr_alarms.attr,
NULL
};
static const struct attribute_group adm1031_group = {
.attrs = adm1031_attributes,
};
static struct attribute *adm1031_attributes_opt[] = {
&sensor_dev_attr_fan2_input.dev_attr.attr,
&sensor_dev_attr_fan2_div.dev_attr.attr,
&sensor_dev_attr_fan2_min.dev_attr.attr,
&sensor_dev_attr_fan2_alarm.dev_attr.attr,
&sensor_dev_attr_fan2_fault.dev_attr.attr,
&sensor_dev_attr_pwm2.dev_attr.attr,
&sensor_dev_attr_auto_fan2_channel.dev_attr.attr,
&sensor_dev_attr_temp3_input.dev_attr.attr,
&sensor_dev_attr_temp3_offset.dev_attr.attr,
&sensor_dev_attr_temp3_min.dev_attr.attr,
&sensor_dev_attr_temp3_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp3_max.dev_attr.attr,
&sensor_dev_attr_temp3_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp3_crit.dev_attr.attr,
&sensor_dev_attr_temp3_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp3_fault.dev_attr.attr,
&sensor_dev_attr_auto_temp3_off.dev_attr.attr,
&sensor_dev_attr_auto_temp3_min.dev_attr.attr,
&sensor_dev_attr_auto_temp3_max.dev_attr.attr,
&sensor_dev_attr_auto_fan2_min_pwm.dev_attr.attr,
NULL
};
static const struct attribute_group adm1031_group_opt = {
.attrs = adm1031_attributes_opt,
};
/* Return 0 if detection is successful, -ENODEV otherwise */
static int adm1031_detect(struct i2c_client *client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
const char *name;
int id, co;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
id = i2c_smbus_read_byte_data(client, 0x3d);
co = i2c_smbus_read_byte_data(client, 0x3e);
if (!((id == 0x31 || id == 0x30) && co == 0x41))
return -ENODEV;
name = (id == 0x30) ? "adm1030" : "adm1031";
strscpy(info->type, name, I2C_NAME_SIZE);
return 0;
}
static void adm1031_init_client(struct i2c_client *client)
{
unsigned int read_val;
unsigned int mask;
int i;
struct adm1031_data *data = i2c_get_clientdata(client);
mask = (ADM1031_CONF2_PWM1_ENABLE | ADM1031_CONF2_TACH1_ENABLE);
if (data->chip_type == adm1031) {
mask |= (ADM1031_CONF2_PWM2_ENABLE |
ADM1031_CONF2_TACH2_ENABLE);
}
/* Initialize the ADM1031 chip (enables fan speed reading ) */
read_val = adm1031_read_value(client, ADM1031_REG_CONF2);
if ((read_val | mask) != read_val)
adm1031_write_value(client, ADM1031_REG_CONF2, read_val | mask);
read_val = adm1031_read_value(client, ADM1031_REG_CONF1);
if ((read_val | ADM1031_CONF1_MONITOR_ENABLE) != read_val) {
adm1031_write_value(client, ADM1031_REG_CONF1,
read_val | ADM1031_CONF1_MONITOR_ENABLE);
}
/* Read the chip's update rate */
mask = ADM1031_UPDATE_RATE_MASK;
read_val = adm1031_read_value(client, ADM1031_REG_FAN_FILTER);
i = (read_val & mask) >> ADM1031_UPDATE_RATE_SHIFT;
/* Save it as update interval */
data->update_interval = update_intervals[i];
}
static const struct i2c_device_id adm1031_id[];
static int adm1031_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct device *hwmon_dev;
struct adm1031_data *data;
data = devm_kzalloc(dev, sizeof(struct adm1031_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
i2c_set_clientdata(client, data);
data->client = client;
data->chip_type = i2c_match_id(adm1031_id, client)->driver_data;
mutex_init(&data->update_lock);
if (data->chip_type == adm1030)
data->chan_select_table = &auto_channel_select_table_adm1030;
else
data->chan_select_table = &auto_channel_select_table_adm1031;
/* Initialize the ADM1031 chip */
adm1031_init_client(client);
/* sysfs hooks */
data->groups[0] = &adm1031_group;
if (data->chip_type == adm1031)
data->groups[1] = &adm1031_group_opt;
hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
data, data->groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id adm1031_id[] = {
{ "adm1030", adm1030 },
{ "adm1031", adm1031 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adm1031_id);
static struct i2c_driver adm1031_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "adm1031",
},
.probe = adm1031_probe,
.id_table = adm1031_id,
.detect = adm1031_detect,
.address_list = normal_i2c,
};
module_i2c_driver(adm1031_driver);
MODULE_AUTHOR("Alexandre d'Alton <[email protected]>");
MODULE_DESCRIPTION("ADM1031/ADM1030 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/adm1031.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for Texas Instruments TMP512, TMP513 power monitor chips
*
* TMP513:
* Thermal/Power Management with Triple Remote and
* Local Temperature Sensor and Current Shunt Monitor
* Datasheet: https://www.ti.com/lit/gpn/tmp513
*
* TMP512:
* Thermal/Power Management with Dual Remote
* and Local Temperature Sensor and Current Shunt Monitor
* Datasheet: https://www.ti.com/lit/gpn/tmp512
*
* Copyright (C) 2019 Eric Tremblay <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/util_macros.h>
// Common register definition
#define TMP51X_SHUNT_CONFIG 0x00
#define TMP51X_TEMP_CONFIG 0x01
#define TMP51X_STATUS 0x02
#define TMP51X_SMBUS_ALERT 0x03
#define TMP51X_SHUNT_CURRENT_RESULT 0x04
#define TMP51X_BUS_VOLTAGE_RESULT 0x05
#define TMP51X_POWER_RESULT 0x06
#define TMP51X_BUS_CURRENT_RESULT 0x07
#define TMP51X_LOCAL_TEMP_RESULT 0x08
#define TMP51X_REMOTE_TEMP_RESULT_1 0x09
#define TMP51X_REMOTE_TEMP_RESULT_2 0x0A
#define TMP51X_SHUNT_CURRENT_H_LIMIT 0x0C
#define TMP51X_SHUNT_CURRENT_L_LIMIT 0x0D
#define TMP51X_BUS_VOLTAGE_H_LIMIT 0x0E
#define TMP51X_BUS_VOLTAGE_L_LIMIT 0x0F
#define TMP51X_POWER_LIMIT 0x10
#define TMP51X_LOCAL_TEMP_LIMIT 0x11
#define TMP51X_REMOTE_TEMP_LIMIT_1 0x12
#define TMP51X_REMOTE_TEMP_LIMIT_2 0x13
#define TMP51X_SHUNT_CALIBRATION 0x15
#define TMP51X_N_FACTOR_AND_HYST_1 0x16
#define TMP51X_N_FACTOR_2 0x17
#define TMP51X_MAN_ID_REG 0xFE
#define TMP51X_DEVICE_ID_REG 0xFF
// TMP513 specific register definition
#define TMP513_REMOTE_TEMP_RESULT_3 0x0B
#define TMP513_REMOTE_TEMP_LIMIT_3 0x14
#define TMP513_N_FACTOR_3 0x18
// Common attrs, and NULL
#define TMP51X_MANUFACTURER_ID 0x55FF
#define TMP512_DEVICE_ID 0x22FF
#define TMP513_DEVICE_ID 0x23FF
// Default config
#define TMP51X_SHUNT_CONFIG_DEFAULT 0x399F
#define TMP51X_SHUNT_VALUE_DEFAULT 1000
#define TMP51X_VBUS_RANGE_DEFAULT TMP51X_VBUS_RANGE_32V
#define TMP51X_PGA_DEFAULT 8
#define TMP51X_MAX_REGISTER_ADDR 0xFF
#define TMP512_TEMP_CONFIG_DEFAULT 0xBF80
#define TMP513_TEMP_CONFIG_DEFAULT 0xFF80
// Mask and shift
#define CURRENT_SENSE_VOLTAGE_320_MASK 0x1800
#define CURRENT_SENSE_VOLTAGE_160_MASK 0x1000
#define CURRENT_SENSE_VOLTAGE_80_MASK 0x0800
#define CURRENT_SENSE_VOLTAGE_40_MASK 0
#define TMP51X_BUS_VOLTAGE_MASK 0x2000
#define TMP51X_NFACTOR_MASK 0xFF00
#define TMP51X_HYST_MASK 0x00FF
#define TMP51X_BUS_VOLTAGE_SHIFT 3
#define TMP51X_TEMP_SHIFT 3
// Alarms
#define TMP51X_SHUNT_CURRENT_H_LIMIT_POS 15
#define TMP51X_SHUNT_CURRENT_L_LIMIT_POS 14
#define TMP51X_BUS_VOLTAGE_H_LIMIT_POS 13
#define TMP51X_BUS_VOLTAGE_L_LIMIT_POS 12
#define TMP51X_POWER_LIMIT_POS 11
#define TMP51X_LOCAL_TEMP_LIMIT_POS 10
#define TMP51X_REMOTE_TEMP_LIMIT_1_POS 9
#define TMP51X_REMOTE_TEMP_LIMIT_2_POS 8
#define TMP513_REMOTE_TEMP_LIMIT_3_POS 7
#define TMP51X_VBUS_RANGE_32V 32000000
#define TMP51X_VBUS_RANGE_16V 16000000
// Max and Min value
#define MAX_BUS_VOLTAGE_32_LIMIT 32764
#define MAX_BUS_VOLTAGE_16_LIMIT 16382
// Max possible value is -256 to +256 but datasheet indicated -40 to 125.
#define MAX_TEMP_LIMIT 125000
#define MIN_TEMP_LIMIT -40000
#define MAX_TEMP_HYST 127500
static const u8 TMP51X_TEMP_INPUT[4] = {
TMP51X_LOCAL_TEMP_RESULT,
TMP51X_REMOTE_TEMP_RESULT_1,
TMP51X_REMOTE_TEMP_RESULT_2,
TMP513_REMOTE_TEMP_RESULT_3
};
static const u8 TMP51X_TEMP_CRIT[4] = {
TMP51X_LOCAL_TEMP_LIMIT,
TMP51X_REMOTE_TEMP_LIMIT_1,
TMP51X_REMOTE_TEMP_LIMIT_2,
TMP513_REMOTE_TEMP_LIMIT_3
};
static const u8 TMP51X_TEMP_CRIT_ALARM[4] = {
TMP51X_LOCAL_TEMP_LIMIT_POS,
TMP51X_REMOTE_TEMP_LIMIT_1_POS,
TMP51X_REMOTE_TEMP_LIMIT_2_POS,
TMP513_REMOTE_TEMP_LIMIT_3_POS
};
static const u8 TMP51X_TEMP_CRIT_HYST[4] = {
TMP51X_N_FACTOR_AND_HYST_1,
TMP51X_N_FACTOR_AND_HYST_1,
TMP51X_N_FACTOR_AND_HYST_1,
TMP51X_N_FACTOR_AND_HYST_1
};
static const u8 TMP51X_CURR_INPUT[2] = {
TMP51X_SHUNT_CURRENT_RESULT,
TMP51X_BUS_CURRENT_RESULT
};
static struct regmap_config tmp51x_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.max_register = TMP51X_MAX_REGISTER_ADDR,
};
enum tmp51x_ids {
tmp512, tmp513
};
struct tmp51x_data {
u16 shunt_config;
u16 pga_gain;
u32 vbus_range_uvolt;
u16 temp_config;
u32 nfactor[3];
u32 shunt_uohms;
u32 curr_lsb_ua;
u32 pwr_lsb_uw;
enum tmp51x_ids id;
struct regmap *regmap;
};
// Set the shift based on the gain 8=4, 4=3, 2=2, 1=1
static inline u8 tmp51x_get_pga_shift(struct tmp51x_data *data)
{
return 5 - ffs(data->pga_gain);
}
static int tmp51x_get_value(struct tmp51x_data *data, u8 reg, u8 pos,
unsigned int regval, long *val)
{
switch (reg) {
case TMP51X_STATUS:
*val = (regval >> pos) & 1;
break;
case TMP51X_SHUNT_CURRENT_RESULT:
case TMP51X_SHUNT_CURRENT_H_LIMIT:
case TMP51X_SHUNT_CURRENT_L_LIMIT:
/*
* The valus is read in voltage in the chip but reported as
* current to the user.
* 2's complement number shifted by one to four depending
* on the pga gain setting. 1lsb = 10uV
*/
*val = sign_extend32(regval, 17 - tmp51x_get_pga_shift(data));
*val = DIV_ROUND_CLOSEST(*val * 10000, data->shunt_uohms);
break;
case TMP51X_BUS_VOLTAGE_RESULT:
case TMP51X_BUS_VOLTAGE_H_LIMIT:
case TMP51X_BUS_VOLTAGE_L_LIMIT:
// 1lsb = 4mV
*val = (regval >> TMP51X_BUS_VOLTAGE_SHIFT) * 4;
break;
case TMP51X_POWER_RESULT:
case TMP51X_POWER_LIMIT:
// Power = (current * BusVoltage) / 5000
*val = regval * data->pwr_lsb_uw;
break;
case TMP51X_BUS_CURRENT_RESULT:
// Current = (ShuntVoltage * CalibrationRegister) / 4096
*val = sign_extend32(regval, 16) * data->curr_lsb_ua;
*val = DIV_ROUND_CLOSEST(*val, 1000);
break;
case TMP51X_LOCAL_TEMP_RESULT:
case TMP51X_REMOTE_TEMP_RESULT_1:
case TMP51X_REMOTE_TEMP_RESULT_2:
case TMP513_REMOTE_TEMP_RESULT_3:
case TMP51X_LOCAL_TEMP_LIMIT:
case TMP51X_REMOTE_TEMP_LIMIT_1:
case TMP51X_REMOTE_TEMP_LIMIT_2:
case TMP513_REMOTE_TEMP_LIMIT_3:
// 1lsb = 0.0625 degrees centigrade
*val = sign_extend32(regval, 16) >> TMP51X_TEMP_SHIFT;
*val = DIV_ROUND_CLOSEST(*val * 625, 10);
break;
case TMP51X_N_FACTOR_AND_HYST_1:
// 1lsb = 0.5 degrees centigrade
*val = (regval & TMP51X_HYST_MASK) * 500;
break;
default:
// Programmer goofed
WARN_ON_ONCE(1);
*val = 0;
return -EOPNOTSUPP;
}
return 0;
}
static int tmp51x_set_value(struct tmp51x_data *data, u8 reg, long val)
{
int regval, max_val;
u32 mask = 0;
switch (reg) {
case TMP51X_SHUNT_CURRENT_H_LIMIT:
case TMP51X_SHUNT_CURRENT_L_LIMIT:
/*
* The user enter current value and we convert it to
* voltage. 1lsb = 10uV
*/
val = DIV_ROUND_CLOSEST(val * data->shunt_uohms, 10000);
max_val = U16_MAX >> tmp51x_get_pga_shift(data);
regval = clamp_val(val, -max_val, max_val);
break;
case TMP51X_BUS_VOLTAGE_H_LIMIT:
case TMP51X_BUS_VOLTAGE_L_LIMIT:
// 1lsb = 4mV
max_val = (data->vbus_range_uvolt == TMP51X_VBUS_RANGE_32V) ?
MAX_BUS_VOLTAGE_32_LIMIT : MAX_BUS_VOLTAGE_16_LIMIT;
val = clamp_val(DIV_ROUND_CLOSEST(val, 4), 0, max_val);
regval = val << TMP51X_BUS_VOLTAGE_SHIFT;
break;
case TMP51X_POWER_LIMIT:
regval = clamp_val(DIV_ROUND_CLOSEST(val, data->pwr_lsb_uw), 0,
U16_MAX);
break;
case TMP51X_LOCAL_TEMP_LIMIT:
case TMP51X_REMOTE_TEMP_LIMIT_1:
case TMP51X_REMOTE_TEMP_LIMIT_2:
case TMP513_REMOTE_TEMP_LIMIT_3:
// 1lsb = 0.0625 degrees centigrade
val = clamp_val(val, MIN_TEMP_LIMIT, MAX_TEMP_LIMIT);
regval = DIV_ROUND_CLOSEST(val * 10, 625) << TMP51X_TEMP_SHIFT;
break;
case TMP51X_N_FACTOR_AND_HYST_1:
// 1lsb = 0.5 degrees centigrade
val = clamp_val(val, 0, MAX_TEMP_HYST);
regval = DIV_ROUND_CLOSEST(val, 500);
mask = TMP51X_HYST_MASK;
break;
default:
// Programmer goofed
WARN_ON_ONCE(1);
return -EOPNOTSUPP;
}
if (mask == 0)
return regmap_write(data->regmap, reg, regval);
else
return regmap_update_bits(data->regmap, reg, mask, regval);
}
static u8 tmp51x_get_reg(enum hwmon_sensor_types type, u32 attr, int channel)
{
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_input:
return TMP51X_TEMP_INPUT[channel];
case hwmon_temp_crit_alarm:
return TMP51X_STATUS;
case hwmon_temp_crit:
return TMP51X_TEMP_CRIT[channel];
case hwmon_temp_crit_hyst:
return TMP51X_TEMP_CRIT_HYST[channel];
}
break;
case hwmon_in:
switch (attr) {
case hwmon_in_input:
return TMP51X_BUS_VOLTAGE_RESULT;
case hwmon_in_lcrit_alarm:
case hwmon_in_crit_alarm:
return TMP51X_STATUS;
case hwmon_in_lcrit:
return TMP51X_BUS_VOLTAGE_L_LIMIT;
case hwmon_in_crit:
return TMP51X_BUS_VOLTAGE_H_LIMIT;
}
break;
case hwmon_curr:
switch (attr) {
case hwmon_curr_input:
return TMP51X_CURR_INPUT[channel];
case hwmon_curr_lcrit_alarm:
case hwmon_curr_crit_alarm:
return TMP51X_STATUS;
case hwmon_curr_lcrit:
return TMP51X_SHUNT_CURRENT_L_LIMIT;
case hwmon_curr_crit:
return TMP51X_SHUNT_CURRENT_H_LIMIT;
}
break;
case hwmon_power:
switch (attr) {
case hwmon_power_input:
return TMP51X_POWER_RESULT;
case hwmon_power_crit_alarm:
return TMP51X_STATUS;
case hwmon_power_crit:
return TMP51X_POWER_LIMIT;
}
break;
default:
break;
}
return 0;
}
static u8 tmp51x_get_status_pos(enum hwmon_sensor_types type, u32 attr,
int channel)
{
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_crit_alarm:
return TMP51X_TEMP_CRIT_ALARM[channel];
}
break;
case hwmon_in:
switch (attr) {
case hwmon_in_lcrit_alarm:
return TMP51X_BUS_VOLTAGE_L_LIMIT_POS;
case hwmon_in_crit_alarm:
return TMP51X_BUS_VOLTAGE_H_LIMIT_POS;
}
break;
case hwmon_curr:
switch (attr) {
case hwmon_curr_lcrit_alarm:
return TMP51X_SHUNT_CURRENT_L_LIMIT_POS;
case hwmon_curr_crit_alarm:
return TMP51X_SHUNT_CURRENT_H_LIMIT_POS;
}
break;
case hwmon_power:
switch (attr) {
case hwmon_power_crit_alarm:
return TMP51X_POWER_LIMIT_POS;
}
break;
default:
break;
}
return 0;
}
static int tmp51x_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct tmp51x_data *data = dev_get_drvdata(dev);
int ret;
u32 regval;
u8 pos = 0, reg = 0;
reg = tmp51x_get_reg(type, attr, channel);
if (reg == 0)
return -EOPNOTSUPP;
if (reg == TMP51X_STATUS)
pos = tmp51x_get_status_pos(type, attr, channel);
ret = regmap_read(data->regmap, reg, ®val);
if (ret < 0)
return ret;
return tmp51x_get_value(data, reg, pos, regval, val);
}
static int tmp51x_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
u8 reg = 0;
reg = tmp51x_get_reg(type, attr, channel);
if (reg == 0)
return -EOPNOTSUPP;
return tmp51x_set_value(dev_get_drvdata(dev), reg, val);
}
static umode_t tmp51x_is_visible(const void *_data,
enum hwmon_sensor_types type, u32 attr,
int channel)
{
const struct tmp51x_data *data = _data;
switch (type) {
case hwmon_temp:
if (data->id == tmp512 && channel == 3)
return 0;
switch (attr) {
case hwmon_temp_input:
case hwmon_temp_crit_alarm:
return 0444;
case hwmon_temp_crit:
return 0644;
case hwmon_temp_crit_hyst:
if (channel == 0)
return 0644;
return 0444;
}
break;
case hwmon_in:
switch (attr) {
case hwmon_in_input:
case hwmon_in_lcrit_alarm:
case hwmon_in_crit_alarm:
return 0444;
case hwmon_in_lcrit:
case hwmon_in_crit:
return 0644;
}
break;
case hwmon_curr:
if (!data->shunt_uohms)
return 0;
switch (attr) {
case hwmon_curr_input:
case hwmon_curr_lcrit_alarm:
case hwmon_curr_crit_alarm:
return 0444;
case hwmon_curr_lcrit:
case hwmon_curr_crit:
return 0644;
}
break;
case hwmon_power:
if (!data->shunt_uohms)
return 0;
switch (attr) {
case hwmon_power_input:
case hwmon_power_crit_alarm:
return 0444;
case hwmon_power_crit:
return 0644;
}
break;
default:
break;
}
return 0;
}
static const struct hwmon_channel_info * const tmp51x_info[] = {
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
HWMON_T_CRIT_HYST,
HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
HWMON_T_CRIT_HYST,
HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
HWMON_T_CRIT_HYST,
HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
HWMON_T_CRIT_HYST),
HWMON_CHANNEL_INFO(in,
HWMON_I_INPUT | HWMON_I_LCRIT | HWMON_I_LCRIT_ALARM |
HWMON_I_CRIT | HWMON_I_CRIT_ALARM),
HWMON_CHANNEL_INFO(curr,
HWMON_C_INPUT | HWMON_C_LCRIT | HWMON_C_LCRIT_ALARM |
HWMON_C_CRIT | HWMON_C_CRIT_ALARM,
HWMON_C_INPUT),
HWMON_CHANNEL_INFO(power,
HWMON_P_INPUT | HWMON_P_CRIT | HWMON_P_CRIT_ALARM),
NULL
};
static const struct hwmon_ops tmp51x_hwmon_ops = {
.is_visible = tmp51x_is_visible,
.read = tmp51x_read,
.write = tmp51x_write,
};
static const struct hwmon_chip_info tmp51x_chip_info = {
.ops = &tmp51x_hwmon_ops,
.info = tmp51x_info,
};
/*
* Calibrate the tmp51x following the datasheet method
*/
static int tmp51x_calibrate(struct tmp51x_data *data)
{
int vshunt_max = data->pga_gain * 40;
u64 max_curr_ma;
u32 div;
/*
* If shunt_uohms is equal to 0, the calibration should be set to 0.
* The consequence will be that the current and power measurement engine
* of the sensor will not work. Temperature and voltage sensing will
* continue to work.
*/
if (data->shunt_uohms == 0)
return regmap_write(data->regmap, TMP51X_SHUNT_CALIBRATION, 0);
max_curr_ma = DIV_ROUND_CLOSEST_ULL(vshunt_max * 1000 * 1000,
data->shunt_uohms);
/*
* Calculate the minimal bit resolution for the current and the power.
* Those values will be used during register interpretation.
*/
data->curr_lsb_ua = DIV_ROUND_CLOSEST_ULL(max_curr_ma * 1000, 32767);
data->pwr_lsb_uw = 20 * data->curr_lsb_ua;
div = DIV_ROUND_CLOSEST_ULL(data->curr_lsb_ua * data->shunt_uohms,
1000 * 1000);
return regmap_write(data->regmap, TMP51X_SHUNT_CALIBRATION,
DIV_ROUND_CLOSEST(40960, div));
}
/*
* Initialize the configuration and calibration registers.
*/
static int tmp51x_init(struct tmp51x_data *data)
{
unsigned int regval;
int ret = regmap_write(data->regmap, TMP51X_SHUNT_CONFIG,
data->shunt_config);
if (ret < 0)
return ret;
ret = regmap_write(data->regmap, TMP51X_TEMP_CONFIG, data->temp_config);
if (ret < 0)
return ret;
// nFactor configuration
ret = regmap_update_bits(data->regmap, TMP51X_N_FACTOR_AND_HYST_1,
TMP51X_NFACTOR_MASK, data->nfactor[0] << 8);
if (ret < 0)
return ret;
ret = regmap_write(data->regmap, TMP51X_N_FACTOR_2,
data->nfactor[1] << 8);
if (ret < 0)
return ret;
if (data->id == tmp513) {
ret = regmap_write(data->regmap, TMP513_N_FACTOR_3,
data->nfactor[2] << 8);
if (ret < 0)
return ret;
}
ret = tmp51x_calibrate(data);
if (ret < 0)
return ret;
// Read the status register before using as the datasheet propose
return regmap_read(data->regmap, TMP51X_STATUS, ®val);
}
static const struct i2c_device_id tmp51x_id[] = {
{ "tmp512", tmp512 },
{ "tmp513", tmp513 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tmp51x_id);
static const struct of_device_id tmp51x_of_match[] = {
{
.compatible = "ti,tmp512",
.data = (void *)tmp512
},
{
.compatible = "ti,tmp513",
.data = (void *)tmp513
},
{ },
};
MODULE_DEVICE_TABLE(of, tmp51x_of_match);
static int tmp51x_vbus_range_to_reg(struct device *dev,
struct tmp51x_data *data)
{
if (data->vbus_range_uvolt == TMP51X_VBUS_RANGE_32V) {
data->shunt_config |= TMP51X_BUS_VOLTAGE_MASK;
} else if (data->vbus_range_uvolt == TMP51X_VBUS_RANGE_16V) {
data->shunt_config &= ~TMP51X_BUS_VOLTAGE_MASK;
} else {
dev_err(dev, "ti,bus-range-microvolt is invalid: %u\n",
data->vbus_range_uvolt);
return -EINVAL;
}
return 0;
}
static int tmp51x_pga_gain_to_reg(struct device *dev, struct tmp51x_data *data)
{
if (data->pga_gain == 8) {
data->shunt_config |= CURRENT_SENSE_VOLTAGE_320_MASK;
} else if (data->pga_gain == 4) {
data->shunt_config |= CURRENT_SENSE_VOLTAGE_160_MASK;
} else if (data->pga_gain == 2) {
data->shunt_config |= CURRENT_SENSE_VOLTAGE_80_MASK;
} else if (data->pga_gain == 1) {
data->shunt_config |= CURRENT_SENSE_VOLTAGE_40_MASK;
} else {
dev_err(dev, "ti,pga-gain is invalid: %u\n", data->pga_gain);
return -EINVAL;
}
return 0;
}
static int tmp51x_read_properties(struct device *dev, struct tmp51x_data *data)
{
int ret;
u32 nfactor[3];
u32 val;
ret = device_property_read_u32(dev, "shunt-resistor-micro-ohms", &val);
data->shunt_uohms = (ret >= 0) ? val : TMP51X_SHUNT_VALUE_DEFAULT;
ret = device_property_read_u32(dev, "ti,bus-range-microvolt", &val);
data->vbus_range_uvolt = (ret >= 0) ? val : TMP51X_VBUS_RANGE_DEFAULT;
ret = tmp51x_vbus_range_to_reg(dev, data);
if (ret < 0)
return ret;
ret = device_property_read_u32(dev, "ti,pga-gain", &val);
data->pga_gain = (ret >= 0) ? val : TMP51X_PGA_DEFAULT;
ret = tmp51x_pga_gain_to_reg(dev, data);
if (ret < 0)
return ret;
ret = device_property_read_u32_array(dev, "ti,nfactor", nfactor,
(data->id == tmp513) ? 3 : 2);
if (ret >= 0)
memcpy(data->nfactor, nfactor, (data->id == tmp513) ? 3 : 2);
// Check if shunt value is compatible with pga-gain
if (data->shunt_uohms > data->pga_gain * 40 * 1000 * 1000) {
dev_err(dev, "shunt-resistor: %u too big for pga_gain: %u\n",
data->shunt_uohms, data->pga_gain);
return -EINVAL;
}
return 0;
}
static void tmp51x_use_default(struct tmp51x_data *data)
{
data->vbus_range_uvolt = TMP51X_VBUS_RANGE_DEFAULT;
data->pga_gain = TMP51X_PGA_DEFAULT;
data->shunt_uohms = TMP51X_SHUNT_VALUE_DEFAULT;
}
static int tmp51x_configure(struct device *dev, struct tmp51x_data *data)
{
data->shunt_config = TMP51X_SHUNT_CONFIG_DEFAULT;
data->temp_config = (data->id == tmp513) ?
TMP513_TEMP_CONFIG_DEFAULT : TMP512_TEMP_CONFIG_DEFAULT;
if (dev->of_node)
return tmp51x_read_properties(dev, data);
tmp51x_use_default(data);
return 0;
}
static int tmp51x_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct tmp51x_data *data;
struct device *hwmon_dev;
int ret;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->id = (uintptr_t)i2c_get_match_data(client);
ret = tmp51x_configure(dev, data);
if (ret < 0) {
dev_err(dev, "error configuring the device: %d\n", ret);
return ret;
}
data->regmap = devm_regmap_init_i2c(client, &tmp51x_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(dev, "failed to allocate register map\n");
return PTR_ERR(data->regmap);
}
ret = tmp51x_init(data);
if (ret < 0) {
dev_err(dev, "error configuring the device: %d\n", ret);
return -ENODEV;
}
hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
data,
&tmp51x_chip_info,
NULL);
if (IS_ERR(hwmon_dev))
return PTR_ERR(hwmon_dev);
dev_dbg(dev, "power monitor %s\n", client->name);
return 0;
}
static struct i2c_driver tmp51x_driver = {
.driver = {
.name = "tmp51x",
.of_match_table = tmp51x_of_match,
},
.probe = tmp51x_probe,
.id_table = tmp51x_id,
};
module_i2c_driver(tmp51x_driver);
MODULE_AUTHOR("Eric Tremblay <[email protected]>");
MODULE_DESCRIPTION("tmp51x driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/tmp513.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Linear Technology LTC4260 I2C Positive Voltage Hot Swap Controller
*
* Copyright (c) 2014 Guenter Roeck
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/jiffies.h>
#include <linux/regmap.h>
/* chip registers */
#define LTC4260_CONTROL 0x00
#define LTC4260_ALERT 0x01
#define LTC4260_STATUS 0x02
#define LTC4260_FAULT 0x03
#define LTC4260_SENSE 0x04
#define LTC4260_SOURCE 0x05
#define LTC4260_ADIN 0x06
/*
* Fault register bits
*/
#define FAULT_OV (1 << 0)
#define FAULT_UV (1 << 1)
#define FAULT_OC (1 << 2)
#define FAULT_POWER_BAD (1 << 3)
#define FAULT_FET_SHORT (1 << 5)
/* Return the voltage from the given register in mV or mA */
static int ltc4260_get_value(struct device *dev, u8 reg)
{
struct regmap *regmap = dev_get_drvdata(dev);
unsigned int val;
int ret;
ret = regmap_read(regmap, reg, &val);
if (ret < 0)
return ret;
switch (reg) {
case LTC4260_ADIN:
/* 10 mV resolution. Convert to mV. */
val = val * 10;
break;
case LTC4260_SOURCE:
/* 400 mV resolution. Convert to mV. */
val = val * 400;
break;
case LTC4260_SENSE:
/*
* 300 uV resolution. Convert to current as measured with
* an 1 mOhm sense resistor, in mA. If a different sense
* resistor is installed, calculate the actual current by
* dividing the reported current by the sense resistor value
* in mOhm.
*/
val = val * 300;
break;
default:
return -EINVAL;
}
return val;
}
static ssize_t ltc4260_value_show(struct device *dev,
struct device_attribute *da, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
int value;
value = ltc4260_get_value(dev, attr->index);
if (value < 0)
return value;
return sysfs_emit(buf, "%d\n", value);
}
static ssize_t ltc4260_bool_show(struct device *dev,
struct device_attribute *da, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
struct regmap *regmap = dev_get_drvdata(dev);
unsigned int fault;
int ret;
ret = regmap_read(regmap, LTC4260_FAULT, &fault);
if (ret < 0)
return ret;
fault &= attr->index;
if (fault) /* Clear reported faults in chip register */
regmap_update_bits(regmap, LTC4260_FAULT, attr->index, 0);
return sysfs_emit(buf, "%d\n", !!fault);
}
/* Voltages */
static SENSOR_DEVICE_ATTR_RO(in1_input, ltc4260_value, LTC4260_SOURCE);
static SENSOR_DEVICE_ATTR_RO(in2_input, ltc4260_value, LTC4260_ADIN);
/*
* Voltage alarms
* UV/OV faults are associated with the input voltage, and the POWER BAD and
* FET SHORT faults are associated with the output voltage.
*/
static SENSOR_DEVICE_ATTR_RO(in1_min_alarm, ltc4260_bool, FAULT_UV);
static SENSOR_DEVICE_ATTR_RO(in1_max_alarm, ltc4260_bool, FAULT_OV);
static SENSOR_DEVICE_ATTR_RO(in2_alarm, ltc4260_bool,
FAULT_POWER_BAD | FAULT_FET_SHORT);
/* Current (via sense resistor) */
static SENSOR_DEVICE_ATTR_RO(curr1_input, ltc4260_value, LTC4260_SENSE);
/* Overcurrent alarm */
static SENSOR_DEVICE_ATTR_RO(curr1_max_alarm, ltc4260_bool, FAULT_OC);
static struct attribute *ltc4260_attrs[] = {
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in1_min_alarm.dev_attr.attr,
&sensor_dev_attr_in1_max_alarm.dev_attr.attr,
&sensor_dev_attr_in2_input.dev_attr.attr,
&sensor_dev_attr_in2_alarm.dev_attr.attr,
&sensor_dev_attr_curr1_input.dev_attr.attr,
&sensor_dev_attr_curr1_max_alarm.dev_attr.attr,
NULL,
};
ATTRIBUTE_GROUPS(ltc4260);
static const struct regmap_config ltc4260_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = LTC4260_ADIN,
};
static int ltc4260_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct device *hwmon_dev;
struct regmap *regmap;
regmap = devm_regmap_init_i2c(client, <c4260_regmap_config);
if (IS_ERR(regmap)) {
dev_err(dev, "failed to allocate register map\n");
return PTR_ERR(regmap);
}
/* Clear faults */
regmap_write(regmap, LTC4260_FAULT, 0x00);
hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
regmap,
ltc4260_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id ltc4260_id[] = {
{"ltc4260", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, ltc4260_id);
static struct i2c_driver ltc4260_driver = {
.driver = {
.name = "ltc4260",
},
.probe = ltc4260_probe,
.id_table = ltc4260_id,
};
module_i2c_driver(ltc4260_driver);
MODULE_AUTHOR("Guenter Roeck <[email protected]>");
MODULE_DESCRIPTION("LTC4260 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/ltc4260.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* max6639.c - Support for Maxim MAX6639
*
* 2-Channel Temperature Monitor with Dual PWM Fan-Speed Controller
*
* Copyright (C) 2010, 2011 Roland Stigge <[email protected]>
*
* based on the initial MAX6639 support from semptian.net
* by He Changqing <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/platform_data/max6639.h>
/* Addresses to scan */
static const unsigned short normal_i2c[] = { 0x2c, 0x2e, 0x2f, I2C_CLIENT_END };
/* The MAX6639 registers, valid channel numbers: 0, 1 */
#define MAX6639_REG_TEMP(ch) (0x00 + (ch))
#define MAX6639_REG_STATUS 0x02
#define MAX6639_REG_OUTPUT_MASK 0x03
#define MAX6639_REG_GCONFIG 0x04
#define MAX6639_REG_TEMP_EXT(ch) (0x05 + (ch))
#define MAX6639_REG_ALERT_LIMIT(ch) (0x08 + (ch))
#define MAX6639_REG_OT_LIMIT(ch) (0x0A + (ch))
#define MAX6639_REG_THERM_LIMIT(ch) (0x0C + (ch))
#define MAX6639_REG_FAN_CONFIG1(ch) (0x10 + (ch) * 4)
#define MAX6639_REG_FAN_CONFIG2a(ch) (0x11 + (ch) * 4)
#define MAX6639_REG_FAN_CONFIG2b(ch) (0x12 + (ch) * 4)
#define MAX6639_REG_FAN_CONFIG3(ch) (0x13 + (ch) * 4)
#define MAX6639_REG_FAN_CNT(ch) (0x20 + (ch))
#define MAX6639_REG_TARGET_CNT(ch) (0x22 + (ch))
#define MAX6639_REG_FAN_PPR(ch) (0x24 + (ch))
#define MAX6639_REG_TARGTDUTY(ch) (0x26 + (ch))
#define MAX6639_REG_FAN_START_TEMP(ch) (0x28 + (ch))
#define MAX6639_REG_DEVID 0x3D
#define MAX6639_REG_MANUID 0x3E
#define MAX6639_REG_DEVREV 0x3F
/* Register bits */
#define MAX6639_GCONFIG_STANDBY 0x80
#define MAX6639_GCONFIG_POR 0x40
#define MAX6639_GCONFIG_DISABLE_TIMEOUT 0x20
#define MAX6639_GCONFIG_CH2_LOCAL 0x10
#define MAX6639_GCONFIG_PWM_FREQ_HI 0x08
#define MAX6639_FAN_CONFIG1_PWM 0x80
#define MAX6639_FAN_CONFIG3_THERM_FULL_SPEED 0x40
static const int rpm_ranges[] = { 2000, 4000, 8000, 16000 };
#define FAN_FROM_REG(val, rpm_range) ((val) == 0 || (val) == 255 ? \
0 : (rpm_ranges[rpm_range] * 30) / (val))
#define TEMP_LIMIT_TO_REG(val) clamp_val((val) / 1000, 0, 255)
/*
* Client data (each client gets its own)
*/
struct max6639_data {
struct i2c_client *client;
struct mutex update_lock;
bool valid; /* true if following fields are valid */
unsigned long last_updated; /* In jiffies */
/* Register values sampled regularly */
u16 temp[2]; /* Temperature, in 1/8 C, 0..255 C */
bool temp_fault[2]; /* Detected temperature diode failure */
u8 fan[2]; /* Register value: TACH count for fans >=30 */
u8 status; /* Detected channel alarms and fan failures */
/* Register values only written to */
u8 pwm[2]; /* Register value: Duty cycle 0..120 */
u8 temp_therm[2]; /* THERM Temperature, 0..255 C (->_max) */
u8 temp_alert[2]; /* ALERT Temperature, 0..255 C (->_crit) */
u8 temp_ot[2]; /* OT Temperature, 0..255 C (->_emergency) */
/* Register values initialized only once */
u8 ppr; /* Pulses per rotation 0..3 for 1..4 ppr */
u8 rpm_range; /* Index in above rpm_ranges table */
/* Optional regulator for FAN supply */
struct regulator *reg;
};
static struct max6639_data *max6639_update_device(struct device *dev)
{
struct max6639_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
struct max6639_data *ret = data;
int i;
int status_reg;
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + 2 * HZ) || !data->valid) {
int res;
dev_dbg(&client->dev, "Starting max6639 update\n");
status_reg = i2c_smbus_read_byte_data(client,
MAX6639_REG_STATUS);
if (status_reg < 0) {
ret = ERR_PTR(status_reg);
goto abort;
}
data->status = status_reg;
for (i = 0; i < 2; i++) {
res = i2c_smbus_read_byte_data(client,
MAX6639_REG_FAN_CNT(i));
if (res < 0) {
ret = ERR_PTR(res);
goto abort;
}
data->fan[i] = res;
res = i2c_smbus_read_byte_data(client,
MAX6639_REG_TEMP_EXT(i));
if (res < 0) {
ret = ERR_PTR(res);
goto abort;
}
data->temp[i] = res >> 5;
data->temp_fault[i] = res & 0x01;
res = i2c_smbus_read_byte_data(client,
MAX6639_REG_TEMP(i));
if (res < 0) {
ret = ERR_PTR(res);
goto abort;
}
data->temp[i] |= res << 3;
}
data->last_updated = jiffies;
data->valid = true;
}
abort:
mutex_unlock(&data->update_lock);
return ret;
}
static ssize_t temp_input_show(struct device *dev,
struct device_attribute *dev_attr, char *buf)
{
long temp;
struct max6639_data *data = max6639_update_device(dev);
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
if (IS_ERR(data))
return PTR_ERR(data);
temp = data->temp[attr->index] * 125;
return sprintf(buf, "%ld\n", temp);
}
static ssize_t temp_fault_show(struct device *dev,
struct device_attribute *dev_attr, char *buf)
{
struct max6639_data *data = max6639_update_device(dev);
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
if (IS_ERR(data))
return PTR_ERR(data);
return sprintf(buf, "%d\n", data->temp_fault[attr->index]);
}
static ssize_t temp_max_show(struct device *dev,
struct device_attribute *dev_attr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
struct max6639_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", (data->temp_therm[attr->index] * 1000));
}
static ssize_t temp_max_store(struct device *dev,
struct device_attribute *dev_attr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
struct max6639_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
unsigned long val;
int res;
res = kstrtoul(buf, 10, &val);
if (res)
return res;
mutex_lock(&data->update_lock);
data->temp_therm[attr->index] = TEMP_LIMIT_TO_REG(val);
i2c_smbus_write_byte_data(client,
MAX6639_REG_THERM_LIMIT(attr->index),
data->temp_therm[attr->index]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t temp_crit_show(struct device *dev,
struct device_attribute *dev_attr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
struct max6639_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", (data->temp_alert[attr->index] * 1000));
}
static ssize_t temp_crit_store(struct device *dev,
struct device_attribute *dev_attr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
struct max6639_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
unsigned long val;
int res;
res = kstrtoul(buf, 10, &val);
if (res)
return res;
mutex_lock(&data->update_lock);
data->temp_alert[attr->index] = TEMP_LIMIT_TO_REG(val);
i2c_smbus_write_byte_data(client,
MAX6639_REG_ALERT_LIMIT(attr->index),
data->temp_alert[attr->index]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t temp_emergency_show(struct device *dev,
struct device_attribute *dev_attr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
struct max6639_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", (data->temp_ot[attr->index] * 1000));
}
static ssize_t temp_emergency_store(struct device *dev,
struct device_attribute *dev_attr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
struct max6639_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
unsigned long val;
int res;
res = kstrtoul(buf, 10, &val);
if (res)
return res;
mutex_lock(&data->update_lock);
data->temp_ot[attr->index] = TEMP_LIMIT_TO_REG(val);
i2c_smbus_write_byte_data(client,
MAX6639_REG_OT_LIMIT(attr->index),
data->temp_ot[attr->index]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t pwm_show(struct device *dev, struct device_attribute *dev_attr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
struct max6639_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", data->pwm[attr->index] * 255 / 120);
}
static ssize_t pwm_store(struct device *dev,
struct device_attribute *dev_attr, const char *buf,
size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
struct max6639_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
unsigned long val;
int res;
res = kstrtoul(buf, 10, &val);
if (res)
return res;
val = clamp_val(val, 0, 255);
mutex_lock(&data->update_lock);
data->pwm[attr->index] = (u8)(val * 120 / 255);
i2c_smbus_write_byte_data(client,
MAX6639_REG_TARGTDUTY(attr->index),
data->pwm[attr->index]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t fan_input_show(struct device *dev,
struct device_attribute *dev_attr, char *buf)
{
struct max6639_data *data = max6639_update_device(dev);
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
if (IS_ERR(data))
return PTR_ERR(data);
return sprintf(buf, "%d\n", FAN_FROM_REG(data->fan[attr->index],
data->rpm_range));
}
static ssize_t alarm_show(struct device *dev,
struct device_attribute *dev_attr, char *buf)
{
struct max6639_data *data = max6639_update_device(dev);
struct sensor_device_attribute *attr = to_sensor_dev_attr(dev_attr);
if (IS_ERR(data))
return PTR_ERR(data);
return sprintf(buf, "%d\n", !!(data->status & (1 << attr->index)));
}
static SENSOR_DEVICE_ATTR_RO(temp1_input, temp_input, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_input, temp_input, 1);
static SENSOR_DEVICE_ATTR_RO(temp1_fault, temp_fault, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_fault, temp_fault, 1);
static SENSOR_DEVICE_ATTR_RW(temp1_max, temp_max, 0);
static SENSOR_DEVICE_ATTR_RW(temp2_max, temp_max, 1);
static SENSOR_DEVICE_ATTR_RW(temp1_crit, temp_crit, 0);
static SENSOR_DEVICE_ATTR_RW(temp2_crit, temp_crit, 1);
static SENSOR_DEVICE_ATTR_RW(temp1_emergency, temp_emergency, 0);
static SENSOR_DEVICE_ATTR_RW(temp2_emergency, temp_emergency, 1);
static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1);
static SENSOR_DEVICE_ATTR_RO(fan1_input, fan_input, 0);
static SENSOR_DEVICE_ATTR_RO(fan2_input, fan_input, 1);
static SENSOR_DEVICE_ATTR_RO(fan1_fault, alarm, 1);
static SENSOR_DEVICE_ATTR_RO(fan2_fault, alarm, 0);
static SENSOR_DEVICE_ATTR_RO(temp1_max_alarm, alarm, 3);
static SENSOR_DEVICE_ATTR_RO(temp2_max_alarm, alarm, 2);
static SENSOR_DEVICE_ATTR_RO(temp1_crit_alarm, alarm, 7);
static SENSOR_DEVICE_ATTR_RO(temp2_crit_alarm, alarm, 6);
static SENSOR_DEVICE_ATTR_RO(temp1_emergency_alarm, alarm, 5);
static SENSOR_DEVICE_ATTR_RO(temp2_emergency_alarm, alarm, 4);
static struct attribute *max6639_attrs[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp1_fault.dev_attr.attr,
&sensor_dev_attr_temp2_fault.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp2_max.dev_attr.attr,
&sensor_dev_attr_temp1_crit.dev_attr.attr,
&sensor_dev_attr_temp2_crit.dev_attr.attr,
&sensor_dev_attr_temp1_emergency.dev_attr.attr,
&sensor_dev_attr_temp2_emergency.dev_attr.attr,
&sensor_dev_attr_pwm1.dev_attr.attr,
&sensor_dev_attr_pwm2.dev_attr.attr,
&sensor_dev_attr_fan1_input.dev_attr.attr,
&sensor_dev_attr_fan2_input.dev_attr.attr,
&sensor_dev_attr_fan1_fault.dev_attr.attr,
&sensor_dev_attr_fan2_fault.dev_attr.attr,
&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_crit_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_emergency_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_emergency_alarm.dev_attr.attr,
NULL
};
ATTRIBUTE_GROUPS(max6639);
/*
* returns respective index in rpm_ranges table
* 1 by default on invalid range
*/
static int rpm_range_to_reg(int range)
{
int i;
for (i = 0; i < ARRAY_SIZE(rpm_ranges); i++) {
if (rpm_ranges[i] == range)
return i;
}
return 1; /* default: 4000 RPM */
}
static int max6639_init_client(struct i2c_client *client,
struct max6639_data *data)
{
struct max6639_platform_data *max6639_info =
dev_get_platdata(&client->dev);
int i;
int rpm_range = 1; /* default: 4000 RPM */
int err;
/* Reset chip to default values, see below for GCONFIG setup */
err = i2c_smbus_write_byte_data(client, MAX6639_REG_GCONFIG,
MAX6639_GCONFIG_POR);
if (err)
goto exit;
/* Fans pulse per revolution is 2 by default */
if (max6639_info && max6639_info->ppr > 0 &&
max6639_info->ppr < 5)
data->ppr = max6639_info->ppr;
else
data->ppr = 2;
data->ppr -= 1;
if (max6639_info)
rpm_range = rpm_range_to_reg(max6639_info->rpm_range);
data->rpm_range = rpm_range;
for (i = 0; i < 2; i++) {
/* Set Fan pulse per revolution */
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_FAN_PPR(i),
data->ppr << 6);
if (err)
goto exit;
/* Fans config PWM, RPM */
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_FAN_CONFIG1(i),
MAX6639_FAN_CONFIG1_PWM | rpm_range);
if (err)
goto exit;
/* Fans PWM polarity high by default */
if (max6639_info && max6639_info->pwm_polarity == 0)
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_FAN_CONFIG2a(i), 0x00);
else
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_FAN_CONFIG2a(i), 0x02);
if (err)
goto exit;
/*
* /THERM full speed enable,
* PWM frequency 25kHz, see also GCONFIG below
*/
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_FAN_CONFIG3(i),
MAX6639_FAN_CONFIG3_THERM_FULL_SPEED | 0x03);
if (err)
goto exit;
/* Max. temp. 80C/90C/100C */
data->temp_therm[i] = 80;
data->temp_alert[i] = 90;
data->temp_ot[i] = 100;
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_THERM_LIMIT(i),
data->temp_therm[i]);
if (err)
goto exit;
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_ALERT_LIMIT(i),
data->temp_alert[i]);
if (err)
goto exit;
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_OT_LIMIT(i), data->temp_ot[i]);
if (err)
goto exit;
/* PWM 120/120 (i.e. 100%) */
data->pwm[i] = 120;
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_TARGTDUTY(i), data->pwm[i]);
if (err)
goto exit;
}
/* Start monitoring */
err = i2c_smbus_write_byte_data(client, MAX6639_REG_GCONFIG,
MAX6639_GCONFIG_DISABLE_TIMEOUT | MAX6639_GCONFIG_CH2_LOCAL |
MAX6639_GCONFIG_PWM_FREQ_HI);
exit:
return err;
}
/* Return 0 if detection is successful, -ENODEV otherwise */
static int max6639_detect(struct i2c_client *client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
int dev_id, manu_id;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
/* Actual detection via device and manufacturer ID */
dev_id = i2c_smbus_read_byte_data(client, MAX6639_REG_DEVID);
manu_id = i2c_smbus_read_byte_data(client, MAX6639_REG_MANUID);
if (dev_id != 0x58 || manu_id != 0x4D)
return -ENODEV;
strscpy(info->type, "max6639", I2C_NAME_SIZE);
return 0;
}
static void max6639_regulator_disable(void *data)
{
regulator_disable(data);
}
static int max6639_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct max6639_data *data;
struct device *hwmon_dev;
int err;
data = devm_kzalloc(dev, sizeof(struct max6639_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
data->reg = devm_regulator_get_optional(dev, "fan");
if (IS_ERR(data->reg)) {
if (PTR_ERR(data->reg) != -ENODEV)
return PTR_ERR(data->reg);
data->reg = NULL;
} else {
/* Spin up fans */
err = regulator_enable(data->reg);
if (err) {
dev_err(dev, "Failed to enable fan supply: %d\n", err);
return err;
}
err = devm_add_action_or_reset(dev, max6639_regulator_disable,
data->reg);
if (err) {
dev_err(dev, "Failed to register action: %d\n", err);
return err;
}
}
mutex_init(&data->update_lock);
/* Initialize the max6639 chip */
err = max6639_init_client(client, data);
if (err < 0)
return err;
hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
data,
max6639_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static int max6639_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct max6639_data *data = dev_get_drvdata(dev);
int ret = i2c_smbus_read_byte_data(client, MAX6639_REG_GCONFIG);
if (ret < 0)
return ret;
if (data->reg)
regulator_disable(data->reg);
return i2c_smbus_write_byte_data(client,
MAX6639_REG_GCONFIG, ret | MAX6639_GCONFIG_STANDBY);
}
static int max6639_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct max6639_data *data = dev_get_drvdata(dev);
int ret;
if (data->reg) {
ret = regulator_enable(data->reg);
if (ret) {
dev_err(dev, "Failed to enable fan supply: %d\n", ret);
return ret;
}
}
ret = i2c_smbus_read_byte_data(client, MAX6639_REG_GCONFIG);
if (ret < 0)
return ret;
return i2c_smbus_write_byte_data(client,
MAX6639_REG_GCONFIG, ret & ~MAX6639_GCONFIG_STANDBY);
}
static const struct i2c_device_id max6639_id[] = {
{"max6639", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, max6639_id);
static DEFINE_SIMPLE_DEV_PM_OPS(max6639_pm_ops, max6639_suspend, max6639_resume);
static const struct of_device_id max6639_of_match[] = {
{ .compatible = "maxim,max6639", },
{ },
};
static struct i2c_driver max6639_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "max6639",
.pm = pm_sleep_ptr(&max6639_pm_ops),
.of_match_table = max6639_of_match,
},
.probe = max6639_probe,
.id_table = max6639_id,
.detect = max6639_detect,
.address_list = normal_i2c,
};
module_i2c_driver(max6639_driver);
MODULE_AUTHOR("Roland Stigge <[email protected]>");
MODULE_DESCRIPTION("max6639 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/max6639.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* via-cputemp.c - Driver for VIA CPU core temperature monitoring
* Copyright (C) 2009 VIA Technologies, Inc.
*
* based on existing coretemp.c, which is
*
* Copyright (C) 2007 Rudolf Marek <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/hwmon.h>
#include <linux/hwmon-vid.h>
#include <linux/sysfs.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/cpu.h>
#include <asm/msr.h>
#include <asm/processor.h>
#include <asm/cpu_device_id.h>
#define DRVNAME "via_cputemp"
enum { SHOW_TEMP, SHOW_LABEL, SHOW_NAME };
/*
* Functions declaration
*/
struct via_cputemp_data {
struct device *hwmon_dev;
const char *name;
u8 vrm;
u32 id;
u32 msr_temp;
u32 msr_vid;
};
/*
* Sysfs stuff
*/
static ssize_t name_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
int ret;
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct via_cputemp_data *data = dev_get_drvdata(dev);
if (attr->index == SHOW_NAME)
ret = sprintf(buf, "%s\n", data->name);
else /* show label */
ret = sprintf(buf, "Core %d\n", data->id);
return ret;
}
static ssize_t temp_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct via_cputemp_data *data = dev_get_drvdata(dev);
u32 eax, edx;
int err;
err = rdmsr_safe_on_cpu(data->id, data->msr_temp, &eax, &edx);
if (err)
return -EAGAIN;
return sprintf(buf, "%lu\n", ((unsigned long)eax & 0xffffff) * 1000);
}
static ssize_t cpu0_vid_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct via_cputemp_data *data = dev_get_drvdata(dev);
u32 eax, edx;
int err;
err = rdmsr_safe_on_cpu(data->id, data->msr_vid, &eax, &edx);
if (err)
return -EAGAIN;
return sprintf(buf, "%d\n", vid_from_reg(~edx & 0x7f, data->vrm));
}
static SENSOR_DEVICE_ATTR_RO(temp1_input, temp, SHOW_TEMP);
static SENSOR_DEVICE_ATTR_RO(temp1_label, name, SHOW_LABEL);
static SENSOR_DEVICE_ATTR_RO(name, name, SHOW_NAME);
static struct attribute *via_cputemp_attributes[] = {
&sensor_dev_attr_name.dev_attr.attr,
&sensor_dev_attr_temp1_label.dev_attr.attr,
&sensor_dev_attr_temp1_input.dev_attr.attr,
NULL
};
static const struct attribute_group via_cputemp_group = {
.attrs = via_cputemp_attributes,
};
/* Optional attributes */
static DEVICE_ATTR_RO(cpu0_vid);
static int via_cputemp_probe(struct platform_device *pdev)
{
struct via_cputemp_data *data;
struct cpuinfo_x86 *c = &cpu_data(pdev->id);
int err;
u32 eax, edx;
data = devm_kzalloc(&pdev->dev, sizeof(struct via_cputemp_data),
GFP_KERNEL);
if (!data)
return -ENOMEM;
data->id = pdev->id;
data->name = "via_cputemp";
if (c->x86 == 7) {
data->msr_temp = 0x1423;
} else {
switch (c->x86_model) {
case 0xA:
/* C7 A */
case 0xD:
/* C7 D */
data->msr_temp = 0x1169;
data->msr_vid = 0x198;
break;
case 0xF:
/* Nano */
data->msr_temp = 0x1423;
break;
default:
return -ENODEV;
}
}
/* test if we can access the TEMPERATURE MSR */
err = rdmsr_safe_on_cpu(data->id, data->msr_temp, &eax, &edx);
if (err) {
dev_err(&pdev->dev,
"Unable to access TEMPERATURE MSR, giving up\n");
return err;
}
platform_set_drvdata(pdev, data);
err = sysfs_create_group(&pdev->dev.kobj, &via_cputemp_group);
if (err)
return err;
if (data->msr_vid)
data->vrm = vid_which_vrm();
if (data->vrm) {
err = device_create_file(&pdev->dev, &dev_attr_cpu0_vid);
if (err)
goto exit_remove;
}
data->hwmon_dev = hwmon_device_register(&pdev->dev);
if (IS_ERR(data->hwmon_dev)) {
err = PTR_ERR(data->hwmon_dev);
dev_err(&pdev->dev, "Class registration failed (%d)\n",
err);
goto exit_remove;
}
return 0;
exit_remove:
if (data->vrm)
device_remove_file(&pdev->dev, &dev_attr_cpu0_vid);
sysfs_remove_group(&pdev->dev.kobj, &via_cputemp_group);
return err;
}
static int via_cputemp_remove(struct platform_device *pdev)
{
struct via_cputemp_data *data = platform_get_drvdata(pdev);
hwmon_device_unregister(data->hwmon_dev);
if (data->vrm)
device_remove_file(&pdev->dev, &dev_attr_cpu0_vid);
sysfs_remove_group(&pdev->dev.kobj, &via_cputemp_group);
return 0;
}
static struct platform_driver via_cputemp_driver = {
.driver = {
.name = DRVNAME,
},
.probe = via_cputemp_probe,
.remove = via_cputemp_remove,
};
struct pdev_entry {
struct list_head list;
struct platform_device *pdev;
unsigned int cpu;
};
static LIST_HEAD(pdev_list);
static DEFINE_MUTEX(pdev_list_mutex);
static int via_cputemp_online(unsigned int cpu)
{
int err;
struct platform_device *pdev;
struct pdev_entry *pdev_entry;
pdev = platform_device_alloc(DRVNAME, cpu);
if (!pdev) {
err = -ENOMEM;
pr_err("Device allocation failed\n");
goto exit;
}
pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL);
if (!pdev_entry) {
err = -ENOMEM;
goto exit_device_put;
}
err = platform_device_add(pdev);
if (err) {
pr_err("Device addition failed (%d)\n", err);
goto exit_device_free;
}
pdev_entry->pdev = pdev;
pdev_entry->cpu = cpu;
mutex_lock(&pdev_list_mutex);
list_add_tail(&pdev_entry->list, &pdev_list);
mutex_unlock(&pdev_list_mutex);
return 0;
exit_device_free:
kfree(pdev_entry);
exit_device_put:
platform_device_put(pdev);
exit:
return err;
}
static int via_cputemp_down_prep(unsigned int cpu)
{
struct pdev_entry *p;
mutex_lock(&pdev_list_mutex);
list_for_each_entry(p, &pdev_list, list) {
if (p->cpu == cpu) {
platform_device_unregister(p->pdev);
list_del(&p->list);
mutex_unlock(&pdev_list_mutex);
kfree(p);
return 0;
}
}
mutex_unlock(&pdev_list_mutex);
return 0;
}
static const struct x86_cpu_id __initconst cputemp_ids[] = {
X86_MATCH_VENDOR_FAM_MODEL(CENTAUR, 6, X86_CENTAUR_FAM6_C7_A, NULL),
X86_MATCH_VENDOR_FAM_MODEL(CENTAUR, 6, X86_CENTAUR_FAM6_C7_D, NULL),
X86_MATCH_VENDOR_FAM_MODEL(CENTAUR, 6, X86_CENTAUR_FAM6_NANO, NULL),
X86_MATCH_VENDOR_FAM_MODEL(CENTAUR, 7, X86_MODEL_ANY, NULL),
{}
};
MODULE_DEVICE_TABLE(x86cpu, cputemp_ids);
static enum cpuhp_state via_temp_online;
static int __init via_cputemp_init(void)
{
int err;
if (!x86_match_cpu(cputemp_ids))
return -ENODEV;
err = platform_driver_register(&via_cputemp_driver);
if (err)
goto exit;
err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hwmon/via:online",
via_cputemp_online, via_cputemp_down_prep);
if (err < 0)
goto exit_driver_unreg;
via_temp_online = err;
#ifndef CONFIG_HOTPLUG_CPU
if (list_empty(&pdev_list)) {
err = -ENODEV;
goto exit_hp_unreg;
}
#endif
return 0;
#ifndef CONFIG_HOTPLUG_CPU
exit_hp_unreg:
cpuhp_remove_state_nocalls(via_temp_online);
#endif
exit_driver_unreg:
platform_driver_unregister(&via_cputemp_driver);
exit:
return err;
}
static void __exit via_cputemp_exit(void)
{
cpuhp_remove_state(via_temp_online);
platform_driver_unregister(&via_cputemp_driver);
}
MODULE_AUTHOR("Harald Welte <[email protected]>");
MODULE_DESCRIPTION("VIA CPU temperature monitor");
MODULE_LICENSE("GPL");
module_init(via_cputemp_init)
module_exit(via_cputemp_exit)
|
linux-master
|
drivers/hwmon/via-cputemp.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/hwmon/nsa320-hwmon.c
*
* ZyXEL NSA320 Media Servers
* hardware monitoring
*
* Copyright (C) 2016 Adam Baker <[email protected]>
* based on a board file driver
* Copyright (C) 2012 Peter Schildmann <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
/* Tests for error return values rely upon this value being < 0x80 */
#define MAGIC_NUMBER 0x55
/*
* The Zyxel hwmon MCU is a Holtek HT46R065 that is factory programmed
* to perform temperature and fan speed monitoring. It is read by taking
* the active pin low. The 32 bit output word is then clocked onto the
* data line. The MSB of the data word is a magic nuber to indicate it
* has been read correctly, the next byte is the fan speed (in hundreds
* of RPM) and the last two bytes are the temperature (in tenths of a
* degree)
*/
struct nsa320_hwmon {
struct mutex update_lock; /* lock GPIO operations */
unsigned long last_updated; /* jiffies */
unsigned long mcu_data;
struct gpio_desc *act;
struct gpio_desc *clk;
struct gpio_desc *data;
};
enum nsa320_inputs {
NSA320_TEMP = 0,
NSA320_FAN = 1,
};
static const char * const nsa320_input_names[] = {
[NSA320_TEMP] = "System Temperature",
[NSA320_FAN] = "Chassis Fan",
};
/*
* Although this protocol looks similar to SPI the long delay
* between the active (aka chip select) signal and the shorter
* delay between clock pulses are needed for reliable operation.
* The delays provided are taken from the manufacturer kernel,
* testing suggest they probably incorporate a reasonable safety
* margin. (The single device tested became unreliable if the
* delay was reduced to 1/10th of this value.)
*/
static s32 nsa320_hwmon_update(struct device *dev)
{
u32 mcu_data;
u32 mask;
struct nsa320_hwmon *hwmon = dev_get_drvdata(dev);
mutex_lock(&hwmon->update_lock);
mcu_data = hwmon->mcu_data;
if (time_after(jiffies, hwmon->last_updated + HZ) || mcu_data == 0) {
gpiod_set_value(hwmon->act, 1);
msleep(100);
mcu_data = 0;
for (mask = BIT(31); mask; mask >>= 1) {
gpiod_set_value(hwmon->clk, 0);
usleep_range(100, 200);
gpiod_set_value(hwmon->clk, 1);
usleep_range(100, 200);
if (gpiod_get_value(hwmon->data))
mcu_data |= mask;
}
gpiod_set_value(hwmon->act, 0);
dev_dbg(dev, "Read raw MCU data %08x\n", mcu_data);
if ((mcu_data >> 24) != MAGIC_NUMBER) {
dev_dbg(dev, "Read invalid MCU data %08x\n", mcu_data);
mcu_data = -EIO;
} else {
hwmon->mcu_data = mcu_data;
hwmon->last_updated = jiffies;
}
}
mutex_unlock(&hwmon->update_lock);
return mcu_data;
}
static ssize_t label_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int channel = to_sensor_dev_attr(attr)->index;
return sprintf(buf, "%s\n", nsa320_input_names[channel]);
}
static ssize_t temp1_input_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
s32 mcu_data = nsa320_hwmon_update(dev);
if (mcu_data < 0)
return mcu_data;
return sprintf(buf, "%d\n", (mcu_data & 0xffff) * 100);
}
static ssize_t fan1_input_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
s32 mcu_data = nsa320_hwmon_update(dev);
if (mcu_data < 0)
return mcu_data;
return sprintf(buf, "%d\n", ((mcu_data & 0xff0000) >> 16) * 100);
}
static SENSOR_DEVICE_ATTR_RO(temp1_label, label, NSA320_TEMP);
static DEVICE_ATTR_RO(temp1_input);
static SENSOR_DEVICE_ATTR_RO(fan1_label, label, NSA320_FAN);
static DEVICE_ATTR_RO(fan1_input);
static struct attribute *nsa320_attrs[] = {
&sensor_dev_attr_temp1_label.dev_attr.attr,
&dev_attr_temp1_input.attr,
&sensor_dev_attr_fan1_label.dev_attr.attr,
&dev_attr_fan1_input.attr,
NULL
};
ATTRIBUTE_GROUPS(nsa320);
static const struct of_device_id of_nsa320_hwmon_match[] = {
{ .compatible = "zyxel,nsa320-mcu", },
{ },
};
static int nsa320_hwmon_probe(struct platform_device *pdev)
{
struct nsa320_hwmon *hwmon;
struct device *classdev;
hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
if (!hwmon)
return -ENOMEM;
/* Look up the GPIO pins to use */
hwmon->act = devm_gpiod_get(&pdev->dev, "act", GPIOD_OUT_LOW);
if (IS_ERR(hwmon->act))
return PTR_ERR(hwmon->act);
hwmon->clk = devm_gpiod_get(&pdev->dev, "clk", GPIOD_OUT_HIGH);
if (IS_ERR(hwmon->clk))
return PTR_ERR(hwmon->clk);
hwmon->data = devm_gpiod_get(&pdev->dev, "data", GPIOD_IN);
if (IS_ERR(hwmon->data))
return PTR_ERR(hwmon->data);
mutex_init(&hwmon->update_lock);
classdev = devm_hwmon_device_register_with_groups(&pdev->dev,
"nsa320", hwmon, nsa320_groups);
return PTR_ERR_OR_ZERO(classdev);
}
/* All allocations use devres so remove() is not needed. */
static struct platform_driver nsa320_hwmon_driver = {
.probe = nsa320_hwmon_probe,
.driver = {
.name = "nsa320-hwmon",
.of_match_table = of_nsa320_hwmon_match,
},
};
module_platform_driver(nsa320_hwmon_driver);
MODULE_DEVICE_TABLE(of, of_nsa320_hwmon_match);
MODULE_AUTHOR("Peter Schildmann <[email protected]>");
MODULE_AUTHOR("Adam Baker <[email protected]>");
MODULE_DESCRIPTION("NSA320 Hardware Monitoring");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:nsa320-hwmon");
|
linux-master
|
drivers/hwmon/nsa320-hwmon.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for the Texas Instruments / Burr Brown INA209
* Bidirectional Current/Power Monitor
*
* Copyright (C) 2012 Guenter Roeck <[email protected]>
*
* Derived from Ira W. Snyder's original driver submission
* Copyright (C) 2008 Paul Hays <[email protected]>
* Copyright (C) 2008-2009 Ira W. Snyder <[email protected]>
*
* Aligned with ina2xx driver
* Copyright (C) 2012 Lothar Felten <[email protected]>
* Thanks to Jan Volkering
*
* Datasheet:
* https://www.ti.com/lit/gpn/ina209
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/bug.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/platform_data/ina2xx.h>
/* register definitions */
#define INA209_CONFIGURATION 0x00
#define INA209_STATUS 0x01
#define INA209_STATUS_MASK 0x02
#define INA209_SHUNT_VOLTAGE 0x03
#define INA209_BUS_VOLTAGE 0x04
#define INA209_POWER 0x05
#define INA209_CURRENT 0x06
#define INA209_SHUNT_VOLTAGE_POS_PEAK 0x07
#define INA209_SHUNT_VOLTAGE_NEG_PEAK 0x08
#define INA209_BUS_VOLTAGE_MAX_PEAK 0x09
#define INA209_BUS_VOLTAGE_MIN_PEAK 0x0a
#define INA209_POWER_PEAK 0x0b
#define INA209_SHUNT_VOLTAGE_POS_WARN 0x0c
#define INA209_SHUNT_VOLTAGE_NEG_WARN 0x0d
#define INA209_POWER_WARN 0x0e
#define INA209_BUS_VOLTAGE_OVER_WARN 0x0f
#define INA209_BUS_VOLTAGE_UNDER_WARN 0x10
#define INA209_POWER_OVER_LIMIT 0x11
#define INA209_BUS_VOLTAGE_OVER_LIMIT 0x12
#define INA209_BUS_VOLTAGE_UNDER_LIMIT 0x13
#define INA209_CRITICAL_DAC_POS 0x14
#define INA209_CRITICAL_DAC_NEG 0x15
#define INA209_CALIBRATION 0x16
#define INA209_REGISTERS 0x17
#define INA209_CONFIG_DEFAULT 0x3c47 /* PGA=8, full range */
#define INA209_SHUNT_DEFAULT 10000 /* uOhm */
struct ina209_data {
struct i2c_client *client;
struct mutex update_lock;
bool valid;
unsigned long last_updated; /* in jiffies */
u16 regs[INA209_REGISTERS]; /* All chip registers */
u16 config_orig; /* Original configuration */
u16 calibration_orig; /* Original calibration */
u16 update_interval;
};
static struct ina209_data *ina209_update_device(struct device *dev)
{
struct ina209_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
struct ina209_data *ret = data;
s32 val;
int i;
mutex_lock(&data->update_lock);
if (!data->valid ||
time_after(jiffies, data->last_updated + data->update_interval)) {
for (i = 0; i < ARRAY_SIZE(data->regs); i++) {
val = i2c_smbus_read_word_swapped(client, i);
if (val < 0) {
ret = ERR_PTR(val);
goto abort;
}
data->regs[i] = val;
}
data->last_updated = jiffies;
data->valid = true;
}
abort:
mutex_unlock(&data->update_lock);
return ret;
}
/*
* Read a value from a device register and convert it to the
* appropriate sysfs units
*/
static long ina209_from_reg(const u8 reg, const u16 val)
{
switch (reg) {
case INA209_SHUNT_VOLTAGE:
case INA209_SHUNT_VOLTAGE_POS_PEAK:
case INA209_SHUNT_VOLTAGE_NEG_PEAK:
case INA209_SHUNT_VOLTAGE_POS_WARN:
case INA209_SHUNT_VOLTAGE_NEG_WARN:
/* LSB=10 uV. Convert to mV. */
return DIV_ROUND_CLOSEST((s16)val, 100);
case INA209_BUS_VOLTAGE:
case INA209_BUS_VOLTAGE_MAX_PEAK:
case INA209_BUS_VOLTAGE_MIN_PEAK:
case INA209_BUS_VOLTAGE_OVER_WARN:
case INA209_BUS_VOLTAGE_UNDER_WARN:
case INA209_BUS_VOLTAGE_OVER_LIMIT:
case INA209_BUS_VOLTAGE_UNDER_LIMIT:
/* LSB=4 mV, last 3 bits unused */
return (val >> 3) * 4;
case INA209_CRITICAL_DAC_POS:
/* LSB=1 mV, in the upper 8 bits */
return val >> 8;
case INA209_CRITICAL_DAC_NEG:
/* LSB=1 mV, in the upper 8 bits */
return -1 * (val >> 8);
case INA209_POWER:
case INA209_POWER_PEAK:
case INA209_POWER_WARN:
case INA209_POWER_OVER_LIMIT:
/* LSB=20 mW. Convert to uW */
return val * 20 * 1000L;
case INA209_CURRENT:
/* LSB=1 mA (selected). Is in mA */
return (s16)val;
}
/* programmer goofed */
WARN_ON_ONCE(1);
return 0;
}
/*
* Take a value and convert it to register format, clamping the value
* to the appropriate range.
*/
static int ina209_to_reg(u8 reg, u16 old, long val)
{
switch (reg) {
case INA209_SHUNT_VOLTAGE_POS_WARN:
case INA209_SHUNT_VOLTAGE_NEG_WARN:
/* Limit to +- 320 mV, 10 uV LSB */
return clamp_val(val, -320, 320) * 100;
case INA209_BUS_VOLTAGE_OVER_WARN:
case INA209_BUS_VOLTAGE_UNDER_WARN:
case INA209_BUS_VOLTAGE_OVER_LIMIT:
case INA209_BUS_VOLTAGE_UNDER_LIMIT:
/*
* Limit to 0-32000 mV, 4 mV LSB
*
* The last three bits aren't part of the value, but we'll
* preserve them in their original state.
*/
return (DIV_ROUND_CLOSEST(clamp_val(val, 0, 32000), 4) << 3)
| (old & 0x7);
case INA209_CRITICAL_DAC_NEG:
/*
* Limit to -255-0 mV, 1 mV LSB
* Convert the value to a positive value for the register
*
* The value lives in the top 8 bits only, be careful
* and keep original value of other bits.
*/
return (clamp_val(-val, 0, 255) << 8) | (old & 0xff);
case INA209_CRITICAL_DAC_POS:
/*
* Limit to 0-255 mV, 1 mV LSB
*
* The value lives in the top 8 bits only, be careful
* and keep original value of other bits.
*/
return (clamp_val(val, 0, 255) << 8) | (old & 0xff);
case INA209_POWER_WARN:
case INA209_POWER_OVER_LIMIT:
/* 20 mW LSB */
return DIV_ROUND_CLOSEST(val, 20 * 1000);
}
/* Other registers are read-only, return access error */
return -EACCES;
}
static int ina209_interval_from_reg(u16 reg)
{
return 68 >> (15 - ((reg >> 3) & 0x0f));
}
static u16 ina209_reg_from_interval(u16 config, long interval)
{
int i, adc;
if (interval <= 0) {
adc = 8;
} else {
adc = 15;
for (i = 34 + 34 / 2; i; i >>= 1) {
if (i < interval)
break;
adc--;
}
}
return (config & 0xf807) | (adc << 3) | (adc << 7);
}
static ssize_t ina209_interval_store(struct device *dev,
struct device_attribute *da,
const char *buf, size_t count)
{
struct ina209_data *data = ina209_update_device(dev);
long val;
u16 regval;
int ret;
if (IS_ERR(data))
return PTR_ERR(data);
ret = kstrtol(buf, 10, &val);
if (ret < 0)
return ret;
mutex_lock(&data->update_lock);
regval = ina209_reg_from_interval(data->regs[INA209_CONFIGURATION],
val);
i2c_smbus_write_word_swapped(data->client, INA209_CONFIGURATION,
regval);
data->regs[INA209_CONFIGURATION] = regval;
data->update_interval = ina209_interval_from_reg(regval);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t ina209_interval_show(struct device *dev,
struct device_attribute *da, char *buf)
{
struct ina209_data *data = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d\n", data->update_interval);
}
/*
* History is reset by writing 1 into bit 0 of the respective peak register.
* Since more than one peak register may be affected by the scope of a
* reset_history attribute write, use a bit mask in attr->index to identify
* which registers are affected.
*/
static u16 ina209_reset_history_regs[] = {
INA209_SHUNT_VOLTAGE_POS_PEAK,
INA209_SHUNT_VOLTAGE_NEG_PEAK,
INA209_BUS_VOLTAGE_MAX_PEAK,
INA209_BUS_VOLTAGE_MIN_PEAK,
INA209_POWER_PEAK
};
static ssize_t ina209_history_store(struct device *dev,
struct device_attribute *da,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
struct ina209_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
u32 mask = attr->index;
long val;
int i, ret;
ret = kstrtol(buf, 10, &val);
if (ret < 0)
return ret;
mutex_lock(&data->update_lock);
for (i = 0; i < ARRAY_SIZE(ina209_reset_history_regs); i++) {
if (mask & (1 << i))
i2c_smbus_write_word_swapped(client,
ina209_reset_history_regs[i], 1);
}
data->valid = false;
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t ina209_value_store(struct device *dev,
struct device_attribute *da,
const char *buf, size_t count)
{
struct ina209_data *data = ina209_update_device(dev);
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
int reg = attr->index;
long val;
int ret;
if (IS_ERR(data))
return PTR_ERR(data);
ret = kstrtol(buf, 10, &val);
if (ret < 0)
return ret;
mutex_lock(&data->update_lock);
ret = ina209_to_reg(reg, data->regs[reg], val);
if (ret < 0) {
count = ret;
goto abort;
}
i2c_smbus_write_word_swapped(data->client, reg, ret);
data->regs[reg] = ret;
abort:
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t ina209_value_show(struct device *dev,
struct device_attribute *da, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
struct ina209_data *data = ina209_update_device(dev);
long val;
if (IS_ERR(data))
return PTR_ERR(data);
val = ina209_from_reg(attr->index, data->regs[attr->index]);
return sysfs_emit(buf, "%ld\n", val);
}
static ssize_t ina209_alarm_show(struct device *dev,
struct device_attribute *da, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
struct ina209_data *data = ina209_update_device(dev);
const unsigned int mask = attr->index;
u16 status;
if (IS_ERR(data))
return PTR_ERR(data);
status = data->regs[INA209_STATUS];
/*
* All alarms are in the INA209_STATUS register. To avoid a long
* switch statement, the mask is passed in attr->index
*/
return sysfs_emit(buf, "%u\n", !!(status & mask));
}
/* Shunt voltage, history, limits, alarms */
static SENSOR_DEVICE_ATTR_RO(in0_input, ina209_value, INA209_SHUNT_VOLTAGE);
static SENSOR_DEVICE_ATTR_RO(in0_input_highest, ina209_value,
INA209_SHUNT_VOLTAGE_POS_PEAK);
static SENSOR_DEVICE_ATTR_RO(in0_input_lowest, ina209_value,
INA209_SHUNT_VOLTAGE_NEG_PEAK);
static SENSOR_DEVICE_ATTR_WO(in0_reset_history, ina209_history,
(1 << 0) | (1 << 1));
static SENSOR_DEVICE_ATTR_RW(in0_max, ina209_value,
INA209_SHUNT_VOLTAGE_POS_WARN);
static SENSOR_DEVICE_ATTR_RW(in0_min, ina209_value,
INA209_SHUNT_VOLTAGE_NEG_WARN);
static SENSOR_DEVICE_ATTR_RW(in0_crit_max, ina209_value,
INA209_CRITICAL_DAC_POS);
static SENSOR_DEVICE_ATTR_RW(in0_crit_min, ina209_value,
INA209_CRITICAL_DAC_NEG);
static SENSOR_DEVICE_ATTR_RO(in0_min_alarm, ina209_alarm, 1 << 11);
static SENSOR_DEVICE_ATTR_RO(in0_max_alarm, ina209_alarm, 1 << 12);
static SENSOR_DEVICE_ATTR_RO(in0_crit_min_alarm, ina209_alarm, 1 << 6);
static SENSOR_DEVICE_ATTR_RO(in0_crit_max_alarm, ina209_alarm, 1 << 7);
/* Bus voltage, history, limits, alarms */
static SENSOR_DEVICE_ATTR_RO(in1_input, ina209_value, INA209_BUS_VOLTAGE);
static SENSOR_DEVICE_ATTR_RO(in1_input_highest, ina209_value,
INA209_BUS_VOLTAGE_MAX_PEAK);
static SENSOR_DEVICE_ATTR_RO(in1_input_lowest, ina209_value,
INA209_BUS_VOLTAGE_MIN_PEAK);
static SENSOR_DEVICE_ATTR_WO(in1_reset_history, ina209_history,
(1 << 2) | (1 << 3));
static SENSOR_DEVICE_ATTR_RW(in1_max, ina209_value,
INA209_BUS_VOLTAGE_OVER_WARN);
static SENSOR_DEVICE_ATTR_RW(in1_min, ina209_value,
INA209_BUS_VOLTAGE_UNDER_WARN);
static SENSOR_DEVICE_ATTR_RW(in1_crit_max, ina209_value,
INA209_BUS_VOLTAGE_OVER_LIMIT);
static SENSOR_DEVICE_ATTR_RW(in1_crit_min, ina209_value,
INA209_BUS_VOLTAGE_UNDER_LIMIT);
static SENSOR_DEVICE_ATTR_RO(in1_min_alarm, ina209_alarm, 1 << 14);
static SENSOR_DEVICE_ATTR_RO(in1_max_alarm, ina209_alarm, 1 << 15);
static SENSOR_DEVICE_ATTR_RO(in1_crit_min_alarm, ina209_alarm, 1 << 9);
static SENSOR_DEVICE_ATTR_RO(in1_crit_max_alarm, ina209_alarm, 1 << 10);
/* Power */
static SENSOR_DEVICE_ATTR_RO(power1_input, ina209_value, INA209_POWER);
static SENSOR_DEVICE_ATTR_RO(power1_input_highest, ina209_value,
INA209_POWER_PEAK);
static SENSOR_DEVICE_ATTR_WO(power1_reset_history, ina209_history, 1 << 4);
static SENSOR_DEVICE_ATTR_RW(power1_max, ina209_value, INA209_POWER_WARN);
static SENSOR_DEVICE_ATTR_RW(power1_crit, ina209_value,
INA209_POWER_OVER_LIMIT);
static SENSOR_DEVICE_ATTR_RO(power1_max_alarm, ina209_alarm, 1 << 13);
static SENSOR_DEVICE_ATTR_RO(power1_crit_alarm, ina209_alarm, 1 << 8);
/* Current */
static SENSOR_DEVICE_ATTR_RO(curr1_input, ina209_value, INA209_CURRENT);
static SENSOR_DEVICE_ATTR_RW(update_interval, ina209_interval, 0);
/*
* Finally, construct an array of pointers to members of the above objects,
* as required for sysfs_create_group()
*/
static struct attribute *ina209_attrs[] = {
&sensor_dev_attr_in0_input.dev_attr.attr,
&sensor_dev_attr_in0_input_highest.dev_attr.attr,
&sensor_dev_attr_in0_input_lowest.dev_attr.attr,
&sensor_dev_attr_in0_reset_history.dev_attr.attr,
&sensor_dev_attr_in0_max.dev_attr.attr,
&sensor_dev_attr_in0_min.dev_attr.attr,
&sensor_dev_attr_in0_crit_max.dev_attr.attr,
&sensor_dev_attr_in0_crit_min.dev_attr.attr,
&sensor_dev_attr_in0_max_alarm.dev_attr.attr,
&sensor_dev_attr_in0_min_alarm.dev_attr.attr,
&sensor_dev_attr_in0_crit_max_alarm.dev_attr.attr,
&sensor_dev_attr_in0_crit_min_alarm.dev_attr.attr,
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in1_input_highest.dev_attr.attr,
&sensor_dev_attr_in1_input_lowest.dev_attr.attr,
&sensor_dev_attr_in1_reset_history.dev_attr.attr,
&sensor_dev_attr_in1_max.dev_attr.attr,
&sensor_dev_attr_in1_min.dev_attr.attr,
&sensor_dev_attr_in1_crit_max.dev_attr.attr,
&sensor_dev_attr_in1_crit_min.dev_attr.attr,
&sensor_dev_attr_in1_max_alarm.dev_attr.attr,
&sensor_dev_attr_in1_min_alarm.dev_attr.attr,
&sensor_dev_attr_in1_crit_max_alarm.dev_attr.attr,
&sensor_dev_attr_in1_crit_min_alarm.dev_attr.attr,
&sensor_dev_attr_power1_input.dev_attr.attr,
&sensor_dev_attr_power1_input_highest.dev_attr.attr,
&sensor_dev_attr_power1_reset_history.dev_attr.attr,
&sensor_dev_attr_power1_max.dev_attr.attr,
&sensor_dev_attr_power1_crit.dev_attr.attr,
&sensor_dev_attr_power1_max_alarm.dev_attr.attr,
&sensor_dev_attr_power1_crit_alarm.dev_attr.attr,
&sensor_dev_attr_curr1_input.dev_attr.attr,
&sensor_dev_attr_update_interval.dev_attr.attr,
NULL,
};
ATTRIBUTE_GROUPS(ina209);
static void ina209_restore_conf(struct i2c_client *client,
struct ina209_data *data)
{
/* Restore initial configuration */
i2c_smbus_write_word_swapped(client, INA209_CONFIGURATION,
data->config_orig);
i2c_smbus_write_word_swapped(client, INA209_CALIBRATION,
data->calibration_orig);
}
static int ina209_init_client(struct i2c_client *client,
struct ina209_data *data)
{
struct ina2xx_platform_data *pdata = dev_get_platdata(&client->dev);
u32 shunt;
int reg;
reg = i2c_smbus_read_word_swapped(client, INA209_CALIBRATION);
if (reg < 0)
return reg;
data->calibration_orig = reg;
reg = i2c_smbus_read_word_swapped(client, INA209_CONFIGURATION);
if (reg < 0)
return reg;
data->config_orig = reg;
if (pdata) {
if (pdata->shunt_uohms <= 0)
return -EINVAL;
shunt = pdata->shunt_uohms;
} else if (!of_property_read_u32(client->dev.of_node, "shunt-resistor",
&shunt)) {
if (shunt == 0)
return -EINVAL;
} else {
shunt = data->calibration_orig ?
40960000 / data->calibration_orig : INA209_SHUNT_DEFAULT;
}
i2c_smbus_write_word_swapped(client, INA209_CONFIGURATION,
INA209_CONFIG_DEFAULT);
data->update_interval = ina209_interval_from_reg(INA209_CONFIG_DEFAULT);
/*
* Calibrate current LSB to 1mA. Shunt is in uOhms.
* See equation 13 in datasheet.
*/
i2c_smbus_write_word_swapped(client, INA209_CALIBRATION,
clamp_val(40960000 / shunt, 1, 65535));
/* Clear status register */
i2c_smbus_read_word_swapped(client, INA209_STATUS);
return 0;
}
static int ina209_probe(struct i2c_client *client)
{
struct i2c_adapter *adapter = client->adapter;
struct ina209_data *data;
struct device *hwmon_dev;
int ret;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA))
return -ENODEV;
data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
i2c_set_clientdata(client, data);
data->client = client;
mutex_init(&data->update_lock);
ret = ina209_init_client(client, data);
if (ret)
return ret;
hwmon_dev = devm_hwmon_device_register_with_groups(&client->dev,
client->name,
data, ina209_groups);
if (IS_ERR(hwmon_dev)) {
ret = PTR_ERR(hwmon_dev);
goto out_restore_conf;
}
return 0;
out_restore_conf:
ina209_restore_conf(client, data);
return ret;
}
static void ina209_remove(struct i2c_client *client)
{
struct ina209_data *data = i2c_get_clientdata(client);
ina209_restore_conf(client, data);
}
static const struct i2c_device_id ina209_id[] = {
{ "ina209", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ina209_id);
static const struct of_device_id __maybe_unused ina209_of_match[] = {
{ .compatible = "ti,ina209" },
{ },
};
MODULE_DEVICE_TABLE(of, ina209_of_match);
/* This is the driver that will be inserted */
static struct i2c_driver ina209_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "ina209",
.of_match_table = of_match_ptr(ina209_of_match),
},
.probe = ina209_probe,
.remove = ina209_remove,
.id_table = ina209_id,
};
module_i2c_driver(ina209_driver);
MODULE_AUTHOR("Ira W. Snyder <[email protected]>, Paul Hays <[email protected]>, Guenter Roeck <[email protected]>");
MODULE_DESCRIPTION("INA209 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/ina209.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* nzxt-kraken2.c - hwmon driver for NZXT Kraken X42/X52/X62/X72 coolers
*
* The device asynchronously sends HID reports (with id 0x04) twice a second to
* communicate current fan speed, pump speed and coolant temperature. The
* device does not respond to Get_Report requests for this status report.
*
* Copyright 2019-2021 Jonas Malaco <[email protected]>
*/
#include <asm/unaligned.h>
#include <linux/hid.h>
#include <linux/hwmon.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#define STATUS_REPORT_ID 0x04
#define STATUS_VALIDITY 2 /* seconds; equivalent to 4 missed updates */
static const char *const kraken2_temp_label[] = {
"Coolant",
};
static const char *const kraken2_fan_label[] = {
"Fan",
"Pump",
};
struct kraken2_priv_data {
struct hid_device *hid_dev;
struct device *hwmon_dev;
s32 temp_input[1];
u16 fan_input[2];
unsigned long updated; /* jiffies */
};
static umode_t kraken2_is_visible(const void *data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
return 0444;
}
static int kraken2_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct kraken2_priv_data *priv = dev_get_drvdata(dev);
if (time_after(jiffies, priv->updated + STATUS_VALIDITY * HZ))
return -ENODATA;
switch (type) {
case hwmon_temp:
*val = priv->temp_input[channel];
break;
case hwmon_fan:
*val = priv->fan_input[channel];
break;
default:
return -EOPNOTSUPP; /* unreachable */
}
return 0;
}
static int kraken2_read_string(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, const char **str)
{
switch (type) {
case hwmon_temp:
*str = kraken2_temp_label[channel];
break;
case hwmon_fan:
*str = kraken2_fan_label[channel];
break;
default:
return -EOPNOTSUPP; /* unreachable */
}
return 0;
}
static const struct hwmon_ops kraken2_hwmon_ops = {
.is_visible = kraken2_is_visible,
.read = kraken2_read,
.read_string = kraken2_read_string,
};
static const struct hwmon_channel_info * const kraken2_info[] = {
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT | HWMON_T_LABEL),
HWMON_CHANNEL_INFO(fan,
HWMON_F_INPUT | HWMON_F_LABEL,
HWMON_F_INPUT | HWMON_F_LABEL),
NULL
};
static const struct hwmon_chip_info kraken2_chip_info = {
.ops = &kraken2_hwmon_ops,
.info = kraken2_info,
};
static int kraken2_raw_event(struct hid_device *hdev,
struct hid_report *report, u8 *data, int size)
{
struct kraken2_priv_data *priv;
if (size < 7 || report->id != STATUS_REPORT_ID)
return 0;
priv = hid_get_drvdata(hdev);
/*
* The fractional byte of the coolant temperature has been observed to
* be in the interval [1,9], but some of these steps are also
* consistently skipped for certain integer parts.
*
* For the lack of a better idea, assume that the resolution is 0.1°C,
* and that the missing steps are artifacts of how the firmware
* processes the raw sensor data.
*/
priv->temp_input[0] = data[1] * 1000 + data[2] * 100;
priv->fan_input[0] = get_unaligned_be16(data + 3);
priv->fan_input[1] = get_unaligned_be16(data + 5);
priv->updated = jiffies;
return 0;
}
static int kraken2_probe(struct hid_device *hdev,
const struct hid_device_id *id)
{
struct kraken2_priv_data *priv;
int ret;
priv = devm_kzalloc(&hdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->hid_dev = hdev;
hid_set_drvdata(hdev, priv);
/*
* Initialize ->updated to STATUS_VALIDITY seconds in the past, making
* the initial empty data invalid for kraken2_read without the need for
* a special case there.
*/
priv->updated = jiffies - STATUS_VALIDITY * HZ;
ret = hid_parse(hdev);
if (ret) {
hid_err(hdev, "hid parse failed with %d\n", ret);
return ret;
}
/*
* Enable hidraw so existing user-space tools can continue to work.
*/
ret = hid_hw_start(hdev, HID_CONNECT_HIDRAW);
if (ret) {
hid_err(hdev, "hid hw start failed with %d\n", ret);
goto fail_and_stop;
}
ret = hid_hw_open(hdev);
if (ret) {
hid_err(hdev, "hid hw open failed with %d\n", ret);
goto fail_and_close;
}
priv->hwmon_dev = hwmon_device_register_with_info(&hdev->dev, "kraken2",
priv, &kraken2_chip_info,
NULL);
if (IS_ERR(priv->hwmon_dev)) {
ret = PTR_ERR(priv->hwmon_dev);
hid_err(hdev, "hwmon registration failed with %d\n", ret);
goto fail_and_close;
}
return 0;
fail_and_close:
hid_hw_close(hdev);
fail_and_stop:
hid_hw_stop(hdev);
return ret;
}
static void kraken2_remove(struct hid_device *hdev)
{
struct kraken2_priv_data *priv = hid_get_drvdata(hdev);
hwmon_device_unregister(priv->hwmon_dev);
hid_hw_close(hdev);
hid_hw_stop(hdev);
}
static const struct hid_device_id kraken2_table[] = {
{ HID_USB_DEVICE(0x1e71, 0x170e) }, /* NZXT Kraken X42/X52/X62/X72 */
{ }
};
MODULE_DEVICE_TABLE(hid, kraken2_table);
static struct hid_driver kraken2_driver = {
.name = "nzxt-kraken2",
.id_table = kraken2_table,
.probe = kraken2_probe,
.remove = kraken2_remove,
.raw_event = kraken2_raw_event,
};
static int __init kraken2_init(void)
{
return hid_register_driver(&kraken2_driver);
}
static void __exit kraken2_exit(void)
{
hid_unregister_driver(&kraken2_driver);
}
/*
* When compiled into the kernel, initialize after the hid bus.
*/
late_initcall(kraken2_init);
module_exit(kraken2_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jonas Malaco <[email protected]>");
MODULE_DESCRIPTION("Hwmon driver for NZXT Kraken X42/X52/X62/X72 coolers");
|
linux-master
|
drivers/hwmon/nzxt-kraken2.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* emc6w201.c - Hardware monitoring driver for the SMSC EMC6W201
* Copyright (C) 2011 Jean Delvare <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
/*
* Addresses to scan
*/
static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, I2C_CLIENT_END };
/*
* The EMC6W201 registers
*/
#define EMC6W201_REG_IN(nr) (0x20 + (nr))
#define EMC6W201_REG_TEMP(nr) (0x26 + (nr))
#define EMC6W201_REG_FAN(nr) (0x2C + (nr) * 2)
#define EMC6W201_REG_COMPANY 0x3E
#define EMC6W201_REG_VERSTEP 0x3F
#define EMC6W201_REG_CONFIG 0x40
#define EMC6W201_REG_IN_LOW(nr) (0x4A + (nr) * 2)
#define EMC6W201_REG_IN_HIGH(nr) (0x4B + (nr) * 2)
#define EMC6W201_REG_TEMP_LOW(nr) (0x56 + (nr) * 2)
#define EMC6W201_REG_TEMP_HIGH(nr) (0x57 + (nr) * 2)
#define EMC6W201_REG_FAN_MIN(nr) (0x62 + (nr) * 2)
enum subfeature { input, min, max };
/*
* Per-device data
*/
struct emc6w201_data {
struct i2c_client *client;
struct mutex update_lock;
bool valid; /* false until following fields are valid */
unsigned long last_updated; /* in jiffies */
/* registers values */
u8 in[3][6];
s8 temp[3][6];
u16 fan[2][5];
};
/*
* Combine LSB and MSB registers in a single value
* Locking: must be called with data->update_lock held
*/
static u16 emc6w201_read16(struct i2c_client *client, u8 reg)
{
int lsb, msb;
lsb = i2c_smbus_read_byte_data(client, reg);
msb = i2c_smbus_read_byte_data(client, reg + 1);
if (unlikely(lsb < 0 || msb < 0)) {
dev_err(&client->dev, "%d-bit %s failed at 0x%02x\n",
16, "read", reg);
return 0xFFFF; /* Arbitrary value */
}
return (msb << 8) | lsb;
}
/*
* Write 16-bit value to LSB and MSB registers
* Locking: must be called with data->update_lock held
*/
static int emc6w201_write16(struct i2c_client *client, u8 reg, u16 val)
{
int err;
err = i2c_smbus_write_byte_data(client, reg, val & 0xff);
if (likely(!err))
err = i2c_smbus_write_byte_data(client, reg + 1, val >> 8);
if (unlikely(err < 0))
dev_err(&client->dev, "%d-bit %s failed at 0x%02x\n",
16, "write", reg);
return err;
}
/* Read 8-bit value from register */
static u8 emc6w201_read8(struct i2c_client *client, u8 reg)
{
int val;
val = i2c_smbus_read_byte_data(client, reg);
if (unlikely(val < 0)) {
dev_err(&client->dev, "%d-bit %s failed at 0x%02x\n",
8, "read", reg);
return 0x00; /* Arbitrary value */
}
return val;
}
/* Write 8-bit value to register */
static int emc6w201_write8(struct i2c_client *client, u8 reg, u8 val)
{
int err;
err = i2c_smbus_write_byte_data(client, reg, val);
if (unlikely(err < 0))
dev_err(&client->dev, "%d-bit %s failed at 0x%02x\n",
8, "write", reg);
return err;
}
static struct emc6w201_data *emc6w201_update_device(struct device *dev)
{
struct emc6w201_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int nr;
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
for (nr = 0; nr < 6; nr++) {
data->in[input][nr] =
emc6w201_read8(client,
EMC6W201_REG_IN(nr));
data->in[min][nr] =
emc6w201_read8(client,
EMC6W201_REG_IN_LOW(nr));
data->in[max][nr] =
emc6w201_read8(client,
EMC6W201_REG_IN_HIGH(nr));
}
for (nr = 0; nr < 6; nr++) {
data->temp[input][nr] =
emc6w201_read8(client,
EMC6W201_REG_TEMP(nr));
data->temp[min][nr] =
emc6w201_read8(client,
EMC6W201_REG_TEMP_LOW(nr));
data->temp[max][nr] =
emc6w201_read8(client,
EMC6W201_REG_TEMP_HIGH(nr));
}
for (nr = 0; nr < 5; nr++) {
data->fan[input][nr] =
emc6w201_read16(client,
EMC6W201_REG_FAN(nr));
data->fan[min][nr] =
emc6w201_read16(client,
EMC6W201_REG_FAN_MIN(nr));
}
data->last_updated = jiffies;
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
/*
* Sysfs callback functions
*/
static const s16 nominal_mv[6] = { 2500, 1500, 3300, 5000, 1500, 1500 };
static ssize_t in_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct emc6w201_data *data = emc6w201_update_device(dev);
int sf = to_sensor_dev_attr_2(devattr)->index;
int nr = to_sensor_dev_attr_2(devattr)->nr;
return sprintf(buf, "%u\n",
(unsigned)data->in[sf][nr] * nominal_mv[nr] / 0xC0);
}
static ssize_t in_store(struct device *dev, struct device_attribute *devattr,
const char *buf, size_t count)
{
struct emc6w201_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int sf = to_sensor_dev_attr_2(devattr)->index;
int nr = to_sensor_dev_attr_2(devattr)->nr;
int err;
long val;
u8 reg;
err = kstrtol(buf, 10, &val);
if (err < 0)
return err;
val = clamp_val(val, 0, 255 * nominal_mv[nr] / 192);
val = DIV_ROUND_CLOSEST(val * 192, nominal_mv[nr]);
reg = (sf == min) ? EMC6W201_REG_IN_LOW(nr)
: EMC6W201_REG_IN_HIGH(nr);
mutex_lock(&data->update_lock);
data->in[sf][nr] = val;
err = emc6w201_write8(client, reg, data->in[sf][nr]);
mutex_unlock(&data->update_lock);
return err < 0 ? err : count;
}
static ssize_t temp_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct emc6w201_data *data = emc6w201_update_device(dev);
int sf = to_sensor_dev_attr_2(devattr)->index;
int nr = to_sensor_dev_attr_2(devattr)->nr;
return sprintf(buf, "%d\n", (int)data->temp[sf][nr] * 1000);
}
static ssize_t temp_store(struct device *dev,
struct device_attribute *devattr, const char *buf,
size_t count)
{
struct emc6w201_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int sf = to_sensor_dev_attr_2(devattr)->index;
int nr = to_sensor_dev_attr_2(devattr)->nr;
int err;
long val;
u8 reg;
err = kstrtol(buf, 10, &val);
if (err < 0)
return err;
val = clamp_val(val, -127000, 127000);
val = DIV_ROUND_CLOSEST(val, 1000);
reg = (sf == min) ? EMC6W201_REG_TEMP_LOW(nr)
: EMC6W201_REG_TEMP_HIGH(nr);
mutex_lock(&data->update_lock);
data->temp[sf][nr] = val;
err = emc6w201_write8(client, reg, data->temp[sf][nr]);
mutex_unlock(&data->update_lock);
return err < 0 ? err : count;
}
static ssize_t fan_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
struct emc6w201_data *data = emc6w201_update_device(dev);
int sf = to_sensor_dev_attr_2(devattr)->index;
int nr = to_sensor_dev_attr_2(devattr)->nr;
unsigned rpm;
if (data->fan[sf][nr] == 0 || data->fan[sf][nr] == 0xFFFF)
rpm = 0;
else
rpm = 5400000U / data->fan[sf][nr];
return sprintf(buf, "%u\n", rpm);
}
static ssize_t fan_store(struct device *dev, struct device_attribute *devattr,
const char *buf, size_t count)
{
struct emc6w201_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
int sf = to_sensor_dev_attr_2(devattr)->index;
int nr = to_sensor_dev_attr_2(devattr)->nr;
int err;
unsigned long val;
err = kstrtoul(buf, 10, &val);
if (err < 0)
return err;
if (val == 0) {
val = 0xFFFF;
} else {
val = DIV_ROUND_CLOSEST(5400000U, val);
val = clamp_val(val, 0, 0xFFFE);
}
mutex_lock(&data->update_lock);
data->fan[sf][nr] = val;
err = emc6w201_write16(client, EMC6W201_REG_FAN_MIN(nr),
data->fan[sf][nr]);
mutex_unlock(&data->update_lock);
return err < 0 ? err : count;
}
static SENSOR_DEVICE_ATTR_2_RO(in0_input, in, 0, input);
static SENSOR_DEVICE_ATTR_2_RW(in0_min, in, 0, min);
static SENSOR_DEVICE_ATTR_2_RW(in0_max, in, 0, max);
static SENSOR_DEVICE_ATTR_2_RO(in1_input, in, 1, input);
static SENSOR_DEVICE_ATTR_2_RW(in1_min, in, 1, min);
static SENSOR_DEVICE_ATTR_2_RW(in1_max, in, 1, max);
static SENSOR_DEVICE_ATTR_2_RO(in2_input, in, 2, input);
static SENSOR_DEVICE_ATTR_2_RW(in2_min, in, 2, min);
static SENSOR_DEVICE_ATTR_2_RW(in2_max, in, 2, max);
static SENSOR_DEVICE_ATTR_2_RO(in3_input, in, 3, input);
static SENSOR_DEVICE_ATTR_2_RW(in3_min, in, 3, min);
static SENSOR_DEVICE_ATTR_2_RW(in3_max, in, 3, max);
static SENSOR_DEVICE_ATTR_2_RO(in4_input, in, 4, input);
static SENSOR_DEVICE_ATTR_2_RW(in4_min, in, 4, min);
static SENSOR_DEVICE_ATTR_2_RW(in4_max, in, 4, max);
static SENSOR_DEVICE_ATTR_2_RO(in5_input, in, 5, input);
static SENSOR_DEVICE_ATTR_2_RW(in5_min, in, 5, min);
static SENSOR_DEVICE_ATTR_2_RW(in5_max, in, 5, max);
static SENSOR_DEVICE_ATTR_2_RO(temp1_input, temp, 0, input);
static SENSOR_DEVICE_ATTR_2_RW(temp1_min, temp, 0, min);
static SENSOR_DEVICE_ATTR_2_RW(temp1_max, temp, 0, max);
static SENSOR_DEVICE_ATTR_2_RO(temp2_input, temp, 1, input);
static SENSOR_DEVICE_ATTR_2_RW(temp2_min, temp, 1, min);
static SENSOR_DEVICE_ATTR_2_RW(temp2_max, temp, 1, max);
static SENSOR_DEVICE_ATTR_2_RO(temp3_input, temp, 2, input);
static SENSOR_DEVICE_ATTR_2_RW(temp3_min, temp, 2, min);
static SENSOR_DEVICE_ATTR_2_RW(temp3_max, temp, 2, max);
static SENSOR_DEVICE_ATTR_2_RO(temp4_input, temp, 3, input);
static SENSOR_DEVICE_ATTR_2_RW(temp4_min, temp, 3, min);
static SENSOR_DEVICE_ATTR_2_RW(temp4_max, temp, 3, max);
static SENSOR_DEVICE_ATTR_2_RO(temp5_input, temp, 4, input);
static SENSOR_DEVICE_ATTR_2_RW(temp5_min, temp, 4, min);
static SENSOR_DEVICE_ATTR_2_RW(temp5_max, temp, 4, max);
static SENSOR_DEVICE_ATTR_2_RO(temp6_input, temp, 5, input);
static SENSOR_DEVICE_ATTR_2_RW(temp6_min, temp, 5, min);
static SENSOR_DEVICE_ATTR_2_RW(temp6_max, temp, 5, max);
static SENSOR_DEVICE_ATTR_2_RO(fan1_input, fan, 0, input);
static SENSOR_DEVICE_ATTR_2_RW(fan1_min, fan, 0, min);
static SENSOR_DEVICE_ATTR_2_RO(fan2_input, fan, 1, input);
static SENSOR_DEVICE_ATTR_2_RW(fan2_min, fan, 1, min);
static SENSOR_DEVICE_ATTR_2_RO(fan3_input, fan, 2, input);
static SENSOR_DEVICE_ATTR_2_RW(fan3_min, fan, 2, min);
static SENSOR_DEVICE_ATTR_2_RO(fan4_input, fan, 3, input);
static SENSOR_DEVICE_ATTR_2_RW(fan4_min, fan, 3, min);
static SENSOR_DEVICE_ATTR_2_RO(fan5_input, fan, 4, input);
static SENSOR_DEVICE_ATTR_2_RW(fan5_min, fan, 4, min);
static struct attribute *emc6w201_attrs[] = {
&sensor_dev_attr_in0_input.dev_attr.attr,
&sensor_dev_attr_in0_min.dev_attr.attr,
&sensor_dev_attr_in0_max.dev_attr.attr,
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in1_min.dev_attr.attr,
&sensor_dev_attr_in1_max.dev_attr.attr,
&sensor_dev_attr_in2_input.dev_attr.attr,
&sensor_dev_attr_in2_min.dev_attr.attr,
&sensor_dev_attr_in2_max.dev_attr.attr,
&sensor_dev_attr_in3_input.dev_attr.attr,
&sensor_dev_attr_in3_min.dev_attr.attr,
&sensor_dev_attr_in3_max.dev_attr.attr,
&sensor_dev_attr_in4_input.dev_attr.attr,
&sensor_dev_attr_in4_min.dev_attr.attr,
&sensor_dev_attr_in4_max.dev_attr.attr,
&sensor_dev_attr_in5_input.dev_attr.attr,
&sensor_dev_attr_in5_min.dev_attr.attr,
&sensor_dev_attr_in5_max.dev_attr.attr,
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_min.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp2_min.dev_attr.attr,
&sensor_dev_attr_temp2_max.dev_attr.attr,
&sensor_dev_attr_temp3_input.dev_attr.attr,
&sensor_dev_attr_temp3_min.dev_attr.attr,
&sensor_dev_attr_temp3_max.dev_attr.attr,
&sensor_dev_attr_temp4_input.dev_attr.attr,
&sensor_dev_attr_temp4_min.dev_attr.attr,
&sensor_dev_attr_temp4_max.dev_attr.attr,
&sensor_dev_attr_temp5_input.dev_attr.attr,
&sensor_dev_attr_temp5_min.dev_attr.attr,
&sensor_dev_attr_temp5_max.dev_attr.attr,
&sensor_dev_attr_temp6_input.dev_attr.attr,
&sensor_dev_attr_temp6_min.dev_attr.attr,
&sensor_dev_attr_temp6_max.dev_attr.attr,
&sensor_dev_attr_fan1_input.dev_attr.attr,
&sensor_dev_attr_fan1_min.dev_attr.attr,
&sensor_dev_attr_fan2_input.dev_attr.attr,
&sensor_dev_attr_fan2_min.dev_attr.attr,
&sensor_dev_attr_fan3_input.dev_attr.attr,
&sensor_dev_attr_fan3_min.dev_attr.attr,
&sensor_dev_attr_fan4_input.dev_attr.attr,
&sensor_dev_attr_fan4_min.dev_attr.attr,
&sensor_dev_attr_fan5_input.dev_attr.attr,
&sensor_dev_attr_fan5_min.dev_attr.attr,
NULL
};
ATTRIBUTE_GROUPS(emc6w201);
/*
* Driver interface
*/
/* Return 0 if detection is successful, -ENODEV otherwise */
static int emc6w201_detect(struct i2c_client *client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
int company, verstep, config;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
/* Identification */
company = i2c_smbus_read_byte_data(client, EMC6W201_REG_COMPANY);
if (company != 0x5C)
return -ENODEV;
verstep = i2c_smbus_read_byte_data(client, EMC6W201_REG_VERSTEP);
if (verstep < 0 || (verstep & 0xF0) != 0xB0)
return -ENODEV;
if ((verstep & 0x0F) > 2) {
dev_dbg(&client->dev, "Unknown EMC6W201 stepping %d\n",
verstep & 0x0F);
return -ENODEV;
}
/* Check configuration */
config = i2c_smbus_read_byte_data(client, EMC6W201_REG_CONFIG);
if (config < 0 || (config & 0xF4) != 0x04)
return -ENODEV;
if (!(config & 0x01)) {
dev_err(&client->dev, "Monitoring not enabled\n");
return -ENODEV;
}
strscpy(info->type, "emc6w201", I2C_NAME_SIZE);
return 0;
}
static int emc6w201_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct emc6w201_data *data;
struct device *hwmon_dev;
data = devm_kzalloc(dev, sizeof(struct emc6w201_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
mutex_init(&data->update_lock);
hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
data,
emc6w201_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id emc6w201_id[] = {
{ "emc6w201", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, emc6w201_id);
static struct i2c_driver emc6w201_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "emc6w201",
},
.probe = emc6w201_probe,
.id_table = emc6w201_id,
.detect = emc6w201_detect,
.address_list = normal_i2c,
};
module_i2c_driver(emc6w201_driver);
MODULE_AUTHOR("Jean Delvare <[email protected]>");
MODULE_DESCRIPTION("SMSC EMC6W201 hardware monitoring driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/emc6w201.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Linear Technology LTC4151 High Voltage I2C Current
* and Voltage Monitor
*
* Copyright (C) 2011 AppearTV AS
*
* Derived from:
*
* Driver for Linear Technology LTC4261 I2C Negative Voltage Hot
* Swap Controller
* Copyright (C) 2010 Ericsson AB.
*
* Datasheet: http://www.linear.com/docs/Datasheet/4151fc.pdf
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/jiffies.h>
/* chip registers */
#define LTC4151_SENSE_H 0x00
#define LTC4151_SENSE_L 0x01
#define LTC4151_VIN_H 0x02
#define LTC4151_VIN_L 0x03
#define LTC4151_ADIN_H 0x04
#define LTC4151_ADIN_L 0x05
struct ltc4151_data {
struct i2c_client *client;
struct mutex update_lock;
bool valid;
unsigned long last_updated; /* in jiffies */
unsigned int shunt; /* in micro ohms */
/* Registers */
u8 regs[6];
};
static struct ltc4151_data *ltc4151_update_device(struct device *dev)
{
struct ltc4151_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
struct ltc4151_data *ret = data;
mutex_lock(&data->update_lock);
/*
* The chip's A/D updates 6 times per second
* (Conversion Rate 6 - 9 Hz)
*/
if (time_after(jiffies, data->last_updated + HZ / 6) || !data->valid) {
int i;
dev_dbg(&client->dev, "Starting ltc4151 update\n");
/* Read all registers */
for (i = 0; i < ARRAY_SIZE(data->regs); i++) {
int val;
val = i2c_smbus_read_byte_data(client, i);
if (unlikely(val < 0)) {
dev_dbg(dev,
"Failed to read ADC value: error %d\n",
val);
ret = ERR_PTR(val);
goto abort;
}
data->regs[i] = val;
}
data->last_updated = jiffies;
data->valid = true;
}
abort:
mutex_unlock(&data->update_lock);
return ret;
}
/* Return the voltage from the given register in mV */
static int ltc4151_get_value(struct ltc4151_data *data, u8 reg)
{
u32 val;
val = (data->regs[reg] << 4) + (data->regs[reg + 1] >> 4);
switch (reg) {
case LTC4151_ADIN_H:
/* 500uV resolution. Convert to mV. */
val = val * 500 / 1000;
break;
case LTC4151_SENSE_H:
/*
* 20uV resolution. Convert to current as measured with
* a given sense resistor, in mA.
*/
val = val * 20 * 1000 / data->shunt;
break;
case LTC4151_VIN_H:
/* 25 mV per increment */
val = val * 25;
break;
default:
/* If we get here, the developer messed up */
WARN_ON_ONCE(1);
val = 0;
break;
}
return val;
}
static ssize_t ltc4151_value_show(struct device *dev,
struct device_attribute *da, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
struct ltc4151_data *data = ltc4151_update_device(dev);
int value;
if (IS_ERR(data))
return PTR_ERR(data);
value = ltc4151_get_value(data, attr->index);
return sysfs_emit(buf, "%d\n", value);
}
/*
* Input voltages.
*/
static SENSOR_DEVICE_ATTR_RO(in1_input, ltc4151_value, LTC4151_VIN_H);
static SENSOR_DEVICE_ATTR_RO(in2_input, ltc4151_value, LTC4151_ADIN_H);
/* Currents (via sense resistor) */
static SENSOR_DEVICE_ATTR_RO(curr1_input, ltc4151_value, LTC4151_SENSE_H);
/*
* Finally, construct an array of pointers to members of the above objects,
* as required for sysfs_create_group()
*/
static struct attribute *ltc4151_attrs[] = {
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in2_input.dev_attr.attr,
&sensor_dev_attr_curr1_input.dev_attr.attr,
NULL,
};
ATTRIBUTE_GROUPS(ltc4151);
static int ltc4151_probe(struct i2c_client *client)
{
struct i2c_adapter *adapter = client->adapter;
struct device *dev = &client->dev;
struct ltc4151_data *data;
struct device *hwmon_dev;
u32 shunt;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
if (of_property_read_u32(client->dev.of_node,
"shunt-resistor-micro-ohms", &shunt))
shunt = 1000; /* 1 mOhm if not set via DT */
if (shunt == 0)
return -EINVAL;
data->shunt = shunt;
data->client = client;
mutex_init(&data->update_lock);
hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
data,
ltc4151_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id ltc4151_id[] = {
{ "ltc4151", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ltc4151_id);
static const struct of_device_id __maybe_unused ltc4151_match[] = {
{ .compatible = "lltc,ltc4151" },
{},
};
MODULE_DEVICE_TABLE(of, ltc4151_match);
/* This is the driver that will be inserted */
static struct i2c_driver ltc4151_driver = {
.driver = {
.name = "ltc4151",
.of_match_table = of_match_ptr(ltc4151_match),
},
.probe = ltc4151_probe,
.id_table = ltc4151_id,
};
module_i2c_driver(ltc4151_driver);
MODULE_AUTHOR("Per Dalen <[email protected]>");
MODULE_DESCRIPTION("LTC4151 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/ltc4151.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* corsair-cpro.c - Linux driver for Corsair Commander Pro
* Copyright (C) 2020 Marius Zachmann <[email protected]>
*
* This driver uses hid reports to communicate with the device to allow hidraw userspace drivers
* still being used. The device does not use report ids. When using hidraw and this driver
* simultaniously, reports could be switched.
*/
#include <linux/bitops.h>
#include <linux/completion.h>
#include <linux/hid.h>
#include <linux/hwmon.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/types.h>
#define USB_VENDOR_ID_CORSAIR 0x1b1c
#define USB_PRODUCT_ID_CORSAIR_COMMANDERPRO 0x0c10
#define USB_PRODUCT_ID_CORSAIR_1000D 0x1d00
#define OUT_BUFFER_SIZE 63
#define IN_BUFFER_SIZE 16
#define LABEL_LENGTH 11
#define REQ_TIMEOUT 300
#define CTL_GET_TMP_CNCT 0x10 /*
* returns in bytes 1-4 for each temp sensor:
* 0 not connected
* 1 connected
*/
#define CTL_GET_TMP 0x11 /*
* send: byte 1 is channel, rest zero
* rcv: returns temp for channel in centi-degree celsius
* in bytes 1 and 2
* returns 0x11 in byte 0 if no sensor is connected
*/
#define CTL_GET_VOLT 0x12 /*
* send: byte 1 is rail number: 0 = 12v, 1 = 5v, 2 = 3.3v
* rcv: returns millivolt in bytes 1,2
* returns error 0x10 if request is invalid
*/
#define CTL_GET_FAN_CNCT 0x20 /*
* returns in bytes 1-6 for each fan:
* 0 not connected
* 1 3pin
* 2 4pin
*/
#define CTL_GET_FAN_RPM 0x21 /*
* send: byte 1 is channel, rest zero
* rcv: returns rpm in bytes 1,2
*/
#define CTL_GET_FAN_PWM 0x22 /*
* send: byte 1 is channel, rest zero
* rcv: returns pwm in byte 1 if it was set
* returns error 0x12 if fan is controlled via
* fan_target or fan curve
*/
#define CTL_SET_FAN_FPWM 0x23 /*
* set fixed pwm
* send: byte 1 is fan number
* send: byte 2 is percentage from 0 - 100
*/
#define CTL_SET_FAN_TARGET 0x24 /*
* set target rpm
* send: byte 1 is fan number
* send: byte 2-3 is target
* device accepts all values from 0x00 - 0xFFFF
*/
#define NUM_FANS 6
#define NUM_TEMP_SENSORS 4
struct ccp_device {
struct hid_device *hdev;
struct device *hwmon_dev;
struct completion wait_input_report;
struct mutex mutex; /* whenever buffer is used, lock before send_usb_cmd */
u8 *buffer;
int target[6];
DECLARE_BITMAP(temp_cnct, NUM_TEMP_SENSORS);
DECLARE_BITMAP(fan_cnct, NUM_FANS);
char fan_label[6][LABEL_LENGTH];
};
/* converts response error in buffer to errno */
static int ccp_get_errno(struct ccp_device *ccp)
{
switch (ccp->buffer[0]) {
case 0x00: /* success */
return 0;
case 0x01: /* called invalid command */
return -EOPNOTSUPP;
case 0x10: /* called GET_VOLT / GET_TMP with invalid arguments */
return -EINVAL;
case 0x11: /* requested temps of disconnected sensors */
case 0x12: /* requested pwm of not pwm controlled channels */
return -ENODATA;
default:
hid_dbg(ccp->hdev, "unknown device response error: %d", ccp->buffer[0]);
return -EIO;
}
}
/* send command, check for error in response, response in ccp->buffer */
static int send_usb_cmd(struct ccp_device *ccp, u8 command, u8 byte1, u8 byte2, u8 byte3)
{
unsigned long t;
int ret;
memset(ccp->buffer, 0x00, OUT_BUFFER_SIZE);
ccp->buffer[0] = command;
ccp->buffer[1] = byte1;
ccp->buffer[2] = byte2;
ccp->buffer[3] = byte3;
reinit_completion(&ccp->wait_input_report);
ret = hid_hw_output_report(ccp->hdev, ccp->buffer, OUT_BUFFER_SIZE);
if (ret < 0)
return ret;
t = wait_for_completion_timeout(&ccp->wait_input_report, msecs_to_jiffies(REQ_TIMEOUT));
if (!t)
return -ETIMEDOUT;
return ccp_get_errno(ccp);
}
static int ccp_raw_event(struct hid_device *hdev, struct hid_report *report, u8 *data, int size)
{
struct ccp_device *ccp = hid_get_drvdata(hdev);
/* only copy buffer when requested */
if (completion_done(&ccp->wait_input_report))
return 0;
memcpy(ccp->buffer, data, min(IN_BUFFER_SIZE, size));
complete(&ccp->wait_input_report);
return 0;
}
/* requests and returns single data values depending on channel */
static int get_data(struct ccp_device *ccp, int command, int channel, bool two_byte_data)
{
int ret;
mutex_lock(&ccp->mutex);
ret = send_usb_cmd(ccp, command, channel, 0, 0);
if (ret)
goto out_unlock;
ret = ccp->buffer[1];
if (two_byte_data)
ret = (ret << 8) + ccp->buffer[2];
out_unlock:
mutex_unlock(&ccp->mutex);
return ret;
}
static int set_pwm(struct ccp_device *ccp, int channel, long val)
{
int ret;
if (val < 0 || val > 255)
return -EINVAL;
/* The Corsair Commander Pro uses values from 0-100 */
val = DIV_ROUND_CLOSEST(val * 100, 255);
mutex_lock(&ccp->mutex);
ret = send_usb_cmd(ccp, CTL_SET_FAN_FPWM, channel, val, 0);
if (!ret)
ccp->target[channel] = -ENODATA;
mutex_unlock(&ccp->mutex);
return ret;
}
static int set_target(struct ccp_device *ccp, int channel, long val)
{
int ret;
val = clamp_val(val, 0, 0xFFFF);
ccp->target[channel] = val;
mutex_lock(&ccp->mutex);
ret = send_usb_cmd(ccp, CTL_SET_FAN_TARGET, channel, val >> 8, val);
mutex_unlock(&ccp->mutex);
return ret;
}
static int ccp_read_string(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, const char **str)
{
struct ccp_device *ccp = dev_get_drvdata(dev);
switch (type) {
case hwmon_fan:
switch (attr) {
case hwmon_fan_label:
*str = ccp->fan_label[channel];
return 0;
default:
break;
}
break;
default:
break;
}
return -EOPNOTSUPP;
}
static int ccp_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct ccp_device *ccp = dev_get_drvdata(dev);
int ret;
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_input:
ret = get_data(ccp, CTL_GET_TMP, channel, true);
if (ret < 0)
return ret;
*val = ret * 10;
return 0;
default:
break;
}
break;
case hwmon_fan:
switch (attr) {
case hwmon_fan_input:
ret = get_data(ccp, CTL_GET_FAN_RPM, channel, true);
if (ret < 0)
return ret;
*val = ret;
return 0;
case hwmon_fan_target:
/* how to read target values from the device is unknown */
/* driver returns last set value or 0 */
if (ccp->target[channel] < 0)
return -ENODATA;
*val = ccp->target[channel];
return 0;
default:
break;
}
break;
case hwmon_pwm:
switch (attr) {
case hwmon_pwm_input:
ret = get_data(ccp, CTL_GET_FAN_PWM, channel, false);
if (ret < 0)
return ret;
*val = DIV_ROUND_CLOSEST(ret * 255, 100);
return 0;
default:
break;
}
break;
case hwmon_in:
switch (attr) {
case hwmon_in_input:
ret = get_data(ccp, CTL_GET_VOLT, channel, true);
if (ret < 0)
return ret;
*val = ret;
return 0;
default:
break;
}
break;
default:
break;
}
return -EOPNOTSUPP;
};
static int ccp_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
struct ccp_device *ccp = dev_get_drvdata(dev);
switch (type) {
case hwmon_pwm:
switch (attr) {
case hwmon_pwm_input:
return set_pwm(ccp, channel, val);
default:
break;
}
break;
case hwmon_fan:
switch (attr) {
case hwmon_fan_target:
return set_target(ccp, channel, val);
default:
break;
}
break;
default:
break;
}
return -EOPNOTSUPP;
};
static umode_t ccp_is_visible(const void *data, enum hwmon_sensor_types type,
u32 attr, int channel)
{
const struct ccp_device *ccp = data;
switch (type) {
case hwmon_temp:
if (!test_bit(channel, ccp->temp_cnct))
break;
switch (attr) {
case hwmon_temp_input:
return 0444;
case hwmon_temp_label:
return 0444;
default:
break;
}
break;
case hwmon_fan:
if (!test_bit(channel, ccp->fan_cnct))
break;
switch (attr) {
case hwmon_fan_input:
return 0444;
case hwmon_fan_label:
return 0444;
case hwmon_fan_target:
return 0644;
default:
break;
}
break;
case hwmon_pwm:
if (!test_bit(channel, ccp->fan_cnct))
break;
switch (attr) {
case hwmon_pwm_input:
return 0644;
default:
break;
}
break;
case hwmon_in:
switch (attr) {
case hwmon_in_input:
return 0444;
default:
break;
}
break;
default:
break;
}
return 0;
};
static const struct hwmon_ops ccp_hwmon_ops = {
.is_visible = ccp_is_visible,
.read = ccp_read,
.read_string = ccp_read_string,
.write = ccp_write,
};
static const struct hwmon_channel_info * const ccp_info[] = {
HWMON_CHANNEL_INFO(chip,
HWMON_C_REGISTER_TZ),
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT,
HWMON_T_INPUT,
HWMON_T_INPUT,
HWMON_T_INPUT
),
HWMON_CHANNEL_INFO(fan,
HWMON_F_INPUT | HWMON_F_LABEL | HWMON_F_TARGET,
HWMON_F_INPUT | HWMON_F_LABEL | HWMON_F_TARGET,
HWMON_F_INPUT | HWMON_F_LABEL | HWMON_F_TARGET,
HWMON_F_INPUT | HWMON_F_LABEL | HWMON_F_TARGET,
HWMON_F_INPUT | HWMON_F_LABEL | HWMON_F_TARGET,
HWMON_F_INPUT | HWMON_F_LABEL | HWMON_F_TARGET
),
HWMON_CHANNEL_INFO(pwm,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT,
HWMON_PWM_INPUT
),
HWMON_CHANNEL_INFO(in,
HWMON_I_INPUT,
HWMON_I_INPUT,
HWMON_I_INPUT
),
NULL
};
static const struct hwmon_chip_info ccp_chip_info = {
.ops = &ccp_hwmon_ops,
.info = ccp_info,
};
/* read fan connection status and set labels */
static int get_fan_cnct(struct ccp_device *ccp)
{
int channel;
int mode;
int ret;
ret = send_usb_cmd(ccp, CTL_GET_FAN_CNCT, 0, 0, 0);
if (ret)
return ret;
for (channel = 0; channel < NUM_FANS; channel++) {
mode = ccp->buffer[channel + 1];
if (mode == 0)
continue;
set_bit(channel, ccp->fan_cnct);
ccp->target[channel] = -ENODATA;
switch (mode) {
case 1:
scnprintf(ccp->fan_label[channel], LABEL_LENGTH,
"fan%d 3pin", channel + 1);
break;
case 2:
scnprintf(ccp->fan_label[channel], LABEL_LENGTH,
"fan%d 4pin", channel + 1);
break;
default:
scnprintf(ccp->fan_label[channel], LABEL_LENGTH,
"fan%d other", channel + 1);
break;
}
}
return 0;
}
/* read temp sensor connection status */
static int get_temp_cnct(struct ccp_device *ccp)
{
int channel;
int mode;
int ret;
ret = send_usb_cmd(ccp, CTL_GET_TMP_CNCT, 0, 0, 0);
if (ret)
return ret;
for (channel = 0; channel < NUM_TEMP_SENSORS; channel++) {
mode = ccp->buffer[channel + 1];
if (mode == 0)
continue;
set_bit(channel, ccp->temp_cnct);
}
return 0;
}
static int ccp_probe(struct hid_device *hdev, const struct hid_device_id *id)
{
struct ccp_device *ccp;
int ret;
ccp = devm_kzalloc(&hdev->dev, sizeof(*ccp), GFP_KERNEL);
if (!ccp)
return -ENOMEM;
ccp->buffer = devm_kmalloc(&hdev->dev, OUT_BUFFER_SIZE, GFP_KERNEL);
if (!ccp->buffer)
return -ENOMEM;
ret = hid_parse(hdev);
if (ret)
return ret;
ret = hid_hw_start(hdev, HID_CONNECT_HIDRAW);
if (ret)
return ret;
ret = hid_hw_open(hdev);
if (ret)
goto out_hw_stop;
ccp->hdev = hdev;
hid_set_drvdata(hdev, ccp);
mutex_init(&ccp->mutex);
init_completion(&ccp->wait_input_report);
hid_device_io_start(hdev);
/* temp and fan connection status only updates when device is powered on */
ret = get_temp_cnct(ccp);
if (ret)
goto out_hw_close;
ret = get_fan_cnct(ccp);
if (ret)
goto out_hw_close;
ccp->hwmon_dev = hwmon_device_register_with_info(&hdev->dev, "corsaircpro",
ccp, &ccp_chip_info, 0);
if (IS_ERR(ccp->hwmon_dev)) {
ret = PTR_ERR(ccp->hwmon_dev);
goto out_hw_close;
}
return 0;
out_hw_close:
hid_hw_close(hdev);
out_hw_stop:
hid_hw_stop(hdev);
return ret;
}
static void ccp_remove(struct hid_device *hdev)
{
struct ccp_device *ccp = hid_get_drvdata(hdev);
hwmon_device_unregister(ccp->hwmon_dev);
hid_hw_close(hdev);
hid_hw_stop(hdev);
}
static const struct hid_device_id ccp_devices[] = {
{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_PRODUCT_ID_CORSAIR_COMMANDERPRO) },
{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_PRODUCT_ID_CORSAIR_1000D) },
{ }
};
static struct hid_driver ccp_driver = {
.name = "corsair-cpro",
.id_table = ccp_devices,
.probe = ccp_probe,
.remove = ccp_remove,
.raw_event = ccp_raw_event,
};
MODULE_DEVICE_TABLE(hid, ccp_devices);
MODULE_LICENSE("GPL");
static int __init ccp_init(void)
{
return hid_register_driver(&ccp_driver);
}
static void __exit ccp_exit(void)
{
hid_unregister_driver(&ccp_driver);
}
/*
* When compiling this driver as built-in, hwmon initcalls will get called before the
* hid driver and this driver would fail to register. late_initcall solves this.
*/
late_initcall(ccp_init);
module_exit(ccp_exit);
|
linux-master
|
drivers/hwmon/corsair-cpro.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* adm1021.c - Part of lm_sensors, Linux kernel modules for hardware
* monitoring
* Copyright (c) 1998, 1999 Frodo Looijaard <[email protected]> and
* Philip Edelbrock <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
/* Addresses to scan */
static const unsigned short normal_i2c[] = {
0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b, 0x4c, 0x4d, 0x4e, I2C_CLIENT_END };
enum chips {
adm1021, adm1023, max1617, max1617a, thmc10, lm84, gl523sm, mc1066 };
/* adm1021 constants specified below */
/* The adm1021 registers */
/* Read-only */
/* For nr in 0-1 */
#define ADM1021_REG_TEMP(nr) (nr)
#define ADM1021_REG_STATUS 0x02
/* 0x41 = AD, 0x49 = TI, 0x4D = Maxim, 0x23 = Genesys , 0x54 = Onsemi */
#define ADM1021_REG_MAN_ID 0xFE
/* ADM1021 = 0x0X, ADM1023 = 0x3X */
#define ADM1021_REG_DEV_ID 0xFF
/* These use different addresses for reading/writing */
#define ADM1021_REG_CONFIG_R 0x03
#define ADM1021_REG_CONFIG_W 0x09
#define ADM1021_REG_CONV_RATE_R 0x04
#define ADM1021_REG_CONV_RATE_W 0x0A
/* These are for the ADM1023's additional precision on the remote temp sensor */
#define ADM1023_REG_REM_TEMP_PREC 0x10
#define ADM1023_REG_REM_OFFSET 0x11
#define ADM1023_REG_REM_OFFSET_PREC 0x12
#define ADM1023_REG_REM_TOS_PREC 0x13
#define ADM1023_REG_REM_THYST_PREC 0x14
/* limits */
/* For nr in 0-1 */
#define ADM1021_REG_TOS_R(nr) (0x05 + 2 * (nr))
#define ADM1021_REG_TOS_W(nr) (0x0B + 2 * (nr))
#define ADM1021_REG_THYST_R(nr) (0x06 + 2 * (nr))
#define ADM1021_REG_THYST_W(nr) (0x0C + 2 * (nr))
/* write-only */
#define ADM1021_REG_ONESHOT 0x0F
/* Initial values */
/*
* Note: Even though I left the low and high limits named os and hyst,
* they don't quite work like a thermostat the way the LM75 does. I.e.,
* a lower temp than THYST actually triggers an alarm instead of
* clearing it. Weird, ey? --Phil
*/
/* Each client has this additional data */
struct adm1021_data {
struct i2c_client *client;
enum chips type;
const struct attribute_group *groups[3];
struct mutex update_lock;
bool valid; /* true if following fields are valid */
char low_power; /* !=0 if device in low power mode */
unsigned long last_updated; /* In jiffies */
int temp_max[2]; /* Register values */
int temp_min[2];
int temp[2];
u8 alarms;
/* Special values for ADM1023 only */
u8 remote_temp_offset;
u8 remote_temp_offset_prec;
};
/* (amalysh) read only mode, otherwise any limit's writing confuse BIOS */
static bool read_only;
static struct adm1021_data *adm1021_update_device(struct device *dev)
{
struct adm1021_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
|| !data->valid) {
int i;
dev_dbg(dev, "Starting adm1021 update\n");
for (i = 0; i < 2; i++) {
data->temp[i] = 1000 *
(s8) i2c_smbus_read_byte_data(
client, ADM1021_REG_TEMP(i));
data->temp_max[i] = 1000 *
(s8) i2c_smbus_read_byte_data(
client, ADM1021_REG_TOS_R(i));
if (data->type != lm84) {
data->temp_min[i] = 1000 *
(s8) i2c_smbus_read_byte_data(client,
ADM1021_REG_THYST_R(i));
}
}
data->alarms = i2c_smbus_read_byte_data(client,
ADM1021_REG_STATUS) & 0x7c;
if (data->type == adm1023) {
/*
* The ADM1023 provides 3 extra bits of precision for
* the remote sensor in extra registers.
*/
data->temp[1] += 125 * (i2c_smbus_read_byte_data(
client, ADM1023_REG_REM_TEMP_PREC) >> 5);
data->temp_max[1] += 125 * (i2c_smbus_read_byte_data(
client, ADM1023_REG_REM_TOS_PREC) >> 5);
data->temp_min[1] += 125 * (i2c_smbus_read_byte_data(
client, ADM1023_REG_REM_THYST_PREC) >> 5);
data->remote_temp_offset =
i2c_smbus_read_byte_data(client,
ADM1023_REG_REM_OFFSET);
data->remote_temp_offset_prec =
i2c_smbus_read_byte_data(client,
ADM1023_REG_REM_OFFSET_PREC);
}
data->last_updated = jiffies;
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
static ssize_t temp_show(struct device *dev, struct device_attribute *devattr,
char *buf)
{
int index = to_sensor_dev_attr(devattr)->index;
struct adm1021_data *data = adm1021_update_device(dev);
return sprintf(buf, "%d\n", data->temp[index]);
}
static ssize_t temp_max_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
int index = to_sensor_dev_attr(devattr)->index;
struct adm1021_data *data = adm1021_update_device(dev);
return sprintf(buf, "%d\n", data->temp_max[index]);
}
static ssize_t temp_min_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
int index = to_sensor_dev_attr(devattr)->index;
struct adm1021_data *data = adm1021_update_device(dev);
return sprintf(buf, "%d\n", data->temp_min[index]);
}
static ssize_t alarm_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int index = to_sensor_dev_attr(attr)->index;
struct adm1021_data *data = adm1021_update_device(dev);
return sprintf(buf, "%u\n", (data->alarms >> index) & 1);
}
static ssize_t alarms_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct adm1021_data *data = adm1021_update_device(dev);
return sprintf(buf, "%u\n", data->alarms);
}
static ssize_t temp_max_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
int index = to_sensor_dev_attr(devattr)->index;
struct adm1021_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
int reg_val, err;
err = kstrtol(buf, 10, &temp);
if (err)
return err;
temp /= 1000;
mutex_lock(&data->update_lock);
reg_val = clamp_val(temp, -128, 127);
data->temp_max[index] = reg_val * 1000;
if (!read_only)
i2c_smbus_write_byte_data(client, ADM1021_REG_TOS_W(index),
reg_val);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t temp_min_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
int index = to_sensor_dev_attr(devattr)->index;
struct adm1021_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long temp;
int reg_val, err;
err = kstrtol(buf, 10, &temp);
if (err)
return err;
temp /= 1000;
mutex_lock(&data->update_lock);
reg_val = clamp_val(temp, -128, 127);
data->temp_min[index] = reg_val * 1000;
if (!read_only)
i2c_smbus_write_byte_data(client, ADM1021_REG_THYST_W(index),
reg_val);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t low_power_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct adm1021_data *data = adm1021_update_device(dev);
return sprintf(buf, "%d\n", data->low_power);
}
static ssize_t low_power_store(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct adm1021_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
char low_power;
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err)
return err;
low_power = val != 0;
mutex_lock(&data->update_lock);
if (low_power != data->low_power) {
int config = i2c_smbus_read_byte_data(
client, ADM1021_REG_CONFIG_R);
data->low_power = low_power;
i2c_smbus_write_byte_data(client, ADM1021_REG_CONFIG_W,
(config & 0xBF) | (low_power << 6));
}
mutex_unlock(&data->update_lock);
return count;
}
static SENSOR_DEVICE_ATTR_RO(temp1_input, temp, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_max, temp_max, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_min, temp_min, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_input, temp, 1);
static SENSOR_DEVICE_ATTR_RW(temp2_max, temp_max, 1);
static SENSOR_DEVICE_ATTR_RW(temp2_min, temp_min, 1);
static SENSOR_DEVICE_ATTR_RO(temp1_max_alarm, alarm, 6);
static SENSOR_DEVICE_ATTR_RO(temp1_min_alarm, alarm, 5);
static SENSOR_DEVICE_ATTR_RO(temp2_max_alarm, alarm, 4);
static SENSOR_DEVICE_ATTR_RO(temp2_min_alarm, alarm, 3);
static SENSOR_DEVICE_ATTR_RO(temp2_fault, alarm, 2);
static DEVICE_ATTR_RO(alarms);
static DEVICE_ATTR_RW(low_power);
static struct attribute *adm1021_attributes[] = {
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp2_max.dev_attr.attr,
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_max_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_fault.dev_attr.attr,
&dev_attr_alarms.attr,
&dev_attr_low_power.attr,
NULL
};
static const struct attribute_group adm1021_group = {
.attrs = adm1021_attributes,
};
static struct attribute *adm1021_min_attributes[] = {
&sensor_dev_attr_temp1_min.dev_attr.attr,
&sensor_dev_attr_temp2_min.dev_attr.attr,
&sensor_dev_attr_temp1_min_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_min_alarm.dev_attr.attr,
NULL
};
static const struct attribute_group adm1021_min_group = {
.attrs = adm1021_min_attributes,
};
/* Return 0 if detection is successful, -ENODEV otherwise */
static int adm1021_detect(struct i2c_client *client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
const char *type_name;
int reg, conv_rate, status, config, man_id, dev_id;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
pr_debug("detect failed, smbus byte data not supported!\n");
return -ENODEV;
}
status = i2c_smbus_read_byte_data(client, ADM1021_REG_STATUS);
conv_rate = i2c_smbus_read_byte_data(client,
ADM1021_REG_CONV_RATE_R);
config = i2c_smbus_read_byte_data(client, ADM1021_REG_CONFIG_R);
/* Check unused bits */
if ((status & 0x03) || (config & 0x3F) || (conv_rate & 0xF8)) {
pr_debug("detect failed, chip not detected!\n");
return -ENODEV;
}
/* Determine the chip type. */
man_id = i2c_smbus_read_byte_data(client, ADM1021_REG_MAN_ID);
dev_id = i2c_smbus_read_byte_data(client, ADM1021_REG_DEV_ID);
if (man_id < 0 || dev_id < 0)
return -ENODEV;
if (man_id == 0x4d && dev_id == 0x01) {
/*
* dev_id 0x01 matches MAX6680, MAX6695, MAX6696, and possibly
* others. Read register which is unsupported on MAX1617 but
* exists on all those chips and compare with the dev_id
* register. If it matches, it may be a MAX1617A.
*/
reg = i2c_smbus_read_byte_data(client,
ADM1023_REG_REM_TEMP_PREC);
if (reg != dev_id)
return -ENODEV;
type_name = "max1617a";
} else if (man_id == 0x41) {
if ((dev_id & 0xF0) == 0x30)
type_name = "adm1023";
else if ((dev_id & 0xF0) == 0x00)
type_name = "adm1021";
else
return -ENODEV;
} else if (man_id == 0x49)
type_name = "thmc10";
else if (man_id == 0x23)
type_name = "gl523sm";
else if (man_id == 0x54)
type_name = "mc1066";
else {
int lte, rte, lhi, rhi, llo, rlo;
/* extra checks for LM84 and MAX1617 to avoid misdetections */
llo = i2c_smbus_read_byte_data(client, ADM1021_REG_THYST_R(0));
rlo = i2c_smbus_read_byte_data(client, ADM1021_REG_THYST_R(1));
/* fail if any of the additional register reads failed */
if (llo < 0 || rlo < 0)
return -ENODEV;
lte = i2c_smbus_read_byte_data(client, ADM1021_REG_TEMP(0));
rte = i2c_smbus_read_byte_data(client, ADM1021_REG_TEMP(1));
lhi = i2c_smbus_read_byte_data(client, ADM1021_REG_TOS_R(0));
rhi = i2c_smbus_read_byte_data(client, ADM1021_REG_TOS_R(1));
/*
* Fail for negative temperatures and negative high limits.
* This check also catches read errors on the tested registers.
*/
if ((s8)lte < 0 || (s8)rte < 0 || (s8)lhi < 0 || (s8)rhi < 0)
return -ENODEV;
/* fail if all registers hold the same value */
if (lte == rte && lte == lhi && lte == rhi && lte == llo
&& lte == rlo)
return -ENODEV;
/*
* LM84 Mfr ID is in a different place,
* and it has more unused bits. Registers at 0xfe and 0xff
* are undefined and return the most recently read value,
* here the value of the configuration register.
*/
if (conv_rate == 0x00
&& man_id == config && dev_id == config
&& (config & 0x7F) == 0x00
&& (status & 0xAB) == 0x00) {
type_name = "lm84";
} else {
if ((config & 0x3f) || (status & 0x03))
return -ENODEV;
/* fail if low limits are larger than high limits */
if ((s8)llo > lhi || (s8)rlo > rhi)
return -ENODEV;
type_name = "max1617";
}
}
pr_debug("Detected chip %s at adapter %d, address 0x%02x.\n",
type_name, i2c_adapter_id(adapter), client->addr);
strscpy(info->type, type_name, I2C_NAME_SIZE);
return 0;
}
static void adm1021_init_client(struct i2c_client *client)
{
/* Enable ADC and disable suspend mode */
i2c_smbus_write_byte_data(client, ADM1021_REG_CONFIG_W,
i2c_smbus_read_byte_data(client, ADM1021_REG_CONFIG_R) & 0xBF);
/* Set Conversion rate to 1/sec (this can be tinkered with) */
i2c_smbus_write_byte_data(client, ADM1021_REG_CONV_RATE_W, 0x04);
}
static const struct i2c_device_id adm1021_id[];
static int adm1021_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct adm1021_data *data;
struct device *hwmon_dev;
data = devm_kzalloc(dev, sizeof(struct adm1021_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
data->type = i2c_match_id(adm1021_id, client)->driver_data;
mutex_init(&data->update_lock);
/* Initialize the ADM1021 chip */
if (data->type != lm84 && !read_only)
adm1021_init_client(client);
data->groups[0] = &adm1021_group;
if (data->type != lm84)
data->groups[1] = &adm1021_min_group;
hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
data, data->groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id adm1021_id[] = {
{ "adm1021", adm1021 },
{ "adm1023", adm1023 },
{ "max1617", max1617 },
{ "max1617a", max1617a },
{ "thmc10", thmc10 },
{ "lm84", lm84 },
{ "gl523sm", gl523sm },
{ "mc1066", mc1066 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adm1021_id);
static struct i2c_driver adm1021_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "adm1021",
},
.probe = adm1021_probe,
.id_table = adm1021_id,
.detect = adm1021_detect,
.address_list = normal_i2c,
};
module_i2c_driver(adm1021_driver);
MODULE_AUTHOR("Frodo Looijaard <[email protected]> and "
"Philip Edelbrock <[email protected]>");
MODULE_DESCRIPTION("adm1021 driver");
MODULE_LICENSE("GPL");
module_param(read_only, bool, 0);
MODULE_PARM_DESC(read_only, "Don't set any values, read only mode");
|
linux-master
|
drivers/hwmon/adm1021.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* sbrmi.c - hwmon driver for a SB-RMI mailbox
* compliant AMD SoC device.
*
* Copyright (C) 2020-2021 Advanced Micro Devices, Inc.
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
/* Do not allow setting negative power limit */
#define SBRMI_PWR_MIN 0
/* Mask for Status Register bit[1] */
#define SW_ALERT_MASK 0x2
/* Software Interrupt for triggering */
#define START_CMD 0x80
#define TRIGGER_MAILBOX 0x01
/*
* SB-RMI supports soft mailbox service request to MP1 (power management
* firmware) through SBRMI inbound/outbound message registers.
* SB-RMI message IDs
*/
enum sbrmi_msg_id {
SBRMI_READ_PKG_PWR_CONSUMPTION = 0x1,
SBRMI_WRITE_PKG_PWR_LIMIT,
SBRMI_READ_PKG_PWR_LIMIT,
SBRMI_READ_PKG_MAX_PWR_LIMIT,
};
/* SB-RMI registers */
enum sbrmi_reg {
SBRMI_CTRL = 0x01,
SBRMI_STATUS,
SBRMI_OUTBNDMSG0 = 0x30,
SBRMI_OUTBNDMSG1,
SBRMI_OUTBNDMSG2,
SBRMI_OUTBNDMSG3,
SBRMI_OUTBNDMSG4,
SBRMI_OUTBNDMSG5,
SBRMI_OUTBNDMSG6,
SBRMI_OUTBNDMSG7,
SBRMI_INBNDMSG0,
SBRMI_INBNDMSG1,
SBRMI_INBNDMSG2,
SBRMI_INBNDMSG3,
SBRMI_INBNDMSG4,
SBRMI_INBNDMSG5,
SBRMI_INBNDMSG6,
SBRMI_INBNDMSG7,
SBRMI_SW_INTERRUPT,
};
/* Each client has this additional data */
struct sbrmi_data {
struct i2c_client *client;
struct mutex lock;
u32 pwr_limit_max;
};
struct sbrmi_mailbox_msg {
u8 cmd;
bool read;
u32 data_in;
u32 data_out;
};
static int sbrmi_enable_alert(struct i2c_client *client)
{
int ctrl;
/*
* Enable the SB-RMI Software alert status
* by writing 0 to bit 4 of Control register(0x1)
*/
ctrl = i2c_smbus_read_byte_data(client, SBRMI_CTRL);
if (ctrl < 0)
return ctrl;
if (ctrl & 0x10) {
ctrl &= ~0x10;
return i2c_smbus_write_byte_data(client,
SBRMI_CTRL, ctrl);
}
return 0;
}
static int rmi_mailbox_xfer(struct sbrmi_data *data,
struct sbrmi_mailbox_msg *msg)
{
int i, ret, retry = 10;
int sw_status;
u8 byte;
mutex_lock(&data->lock);
/* Indicate firmware a command is to be serviced */
ret = i2c_smbus_write_byte_data(data->client,
SBRMI_INBNDMSG7, START_CMD);
if (ret < 0)
goto exit_unlock;
/* Write the command to SBRMI::InBndMsg_inst0 */
ret = i2c_smbus_write_byte_data(data->client,
SBRMI_INBNDMSG0, msg->cmd);
if (ret < 0)
goto exit_unlock;
/*
* For both read and write the initiator (BMC) writes
* Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1]
* SBRMI_x3C(MSB):SBRMI_x39(LSB)
*/
for (i = 0; i < 4; i++) {
byte = (msg->data_in >> i * 8) & 0xff;
ret = i2c_smbus_write_byte_data(data->client,
SBRMI_INBNDMSG1 + i, byte);
if (ret < 0)
goto exit_unlock;
}
/*
* Write 0x01 to SBRMI::SoftwareInterrupt to notify firmware to
* perform the requested read or write command
*/
ret = i2c_smbus_write_byte_data(data->client,
SBRMI_SW_INTERRUPT, TRIGGER_MAILBOX);
if (ret < 0)
goto exit_unlock;
/*
* Firmware will write SBRMI::Status[SwAlertSts]=1 to generate
* an ALERT (if enabled) to initiator (BMC) to indicate completion
* of the requested command
*/
do {
sw_status = i2c_smbus_read_byte_data(data->client,
SBRMI_STATUS);
if (sw_status < 0) {
ret = sw_status;
goto exit_unlock;
}
if (sw_status & SW_ALERT_MASK)
break;
usleep_range(50, 100);
} while (retry--);
if (retry < 0) {
dev_err(&data->client->dev,
"Firmware fail to indicate command completion\n");
ret = -EIO;
goto exit_unlock;
}
/*
* For a read operation, the initiator (BMC) reads the firmware
* response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1]
* {SBRMI_x34(MSB):SBRMI_x31(LSB)}.
*/
if (msg->read) {
for (i = 0; i < 4; i++) {
ret = i2c_smbus_read_byte_data(data->client,
SBRMI_OUTBNDMSG1 + i);
if (ret < 0)
goto exit_unlock;
msg->data_out |= ret << i * 8;
}
}
/*
* BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the
* ALERT to initiator
*/
ret = i2c_smbus_write_byte_data(data->client, SBRMI_STATUS,
sw_status | SW_ALERT_MASK);
exit_unlock:
mutex_unlock(&data->lock);
return ret;
}
static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct sbrmi_data *data = dev_get_drvdata(dev);
struct sbrmi_mailbox_msg msg = { 0 };
int ret;
if (type != hwmon_power)
return -EINVAL;
msg.read = true;
switch (attr) {
case hwmon_power_input:
msg.cmd = SBRMI_READ_PKG_PWR_CONSUMPTION;
ret = rmi_mailbox_xfer(data, &msg);
break;
case hwmon_power_cap:
msg.cmd = SBRMI_READ_PKG_PWR_LIMIT;
ret = rmi_mailbox_xfer(data, &msg);
break;
case hwmon_power_cap_max:
msg.data_out = data->pwr_limit_max;
ret = 0;
break;
default:
return -EINVAL;
}
if (ret < 0)
return ret;
/* hwmon power attributes are in microWatt */
*val = (long)msg.data_out * 1000;
return ret;
}
static int sbrmi_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
struct sbrmi_data *data = dev_get_drvdata(dev);
struct sbrmi_mailbox_msg msg = { 0 };
if (type != hwmon_power && attr != hwmon_power_cap)
return -EINVAL;
/*
* hwmon power attributes are in microWatt
* mailbox read/write is in mWatt
*/
val /= 1000;
val = clamp_val(val, SBRMI_PWR_MIN, data->pwr_limit_max);
msg.cmd = SBRMI_WRITE_PKG_PWR_LIMIT;
msg.data_in = val;
msg.read = false;
return rmi_mailbox_xfer(data, &msg);
}
static umode_t sbrmi_is_visible(const void *data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
switch (type) {
case hwmon_power:
switch (attr) {
case hwmon_power_input:
case hwmon_power_cap_max:
return 0444;
case hwmon_power_cap:
return 0644;
}
break;
default:
break;
}
return 0;
}
static const struct hwmon_channel_info * const sbrmi_info[] = {
HWMON_CHANNEL_INFO(power,
HWMON_P_INPUT | HWMON_P_CAP | HWMON_P_CAP_MAX),
NULL
};
static const struct hwmon_ops sbrmi_hwmon_ops = {
.is_visible = sbrmi_is_visible,
.read = sbrmi_read,
.write = sbrmi_write,
};
static const struct hwmon_chip_info sbrmi_chip_info = {
.ops = &sbrmi_hwmon_ops,
.info = sbrmi_info,
};
static int sbrmi_get_max_pwr_limit(struct sbrmi_data *data)
{
struct sbrmi_mailbox_msg msg = { 0 };
int ret;
msg.cmd = SBRMI_READ_PKG_MAX_PWR_LIMIT;
msg.read = true;
ret = rmi_mailbox_xfer(data, &msg);
if (ret < 0)
return ret;
data->pwr_limit_max = msg.data_out;
return ret;
}
static int sbrmi_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct device *hwmon_dev;
struct sbrmi_data *data;
int ret;
data = devm_kzalloc(dev, sizeof(struct sbrmi_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
mutex_init(&data->lock);
/* Enable alert for SB-RMI sequence */
ret = sbrmi_enable_alert(client);
if (ret < 0)
return ret;
/* Cache maximum power limit */
ret = sbrmi_get_max_pwr_limit(data);
if (ret < 0)
return ret;
hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, data,
&sbrmi_chip_info, NULL);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id sbrmi_id[] = {
{"sbrmi", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, sbrmi_id);
static const struct of_device_id __maybe_unused sbrmi_of_match[] = {
{
.compatible = "amd,sbrmi",
},
{ },
};
MODULE_DEVICE_TABLE(of, sbrmi_of_match);
static struct i2c_driver sbrmi_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "sbrmi",
.of_match_table = of_match_ptr(sbrmi_of_match),
},
.probe = sbrmi_probe,
.id_table = sbrmi_id,
};
module_i2c_driver(sbrmi_driver);
MODULE_AUTHOR("Akshay Gupta <[email protected]>");
MODULE_DESCRIPTION("Hwmon driver for AMD SB-RMI emulated sensor");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/sbrmi.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* adm1025.c
*
* Copyright (C) 2000 Chen-Yuan Wu <[email protected]>
* Copyright (C) 2003-2009 Jean Delvare <[email protected]>
*
* The ADM1025 is a sensor chip made by Analog Devices. It reports up to 6
* voltages (including its own power source) and up to two temperatures
* (its own plus up to one external one). Voltages are scaled internally
* (which is not the common way) with ratios such that the nominal value
* of each voltage correspond to a register value of 192 (which means a
* resolution of about 0.5% of the nominal value). Temperature values are
* reported with a 1 deg resolution and a 3 deg accuracy. Complete
* datasheet can be obtained from Analog's website at:
* https://www.onsemi.com/PowerSolutions/product.do?id=ADM1025
*
* This driver also supports the ADM1025A, which differs from the ADM1025
* only in that it has "open-drain VID inputs while the ADM1025 has
* on-chip 100k pull-ups on the VID inputs". It doesn't make any
* difference for us.
*
* This driver also supports the NE1619, a sensor chip made by Philips.
* That chip is similar to the ADM1025A, with a few differences. The only
* difference that matters to us is that the NE1619 has only two possible
* addresses while the ADM1025A has a third one. Complete datasheet can be
* obtained from Philips's website at:
* http://www.semiconductors.philips.com/pip/NE1619DS.html
*
* Since the ADM1025 was the first chipset supported by this driver, most
* comments will refer to this chipset, but are actually general and
* concern all supported chipsets, unless mentioned otherwise.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/hwmon-vid.h>
#include <linux/err.h>
#include <linux/mutex.h>
/*
* Addresses to scan
* ADM1025 and ADM1025A have three possible addresses: 0x2c, 0x2d and 0x2e.
* NE1619 has two possible addresses: 0x2c and 0x2d.
*/
static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, I2C_CLIENT_END };
enum chips { adm1025, ne1619 };
/*
* The ADM1025 registers
*/
#define ADM1025_REG_MAN_ID 0x3E
#define ADM1025_REG_CHIP_ID 0x3F
#define ADM1025_REG_CONFIG 0x40
#define ADM1025_REG_STATUS1 0x41
#define ADM1025_REG_STATUS2 0x42
#define ADM1025_REG_IN(nr) (0x20 + (nr))
#define ADM1025_REG_IN_MAX(nr) (0x2B + (nr) * 2)
#define ADM1025_REG_IN_MIN(nr) (0x2C + (nr) * 2)
#define ADM1025_REG_TEMP(nr) (0x26 + (nr))
#define ADM1025_REG_TEMP_HIGH(nr) (0x37 + (nr) * 2)
#define ADM1025_REG_TEMP_LOW(nr) (0x38 + (nr) * 2)
#define ADM1025_REG_VID 0x47
#define ADM1025_REG_VID4 0x49
/*
* Conversions and various macros
* The ADM1025 uses signed 8-bit values for temperatures.
*/
static const int in_scale[6] = { 2500, 2250, 3300, 5000, 12000, 3300 };
#define IN_FROM_REG(reg, scale) (((reg) * (scale) + 96) / 192)
#define IN_TO_REG(val, scale) ((val) <= 0 ? 0 : \
(val) >= (scale) * 255 / 192 ? 255 : \
((val) * 192 + (scale) / 2) / (scale))
#define TEMP_FROM_REG(reg) ((reg) * 1000)
#define TEMP_TO_REG(val) ((val) <= -127500 ? -128 : \
(val) >= 126500 ? 127 : \
(((val) < 0 ? (val) - 500 : \
(val) + 500) / 1000))
/*
* Client data (each client gets its own)
*/
struct adm1025_data {
struct i2c_client *client;
const struct attribute_group *groups[3];
struct mutex update_lock;
bool valid; /* false until following fields are valid */
unsigned long last_updated; /* in jiffies */
u8 in[6]; /* register value */
u8 in_max[6]; /* register value */
u8 in_min[6]; /* register value */
s8 temp[2]; /* register value */
s8 temp_min[2]; /* register value */
s8 temp_max[2]; /* register value */
u16 alarms; /* register values, combined */
u8 vid; /* register values, combined */
u8 vrm;
};
static struct adm1025_data *adm1025_update_device(struct device *dev)
{
struct adm1025_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ * 2) || !data->valid) {
int i;
dev_dbg(&client->dev, "Updating data.\n");
for (i = 0; i < 6; i++) {
data->in[i] = i2c_smbus_read_byte_data(client,
ADM1025_REG_IN(i));
data->in_min[i] = i2c_smbus_read_byte_data(client,
ADM1025_REG_IN_MIN(i));
data->in_max[i] = i2c_smbus_read_byte_data(client,
ADM1025_REG_IN_MAX(i));
}
for (i = 0; i < 2; i++) {
data->temp[i] = i2c_smbus_read_byte_data(client,
ADM1025_REG_TEMP(i));
data->temp_min[i] = i2c_smbus_read_byte_data(client,
ADM1025_REG_TEMP_LOW(i));
data->temp_max[i] = i2c_smbus_read_byte_data(client,
ADM1025_REG_TEMP_HIGH(i));
}
data->alarms = i2c_smbus_read_byte_data(client,
ADM1025_REG_STATUS1)
| (i2c_smbus_read_byte_data(client,
ADM1025_REG_STATUS2) << 8);
data->vid = (i2c_smbus_read_byte_data(client,
ADM1025_REG_VID) & 0x0f)
| ((i2c_smbus_read_byte_data(client,
ADM1025_REG_VID4) & 0x01) << 4);
data->last_updated = jiffies;
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
/*
* Sysfs stuff
*/
static ssize_t
in_show(struct device *dev, struct device_attribute *attr, char *buf)
{
int index = to_sensor_dev_attr(attr)->index;
struct adm1025_data *data = adm1025_update_device(dev);
return sprintf(buf, "%u\n", IN_FROM_REG(data->in[index],
in_scale[index]));
}
static ssize_t
in_min_show(struct device *dev, struct device_attribute *attr, char *buf)
{
int index = to_sensor_dev_attr(attr)->index;
struct adm1025_data *data = adm1025_update_device(dev);
return sprintf(buf, "%u\n", IN_FROM_REG(data->in_min[index],
in_scale[index]));
}
static ssize_t
in_max_show(struct device *dev, struct device_attribute *attr, char *buf)
{
int index = to_sensor_dev_attr(attr)->index;
struct adm1025_data *data = adm1025_update_device(dev);
return sprintf(buf, "%u\n", IN_FROM_REG(data->in_max[index],
in_scale[index]));
}
static ssize_t
temp_show(struct device *dev, struct device_attribute *attr, char *buf)
{
int index = to_sensor_dev_attr(attr)->index;
struct adm1025_data *data = adm1025_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[index]));
}
static ssize_t
temp_min_show(struct device *dev, struct device_attribute *attr, char *buf)
{
int index = to_sensor_dev_attr(attr)->index;
struct adm1025_data *data = adm1025_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp_min[index]));
}
static ssize_t
temp_max_show(struct device *dev, struct device_attribute *attr, char *buf)
{
int index = to_sensor_dev_attr(attr)->index;
struct adm1025_data *data = adm1025_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp_max[index]));
}
static ssize_t in_min_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int index = to_sensor_dev_attr(attr)->index;
struct adm1025_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->in_min[index] = IN_TO_REG(val, in_scale[index]);
i2c_smbus_write_byte_data(client, ADM1025_REG_IN_MIN(index),
data->in_min[index]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t in_max_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int index = to_sensor_dev_attr(attr)->index;
struct adm1025_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->in_max[index] = IN_TO_REG(val, in_scale[index]);
i2c_smbus_write_byte_data(client, ADM1025_REG_IN_MAX(index),
data->in_max[index]);
mutex_unlock(&data->update_lock);
return count;
}
static SENSOR_DEVICE_ATTR_RO(in0_input, in, 0);
static SENSOR_DEVICE_ATTR_RW(in0_min, in_min, 0);
static SENSOR_DEVICE_ATTR_RW(in0_max, in_max, 0);
static SENSOR_DEVICE_ATTR_RO(in1_input, in, 1);
static SENSOR_DEVICE_ATTR_RW(in1_min, in_min, 1);
static SENSOR_DEVICE_ATTR_RW(in1_max, in_max, 1);
static SENSOR_DEVICE_ATTR_RO(in2_input, in, 2);
static SENSOR_DEVICE_ATTR_RW(in2_min, in_min, 2);
static SENSOR_DEVICE_ATTR_RW(in2_max, in_max, 2);
static SENSOR_DEVICE_ATTR_RO(in3_input, in, 3);
static SENSOR_DEVICE_ATTR_RW(in3_min, in_min, 3);
static SENSOR_DEVICE_ATTR_RW(in3_max, in_max, 3);
static SENSOR_DEVICE_ATTR_RO(in4_input, in, 4);
static SENSOR_DEVICE_ATTR_RW(in4_min, in_min, 4);
static SENSOR_DEVICE_ATTR_RW(in4_max, in_max, 4);
static SENSOR_DEVICE_ATTR_RO(in5_input, in, 5);
static SENSOR_DEVICE_ATTR_RW(in5_min, in_min, 5);
static SENSOR_DEVICE_ATTR_RW(in5_max, in_max, 5);
static ssize_t temp_min_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
int index = to_sensor_dev_attr(attr)->index;
struct adm1025_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->temp_min[index] = TEMP_TO_REG(val);
i2c_smbus_write_byte_data(client, ADM1025_REG_TEMP_LOW(index),
data->temp_min[index]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t temp_max_store(struct device *dev,
struct device_attribute *attr, const char *buf,
size_t count)
{
int index = to_sensor_dev_attr(attr)->index;
struct adm1025_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
long val;
int err;
err = kstrtol(buf, 10, &val);
if (err)
return err;
mutex_lock(&data->update_lock);
data->temp_max[index] = TEMP_TO_REG(val);
i2c_smbus_write_byte_data(client, ADM1025_REG_TEMP_HIGH(index),
data->temp_max[index]);
mutex_unlock(&data->update_lock);
return count;
}
static SENSOR_DEVICE_ATTR_RO(temp1_input, temp, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_min, temp_min, 0);
static SENSOR_DEVICE_ATTR_RW(temp1_max, temp_max, 0);
static SENSOR_DEVICE_ATTR_RO(temp2_input, temp, 1);
static SENSOR_DEVICE_ATTR_RW(temp2_min, temp_min, 1);
static SENSOR_DEVICE_ATTR_RW(temp2_max, temp_max, 1);
static ssize_t
alarms_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct adm1025_data *data = adm1025_update_device(dev);
return sprintf(buf, "%u\n", data->alarms);
}
static DEVICE_ATTR_RO(alarms);
static ssize_t
alarm_show(struct device *dev, struct device_attribute *attr, char *buf)
{
int bitnr = to_sensor_dev_attr(attr)->index;
struct adm1025_data *data = adm1025_update_device(dev);
return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
}
static SENSOR_DEVICE_ATTR_RO(in0_alarm, alarm, 0);
static SENSOR_DEVICE_ATTR_RO(in1_alarm, alarm, 1);
static SENSOR_DEVICE_ATTR_RO(in2_alarm, alarm, 2);
static SENSOR_DEVICE_ATTR_RO(in3_alarm, alarm, 3);
static SENSOR_DEVICE_ATTR_RO(in4_alarm, alarm, 8);
static SENSOR_DEVICE_ATTR_RO(in5_alarm, alarm, 9);
static SENSOR_DEVICE_ATTR_RO(temp1_alarm, alarm, 5);
static SENSOR_DEVICE_ATTR_RO(temp2_alarm, alarm, 4);
static SENSOR_DEVICE_ATTR_RO(temp1_fault, alarm, 14);
static ssize_t
cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct adm1025_data *data = adm1025_update_device(dev);
return sprintf(buf, "%u\n", vid_from_reg(data->vid, data->vrm));
}
static DEVICE_ATTR_RO(cpu0_vid);
static ssize_t
vrm_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct adm1025_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%u\n", data->vrm);
}
static ssize_t vrm_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct adm1025_data *data = dev_get_drvdata(dev);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err)
return err;
if (val > 255)
return -EINVAL;
data->vrm = val;
return count;
}
static DEVICE_ATTR_RW(vrm);
/*
* Real code
*/
static struct attribute *adm1025_attributes[] = {
&sensor_dev_attr_in0_input.dev_attr.attr,
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in2_input.dev_attr.attr,
&sensor_dev_attr_in3_input.dev_attr.attr,
&sensor_dev_attr_in5_input.dev_attr.attr,
&sensor_dev_attr_in0_min.dev_attr.attr,
&sensor_dev_attr_in1_min.dev_attr.attr,
&sensor_dev_attr_in2_min.dev_attr.attr,
&sensor_dev_attr_in3_min.dev_attr.attr,
&sensor_dev_attr_in5_min.dev_attr.attr,
&sensor_dev_attr_in0_max.dev_attr.attr,
&sensor_dev_attr_in1_max.dev_attr.attr,
&sensor_dev_attr_in2_max.dev_attr.attr,
&sensor_dev_attr_in3_max.dev_attr.attr,
&sensor_dev_attr_in5_max.dev_attr.attr,
&sensor_dev_attr_in0_alarm.dev_attr.attr,
&sensor_dev_attr_in1_alarm.dev_attr.attr,
&sensor_dev_attr_in2_alarm.dev_attr.attr,
&sensor_dev_attr_in3_alarm.dev_attr.attr,
&sensor_dev_attr_in5_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp1_min.dev_attr.attr,
&sensor_dev_attr_temp2_min.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp2_max.dev_attr.attr,
&sensor_dev_attr_temp1_alarm.dev_attr.attr,
&sensor_dev_attr_temp2_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_fault.dev_attr.attr,
&dev_attr_alarms.attr,
&dev_attr_cpu0_vid.attr,
&dev_attr_vrm.attr,
NULL
};
static const struct attribute_group adm1025_group = {
.attrs = adm1025_attributes,
};
static struct attribute *adm1025_attributes_in4[] = {
&sensor_dev_attr_in4_input.dev_attr.attr,
&sensor_dev_attr_in4_min.dev_attr.attr,
&sensor_dev_attr_in4_max.dev_attr.attr,
&sensor_dev_attr_in4_alarm.dev_attr.attr,
NULL
};
static const struct attribute_group adm1025_group_in4 = {
.attrs = adm1025_attributes_in4,
};
/* Return 0 if detection is successful, -ENODEV otherwise */
static int adm1025_detect(struct i2c_client *client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
const char *name;
u8 man_id, chip_id;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
/* Check for unused bits */
if ((i2c_smbus_read_byte_data(client, ADM1025_REG_CONFIG) & 0x80)
|| (i2c_smbus_read_byte_data(client, ADM1025_REG_STATUS1) & 0xC0)
|| (i2c_smbus_read_byte_data(client, ADM1025_REG_STATUS2) & 0xBC)) {
dev_dbg(&adapter->dev, "ADM1025 detection failed at 0x%02x\n",
client->addr);
return -ENODEV;
}
/* Identification */
chip_id = i2c_smbus_read_byte_data(client, ADM1025_REG_CHIP_ID);
if ((chip_id & 0xF0) != 0x20)
return -ENODEV;
man_id = i2c_smbus_read_byte_data(client, ADM1025_REG_MAN_ID);
if (man_id == 0x41)
name = "adm1025";
else if (man_id == 0xA1 && client->addr != 0x2E)
name = "ne1619";
else
return -ENODEV;
strscpy(info->type, name, I2C_NAME_SIZE);
return 0;
}
static void adm1025_init_client(struct i2c_client *client)
{
u8 reg;
struct adm1025_data *data = i2c_get_clientdata(client);
int i;
data->vrm = vid_which_vrm();
/*
* Set high limits
* Usually we avoid setting limits on driver init, but it happens
* that the ADM1025 comes with stupid default limits (all registers
* set to 0). In case the chip has not gone through any limit
* setting yet, we better set the high limits to the max so that
* no alarm triggers.
*/
for (i = 0; i < 6; i++) {
reg = i2c_smbus_read_byte_data(client,
ADM1025_REG_IN_MAX(i));
if (reg == 0)
i2c_smbus_write_byte_data(client,
ADM1025_REG_IN_MAX(i),
0xFF);
}
for (i = 0; i < 2; i++) {
reg = i2c_smbus_read_byte_data(client,
ADM1025_REG_TEMP_HIGH(i));
if (reg == 0)
i2c_smbus_write_byte_data(client,
ADM1025_REG_TEMP_HIGH(i),
0x7F);
}
/*
* Start the conversions
*/
reg = i2c_smbus_read_byte_data(client, ADM1025_REG_CONFIG);
if (!(reg & 0x01))
i2c_smbus_write_byte_data(client, ADM1025_REG_CONFIG,
(reg&0x7E)|0x01);
}
static int adm1025_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct device *hwmon_dev;
struct adm1025_data *data;
u8 config;
data = devm_kzalloc(dev, sizeof(struct adm1025_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
i2c_set_clientdata(client, data);
data->client = client;
mutex_init(&data->update_lock);
/* Initialize the ADM1025 chip */
adm1025_init_client(client);
/* sysfs hooks */
data->groups[0] = &adm1025_group;
/* Pin 11 is either in4 (+12V) or VID4 */
config = i2c_smbus_read_byte_data(client, ADM1025_REG_CONFIG);
if (!(config & 0x20))
data->groups[1] = &adm1025_group_in4;
hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
data, data->groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id adm1025_id[] = {
{ "adm1025", adm1025 },
{ "ne1619", ne1619 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adm1025_id);
static struct i2c_driver adm1025_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "adm1025",
},
.probe = adm1025_probe,
.id_table = adm1025_id,
.detect = adm1025_detect,
.address_list = normal_i2c,
};
module_i2c_driver(adm1025_driver);
MODULE_AUTHOR("Jean Delvare <[email protected]>");
MODULE_DESCRIPTION("ADM1025 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/adm1025.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Copyright (C) 2010-2012 Hans de Goede <[email protected]> *
* *
***************************************************************************/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/platform_device.h>
#include <linux/hwmon.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include "sch56xx-common.h"
#define DRVNAME "sch5627"
#define DEVNAME DRVNAME /* We only support one model */
#define SCH5627_HWMON_ID 0xa5
#define SCH5627_COMPANY_ID 0x5c
#define SCH5627_PRIMARY_ID 0xa0
#define SCH5627_REG_BUILD_CODE 0x39
#define SCH5627_REG_BUILD_ID 0x3a
#define SCH5627_REG_HWMON_ID 0x3c
#define SCH5627_REG_HWMON_REV 0x3d
#define SCH5627_REG_COMPANY_ID 0x3e
#define SCH5627_REG_PRIMARY_ID 0x3f
#define SCH5627_REG_CTRL 0x40
#define SCH5627_NO_TEMPS 8
#define SCH5627_NO_FANS 4
#define SCH5627_NO_IN 5
static const u16 SCH5627_REG_TEMP_MSB[SCH5627_NO_TEMPS] = {
0x2B, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x180, 0x181 };
static const u16 SCH5627_REG_TEMP_LSN[SCH5627_NO_TEMPS] = {
0xE2, 0xE1, 0xE1, 0xE5, 0xE5, 0xE6, 0x182, 0x182 };
static const u16 SCH5627_REG_TEMP_HIGH_NIBBLE[SCH5627_NO_TEMPS] = {
0, 0, 1, 1, 0, 0, 0, 1 };
static const u16 SCH5627_REG_TEMP_HIGH[SCH5627_NO_TEMPS] = {
0x61, 0x57, 0x59, 0x5B, 0x5D, 0x5F, 0x184, 0x186 };
static const u16 SCH5627_REG_TEMP_ABS[SCH5627_NO_TEMPS] = {
0x9B, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x1A8, 0x1A9 };
static const u16 SCH5627_REG_FAN[SCH5627_NO_FANS] = {
0x2C, 0x2E, 0x30, 0x32 };
static const u16 SCH5627_REG_FAN_MIN[SCH5627_NO_FANS] = {
0x62, 0x64, 0x66, 0x68 };
static const u16 SCH5627_REG_PWM_MAP[SCH5627_NO_FANS] = {
0xA0, 0xA1, 0xA2, 0xA3 };
static const u16 SCH5627_REG_IN_MSB[SCH5627_NO_IN] = {
0x22, 0x23, 0x24, 0x25, 0x189 };
static const u16 SCH5627_REG_IN_LSN[SCH5627_NO_IN] = {
0xE4, 0xE4, 0xE3, 0xE3, 0x18A };
static const u16 SCH5627_REG_IN_HIGH_NIBBLE[SCH5627_NO_IN] = {
1, 0, 1, 0, 1 };
static const u16 SCH5627_REG_IN_FACTOR[SCH5627_NO_IN] = {
10745, 3660, 9765, 10745, 3660 };
static const char * const SCH5627_IN_LABELS[SCH5627_NO_IN] = {
"VCC", "VTT", "VBAT", "VTR", "V_IN" };
struct sch5627_data {
unsigned short addr;
u8 control;
u8 temp_max[SCH5627_NO_TEMPS];
u8 temp_crit[SCH5627_NO_TEMPS];
u16 fan_min[SCH5627_NO_FANS];
struct mutex update_lock;
unsigned long last_battery; /* In jiffies */
char temp_valid; /* !=0 if following fields are valid */
char fan_valid;
char in_valid;
unsigned long temp_last_updated; /* In jiffies */
unsigned long fan_last_updated;
unsigned long in_last_updated;
u16 temp[SCH5627_NO_TEMPS];
u16 fan[SCH5627_NO_FANS];
u16 in[SCH5627_NO_IN];
};
static int sch5627_update_temp(struct sch5627_data *data)
{
int ret = 0;
int i, val;
mutex_lock(&data->update_lock);
/* Cache the values for 1 second */
if (time_after(jiffies, data->temp_last_updated + HZ) || !data->temp_valid) {
for (i = 0; i < SCH5627_NO_TEMPS; i++) {
val = sch56xx_read_virtual_reg12(data->addr, SCH5627_REG_TEMP_MSB[i],
SCH5627_REG_TEMP_LSN[i],
SCH5627_REG_TEMP_HIGH_NIBBLE[i]);
if (unlikely(val < 0)) {
ret = val;
goto abort;
}
data->temp[i] = val;
}
data->temp_last_updated = jiffies;
data->temp_valid = 1;
}
abort:
mutex_unlock(&data->update_lock);
return ret;
}
static int sch5627_update_fan(struct sch5627_data *data)
{
int ret = 0;
int i, val;
mutex_lock(&data->update_lock);
/* Cache the values for 1 second */
if (time_after(jiffies, data->fan_last_updated + HZ) || !data->fan_valid) {
for (i = 0; i < SCH5627_NO_FANS; i++) {
val = sch56xx_read_virtual_reg16(data->addr, SCH5627_REG_FAN[i]);
if (unlikely(val < 0)) {
ret = val;
goto abort;
}
data->fan[i] = val;
}
data->fan_last_updated = jiffies;
data->fan_valid = 1;
}
abort:
mutex_unlock(&data->update_lock);
return ret;
}
static int sch5627_update_in(struct sch5627_data *data)
{
int ret = 0;
int i, val;
mutex_lock(&data->update_lock);
/* Trigger a Vbat voltage measurement every 5 minutes */
if (time_after(jiffies, data->last_battery + 300 * HZ)) {
sch56xx_write_virtual_reg(data->addr, SCH5627_REG_CTRL, data->control | 0x10);
data->last_battery = jiffies;
}
/* Cache the values for 1 second */
if (time_after(jiffies, data->in_last_updated + HZ) || !data->in_valid) {
for (i = 0; i < SCH5627_NO_IN; i++) {
val = sch56xx_read_virtual_reg12(data->addr, SCH5627_REG_IN_MSB[i],
SCH5627_REG_IN_LSN[i],
SCH5627_REG_IN_HIGH_NIBBLE[i]);
if (unlikely(val < 0)) {
ret = val;
goto abort;
}
data->in[i] = val;
}
data->in_last_updated = jiffies;
data->in_valid = 1;
}
abort:
mutex_unlock(&data->update_lock);
return ret;
}
static int sch5627_read_limits(struct sch5627_data *data)
{
int i, val;
for (i = 0; i < SCH5627_NO_TEMPS; i++) {
/*
* Note what SMSC calls ABS, is what lm_sensors calls max
* (aka high), and HIGH is what lm_sensors calls crit.
*/
val = sch56xx_read_virtual_reg(data->addr,
SCH5627_REG_TEMP_ABS[i]);
if (val < 0)
return val;
data->temp_max[i] = val;
val = sch56xx_read_virtual_reg(data->addr,
SCH5627_REG_TEMP_HIGH[i]);
if (val < 0)
return val;
data->temp_crit[i] = val;
}
for (i = 0; i < SCH5627_NO_FANS; i++) {
val = sch56xx_read_virtual_reg16(data->addr,
SCH5627_REG_FAN_MIN[i]);
if (val < 0)
return val;
data->fan_min[i] = val;
}
return 0;
}
static int reg_to_temp(u16 reg)
{
return (reg * 625) / 10 - 64000;
}
static int reg_to_temp_limit(u8 reg)
{
return (reg - 64) * 1000;
}
static int reg_to_rpm(u16 reg)
{
if (reg == 0)
return -EIO;
if (reg == 0xffff)
return 0;
return 5400540 / reg;
}
static umode_t sch5627_is_visible(const void *drvdata, enum hwmon_sensor_types type, u32 attr,
int channel)
{
if (type == hwmon_pwm && attr == hwmon_pwm_auto_channels_temp)
return 0644;
return 0444;
}
static int sch5627_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
long *val)
{
struct sch5627_data *data = dev_get_drvdata(dev);
int ret;
switch (type) {
case hwmon_temp:
ret = sch5627_update_temp(data);
if (ret < 0)
return ret;
switch (attr) {
case hwmon_temp_input:
*val = reg_to_temp(data->temp[channel]);
return 0;
case hwmon_temp_max:
*val = reg_to_temp_limit(data->temp_max[channel]);
return 0;
case hwmon_temp_crit:
*val = reg_to_temp_limit(data->temp_crit[channel]);
return 0;
case hwmon_temp_fault:
*val = (data->temp[channel] == 0);
return 0;
default:
break;
}
break;
case hwmon_fan:
ret = sch5627_update_fan(data);
if (ret < 0)
return ret;
switch (attr) {
case hwmon_fan_input:
ret = reg_to_rpm(data->fan[channel]);
if (ret < 0)
return ret;
*val = ret;
return 0;
case hwmon_fan_min:
ret = reg_to_rpm(data->fan_min[channel]);
if (ret < 0)
return ret;
*val = ret;
return 0;
case hwmon_fan_fault:
*val = (data->fan[channel] == 0xffff);
return 0;
default:
break;
}
break;
case hwmon_pwm:
switch (attr) {
case hwmon_pwm_auto_channels_temp:
mutex_lock(&data->update_lock);
ret = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_PWM_MAP[channel]);
mutex_unlock(&data->update_lock);
if (ret < 0)
return ret;
*val = ret;
return 0;
default:
break;
}
break;
case hwmon_in:
ret = sch5627_update_in(data);
if (ret < 0)
return ret;
switch (attr) {
case hwmon_in_input:
*val = DIV_ROUND_CLOSEST(data->in[channel] * SCH5627_REG_IN_FACTOR[channel],
10000);
return 0;
default:
break;
}
break;
default:
break;
}
return -EOPNOTSUPP;
}
static int sch5627_read_string(struct device *dev, enum hwmon_sensor_types type, u32 attr,
int channel, const char **str)
{
switch (type) {
case hwmon_in:
switch (attr) {
case hwmon_in_label:
*str = SCH5627_IN_LABELS[channel];
return 0;
default:
break;
}
break;
default:
break;
}
return -EOPNOTSUPP;
}
static int sch5627_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
long val)
{
struct sch5627_data *data = dev_get_drvdata(dev);
int ret;
switch (type) {
case hwmon_pwm:
switch (attr) {
case hwmon_pwm_auto_channels_temp:
/* registers are 8 bit wide */
if (val > U8_MAX || val < 0)
return -EINVAL;
mutex_lock(&data->update_lock);
ret = sch56xx_write_virtual_reg(data->addr, SCH5627_REG_PWM_MAP[channel],
val);
mutex_unlock(&data->update_lock);
return ret;
default:
break;
}
break;
default:
break;
}
return -EOPNOTSUPP;
}
static const struct hwmon_ops sch5627_ops = {
.is_visible = sch5627_is_visible,
.read = sch5627_read,
.read_string = sch5627_read_string,
.write = sch5627_write,
};
static const struct hwmon_channel_info * const sch5627_info[] = {
HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_FAULT,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_FAULT,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_FAULT,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_FAULT,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_FAULT,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_FAULT,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_FAULT,
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_FAULT
),
HWMON_CHANNEL_INFO(fan,
HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_FAULT,
HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_FAULT,
HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_FAULT,
HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_FAULT
),
HWMON_CHANNEL_INFO(pwm,
HWMON_PWM_AUTO_CHANNELS_TEMP,
HWMON_PWM_AUTO_CHANNELS_TEMP,
HWMON_PWM_AUTO_CHANNELS_TEMP,
HWMON_PWM_AUTO_CHANNELS_TEMP
),
HWMON_CHANNEL_INFO(in,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT | HWMON_I_LABEL,
HWMON_I_INPUT
),
NULL
};
static const struct hwmon_chip_info sch5627_chip_info = {
.ops = &sch5627_ops,
.info = sch5627_info,
};
static int sch5627_probe(struct platform_device *pdev)
{
struct sch5627_data *data;
struct device *hwmon_dev;
int err, build_code, build_id, hwmon_rev, val;
data = devm_kzalloc(&pdev->dev, sizeof(struct sch5627_data),
GFP_KERNEL);
if (!data)
return -ENOMEM;
data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start;
mutex_init(&data->update_lock);
platform_set_drvdata(pdev, data);
val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_HWMON_ID);
if (val < 0)
return val;
if (val != SCH5627_HWMON_ID) {
pr_err("invalid %s id: 0x%02X (expected 0x%02X)\n", "hwmon",
val, SCH5627_HWMON_ID);
return -ENODEV;
}
val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_COMPANY_ID);
if (val < 0)
return val;
if (val != SCH5627_COMPANY_ID) {
pr_err("invalid %s id: 0x%02X (expected 0x%02X)\n", "company",
val, SCH5627_COMPANY_ID);
return -ENODEV;
}
val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_PRIMARY_ID);
if (val < 0)
return val;
if (val != SCH5627_PRIMARY_ID) {
pr_err("invalid %s id: 0x%02X (expected 0x%02X)\n", "primary",
val, SCH5627_PRIMARY_ID);
return -ENODEV;
}
build_code = sch56xx_read_virtual_reg(data->addr,
SCH5627_REG_BUILD_CODE);
if (build_code < 0)
return build_code;
build_id = sch56xx_read_virtual_reg16(data->addr,
SCH5627_REG_BUILD_ID);
if (build_id < 0)
return build_id;
hwmon_rev = sch56xx_read_virtual_reg(data->addr,
SCH5627_REG_HWMON_REV);
if (hwmon_rev < 0)
return hwmon_rev;
val = sch56xx_read_virtual_reg(data->addr, SCH5627_REG_CTRL);
if (val < 0)
return val;
data->control = val;
if (!(data->control & 0x01)) {
pr_err("hardware monitoring not enabled\n");
return -ENODEV;
}
/* Trigger a Vbat voltage measurement, so that we get a valid reading
the first time we read Vbat */
sch56xx_write_virtual_reg(data->addr, SCH5627_REG_CTRL,
data->control | 0x10);
data->last_battery = jiffies;
/*
* Read limits, we do this only once as reading a register on
* the sch5627 is quite expensive (and they don't change).
*/
err = sch5627_read_limits(data);
if (err)
return err;
pr_info("found %s chip at %#hx\n", DEVNAME, data->addr);
pr_info("firmware build: code 0x%02X, id 0x%04X, hwmon: rev 0x%02X\n",
build_code, build_id, hwmon_rev);
hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, DEVNAME, data,
&sch5627_chip_info, NULL);
if (IS_ERR(hwmon_dev))
return PTR_ERR(hwmon_dev);
/* Note failing to register the watchdog is not a fatal error */
sch56xx_watchdog_register(&pdev->dev, data->addr,
(build_code << 24) | (build_id << 8) | hwmon_rev,
&data->update_lock, 1);
return 0;
}
static const struct platform_device_id sch5627_device_id[] = {
{
.name = "sch5627",
},
{ }
};
MODULE_DEVICE_TABLE(platform, sch5627_device_id);
static struct platform_driver sch5627_driver = {
.driver = {
.name = DRVNAME,
},
.probe = sch5627_probe,
.id_table = sch5627_device_id,
};
module_platform_driver(sch5627_driver);
MODULE_DESCRIPTION("SMSC SCH5627 Hardware Monitoring Driver");
MODULE_AUTHOR("Hans de Goede <[email protected]>");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/sch5627.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for Linear Technology LTC4215 I2C Hot Swap Controller
*
* Copyright (C) 2009 Ira W. Snyder <[email protected]>
*
* Datasheet:
* http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1003,C1006,C1163,P17572,D12697
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/jiffies.h>
/* Here are names of the chip's registers (a.k.a. commands) */
enum ltc4215_cmd {
LTC4215_CONTROL = 0x00, /* rw */
LTC4215_ALERT = 0x01, /* rw */
LTC4215_STATUS = 0x02, /* ro */
LTC4215_FAULT = 0x03, /* rw */
LTC4215_SENSE = 0x04, /* rw */
LTC4215_SOURCE = 0x05, /* rw */
LTC4215_ADIN = 0x06, /* rw */
};
struct ltc4215_data {
struct i2c_client *client;
struct mutex update_lock;
bool valid;
unsigned long last_updated; /* in jiffies */
/* Registers */
u8 regs[7];
};
static struct ltc4215_data *ltc4215_update_device(struct device *dev)
{
struct ltc4215_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
s32 val;
int i;
mutex_lock(&data->update_lock);
/* The chip's A/D updates 10 times per second */
if (time_after(jiffies, data->last_updated + HZ / 10) || !data->valid) {
dev_dbg(&client->dev, "Starting ltc4215 update\n");
/* Read all registers */
for (i = 0; i < ARRAY_SIZE(data->regs); i++) {
val = i2c_smbus_read_byte_data(client, i);
if (unlikely(val < 0))
data->regs[i] = 0;
else
data->regs[i] = val;
}
data->last_updated = jiffies;
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
/* Return the voltage from the given register in millivolts */
static int ltc4215_get_voltage(struct device *dev, u8 reg)
{
struct ltc4215_data *data = ltc4215_update_device(dev);
const u8 regval = data->regs[reg];
u32 voltage = 0;
switch (reg) {
case LTC4215_SENSE:
/* 151 uV per increment */
voltage = regval * 151 / 1000;
break;
case LTC4215_SOURCE:
/* 60.5 mV per increment */
voltage = regval * 605 / 10;
break;
case LTC4215_ADIN:
/*
* The ADIN input is divided by 12.5, and has 4.82 mV
* per increment, so we have the additional multiply
*/
voltage = regval * 482 * 125 / 1000;
break;
default:
/* If we get here, the developer messed up */
WARN_ON_ONCE(1);
break;
}
return voltage;
}
/* Return the current from the sense resistor in mA */
static unsigned int ltc4215_get_current(struct device *dev)
{
struct ltc4215_data *data = ltc4215_update_device(dev);
/*
* The strange looking conversions that follow are fixed-point
* math, since we cannot do floating point in the kernel.
*
* Step 1: convert sense register to microVolts
* Step 2: convert voltage to milliAmperes
*
* If you play around with the V=IR equation, you come up with
* the following: X uV / Y mOhm == Z mA
*
* With the resistors that are fractions of a milliOhm, we multiply
* the voltage and resistance by 10, to shift the decimal point.
* Now we can use the normal division operator again.
*/
/* Calculate voltage in microVolts (151 uV per increment) */
const unsigned int voltage = data->regs[LTC4215_SENSE] * 151;
/* Calculate current in milliAmperes (4 milliOhm sense resistor) */
const unsigned int curr = voltage / 4;
return curr;
}
static ssize_t ltc4215_voltage_show(struct device *dev,
struct device_attribute *da, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
const int voltage = ltc4215_get_voltage(dev, attr->index);
return sysfs_emit(buf, "%d\n", voltage);
}
static ssize_t ltc4215_current_show(struct device *dev,
struct device_attribute *da, char *buf)
{
const unsigned int curr = ltc4215_get_current(dev);
return sysfs_emit(buf, "%u\n", curr);
}
static ssize_t ltc4215_power_show(struct device *dev,
struct device_attribute *da, char *buf)
{
const unsigned int curr = ltc4215_get_current(dev);
const int output_voltage = ltc4215_get_voltage(dev, LTC4215_ADIN);
/* current in mA * voltage in mV == power in uW */
const unsigned int power = abs(output_voltage * curr);
return sysfs_emit(buf, "%u\n", power);
}
static ssize_t ltc4215_alarm_show(struct device *dev,
struct device_attribute *da, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
struct ltc4215_data *data = ltc4215_update_device(dev);
const u8 reg = data->regs[LTC4215_STATUS];
const u32 mask = attr->index;
return sysfs_emit(buf, "%u\n", !!(reg & mask));
}
/*
* These macros are used below in constructing device attribute objects
* for use with sysfs_create_group() to make a sysfs device file
* for each register.
*/
/* Construct a sensor_device_attribute structure for each register */
/* Current */
static SENSOR_DEVICE_ATTR_RO(curr1_input, ltc4215_current, 0);
static SENSOR_DEVICE_ATTR_RO(curr1_max_alarm, ltc4215_alarm, 1 << 2);
/* Power (virtual) */
static SENSOR_DEVICE_ATTR_RO(power1_input, ltc4215_power, 0);
/* Input Voltage */
static SENSOR_DEVICE_ATTR_RO(in1_input, ltc4215_voltage, LTC4215_ADIN);
static SENSOR_DEVICE_ATTR_RO(in1_max_alarm, ltc4215_alarm, 1 << 0);
static SENSOR_DEVICE_ATTR_RO(in1_min_alarm, ltc4215_alarm, 1 << 1);
/* Output Voltage */
static SENSOR_DEVICE_ATTR_RO(in2_input, ltc4215_voltage, LTC4215_SOURCE);
static SENSOR_DEVICE_ATTR_RO(in2_min_alarm, ltc4215_alarm, 1 << 3);
/*
* Finally, construct an array of pointers to members of the above objects,
* as required for sysfs_create_group()
*/
static struct attribute *ltc4215_attrs[] = {
&sensor_dev_attr_curr1_input.dev_attr.attr,
&sensor_dev_attr_curr1_max_alarm.dev_attr.attr,
&sensor_dev_attr_power1_input.dev_attr.attr,
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in1_max_alarm.dev_attr.attr,
&sensor_dev_attr_in1_min_alarm.dev_attr.attr,
&sensor_dev_attr_in2_input.dev_attr.attr,
&sensor_dev_attr_in2_min_alarm.dev_attr.attr,
NULL,
};
ATTRIBUTE_GROUPS(ltc4215);
static int ltc4215_probe(struct i2c_client *client)
{
struct i2c_adapter *adapter = client->adapter;
struct device *dev = &client->dev;
struct ltc4215_data *data;
struct device *hwmon_dev;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
mutex_init(&data->update_lock);
/* Initialize the LTC4215 chip */
i2c_smbus_write_byte_data(client, LTC4215_FAULT, 0x00);
hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
data,
ltc4215_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id ltc4215_id[] = {
{ "ltc4215", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ltc4215_id);
/* This is the driver that will be inserted */
static struct i2c_driver ltc4215_driver = {
.driver = {
.name = "ltc4215",
},
.probe = ltc4215_probe,
.id_table = ltc4215_id,
};
module_i2c_driver(ltc4215_driver);
MODULE_AUTHOR("Ira W. Snyder <[email protected]>");
MODULE_DESCRIPTION("LTC4215 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/ltc4215.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* A hwmon driver for ACPI 4.0 power meters
* Copyright (C) 2009 IBM
*
* Author: Darrick J. Wong <[email protected]>
*/
#include <linux/module.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/jiffies.h>
#include <linux/mutex.h>
#include <linux/dmi.h>
#include <linux/slab.h>
#include <linux/kdev_t.h>
#include <linux/sched.h>
#include <linux/time.h>
#include <linux/err.h>
#include <linux/acpi.h>
#define ACPI_POWER_METER_NAME "power_meter"
#define ACPI_POWER_METER_DEVICE_NAME "Power Meter"
#define ACPI_POWER_METER_CLASS "pwr_meter_resource"
#define NUM_SENSORS 17
#define POWER_METER_CAN_MEASURE (1 << 0)
#define POWER_METER_CAN_TRIP (1 << 1)
#define POWER_METER_CAN_CAP (1 << 2)
#define POWER_METER_CAN_NOTIFY (1 << 3)
#define POWER_METER_IS_BATTERY (1 << 8)
#define UNKNOWN_HYSTERESIS 0xFFFFFFFF
#define METER_NOTIFY_CONFIG 0x80
#define METER_NOTIFY_TRIP 0x81
#define METER_NOTIFY_CAP 0x82
#define METER_NOTIFY_CAPPING 0x83
#define METER_NOTIFY_INTERVAL 0x84
#define POWER_AVERAGE_NAME "power1_average"
#define POWER_CAP_NAME "power1_cap"
#define POWER_AVG_INTERVAL_NAME "power1_average_interval"
#define POWER_ALARM_NAME "power1_alarm"
static int cap_in_hardware;
static bool force_cap_on;
static int can_cap_in_hardware(void)
{
return force_cap_on || cap_in_hardware;
}
static const struct acpi_device_id power_meter_ids[] = {
{"ACPI000D", 0},
{"", 0},
};
MODULE_DEVICE_TABLE(acpi, power_meter_ids);
struct acpi_power_meter_capabilities {
u64 flags;
u64 units;
u64 type;
u64 accuracy;
u64 sampling_time;
u64 min_avg_interval;
u64 max_avg_interval;
u64 hysteresis;
u64 configurable_cap;
u64 min_cap;
u64 max_cap;
};
struct acpi_power_meter_resource {
struct acpi_device *acpi_dev;
acpi_bus_id name;
struct mutex lock;
struct device *hwmon_dev;
struct acpi_power_meter_capabilities caps;
acpi_string model_number;
acpi_string serial_number;
acpi_string oem_info;
u64 power;
u64 cap;
u64 avg_interval;
int sensors_valid;
unsigned long sensors_last_updated;
struct sensor_device_attribute sensors[NUM_SENSORS];
int num_sensors;
s64 trip[2];
int num_domain_devices;
struct acpi_device **domain_devices;
struct kobject *holders_dir;
};
struct sensor_template {
char *label;
ssize_t (*show)(struct device *dev,
struct device_attribute *devattr,
char *buf);
ssize_t (*set)(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count);
int index;
};
/* Averaging interval */
static int update_avg_interval(struct acpi_power_meter_resource *resource)
{
unsigned long long data;
acpi_status status;
status = acpi_evaluate_integer(resource->acpi_dev->handle, "_GAI",
NULL, &data);
if (ACPI_FAILURE(status)) {
acpi_evaluation_failure_warn(resource->acpi_dev->handle, "_GAI",
status);
return -ENODEV;
}
resource->avg_interval = data;
return 0;
}
static ssize_t show_avg_interval(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct acpi_device *acpi_dev = to_acpi_device(dev);
struct acpi_power_meter_resource *resource = acpi_dev->driver_data;
mutex_lock(&resource->lock);
update_avg_interval(resource);
mutex_unlock(&resource->lock);
return sprintf(buf, "%llu\n", resource->avg_interval);
}
static ssize_t set_avg_interval(struct device *dev,
struct device_attribute *devattr,
const char *buf, size_t count)
{
struct acpi_device *acpi_dev = to_acpi_device(dev);
struct acpi_power_meter_resource *resource = acpi_dev->driver_data;
union acpi_object arg0 = { ACPI_TYPE_INTEGER };
struct acpi_object_list args = { 1, &arg0 };
int res;
unsigned long temp;
unsigned long long data;
acpi_status status;
res = kstrtoul(buf, 10, &temp);
if (res)
return res;
if (temp > resource->caps.max_avg_interval ||
temp < resource->caps.min_avg_interval)
return -EINVAL;
arg0.integer.value = temp;
mutex_lock(&resource->lock);
status = acpi_evaluate_integer(resource->acpi_dev->handle, "_PAI",
&args, &data);
if (ACPI_SUCCESS(status))
resource->avg_interval = temp;
mutex_unlock(&resource->lock);
if (ACPI_FAILURE(status)) {
acpi_evaluation_failure_warn(resource->acpi_dev->handle, "_PAI",
status);
return -EINVAL;
}
/* _PAI returns 0 on success, nonzero otherwise */
if (data)
return -EINVAL;
return count;
}
/* Cap functions */
static int update_cap(struct acpi_power_meter_resource *resource)
{
unsigned long long data;
acpi_status status;
status = acpi_evaluate_integer(resource->acpi_dev->handle, "_GHL",
NULL, &data);
if (ACPI_FAILURE(status)) {
acpi_evaluation_failure_warn(resource->acpi_dev->handle, "_GHL",
status);
return -ENODEV;
}
resource->cap = data;
return 0;
}
static ssize_t show_cap(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct acpi_device *acpi_dev = to_acpi_device(dev);
struct acpi_power_meter_resource *resource = acpi_dev->driver_data;
mutex_lock(&resource->lock);
update_cap(resource);
mutex_unlock(&resource->lock);
return sprintf(buf, "%llu\n", resource->cap * 1000);
}
static ssize_t set_cap(struct device *dev, struct device_attribute *devattr,
const char *buf, size_t count)
{
struct acpi_device *acpi_dev = to_acpi_device(dev);
struct acpi_power_meter_resource *resource = acpi_dev->driver_data;
union acpi_object arg0 = { ACPI_TYPE_INTEGER };
struct acpi_object_list args = { 1, &arg0 };
int res;
unsigned long temp;
unsigned long long data;
acpi_status status;
res = kstrtoul(buf, 10, &temp);
if (res)
return res;
temp = DIV_ROUND_CLOSEST(temp, 1000);
if (temp > resource->caps.max_cap || temp < resource->caps.min_cap)
return -EINVAL;
arg0.integer.value = temp;
mutex_lock(&resource->lock);
status = acpi_evaluate_integer(resource->acpi_dev->handle, "_SHL",
&args, &data);
if (ACPI_SUCCESS(status))
resource->cap = temp;
mutex_unlock(&resource->lock);
if (ACPI_FAILURE(status)) {
acpi_evaluation_failure_warn(resource->acpi_dev->handle, "_SHL",
status);
return -EINVAL;
}
/* _SHL returns 0 on success, nonzero otherwise */
if (data)
return -EINVAL;
return count;
}
/* Power meter trip points */
static int set_acpi_trip(struct acpi_power_meter_resource *resource)
{
union acpi_object arg_objs[] = {
{ACPI_TYPE_INTEGER},
{ACPI_TYPE_INTEGER}
};
struct acpi_object_list args = { 2, arg_objs };
unsigned long long data;
acpi_status status;
/* Both trip levels must be set */
if (resource->trip[0] < 0 || resource->trip[1] < 0)
return 0;
/* This driver stores min, max; ACPI wants max, min. */
arg_objs[0].integer.value = resource->trip[1];
arg_objs[1].integer.value = resource->trip[0];
status = acpi_evaluate_integer(resource->acpi_dev->handle, "_PTP",
&args, &data);
if (ACPI_FAILURE(status)) {
acpi_evaluation_failure_warn(resource->acpi_dev->handle, "_PTP",
status);
return -EINVAL;
}
/* _PTP returns 0 on success, nonzero otherwise */
if (data)
return -EINVAL;
return 0;
}
static ssize_t set_trip(struct device *dev, struct device_attribute *devattr,
const char *buf, size_t count)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct acpi_device *acpi_dev = to_acpi_device(dev);
struct acpi_power_meter_resource *resource = acpi_dev->driver_data;
int res;
unsigned long temp;
res = kstrtoul(buf, 10, &temp);
if (res)
return res;
temp = DIV_ROUND_CLOSEST(temp, 1000);
mutex_lock(&resource->lock);
resource->trip[attr->index - 7] = temp;
res = set_acpi_trip(resource);
mutex_unlock(&resource->lock);
if (res)
return res;
return count;
}
/* Power meter */
static int update_meter(struct acpi_power_meter_resource *resource)
{
unsigned long long data;
acpi_status status;
unsigned long local_jiffies = jiffies;
if (time_before(local_jiffies, resource->sensors_last_updated +
msecs_to_jiffies(resource->caps.sampling_time)) &&
resource->sensors_valid)
return 0;
status = acpi_evaluate_integer(resource->acpi_dev->handle, "_PMM",
NULL, &data);
if (ACPI_FAILURE(status)) {
acpi_evaluation_failure_warn(resource->acpi_dev->handle, "_PMM",
status);
return -ENODEV;
}
resource->power = data;
resource->sensors_valid = 1;
resource->sensors_last_updated = jiffies;
return 0;
}
static ssize_t show_power(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct acpi_device *acpi_dev = to_acpi_device(dev);
struct acpi_power_meter_resource *resource = acpi_dev->driver_data;
mutex_lock(&resource->lock);
update_meter(resource);
mutex_unlock(&resource->lock);
return sprintf(buf, "%llu\n", resource->power * 1000);
}
/* Miscellaneous */
static ssize_t show_str(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct acpi_device *acpi_dev = to_acpi_device(dev);
struct acpi_power_meter_resource *resource = acpi_dev->driver_data;
acpi_string val;
int ret;
mutex_lock(&resource->lock);
switch (attr->index) {
case 0:
val = resource->model_number;
break;
case 1:
val = resource->serial_number;
break;
case 2:
val = resource->oem_info;
break;
default:
WARN(1, "Implementation error: unexpected attribute index %d\n",
attr->index);
val = "";
break;
}
ret = sprintf(buf, "%s\n", val);
mutex_unlock(&resource->lock);
return ret;
}
static ssize_t show_val(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct acpi_device *acpi_dev = to_acpi_device(dev);
struct acpi_power_meter_resource *resource = acpi_dev->driver_data;
u64 val = 0;
switch (attr->index) {
case 0:
val = resource->caps.min_avg_interval;
break;
case 1:
val = resource->caps.max_avg_interval;
break;
case 2:
val = resource->caps.min_cap * 1000;
break;
case 3:
val = resource->caps.max_cap * 1000;
break;
case 4:
if (resource->caps.hysteresis == UNKNOWN_HYSTERESIS)
return sprintf(buf, "unknown\n");
val = resource->caps.hysteresis * 1000;
break;
case 5:
if (resource->caps.flags & POWER_METER_IS_BATTERY)
val = 1;
else
val = 0;
break;
case 6:
if (resource->power > resource->cap)
val = 1;
else
val = 0;
break;
case 7:
case 8:
if (resource->trip[attr->index - 7] < 0)
return sprintf(buf, "unknown\n");
val = resource->trip[attr->index - 7] * 1000;
break;
default:
WARN(1, "Implementation error: unexpected attribute index %d\n",
attr->index);
break;
}
return sprintf(buf, "%llu\n", val);
}
static ssize_t show_accuracy(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct acpi_device *acpi_dev = to_acpi_device(dev);
struct acpi_power_meter_resource *resource = acpi_dev->driver_data;
unsigned int acc = resource->caps.accuracy;
return sprintf(buf, "%u.%u%%\n", acc / 1000, acc % 1000);
}
static ssize_t show_name(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
return sprintf(buf, "%s\n", ACPI_POWER_METER_NAME);
}
#define RO_SENSOR_TEMPLATE(_label, _show, _index) \
{ \
.label = _label, \
.show = _show, \
.index = _index, \
}
#define RW_SENSOR_TEMPLATE(_label, _show, _set, _index) \
{ \
.label = _label, \
.show = _show, \
.set = _set, \
.index = _index, \
}
/* Sensor descriptions. If you add a sensor, update NUM_SENSORS above! */
static struct sensor_template meter_attrs[] = {
RO_SENSOR_TEMPLATE(POWER_AVERAGE_NAME, show_power, 0),
RO_SENSOR_TEMPLATE("power1_accuracy", show_accuracy, 0),
RO_SENSOR_TEMPLATE("power1_average_interval_min", show_val, 0),
RO_SENSOR_TEMPLATE("power1_average_interval_max", show_val, 1),
RO_SENSOR_TEMPLATE("power1_is_battery", show_val, 5),
RW_SENSOR_TEMPLATE(POWER_AVG_INTERVAL_NAME, show_avg_interval,
set_avg_interval, 0),
{},
};
static struct sensor_template misc_cap_attrs[] = {
RO_SENSOR_TEMPLATE("power1_cap_min", show_val, 2),
RO_SENSOR_TEMPLATE("power1_cap_max", show_val, 3),
RO_SENSOR_TEMPLATE("power1_cap_hyst", show_val, 4),
RO_SENSOR_TEMPLATE(POWER_ALARM_NAME, show_val, 6),
{},
};
static struct sensor_template ro_cap_attrs[] = {
RO_SENSOR_TEMPLATE(POWER_CAP_NAME, show_cap, 0),
{},
};
static struct sensor_template rw_cap_attrs[] = {
RW_SENSOR_TEMPLATE(POWER_CAP_NAME, show_cap, set_cap, 0),
{},
};
static struct sensor_template trip_attrs[] = {
RW_SENSOR_TEMPLATE("power1_average_min", show_val, set_trip, 7),
RW_SENSOR_TEMPLATE("power1_average_max", show_val, set_trip, 8),
{},
};
static struct sensor_template misc_attrs[] = {
RO_SENSOR_TEMPLATE("name", show_name, 0),
RO_SENSOR_TEMPLATE("power1_model_number", show_str, 0),
RO_SENSOR_TEMPLATE("power1_oem_info", show_str, 2),
RO_SENSOR_TEMPLATE("power1_serial_number", show_str, 1),
{},
};
#undef RO_SENSOR_TEMPLATE
#undef RW_SENSOR_TEMPLATE
/* Read power domain data */
static void remove_domain_devices(struct acpi_power_meter_resource *resource)
{
int i;
if (!resource->num_domain_devices)
return;
for (i = 0; i < resource->num_domain_devices; i++) {
struct acpi_device *obj = resource->domain_devices[i];
if (!obj)
continue;
sysfs_remove_link(resource->holders_dir,
kobject_name(&obj->dev.kobj));
acpi_dev_put(obj);
}
kfree(resource->domain_devices);
kobject_put(resource->holders_dir);
resource->num_domain_devices = 0;
}
static int read_domain_devices(struct acpi_power_meter_resource *resource)
{
int res = 0;
int i;
struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
union acpi_object *pss;
acpi_status status;
status = acpi_evaluate_object(resource->acpi_dev->handle, "_PMD", NULL,
&buffer);
if (ACPI_FAILURE(status)) {
acpi_evaluation_failure_warn(resource->acpi_dev->handle, "_PMD",
status);
return -ENODEV;
}
pss = buffer.pointer;
if (!pss ||
pss->type != ACPI_TYPE_PACKAGE) {
dev_err(&resource->acpi_dev->dev, ACPI_POWER_METER_NAME
"Invalid _PMD data\n");
res = -EFAULT;
goto end;
}
if (!pss->package.count)
goto end;
resource->domain_devices = kcalloc(pss->package.count,
sizeof(struct acpi_device *),
GFP_KERNEL);
if (!resource->domain_devices) {
res = -ENOMEM;
goto end;
}
resource->holders_dir = kobject_create_and_add("measures",
&resource->acpi_dev->dev.kobj);
if (!resource->holders_dir) {
res = -ENOMEM;
goto exit_free;
}
resource->num_domain_devices = pss->package.count;
for (i = 0; i < pss->package.count; i++) {
struct acpi_device *obj;
union acpi_object *element = &pss->package.elements[i];
/* Refuse non-references */
if (element->type != ACPI_TYPE_LOCAL_REFERENCE)
continue;
/* Create a symlink to domain objects */
obj = acpi_get_acpi_dev(element->reference.handle);
resource->domain_devices[i] = obj;
if (!obj)
continue;
res = sysfs_create_link(resource->holders_dir, &obj->dev.kobj,
kobject_name(&obj->dev.kobj));
if (res) {
acpi_dev_put(obj);
resource->domain_devices[i] = NULL;
}
}
res = 0;
goto end;
exit_free:
kfree(resource->domain_devices);
end:
kfree(buffer.pointer);
return res;
}
/* Registration and deregistration */
static int register_attrs(struct acpi_power_meter_resource *resource,
struct sensor_template *attrs)
{
struct device *dev = &resource->acpi_dev->dev;
struct sensor_device_attribute *sensors =
&resource->sensors[resource->num_sensors];
int res = 0;
while (attrs->label) {
sensors->dev_attr.attr.name = attrs->label;
sensors->dev_attr.attr.mode = 0444;
sensors->dev_attr.show = attrs->show;
sensors->index = attrs->index;
if (attrs->set) {
sensors->dev_attr.attr.mode |= 0200;
sensors->dev_attr.store = attrs->set;
}
sysfs_attr_init(&sensors->dev_attr.attr);
res = device_create_file(dev, &sensors->dev_attr);
if (res) {
sensors->dev_attr.attr.name = NULL;
goto error;
}
sensors++;
resource->num_sensors++;
attrs++;
}
error:
return res;
}
static void remove_attrs(struct acpi_power_meter_resource *resource)
{
int i;
for (i = 0; i < resource->num_sensors; i++) {
if (!resource->sensors[i].dev_attr.attr.name)
continue;
device_remove_file(&resource->acpi_dev->dev,
&resource->sensors[i].dev_attr);
}
remove_domain_devices(resource);
resource->num_sensors = 0;
}
static int setup_attrs(struct acpi_power_meter_resource *resource)
{
int res = 0;
res = read_domain_devices(resource);
if (res)
return res;
if (resource->caps.flags & POWER_METER_CAN_MEASURE) {
res = register_attrs(resource, meter_attrs);
if (res)
goto error;
}
if (resource->caps.flags & POWER_METER_CAN_CAP) {
if (!can_cap_in_hardware()) {
dev_warn(&resource->acpi_dev->dev,
"Ignoring unsafe software power cap!\n");
goto skip_unsafe_cap;
}
if (resource->caps.configurable_cap)
res = register_attrs(resource, rw_cap_attrs);
else
res = register_attrs(resource, ro_cap_attrs);
if (res)
goto error;
res = register_attrs(resource, misc_cap_attrs);
if (res)
goto error;
}
skip_unsafe_cap:
if (resource->caps.flags & POWER_METER_CAN_TRIP) {
res = register_attrs(resource, trip_attrs);
if (res)
goto error;
}
res = register_attrs(resource, misc_attrs);
if (res)
goto error;
return res;
error:
remove_attrs(resource);
return res;
}
static void free_capabilities(struct acpi_power_meter_resource *resource)
{
acpi_string *str;
int i;
str = &resource->model_number;
for (i = 0; i < 3; i++, str++) {
kfree(*str);
*str = NULL;
}
}
static int read_capabilities(struct acpi_power_meter_resource *resource)
{
int res = 0;
int i;
struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
struct acpi_buffer state = { 0, NULL };
struct acpi_buffer format = { sizeof("NNNNNNNNNNN"), "NNNNNNNNNNN" };
union acpi_object *pss;
acpi_string *str;
acpi_status status;
status = acpi_evaluate_object(resource->acpi_dev->handle, "_PMC", NULL,
&buffer);
if (ACPI_FAILURE(status)) {
acpi_evaluation_failure_warn(resource->acpi_dev->handle, "_PMC",
status);
return -ENODEV;
}
pss = buffer.pointer;
if (!pss ||
pss->type != ACPI_TYPE_PACKAGE ||
pss->package.count != 14) {
dev_err(&resource->acpi_dev->dev, ACPI_POWER_METER_NAME
"Invalid _PMC data\n");
res = -EFAULT;
goto end;
}
/* Grab all the integer data at once */
state.length = sizeof(struct acpi_power_meter_capabilities);
state.pointer = &resource->caps;
status = acpi_extract_package(pss, &format, &state);
if (ACPI_FAILURE(status)) {
dev_err(&resource->acpi_dev->dev, ACPI_POWER_METER_NAME
"_PMC package parsing failed: %s\n",
acpi_format_exception(status));
res = -EFAULT;
goto end;
}
if (resource->caps.units) {
dev_err(&resource->acpi_dev->dev, ACPI_POWER_METER_NAME
"Unknown units %llu.\n",
resource->caps.units);
res = -EINVAL;
goto end;
}
/* Grab the string data */
str = &resource->model_number;
for (i = 11; i < 14; i++) {
union acpi_object *element = &pss->package.elements[i];
if (element->type != ACPI_TYPE_STRING) {
res = -EINVAL;
goto error;
}
*str = kcalloc(element->string.length + 1, sizeof(u8),
GFP_KERNEL);
if (!*str) {
res = -ENOMEM;
goto error;
}
strncpy(*str, element->string.pointer, element->string.length);
str++;
}
dev_info(&resource->acpi_dev->dev, "Found ACPI power meter.\n");
goto end;
error:
free_capabilities(resource);
end:
kfree(buffer.pointer);
return res;
}
/* Handle ACPI event notifications */
static void acpi_power_meter_notify(struct acpi_device *device, u32 event)
{
struct acpi_power_meter_resource *resource;
int res;
if (!device || !acpi_driver_data(device))
return;
resource = acpi_driver_data(device);
switch (event) {
case METER_NOTIFY_CONFIG:
mutex_lock(&resource->lock);
free_capabilities(resource);
res = read_capabilities(resource);
mutex_unlock(&resource->lock);
if (res)
break;
remove_attrs(resource);
setup_attrs(resource);
break;
case METER_NOTIFY_TRIP:
sysfs_notify(&device->dev.kobj, NULL, POWER_AVERAGE_NAME);
break;
case METER_NOTIFY_CAP:
sysfs_notify(&device->dev.kobj, NULL, POWER_CAP_NAME);
break;
case METER_NOTIFY_INTERVAL:
sysfs_notify(&device->dev.kobj, NULL, POWER_AVG_INTERVAL_NAME);
break;
case METER_NOTIFY_CAPPING:
sysfs_notify(&device->dev.kobj, NULL, POWER_ALARM_NAME);
dev_info(&device->dev, "Capping in progress.\n");
break;
default:
WARN(1, "Unexpected event %d\n", event);
break;
}
acpi_bus_generate_netlink_event(ACPI_POWER_METER_CLASS,
dev_name(&device->dev), event, 0);
}
static int acpi_power_meter_add(struct acpi_device *device)
{
int res;
struct acpi_power_meter_resource *resource;
if (!device)
return -EINVAL;
resource = kzalloc(sizeof(*resource), GFP_KERNEL);
if (!resource)
return -ENOMEM;
resource->sensors_valid = 0;
resource->acpi_dev = device;
mutex_init(&resource->lock);
strcpy(acpi_device_name(device), ACPI_POWER_METER_DEVICE_NAME);
strcpy(acpi_device_class(device), ACPI_POWER_METER_CLASS);
device->driver_data = resource;
res = read_capabilities(resource);
if (res)
goto exit_free;
resource->trip[0] = -1;
resource->trip[1] = -1;
res = setup_attrs(resource);
if (res)
goto exit_free_capability;
resource->hwmon_dev = hwmon_device_register(&device->dev);
if (IS_ERR(resource->hwmon_dev)) {
res = PTR_ERR(resource->hwmon_dev);
goto exit_remove;
}
res = 0;
goto exit;
exit_remove:
remove_attrs(resource);
exit_free_capability:
free_capabilities(resource);
exit_free:
kfree(resource);
exit:
return res;
}
static void acpi_power_meter_remove(struct acpi_device *device)
{
struct acpi_power_meter_resource *resource;
if (!device || !acpi_driver_data(device))
return;
resource = acpi_driver_data(device);
hwmon_device_unregister(resource->hwmon_dev);
remove_attrs(resource);
free_capabilities(resource);
kfree(resource);
}
static int acpi_power_meter_resume(struct device *dev)
{
struct acpi_power_meter_resource *resource;
if (!dev)
return -EINVAL;
resource = acpi_driver_data(to_acpi_device(dev));
if (!resource)
return -EINVAL;
free_capabilities(resource);
read_capabilities(resource);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(acpi_power_meter_pm, NULL,
acpi_power_meter_resume);
static struct acpi_driver acpi_power_meter_driver = {
.name = "power_meter",
.class = ACPI_POWER_METER_CLASS,
.ids = power_meter_ids,
.ops = {
.add = acpi_power_meter_add,
.remove = acpi_power_meter_remove,
.notify = acpi_power_meter_notify,
},
.drv.pm = pm_sleep_ptr(&acpi_power_meter_pm),
};
/* Module init/exit routines */
static int __init enable_cap_knobs(const struct dmi_system_id *d)
{
cap_in_hardware = 1;
return 0;
}
static const struct dmi_system_id pm_dmi_table[] __initconst = {
{
enable_cap_knobs, "IBM Active Energy Manager",
{
DMI_MATCH(DMI_SYS_VENDOR, "IBM")
},
},
{}
};
static int __init acpi_power_meter_init(void)
{
int result;
if (acpi_disabled)
return -ENODEV;
dmi_check_system(pm_dmi_table);
result = acpi_bus_register_driver(&acpi_power_meter_driver);
if (result < 0)
return result;
return 0;
}
static void __exit acpi_power_meter_exit(void)
{
acpi_bus_unregister_driver(&acpi_power_meter_driver);
}
MODULE_AUTHOR("Darrick J. Wong <[email protected]>");
MODULE_DESCRIPTION("ACPI 4.0 power meter driver");
MODULE_LICENSE("GPL");
module_param(force_cap_on, bool, 0644);
MODULE_PARM_DESC(force_cap_on, "Enable power cap even it is unsafe to do so.");
module_init(acpi_power_meter_init);
module_exit(acpi_power_meter_exit);
|
linux-master
|
drivers/hwmon/acpi_power_meter.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* abituguru3.c
*
* Copyright (c) 2006-2008 Hans de Goede <[email protected]>
* Copyright (c) 2008 Alistair John Strachan <[email protected]>
*/
/*
* This driver supports the sensor part of revision 3 of the custom Abit uGuru
* chip found on newer Abit uGuru motherboards. Note: because of lack of specs
* only reading the sensors and their settings is supported.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/dmi.h>
#include <linux/io.h>
/* uGuru3 bank addresses */
#define ABIT_UGURU3_SETTINGS_BANK 0x01
#define ABIT_UGURU3_SENSORS_BANK 0x08
#define ABIT_UGURU3_MISC_BANK 0x09
#define ABIT_UGURU3_ALARMS_START 0x1E
#define ABIT_UGURU3_SETTINGS_START 0x24
#define ABIT_UGURU3_VALUES_START 0x80
#define ABIT_UGURU3_BOARD_ID 0x0A
/* uGuru3 sensor bank flags */ /* Alarm if: */
#define ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE 0x01 /* temp over warn */
#define ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE 0x02 /* volt over max */
#define ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE 0x04 /* volt under min */
#define ABIT_UGURU3_TEMP_HIGH_ALARM_FLAG 0x10 /* temp is over warn */
#define ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG 0x20 /* volt is over max */
#define ABIT_UGURU3_VOLT_LOW_ALARM_FLAG 0x40 /* volt is under min */
#define ABIT_UGURU3_FAN_LOW_ALARM_ENABLE 0x01 /* fan under min */
#define ABIT_UGURU3_BEEP_ENABLE 0x08 /* beep if alarm */
#define ABIT_UGURU3_SHUTDOWN_ENABLE 0x80 /* shutdown if alarm */
/* sensor types */
#define ABIT_UGURU3_IN_SENSOR 0
#define ABIT_UGURU3_TEMP_SENSOR 1
#define ABIT_UGURU3_FAN_SENSOR 2
/*
* Timeouts / Retries, if these turn out to need a lot of fiddling we could
* convert them to params. Determined by trial and error. I assume this is
* cpu-speed independent, since the ISA-bus and not the CPU should be the
* bottleneck.
*/
#define ABIT_UGURU3_WAIT_TIMEOUT 250
/*
* Normally the 0xAC at the end of synchronize() is reported after the
* first read, but sometimes not and we need to poll
*/
#define ABIT_UGURU3_SYNCHRONIZE_TIMEOUT 5
/* utility macros */
#define ABIT_UGURU3_NAME "abituguru3"
#define ABIT_UGURU3_DEBUG(format, arg...) \
do { \
if (verbose) \
pr_debug(format , ## arg); \
} while (0)
/* Macros to help calculate the sysfs_names array length */
#define ABIT_UGURU3_MAX_NO_SENSORS 26
/*
* sum of strlen +1 of: in??_input\0, in??_{min,max}\0, in??_{min,max}_alarm\0,
* in??_{min,max}_alarm_enable\0, in??_beep\0, in??_shutdown\0, in??_label\0
*/
#define ABIT_UGURU3_IN_NAMES_LENGTH \
(11 + 2 * 9 + 2 * 15 + 2 * 22 + 10 + 14 + 11)
/*
* sum of strlen +1 of: temp??_input\0, temp??_max\0, temp??_crit\0,
* temp??_alarm\0, temp??_alarm_enable\0, temp??_beep\0, temp??_shutdown\0,
* temp??_label\0
*/
#define ABIT_UGURU3_TEMP_NAMES_LENGTH (13 + 11 + 12 + 13 + 20 + 12 + 16 + 13)
/*
* sum of strlen +1 of: fan??_input\0, fan??_min\0, fan??_alarm\0,
* fan??_alarm_enable\0, fan??_beep\0, fan??_shutdown\0, fan??_label\0
*/
#define ABIT_UGURU3_FAN_NAMES_LENGTH (12 + 10 + 12 + 19 + 11 + 15 + 12)
/*
* Worst case scenario 16 in sensors (longest names_length) and the rest
* temp sensors (second longest names_length).
*/
#define ABIT_UGURU3_SYSFS_NAMES_LENGTH (16 * ABIT_UGURU3_IN_NAMES_LENGTH + \
(ABIT_UGURU3_MAX_NO_SENSORS - 16) * ABIT_UGURU3_TEMP_NAMES_LENGTH)
/*
* All the macros below are named identical to the openguru2 program
* reverse engineered by Louis Kruger, hence the names might not be 100%
* logical. I could come up with better names, but I prefer keeping the names
* identical so that this driver can be compared with his work more easily.
*/
/* Two i/o-ports are used by uGuru */
#define ABIT_UGURU3_BASE 0x00E0
#define ABIT_UGURU3_CMD 0x00
#define ABIT_UGURU3_DATA 0x04
#define ABIT_UGURU3_REGION_LENGTH 5
/*
* The wait_xxx functions return this on success and the last contents
* of the DATA register (0-255) on failure.
*/
#define ABIT_UGURU3_SUCCESS -1
/* uGuru status flags */
#define ABIT_UGURU3_STATUS_READY_FOR_READ 0x01
#define ABIT_UGURU3_STATUS_BUSY 0x02
/* Structures */
struct abituguru3_sensor_info {
const char *name;
int port;
int type;
int multiplier;
int divisor;
int offset;
};
/* Avoid use of flexible array members */
#define ABIT_UGURU3_MAX_DMI_NAMES 2
struct abituguru3_motherboard_info {
u16 id;
const char *dmi_name[ABIT_UGURU3_MAX_DMI_NAMES + 1];
/* + 1 -> end of sensors indicated by a sensor with name == NULL */
struct abituguru3_sensor_info sensors[ABIT_UGURU3_MAX_NO_SENSORS + 1];
};
/*
* For the Abit uGuru, we need to keep some data in memory.
* The structure is dynamically allocated, at the same time when a new
* abituguru3 device is allocated.
*/
struct abituguru3_data {
struct device *hwmon_dev; /* hwmon registered device */
struct mutex update_lock; /* protect access to data and uGuru */
unsigned short addr; /* uguru base address */
bool valid; /* true if following fields are valid */
unsigned long last_updated; /* In jiffies */
/*
* For convenience the sysfs attr and their names are generated
* automatically. We have max 10 entries per sensor (for in sensors)
*/
struct sensor_device_attribute_2 sysfs_attr[ABIT_UGURU3_MAX_NO_SENSORS
* 10];
/* Buffer to store the dynamically generated sysfs names */
char sysfs_names[ABIT_UGURU3_SYSFS_NAMES_LENGTH];
/* Pointer to the sensors info for the detected motherboard */
const struct abituguru3_sensor_info *sensors;
/*
* The abituguru3 supports up to 48 sensors, and thus has registers
* sets for 48 sensors, for convenience reasons / simplicity of the
* code we always read and store all registers for all 48 sensors
*/
/* Alarms for all 48 sensors (1 bit per sensor) */
u8 alarms[48/8];
/* Value of all 48 sensors */
u8 value[48];
/*
* Settings of all 48 sensors, note in and temp sensors (the first 32
* sensors) have 3 bytes of settings, while fans only have 2 bytes,
* for convenience we use 3 bytes for all sensors
*/
u8 settings[48][3];
};
/* Constants */
static const struct abituguru3_motherboard_info abituguru3_motherboards[] = {
{ 0x000C, { NULL } /* Unknown, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS FAN", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x000D, { NULL } /* Abit AW8, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM1", 26, 1, 1, 1, 0 },
{ "PWM2", 27, 1, 1, 1, 0 },
{ "PWM3", 28, 1, 1, 1, 0 },
{ "PWM4", 29, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
{ "AUX3 Fan", 37, 2, 60, 1, 0 },
{ "AUX4 Fan", 38, 2, 60, 1, 0 },
{ "AUX5 Fan", 39, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x000E, { NULL } /* AL-8, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x000F, { NULL } /* Unknown, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0010, { NULL } /* Abit NI8 SLI GR, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "NB 1.4V", 4, 0, 10, 1, 0 },
{ "SB 1.5V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "SYS", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ "OTES1 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0011, { "AT8 32X", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 20, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
{ "NB 1.8V", 4, 0, 10, 1, 0 },
{ "NB 1.8V Dual", 5, 0, 10, 1, 0 },
{ "HTV 1.2", 3, 0, 10, 1, 0 },
{ "PCIE 1.2V", 12, 0, 10, 1, 0 },
{ "NB 1.2V", 13, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "NB", 25, 1, 1, 1, 0 },
{ "System", 26, 1, 1, 1, 0 },
{ "PWM", 27, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
{ "AUX3 Fan", 37, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0012, { NULL } /* Abit AN8 32X, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 20, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "HyperTransport", 3, 0, 10, 1, 0 },
{ "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
{ "NB", 4, 0, 10, 1, 0 },
{ "SB", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "SYS", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0013, { NULL } /* Abit AW8D, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM1", 26, 1, 1, 1, 0 },
{ "PWM2", 27, 1, 1, 1, 0 },
{ "PWM3", 28, 1, 1, 1, 0 },
{ "PWM4", 29, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
{ "AUX3 Fan", 37, 2, 60, 1, 0 },
{ "AUX4 Fan", 38, 2, 60, 1, 0 },
{ "AUX5 Fan", 39, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0014, { "AB9", "AB9 Pro", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0015, { NULL } /* Unknown, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 20, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "HyperTransport", 3, 0, 10, 1, 0 },
{ "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
{ "NB", 4, 0, 10, 1, 0 },
{ "SB", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "SYS", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0016, { "AW9D-MAX", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR2", 1, 0, 20, 1, 0 },
{ "DDR2 VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM1", 26, 1, 1, 1, 0 },
{ "PWM2", 27, 1, 1, 1, 0 },
{ "PWM3", 28, 1, 1, 1, 0 },
{ "PWM4", 29, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
{ "AUX3 Fan", 37, 2, 60, 1, 0 },
{ "OTES1 Fan", 38, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0017, { NULL } /* Unknown, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR2", 1, 0, 20, 1, 0 },
{ "DDR2 VTT", 2, 0, 10, 1, 0 },
{ "HyperTransport", 3, 0, 10, 1, 0 },
{ "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
{ "NB 1.8V", 4, 0, 10, 1, 0 },
{ "NB 1.2V ", 13, 0, 10, 1, 0 },
{ "SB 1.2V", 5, 0, 10, 1, 0 },
{ "PCIE 1.2V", 12, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "ATX +3.3V", 10, 0, 20, 1, 0 },
{ "ATX 5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 26, 1, 1, 1, 0 },
{ "PWM", 27, 1, 1, 1, 0 },
{ "CPU FAN", 32, 2, 60, 1, 0 },
{ "SYS FAN", 34, 2, 60, 1, 0 },
{ "AUX1 FAN", 35, 2, 60, 1, 0 },
{ "AUX2 FAN", 36, 2, 60, 1, 0 },
{ "AUX3 FAN", 37, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0018, { "AB9 QuadGT", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR2", 1, 0, 20, 1, 0 },
{ "DDR2 VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT", 3, 0, 10, 1, 0 },
{ "MCH 1.25V", 4, 0, 10, 1, 0 },
{ "ICHIO 1.5V", 5, 0, 10, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM Phase1", 26, 1, 1, 1, 0 },
{ "PWM Phase2", 27, 1, 1, 1, 0 },
{ "PWM Phase3", 28, 1, 1, 1, 0 },
{ "PWM Phase4", 29, 1, 1, 1, 0 },
{ "PWM Phase5", 30, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0019, { "IN9 32X MAX", NULL }, {
{ "CPU Core", 7, 0, 10, 1, 0 },
{ "DDR2", 13, 0, 20, 1, 0 },
{ "DDR2 VTT", 14, 0, 10, 1, 0 },
{ "CPU VTT", 3, 0, 20, 1, 0 },
{ "NB 1.2V", 4, 0, 10, 1, 0 },
{ "SB 1.5V", 6, 0, 10, 1, 0 },
{ "HyperTransport", 5, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 12, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "ATX +3.3V", 10, 0, 20, 1, 0 },
{ "ATX 5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM Phase1", 26, 1, 1, 1, 0 },
{ "PWM Phase2", 27, 1, 1, 1, 0 },
{ "PWM Phase3", 28, 1, 1, 1, 0 },
{ "PWM Phase4", 29, 1, 1, 1, 0 },
{ "PWM Phase5", 30, 1, 1, 1, 0 },
{ "CPU FAN", 32, 2, 60, 1, 0 },
{ "SYS FAN", 34, 2, 60, 1, 0 },
{ "AUX1 FAN", 33, 2, 60, 1, 0 },
{ "AUX2 FAN", 35, 2, 60, 1, 0 },
{ "AUX3 FAN", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x001A, { "IP35 Pro", "IP35 Pro XE", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR2", 1, 0, 20, 1, 0 },
{ "DDR2 VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH 1.25V", 4, 0, 10, 1, 0 },
{ "ICHIO 1.5V", 5, 0, 10, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "PWM Phase2", 27, 1, 1, 1, 0 },
{ "PWM Phase3", 28, 1, 1, 1, 0 },
{ "PWM Phase4", 29, 1, 1, 1, 0 },
{ "PWM Phase5", 30, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
{ "AUX4 Fan", 37, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x001B, { NULL } /* Unknown, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR3", 1, 0, 20, 1, 0 },
{ "DDR3 VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT", 3, 0, 10, 1, 0 },
{ "MCH 1.25V", 4, 0, 10, 1, 0 },
{ "ICHIO 1.5V", 5, 0, 10, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM Phase1", 26, 1, 1, 1, 0 },
{ "PWM Phase2", 27, 1, 1, 1, 0 },
{ "PWM Phase3", 28, 1, 1, 1, 0 },
{ "PWM Phase4", 29, 1, 1, 1, 0 },
{ "PWM Phase5", 30, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x001C, { "IX38 QuadGT", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR2", 1, 0, 20, 1, 0 },
{ "DDR2 VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT", 3, 0, 10, 1, 0 },
{ "MCH 1.25V", 4, 0, 10, 1, 0 },
{ "ICHIO 1.5V", 5, 0, 10, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM Phase1", 26, 1, 1, 1, 0 },
{ "PWM Phase2", 27, 1, 1, 1, 0 },
{ "PWM Phase3", 28, 1, 1, 1, 0 },
{ "PWM Phase4", 29, 1, 1, 1, 0 },
{ "PWM Phase5", 30, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0000, { NULL }, { { NULL, 0, 0, 0, 0, 0 } } }
};
/* Insmod parameters */
static bool force;
module_param(force, bool, 0);
MODULE_PARM_DESC(force, "Set to one to force detection.");
/* Default verbose is 1, since this driver is still in the testing phase */
static bool verbose = 1;
module_param(verbose, bool, 0644);
MODULE_PARM_DESC(verbose, "Enable/disable verbose error reporting");
static const char *never_happen = "This should never happen.";
static const char *report_this =
"Please report this to the abituguru3 maintainer (see MAINTAINERS)";
/* wait while the uguru is busy (usually after a write) */
static int abituguru3_wait_while_busy(struct abituguru3_data *data)
{
u8 x;
int timeout = ABIT_UGURU3_WAIT_TIMEOUT;
while ((x = inb_p(data->addr + ABIT_UGURU3_DATA)) &
ABIT_UGURU3_STATUS_BUSY) {
timeout--;
if (timeout == 0)
return x;
/*
* sleep a bit before our last try, to give the uGuru3 one
* last chance to respond.
*/
if (timeout == 1)
msleep(1);
}
return ABIT_UGURU3_SUCCESS;
}
/* wait till uguru is ready to be read */
static int abituguru3_wait_for_read(struct abituguru3_data *data)
{
u8 x;
int timeout = ABIT_UGURU3_WAIT_TIMEOUT;
while (!((x = inb_p(data->addr + ABIT_UGURU3_DATA)) &
ABIT_UGURU3_STATUS_READY_FOR_READ)) {
timeout--;
if (timeout == 0)
return x;
/*
* sleep a bit before our last try, to give the uGuru3 one
* last chance to respond.
*/
if (timeout == 1)
msleep(1);
}
return ABIT_UGURU3_SUCCESS;
}
/*
* This synchronizes us with the uGuru3's protocol state machine, this
* must be done before each command.
*/
static int abituguru3_synchronize(struct abituguru3_data *data)
{
int x, timeout = ABIT_UGURU3_SYNCHRONIZE_TIMEOUT;
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("synchronize timeout during initial busy "
"wait, status: 0x%02x\n", x);
return -EIO;
}
outb(0x20, data->addr + ABIT_UGURU3_DATA);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x20, "
"status: 0x%02x\n", x);
return -EIO;
}
outb(0x10, data->addr + ABIT_UGURU3_CMD);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x10, "
"status: 0x%02x\n", x);
return -EIO;
}
outb(0x00, data->addr + ABIT_UGURU3_CMD);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x00, "
"status: 0x%02x\n", x);
return -EIO;
}
x = abituguru3_wait_for_read(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("synchronize timeout waiting for read, "
"status: 0x%02x\n", x);
return -EIO;
}
while ((x = inb(data->addr + ABIT_UGURU3_CMD)) != 0xAC) {
timeout--;
if (timeout == 0) {
ABIT_UGURU3_DEBUG("synchronize timeout cmd does not "
"hold 0xAC after synchronize, cmd: 0x%02x\n",
x);
return -EIO;
}
msleep(1);
}
return 0;
}
/*
* Read count bytes from sensor sensor_addr in bank bank_addr and store the
* result in buf
*/
static int abituguru3_read(struct abituguru3_data *data, u8 bank, u8 offset,
u8 count, u8 *buf)
{
int i, x;
x = abituguru3_synchronize(data);
if (x)
return x;
outb(0x1A, data->addr + ABIT_UGURU3_DATA);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
"sending 0x1A, status: 0x%02x\n", (unsigned int)bank,
(unsigned int)offset, x);
return -EIO;
}
outb(bank, data->addr + ABIT_UGURU3_CMD);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
"sending the bank, status: 0x%02x\n",
(unsigned int)bank, (unsigned int)offset, x);
return -EIO;
}
outb(offset, data->addr + ABIT_UGURU3_CMD);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
"sending the offset, status: 0x%02x\n",
(unsigned int)bank, (unsigned int)offset, x);
return -EIO;
}
outb(count, data->addr + ABIT_UGURU3_CMD);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
"sending the count, status: 0x%02x\n",
(unsigned int)bank, (unsigned int)offset, x);
return -EIO;
}
for (i = 0; i < count; i++) {
x = abituguru3_wait_for_read(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("timeout reading byte %d from "
"0x%02x:0x%02x, status: 0x%02x\n", i,
(unsigned int)bank, (unsigned int)offset, x);
break;
}
buf[i] = inb(data->addr + ABIT_UGURU3_CMD);
}
return i;
}
/*
* Sensor settings are stored 1 byte per offset with the bytes
* placed add consecutive offsets.
*/
static int abituguru3_read_increment_offset(struct abituguru3_data *data,
u8 bank, u8 offset, u8 count,
u8 *buf, int offset_count)
{
int i, x;
for (i = 0; i < offset_count; i++) {
x = abituguru3_read(data, bank, offset + i, count,
buf + i * count);
if (x != count) {
if (x < 0)
return x;
return i * count + x;
}
}
return i * count;
}
/*
* Following are the sysfs callback functions. These functions expect:
* sensor_device_attribute_2->index: index into the data->sensors array
* sensor_device_attribute_2->nr: register offset, bitmask or NA.
*/
static struct abituguru3_data *abituguru3_update_device(struct device *dev);
static ssize_t show_value(struct device *dev,
struct device_attribute *devattr, char *buf)
{
int value;
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru3_data *data = abituguru3_update_device(dev);
const struct abituguru3_sensor_info *sensor;
if (!data)
return -EIO;
sensor = &data->sensors[attr->index];
/* are we reading a setting, or is this a normal read? */
if (attr->nr)
value = data->settings[sensor->port][attr->nr];
else
value = data->value[sensor->port];
/* convert the value */
value = (value * sensor->multiplier) / sensor->divisor +
sensor->offset;
/*
* alternatively we could update the sensors settings struct for this,
* but then its contents would differ from the windows sw ini files
*/
if (sensor->type == ABIT_UGURU3_TEMP_SENSOR)
value *= 1000;
return sprintf(buf, "%d\n", value);
}
static ssize_t show_alarm(struct device *dev,
struct device_attribute *devattr, char *buf)
{
int port;
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru3_data *data = abituguru3_update_device(dev);
if (!data)
return -EIO;
port = data->sensors[attr->index].port;
/*
* See if the alarm bit for this sensor is set and if a bitmask is
* given in attr->nr also check if the alarm matches the type of alarm
* we're looking for (for volt it can be either low or high). The type
* is stored in a few readonly bits in the settings of the sensor.
*/
if ((data->alarms[port / 8] & (0x01 << (port % 8))) &&
(!attr->nr || (data->settings[port][0] & attr->nr)))
return sprintf(buf, "1\n");
else
return sprintf(buf, "0\n");
}
static ssize_t show_mask(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru3_data *data = dev_get_drvdata(dev);
if (data->settings[data->sensors[attr->index].port][0] & attr->nr)
return sprintf(buf, "1\n");
else
return sprintf(buf, "0\n");
}
static ssize_t show_label(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru3_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%s\n", data->sensors[attr->index].name);
}
static ssize_t show_name(struct device *dev,
struct device_attribute *devattr, char *buf)
{
return sprintf(buf, "%s\n", ABIT_UGURU3_NAME);
}
/* Sysfs attr templates, the real entries are generated automatically. */
static const
struct sensor_device_attribute_2 abituguru3_sysfs_templ[3][10] = { {
SENSOR_ATTR_2(in%d_input, 0444, show_value, NULL, 0, 0),
SENSOR_ATTR_2(in%d_min, 0444, show_value, NULL, 1, 0),
SENSOR_ATTR_2(in%d_max, 0444, show_value, NULL, 2, 0),
SENSOR_ATTR_2(in%d_min_alarm, 0444, show_alarm, NULL,
ABIT_UGURU3_VOLT_LOW_ALARM_FLAG, 0),
SENSOR_ATTR_2(in%d_max_alarm, 0444, show_alarm, NULL,
ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG, 0),
SENSOR_ATTR_2(in%d_beep, 0444, show_mask, NULL,
ABIT_UGURU3_BEEP_ENABLE, 0),
SENSOR_ATTR_2(in%d_shutdown, 0444, show_mask, NULL,
ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
SENSOR_ATTR_2(in%d_min_alarm_enable, 0444, show_mask, NULL,
ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE, 0),
SENSOR_ATTR_2(in%d_max_alarm_enable, 0444, show_mask, NULL,
ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE, 0),
SENSOR_ATTR_2(in%d_label, 0444, show_label, NULL, 0, 0)
}, {
SENSOR_ATTR_2(temp%d_input, 0444, show_value, NULL, 0, 0),
SENSOR_ATTR_2(temp%d_max, 0444, show_value, NULL, 1, 0),
SENSOR_ATTR_2(temp%d_crit, 0444, show_value, NULL, 2, 0),
SENSOR_ATTR_2(temp%d_alarm, 0444, show_alarm, NULL, 0, 0),
SENSOR_ATTR_2(temp%d_beep, 0444, show_mask, NULL,
ABIT_UGURU3_BEEP_ENABLE, 0),
SENSOR_ATTR_2(temp%d_shutdown, 0444, show_mask, NULL,
ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
SENSOR_ATTR_2(temp%d_alarm_enable, 0444, show_mask, NULL,
ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE, 0),
SENSOR_ATTR_2(temp%d_label, 0444, show_label, NULL, 0, 0)
}, {
SENSOR_ATTR_2(fan%d_input, 0444, show_value, NULL, 0, 0),
SENSOR_ATTR_2(fan%d_min, 0444, show_value, NULL, 1, 0),
SENSOR_ATTR_2(fan%d_alarm, 0444, show_alarm, NULL, 0, 0),
SENSOR_ATTR_2(fan%d_beep, 0444, show_mask, NULL,
ABIT_UGURU3_BEEP_ENABLE, 0),
SENSOR_ATTR_2(fan%d_shutdown, 0444, show_mask, NULL,
ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
SENSOR_ATTR_2(fan%d_alarm_enable, 0444, show_mask, NULL,
ABIT_UGURU3_FAN_LOW_ALARM_ENABLE, 0),
SENSOR_ATTR_2(fan%d_label, 0444, show_label, NULL, 0, 0)
} };
static struct sensor_device_attribute_2 abituguru3_sysfs_attr[] = {
SENSOR_ATTR_2(name, 0444, show_name, NULL, 0, 0),
};
static int abituguru3_probe(struct platform_device *pdev)
{
const int no_sysfs_attr[3] = { 10, 8, 7 };
int sensor_index[3] = { 0, 1, 1 };
struct abituguru3_data *data;
int i, j, type, used, sysfs_names_free, sysfs_attr_i, res = -ENODEV;
char *sysfs_filename;
u8 buf[2];
u16 id;
data = devm_kzalloc(&pdev->dev, sizeof(struct abituguru3_data),
GFP_KERNEL);
if (!data)
return -ENOMEM;
data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start;
mutex_init(&data->update_lock);
platform_set_drvdata(pdev, data);
/* Read the motherboard ID */
i = abituguru3_read(data, ABIT_UGURU3_MISC_BANK, ABIT_UGURU3_BOARD_ID,
2, buf);
if (i != 2)
goto abituguru3_probe_error;
/* Completely read the uGuru to see if one really is there */
if (!abituguru3_update_device(&pdev->dev))
goto abituguru3_probe_error;
/* lookup the ID in our motherboard table */
id = ((u16)buf[0] << 8) | (u16)buf[1];
for (i = 0; abituguru3_motherboards[i].id; i++)
if (abituguru3_motherboards[i].id == id)
break;
if (!abituguru3_motherboards[i].id) {
pr_err("error unknown motherboard ID: %04X. %s\n",
(unsigned int)id, report_this);
goto abituguru3_probe_error;
}
data->sensors = abituguru3_motherboards[i].sensors;
pr_info("found Abit uGuru3, motherboard ID: %04X\n", (unsigned int)id);
/* Fill the sysfs attr array */
sysfs_attr_i = 0;
sysfs_filename = data->sysfs_names;
sysfs_names_free = ABIT_UGURU3_SYSFS_NAMES_LENGTH;
for (i = 0; data->sensors[i].name; i++) {
/* Fail safe check, this should never happen! */
if (i >= ABIT_UGURU3_MAX_NO_SENSORS) {
pr_err("Fatal error motherboard has more sensors then ABIT_UGURU3_MAX_NO_SENSORS. %s %s\n",
never_happen, report_this);
res = -ENAMETOOLONG;
goto abituguru3_probe_error;
}
type = data->sensors[i].type;
for (j = 0; j < no_sysfs_attr[type]; j++) {
used = snprintf(sysfs_filename, sysfs_names_free,
abituguru3_sysfs_templ[type][j].dev_attr.attr.
name, sensor_index[type]) + 1;
data->sysfs_attr[sysfs_attr_i] =
abituguru3_sysfs_templ[type][j];
data->sysfs_attr[sysfs_attr_i].dev_attr.attr.name =
sysfs_filename;
data->sysfs_attr[sysfs_attr_i].index = i;
sysfs_filename += used;
sysfs_names_free -= used;
sysfs_attr_i++;
}
sensor_index[type]++;
}
/* Fail safe check, this should never happen! */
if (sysfs_names_free < 0) {
pr_err("Fatal error ran out of space for sysfs attr names. %s %s\n",
never_happen, report_this);
res = -ENAMETOOLONG;
goto abituguru3_probe_error;
}
/* Register sysfs hooks */
for (i = 0; i < sysfs_attr_i; i++)
if (device_create_file(&pdev->dev,
&data->sysfs_attr[i].dev_attr))
goto abituguru3_probe_error;
for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++)
if (device_create_file(&pdev->dev,
&abituguru3_sysfs_attr[i].dev_attr))
goto abituguru3_probe_error;
data->hwmon_dev = hwmon_device_register(&pdev->dev);
if (IS_ERR(data->hwmon_dev)) {
res = PTR_ERR(data->hwmon_dev);
goto abituguru3_probe_error;
}
return 0; /* success */
abituguru3_probe_error:
for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++)
device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr);
for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++)
device_remove_file(&pdev->dev,
&abituguru3_sysfs_attr[i].dev_attr);
return res;
}
static int abituguru3_remove(struct platform_device *pdev)
{
int i;
struct abituguru3_data *data = platform_get_drvdata(pdev);
hwmon_device_unregister(data->hwmon_dev);
for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++)
device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr);
for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++)
device_remove_file(&pdev->dev,
&abituguru3_sysfs_attr[i].dev_attr);
return 0;
}
static struct abituguru3_data *abituguru3_update_device(struct device *dev)
{
int i;
struct abituguru3_data *data = dev_get_drvdata(dev);
mutex_lock(&data->update_lock);
if (!data->valid || time_after(jiffies, data->last_updated + HZ)) {
/* Clear data->valid while updating */
data->valid = false;
/* Read alarms */
if (abituguru3_read_increment_offset(data,
ABIT_UGURU3_SETTINGS_BANK,
ABIT_UGURU3_ALARMS_START,
1, data->alarms, 48/8) != (48/8))
goto LEAVE_UPDATE;
/* Read in and temp sensors (3 byte settings / sensor) */
for (i = 0; i < 32; i++) {
if (abituguru3_read(data, ABIT_UGURU3_SENSORS_BANK,
ABIT_UGURU3_VALUES_START + i,
1, &data->value[i]) != 1)
goto LEAVE_UPDATE;
if (abituguru3_read_increment_offset(data,
ABIT_UGURU3_SETTINGS_BANK,
ABIT_UGURU3_SETTINGS_START + i * 3,
1,
data->settings[i], 3) != 3)
goto LEAVE_UPDATE;
}
/* Read temp sensors (2 byte settings / sensor) */
for (i = 0; i < 16; i++) {
if (abituguru3_read(data, ABIT_UGURU3_SENSORS_BANK,
ABIT_UGURU3_VALUES_START + 32 + i,
1, &data->value[32 + i]) != 1)
goto LEAVE_UPDATE;
if (abituguru3_read_increment_offset(data,
ABIT_UGURU3_SETTINGS_BANK,
ABIT_UGURU3_SETTINGS_START + 32 * 3 +
i * 2, 1,
data->settings[32 + i], 2) != 2)
goto LEAVE_UPDATE;
}
data->last_updated = jiffies;
data->valid = true;
}
LEAVE_UPDATE:
mutex_unlock(&data->update_lock);
if (data->valid)
return data;
else
return NULL;
}
static int abituguru3_suspend(struct device *dev)
{
struct abituguru3_data *data = dev_get_drvdata(dev);
/*
* make sure all communications with the uguru3 are done and no new
* ones are started
*/
mutex_lock(&data->update_lock);
return 0;
}
static int abituguru3_resume(struct device *dev)
{
struct abituguru3_data *data = dev_get_drvdata(dev);
mutex_unlock(&data->update_lock);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(abituguru3_pm, abituguru3_suspend, abituguru3_resume);
static struct platform_driver abituguru3_driver = {
.driver = {
.name = ABIT_UGURU3_NAME,
.pm = pm_sleep_ptr(&abituguru3_pm),
},
.probe = abituguru3_probe,
.remove = abituguru3_remove,
};
static int __init abituguru3_dmi_detect(void)
{
const char *board_vendor, *board_name;
int i, err = (force) ? 1 : -ENODEV;
const char *const *dmi_name;
size_t sublen;
board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
if (!board_vendor || strcmp(board_vendor, "http://www.abit.com.tw/"))
return err;
board_name = dmi_get_system_info(DMI_BOARD_NAME);
if (!board_name)
return err;
/*
* At the moment, we don't care about the part of the vendor
* DMI string contained in brackets. Truncate the string at
* the first occurrence of a bracket. Trim any trailing space
* from the substring.
*/
sublen = strcspn(board_name, "(");
while (sublen > 0 && board_name[sublen - 1] == ' ')
sublen--;
for (i = 0; abituguru3_motherboards[i].id; i++) {
dmi_name = abituguru3_motherboards[i].dmi_name;
for ( ; *dmi_name; dmi_name++) {
if (strlen(*dmi_name) != sublen)
continue;
if (!strncasecmp(board_name, *dmi_name, sublen))
return 0;
}
}
/* No match found */
return 1;
}
/*
* FIXME: Manual detection should die eventually; we need to collect stable
* DMI model names first before we can rely entirely on CONFIG_DMI.
*/
static int __init abituguru3_detect(void)
{
/*
* See if there is an uguru3 there. An idle uGuru3 will hold 0x00 or
* 0x08 at DATA and 0xAC at CMD. Sometimes the uGuru3 will hold 0x05
* or 0x55 at CMD instead, why is unknown.
*/
u8 data_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_DATA);
u8 cmd_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_CMD);
if (((data_val == 0x00) || (data_val == 0x08)) &&
((cmd_val == 0xAC) || (cmd_val == 0x05) ||
(cmd_val == 0x55)))
return 0;
ABIT_UGURU3_DEBUG("no Abit uGuru3 found, data = 0x%02X, cmd = "
"0x%02X\n", (unsigned int)data_val, (unsigned int)cmd_val);
if (force) {
pr_info("Assuming Abit uGuru3 is present because of \"force\" parameter\n");
return 0;
}
/* No uGuru3 found */
return -ENODEV;
}
static struct platform_device *abituguru3_pdev;
static int __init abituguru3_init(void)
{
struct resource res = { .flags = IORESOURCE_IO };
int err;
/* Attempt DMI detection first */
err = abituguru3_dmi_detect();
if (err < 0)
return err;
/*
* Fall back to manual detection if there was no exact
* board name match, or force was specified.
*/
if (err > 0) {
err = abituguru3_detect();
if (err)
return err;
pr_warn("this motherboard was not detected using DMI. "
"Please send the output of \"dmidecode\" to the abituguru3 maintainer (see MAINTAINERS)\n");
}
err = platform_driver_register(&abituguru3_driver);
if (err)
goto exit;
abituguru3_pdev = platform_device_alloc(ABIT_UGURU3_NAME,
ABIT_UGURU3_BASE);
if (!abituguru3_pdev) {
pr_err("Device allocation failed\n");
err = -ENOMEM;
goto exit_driver_unregister;
}
res.start = ABIT_UGURU3_BASE;
res.end = ABIT_UGURU3_BASE + ABIT_UGURU3_REGION_LENGTH - 1;
res.name = ABIT_UGURU3_NAME;
err = platform_device_add_resources(abituguru3_pdev, &res, 1);
if (err) {
pr_err("Device resource addition failed (%d)\n", err);
goto exit_device_put;
}
err = platform_device_add(abituguru3_pdev);
if (err) {
pr_err("Device addition failed (%d)\n", err);
goto exit_device_put;
}
return 0;
exit_device_put:
platform_device_put(abituguru3_pdev);
exit_driver_unregister:
platform_driver_unregister(&abituguru3_driver);
exit:
return err;
}
static void __exit abituguru3_exit(void)
{
platform_device_unregister(abituguru3_pdev);
platform_driver_unregister(&abituguru3_driver);
}
MODULE_AUTHOR("Hans de Goede <[email protected]>");
MODULE_DESCRIPTION("Abit uGuru3 Sensor device");
MODULE_LICENSE("GPL");
module_init(abituguru3_init);
module_exit(abituguru3_exit);
|
linux-master
|
drivers/hwmon/abituguru3.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Hardware monitoring driver for MAX127.
*
* Copyright (c) 2020 Facebook Inc.
*/
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/module.h>
/*
* MAX127 Control Byte. Refer to MAX127 datasheet, Table 1 "Control-Byte
* Format" for details.
*/
#define MAX127_CTRL_START BIT(7)
#define MAX127_CTRL_SEL_SHIFT 4
#define MAX127_CTRL_RNG BIT(3)
#define MAX127_CTRL_BIP BIT(2)
#define MAX127_CTRL_PD1 BIT(1)
#define MAX127_CTRL_PD0 BIT(0)
#define MAX127_NUM_CHANNELS 8
#define MAX127_SET_CHANNEL(ch) (((ch) & 7) << MAX127_CTRL_SEL_SHIFT)
/*
* MAX127 channel input ranges. Refer to MAX127 datasheet, Table 3 "Range
* and Polarity Selection" for details.
*/
#define MAX127_FULL_RANGE 10000 /* 10V */
#define MAX127_HALF_RANGE 5000 /* 5V */
/*
* MAX127 returns 2 bytes at read:
* - the first byte contains data[11:4].
* - the second byte contains data[3:0] (MSB) and 4 dummy 0s (LSB).
* Refer to MAX127 datasheet, "Read a Conversion (Read Cycle)" section
* for details.
*/
#define MAX127_DATA_LEN 2
#define MAX127_DATA_SHIFT 4
#define MAX127_SIGN_BIT BIT(11)
struct max127_data {
struct mutex lock;
struct i2c_client *client;
u8 ctrl_byte[MAX127_NUM_CHANNELS];
};
static int max127_select_channel(struct i2c_client *client, u8 ctrl_byte)
{
int status;
struct i2c_msg msg = {
.addr = client->addr,
.flags = 0,
.len = sizeof(ctrl_byte),
.buf = &ctrl_byte,
};
status = i2c_transfer(client->adapter, &msg, 1);
if (status < 0)
return status;
if (status != 1)
return -EIO;
return 0;
}
static int max127_read_channel(struct i2c_client *client, long *val)
{
int status;
u8 i2c_data[MAX127_DATA_LEN];
struct i2c_msg msg = {
.addr = client->addr,
.flags = I2C_M_RD,
.len = sizeof(i2c_data),
.buf = i2c_data,
};
status = i2c_transfer(client->adapter, &msg, 1);
if (status < 0)
return status;
if (status != 1)
return -EIO;
*val = (i2c_data[1] >> MAX127_DATA_SHIFT) |
((u16)i2c_data[0] << MAX127_DATA_SHIFT);
return 0;
}
static long max127_process_raw(u8 ctrl_byte, long raw)
{
long scale, weight;
/*
* MAX127's data coding is binary in unipolar mode with 1 LSB =
* (Full-Scale/4096) and two’s complement binary in bipolar mode
* with 1 LSB = [(2 x |FS|)/4096].
* Refer to MAX127 datasheet, "Transfer Function" section for
* details.
*/
scale = (ctrl_byte & MAX127_CTRL_RNG) ? MAX127_FULL_RANGE :
MAX127_HALF_RANGE;
if (ctrl_byte & MAX127_CTRL_BIP) {
weight = (raw & MAX127_SIGN_BIT);
raw &= ~MAX127_SIGN_BIT;
raw -= weight;
raw *= 2;
}
return raw * scale / 4096;
}
static int max127_read_input(struct max127_data *data, int channel, long *val)
{
long raw;
int status;
struct i2c_client *client = data->client;
u8 ctrl_byte = data->ctrl_byte[channel];
mutex_lock(&data->lock);
status = max127_select_channel(client, ctrl_byte);
if (status)
goto exit;
status = max127_read_channel(client, &raw);
if (status)
goto exit;
*val = max127_process_raw(ctrl_byte, raw);
exit:
mutex_unlock(&data->lock);
return status;
}
static int max127_read_min(struct max127_data *data, int channel, long *val)
{
u8 rng_bip = (data->ctrl_byte[channel] >> 2) & 3;
static const int min_input_map[4] = {
0, /* RNG=0, BIP=0 */
-MAX127_HALF_RANGE, /* RNG=0, BIP=1 */
0, /* RNG=1, BIP=0 */
-MAX127_FULL_RANGE, /* RNG=1, BIP=1 */
};
*val = min_input_map[rng_bip];
return 0;
}
static int max127_read_max(struct max127_data *data, int channel, long *val)
{
u8 rng_bip = (data->ctrl_byte[channel] >> 2) & 3;
static const int max_input_map[4] = {
MAX127_HALF_RANGE, /* RNG=0, BIP=0 */
MAX127_HALF_RANGE, /* RNG=0, BIP=1 */
MAX127_FULL_RANGE, /* RNG=1, BIP=0 */
MAX127_FULL_RANGE, /* RNG=1, BIP=1 */
};
*val = max_input_map[rng_bip];
return 0;
}
static int max127_write_min(struct max127_data *data, int channel, long val)
{
u8 ctrl;
mutex_lock(&data->lock);
ctrl = data->ctrl_byte[channel];
if (val <= -MAX127_FULL_RANGE) {
ctrl |= (MAX127_CTRL_RNG | MAX127_CTRL_BIP);
} else if (val < 0) {
ctrl |= MAX127_CTRL_BIP;
ctrl &= ~MAX127_CTRL_RNG;
} else {
ctrl &= ~MAX127_CTRL_BIP;
}
data->ctrl_byte[channel] = ctrl;
mutex_unlock(&data->lock);
return 0;
}
static int max127_write_max(struct max127_data *data, int channel, long val)
{
mutex_lock(&data->lock);
if (val >= MAX127_FULL_RANGE)
data->ctrl_byte[channel] |= MAX127_CTRL_RNG;
else
data->ctrl_byte[channel] &= ~MAX127_CTRL_RNG;
mutex_unlock(&data->lock);
return 0;
}
static umode_t max127_is_visible(const void *_data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
if (type == hwmon_in) {
switch (attr) {
case hwmon_in_input:
return 0444;
case hwmon_in_min:
case hwmon_in_max:
return 0644;
default:
break;
}
}
return 0;
}
static int max127_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
int status;
struct max127_data *data = dev_get_drvdata(dev);
if (type != hwmon_in)
return -EOPNOTSUPP;
switch (attr) {
case hwmon_in_input:
status = max127_read_input(data, channel, val);
break;
case hwmon_in_min:
status = max127_read_min(data, channel, val);
break;
case hwmon_in_max:
status = max127_read_max(data, channel, val);
break;
default:
status = -EOPNOTSUPP;
break;
}
return status;
}
static int max127_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
int status;
struct max127_data *data = dev_get_drvdata(dev);
if (type != hwmon_in)
return -EOPNOTSUPP;
switch (attr) {
case hwmon_in_min:
status = max127_write_min(data, channel, val);
break;
case hwmon_in_max:
status = max127_write_max(data, channel, val);
break;
default:
status = -EOPNOTSUPP;
break;
}
return status;
}
static const struct hwmon_ops max127_hwmon_ops = {
.is_visible = max127_is_visible,
.read = max127_read,
.write = max127_write,
};
static const struct hwmon_channel_info * const max127_info[] = {
HWMON_CHANNEL_INFO(in,
HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX,
HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX,
HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX,
HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX,
HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX,
HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX,
HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX,
HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX),
NULL,
};
static const struct hwmon_chip_info max127_chip_info = {
.ops = &max127_hwmon_ops,
.info = max127_info,
};
static int max127_probe(struct i2c_client *client)
{
int i;
struct device *hwmon_dev;
struct max127_data *data;
struct device *dev = &client->dev;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
mutex_init(&data->lock);
for (i = 0; i < ARRAY_SIZE(data->ctrl_byte); i++)
data->ctrl_byte[i] = (MAX127_CTRL_START |
MAX127_SET_CHANNEL(i));
hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
data,
&max127_chip_info,
NULL);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id max127_id[] = {
{ "max127", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max127_id);
static struct i2c_driver max127_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "max127",
},
.probe = max127_probe,
.id_table = max127_id,
};
module_i2c_driver(max127_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Mike Choi <[email protected]>");
MODULE_AUTHOR("Tao Ren <[email protected]>");
MODULE_DESCRIPTION("MAX127 Hardware Monitoring driver");
|
linux-master
|
drivers/hwmon/max127.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* max1111.c - +2.7V, Low-Power, Multichannel, Serial 8-bit ADCs
*
* Based on arch/arm/mach-pxa/corgi_ssp.c
*
* Copyright (C) 2004-2005 Richard Purdie
*
* Copyright (C) 2008 Marvell International Ltd.
* Eric Miao <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
enum chips { max1110, max1111, max1112, max1113 };
#define MAX1111_TX_BUF_SIZE 1
#define MAX1111_RX_BUF_SIZE 2
/* MAX1111 Commands */
#define MAX1111_CTRL_PD0 (1u << 0)
#define MAX1111_CTRL_PD1 (1u << 1)
#define MAX1111_CTRL_SGL (1u << 2)
#define MAX1111_CTRL_UNI (1u << 3)
#define MAX1110_CTRL_SEL_SH (4)
#define MAX1111_CTRL_SEL_SH (5) /* NOTE: bit 4 is ignored */
#define MAX1111_CTRL_STR (1u << 7)
struct max1111_data {
struct spi_device *spi;
struct device *hwmon_dev;
struct spi_message msg;
struct spi_transfer xfer[2];
uint8_t tx_buf[MAX1111_TX_BUF_SIZE];
uint8_t rx_buf[MAX1111_RX_BUF_SIZE];
struct mutex drvdata_lock;
/* protect msg, xfer and buffers from multiple access */
int sel_sh;
int lsb;
};
static int max1111_read(struct device *dev, int channel)
{
struct max1111_data *data = dev_get_drvdata(dev);
uint8_t v1, v2;
int err;
/* writing to drvdata struct is not thread safe, wait on mutex */
mutex_lock(&data->drvdata_lock);
data->tx_buf[0] = (channel << data->sel_sh) |
MAX1111_CTRL_PD0 | MAX1111_CTRL_PD1 |
MAX1111_CTRL_SGL | MAX1111_CTRL_UNI | MAX1111_CTRL_STR;
err = spi_sync(data->spi, &data->msg);
if (err < 0) {
dev_err(dev, "spi_sync failed with %d\n", err);
mutex_unlock(&data->drvdata_lock);
return err;
}
v1 = data->rx_buf[0];
v2 = data->rx_buf[1];
mutex_unlock(&data->drvdata_lock);
if ((v1 & 0xc0) || (v2 & 0x3f))
return -EINVAL;
return (v1 << 2) | (v2 >> 6);
}
#ifdef CONFIG_SHARPSL_PM
static struct max1111_data *the_max1111;
int max1111_read_channel(int channel);
int max1111_read_channel(int channel)
{
if (!the_max1111 || !the_max1111->spi)
return -ENODEV;
return max1111_read(&the_max1111->spi->dev, channel);
}
EXPORT_SYMBOL(max1111_read_channel);
#endif
/*
* NOTE: SPI devices do not have a default 'name' attribute, which is
* likely to be used by hwmon applications to distinguish between
* different devices, explicitly add a name attribute here.
*/
static ssize_t name_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%s\n", to_spi_device(dev)->modalias);
}
static ssize_t show_adc(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct max1111_data *data = dev_get_drvdata(dev);
int channel = to_sensor_dev_attr(attr)->index;
int ret;
ret = max1111_read(dev, channel);
if (ret < 0)
return ret;
/*
* Assume the reference voltage to be 2.048V or 4.096V, with an 8-bit
* sample. The LSB weight is 8mV or 16mV depending on the chip type.
*/
return sprintf(buf, "%d\n", ret * data->lsb);
}
#define MAX1111_ADC_ATTR(_id) \
SENSOR_DEVICE_ATTR(in##_id##_input, S_IRUGO, show_adc, NULL, _id)
static DEVICE_ATTR_RO(name);
static MAX1111_ADC_ATTR(0);
static MAX1111_ADC_ATTR(1);
static MAX1111_ADC_ATTR(2);
static MAX1111_ADC_ATTR(3);
static MAX1111_ADC_ATTR(4);
static MAX1111_ADC_ATTR(5);
static MAX1111_ADC_ATTR(6);
static MAX1111_ADC_ATTR(7);
static struct attribute *max1111_attributes[] = {
&dev_attr_name.attr,
&sensor_dev_attr_in0_input.dev_attr.attr,
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in2_input.dev_attr.attr,
&sensor_dev_attr_in3_input.dev_attr.attr,
NULL,
};
static const struct attribute_group max1111_attr_group = {
.attrs = max1111_attributes,
};
static struct attribute *max1110_attributes[] = {
&sensor_dev_attr_in4_input.dev_attr.attr,
&sensor_dev_attr_in5_input.dev_attr.attr,
&sensor_dev_attr_in6_input.dev_attr.attr,
&sensor_dev_attr_in7_input.dev_attr.attr,
NULL,
};
static const struct attribute_group max1110_attr_group = {
.attrs = max1110_attributes,
};
static int setup_transfer(struct max1111_data *data)
{
struct spi_message *m;
struct spi_transfer *x;
m = &data->msg;
x = &data->xfer[0];
spi_message_init(m);
x->tx_buf = &data->tx_buf[0];
x->len = MAX1111_TX_BUF_SIZE;
spi_message_add_tail(x, m);
x++;
x->rx_buf = &data->rx_buf[0];
x->len = MAX1111_RX_BUF_SIZE;
spi_message_add_tail(x, m);
return 0;
}
static int max1111_probe(struct spi_device *spi)
{
enum chips chip = spi_get_device_id(spi)->driver_data;
struct max1111_data *data;
int err;
spi->bits_per_word = 8;
spi->mode = SPI_MODE_0;
err = spi_setup(spi);
if (err < 0)
return err;
data = devm_kzalloc(&spi->dev, sizeof(struct max1111_data), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
switch (chip) {
case max1110:
data->lsb = 8;
data->sel_sh = MAX1110_CTRL_SEL_SH;
break;
case max1111:
data->lsb = 8;
data->sel_sh = MAX1111_CTRL_SEL_SH;
break;
case max1112:
data->lsb = 16;
data->sel_sh = MAX1110_CTRL_SEL_SH;
break;
case max1113:
data->lsb = 16;
data->sel_sh = MAX1111_CTRL_SEL_SH;
break;
}
err = setup_transfer(data);
if (err)
return err;
mutex_init(&data->drvdata_lock);
data->spi = spi;
spi_set_drvdata(spi, data);
err = sysfs_create_group(&spi->dev.kobj, &max1111_attr_group);
if (err) {
dev_err(&spi->dev, "failed to create attribute group\n");
return err;
}
if (chip == max1110 || chip == max1112) {
err = sysfs_create_group(&spi->dev.kobj, &max1110_attr_group);
if (err) {
dev_err(&spi->dev,
"failed to create extended attribute group\n");
goto err_remove;
}
}
data->hwmon_dev = hwmon_device_register(&spi->dev);
if (IS_ERR(data->hwmon_dev)) {
dev_err(&spi->dev, "failed to create hwmon device\n");
err = PTR_ERR(data->hwmon_dev);
goto err_remove;
}
#ifdef CONFIG_SHARPSL_PM
the_max1111 = data;
#endif
return 0;
err_remove:
sysfs_remove_group(&spi->dev.kobj, &max1110_attr_group);
sysfs_remove_group(&spi->dev.kobj, &max1111_attr_group);
return err;
}
static void max1111_remove(struct spi_device *spi)
{
struct max1111_data *data = spi_get_drvdata(spi);
#ifdef CONFIG_SHARPSL_PM
the_max1111 = NULL;
#endif
hwmon_device_unregister(data->hwmon_dev);
sysfs_remove_group(&spi->dev.kobj, &max1110_attr_group);
sysfs_remove_group(&spi->dev.kobj, &max1111_attr_group);
mutex_destroy(&data->drvdata_lock);
}
static const struct spi_device_id max1111_ids[] = {
{ "max1110", max1110 },
{ "max1111", max1111 },
{ "max1112", max1112 },
{ "max1113", max1113 },
{ },
};
MODULE_DEVICE_TABLE(spi, max1111_ids);
static struct spi_driver max1111_driver = {
.driver = {
.name = "max1111",
},
.id_table = max1111_ids,
.probe = max1111_probe,
.remove = max1111_remove,
};
module_spi_driver(max1111_driver);
MODULE_AUTHOR("Eric Miao <[email protected]>");
MODULE_DESCRIPTION("MAX1110/MAX1111/MAX1112/MAX1113 ADC Driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/max1111.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for MAX31730 3-Channel Remote Temperature Sensor
*
* Copyright (c) 2019 Guenter Roeck <[email protected]>
*/
#include <linux/bits.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/hwmon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/slab.h>
/* Addresses scanned */
static const unsigned short normal_i2c[] = { 0x1c, 0x1d, 0x1e, 0x1f, 0x4c,
0x4d, 0x4e, 0x4f, I2C_CLIENT_END };
/* The MAX31730 registers */
#define MAX31730_REG_TEMP 0x00
#define MAX31730_REG_CONF 0x13
#define MAX31730_STOP BIT(7)
#define MAX31730_EXTRANGE BIT(1)
#define MAX31730_REG_TEMP_OFFSET 0x16
#define MAX31730_TEMP_OFFSET_BASELINE 0x77
#define MAX31730_REG_OFFSET_ENABLE 0x17
#define MAX31730_REG_TEMP_MAX 0x20
#define MAX31730_REG_TEMP_MIN 0x30
#define MAX31730_REG_STATUS_HIGH 0x32
#define MAX31730_REG_STATUS_LOW 0x33
#define MAX31730_REG_CHANNEL_ENABLE 0x35
#define MAX31730_REG_TEMP_FAULT 0x36
#define MAX31730_REG_MFG_ID 0x50
#define MAX31730_MFG_ID 0x4d
#define MAX31730_REG_MFG_REV 0x51
#define MAX31730_MFG_REV 0x01
#define MAX31730_TEMP_MIN (-128000)
#define MAX31730_TEMP_MAX 127937
/* Each client has this additional data */
struct max31730_data {
struct i2c_client *client;
u8 orig_conf;
u8 current_conf;
u8 offset_enable;
u8 channel_enable;
};
/*-----------------------------------------------------------------------*/
static inline long max31730_reg_to_mc(s16 temp)
{
return DIV_ROUND_CLOSEST((temp >> 4) * 1000, 16);
}
static int max31730_write_config(struct max31730_data *data, u8 set_mask,
u8 clr_mask)
{
u8 value;
clr_mask |= MAX31730_EXTRANGE;
value = data->current_conf & ~clr_mask;
value |= set_mask;
if (data->current_conf != value) {
s32 err;
err = i2c_smbus_write_byte_data(data->client, MAX31730_REG_CONF,
value);
if (err)
return err;
data->current_conf = value;
}
return 0;
}
static int max31730_set_enable(struct i2c_client *client, int reg,
u8 *confdata, int channel, bool enable)
{
u8 regval = *confdata;
int err;
if (enable)
regval |= BIT(channel);
else
regval &= ~BIT(channel);
if (regval != *confdata) {
err = i2c_smbus_write_byte_data(client, reg, regval);
if (err)
return err;
*confdata = regval;
}
return 0;
}
static int max31730_set_offset_enable(struct max31730_data *data, int channel,
bool enable)
{
return max31730_set_enable(data->client, MAX31730_REG_OFFSET_ENABLE,
&data->offset_enable, channel, enable);
}
static int max31730_set_channel_enable(struct max31730_data *data, int channel,
bool enable)
{
return max31730_set_enable(data->client, MAX31730_REG_CHANNEL_ENABLE,
&data->channel_enable, channel, enable);
}
static int max31730_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct max31730_data *data = dev_get_drvdata(dev);
int regval, reg, offset;
if (type != hwmon_temp)
return -EINVAL;
switch (attr) {
case hwmon_temp_input:
if (!(data->channel_enable & BIT(channel)))
return -ENODATA;
reg = MAX31730_REG_TEMP + (channel * 2);
break;
case hwmon_temp_max:
reg = MAX31730_REG_TEMP_MAX + (channel * 2);
break;
case hwmon_temp_min:
reg = MAX31730_REG_TEMP_MIN;
break;
case hwmon_temp_enable:
*val = !!(data->channel_enable & BIT(channel));
return 0;
case hwmon_temp_offset:
if (!channel)
return -EINVAL;
if (!(data->offset_enable & BIT(channel))) {
*val = 0;
return 0;
}
offset = i2c_smbus_read_byte_data(data->client,
MAX31730_REG_TEMP_OFFSET);
if (offset < 0)
return offset;
*val = (offset - MAX31730_TEMP_OFFSET_BASELINE) * 125;
return 0;
case hwmon_temp_fault:
regval = i2c_smbus_read_byte_data(data->client,
MAX31730_REG_TEMP_FAULT);
if (regval < 0)
return regval;
*val = !!(regval & BIT(channel));
return 0;
case hwmon_temp_min_alarm:
regval = i2c_smbus_read_byte_data(data->client,
MAX31730_REG_STATUS_LOW);
if (regval < 0)
return regval;
*val = !!(regval & BIT(channel));
return 0;
case hwmon_temp_max_alarm:
regval = i2c_smbus_read_byte_data(data->client,
MAX31730_REG_STATUS_HIGH);
if (regval < 0)
return regval;
*val = !!(regval & BIT(channel));
return 0;
default:
return -EINVAL;
}
regval = i2c_smbus_read_word_swapped(data->client, reg);
if (regval < 0)
return regval;
*val = max31730_reg_to_mc(regval);
return 0;
}
static int max31730_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
struct max31730_data *data = dev_get_drvdata(dev);
int reg, err;
if (type != hwmon_temp)
return -EINVAL;
switch (attr) {
case hwmon_temp_max:
reg = MAX31730_REG_TEMP_MAX + channel * 2;
break;
case hwmon_temp_min:
reg = MAX31730_REG_TEMP_MIN;
break;
case hwmon_temp_enable:
if (val != 0 && val != 1)
return -EINVAL;
return max31730_set_channel_enable(data, channel, val);
case hwmon_temp_offset:
val = clamp_val(val, -14875, 17000) + 14875;
val = DIV_ROUND_CLOSEST(val, 125);
err = max31730_set_offset_enable(data, channel,
val != MAX31730_TEMP_OFFSET_BASELINE);
if (err)
return err;
return i2c_smbus_write_byte_data(data->client,
MAX31730_REG_TEMP_OFFSET, val);
default:
return -EINVAL;
}
val = clamp_val(val, MAX31730_TEMP_MIN, MAX31730_TEMP_MAX);
val = DIV_ROUND_CLOSEST(val << 4, 1000) << 4;
return i2c_smbus_write_word_swapped(data->client, reg, (u16)val);
}
static umode_t max31730_is_visible(const void *data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_input:
case hwmon_temp_min_alarm:
case hwmon_temp_max_alarm:
case hwmon_temp_fault:
return 0444;
case hwmon_temp_min:
return channel ? 0444 : 0644;
case hwmon_temp_offset:
case hwmon_temp_enable:
case hwmon_temp_max:
return 0644;
}
break;
default:
break;
}
return 0;
}
static const struct hwmon_channel_info * const max31730_info[] = {
HWMON_CHANNEL_INFO(chip,
HWMON_C_REGISTER_TZ),
HWMON_CHANNEL_INFO(temp,
HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
HWMON_T_ENABLE |
HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM,
HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
HWMON_T_OFFSET | HWMON_T_ENABLE |
HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM |
HWMON_T_FAULT,
HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
HWMON_T_OFFSET | HWMON_T_ENABLE |
HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM |
HWMON_T_FAULT,
HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
HWMON_T_OFFSET | HWMON_T_ENABLE |
HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM |
HWMON_T_FAULT
),
NULL
};
static const struct hwmon_ops max31730_hwmon_ops = {
.is_visible = max31730_is_visible,
.read = max31730_read,
.write = max31730_write,
};
static const struct hwmon_chip_info max31730_chip_info = {
.ops = &max31730_hwmon_ops,
.info = max31730_info,
};
static void max31730_remove(void *data)
{
struct max31730_data *max31730 = data;
struct i2c_client *client = max31730->client;
i2c_smbus_write_byte_data(client, MAX31730_REG_CONF,
max31730->orig_conf);
}
static int
max31730_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct device *hwmon_dev;
struct max31730_data *data;
int status, err;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA))
return -EIO;
data = devm_kzalloc(dev, sizeof(struct max31730_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
/* Cache original configuration and enable status */
status = i2c_smbus_read_byte_data(client, MAX31730_REG_CHANNEL_ENABLE);
if (status < 0)
return status;
data->channel_enable = status;
status = i2c_smbus_read_byte_data(client, MAX31730_REG_OFFSET_ENABLE);
if (status < 0)
return status;
data->offset_enable = status;
status = i2c_smbus_read_byte_data(client, MAX31730_REG_CONF);
if (status < 0)
return status;
data->orig_conf = status;
data->current_conf = status;
err = max31730_write_config(data,
data->channel_enable ? 0 : MAX31730_STOP,
data->channel_enable ? MAX31730_STOP : 0);
if (err)
return err;
dev_set_drvdata(dev, data);
err = devm_add_action_or_reset(dev, max31730_remove, data);
if (err)
return err;
hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
data,
&max31730_chip_info,
NULL);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id max31730_ids[] = {
{ "max31730", 0, },
{ }
};
MODULE_DEVICE_TABLE(i2c, max31730_ids);
static const struct of_device_id __maybe_unused max31730_of_match[] = {
{
.compatible = "maxim,max31730",
},
{ },
};
MODULE_DEVICE_TABLE(of, max31730_of_match);
static bool max31730_check_reg_temp(struct i2c_client *client,
int reg)
{
int regval;
regval = i2c_smbus_read_byte_data(client, reg + 1);
return regval < 0 || (regval & 0x0f);
}
/* Return 0 if detection is successful, -ENODEV otherwise */
static int max31730_detect(struct i2c_client *client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
int regval;
int i;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_WORD_DATA))
return -ENODEV;
regval = i2c_smbus_read_byte_data(client, MAX31730_REG_MFG_ID);
if (regval != MAX31730_MFG_ID)
return -ENODEV;
regval = i2c_smbus_read_byte_data(client, MAX31730_REG_MFG_REV);
if (regval != MAX31730_MFG_REV)
return -ENODEV;
/* lower 4 bit of temperature and limit registers must be 0 */
if (max31730_check_reg_temp(client, MAX31730_REG_TEMP_MIN))
return -ENODEV;
for (i = 0; i < 4; i++) {
if (max31730_check_reg_temp(client, MAX31730_REG_TEMP + i * 2))
return -ENODEV;
if (max31730_check_reg_temp(client,
MAX31730_REG_TEMP_MAX + i * 2))
return -ENODEV;
}
strscpy(info->type, "max31730", I2C_NAME_SIZE);
return 0;
}
static int max31730_suspend(struct device *dev)
{
struct max31730_data *data = dev_get_drvdata(dev);
return max31730_write_config(data, MAX31730_STOP, 0);
}
static int max31730_resume(struct device *dev)
{
struct max31730_data *data = dev_get_drvdata(dev);
return max31730_write_config(data, 0, MAX31730_STOP);
}
static DEFINE_SIMPLE_DEV_PM_OPS(max31730_pm_ops, max31730_suspend, max31730_resume);
static struct i2c_driver max31730_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "max31730",
.of_match_table = of_match_ptr(max31730_of_match),
.pm = pm_sleep_ptr(&max31730_pm_ops),
},
.probe = max31730_probe,
.id_table = max31730_ids,
.detect = max31730_detect,
.address_list = normal_i2c,
};
module_i2c_driver(max31730_driver);
MODULE_AUTHOR("Guenter Roeck <[email protected]>");
MODULE_DESCRIPTION("MAX31730 driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/max31730.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2007-2009 Luca Tettamanti <[email protected]>
*
* See COPYING in the top level directory of the kernel tree.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/debugfs.h>
#include <linux/kernel.h>
#include <linux/hwmon.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/dmi.h>
#include <linux/jiffies.h>
#include <linux/err.h>
#include <linux/acpi.h>
#define ATK_HID "ATK0110"
static bool new_if;
module_param(new_if, bool, 0);
MODULE_PARM_DESC(new_if, "Override detection heuristic and force the use of the new ATK0110 interface");
static const struct dmi_system_id __initconst atk_force_new_if[] = {
{
/* Old interface has broken MCH temp monitoring */
.ident = "Asus Sabertooth X58",
.matches = {
DMI_MATCH(DMI_BOARD_NAME, "SABERTOOTH X58")
}
}, {
/* Old interface reads the same sensor for fan0 and fan1 */
.ident = "Asus M5A78L",
.matches = {
DMI_MATCH(DMI_BOARD_NAME, "M5A78L")
}
},
{ }
};
/*
* Minimum time between readings, enforced in order to avoid
* hogging the CPU.
*/
#define CACHE_TIME HZ
#define BOARD_ID "MBIF"
#define METHOD_ENUMERATE "GGRP"
#define METHOD_READ "GITM"
#define METHOD_WRITE "SITM"
#define METHOD_OLD_READ_TMP "RTMP"
#define METHOD_OLD_READ_VLT "RVLT"
#define METHOD_OLD_READ_FAN "RFAN"
#define METHOD_OLD_ENUM_TMP "TSIF"
#define METHOD_OLD_ENUM_VLT "VSIF"
#define METHOD_OLD_ENUM_FAN "FSIF"
#define ATK_MUX_HWMON 0x00000006ULL
#define ATK_MUX_MGMT 0x00000011ULL
#define ATK_CLASS_MASK 0xff000000ULL
#define ATK_CLASS_FREQ_CTL 0x03000000ULL
#define ATK_CLASS_FAN_CTL 0x04000000ULL
#define ATK_CLASS_HWMON 0x06000000ULL
#define ATK_CLASS_MGMT 0x11000000ULL
#define ATK_TYPE_MASK 0x00ff0000ULL
#define HWMON_TYPE_VOLT 0x00020000ULL
#define HWMON_TYPE_TEMP 0x00030000ULL
#define HWMON_TYPE_FAN 0x00040000ULL
#define ATK_ELEMENT_ID_MASK 0x0000ffffULL
#define ATK_EC_ID 0x11060004ULL
enum atk_pack_member {
HWMON_PACK_FLAGS,
HWMON_PACK_NAME,
HWMON_PACK_LIMIT1,
HWMON_PACK_LIMIT2,
HWMON_PACK_ENABLE
};
/* New package format */
#define _HWMON_NEW_PACK_SIZE 7
#define _HWMON_NEW_PACK_FLAGS 0
#define _HWMON_NEW_PACK_NAME 1
#define _HWMON_NEW_PACK_UNK1 2
#define _HWMON_NEW_PACK_UNK2 3
#define _HWMON_NEW_PACK_LIMIT1 4
#define _HWMON_NEW_PACK_LIMIT2 5
#define _HWMON_NEW_PACK_ENABLE 6
/* Old package format */
#define _HWMON_OLD_PACK_SIZE 5
#define _HWMON_OLD_PACK_FLAGS 0
#define _HWMON_OLD_PACK_NAME 1
#define _HWMON_OLD_PACK_LIMIT1 2
#define _HWMON_OLD_PACK_LIMIT2 3
#define _HWMON_OLD_PACK_ENABLE 4
struct atk_data {
struct device *hwmon_dev;
acpi_handle atk_handle;
struct acpi_device *acpi_dev;
bool old_interface;
/* old interface */
acpi_handle rtmp_handle;
acpi_handle rvlt_handle;
acpi_handle rfan_handle;
/* new interface */
acpi_handle enumerate_handle;
acpi_handle read_handle;
acpi_handle write_handle;
bool disable_ec;
int voltage_count;
int temperature_count;
int fan_count;
struct list_head sensor_list;
struct attribute_group attr_group;
const struct attribute_group *attr_groups[2];
struct {
struct dentry *root;
u32 id;
} debugfs;
};
typedef ssize_t (*sysfs_show_func)(struct device *dev,
struct device_attribute *attr, char *buf);
static const struct acpi_device_id atk_ids[] = {
{ATK_HID, 0},
{"", 0},
};
MODULE_DEVICE_TABLE(acpi, atk_ids);
#define ATTR_NAME_SIZE 16 /* Worst case is "tempN_input" */
struct atk_sensor_data {
struct list_head list;
struct atk_data *data;
struct device_attribute label_attr;
struct device_attribute input_attr;
struct device_attribute limit1_attr;
struct device_attribute limit2_attr;
char label_attr_name[ATTR_NAME_SIZE];
char input_attr_name[ATTR_NAME_SIZE];
char limit1_attr_name[ATTR_NAME_SIZE];
char limit2_attr_name[ATTR_NAME_SIZE];
u64 id;
u64 type;
u64 limit1;
u64 limit2;
u64 cached_value;
unsigned long last_updated; /* in jiffies */
bool is_valid;
char const *acpi_name;
};
/*
* Return buffer format:
* [0-3] "value" is valid flag
* [4-7] value
* [8- ] unknown stuff on newer mobos
*/
struct atk_acpi_ret_buffer {
u32 flags;
u32 value;
u8 data[];
};
/* Input buffer used for GITM and SITM methods */
struct atk_acpi_input_buf {
u32 id;
u32 param1;
u32 param2;
};
static int atk_add(struct acpi_device *device);
static void atk_remove(struct acpi_device *device);
static void atk_print_sensor(struct atk_data *data, union acpi_object *obj);
static int atk_read_value(struct atk_sensor_data *sensor, u64 *value);
static struct acpi_driver atk_driver = {
.name = ATK_HID,
.class = "hwmon",
.ids = atk_ids,
.ops = {
.add = atk_add,
.remove = atk_remove,
},
};
#define input_to_atk_sensor(attr) \
container_of(attr, struct atk_sensor_data, input_attr)
#define label_to_atk_sensor(attr) \
container_of(attr, struct atk_sensor_data, label_attr)
#define limit1_to_atk_sensor(attr) \
container_of(attr, struct atk_sensor_data, limit1_attr)
#define limit2_to_atk_sensor(attr) \
container_of(attr, struct atk_sensor_data, limit2_attr)
static ssize_t atk_input_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct atk_sensor_data *s = input_to_atk_sensor(attr);
u64 value;
int err;
err = atk_read_value(s, &value);
if (err)
return err;
if (s->type == HWMON_TYPE_TEMP)
/* ACPI returns decidegree */
value *= 100;
return sprintf(buf, "%llu\n", value);
}
static ssize_t atk_label_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct atk_sensor_data *s = label_to_atk_sensor(attr);
return sprintf(buf, "%s\n", s->acpi_name);
}
static ssize_t atk_limit1_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct atk_sensor_data *s = limit1_to_atk_sensor(attr);
u64 value = s->limit1;
if (s->type == HWMON_TYPE_TEMP)
value *= 100;
return sprintf(buf, "%lld\n", value);
}
static ssize_t atk_limit2_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct atk_sensor_data *s = limit2_to_atk_sensor(attr);
u64 value = s->limit2;
if (s->type == HWMON_TYPE_TEMP)
value *= 100;
return sprintf(buf, "%lld\n", value);
}
static void atk_init_attribute(struct device_attribute *attr, char *name,
sysfs_show_func show)
{
sysfs_attr_init(&attr->attr);
attr->attr.name = name;
attr->attr.mode = 0444;
attr->show = show;
attr->store = NULL;
}
static union acpi_object *atk_get_pack_member(struct atk_data *data,
union acpi_object *pack,
enum atk_pack_member m)
{
bool old_if = data->old_interface;
int offset;
switch (m) {
case HWMON_PACK_FLAGS:
offset = old_if ? _HWMON_OLD_PACK_FLAGS : _HWMON_NEW_PACK_FLAGS;
break;
case HWMON_PACK_NAME:
offset = old_if ? _HWMON_OLD_PACK_NAME : _HWMON_NEW_PACK_NAME;
break;
case HWMON_PACK_LIMIT1:
offset = old_if ? _HWMON_OLD_PACK_LIMIT1 :
_HWMON_NEW_PACK_LIMIT1;
break;
case HWMON_PACK_LIMIT2:
offset = old_if ? _HWMON_OLD_PACK_LIMIT2 :
_HWMON_NEW_PACK_LIMIT2;
break;
case HWMON_PACK_ENABLE:
offset = old_if ? _HWMON_OLD_PACK_ENABLE :
_HWMON_NEW_PACK_ENABLE;
break;
default:
return NULL;
}
return &pack->package.elements[offset];
}
/*
* New package format is:
* - flag (int)
* class - used for de-muxing the request to the correct GITn
* type (volt, temp, fan)
* sensor id |
* sensor id - used for de-muxing the request _inside_ the GITn
* - name (str)
* - unknown (int)
* - unknown (int)
* - limit1 (int)
* - limit2 (int)
* - enable (int)
*
* The old package has the same format but it's missing the two unknown fields.
*/
static int validate_hwmon_pack(struct atk_data *data, union acpi_object *obj)
{
struct device *dev = &data->acpi_dev->dev;
union acpi_object *tmp;
bool old_if = data->old_interface;
int const expected_size = old_if ? _HWMON_OLD_PACK_SIZE :
_HWMON_NEW_PACK_SIZE;
if (obj->type != ACPI_TYPE_PACKAGE) {
dev_warn(dev, "Invalid type: %d\n", obj->type);
return -EINVAL;
}
if (obj->package.count != expected_size) {
dev_warn(dev, "Invalid package size: %d, expected: %d\n",
obj->package.count, expected_size);
return -EINVAL;
}
tmp = atk_get_pack_member(data, obj, HWMON_PACK_FLAGS);
if (tmp->type != ACPI_TYPE_INTEGER) {
dev_warn(dev, "Invalid type (flag): %d\n", tmp->type);
return -EINVAL;
}
tmp = atk_get_pack_member(data, obj, HWMON_PACK_NAME);
if (tmp->type != ACPI_TYPE_STRING) {
dev_warn(dev, "Invalid type (name): %d\n", tmp->type);
return -EINVAL;
}
/* Don't check... we don't know what they're useful for anyway */
#if 0
tmp = &obj->package.elements[HWMON_PACK_UNK1];
if (tmp->type != ACPI_TYPE_INTEGER) {
dev_warn(dev, "Invalid type (unk1): %d\n", tmp->type);
return -EINVAL;
}
tmp = &obj->package.elements[HWMON_PACK_UNK2];
if (tmp->type != ACPI_TYPE_INTEGER) {
dev_warn(dev, "Invalid type (unk2): %d\n", tmp->type);
return -EINVAL;
}
#endif
tmp = atk_get_pack_member(data, obj, HWMON_PACK_LIMIT1);
if (tmp->type != ACPI_TYPE_INTEGER) {
dev_warn(dev, "Invalid type (limit1): %d\n", tmp->type);
return -EINVAL;
}
tmp = atk_get_pack_member(data, obj, HWMON_PACK_LIMIT2);
if (tmp->type != ACPI_TYPE_INTEGER) {
dev_warn(dev, "Invalid type (limit2): %d\n", tmp->type);
return -EINVAL;
}
tmp = atk_get_pack_member(data, obj, HWMON_PACK_ENABLE);
if (tmp->type != ACPI_TYPE_INTEGER) {
dev_warn(dev, "Invalid type (enable): %d\n", tmp->type);
return -EINVAL;
}
atk_print_sensor(data, obj);
return 0;
}
#ifdef DEBUG
static char const *atk_sensor_type(union acpi_object *flags)
{
u64 type = flags->integer.value & ATK_TYPE_MASK;
char const *what;
switch (type) {
case HWMON_TYPE_VOLT:
what = "voltage";
break;
case HWMON_TYPE_TEMP:
what = "temperature";
break;
case HWMON_TYPE_FAN:
what = "fan";
break;
default:
what = "unknown";
break;
}
return what;
}
#endif
static void atk_print_sensor(struct atk_data *data, union acpi_object *obj)
{
#ifdef DEBUG
struct device *dev = &data->acpi_dev->dev;
union acpi_object *flags;
union acpi_object *name;
union acpi_object *limit1;
union acpi_object *limit2;
union acpi_object *enable;
char const *what;
flags = atk_get_pack_member(data, obj, HWMON_PACK_FLAGS);
name = atk_get_pack_member(data, obj, HWMON_PACK_NAME);
limit1 = atk_get_pack_member(data, obj, HWMON_PACK_LIMIT1);
limit2 = atk_get_pack_member(data, obj, HWMON_PACK_LIMIT2);
enable = atk_get_pack_member(data, obj, HWMON_PACK_ENABLE);
what = atk_sensor_type(flags);
dev_dbg(dev, "%s: %#llx %s [%llu-%llu] %s\n", what,
flags->integer.value,
name->string.pointer,
limit1->integer.value, limit2->integer.value,
enable->integer.value ? "enabled" : "disabled");
#endif
}
static int atk_read_value_old(struct atk_sensor_data *sensor, u64 *value)
{
struct atk_data *data = sensor->data;
struct device *dev = &data->acpi_dev->dev;
struct acpi_object_list params;
union acpi_object id;
acpi_status status;
acpi_handle method;
switch (sensor->type) {
case HWMON_TYPE_VOLT:
method = data->rvlt_handle;
break;
case HWMON_TYPE_TEMP:
method = data->rtmp_handle;
break;
case HWMON_TYPE_FAN:
method = data->rfan_handle;
break;
default:
return -EINVAL;
}
id.type = ACPI_TYPE_INTEGER;
id.integer.value = sensor->id;
params.count = 1;
params.pointer = &id;
status = acpi_evaluate_integer(method, NULL, ¶ms, value);
if (status != AE_OK) {
dev_warn(dev, "%s: ACPI exception: %s\n", __func__,
acpi_format_exception(status));
return -EIO;
}
return 0;
}
static union acpi_object *atk_ggrp(struct atk_data *data, u16 mux)
{
struct device *dev = &data->acpi_dev->dev;
struct acpi_buffer buf;
acpi_status ret;
struct acpi_object_list params;
union acpi_object id;
union acpi_object *pack;
id.type = ACPI_TYPE_INTEGER;
id.integer.value = mux;
params.count = 1;
params.pointer = &id;
buf.length = ACPI_ALLOCATE_BUFFER;
ret = acpi_evaluate_object(data->enumerate_handle, NULL, ¶ms, &buf);
if (ret != AE_OK) {
dev_err(dev, "GGRP[%#x] ACPI exception: %s\n", mux,
acpi_format_exception(ret));
return ERR_PTR(-EIO);
}
pack = buf.pointer;
if (pack->type != ACPI_TYPE_PACKAGE) {
/* Execution was successful, but the id was not found */
ACPI_FREE(pack);
return ERR_PTR(-ENOENT);
}
if (pack->package.count < 1) {
dev_err(dev, "GGRP[%#x] package is too small\n", mux);
ACPI_FREE(pack);
return ERR_PTR(-EIO);
}
return pack;
}
static union acpi_object *atk_gitm(struct atk_data *data, u64 id)
{
struct device *dev = &data->acpi_dev->dev;
struct atk_acpi_input_buf buf;
union acpi_object tmp;
struct acpi_object_list params;
struct acpi_buffer ret;
union acpi_object *obj;
acpi_status status;
buf.id = id;
buf.param1 = 0;
buf.param2 = 0;
tmp.type = ACPI_TYPE_BUFFER;
tmp.buffer.pointer = (u8 *)&buf;
tmp.buffer.length = sizeof(buf);
params.count = 1;
params.pointer = (void *)&tmp;
ret.length = ACPI_ALLOCATE_BUFFER;
status = acpi_evaluate_object_typed(data->read_handle, NULL, ¶ms,
&ret, ACPI_TYPE_BUFFER);
if (status != AE_OK) {
dev_warn(dev, "GITM[%#llx] ACPI exception: %s\n", id,
acpi_format_exception(status));
return ERR_PTR(-EIO);
}
obj = ret.pointer;
/* Sanity check */
if (obj->buffer.length < 8) {
dev_warn(dev, "Unexpected ASBF length: %u\n",
obj->buffer.length);
ACPI_FREE(obj);
return ERR_PTR(-EIO);
}
return obj;
}
static union acpi_object *atk_sitm(struct atk_data *data,
struct atk_acpi_input_buf *buf)
{
struct device *dev = &data->acpi_dev->dev;
struct acpi_object_list params;
union acpi_object tmp;
struct acpi_buffer ret;
union acpi_object *obj;
acpi_status status;
tmp.type = ACPI_TYPE_BUFFER;
tmp.buffer.pointer = (u8 *)buf;
tmp.buffer.length = sizeof(*buf);
params.count = 1;
params.pointer = &tmp;
ret.length = ACPI_ALLOCATE_BUFFER;
status = acpi_evaluate_object_typed(data->write_handle, NULL, ¶ms,
&ret, ACPI_TYPE_BUFFER);
if (status != AE_OK) {
dev_warn(dev, "SITM[%#x] ACPI exception: %s\n", buf->id,
acpi_format_exception(status));
return ERR_PTR(-EIO);
}
obj = ret.pointer;
/* Sanity check */
if (obj->buffer.length < 8) {
dev_warn(dev, "Unexpected ASBF length: %u\n",
obj->buffer.length);
ACPI_FREE(obj);
return ERR_PTR(-EIO);
}
return obj;
}
static int atk_read_value_new(struct atk_sensor_data *sensor, u64 *value)
{
struct atk_data *data = sensor->data;
struct device *dev = &data->acpi_dev->dev;
union acpi_object *obj;
struct atk_acpi_ret_buffer *buf;
int err = 0;
obj = atk_gitm(data, sensor->id);
if (IS_ERR(obj))
return PTR_ERR(obj);
buf = (struct atk_acpi_ret_buffer *)obj->buffer.pointer;
if (buf->flags == 0) {
/*
* The reading is not valid, possible causes:
* - sensor failure
* - enumeration was FUBAR (and we didn't notice)
*/
dev_warn(dev, "Read failed, sensor = %#llx\n", sensor->id);
err = -EIO;
goto out;
}
*value = buf->value;
out:
ACPI_FREE(obj);
return err;
}
static int atk_read_value(struct atk_sensor_data *sensor, u64 *value)
{
int err;
if (!sensor->is_valid ||
time_after(jiffies, sensor->last_updated + CACHE_TIME)) {
if (sensor->data->old_interface)
err = atk_read_value_old(sensor, value);
else
err = atk_read_value_new(sensor, value);
if (err)
return err;
sensor->is_valid = true;
sensor->last_updated = jiffies;
sensor->cached_value = *value;
} else {
*value = sensor->cached_value;
err = 0;
}
return err;
}
#ifdef CONFIG_DEBUG_FS
static int atk_debugfs_gitm_get(void *p, u64 *val)
{
struct atk_data *data = p;
union acpi_object *ret;
struct atk_acpi_ret_buffer *buf;
int err = 0;
if (!data->read_handle)
return -ENODEV;
if (!data->debugfs.id)
return -EINVAL;
ret = atk_gitm(data, data->debugfs.id);
if (IS_ERR(ret))
return PTR_ERR(ret);
buf = (struct atk_acpi_ret_buffer *)ret->buffer.pointer;
if (buf->flags)
*val = buf->value;
else
err = -EIO;
ACPI_FREE(ret);
return err;
}
DEFINE_DEBUGFS_ATTRIBUTE(atk_debugfs_gitm, atk_debugfs_gitm_get, NULL,
"0x%08llx\n");
static int atk_acpi_print(char *buf, size_t sz, union acpi_object *obj)
{
int ret = 0;
switch (obj->type) {
case ACPI_TYPE_INTEGER:
ret = snprintf(buf, sz, "0x%08llx\n", obj->integer.value);
break;
case ACPI_TYPE_STRING:
ret = snprintf(buf, sz, "%s\n", obj->string.pointer);
break;
}
return ret;
}
static void atk_pack_print(char *buf, size_t sz, union acpi_object *pack)
{
int ret;
int i;
for (i = 0; i < pack->package.count; i++) {
union acpi_object *obj = &pack->package.elements[i];
ret = atk_acpi_print(buf, sz, obj);
if (ret >= sz)
break;
buf += ret;
sz -= ret;
}
}
static int atk_debugfs_ggrp_open(struct inode *inode, struct file *file)
{
struct atk_data *data = inode->i_private;
char *buf = NULL;
union acpi_object *ret;
u8 cls;
int i;
if (!data->enumerate_handle)
return -ENODEV;
if (!data->debugfs.id)
return -EINVAL;
cls = (data->debugfs.id & 0xff000000) >> 24;
ret = atk_ggrp(data, cls);
if (IS_ERR(ret))
return PTR_ERR(ret);
for (i = 0; i < ret->package.count; i++) {
union acpi_object *pack = &ret->package.elements[i];
union acpi_object *id;
if (pack->type != ACPI_TYPE_PACKAGE)
continue;
if (!pack->package.count)
continue;
id = &pack->package.elements[0];
if (id->integer.value == data->debugfs.id) {
/* Print the package */
buf = kzalloc(512, GFP_KERNEL);
if (!buf) {
ACPI_FREE(ret);
return -ENOMEM;
}
atk_pack_print(buf, 512, pack);
break;
}
}
ACPI_FREE(ret);
if (!buf)
return -EINVAL;
file->private_data = buf;
return nonseekable_open(inode, file);
}
static ssize_t atk_debugfs_ggrp_read(struct file *file, char __user *buf,
size_t count, loff_t *pos)
{
char *str = file->private_data;
size_t len = strlen(str);
return simple_read_from_buffer(buf, count, pos, str, len);
}
static int atk_debugfs_ggrp_release(struct inode *inode, struct file *file)
{
kfree(file->private_data);
return 0;
}
static const struct file_operations atk_debugfs_ggrp_fops = {
.read = atk_debugfs_ggrp_read,
.open = atk_debugfs_ggrp_open,
.release = atk_debugfs_ggrp_release,
.llseek = no_llseek,
};
static void atk_debugfs_init(struct atk_data *data)
{
struct dentry *d;
data->debugfs.id = 0;
d = debugfs_create_dir("asus_atk0110", NULL);
debugfs_create_x32("id", 0600, d, &data->debugfs.id);
debugfs_create_file_unsafe("gitm", 0400, d, data, &atk_debugfs_gitm);
debugfs_create_file("ggrp", 0400, d, data, &atk_debugfs_ggrp_fops);
data->debugfs.root = d;
}
static void atk_debugfs_cleanup(struct atk_data *data)
{
debugfs_remove_recursive(data->debugfs.root);
}
#else /* CONFIG_DEBUG_FS */
static void atk_debugfs_init(struct atk_data *data)
{
}
static void atk_debugfs_cleanup(struct atk_data *data)
{
}
#endif
static int atk_add_sensor(struct atk_data *data, union acpi_object *obj)
{
struct device *dev = &data->acpi_dev->dev;
union acpi_object *flags;
union acpi_object *name;
union acpi_object *limit1;
union acpi_object *limit2;
union acpi_object *enable;
struct atk_sensor_data *sensor;
char const *base_name;
char const *limit1_name;
char const *limit2_name;
u64 type;
int err;
int *num;
int start;
if (obj->type != ACPI_TYPE_PACKAGE) {
/* wft is this? */
dev_warn(dev, "Unknown type for ACPI object: (%d)\n",
obj->type);
return -EINVAL;
}
err = validate_hwmon_pack(data, obj);
if (err)
return err;
/* Ok, we have a valid hwmon package */
type = atk_get_pack_member(data, obj, HWMON_PACK_FLAGS)->integer.value
& ATK_TYPE_MASK;
switch (type) {
case HWMON_TYPE_VOLT:
base_name = "in";
limit1_name = "min";
limit2_name = "max";
num = &data->voltage_count;
start = 0;
break;
case HWMON_TYPE_TEMP:
base_name = "temp";
limit1_name = "max";
limit2_name = "crit";
num = &data->temperature_count;
start = 1;
break;
case HWMON_TYPE_FAN:
base_name = "fan";
limit1_name = "min";
limit2_name = "max";
num = &data->fan_count;
start = 1;
break;
default:
dev_warn(dev, "Unknown sensor type: %#llx\n", type);
return -EINVAL;
}
enable = atk_get_pack_member(data, obj, HWMON_PACK_ENABLE);
if (!enable->integer.value)
/* sensor is disabled */
return 0;
flags = atk_get_pack_member(data, obj, HWMON_PACK_FLAGS);
name = atk_get_pack_member(data, obj, HWMON_PACK_NAME);
limit1 = atk_get_pack_member(data, obj, HWMON_PACK_LIMIT1);
limit2 = atk_get_pack_member(data, obj, HWMON_PACK_LIMIT2);
sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
if (!sensor)
return -ENOMEM;
sensor->acpi_name = devm_kstrdup(dev, name->string.pointer, GFP_KERNEL);
if (!sensor->acpi_name)
return -ENOMEM;
INIT_LIST_HEAD(&sensor->list);
sensor->type = type;
sensor->data = data;
sensor->id = flags->integer.value;
sensor->limit1 = limit1->integer.value;
if (data->old_interface)
sensor->limit2 = limit2->integer.value;
else
/* The upper limit is expressed as delta from lower limit */
sensor->limit2 = sensor->limit1 + limit2->integer.value;
snprintf(sensor->input_attr_name, ATTR_NAME_SIZE,
"%s%d_input", base_name, start + *num);
atk_init_attribute(&sensor->input_attr,
sensor->input_attr_name,
atk_input_show);
snprintf(sensor->label_attr_name, ATTR_NAME_SIZE,
"%s%d_label", base_name, start + *num);
atk_init_attribute(&sensor->label_attr,
sensor->label_attr_name,
atk_label_show);
snprintf(sensor->limit1_attr_name, ATTR_NAME_SIZE,
"%s%d_%s", base_name, start + *num, limit1_name);
atk_init_attribute(&sensor->limit1_attr,
sensor->limit1_attr_name,
atk_limit1_show);
snprintf(sensor->limit2_attr_name, ATTR_NAME_SIZE,
"%s%d_%s", base_name, start + *num, limit2_name);
atk_init_attribute(&sensor->limit2_attr,
sensor->limit2_attr_name,
atk_limit2_show);
list_add(&sensor->list, &data->sensor_list);
(*num)++;
return 1;
}
static int atk_enumerate_old_hwmon(struct atk_data *data)
{
struct device *dev = &data->acpi_dev->dev;
struct acpi_buffer buf;
union acpi_object *pack;
acpi_status status;
int i, ret;
int count = 0;
/* Voltages */
buf.length = ACPI_ALLOCATE_BUFFER;
status = acpi_evaluate_object_typed(data->atk_handle,
METHOD_OLD_ENUM_VLT, NULL, &buf, ACPI_TYPE_PACKAGE);
if (status != AE_OK) {
dev_warn(dev, METHOD_OLD_ENUM_VLT ": ACPI exception: %s\n",
acpi_format_exception(status));
return -ENODEV;
}
pack = buf.pointer;
for (i = 1; i < pack->package.count; i++) {
union acpi_object *obj = &pack->package.elements[i];
ret = atk_add_sensor(data, obj);
if (ret > 0)
count++;
}
ACPI_FREE(buf.pointer);
/* Temperatures */
buf.length = ACPI_ALLOCATE_BUFFER;
status = acpi_evaluate_object_typed(data->atk_handle,
METHOD_OLD_ENUM_TMP, NULL, &buf, ACPI_TYPE_PACKAGE);
if (status != AE_OK) {
dev_warn(dev, METHOD_OLD_ENUM_TMP ": ACPI exception: %s\n",
acpi_format_exception(status));
return -ENODEV;
}
pack = buf.pointer;
for (i = 1; i < pack->package.count; i++) {
union acpi_object *obj = &pack->package.elements[i];
ret = atk_add_sensor(data, obj);
if (ret > 0)
count++;
}
ACPI_FREE(buf.pointer);
/* Fans */
buf.length = ACPI_ALLOCATE_BUFFER;
status = acpi_evaluate_object_typed(data->atk_handle,
METHOD_OLD_ENUM_FAN, NULL, &buf, ACPI_TYPE_PACKAGE);
if (status != AE_OK) {
dev_warn(dev, METHOD_OLD_ENUM_FAN ": ACPI exception: %s\n",
acpi_format_exception(status));
return -ENODEV;
}
pack = buf.pointer;
for (i = 1; i < pack->package.count; i++) {
union acpi_object *obj = &pack->package.elements[i];
ret = atk_add_sensor(data, obj);
if (ret > 0)
count++;
}
ACPI_FREE(buf.pointer);
return count;
}
static int atk_ec_present(struct atk_data *data)
{
struct device *dev = &data->acpi_dev->dev;
union acpi_object *pack;
union acpi_object *ec;
int ret;
int i;
pack = atk_ggrp(data, ATK_MUX_MGMT);
if (IS_ERR(pack)) {
if (PTR_ERR(pack) == -ENOENT) {
/* The MGMT class does not exists - that's ok */
dev_dbg(dev, "Class %#llx not found\n", ATK_MUX_MGMT);
return 0;
}
return PTR_ERR(pack);
}
/* Search the EC */
ec = NULL;
for (i = 0; i < pack->package.count; i++) {
union acpi_object *obj = &pack->package.elements[i];
union acpi_object *id;
if (obj->type != ACPI_TYPE_PACKAGE)
continue;
id = &obj->package.elements[0];
if (id->type != ACPI_TYPE_INTEGER)
continue;
if (id->integer.value == ATK_EC_ID) {
ec = obj;
break;
}
}
ret = (ec != NULL);
if (!ret)
/* The system has no EC */
dev_dbg(dev, "EC not found\n");
ACPI_FREE(pack);
return ret;
}
static int atk_ec_enabled(struct atk_data *data)
{
struct device *dev = &data->acpi_dev->dev;
union acpi_object *obj;
struct atk_acpi_ret_buffer *buf;
int err;
obj = atk_gitm(data, ATK_EC_ID);
if (IS_ERR(obj)) {
dev_err(dev, "Unable to query EC status\n");
return PTR_ERR(obj);
}
buf = (struct atk_acpi_ret_buffer *)obj->buffer.pointer;
if (buf->flags == 0) {
dev_err(dev, "Unable to query EC status\n");
err = -EIO;
} else {
err = (buf->value != 0);
dev_dbg(dev, "EC is %sabled\n",
err ? "en" : "dis");
}
ACPI_FREE(obj);
return err;
}
static int atk_ec_ctl(struct atk_data *data, int enable)
{
struct device *dev = &data->acpi_dev->dev;
union acpi_object *obj;
struct atk_acpi_input_buf sitm;
struct atk_acpi_ret_buffer *ec_ret;
int err = 0;
sitm.id = ATK_EC_ID;
sitm.param1 = enable;
sitm.param2 = 0;
obj = atk_sitm(data, &sitm);
if (IS_ERR(obj)) {
dev_err(dev, "Failed to %sable the EC\n",
enable ? "en" : "dis");
return PTR_ERR(obj);
}
ec_ret = (struct atk_acpi_ret_buffer *)obj->buffer.pointer;
if (ec_ret->flags == 0) {
dev_err(dev, "Failed to %sable the EC\n",
enable ? "en" : "dis");
err = -EIO;
} else {
dev_info(dev, "EC %sabled\n",
enable ? "en" : "dis");
}
ACPI_FREE(obj);
return err;
}
static int atk_enumerate_new_hwmon(struct atk_data *data)
{
struct device *dev = &data->acpi_dev->dev;
union acpi_object *pack;
int err;
int i;
err = atk_ec_present(data);
if (err < 0)
return err;
if (err) {
err = atk_ec_enabled(data);
if (err < 0)
return err;
/* If the EC was disabled we will disable it again on unload */
data->disable_ec = err;
err = atk_ec_ctl(data, 1);
if (err) {
data->disable_ec = false;
return err;
}
}
dev_dbg(dev, "Enumerating hwmon sensors\n");
pack = atk_ggrp(data, ATK_MUX_HWMON);
if (IS_ERR(pack))
return PTR_ERR(pack);
for (i = 0; i < pack->package.count; i++) {
union acpi_object *obj = &pack->package.elements[i];
atk_add_sensor(data, obj);
}
err = data->voltage_count + data->temperature_count + data->fan_count;
ACPI_FREE(pack);
return err;
}
static int atk_init_attribute_groups(struct atk_data *data)
{
struct device *dev = &data->acpi_dev->dev;
struct atk_sensor_data *s;
struct attribute **attrs;
int i = 0;
int len = (data->voltage_count + data->temperature_count
+ data->fan_count) * 4 + 1;
attrs = devm_kcalloc(dev, len, sizeof(struct attribute *), GFP_KERNEL);
if (!attrs)
return -ENOMEM;
list_for_each_entry(s, &data->sensor_list, list) {
attrs[i++] = &s->input_attr.attr;
attrs[i++] = &s->label_attr.attr;
attrs[i++] = &s->limit1_attr.attr;
attrs[i++] = &s->limit2_attr.attr;
}
data->attr_group.attrs = attrs;
data->attr_groups[0] = &data->attr_group;
return 0;
}
static int atk_register_hwmon(struct atk_data *data)
{
struct device *dev = &data->acpi_dev->dev;
dev_dbg(dev, "registering hwmon device\n");
data->hwmon_dev = hwmon_device_register_with_groups(dev, "atk0110",
data,
data->attr_groups);
return PTR_ERR_OR_ZERO(data->hwmon_dev);
}
static int atk_probe_if(struct atk_data *data)
{
struct device *dev = &data->acpi_dev->dev;
acpi_handle ret;
acpi_status status;
int err = 0;
/* RTMP: read temperature */
status = acpi_get_handle(data->atk_handle, METHOD_OLD_READ_TMP, &ret);
if (ACPI_SUCCESS(status))
data->rtmp_handle = ret;
else
dev_dbg(dev, "method " METHOD_OLD_READ_TMP " not found: %s\n",
acpi_format_exception(status));
/* RVLT: read voltage */
status = acpi_get_handle(data->atk_handle, METHOD_OLD_READ_VLT, &ret);
if (ACPI_SUCCESS(status))
data->rvlt_handle = ret;
else
dev_dbg(dev, "method " METHOD_OLD_READ_VLT " not found: %s\n",
acpi_format_exception(status));
/* RFAN: read fan status */
status = acpi_get_handle(data->atk_handle, METHOD_OLD_READ_FAN, &ret);
if (ACPI_SUCCESS(status))
data->rfan_handle = ret;
else
dev_dbg(dev, "method " METHOD_OLD_READ_FAN " not found: %s\n",
acpi_format_exception(status));
/* Enumeration */
status = acpi_get_handle(data->atk_handle, METHOD_ENUMERATE, &ret);
if (ACPI_SUCCESS(status))
data->enumerate_handle = ret;
else
dev_dbg(dev, "method " METHOD_ENUMERATE " not found: %s\n",
acpi_format_exception(status));
/* De-multiplexer (read) */
status = acpi_get_handle(data->atk_handle, METHOD_READ, &ret);
if (ACPI_SUCCESS(status))
data->read_handle = ret;
else
dev_dbg(dev, "method " METHOD_READ " not found: %s\n",
acpi_format_exception(status));
/* De-multiplexer (write) */
status = acpi_get_handle(data->atk_handle, METHOD_WRITE, &ret);
if (ACPI_SUCCESS(status))
data->write_handle = ret;
else
dev_dbg(dev, "method " METHOD_WRITE " not found: %s\n",
acpi_format_exception(status));
/*
* Check for hwmon methods: first check "old" style methods; note that
* both may be present: in this case we stick to the old interface;
* analysis of multiple DSDTs indicates that when both interfaces
* are present the new one (GGRP/GITM) is not functional.
*/
if (new_if)
dev_info(dev, "Overriding interface detection\n");
if (data->rtmp_handle &&
data->rvlt_handle && data->rfan_handle && !new_if)
data->old_interface = true;
else if (data->enumerate_handle && data->read_handle &&
data->write_handle)
data->old_interface = false;
else
err = -ENODEV;
return err;
}
static int atk_add(struct acpi_device *device)
{
acpi_status ret;
int err;
struct acpi_buffer buf;
union acpi_object *obj;
struct atk_data *data;
dev_dbg(&device->dev, "adding...\n");
data = devm_kzalloc(&device->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->acpi_dev = device;
data->atk_handle = device->handle;
INIT_LIST_HEAD(&data->sensor_list);
data->disable_ec = false;
buf.length = ACPI_ALLOCATE_BUFFER;
ret = acpi_evaluate_object_typed(data->atk_handle, BOARD_ID, NULL,
&buf, ACPI_TYPE_PACKAGE);
if (ret != AE_OK) {
dev_dbg(&device->dev, "atk: method MBIF not found\n");
} else {
obj = buf.pointer;
if (obj->package.count >= 2) {
union acpi_object *id = &obj->package.elements[1];
if (id->type == ACPI_TYPE_STRING)
dev_dbg(&device->dev, "board ID = %s\n",
id->string.pointer);
}
ACPI_FREE(buf.pointer);
}
err = atk_probe_if(data);
if (err) {
dev_err(&device->dev, "No usable hwmon interface detected\n");
goto out;
}
if (data->old_interface) {
dev_dbg(&device->dev, "Using old hwmon interface\n");
err = atk_enumerate_old_hwmon(data);
} else {
dev_dbg(&device->dev, "Using new hwmon interface\n");
err = atk_enumerate_new_hwmon(data);
}
if (err < 0)
goto out;
if (err == 0) {
dev_info(&device->dev,
"No usable sensor detected, bailing out\n");
err = -ENODEV;
goto out;
}
err = atk_init_attribute_groups(data);
if (err)
goto out;
err = atk_register_hwmon(data);
if (err)
goto out;
atk_debugfs_init(data);
device->driver_data = data;
return 0;
out:
if (data->disable_ec)
atk_ec_ctl(data, 0);
return err;
}
static void atk_remove(struct acpi_device *device)
{
struct atk_data *data = device->driver_data;
dev_dbg(&device->dev, "removing...\n");
device->driver_data = NULL;
atk_debugfs_cleanup(data);
hwmon_device_unregister(data->hwmon_dev);
if (data->disable_ec) {
if (atk_ec_ctl(data, 0))
dev_err(&device->dev, "Failed to disable EC\n");
}
}
static int __init atk0110_init(void)
{
int ret;
/* Make sure it's safe to access the device through ACPI */
if (!acpi_resources_are_enforced()) {
pr_err("Resources not safely usable due to acpi_enforce_resources kernel parameter\n");
return -EBUSY;
}
if (dmi_check_system(atk_force_new_if))
new_if = true;
ret = acpi_bus_register_driver(&atk_driver);
if (ret)
pr_info("acpi_bus_register_driver failed: %d\n", ret);
return ret;
}
static void __exit atk0110_exit(void)
{
acpi_bus_unregister_driver(&atk_driver);
}
module_init(atk0110_init);
module_exit(atk0110_exit);
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/asus_atk0110.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/* Sparx5 SoC temperature sensor driver
*
* Copyright (C) 2020 Lars Povlsen <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/hwmon.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#define TEMP_CTRL 0
#define TEMP_CFG 4
#define TEMP_CFG_CYCLES GENMASK(24, 15)
#define TEMP_CFG_ENA BIT(0)
#define TEMP_STAT 8
#define TEMP_STAT_VALID BIT(12)
#define TEMP_STAT_TEMP GENMASK(11, 0)
struct s5_hwmon {
void __iomem *base;
struct clk *clk;
};
static void s5_temp_enable(struct s5_hwmon *hwmon)
{
u32 val = readl(hwmon->base + TEMP_CFG);
u32 clk = clk_get_rate(hwmon->clk) / USEC_PER_SEC;
val &= ~TEMP_CFG_CYCLES;
val |= FIELD_PREP(TEMP_CFG_CYCLES, clk);
val |= TEMP_CFG_ENA;
writel(val, hwmon->base + TEMP_CFG);
}
static int s5_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *temp)
{
struct s5_hwmon *hwmon = dev_get_drvdata(dev);
int rc = 0, value;
u32 stat;
switch (attr) {
case hwmon_temp_input:
stat = readl_relaxed(hwmon->base + TEMP_STAT);
if (!(stat & TEMP_STAT_VALID))
return -EAGAIN;
value = stat & TEMP_STAT_TEMP;
/*
* From register documentation:
* Temp(C) = TEMP_SENSOR_STAT.TEMP / 4096 * 352.2 - 109.4
*/
value = DIV_ROUND_CLOSEST(value * 3522, 4096) - 1094;
/*
* Scale down by 10 from above and multiply by 1000 to
* have millidegrees as specified by the hwmon sysfs
* interface.
*/
value *= 100;
*temp = value;
break;
default:
rc = -EOPNOTSUPP;
break;
}
return rc;
}
static umode_t s5_is_visible(const void *_data, enum hwmon_sensor_types type,
u32 attr, int channel)
{
if (type != hwmon_temp)
return 0;
switch (attr) {
case hwmon_temp_input:
return 0444;
default:
return 0;
}
}
static const struct hwmon_channel_info * const s5_info[] = {
HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
NULL
};
static const struct hwmon_ops s5_hwmon_ops = {
.is_visible = s5_is_visible,
.read = s5_read,
};
static const struct hwmon_chip_info s5_chip_info = {
.ops = &s5_hwmon_ops,
.info = s5_info,
};
static int s5_temp_probe(struct platform_device *pdev)
{
struct device *hwmon_dev;
struct s5_hwmon *hwmon;
hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
if (!hwmon)
return -ENOMEM;
hwmon->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(hwmon->base))
return PTR_ERR(hwmon->base);
hwmon->clk = devm_clk_get_enabled(&pdev->dev, NULL);
if (IS_ERR(hwmon->clk))
return PTR_ERR(hwmon->clk);
s5_temp_enable(hwmon);
hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
"s5_temp",
hwmon,
&s5_chip_info,
NULL);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct of_device_id s5_temp_match[] = {
{ .compatible = "microchip,sparx5-temp" },
{},
};
MODULE_DEVICE_TABLE(of, s5_temp_match);
static struct platform_driver s5_temp_driver = {
.probe = s5_temp_probe,
.driver = {
.name = "sparx5-temp",
.of_match_table = s5_temp_match,
},
};
module_platform_driver(s5_temp_driver);
MODULE_AUTHOR("Lars Povlsen <[email protected]>");
MODULE_DESCRIPTION("Sparx5 SoC temperature sensor driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/sparx5-temp.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* sbtsi_temp.c - hwmon driver for a SBI Temperature Sensor Interface (SB-TSI)
* compliant AMD SoC temperature device.
*
* Copyright (c) 2020, Google Inc.
* Copyright (c) 2020, Kun Yi <[email protected]>
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/hwmon.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
/*
* SB-TSI registers only support SMBus byte data access. "_INT" registers are
* the integer part of a temperature value or limit, and "_DEC" registers are
* corresponding decimal parts.
*/
#define SBTSI_REG_TEMP_INT 0x01 /* RO */
#define SBTSI_REG_STATUS 0x02 /* RO */
#define SBTSI_REG_CONFIG 0x03 /* RO */
#define SBTSI_REG_TEMP_HIGH_INT 0x07 /* RW */
#define SBTSI_REG_TEMP_LOW_INT 0x08 /* RW */
#define SBTSI_REG_TEMP_DEC 0x10 /* RW */
#define SBTSI_REG_TEMP_HIGH_DEC 0x13 /* RW */
#define SBTSI_REG_TEMP_LOW_DEC 0x14 /* RW */
#define SBTSI_CONFIG_READ_ORDER_SHIFT 5
#define SBTSI_TEMP_MIN 0
#define SBTSI_TEMP_MAX 255875
/* Each client has this additional data */
struct sbtsi_data {
struct i2c_client *client;
struct mutex lock;
};
/*
* From SB-TSI spec: CPU temperature readings and limit registers encode the
* temperature in increments of 0.125 from 0 to 255.875. The "high byte"
* register encodes the base-2 of the integer portion, and the upper 3 bits of
* the "low byte" encode in base-2 the decimal portion.
*
* e.g. INT=0x19, DEC=0x20 represents 25.125 degrees Celsius
*
* Therefore temperature in millidegree Celsius =
* (INT + DEC / 256) * 1000 = (INT * 8 + DEC / 32) * 125
*/
static inline int sbtsi_reg_to_mc(s32 integer, s32 decimal)
{
return ((integer << 3) + (decimal >> 5)) * 125;
}
/*
* Inversely, given temperature in millidegree Celsius
* INT = (TEMP / 125) / 8
* DEC = ((TEMP / 125) % 8) * 32
* Caller have to make sure temp doesn't exceed 255875, the max valid value.
*/
static inline void sbtsi_mc_to_reg(s32 temp, u8 *integer, u8 *decimal)
{
temp /= 125;
*integer = temp >> 3;
*decimal = (temp & 0x7) << 5;
}
static int sbtsi_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct sbtsi_data *data = dev_get_drvdata(dev);
s32 temp_int, temp_dec;
int err;
switch (attr) {
case hwmon_temp_input:
/*
* ReadOrder bit specifies the reading order of integer and
* decimal part of CPU temp for atomic reads. If bit == 0,
* reading integer part triggers latching of the decimal part,
* so integer part should be read first. If bit == 1, read
* order should be reversed.
*/
err = i2c_smbus_read_byte_data(data->client, SBTSI_REG_CONFIG);
if (err < 0)
return err;
mutex_lock(&data->lock);
if (err & BIT(SBTSI_CONFIG_READ_ORDER_SHIFT)) {
temp_dec = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_DEC);
temp_int = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_INT);
} else {
temp_int = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_INT);
temp_dec = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_DEC);
}
mutex_unlock(&data->lock);
break;
case hwmon_temp_max:
mutex_lock(&data->lock);
temp_int = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_HIGH_INT);
temp_dec = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_HIGH_DEC);
mutex_unlock(&data->lock);
break;
case hwmon_temp_min:
mutex_lock(&data->lock);
temp_int = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_LOW_INT);
temp_dec = i2c_smbus_read_byte_data(data->client, SBTSI_REG_TEMP_LOW_DEC);
mutex_unlock(&data->lock);
break;
default:
return -EINVAL;
}
if (temp_int < 0)
return temp_int;
if (temp_dec < 0)
return temp_dec;
*val = sbtsi_reg_to_mc(temp_int, temp_dec);
return 0;
}
static int sbtsi_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
struct sbtsi_data *data = dev_get_drvdata(dev);
int reg_int, reg_dec, err;
u8 temp_int, temp_dec;
switch (attr) {
case hwmon_temp_max:
reg_int = SBTSI_REG_TEMP_HIGH_INT;
reg_dec = SBTSI_REG_TEMP_HIGH_DEC;
break;
case hwmon_temp_min:
reg_int = SBTSI_REG_TEMP_LOW_INT;
reg_dec = SBTSI_REG_TEMP_LOW_DEC;
break;
default:
return -EINVAL;
}
val = clamp_val(val, SBTSI_TEMP_MIN, SBTSI_TEMP_MAX);
sbtsi_mc_to_reg(val, &temp_int, &temp_dec);
mutex_lock(&data->lock);
err = i2c_smbus_write_byte_data(data->client, reg_int, temp_int);
if (err)
goto exit;
err = i2c_smbus_write_byte_data(data->client, reg_dec, temp_dec);
exit:
mutex_unlock(&data->lock);
return err;
}
static umode_t sbtsi_is_visible(const void *data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
switch (type) {
case hwmon_temp:
switch (attr) {
case hwmon_temp_input:
return 0444;
case hwmon_temp_min:
return 0644;
case hwmon_temp_max:
return 0644;
}
break;
default:
break;
}
return 0;
}
static const struct hwmon_channel_info * const sbtsi_info[] = {
HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX),
NULL
};
static const struct hwmon_ops sbtsi_hwmon_ops = {
.is_visible = sbtsi_is_visible,
.read = sbtsi_read,
.write = sbtsi_write,
};
static const struct hwmon_chip_info sbtsi_chip_info = {
.ops = &sbtsi_hwmon_ops,
.info = sbtsi_info,
};
static int sbtsi_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct device *hwmon_dev;
struct sbtsi_data *data;
data = devm_kzalloc(dev, sizeof(struct sbtsi_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
mutex_init(&data->lock);
hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, data, &sbtsi_chip_info,
NULL);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static const struct i2c_device_id sbtsi_id[] = {
{"sbtsi", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, sbtsi_id);
static const struct of_device_id __maybe_unused sbtsi_of_match[] = {
{
.compatible = "amd,sbtsi",
},
{ },
};
MODULE_DEVICE_TABLE(of, sbtsi_of_match);
static struct i2c_driver sbtsi_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "sbtsi",
.of_match_table = of_match_ptr(sbtsi_of_match),
},
.probe = sbtsi_probe,
.id_table = sbtsi_id,
};
module_i2c_driver(sbtsi_driver);
MODULE_AUTHOR("Kun Yi <[email protected]>");
MODULE_DESCRIPTION("Hwmon driver for AMD SB-TSI emulated sensor");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/sbtsi_temp.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* HWMON Driver for Dialog DA9055
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <[email protected]>
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/completion.h>
#include <linux/mfd/da9055/core.h>
#include <linux/mfd/da9055/reg.h>
#define DA9055_ADCIN_DIV 102
#define DA9055_VSYS_DIV 85
#define DA9055_ADC_VSYS 0
#define DA9055_ADC_ADCIN1 1
#define DA9055_ADC_ADCIN2 2
#define DA9055_ADC_ADCIN3 3
#define DA9055_ADC_TJUNC 4
struct da9055_hwmon {
struct da9055 *da9055;
struct mutex hwmon_lock;
struct mutex irq_lock;
struct completion done;
};
static const char * const input_names[] = {
[DA9055_ADC_VSYS] = "VSYS",
[DA9055_ADC_ADCIN1] = "ADC IN1",
[DA9055_ADC_ADCIN2] = "ADC IN2",
[DA9055_ADC_ADCIN3] = "ADC IN3",
[DA9055_ADC_TJUNC] = "CHIP TEMP",
};
static const u8 chan_mux[DA9055_ADC_TJUNC + 1] = {
[DA9055_ADC_VSYS] = DA9055_ADC_MUX_VSYS,
[DA9055_ADC_ADCIN1] = DA9055_ADC_MUX_ADCIN1,
[DA9055_ADC_ADCIN2] = DA9055_ADC_MUX_ADCIN2,
[DA9055_ADC_ADCIN3] = DA9055_ADC_MUX_ADCIN3,
[DA9055_ADC_TJUNC] = DA9055_ADC_MUX_T_SENSE,
};
static int da9055_adc_manual_read(struct da9055_hwmon *hwmon,
unsigned char channel)
{
int ret;
unsigned short calc_data;
unsigned short data;
unsigned char mux_sel;
struct da9055 *da9055 = hwmon->da9055;
if (channel > DA9055_ADC_TJUNC)
return -EINVAL;
mutex_lock(&hwmon->irq_lock);
/* Selects desired MUX for manual conversion */
mux_sel = chan_mux[channel] | DA9055_ADC_MAN_CONV;
ret = da9055_reg_write(da9055, DA9055_REG_ADC_MAN, mux_sel);
if (ret < 0)
goto err;
/* Wait for an interrupt */
if (!wait_for_completion_timeout(&hwmon->done,
msecs_to_jiffies(500))) {
dev_err(da9055->dev,
"timeout waiting for ADC conversion interrupt\n");
ret = -ETIMEDOUT;
goto err;
}
ret = da9055_reg_read(da9055, DA9055_REG_ADC_RES_H);
if (ret < 0)
goto err;
calc_data = (unsigned short)ret;
data = calc_data << 2;
ret = da9055_reg_read(da9055, DA9055_REG_ADC_RES_L);
if (ret < 0)
goto err;
calc_data = (unsigned short)(ret & DA9055_ADC_LSB_MASK);
data |= calc_data;
ret = data;
err:
mutex_unlock(&hwmon->irq_lock);
return ret;
}
static irqreturn_t da9055_auxadc_irq(int irq, void *irq_data)
{
struct da9055_hwmon *hwmon = irq_data;
complete(&hwmon->done);
return IRQ_HANDLED;
}
/* Conversion function for VSYS and ADCINx */
static inline int volt_reg_to_mv(int value, int channel)
{
if (channel == DA9055_ADC_VSYS)
return DIV_ROUND_CLOSEST(value * 1000, DA9055_VSYS_DIV) + 2500;
else
return DIV_ROUND_CLOSEST(value * 1000, DA9055_ADCIN_DIV);
}
static int da9055_enable_auto_mode(struct da9055 *da9055, int channel)
{
return da9055_reg_update(da9055, DA9055_REG_ADC_CONT, 1 << channel,
1 << channel);
}
static int da9055_disable_auto_mode(struct da9055 *da9055, int channel)
{
return da9055_reg_update(da9055, DA9055_REG_ADC_CONT, 1 << channel, 0);
}
static ssize_t da9055_auto_ch_show(struct device *dev,
struct device_attribute *devattr,
char *buf)
{
struct da9055_hwmon *hwmon = dev_get_drvdata(dev);
int ret, adc;
int channel = to_sensor_dev_attr(devattr)->index;
mutex_lock(&hwmon->hwmon_lock);
ret = da9055_enable_auto_mode(hwmon->da9055, channel);
if (ret < 0)
goto hwmon_err;
usleep_range(10000, 10500);
adc = da9055_reg_read(hwmon->da9055, DA9055_REG_VSYS_RES + channel);
if (adc < 0) {
ret = adc;
goto hwmon_err_release;
}
ret = da9055_disable_auto_mode(hwmon->da9055, channel);
if (ret < 0)
goto hwmon_err;
mutex_unlock(&hwmon->hwmon_lock);
return sprintf(buf, "%d\n", volt_reg_to_mv(adc, channel));
hwmon_err_release:
da9055_disable_auto_mode(hwmon->da9055, channel);
hwmon_err:
mutex_unlock(&hwmon->hwmon_lock);
return ret;
}
static ssize_t da9055_tjunc_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct da9055_hwmon *hwmon = dev_get_drvdata(dev);
int tjunc;
int toffset;
tjunc = da9055_adc_manual_read(hwmon, DA9055_ADC_TJUNC);
if (tjunc < 0)
return tjunc;
toffset = da9055_reg_read(hwmon->da9055, DA9055_REG_T_OFFSET);
if (toffset < 0)
return toffset;
/*
* Degrees celsius = -0.4084 * (ADC_RES - T_OFFSET) + 307.6332
* T_OFFSET is a trim value used to improve accuracy of the result
*/
return sprintf(buf, "%d\n", DIV_ROUND_CLOSEST(-4084 * (tjunc - toffset)
+ 3076332, 10000));
}
static ssize_t label_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
return sprintf(buf, "%s\n",
input_names[to_sensor_dev_attr(devattr)->index]);
}
static SENSOR_DEVICE_ATTR_RO(in0_input, da9055_auto_ch, DA9055_ADC_VSYS);
static SENSOR_DEVICE_ATTR_RO(in0_label, label, DA9055_ADC_VSYS);
static SENSOR_DEVICE_ATTR_RO(in1_input, da9055_auto_ch, DA9055_ADC_ADCIN1);
static SENSOR_DEVICE_ATTR_RO(in1_label, label, DA9055_ADC_ADCIN1);
static SENSOR_DEVICE_ATTR_RO(in2_input, da9055_auto_ch, DA9055_ADC_ADCIN2);
static SENSOR_DEVICE_ATTR_RO(in2_label, label, DA9055_ADC_ADCIN2);
static SENSOR_DEVICE_ATTR_RO(in3_input, da9055_auto_ch, DA9055_ADC_ADCIN3);
static SENSOR_DEVICE_ATTR_RO(in3_label, label, DA9055_ADC_ADCIN3);
static SENSOR_DEVICE_ATTR_RO(temp1_input, da9055_tjunc, DA9055_ADC_TJUNC);
static SENSOR_DEVICE_ATTR_RO(temp1_label, label, DA9055_ADC_TJUNC);
static struct attribute *da9055_attrs[] = {
&sensor_dev_attr_in0_input.dev_attr.attr,
&sensor_dev_attr_in0_label.dev_attr.attr,
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in1_label.dev_attr.attr,
&sensor_dev_attr_in2_input.dev_attr.attr,
&sensor_dev_attr_in2_label.dev_attr.attr,
&sensor_dev_attr_in3_input.dev_attr.attr,
&sensor_dev_attr_in3_label.dev_attr.attr,
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_label.dev_attr.attr,
NULL
};
ATTRIBUTE_GROUPS(da9055);
static int da9055_hwmon_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct da9055_hwmon *hwmon;
struct device *hwmon_dev;
int hwmon_irq, ret;
hwmon = devm_kzalloc(dev, sizeof(struct da9055_hwmon), GFP_KERNEL);
if (!hwmon)
return -ENOMEM;
mutex_init(&hwmon->hwmon_lock);
mutex_init(&hwmon->irq_lock);
init_completion(&hwmon->done);
hwmon->da9055 = dev_get_drvdata(pdev->dev.parent);
hwmon_irq = platform_get_irq_byname(pdev, "HWMON");
if (hwmon_irq < 0)
return hwmon_irq;
ret = devm_request_threaded_irq(&pdev->dev, hwmon_irq,
NULL, da9055_auxadc_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
"adc-irq", hwmon);
if (ret != 0) {
dev_err(hwmon->da9055->dev, "DA9055 ADC IRQ failed ret=%d\n",
ret);
return ret;
}
hwmon_dev = devm_hwmon_device_register_with_groups(dev, "da9055",
hwmon,
da9055_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}
static struct platform_driver da9055_hwmon_driver = {
.probe = da9055_hwmon_probe,
.driver = {
.name = "da9055-hwmon",
},
};
module_platform_driver(da9055_hwmon_driver);
MODULE_AUTHOR("David Dajun Chen <[email protected]>");
MODULE_DESCRIPTION("DA9055 HWMON driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:da9055-hwmon");
|
linux-master
|
drivers/hwmon/da9055-hwmon.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* f75375s.c - driver for the Fintek F75375/SP, F75373 and
* F75387SG/RG hardware monitoring features
* Copyright (C) 2006-2007 Riku Voipio
*
* Datasheets available at:
*
* f75375:
* http://www.fintek.com.tw/files/productfiles/F75375_V026P.pdf
*
* f75373:
* http://www.fintek.com.tw/files/productfiles/F75373_V025P.pdf
*
* f75387:
* http://www.fintek.com.tw/files/productfiles/F75387_V027P.pdf
*/
#include <linux/module.h>
#include <linux/jiffies.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/f75375s.h>
#include <linux/slab.h>
/* Addresses to scan */
static const unsigned short normal_i2c[] = { 0x2d, 0x2e, I2C_CLIENT_END };
enum chips { f75373, f75375, f75387 };
/* Fintek F75375 registers */
#define F75375_REG_CONFIG0 0x0
#define F75375_REG_CONFIG1 0x1
#define F75375_REG_CONFIG2 0x2
#define F75375_REG_CONFIG3 0x3
#define F75375_REG_ADDR 0x4
#define F75375_REG_INTR 0x31
#define F75375_CHIP_ID 0x5A
#define F75375_REG_VERSION 0x5C
#define F75375_REG_VENDOR 0x5D
#define F75375_REG_FAN_TIMER 0x60
#define F75375_REG_VOLT(nr) (0x10 + (nr))
#define F75375_REG_VOLT_HIGH(nr) (0x20 + (nr) * 2)
#define F75375_REG_VOLT_LOW(nr) (0x21 + (nr) * 2)
#define F75375_REG_TEMP(nr) (0x14 + (nr))
#define F75387_REG_TEMP11_LSB(nr) (0x1a + (nr))
#define F75375_REG_TEMP_HIGH(nr) (0x28 + (nr) * 2)
#define F75375_REG_TEMP_HYST(nr) (0x29 + (nr) * 2)
#define F75375_REG_FAN(nr) (0x16 + (nr) * 2)
#define F75375_REG_FAN_MIN(nr) (0x2C + (nr) * 2)
#define F75375_REG_FAN_FULL(nr) (0x70 + (nr) * 0x10)
#define F75375_REG_FAN_PWM_DUTY(nr) (0x76 + (nr) * 0x10)
#define F75375_REG_FAN_PWM_CLOCK(nr) (0x7D + (nr) * 0x10)
#define F75375_REG_FAN_EXP(nr) (0x74 + (nr) * 0x10)
#define F75375_REG_FAN_B_TEMP(nr, step) ((0xA0 + (nr) * 0x10) + (step))
#define F75375_REG_FAN_B_SPEED(nr, step) \
((0xA5 + (nr) * 0x10) + (step) * 2)
#define F75375_REG_PWM1_RAISE_DUTY 0x69
#define F75375_REG_PWM2_RAISE_DUTY 0x6A
#define F75375_REG_PWM1_DROP_DUTY 0x6B
#define F75375_REG_PWM2_DROP_DUTY 0x6C
#define F75375_FAN_CTRL_LINEAR(nr) (4 + nr)
#define F75387_FAN_CTRL_LINEAR(nr) (1 + ((nr) * 4))
#define FAN_CTRL_MODE(nr) (4 + ((nr) * 2))
#define F75387_FAN_DUTY_MODE(nr) (2 + ((nr) * 4))
#define F75387_FAN_MANU_MODE(nr) ((nr) * 4)
/*
* Data structures and manipulation thereof
*/
struct f75375_data {
unsigned short addr;
struct device *hwmon_dev;
const char *name;
int kind;
struct mutex update_lock; /* protect register access */
bool valid;
unsigned long last_updated; /* In jiffies */
unsigned long last_limits; /* In jiffies */
/* Register values */
u8 in[4];
u8 in_max[4];
u8 in_min[4];
u16 fan[2];
u16 fan_min[2];
u16 fan_max[2];
u16 fan_target[2];
u8 fan_timer;
u8 pwm[2];
u8 pwm_mode[2];
u8 pwm_enable[2];
/*
* f75387: For remote temperature reading, it uses signed 11-bit
* values with LSB = 0.125 degree Celsius, left-justified in 16-bit
* registers. For original 8-bit temp readings, the LSB just is 0.
*/
s16 temp11[2];
s8 temp_high[2];
s8 temp_max_hyst[2];
};
static int f75375_detect(struct i2c_client *client,
struct i2c_board_info *info);
static int f75375_probe(struct i2c_client *client);
static void f75375_remove(struct i2c_client *client);
static const struct i2c_device_id f75375_id[] = {
{ "f75373", f75373 },
{ "f75375", f75375 },
{ "f75387", f75387 },
{ }
};
MODULE_DEVICE_TABLE(i2c, f75375_id);
static struct i2c_driver f75375_driver = {
.class = I2C_CLASS_HWMON,
.driver = {
.name = "f75375",
},
.probe = f75375_probe,
.remove = f75375_remove,
.id_table = f75375_id,
.detect = f75375_detect,
.address_list = normal_i2c,
};
static inline int f75375_read8(struct i2c_client *client, u8 reg)
{
return i2c_smbus_read_byte_data(client, reg);
}
/* in most cases, should be called while holding update_lock */
static inline u16 f75375_read16(struct i2c_client *client, u8 reg)
{
return (i2c_smbus_read_byte_data(client, reg) << 8)
| i2c_smbus_read_byte_data(client, reg + 1);
}
static inline void f75375_write8(struct i2c_client *client, u8 reg,
u8 value)
{
i2c_smbus_write_byte_data(client, reg, value);
}
static inline void f75375_write16(struct i2c_client *client, u8 reg,
u16 value)
{
int err = i2c_smbus_write_byte_data(client, reg, (value >> 8));
if (err)
return;
i2c_smbus_write_byte_data(client, reg + 1, (value & 0xFF));
}
static void f75375_write_pwm(struct i2c_client *client, int nr)
{
struct f75375_data *data = i2c_get_clientdata(client);
if (data->kind == f75387)
f75375_write16(client, F75375_REG_FAN_EXP(nr), data->pwm[nr]);
else
f75375_write8(client, F75375_REG_FAN_PWM_DUTY(nr),
data->pwm[nr]);
}
static struct f75375_data *f75375_update_device(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct f75375_data *data = i2c_get_clientdata(client);
int nr;
mutex_lock(&data->update_lock);
/* Limit registers cache is refreshed after 60 seconds */
if (time_after(jiffies, data->last_limits + 60 * HZ)
|| !data->valid) {
for (nr = 0; nr < 2; nr++) {
data->temp_high[nr] =
f75375_read8(client, F75375_REG_TEMP_HIGH(nr));
data->temp_max_hyst[nr] =
f75375_read8(client, F75375_REG_TEMP_HYST(nr));
data->fan_max[nr] =
f75375_read16(client, F75375_REG_FAN_FULL(nr));
data->fan_min[nr] =
f75375_read16(client, F75375_REG_FAN_MIN(nr));
data->fan_target[nr] =
f75375_read16(client, F75375_REG_FAN_EXP(nr));
}
for (nr = 0; nr < 4; nr++) {
data->in_max[nr] =
f75375_read8(client, F75375_REG_VOLT_HIGH(nr));
data->in_min[nr] =
f75375_read8(client, F75375_REG_VOLT_LOW(nr));
}
data->fan_timer = f75375_read8(client, F75375_REG_FAN_TIMER);
data->last_limits = jiffies;
}
/* Measurement registers cache is refreshed after 2 second */
if (time_after(jiffies, data->last_updated + 2 * HZ)
|| !data->valid) {
for (nr = 0; nr < 2; nr++) {
data->pwm[nr] = f75375_read8(client,
F75375_REG_FAN_PWM_DUTY(nr));
/* assign MSB, therefore shift it by 8 bits */
data->temp11[nr] =
f75375_read8(client, F75375_REG_TEMP(nr)) << 8;
if (data->kind == f75387)
/* merge F75387's temperature LSB (11-bit) */
data->temp11[nr] |=
f75375_read8(client,
F75387_REG_TEMP11_LSB(nr));
data->fan[nr] =
f75375_read16(client, F75375_REG_FAN(nr));
}
for (nr = 0; nr < 4; nr++)
data->in[nr] =
f75375_read8(client, F75375_REG_VOLT(nr));
data->last_updated = jiffies;
data->valid = true;
}
mutex_unlock(&data->update_lock);
return data;
}
static inline u16 rpm_from_reg(u16 reg)
{
if (reg == 0 || reg == 0xffff)
return 0;
return 1500000 / reg;
}
static inline u16 rpm_to_reg(int rpm)
{
if (rpm < 367 || rpm > 0xffff)
return 0xffff;
return 1500000 / rpm;
}
static bool duty_mode_enabled(u8 pwm_enable)
{
switch (pwm_enable) {
case 0: /* Manual, duty mode (full speed) */
case 1: /* Manual, duty mode */
case 4: /* Auto, duty mode */
return true;
case 2: /* Auto, speed mode */
case 3: /* Manual, speed mode */
return false;
default:
WARN(1, "Unexpected pwm_enable value %d\n", pwm_enable);
return true;
}
}
static bool auto_mode_enabled(u8 pwm_enable)
{
switch (pwm_enable) {
case 0: /* Manual, duty mode (full speed) */
case 1: /* Manual, duty mode */
case 3: /* Manual, speed mode */
return false;
case 2: /* Auto, speed mode */
case 4: /* Auto, duty mode */
return true;
default:
WARN(1, "Unexpected pwm_enable value %d\n", pwm_enable);
return false;
}
}
static ssize_t set_fan_min(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int nr = to_sensor_dev_attr(attr)->index;
struct i2c_client *client = to_i2c_client(dev);
struct f75375_data *data = i2c_get_clientdata(client);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err < 0)
return err;
mutex_lock(&data->update_lock);
data->fan_min[nr] = rpm_to_reg(val);
f75375_write16(client, F75375_REG_FAN_MIN(nr), data->fan_min[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t set_fan_target(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int nr = to_sensor_dev_attr(attr)->index;
struct i2c_client *client = to_i2c_client(dev);
struct f75375_data *data = i2c_get_clientdata(client);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err < 0)
return err;
if (auto_mode_enabled(data->pwm_enable[nr]))
return -EINVAL;
if (data->kind == f75387 && duty_mode_enabled(data->pwm_enable[nr]))
return -EINVAL;
mutex_lock(&data->update_lock);
data->fan_target[nr] = rpm_to_reg(val);
f75375_write16(client, F75375_REG_FAN_EXP(nr), data->fan_target[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int nr = to_sensor_dev_attr(attr)->index;
struct i2c_client *client = to_i2c_client(dev);
struct f75375_data *data = i2c_get_clientdata(client);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err < 0)
return err;
if (auto_mode_enabled(data->pwm_enable[nr]) ||
!duty_mode_enabled(data->pwm_enable[nr]))
return -EINVAL;
mutex_lock(&data->update_lock);
data->pwm[nr] = clamp_val(val, 0, 255);
f75375_write_pwm(client, nr);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t show_pwm_enable(struct device *dev, struct device_attribute
*attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct f75375_data *data = f75375_update_device(dev);
return sprintf(buf, "%d\n", data->pwm_enable[nr]);
}
static int set_pwm_enable_direct(struct i2c_client *client, int nr, int val)
{
struct f75375_data *data = i2c_get_clientdata(client);
u8 fanmode;
if (val < 0 || val > 4)
return -EINVAL;
fanmode = f75375_read8(client, F75375_REG_FAN_TIMER);
if (data->kind == f75387) {
/* For now, deny dangerous toggling of duty mode */
if (duty_mode_enabled(data->pwm_enable[nr]) !=
duty_mode_enabled(val))
return -EOPNOTSUPP;
/* clear each fanX_mode bit before setting them properly */
fanmode &= ~(1 << F75387_FAN_DUTY_MODE(nr));
fanmode &= ~(1 << F75387_FAN_MANU_MODE(nr));
switch (val) {
case 0: /* full speed */
fanmode |= (1 << F75387_FAN_MANU_MODE(nr));
fanmode |= (1 << F75387_FAN_DUTY_MODE(nr));
data->pwm[nr] = 255;
break;
case 1: /* PWM */
fanmode |= (1 << F75387_FAN_MANU_MODE(nr));
fanmode |= (1 << F75387_FAN_DUTY_MODE(nr));
break;
case 2: /* Automatic, speed mode */
break;
case 3: /* fan speed */
fanmode |= (1 << F75387_FAN_MANU_MODE(nr));
break;
case 4: /* Automatic, pwm */
fanmode |= (1 << F75387_FAN_DUTY_MODE(nr));
break;
}
} else {
/* clear each fanX_mode bit before setting them properly */
fanmode &= ~(3 << FAN_CTRL_MODE(nr));
switch (val) {
case 0: /* full speed */
fanmode |= (3 << FAN_CTRL_MODE(nr));
data->pwm[nr] = 255;
break;
case 1: /* PWM */
fanmode |= (3 << FAN_CTRL_MODE(nr));
break;
case 2: /* AUTOMATIC*/
fanmode |= (1 << FAN_CTRL_MODE(nr));
break;
case 3: /* fan speed */
break;
case 4: /* Automatic pwm */
return -EINVAL;
}
}
f75375_write8(client, F75375_REG_FAN_TIMER, fanmode);
data->pwm_enable[nr] = val;
if (val == 0)
f75375_write_pwm(client, nr);
return 0;
}
static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int nr = to_sensor_dev_attr(attr)->index;
struct i2c_client *client = to_i2c_client(dev);
struct f75375_data *data = i2c_get_clientdata(client);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err < 0)
return err;
mutex_lock(&data->update_lock);
err = set_pwm_enable_direct(client, nr, val);
mutex_unlock(&data->update_lock);
return err ? err : count;
}
static ssize_t set_pwm_mode(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int nr = to_sensor_dev_attr(attr)->index;
struct i2c_client *client = to_i2c_client(dev);
struct f75375_data *data = i2c_get_clientdata(client);
unsigned long val;
int err;
u8 conf;
char reg, ctrl;
err = kstrtoul(buf, 10, &val);
if (err < 0)
return err;
if (!(val == 0 || val == 1))
return -EINVAL;
/* F75373 does not support DC (linear voltage) fan control mode */
if (data->kind == f75373 && val == 0)
return -EINVAL;
/* take care for different registers */
if (data->kind == f75387) {
reg = F75375_REG_FAN_TIMER;
ctrl = F75387_FAN_CTRL_LINEAR(nr);
} else {
reg = F75375_REG_CONFIG1;
ctrl = F75375_FAN_CTRL_LINEAR(nr);
}
mutex_lock(&data->update_lock);
conf = f75375_read8(client, reg);
conf &= ~(1 << ctrl);
if (val == 0)
conf |= (1 << ctrl);
f75375_write8(client, reg, conf);
data->pwm_mode[nr] = val;
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t show_pwm(struct device *dev, struct device_attribute
*attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct f75375_data *data = f75375_update_device(dev);
return sprintf(buf, "%d\n", data->pwm[nr]);
}
static ssize_t show_pwm_mode(struct device *dev, struct device_attribute
*attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct f75375_data *data = f75375_update_device(dev);
return sprintf(buf, "%d\n", data->pwm_mode[nr]);
}
#define VOLT_FROM_REG(val) ((val) * 8)
#define VOLT_TO_REG(val) ((val) / 8)
static ssize_t show_in(struct device *dev, struct device_attribute *attr,
char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct f75375_data *data = f75375_update_device(dev);
return sprintf(buf, "%d\n", VOLT_FROM_REG(data->in[nr]));
}
static ssize_t show_in_max(struct device *dev, struct device_attribute *attr,
char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct f75375_data *data = f75375_update_device(dev);
return sprintf(buf, "%d\n", VOLT_FROM_REG(data->in_max[nr]));
}
static ssize_t show_in_min(struct device *dev, struct device_attribute *attr,
char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct f75375_data *data = f75375_update_device(dev);
return sprintf(buf, "%d\n", VOLT_FROM_REG(data->in_min[nr]));
}
static ssize_t set_in_max(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int nr = to_sensor_dev_attr(attr)->index;
struct i2c_client *client = to_i2c_client(dev);
struct f75375_data *data = i2c_get_clientdata(client);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err < 0)
return err;
val = clamp_val(VOLT_TO_REG(val), 0, 0xff);
mutex_lock(&data->update_lock);
data->in_max[nr] = val;
f75375_write8(client, F75375_REG_VOLT_HIGH(nr), data->in_max[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t set_in_min(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int nr = to_sensor_dev_attr(attr)->index;
struct i2c_client *client = to_i2c_client(dev);
struct f75375_data *data = i2c_get_clientdata(client);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err < 0)
return err;
val = clamp_val(VOLT_TO_REG(val), 0, 0xff);
mutex_lock(&data->update_lock);
data->in_min[nr] = val;
f75375_write8(client, F75375_REG_VOLT_LOW(nr), data->in_min[nr]);
mutex_unlock(&data->update_lock);
return count;
}
#define TEMP_FROM_REG(val) ((val) * 1000)
#define TEMP_TO_REG(val) ((val) / 1000)
#define TEMP11_FROM_REG(reg) ((reg) / 32 * 125)
static ssize_t show_temp11(struct device *dev, struct device_attribute *attr,
char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct f75375_data *data = f75375_update_device(dev);
return sprintf(buf, "%d\n", TEMP11_FROM_REG(data->temp11[nr]));
}
static ssize_t show_temp_max(struct device *dev, struct device_attribute *attr,
char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct f75375_data *data = f75375_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp_high[nr]));
}
static ssize_t show_temp_max_hyst(struct device *dev,
struct device_attribute *attr, char *buf)
{
int nr = to_sensor_dev_attr(attr)->index;
struct f75375_data *data = f75375_update_device(dev);
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp_max_hyst[nr]));
}
static ssize_t set_temp_max(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int nr = to_sensor_dev_attr(attr)->index;
struct i2c_client *client = to_i2c_client(dev);
struct f75375_data *data = i2c_get_clientdata(client);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err < 0)
return err;
val = clamp_val(TEMP_TO_REG(val), 0, 127);
mutex_lock(&data->update_lock);
data->temp_high[nr] = val;
f75375_write8(client, F75375_REG_TEMP_HIGH(nr), data->temp_high[nr]);
mutex_unlock(&data->update_lock);
return count;
}
static ssize_t set_temp_max_hyst(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
int nr = to_sensor_dev_attr(attr)->index;
struct i2c_client *client = to_i2c_client(dev);
struct f75375_data *data = i2c_get_clientdata(client);
unsigned long val;
int err;
err = kstrtoul(buf, 10, &val);
if (err < 0)
return err;
val = clamp_val(TEMP_TO_REG(val), 0, 127);
mutex_lock(&data->update_lock);
data->temp_max_hyst[nr] = val;
f75375_write8(client, F75375_REG_TEMP_HYST(nr),
data->temp_max_hyst[nr]);
mutex_unlock(&data->update_lock);
return count;
}
#define show_fan(thing) \
static ssize_t show_##thing(struct device *dev, struct device_attribute *attr, \
char *buf)\
{\
int nr = to_sensor_dev_attr(attr)->index;\
struct f75375_data *data = f75375_update_device(dev); \
return sprintf(buf, "%d\n", rpm_from_reg(data->thing[nr])); \
}
show_fan(fan);
show_fan(fan_min);
show_fan(fan_max);
show_fan(fan_target);
static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, show_in, NULL, 0);
static SENSOR_DEVICE_ATTR(in0_max, S_IRUGO|S_IWUSR,
show_in_max, set_in_max, 0);
static SENSOR_DEVICE_ATTR(in0_min, S_IRUGO|S_IWUSR,
show_in_min, set_in_min, 0);
static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, show_in, NULL, 1);
static SENSOR_DEVICE_ATTR(in1_max, S_IRUGO|S_IWUSR,
show_in_max, set_in_max, 1);
static SENSOR_DEVICE_ATTR(in1_min, S_IRUGO|S_IWUSR,
show_in_min, set_in_min, 1);
static SENSOR_DEVICE_ATTR(in2_input, S_IRUGO, show_in, NULL, 2);
static SENSOR_DEVICE_ATTR(in2_max, S_IRUGO|S_IWUSR,
show_in_max, set_in_max, 2);
static SENSOR_DEVICE_ATTR(in2_min, S_IRUGO|S_IWUSR,
show_in_min, set_in_min, 2);
static SENSOR_DEVICE_ATTR(in3_input, S_IRUGO, show_in, NULL, 3);
static SENSOR_DEVICE_ATTR(in3_max, S_IRUGO|S_IWUSR,
show_in_max, set_in_max, 3);
static SENSOR_DEVICE_ATTR(in3_min, S_IRUGO|S_IWUSR,
show_in_min, set_in_min, 3);
static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp11, NULL, 0);
static SENSOR_DEVICE_ATTR(temp1_max_hyst, S_IRUGO|S_IWUSR,
show_temp_max_hyst, set_temp_max_hyst, 0);
static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO|S_IWUSR,
show_temp_max, set_temp_max, 0);
static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, show_temp11, NULL, 1);
static SENSOR_DEVICE_ATTR(temp2_max_hyst, S_IRUGO|S_IWUSR,
show_temp_max_hyst, set_temp_max_hyst, 1);
static SENSOR_DEVICE_ATTR(temp2_max, S_IRUGO|S_IWUSR,
show_temp_max, set_temp_max, 1);
static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0);
static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, show_fan_max, NULL, 0);
static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO|S_IWUSR,
show_fan_min, set_fan_min, 0);
static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO|S_IWUSR,
show_fan_target, set_fan_target, 0);
static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1);
static SENSOR_DEVICE_ATTR(fan2_max, S_IRUGO, show_fan_max, NULL, 1);
static SENSOR_DEVICE_ATTR(fan2_min, S_IRUGO|S_IWUSR,
show_fan_min, set_fan_min, 1);
static SENSOR_DEVICE_ATTR(fan2_target, S_IRUGO|S_IWUSR,
show_fan_target, set_fan_target, 1);
static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO|S_IWUSR,
show_pwm, set_pwm, 0);
static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO|S_IWUSR,
show_pwm_enable, set_pwm_enable, 0);
static SENSOR_DEVICE_ATTR(pwm1_mode, S_IRUGO,
show_pwm_mode, set_pwm_mode, 0);
static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR,
show_pwm, set_pwm, 1);
static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO|S_IWUSR,
show_pwm_enable, set_pwm_enable, 1);
static SENSOR_DEVICE_ATTR(pwm2_mode, S_IRUGO,
show_pwm_mode, set_pwm_mode, 1);
static struct attribute *f75375_attributes[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp1_max_hyst.dev_attr.attr,
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp2_max.dev_attr.attr,
&sensor_dev_attr_temp2_max_hyst.dev_attr.attr,
&sensor_dev_attr_fan1_input.dev_attr.attr,
&sensor_dev_attr_fan1_max.dev_attr.attr,
&sensor_dev_attr_fan1_min.dev_attr.attr,
&sensor_dev_attr_fan1_target.dev_attr.attr,
&sensor_dev_attr_fan2_input.dev_attr.attr,
&sensor_dev_attr_fan2_max.dev_attr.attr,
&sensor_dev_attr_fan2_min.dev_attr.attr,
&sensor_dev_attr_fan2_target.dev_attr.attr,
&sensor_dev_attr_pwm1.dev_attr.attr,
&sensor_dev_attr_pwm1_enable.dev_attr.attr,
&sensor_dev_attr_pwm1_mode.dev_attr.attr,
&sensor_dev_attr_pwm2.dev_attr.attr,
&sensor_dev_attr_pwm2_enable.dev_attr.attr,
&sensor_dev_attr_pwm2_mode.dev_attr.attr,
&sensor_dev_attr_in0_input.dev_attr.attr,
&sensor_dev_attr_in0_max.dev_attr.attr,
&sensor_dev_attr_in0_min.dev_attr.attr,
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in1_max.dev_attr.attr,
&sensor_dev_attr_in1_min.dev_attr.attr,
&sensor_dev_attr_in2_input.dev_attr.attr,
&sensor_dev_attr_in2_max.dev_attr.attr,
&sensor_dev_attr_in2_min.dev_attr.attr,
&sensor_dev_attr_in3_input.dev_attr.attr,
&sensor_dev_attr_in3_max.dev_attr.attr,
&sensor_dev_attr_in3_min.dev_attr.attr,
NULL
};
static const struct attribute_group f75375_group = {
.attrs = f75375_attributes,
};
static void f75375_init(struct i2c_client *client, struct f75375_data *data,
struct f75375s_platform_data *f75375s_pdata)
{
int nr;
if (!f75375s_pdata) {
u8 conf, mode;
int nr;
conf = f75375_read8(client, F75375_REG_CONFIG1);
mode = f75375_read8(client, F75375_REG_FAN_TIMER);
for (nr = 0; nr < 2; nr++) {
if (data->kind == f75387) {
bool manu, duty;
if (!(mode & (1 << F75387_FAN_CTRL_LINEAR(nr))))
data->pwm_mode[nr] = 1;
manu = ((mode >> F75387_FAN_MANU_MODE(nr)) & 1);
duty = ((mode >> F75387_FAN_DUTY_MODE(nr)) & 1);
if (!manu && duty)
/* auto, pwm */
data->pwm_enable[nr] = 4;
else if (manu && !duty)
/* manual, speed */
data->pwm_enable[nr] = 3;
else if (!manu && !duty)
/* automatic, speed */
data->pwm_enable[nr] = 2;
else
/* manual, pwm */
data->pwm_enable[nr] = 1;
} else {
if (!(conf & (1 << F75375_FAN_CTRL_LINEAR(nr))))
data->pwm_mode[nr] = 1;
switch ((mode >> FAN_CTRL_MODE(nr)) & 3) {
case 0: /* speed */
data->pwm_enable[nr] = 3;
break;
case 1: /* automatic */
data->pwm_enable[nr] = 2;
break;
default: /* manual */
data->pwm_enable[nr] = 1;
break;
}
}
}
return;
}
set_pwm_enable_direct(client, 0, f75375s_pdata->pwm_enable[0]);
set_pwm_enable_direct(client, 1, f75375s_pdata->pwm_enable[1]);
for (nr = 0; nr < 2; nr++) {
if (auto_mode_enabled(f75375s_pdata->pwm_enable[nr]) ||
!duty_mode_enabled(f75375s_pdata->pwm_enable[nr]))
continue;
data->pwm[nr] = clamp_val(f75375s_pdata->pwm[nr], 0, 255);
f75375_write_pwm(client, nr);
}
}
static int f75375_probe(struct i2c_client *client)
{
struct f75375_data *data;
struct f75375s_platform_data *f75375s_pdata =
dev_get_platdata(&client->dev);
int err;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE_DATA))
return -EIO;
data = devm_kzalloc(&client->dev, sizeof(struct f75375_data),
GFP_KERNEL);
if (!data)
return -ENOMEM;
i2c_set_clientdata(client, data);
mutex_init(&data->update_lock);
data->kind = i2c_match_id(f75375_id, client)->driver_data;
err = sysfs_create_group(&client->dev.kobj, &f75375_group);
if (err)
return err;
if (data->kind != f75373) {
err = sysfs_chmod_file(&client->dev.kobj,
&sensor_dev_attr_pwm1_mode.dev_attr.attr,
S_IRUGO | S_IWUSR);
if (err)
goto exit_remove;
err = sysfs_chmod_file(&client->dev.kobj,
&sensor_dev_attr_pwm2_mode.dev_attr.attr,
S_IRUGO | S_IWUSR);
if (err)
goto exit_remove;
}
data->hwmon_dev = hwmon_device_register(&client->dev);
if (IS_ERR(data->hwmon_dev)) {
err = PTR_ERR(data->hwmon_dev);
goto exit_remove;
}
f75375_init(client, data, f75375s_pdata);
return 0;
exit_remove:
sysfs_remove_group(&client->dev.kobj, &f75375_group);
return err;
}
static void f75375_remove(struct i2c_client *client)
{
struct f75375_data *data = i2c_get_clientdata(client);
hwmon_device_unregister(data->hwmon_dev);
sysfs_remove_group(&client->dev.kobj, &f75375_group);
}
/* Return 0 if detection is successful, -ENODEV otherwise */
static int f75375_detect(struct i2c_client *client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
u16 vendid, chipid;
u8 version;
const char *name;
vendid = f75375_read16(client, F75375_REG_VENDOR);
chipid = f75375_read16(client, F75375_CHIP_ID);
if (vendid != 0x1934)
return -ENODEV;
if (chipid == 0x0306)
name = "f75375";
else if (chipid == 0x0204)
name = "f75373";
else if (chipid == 0x0410)
name = "f75387";
else
return -ENODEV;
version = f75375_read8(client, F75375_REG_VERSION);
dev_info(&adapter->dev, "found %s version: %02X\n", name, version);
strscpy(info->type, name, I2C_NAME_SIZE);
return 0;
}
module_i2c_driver(f75375_driver);
MODULE_AUTHOR("Riku Voipio");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("F75373/F75375/F75387 hardware monitoring driver");
|
linux-master
|
drivers/hwmon/f75375s.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MEN 14F021P00 Board Management Controller (BMC) hwmon driver.
*
* This is the core hwmon driver of the MEN 14F021P00 BMC.
* The BMC monitors the board voltages which can be access with this
* driver through sysfs.
*
* Copyright (C) 2014 MEN Mikro Elektronik Nuernberg GmbH
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/jiffies.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/err.h>
#define DRV_NAME "menf21bmc_hwmon"
#define BMC_VOLT_COUNT 5
#define MENF21BMC_V33 0
#define MENF21BMC_V5 1
#define MENF21BMC_V12 2
#define MENF21BMC_V5_SB 3
#define MENF21BMC_VBAT 4
#define IDX_TO_VOLT_MIN_CMD(idx) (0x40 + idx)
#define IDX_TO_VOLT_MAX_CMD(idx) (0x50 + idx)
#define IDX_TO_VOLT_INP_CMD(idx) (0x60 + idx)
struct menf21bmc_hwmon {
bool valid;
struct i2c_client *i2c_client;
unsigned long last_update;
int in_val[BMC_VOLT_COUNT];
int in_min[BMC_VOLT_COUNT];
int in_max[BMC_VOLT_COUNT];
};
static const char *const input_names[] = {
[MENF21BMC_V33] = "MON_3_3V",
[MENF21BMC_V5] = "MON_5V",
[MENF21BMC_V12] = "MON_12V",
[MENF21BMC_V5_SB] = "5V_STANDBY",
[MENF21BMC_VBAT] = "VBAT"
};
static struct menf21bmc_hwmon *menf21bmc_hwmon_update(struct device *dev)
{
int i;
int val;
struct menf21bmc_hwmon *drv_data = dev_get_drvdata(dev);
struct menf21bmc_hwmon *data_ret = drv_data;
if (time_after(jiffies, drv_data->last_update + HZ)
|| !drv_data->valid) {
for (i = 0; i < BMC_VOLT_COUNT; i++) {
val = i2c_smbus_read_word_data(drv_data->i2c_client,
IDX_TO_VOLT_INP_CMD(i));
if (val < 0) {
data_ret = ERR_PTR(val);
goto abort;
}
drv_data->in_val[i] = val;
}
drv_data->last_update = jiffies;
drv_data->valid = true;
}
abort:
return data_ret;
}
static int menf21bmc_hwmon_get_volt_limits(struct menf21bmc_hwmon *drv_data)
{
int i, val;
for (i = 0; i < BMC_VOLT_COUNT; i++) {
val = i2c_smbus_read_word_data(drv_data->i2c_client,
IDX_TO_VOLT_MIN_CMD(i));
if (val < 0)
return val;
drv_data->in_min[i] = val;
val = i2c_smbus_read_word_data(drv_data->i2c_client,
IDX_TO_VOLT_MAX_CMD(i));
if (val < 0)
return val;
drv_data->in_max[i] = val;
}
return 0;
}
static ssize_t
label_show(struct device *dev, struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
return sprintf(buf, "%s\n", input_names[attr->index]);
}
static ssize_t
in_show(struct device *dev, struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct menf21bmc_hwmon *drv_data = menf21bmc_hwmon_update(dev);
if (IS_ERR(drv_data))
return PTR_ERR(drv_data);
return sprintf(buf, "%d\n", drv_data->in_val[attr->index]);
}
static ssize_t
min_show(struct device *dev, struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct menf21bmc_hwmon *drv_data = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", drv_data->in_min[attr->index]);
}
static ssize_t
max_show(struct device *dev, struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct menf21bmc_hwmon *drv_data = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", drv_data->in_max[attr->index]);
}
static SENSOR_DEVICE_ATTR_RO(in0_input, in, 0);
static SENSOR_DEVICE_ATTR_RO(in0_min, min, 0);
static SENSOR_DEVICE_ATTR_RO(in0_max, max, 0);
static SENSOR_DEVICE_ATTR_RO(in0_label, label, 0);
static SENSOR_DEVICE_ATTR_RO(in1_input, in, 1);
static SENSOR_DEVICE_ATTR_RO(in1_min, min, 1);
static SENSOR_DEVICE_ATTR_RO(in1_max, max, 1);
static SENSOR_DEVICE_ATTR_RO(in1_label, label, 1);
static SENSOR_DEVICE_ATTR_RO(in2_input, in, 2);
static SENSOR_DEVICE_ATTR_RO(in2_min, min, 2);
static SENSOR_DEVICE_ATTR_RO(in2_max, max, 2);
static SENSOR_DEVICE_ATTR_RO(in2_label, label, 2);
static SENSOR_DEVICE_ATTR_RO(in3_input, in, 3);
static SENSOR_DEVICE_ATTR_RO(in3_min, min, 3);
static SENSOR_DEVICE_ATTR_RO(in3_max, max, 3);
static SENSOR_DEVICE_ATTR_RO(in3_label, label, 3);
static SENSOR_DEVICE_ATTR_RO(in4_input, in, 4);
static SENSOR_DEVICE_ATTR_RO(in4_min, min, 4);
static SENSOR_DEVICE_ATTR_RO(in4_max, max, 4);
static SENSOR_DEVICE_ATTR_RO(in4_label, label, 4);
static struct attribute *menf21bmc_hwmon_attrs[] = {
&sensor_dev_attr_in0_input.dev_attr.attr,
&sensor_dev_attr_in0_min.dev_attr.attr,
&sensor_dev_attr_in0_max.dev_attr.attr,
&sensor_dev_attr_in0_label.dev_attr.attr,
&sensor_dev_attr_in1_input.dev_attr.attr,
&sensor_dev_attr_in1_min.dev_attr.attr,
&sensor_dev_attr_in1_max.dev_attr.attr,
&sensor_dev_attr_in1_label.dev_attr.attr,
&sensor_dev_attr_in2_input.dev_attr.attr,
&sensor_dev_attr_in2_min.dev_attr.attr,
&sensor_dev_attr_in2_max.dev_attr.attr,
&sensor_dev_attr_in2_label.dev_attr.attr,
&sensor_dev_attr_in3_input.dev_attr.attr,
&sensor_dev_attr_in3_min.dev_attr.attr,
&sensor_dev_attr_in3_max.dev_attr.attr,
&sensor_dev_attr_in3_label.dev_attr.attr,
&sensor_dev_attr_in4_input.dev_attr.attr,
&sensor_dev_attr_in4_min.dev_attr.attr,
&sensor_dev_attr_in4_max.dev_attr.attr,
&sensor_dev_attr_in4_label.dev_attr.attr,
NULL
};
ATTRIBUTE_GROUPS(menf21bmc_hwmon);
static int menf21bmc_hwmon_probe(struct platform_device *pdev)
{
int ret;
struct menf21bmc_hwmon *drv_data;
struct i2c_client *i2c_client = to_i2c_client(pdev->dev.parent);
struct device *hwmon_dev;
drv_data = devm_kzalloc(&pdev->dev, sizeof(struct menf21bmc_hwmon),
GFP_KERNEL);
if (!drv_data)
return -ENOMEM;
drv_data->i2c_client = i2c_client;
ret = menf21bmc_hwmon_get_volt_limits(drv_data);
if (ret) {
dev_err(&pdev->dev, "failed to read sensor limits");
return ret;
}
hwmon_dev = devm_hwmon_device_register_with_groups(&pdev->dev,
"menf21bmc", drv_data,
menf21bmc_hwmon_groups);
if (IS_ERR(hwmon_dev))
return PTR_ERR(hwmon_dev);
dev_info(&pdev->dev, "MEN 14F021P00 BMC hwmon device enabled");
return 0;
}
static struct platform_driver menf21bmc_hwmon = {
.probe = menf21bmc_hwmon_probe,
.driver = {
.name = DRV_NAME,
},
};
module_platform_driver(menf21bmc_hwmon);
MODULE_AUTHOR("Andreas Werner <[email protected]>");
MODULE_DESCRIPTION("MEN 14F021P00 BMC hwmon");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:menf21bmc_hwmon");
|
linux-master
|
drivers/hwmon/menf21bmc_hwmon.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Copyright (C) 2010-2012 Hans de Goede <[email protected]> *
* *
***************************************************************************/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dmi.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/watchdog.h>
#include <linux/uaccess.h>
#include <linux/slab.h>
#include "sch56xx-common.h"
static bool ignore_dmi;
module_param(ignore_dmi, bool, 0);
MODULE_PARM_DESC(ignore_dmi, "Omit DMI check for supported devices (default=0)");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
#define SIO_SCH56XX_LD_EM 0x0C /* Embedded uController Logical Dev */
#define SIO_UNLOCK_KEY 0x55 /* Key to enable Super-I/O */
#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
#define SIO_REG_LDSEL 0x07 /* Logical device select */
#define SIO_REG_DEVID 0x20 /* Device ID */
#define SIO_REG_ENABLE 0x30 /* Logical device enable */
#define SIO_REG_ADDR 0x66 /* Logical device address (2 bytes) */
#define SIO_SCH5627_ID 0xC6 /* Chipset ID */
#define SIO_SCH5636_ID 0xC7 /* Chipset ID */
#define REGION_LENGTH 10
#define SCH56XX_CMD_READ 0x02
#define SCH56XX_CMD_WRITE 0x03
/* Watchdog registers */
#define SCH56XX_REG_WDOG_PRESET 0x58B
#define SCH56XX_REG_WDOG_CONTROL 0x58C
#define SCH56XX_WDOG_TIME_BASE_SEC 0x01
#define SCH56XX_REG_WDOG_OUTPUT_ENABLE 0x58E
#define SCH56XX_WDOG_OUTPUT_ENABLE 0x02
struct sch56xx_watchdog_data {
u16 addr;
struct mutex *io_lock;
struct watchdog_info wdinfo;
struct watchdog_device wddev;
u8 watchdog_preset;
u8 watchdog_control;
u8 watchdog_output_enable;
};
static struct platform_device *sch56xx_pdev;
/* Super I/O functions */
static inline int superio_inb(int base, int reg)
{
outb(reg, base);
return inb(base + 1);
}
static inline int superio_enter(int base)
{
/* Don't step on other drivers' I/O space by accident */
if (!request_muxed_region(base, 2, "sch56xx")) {
pr_err("I/O address 0x%04x already in use\n", base);
return -EBUSY;
}
outb(SIO_UNLOCK_KEY, base);
return 0;
}
static inline void superio_select(int base, int ld)
{
outb(SIO_REG_LDSEL, base);
outb(ld, base + 1);
}
static inline void superio_exit(int base)
{
outb(SIO_LOCK_KEY, base);
release_region(base, 2);
}
static int sch56xx_send_cmd(u16 addr, u8 cmd, u16 reg, u8 v)
{
u8 val;
int i;
/*
* According to SMSC for the commands we use the maximum time for
* the EM to respond is 15 ms, but testing shows in practice it
* responds within 15-32 reads, so we first busy poll, and if
* that fails sleep a bit and try again until we are way past
* the 15 ms maximum response time.
*/
const int max_busy_polls = 64;
const int max_lazy_polls = 32;
/* (Optional) Write-Clear the EC to Host Mailbox Register */
val = inb(addr + 1);
outb(val, addr + 1);
/* Set Mailbox Address Pointer to first location in Region 1 */
outb(0x00, addr + 2);
outb(0x80, addr + 3);
/* Write Request Packet Header */
outb(cmd, addr + 4); /* VREG Access Type read:0x02 write:0x03 */
outb(0x01, addr + 5); /* # of Entries: 1 Byte (8-bit) */
outb(0x04, addr + 2); /* Mailbox AP to first data entry loc. */
/* Write Value field */
if (cmd == SCH56XX_CMD_WRITE)
outb(v, addr + 4);
/* Write Address field */
outb(reg & 0xff, addr + 6);
outb(reg >> 8, addr + 7);
/* Execute the Random Access Command */
outb(0x01, addr); /* Write 01h to the Host-to-EC register */
/* EM Interface Polling "Algorithm" */
for (i = 0; i < max_busy_polls + max_lazy_polls; i++) {
if (i >= max_busy_polls)
usleep_range(1000, 2000);
/* Read Interrupt source Register */
val = inb(addr + 8);
/* Write Clear the interrupt source bits */
if (val)
outb(val, addr + 8);
/* Command Completed ? */
if (val & 0x01)
break;
}
if (i == max_busy_polls + max_lazy_polls) {
pr_err("Max retries exceeded reading virtual register 0x%04hx (%d)\n",
reg, 1);
return -EIO;
}
/*
* According to SMSC we may need to retry this, but sofar I've always
* seen this succeed in 1 try.
*/
for (i = 0; i < max_busy_polls; i++) {
/* Read EC-to-Host Register */
val = inb(addr + 1);
/* Command Completed ? */
if (val == 0x01)
break;
if (i == 0)
pr_warn("EC reports: 0x%02x reading virtual register 0x%04hx\n",
(unsigned int)val, reg);
}
if (i == max_busy_polls) {
pr_err("Max retries exceeded reading virtual register 0x%04hx (%d)\n",
reg, 2);
return -EIO;
}
/*
* According to the SMSC app note we should now do:
*
* Set Mailbox Address Pointer to first location in Region 1 *
* outb(0x00, addr + 2);
* outb(0x80, addr + 3);
*
* But if we do that things don't work, so let's not.
*/
/* Read Value field */
if (cmd == SCH56XX_CMD_READ)
return inb(addr + 4);
return 0;
}
int sch56xx_read_virtual_reg(u16 addr, u16 reg)
{
return sch56xx_send_cmd(addr, SCH56XX_CMD_READ, reg, 0);
}
EXPORT_SYMBOL(sch56xx_read_virtual_reg);
int sch56xx_write_virtual_reg(u16 addr, u16 reg, u8 val)
{
return sch56xx_send_cmd(addr, SCH56XX_CMD_WRITE, reg, val);
}
EXPORT_SYMBOL(sch56xx_write_virtual_reg);
int sch56xx_read_virtual_reg16(u16 addr, u16 reg)
{
int lsb, msb;
/* Read LSB first, this will cause the matching MSB to be latched */
lsb = sch56xx_read_virtual_reg(addr, reg);
if (lsb < 0)
return lsb;
msb = sch56xx_read_virtual_reg(addr, reg + 1);
if (msb < 0)
return msb;
return lsb | (msb << 8);
}
EXPORT_SYMBOL(sch56xx_read_virtual_reg16);
int sch56xx_read_virtual_reg12(u16 addr, u16 msb_reg, u16 lsn_reg,
int high_nibble)
{
int msb, lsn;
/* Read MSB first, this will cause the matching LSN to be latched */
msb = sch56xx_read_virtual_reg(addr, msb_reg);
if (msb < 0)
return msb;
lsn = sch56xx_read_virtual_reg(addr, lsn_reg);
if (lsn < 0)
return lsn;
if (high_nibble)
return (msb << 4) | (lsn >> 4);
else
return (msb << 4) | (lsn & 0x0f);
}
EXPORT_SYMBOL(sch56xx_read_virtual_reg12);
/*
* Watchdog routines
*/
static int watchdog_set_timeout(struct watchdog_device *wddev,
unsigned int timeout)
{
struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev);
unsigned int resolution;
u8 control;
int ret;
/* 1 second or 60 second resolution? */
if (timeout <= 255)
resolution = 1;
else
resolution = 60;
if (timeout < resolution || timeout > (resolution * 255))
return -EINVAL;
if (resolution == 1)
control = data->watchdog_control | SCH56XX_WDOG_TIME_BASE_SEC;
else
control = data->watchdog_control & ~SCH56XX_WDOG_TIME_BASE_SEC;
if (data->watchdog_control != control) {
mutex_lock(data->io_lock);
ret = sch56xx_write_virtual_reg(data->addr,
SCH56XX_REG_WDOG_CONTROL,
control);
mutex_unlock(data->io_lock);
if (ret)
return ret;
data->watchdog_control = control;
}
/*
* Remember new timeout value, but do not write as that (re)starts
* the watchdog countdown.
*/
data->watchdog_preset = DIV_ROUND_UP(timeout, resolution);
wddev->timeout = data->watchdog_preset * resolution;
return 0;
}
static int watchdog_start(struct watchdog_device *wddev)
{
struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev);
int ret;
u8 val;
/*
* The sch56xx's watchdog cannot really be started / stopped
* it is always running, but we can avoid the timer expiring
* from causing a system reset by clearing the output enable bit.
*
* The sch56xx's watchdog will set the watchdog event bit, bit 0
* of the second interrupt source register (at base-address + 9),
* when the timer expires.
*
* This will only cause a system reset if the 0-1 flank happens when
* output enable is true. Setting output enable after the flank will
* not cause a reset, nor will the timer expiring a second time.
* This means we must clear the watchdog event bit in case it is set.
*
* The timer may still be running (after a recent watchdog_stop) and
* mere milliseconds away from expiring, so the timer must be reset
* first!
*/
mutex_lock(data->io_lock);
/* 1. Reset the watchdog countdown counter */
ret = sch56xx_write_virtual_reg(data->addr, SCH56XX_REG_WDOG_PRESET,
data->watchdog_preset);
if (ret)
goto leave;
/* 2. Enable output */
val = data->watchdog_output_enable | SCH56XX_WDOG_OUTPUT_ENABLE;
ret = sch56xx_write_virtual_reg(data->addr,
SCH56XX_REG_WDOG_OUTPUT_ENABLE, val);
if (ret)
goto leave;
data->watchdog_output_enable = val;
/* 3. Clear the watchdog event bit if set */
val = inb(data->addr + 9);
if (val & 0x01)
outb(0x01, data->addr + 9);
leave:
mutex_unlock(data->io_lock);
return ret;
}
static int watchdog_trigger(struct watchdog_device *wddev)
{
struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev);
int ret;
/* Reset the watchdog countdown counter */
mutex_lock(data->io_lock);
ret = sch56xx_write_virtual_reg(data->addr, SCH56XX_REG_WDOG_PRESET,
data->watchdog_preset);
mutex_unlock(data->io_lock);
return ret;
}
static int watchdog_stop(struct watchdog_device *wddev)
{
struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev);
int ret = 0;
u8 val;
val = data->watchdog_output_enable & ~SCH56XX_WDOG_OUTPUT_ENABLE;
mutex_lock(data->io_lock);
ret = sch56xx_write_virtual_reg(data->addr,
SCH56XX_REG_WDOG_OUTPUT_ENABLE, val);
mutex_unlock(data->io_lock);
if (ret)
return ret;
data->watchdog_output_enable = val;
return 0;
}
static const struct watchdog_ops watchdog_ops = {
.owner = THIS_MODULE,
.start = watchdog_start,
.stop = watchdog_stop,
.ping = watchdog_trigger,
.set_timeout = watchdog_set_timeout,
};
void sch56xx_watchdog_register(struct device *parent, u16 addr, u32 revision,
struct mutex *io_lock, int check_enabled)
{
struct sch56xx_watchdog_data *data;
int err, control, output_enable;
/* Cache the watchdog registers */
mutex_lock(io_lock);
control =
sch56xx_read_virtual_reg(addr, SCH56XX_REG_WDOG_CONTROL);
output_enable =
sch56xx_read_virtual_reg(addr, SCH56XX_REG_WDOG_OUTPUT_ENABLE);
mutex_unlock(io_lock);
if (control < 0)
return;
if (output_enable < 0)
return;
if (check_enabled && !(output_enable & SCH56XX_WDOG_OUTPUT_ENABLE)) {
pr_warn("Watchdog not enabled by BIOS, not registering\n");
return;
}
data = devm_kzalloc(parent, sizeof(struct sch56xx_watchdog_data), GFP_KERNEL);
if (!data)
return;
data->addr = addr;
data->io_lock = io_lock;
strscpy(data->wdinfo.identity, "sch56xx watchdog", sizeof(data->wdinfo.identity));
data->wdinfo.firmware_version = revision;
data->wdinfo.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT;
if (!nowayout)
data->wdinfo.options |= WDIOF_MAGICCLOSE;
data->wddev.info = &data->wdinfo;
data->wddev.ops = &watchdog_ops;
data->wddev.parent = parent;
data->wddev.timeout = 60;
data->wddev.min_timeout = 1;
data->wddev.max_timeout = 255 * 60;
watchdog_set_nowayout(&data->wddev, nowayout);
if (output_enable & SCH56XX_WDOG_OUTPUT_ENABLE)
set_bit(WDOG_HW_RUNNING, &data->wddev.status);
/* Since the watchdog uses a downcounter there is no register to read
the BIOS set timeout from (if any was set at all) ->
Choose a preset which will give us a 1 minute timeout */
if (control & SCH56XX_WDOG_TIME_BASE_SEC)
data->watchdog_preset = 60; /* seconds */
else
data->watchdog_preset = 1; /* minute */
data->watchdog_control = control;
data->watchdog_output_enable = output_enable;
watchdog_set_drvdata(&data->wddev, data);
err = devm_watchdog_register_device(parent, &data->wddev);
if (err) {
pr_err("Registering watchdog chardev: %d\n", err);
devm_kfree(parent, data);
}
}
EXPORT_SYMBOL(sch56xx_watchdog_register);
/*
* platform dev find, add and remove functions
*/
static int __init sch56xx_find(int sioaddr, const char **name)
{
u8 devid;
unsigned short address;
int err;
err = superio_enter(sioaddr);
if (err)
return err;
devid = superio_inb(sioaddr, SIO_REG_DEVID);
switch (devid) {
case SIO_SCH5627_ID:
*name = "sch5627";
break;
case SIO_SCH5636_ID:
*name = "sch5636";
break;
default:
pr_debug("Unsupported device id: 0x%02x\n",
(unsigned int)devid);
err = -ENODEV;
goto exit;
}
superio_select(sioaddr, SIO_SCH56XX_LD_EM);
if (!(superio_inb(sioaddr, SIO_REG_ENABLE) & 0x01)) {
pr_warn("Device not activated\n");
err = -ENODEV;
goto exit;
}
/*
* Warning the order of the low / high byte is the other way around
* as on most other superio devices!!
*/
address = superio_inb(sioaddr, SIO_REG_ADDR) |
superio_inb(sioaddr, SIO_REG_ADDR + 1) << 8;
if (address == 0) {
pr_warn("Base address not set\n");
err = -ENODEV;
goto exit;
}
err = address;
exit:
superio_exit(sioaddr);
return err;
}
static int __init sch56xx_device_add(int address, const char *name)
{
struct resource res = {
.start = address,
.end = address + REGION_LENGTH - 1,
.name = name,
.flags = IORESOURCE_IO,
};
int err;
err = acpi_check_resource_conflict(&res);
if (err)
return err;
sch56xx_pdev = platform_device_register_simple(name, -1, &res, 1);
return PTR_ERR_OR_ZERO(sch56xx_pdev);
}
static const struct dmi_system_id sch56xx_dmi_override_table[] __initconst = {
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
DMI_MATCH(DMI_PRODUCT_NAME, "CELSIUS W380"),
},
},
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO P710"),
},
},
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO E9900"),
},
},
{ }
};
/* For autoloading only */
static const struct dmi_system_id sch56xx_dmi_table[] __initconst = {
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
},
},
{ }
};
MODULE_DEVICE_TABLE(dmi, sch56xx_dmi_table);
static int __init sch56xx_init(void)
{
const char *name = NULL;
int address;
if (!ignore_dmi) {
if (!dmi_check_system(sch56xx_dmi_table))
return -ENODEV;
if (!dmi_check_system(sch56xx_dmi_override_table)) {
/*
* Some machines like the Esprimo P720 and Esprimo C700 have
* onboard devices named " Antiope"/" Theseus" instead of
* "Antiope"/"Theseus", so we need to check for both.
*/
if (!dmi_find_device(DMI_DEV_TYPE_OTHER, "Antiope", NULL) &&
!dmi_find_device(DMI_DEV_TYPE_OTHER, " Antiope", NULL) &&
!dmi_find_device(DMI_DEV_TYPE_OTHER, "Theseus", NULL) &&
!dmi_find_device(DMI_DEV_TYPE_OTHER, " Theseus", NULL))
return -ENODEV;
}
}
/*
* Some devices like the Esprimo C700 have both onboard devices,
* so we still have to check manually
*/
address = sch56xx_find(0x4e, &name);
if (address < 0)
address = sch56xx_find(0x2e, &name);
if (address < 0)
return address;
return sch56xx_device_add(address, name);
}
static void __exit sch56xx_exit(void)
{
platform_device_unregister(sch56xx_pdev);
}
MODULE_DESCRIPTION("SMSC SCH56xx Hardware Monitoring Common Code");
MODULE_AUTHOR("Hans de Goede <[email protected]>");
MODULE_LICENSE("GPL");
module_init(sch56xx_init);
module_exit(sch56xx_exit);
|
linux-master
|
drivers/hwmon/sch56xx-common.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices LTC2947 high precision power and energy monitor over I2C
*
* Copyright 2019 Analog Devices Inc.
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include "ltc2947.h"
static const struct regmap_config ltc2947_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static int ltc2947_probe(struct i2c_client *i2c)
{
struct regmap *map;
map = devm_regmap_init_i2c(i2c, <c2947_regmap_config);
if (IS_ERR(map))
return PTR_ERR(map);
return ltc2947_core_probe(map, i2c->name);
}
static const struct i2c_device_id ltc2947_id[] = {
{"ltc2947", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, ltc2947_id);
static struct i2c_driver ltc2947_driver = {
.driver = {
.name = "ltc2947",
.of_match_table = ltc2947_of_match,
.pm = pm_sleep_ptr(<c2947_pm_ops),
},
.probe = ltc2947_probe,
.id_table = ltc2947_id,
};
module_i2c_driver(ltc2947_driver);
MODULE_AUTHOR("Nuno Sa <[email protected]>");
MODULE_DESCRIPTION("LTC2947 I2C power and energy monitor driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/hwmon/ltc2947-i2c.c
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.